1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
97 #ifndef ACCUMULATE_OUTGOING_ARGS
98 #define ACCUMULATE_OUTGOING_ARGS 0
101 /* Supply a default definition for PUSH_ARGS. */
104 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
110 /* It is not safe to use ordinary gen_lowpart in combine.
111 Use gen_lowpart_for_combine instead. See comments there. */
112 #define gen_lowpart dont_use_gen_lowpart_you_dummy
114 /* Number of attempts to combine instructions in this function. */
116 static int combine_attempts;
118 /* Number of attempts that got as far as substitution in this function. */
120 static int combine_merges;
122 /* Number of instructions combined with added SETs in this function. */
124 static int combine_extras;
126 /* Number of instructions combined in this function. */
128 static int combine_successes;
130 /* Totals over entire compilation. */
132 static int total_attempts, total_merges, total_extras, total_successes;
134 /* Define a default value for REVERSIBLE_CC_MODE.
135 We can never assume that a condition code mode is safe to reverse unless
136 the md tells us so. */
137 #ifndef REVERSIBLE_CC_MODE
138 #define REVERSIBLE_CC_MODE(MODE) 0
141 /* Vector mapping INSN_UIDs to cuids.
142 The cuids are like uids but increase monotonically always.
143 Combine always uses cuids so that it can compare them.
144 But actually renumbering the uids, which we used to do,
145 proves to be a bad idea because it makes it hard to compare
146 the dumps produced by earlier passes with those from later passes. */
148 static int *uid_cuid;
149 static int max_uid_cuid;
151 /* Get the cuid of an insn. */
153 #define INSN_CUID(INSN) \
154 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
156 /* Maximum register number, which is the size of the tables below. */
158 static unsigned int combine_max_regno;
160 /* Record last point of death of (hard or pseudo) register n. */
162 static rtx *reg_last_death;
164 /* Record last point of modification of (hard or pseudo) register n. */
166 static rtx *reg_last_set;
168 /* Record the cuid of the last insn that invalidated memory
169 (anything that writes memory, and subroutine calls, but not pushes). */
171 static int mem_last_set;
173 /* Record the cuid of the last CALL_INSN
174 so we can tell whether a potential combination crosses any calls. */
176 static int last_call_cuid;
178 /* When `subst' is called, this is the insn that is being modified
179 (by combining in a previous insn). The PATTERN of this insn
180 is still the old pattern partially modified and it should not be
181 looked at, but this may be used to examine the successors of the insn
182 to judge whether a simplification is valid. */
184 static rtx subst_insn;
186 /* This is an insn that belongs before subst_insn, but is not currently
187 on the insn chain. */
189 static rtx subst_prev_insn;
191 /* This is the lowest CUID that `subst' is currently dealing with.
192 get_last_value will not return a value if the register was set at or
193 after this CUID. If not for this mechanism, we could get confused if
194 I2 or I1 in try_combine were an insn that used the old value of a register
195 to obtain a new value. In that case, we might erroneously get the
196 new value of the register when we wanted the old one. */
198 static int subst_low_cuid;
200 /* This contains any hard registers that are used in newpat; reg_dead_at_p
201 must consider all these registers to be always live. */
203 static HARD_REG_SET newpat_used_regs;
205 /* This is an insn to which a LOG_LINKS entry has been added. If this
206 insn is the earlier than I2 or I3, combine should rescan starting at
209 static rtx added_links_insn;
211 /* Basic block number of the block in which we are performing combines. */
212 static int this_basic_block;
214 /* A bitmap indicating which blocks had registers go dead at entry.
215 After combine, we'll need to re-do global life analysis with
216 those blocks as starting points. */
217 static sbitmap refresh_blocks;
218 static int need_refresh;
220 /* The next group of arrays allows the recording of the last value assigned
221 to (hard or pseudo) register n. We use this information to see if a
222 operation being processed is redundant given a prior operation performed
223 on the register. For example, an `and' with a constant is redundant if
224 all the zero bits are already known to be turned off.
226 We use an approach similar to that used by cse, but change it in the
229 (1) We do not want to reinitialize at each label.
230 (2) It is useful, but not critical, to know the actual value assigned
231 to a register. Often just its form is helpful.
233 Therefore, we maintain the following arrays:
235 reg_last_set_value the last value assigned
236 reg_last_set_label records the value of label_tick when the
237 register was assigned
238 reg_last_set_table_tick records the value of label_tick when a
239 value using the register is assigned
240 reg_last_set_invalid set to non-zero when it is not valid
241 to use the value of this register in some
244 To understand the usage of these tables, it is important to understand
245 the distinction between the value in reg_last_set_value being valid
246 and the register being validly contained in some other expression in the
249 Entry I in reg_last_set_value is valid if it is non-zero, and either
250 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
252 Register I may validly appear in any expression returned for the value
253 of another register if reg_n_sets[i] is 1. It may also appear in the
254 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
255 reg_last_set_invalid[j] is zero.
257 If an expression is found in the table containing a register which may
258 not validly appear in an expression, the register is replaced by
259 something that won't match, (clobber (const_int 0)).
261 reg_last_set_invalid[i] is set non-zero when register I is being assigned
262 to and reg_last_set_table_tick[i] == label_tick. */
264 /* Record last value assigned to (hard or pseudo) register n. */
266 static rtx *reg_last_set_value;
268 /* Record the value of label_tick when the value for register n is placed in
269 reg_last_set_value[n]. */
271 static int *reg_last_set_label;
273 /* Record the value of label_tick when an expression involving register n
274 is placed in reg_last_set_value. */
276 static int *reg_last_set_table_tick;
278 /* Set non-zero if references to register n in expressions should not be
281 static char *reg_last_set_invalid;
283 /* Incremented for each label. */
285 static int label_tick;
287 /* Some registers that are set more than once and used in more than one
288 basic block are nevertheless always set in similar ways. For example,
289 a QImode register may be loaded from memory in two places on a machine
290 where byte loads zero extend.
292 We record in the following array what we know about the nonzero
293 bits of a register, specifically which bits are known to be zero.
295 If an entry is zero, it means that we don't know anything special. */
297 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
299 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
300 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
302 static enum machine_mode nonzero_bits_mode;
304 /* Nonzero if we know that a register has some leading bits that are always
305 equal to the sign bit. */
307 static unsigned char *reg_sign_bit_copies;
309 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
310 It is zero while computing them and after combine has completed. This
311 former test prevents propagating values based on previously set values,
312 which can be incorrect if a variable is modified in a loop. */
314 static int nonzero_sign_valid;
316 /* These arrays are maintained in parallel with reg_last_set_value
317 and are used to store the mode in which the register was last set,
318 the bits that were known to be zero when it was last set, and the
319 number of sign bits copies it was known to have when it was last set. */
321 static enum machine_mode *reg_last_set_mode;
322 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
323 static char *reg_last_set_sign_bit_copies;
325 /* Record one modification to rtl structure
326 to be undone by storing old_contents into *where.
327 is_int is 1 if the contents are an int. */
333 union {rtx r; int i;} old_contents;
334 union {rtx *r; int *i;} where;
337 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
338 num_undo says how many are currently recorded.
340 storage is nonzero if we must undo the allocation of new storage.
341 The value of storage is what to pass to obfree.
343 other_insn is nonzero if we have modified some other insn in the process
344 of working on subst_insn. It must be verified too.
346 previous_undos is the value of undobuf.undos when we started processing
347 this substitution. This will prevent gen_rtx_combine from re-used a piece
348 from the previous expression. Doing so can produce circular rtl
356 struct undo *previous_undos;
360 static struct undobuf undobuf;
362 /* Number of times the pseudo being substituted for
363 was found and replaced. */
365 static int n_occurrences;
367 static void do_SUBST PARAMS ((rtx *, rtx));
368 static void do_SUBST_INT PARAMS ((int *, int));
369 static void init_reg_last_arrays PARAMS ((void));
370 static void setup_incoming_promotions PARAMS ((void));
371 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
372 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
373 static int sets_function_arg_p PARAMS ((rtx));
374 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
375 static int contains_muldiv PARAMS ((rtx));
376 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
377 static void undo_all PARAMS ((void));
378 static void undo_commit PARAMS ((void));
379 static rtx *find_split_point PARAMS ((rtx *, rtx));
380 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
381 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
382 static rtx simplify_if_then_else PARAMS ((rtx));
383 static rtx simplify_set PARAMS ((rtx));
384 static rtx simplify_logical PARAMS ((rtx, int));
385 static rtx expand_compound_operation PARAMS ((rtx));
386 static rtx expand_field_assignment PARAMS ((rtx));
387 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
388 rtx, unsigned HOST_WIDE_INT, int,
390 static rtx extract_left_shift PARAMS ((rtx, int));
391 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
392 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
393 unsigned HOST_WIDE_INT *));
394 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
395 unsigned HOST_WIDE_INT, rtx, int));
396 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
397 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
398 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
399 static rtx make_field_assignment PARAMS ((rtx));
400 static rtx apply_distributive_law PARAMS ((rtx));
401 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
402 unsigned HOST_WIDE_INT));
403 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
404 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
405 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
406 enum rtx_code, HOST_WIDE_INT,
407 enum machine_mode, int *));
408 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
410 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
411 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
412 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
414 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
416 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
417 enum machine_mode, rtx));
418 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
419 static int reversible_comparison_p PARAMS ((rtx));
420 static void update_table_tick PARAMS ((rtx));
421 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
422 static void check_promoted_subreg PARAMS ((rtx, rtx));
423 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
424 static void record_dead_and_set_regs PARAMS ((rtx));
425 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
426 static rtx get_last_value PARAMS ((rtx));
427 static int use_crosses_set_p PARAMS ((rtx, int));
428 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
429 static int reg_dead_at_p PARAMS ((rtx, rtx));
430 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
431 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
432 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
433 static void distribute_links PARAMS ((rtx));
434 static void mark_used_regs_combine PARAMS ((rtx));
435 static int insn_cuid PARAMS ((rtx));
436 static void record_promoted_value PARAMS ((rtx, rtx));
438 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
439 insn. The substitution can be undone by undo_all. If INTO is already
440 set to NEWVAL, do not record this change. Because computing NEWVAL might
441 also call SUBST, we have to compute it before we put anything into
445 do_SUBST (into, newval)
451 if (oldval == newval)
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
508 register rtx insn, next;
513 register rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in persuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, XEXP (links, 0),
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
745 compute_bb_for_insn (get_max_uid ());
746 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
751 sbitmap_free (refresh_blocks);
752 free (reg_nonzero_bits);
753 free (reg_sign_bit_copies);
754 free (reg_last_death);
756 free (reg_last_set_value);
757 free (reg_last_set_table_tick);
758 free (reg_last_set_label);
759 free (reg_last_set_invalid);
760 free (reg_last_set_mode);
761 free (reg_last_set_nonzero_bits);
762 free (reg_last_set_sign_bit_copies);
766 struct undo *undo, *next;
767 for (undo = undobuf.frees; undo; undo = next)
775 total_attempts += combine_attempts;
776 total_merges += combine_merges;
777 total_extras += combine_extras;
778 total_successes += combine_successes;
780 nonzero_sign_valid = 0;
782 /* Make recognizer allow volatile MEMs again. */
785 return new_direct_jump_p;
788 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
791 init_reg_last_arrays ()
793 unsigned int nregs = combine_max_regno;
795 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
796 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
797 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
798 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
799 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
800 bzero (reg_last_set_invalid, nregs * sizeof (char));
801 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
802 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
803 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
806 /* Set up any promoted values for incoming argument registers. */
809 setup_incoming_promotions ()
811 #ifdef PROMOTE_FUNCTION_ARGS
814 enum machine_mode mode;
816 rtx first = get_insns ();
818 #ifndef OUTGOING_REGNO
819 #define OUTGOING_REGNO(N) N
821 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
822 /* Check whether this register can hold an incoming pointer
823 argument. FUNCTION_ARG_REGNO_P tests outgoing register
824 numbers, so translate if necessary due to register windows. */
825 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
826 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
829 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
832 gen_rtx_CLOBBER (mode, const0_rtx)));
837 /* Called via note_stores. If X is a pseudo that is narrower than
838 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
840 If we are setting only a portion of X and we can't figure out what
841 portion, assume all bits will be used since we don't know what will
844 Similarly, set how many bits of X are known to be copies of the sign bit
845 at all locations in the function. This is the smallest number implied
849 set_nonzero_bits_and_sign_copies (x, set, data)
852 void *data ATTRIBUTE_UNUSED;
856 if (GET_CODE (x) == REG
857 && REGNO (x) >= FIRST_PSEUDO_REGISTER
858 /* If this register is undefined at the start of the file, we can't
859 say what its contents were. */
860 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
861 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
863 if (set == 0 || GET_CODE (set) == CLOBBER)
865 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
866 reg_sign_bit_copies[REGNO (x)] = 1;
870 /* If this is a complex assignment, see if we can convert it into a
871 simple assignment. */
872 set = expand_field_assignment (set);
874 /* If this is a simple assignment, or we have a paradoxical SUBREG,
875 set what we know about X. */
877 if (SET_DEST (set) == x
878 || (GET_CODE (SET_DEST (set)) == SUBREG
879 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
880 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
881 && SUBREG_REG (SET_DEST (set)) == x))
883 rtx src = SET_SRC (set);
885 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
886 /* If X is narrower than a word and SRC is a non-negative
887 constant that would appear negative in the mode of X,
888 sign-extend it for use in reg_nonzero_bits because some
889 machines (maybe most) will actually do the sign-extension
890 and this is the conservative approach.
892 ??? For 2.5, try to tighten up the MD files in this regard
893 instead of this kludge. */
895 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
896 && GET_CODE (src) == CONST_INT
898 && 0 != (INTVAL (src)
900 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
901 src = GEN_INT (INTVAL (src)
902 | ((HOST_WIDE_INT) (-1)
903 << GET_MODE_BITSIZE (GET_MODE (x))));
906 reg_nonzero_bits[REGNO (x)]
907 |= nonzero_bits (src, nonzero_bits_mode);
908 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
909 if (reg_sign_bit_copies[REGNO (x)] == 0
910 || reg_sign_bit_copies[REGNO (x)] > num)
911 reg_sign_bit_copies[REGNO (x)] = num;
915 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
916 reg_sign_bit_copies[REGNO (x)] = 1;
921 /* See if INSN can be combined into I3. PRED and SUCC are optionally
922 insns that were previously combined into I3 or that will be combined
923 into the merger of INSN and I3.
925 Return 0 if the combination is not allowed for any reason.
927 If the combination is allowed, *PDEST will be set to the single
928 destination of INSN and *PSRC to the single source, and this function
932 can_combine_p (insn, i3, pred, succ, pdest, psrc)
935 rtx pred ATTRIBUTE_UNUSED;
940 rtx set = 0, src, dest;
945 int all_adjacent = (succ ? (next_active_insn (insn) == succ
946 && next_active_insn (succ) == i3)
947 : next_active_insn (insn) == i3);
949 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
950 or a PARALLEL consisting of such a SET and CLOBBERs.
952 If INSN has CLOBBER parallel parts, ignore them for our processing.
953 By definition, these happen during the execution of the insn. When it
954 is merged with another insn, all bets are off. If they are, in fact,
955 needed and aren't also supplied in I3, they may be added by
956 recog_for_combine. Otherwise, it won't match.
958 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
961 Get the source and destination of INSN. If more than one, can't
964 if (GET_CODE (PATTERN (insn)) == SET)
965 set = PATTERN (insn);
966 else if (GET_CODE (PATTERN (insn)) == PARALLEL
967 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
969 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
971 rtx elt = XVECEXP (PATTERN (insn), 0, i);
973 switch (GET_CODE (elt))
975 /* This is important to combine floating point insns
978 /* Combining an isolated USE doesn't make sense.
979 We depend here on combinable_i3_pat to reject them. */
980 /* The code below this loop only verifies that the inputs of
981 the SET in INSN do not change. We call reg_set_between_p
982 to verify that the REG in the USE does not change betweeen
984 If the USE in INSN was for a pseudo register, the matching
985 insn pattern will likely match any register; combining this
986 with any other USE would only be safe if we knew that the
987 used registers have identical values, or if there was
988 something to tell them apart, e.g. different modes. For
989 now, we forgo such compilcated tests and simply disallow
990 combining of USES of pseudo registers with any other USE. */
991 if (GET_CODE (XEXP (elt, 0)) == REG
992 && GET_CODE (PATTERN (i3)) == PARALLEL)
994 rtx i3pat = PATTERN (i3);
995 int i = XVECLEN (i3pat, 0) - 1;
996 unsigned int regno = REGNO (XEXP (elt, 0));
1000 rtx i3elt = XVECEXP (i3pat, 0, i);
1002 if (GET_CODE (i3elt) == USE
1003 && GET_CODE (XEXP (i3elt, 0)) == REG
1004 && (REGNO (XEXP (i3elt, 0)) == regno
1005 ? reg_set_between_p (XEXP (elt, 0),
1006 PREV_INSN (insn), i3)
1007 : regno >= FIRST_PSEUDO_REGISTER))
1014 /* We can ignore CLOBBERs. */
1019 /* Ignore SETs whose result isn't used but not those that
1020 have side-effects. */
1021 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1022 && ! side_effects_p (elt))
1025 /* If we have already found a SET, this is a second one and
1026 so we cannot combine with this insn. */
1034 /* Anything else means we can't combine. */
1040 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1041 so don't do anything with it. */
1042 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1051 set = expand_field_assignment (set);
1052 src = SET_SRC (set), dest = SET_DEST (set);
1054 /* Don't eliminate a store in the stack pointer. */
1055 if (dest == stack_pointer_rtx
1056 /* If we couldn't eliminate a field assignment, we can't combine. */
1057 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1058 /* Don't combine with an insn that sets a register to itself if it has
1059 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1060 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1061 /* Can't merge a function call. */
1062 || GET_CODE (src) == CALL
1063 /* Don't eliminate a function call argument. */
1064 || (GET_CODE (i3) == CALL_INSN
1065 && (find_reg_fusage (i3, USE, dest)
1066 || (GET_CODE (dest) == REG
1067 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1068 && global_regs[REGNO (dest)])))
1069 /* Don't substitute into an incremented register. */
1070 || FIND_REG_INC_NOTE (i3, dest)
1071 || (succ && FIND_REG_INC_NOTE (succ, dest))
1073 /* Don't combine the end of a libcall into anything. */
1074 /* ??? This gives worse code, and appears to be unnecessary, since no
1075 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1076 use REG_RETVAL notes for noconflict blocks, but other code here
1077 makes sure that those insns don't disappear. */
1078 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1080 /* Make sure that DEST is not used after SUCC but before I3. */
1081 || (succ && ! all_adjacent
1082 && reg_used_between_p (dest, succ, i3))
1083 /* Make sure that the value that is to be substituted for the register
1084 does not use any registers whose values alter in between. However,
1085 If the insns are adjacent, a use can't cross a set even though we
1086 think it might (this can happen for a sequence of insns each setting
1087 the same destination; reg_last_set of that register might point to
1088 a NOTE). If INSN has a REG_EQUIV note, the register is always
1089 equivalent to the memory so the substitution is valid even if there
1090 are intervening stores. Also, don't move a volatile asm or
1091 UNSPEC_VOLATILE across any other insns. */
1093 && (((GET_CODE (src) != MEM
1094 || ! find_reg_note (insn, REG_EQUIV, src))
1095 && use_crosses_set_p (src, INSN_CUID (insn)))
1096 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1097 || GET_CODE (src) == UNSPEC_VOLATILE))
1098 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1099 better register allocation by not doing the combine. */
1100 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1101 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1102 /* Don't combine across a CALL_INSN, because that would possibly
1103 change whether the life span of some REGs crosses calls or not,
1104 and it is a pain to update that information.
1105 Exception: if source is a constant, moving it later can't hurt.
1106 Accept that special case, because it helps -fforce-addr a lot. */
1107 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1110 /* DEST must either be a REG or CC0. */
1111 if (GET_CODE (dest) == REG)
1113 /* If register alignment is being enforced for multi-word items in all
1114 cases except for parameters, it is possible to have a register copy
1115 insn referencing a hard register that is not allowed to contain the
1116 mode being copied and which would not be valid as an operand of most
1117 insns. Eliminate this problem by not combining with such an insn.
1119 Also, on some machines we don't want to extend the life of a hard
1122 This is the same test done in can_combine except that we don't test
1123 if SRC is a CALL operation to permit a hard register with
1124 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1139 || (SMALL_REGISTER_CLASSES
1140 && ((! all_adjacent && ! REG_USERVAR_P (src))
1141 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1142 && ! REG_USERVAR_P (src))))))))
1145 else if (GET_CODE (dest) != CC0)
1148 /* Don't substitute for a register intended as a clobberable operand.
1149 Similarly, don't substitute an expression containing a register that
1150 will be clobbered in I3. */
1151 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1152 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1153 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1154 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1156 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1159 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1160 or not), reject, unless nothing volatile comes between it and I3 */
1162 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1164 /* Make sure succ doesn't contain a volatile reference. */
1165 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1168 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1169 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1173 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1174 to be an explicit register variable, and was chosen for a reason. */
1176 if (GET_CODE (src) == ASM_OPERANDS
1177 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1180 /* If there are any volatile insns between INSN and I3, reject, because
1181 they might affect machine state. */
1183 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1184 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1187 /* If INSN or I2 contains an autoincrement or autodecrement,
1188 make sure that register is not used between there and I3,
1189 and not already used in I3 either.
1190 Also insist that I3 not be a jump; if it were one
1191 and the incremented register were spilled, we would lose. */
1194 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1195 if (REG_NOTE_KIND (link) == REG_INC
1196 && (GET_CODE (i3) == JUMP_INSN
1197 || reg_used_between_p (XEXP (link, 0), insn, i3)
1198 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1203 /* Don't combine an insn that follows a CC0-setting insn.
1204 An insn that uses CC0 must not be separated from the one that sets it.
1205 We do, however, allow I2 to follow a CC0-setting insn if that insn
1206 is passed as I1; in that case it will be deleted also.
1207 We also allow combining in this case if all the insns are adjacent
1208 because that would leave the two CC0 insns adjacent as well.
1209 It would be more logical to test whether CC0 occurs inside I1 or I2,
1210 but that would be much slower, and this ought to be equivalent. */
1212 p = prev_nonnote_insn (insn);
1213 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1218 /* If we get here, we have passed all the tests and the combination is
1227 /* Check if PAT is an insn - or a part of it - used to set up an
1228 argument for a function in a hard register. */
1231 sets_function_arg_p (pat)
1237 switch (GET_CODE (pat))
1240 return sets_function_arg_p (PATTERN (pat));
1243 for (i = XVECLEN (pat, 0); --i >= 0;)
1244 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1250 inner_dest = SET_DEST (pat);
1251 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1252 || GET_CODE (inner_dest) == SUBREG
1253 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1254 inner_dest = XEXP (inner_dest, 0);
1256 return (GET_CODE (inner_dest) == REG
1257 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1258 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1267 /* LOC is the location within I3 that contains its pattern or the component
1268 of a PARALLEL of the pattern. We validate that it is valid for combining.
1270 One problem is if I3 modifies its output, as opposed to replacing it
1271 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1272 so would produce an insn that is not equivalent to the original insns.
1276 (set (reg:DI 101) (reg:DI 100))
1277 (set (subreg:SI (reg:DI 101) 0) <foo>)
1279 This is NOT equivalent to:
1281 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1282 (set (reg:DI 101) (reg:DI 100))])
1284 Not only does this modify 100 (in which case it might still be valid
1285 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1287 We can also run into a problem if I2 sets a register that I1
1288 uses and I1 gets directly substituted into I3 (not via I2). In that
1289 case, we would be getting the wrong value of I2DEST into I3, so we
1290 must reject the combination. This case occurs when I2 and I1 both
1291 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1292 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1293 of a SET must prevent combination from occurring.
1295 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1296 if the destination of a SET is a hard register that isn't a user
1299 Before doing the above check, we first try to expand a field assignment
1300 into a set of logical operations.
1302 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1303 we place a register that is both set and used within I3. If more than one
1304 such register is detected, we fail.
1306 Return 1 if the combination is valid, zero otherwise. */
1309 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1315 rtx *pi3dest_killed;
1319 if (GET_CODE (x) == SET)
1321 rtx set = expand_field_assignment (x);
1322 rtx dest = SET_DEST (set);
1323 rtx src = SET_SRC (set);
1324 rtx inner_dest = dest;
1327 rtx inner_src = src;
1332 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1333 || GET_CODE (inner_dest) == SUBREG
1334 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1335 inner_dest = XEXP (inner_dest, 0);
1337 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1340 while (GET_CODE (inner_src) == STRICT_LOW_PART
1341 || GET_CODE (inner_src) == SUBREG
1342 || GET_CODE (inner_src) == ZERO_EXTRACT)
1343 inner_src = XEXP (inner_src, 0);
1345 /* If it is better that two different modes keep two different pseudos,
1346 avoid combining them. This avoids producing the following pattern
1348 (set (subreg:SI (reg/v:QI 21) 0)
1349 (lshiftrt:SI (reg/v:SI 20)
1351 If that were made, reload could not handle the pair of
1352 reg 20/21, since it would try to get any GENERAL_REGS
1353 but some of them don't handle QImode. */
1355 if (rtx_equal_p (inner_src, i2dest)
1356 && GET_CODE (inner_dest) == REG
1357 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1361 /* Check for the case where I3 modifies its output, as
1363 if ((inner_dest != dest
1364 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1365 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1367 /* This is the same test done in can_combine_p except that we
1368 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1369 CALL operation. Moreover, we can't test all_adjacent; we don't
1370 have to, since this instruction will stay in place, thus we are
1371 not considering increasing the lifetime of INNER_DEST.
1373 Also, if this insn sets a function argument, combining it with
1374 something that might need a spill could clobber a previous
1375 function argument; the all_adjacent test in can_combine_p also
1376 checks this; here, we do a more specific test for this case. */
1378 || (GET_CODE (inner_dest) == REG
1379 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1380 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1381 GET_MODE (inner_dest))
1382 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1383 && ! REG_USERVAR_P (inner_dest)
1384 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1385 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1387 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1388 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1391 /* If DEST is used in I3, it is being killed in this insn,
1392 so record that for later.
1393 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1394 STACK_POINTER_REGNUM, since these are always considered to be
1395 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1396 if (pi3dest_killed && GET_CODE (dest) == REG
1397 && reg_referenced_p (dest, PATTERN (i3))
1398 && REGNO (dest) != FRAME_POINTER_REGNUM
1399 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1400 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1402 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1403 && (REGNO (dest) != ARG_POINTER_REGNUM
1404 || ! fixed_regs [REGNO (dest)])
1406 && REGNO (dest) != STACK_POINTER_REGNUM)
1408 if (*pi3dest_killed)
1411 *pi3dest_killed = dest;
1415 else if (GET_CODE (x) == PARALLEL)
1419 for (i = 0; i < XVECLEN (x, 0); i++)
1420 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1421 i1_not_in_src, pi3dest_killed))
1428 /* Return 1 if X is an arithmetic expression that contains a multiplication
1429 and division. We don't count multiplications by powers of two here. */
1435 switch (GET_CODE (x))
1437 case MOD: case DIV: case UMOD: case UDIV:
1441 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1442 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1444 switch (GET_RTX_CLASS (GET_CODE (x)))
1446 case 'c': case '<': case '2':
1447 return contains_muldiv (XEXP (x, 0))
1448 || contains_muldiv (XEXP (x, 1));
1451 return contains_muldiv (XEXP (x, 0));
1459 /* Try to combine the insns I1 and I2 into I3.
1460 Here I1 and I2 appear earlier than I3.
1461 I1 can be zero; then we combine just I2 into I3.
1463 It we are combining three insns and the resulting insn is not recognized,
1464 try splitting it into two insns. If that happens, I2 and I3 are retained
1465 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1468 Return 0 if the combination does not work. Then nothing is changed.
1469 If we did the combination, return the insn at which combine should
1472 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1473 new direct jump instruction. */
1476 try_combine (i3, i2, i1, new_direct_jump_p)
1477 register rtx i3, i2, i1;
1478 register int *new_direct_jump_p;
1480 /* New patterns for I3 and I2, respectively. */
1481 rtx newpat, newi2pat = 0;
1482 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1483 int added_sets_1, added_sets_2;
1484 /* Total number of SETs to put into I3. */
1486 /* Nonzero is I2's body now appears in I3. */
1488 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1489 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1490 /* Contains I3 if the destination of I3 is used in its source, which means
1491 that the old life of I3 is being killed. If that usage is placed into
1492 I2 and not in I3, a REG_DEAD note must be made. */
1493 rtx i3dest_killed = 0;
1494 /* SET_DEST and SET_SRC of I2 and I1. */
1495 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1496 /* PATTERN (I2), or a copy of it in certain cases. */
1498 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1499 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1500 int i1_feeds_i3 = 0;
1501 /* Notes that must be added to REG_NOTES in I3 and I2. */
1502 rtx new_i3_notes, new_i2_notes;
1503 /* Notes that we substituted I3 into I2 instead of the normal case. */
1504 int i3_subst_into_i2 = 0;
1505 /* Notes that I1, I2 or I3 is a MULT operation. */
1513 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1514 This can occur when flow deletes an insn that it has merged into an
1515 auto-increment address. We also can't do anything if I3 has a
1516 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1519 if (! INSN_P (i3) || ! INSN_P (i2) || (i1 && ! INSN_P (i1))
1521 /* ??? This gives worse code, and appears to be unnecessary, since no
1522 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1523 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1529 undobuf.other_insn = 0;
1531 /* Save the current high-water-mark so we can free storage if we didn't
1532 accept this combination. */
1533 undobuf.storage = (char *) oballoc (0);
1535 /* Reset the hard register usage information. */
1536 CLEAR_HARD_REG_SET (newpat_used_regs);
1538 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1539 code below, set I1 to be the earlier of the two insns. */
1540 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1541 temp = i1, i1 = i2, i2 = temp;
1543 added_links_insn = 0;
1545 /* First check for one important special-case that the code below will
1546 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1547 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1548 we may be able to replace that destination with the destination of I3.
1549 This occurs in the common code where we compute both a quotient and
1550 remainder into a structure, in which case we want to do the computation
1551 directly into the structure to avoid register-register copies.
1553 We make very conservative checks below and only try to handle the
1554 most common cases of this. For example, we only handle the case
1555 where I2 and I3 are adjacent to avoid making difficult register
1558 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1560 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1561 && (! SMALL_REGISTER_CLASSES
1562 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1563 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1564 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1565 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1566 && GET_CODE (PATTERN (i2)) == PARALLEL
1567 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1568 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1569 below would need to check what is inside (and reg_overlap_mentioned_p
1570 doesn't support those codes anyway). Don't allow those destinations;
1571 the resulting insn isn't likely to be recognized anyway. */
1572 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1573 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1574 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1575 SET_DEST (PATTERN (i3)))
1576 && next_real_insn (i2) == i3)
1578 rtx p2 = PATTERN (i2);
1580 /* Make sure that the destination of I3,
1581 which we are going to substitute into one output of I2,
1582 is not used within another output of I2. We must avoid making this:
1583 (parallel [(set (mem (reg 69)) ...)
1584 (set (reg 69) ...)])
1585 which is not well-defined as to order of actions.
1586 (Besides, reload can't handle output reloads for this.)
1588 The problem can also happen if the dest of I3 is a memory ref,
1589 if another dest in I2 is an indirect memory ref. */
1590 for (i = 0; i < XVECLEN (p2, 0); i++)
1591 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1592 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1593 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1594 SET_DEST (XVECEXP (p2, 0, i))))
1597 if (i == XVECLEN (p2, 0))
1598 for (i = 0; i < XVECLEN (p2, 0); i++)
1599 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1600 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1601 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1606 subst_low_cuid = INSN_CUID (i2);
1608 added_sets_2 = added_sets_1 = 0;
1609 i2dest = SET_SRC (PATTERN (i3));
1611 /* Replace the dest in I2 with our dest and make the resulting
1612 insn the new pattern for I3. Then skip to where we
1613 validate the pattern. Everything was set up above. */
1614 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1615 SET_DEST (PATTERN (i3)));
1618 i3_subst_into_i2 = 1;
1619 goto validate_replacement;
1623 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1624 one of those words to another constant, merge them by making a new
1627 && (temp = single_set (i2)) != 0
1628 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1629 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1630 && GET_CODE (SET_DEST (temp)) == REG
1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1633 && GET_CODE (PATTERN (i3)) == SET
1634 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1635 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1636 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1637 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1638 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1640 HOST_WIDE_INT lo, hi;
1642 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1643 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1646 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1647 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1650 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1651 lo = INTVAL (SET_SRC (PATTERN (i3)));
1653 hi = INTVAL (SET_SRC (PATTERN (i3)));
1657 subst_low_cuid = INSN_CUID (i2);
1658 added_sets_2 = added_sets_1 = 0;
1659 i2dest = SET_DEST (temp);
1661 SUBST (SET_SRC (temp),
1662 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1664 newpat = PATTERN (i2);
1665 i3_subst_into_i2 = 1;
1666 goto validate_replacement;
1670 /* If we have no I1 and I2 looks like:
1671 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1673 make up a dummy I1 that is
1676 (set (reg:CC X) (compare:CC Y (const_int 0)))
1678 (We can ignore any trailing CLOBBERs.)
1680 This undoes a previous combination and allows us to match a branch-and-
1683 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1684 && XVECLEN (PATTERN (i2), 0) >= 2
1685 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1686 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1688 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1689 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1690 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1691 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1692 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1693 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1695 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1696 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1701 /* We make I1 with the same INSN_UID as I2. This gives it
1702 the same INSN_CUID for value tracking. Our fake I1 will
1703 never appear in the insn stream so giving it the same INSN_UID
1704 as I2 will not cause a problem. */
1706 subst_prev_insn = i1
1707 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1708 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1711 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1712 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1713 SET_DEST (PATTERN (i1)));
1718 /* Verify that I2 and I1 are valid for combining. */
1719 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1720 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1726 /* Record whether I2DEST is used in I2SRC and similarly for the other
1727 cases. Knowing this will help in register status updating below. */
1728 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1729 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1730 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1732 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1734 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1736 /* Ensure that I3's pattern can be the destination of combines. */
1737 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1738 i1 && i2dest_in_i1src && i1_feeds_i3,
1745 /* See if any of the insns is a MULT operation. Unless one is, we will
1746 reject a combination that is, since it must be slower. Be conservative
1748 if (GET_CODE (i2src) == MULT
1749 || (i1 != 0 && GET_CODE (i1src) == MULT)
1750 || (GET_CODE (PATTERN (i3)) == SET
1751 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1754 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1755 We used to do this EXCEPT in one case: I3 has a post-inc in an
1756 output operand. However, that exception can give rise to insns like
1758 which is a famous insn on the PDP-11 where the value of r3 used as the
1759 source was model-dependent. Avoid this sort of thing. */
1762 if (!(GET_CODE (PATTERN (i3)) == SET
1763 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1764 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1765 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1766 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1767 /* It's not the exception. */
1770 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1771 if (REG_NOTE_KIND (link) == REG_INC
1772 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1774 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1781 /* See if the SETs in I1 or I2 need to be kept around in the merged
1782 instruction: whenever the value set there is still needed past I3.
1783 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1785 For the SET in I1, we have two cases: If I1 and I2 independently
1786 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1787 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1788 in I1 needs to be kept around unless I1DEST dies or is set in either
1789 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1790 I1DEST. If so, we know I1 feeds into I2. */
1792 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1795 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1796 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1798 /* If the set in I2 needs to be kept around, we must make a copy of
1799 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1800 PATTERN (I2), we are only substituting for the original I1DEST, not into
1801 an already-substituted copy. This also prevents making self-referential
1802 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1805 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1806 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1810 i2pat = copy_rtx (i2pat);
1814 /* Substitute in the latest insn for the regs set by the earlier ones. */
1816 maxreg = max_reg_num ();
1820 /* It is possible that the source of I2 or I1 may be performing an
1821 unneeded operation, such as a ZERO_EXTEND of something that is known
1822 to have the high part zero. Handle that case by letting subst look at
1823 the innermost one of them.
1825 Another way to do this would be to have a function that tries to
1826 simplify a single insn instead of merging two or more insns. We don't
1827 do this because of the potential of infinite loops and because
1828 of the potential extra memory required. However, doing it the way
1829 we are is a bit of a kludge and doesn't catch all cases.
1831 But only do this if -fexpensive-optimizations since it slows things down
1832 and doesn't usually win. */
1834 if (flag_expensive_optimizations)
1836 /* Pass pc_rtx so no substitutions are done, just simplifications.
1837 The cases that we are interested in here do not involve the few
1838 cases were is_replaced is checked. */
1841 subst_low_cuid = INSN_CUID (i1);
1842 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1846 subst_low_cuid = INSN_CUID (i2);
1847 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1850 undobuf.previous_undos = undobuf.undos;
1854 /* Many machines that don't use CC0 have insns that can both perform an
1855 arithmetic operation and set the condition code. These operations will
1856 be represented as a PARALLEL with the first element of the vector
1857 being a COMPARE of an arithmetic operation with the constant zero.
1858 The second element of the vector will set some pseudo to the result
1859 of the same arithmetic operation. If we simplify the COMPARE, we won't
1860 match such a pattern and so will generate an extra insn. Here we test
1861 for this case, where both the comparison and the operation result are
1862 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1863 I2SRC. Later we will make the PARALLEL that contains I2. */
1865 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1866 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1867 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1868 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1870 #ifdef EXTRA_CC_MODES
1872 enum machine_mode compare_mode;
1875 newpat = PATTERN (i3);
1876 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1880 #ifdef EXTRA_CC_MODES
1881 /* See if a COMPARE with the operand we substituted in should be done
1882 with the mode that is currently being used. If not, do the same
1883 processing we do in `subst' for a SET; namely, if the destination
1884 is used only once, try to replace it with a register of the proper
1885 mode and also replace the COMPARE. */
1886 if (undobuf.other_insn == 0
1887 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1888 &undobuf.other_insn))
1889 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1891 != GET_MODE (SET_DEST (newpat))))
1893 unsigned int regno = REGNO (SET_DEST (newpat));
1894 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1896 if (regno < FIRST_PSEUDO_REGISTER
1897 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1898 && ! REG_USERVAR_P (SET_DEST (newpat))))
1900 if (regno >= FIRST_PSEUDO_REGISTER)
1901 SUBST (regno_reg_rtx[regno], new_dest);
1903 SUBST (SET_DEST (newpat), new_dest);
1904 SUBST (XEXP (*cc_use, 0), new_dest);
1905 SUBST (SET_SRC (newpat),
1906 gen_rtx_combine (COMPARE, compare_mode,
1907 i2src, const0_rtx));
1910 undobuf.other_insn = 0;
1917 n_occurrences = 0; /* `subst' counts here */
1919 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1920 need to make a unique copy of I2SRC each time we substitute it
1921 to avoid self-referential rtl. */
1923 subst_low_cuid = INSN_CUID (i2);
1924 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1925 ! i1_feeds_i3 && i1dest_in_i1src);
1926 undobuf.previous_undos = undobuf.undos;
1928 /* Record whether i2's body now appears within i3's body. */
1929 i2_is_used = n_occurrences;
1932 /* If we already got a failure, don't try to do more. Otherwise,
1933 try to substitute in I1 if we have it. */
1935 if (i1 && GET_CODE (newpat) != CLOBBER)
1937 /* Before we can do this substitution, we must redo the test done
1938 above (see detailed comments there) that ensures that I1DEST
1939 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1941 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1949 subst_low_cuid = INSN_CUID (i1);
1950 newpat = subst (newpat, i1dest, i1src, 0, 0);
1951 undobuf.previous_undos = undobuf.undos;
1954 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1955 to count all the ways that I2SRC and I1SRC can be used. */
1956 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1957 && i2_is_used + added_sets_2 > 1)
1958 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1959 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1961 /* Fail if we tried to make a new register (we used to abort, but there's
1962 really no reason to). */
1963 || max_reg_num () != maxreg
1964 /* Fail if we couldn't do something and have a CLOBBER. */
1965 || GET_CODE (newpat) == CLOBBER
1966 /* Fail if this new pattern is a MULT and we didn't have one before
1967 at the outer level. */
1968 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1975 /* If the actions of the earlier insns must be kept
1976 in addition to substituting them into the latest one,
1977 we must make a new PARALLEL for the latest insn
1978 to hold additional the SETs. */
1980 if (added_sets_1 || added_sets_2)
1984 if (GET_CODE (newpat) == PARALLEL)
1986 rtvec old = XVEC (newpat, 0);
1987 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1988 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1989 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1990 sizeof (old->elem[0]) * old->num_elem);
1995 total_sets = 1 + added_sets_1 + added_sets_2;
1996 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1997 XVECEXP (newpat, 0, 0) = old;
2001 XVECEXP (newpat, 0, --total_sets)
2002 = (GET_CODE (PATTERN (i1)) == PARALLEL
2003 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2007 /* If there is no I1, use I2's body as is. We used to also not do
2008 the subst call below if I2 was substituted into I3,
2009 but that could lose a simplification. */
2011 XVECEXP (newpat, 0, --total_sets) = i2pat;
2013 /* See comment where i2pat is assigned. */
2014 XVECEXP (newpat, 0, --total_sets)
2015 = subst (i2pat, i1dest, i1src, 0, 0);
2019 /* We come here when we are replacing a destination in I2 with the
2020 destination of I3. */
2021 validate_replacement:
2023 /* Note which hard regs this insn has as inputs. */
2024 mark_used_regs_combine (newpat);
2026 /* Is the result of combination a valid instruction? */
2027 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2029 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2030 the second SET's destination is a register that is unused. In that case,
2031 we just need the first SET. This can occur when simplifying a divmod
2032 insn. We *must* test for this case here because the code below that
2033 splits two independent SETs doesn't handle this case correctly when it
2034 updates the register status. Also check the case where the first
2035 SET's destination is unused. That would not cause incorrect code, but
2036 does cause an unneeded insn to remain. */
2038 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2039 && XVECLEN (newpat, 0) == 2
2040 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2041 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2042 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2043 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2044 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2045 && asm_noperands (newpat) < 0)
2047 newpat = XVECEXP (newpat, 0, 0);
2048 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2051 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2052 && XVECLEN (newpat, 0) == 2
2053 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2054 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2056 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2057 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2058 && asm_noperands (newpat) < 0)
2060 newpat = XVECEXP (newpat, 0, 1);
2061 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2064 /* If we were combining three insns and the result is a simple SET
2065 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2066 insns. There are two ways to do this. It can be split using a
2067 machine-specific method (like when you have an addition of a large
2068 constant) or by combine in the function find_split_point. */
2070 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2071 && asm_noperands (newpat) < 0)
2073 rtx m_split, *split;
2074 rtx ni2dest = i2dest;
2076 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2077 use I2DEST as a scratch register will help. In the latter case,
2078 convert I2DEST to the mode of the source of NEWPAT if we can. */
2080 m_split = split_insns (newpat, i3);
2082 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2083 inputs of NEWPAT. */
2085 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2086 possible to try that as a scratch reg. This would require adding
2087 more code to make it work though. */
2089 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2091 /* If I2DEST is a hard register or the only use of a pseudo,
2092 we can change its mode. */
2093 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2094 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2095 && GET_CODE (i2dest) == REG
2096 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2097 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2098 && ! REG_USERVAR_P (i2dest))))
2099 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2102 m_split = split_insns (gen_rtx_PARALLEL
2104 gen_rtvec (2, newpat,
2105 gen_rtx_CLOBBER (VOIDmode,
2110 if (m_split && GET_CODE (m_split) == SEQUENCE
2111 && XVECLEN (m_split, 0) == 2
2112 && (next_real_insn (i2) == i3
2113 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2117 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2118 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2120 i3set = single_set (XVECEXP (m_split, 0, 1));
2121 i2set = single_set (XVECEXP (m_split, 0, 0));
2123 /* In case we changed the mode of I2DEST, replace it in the
2124 pseudo-register table here. We can't do it above in case this
2125 code doesn't get executed and we do a split the other way. */
2127 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2128 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2130 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2132 /* If I2 or I3 has multiple SETs, we won't know how to track
2133 register status, so don't use these insns. If I2's destination
2134 is used between I2 and I3, we also can't use these insns. */
2136 if (i2_code_number >= 0 && i2set && i3set
2137 && (next_real_insn (i2) == i3
2138 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2139 insn_code_number = recog_for_combine (&newi3pat, i3,
2141 if (insn_code_number >= 0)
2144 /* It is possible that both insns now set the destination of I3.
2145 If so, we must show an extra use of it. */
2147 if (insn_code_number >= 0)
2149 rtx new_i3_dest = SET_DEST (i3set);
2150 rtx new_i2_dest = SET_DEST (i2set);
2152 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2153 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2154 || GET_CODE (new_i3_dest) == SUBREG)
2155 new_i3_dest = XEXP (new_i3_dest, 0);
2157 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2158 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2159 || GET_CODE (new_i2_dest) == SUBREG)
2160 new_i2_dest = XEXP (new_i2_dest, 0);
2162 if (GET_CODE (new_i3_dest) == REG
2163 && GET_CODE (new_i2_dest) == REG
2164 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2165 REG_N_SETS (REGNO (new_i2_dest))++;
2169 /* If we can split it and use I2DEST, go ahead and see if that
2170 helps things be recognized. Verify that none of the registers
2171 are set between I2 and I3. */
2172 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2174 && GET_CODE (i2dest) == REG
2176 /* We need I2DEST in the proper mode. If it is a hard register
2177 or the only use of a pseudo, we can change its mode. */
2178 && (GET_MODE (*split) == GET_MODE (i2dest)
2179 || GET_MODE (*split) == VOIDmode
2180 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2181 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2182 && ! REG_USERVAR_P (i2dest)))
2183 && (next_real_insn (i2) == i3
2184 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2185 /* We can't overwrite I2DEST if its value is still used by
2187 && ! reg_referenced_p (i2dest, newpat))
2189 rtx newdest = i2dest;
2190 enum rtx_code split_code = GET_CODE (*split);
2191 enum machine_mode split_mode = GET_MODE (*split);
2193 /* Get NEWDEST as a register in the proper mode. We have already
2194 validated that we can do this. */
2195 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2197 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2199 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2200 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2203 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2204 an ASHIFT. This can occur if it was inside a PLUS and hence
2205 appeared to be a memory address. This is a kludge. */
2206 if (split_code == MULT
2207 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2208 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2210 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2211 XEXP (*split, 0), GEN_INT (i)));
2212 /* Update split_code because we may not have a multiply
2214 split_code = GET_CODE (*split);
2217 #ifdef INSN_SCHEDULING
2218 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2219 be written as a ZERO_EXTEND. */
2220 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2221 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2225 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2226 SUBST (*split, newdest);
2227 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2229 /* If the split point was a MULT and we didn't have one before,
2230 don't use one now. */
2231 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2232 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2236 /* Check for a case where we loaded from memory in a narrow mode and
2237 then sign extended it, but we need both registers. In that case,
2238 we have a PARALLEL with both loads from the same memory location.
2239 We can split this into a load from memory followed by a register-register
2240 copy. This saves at least one insn, more if register allocation can
2243 We cannot do this if the destination of the second assignment is
2244 a register that we have already assumed is zero-extended. Similarly
2245 for a SUBREG of such a register. */
2247 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2248 && GET_CODE (newpat) == PARALLEL
2249 && XVECLEN (newpat, 0) == 2
2250 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2251 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2252 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2253 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2254 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2255 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2257 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2258 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2259 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2260 (GET_CODE (temp) == REG
2261 && reg_nonzero_bits[REGNO (temp)] != 0
2262 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2263 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2264 && (reg_nonzero_bits[REGNO (temp)]
2265 != GET_MODE_MASK (word_mode))))
2266 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2267 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2268 (GET_CODE (temp) == REG
2269 && reg_nonzero_bits[REGNO (temp)] != 0
2270 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2271 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2272 && (reg_nonzero_bits[REGNO (temp)]
2273 != GET_MODE_MASK (word_mode)))))
2274 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2275 SET_SRC (XVECEXP (newpat, 0, 1)))
2276 && ! find_reg_note (i3, REG_UNUSED,
2277 SET_DEST (XVECEXP (newpat, 0, 0))))
2281 newi2pat = XVECEXP (newpat, 0, 0);
2282 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2283 newpat = XVECEXP (newpat, 0, 1);
2284 SUBST (SET_SRC (newpat),
2285 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2286 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2288 if (i2_code_number >= 0)
2289 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2291 if (insn_code_number >= 0)
2296 /* If we will be able to accept this, we have made a change to the
2297 destination of I3. This can invalidate a LOG_LINKS pointing
2298 to I3. No other part of combine.c makes such a transformation.
2300 The new I3 will have a destination that was previously the
2301 destination of I1 or I2 and which was used in i2 or I3. Call
2302 distribute_links to make a LOG_LINK from the next use of
2303 that destination. */
2305 PATTERN (i3) = newpat;
2306 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2308 /* I3 now uses what used to be its destination and which is
2309 now I2's destination. That means we need a LOG_LINK from
2310 I3 to I2. But we used to have one, so we still will.
2312 However, some later insn might be using I2's dest and have
2313 a LOG_LINK pointing at I3. We must remove this link.
2314 The simplest way to remove the link is to point it at I1,
2315 which we know will be a NOTE. */
2317 for (insn = NEXT_INSN (i3);
2318 insn && (this_basic_block == n_basic_blocks - 1
2319 || insn != BLOCK_HEAD (this_basic_block + 1));
2320 insn = NEXT_INSN (insn))
2322 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2324 for (link = LOG_LINKS (insn); link;
2325 link = XEXP (link, 1))
2326 if (XEXP (link, 0) == i3)
2327 XEXP (link, 0) = i1;
2335 /* Similarly, check for a case where we have a PARALLEL of two independent
2336 SETs but we started with three insns. In this case, we can do the sets
2337 as two separate insns. This case occurs when some SET allows two
2338 other insns to combine, but the destination of that SET is still live. */
2340 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2341 && GET_CODE (newpat) == PARALLEL
2342 && XVECLEN (newpat, 0) == 2
2343 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2344 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2345 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2346 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2347 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2348 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2349 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2351 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2352 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2353 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2354 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2355 XVECEXP (newpat, 0, 0))
2356 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2357 XVECEXP (newpat, 0, 1))
2358 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2359 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2361 /* Normally, it doesn't matter which of the two is done first,
2362 but it does if one references cc0. In that case, it has to
2365 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2367 newi2pat = XVECEXP (newpat, 0, 0);
2368 newpat = XVECEXP (newpat, 0, 1);
2373 newi2pat = XVECEXP (newpat, 0, 1);
2374 newpat = XVECEXP (newpat, 0, 0);
2377 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2379 if (i2_code_number >= 0)
2380 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2383 /* If it still isn't recognized, fail and change things back the way they
2385 if ((insn_code_number < 0
2386 /* Is the result a reasonable ASM_OPERANDS? */
2387 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2393 /* If we had to change another insn, make sure it is valid also. */
2394 if (undobuf.other_insn)
2396 rtx other_pat = PATTERN (undobuf.other_insn);
2397 rtx new_other_notes;
2400 CLEAR_HARD_REG_SET (newpat_used_regs);
2402 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2405 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2411 PATTERN (undobuf.other_insn) = other_pat;
2413 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2414 are still valid. Then add any non-duplicate notes added by
2415 recog_for_combine. */
2416 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2418 next = XEXP (note, 1);
2420 if (REG_NOTE_KIND (note) == REG_UNUSED
2421 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2423 if (GET_CODE (XEXP (note, 0)) == REG)
2424 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2426 remove_note (undobuf.other_insn, note);
2430 for (note = new_other_notes; note; note = XEXP (note, 1))
2431 if (GET_CODE (XEXP (note, 0)) == REG)
2432 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2434 distribute_notes (new_other_notes, undobuf.other_insn,
2435 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2438 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2439 they are adjacent to each other or not. */
2441 rtx p = prev_nonnote_insn (i3);
2442 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2443 && sets_cc0_p (newi2pat))
2451 /* We now know that we can do this combination. Merge the insns and
2452 update the status of registers and LOG_LINKS. */
2455 rtx i3notes, i2notes, i1notes = 0;
2456 rtx i3links, i2links, i1links = 0;
2459 /* Compute which registers we expect to eliminate. newi2pat may be setting
2460 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2461 same as i3dest, in which case newi2pat may be setting i1dest. */
2462 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2463 || i2dest_in_i2src || i2dest_in_i1src
2465 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2466 || (newi2pat && reg_set_p (i1dest, newi2pat))
2469 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2471 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2472 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2474 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2476 /* Ensure that we do not have something that should not be shared but
2477 occurs multiple times in the new insns. Check this by first
2478 resetting all the `used' flags and then copying anything is shared. */
2480 reset_used_flags (i3notes);
2481 reset_used_flags (i2notes);
2482 reset_used_flags (i1notes);
2483 reset_used_flags (newpat);
2484 reset_used_flags (newi2pat);
2485 if (undobuf.other_insn)
2486 reset_used_flags (PATTERN (undobuf.other_insn));
2488 i3notes = copy_rtx_if_shared (i3notes);
2489 i2notes = copy_rtx_if_shared (i2notes);
2490 i1notes = copy_rtx_if_shared (i1notes);
2491 newpat = copy_rtx_if_shared (newpat);
2492 newi2pat = copy_rtx_if_shared (newi2pat);
2493 if (undobuf.other_insn)
2494 reset_used_flags (PATTERN (undobuf.other_insn));
2496 INSN_CODE (i3) = insn_code_number;
2497 PATTERN (i3) = newpat;
2498 if (undobuf.other_insn)
2499 INSN_CODE (undobuf.other_insn) = other_code_number;
2501 /* We had one special case above where I2 had more than one set and
2502 we replaced a destination of one of those sets with the destination
2503 of I3. In that case, we have to update LOG_LINKS of insns later
2504 in this basic block. Note that this (expensive) case is rare.
2506 Also, in this case, we must pretend that all REG_NOTEs for I2
2507 actually came from I3, so that REG_UNUSED notes from I2 will be
2508 properly handled. */
2510 if (i3_subst_into_i2 && GET_CODE (PATTERN (i2)) == PARALLEL)
2512 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2514 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2515 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2516 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2517 && ! find_reg_note (i2, REG_UNUSED,
2518 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2519 for (temp = NEXT_INSN (i2);
2520 temp && (this_basic_block == n_basic_blocks - 1
2521 || BLOCK_HEAD (this_basic_block) != temp);
2522 temp = NEXT_INSN (temp))
2523 if (temp != i3 && INSN_P (temp))
2524 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2525 if (XEXP (link, 0) == i2)
2526 XEXP (link, 0) = i3;
2532 while (XEXP (link, 1))
2533 link = XEXP (link, 1);
2534 XEXP (link, 1) = i2notes;
2548 INSN_CODE (i2) = i2_code_number;
2549 PATTERN (i2) = newi2pat;
2553 PUT_CODE (i2, NOTE);
2554 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2555 NOTE_SOURCE_FILE (i2) = 0;
2562 PUT_CODE (i1, NOTE);
2563 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2564 NOTE_SOURCE_FILE (i1) = 0;
2567 /* Get death notes for everything that is now used in either I3 or
2568 I2 and used to die in a previous insn. If we built two new
2569 patterns, move from I1 to I2 then I2 to I3 so that we get the
2570 proper movement on registers that I2 modifies. */
2574 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2575 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2578 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2581 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2583 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2586 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2589 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2592 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2595 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2596 know these are REG_UNUSED and want them to go to the desired insn,
2597 so we always pass it as i3. We have not counted the notes in
2598 reg_n_deaths yet, so we need to do so now. */
2600 if (newi2pat && new_i2_notes)
2602 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2603 if (GET_CODE (XEXP (temp, 0)) == REG)
2604 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2606 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2611 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2612 if (GET_CODE (XEXP (temp, 0)) == REG)
2613 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2615 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2618 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2619 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2620 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2621 in that case, it might delete I2. Similarly for I2 and I1.
2622 Show an additional death due to the REG_DEAD note we make here. If
2623 we discard it in distribute_notes, we will decrement it again. */
2627 if (GET_CODE (i3dest_killed) == REG)
2628 REG_N_DEATHS (REGNO (i3dest_killed))++;
2630 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2631 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2633 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2635 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2637 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2641 if (i2dest_in_i2src)
2643 if (GET_CODE (i2dest) == REG)
2644 REG_N_DEATHS (REGNO (i2dest))++;
2646 if (newi2pat && reg_set_p (i2dest, newi2pat))
2647 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2648 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2650 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2651 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2652 NULL_RTX, NULL_RTX);
2655 if (i1dest_in_i1src)
2657 if (GET_CODE (i1dest) == REG)
2658 REG_N_DEATHS (REGNO (i1dest))++;
2660 if (newi2pat && reg_set_p (i1dest, newi2pat))
2661 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2662 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2664 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2665 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2666 NULL_RTX, NULL_RTX);
2669 distribute_links (i3links);
2670 distribute_links (i2links);
2671 distribute_links (i1links);
2673 if (GET_CODE (i2dest) == REG)
2676 rtx i2_insn = 0, i2_val = 0, set;
2678 /* The insn that used to set this register doesn't exist, and
2679 this life of the register may not exist either. See if one of
2680 I3's links points to an insn that sets I2DEST. If it does,
2681 that is now the last known value for I2DEST. If we don't update
2682 this and I2 set the register to a value that depended on its old
2683 contents, we will get confused. If this insn is used, thing
2684 will be set correctly in combine_instructions. */
2686 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2687 if ((set = single_set (XEXP (link, 0))) != 0
2688 && rtx_equal_p (i2dest, SET_DEST (set)))
2689 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2691 record_value_for_reg (i2dest, i2_insn, i2_val);
2693 /* If the reg formerly set in I2 died only once and that was in I3,
2694 zero its use count so it won't make `reload' do any work. */
2696 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2697 && ! i2dest_in_i2src)
2699 regno = REGNO (i2dest);
2700 REG_N_SETS (regno)--;
2704 if (i1 && GET_CODE (i1dest) == REG)
2707 rtx i1_insn = 0, i1_val = 0, set;
2709 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2710 if ((set = single_set (XEXP (link, 0))) != 0
2711 && rtx_equal_p (i1dest, SET_DEST (set)))
2712 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2714 record_value_for_reg (i1dest, i1_insn, i1_val);
2716 regno = REGNO (i1dest);
2717 if (! added_sets_1 && ! i1dest_in_i1src)
2718 REG_N_SETS (regno)--;
2721 /* Update reg_nonzero_bits et al for any changes that may have been made
2722 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2723 important. Because newi2pat can affect nonzero_bits of newpat */
2725 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2726 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2728 /* Set new_direct_jump_p if a new return or simple jump instruction
2731 If I3 is now an unconditional jump, ensure that it has a
2732 BARRIER following it since it may have initially been a
2733 conditional jump. It may also be the last nonnote insn. */
2735 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2737 *new_direct_jump_p = 1;
2739 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2740 || GET_CODE (temp) != BARRIER)
2741 emit_barrier_after (i3);
2745 combine_successes++;
2748 /* Clear this here, so that subsequent get_last_value calls are not
2750 subst_prev_insn = NULL_RTX;
2752 if (added_links_insn
2753 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2754 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2755 return added_links_insn;
2757 return newi2pat ? i2 : i3;
2760 /* Undo all the modifications recorded in undobuf. */
2765 struct undo *undo, *next;
2767 for (undo = undobuf.undos; undo; undo = next)
2771 *undo->where.i = undo->old_contents.i;
2773 *undo->where.r = undo->old_contents.r;
2775 undo->next = undobuf.frees;
2776 undobuf.frees = undo;
2779 obfree (undobuf.storage);
2780 undobuf.undos = undobuf.previous_undos = 0;
2782 /* Clear this here, so that subsequent get_last_value calls are not
2784 subst_prev_insn = NULL_RTX;
2787 /* We've committed to accepting the changes we made. Move all
2788 of the undos to the free list. */
2793 struct undo *undo, *next;
2795 for (undo = undobuf.undos; undo; undo = next)
2798 undo->next = undobuf.frees;
2799 undobuf.frees = undo;
2801 undobuf.undos = undobuf.previous_undos = 0;
2805 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2806 where we have an arithmetic expression and return that point. LOC will
2809 try_combine will call this function to see if an insn can be split into
2813 find_split_point (loc, insn)
2818 enum rtx_code code = GET_CODE (x);
2820 unsigned HOST_WIDE_INT len = 0;
2821 HOST_WIDE_INT pos = 0;
2823 rtx inner = NULL_RTX;
2825 /* First special-case some codes. */
2829 #ifdef INSN_SCHEDULING
2830 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2832 if (GET_CODE (SUBREG_REG (x)) == MEM)
2835 return find_split_point (&SUBREG_REG (x), insn);
2839 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2840 using LO_SUM and HIGH. */
2841 if (GET_CODE (XEXP (x, 0)) == CONST
2842 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2845 gen_rtx_combine (LO_SUM, Pmode,
2846 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2848 return &XEXP (XEXP (x, 0), 0);
2852 /* If we have a PLUS whose second operand is a constant and the
2853 address is not valid, perhaps will can split it up using
2854 the machine-specific way to split large constants. We use
2855 the first pseudo-reg (one of the virtual regs) as a placeholder;
2856 it will not remain in the result. */
2857 if (GET_CODE (XEXP (x, 0)) == PLUS
2858 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2859 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2861 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2862 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2865 /* This should have produced two insns, each of which sets our
2866 placeholder. If the source of the second is a valid address,
2867 we can make put both sources together and make a split point
2870 if (seq && XVECLEN (seq, 0) == 2
2871 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2872 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2873 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2874 && ! reg_mentioned_p (reg,
2875 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2876 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2877 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2878 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2879 && memory_address_p (GET_MODE (x),
2880 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2882 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2883 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2885 /* Replace the placeholder in SRC2 with SRC1. If we can
2886 find where in SRC2 it was placed, that can become our
2887 split point and we can replace this address with SRC2.
2888 Just try two obvious places. */
2890 src2 = replace_rtx (src2, reg, src1);
2892 if (XEXP (src2, 0) == src1)
2893 split = &XEXP (src2, 0);
2894 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2895 && XEXP (XEXP (src2, 0), 0) == src1)
2896 split = &XEXP (XEXP (src2, 0), 0);
2900 SUBST (XEXP (x, 0), src2);
2905 /* If that didn't work, perhaps the first operand is complex and
2906 needs to be computed separately, so make a split point there.
2907 This will occur on machines that just support REG + CONST
2908 and have a constant moved through some previous computation. */
2910 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2911 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2912 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2914 return &XEXP (XEXP (x, 0), 0);
2920 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2921 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2922 we need to put the operand into a register. So split at that
2925 if (SET_DEST (x) == cc0_rtx
2926 && GET_CODE (SET_SRC (x)) != COMPARE
2927 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2928 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2929 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2930 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2931 return &SET_SRC (x);
2934 /* See if we can split SET_SRC as it stands. */
2935 split = find_split_point (&SET_SRC (x), insn);
2936 if (split && split != &SET_SRC (x))
2939 /* See if we can split SET_DEST as it stands. */
2940 split = find_split_point (&SET_DEST (x), insn);
2941 if (split && split != &SET_DEST (x))
2944 /* See if this is a bitfield assignment with everything constant. If
2945 so, this is an IOR of an AND, so split it into that. */
2946 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2947 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2948 <= HOST_BITS_PER_WIDE_INT)
2949 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2950 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2951 && GET_CODE (SET_SRC (x)) == CONST_INT
2952 && ((INTVAL (XEXP (SET_DEST (x), 1))
2953 + INTVAL (XEXP (SET_DEST (x), 2)))
2954 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2955 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2957 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2958 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2959 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2960 rtx dest = XEXP (SET_DEST (x), 0);
2961 enum machine_mode mode = GET_MODE (dest);
2962 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2964 if (BITS_BIG_ENDIAN)
2965 pos = GET_MODE_BITSIZE (mode) - len - pos;
2969 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2972 gen_binary (IOR, mode,
2973 gen_binary (AND, mode, dest,
2974 GEN_INT (~(mask << pos)
2975 & GET_MODE_MASK (mode))),
2976 GEN_INT (src << pos)));
2978 SUBST (SET_DEST (x), dest);
2980 split = find_split_point (&SET_SRC (x), insn);
2981 if (split && split != &SET_SRC (x))
2985 /* Otherwise, see if this is an operation that we can split into two.
2986 If so, try to split that. */
2987 code = GET_CODE (SET_SRC (x));
2992 /* If we are AND'ing with a large constant that is only a single
2993 bit and the result is only being used in a context where we
2994 need to know if it is zero or non-zero, replace it with a bit
2995 extraction. This will avoid the large constant, which might
2996 have taken more than one insn to make. If the constant were
2997 not a valid argument to the AND but took only one insn to make,
2998 this is no worse, but if it took more than one insn, it will
3001 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3002 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3003 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3004 && GET_CODE (SET_DEST (x)) == REG
3005 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3006 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3007 && XEXP (*split, 0) == SET_DEST (x)
3008 && XEXP (*split, 1) == const0_rtx)
3010 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3011 XEXP (SET_SRC (x), 0),
3012 pos, NULL_RTX, 1, 1, 0, 0);
3013 if (extraction != 0)
3015 SUBST (SET_SRC (x), extraction);
3016 return find_split_point (loc, insn);
3022 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3023 is known to be on, this can be converted into a NEG of a shift. */
3024 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3025 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3026 && 1 <= (pos = exact_log2
3027 (nonzero_bits (XEXP (SET_SRC (x), 0),
3028 GET_MODE (XEXP (SET_SRC (x), 0))))))
3030 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3033 gen_rtx_combine (NEG, mode,
3034 gen_rtx_combine (LSHIFTRT, mode,
3035 XEXP (SET_SRC (x), 0),
3038 split = find_split_point (&SET_SRC (x), insn);
3039 if (split && split != &SET_SRC (x))
3045 inner = XEXP (SET_SRC (x), 0);
3047 /* We can't optimize if either mode is a partial integer
3048 mode as we don't know how many bits are significant
3050 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3051 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3055 len = GET_MODE_BITSIZE (GET_MODE (inner));
3061 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3062 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3064 inner = XEXP (SET_SRC (x), 0);
3065 len = INTVAL (XEXP (SET_SRC (x), 1));
3066 pos = INTVAL (XEXP (SET_SRC (x), 2));
3068 if (BITS_BIG_ENDIAN)
3069 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3070 unsignedp = (code == ZERO_EXTRACT);
3078 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3080 enum machine_mode mode = GET_MODE (SET_SRC (x));
3082 /* For unsigned, we have a choice of a shift followed by an
3083 AND or two shifts. Use two shifts for field sizes where the
3084 constant might be too large. We assume here that we can
3085 always at least get 8-bit constants in an AND insn, which is
3086 true for every current RISC. */
3088 if (unsignedp && len <= 8)
3093 gen_rtx_combine (LSHIFTRT, mode,
3094 gen_lowpart_for_combine (mode, inner),
3096 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3098 split = find_split_point (&SET_SRC (x), insn);
3099 if (split && split != &SET_SRC (x))
3106 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3107 gen_rtx_combine (ASHIFT, mode,
3108 gen_lowpart_for_combine (mode, inner),
3109 GEN_INT (GET_MODE_BITSIZE (mode)
3111 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3113 split = find_split_point (&SET_SRC (x), insn);
3114 if (split && split != &SET_SRC (x))
3119 /* See if this is a simple operation with a constant as the second
3120 operand. It might be that this constant is out of range and hence
3121 could be used as a split point. */
3122 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3123 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3124 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3125 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3126 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3127 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3128 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3130 return &XEXP (SET_SRC (x), 1);
3132 /* Finally, see if this is a simple operation with its first operand
3133 not in a register. The operation might require this operand in a
3134 register, so return it as a split point. We can always do this
3135 because if the first operand were another operation, we would have
3136 already found it as a split point. */
3137 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3138 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3139 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3140 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3141 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3142 return &XEXP (SET_SRC (x), 0);
3148 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3149 it is better to write this as (not (ior A B)) so we can split it.
3150 Similarly for IOR. */
3151 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3154 gen_rtx_combine (NOT, GET_MODE (x),
3155 gen_rtx_combine (code == IOR ? AND : IOR,
3157 XEXP (XEXP (x, 0), 0),
3158 XEXP (XEXP (x, 1), 0))));
3159 return find_split_point (loc, insn);
3162 /* Many RISC machines have a large set of logical insns. If the
3163 second operand is a NOT, put it first so we will try to split the
3164 other operand first. */
3165 if (GET_CODE (XEXP (x, 1)) == NOT)
3167 rtx tem = XEXP (x, 0);
3168 SUBST (XEXP (x, 0), XEXP (x, 1));
3169 SUBST (XEXP (x, 1), tem);
3177 /* Otherwise, select our actions depending on our rtx class. */
3178 switch (GET_RTX_CLASS (code))
3180 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3182 split = find_split_point (&XEXP (x, 2), insn);
3185 /* ... fall through ... */
3189 split = find_split_point (&XEXP (x, 1), insn);
3192 /* ... fall through ... */
3194 /* Some machines have (and (shift ...) ...) insns. If X is not
3195 an AND, but XEXP (X, 0) is, use it as our split point. */
3196 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3197 return &XEXP (x, 0);
3199 split = find_split_point (&XEXP (x, 0), insn);
3205 /* Otherwise, we don't have a split point. */
3209 /* Throughout X, replace FROM with TO, and return the result.
3210 The result is TO if X is FROM;
3211 otherwise the result is X, but its contents may have been modified.
3212 If they were modified, a record was made in undobuf so that
3213 undo_all will (among other things) return X to its original state.
3215 If the number of changes necessary is too much to record to undo,
3216 the excess changes are not made, so the result is invalid.
3217 The changes already made can still be undone.
3218 undobuf.num_undo is incremented for such changes, so by testing that
3219 the caller can tell whether the result is valid.
3221 `n_occurrences' is incremented each time FROM is replaced.
3223 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3225 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3226 by copying if `n_occurrences' is non-zero. */
3229 subst (x, from, to, in_dest, unique_copy)
3230 register rtx x, from, to;
3234 register enum rtx_code code = GET_CODE (x);
3235 enum machine_mode op0_mode = VOIDmode;
3236 register const char *fmt;
3237 register int len, i;
3240 /* Two expressions are equal if they are identical copies of a shared
3241 RTX or if they are both registers with the same register number
3244 #define COMBINE_RTX_EQUAL_P(X,Y) \
3246 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3247 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3249 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3252 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3255 /* If X and FROM are the same register but different modes, they will
3256 not have been seen as equal above. However, flow.c will make a
3257 LOG_LINKS entry for that case. If we do nothing, we will try to
3258 rerecognize our original insn and, when it succeeds, we will
3259 delete the feeding insn, which is incorrect.
3261 So force this insn not to match in this (rare) case. */
3262 if (! in_dest && code == REG && GET_CODE (from) == REG
3263 && REGNO (x) == REGNO (from))
3264 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3266 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3267 of which may contain things that can be combined. */
3268 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3271 /* It is possible to have a subexpression appear twice in the insn.
3272 Suppose that FROM is a register that appears within TO.
3273 Then, after that subexpression has been scanned once by `subst',
3274 the second time it is scanned, TO may be found. If we were
3275 to scan TO here, we would find FROM within it and create a
3276 self-referent rtl structure which is completely wrong. */
3277 if (COMBINE_RTX_EQUAL_P (x, to))
3280 /* Parallel asm_operands need special attention because all of the
3281 inputs are shared across the arms. Furthermore, unsharing the
3282 rtl results in recognition failures. Failure to handle this case
3283 specially can result in circular rtl.
3285 Solve this by doing a normal pass across the first entry of the
3286 parallel, and only processing the SET_DESTs of the subsequent
3289 if (code == PARALLEL
3290 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3291 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3293 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3295 /* If this substitution failed, this whole thing fails. */
3296 if (GET_CODE (new) == CLOBBER
3297 && XEXP (new, 0) == const0_rtx)
3300 SUBST (XVECEXP (x, 0, 0), new);
3302 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3304 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3306 if (GET_CODE (dest) != REG
3307 && GET_CODE (dest) != CC0
3308 && GET_CODE (dest) != PC)
3310 new = subst (dest, from, to, 0, unique_copy);
3312 /* If this substitution failed, this whole thing fails. */
3313 if (GET_CODE (new) == CLOBBER
3314 && XEXP (new, 0) == const0_rtx)
3317 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3323 len = GET_RTX_LENGTH (code);
3324 fmt = GET_RTX_FORMAT (code);
3326 /* We don't need to process a SET_DEST that is a register, CC0,
3327 or PC, so set up to skip this common case. All other cases
3328 where we want to suppress replacing something inside a
3329 SET_SRC are handled via the IN_DEST operand. */
3331 && (GET_CODE (SET_DEST (x)) == REG
3332 || GET_CODE (SET_DEST (x)) == CC0
3333 || GET_CODE (SET_DEST (x)) == PC))
3336 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3339 op0_mode = GET_MODE (XEXP (x, 0));
3341 for (i = 0; i < len; i++)
3346 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3348 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3350 new = (unique_copy && n_occurrences
3351 ? copy_rtx (to) : to);
3356 new = subst (XVECEXP (x, i, j), from, to, 0,
3359 /* If this substitution failed, this whole thing
3361 if (GET_CODE (new) == CLOBBER
3362 && XEXP (new, 0) == const0_rtx)
3366 SUBST (XVECEXP (x, i, j), new);
3369 else if (fmt[i] == 'e')
3371 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3373 /* In general, don't install a subreg involving two
3374 modes not tieable. It can worsen register
3375 allocation, and can even make invalid reload
3376 insns, since the reg inside may need to be copied
3377 from in the outside mode, and that may be invalid
3378 if it is an fp reg copied in integer mode.
3380 We allow two exceptions to this: It is valid if
3381 it is inside another SUBREG and the mode of that
3382 SUBREG and the mode of the inside of TO is
3383 tieable and it is valid if X is a SET that copies
3386 if (GET_CODE (to) == SUBREG
3387 && ! MODES_TIEABLE_P (GET_MODE (to),
3388 GET_MODE (SUBREG_REG (to)))
3389 && ! (code == SUBREG
3390 && MODES_TIEABLE_P (GET_MODE (x),
3391 GET_MODE (SUBREG_REG (to))))
3393 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3396 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3398 #ifdef CLASS_CANNOT_CHANGE_MODE
3400 && GET_CODE (to) == REG
3401 && REGNO (to) < FIRST_PSEUDO_REGISTER
3402 && (TEST_HARD_REG_BIT
3403 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3405 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3407 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3410 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3414 /* If we are in a SET_DEST, suppress most cases unless we
3415 have gone inside a MEM, in which case we want to
3416 simplify the address. We assume here that things that
3417 are actually part of the destination have their inner
3418 parts in the first expression. This is true for SUBREG,
3419 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3420 things aside from REG and MEM that should appear in a
3422 new = subst (XEXP (x, i), from, to,
3424 && (code == SUBREG || code == STRICT_LOW_PART
3425 || code == ZERO_EXTRACT))
3427 && i == 0), unique_copy);
3429 /* If we found that we will have to reject this combination,
3430 indicate that by returning the CLOBBER ourselves, rather than
3431 an expression containing it. This will speed things up as
3432 well as prevent accidents where two CLOBBERs are considered
3433 to be equal, thus producing an incorrect simplification. */
3435 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3438 SUBST (XEXP (x, i), new);
3443 /* Try to simplify X. If the simplification changed the code, it is likely
3444 that further simplification will help, so loop, but limit the number
3445 of repetitions that will be performed. */
3447 for (i = 0; i < 4; i++)
3449 /* If X is sufficiently simple, don't bother trying to do anything
3451 if (code != CONST_INT && code != REG && code != CLOBBER)
3452 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3454 if (GET_CODE (x) == code)
3457 code = GET_CODE (x);
3459 /* We no longer know the original mode of operand 0 since we
3460 have changed the form of X) */
3461 op0_mode = VOIDmode;
3467 /* Simplify X, a piece of RTL. We just operate on the expression at the
3468 outer level; call `subst' to simplify recursively. Return the new
3471 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3472 will be the iteration even if an expression with a code different from
3473 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3476 combine_simplify_rtx (x, op0_mode, last, in_dest)
3478 enum machine_mode op0_mode;
3482 enum rtx_code code = GET_CODE (x);
3483 enum machine_mode mode = GET_MODE (x);
3487 /* If this is a commutative operation, put a constant last and a complex
3488 expression first. We don't need to do this for comparisons here. */
3489 if (GET_RTX_CLASS (code) == 'c'
3490 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3491 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3492 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3493 || (GET_CODE (XEXP (x, 0)) == SUBREG
3494 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3495 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3498 SUBST (XEXP (x, 0), XEXP (x, 1));
3499 SUBST (XEXP (x, 1), temp);
3502 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3503 sign extension of a PLUS with a constant, reverse the order of the sign
3504 extension and the addition. Note that this not the same as the original
3505 code, but overflow is undefined for signed values. Also note that the
3506 PLUS will have been partially moved "inside" the sign-extension, so that
3507 the first operand of X will really look like:
3508 (ashiftrt (plus (ashift A C4) C5) C4).
3510 (plus (ashiftrt (ashift A C4) C2) C4)
3511 and replace the first operand of X with that expression. Later parts
3512 of this function may simplify the expression further.
3514 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3515 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3516 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3518 We do this to simplify address expressions. */
3520 if ((code == PLUS || code == MINUS || code == MULT)
3521 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3522 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3523 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3524 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3525 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3526 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3527 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3528 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3529 XEXP (XEXP (XEXP (x, 0), 0), 1),
3530 XEXP (XEXP (x, 0), 1))) != 0)
3533 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3534 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3535 INTVAL (XEXP (XEXP (x, 0), 1)));
3537 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3538 INTVAL (XEXP (XEXP (x, 0), 1)));
3540 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3543 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3544 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3545 things. Check for cases where both arms are testing the same
3548 Don't do anything if all operands are very simple. */
3550 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3551 || GET_RTX_CLASS (code) == '<')
3552 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3553 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3554 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3556 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3557 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3558 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3560 || (GET_RTX_CLASS (code) == '1'
3561 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3562 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3563 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3566 rtx cond, true, false;
3568 cond = if_then_else_cond (x, &true, &false);
3570 /* If everything is a comparison, what we have is highly unlikely
3571 to be simpler, so don't use it. */
3572 && ! (GET_RTX_CLASS (code) == '<'
3573 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3574 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3576 rtx cop1 = const0_rtx;
3577 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3579 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3582 /* Simplify the alternative arms; this may collapse the true and
3583 false arms to store-flag values. */
3584 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3585 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3587 /* If true and false are not general_operands, an if_then_else
3588 is unlikely to be simpler. */
3589 if (general_operand (true, VOIDmode)
3590 && general_operand (false, VOIDmode))
3592 /* Restarting if we generate a store-flag expression will cause
3593 us to loop. Just drop through in this case. */
3595 /* If the result values are STORE_FLAG_VALUE and zero, we can
3596 just make the comparison operation. */
3597 if (true == const_true_rtx && false == const0_rtx)
3598 x = gen_binary (cond_code, mode, cond, cop1);
3599 else if (true == const0_rtx && false == const_true_rtx)
3600 x = gen_binary (reverse_condition (cond_code),
3603 /* Likewise, we can make the negate of a comparison operation
3604 if the result values are - STORE_FLAG_VALUE and zero. */
3605 else if (GET_CODE (true) == CONST_INT
3606 && INTVAL (true) == - STORE_FLAG_VALUE
3607 && false == const0_rtx)
3608 x = gen_unary (NEG, mode, mode,
3609 gen_binary (cond_code, mode, cond, cop1));
3610 else if (GET_CODE (false) == CONST_INT
3611 && INTVAL (false) == - STORE_FLAG_VALUE
3612 && true == const0_rtx)
3613 x = gen_unary (NEG, mode, mode,
3614 gen_binary (reverse_condition (cond_code),
3617 return gen_rtx_IF_THEN_ELSE (mode,
3618 gen_binary (cond_code, VOIDmode,
3622 code = GET_CODE (x);
3623 op0_mode = VOIDmode;
3628 /* Try to fold this expression in case we have constants that weren't
3631 switch (GET_RTX_CLASS (code))
3634 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3638 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3639 if (cmp_mode == VOIDmode)
3640 cmp_mode = GET_MODE (XEXP (x, 1));
3641 temp = simplify_relational_operation (code, cmp_mode,
3642 XEXP (x, 0), XEXP (x, 1));
3644 #ifdef FLOAT_STORE_FLAG_VALUE
3645 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3647 if (temp == const0_rtx)
3648 temp = CONST0_RTX (mode);
3650 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3656 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3660 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3661 XEXP (x, 1), XEXP (x, 2));
3666 x = temp, code = GET_CODE (temp);
3668 /* First see if we can apply the inverse distributive law. */
3669 if (code == PLUS || code == MINUS
3670 || code == AND || code == IOR || code == XOR)
3672 x = apply_distributive_law (x);
3673 code = GET_CODE (x);
3676 /* If CODE is an associative operation not otherwise handled, see if we
3677 can associate some operands. This can win if they are constants or
3678 if they are logically related (i.e. (a & b) & a. */
3679 if ((code == PLUS || code == MINUS
3680 || code == MULT || code == AND || code == IOR || code == XOR
3681 || code == DIV || code == UDIV
3682 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3683 && INTEGRAL_MODE_P (mode))
3685 if (GET_CODE (XEXP (x, 0)) == code)
3687 rtx other = XEXP (XEXP (x, 0), 0);
3688 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3689 rtx inner_op1 = XEXP (x, 1);
3692 /* Make sure we pass the constant operand if any as the second
3693 one if this is a commutative operation. */
3694 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3696 rtx tem = inner_op0;
3697 inner_op0 = inner_op1;
3700 inner = simplify_binary_operation (code == MINUS ? PLUS
3701 : code == DIV ? MULT
3702 : code == UDIV ? MULT
3704 mode, inner_op0, inner_op1);
3706 /* For commutative operations, try the other pair if that one
3708 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3710 other = XEXP (XEXP (x, 0), 1);
3711 inner = simplify_binary_operation (code, mode,
3712 XEXP (XEXP (x, 0), 0),
3717 return gen_binary (code, mode, other, inner);
3721 /* A little bit of algebraic simplification here. */
3725 /* Ensure that our address has any ASHIFTs converted to MULT in case
3726 address-recognizing predicates are called later. */
3727 temp = make_compound_operation (XEXP (x, 0), MEM);
3728 SUBST (XEXP (x, 0), temp);
3732 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3733 is paradoxical. If we can't do that safely, then it becomes
3734 something nonsensical so that this combination won't take place. */
3736 if (GET_CODE (SUBREG_REG (x)) == MEM
3737 && (GET_MODE_SIZE (mode)
3738 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3740 rtx inner = SUBREG_REG (x);
3741 int endian_offset = 0;
3742 /* Don't change the mode of the MEM
3743 if that would change the meaning of the address. */
3744 if (MEM_VOLATILE_P (SUBREG_REG (x))
3745 || mode_dependent_address_p (XEXP (inner, 0)))
3746 return gen_rtx_CLOBBER (mode, const0_rtx);
3748 if (BYTES_BIG_ENDIAN)
3750 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3751 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3752 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3753 endian_offset -= (UNITS_PER_WORD
3754 - GET_MODE_SIZE (GET_MODE (inner)));
3756 /* Note if the plus_constant doesn't make a valid address
3757 then this combination won't be accepted. */
3758 x = gen_rtx_MEM (mode,
3759 plus_constant (XEXP (inner, 0),
3760 (SUBREG_WORD (x) * UNITS_PER_WORD
3762 MEM_COPY_ATTRIBUTES (x, inner);
3766 /* If we are in a SET_DEST, these other cases can't apply. */
3770 /* Changing mode twice with SUBREG => just change it once,
3771 or not at all if changing back to starting mode. */
3772 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3774 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3775 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3776 return SUBREG_REG (SUBREG_REG (x));
3778 SUBST_INT (SUBREG_WORD (x),
3779 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3780 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3783 /* SUBREG of a hard register => just change the register number
3784 and/or mode. If the hard register is not valid in that mode,
3785 suppress this combination. If the hard register is the stack,
3786 frame, or argument pointer, leave this as a SUBREG. */
3788 if (GET_CODE (SUBREG_REG (x)) == REG
3789 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3790 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3791 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3792 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3794 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3795 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3797 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3799 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3801 return gen_rtx_REG (mode,
3802 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3804 return gen_rtx_CLOBBER (mode, const0_rtx);
3807 /* For a constant, try to pick up the part we want. Handle a full
3808 word and low-order part. Only do this if we are narrowing
3809 the constant; if it is being widened, we have no idea what
3810 the extra bits will have been set to. */
3812 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3813 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3814 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3815 && GET_MODE_CLASS (mode) == MODE_INT)
3817 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3823 /* If we want a subreg of a constant, at offset 0,
3824 take the low bits. On a little-endian machine, that's
3825 always valid. On a big-endian machine, it's valid
3826 only if the constant's mode fits in one word. Note that we
3827 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3828 if (CONSTANT_P (SUBREG_REG (x))
3829 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3830 || ! WORDS_BIG_ENDIAN)
3831 ? SUBREG_WORD (x) == 0
3833 == ((GET_MODE_SIZE (op0_mode)
3834 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3836 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3837 && (! WORDS_BIG_ENDIAN
3838 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3839 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3841 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3842 since we are saying that the high bits don't matter. */
3843 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3844 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3846 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3847 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3848 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3849 return SUBREG_REG (x);
3852 /* Note that we cannot do any narrowing for non-constants since
3853 we might have been counting on using the fact that some bits were
3854 zero. We now do this in the SET. */
3859 /* (not (plus X -1)) can become (neg X). */
3860 if (GET_CODE (XEXP (x, 0)) == PLUS
3861 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3862 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3864 /* Similarly, (not (neg X)) is (plus X -1). */
3865 if (GET_CODE (XEXP (x, 0)) == NEG)
3866 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3869 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3870 if (GET_CODE (XEXP (x, 0)) == XOR
3871 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3872 && (temp = simplify_unary_operation (NOT, mode,
3873 XEXP (XEXP (x, 0), 1),
3875 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3877 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3878 other than 1, but that is not valid. We could do a similar
3879 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3880 but this doesn't seem common enough to bother with. */
3881 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3882 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3883 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3884 XEXP (XEXP (x, 0), 1));
3886 if (GET_CODE (XEXP (x, 0)) == SUBREG
3887 && subreg_lowpart_p (XEXP (x, 0))
3888 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3889 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3890 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3891 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3893 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3895 x = gen_rtx_ROTATE (inner_mode,
3896 gen_unary (NOT, inner_mode, inner_mode,
3898 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3899 return gen_lowpart_for_combine (mode, x);
3902 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3903 reversing the comparison code if valid. */
3904 if (STORE_FLAG_VALUE == -1
3905 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3906 && reversible_comparison_p (XEXP (x, 0)))
3907 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3908 mode, XEXP (XEXP (x, 0), 0),
3909 XEXP (XEXP (x, 0), 1));
3911 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3912 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3913 perform the above simplification. */
3915 if (STORE_FLAG_VALUE == -1
3916 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3917 && XEXP (x, 1) == const1_rtx
3918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3919 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3920 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3922 /* Apply De Morgan's laws to reduce number of patterns for machines
3923 with negating logical insns (and-not, nand, etc.). If result has
3924 only one NOT, put it first, since that is how the patterns are
3927 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3929 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3931 if (GET_CODE (in1) == NOT)
3932 in1 = XEXP (in1, 0);
3934 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3936 if (GET_CODE (in2) == NOT)
3937 in2 = XEXP (in2, 0);
3938 else if (GET_CODE (in2) == CONST_INT
3939 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3940 in2 = GEN_INT (GET_MODE_MASK (mode) & ~INTVAL (in2));
3942 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3944 if (GET_CODE (in2) == NOT)
3947 in2 = in1; in1 = tem;
3950 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3956 /* (neg (plus X 1)) can become (not X). */
3957 if (GET_CODE (XEXP (x, 0)) == PLUS
3958 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3959 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3961 /* Similarly, (neg (not X)) is (plus X 1). */
3962 if (GET_CODE (XEXP (x, 0)) == NOT)
3963 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3965 /* (neg (minus X Y)) can become (minus Y X). */
3966 if (GET_CODE (XEXP (x, 0)) == MINUS
3967 && (! FLOAT_MODE_P (mode)
3968 /* x-y != -(y-x) with IEEE floating point. */
3969 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3971 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3972 XEXP (XEXP (x, 0), 0));
3974 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3975 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3976 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3977 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3979 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3980 if we can then eliminate the NEG (e.g.,
3981 if the operand is a constant). */
3983 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3985 temp = simplify_unary_operation (NEG, mode,
3986 XEXP (XEXP (x, 0), 0), mode);
3989 SUBST (XEXP (XEXP (x, 0), 0), temp);
3994 temp = expand_compound_operation (XEXP (x, 0));
3996 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3997 replaced by (lshiftrt X C). This will convert
3998 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4000 if (GET_CODE (temp) == ASHIFTRT
4001 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4002 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4003 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4004 INTVAL (XEXP (temp, 1)));
4006 /* If X has only a single bit that might be nonzero, say, bit I, convert
4007 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4008 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4009 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4010 or a SUBREG of one since we'd be making the expression more
4011 complex if it was just a register. */
4013 if (GET_CODE (temp) != REG
4014 && ! (GET_CODE (temp) == SUBREG
4015 && GET_CODE (SUBREG_REG (temp)) == REG)
4016 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4018 rtx temp1 = simplify_shift_const
4019 (NULL_RTX, ASHIFTRT, mode,
4020 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4021 GET_MODE_BITSIZE (mode) - 1 - i),
4022 GET_MODE_BITSIZE (mode) - 1 - i);
4024 /* If all we did was surround TEMP with the two shifts, we
4025 haven't improved anything, so don't use it. Otherwise,
4026 we are better off with TEMP1. */
4027 if (GET_CODE (temp1) != ASHIFTRT
4028 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4029 || XEXP (XEXP (temp1, 0), 0) != temp)
4035 /* We can't handle truncation to a partial integer mode here
4036 because we don't know the real bitsize of the partial
4038 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4041 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4042 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4043 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4045 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4046 GET_MODE_MASK (mode), NULL_RTX, 0));
4048 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4049 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4050 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4051 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4052 return XEXP (XEXP (x, 0), 0);
4054 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4055 (OP:SI foo:SI) if OP is NEG or ABS. */
4056 if ((GET_CODE (XEXP (x, 0)) == ABS
4057 || GET_CODE (XEXP (x, 0)) == NEG)
4058 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4059 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4060 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4061 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4062 XEXP (XEXP (XEXP (x, 0), 0), 0));
4064 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4066 if (GET_CODE (XEXP (x, 0)) == SUBREG
4067 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4068 && subreg_lowpart_p (XEXP (x, 0)))
4069 return SUBREG_REG (XEXP (x, 0));
4071 /* If we know that the value is already truncated, we can
4072 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4073 is nonzero for the corresponding modes. But don't do this
4074 for an (LSHIFTRT (MULT ...)) since this will cause problems
4075 with the umulXi3_highpart patterns. */
4076 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4077 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4078 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4079 >= GET_MODE_BITSIZE (mode) + 1
4080 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4081 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4082 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4084 /* A truncate of a comparison can be replaced with a subreg if
4085 STORE_FLAG_VALUE permits. This is like the previous test,
4086 but it works even if the comparison is done in a mode larger
4087 than HOST_BITS_PER_WIDE_INT. */
4088 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4089 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4090 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4091 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4093 /* Similarly, a truncate of a register whose value is a
4094 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4096 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4097 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4098 && (temp = get_last_value (XEXP (x, 0)))
4099 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4100 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4104 case FLOAT_TRUNCATE:
4105 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4106 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4107 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4108 return XEXP (XEXP (x, 0), 0);
4110 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4111 (OP:SF foo:SF) if OP is NEG or ABS. */
4112 if ((GET_CODE (XEXP (x, 0)) == ABS
4113 || GET_CODE (XEXP (x, 0)) == NEG)
4114 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4115 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4116 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4117 XEXP (XEXP (XEXP (x, 0), 0), 0));
4119 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4120 is (float_truncate:SF x). */
4121 if (GET_CODE (XEXP (x, 0)) == SUBREG
4122 && subreg_lowpart_p (XEXP (x, 0))
4123 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4124 return SUBREG_REG (XEXP (x, 0));
4129 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4130 using cc0, in which case we want to leave it as a COMPARE
4131 so we can distinguish it from a register-register-copy. */
4132 if (XEXP (x, 1) == const0_rtx)
4135 /* In IEEE floating point, x-0 is not the same as x. */
4136 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4137 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4139 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4145 /* (const (const X)) can become (const X). Do it this way rather than
4146 returning the inner CONST since CONST can be shared with a
4148 if (GET_CODE (XEXP (x, 0)) == CONST)
4149 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4154 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4155 can add in an offset. find_split_point will split this address up
4156 again if it doesn't match. */
4157 if (GET_CODE (XEXP (x, 0)) == HIGH
4158 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4164 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4165 outermost. That's because that's the way indexed addresses are
4166 supposed to appear. This code used to check many more cases, but
4167 they are now checked elsewhere. */
4168 if (GET_CODE (XEXP (x, 0)) == PLUS
4169 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4170 return gen_binary (PLUS, mode,
4171 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4173 XEXP (XEXP (x, 0), 1));
4175 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4176 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4177 bit-field and can be replaced by either a sign_extend or a
4178 sign_extract. The `and' may be a zero_extend and the two
4179 <c>, -<c> constants may be reversed. */
4180 if (GET_CODE (XEXP (x, 0)) == XOR
4181 && GET_CODE (XEXP (x, 1)) == CONST_INT
4182 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4183 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4184 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4185 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4186 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4187 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4188 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4189 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4190 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4191 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4192 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4193 == (unsigned int) i + 1))))
4194 return simplify_shift_const
4195 (NULL_RTX, ASHIFTRT, mode,
4196 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4197 XEXP (XEXP (XEXP (x, 0), 0), 0),
4198 GET_MODE_BITSIZE (mode) - (i + 1)),
4199 GET_MODE_BITSIZE (mode) - (i + 1));
4201 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4202 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4203 is 1. This produces better code than the alternative immediately
4205 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4206 && reversible_comparison_p (XEXP (x, 0))
4207 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4208 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
4210 gen_unary (NEG, mode, mode,
4211 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
4212 mode, XEXP (XEXP (x, 0), 0),
4213 XEXP (XEXP (x, 0), 1)));
4215 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4216 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4217 the bitsize of the mode - 1. This allows simplification of
4218 "a = (b & 8) == 0;" */
4219 if (XEXP (x, 1) == constm1_rtx
4220 && GET_CODE (XEXP (x, 0)) != REG
4221 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4222 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4223 && nonzero_bits (XEXP (x, 0), mode) == 1)
4224 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4225 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4226 gen_rtx_combine (XOR, mode,
4227 XEXP (x, 0), const1_rtx),
4228 GET_MODE_BITSIZE (mode) - 1),
4229 GET_MODE_BITSIZE (mode) - 1);
4231 /* If we are adding two things that have no bits in common, convert
4232 the addition into an IOR. This will often be further simplified,
4233 for example in cases like ((a & 1) + (a & 2)), which can
4236 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4237 && (nonzero_bits (XEXP (x, 0), mode)
4238 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4240 /* Try to simplify the expression further. */
4241 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4242 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4244 /* If we could, great. If not, do not go ahead with the IOR
4245 replacement, since PLUS appears in many special purpose
4246 address arithmetic instructions. */
4247 if (GET_CODE (temp) != CLOBBER && temp != tor)
4253 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4254 by reversing the comparison code if valid. */
4255 if (STORE_FLAG_VALUE == 1
4256 && XEXP (x, 0) == const1_rtx
4257 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4258 && reversible_comparison_p (XEXP (x, 1)))
4259 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))), mode,
4260 XEXP (XEXP (x, 1), 0),
4261 XEXP (XEXP (x, 1), 1));
4263 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4264 (and <foo> (const_int pow2-1)) */
4265 if (GET_CODE (XEXP (x, 1)) == AND
4266 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4267 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4268 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4269 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4270 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4272 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4274 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4275 return gen_binary (MINUS, mode,
4276 gen_binary (MINUS, mode, XEXP (x, 0),
4277 XEXP (XEXP (x, 1), 0)),
4278 XEXP (XEXP (x, 1), 1));
4282 /* If we have (mult (plus A B) C), apply the distributive law and then
4283 the inverse distributive law to see if things simplify. This
4284 occurs mostly in addresses, often when unrolling loops. */
4286 if (GET_CODE (XEXP (x, 0)) == PLUS)
4288 x = apply_distributive_law
4289 (gen_binary (PLUS, mode,
4290 gen_binary (MULT, mode,
4291 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4292 gen_binary (MULT, mode,
4293 XEXP (XEXP (x, 0), 1),
4294 copy_rtx (XEXP (x, 1)))));
4296 if (GET_CODE (x) != MULT)
4302 /* If this is a divide by a power of two, treat it as a shift if
4303 its first operand is a shift. */
4304 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4305 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4306 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4307 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4308 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4309 || GET_CODE (XEXP (x, 0)) == ROTATE
4310 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4311 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4315 case GT: case GTU: case GE: case GEU:
4316 case LT: case LTU: case LE: case LEU:
4317 /* If the first operand is a condition code, we can't do anything
4319 if (GET_CODE (XEXP (x, 0)) == COMPARE
4320 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4322 && XEXP (x, 0) != cc0_rtx
4326 rtx op0 = XEXP (x, 0);
4327 rtx op1 = XEXP (x, 1);
4328 enum rtx_code new_code;
4330 if (GET_CODE (op0) == COMPARE)
4331 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4333 /* Simplify our comparison, if possible. */
4334 new_code = simplify_comparison (code, &op0, &op1);
4336 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4337 if only the low-order bit is possibly nonzero in X (such as when
4338 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4339 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4340 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4343 Remove any ZERO_EXTRACT we made when thinking this was a
4344 comparison. It may now be simpler to use, e.g., an AND. If a
4345 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4346 the call to make_compound_operation in the SET case. */
4348 if (STORE_FLAG_VALUE == 1
4349 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4350 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4351 return gen_lowpart_for_combine (mode,
4352 expand_compound_operation (op0));
4354 else if (STORE_FLAG_VALUE == 1
4355 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4356 && op1 == const0_rtx
4357 && (num_sign_bit_copies (op0, mode)
4358 == GET_MODE_BITSIZE (mode)))
4360 op0 = expand_compound_operation (op0);
4361 return gen_unary (NEG, mode, mode,
4362 gen_lowpart_for_combine (mode, op0));
4365 else if (STORE_FLAG_VALUE == 1
4366 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4367 && op1 == const0_rtx
4368 && nonzero_bits (op0, mode) == 1)
4370 op0 = expand_compound_operation (op0);
4371 return gen_binary (XOR, mode,
4372 gen_lowpart_for_combine (mode, op0),
4376 else if (STORE_FLAG_VALUE == 1
4377 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4378 && op1 == const0_rtx
4379 && (num_sign_bit_copies (op0, mode)
4380 == GET_MODE_BITSIZE (mode)))
4382 op0 = expand_compound_operation (op0);
4383 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4386 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4388 if (STORE_FLAG_VALUE == -1
4389 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4390 && op1 == const0_rtx
4391 && (num_sign_bit_copies (op0, mode)
4392 == GET_MODE_BITSIZE (mode)))
4393 return gen_lowpart_for_combine (mode,
4394 expand_compound_operation (op0));
4396 else if (STORE_FLAG_VALUE == -1
4397 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4398 && op1 == const0_rtx
4399 && nonzero_bits (op0, mode) == 1)
4401 op0 = expand_compound_operation (op0);
4402 return gen_unary (NEG, mode, mode,
4403 gen_lowpart_for_combine (mode, op0));
4406 else if (STORE_FLAG_VALUE == -1
4407 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4408 && op1 == const0_rtx
4409 && (num_sign_bit_copies (op0, mode)
4410 == GET_MODE_BITSIZE (mode)))
4412 op0 = expand_compound_operation (op0);
4413 return gen_unary (NOT, mode, mode,
4414 gen_lowpart_for_combine (mode, op0));
4417 /* If X is 0/1, (eq X 0) is X-1. */
4418 else if (STORE_FLAG_VALUE == -1
4419 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4420 && op1 == const0_rtx
4421 && nonzero_bits (op0, mode) == 1)
4423 op0 = expand_compound_operation (op0);
4424 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4427 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4428 one bit that might be nonzero, we can convert (ne x 0) to
4429 (ashift x c) where C puts the bit in the sign bit. Remove any
4430 AND with STORE_FLAG_VALUE when we are done, since we are only
4431 going to test the sign bit. */
4432 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4433 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4434 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4435 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4436 && op1 == const0_rtx
4437 && mode == GET_MODE (op0)
4438 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4440 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4441 expand_compound_operation (op0),
4442 GET_MODE_BITSIZE (mode) - 1 - i);
4443 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4449 /* If the code changed, return a whole new comparison. */
4450 if (new_code != code)
4451 return gen_rtx_combine (new_code, mode, op0, op1);
4453 /* Otherwise, keep this operation, but maybe change its operands.
4454 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4455 SUBST (XEXP (x, 0), op0);
4456 SUBST (XEXP (x, 1), op1);
4461 return simplify_if_then_else (x);
4467 /* If we are processing SET_DEST, we are done. */
4471 return expand_compound_operation (x);
4474 return simplify_set (x);
4479 return simplify_logical (x, last);
4482 /* (abs (neg <foo>)) -> (abs <foo>) */
4483 if (GET_CODE (XEXP (x, 0)) == NEG)
4484 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4486 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4488 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4491 /* If operand is something known to be positive, ignore the ABS. */
4492 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4493 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4494 <= HOST_BITS_PER_WIDE_INT)
4495 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4496 & ((HOST_WIDE_INT) 1
4497 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4501 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4502 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4503 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4508 /* (ffs (*_extend <X>)) = (ffs <X>) */
4509 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4510 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4511 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4515 /* (float (sign_extend <X>)) = (float <X>). */
4516 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4517 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4525 /* If this is a shift by a constant amount, simplify it. */
4526 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4527 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4528 INTVAL (XEXP (x, 1)));
4530 #ifdef SHIFT_COUNT_TRUNCATED
4531 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4533 force_to_mode (XEXP (x, 1), GET_MODE (x),
4535 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4549 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4552 simplify_if_then_else (x)
4555 enum machine_mode mode = GET_MODE (x);
4556 rtx cond = XEXP (x, 0);
4557 rtx true = XEXP (x, 1);
4558 rtx false = XEXP (x, 2);
4559 enum rtx_code true_code = GET_CODE (cond);
4560 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4564 /* Simplify storing of the truth value. */
4565 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4566 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4568 /* Also when the truth value has to be reversed. */
4569 if (comparison_p && reversible_comparison_p (cond)
4570 && true == const0_rtx && false == const_true_rtx)
4571 return gen_binary (reverse_condition (true_code),
4572 mode, XEXP (cond, 0), XEXP (cond, 1));
4574 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4575 in it is being compared against certain values. Get the true and false
4576 comparisons and see if that says anything about the value of each arm. */
4578 if (comparison_p && reversible_comparison_p (cond)
4579 && GET_CODE (XEXP (cond, 0)) == REG)
4582 rtx from = XEXP (cond, 0);
4583 enum rtx_code false_code = reverse_condition (true_code);
4584 rtx true_val = XEXP (cond, 1);
4585 rtx false_val = true_val;
4588 /* If FALSE_CODE is EQ, swap the codes and arms. */
4590 if (false_code == EQ)
4592 swapped = 1, true_code = EQ, false_code = NE;
4593 temp = true, true = false, false = temp;
4596 /* If we are comparing against zero and the expression being tested has
4597 only a single bit that might be nonzero, that is its value when it is
4598 not equal to zero. Similarly if it is known to be -1 or 0. */
4600 if (true_code == EQ && true_val == const0_rtx
4601 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4602 false_code = EQ, false_val = GEN_INT (nzb);
4603 else if (true_code == EQ && true_val == const0_rtx
4604 && (num_sign_bit_copies (from, GET_MODE (from))
4605 == GET_MODE_BITSIZE (GET_MODE (from))))
4606 false_code = EQ, false_val = constm1_rtx;
4608 /* Now simplify an arm if we know the value of the register in the
4609 branch and it is used in the arm. Be careful due to the potential
4610 of locally-shared RTL. */
4612 if (reg_mentioned_p (from, true))
4613 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4614 pc_rtx, pc_rtx, 0, 0);
4615 if (reg_mentioned_p (from, false))
4616 false = subst (known_cond (copy_rtx (false), false_code,
4618 pc_rtx, pc_rtx, 0, 0);
4620 SUBST (XEXP (x, 1), swapped ? false : true);
4621 SUBST (XEXP (x, 2), swapped ? true : false);
4623 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4626 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4627 reversed, do so to avoid needing two sets of patterns for
4628 subtract-and-branch insns. Similarly if we have a constant in the true
4629 arm, the false arm is the same as the first operand of the comparison, or
4630 the false arm is more complicated than the true arm. */
4632 if (comparison_p && reversible_comparison_p (cond)
4634 || (CONSTANT_P (true)
4635 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4636 || true == const0_rtx
4637 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4638 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4639 || (GET_CODE (true) == SUBREG
4640 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4641 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4642 || reg_mentioned_p (true, false)
4643 || rtx_equal_p (false, XEXP (cond, 0))))
4645 true_code = reverse_condition (true_code);
4647 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4650 SUBST (XEXP (x, 1), false);
4651 SUBST (XEXP (x, 2), true);
4653 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4655 /* It is possible that the conditional has been simplified out. */
4656 true_code = GET_CODE (cond);
4657 comparison_p = GET_RTX_CLASS (true_code) == '<';
4660 /* If the two arms are identical, we don't need the comparison. */
4662 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4665 /* Convert a == b ? b : a to "a". */
4666 if (true_code == EQ && ! side_effects_p (cond)
4667 && rtx_equal_p (XEXP (cond, 0), false)
4668 && rtx_equal_p (XEXP (cond, 1), true))
4670 else if (true_code == NE && ! side_effects_p (cond)
4671 && rtx_equal_p (XEXP (cond, 0), true)
4672 && rtx_equal_p (XEXP (cond, 1), false))
4675 /* Look for cases where we have (abs x) or (neg (abs X)). */
4677 if (GET_MODE_CLASS (mode) == MODE_INT
4678 && GET_CODE (false) == NEG
4679 && rtx_equal_p (true, XEXP (false, 0))
4681 && rtx_equal_p (true, XEXP (cond, 0))
4682 && ! side_effects_p (true))
4687 return gen_unary (ABS, mode, mode, true);
4690 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4695 /* Look for MIN or MAX. */
4697 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4699 && rtx_equal_p (XEXP (cond, 0), true)
4700 && rtx_equal_p (XEXP (cond, 1), false)
4701 && ! side_effects_p (cond))
4706 return gen_binary (SMAX, mode, true, false);
4709 return gen_binary (SMIN, mode, true, false);
4712 return gen_binary (UMAX, mode, true, false);
4715 return gen_binary (UMIN, mode, true, false);
4720 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4721 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4722 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4723 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4724 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4725 neither 1 or -1, but it isn't worth checking for. */
4727 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4728 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4730 rtx t = make_compound_operation (true, SET);
4731 rtx f = make_compound_operation (false, SET);
4732 rtx cond_op0 = XEXP (cond, 0);
4733 rtx cond_op1 = XEXP (cond, 1);
4734 enum rtx_code op = NIL, extend_op = NIL;
4735 enum machine_mode m = mode;
4736 rtx z = 0, c1 = NULL_RTX;
4738 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4739 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4740 || GET_CODE (t) == ASHIFT
4741 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4742 && rtx_equal_p (XEXP (t, 0), f))
4743 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4745 /* If an identity-zero op is commutative, check whether there
4746 would be a match if we swapped the operands. */
4747 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4748 || GET_CODE (t) == XOR)
4749 && rtx_equal_p (XEXP (t, 1), f))
4750 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4751 else if (GET_CODE (t) == SIGN_EXTEND
4752 && (GET_CODE (XEXP (t, 0)) == PLUS
4753 || GET_CODE (XEXP (t, 0)) == MINUS
4754 || GET_CODE (XEXP (t, 0)) == IOR
4755 || GET_CODE (XEXP (t, 0)) == XOR
4756 || GET_CODE (XEXP (t, 0)) == ASHIFT
4757 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4758 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4759 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4760 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4761 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4762 && (num_sign_bit_copies (f, GET_MODE (f))
4763 > (GET_MODE_BITSIZE (mode)
4764 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4766 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4767 extend_op = SIGN_EXTEND;
4768 m = GET_MODE (XEXP (t, 0));
4770 else if (GET_CODE (t) == SIGN_EXTEND
4771 && (GET_CODE (XEXP (t, 0)) == PLUS
4772 || GET_CODE (XEXP (t, 0)) == IOR
4773 || GET_CODE (XEXP (t, 0)) == XOR)
4774 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4775 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4776 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4777 && (num_sign_bit_copies (f, GET_MODE (f))
4778 > (GET_MODE_BITSIZE (mode)
4779 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4781 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4782 extend_op = SIGN_EXTEND;
4783 m = GET_MODE (XEXP (t, 0));
4785 else if (GET_CODE (t) == ZERO_EXTEND
4786 && (GET_CODE (XEXP (t, 0)) == PLUS
4787 || GET_CODE (XEXP (t, 0)) == MINUS
4788 || GET_CODE (XEXP (t, 0)) == IOR
4789 || GET_CODE (XEXP (t, 0)) == XOR
4790 || GET_CODE (XEXP (t, 0)) == ASHIFT
4791 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4792 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4793 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4794 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4795 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4796 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4797 && ((nonzero_bits (f, GET_MODE (f))
4798 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4801 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4802 extend_op = ZERO_EXTEND;
4803 m = GET_MODE (XEXP (t, 0));
4805 else if (GET_CODE (t) == ZERO_EXTEND
4806 && (GET_CODE (XEXP (t, 0)) == PLUS
4807 || GET_CODE (XEXP (t, 0)) == IOR
4808 || GET_CODE (XEXP (t, 0)) == XOR)
4809 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4810 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4811 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4812 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4813 && ((nonzero_bits (f, GET_MODE (f))
4814 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4817 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4818 extend_op = ZERO_EXTEND;
4819 m = GET_MODE (XEXP (t, 0));
4824 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4825 pc_rtx, pc_rtx, 0, 0);
4826 temp = gen_binary (MULT, m, temp,
4827 gen_binary (MULT, m, c1, const_true_rtx));
4828 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4829 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4831 if (extend_op != NIL)
4832 temp = gen_unary (extend_op, mode, m, temp);
4838 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4839 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4840 negation of a single bit, we can convert this operation to a shift. We
4841 can actually do this more generally, but it doesn't seem worth it. */
4843 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4844 && false == const0_rtx && GET_CODE (true) == CONST_INT
4845 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4846 && (i = exact_log2 (INTVAL (true))) >= 0)
4847 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4848 == GET_MODE_BITSIZE (mode))
4849 && (i = exact_log2 (-INTVAL (true))) >= 0)))
4851 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4852 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4857 /* Simplify X, a SET expression. Return the new expression. */
4863 rtx src = SET_SRC (x);
4864 rtx dest = SET_DEST (x);
4865 enum machine_mode mode
4866 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4870 /* (set (pc) (return)) gets written as (return). */
4871 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4874 /* Now that we know for sure which bits of SRC we are using, see if we can
4875 simplify the expression for the object knowing that we only need the
4878 if (GET_MODE_CLASS (mode) == MODE_INT)
4880 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4881 SUBST (SET_SRC (x), src);
4884 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4885 the comparison result and try to simplify it unless we already have used
4886 undobuf.other_insn. */
4887 if ((GET_CODE (src) == COMPARE
4892 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4893 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4894 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4895 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4897 enum rtx_code old_code = GET_CODE (*cc_use);
4898 enum rtx_code new_code;
4900 int other_changed = 0;
4901 enum machine_mode compare_mode = GET_MODE (dest);
4903 if (GET_CODE (src) == COMPARE)
4904 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4906 op0 = src, op1 = const0_rtx;
4908 /* Simplify our comparison, if possible. */
4909 new_code = simplify_comparison (old_code, &op0, &op1);
4911 #ifdef EXTRA_CC_MODES
4912 /* If this machine has CC modes other than CCmode, check to see if we
4913 need to use a different CC mode here. */
4914 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4915 #endif /* EXTRA_CC_MODES */
4917 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4918 /* If the mode changed, we have to change SET_DEST, the mode in the
4919 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4920 a hard register, just build new versions with the proper mode. If it
4921 is a pseudo, we lose unless it is only time we set the pseudo, in
4922 which case we can safely change its mode. */
4923 if (compare_mode != GET_MODE (dest))
4925 unsigned int regno = REGNO (dest);
4926 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4928 if (regno < FIRST_PSEUDO_REGISTER
4929 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4931 if (regno >= FIRST_PSEUDO_REGISTER)
4932 SUBST (regno_reg_rtx[regno], new_dest);
4934 SUBST (SET_DEST (x), new_dest);
4935 SUBST (XEXP (*cc_use, 0), new_dest);
4943 /* If the code changed, we have to build a new comparison in
4944 undobuf.other_insn. */
4945 if (new_code != old_code)
4947 unsigned HOST_WIDE_INT mask;
4949 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4952 /* If the only change we made was to change an EQ into an NE or
4953 vice versa, OP0 has only one bit that might be nonzero, and OP1
4954 is zero, check if changing the user of the condition code will
4955 produce a valid insn. If it won't, we can keep the original code
4956 in that insn by surrounding our operation with an XOR. */
4958 if (((old_code == NE && new_code == EQ)
4959 || (old_code == EQ && new_code == NE))
4960 && ! other_changed && op1 == const0_rtx
4961 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4962 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4964 rtx pat = PATTERN (other_insn), note = 0;
4966 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4967 && ! check_asm_operands (pat)))
4969 PUT_CODE (*cc_use, old_code);
4972 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4980 undobuf.other_insn = other_insn;
4983 /* If we are now comparing against zero, change our source if
4984 needed. If we do not use cc0, we always have a COMPARE. */
4985 if (op1 == const0_rtx && dest == cc0_rtx)
4987 SUBST (SET_SRC (x), op0);
4993 /* Otherwise, if we didn't previously have a COMPARE in the
4994 correct mode, we need one. */
4995 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4998 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5003 /* Otherwise, update the COMPARE if needed. */
5004 SUBST (XEXP (src, 0), op0);
5005 SUBST (XEXP (src, 1), op1);
5010 /* Get SET_SRC in a form where we have placed back any
5011 compound expressions. Then do the checks below. */
5012 src = make_compound_operation (src, SET);
5013 SUBST (SET_SRC (x), src);
5016 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5017 and X being a REG or (subreg (reg)), we may be able to convert this to
5018 (set (subreg:m2 x) (op)).
5020 We can always do this if M1 is narrower than M2 because that means that
5021 we only care about the low bits of the result.
5023 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5024 perform a narrower operation than requested since the high-order bits will
5025 be undefined. On machine where it is defined, this transformation is safe
5026 as long as M1 and M2 have the same number of words. */
5028 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5029 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5030 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5032 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5033 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5034 #ifndef WORD_REGISTER_OPERATIONS
5035 && (GET_MODE_SIZE (GET_MODE (src))
5036 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5038 #ifdef CLASS_CANNOT_CHANGE_MODE
5039 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5040 && (TEST_HARD_REG_BIT
5041 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5043 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5044 GET_MODE (SUBREG_REG (src))))
5046 && (GET_CODE (dest) == REG
5047 || (GET_CODE (dest) == SUBREG
5048 && GET_CODE (SUBREG_REG (dest)) == REG)))
5050 SUBST (SET_DEST (x),
5051 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5053 SUBST (SET_SRC (x), SUBREG_REG (src));
5055 src = SET_SRC (x), dest = SET_DEST (x);
5058 #ifdef LOAD_EXTEND_OP
5059 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5060 would require a paradoxical subreg. Replace the subreg with a
5061 zero_extend to avoid the reload that would otherwise be required. */
5063 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5064 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5065 && SUBREG_WORD (src) == 0
5066 && (GET_MODE_SIZE (GET_MODE (src))
5067 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5068 && GET_CODE (SUBREG_REG (src)) == MEM)
5071 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5072 GET_MODE (src), XEXP (src, 0)));
5078 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5079 are comparing an item known to be 0 or -1 against 0, use a logical
5080 operation instead. Check for one of the arms being an IOR of the other
5081 arm with some value. We compute three terms to be IOR'ed together. In
5082 practice, at most two will be nonzero. Then we do the IOR's. */
5084 if (GET_CODE (dest) != PC
5085 && GET_CODE (src) == IF_THEN_ELSE
5086 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5087 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5088 && XEXP (XEXP (src, 0), 1) == const0_rtx
5089 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5090 #ifdef HAVE_conditional_move
5091 && ! can_conditionally_move_p (GET_MODE (src))
5093 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5094 GET_MODE (XEXP (XEXP (src, 0), 0)))
5095 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5096 && ! side_effects_p (src))
5098 rtx true = (GET_CODE (XEXP (src, 0)) == NE
5099 ? XEXP (src, 1) : XEXP (src, 2));
5100 rtx false = (GET_CODE (XEXP (src, 0)) == NE
5101 ? XEXP (src, 2) : XEXP (src, 1));
5102 rtx term1 = const0_rtx, term2, term3;
5104 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
5105 term1 = false, true = XEXP (true, 1), false = const0_rtx;
5106 else if (GET_CODE (true) == IOR
5107 && rtx_equal_p (XEXP (true, 1), false))
5108 term1 = false, true = XEXP (true, 0), false = const0_rtx;
5109 else if (GET_CODE (false) == IOR
5110 && rtx_equal_p (XEXP (false, 0), true))
5111 term1 = true, false = XEXP (false, 1), true = const0_rtx;
5112 else if (GET_CODE (false) == IOR
5113 && rtx_equal_p (XEXP (false, 1), true))
5114 term1 = true, false = XEXP (false, 0), true = const0_rtx;
5116 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
5117 term3 = gen_binary (AND, GET_MODE (src),
5118 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5119 XEXP (XEXP (src, 0), 0)),
5123 gen_binary (IOR, GET_MODE (src),
5124 gen_binary (IOR, GET_MODE (src), term1, term2),
5130 #ifdef HAVE_conditional_arithmetic
5131 /* If we have conditional arithmetic and the operand of a SET is
5132 a conditional expression, replace this with an IF_THEN_ELSE.
5133 We can either have a conditional expression or a MULT of that expression
5135 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
5136 || GET_RTX_CLASS (GET_CODE (src)) == '2'
5137 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
5138 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
5139 || (GET_CODE (XEXP (src, 0)) == MULT
5140 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
5141 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
5143 rtx cond = XEXP (src, 0);
5144 rtx true_val = const1_rtx;
5145 rtx false_arm, true_arm;
5147 if (GET_CODE (cond) == MULT)
5149 true_val = XEXP (cond, 1);
5150 cond = XEXP (cond, 0);
5153 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
5155 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5156 GET_MODE (XEXP (src, 0)), true_val);
5157 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
5158 GET_MODE (XEXP (src, 0)), const0_rtx);
5162 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5163 true_val, XEXP (src, 1));
5164 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
5165 const0_rtx, XEXP (src, 1));
5168 /* Canonicalize if true_arm is the simpler one. */
5169 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
5170 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
5171 && reversible_comparison_p (cond))
5173 rtx temp = true_arm;
5175 true_arm = false_arm;
5178 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
5179 GET_MODE (cond), XEXP (cond, 0),
5183 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
5184 gen_rtx_combine (GET_CODE (cond), VOIDmode,
5187 true_arm, false_arm);
5188 SUBST (SET_SRC (x), src);
5192 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5193 whole thing fail. */
5194 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5196 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5199 /* Convert this into a field assignment operation, if possible. */
5200 return make_field_assignment (x);
5203 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5204 result. LAST is nonzero if this is the last retry. */
5207 simplify_logical (x, last)
5211 enum machine_mode mode = GET_MODE (x);
5212 rtx op0 = XEXP (x, 0);
5213 rtx op1 = XEXP (x, 1);
5215 switch (GET_CODE (x))
5218 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5219 insn (and may simplify more). */
5220 if (GET_CODE (op0) == XOR
5221 && rtx_equal_p (XEXP (op0, 0), op1)
5222 && ! side_effects_p (op1))
5223 x = gen_binary (AND, mode,
5224 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5226 if (GET_CODE (op0) == XOR
5227 && rtx_equal_p (XEXP (op0, 1), op1)
5228 && ! side_effects_p (op1))
5229 x = gen_binary (AND, mode,
5230 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5232 /* Similarly for (~(A ^ B)) & A. */
5233 if (GET_CODE (op0) == NOT
5234 && GET_CODE (XEXP (op0, 0)) == XOR
5235 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5236 && ! side_effects_p (op1))
5237 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5239 if (GET_CODE (op0) == NOT
5240 && GET_CODE (XEXP (op0, 0)) == XOR
5241 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5242 && ! side_effects_p (op1))
5243 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5245 /* We can call simplify_and_const_int only if we don't lose
5246 any (sign) bits when converting INTVAL (op1) to
5247 "unsigned HOST_WIDE_INT". */
5248 if (GET_CODE (op1) == CONST_INT
5249 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5250 || INTVAL (op1) > 0))
5252 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5254 /* If we have (ior (and (X C1) C2)) and the next restart would be
5255 the last, simplify this by making C1 as small as possible
5258 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5259 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5260 && GET_CODE (op1) == CONST_INT)
5261 return gen_binary (IOR, mode,
5262 gen_binary (AND, mode, XEXP (op0, 0),
5263 GEN_INT (INTVAL (XEXP (op0, 1))
5264 & ~INTVAL (op1))), op1);
5266 if (GET_CODE (x) != AND)
5269 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5270 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5271 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5274 /* Convert (A | B) & A to A. */
5275 if (GET_CODE (op0) == IOR
5276 && (rtx_equal_p (XEXP (op0, 0), op1)
5277 || rtx_equal_p (XEXP (op0, 1), op1))
5278 && ! side_effects_p (XEXP (op0, 0))
5279 && ! side_effects_p (XEXP (op0, 1)))
5282 /* In the following group of tests (and those in case IOR below),
5283 we start with some combination of logical operations and apply
5284 the distributive law followed by the inverse distributive law.
5285 Most of the time, this results in no change. However, if some of
5286 the operands are the same or inverses of each other, simplifications
5289 For example, (and (ior A B) (not B)) can occur as the result of
5290 expanding a bit field assignment. When we apply the distributive
5291 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5292 which then simplifies to (and (A (not B))).
5294 If we have (and (ior A B) C), apply the distributive law and then
5295 the inverse distributive law to see if things simplify. */
5297 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5299 x = apply_distributive_law
5300 (gen_binary (GET_CODE (op0), mode,
5301 gen_binary (AND, mode, XEXP (op0, 0), op1),
5302 gen_binary (AND, mode, XEXP (op0, 1),
5304 if (GET_CODE (x) != AND)
5308 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5309 return apply_distributive_law
5310 (gen_binary (GET_CODE (op1), mode,
5311 gen_binary (AND, mode, XEXP (op1, 0), op0),
5312 gen_binary (AND, mode, XEXP (op1, 1),
5315 /* Similarly, taking advantage of the fact that
5316 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5318 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5319 return apply_distributive_law
5320 (gen_binary (XOR, mode,
5321 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5322 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5325 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5326 return apply_distributive_law
5327 (gen_binary (XOR, mode,
5328 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5329 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5333 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5334 if (GET_CODE (op1) == CONST_INT
5335 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5336 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5339 /* Convert (A & B) | A to A. */
5340 if (GET_CODE (op0) == AND
5341 && (rtx_equal_p (XEXP (op0, 0), op1)
5342 || rtx_equal_p (XEXP (op0, 1), op1))
5343 && ! side_effects_p (XEXP (op0, 0))
5344 && ! side_effects_p (XEXP (op0, 1)))
5347 /* If we have (ior (and A B) C), apply the distributive law and then
5348 the inverse distributive law to see if things simplify. */
5350 if (GET_CODE (op0) == AND)
5352 x = apply_distributive_law
5353 (gen_binary (AND, mode,
5354 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5355 gen_binary (IOR, mode, XEXP (op0, 1),
5358 if (GET_CODE (x) != IOR)
5362 if (GET_CODE (op1) == AND)
5364 x = apply_distributive_law
5365 (gen_binary (AND, mode,
5366 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5367 gen_binary (IOR, mode, XEXP (op1, 1),
5370 if (GET_CODE (x) != IOR)
5374 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5375 mode size to (rotate A CX). */
5377 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5378 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5379 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5380 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5381 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5382 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5383 == GET_MODE_BITSIZE (mode)))
5384 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5385 (GET_CODE (op0) == ASHIFT
5386 ? XEXP (op0, 1) : XEXP (op1, 1)));
5388 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5389 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5390 does not affect any of the bits in OP1, it can really be done
5391 as a PLUS and we can associate. We do this by seeing if OP1
5392 can be safely shifted left C bits. */
5393 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5394 && GET_CODE (XEXP (op0, 0)) == PLUS
5395 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5396 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5397 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5399 int count = INTVAL (XEXP (op0, 1));
5400 HOST_WIDE_INT mask = INTVAL (op1) << count;
5402 if (mask >> count == INTVAL (op1)
5403 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5405 SUBST (XEXP (XEXP (op0, 0), 1),
5406 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5413 /* If we are XORing two things that have no bits in common,
5414 convert them into an IOR. This helps to detect rotation encoded
5415 using those methods and possibly other simplifications. */
5417 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5418 && (nonzero_bits (op0, mode)
5419 & nonzero_bits (op1, mode)) == 0)
5420 return (gen_binary (IOR, mode, op0, op1));
5422 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5423 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5426 int num_negated = 0;
5428 if (GET_CODE (op0) == NOT)
5429 num_negated++, op0 = XEXP (op0, 0);
5430 if (GET_CODE (op1) == NOT)
5431 num_negated++, op1 = XEXP (op1, 0);
5433 if (num_negated == 2)
5435 SUBST (XEXP (x, 0), op0);
5436 SUBST (XEXP (x, 1), op1);
5438 else if (num_negated == 1)
5439 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5442 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5443 correspond to a machine insn or result in further simplifications
5444 if B is a constant. */
5446 if (GET_CODE (op0) == AND
5447 && rtx_equal_p (XEXP (op0, 1), op1)
5448 && ! side_effects_p (op1))
5449 return gen_binary (AND, mode,
5450 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5453 else if (GET_CODE (op0) == AND
5454 && rtx_equal_p (XEXP (op0, 0), op1)
5455 && ! side_effects_p (op1))
5456 return gen_binary (AND, mode,
5457 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5460 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5461 comparison if STORE_FLAG_VALUE is 1. */
5462 if (STORE_FLAG_VALUE == 1
5463 && op1 == const1_rtx
5464 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5465 && reversible_comparison_p (op0))
5466 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5467 mode, XEXP (op0, 0), XEXP (op0, 1));
5469 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5470 is (lt foo (const_int 0)), so we can perform the above
5471 simplification if STORE_FLAG_VALUE is 1. */
5473 if (STORE_FLAG_VALUE == 1
5474 && op1 == const1_rtx
5475 && GET_CODE (op0) == LSHIFTRT
5476 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5477 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5478 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5480 /* (xor (comparison foo bar) (const_int sign-bit))
5481 when STORE_FLAG_VALUE is the sign bit. */
5482 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5483 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5484 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5485 && op1 == const_true_rtx
5486 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5487 && reversible_comparison_p (op0))
5488 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5489 mode, XEXP (op0, 0), XEXP (op0, 1));
5500 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5501 operations" because they can be replaced with two more basic operations.
5502 ZERO_EXTEND is also considered "compound" because it can be replaced with
5503 an AND operation, which is simpler, though only one operation.
5505 The function expand_compound_operation is called with an rtx expression
5506 and will convert it to the appropriate shifts and AND operations,
5507 simplifying at each stage.
5509 The function make_compound_operation is called to convert an expression
5510 consisting of shifts and ANDs into the equivalent compound expression.
5511 It is the inverse of this function, loosely speaking. */
5514 expand_compound_operation (x)
5517 unsigned HOST_WIDE_INT pos = 0, len;
5519 unsigned int modewidth;
5522 switch (GET_CODE (x))
5527 /* We can't necessarily use a const_int for a multiword mode;
5528 it depends on implicitly extending the value.
5529 Since we don't know the right way to extend it,
5530 we can't tell whether the implicit way is right.
5532 Even for a mode that is no wider than a const_int,
5533 we can't win, because we need to sign extend one of its bits through
5534 the rest of it, and we don't know which bit. */
5535 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5538 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5539 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5540 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5541 reloaded. If not for that, MEM's would very rarely be safe.
5543 Reject MODEs bigger than a word, because we might not be able
5544 to reference a two-register group starting with an arbitrary register
5545 (and currently gen_lowpart might crash for a SUBREG). */
5547 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5550 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5551 /* If the inner object has VOIDmode (the only way this can happen
5552 is if it is a ASM_OPERANDS), we can't do anything since we don't
5553 know how much masking to do. */
5562 /* If the operand is a CLOBBER, just return it. */
5563 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5566 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5567 || GET_CODE (XEXP (x, 2)) != CONST_INT
5568 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5571 len = INTVAL (XEXP (x, 1));
5572 pos = INTVAL (XEXP (x, 2));
5574 /* If this goes outside the object being extracted, replace the object
5575 with a (use (mem ...)) construct that only combine understands
5576 and is used only for this purpose. */
5577 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5578 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5580 if (BITS_BIG_ENDIAN)
5581 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5588 /* Convert sign extension to zero extension, if we know that the high
5589 bit is not set, as this is easier to optimize. It will be converted
5590 back to cheaper alternative in make_extraction. */
5591 if (GET_CODE (x) == SIGN_EXTEND
5592 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5593 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5594 & ~(((unsigned HOST_WIDE_INT)
5595 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5599 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5600 return expand_compound_operation (temp);
5603 /* We can optimize some special cases of ZERO_EXTEND. */
5604 if (GET_CODE (x) == ZERO_EXTEND)
5606 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5607 know that the last value didn't have any inappropriate bits
5609 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5610 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5611 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5612 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5613 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5614 return XEXP (XEXP (x, 0), 0);
5616 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5617 if (GET_CODE (XEXP (x, 0)) == SUBREG
5618 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5619 && subreg_lowpart_p (XEXP (x, 0))
5620 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5621 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5622 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5623 return SUBREG_REG (XEXP (x, 0));
5625 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5626 is a comparison and STORE_FLAG_VALUE permits. This is like
5627 the first case, but it works even when GET_MODE (x) is larger
5628 than HOST_WIDE_INT. */
5629 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5630 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5631 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5632 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5633 <= HOST_BITS_PER_WIDE_INT)
5634 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5635 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5636 return XEXP (XEXP (x, 0), 0);
5638 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5639 if (GET_CODE (XEXP (x, 0)) == SUBREG
5640 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5641 && subreg_lowpart_p (XEXP (x, 0))
5642 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5643 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5644 <= HOST_BITS_PER_WIDE_INT)
5645 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5646 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5647 return SUBREG_REG (XEXP (x, 0));
5651 /* If we reach here, we want to return a pair of shifts. The inner
5652 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5653 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5654 logical depending on the value of UNSIGNEDP.
5656 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5657 converted into an AND of a shift.
5659 We must check for the case where the left shift would have a negative
5660 count. This can happen in a case like (x >> 31) & 255 on machines
5661 that can't shift by a constant. On those machines, we would first
5662 combine the shift with the AND to produce a variable-position
5663 extraction. Then the constant of 31 would be substituted in to produce
5664 a such a position. */
5666 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5667 if (modewidth + len >= pos)
5668 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5670 simplify_shift_const (NULL_RTX, ASHIFT,
5673 modewidth - pos - len),
5676 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5677 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5678 simplify_shift_const (NULL_RTX, LSHIFTRT,
5681 ((HOST_WIDE_INT) 1 << len) - 1);
5683 /* Any other cases we can't handle. */
5686 /* If we couldn't do this for some reason, return the original
5688 if (GET_CODE (tem) == CLOBBER)
5694 /* X is a SET which contains an assignment of one object into
5695 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5696 or certain SUBREGS). If possible, convert it into a series of
5699 We half-heartedly support variable positions, but do not at all
5700 support variable lengths. */
5703 expand_field_assignment (x)
5707 rtx pos; /* Always counts from low bit. */
5710 enum machine_mode compute_mode;
5712 /* Loop until we find something we can't simplify. */
5715 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5716 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5718 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5719 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5720 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5722 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5723 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5725 inner = XEXP (SET_DEST (x), 0);
5726 len = INTVAL (XEXP (SET_DEST (x), 1));
5727 pos = XEXP (SET_DEST (x), 2);
5729 /* If the position is constant and spans the width of INNER,
5730 surround INNER with a USE to indicate this. */
5731 if (GET_CODE (pos) == CONST_INT
5732 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5733 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5735 if (BITS_BIG_ENDIAN)
5737 if (GET_CODE (pos) == CONST_INT)
5738 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5740 else if (GET_CODE (pos) == MINUS
5741 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5742 && (INTVAL (XEXP (pos, 1))
5743 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5744 /* If position is ADJUST - X, new position is X. */
5745 pos = XEXP (pos, 0);
5747 pos = gen_binary (MINUS, GET_MODE (pos),
5748 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5754 /* A SUBREG between two modes that occupy the same numbers of words
5755 can be done by moving the SUBREG to the source. */
5756 else if (GET_CODE (SET_DEST (x)) == SUBREG
5757 /* We need SUBREGs to compute nonzero_bits properly. */
5758 && nonzero_sign_valid
5759 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5760 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5761 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5762 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5764 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5765 gen_lowpart_for_combine
5766 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5773 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5774 inner = SUBREG_REG (inner);
5776 compute_mode = GET_MODE (inner);
5778 /* Don't attempt bitwise arithmetic on non-integral modes. */
5779 if (! INTEGRAL_MODE_P (compute_mode))
5781 enum machine_mode imode;
5783 /* Something is probably seriously wrong if this matches. */
5784 if (! FLOAT_MODE_P (compute_mode))
5787 /* Try to find an integral mode to pun with. */
5788 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5789 if (imode == BLKmode)
5792 compute_mode = imode;
5793 inner = gen_lowpart_for_combine (imode, inner);
5796 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5797 if (len < HOST_BITS_PER_WIDE_INT)
5798 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5802 /* Now compute the equivalent expression. Make a copy of INNER
5803 for the SET_DEST in case it is a MEM into which we will substitute;
5804 we don't want shared RTL in that case. */
5806 (VOIDmode, copy_rtx (inner),
5807 gen_binary (IOR, compute_mode,
5808 gen_binary (AND, compute_mode,
5809 gen_unary (NOT, compute_mode,
5815 gen_binary (ASHIFT, compute_mode,
5816 gen_binary (AND, compute_mode,
5817 gen_lowpart_for_combine
5818 (compute_mode, SET_SRC (x)),
5826 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5827 it is an RTX that represents a variable starting position; otherwise,
5828 POS is the (constant) starting bit position (counted from the LSB).
5830 INNER may be a USE. This will occur when we started with a bitfield
5831 that went outside the boundary of the object in memory, which is
5832 allowed on most machines. To isolate this case, we produce a USE
5833 whose mode is wide enough and surround the MEM with it. The only
5834 code that understands the USE is this routine. If it is not removed,
5835 it will cause the resulting insn not to match.
5837 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5840 IN_DEST is non-zero if this is a reference in the destination of a
5841 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5842 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5845 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5846 ZERO_EXTRACT should be built even for bits starting at bit 0.
5848 MODE is the desired mode of the result (if IN_DEST == 0).
5850 The result is an RTX for the extraction or NULL_RTX if the target
5854 make_extraction (mode, inner, pos, pos_rtx, len,
5855 unsignedp, in_dest, in_compare)
5856 enum machine_mode mode;
5860 unsigned HOST_WIDE_INT len;
5862 int in_dest, in_compare;
5864 /* This mode describes the size of the storage area
5865 to fetch the overall value from. Within that, we
5866 ignore the POS lowest bits, etc. */
5867 enum machine_mode is_mode = GET_MODE (inner);
5868 enum machine_mode inner_mode;
5869 enum machine_mode wanted_inner_mode = byte_mode;
5870 enum machine_mode wanted_inner_reg_mode = word_mode;
5871 enum machine_mode pos_mode = word_mode;
5872 enum machine_mode extraction_mode = word_mode;
5873 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5876 rtx orig_pos_rtx = pos_rtx;
5877 HOST_WIDE_INT orig_pos;
5879 /* Get some information about INNER and get the innermost object. */
5880 if (GET_CODE (inner) == USE)
5881 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5882 /* We don't need to adjust the position because we set up the USE
5883 to pretend that it was a full-word object. */
5884 spans_byte = 1, inner = XEXP (inner, 0);
5885 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5887 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5888 consider just the QI as the memory to extract from.
5889 The subreg adds or removes high bits; its mode is
5890 irrelevant to the meaning of this extraction,
5891 since POS and LEN count from the lsb. */
5892 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5893 is_mode = GET_MODE (SUBREG_REG (inner));
5894 inner = SUBREG_REG (inner);
5897 inner_mode = GET_MODE (inner);
5899 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5900 pos = INTVAL (pos_rtx), pos_rtx = 0;
5902 /* See if this can be done without an extraction. We never can if the
5903 width of the field is not the same as that of some integer mode. For
5904 registers, we can only avoid the extraction if the position is at the
5905 low-order bit and this is either not in the destination or we have the
5906 appropriate STRICT_LOW_PART operation available.
5908 For MEM, we can avoid an extract if the field starts on an appropriate
5909 boundary and we can change the mode of the memory reference. However,
5910 we cannot directly access the MEM if we have a USE and the underlying
5911 MEM is not TMODE. This combination means that MEM was being used in a
5912 context where bits outside its mode were being referenced; that is only
5913 valid in bit-field insns. */
5915 if (tmode != BLKmode
5916 && ! (spans_byte && inner_mode != tmode)
5917 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5918 && GET_CODE (inner) != MEM
5920 || (GET_CODE (inner) == REG
5921 && (movstrict_optab->handlers[(int) tmode].insn_code
5922 != CODE_FOR_nothing))))
5923 || (GET_CODE (inner) == MEM && pos_rtx == 0
5925 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5926 : BITS_PER_UNIT)) == 0
5927 /* We can't do this if we are widening INNER_MODE (it
5928 may not be aligned, for one thing). */
5929 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5930 && (inner_mode == tmode
5931 || (! mode_dependent_address_p (XEXP (inner, 0))
5932 && ! MEM_VOLATILE_P (inner))))))
5934 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5935 field. If the original and current mode are the same, we need not
5936 adjust the offset. Otherwise, we do if bytes big endian.
5938 If INNER is not a MEM, get a piece consisting of just the field
5939 of interest (in this case POS % BITS_PER_WORD must be 0). */
5941 if (GET_CODE (inner) == MEM)
5944 /* POS counts from lsb, but make OFFSET count in memory order. */
5945 if (BYTES_BIG_ENDIAN)
5946 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5948 offset = pos / BITS_PER_UNIT;
5950 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5951 MEM_COPY_ATTRIBUTES (new, inner);
5953 else if (GET_CODE (inner) == REG)
5955 /* We can't call gen_lowpart_for_combine here since we always want
5956 a SUBREG and it would sometimes return a new hard register. */
5957 if (tmode != inner_mode)
5958 new = gen_rtx_SUBREG (tmode, inner,
5960 && (GET_MODE_SIZE (inner_mode)
5962 ? (((GET_MODE_SIZE (inner_mode)
5963 - GET_MODE_SIZE (tmode))
5965 - pos / BITS_PER_WORD)
5966 : pos / BITS_PER_WORD));
5971 new = force_to_mode (inner, tmode,
5972 len >= HOST_BITS_PER_WIDE_INT
5973 ? ~(HOST_WIDE_INT) 0
5974 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5977 /* If this extraction is going into the destination of a SET,
5978 make a STRICT_LOW_PART unless we made a MEM. */
5981 return (GET_CODE (new) == MEM ? new
5982 : (GET_CODE (new) != SUBREG
5983 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5984 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5989 /* If we know that no extraneous bits are set, and that the high
5990 bit is not set, convert the extraction to the cheaper of
5991 sign and zero extension, that are equivalent in these cases. */
5992 if (flag_expensive_optimizations
5993 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5994 && ((nonzero_bits (new, tmode)
5995 & ~(((unsigned HOST_WIDE_INT)
5996 GET_MODE_MASK (tmode))
6000 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6001 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6003 /* Prefer ZERO_EXTENSION, since it gives more information to
6005 if (rtx_cost (temp, SET) < rtx_cost (temp1, SET))
6010 /* Otherwise, sign- or zero-extend unless we already are in the
6013 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6017 /* Unless this is a COMPARE or we have a funny memory reference,
6018 don't do anything with zero-extending field extracts starting at
6019 the low-order bit since they are simple AND operations. */
6020 if (pos_rtx == 0 && pos == 0 && ! in_dest
6021 && ! in_compare && ! spans_byte && unsignedp)
6024 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6025 we would be spanning bytes or if the position is not a constant and the
6026 length is not 1. In all other cases, we would only be going outside
6027 our object in cases when an original shift would have been
6029 if (! spans_byte && GET_CODE (inner) == MEM
6030 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6031 || (pos_rtx != 0 && len != 1)))
6034 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6035 and the mode for the result. */
6039 wanted_inner_reg_mode
6040 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6041 if (wanted_inner_reg_mode == VOIDmode)
6042 wanted_inner_reg_mode = word_mode;
6044 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6045 if (pos_mode == VOIDmode)
6046 pos_mode = word_mode;
6048 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6049 if (extraction_mode == VOIDmode)
6050 extraction_mode = word_mode;
6055 if (! in_dest && unsignedp)
6057 wanted_inner_reg_mode
6058 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6059 if (wanted_inner_reg_mode == VOIDmode)
6060 wanted_inner_reg_mode = word_mode;
6062 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6063 if (pos_mode == VOIDmode)
6064 pos_mode = word_mode;
6066 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6067 if (extraction_mode == VOIDmode)
6068 extraction_mode = word_mode;
6073 if (! in_dest && ! unsignedp)
6075 wanted_inner_reg_mode
6076 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6077 if (wanted_inner_reg_mode == VOIDmode)
6078 wanted_inner_reg_mode = word_mode;
6080 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6081 if (pos_mode == VOIDmode)
6082 pos_mode = word_mode;
6084 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6085 if (extraction_mode == VOIDmode)
6086 extraction_mode = word_mode;
6090 /* Never narrow an object, since that might not be safe. */
6092 if (mode != VOIDmode
6093 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6094 extraction_mode = mode;
6096 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6097 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6098 pos_mode = GET_MODE (pos_rtx);
6100 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6101 if we have to change the mode of memory and cannot, the desired mode is
6103 if (GET_CODE (inner) != MEM)
6104 wanted_inner_mode = wanted_inner_reg_mode;
6105 else if (inner_mode != wanted_inner_mode
6106 && (mode_dependent_address_p (XEXP (inner, 0))
6107 || MEM_VOLATILE_P (inner)))
6108 wanted_inner_mode = extraction_mode;
6112 if (BITS_BIG_ENDIAN)
6114 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6115 BITS_BIG_ENDIAN style. If position is constant, compute new
6116 position. Otherwise, build subtraction.
6117 Note that POS is relative to the mode of the original argument.
6118 If it's a MEM we need to recompute POS relative to that.
6119 However, if we're extracting from (or inserting into) a register,
6120 we want to recompute POS relative to wanted_inner_mode. */
6121 int width = (GET_CODE (inner) == MEM
6122 ? GET_MODE_BITSIZE (is_mode)
6123 : GET_MODE_BITSIZE (wanted_inner_mode));
6126 pos = width - len - pos;
6129 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6130 GEN_INT (width - len), pos_rtx);
6131 /* POS may be less than 0 now, but we check for that below.
6132 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6135 /* If INNER has a wider mode, make it smaller. If this is a constant
6136 extract, try to adjust the byte to point to the byte containing
6138 if (wanted_inner_mode != VOIDmode
6139 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6140 && ((GET_CODE (inner) == MEM
6141 && (inner_mode == wanted_inner_mode
6142 || (! mode_dependent_address_p (XEXP (inner, 0))
6143 && ! MEM_VOLATILE_P (inner))))))
6147 /* The computations below will be correct if the machine is big
6148 endian in both bits and bytes or little endian in bits and bytes.
6149 If it is mixed, we must adjust. */
6151 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6152 adjust OFFSET to compensate. */
6153 if (BYTES_BIG_ENDIAN
6155 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6156 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6158 /* If this is a constant position, we can move to the desired byte. */
6161 offset += pos / BITS_PER_UNIT;
6162 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6165 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6167 && is_mode != wanted_inner_mode)
6168 offset = (GET_MODE_SIZE (is_mode)
6169 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6171 if (offset != 0 || inner_mode != wanted_inner_mode)
6173 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6174 plus_constant (XEXP (inner, 0), offset));
6176 MEM_COPY_ATTRIBUTES (newmem, inner);
6181 /* If INNER is not memory, we can always get it into the proper mode. If we
6182 are changing its mode, POS must be a constant and smaller than the size
6184 else if (GET_CODE (inner) != MEM)
6186 if (GET_MODE (inner) != wanted_inner_mode
6188 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6191 inner = force_to_mode (inner, wanted_inner_mode,
6193 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6194 ? ~(HOST_WIDE_INT) 0
6195 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6200 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6201 have to zero extend. Otherwise, we can just use a SUBREG. */
6203 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6205 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6207 /* If we know that no extraneous bits are set, and that the high
6208 bit is not set, convert extraction to cheaper one - eighter
6209 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6211 if (flag_expensive_optimizations
6212 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6213 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6214 & ~(((unsigned HOST_WIDE_INT)
6215 GET_MODE_MASK (GET_MODE (pos_rtx)))
6219 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6221 /* Preffer ZERO_EXTENSION, since it gives more information to
6223 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6228 else if (pos_rtx != 0
6229 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6230 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6232 /* Make POS_RTX unless we already have it and it is correct. If we don't
6233 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6235 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6236 pos_rtx = orig_pos_rtx;
6238 else if (pos_rtx == 0)
6239 pos_rtx = GEN_INT (pos);
6241 /* Make the required operation. See if we can use existing rtx. */
6242 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6243 extraction_mode, inner, GEN_INT (len), pos_rtx);
6245 new = gen_lowpart_for_combine (mode, new);
6250 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6251 with any other operations in X. Return X without that shift if so. */
6254 extract_left_shift (x, count)
6258 enum rtx_code code = GET_CODE (x);
6259 enum machine_mode mode = GET_MODE (x);
6265 /* This is the shift itself. If it is wide enough, we will return
6266 either the value being shifted if the shift count is equal to
6267 COUNT or a shift for the difference. */
6268 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6269 && INTVAL (XEXP (x, 1)) >= count)
6270 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6271 INTVAL (XEXP (x, 1)) - count);
6275 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6276 return gen_unary (code, mode, mode, tem);
6280 case PLUS: case IOR: case XOR: case AND:
6281 /* If we can safely shift this constant and we find the inner shift,
6282 make a new operation. */
6283 if (GET_CODE (XEXP (x,1)) == CONST_INT
6284 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6285 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6286 return gen_binary (code, mode, tem,
6287 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6298 /* Look at the expression rooted at X. Look for expressions
6299 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6300 Form these expressions.
6302 Return the new rtx, usually just X.
6304 Also, for machines like the Vax that don't have logical shift insns,
6305 try to convert logical to arithmetic shift operations in cases where
6306 they are equivalent. This undoes the canonicalizations to logical
6307 shifts done elsewhere.
6309 We try, as much as possible, to re-use rtl expressions to save memory.
6311 IN_CODE says what kind of expression we are processing. Normally, it is
6312 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6313 being kludges), it is MEM. When processing the arguments of a comparison
6314 or a COMPARE against zero, it is COMPARE. */
6317 make_compound_operation (x, in_code)
6319 enum rtx_code in_code;
6321 enum rtx_code code = GET_CODE (x);
6322 enum machine_mode mode = GET_MODE (x);
6323 int mode_width = GET_MODE_BITSIZE (mode);
6325 enum rtx_code next_code;
6331 /* Select the code to be used in recursive calls. Once we are inside an
6332 address, we stay there. If we have a comparison, set to COMPARE,
6333 but once inside, go back to our default of SET. */
6335 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6336 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6337 && XEXP (x, 1) == const0_rtx) ? COMPARE
6338 : in_code == COMPARE ? SET : in_code);
6340 /* Process depending on the code of this operation. If NEW is set
6341 non-zero, it will be returned. */
6346 /* Convert shifts by constants into multiplications if inside
6348 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6349 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6350 && INTVAL (XEXP (x, 1)) >= 0)
6352 new = make_compound_operation (XEXP (x, 0), next_code);
6353 new = gen_rtx_combine (MULT, mode, new,
6354 GEN_INT ((HOST_WIDE_INT) 1
6355 << INTVAL (XEXP (x, 1))));
6360 /* If the second operand is not a constant, we can't do anything
6362 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6365 /* If the constant is a power of two minus one and the first operand
6366 is a logical right shift, make an extraction. */
6367 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6368 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6370 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6371 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6372 0, in_code == COMPARE);
6375 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6376 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6377 && subreg_lowpart_p (XEXP (x, 0))
6378 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6379 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6381 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6383 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6384 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6385 0, in_code == COMPARE);
6387 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6388 else if ((GET_CODE (XEXP (x, 0)) == XOR
6389 || GET_CODE (XEXP (x, 0)) == IOR)
6390 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6391 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6392 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6394 /* Apply the distributive law, and then try to make extractions. */
6395 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6396 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6398 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6400 new = make_compound_operation (new, in_code);
6403 /* If we are have (and (rotate X C) M) and C is larger than the number
6404 of bits in M, this is an extraction. */
6406 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6407 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6408 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6409 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6411 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6412 new = make_extraction (mode, new,
6413 (GET_MODE_BITSIZE (mode)
6414 - INTVAL (XEXP (XEXP (x, 0), 1))),
6415 NULL_RTX, i, 1, 0, in_code == COMPARE);
6418 /* On machines without logical shifts, if the operand of the AND is
6419 a logical shift and our mask turns off all the propagated sign
6420 bits, we can replace the logical shift with an arithmetic shift. */
6421 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6422 && (lshr_optab->handlers[(int) mode].insn_code
6423 == CODE_FOR_nothing)
6424 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6425 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6426 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6427 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6428 && mode_width <= HOST_BITS_PER_WIDE_INT)
6430 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6432 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6433 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6435 gen_rtx_combine (ASHIFTRT, mode,
6436 make_compound_operation (XEXP (XEXP (x, 0), 0),
6438 XEXP (XEXP (x, 0), 1)));
6441 /* If the constant is one less than a power of two, this might be
6442 representable by an extraction even if no shift is present.
6443 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6444 we are in a COMPARE. */
6445 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6446 new = make_extraction (mode,
6447 make_compound_operation (XEXP (x, 0),
6449 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6451 /* If we are in a comparison and this is an AND with a power of two,
6452 convert this into the appropriate bit extract. */
6453 else if (in_code == COMPARE
6454 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6455 new = make_extraction (mode,
6456 make_compound_operation (XEXP (x, 0),
6458 i, NULL_RTX, 1, 1, 0, 1);
6463 /* If the sign bit is known to be zero, replace this with an
6464 arithmetic shift. */
6465 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6466 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6467 && mode_width <= HOST_BITS_PER_WIDE_INT
6468 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6470 new = gen_rtx_combine (ASHIFTRT, mode,
6471 make_compound_operation (XEXP (x, 0),
6477 /* ... fall through ... */
6483 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6484 this is a SIGN_EXTRACT. */
6485 if (GET_CODE (rhs) == CONST_INT
6486 && GET_CODE (lhs) == ASHIFT
6487 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6488 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6490 new = make_compound_operation (XEXP (lhs, 0), next_code);
6491 new = make_extraction (mode, new,
6492 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6493 NULL_RTX, mode_width - INTVAL (rhs),
6494 code == LSHIFTRT, 0, in_code == COMPARE);
6497 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6498 If so, try to merge the shifts into a SIGN_EXTEND. We could
6499 also do this for some cases of SIGN_EXTRACT, but it doesn't
6500 seem worth the effort; the case checked for occurs on Alpha. */
6502 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6503 && ! (GET_CODE (lhs) == SUBREG
6504 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6505 && GET_CODE (rhs) == CONST_INT
6506 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6507 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6508 new = make_extraction (mode, make_compound_operation (new, next_code),
6509 0, NULL_RTX, mode_width - INTVAL (rhs),
6510 code == LSHIFTRT, 0, in_code == COMPARE);
6515 /* Call ourselves recursively on the inner expression. If we are
6516 narrowing the object and it has a different RTL code from
6517 what it originally did, do this SUBREG as a force_to_mode. */
6519 tem = make_compound_operation (SUBREG_REG (x), in_code);
6520 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6521 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6522 && subreg_lowpart_p (x))
6524 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6527 /* If we have something other than a SUBREG, we might have
6528 done an expansion, so rerun outselves. */
6529 if (GET_CODE (newer) != SUBREG)
6530 newer = make_compound_operation (newer, in_code);
6535 /* If this is a paradoxical subreg, and the new code is a sign or
6536 zero extension, omit the subreg and widen the extension. If it
6537 is a regular subreg, we can still get rid of the subreg by not
6538 widening so much, or in fact removing the extension entirely. */
6539 if ((GET_CODE (tem) == SIGN_EXTEND
6540 || GET_CODE (tem) == ZERO_EXTEND)
6541 && subreg_lowpart_p (x))
6543 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6544 || (GET_MODE_SIZE (mode) >
6545 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6546 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6548 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6559 x = gen_lowpart_for_combine (mode, new);
6560 code = GET_CODE (x);
6563 /* Now recursively process each operand of this operation. */
6564 fmt = GET_RTX_FORMAT (code);
6565 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6568 new = make_compound_operation (XEXP (x, i), next_code);
6569 SUBST (XEXP (x, i), new);
6575 /* Given M see if it is a value that would select a field of bits
6576 within an item, but not the entire word. Return -1 if not.
6577 Otherwise, return the starting position of the field, where 0 is the
6580 *PLEN is set to the length of the field. */
6583 get_pos_from_mask (m, plen)
6584 unsigned HOST_WIDE_INT m;
6585 unsigned HOST_WIDE_INT *plen;
6587 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6588 int pos = exact_log2 (m & -m);
6594 /* Now shift off the low-order zero bits and see if we have a power of
6596 len = exact_log2 ((m >> pos) + 1);
6605 /* See if X can be simplified knowing that we will only refer to it in
6606 MODE and will only refer to those bits that are nonzero in MASK.
6607 If other bits are being computed or if masking operations are done
6608 that select a superset of the bits in MASK, they can sometimes be
6611 Return a possibly simplified expression, but always convert X to
6612 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6614 Also, if REG is non-zero and X is a register equal in value to REG,
6617 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6618 are all off in X. This is used when X will be complemented, by either
6619 NOT, NEG, or XOR. */
6622 force_to_mode (x, mode, mask, reg, just_select)
6624 enum machine_mode mode;
6625 unsigned HOST_WIDE_INT mask;
6629 enum rtx_code code = GET_CODE (x);
6630 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6631 enum machine_mode op_mode;
6632 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6635 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6636 code below will do the wrong thing since the mode of such an
6637 expression is VOIDmode.
6639 Also do nothing if X is a CLOBBER; this can happen if X was
6640 the return value from a call to gen_lowpart_for_combine. */
6641 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6644 /* We want to perform the operation is its present mode unless we know
6645 that the operation is valid in MODE, in which case we do the operation
6647 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6648 && code_to_optab[(int) code] != 0
6649 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6650 != CODE_FOR_nothing))
6651 ? mode : GET_MODE (x));
6653 /* It is not valid to do a right-shift in a narrower mode
6654 than the one it came in with. */
6655 if ((code == LSHIFTRT || code == ASHIFTRT)
6656 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6657 op_mode = GET_MODE (x);
6659 /* Truncate MASK to fit OP_MODE. */
6661 mask &= GET_MODE_MASK (op_mode);
6663 /* When we have an arithmetic operation, or a shift whose count we
6664 do not know, we need to assume that all bit the up to the highest-order
6665 bit in MASK will be needed. This is how we form such a mask. */
6667 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6668 ? GET_MODE_MASK (op_mode)
6669 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6672 fuller_mask = ~(HOST_WIDE_INT) 0;
6674 /* Determine what bits of X are guaranteed to be (non)zero. */
6675 nonzero = nonzero_bits (x, mode);
6677 /* If none of the bits in X are needed, return a zero. */
6678 if (! just_select && (nonzero & mask) == 0)
6681 /* If X is a CONST_INT, return a new one. Do this here since the
6682 test below will fail. */
6683 if (GET_CODE (x) == CONST_INT)
6685 HOST_WIDE_INT cval = INTVAL (x) & mask;
6686 int width = GET_MODE_BITSIZE (mode);
6688 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6689 number, sign extend it. */
6690 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6691 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6692 cval |= (HOST_WIDE_INT) -1 << width;
6694 return GEN_INT (cval);
6697 /* If X is narrower than MODE and we want all the bits in X's mode, just
6698 get X in the proper mode. */
6699 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6700 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6701 return gen_lowpart_for_combine (mode, x);
6703 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6704 MASK are already known to be zero in X, we need not do anything. */
6705 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6711 /* If X is a (clobber (const_int)), return it since we know we are
6712 generating something that won't match. */
6716 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6717 spanned the boundary of the MEM. If we are now masking so it is
6718 within that boundary, we don't need the USE any more. */
6719 if (! BITS_BIG_ENDIAN
6720 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6721 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6728 x = expand_compound_operation (x);
6729 if (GET_CODE (x) != code)
6730 return force_to_mode (x, mode, mask, reg, next_select);
6734 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6735 || rtx_equal_p (reg, get_last_value (x))))
6740 if (subreg_lowpart_p (x)
6741 /* We can ignore the effect of this SUBREG if it narrows the mode or
6742 if the constant masks to zero all the bits the mode doesn't
6744 && ((GET_MODE_SIZE (GET_MODE (x))
6745 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6747 & GET_MODE_MASK (GET_MODE (x))
6748 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6749 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6753 /* If this is an AND with a constant, convert it into an AND
6754 whose constant is the AND of that constant with MASK. If it
6755 remains an AND of MASK, delete it since it is redundant. */
6757 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6759 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6760 mask & INTVAL (XEXP (x, 1)));
6762 /* If X is still an AND, see if it is an AND with a mask that
6763 is just some low-order bits. If so, and it is MASK, we don't
6766 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6767 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6770 /* If it remains an AND, try making another AND with the bits
6771 in the mode mask that aren't in MASK turned on. If the
6772 constant in the AND is wide enough, this might make a
6773 cheaper constant. */
6775 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6776 && GET_MODE_MASK (GET_MODE (x)) != mask
6777 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6779 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6780 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6781 int width = GET_MODE_BITSIZE (GET_MODE (x));
6784 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6785 number, sign extend it. */
6786 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6787 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6788 cval |= (HOST_WIDE_INT) -1 << width;
6790 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6791 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6801 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6802 low-order bits (as in an alignment operation) and FOO is already
6803 aligned to that boundary, mask C1 to that boundary as well.
6804 This may eliminate that PLUS and, later, the AND. */
6807 unsigned int width = GET_MODE_BITSIZE (mode);
6808 unsigned HOST_WIDE_INT smask = mask;
6810 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6811 number, sign extend it. */
6813 if (width < HOST_BITS_PER_WIDE_INT
6814 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6815 smask |= (HOST_WIDE_INT) -1 << width;
6817 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6818 && exact_log2 (- smask) >= 0)
6822 && (XEXP (x, 0) == stack_pointer_rtx
6823 || XEXP (x, 0) == frame_pointer_rtx))
6825 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6826 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6828 sp_mask &= ~(sp_alignment - 1);
6829 if ((sp_mask & ~smask) == 0
6830 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
6831 return force_to_mode (plus_constant (XEXP (x, 0),
6832 ((INTVAL (XEXP (x, 1)) -
6833 STACK_BIAS) & smask)
6835 mode, smask, reg, next_select);
6838 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6839 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6840 return force_to_mode (plus_constant (XEXP (x, 0),
6841 (INTVAL (XEXP (x, 1))
6843 mode, smask, reg, next_select);
6847 /* ... fall through ... */
6850 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6851 most significant bit in MASK since carries from those bits will
6852 affect the bits we are interested in. */
6857 /* If X is (minus C Y) where C's least set bit is larger than any bit
6858 in the mask, then we may replace with (neg Y). */
6859 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6860 && (INTVAL (XEXP (x, 0)) & -INTVAL (XEXP (x, 0))) > mask)
6862 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6863 return force_to_mode (x, mode, mask, reg, next_select);
6866 /* Similarly, if C contains every bit in the mask, then we may
6867 replace with (not Y). */
6868 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6869 && (INTVAL (XEXP (x, 0)) | mask) == INTVAL (XEXP (x, 0)))
6871 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6872 return force_to_mode (x, mode, mask, reg, next_select);
6880 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6881 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6882 operation which may be a bitfield extraction. Ensure that the
6883 constant we form is not wider than the mode of X. */
6885 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6886 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6887 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6888 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6889 && GET_CODE (XEXP (x, 1)) == CONST_INT
6890 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6891 + floor_log2 (INTVAL (XEXP (x, 1))))
6892 < GET_MODE_BITSIZE (GET_MODE (x)))
6893 && (INTVAL (XEXP (x, 1))
6894 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6896 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6897 << INTVAL (XEXP (XEXP (x, 0), 1)));
6898 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6899 XEXP (XEXP (x, 0), 0), temp);
6900 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6901 XEXP (XEXP (x, 0), 1));
6902 return force_to_mode (x, mode, mask, reg, next_select);
6906 /* For most binary operations, just propagate into the operation and
6907 change the mode if we have an operation of that mode. */
6909 op0 = gen_lowpart_for_combine (op_mode,
6910 force_to_mode (XEXP (x, 0), mode, mask,
6912 op1 = gen_lowpart_for_combine (op_mode,
6913 force_to_mode (XEXP (x, 1), mode, mask,
6916 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6917 MASK since OP1 might have been sign-extended but we never want
6918 to turn on extra bits, since combine might have previously relied
6919 on them being off. */
6920 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6921 && (INTVAL (op1) & mask) != 0)
6922 op1 = GEN_INT (INTVAL (op1) & mask);
6924 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6925 x = gen_binary (code, op_mode, op0, op1);
6929 /* For left shifts, do the same, but just for the first operand.
6930 However, we cannot do anything with shifts where we cannot
6931 guarantee that the counts are smaller than the size of the mode
6932 because such a count will have a different meaning in a
6935 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6936 && INTVAL (XEXP (x, 1)) >= 0
6937 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6938 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6939 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6940 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6943 /* If the shift count is a constant and we can do arithmetic in
6944 the mode of the shift, refine which bits we need. Otherwise, use the
6945 conservative form of the mask. */
6946 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6947 && INTVAL (XEXP (x, 1)) >= 0
6948 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6949 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6950 mask >>= INTVAL (XEXP (x, 1));
6954 op0 = gen_lowpart_for_combine (op_mode,
6955 force_to_mode (XEXP (x, 0), op_mode,
6956 mask, reg, next_select));
6958 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6959 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6963 /* Here we can only do something if the shift count is a constant,
6964 this shift constant is valid for the host, and we can do arithmetic
6967 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6968 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6969 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6971 rtx inner = XEXP (x, 0);
6972 unsigned HOST_WIDE_INT inner_mask;
6974 /* Select the mask of the bits we need for the shift operand. */
6975 inner_mask = mask << INTVAL (XEXP (x, 1));
6977 /* We can only change the mode of the shift if we can do arithmetic
6978 in the mode of the shift and INNER_MASK is no wider than the
6979 width of OP_MODE. */
6980 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6981 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6982 op_mode = GET_MODE (x);
6984 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6986 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6987 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6990 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6991 shift and AND produces only copies of the sign bit (C2 is one less
6992 than a power of two), we can do this with just a shift. */
6994 if (GET_CODE (x) == LSHIFTRT
6995 && GET_CODE (XEXP (x, 1)) == CONST_INT
6996 /* The shift puts one of the sign bit copies in the least significant
6998 && ((INTVAL (XEXP (x, 1))
6999 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7000 >= GET_MODE_BITSIZE (GET_MODE (x)))
7001 && exact_log2 (mask + 1) >= 0
7002 /* Number of bits left after the shift must be more than the mask
7004 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7005 <= GET_MODE_BITSIZE (GET_MODE (x)))
7006 /* Must be more sign bit copies than the mask needs. */
7007 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7008 >= exact_log2 (mask + 1)))
7009 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7010 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7011 - exact_log2 (mask + 1)));
7016 /* If we are just looking for the sign bit, we don't need this shift at
7017 all, even if it has a variable count. */
7018 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7019 && (mask == ((unsigned HOST_WIDE_INT) 1
7020 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7021 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7023 /* If this is a shift by a constant, get a mask that contains those bits
7024 that are not copies of the sign bit. We then have two cases: If
7025 MASK only includes those bits, this can be a logical shift, which may
7026 allow simplifications. If MASK is a single-bit field not within
7027 those bits, we are requesting a copy of the sign bit and hence can
7028 shift the sign bit to the appropriate location. */
7030 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7031 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7035 /* If the considered data is wider then HOST_WIDE_INT, we can't
7036 represent a mask for all its bits in a single scalar.
7037 But we only care about the lower bits, so calculate these. */
7039 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7041 nonzero = ~(HOST_WIDE_INT) 0;
7043 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7044 is the number of bits a full-width mask would have set.
7045 We need only shift if these are fewer than nonzero can
7046 hold. If not, we must keep all bits set in nonzero. */
7048 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7049 < HOST_BITS_PER_WIDE_INT)
7050 nonzero >>= INTVAL (XEXP (x, 1))
7051 + HOST_BITS_PER_WIDE_INT
7052 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7056 nonzero = GET_MODE_MASK (GET_MODE (x));
7057 nonzero >>= INTVAL (XEXP (x, 1));
7060 if ((mask & ~nonzero) == 0
7061 || (i = exact_log2 (mask)) >= 0)
7063 x = simplify_shift_const
7064 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7065 i < 0 ? INTVAL (XEXP (x, 1))
7066 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7068 if (GET_CODE (x) != ASHIFTRT)
7069 return force_to_mode (x, mode, mask, reg, next_select);
7073 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7074 even if the shift count isn't a constant. */
7076 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7080 /* If this is a zero- or sign-extension operation that just affects bits
7081 we don't care about, remove it. Be sure the call above returned
7082 something that is still a shift. */
7084 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7085 && GET_CODE (XEXP (x, 1)) == CONST_INT
7086 && INTVAL (XEXP (x, 1)) >= 0
7087 && (INTVAL (XEXP (x, 1))
7088 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7089 && GET_CODE (XEXP (x, 0)) == ASHIFT
7090 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7091 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7092 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7099 /* If the shift count is constant and we can do computations
7100 in the mode of X, compute where the bits we care about are.
7101 Otherwise, we can't do anything. Don't change the mode of
7102 the shift or propagate MODE into the shift, though. */
7103 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7104 && INTVAL (XEXP (x, 1)) >= 0)
7106 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7107 GET_MODE (x), GEN_INT (mask),
7109 if (temp && GET_CODE(temp) == CONST_INT)
7111 force_to_mode (XEXP (x, 0), GET_MODE (x),
7112 INTVAL (temp), reg, next_select));
7117 /* If we just want the low-order bit, the NEG isn't needed since it
7118 won't change the low-order bit. */
7120 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7122 /* We need any bits less significant than the most significant bit in
7123 MASK since carries from those bits will affect the bits we are
7129 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7130 same as the XOR case above. Ensure that the constant we form is not
7131 wider than the mode of X. */
7133 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7134 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7135 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7136 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7137 < GET_MODE_BITSIZE (GET_MODE (x)))
7138 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7140 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7141 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7142 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7144 return force_to_mode (x, mode, mask, reg, next_select);
7147 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7148 use the full mask inside the NOT. */
7152 op0 = gen_lowpart_for_combine (op_mode,
7153 force_to_mode (XEXP (x, 0), mode, mask,
7155 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7156 x = gen_unary (code, op_mode, op_mode, op0);
7160 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7161 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7162 which is equal to STORE_FLAG_VALUE. */
7163 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7164 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7165 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7166 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7171 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7172 written in a narrower mode. We play it safe and do not do so. */
7175 gen_lowpart_for_combine (GET_MODE (x),
7176 force_to_mode (XEXP (x, 1), mode,
7177 mask, reg, next_select)));
7179 gen_lowpart_for_combine (GET_MODE (x),
7180 force_to_mode (XEXP (x, 2), mode,
7181 mask, reg,next_select)));
7188 /* Ensure we return a value of the proper mode. */
7189 return gen_lowpart_for_combine (mode, x);
7192 /* Return nonzero if X is an expression that has one of two values depending on
7193 whether some other value is zero or nonzero. In that case, we return the
7194 value that is being tested, *PTRUE is set to the value if the rtx being
7195 returned has a nonzero value, and *PFALSE is set to the other alternative.
7197 If we return zero, we set *PTRUE and *PFALSE to X. */
7200 if_then_else_cond (x, ptrue, pfalse)
7202 rtx *ptrue, *pfalse;
7204 enum machine_mode mode = GET_MODE (x);
7205 enum rtx_code code = GET_CODE (x);
7206 rtx cond0, cond1, true0, true1, false0, false1;
7207 unsigned HOST_WIDE_INT nz;
7209 /* If we are comparing a value against zero, we are done. */
7210 if ((code == NE || code == EQ)
7211 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7213 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7214 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7218 /* If this is a unary operation whose operand has one of two values, apply
7219 our opcode to compute those values. */
7220 else if (GET_RTX_CLASS (code) == '1'
7221 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7223 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7224 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7228 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7229 make can't possibly match and would suppress other optimizations. */
7230 else if (code == COMPARE)
7233 /* If this is a binary operation, see if either side has only one of two
7234 values. If either one does or if both do and they are conditional on
7235 the same value, compute the new true and false values. */
7236 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7237 || GET_RTX_CLASS (code) == '<')
7239 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7240 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7242 if ((cond0 != 0 || cond1 != 0)
7243 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7245 /* If if_then_else_cond returned zero, then true/false are the
7246 same rtl. We must copy one of them to prevent invalid rtl
7249 true0 = copy_rtx (true0);
7250 else if (cond1 == 0)
7251 true1 = copy_rtx (true1);
7253 *ptrue = gen_binary (code, mode, true0, true1);
7254 *pfalse = gen_binary (code, mode, false0, false1);
7255 return cond0 ? cond0 : cond1;
7258 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7259 operands is zero when the other is non-zero, and vice-versa,
7260 and STORE_FLAG_VALUE is 1 or -1. */
7262 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7263 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7265 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7267 rtx op0 = XEXP (XEXP (x, 0), 1);
7268 rtx op1 = XEXP (XEXP (x, 1), 1);
7270 cond0 = XEXP (XEXP (x, 0), 0);
7271 cond1 = XEXP (XEXP (x, 1), 0);
7273 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7274 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7275 && reversible_comparison_p (cond1)
7276 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7277 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7278 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7279 || ((swap_condition (GET_CODE (cond0))
7280 == reverse_condition (GET_CODE (cond1)))
7281 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7282 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7283 && ! side_effects_p (x))
7285 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7286 *pfalse = gen_binary (MULT, mode,
7288 ? gen_unary (NEG, mode, mode, op1) : op1),
7294 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7296 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7297 && (code == MULT || code == AND || code == UMIN)
7298 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7300 cond0 = XEXP (XEXP (x, 0), 0);
7301 cond1 = XEXP (XEXP (x, 1), 0);
7303 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7304 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7305 && reversible_comparison_p (cond1)
7306 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
7307 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7308 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7309 || ((swap_condition (GET_CODE (cond0))
7310 == reverse_condition (GET_CODE (cond1)))
7311 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7312 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7313 && ! side_effects_p (x))
7315 *ptrue = *pfalse = const0_rtx;
7321 else if (code == IF_THEN_ELSE)
7323 /* If we have IF_THEN_ELSE already, extract the condition and
7324 canonicalize it if it is NE or EQ. */
7325 cond0 = XEXP (x, 0);
7326 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7327 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7328 return XEXP (cond0, 0);
7329 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7331 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7332 return XEXP (cond0, 0);
7338 /* If X is a normal SUBREG with both inner and outer modes integral,
7339 we can narrow both the true and false values of the inner expression,
7340 if there is a condition. */
7341 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7342 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7343 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7344 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7347 if ((GET_CODE (SUBREG_REG (x)) == REG
7348 || GET_CODE (SUBREG_REG (x)) == MEM
7349 || CONSTANT_P (SUBREG_REG (x)))
7350 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7351 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7353 true0 = operand_subword (true0, SUBREG_WORD (x), 0, mode);
7354 false0 = operand_subword (false0, SUBREG_WORD (x), 0, mode);
7356 *ptrue = force_to_mode (true0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7358 = force_to_mode (false0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7363 /* If X is a constant, this isn't special and will cause confusions
7364 if we treat it as such. Likewise if it is equivalent to a constant. */
7365 else if (CONSTANT_P (x)
7366 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7369 /* If X is known to be either 0 or -1, those are the true and
7370 false values when testing X. */
7371 else if (x == constm1_rtx || x == const0_rtx
7372 || (mode != VOIDmode
7373 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7375 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7379 /* Likewise for 0 or a single bit. */
7380 else if (mode != VOIDmode
7381 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7382 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7384 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7388 /* Otherwise fail; show no condition with true and false values the same. */
7389 *ptrue = *pfalse = x;
7393 /* Return the value of expression X given the fact that condition COND
7394 is known to be true when applied to REG as its first operand and VAL
7395 as its second. X is known to not be shared and so can be modified in
7398 We only handle the simplest cases, and specifically those cases that
7399 arise with IF_THEN_ELSE expressions. */
7402 known_cond (x, cond, reg, val)
7407 enum rtx_code code = GET_CODE (x);
7412 if (side_effects_p (x))
7415 if (cond == EQ && rtx_equal_p (x, reg))
7418 /* If X is (abs REG) and we know something about REG's relationship
7419 with zero, we may be able to simplify this. */
7421 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7424 case GE: case GT: case EQ:
7427 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7433 /* The only other cases we handle are MIN, MAX, and comparisons if the
7434 operands are the same as REG and VAL. */
7436 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7438 if (rtx_equal_p (XEXP (x, 0), val))
7439 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7441 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7443 if (GET_RTX_CLASS (code) == '<')
7445 if (comparison_dominates_p (cond, code))
7446 return const_true_rtx;
7448 code = reverse_condition (code);
7450 && comparison_dominates_p (cond, code))
7455 else if (code == SMAX || code == SMIN
7456 || code == UMIN || code == UMAX)
7458 int unsignedp = (code == UMIN || code == UMAX);
7460 if (code == SMAX || code == UMAX)
7461 cond = reverse_condition (cond);
7466 return unsignedp ? x : XEXP (x, 1);
7468 return unsignedp ? x : XEXP (x, 0);
7470 return unsignedp ? XEXP (x, 1) : x;
7472 return unsignedp ? XEXP (x, 0) : x;
7480 fmt = GET_RTX_FORMAT (code);
7481 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7484 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7485 else if (fmt[i] == 'E')
7486 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7487 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7494 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7495 assignment as a field assignment. */
7498 rtx_equal_for_field_assignment_p (x, y)
7502 if (x == y || rtx_equal_p (x, y))
7505 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7508 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7509 Note that all SUBREGs of MEM are paradoxical; otherwise they
7510 would have been rewritten. */
7511 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7512 && GET_CODE (SUBREG_REG (y)) == MEM
7513 && rtx_equal_p (SUBREG_REG (y),
7514 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7517 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7518 && GET_CODE (SUBREG_REG (x)) == MEM
7519 && rtx_equal_p (SUBREG_REG (x),
7520 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7523 /* We used to see if get_last_value of X and Y were the same but that's
7524 not correct. In one direction, we'll cause the assignment to have
7525 the wrong destination and in the case, we'll import a register into this
7526 insn that might have already have been dead. So fail if none of the
7527 above cases are true. */
7531 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7532 Return that assignment if so.
7534 We only handle the most common cases. */
7537 make_field_assignment (x)
7540 rtx dest = SET_DEST (x);
7541 rtx src = SET_SRC (x);
7546 unsigned HOST_WIDE_INT len;
7548 enum machine_mode mode;
7550 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7551 a clear of a one-bit field. We will have changed it to
7552 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7555 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7556 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7557 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7558 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7560 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7563 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7567 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7568 && subreg_lowpart_p (XEXP (src, 0))
7569 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7570 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7571 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7572 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7573 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7575 assign = make_extraction (VOIDmode, dest, 0,
7576 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7579 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7583 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7585 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7586 && XEXP (XEXP (src, 0), 0) == const1_rtx
7587 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7589 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7592 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7596 /* The other case we handle is assignments into a constant-position
7597 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7598 a mask that has all one bits except for a group of zero bits and
7599 OTHER is known to have zeros where C1 has ones, this is such an
7600 assignment. Compute the position and length from C1. Shift OTHER
7601 to the appropriate position, force it to the required mode, and
7602 make the extraction. Check for the AND in both operands. */
7604 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7607 rhs = expand_compound_operation (XEXP (src, 0));
7608 lhs = expand_compound_operation (XEXP (src, 1));
7610 if (GET_CODE (rhs) == AND
7611 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7612 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7613 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7614 else if (GET_CODE (lhs) == AND
7615 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7616 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7617 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7621 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7622 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7623 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7624 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7627 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7631 /* The mode to use for the source is the mode of the assignment, or of
7632 what is inside a possible STRICT_LOW_PART. */
7633 mode = (GET_CODE (assign) == STRICT_LOW_PART
7634 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7636 /* Shift OTHER right POS places and make it the source, restricting it
7637 to the proper length and mode. */
7639 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7640 GET_MODE (src), other, pos),
7642 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7643 ? ~(HOST_WIDE_INT) 0
7644 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7647 return gen_rtx_combine (SET, VOIDmode, assign, src);
7650 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7654 apply_distributive_law (x)
7657 enum rtx_code code = GET_CODE (x);
7658 rtx lhs, rhs, other;
7660 enum rtx_code inner_code;
7662 /* Distributivity is not true for floating point.
7663 It can change the value. So don't do it.
7664 -- rms and moshier@world.std.com. */
7665 if (FLOAT_MODE_P (GET_MODE (x)))
7668 /* The outer operation can only be one of the following: */
7669 if (code != IOR && code != AND && code != XOR
7670 && code != PLUS && code != MINUS)
7673 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7675 /* If either operand is a primitive we can't do anything, so get out
7677 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7678 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7681 lhs = expand_compound_operation (lhs);
7682 rhs = expand_compound_operation (rhs);
7683 inner_code = GET_CODE (lhs);
7684 if (inner_code != GET_CODE (rhs))
7687 /* See if the inner and outer operations distribute. */
7694 /* These all distribute except over PLUS. */
7695 if (code == PLUS || code == MINUS)
7700 if (code != PLUS && code != MINUS)
7705 /* This is also a multiply, so it distributes over everything. */
7709 /* Non-paradoxical SUBREGs distributes over all operations, provided
7710 the inner modes and word numbers are the same, this is an extraction
7711 of a low-order part, we don't convert an fp operation to int or
7712 vice versa, and we would not be converting a single-word
7713 operation into a multi-word operation. The latter test is not
7714 required, but it prevents generating unneeded multi-word operations.
7715 Some of the previous tests are redundant given the latter test, but
7716 are retained because they are required for correctness.
7718 We produce the result slightly differently in this case. */
7720 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7721 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7722 || ! subreg_lowpart_p (lhs)
7723 || (GET_MODE_CLASS (GET_MODE (lhs))
7724 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7725 || (GET_MODE_SIZE (GET_MODE (lhs))
7726 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7727 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7730 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7731 SUBREG_REG (lhs), SUBREG_REG (rhs));
7732 return gen_lowpart_for_combine (GET_MODE (x), tem);
7738 /* Set LHS and RHS to the inner operands (A and B in the example
7739 above) and set OTHER to the common operand (C in the example).
7740 These is only one way to do this unless the inner operation is
7742 if (GET_RTX_CLASS (inner_code) == 'c'
7743 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7744 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7745 else if (GET_RTX_CLASS (inner_code) == 'c'
7746 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7747 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7748 else if (GET_RTX_CLASS (inner_code) == 'c'
7749 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7750 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7751 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7752 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7756 /* Form the new inner operation, seeing if it simplifies first. */
7757 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7759 /* There is one exception to the general way of distributing:
7760 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7761 if (code == XOR && inner_code == IOR)
7764 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7767 /* We may be able to continuing distributing the result, so call
7768 ourselves recursively on the inner operation before forming the
7769 outer operation, which we return. */
7770 return gen_binary (inner_code, GET_MODE (x),
7771 apply_distributive_law (tem), other);
7774 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7777 Return an equivalent form, if different from X. Otherwise, return X. If
7778 X is zero, we are to always construct the equivalent form. */
7781 simplify_and_const_int (x, mode, varop, constop)
7783 enum machine_mode mode;
7785 unsigned HOST_WIDE_INT constop;
7787 unsigned HOST_WIDE_INT nonzero;
7790 /* Simplify VAROP knowing that we will be only looking at some of the
7792 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7794 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7795 CONST_INT, we are done. */
7796 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7799 /* See what bits may be nonzero in VAROP. Unlike the general case of
7800 a call to nonzero_bits, here we don't care about bits outside
7803 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7804 nonzero = trunc_int_for_mode (nonzero, mode);
7806 /* Turn off all bits in the constant that are known to already be zero.
7807 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7808 which is tested below. */
7812 /* If we don't have any bits left, return zero. */
7816 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7817 a power of two, we can replace this with a ASHIFT. */
7818 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7819 && (i = exact_log2 (constop)) >= 0)
7820 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7822 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7823 or XOR, then try to apply the distributive law. This may eliminate
7824 operations if either branch can be simplified because of the AND.
7825 It may also make some cases more complex, but those cases probably
7826 won't match a pattern either with or without this. */
7828 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7830 gen_lowpart_for_combine
7832 apply_distributive_law
7833 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7834 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7835 XEXP (varop, 0), constop),
7836 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7837 XEXP (varop, 1), constop))));
7839 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7840 if we already had one (just check for the simplest cases). */
7841 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7842 && GET_MODE (XEXP (x, 0)) == mode
7843 && SUBREG_REG (XEXP (x, 0)) == varop)
7844 varop = XEXP (x, 0);
7846 varop = gen_lowpart_for_combine (mode, varop);
7848 /* If we can't make the SUBREG, try to return what we were given. */
7849 if (GET_CODE (varop) == CLOBBER)
7850 return x ? x : varop;
7852 /* If we are only masking insignificant bits, return VAROP. */
7853 if (constop == nonzero)
7856 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7857 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7858 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7862 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7863 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7864 SUBST (XEXP (x, 1), GEN_INT (constop));
7866 SUBST (XEXP (x, 0), varop);
7872 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7873 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7874 is less useful. We can't allow both, because that results in exponential
7875 run time recursion. There is a nullstone testcase that triggered
7876 this. This macro avoids accidental uses of num_sign_bit_copies. */
7877 #define num_sign_bit_copies()
7879 /* Given an expression, X, compute which bits in X can be non-zero.
7880 We don't care about bits outside of those defined in MODE.
7882 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7883 a shift, AND, or zero_extract, we can do better. */
7885 static unsigned HOST_WIDE_INT
7886 nonzero_bits (x, mode)
7888 enum machine_mode mode;
7890 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7891 unsigned HOST_WIDE_INT inner_nz;
7893 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7896 /* For floating-point values, assume all bits are needed. */
7897 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7900 /* If X is wider than MODE, use its mode instead. */
7901 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7903 mode = GET_MODE (x);
7904 nonzero = GET_MODE_MASK (mode);
7905 mode_width = GET_MODE_BITSIZE (mode);
7908 if (mode_width > HOST_BITS_PER_WIDE_INT)
7909 /* Our only callers in this case look for single bit values. So
7910 just return the mode mask. Those tests will then be false. */
7913 #ifndef WORD_REGISTER_OPERATIONS
7914 /* If MODE is wider than X, but both are a single word for both the host
7915 and target machines, we can compute this from which bits of the
7916 object might be nonzero in its own mode, taking into account the fact
7917 that on many CISC machines, accessing an object in a wider mode
7918 causes the high-order bits to become undefined. So they are
7919 not known to be zero. */
7921 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7922 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7923 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7924 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7926 nonzero &= nonzero_bits (x, GET_MODE (x));
7927 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
7932 code = GET_CODE (x);
7936 #ifdef POINTERS_EXTEND_UNSIGNED
7937 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7938 all the bits above ptr_mode are known to be zero. */
7939 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7940 && REGNO_POINTER_FLAG (REGNO (x)))
7941 nonzero &= GET_MODE_MASK (ptr_mode);
7944 #ifdef STACK_BOUNDARY
7945 /* If this is the stack pointer, we may know something about its
7946 alignment. If PUSH_ROUNDING is defined, it is possible for the
7947 stack to be momentarily aligned only to that amount, so we pick
7948 the least alignment. */
7950 /* We can't check for arg_pointer_rtx here, because it is not
7951 guaranteed to have as much alignment as the stack pointer.
7952 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7953 alignment but the argument pointer has only 64 bit alignment. */
7955 if ((x == frame_pointer_rtx
7956 || x == stack_pointer_rtx
7957 || x == hard_frame_pointer_rtx
7958 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7959 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7965 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7967 #ifdef PUSH_ROUNDING
7968 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
7969 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7972 /* We must return here, otherwise we may get a worse result from
7973 one of the choices below. There is nothing useful below as
7974 far as the stack pointer is concerned. */
7975 return nonzero &= ~(sp_alignment - 1);
7979 /* If X is a register whose nonzero bits value is current, use it.
7980 Otherwise, if X is a register whose value we can find, use that
7981 value. Otherwise, use the previously-computed global nonzero bits
7982 for this register. */
7984 if (reg_last_set_value[REGNO (x)] != 0
7985 && reg_last_set_mode[REGNO (x)] == mode
7986 && (reg_last_set_label[REGNO (x)] == label_tick
7987 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7988 && REG_N_SETS (REGNO (x)) == 1
7989 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7991 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7992 return reg_last_set_nonzero_bits[REGNO (x)];
7994 tem = get_last_value (x);
7998 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7999 /* If X is narrower than MODE and TEM is a non-negative
8000 constant that would appear negative in the mode of X,
8001 sign-extend it for use in reg_nonzero_bits because some
8002 machines (maybe most) will actually do the sign-extension
8003 and this is the conservative approach.
8005 ??? For 2.5, try to tighten up the MD files in this regard
8006 instead of this kludge. */
8008 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8009 && GET_CODE (tem) == CONST_INT
8011 && 0 != (INTVAL (tem)
8012 & ((HOST_WIDE_INT) 1
8013 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8014 tem = GEN_INT (INTVAL (tem)
8015 | ((HOST_WIDE_INT) (-1)
8016 << GET_MODE_BITSIZE (GET_MODE (x))));
8018 return nonzero_bits (tem, mode);
8020 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8021 return reg_nonzero_bits[REGNO (x)] & nonzero;
8026 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8027 /* If X is negative in MODE, sign-extend the value. */
8028 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8029 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8030 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8036 #ifdef LOAD_EXTEND_OP
8037 /* In many, if not most, RISC machines, reading a byte from memory
8038 zeros the rest of the register. Noticing that fact saves a lot
8039 of extra zero-extends. */
8040 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8041 nonzero &= GET_MODE_MASK (GET_MODE (x));
8051 /* If this produces an integer result, we know which bits are set.
8052 Code here used to clear bits outside the mode of X, but that is
8055 if (GET_MODE_CLASS (mode) == MODE_INT
8056 && mode_width <= HOST_BITS_PER_WIDE_INT)
8057 nonzero = STORE_FLAG_VALUE;
8062 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8063 and num_sign_bit_copies. */
8064 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8065 == GET_MODE_BITSIZE (GET_MODE (x)))
8069 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8070 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8075 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8076 and num_sign_bit_copies. */
8077 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8078 == GET_MODE_BITSIZE (GET_MODE (x)))
8084 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8088 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8089 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8090 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8094 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8095 Otherwise, show all the bits in the outer mode but not the inner
8097 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8098 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8100 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8102 & (((HOST_WIDE_INT) 1
8103 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8104 inner_nz |= (GET_MODE_MASK (mode)
8105 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8108 nonzero &= inner_nz;
8112 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8113 & nonzero_bits (XEXP (x, 1), mode));
8117 case UMIN: case UMAX: case SMIN: case SMAX:
8118 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8119 | nonzero_bits (XEXP (x, 1), mode));
8122 case PLUS: case MINUS:
8124 case DIV: case UDIV:
8125 case MOD: case UMOD:
8126 /* We can apply the rules of arithmetic to compute the number of
8127 high- and low-order zero bits of these operations. We start by
8128 computing the width (position of the highest-order non-zero bit)
8129 and the number of low-order zero bits for each value. */
8131 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8132 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8133 int width0 = floor_log2 (nz0) + 1;
8134 int width1 = floor_log2 (nz1) + 1;
8135 int low0 = floor_log2 (nz0 & -nz0);
8136 int low1 = floor_log2 (nz1 & -nz1);
8137 HOST_WIDE_INT op0_maybe_minusp
8138 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8139 HOST_WIDE_INT op1_maybe_minusp
8140 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8141 unsigned int result_width = mode_width;
8149 && (XEXP (x, 0) == stack_pointer_rtx
8150 || XEXP (x, 0) == frame_pointer_rtx)
8151 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8153 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8155 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
8156 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8157 width0 = floor_log2 (nz0) + 1;
8158 width1 = floor_log2 (nz1) + 1;
8159 low0 = floor_log2 (nz0 & -nz0);
8160 low1 = floor_log2 (nz1 & -nz1);
8163 result_width = MAX (width0, width1) + 1;
8164 result_low = MIN (low0, low1);
8167 result_low = MIN (low0, low1);
8170 result_width = width0 + width1;
8171 result_low = low0 + low1;
8174 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8175 result_width = width0;
8178 result_width = width0;
8181 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8182 result_width = MIN (width0, width1);
8183 result_low = MIN (low0, low1);
8186 result_width = MIN (width0, width1);
8187 result_low = MIN (low0, low1);
8193 if (result_width < mode_width)
8194 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8197 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8202 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8203 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8204 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8208 /* If this is a SUBREG formed for a promoted variable that has
8209 been zero-extended, we know that at least the high-order bits
8210 are zero, though others might be too. */
8212 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8213 nonzero = (GET_MODE_MASK (GET_MODE (x))
8214 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8216 /* If the inner mode is a single word for both the host and target
8217 machines, we can compute this from which bits of the inner
8218 object might be nonzero. */
8219 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8220 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8221 <= HOST_BITS_PER_WIDE_INT))
8223 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8225 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8226 /* If this is a typical RISC machine, we only have to worry
8227 about the way loads are extended. */
8228 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8230 & (((unsigned HOST_WIDE_INT) 1
8231 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8233 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8236 /* On many CISC machines, accessing an object in a wider mode
8237 causes the high-order bits to become undefined. So they are
8238 not known to be zero. */
8239 if (GET_MODE_SIZE (GET_MODE (x))
8240 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8241 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8242 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8251 /* The nonzero bits are in two classes: any bits within MODE
8252 that aren't in GET_MODE (x) are always significant. The rest of the
8253 nonzero bits are those that are significant in the operand of
8254 the shift when shifted the appropriate number of bits. This
8255 shows that high-order bits are cleared by the right shift and
8256 low-order bits by left shifts. */
8257 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8258 && INTVAL (XEXP (x, 1)) >= 0
8259 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8261 enum machine_mode inner_mode = GET_MODE (x);
8262 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8263 int count = INTVAL (XEXP (x, 1));
8264 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8265 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8266 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8267 unsigned HOST_WIDE_INT outer = 0;
8269 if (mode_width > width)
8270 outer = (op_nonzero & nonzero & ~mode_mask);
8272 if (code == LSHIFTRT)
8274 else if (code == ASHIFTRT)
8278 /* If the sign bit may have been nonzero before the shift, we
8279 need to mark all the places it could have been copied to
8280 by the shift as possibly nonzero. */
8281 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8282 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8284 else if (code == ASHIFT)
8287 inner = ((inner << (count % width)
8288 | (inner >> (width - (count % width)))) & mode_mask);
8290 nonzero &= (outer | inner);
8295 /* This is at most the number of bits in the mode. */
8296 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8300 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8301 | nonzero_bits (XEXP (x, 2), mode));
8311 /* See the macro definition above. */
8312 #undef num_sign_bit_copies
8314 /* Return the number of bits at the high-order end of X that are known to
8315 be equal to the sign bit. X will be used in mode MODE; if MODE is
8316 VOIDmode, X will be used in its own mode. The returned value will always
8317 be between 1 and the number of bits in MODE. */
8320 num_sign_bit_copies (x, mode)
8322 enum machine_mode mode;
8324 enum rtx_code code = GET_CODE (x);
8325 unsigned int bitwidth;
8326 int num0, num1, result;
8327 unsigned HOST_WIDE_INT nonzero;
8330 /* If we weren't given a mode, use the mode of X. If the mode is still
8331 VOIDmode, we don't know anything. Likewise if one of the modes is
8334 if (mode == VOIDmode)
8335 mode = GET_MODE (x);
8337 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8340 bitwidth = GET_MODE_BITSIZE (mode);
8342 /* For a smaller object, just ignore the high bits. */
8343 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8345 num0 = num_sign_bit_copies (x, GET_MODE (x));
8347 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8350 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8352 #ifndef WORD_REGISTER_OPERATIONS
8353 /* If this machine does not do all register operations on the entire
8354 register and MODE is wider than the mode of X, we can say nothing
8355 at all about the high-order bits. */
8358 /* Likewise on machines that do, if the mode of the object is smaller
8359 than a word and loads of that size don't sign extend, we can say
8360 nothing about the high order bits. */
8361 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8362 #ifdef LOAD_EXTEND_OP
8363 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8374 #ifdef POINTERS_EXTEND_UNSIGNED
8375 /* If pointers extend signed and this is a pointer in Pmode, say that
8376 all the bits above ptr_mode are known to be sign bit copies. */
8377 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8378 && REGNO_POINTER_FLAG (REGNO (x)))
8379 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8382 if (reg_last_set_value[REGNO (x)] != 0
8383 && reg_last_set_mode[REGNO (x)] == mode
8384 && (reg_last_set_label[REGNO (x)] == label_tick
8385 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8386 && REG_N_SETS (REGNO (x)) == 1
8387 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8389 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8390 return reg_last_set_sign_bit_copies[REGNO (x)];
8392 tem = get_last_value (x);
8394 return num_sign_bit_copies (tem, mode);
8396 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8397 return reg_sign_bit_copies[REGNO (x)];
8401 #ifdef LOAD_EXTEND_OP
8402 /* Some RISC machines sign-extend all loads of smaller than a word. */
8403 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8404 return MAX (1, ((int) bitwidth
8405 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8410 /* If the constant is negative, take its 1's complement and remask.
8411 Then see how many zero bits we have. */
8412 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8413 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8414 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8415 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8417 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8420 /* If this is a SUBREG for a promoted object that is sign-extended
8421 and we are looking at it in a wider mode, we know that at least the
8422 high-order bits are known to be sign bit copies. */
8424 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8426 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8427 return MAX ((int) bitwidth
8428 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8432 /* For a smaller object, just ignore the high bits. */
8433 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8435 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8436 return MAX (1, (num0
8437 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8441 #ifdef WORD_REGISTER_OPERATIONS
8442 #ifdef LOAD_EXTEND_OP
8443 /* For paradoxical SUBREGs on machines where all register operations
8444 affect the entire register, just look inside. Note that we are
8445 passing MODE to the recursive call, so the number of sign bit copies
8446 will remain relative to that mode, not the inner mode. */
8448 /* This works only if loads sign extend. Otherwise, if we get a
8449 reload for the inner part, it may be loaded from the stack, and
8450 then we lose all sign bit copies that existed before the store
8453 if ((GET_MODE_SIZE (GET_MODE (x))
8454 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8455 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8456 return num_sign_bit_copies (SUBREG_REG (x), mode);
8462 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8463 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8467 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8468 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8471 /* For a smaller object, just ignore the high bits. */
8472 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8473 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8477 return num_sign_bit_copies (XEXP (x, 0), mode);
8479 case ROTATE: case ROTATERT:
8480 /* If we are rotating left by a number of bits less than the number
8481 of sign bit copies, we can just subtract that amount from the
8483 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8484 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8486 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8487 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8488 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8493 /* In general, this subtracts one sign bit copy. But if the value
8494 is known to be positive, the number of sign bit copies is the
8495 same as that of the input. Finally, if the input has just one bit
8496 that might be nonzero, all the bits are copies of the sign bit. */
8497 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8498 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8499 return num0 > 1 ? num0 - 1 : 1;
8501 nonzero = nonzero_bits (XEXP (x, 0), mode);
8506 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8511 case IOR: case AND: case XOR:
8512 case SMIN: case SMAX: case UMIN: case UMAX:
8513 /* Logical operations will preserve the number of sign-bit copies.
8514 MIN and MAX operations always return one of the operands. */
8515 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8516 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8517 return MIN (num0, num1);
8519 case PLUS: case MINUS:
8520 /* For addition and subtraction, we can have a 1-bit carry. However,
8521 if we are subtracting 1 from a positive number, there will not
8522 be such a carry. Furthermore, if the positive number is known to
8523 be 0 or 1, we know the result is either -1 or 0. */
8525 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8526 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8528 nonzero = nonzero_bits (XEXP (x, 0), mode);
8529 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8530 return (nonzero == 1 || nonzero == 0 ? bitwidth
8531 : bitwidth - floor_log2 (nonzero) - 1);
8534 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8535 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8536 return MAX (1, MIN (num0, num1) - 1);
8539 /* The number of bits of the product is the sum of the number of
8540 bits of both terms. However, unless one of the terms if known
8541 to be positive, we must allow for an additional bit since negating
8542 a negative number can remove one sign bit copy. */
8544 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8545 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8547 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8549 && (bitwidth > HOST_BITS_PER_WIDE_INT
8550 || (((nonzero_bits (XEXP (x, 0), mode)
8551 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8552 && ((nonzero_bits (XEXP (x, 1), mode)
8553 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8556 return MAX (1, result);
8559 /* The result must be <= the first operand. If the first operand
8560 has the high bit set, we know nothing about the number of sign
8562 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8564 else if ((nonzero_bits (XEXP (x, 0), mode)
8565 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8568 return num_sign_bit_copies (XEXP (x, 0), mode);
8571 /* The result must be <= the scond operand. */
8572 return num_sign_bit_copies (XEXP (x, 1), mode);
8575 /* Similar to unsigned division, except that we have to worry about
8576 the case where the divisor is negative, in which case we have
8578 result = num_sign_bit_copies (XEXP (x, 0), mode);
8580 && (bitwidth > HOST_BITS_PER_WIDE_INT
8581 || (nonzero_bits (XEXP (x, 1), mode)
8582 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8588 result = num_sign_bit_copies (XEXP (x, 1), mode);
8590 && (bitwidth > HOST_BITS_PER_WIDE_INT
8591 || (nonzero_bits (XEXP (x, 1), mode)
8592 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8598 /* Shifts by a constant add to the number of bits equal to the
8600 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8601 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8602 && INTVAL (XEXP (x, 1)) > 0)
8603 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8608 /* Left shifts destroy copies. */
8609 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8610 || INTVAL (XEXP (x, 1)) < 0
8611 || INTVAL (XEXP (x, 1)) >= bitwidth)
8614 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8615 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8618 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8619 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8620 return MIN (num0, num1);
8622 case EQ: case NE: case GE: case GT: case LE: case LT:
8623 case GEU: case GTU: case LEU: case LTU:
8624 if (STORE_FLAG_VALUE == -1)
8632 /* If we haven't been able to figure it out by one of the above rules,
8633 see if some of the high-order bits are known to be zero. If so,
8634 count those bits and return one less than that amount. If we can't
8635 safely compute the mask for this mode, always return BITWIDTH. */
8637 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8640 nonzero = nonzero_bits (x, mode);
8641 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8642 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8645 /* Return the number of "extended" bits there are in X, when interpreted
8646 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8647 unsigned quantities, this is the number of high-order zero bits.
8648 For signed quantities, this is the number of copies of the sign bit
8649 minus 1. In both case, this function returns the number of "spare"
8650 bits. For example, if two quantities for which this function returns
8651 at least 1 are added, the addition is known not to overflow.
8653 This function will always return 0 unless called during combine, which
8654 implies that it must be called from a define_split. */
8657 extended_count (x, mode, unsignedp)
8659 enum machine_mode mode;
8662 if (nonzero_sign_valid == 0)
8666 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8667 ? (GET_MODE_BITSIZE (mode) - 1
8668 - floor_log2 (nonzero_bits (x, mode)))
8670 : num_sign_bit_copies (x, mode) - 1);
8673 /* This function is called from `simplify_shift_const' to merge two
8674 outer operations. Specifically, we have already found that we need
8675 to perform operation *POP0 with constant *PCONST0 at the outermost
8676 position. We would now like to also perform OP1 with constant CONST1
8677 (with *POP0 being done last).
8679 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8680 the resulting operation. *PCOMP_P is set to 1 if we would need to
8681 complement the innermost operand, otherwise it is unchanged.
8683 MODE is the mode in which the operation will be done. No bits outside
8684 the width of this mode matter. It is assumed that the width of this mode
8685 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8687 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8688 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8689 result is simply *PCONST0.
8691 If the resulting operation cannot be expressed as one operation, we
8692 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8695 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8696 enum rtx_code *pop0;
8697 HOST_WIDE_INT *pconst0;
8699 HOST_WIDE_INT const1;
8700 enum machine_mode mode;
8703 enum rtx_code op0 = *pop0;
8704 HOST_WIDE_INT const0 = *pconst0;
8706 const0 &= GET_MODE_MASK (mode);
8707 const1 &= GET_MODE_MASK (mode);
8709 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8713 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8716 if (op1 == NIL || op0 == SET)
8719 else if (op0 == NIL)
8720 op0 = op1, const0 = const1;
8722 else if (op0 == op1)
8746 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8747 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8750 /* If the two constants aren't the same, we can't do anything. The
8751 remaining six cases can all be done. */
8752 else if (const0 != const1)
8760 /* (a & b) | b == b */
8762 else /* op1 == XOR */
8763 /* (a ^ b) | b == a | b */
8769 /* (a & b) ^ b == (~a) & b */
8770 op0 = AND, *pcomp_p = 1;
8771 else /* op1 == IOR */
8772 /* (a | b) ^ b == a & ~b */
8773 op0 = AND, *pconst0 = ~const0;
8778 /* (a | b) & b == b */
8780 else /* op1 == XOR */
8781 /* (a ^ b) & b) == (~a) & b */
8788 /* Check for NO-OP cases. */
8789 const0 &= GET_MODE_MASK (mode);
8791 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8793 else if (const0 == 0 && op0 == AND)
8795 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8799 /* ??? Slightly redundant with the above mask, but not entirely.
8800 Moving this above means we'd have to sign-extend the mode mask
8801 for the final test. */
8802 const0 = trunc_int_for_mode (const0, mode);
8810 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8811 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8812 that we started with.
8814 The shift is normally computed in the widest mode we find in VAROP, as
8815 long as it isn't a different number of words than RESULT_MODE. Exceptions
8816 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8819 simplify_shift_const (x, code, result_mode, varop, input_count)
8822 enum machine_mode result_mode;
8826 enum rtx_code orig_code = code;
8827 int orig_count = input_count;
8830 enum machine_mode mode = result_mode;
8831 enum machine_mode shift_mode, tmode;
8832 unsigned int mode_words
8833 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8834 /* We form (outer_op (code varop count) (outer_const)). */
8835 enum rtx_code outer_op = NIL;
8836 HOST_WIDE_INT outer_const = 0;
8838 int complement_p = 0;
8841 /* If we were given an invalid count, don't do anything except exactly
8842 what was requested. */
8844 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8849 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8852 count = input_count;
8854 /* Make sure and truncate the "natural" shift on the way in. We don't
8855 want to do this inside the loop as it makes it more difficult to
8857 #ifdef SHIFT_COUNT_TRUNCATED
8858 if (SHIFT_COUNT_TRUNCATED)
8859 count %= GET_MODE_BITSIZE (mode);
8862 /* Unless one of the branches of the `if' in this loop does a `continue',
8863 we will `break' the loop after the `if'. */
8867 /* If we have an operand of (clobber (const_int 0)), just return that
8869 if (GET_CODE (varop) == CLOBBER)
8872 /* If we discovered we had to complement VAROP, leave. Making a NOT
8873 here would cause an infinite loop. */
8877 /* Convert ROTATERT to ROTATE. */
8878 if (code == ROTATERT)
8879 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8881 /* We need to determine what mode we will do the shift in. If the
8882 shift is a right shift or a ROTATE, we must always do it in the mode
8883 it was originally done in. Otherwise, we can do it in MODE, the
8884 widest mode encountered. */
8886 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8887 ? result_mode : mode);
8889 /* Handle cases where the count is greater than the size of the mode
8890 minus 1. For ASHIFT, use the size minus one as the count (this can
8891 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8892 take the count modulo the size. For other shifts, the result is
8895 Since these shifts are being produced by the compiler by combining
8896 multiple operations, each of which are defined, we know what the
8897 result is supposed to be. */
8899 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8901 if (code == ASHIFTRT)
8902 count = GET_MODE_BITSIZE (shift_mode) - 1;
8903 else if (code == ROTATE || code == ROTATERT)
8904 count %= GET_MODE_BITSIZE (shift_mode);
8907 /* We can't simply return zero because there may be an
8915 /* An arithmetic right shift of a quantity known to be -1 or 0
8917 if (code == ASHIFTRT
8918 && (num_sign_bit_copies (varop, shift_mode)
8919 == GET_MODE_BITSIZE (shift_mode)))
8925 /* If we are doing an arithmetic right shift and discarding all but
8926 the sign bit copies, this is equivalent to doing a shift by the
8927 bitsize minus one. Convert it into that shift because it will often
8928 allow other simplifications. */
8930 if (code == ASHIFTRT
8931 && (count + num_sign_bit_copies (varop, shift_mode)
8932 >= GET_MODE_BITSIZE (shift_mode)))
8933 count = GET_MODE_BITSIZE (shift_mode) - 1;
8935 /* We simplify the tests below and elsewhere by converting
8936 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8937 `make_compound_operation' will convert it to a ASHIFTRT for
8938 those machines (such as Vax) that don't have a LSHIFTRT. */
8939 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8941 && ((nonzero_bits (varop, shift_mode)
8942 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8946 switch (GET_CODE (varop))
8952 new = expand_compound_operation (varop);
8961 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8962 minus the width of a smaller mode, we can do this with a
8963 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8964 if ((code == ASHIFTRT || code == LSHIFTRT)
8965 && ! mode_dependent_address_p (XEXP (varop, 0))
8966 && ! MEM_VOLATILE_P (varop)
8967 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8968 MODE_INT, 1)) != BLKmode)
8970 if (BYTES_BIG_ENDIAN)
8971 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8973 new = gen_rtx_MEM (tmode,
8974 plus_constant (XEXP (varop, 0),
8975 count / BITS_PER_UNIT));
8977 MEM_COPY_ATTRIBUTES (new, varop);
8978 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8979 : ZERO_EXTEND, mode, new);
8986 /* Similar to the case above, except that we can only do this if
8987 the resulting mode is the same as that of the underlying
8988 MEM and adjust the address depending on the *bits* endianness
8989 because of the way that bit-field extract insns are defined. */
8990 if ((code == ASHIFTRT || code == LSHIFTRT)
8991 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8992 MODE_INT, 1)) != BLKmode
8993 && tmode == GET_MODE (XEXP (varop, 0)))
8995 if (BITS_BIG_ENDIAN)
8996 new = XEXP (varop, 0);
8999 new = copy_rtx (XEXP (varop, 0));
9000 SUBST (XEXP (new, 0),
9001 plus_constant (XEXP (new, 0),
9002 count / BITS_PER_UNIT));
9005 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9006 : ZERO_EXTEND, mode, new);
9013 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9014 the same number of words as what we've seen so far. Then store
9015 the widest mode in MODE. */
9016 if (subreg_lowpart_p (varop)
9017 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9018 > GET_MODE_SIZE (GET_MODE (varop)))
9019 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9020 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9023 varop = SUBREG_REG (varop);
9024 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9025 mode = GET_MODE (varop);
9031 /* Some machines use MULT instead of ASHIFT because MULT
9032 is cheaper. But it is still better on those machines to
9033 merge two shifts into one. */
9034 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9035 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9038 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9039 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9045 /* Similar, for when divides are cheaper. */
9046 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9047 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9050 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9051 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9057 /* If we are extracting just the sign bit of an arithmetic right
9058 shift, that shift is not needed. */
9059 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
9061 varop = XEXP (varop, 0);
9065 /* ... fall through ... */
9070 /* Here we have two nested shifts. The result is usually the
9071 AND of a new shift with a mask. We compute the result below. */
9072 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9073 && INTVAL (XEXP (varop, 1)) >= 0
9074 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9075 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9076 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9078 enum rtx_code first_code = GET_CODE (varop);
9079 unsigned int first_count = INTVAL (XEXP (varop, 1));
9080 unsigned HOST_WIDE_INT mask;
9083 /* We have one common special case. We can't do any merging if
9084 the inner code is an ASHIFTRT of a smaller mode. However, if
9085 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9086 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9087 we can convert it to
9088 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9089 This simplifies certain SIGN_EXTEND operations. */
9090 if (code == ASHIFT && first_code == ASHIFTRT
9091 && (GET_MODE_BITSIZE (result_mode)
9092 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9094 /* C3 has the low-order C1 bits zero. */
9096 mask = (GET_MODE_MASK (mode)
9097 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9099 varop = simplify_and_const_int (NULL_RTX, result_mode,
9100 XEXP (varop, 0), mask);
9101 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9103 count = first_count;
9108 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9109 than C1 high-order bits equal to the sign bit, we can convert
9110 this to either an ASHIFT or a ASHIFTRT depending on the
9113 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9115 if (code == ASHIFTRT && first_code == ASHIFT
9116 && GET_MODE (varop) == shift_mode
9117 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9120 varop = XEXP (varop, 0);
9122 signed_count = count - first_count;
9123 if (signed_count < 0)
9124 count = -signed_count, code = ASHIFT;
9126 count = signed_count;
9131 /* There are some cases we can't do. If CODE is ASHIFTRT,
9132 we can only do this if FIRST_CODE is also ASHIFTRT.
9134 We can't do the case when CODE is ROTATE and FIRST_CODE is
9137 If the mode of this shift is not the mode of the outer shift,
9138 we can't do this if either shift is a right shift or ROTATE.
9140 Finally, we can't do any of these if the mode is too wide
9141 unless the codes are the same.
9143 Handle the case where the shift codes are the same
9146 if (code == first_code)
9148 if (GET_MODE (varop) != result_mode
9149 && (code == ASHIFTRT || code == LSHIFTRT
9153 count += first_count;
9154 varop = XEXP (varop, 0);
9158 if (code == ASHIFTRT
9159 || (code == ROTATE && first_code == ASHIFTRT)
9160 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9161 || (GET_MODE (varop) != result_mode
9162 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9163 || first_code == ROTATE
9164 || code == ROTATE)))
9167 /* To compute the mask to apply after the shift, shift the
9168 nonzero bits of the inner shift the same way the
9169 outer shift will. */
9171 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9174 = simplify_binary_operation (code, result_mode, mask_rtx,
9177 /* Give up if we can't compute an outer operation to use. */
9179 || GET_CODE (mask_rtx) != CONST_INT
9180 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9182 result_mode, &complement_p))
9185 /* If the shifts are in the same direction, we add the
9186 counts. Otherwise, we subtract them. */
9187 signed_count = count;
9188 if ((code == ASHIFTRT || code == LSHIFTRT)
9189 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9190 signed_count += first_count;
9192 signed_count -= first_count;
9194 /* If COUNT is positive, the new shift is usually CODE,
9195 except for the two exceptions below, in which case it is
9196 FIRST_CODE. If the count is negative, FIRST_CODE should
9198 if (signed_count > 0
9199 && ((first_code == ROTATE && code == ASHIFT)
9200 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9201 code = first_code, count = signed_count;
9202 else if (signed_count < 0)
9203 code = first_code, count = -signed_count;
9205 count = signed_count;
9207 varop = XEXP (varop, 0);
9211 /* If we have (A << B << C) for any shift, we can convert this to
9212 (A << C << B). This wins if A is a constant. Only try this if
9213 B is not a constant. */
9215 else if (GET_CODE (varop) == code
9216 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9218 = simplify_binary_operation (code, mode,
9222 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9229 /* Make this fit the case below. */
9230 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9231 GEN_INT (GET_MODE_MASK (mode)));
9237 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9238 with C the size of VAROP - 1 and the shift is logical if
9239 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9240 we have an (le X 0) operation. If we have an arithmetic shift
9241 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9242 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9244 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9245 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9246 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9247 && (code == LSHIFTRT || code == ASHIFTRT)
9248 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9249 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9252 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9255 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9256 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9261 /* If we have (shift (logical)), move the logical to the outside
9262 to allow it to possibly combine with another logical and the
9263 shift to combine with another shift. This also canonicalizes to
9264 what a ZERO_EXTRACT looks like. Also, some machines have
9265 (and (shift)) insns. */
9267 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9268 && (new = simplify_binary_operation (code, result_mode,
9270 GEN_INT (count))) != 0
9271 && GET_CODE (new) == CONST_INT
9272 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9273 INTVAL (new), result_mode, &complement_p))
9275 varop = XEXP (varop, 0);
9279 /* If we can't do that, try to simplify the shift in each arm of the
9280 logical expression, make a new logical expression, and apply
9281 the inverse distributive law. */
9283 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9284 XEXP (varop, 0), count);
9285 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9286 XEXP (varop, 1), count);
9288 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9289 varop = apply_distributive_law (varop);
9296 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9297 says that the sign bit can be tested, FOO has mode MODE, C is
9298 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9299 that may be nonzero. */
9300 if (code == LSHIFTRT
9301 && XEXP (varop, 1) == const0_rtx
9302 && GET_MODE (XEXP (varop, 0)) == result_mode
9303 && count == GET_MODE_BITSIZE (result_mode) - 1
9304 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9305 && ((STORE_FLAG_VALUE
9306 & ((HOST_WIDE_INT) 1
9307 < (GET_MODE_BITSIZE (result_mode) - 1))))
9308 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9309 && merge_outer_ops (&outer_op, &outer_const, XOR,
9310 (HOST_WIDE_INT) 1, result_mode,
9313 varop = XEXP (varop, 0);
9320 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9321 than the number of bits in the mode is equivalent to A. */
9322 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9323 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9325 varop = XEXP (varop, 0);
9330 /* NEG commutes with ASHIFT since it is multiplication. Move the
9331 NEG outside to allow shifts to combine. */
9333 && merge_outer_ops (&outer_op, &outer_const, NEG,
9334 (HOST_WIDE_INT) 0, result_mode,
9337 varop = XEXP (varop, 0);
9343 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9344 is one less than the number of bits in the mode is
9345 equivalent to (xor A 1). */
9346 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9347 && XEXP (varop, 1) == constm1_rtx
9348 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9349 && merge_outer_ops (&outer_op, &outer_const, XOR,
9350 (HOST_WIDE_INT) 1, result_mode,
9354 varop = XEXP (varop, 0);
9358 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9359 that might be nonzero in BAR are those being shifted out and those
9360 bits are known zero in FOO, we can replace the PLUS with FOO.
9361 Similarly in the other operand order. This code occurs when
9362 we are computing the size of a variable-size array. */
9364 if ((code == ASHIFTRT || code == LSHIFTRT)
9365 && count < HOST_BITS_PER_WIDE_INT
9366 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9367 && (nonzero_bits (XEXP (varop, 1), result_mode)
9368 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9370 varop = XEXP (varop, 0);
9373 else if ((code == ASHIFTRT || code == LSHIFTRT)
9374 && count < HOST_BITS_PER_WIDE_INT
9375 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9376 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9378 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9379 & nonzero_bits (XEXP (varop, 1),
9382 varop = XEXP (varop, 1);
9386 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9388 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9389 && (new = simplify_binary_operation (ASHIFT, result_mode,
9391 GEN_INT (count))) != 0
9392 && GET_CODE (new) == CONST_INT
9393 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9394 INTVAL (new), result_mode, &complement_p))
9396 varop = XEXP (varop, 0);
9402 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9403 with C the size of VAROP - 1 and the shift is logical if
9404 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9405 we have a (gt X 0) operation. If the shift is arithmetic with
9406 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9407 we have a (neg (gt X 0)) operation. */
9409 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9410 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9411 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9412 && (code == LSHIFTRT || code == ASHIFTRT)
9413 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9414 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9415 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9418 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9421 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9422 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9429 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9430 if the truncate does not affect the value. */
9431 if (code == LSHIFTRT
9432 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9433 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9434 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9435 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9436 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9438 rtx varop_inner = XEXP (varop, 0);
9441 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9442 XEXP (varop_inner, 0),
9444 + INTVAL (XEXP (varop_inner, 1))));
9445 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9459 /* We need to determine what mode to do the shift in. If the shift is
9460 a right shift or ROTATE, we must always do it in the mode it was
9461 originally done in. Otherwise, we can do it in MODE, the widest mode
9462 encountered. The code we care about is that of the shift that will
9463 actually be done, not the shift that was originally requested. */
9465 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9466 ? result_mode : mode);
9468 /* We have now finished analyzing the shift. The result should be
9469 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9470 OUTER_OP is non-NIL, it is an operation that needs to be applied
9471 to the result of the shift. OUTER_CONST is the relevant constant,
9472 but we must turn off all bits turned off in the shift.
9474 If we were passed a value for X, see if we can use any pieces of
9475 it. If not, make new rtx. */
9477 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9478 && GET_CODE (XEXP (x, 1)) == CONST_INT
9479 && INTVAL (XEXP (x, 1)) == count)
9480 const_rtx = XEXP (x, 1);
9482 const_rtx = GEN_INT (count);
9484 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9485 && GET_MODE (XEXP (x, 0)) == shift_mode
9486 && SUBREG_REG (XEXP (x, 0)) == varop)
9487 varop = XEXP (x, 0);
9488 else if (GET_MODE (varop) != shift_mode)
9489 varop = gen_lowpart_for_combine (shift_mode, varop);
9491 /* If we can't make the SUBREG, try to return what we were given. */
9492 if (GET_CODE (varop) == CLOBBER)
9493 return x ? x : varop;
9495 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9500 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9501 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9503 SUBST (XEXP (x, 0), varop);
9504 SUBST (XEXP (x, 1), const_rtx);
9507 /* If we have an outer operation and we just made a shift, it is
9508 possible that we could have simplified the shift were it not
9509 for the outer operation. So try to do the simplification
9512 if (outer_op != NIL && GET_CODE (x) == code
9513 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9514 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9515 INTVAL (XEXP (x, 1)));
9517 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9518 turn off all the bits that the shift would have turned off. */
9519 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9520 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9521 GET_MODE_MASK (result_mode) >> orig_count);
9523 /* Do the remainder of the processing in RESULT_MODE. */
9524 x = gen_lowpart_for_combine (result_mode, x);
9526 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9529 x = gen_unary (NOT, result_mode, result_mode, x);
9531 if (outer_op != NIL)
9533 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9534 outer_const = trunc_int_for_mode (outer_const, result_mode);
9536 if (outer_op == AND)
9537 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9538 else if (outer_op == SET)
9539 /* This means that we have determined that the result is
9540 equivalent to a constant. This should be rare. */
9541 x = GEN_INT (outer_const);
9542 else if (GET_RTX_CLASS (outer_op) == '1')
9543 x = gen_unary (outer_op, result_mode, result_mode, x);
9545 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9551 /* Like recog, but we receive the address of a pointer to a new pattern.
9552 We try to match the rtx that the pointer points to.
9553 If that fails, we may try to modify or replace the pattern,
9554 storing the replacement into the same pointer object.
9556 Modifications include deletion or addition of CLOBBERs.
9558 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9559 the CLOBBERs are placed.
9561 The value is the final insn code from the pattern ultimately matched,
9565 recog_for_combine (pnewpat, insn, pnotes)
9570 register rtx pat = *pnewpat;
9571 int insn_code_number;
9572 int num_clobbers_to_add = 0;
9577 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9578 we use to indicate that something didn't match. If we find such a
9579 thing, force rejection. */
9580 if (GET_CODE (pat) == PARALLEL)
9581 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9582 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9583 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9586 /* Remove the old notes prior to trying to recognize the new pattern. */
9587 old_notes = REG_NOTES (insn);
9588 REG_NOTES (insn) = 0;
9590 /* Is the result of combination a valid instruction? */
9591 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9593 /* If it isn't, there is the possibility that we previously had an insn
9594 that clobbered some register as a side effect, but the combined
9595 insn doesn't need to do that. So try once more without the clobbers
9596 unless this represents an ASM insn. */
9598 if (insn_code_number < 0 && ! check_asm_operands (pat)
9599 && GET_CODE (pat) == PARALLEL)
9603 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9604 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9607 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9611 SUBST_INT (XVECLEN (pat, 0), pos);
9614 pat = XVECEXP (pat, 0, 0);
9616 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9619 REG_NOTES (insn) = old_notes;
9621 /* If we had any clobbers to add, make a new pattern than contains
9622 them. Then check to make sure that all of them are dead. */
9623 if (num_clobbers_to_add)
9625 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9626 gen_rtvec (GET_CODE (pat) == PARALLEL
9628 + num_clobbers_to_add)
9629 : num_clobbers_to_add + 1));
9631 if (GET_CODE (pat) == PARALLEL)
9632 for (i = 0; i < XVECLEN (pat, 0); i++)
9633 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9635 XVECEXP (newpat, 0, 0) = pat;
9637 add_clobbers (newpat, insn_code_number);
9639 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9640 i < XVECLEN (newpat, 0); i++)
9642 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9643 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9645 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9646 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9654 return insn_code_number;
9657 /* Like gen_lowpart but for use by combine. In combine it is not possible
9658 to create any new pseudoregs. However, it is safe to create
9659 invalid memory addresses, because combine will try to recognize
9660 them and all they will do is make the combine attempt fail.
9662 If for some reason this cannot do its job, an rtx
9663 (clobber (const_int 0)) is returned.
9664 An insn containing that will not be recognized. */
9669 gen_lowpart_for_combine (mode, x)
9670 enum machine_mode mode;
9675 if (GET_MODE (x) == mode)
9678 /* We can only support MODE being wider than a word if X is a
9679 constant integer or has a mode the same size. */
9681 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9682 && ! ((GET_MODE (x) == VOIDmode
9683 && (GET_CODE (x) == CONST_INT
9684 || GET_CODE (x) == CONST_DOUBLE))
9685 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9686 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9688 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9689 won't know what to do. So we will strip off the SUBREG here and
9690 process normally. */
9691 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9694 if (GET_MODE (x) == mode)
9698 result = gen_lowpart_common (mode, x);
9699 #ifdef CLASS_CANNOT_CHANGE_MODE
9701 && GET_CODE (result) == SUBREG
9702 && GET_CODE (SUBREG_REG (result)) == REG
9703 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9704 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9705 GET_MODE (SUBREG_REG (result))))
9706 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9712 if (GET_CODE (x) == MEM)
9714 register int offset = 0;
9717 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9719 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9720 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9722 /* If we want to refer to something bigger than the original memref,
9723 generate a perverse subreg instead. That will force a reload
9724 of the original memref X. */
9725 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9726 return gen_rtx_SUBREG (mode, x, 0);
9728 if (WORDS_BIG_ENDIAN)
9729 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9730 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9732 if (BYTES_BIG_ENDIAN)
9734 /* Adjust the address so that the address-after-the-data is
9736 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9737 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9739 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9740 MEM_COPY_ATTRIBUTES (new, x);
9744 /* If X is a comparison operator, rewrite it in a new mode. This
9745 probably won't match, but may allow further simplifications. */
9746 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9747 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9749 /* If we couldn't simplify X any other way, just enclose it in a
9750 SUBREG. Normally, this SUBREG won't match, but some patterns may
9751 include an explicit SUBREG or we may simplify it further in combine. */
9756 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9757 word = ((GET_MODE_SIZE (GET_MODE (x))
9758 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9760 return gen_rtx_SUBREG (mode, x, word);
9764 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9765 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9767 If the identical expression was previously in the insn (in the undobuf),
9768 it will be returned. Only if it is not found will a new expression
9773 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9775 #ifndef ANSI_PROTOTYPES
9777 enum machine_mode mode;
9789 #ifndef ANSI_PROTOTYPES
9790 code = va_arg (p, enum rtx_code);
9791 mode = va_arg (p, enum machine_mode);
9794 n_args = GET_RTX_LENGTH (code);
9795 fmt = GET_RTX_FORMAT (code);
9797 if (n_args == 0 || n_args > 3)
9800 /* Get each arg and verify that it is supposed to be an expression. */
9801 for (j = 0; j < n_args; j++)
9806 args[j] = va_arg (p, rtx);
9811 /* See if this is in undobuf. Be sure we don't use objects that came
9812 from another insn; this could produce circular rtl structures. */
9814 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9816 && GET_CODE (undo->old_contents.r) == code
9817 && GET_MODE (undo->old_contents.r) == mode)
9819 for (j = 0; j < n_args; j++)
9820 if (XEXP (undo->old_contents.r, j) != args[j])
9824 return undo->old_contents.r;
9827 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9828 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9829 rt = rtx_alloc (code);
9830 PUT_MODE (rt, mode);
9831 XEXP (rt, 0) = args[0];
9834 XEXP (rt, 1) = args[1];
9836 XEXP (rt, 2) = args[2];
9841 /* These routines make binary and unary operations by first seeing if they
9842 fold; if not, a new expression is allocated. */
9845 gen_binary (code, mode, op0, op1)
9847 enum machine_mode mode;
9853 if (GET_RTX_CLASS (code) == 'c'
9854 && (GET_CODE (op0) == CONST_INT
9855 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9856 tem = op0, op0 = op1, op1 = tem;
9858 if (GET_RTX_CLASS (code) == '<')
9860 enum machine_mode op_mode = GET_MODE (op0);
9862 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9863 just (REL_OP X Y). */
9864 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9866 op1 = XEXP (op0, 1);
9867 op0 = XEXP (op0, 0);
9868 op_mode = GET_MODE (op0);
9871 if (op_mode == VOIDmode)
9872 op_mode = GET_MODE (op1);
9873 result = simplify_relational_operation (code, op_mode, op0, op1);
9876 result = simplify_binary_operation (code, mode, op0, op1);
9881 /* Put complex operands first and constants second. */
9882 if (GET_RTX_CLASS (code) == 'c'
9883 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9884 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9885 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9886 || (GET_CODE (op0) == SUBREG
9887 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9888 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9889 return gen_rtx_combine (code, mode, op1, op0);
9891 /* If we are turning off bits already known off in OP0, we need not do
9893 else if (code == AND && GET_CODE (op1) == CONST_INT
9894 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9895 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9898 return gen_rtx_combine (code, mode, op0, op1);
9902 gen_unary (code, mode, op0_mode, op0)
9904 enum machine_mode mode, op0_mode;
9907 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9912 return gen_rtx_combine (code, mode, op0);
9915 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9916 comparison code that will be tested.
9918 The result is a possibly different comparison code to use. *POP0 and
9919 *POP1 may be updated.
9921 It is possible that we might detect that a comparison is either always
9922 true or always false. However, we do not perform general constant
9923 folding in combine, so this knowledge isn't useful. Such tautologies
9924 should have been detected earlier. Hence we ignore all such cases. */
9926 static enum rtx_code
9927 simplify_comparison (code, pop0, pop1)
9936 enum machine_mode mode, tmode;
9938 /* Try a few ways of applying the same transformation to both operands. */
9941 #ifndef WORD_REGISTER_OPERATIONS
9942 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9943 so check specially. */
9944 if (code != GTU && code != GEU && code != LTU && code != LEU
9945 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9946 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9947 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9948 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9949 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9950 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9951 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9952 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9953 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9954 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9955 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9956 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9957 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9958 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9959 && (INTVAL (XEXP (op0, 1))
9960 == (GET_MODE_BITSIZE (GET_MODE (op0))
9962 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9964 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9965 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9969 /* If both operands are the same constant shift, see if we can ignore the
9970 shift. We can if the shift is a rotate or if the bits shifted out of
9971 this shift are known to be zero for both inputs and if the type of
9972 comparison is compatible with the shift. */
9973 if (GET_CODE (op0) == GET_CODE (op1)
9974 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9975 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9976 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9977 && (code != GT && code != LT && code != GE && code != LE))
9978 || (GET_CODE (op0) == ASHIFTRT
9979 && (code != GTU && code != LTU
9980 && code != GEU && code != GEU)))
9981 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9982 && INTVAL (XEXP (op0, 1)) >= 0
9983 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9984 && XEXP (op0, 1) == XEXP (op1, 1))
9986 enum machine_mode mode = GET_MODE (op0);
9987 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9988 int shift_count = INTVAL (XEXP (op0, 1));
9990 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9991 mask &= (mask >> shift_count) << shift_count;
9992 else if (GET_CODE (op0) == ASHIFT)
9993 mask = (mask & (mask << shift_count)) >> shift_count;
9995 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9996 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9997 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10002 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10003 SUBREGs are of the same mode, and, in both cases, the AND would
10004 be redundant if the comparison was done in the narrower mode,
10005 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10006 and the operand's possibly nonzero bits are 0xffffff01; in that case
10007 if we only care about QImode, we don't need the AND). This case
10008 occurs if the output mode of an scc insn is not SImode and
10009 STORE_FLAG_VALUE == 1 (e.g., the 386).
10011 Similarly, check for a case where the AND's are ZERO_EXTEND
10012 operations from some narrower mode even though a SUBREG is not
10015 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10016 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10017 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10019 rtx inner_op0 = XEXP (op0, 0);
10020 rtx inner_op1 = XEXP (op1, 0);
10021 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10022 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10025 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10026 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10027 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10028 && (GET_MODE (SUBREG_REG (inner_op0))
10029 == GET_MODE (SUBREG_REG (inner_op1)))
10030 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10031 <= HOST_BITS_PER_WIDE_INT)
10032 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10033 GET_MODE (SUBREG_REG (inner_op0)))))
10034 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10035 GET_MODE (SUBREG_REG (inner_op1))))))
10037 op0 = SUBREG_REG (inner_op0);
10038 op1 = SUBREG_REG (inner_op1);
10040 /* The resulting comparison is always unsigned since we masked
10041 off the original sign bit. */
10042 code = unsigned_condition (code);
10048 for (tmode = GET_CLASS_NARROWEST_MODE
10049 (GET_MODE_CLASS (GET_MODE (op0)));
10050 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10051 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10053 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10054 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10055 code = unsigned_condition (code);
10064 /* If both operands are NOT, we can strip off the outer operation
10065 and adjust the comparison code for swapped operands; similarly for
10066 NEG, except that this must be an equality comparison. */
10067 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10068 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10069 && (code == EQ || code == NE)))
10070 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10076 /* If the first operand is a constant, swap the operands and adjust the
10077 comparison code appropriately, but don't do this if the second operand
10078 is already a constant integer. */
10079 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10081 tem = op0, op0 = op1, op1 = tem;
10082 code = swap_condition (code);
10085 /* We now enter a loop during which we will try to simplify the comparison.
10086 For the most part, we only are concerned with comparisons with zero,
10087 but some things may really be comparisons with zero but not start
10088 out looking that way. */
10090 while (GET_CODE (op1) == CONST_INT)
10092 enum machine_mode mode = GET_MODE (op0);
10093 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10094 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10095 int equality_comparison_p;
10096 int sign_bit_comparison_p;
10097 int unsigned_comparison_p;
10098 HOST_WIDE_INT const_op;
10100 /* We only want to handle integral modes. This catches VOIDmode,
10101 CCmode, and the floating-point modes. An exception is that we
10102 can handle VOIDmode if OP0 is a COMPARE or a comparison
10105 if (GET_MODE_CLASS (mode) != MODE_INT
10106 && ! (mode == VOIDmode
10107 && (GET_CODE (op0) == COMPARE
10108 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10111 /* Get the constant we are comparing against and turn off all bits
10112 not on in our mode. */
10113 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10115 /* If we are comparing against a constant power of two and the value
10116 being compared can only have that single bit nonzero (e.g., it was
10117 `and'ed with that bit), we can replace this with a comparison
10120 && (code == EQ || code == NE || code == GE || code == GEU
10121 || code == LT || code == LTU)
10122 && mode_width <= HOST_BITS_PER_WIDE_INT
10123 && exact_log2 (const_op) >= 0
10124 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10126 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10127 op1 = const0_rtx, const_op = 0;
10130 /* Similarly, if we are comparing a value known to be either -1 or
10131 0 with -1, change it to the opposite comparison against zero. */
10134 && (code == EQ || code == NE || code == GT || code == LE
10135 || code == GEU || code == LTU)
10136 && num_sign_bit_copies (op0, mode) == mode_width)
10138 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10139 op1 = const0_rtx, const_op = 0;
10142 /* Do some canonicalizations based on the comparison code. We prefer
10143 comparisons against zero and then prefer equality comparisons.
10144 If we can reduce the size of a constant, we will do that too. */
10149 /* < C is equivalent to <= (C - 1) */
10153 op1 = GEN_INT (const_op);
10155 /* ... fall through to LE case below. */
10161 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10165 op1 = GEN_INT (const_op);
10169 /* If we are doing a <= 0 comparison on a value known to have
10170 a zero sign bit, we can replace this with == 0. */
10171 else if (const_op == 0
10172 && mode_width <= HOST_BITS_PER_WIDE_INT
10173 && (nonzero_bits (op0, mode)
10174 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10179 /* >= C is equivalent to > (C - 1). */
10183 op1 = GEN_INT (const_op);
10185 /* ... fall through to GT below. */
10191 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10195 op1 = GEN_INT (const_op);
10199 /* If we are doing a > 0 comparison on a value known to have
10200 a zero sign bit, we can replace this with != 0. */
10201 else if (const_op == 0
10202 && mode_width <= HOST_BITS_PER_WIDE_INT
10203 && (nonzero_bits (op0, mode)
10204 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10209 /* < C is equivalent to <= (C - 1). */
10213 op1 = GEN_INT (const_op);
10215 /* ... fall through ... */
10218 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10219 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10220 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10222 const_op = 0, op1 = const0_rtx;
10230 /* unsigned <= 0 is equivalent to == 0 */
10234 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10235 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10236 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10238 const_op = 0, op1 = const0_rtx;
10244 /* >= C is equivalent to < (C - 1). */
10248 op1 = GEN_INT (const_op);
10250 /* ... fall through ... */
10253 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10254 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10255 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10257 const_op = 0, op1 = const0_rtx;
10265 /* unsigned > 0 is equivalent to != 0 */
10269 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10270 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10271 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10273 const_op = 0, op1 = const0_rtx;
10282 /* Compute some predicates to simplify code below. */
10284 equality_comparison_p = (code == EQ || code == NE);
10285 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10286 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10289 /* If this is a sign bit comparison and we can do arithmetic in
10290 MODE, say that we will only be needing the sign bit of OP0. */
10291 if (sign_bit_comparison_p
10292 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10293 op0 = force_to_mode (op0, mode,
10295 << (GET_MODE_BITSIZE (mode) - 1)),
10298 /* Now try cases based on the opcode of OP0. If none of the cases
10299 does a "continue", we exit this loop immediately after the
10302 switch (GET_CODE (op0))
10305 /* If we are extracting a single bit from a variable position in
10306 a constant that has only a single bit set and are comparing it
10307 with zero, we can convert this into an equality comparison
10308 between the position and the location of the single bit. */
10310 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10311 && XEXP (op0, 1) == const1_rtx
10312 && equality_comparison_p && const_op == 0
10313 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10315 if (BITS_BIG_ENDIAN)
10318 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10319 if (mode == VOIDmode)
10321 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10323 i = BITS_PER_WORD - 1 - i;
10327 op0 = XEXP (op0, 2);
10331 /* Result is nonzero iff shift count is equal to I. */
10332 code = reverse_condition (code);
10336 /* ... fall through ... */
10339 tem = expand_compound_operation (op0);
10348 /* If testing for equality, we can take the NOT of the constant. */
10349 if (equality_comparison_p
10350 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10352 op0 = XEXP (op0, 0);
10357 /* If just looking at the sign bit, reverse the sense of the
10359 if (sign_bit_comparison_p)
10361 op0 = XEXP (op0, 0);
10362 code = (code == GE ? LT : GE);
10368 /* If testing for equality, we can take the NEG of the constant. */
10369 if (equality_comparison_p
10370 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10372 op0 = XEXP (op0, 0);
10377 /* The remaining cases only apply to comparisons with zero. */
10381 /* When X is ABS or is known positive,
10382 (neg X) is < 0 if and only if X != 0. */
10384 if (sign_bit_comparison_p
10385 && (GET_CODE (XEXP (op0, 0)) == ABS
10386 || (mode_width <= HOST_BITS_PER_WIDE_INT
10387 && (nonzero_bits (XEXP (op0, 0), mode)
10388 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10390 op0 = XEXP (op0, 0);
10391 code = (code == LT ? NE : EQ);
10395 /* If we have NEG of something whose two high-order bits are the
10396 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10397 if (num_sign_bit_copies (op0, mode) >= 2)
10399 op0 = XEXP (op0, 0);
10400 code = swap_condition (code);
10406 /* If we are testing equality and our count is a constant, we
10407 can perform the inverse operation on our RHS. */
10408 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10409 && (tem = simplify_binary_operation (ROTATERT, mode,
10410 op1, XEXP (op0, 1))) != 0)
10412 op0 = XEXP (op0, 0);
10417 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10418 a particular bit. Convert it to an AND of a constant of that
10419 bit. This will be converted into a ZERO_EXTRACT. */
10420 if (const_op == 0 && sign_bit_comparison_p
10421 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10422 && mode_width <= HOST_BITS_PER_WIDE_INT)
10424 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10427 - INTVAL (XEXP (op0, 1)))));
10428 code = (code == LT ? NE : EQ);
10432 /* Fall through. */
10435 /* ABS is ignorable inside an equality comparison with zero. */
10436 if (const_op == 0 && equality_comparison_p)
10438 op0 = XEXP (op0, 0);
10444 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10445 to (compare FOO CONST) if CONST fits in FOO's mode and we
10446 are either testing inequality or have an unsigned comparison
10447 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10448 if (! unsigned_comparison_p
10449 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10450 <= HOST_BITS_PER_WIDE_INT)
10451 && ((unsigned HOST_WIDE_INT) const_op
10452 < (((unsigned HOST_WIDE_INT) 1
10453 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10455 op0 = XEXP (op0, 0);
10461 /* Check for the case where we are comparing A - C1 with C2,
10462 both constants are smaller than 1/2 the maximum positive
10463 value in MODE, and the comparison is equality or unsigned.
10464 In that case, if A is either zero-extended to MODE or has
10465 sufficient sign bits so that the high-order bit in MODE
10466 is a copy of the sign in the inner mode, we can prove that it is
10467 safe to do the operation in the wider mode. This simplifies
10468 many range checks. */
10470 if (mode_width <= HOST_BITS_PER_WIDE_INT
10471 && subreg_lowpart_p (op0)
10472 && GET_CODE (SUBREG_REG (op0)) == PLUS
10473 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10474 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10475 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10476 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10477 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10478 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10479 GET_MODE (SUBREG_REG (op0)))
10480 & ~GET_MODE_MASK (mode))
10481 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10482 GET_MODE (SUBREG_REG (op0)))
10483 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10484 - GET_MODE_BITSIZE (mode)))))
10486 op0 = SUBREG_REG (op0);
10490 /* If the inner mode is narrower and we are extracting the low part,
10491 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10492 if (subreg_lowpart_p (op0)
10493 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10494 /* Fall through */ ;
10498 /* ... fall through ... */
10501 if ((unsigned_comparison_p || equality_comparison_p)
10502 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10503 <= HOST_BITS_PER_WIDE_INT)
10504 && ((unsigned HOST_WIDE_INT) const_op
10505 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10507 op0 = XEXP (op0, 0);
10513 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10514 this for equality comparisons due to pathological cases involving
10516 if (equality_comparison_p
10517 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10518 op1, XEXP (op0, 1))))
10520 op0 = XEXP (op0, 0);
10525 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10526 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10527 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10529 op0 = XEXP (XEXP (op0, 0), 0);
10530 code = (code == LT ? EQ : NE);
10536 /* We used to optimize signed comparisons against zero, but that
10537 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10538 arrive here as equality comparisons, or (GEU, LTU) are
10539 optimized away. No need to special-case them. */
10541 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10542 (eq B (minus A C)), whichever simplifies. We can only do
10543 this for equality comparisons due to pathological cases involving
10545 if (equality_comparison_p
10546 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10547 XEXP (op0, 1), op1)))
10549 op0 = XEXP (op0, 0);
10554 if (equality_comparison_p
10555 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10556 XEXP (op0, 0), op1)))
10558 op0 = XEXP (op0, 1);
10563 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10564 of bits in X minus 1, is one iff X > 0. */
10565 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10566 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10567 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10568 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10570 op0 = XEXP (op0, 1);
10571 code = (code == GE ? LE : GT);
10577 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10578 if C is zero or B is a constant. */
10579 if (equality_comparison_p
10580 && 0 != (tem = simplify_binary_operation (XOR, mode,
10581 XEXP (op0, 1), op1)))
10583 op0 = XEXP (op0, 0);
10590 case LT: case LTU: case LE: case LEU:
10591 case GT: case GTU: case GE: case GEU:
10592 /* We can't do anything if OP0 is a condition code value, rather
10593 than an actual data value. */
10596 || XEXP (op0, 0) == cc0_rtx
10598 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10601 /* Get the two operands being compared. */
10602 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10603 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10605 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10607 /* Check for the cases where we simply want the result of the
10608 earlier test or the opposite of that result. */
10610 || (code == EQ && reversible_comparison_p (op0))
10611 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10612 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10613 && (STORE_FLAG_VALUE
10614 & (((HOST_WIDE_INT) 1
10615 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10617 || (code == GE && reversible_comparison_p (op0)))))
10619 code = (code == LT || code == NE
10620 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10621 op0 = tem, op1 = tem1;
10627 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10629 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10630 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10631 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10633 op0 = XEXP (op0, 1);
10634 code = (code == GE ? GT : LE);
10640 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10641 will be converted to a ZERO_EXTRACT later. */
10642 if (const_op == 0 && equality_comparison_p
10643 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10644 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10646 op0 = simplify_and_const_int
10647 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10649 XEXP (XEXP (op0, 0), 1)),
10650 (HOST_WIDE_INT) 1);
10654 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10655 zero and X is a comparison and C1 and C2 describe only bits set
10656 in STORE_FLAG_VALUE, we can compare with X. */
10657 if (const_op == 0 && equality_comparison_p
10658 && mode_width <= HOST_BITS_PER_WIDE_INT
10659 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10660 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10661 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10662 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10663 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10665 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10666 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10667 if ((~STORE_FLAG_VALUE & mask) == 0
10668 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10669 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10670 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10672 op0 = XEXP (XEXP (op0, 0), 0);
10677 /* If we are doing an equality comparison of an AND of a bit equal
10678 to the sign bit, replace this with a LT or GE comparison of
10679 the underlying value. */
10680 if (equality_comparison_p
10682 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10683 && mode_width <= HOST_BITS_PER_WIDE_INT
10684 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10685 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10687 op0 = XEXP (op0, 0);
10688 code = (code == EQ ? GE : LT);
10692 /* If this AND operation is really a ZERO_EXTEND from a narrower
10693 mode, the constant fits within that mode, and this is either an
10694 equality or unsigned comparison, try to do this comparison in
10695 the narrower mode. */
10696 if ((equality_comparison_p || unsigned_comparison_p)
10697 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10698 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10699 & GET_MODE_MASK (mode))
10701 && const_op >> i == 0
10702 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10704 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10708 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10709 in both M1 and M2 and the SUBREG is either paradoxical or
10710 represents the low part, permute the SUBREG and the AND and
10712 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10714 #ifdef WORD_REGISTER_OPERATIONS
10716 > (GET_MODE_BITSIZE
10717 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10718 && mode_width <= BITS_PER_WORD)
10721 <= (GET_MODE_BITSIZE
10722 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10723 && subreg_lowpart_p (XEXP (op0, 0))))
10724 #ifndef WORD_REGISTER_OPERATIONS
10725 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10726 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10727 As originally written the upper bits have a defined value
10728 due to the AND operation. However, if we commute the AND
10729 inside the SUBREG then they no longer have defined values
10730 and the meaning of the code has been changed. */
10731 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10732 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10734 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10735 && mode_width <= HOST_BITS_PER_WIDE_INT
10736 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10737 <= HOST_BITS_PER_WIDE_INT)
10738 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10739 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10740 & INTVAL (XEXP (op0, 1)))
10741 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10742 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10743 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10747 = gen_lowpart_for_combine
10749 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10750 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10757 /* If we have (compare (ashift FOO N) (const_int C)) and
10758 the high order N bits of FOO (N+1 if an inequality comparison)
10759 are known to be zero, we can do this by comparing FOO with C
10760 shifted right N bits so long as the low-order N bits of C are
10762 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10763 && INTVAL (XEXP (op0, 1)) >= 0
10764 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10765 < HOST_BITS_PER_WIDE_INT)
10767 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10768 && mode_width <= HOST_BITS_PER_WIDE_INT
10769 && (nonzero_bits (XEXP (op0, 0), mode)
10770 & ~(mask >> (INTVAL (XEXP (op0, 1))
10771 + ! equality_comparison_p))) == 0)
10773 /* We must perform a logical shift, not an arithmetic one,
10774 as we want the top N bits of C to be zero. */
10775 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10777 temp >>= INTVAL (XEXP (op0, 1));
10778 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10779 op0 = XEXP (op0, 0);
10783 /* If we are doing a sign bit comparison, it means we are testing
10784 a particular bit. Convert it to the appropriate AND. */
10785 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10786 && mode_width <= HOST_BITS_PER_WIDE_INT)
10788 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10791 - INTVAL (XEXP (op0, 1)))));
10792 code = (code == LT ? NE : EQ);
10796 /* If this an equality comparison with zero and we are shifting
10797 the low bit to the sign bit, we can convert this to an AND of the
10799 if (const_op == 0 && equality_comparison_p
10800 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10801 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10803 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10804 (HOST_WIDE_INT) 1);
10810 /* If this is an equality comparison with zero, we can do this
10811 as a logical shift, which might be much simpler. */
10812 if (equality_comparison_p && const_op == 0
10813 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10815 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10817 INTVAL (XEXP (op0, 1)));
10821 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10822 do the comparison in a narrower mode. */
10823 if (! unsigned_comparison_p
10824 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10825 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10826 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10827 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10828 MODE_INT, 1)) != BLKmode
10829 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10830 || ((unsigned HOST_WIDE_INT) -const_op
10831 <= GET_MODE_MASK (tmode))))
10833 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10837 /* Likewise if OP0 is a PLUS of a sign extension with a
10838 constant, which is usually represented with the PLUS
10839 between the shifts. */
10840 if (! unsigned_comparison_p
10841 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10842 && GET_CODE (XEXP (op0, 0)) == PLUS
10843 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10844 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10845 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10846 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10847 MODE_INT, 1)) != BLKmode
10848 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10849 || ((unsigned HOST_WIDE_INT) -const_op
10850 <= GET_MODE_MASK (tmode))))
10852 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10853 rtx add_const = XEXP (XEXP (op0, 0), 1);
10854 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10857 op0 = gen_binary (PLUS, tmode,
10858 gen_lowpart_for_combine (tmode, inner),
10863 /* ... fall through ... */
10865 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10866 the low order N bits of FOO are known to be zero, we can do this
10867 by comparing FOO with C shifted left N bits so long as no
10868 overflow occurs. */
10869 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10870 && INTVAL (XEXP (op0, 1)) >= 0
10871 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10872 && mode_width <= HOST_BITS_PER_WIDE_INT
10873 && (nonzero_bits (XEXP (op0, 0), mode)
10874 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10876 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10879 const_op <<= INTVAL (XEXP (op0, 1));
10880 op1 = GEN_INT (const_op);
10881 op0 = XEXP (op0, 0);
10885 /* If we are using this shift to extract just the sign bit, we
10886 can replace this with an LT or GE comparison. */
10888 && (equality_comparison_p || sign_bit_comparison_p)
10889 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10890 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10892 op0 = XEXP (op0, 0);
10893 code = (code == NE || code == GT ? LT : GE);
10905 /* Now make any compound operations involved in this comparison. Then,
10906 check for an outmost SUBREG on OP0 that is not doing anything or is
10907 paradoxical. The latter case can only occur when it is known that the
10908 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10909 We can never remove a SUBREG for a non-equality comparison because the
10910 sign bit is in a different place in the underlying object. */
10912 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10913 op1 = make_compound_operation (op1, SET);
10915 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10916 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10917 && (code == NE || code == EQ)
10918 && ((GET_MODE_SIZE (GET_MODE (op0))
10919 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10921 op0 = SUBREG_REG (op0);
10922 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10925 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10926 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10927 && (code == NE || code == EQ)
10928 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10929 <= HOST_BITS_PER_WIDE_INT)
10930 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10931 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10932 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10934 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10935 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10936 op0 = SUBREG_REG (op0), op1 = tem;
10938 /* We now do the opposite procedure: Some machines don't have compare
10939 insns in all modes. If OP0's mode is an integer mode smaller than a
10940 word and we can't do a compare in that mode, see if there is a larger
10941 mode for which we can do the compare. There are a number of cases in
10942 which we can use the wider mode. */
10944 mode = GET_MODE (op0);
10945 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10946 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10947 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10948 for (tmode = GET_MODE_WIDER_MODE (mode);
10950 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10951 tmode = GET_MODE_WIDER_MODE (tmode))
10952 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10954 /* If the only nonzero bits in OP0 and OP1 are those in the
10955 narrower mode and this is an equality or unsigned comparison,
10956 we can use the wider mode. Similarly for sign-extended
10957 values, in which case it is true for all comparisons. */
10958 if (((code == EQ || code == NE
10959 || code == GEU || code == GTU || code == LEU || code == LTU)
10960 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
10961 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
10962 || ((num_sign_bit_copies (op0, tmode)
10963 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10964 && (num_sign_bit_copies (op1, tmode)
10965 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10967 /* If OP0 is an AND and we don't have an AND in MODE either,
10968 make a new AND in the proper mode. */
10969 if (GET_CODE (op0) == AND
10970 && (add_optab->handlers[(int) mode].insn_code
10971 == CODE_FOR_nothing))
10972 op0 = gen_binary (AND, tmode,
10973 gen_lowpart_for_combine (tmode,
10975 gen_lowpart_for_combine (tmode,
10978 op0 = gen_lowpart_for_combine (tmode, op0);
10979 op1 = gen_lowpart_for_combine (tmode, op1);
10983 /* If this is a test for negative, we can make an explicit
10984 test of the sign bit. */
10986 if (op1 == const0_rtx && (code == LT || code == GE)
10987 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10989 op0 = gen_binary (AND, tmode,
10990 gen_lowpart_for_combine (tmode, op0),
10991 GEN_INT ((HOST_WIDE_INT) 1
10992 << (GET_MODE_BITSIZE (mode) - 1)));
10993 code = (code == LT) ? NE : EQ;
10998 #ifdef CANONICALIZE_COMPARISON
10999 /* If this machine only supports a subset of valid comparisons, see if we
11000 can convert an unsupported one into a supported one. */
11001 CANONICALIZE_COMPARISON (code, op0, op1);
11010 /* Return 1 if we know that X, a comparison operation, is not operating
11011 on a floating-point value or is EQ or NE, meaning that we can safely
11015 reversible_comparison_p (x)
11018 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
11020 || GET_CODE (x) == NE || GET_CODE (x) == EQ
11021 || GET_CODE (x) == UNORDERED || GET_CODE (x) == ORDERED)
11024 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
11027 case MODE_PARTIAL_INT:
11028 case MODE_COMPLEX_INT:
11032 /* If the mode of the condition codes tells us that this is safe,
11033 we need look no further. */
11034 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
11037 /* Otherwise try and find where the condition codes were last set and
11039 x = get_last_value (XEXP (x, 0));
11040 return (x && GET_CODE (x) == COMPARE
11041 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
11048 /* Utility function for following routine. Called when X is part of a value
11049 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11050 for each register mentioned. Similar to mention_regs in cse.c */
11053 update_table_tick (x)
11056 register enum rtx_code code = GET_CODE (x);
11057 register const char *fmt = GET_RTX_FORMAT (code);
11062 unsigned int regno = REGNO (x);
11063 unsigned int endregno
11064 = regno + (regno < FIRST_PSEUDO_REGISTER
11065 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11068 for (r = regno; r < endregno; r++)
11069 reg_last_set_table_tick[r] = label_tick;
11074 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11075 /* Note that we can't have an "E" in values stored; see
11076 get_last_value_validate. */
11078 update_table_tick (XEXP (x, i));
11081 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11082 are saying that the register is clobbered and we no longer know its
11083 value. If INSN is zero, don't update reg_last_set; this is only permitted
11084 with VALUE also zero and is used to invalidate the register. */
11087 record_value_for_reg (reg, insn, value)
11092 unsigned int regno = REGNO (reg);
11093 unsigned int endregno
11094 = regno + (regno < FIRST_PSEUDO_REGISTER
11095 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11098 /* If VALUE contains REG and we have a previous value for REG, substitute
11099 the previous value. */
11100 if (value && insn && reg_overlap_mentioned_p (reg, value))
11104 /* Set things up so get_last_value is allowed to see anything set up to
11106 subst_low_cuid = INSN_CUID (insn);
11107 tem = get_last_value (reg);
11109 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11110 it isn't going to be useful and will take a lot of time to process,
11111 so just use the CLOBBER. */
11115 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11116 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11117 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11118 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11119 tem = XEXP (tem, 0);
11121 value = replace_rtx (copy_rtx (value), reg, tem);
11125 /* For each register modified, show we don't know its value, that
11126 we don't know about its bitwise content, that its value has been
11127 updated, and that we don't know the location of the death of the
11129 for (i = regno; i < endregno; i++)
11132 reg_last_set[i] = insn;
11134 reg_last_set_value[i] = 0;
11135 reg_last_set_mode[i] = 0;
11136 reg_last_set_nonzero_bits[i] = 0;
11137 reg_last_set_sign_bit_copies[i] = 0;
11138 reg_last_death[i] = 0;
11141 /* Mark registers that are being referenced in this value. */
11143 update_table_tick (value);
11145 /* Now update the status of each register being set.
11146 If someone is using this register in this block, set this register
11147 to invalid since we will get confused between the two lives in this
11148 basic block. This makes using this register always invalid. In cse, we
11149 scan the table to invalidate all entries using this register, but this
11150 is too much work for us. */
11152 for (i = regno; i < endregno; i++)
11154 reg_last_set_label[i] = label_tick;
11155 if (value && reg_last_set_table_tick[i] == label_tick)
11156 reg_last_set_invalid[i] = 1;
11158 reg_last_set_invalid[i] = 0;
11161 /* The value being assigned might refer to X (like in "x++;"). In that
11162 case, we must replace it with (clobber (const_int 0)) to prevent
11164 if (value && ! get_last_value_validate (&value, insn,
11165 reg_last_set_label[regno], 0))
11167 value = copy_rtx (value);
11168 if (! get_last_value_validate (&value, insn,
11169 reg_last_set_label[regno], 1))
11173 /* For the main register being modified, update the value, the mode, the
11174 nonzero bits, and the number of sign bit copies. */
11176 reg_last_set_value[regno] = value;
11180 subst_low_cuid = INSN_CUID (insn);
11181 reg_last_set_mode[regno] = GET_MODE (reg);
11182 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11183 reg_last_set_sign_bit_copies[regno]
11184 = num_sign_bit_copies (value, GET_MODE (reg));
11188 /* Called via note_stores from record_dead_and_set_regs to handle one
11189 SET or CLOBBER in an insn. DATA is the instruction in which the
11190 set is occurring. */
11193 record_dead_and_set_regs_1 (dest, setter, data)
11197 rtx record_dead_insn = (rtx) data;
11199 if (GET_CODE (dest) == SUBREG)
11200 dest = SUBREG_REG (dest);
11202 if (GET_CODE (dest) == REG)
11204 /* If we are setting the whole register, we know its value. Otherwise
11205 show that we don't know the value. We can handle SUBREG in
11207 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11208 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11209 else if (GET_CODE (setter) == SET
11210 && GET_CODE (SET_DEST (setter)) == SUBREG
11211 && SUBREG_REG (SET_DEST (setter)) == dest
11212 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11213 && subreg_lowpart_p (SET_DEST (setter)))
11214 record_value_for_reg (dest, record_dead_insn,
11215 gen_lowpart_for_combine (GET_MODE (dest),
11216 SET_SRC (setter)));
11218 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11220 else if (GET_CODE (dest) == MEM
11221 /* Ignore pushes, they clobber nothing. */
11222 && ! push_operand (dest, GET_MODE (dest)))
11223 mem_last_set = INSN_CUID (record_dead_insn);
11226 /* Update the records of when each REG was most recently set or killed
11227 for the things done by INSN. This is the last thing done in processing
11228 INSN in the combiner loop.
11230 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11231 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11232 and also the similar information mem_last_set (which insn most recently
11233 modified memory) and last_call_cuid (which insn was the most recent
11234 subroutine call). */
11237 record_dead_and_set_regs (insn)
11243 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11245 if (REG_NOTE_KIND (link) == REG_DEAD
11246 && GET_CODE (XEXP (link, 0)) == REG)
11248 unsigned int regno = REGNO (XEXP (link, 0));
11249 unsigned int endregno
11250 = regno + (regno < FIRST_PSEUDO_REGISTER
11251 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11254 for (i = regno; i < endregno; i++)
11255 reg_last_death[i] = insn;
11257 else if (REG_NOTE_KIND (link) == REG_INC)
11258 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11261 if (GET_CODE (insn) == CALL_INSN)
11263 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11264 if (call_used_regs[i])
11266 reg_last_set_value[i] = 0;
11267 reg_last_set_mode[i] = 0;
11268 reg_last_set_nonzero_bits[i] = 0;
11269 reg_last_set_sign_bit_copies[i] = 0;
11270 reg_last_death[i] = 0;
11273 last_call_cuid = mem_last_set = INSN_CUID (insn);
11276 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11279 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11280 register present in the SUBREG, so for each such SUBREG go back and
11281 adjust nonzero and sign bit information of the registers that are
11282 known to have some zero/sign bits set.
11284 This is needed because when combine blows the SUBREGs away, the
11285 information on zero/sign bits is lost and further combines can be
11286 missed because of that. */
11289 record_promoted_value (insn, subreg)
11294 unsigned int regno = REGNO (SUBREG_REG (subreg));
11295 enum machine_mode mode = GET_MODE (subreg);
11297 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11300 for (links = LOG_LINKS (insn); links;)
11302 insn = XEXP (links, 0);
11303 set = single_set (insn);
11305 if (! set || GET_CODE (SET_DEST (set)) != REG
11306 || REGNO (SET_DEST (set)) != regno
11307 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11309 links = XEXP (links, 1);
11313 if (reg_last_set[regno] == insn)
11315 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11316 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11319 if (GET_CODE (SET_SRC (set)) == REG)
11321 regno = REGNO (SET_SRC (set));
11322 links = LOG_LINKS (insn);
11329 /* Scan X for promoted SUBREGs. For each one found,
11330 note what it implies to the registers used in it. */
11333 check_promoted_subreg (insn, x)
11337 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11338 && GET_CODE (SUBREG_REG (x)) == REG)
11339 record_promoted_value (insn, x);
11342 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11345 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11349 check_promoted_subreg (insn, XEXP (x, i));
11353 if (XVEC (x, i) != 0)
11354 for (j = 0; j < XVECLEN (x, i); j++)
11355 check_promoted_subreg (insn, XVECEXP (x, i, j));
11361 /* Utility routine for the following function. Verify that all the registers
11362 mentioned in *LOC are valid when *LOC was part of a value set when
11363 label_tick == TICK. Return 0 if some are not.
11365 If REPLACE is non-zero, replace the invalid reference with
11366 (clobber (const_int 0)) and return 1. This replacement is useful because
11367 we often can get useful information about the form of a value (e.g., if
11368 it was produced by a shift that always produces -1 or 0) even though
11369 we don't know exactly what registers it was produced from. */
11372 get_last_value_validate (loc, insn, tick, replace)
11379 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11380 int len = GET_RTX_LENGTH (GET_CODE (x));
11383 if (GET_CODE (x) == REG)
11385 unsigned int regno = REGNO (x);
11386 unsigned int endregno
11387 = regno + (regno < FIRST_PSEUDO_REGISTER
11388 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11391 for (j = regno; j < endregno; j++)
11392 if (reg_last_set_invalid[j]
11393 /* If this is a pseudo-register that was only set once and not
11394 live at the beginning of the function, it is always valid. */
11395 || (! (regno >= FIRST_PSEUDO_REGISTER
11396 && REG_N_SETS (regno) == 1
11397 && (! REGNO_REG_SET_P
11398 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11399 && reg_last_set_label[j] > tick))
11402 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11408 /* If this is a memory reference, make sure that there were
11409 no stores after it that might have clobbered the value. We don't
11410 have alias info, so we assume any store invalidates it. */
11411 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11412 && INSN_CUID (insn) <= mem_last_set)
11415 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11419 for (i = 0; i < len; i++)
11421 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11422 /* Don't bother with these. They shouldn't occur anyway. */
11426 /* If we haven't found a reason for it to be invalid, it is valid. */
11430 /* Get the last value assigned to X, if known. Some registers
11431 in the value may be replaced with (clobber (const_int 0)) if their value
11432 is known longer known reliably. */
11438 unsigned int regno;
11441 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11442 then convert it to the desired mode. If this is a paradoxical SUBREG,
11443 we cannot predict what values the "extra" bits might have. */
11444 if (GET_CODE (x) == SUBREG
11445 && subreg_lowpart_p (x)
11446 && (GET_MODE_SIZE (GET_MODE (x))
11447 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11448 && (value = get_last_value (SUBREG_REG (x))) != 0)
11449 return gen_lowpart_for_combine (GET_MODE (x), value);
11451 if (GET_CODE (x) != REG)
11455 value = reg_last_set_value[regno];
11457 /* If we don't have a value, or if it isn't for this basic block and
11458 it's either a hard register, set more than once, or it's a live
11459 at the beginning of the function, return 0.
11461 Because if it's not live at the beginnning of the function then the reg
11462 is always set before being used (is never used without being set).
11463 And, if it's set only once, and it's always set before use, then all
11464 uses must have the same last value, even if it's not from this basic
11468 || (reg_last_set_label[regno] != label_tick
11469 && (regno < FIRST_PSEUDO_REGISTER
11470 || REG_N_SETS (regno) != 1
11471 || (REGNO_REG_SET_P
11472 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11475 /* If the value was set in a later insn than the ones we are processing,
11476 we can't use it even if the register was only set once. */
11477 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11480 /* If the value has all its registers valid, return it. */
11481 if (get_last_value_validate (&value, reg_last_set[regno],
11482 reg_last_set_label[regno], 0))
11485 /* Otherwise, make a copy and replace any invalid register with
11486 (clobber (const_int 0)). If that fails for some reason, return 0. */
11488 value = copy_rtx (value);
11489 if (get_last_value_validate (&value, reg_last_set[regno],
11490 reg_last_set_label[regno], 1))
11496 /* Return nonzero if expression X refers to a REG or to memory
11497 that is set in an instruction more recent than FROM_CUID. */
11500 use_crosses_set_p (x, from_cuid)
11504 register const char *fmt;
11506 register enum rtx_code code = GET_CODE (x);
11510 unsigned int regno = REGNO (x);
11511 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11512 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11514 #ifdef PUSH_ROUNDING
11515 /* Don't allow uses of the stack pointer to be moved,
11516 because we don't know whether the move crosses a push insn. */
11517 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11520 for (; regno < endreg; regno++)
11521 if (reg_last_set[regno]
11522 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11527 if (code == MEM && mem_last_set > from_cuid)
11530 fmt = GET_RTX_FORMAT (code);
11532 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11537 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11538 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11541 else if (fmt[i] == 'e'
11542 && use_crosses_set_p (XEXP (x, i), from_cuid))
11548 /* Define three variables used for communication between the following
11551 static unsigned int reg_dead_regno, reg_dead_endregno;
11552 static int reg_dead_flag;
11554 /* Function called via note_stores from reg_dead_at_p.
11556 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11557 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11560 reg_dead_at_p_1 (dest, x, data)
11563 void *data ATTRIBUTE_UNUSED;
11565 unsigned int regno, endregno;
11567 if (GET_CODE (dest) != REG)
11570 regno = REGNO (dest);
11571 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11572 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11574 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11575 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11578 /* Return non-zero if REG is known to be dead at INSN.
11580 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11581 referencing REG, it is dead. If we hit a SET referencing REG, it is
11582 live. Otherwise, see if it is live or dead at the start of the basic
11583 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11584 must be assumed to be always live. */
11587 reg_dead_at_p (reg, insn)
11594 /* Set variables for reg_dead_at_p_1. */
11595 reg_dead_regno = REGNO (reg);
11596 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11597 ? HARD_REGNO_NREGS (reg_dead_regno,
11603 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11604 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11606 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11607 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11611 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11612 beginning of function. */
11613 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11614 insn = prev_nonnote_insn (insn))
11616 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11618 return reg_dead_flag == 1 ? 1 : 0;
11620 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11624 /* Get the basic block number that we were in. */
11629 for (block = 0; block < n_basic_blocks; block++)
11630 if (insn == BLOCK_HEAD (block))
11633 if (block == n_basic_blocks)
11637 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11638 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11644 /* Note hard registers in X that are used. This code is similar to
11645 that in flow.c, but much simpler since we don't care about pseudos. */
11648 mark_used_regs_combine (x)
11651 RTX_CODE code = GET_CODE (x);
11652 unsigned int regno;
11664 case ADDR_DIFF_VEC:
11667 /* CC0 must die in the insn after it is set, so we don't need to take
11668 special note of it here. */
11674 /* If we are clobbering a MEM, mark any hard registers inside the
11675 address as used. */
11676 if (GET_CODE (XEXP (x, 0)) == MEM)
11677 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11682 /* A hard reg in a wide mode may really be multiple registers.
11683 If so, mark all of them just like the first. */
11684 if (regno < FIRST_PSEUDO_REGISTER)
11686 unsigned int endregno, r;
11688 /* None of this applies to the stack, frame or arg pointers */
11689 if (regno == STACK_POINTER_REGNUM
11690 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11691 || regno == HARD_FRAME_POINTER_REGNUM
11693 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11694 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11696 || regno == FRAME_POINTER_REGNUM)
11699 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11700 for (r = regno; r < endregno; r++)
11701 SET_HARD_REG_BIT (newpat_used_regs, r);
11707 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11709 register rtx testreg = SET_DEST (x);
11711 while (GET_CODE (testreg) == SUBREG
11712 || GET_CODE (testreg) == ZERO_EXTRACT
11713 || GET_CODE (testreg) == SIGN_EXTRACT
11714 || GET_CODE (testreg) == STRICT_LOW_PART)
11715 testreg = XEXP (testreg, 0);
11717 if (GET_CODE (testreg) == MEM)
11718 mark_used_regs_combine (XEXP (testreg, 0));
11720 mark_used_regs_combine (SET_SRC (x));
11728 /* Recursively scan the operands of this expression. */
11731 register const char *fmt = GET_RTX_FORMAT (code);
11733 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11736 mark_used_regs_combine (XEXP (x, i));
11737 else if (fmt[i] == 'E')
11741 for (j = 0; j < XVECLEN (x, i); j++)
11742 mark_used_regs_combine (XVECEXP (x, i, j));
11748 /* Remove register number REGNO from the dead registers list of INSN.
11750 Return the note used to record the death, if there was one. */
11753 remove_death (regno, insn)
11754 unsigned int regno;
11757 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11761 REG_N_DEATHS (regno)--;
11762 remove_note (insn, note);
11768 /* For each register (hardware or pseudo) used within expression X, if its
11769 death is in an instruction with cuid between FROM_CUID (inclusive) and
11770 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11771 list headed by PNOTES.
11773 That said, don't move registers killed by maybe_kill_insn.
11775 This is done when X is being merged by combination into TO_INSN. These
11776 notes will then be distributed as needed. */
11779 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11781 rtx maybe_kill_insn;
11786 register const char *fmt;
11787 register int len, i;
11788 register enum rtx_code code = GET_CODE (x);
11792 unsigned int regno = REGNO (x);
11793 register rtx where_dead = reg_last_death[regno];
11794 register rtx before_dead, after_dead;
11796 /* Don't move the register if it gets killed in between from and to */
11797 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11798 && ! reg_referenced_p (x, maybe_kill_insn))
11801 /* WHERE_DEAD could be a USE insn made by combine, so first we
11802 make sure that we have insns with valid INSN_CUID values. */
11803 before_dead = where_dead;
11804 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11805 before_dead = PREV_INSN (before_dead);
11807 after_dead = where_dead;
11808 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11809 after_dead = NEXT_INSN (after_dead);
11811 if (before_dead && after_dead
11812 && INSN_CUID (before_dead) >= from_cuid
11813 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11814 || (where_dead != after_dead
11815 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11817 rtx note = remove_death (regno, where_dead);
11819 /* It is possible for the call above to return 0. This can occur
11820 when reg_last_death points to I2 or I1 that we combined with.
11821 In that case make a new note.
11823 We must also check for the case where X is a hard register
11824 and NOTE is a death note for a range of hard registers
11825 including X. In that case, we must put REG_DEAD notes for
11826 the remaining registers in place of NOTE. */
11828 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11829 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11830 > GET_MODE_SIZE (GET_MODE (x))))
11832 unsigned int deadregno = REGNO (XEXP (note, 0));
11833 unsigned int deadend
11834 = (deadregno + HARD_REGNO_NREGS (deadregno,
11835 GET_MODE (XEXP (note, 0))));
11836 unsigned int ourend
11837 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11840 for (i = deadregno; i < deadend; i++)
11841 if (i < regno || i >= ourend)
11842 REG_NOTES (where_dead)
11843 = gen_rtx_EXPR_LIST (REG_DEAD,
11844 gen_rtx_REG (reg_raw_mode[i], i),
11845 REG_NOTES (where_dead));
11848 /* If we didn't find any note, or if we found a REG_DEAD note that
11849 covers only part of the given reg, and we have a multi-reg hard
11850 register, then to be safe we must check for REG_DEAD notes
11851 for each register other than the first. They could have
11852 their own REG_DEAD notes lying around. */
11853 else if ((note == 0
11855 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11856 < GET_MODE_SIZE (GET_MODE (x)))))
11857 && regno < FIRST_PSEUDO_REGISTER
11858 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11860 unsigned int ourend
11861 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11862 unsigned int i, offset;
11866 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11870 for (i = regno + offset; i < ourend; i++)
11871 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11872 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11875 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11877 XEXP (note, 1) = *pnotes;
11881 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11883 REG_N_DEATHS (regno)++;
11889 else if (GET_CODE (x) == SET)
11891 rtx dest = SET_DEST (x);
11893 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11895 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11896 that accesses one word of a multi-word item, some
11897 piece of everything register in the expression is used by
11898 this insn, so remove any old death. */
11900 if (GET_CODE (dest) == ZERO_EXTRACT
11901 || GET_CODE (dest) == STRICT_LOW_PART
11902 || (GET_CODE (dest) == SUBREG
11903 && (((GET_MODE_SIZE (GET_MODE (dest))
11904 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11905 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11906 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11908 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11912 /* If this is some other SUBREG, we know it replaces the entire
11913 value, so use that as the destination. */
11914 if (GET_CODE (dest) == SUBREG)
11915 dest = SUBREG_REG (dest);
11917 /* If this is a MEM, adjust deaths of anything used in the address.
11918 For a REG (the only other possibility), the entire value is
11919 being replaced so the old value is not used in this insn. */
11921 if (GET_CODE (dest) == MEM)
11922 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11927 else if (GET_CODE (x) == CLOBBER)
11930 len = GET_RTX_LENGTH (code);
11931 fmt = GET_RTX_FORMAT (code);
11933 for (i = 0; i < len; i++)
11938 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11939 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11942 else if (fmt[i] == 'e')
11943 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11947 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11948 pattern of an insn. X must be a REG. */
11951 reg_bitfield_target_p (x, body)
11957 if (GET_CODE (body) == SET)
11959 rtx dest = SET_DEST (body);
11961 unsigned int regno, tregno, endregno, endtregno;
11963 if (GET_CODE (dest) == ZERO_EXTRACT)
11964 target = XEXP (dest, 0);
11965 else if (GET_CODE (dest) == STRICT_LOW_PART)
11966 target = SUBREG_REG (XEXP (dest, 0));
11970 if (GET_CODE (target) == SUBREG)
11971 target = SUBREG_REG (target);
11973 if (GET_CODE (target) != REG)
11976 tregno = REGNO (target), regno = REGNO (x);
11977 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11978 return target == x;
11980 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11981 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11983 return endregno > tregno && regno < endtregno;
11986 else if (GET_CODE (body) == PARALLEL)
11987 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11988 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11994 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11995 as appropriate. I3 and I2 are the insns resulting from the combination
11996 insns including FROM (I2 may be zero).
11998 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11999 not need REG_DEAD notes because they are being substituted for. This
12000 saves searching in the most common cases.
12002 Each note in the list is either ignored or placed on some insns, depending
12003 on the type of note. */
12006 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12010 rtx elim_i2, elim_i1;
12012 rtx note, next_note;
12015 for (note = notes; note; note = next_note)
12017 rtx place = 0, place2 = 0;
12019 /* If this NOTE references a pseudo register, ensure it references
12020 the latest copy of that register. */
12021 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12022 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12023 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12025 next_note = XEXP (note, 1);
12026 switch (REG_NOTE_KIND (note))
12029 case REG_EXEC_COUNT:
12030 /* Doesn't matter much where we put this, as long as it's somewhere.
12031 It is preferable to keep these notes on branches, which is most
12032 likely to be i3. */
12036 case REG_EH_REGION:
12037 case REG_EH_RETHROW:
12038 /* These notes must remain with the call. It should not be
12039 possible for both I2 and I3 to be a call. */
12040 if (GET_CODE (i3) == CALL_INSN)
12042 else if (i2 && GET_CODE (i2) == CALL_INSN)
12049 /* Any clobbers for i3 may still exist, and so we must process
12050 REG_UNUSED notes from that insn.
12052 Any clobbers from i2 or i1 can only exist if they were added by
12053 recog_for_combine. In that case, recog_for_combine created the
12054 necessary REG_UNUSED notes. Trying to keep any original
12055 REG_UNUSED notes from these insns can cause incorrect output
12056 if it is for the same register as the original i3 dest.
12057 In that case, we will notice that the register is set in i3,
12058 and then add a REG_UNUSED note for the destination of i3, which
12059 is wrong. However, it is possible to have REG_UNUSED notes from
12060 i2 or i1 for register which were both used and clobbered, so
12061 we keep notes from i2 or i1 if they will turn into REG_DEAD
12064 /* If this register is set or clobbered in I3, put the note there
12065 unless there is one already. */
12066 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12068 if (from_insn != i3)
12071 if (! (GET_CODE (XEXP (note, 0)) == REG
12072 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12073 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12076 /* Otherwise, if this register is used by I3, then this register
12077 now dies here, so we must put a REG_DEAD note here unless there
12079 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12080 && ! (GET_CODE (XEXP (note, 0)) == REG
12081 ? find_regno_note (i3, REG_DEAD,
12082 REGNO (XEXP (note, 0)))
12083 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12085 PUT_REG_NOTE_KIND (note, REG_DEAD);
12093 /* These notes say something about results of an insn. We can
12094 only support them if they used to be on I3 in which case they
12095 remain on I3. Otherwise they are ignored.
12097 If the note refers to an expression that is not a constant, we
12098 must also ignore the note since we cannot tell whether the
12099 equivalence is still true. It might be possible to do
12100 slightly better than this (we only have a problem if I2DEST
12101 or I1DEST is present in the expression), but it doesn't
12102 seem worth the trouble. */
12104 if (from_insn == i3
12105 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12110 case REG_NO_CONFLICT:
12111 /* These notes say something about how a register is used. They must
12112 be present on any use of the register in I2 or I3. */
12113 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12116 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12126 /* This can show up in several ways -- either directly in the
12127 pattern, or hidden off in the constant pool with (or without?)
12128 a REG_EQUAL note. */
12129 /* ??? Ignore the without-reg_equal-note problem for now. */
12130 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12131 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12132 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12133 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12137 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12138 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12139 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12140 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12151 /* These notes say something about the value of a register prior
12152 to the execution of an insn. It is too much trouble to see
12153 if the note is still correct in all situations. It is better
12154 to simply delete it. */
12158 /* If the insn previously containing this note still exists,
12159 put it back where it was. Otherwise move it to the previous
12160 insn. Adjust the corresponding REG_LIBCALL note. */
12161 if (GET_CODE (from_insn) != NOTE)
12165 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12166 place = prev_real_insn (from_insn);
12168 XEXP (tem, 0) = place;
12173 /* This is handled similarly to REG_RETVAL. */
12174 if (GET_CODE (from_insn) != NOTE)
12178 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12179 place = next_real_insn (from_insn);
12181 XEXP (tem, 0) = place;
12186 /* If the register is used as an input in I3, it dies there.
12187 Similarly for I2, if it is non-zero and adjacent to I3.
12189 If the register is not used as an input in either I3 or I2
12190 and it is not one of the registers we were supposed to eliminate,
12191 there are two possibilities. We might have a non-adjacent I2
12192 or we might have somehow eliminated an additional register
12193 from a computation. For example, we might have had A & B where
12194 we discover that B will always be zero. In this case we will
12195 eliminate the reference to A.
12197 In both cases, we must search to see if we can find a previous
12198 use of A and put the death note there. */
12201 && GET_CODE (from_insn) == CALL_INSN
12202 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12204 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12206 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12207 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12210 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
12215 basic_block bb = BASIC_BLOCK (this_basic_block);
12217 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12219 if (! INSN_P (tem))
12221 if (tem == bb->head)
12226 /* If the register is being set at TEM, see if that is all
12227 TEM is doing. If so, delete TEM. Otherwise, make this
12228 into a REG_UNUSED note instead. */
12229 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12231 rtx set = single_set (tem);
12232 rtx inner_dest = 0;
12234 rtx cc0_setter = NULL_RTX;
12238 for (inner_dest = SET_DEST (set);
12239 (GET_CODE (inner_dest) == STRICT_LOW_PART
12240 || GET_CODE (inner_dest) == SUBREG
12241 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12242 inner_dest = XEXP (inner_dest, 0))
12245 /* Verify that it was the set, and not a clobber that
12246 modified the register.
12248 CC0 targets must be careful to maintain setter/user
12249 pairs. If we cannot delete the setter due to side
12250 effects, mark the user with an UNUSED note instead
12253 if (set != 0 && ! side_effects_p (SET_SRC (set))
12254 && rtx_equal_p (XEXP (note, 0), inner_dest)
12256 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12257 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12258 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12262 /* Move the notes and links of TEM elsewhere.
12263 This might delete other dead insns recursively.
12264 First set the pattern to something that won't use
12267 PATTERN (tem) = pc_rtx;
12269 distribute_notes (REG_NOTES (tem), tem, tem,
12270 NULL_RTX, NULL_RTX, NULL_RTX);
12271 distribute_links (LOG_LINKS (tem));
12273 PUT_CODE (tem, NOTE);
12274 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12275 NOTE_SOURCE_FILE (tem) = 0;
12278 /* Delete the setter too. */
12281 PATTERN (cc0_setter) = pc_rtx;
12283 distribute_notes (REG_NOTES (cc0_setter),
12284 cc0_setter, cc0_setter,
12285 NULL_RTX, NULL_RTX, NULL_RTX);
12286 distribute_links (LOG_LINKS (cc0_setter));
12288 PUT_CODE (cc0_setter, NOTE);
12289 NOTE_LINE_NUMBER (cc0_setter)
12290 = NOTE_INSN_DELETED;
12291 NOTE_SOURCE_FILE (cc0_setter) = 0;
12295 /* If the register is both set and used here, put the
12296 REG_DEAD note here, but place a REG_UNUSED note
12297 here too unless there already is one. */
12298 else if (reg_referenced_p (XEXP (note, 0),
12303 if (! find_regno_note (tem, REG_UNUSED,
12304 REGNO (XEXP (note, 0))))
12306 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12311 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12313 /* If there isn't already a REG_UNUSED note, put one
12315 if (! find_regno_note (tem, REG_UNUSED,
12316 REGNO (XEXP (note, 0))))
12321 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12322 || (GET_CODE (tem) == CALL_INSN
12323 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12327 /* If we are doing a 3->2 combination, and we have a
12328 register which formerly died in i3 and was not used
12329 by i2, which now no longer dies in i3 and is used in
12330 i2 but does not die in i2, and place is between i2
12331 and i3, then we may need to move a link from place to
12333 if (i2 && INSN_UID (place) <= max_uid_cuid
12334 && INSN_CUID (place) > INSN_CUID (i2)
12336 && INSN_CUID (from_insn) > INSN_CUID (i2)
12337 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12339 rtx links = LOG_LINKS (place);
12340 LOG_LINKS (place) = 0;
12341 distribute_links (links);
12346 if (tem == bb->head)
12350 /* We haven't found an insn for the death note and it
12351 is still a REG_DEAD note, but we have hit the beginning
12352 of the block. If the existing life info says the reg
12353 was dead, there's nothing left to do. Otherwise, we'll
12354 need to do a global life update after combine. */
12355 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12356 && REGNO_REG_SET_P (bb->global_live_at_start,
12357 REGNO (XEXP (note, 0))))
12359 SET_BIT (refresh_blocks, this_basic_block);
12364 /* If the register is set or already dead at PLACE, we needn't do
12365 anything with this note if it is still a REG_DEAD note.
12366 We can here if it is set at all, not if is it totally replace,
12367 which is what `dead_or_set_p' checks, so also check for it being
12370 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12372 unsigned int regno = REGNO (XEXP (note, 0));
12374 if (dead_or_set_p (place, XEXP (note, 0))
12375 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12377 /* Unless the register previously died in PLACE, clear
12378 reg_last_death. [I no longer understand why this is
12380 if (reg_last_death[regno] != place)
12381 reg_last_death[regno] = 0;
12385 reg_last_death[regno] = place;
12387 /* If this is a death note for a hard reg that is occupying
12388 multiple registers, ensure that we are still using all
12389 parts of the object. If we find a piece of the object
12390 that is unused, we must add a USE for that piece before
12391 PLACE and put the appropriate REG_DEAD note on it.
12393 An alternative would be to put a REG_UNUSED for the pieces
12394 on the insn that set the register, but that can't be done if
12395 it is not in the same block. It is simpler, though less
12396 efficient, to add the USE insns. */
12398 if (place && regno < FIRST_PSEUDO_REGISTER
12399 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12401 unsigned int endregno
12402 = regno + HARD_REGNO_NREGS (regno,
12403 GET_MODE (XEXP (note, 0)));
12407 for (i = regno; i < endregno; i++)
12408 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12409 && ! find_regno_fusage (place, USE, i))
12411 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12414 /* See if we already placed a USE note for this
12415 register in front of PLACE. */
12417 GET_CODE (PREV_INSN (p)) == INSN
12418 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
12420 if (rtx_equal_p (piece,
12421 XEXP (PATTERN (PREV_INSN (p)), 0)))
12430 = emit_insn_before (gen_rtx_USE (VOIDmode,
12433 REG_NOTES (use_insn)
12434 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12435 REG_NOTES (use_insn));
12441 /* Check for the case where the register dying partially
12442 overlaps the register set by this insn. */
12444 for (i = regno; i < endregno; i++)
12445 if (dead_or_set_regno_p (place, i))
12453 /* Put only REG_DEAD notes for pieces that are
12454 still used and that are not already dead or set. */
12456 for (i = regno; i < endregno; i++)
12458 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12460 if ((reg_referenced_p (piece, PATTERN (place))
12461 || (GET_CODE (place) == CALL_INSN
12462 && find_reg_fusage (place, USE, piece)))
12463 && ! dead_or_set_p (place, piece)
12464 && ! reg_bitfield_target_p (piece,
12467 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
12468 REG_NOTES (place));
12478 /* Any other notes should not be present at this point in the
12485 XEXP (note, 1) = REG_NOTES (place);
12486 REG_NOTES (place) = note;
12488 else if ((REG_NOTE_KIND (note) == REG_DEAD
12489 || REG_NOTE_KIND (note) == REG_UNUSED)
12490 && GET_CODE (XEXP (note, 0)) == REG)
12491 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12495 if ((REG_NOTE_KIND (note) == REG_DEAD
12496 || REG_NOTE_KIND (note) == REG_UNUSED)
12497 && GET_CODE (XEXP (note, 0)) == REG)
12498 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12500 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12501 REG_NOTE_KIND (note),
12503 REG_NOTES (place2));
12508 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12509 I3, I2, and I1 to new locations. This is also called in one case to
12510 add a link pointing at I3 when I3's destination is changed. */
12513 distribute_links (links)
12516 rtx link, next_link;
12518 for (link = links; link; link = next_link)
12524 next_link = XEXP (link, 1);
12526 /* If the insn that this link points to is a NOTE or isn't a single
12527 set, ignore it. In the latter case, it isn't clear what we
12528 can do other than ignore the link, since we can't tell which
12529 register it was for. Such links wouldn't be used by combine
12532 It is not possible for the destination of the target of the link to
12533 have been changed by combine. The only potential of this is if we
12534 replace I3, I2, and I1 by I3 and I2. But in that case the
12535 destination of I2 also remains unchanged. */
12537 if (GET_CODE (XEXP (link, 0)) == NOTE
12538 || (set = single_set (XEXP (link, 0))) == 0)
12541 reg = SET_DEST (set);
12542 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12543 || GET_CODE (reg) == SIGN_EXTRACT
12544 || GET_CODE (reg) == STRICT_LOW_PART)
12545 reg = XEXP (reg, 0);
12547 /* A LOG_LINK is defined as being placed on the first insn that uses
12548 a register and points to the insn that sets the register. Start
12549 searching at the next insn after the target of the link and stop
12550 when we reach a set of the register or the end of the basic block.
12552 Note that this correctly handles the link that used to point from
12553 I3 to I2. Also note that not much searching is typically done here
12554 since most links don't point very far away. */
12556 for (insn = NEXT_INSN (XEXP (link, 0));
12557 (insn && (this_basic_block == n_basic_blocks - 1
12558 || BLOCK_HEAD (this_basic_block + 1) != insn));
12559 insn = NEXT_INSN (insn))
12560 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12562 if (reg_referenced_p (reg, PATTERN (insn)))
12566 else if (GET_CODE (insn) == CALL_INSN
12567 && find_reg_fusage (insn, USE, reg))
12573 /* If we found a place to put the link, place it there unless there
12574 is already a link to the same insn as LINK at that point. */
12580 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12581 if (XEXP (link2, 0) == XEXP (link, 0))
12586 XEXP (link, 1) = LOG_LINKS (place);
12587 LOG_LINKS (place) = link;
12589 /* Set added_links_insn to the earliest insn we added a
12591 if (added_links_insn == 0
12592 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12593 added_links_insn = place;
12599 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12605 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12606 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12607 insn = NEXT_INSN (insn);
12609 if (INSN_UID (insn) > max_uid_cuid)
12612 return INSN_CUID (insn);
12616 dump_combine_stats (file)
12621 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12622 combine_attempts, combine_merges, combine_extras, combine_successes);
12626 dump_combine_total_stats (file)
12631 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12632 total_attempts, total_merges, total_extras, total_successes);