1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
82 #include "basic-block.h"
83 #include "insn-config.h"
84 #include "insn-flags.h"
85 #include "insn-codes.h"
86 #include "insn-attr.h"
91 /* It is not safe to use ordinary gen_lowpart in combine.
92 Use gen_lowpart_for_combine instead. See comments there. */
93 #define gen_lowpart dont_use_gen_lowpart_you_dummy
95 /* Number of attempts to combine instructions in this function. */
97 static int combine_attempts;
99 /* Number of attempts that got as far as substitution in this function. */
101 static int combine_merges;
103 /* Number of instructions combined with added SETs in this function. */
105 static int combine_extras;
107 /* Number of instructions combined in this function. */
109 static int combine_successes;
111 /* Totals over entire compilation. */
113 static int total_attempts, total_merges, total_extras, total_successes;
115 /* Vector mapping INSN_UIDs to cuids.
116 The cuids are like uids but increase monotonically always.
117 Combine always uses cuids so that it can compare them.
118 But actually renumbering the uids, which we used to do,
119 proves to be a bad idea because it makes it hard to compare
120 the dumps produced by earlier passes with those from later passes. */
122 static int *uid_cuid;
124 /* Get the cuid of an insn. */
126 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
128 /* Maximum register number, which is the size of the tables below. */
130 static int combine_max_regno;
132 /* Record last point of death of (hard or pseudo) register n. */
134 static rtx *reg_last_death;
136 /* Record last point of modification of (hard or pseudo) register n. */
138 static rtx *reg_last_set;
140 /* Record the cuid of the last insn that invalidated memory
141 (anything that writes memory, and subroutine calls, but not pushes). */
143 static int mem_last_set;
145 /* Record the cuid of the last CALL_INSN
146 so we can tell whether a potential combination crosses any calls. */
148 static int last_call_cuid;
150 /* When `subst' is called, this is the insn that is being modified
151 (by combining in a previous insn). The PATTERN of this insn
152 is still the old pattern partially modified and it should not be
153 looked at, but this may be used to examine the successors of the insn
154 to judge whether a simplification is valid. */
156 static rtx subst_insn;
158 /* This is the lowest CUID that `subst' is currently dealing with.
159 get_last_value will not return a value if the register was set at or
160 after this CUID. If not for this mechanism, we could get confused if
161 I2 or I1 in try_combine were an insn that used the old value of a register
162 to obtain a new value. In that case, we might erroneously get the
163 new value of the register when we wanted the old one. */
165 static int subst_low_cuid;
167 /* This is the value of undobuf.num_undo when we started processing this
168 substitution. This will prevent gen_rtx_combine from re-used a piece
169 from the previous expression. Doing so can produce circular rtl
172 static int previous_num_undos;
174 /* The next group of arrays allows the recording of the last value assigned
175 to (hard or pseudo) register n. We use this information to see if a
176 operation being processed is redundant given a prior operation performed
177 on the register. For example, an `and' with a constant is redundant if
178 all the zero bits are already known to be turned off.
180 We use an approach similar to that used by cse, but change it in the
183 (1) We do not want to reinitialize at each label.
184 (2) It is useful, but not critical, to know the actual value assigned
185 to a register. Often just its form is helpful.
187 Therefore, we maintain the following arrays:
189 reg_last_set_value the last value assigned
190 reg_last_set_label records the value of label_tick when the
191 register was assigned
192 reg_last_set_table_tick records the value of label_tick when a
193 value using the register is assigned
194 reg_last_set_invalid set to non-zero when it is not valid
195 to use the value of this register in some
198 To understand the usage of these tables, it is important to understand
199 the distinction between the value in reg_last_set_value being valid
200 and the register being validly contained in some other expression in the
203 Entry I in reg_last_set_value is valid if it is non-zero, and either
204 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
206 Register I may validly appear in any expression returned for the value
207 of another register if reg_n_sets[i] is 1. It may also appear in the
208 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
209 reg_last_set_invalid[j] is zero.
211 If an expression is found in the table containing a register which may
212 not validly appear in an expression, the register is replaced by
213 something that won't match, (clobber (const_int 0)).
215 reg_last_set_invalid[i] is set non-zero when register I is being assigned
216 to and reg_last_set_table_tick[i] == label_tick. */
218 /* Record last value assigned to (hard or pseudo) register n. */
220 static rtx *reg_last_set_value;
222 /* Record the value of label_tick when the value for register n is placed in
223 reg_last_set_value[n]. */
225 static short *reg_last_set_label;
227 /* Record the value of label_tick when an expression involving register n
228 is placed in reg_last_set_value. */
230 static short *reg_last_set_table_tick;
232 /* Set non-zero if references to register n in expressions should not be
235 static char *reg_last_set_invalid;
237 /* Incremented for each label. */
239 static short label_tick;
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following array what we know about the nonzero
247 bits of a register, specifically which bits are known to be zero.
249 If an entry is zero, it means that we don't know anything special. */
251 static HOST_WIDE_INT *reg_nonzero_bits;
253 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
254 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
256 static enum machine_mode nonzero_bits_mode;
258 /* Nonzero if we know that a register has some leading bits that are always
259 equal to the sign bit. */
261 static char *reg_sign_bit_copies;
263 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
264 It is zero while computing them and after combine has completed. This
265 former test prevents propagating values based on previously set values,
266 which can be incorrect if a variable is modified in a loop. */
268 static int nonzero_sign_valid;
270 /* Record one modification to rtl structure
271 to be undone by storing old_contents into *where.
272 is_int is 1 if the contents are an int. */
277 union {rtx rtx; int i;} old_contents;
278 union {rtx *rtx; int *i;} where;
281 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
282 num_undo says how many are currently recorded.
284 storage is nonzero if we must undo the allocation of new storage.
285 The value of storage is what to pass to obfree.
287 other_insn is nonzero if we have modified some other insn in the process
288 of working on subst_insn. It must be verified too. */
296 struct undo undo[MAX_UNDO];
300 static struct undobuf undobuf;
302 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
303 insn. The substitution can be undone by undo_all. If INTO is already
304 set to NEWVAL, do not record this change. Because computing NEWVAL might
305 also call SUBST, we have to compute it before we put anything into
308 #define SUBST(INTO, NEWVAL) \
309 do { rtx _new = (NEWVAL); \
310 if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].is_int = 0; \
313 undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
314 undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
316 if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
328 undobuf.undo[undobuf.num_undo].is_int = 1; \
329 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
330 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
332 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
333 undobuf.num_undo++; \
337 /* Number of times the pseudo being substituted for
338 was found and replaced. */
340 static int n_occurrences;
342 static void set_nonzero_bits_and_sign_copies ();
343 static void move_deaths ();
345 static void record_value_for_reg ();
346 static void record_dead_and_set_regs ();
347 static int use_crosses_set_p ();
348 static rtx try_combine ();
349 static rtx *find_split_point ();
351 static void undo_all ();
352 static int reg_dead_at_p ();
353 static rtx expand_compound_operation ();
354 static rtx expand_field_assignment ();
355 static rtx make_extraction ();
356 static int get_pos_from_mask ();
357 static rtx force_to_mode ();
358 static rtx known_cond ();
359 static rtx make_field_assignment ();
360 static rtx make_compound_operation ();
361 static rtx apply_distributive_law ();
362 static rtx simplify_and_const_int ();
363 static unsigned HOST_WIDE_INT nonzero_bits ();
364 static int num_sign_bit_copies ();
365 static int merge_outer_ops ();
366 static rtx simplify_shift_const ();
367 static int recog_for_combine ();
368 static rtx gen_lowpart_for_combine ();
369 static rtx gen_rtx_combine ();
370 static rtx gen_binary ();
371 static rtx gen_unary ();
372 static enum rtx_code simplify_comparison ();
373 static int reversible_comparison_p ();
374 static int get_last_value_validate ();
375 static rtx get_last_value ();
376 static void distribute_notes ();
377 static void distribute_links ();
379 /* Main entry point for combiner. F is the first insn of the function.
380 NREGS is the first unused pseudo-reg number. */
383 combine_instructions (f, nregs)
387 register rtx insn, next, prev;
389 register rtx links, nextlinks;
391 combine_attempts = 0;
394 combine_successes = 0;
396 combine_max_regno = nregs;
398 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
399 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
400 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
401 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
402 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
403 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
404 reg_nonzero_bits = (HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
405 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
407 bzero (reg_last_death, nregs * sizeof (rtx));
408 bzero (reg_last_set, nregs * sizeof (rtx));
409 bzero (reg_last_set_value, nregs * sizeof (rtx));
410 bzero (reg_last_set_table_tick, nregs * sizeof (short));
411 bzero (reg_last_set_invalid, nregs * sizeof (char));
412 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
413 bzero (reg_sign_bit_copies, nregs * sizeof (char));
415 init_recog_no_volatile ();
417 /* Compute maximum uid value so uid_cuid can be allocated. */
419 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
420 if (INSN_UID (insn) > i)
423 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
425 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
427 /* Don't use reg_nonzero_bits when computing it. This can cause problems
428 when, for example, we have j <<= 1 in a loop. */
430 nonzero_sign_valid = 0;
432 /* Compute the mapping from uids to cuids.
433 Cuids are numbers assigned to insns, like uids,
434 except that cuids increase monotonically through the code.
436 Scan all SETs and see if we can deduce anything about what
437 bits are known to be zero for some registers and how many copies
438 of the sign bit are known to exist for those registers. */
440 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
442 INSN_CUID (insn) = ++i;
443 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
444 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
447 nonzero_sign_valid = 1;
449 /* Now scan all the insns in forward order. */
455 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
459 if (GET_CODE (insn) == CODE_LABEL)
462 else if (GET_CODE (insn) == INSN
463 || GET_CODE (insn) == CALL_INSN
464 || GET_CODE (insn) == JUMP_INSN)
466 /* Try this insn with each insn it links back to. */
468 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
469 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
472 /* Try each sequence of three linked insns ending with this one. */
474 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
475 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
476 nextlinks = XEXP (nextlinks, 1))
477 if ((next = try_combine (insn, XEXP (links, 0),
478 XEXP (nextlinks, 0))) != 0)
482 /* Try to combine a jump insn that uses CC0
483 with a preceding insn that sets CC0, and maybe with its
484 logical predecessor as well.
485 This is how we make decrement-and-branch insns.
486 We need this special code because data flow connections
487 via CC0 do not get entered in LOG_LINKS. */
489 if (GET_CODE (insn) == JUMP_INSN
490 && (prev = prev_nonnote_insn (insn)) != 0
491 && GET_CODE (prev) == INSN
492 && sets_cc0_p (PATTERN (prev)))
494 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
497 for (nextlinks = LOG_LINKS (prev); nextlinks;
498 nextlinks = XEXP (nextlinks, 1))
499 if ((next = try_combine (insn, prev,
500 XEXP (nextlinks, 0))) != 0)
504 /* Do the same for an insn that explicitly references CC0. */
505 if (GET_CODE (insn) == INSN
506 && (prev = prev_nonnote_insn (insn)) != 0
507 && GET_CODE (prev) == INSN
508 && sets_cc0_p (PATTERN (prev))
509 && GET_CODE (PATTERN (insn)) == SET
510 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
512 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
515 for (nextlinks = LOG_LINKS (prev); nextlinks;
516 nextlinks = XEXP (nextlinks, 1))
517 if ((next = try_combine (insn, prev,
518 XEXP (nextlinks, 0))) != 0)
522 /* Finally, see if any of the insns that this insn links to
523 explicitly references CC0. If so, try this insn, that insn,
524 and its predecessor if it sets CC0. */
525 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
526 if (GET_CODE (XEXP (links, 0)) == INSN
527 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
528 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
529 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
530 && GET_CODE (prev) == INSN
531 && sets_cc0_p (PATTERN (prev))
532 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
536 /* Try combining an insn with two different insns whose results it
538 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
539 for (nextlinks = XEXP (links, 1); nextlinks;
540 nextlinks = XEXP (nextlinks, 1))
541 if ((next = try_combine (insn, XEXP (links, 0),
542 XEXP (nextlinks, 0))) != 0)
545 if (GET_CODE (insn) != NOTE)
546 record_dead_and_set_regs (insn);
553 total_attempts += combine_attempts;
554 total_merges += combine_merges;
555 total_extras += combine_extras;
556 total_successes += combine_successes;
558 nonzero_sign_valid = 0;
561 /* Called via note_stores. If X is a pseudo that is used in more than
562 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
563 set, record what bits are known zero. If we are clobbering X,
564 ignore this "set" because the clobbered value won't be used.
566 If we are setting only a portion of X and we can't figure out what
567 portion, assume all bits will be used since we don't know what will
570 Similarly, set how many bits of X are known to be copies of the sign bit
571 at all locations in the function. This is the smallest number implied
575 set_nonzero_bits_and_sign_copies (x, set)
581 if (GET_CODE (x) == REG
582 && REGNO (x) >= FIRST_PSEUDO_REGISTER
583 && reg_n_sets[REGNO (x)] > 1
584 && reg_basic_block[REGNO (x)] < 0
585 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
587 if (GET_CODE (set) == CLOBBER)
590 /* If this is a complex assignment, see if we can convert it into a
591 simple assignment. */
592 set = expand_field_assignment (set);
593 if (SET_DEST (set) == x)
595 reg_nonzero_bits[REGNO (x)]
596 |= nonzero_bits (SET_SRC (set), nonzero_bits_mode);
597 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
598 if (reg_sign_bit_copies[REGNO (x)] == 0
599 || reg_sign_bit_copies[REGNO (x)] > num)
600 reg_sign_bit_copies[REGNO (x)] = num;
604 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
605 reg_sign_bit_copies[REGNO (x)] = 0;
610 /* See if INSN can be combined into I3. PRED and SUCC are optionally
611 insns that were previously combined into I3 or that will be combined
612 into the merger of INSN and I3.
614 Return 0 if the combination is not allowed for any reason.
616 If the combination is allowed, *PDEST will be set to the single
617 destination of INSN and *PSRC to the single source, and this function
621 can_combine_p (insn, i3, pred, succ, pdest, psrc)
628 rtx set = 0, src, dest;
630 int all_adjacent = (succ ? (next_active_insn (insn) == succ
631 && next_active_insn (succ) == i3)
632 : next_active_insn (insn) == i3);
634 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
635 or a PARALLEL consisting of such a SET and CLOBBERs.
637 If INSN has CLOBBER parallel parts, ignore them for our processing.
638 By definition, these happen during the execution of the insn. When it
639 is merged with another insn, all bets are off. If they are, in fact,
640 needed and aren't also supplied in I3, they may be added by
641 recog_for_combine. Otherwise, it won't match.
643 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
646 Get the source and destination of INSN. If more than one, can't
649 if (GET_CODE (PATTERN (insn)) == SET)
650 set = PATTERN (insn);
651 else if (GET_CODE (PATTERN (insn)) == PARALLEL
652 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
654 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
656 rtx elt = XVECEXP (PATTERN (insn), 0, i);
658 switch (GET_CODE (elt))
660 /* We can ignore CLOBBERs. */
665 /* Ignore SETs whose result isn't used but not those that
666 have side-effects. */
667 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
668 && ! side_effects_p (elt))
671 /* If we have already found a SET, this is a second one and
672 so we cannot combine with this insn. */
680 /* Anything else means we can't combine. */
686 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
687 so don't do anything with it. */
688 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
697 set = expand_field_assignment (set);
698 src = SET_SRC (set), dest = SET_DEST (set);
700 /* Don't eliminate a store in the stack pointer. */
701 if (dest == stack_pointer_rtx
702 /* Don't install a subreg involving two modes not tieable.
703 It can worsen register allocation, and can even make invalid reload
704 insns, since the reg inside may need to be copied from in the
705 outside mode, and that may be invalid if it is an fp reg copied in
706 integer mode. As a special exception, we can allow this if
707 I3 is simply copying DEST, a REG, to CC0. */
708 || (GET_CODE (src) == SUBREG
709 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
711 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
712 && SET_DEST (PATTERN (i3)) == cc0_rtx
713 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
716 /* If we couldn't eliminate a field assignment, we can't combine. */
717 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
718 /* Don't combine with an insn that sets a register to itself if it has
719 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
720 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
721 /* Can't merge a function call. */
722 || GET_CODE (src) == CALL
723 /* Don't substitute into an incremented register. */
724 || FIND_REG_INC_NOTE (i3, dest)
725 || (succ && FIND_REG_INC_NOTE (succ, dest))
726 /* Don't combine the end of a libcall into anything. */
727 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
728 /* Make sure that DEST is not used after SUCC but before I3. */
729 || (succ && ! all_adjacent
730 && reg_used_between_p (dest, succ, i3))
731 /* Make sure that the value that is to be substituted for the register
732 does not use any registers whose values alter in between. However,
733 If the insns are adjacent, a use can't cross a set even though we
734 think it might (this can happen for a sequence of insns each setting
735 the same destination; reg_last_set of that register might point to
736 a NOTE). Also, don't move a volatile asm across any other insns. */
738 && (use_crosses_set_p (src, INSN_CUID (insn))
739 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
740 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
741 better register allocation by not doing the combine. */
742 || find_reg_note (i3, REG_NO_CONFLICT, dest)
743 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
744 /* Don't combine across a CALL_INSN, because that would possibly
745 change whether the life span of some REGs crosses calls or not,
746 and it is a pain to update that information.
747 Exception: if source is a constant, moving it later can't hurt.
748 Accept that special case, because it helps -fforce-addr a lot. */
749 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
752 /* DEST must either be a REG or CC0. */
753 if (GET_CODE (dest) == REG)
755 /* If register alignment is being enforced for multi-word items in all
756 cases except for parameters, it is possible to have a register copy
757 insn referencing a hard register that is not allowed to contain the
758 mode being copied and which would not be valid as an operand of most
759 insns. Eliminate this problem by not combining with such an insn.
761 Also, on some machines we don't want to extend the life of a hard
764 if (GET_CODE (src) == REG
765 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
766 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
767 #ifdef SMALL_REGISTER_CLASSES
768 /* Don't extend the life of a hard register. */
769 || REGNO (src) < FIRST_PSEUDO_REGISTER
771 || (REGNO (src) < FIRST_PSEUDO_REGISTER
772 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
777 else if (GET_CODE (dest) != CC0)
780 /* Don't substitute for a register intended as a clobberable operand.
781 Similarly, don't substitute an expression containing a register that
782 will be clobbered in I3. */
783 if (GET_CODE (PATTERN (i3)) == PARALLEL)
784 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
785 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
786 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
788 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
791 /* If INSN contains anything volatile, or is an `asm' (whether volatile
792 or not), reject, unless nothing volatile comes between it and I3,
793 with the exception of SUCC. */
795 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
796 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
797 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
798 && p != succ && volatile_refs_p (PATTERN (p)))
801 /* If INSN or I2 contains an autoincrement or autodecrement,
802 make sure that register is not used between there and I3,
803 and not already used in I3 either.
804 Also insist that I3 not be a jump; if it were one
805 and the incremented register were spilled, we would lose. */
808 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
809 if (REG_NOTE_KIND (link) == REG_INC
810 && (GET_CODE (i3) == JUMP_INSN
811 || reg_used_between_p (XEXP (link, 0), insn, i3)
812 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
817 /* Don't combine an insn that follows a CC0-setting insn.
818 An insn that uses CC0 must not be separated from the one that sets it.
819 We do, however, allow I2 to follow a CC0-setting insn if that insn
820 is passed as I1; in that case it will be deleted also.
821 We also allow combining in this case if all the insns are adjacent
822 because that would leave the two CC0 insns adjacent as well.
823 It would be more logical to test whether CC0 occurs inside I1 or I2,
824 but that would be much slower, and this ought to be equivalent. */
826 p = prev_nonnote_insn (insn);
827 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
832 /* If we get here, we have passed all the tests and the combination is
841 /* LOC is the location within I3 that contains its pattern or the component
842 of a PARALLEL of the pattern. We validate that it is valid for combining.
844 One problem is if I3 modifies its output, as opposed to replacing it
845 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
846 so would produce an insn that is not equivalent to the original insns.
850 (set (reg:DI 101) (reg:DI 100))
851 (set (subreg:SI (reg:DI 101) 0) <foo>)
853 This is NOT equivalent to:
855 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
856 (set (reg:DI 101) (reg:DI 100))])
858 Not only does this modify 100 (in which case it might still be valid
859 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
861 We can also run into a problem if I2 sets a register that I1
862 uses and I1 gets directly substituted into I3 (not via I2). In that
863 case, we would be getting the wrong value of I2DEST into I3, so we
864 must reject the combination. This case occurs when I2 and I1 both
865 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
866 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
867 of a SET must prevent combination from occurring.
869 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
870 if the destination of a SET is a hard register.
872 Before doing the above check, we first try to expand a field assignment
873 into a set of logical operations.
875 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
876 we place a register that is both set and used within I3. If more than one
877 such register is detected, we fail.
879 Return 1 if the combination is valid, zero otherwise. */
882 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
892 if (GET_CODE (x) == SET)
894 rtx set = expand_field_assignment (x);
895 rtx dest = SET_DEST (set);
896 rtx src = SET_SRC (set);
897 rtx inner_dest = dest, inner_src = src;
901 while (GET_CODE (inner_dest) == STRICT_LOW_PART
902 || GET_CODE (inner_dest) == SUBREG
903 || GET_CODE (inner_dest) == ZERO_EXTRACT)
904 inner_dest = XEXP (inner_dest, 0);
906 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
909 while (GET_CODE (inner_src) == STRICT_LOW_PART
910 || GET_CODE (inner_src) == SUBREG
911 || GET_CODE (inner_src) == ZERO_EXTRACT)
912 inner_src = XEXP (inner_src, 0);
914 /* If it is better that two different modes keep two different pseudos,
915 avoid combining them. This avoids producing the following pattern
917 (set (subreg:SI (reg/v:QI 21) 0)
918 (lshiftrt:SI (reg/v:SI 20)
920 If that were made, reload could not handle the pair of
921 reg 20/21, since it would try to get any GENERAL_REGS
922 but some of them don't handle QImode. */
924 if (rtx_equal_p (inner_src, i2dest)
925 && GET_CODE (inner_dest) == REG
926 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
930 /* Check for the case where I3 modifies its output, as
932 if ((inner_dest != dest
933 && (reg_overlap_mentioned_p (i2dest, inner_dest)
934 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
935 /* This is the same test done in can_combine_p except that we
936 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
938 || (GET_CODE (inner_dest) == REG
939 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
940 #ifdef SMALL_REGISTER_CLASSES
941 && GET_CODE (src) != CALL
943 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
944 GET_MODE (inner_dest))
948 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
951 /* If DEST is used in I3, it is being killed in this insn,
952 so record that for later. */
953 if (pi3dest_killed && GET_CODE (dest) == REG
954 && reg_referenced_p (dest, PATTERN (i3)))
959 *pi3dest_killed = dest;
963 else if (GET_CODE (x) == PARALLEL)
967 for (i = 0; i < XVECLEN (x, 0); i++)
968 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
969 i1_not_in_src, pi3dest_killed))
976 /* Try to combine the insns I1 and I2 into I3.
977 Here I1 and I2 appear earlier than I3.
978 I1 can be zero; then we combine just I2 into I3.
980 It we are combining three insns and the resulting insn is not recognized,
981 try splitting it into two insns. If that happens, I2 and I3 are retained
982 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
985 If we created two insns, return I2; otherwise return I3.
986 Return 0 if the combination does not work. Then nothing is changed. */
989 try_combine (i3, i2, i1)
990 register rtx i3, i2, i1;
992 /* New patterns for I3 and I3, respectively. */
993 rtx newpat, newi2pat = 0;
994 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
995 int added_sets_1, added_sets_2;
996 /* Total number of SETs to put into I3. */
998 /* Nonzero is I2's body now appears in I3. */
1000 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1001 int insn_code_number, i2_code_number, other_code_number;
1002 /* Contains I3 if the destination of I3 is used in its source, which means
1003 that the old life of I3 is being killed. If that usage is placed into
1004 I2 and not in I3, a REG_DEAD note must be made. */
1005 rtx i3dest_killed = 0;
1006 /* SET_DEST and SET_SRC of I2 and I1. */
1007 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1008 /* PATTERN (I2), or a copy of it in certain cases. */
1010 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1011 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1012 int i1_feeds_i3 = 0;
1013 /* Notes that must be added to REG_NOTES in I3 and I2. */
1014 rtx new_i3_notes, new_i2_notes;
1021 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1022 This can occur when flow deletes an insn that it has merged into an
1023 auto-increment address. We also can't do anything if I3 has a
1024 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1027 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1028 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1029 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1030 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1035 undobuf.num_undo = previous_num_undos = 0;
1036 undobuf.other_insn = 0;
1038 /* Save the current high-water-mark so we can free storage if we didn't
1039 accept this combination. */
1040 undobuf.storage = (char *) oballoc (0);
1042 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1043 code below, set I1 to be the earlier of the two insns. */
1044 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1045 temp = i1, i1 = i2, i2 = temp;
1047 /* First check for one important special-case that the code below will
1048 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1049 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1050 we may be able to replace that destination with the destination of I3.
1051 This occurs in the common code where we compute both a quotient and
1052 remainder into a structure, in which case we want to do the computation
1053 directly into the structure to avoid register-register copies.
1055 We make very conservative checks below and only try to handle the
1056 most common cases of this. For example, we only handle the case
1057 where I2 and I3 are adjacent to avoid making difficult register
1060 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1061 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1062 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1063 #ifdef SMALL_REGISTER_CLASSES
1064 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1065 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1067 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1068 && GET_CODE (PATTERN (i2)) == PARALLEL
1069 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1070 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1071 below would need to check what is inside (and reg_overlap_mentioned_p
1072 doesn't support those codes anyway). Don't allow those destinations;
1073 the resulting insn isn't likely to be recognized anyway. */
1074 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1075 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1076 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1077 SET_DEST (PATTERN (i3)))
1078 && next_real_insn (i2) == i3)
1080 rtx p2 = PATTERN (i2);
1082 /* Make sure that the destination of I3,
1083 which we are going to substitute into one output of I2,
1084 is not used within another output of I2. We must avoid making this:
1085 (parallel [(set (mem (reg 69)) ...)
1086 (set (reg 69) ...)])
1087 which is not well-defined as to order of actions.
1088 (Besides, reload can't handle output reloads for this.)
1090 The problem can also happen if the dest of I3 is a memory ref,
1091 if another dest in I2 is an indirect memory ref. */
1092 for (i = 0; i < XVECLEN (p2, 0); i++)
1093 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1094 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1095 SET_DEST (XVECEXP (p2, 0, i))))
1098 if (i == XVECLEN (p2, 0))
1099 for (i = 0; i < XVECLEN (p2, 0); i++)
1100 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1105 subst_low_cuid = INSN_CUID (i2);
1108 i2dest = SET_SRC (PATTERN (i3));
1110 /* Replace the dest in I2 with our dest and make the resulting
1111 insn the new pattern for I3. Then skip to where we
1112 validate the pattern. Everything was set up above. */
1113 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1114 SET_DEST (PATTERN (i3)));
1117 goto validate_replacement;
1122 /* If we have no I1 and I2 looks like:
1123 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1125 make up a dummy I1 that is
1128 (set (reg:CC X) (compare:CC Y (const_int 0)))
1130 (We can ignore any trailing CLOBBERs.)
1132 This undoes a previous combination and allows us to match a branch-and-
1135 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1136 && XVECLEN (PATTERN (i2), 0) >= 2
1137 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1138 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1140 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1141 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1142 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1143 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1144 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1145 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1147 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1148 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1153 /* We make I1 with the same INSN_UID as I2. This gives it
1154 the same INSN_CUID for value tracking. Our fake I1 will
1155 never appear in the insn stream so giving it the same INSN_UID
1156 as I2 will not cause a problem. */
1158 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1159 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1161 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1162 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1163 SET_DEST (PATTERN (i1)));
1168 /* Verify that I2 and I1 are valid for combining. */
1169 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1170 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1176 /* Record whether I2DEST is used in I2SRC and similarly for the other
1177 cases. Knowing this will help in register status updating below. */
1178 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1179 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1180 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1182 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1184 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1186 /* Ensure that I3's pattern can be the destination of combines. */
1187 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1188 i1 && i2dest_in_i1src && i1_feeds_i3,
1195 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1196 We used to do this EXCEPT in one case: I3 has a post-inc in an
1197 output operand. However, that exception can give rise to insns like
1199 which is a famous insn on the PDP-11 where the value of r3 used as the
1200 source was model-dependent. Avoid this sort of thing. */
1203 if (!(GET_CODE (PATTERN (i3)) == SET
1204 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1205 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1206 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1207 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1208 /* It's not the exception. */
1211 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1212 if (REG_NOTE_KIND (link) == REG_INC
1213 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1215 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1222 /* See if the SETs in I1 or I2 need to be kept around in the merged
1223 instruction: whenever the value set there is still needed past I3.
1224 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1226 For the SET in I1, we have two cases: If I1 and I2 independently
1227 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1228 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1229 in I1 needs to be kept around unless I1DEST dies or is set in either
1230 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1231 I1DEST. If so, we know I1 feeds into I2. */
1233 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1236 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1237 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1239 /* If the set in I2 needs to be kept around, we must make a copy of
1240 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1241 PATTERN (I2), we are only substituting for the original I1DEST, not into
1242 an already-substituted copy. This also prevents making self-referential
1243 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1246 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1247 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1251 i2pat = copy_rtx (i2pat);
1255 /* Substitute in the latest insn for the regs set by the earlier ones. */
1257 maxreg = max_reg_num ();
1261 /* It is possible that the source of I2 or I1 may be performing an
1262 unneeded operation, such as a ZERO_EXTEND of something that is known
1263 to have the high part zero. Handle that case by letting subst look at
1264 the innermost one of them.
1266 Another way to do this would be to have a function that tries to
1267 simplify a single insn instead of merging two or more insns. We don't
1268 do this because of the potential of infinite loops and because
1269 of the potential extra memory required. However, doing it the way
1270 we are is a bit of a kludge and doesn't catch all cases.
1272 But only do this if -fexpensive-optimizations since it slows things down
1273 and doesn't usually win. */
1275 if (flag_expensive_optimizations)
1277 /* Pass pc_rtx so no substitutions are done, just simplifications.
1278 The cases that we are interested in here do not involve the few
1279 cases were is_replaced is checked. */
1282 subst_low_cuid = INSN_CUID (i1);
1283 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1287 subst_low_cuid = INSN_CUID (i2);
1288 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1291 previous_num_undos = undobuf.num_undo;
1295 /* Many machines that don't use CC0 have insns that can both perform an
1296 arithmetic operation and set the condition code. These operations will
1297 be represented as a PARALLEL with the first element of the vector
1298 being a COMPARE of an arithmetic operation with the constant zero.
1299 The second element of the vector will set some pseudo to the result
1300 of the same arithmetic operation. If we simplify the COMPARE, we won't
1301 match such a pattern and so will generate an extra insn. Here we test
1302 for this case, where both the comparison and the operation result are
1303 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1304 I2SRC. Later we will make the PARALLEL that contains I2. */
1306 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1307 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1308 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1309 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1312 enum machine_mode compare_mode;
1314 newpat = PATTERN (i3);
1315 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1319 #ifdef EXTRA_CC_MODES
1320 /* See if a COMPARE with the operand we substituted in should be done
1321 with the mode that is currently being used. If not, do the same
1322 processing we do in `subst' for a SET; namely, if the destination
1323 is used only once, try to replace it with a register of the proper
1324 mode and also replace the COMPARE. */
1325 if (undobuf.other_insn == 0
1326 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1327 &undobuf.other_insn))
1328 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1330 != GET_MODE (SET_DEST (newpat))))
1332 int regno = REGNO (SET_DEST (newpat));
1333 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1335 if (regno < FIRST_PSEUDO_REGISTER
1336 || (reg_n_sets[regno] == 1 && ! added_sets_2
1337 && ! REG_USERVAR_P (SET_DEST (newpat))))
1339 if (regno >= FIRST_PSEUDO_REGISTER)
1340 SUBST (regno_reg_rtx[regno], new_dest);
1342 SUBST (SET_DEST (newpat), new_dest);
1343 SUBST (XEXP (*cc_use, 0), new_dest);
1344 SUBST (SET_SRC (newpat),
1345 gen_rtx_combine (COMPARE, compare_mode,
1346 i2src, const0_rtx));
1349 undobuf.other_insn = 0;
1356 n_occurrences = 0; /* `subst' counts here */
1358 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1359 need to make a unique copy of I2SRC each time we substitute it
1360 to avoid self-referential rtl. */
1362 subst_low_cuid = INSN_CUID (i2);
1363 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1364 ! i1_feeds_i3 && i1dest_in_i1src);
1365 previous_num_undos = undobuf.num_undo;
1367 /* Record whether i2's body now appears within i3's body. */
1368 i2_is_used = n_occurrences;
1371 /* If we already got a failure, don't try to do more. Otherwise,
1372 try to substitute in I1 if we have it. */
1374 if (i1 && GET_CODE (newpat) != CLOBBER)
1376 /* Before we can do this substitution, we must redo the test done
1377 above (see detailed comments there) that ensures that I1DEST
1378 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1380 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1388 subst_low_cuid = INSN_CUID (i1);
1389 newpat = subst (newpat, i1dest, i1src, 0, 0);
1390 previous_num_undos = undobuf.num_undo;
1393 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1394 to count all the ways that I2SRC and I1SRC can be used. */
1395 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1396 && i2_is_used + added_sets_2 > 1)
1397 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1398 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1400 /* Fail if we tried to make a new register (we used to abort, but there's
1401 really no reason to). */
1402 || max_reg_num () != maxreg
1403 /* Fail if we couldn't do something and have a CLOBBER. */
1404 || GET_CODE (newpat) == CLOBBER)
1410 /* If the actions of the earlier insns must be kept
1411 in addition to substituting them into the latest one,
1412 we must make a new PARALLEL for the latest insn
1413 to hold additional the SETs. */
1415 if (added_sets_1 || added_sets_2)
1419 if (GET_CODE (newpat) == PARALLEL)
1421 rtvec old = XVEC (newpat, 0);
1422 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1423 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1424 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1425 sizeof (old->elem[0]) * old->num_elem);
1430 total_sets = 1 + added_sets_1 + added_sets_2;
1431 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1432 XVECEXP (newpat, 0, 0) = old;
1436 XVECEXP (newpat, 0, --total_sets)
1437 = (GET_CODE (PATTERN (i1)) == PARALLEL
1438 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1442 /* If there is no I1, use I2's body as is. We used to also not do
1443 the subst call below if I2 was substituted into I3,
1444 but that could lose a simplification. */
1446 XVECEXP (newpat, 0, --total_sets) = i2pat;
1448 /* See comment where i2pat is assigned. */
1449 XVECEXP (newpat, 0, --total_sets)
1450 = subst (i2pat, i1dest, i1src, 0, 0);
1454 /* We come here when we are replacing a destination in I2 with the
1455 destination of I3. */
1456 validate_replacement:
1458 /* Is the result of combination a valid instruction? */
1459 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1461 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1462 the second SET's destination is a register that is unused. In that case,
1463 we just need the first SET. This can occur when simplifying a divmod
1464 insn. We *must* test for this case here because the code below that
1465 splits two independent SETs doesn't handle this case correctly when it
1466 updates the register status. Also check the case where the first
1467 SET's destination is unused. That would not cause incorrect code, but
1468 does cause an unneeded insn to remain. */
1470 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1471 && XVECLEN (newpat, 0) == 2
1472 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1473 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1474 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1475 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1476 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1477 && asm_noperands (newpat) < 0)
1479 newpat = XVECEXP (newpat, 0, 0);
1480 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1483 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1484 && XVECLEN (newpat, 0) == 2
1485 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1486 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1487 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1488 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1489 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1490 && asm_noperands (newpat) < 0)
1492 newpat = XVECEXP (newpat, 0, 1);
1493 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1496 /* See if this is an XOR. If so, perhaps the problem is that the
1497 constant is out of range. Replace it with a complemented XOR with
1498 a complemented constant; it might be in range. */
1500 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1501 && GET_CODE (SET_SRC (newpat)) == XOR
1502 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1503 && ((temp = simplify_unary_operation (NOT,
1504 GET_MODE (SET_SRC (newpat)),
1505 XEXP (SET_SRC (newpat), 1),
1506 GET_MODE (SET_SRC (newpat))))
1509 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1511 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1512 gen_unary (NOT, i_mode,
1513 gen_binary (XOR, i_mode,
1514 XEXP (SET_SRC (newpat), 0),
1517 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1518 if (insn_code_number >= 0)
1522 /* If we were combining three insns and the result is a simple SET
1523 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1524 insns. There are two ways to do this. It can be split using a
1525 machine-specific method (like when you have an addition of a large
1526 constant) or by combine in the function find_split_point. */
1528 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1529 && asm_noperands (newpat) < 0)
1531 rtx m_split, *split;
1532 rtx ni2dest = i2dest;
1534 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1535 use I2DEST as a scratch register will help. In the latter case,
1536 convert I2DEST to the mode of the source of NEWPAT if we can. */
1538 m_split = split_insns (newpat, i3);
1540 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1541 inputs of NEWPAT. */
1543 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1544 possible to try that as a scratch reg. This would require adding
1545 more code to make it work though. */
1547 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1549 /* If I2DEST is a hard register or the only use of a pseudo,
1550 we can change its mode. */
1551 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1552 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1553 && GET_CODE (i2dest) == REG
1554 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1555 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1556 && ! REG_USERVAR_P (i2dest))))
1557 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1560 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1561 gen_rtvec (2, newpat,
1568 if (m_split && GET_CODE (m_split) == SEQUENCE
1569 && XVECLEN (m_split, 0) == 2
1570 && (next_real_insn (i2) == i3
1571 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1575 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1576 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1578 i3set = single_set (XVECEXP (m_split, 0, 1));
1579 i2set = single_set (XVECEXP (m_split, 0, 0));
1581 /* In case we changed the mode of I2DEST, replace it in the
1582 pseudo-register table here. We can't do it above in case this
1583 code doesn't get executed and we do a split the other way. */
1585 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1586 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1588 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1590 /* If I2 or I3 has multiple SETs, we won't know how to track
1591 register status, so don't use these insns. */
1593 if (i2_code_number >= 0 && i2set && i3set)
1594 insn_code_number = recog_for_combine (&newi3pat, i3,
1597 if (insn_code_number >= 0)
1600 /* It is possible that both insns now set the destination of I3.
1601 If so, we must show an extra use of it. */
1603 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1604 && GET_CODE (SET_DEST (i2set)) == REG
1605 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1606 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1609 /* If we can split it and use I2DEST, go ahead and see if that
1610 helps things be recognized. Verify that none of the registers
1611 are set between I2 and I3. */
1612 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1614 && GET_CODE (i2dest) == REG
1616 /* We need I2DEST in the proper mode. If it is a hard register
1617 or the only use of a pseudo, we can change its mode. */
1618 && (GET_MODE (*split) == GET_MODE (i2dest)
1619 || GET_MODE (*split) == VOIDmode
1620 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1621 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1622 && ! REG_USERVAR_P (i2dest)))
1623 && (next_real_insn (i2) == i3
1624 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1625 /* We can't overwrite I2DEST if its value is still used by
1627 && ! reg_referenced_p (i2dest, newpat))
1629 rtx newdest = i2dest;
1631 /* Get NEWDEST as a register in the proper mode. We have already
1632 validated that we can do this. */
1633 if (GET_MODE (i2dest) != GET_MODE (*split)
1634 && GET_MODE (*split) != VOIDmode)
1636 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1638 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1639 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1642 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1643 an ASHIFT. This can occur if it was inside a PLUS and hence
1644 appeared to be a memory address. This is a kludge. */
1645 if (GET_CODE (*split) == MULT
1646 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1647 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1648 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1649 XEXP (*split, 0), GEN_INT (i)));
1651 #ifdef INSN_SCHEDULING
1652 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1653 be written as a ZERO_EXTEND. */
1654 if (GET_CODE (*split) == SUBREG
1655 && GET_CODE (SUBREG_REG (*split)) == MEM)
1656 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1660 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1661 SUBST (*split, newdest);
1662 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1663 if (i2_code_number >= 0)
1664 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1668 /* Check for a case where we loaded from memory in a narrow mode and
1669 then sign extended it, but we need both registers. In that case,
1670 we have a PARALLEL with both loads from the same memory location.
1671 We can split this into a load from memory followed by a register-register
1672 copy. This saves at least one insn, more if register allocation can
1673 eliminate the copy. */
1675 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1676 && GET_CODE (newpat) == PARALLEL
1677 && XVECLEN (newpat, 0) == 2
1678 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1679 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1680 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1681 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1682 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1683 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1685 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1686 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1687 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1688 SET_SRC (XVECEXP (newpat, 0, 1)))
1689 && ! find_reg_note (i3, REG_UNUSED,
1690 SET_DEST (XVECEXP (newpat, 0, 0))))
1694 newi2pat = XVECEXP (newpat, 0, 0);
1695 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1696 newpat = XVECEXP (newpat, 0, 1);
1697 SUBST (SET_SRC (newpat),
1698 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1699 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1700 if (i2_code_number >= 0)
1701 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1703 if (insn_code_number >= 0)
1708 /* If we will be able to accept this, we have made a change to the
1709 destination of I3. This can invalidate a LOG_LINKS pointing
1710 to I3. No other part of combine.c makes such a transformation.
1712 The new I3 will have a destination that was previously the
1713 destination of I1 or I2 and which was used in i2 or I3. Call
1714 distribute_links to make a LOG_LINK from the next use of
1715 that destination. */
1717 PATTERN (i3) = newpat;
1718 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1720 /* I3 now uses what used to be its destination and which is
1721 now I2's destination. That means we need a LOG_LINK from
1722 I3 to I2. But we used to have one, so we still will.
1724 However, some later insn might be using I2's dest and have
1725 a LOG_LINK pointing at I3. We must remove this link.
1726 The simplest way to remove the link is to point it at I1,
1727 which we know will be a NOTE. */
1729 for (insn = NEXT_INSN (i3);
1730 insn && GET_CODE (insn) != CODE_LABEL
1731 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1732 insn = NEXT_INSN (insn))
1734 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1735 && reg_referenced_p (ni2dest, PATTERN (insn)))
1737 for (link = LOG_LINKS (insn); link;
1738 link = XEXP (link, 1))
1739 if (XEXP (link, 0) == i3)
1740 XEXP (link, 0) = i1;
1748 /* Similarly, check for a case where we have a PARALLEL of two independent
1749 SETs but we started with three insns. In this case, we can do the sets
1750 as two separate insns. This case occurs when some SET allows two
1751 other insns to combine, but the destination of that SET is still live. */
1753 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1754 && GET_CODE (newpat) == PARALLEL
1755 && XVECLEN (newpat, 0) == 2
1756 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1757 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1758 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1759 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1760 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1761 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1762 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1764 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1765 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1766 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1767 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1768 XVECEXP (newpat, 0, 0))
1769 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1770 XVECEXP (newpat, 0, 1)))
1772 newi2pat = XVECEXP (newpat, 0, 1);
1773 newpat = XVECEXP (newpat, 0, 0);
1775 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1776 if (i2_code_number >= 0)
1777 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1780 /* If it still isn't recognized, fail and change things back the way they
1782 if ((insn_code_number < 0
1783 /* Is the result a reasonable ASM_OPERANDS? */
1784 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1790 /* If we had to change another insn, make sure it is valid also. */
1791 if (undobuf.other_insn)
1793 rtx other_notes = REG_NOTES (undobuf.other_insn);
1794 rtx other_pat = PATTERN (undobuf.other_insn);
1795 rtx new_other_notes;
1798 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1801 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1807 PATTERN (undobuf.other_insn) = other_pat;
1809 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1810 are still valid. Then add any non-duplicate notes added by
1811 recog_for_combine. */
1812 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1814 next = XEXP (note, 1);
1816 if (REG_NOTE_KIND (note) == REG_UNUSED
1817 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1819 if (GET_CODE (XEXP (note, 0)) == REG)
1820 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1822 remove_note (undobuf.other_insn, note);
1826 for (note = new_other_notes; note; note = XEXP (note, 1))
1827 if (GET_CODE (XEXP (note, 0)) == REG)
1828 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1830 distribute_notes (new_other_notes, undobuf.other_insn,
1831 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1834 /* We now know that we can do this combination. Merge the insns and
1835 update the status of registers and LOG_LINKS. */
1838 rtx i3notes, i2notes, i1notes = 0;
1839 rtx i3links, i2links, i1links = 0;
1841 int all_adjacent = (next_real_insn (i2) == i3
1842 && (i1 == 0 || next_real_insn (i1) == i2));
1844 /* Compute which registers we expect to eliminate. */
1845 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1847 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1849 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1851 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1852 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1854 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1856 /* Ensure that we do not have something that should not be shared but
1857 occurs multiple times in the new insns. Check this by first
1858 resetting all the `used' flags and then copying anything is shared. */
1860 reset_used_flags (i3notes);
1861 reset_used_flags (i2notes);
1862 reset_used_flags (i1notes);
1863 reset_used_flags (newpat);
1864 reset_used_flags (newi2pat);
1865 if (undobuf.other_insn)
1866 reset_used_flags (PATTERN (undobuf.other_insn));
1868 i3notes = copy_rtx_if_shared (i3notes);
1869 i2notes = copy_rtx_if_shared (i2notes);
1870 i1notes = copy_rtx_if_shared (i1notes);
1871 newpat = copy_rtx_if_shared (newpat);
1872 newi2pat = copy_rtx_if_shared (newi2pat);
1873 if (undobuf.other_insn)
1874 reset_used_flags (PATTERN (undobuf.other_insn));
1876 INSN_CODE (i3) = insn_code_number;
1877 PATTERN (i3) = newpat;
1878 if (undobuf.other_insn)
1879 INSN_CODE (undobuf.other_insn) = other_code_number;
1881 /* We had one special case above where I2 had more than one set and
1882 we replaced a destination of one of those sets with the destination
1883 of I3. In that case, we have to update LOG_LINKS of insns later
1884 in this basic block. Note that this (expensive) case is rare. */
1886 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1887 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1888 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1889 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1890 && ! find_reg_note (i2, REG_UNUSED,
1891 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1895 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1897 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1898 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1899 if (XEXP (link, 0) == i2)
1900 XEXP (link, 0) = i3;
1902 if (GET_CODE (insn) == CODE_LABEL
1903 || GET_CODE (insn) == JUMP_INSN)
1915 INSN_CODE (i2) = i2_code_number;
1916 PATTERN (i2) = newi2pat;
1920 PUT_CODE (i2, NOTE);
1921 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1922 NOTE_SOURCE_FILE (i2) = 0;
1929 PUT_CODE (i1, NOTE);
1930 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1931 NOTE_SOURCE_FILE (i1) = 0;
1934 /* Get death notes for everything that is now used in either I3 or
1935 I2 and used to die in a previous insn. */
1937 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1939 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1941 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1943 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
1946 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
1949 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
1952 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1955 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1956 know these are REG_UNUSED and want them to go to the desired insn,
1957 so we always pass it as i3. We have not counted the notes in
1958 reg_n_deaths yet, so we need to do so now. */
1960 if (newi2pat && new_i2_notes)
1962 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
1963 if (GET_CODE (XEXP (temp, 0)) == REG)
1964 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
1966 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
1971 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
1972 if (GET_CODE (XEXP (temp, 0)) == REG)
1973 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
1975 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
1978 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1979 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
1980 Show an additional death due to the REG_DEAD note we make here. If
1981 we discard it in distribute_notes, we will decrement it again. */
1985 if (GET_CODE (i3dest_killed) == REG)
1986 reg_n_deaths[REGNO (i3dest_killed)]++;
1988 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
1990 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
1991 NULL_RTX, NULL_RTX);
1994 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
1995 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
1996 we passed I3 in that case, it might delete I2. */
1998 if (i2dest_in_i2src)
2000 if (GET_CODE (i2dest) == REG)
2001 reg_n_deaths[REGNO (i2dest)]++;
2003 if (newi2pat && reg_set_p (i2dest, newi2pat))
2004 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2005 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2007 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2008 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2009 NULL_RTX, NULL_RTX);
2012 if (i1dest_in_i1src)
2014 if (GET_CODE (i1dest) == REG)
2015 reg_n_deaths[REGNO (i1dest)]++;
2017 if (newi2pat && reg_set_p (i1dest, newi2pat))
2018 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2019 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2021 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2022 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2023 NULL_RTX, NULL_RTX);
2026 distribute_links (i3links);
2027 distribute_links (i2links);
2028 distribute_links (i1links);
2030 if (GET_CODE (i2dest) == REG)
2033 rtx i2_insn = 0, i2_val = 0, set;
2035 /* The insn that used to set this register doesn't exist, and
2036 this life of the register may not exist either. See if one of
2037 I3's links points to an insn that sets I2DEST. If it does,
2038 that is now the last known value for I2DEST. If we don't update
2039 this and I2 set the register to a value that depended on its old
2040 contents, we will get confused. If this insn is used, thing
2041 will be set correctly in combine_instructions. */
2043 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2044 if ((set = single_set (XEXP (link, 0))) != 0
2045 && rtx_equal_p (i2dest, SET_DEST (set)))
2046 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2048 record_value_for_reg (i2dest, i2_insn, i2_val);
2050 /* If the reg formerly set in I2 died only once and that was in I3,
2051 zero its use count so it won't make `reload' do any work. */
2052 if (! added_sets_2 && newi2pat == 0)
2054 regno = REGNO (i2dest);
2055 reg_n_sets[regno]--;
2056 if (reg_n_sets[regno] == 0
2057 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2058 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2059 reg_n_refs[regno] = 0;
2063 if (i1 && GET_CODE (i1dest) == REG)
2066 rtx i1_insn = 0, i1_val = 0, set;
2068 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2069 if ((set = single_set (XEXP (link, 0))) != 0
2070 && rtx_equal_p (i1dest, SET_DEST (set)))
2071 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2073 record_value_for_reg (i1dest, i1_insn, i1_val);
2075 regno = REGNO (i1dest);
2078 reg_n_sets[regno]--;
2079 if (reg_n_sets[regno] == 0
2080 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2081 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2082 reg_n_refs[regno] = 0;
2086 /* Update reg_nonzero_bits et al for any changes that may have been made
2089 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2091 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2093 /* If I3 is now an unconditional jump, ensure that it has a
2094 BARRIER following it since it may have initially been a
2095 conditional jump. It may also be the last nonnote insn. */
2097 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2098 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2099 || GET_CODE (temp) != BARRIER))
2100 emit_barrier_after (i3);
2103 combine_successes++;
2105 return newi2pat ? i2 : i3;
2108 /* Undo all the modifications recorded in undobuf. */
2114 if (undobuf.num_undo > MAX_UNDO)
2115 undobuf.num_undo = MAX_UNDO;
2116 for (i = undobuf.num_undo - 1; i >= 0; i--)
2118 if (undobuf.undo[i].is_int)
2119 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2121 *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
2125 obfree (undobuf.storage);
2126 undobuf.num_undo = 0;
2129 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2130 where we have an arithmetic expression and return that point. LOC will
2133 try_combine will call this function to see if an insn can be split into
2137 find_split_point (loc, insn)
2142 enum rtx_code code = GET_CODE (x);
2144 int len = 0, pos, unsignedp;
2147 /* First special-case some codes. */
2151 #ifdef INSN_SCHEDULING
2152 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2154 if (GET_CODE (SUBREG_REG (x)) == MEM)
2157 return find_split_point (&SUBREG_REG (x), insn);
2161 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2162 using LO_SUM and HIGH. */
2163 if (GET_CODE (XEXP (x, 0)) == CONST
2164 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2167 gen_rtx_combine (LO_SUM, Pmode,
2168 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2170 return &XEXP (XEXP (x, 0), 0);
2174 /* If we have a PLUS whose second operand is a constant and the
2175 address is not valid, perhaps will can split it up using
2176 the machine-specific way to split large constants. We use
2177 the first psuedo-reg (one of the virtual regs) as a placeholder;
2178 it will not remain in the result. */
2179 if (GET_CODE (XEXP (x, 0)) == PLUS
2180 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2181 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2183 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2184 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2187 /* This should have produced two insns, each of which sets our
2188 placeholder. If the source of the second is a valid address,
2189 we can make put both sources together and make a split point
2192 if (seq && XVECLEN (seq, 0) == 2
2193 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2194 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2195 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2196 && ! reg_mentioned_p (reg,
2197 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2198 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2199 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2200 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2201 && memory_address_p (GET_MODE (x),
2202 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2204 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2205 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2207 /* Replace the placeholder in SRC2 with SRC1. If we can
2208 find where in SRC2 it was placed, that can become our
2209 split point and we can replace this address with SRC2.
2210 Just try two obvious places. */
2212 src2 = replace_rtx (src2, reg, src1);
2214 if (XEXP (src2, 0) == src1)
2215 split = &XEXP (src2, 0);
2216 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2217 && XEXP (XEXP (src2, 0), 0) == src1)
2218 split = &XEXP (XEXP (src2, 0), 0);
2222 SUBST (XEXP (x, 0), src2);
2227 /* If that didn't work, perhaps the first operand is complex and
2228 needs to be computed separately, so make a split point there.
2229 This will occur on machines that just support REG + CONST
2230 and have a constant moved through some previous computation. */
2232 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2233 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2234 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2236 return &XEXP (XEXP (x, 0), 0);
2242 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2243 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2244 we need to put the operand into a register. So split at that
2247 if (SET_DEST (x) == cc0_rtx
2248 && GET_CODE (SET_SRC (x)) != COMPARE
2249 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2250 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2251 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2252 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2253 return &SET_SRC (x);
2256 /* See if we can split SET_SRC as it stands. */
2257 split = find_split_point (&SET_SRC (x), insn);
2258 if (split && split != &SET_SRC (x))
2261 /* See if this is a bitfield assignment with everything constant. If
2262 so, this is an IOR of an AND, so split it into that. */
2263 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2264 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2265 <= HOST_BITS_PER_WIDE_INT)
2266 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2267 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2268 && GET_CODE (SET_SRC (x)) == CONST_INT
2269 && ((INTVAL (XEXP (SET_DEST (x), 1))
2270 + INTVAL (XEXP (SET_DEST (x), 2)))
2271 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2272 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2274 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2275 int len = INTVAL (XEXP (SET_DEST (x), 1));
2276 int src = INTVAL (SET_SRC (x));
2277 rtx dest = XEXP (SET_DEST (x), 0);
2278 enum machine_mode mode = GET_MODE (dest);
2279 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2282 pos = GET_MODE_BITSIZE (mode) - len - pos;
2287 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2290 gen_binary (IOR, mode,
2291 gen_binary (AND, mode, dest,
2292 GEN_INT (~ (mask << pos)
2293 & GET_MODE_MASK (mode))),
2294 GEN_INT (src << pos)));
2296 SUBST (SET_DEST (x), dest);
2298 split = find_split_point (&SET_SRC (x), insn);
2299 if (split && split != &SET_SRC (x))
2303 /* Otherwise, see if this is an operation that we can split into two.
2304 If so, try to split that. */
2305 code = GET_CODE (SET_SRC (x));
2310 /* If we are AND'ing with a large constant that is only a single
2311 bit and the result is only being used in a context where we
2312 need to know if it is zero or non-zero, replace it with a bit
2313 extraction. This will avoid the large constant, which might
2314 have taken more than one insn to make. If the constant were
2315 not a valid argument to the AND but took only one insn to make,
2316 this is no worse, but if it took more than one insn, it will
2319 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2320 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2321 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2322 && GET_CODE (SET_DEST (x)) == REG
2323 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2324 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2325 && XEXP (*split, 0) == SET_DEST (x)
2326 && XEXP (*split, 1) == const0_rtx)
2329 make_extraction (GET_MODE (SET_DEST (x)),
2330 XEXP (SET_SRC (x), 0),
2331 pos, NULL_RTX, 1, 1, 0, 0));
2332 return find_split_point (loc, insn);
2337 inner = XEXP (SET_SRC (x), 0);
2339 len = GET_MODE_BITSIZE (GET_MODE (inner));
2345 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2346 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2348 inner = XEXP (SET_SRC (x), 0);
2349 len = INTVAL (XEXP (SET_SRC (x), 1));
2350 pos = INTVAL (XEXP (SET_SRC (x), 2));
2353 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2355 unsignedp = (code == ZERO_EXTRACT);
2360 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2362 enum machine_mode mode = GET_MODE (SET_SRC (x));
2364 /* For unsigned, we have a choice of a shift followed by an
2365 AND or two shifts. Use two shifts for field sizes where the
2366 constant might be too large. We assume here that we can
2367 always at least get 8-bit constants in an AND insn, which is
2368 true for every current RISC. */
2370 if (unsignedp && len <= 8)
2375 gen_rtx_combine (LSHIFTRT, mode,
2376 gen_lowpart_for_combine (mode, inner),
2378 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2380 split = find_split_point (&SET_SRC (x), insn);
2381 if (split && split != &SET_SRC (x))
2388 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2389 gen_rtx_combine (ASHIFT, mode,
2390 gen_lowpart_for_combine (mode, inner),
2391 GEN_INT (GET_MODE_BITSIZE (mode)
2393 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2395 split = find_split_point (&SET_SRC (x), insn);
2396 if (split && split != &SET_SRC (x))
2401 /* See if this is a simple operation with a constant as the second
2402 operand. It might be that this constant is out of range and hence
2403 could be used as a split point. */
2404 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2405 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2406 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2407 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2408 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2409 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2410 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2412 return &XEXP (SET_SRC (x), 1);
2414 /* Finally, see if this is a simple operation with its first operand
2415 not in a register. The operation might require this operand in a
2416 register, so return it as a split point. We can always do this
2417 because if the first operand were another operation, we would have
2418 already found it as a split point. */
2419 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2420 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2421 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2422 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2423 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2424 return &XEXP (SET_SRC (x), 0);
2430 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2431 it is better to write this as (not (ior A B)) so we can split it.
2432 Similarly for IOR. */
2433 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2436 gen_rtx_combine (NOT, GET_MODE (x),
2437 gen_rtx_combine (code == IOR ? AND : IOR,
2439 XEXP (XEXP (x, 0), 0),
2440 XEXP (XEXP (x, 1), 0))));
2441 return find_split_point (loc, insn);
2444 /* Many RISC machines have a large set of logical insns. If the
2445 second operand is a NOT, put it first so we will try to split the
2446 other operand first. */
2447 if (GET_CODE (XEXP (x, 1)) == NOT)
2449 rtx tem = XEXP (x, 0);
2450 SUBST (XEXP (x, 0), XEXP (x, 1));
2451 SUBST (XEXP (x, 1), tem);
2456 /* Otherwise, select our actions depending on our rtx class. */
2457 switch (GET_RTX_CLASS (code))
2459 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2461 split = find_split_point (&XEXP (x, 2), insn);
2464 /* ... fall through ... */
2468 split = find_split_point (&XEXP (x, 1), insn);
2471 /* ... fall through ... */
2473 /* Some machines have (and (shift ...) ...) insns. If X is not
2474 an AND, but XEXP (X, 0) is, use it as our split point. */
2475 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2476 return &XEXP (x, 0);
2478 split = find_split_point (&XEXP (x, 0), insn);
2484 /* Otherwise, we don't have a split point. */
2488 /* Throughout X, replace FROM with TO, and return the result.
2489 The result is TO if X is FROM;
2490 otherwise the result is X, but its contents may have been modified.
2491 If they were modified, a record was made in undobuf so that
2492 undo_all will (among other things) return X to its original state.
2494 If the number of changes necessary is too much to record to undo,
2495 the excess changes are not made, so the result is invalid.
2496 The changes already made can still be undone.
2497 undobuf.num_undo is incremented for such changes, so by testing that
2498 the caller can tell whether the result is valid.
2500 `n_occurrences' is incremented each time FROM is replaced.
2502 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2504 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2505 by copying if `n_occurrences' is non-zero. */
2508 subst (x, from, to, in_dest, unique_copy)
2509 register rtx x, from, to;
2514 register int len, i;
2515 register enum rtx_code code = GET_CODE (x), orig_code = code;
2517 enum machine_mode mode = GET_MODE (x);
2518 enum machine_mode op0_mode = VOIDmode;
2523 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2524 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2525 If it is 0, that cannot be done. We can now do this for any MEM
2526 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2527 If not for that, MEM's would very rarely be safe. */
2529 /* Reject MODEs bigger than a word, because we might not be able
2530 to reference a two-register group starting with an arbitrary register
2531 (and currently gen_lowpart might crash for a SUBREG). */
2533 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2534 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2536 /* Two expressions are equal if they are identical copies of a shared
2537 RTX or if they are both registers with the same register number
2540 #define COMBINE_RTX_EQUAL_P(X,Y) \
2542 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2543 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2545 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2548 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2551 /* If X and FROM are the same register but different modes, they will
2552 not have been seen as equal above. However, flow.c will make a
2553 LOG_LINKS entry for that case. If we do nothing, we will try to
2554 rerecognize our original insn and, when it succeeds, we will
2555 delete the feeding insn, which is incorrect.
2557 So force this insn not to match in this (rare) case. */
2558 if (! in_dest && code == REG && GET_CODE (from) == REG
2559 && REGNO (x) == REGNO (from))
2560 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2562 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2563 of which may contain things that can be combined. */
2564 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2567 /* It is possible to have a subexpression appear twice in the insn.
2568 Suppose that FROM is a register that appears within TO.
2569 Then, after that subexpression has been scanned once by `subst',
2570 the second time it is scanned, TO may be found. If we were
2571 to scan TO here, we would find FROM within it and create a
2572 self-referent rtl structure which is completely wrong. */
2573 if (COMBINE_RTX_EQUAL_P (x, to))
2576 len = GET_RTX_LENGTH (code);
2577 fmt = GET_RTX_FORMAT (code);
2579 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2580 set up to skip this common case. All other cases where we want to
2581 suppress replacing something inside a SET_SRC are handled via the
2584 && (GET_CODE (SET_DEST (x)) == REG
2585 || GET_CODE (SET_DEST (x)) == CC0
2586 || GET_CODE (SET_DEST (x)) == PC))
2589 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2591 op0_mode = GET_MODE (XEXP (x, 0));
2593 for (i = 0; i < len; i++)
2598 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2601 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2603 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2608 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2610 /* If this substitution failed, this whole thing fails. */
2611 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2615 SUBST (XVECEXP (x, i, j), new);
2618 else if (fmt[i] == 'e')
2622 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2624 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2628 /* If we are in a SET_DEST, suppress most cases unless we
2629 have gone inside a MEM, in which case we want to
2630 simplify the address. We assume here that things that
2631 are actually part of the destination have their inner
2632 parts in the first expression. This is true for SUBREG,
2633 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2634 things aside from REG and MEM that should appear in a
2636 new = subst (XEXP (x, i), from, to,
2638 && (code == SUBREG || code == STRICT_LOW_PART
2639 || code == ZERO_EXTRACT))
2641 && i == 0), unique_copy);
2643 /* If we found that we will have to reject this combination,
2644 indicate that by returning the CLOBBER ourselves, rather than
2645 an expression containing it. This will speed things up as
2646 well as prevent accidents where two CLOBBERs are considered
2647 to be equal, thus producing an incorrect simplification. */
2649 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2652 SUBST (XEXP (x, i), new);
2656 /* We come back to here if we have replaced the expression with one of
2657 a different code and it is likely that further simplification will be
2662 /* If we have restarted more than 4 times, we are probably looping, so
2664 if (++n_restarts > 4)
2667 /* If we are restarting at all, it means that we no longer know the
2668 original mode of operand 0 (since we have probably changed the
2672 op0_mode = VOIDmode;
2674 code = GET_CODE (x);
2676 /* If this is a commutative operation, put a constant last and a complex
2677 expression first. We don't need to do this for comparisons here. */
2678 if (GET_RTX_CLASS (code) == 'c'
2679 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2680 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2681 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2682 || (GET_CODE (XEXP (x, 0)) == SUBREG
2683 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2684 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2687 SUBST (XEXP (x, 0), XEXP (x, 1));
2688 SUBST (XEXP (x, 1), temp);
2691 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2692 sign extension of a PLUS with a constant, reverse the order of the sign
2693 extension and the addition. Note that this not the same as the original
2694 code, but overflow is undefined for signed values. Also note that the
2695 PLUS will have been partially moved "inside" the sign-extension, so that
2696 the first operand of X will really look like:
2697 (ashiftrt (plus (ashift A C4) C5) C4).
2699 (plus (ashiftrt (ashift A C4) C2) C4)
2700 and replace the first operand of X with that expression. Later parts
2701 of this function may simplify the expression further.
2703 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2704 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2705 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2707 We do this to simplify address expressions. */
2709 if ((code == PLUS || code == MINUS || code == MULT)
2710 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2711 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2712 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2713 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2714 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2715 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2716 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2717 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2718 XEXP (XEXP (XEXP (x, 0), 0), 1),
2719 XEXP (XEXP (x, 0), 1))) != 0)
2722 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2723 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2724 INTVAL (XEXP (XEXP (x, 0), 1)));
2726 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2727 INTVAL (XEXP (XEXP (x, 0), 1)));
2729 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2732 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2733 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2734 things. Don't deal with operations that change modes here. */
2736 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2737 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2739 /* Don't do this by using SUBST inside X since we might be messing
2740 up a shared expression. */
2741 rtx cond = XEXP (XEXP (x, 0), 0);
2742 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2744 pc_rtx, pc_rtx, 0, 0);
2745 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2747 pc_rtx, pc_rtx, 0, 0);
2750 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2754 else if (GET_RTX_CLASS (code) == '1'
2755 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2756 && GET_MODE (XEXP (x, 0)) == mode)
2758 rtx cond = XEXP (XEXP (x, 0), 0);
2759 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2760 pc_rtx, pc_rtx, 0, 0);
2761 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2762 pc_rtx, pc_rtx, 0, 0);
2764 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2768 /* Try to fold this expression in case we have constants that weren't
2771 switch (GET_RTX_CLASS (code))
2774 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2777 temp = simplify_relational_operation (code, op0_mode,
2778 XEXP (x, 0), XEXP (x, 1));
2779 #ifdef FLOAT_STORE_FLAG_VALUE
2780 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2781 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2782 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2787 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2791 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2792 XEXP (x, 1), XEXP (x, 2));
2797 x = temp, code = GET_CODE (temp);
2799 /* First see if we can apply the inverse distributive law. */
2800 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2802 x = apply_distributive_law (x);
2803 code = GET_CODE (x);
2806 /* If CODE is an associative operation not otherwise handled, see if we
2807 can associate some operands. This can win if they are constants or
2808 if they are logically related (i.e. (a & b) & a. */
2809 if ((code == PLUS || code == MINUS
2810 || code == MULT || code == AND || code == IOR || code == XOR
2811 || code == DIV || code == UDIV
2812 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2813 && GET_MODE_CLASS (mode) == MODE_INT)
2815 if (GET_CODE (XEXP (x, 0)) == code)
2817 rtx other = XEXP (XEXP (x, 0), 0);
2818 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2819 rtx inner_op1 = XEXP (x, 1);
2822 /* Make sure we pass the constant operand if any as the second
2823 one if this is a commutative operation. */
2824 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2826 rtx tem = inner_op0;
2827 inner_op0 = inner_op1;
2830 inner = simplify_binary_operation (code == MINUS ? PLUS
2831 : code == DIV ? MULT
2832 : code == UDIV ? MULT
2834 mode, inner_op0, inner_op1);
2836 /* For commutative operations, try the other pair if that one
2838 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2840 other = XEXP (XEXP (x, 0), 1);
2841 inner = simplify_binary_operation (code, mode,
2842 XEXP (XEXP (x, 0), 0),
2848 x = gen_binary (code, mode, other, inner);
2855 /* A little bit of algebraic simplification here. */
2859 /* Ensure that our address has any ASHIFTs converted to MULT in case
2860 address-recognizing predicates are called later. */
2861 temp = make_compound_operation (XEXP (x, 0), MEM);
2862 SUBST (XEXP (x, 0), temp);
2866 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2867 is paradoxical. If we can't do that safely, then it becomes
2868 something nonsensical so that this combination won't take place. */
2870 if (GET_CODE (SUBREG_REG (x)) == MEM
2871 && (GET_MODE_SIZE (mode)
2872 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2874 rtx inner = SUBREG_REG (x);
2875 int endian_offset = 0;
2876 /* Don't change the mode of the MEM
2877 if that would change the meaning of the address. */
2878 if (MEM_VOLATILE_P (SUBREG_REG (x))
2879 || mode_dependent_address_p (XEXP (inner, 0)))
2880 return gen_rtx (CLOBBER, mode, const0_rtx);
2882 #if BYTES_BIG_ENDIAN
2883 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2884 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2885 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2886 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2888 /* Note if the plus_constant doesn't make a valid address
2889 then this combination won't be accepted. */
2890 x = gen_rtx (MEM, mode,
2891 plus_constant (XEXP (inner, 0),
2892 (SUBREG_WORD (x) * UNITS_PER_WORD
2894 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2895 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2896 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2900 /* If we are in a SET_DEST, these other cases can't apply. */
2904 /* Changing mode twice with SUBREG => just change it once,
2905 or not at all if changing back to starting mode. */
2906 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2908 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2909 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2910 return SUBREG_REG (SUBREG_REG (x));
2912 SUBST_INT (SUBREG_WORD (x),
2913 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2914 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2917 /* SUBREG of a hard register => just change the register number
2918 and/or mode. If the hard register is not valid in that mode,
2919 suppress this combination. If the hard register is the stack,
2920 frame, or argument pointer, leave this as a SUBREG. */
2922 if (GET_CODE (SUBREG_REG (x)) == REG
2923 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
2924 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
2925 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
2926 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
2928 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
2930 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2932 return gen_rtx (REG, mode,
2933 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2935 return gen_rtx (CLOBBER, mode, const0_rtx);
2938 /* For a constant, try to pick up the part we want. Handle a full
2939 word and low-order part. Only do this if we are narrowing
2940 the constant; if it is being widened, we have no idea what
2941 the extra bits will have been set to. */
2943 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2944 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2945 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
2946 && GET_MODE_CLASS (mode) == MODE_INT)
2948 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2954 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2955 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
2956 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2958 /* If we are narrowing the object, we need to see if we can simplify
2959 the expression for the object knowing that we only need the
2962 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2963 && subreg_lowpart_p (x))
2964 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
2969 /* (not (plus X -1)) can become (neg X). */
2970 if (GET_CODE (XEXP (x, 0)) == PLUS
2971 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2973 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2977 /* Similarly, (not (neg X)) is (plus X -1). */
2978 if (GET_CODE (XEXP (x, 0)) == NEG)
2980 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2984 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
2985 if (GET_CODE (XEXP (x, 0)) == XOR
2986 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2987 && (temp = simplify_unary_operation (NOT, mode,
2988 XEXP (XEXP (x, 0), 1),
2991 SUBST (XEXP (XEXP (x, 0), 1), temp);
2995 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2996 other than 1, but that is not valid. We could do a similar
2997 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2998 but this doesn't seem common enough to bother with. */
2999 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3000 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3002 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3003 XEXP (XEXP (x, 0), 1));
3007 if (GET_CODE (XEXP (x, 0)) == SUBREG
3008 && subreg_lowpart_p (XEXP (x, 0))
3009 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3010 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3011 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3012 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3014 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3016 x = gen_rtx (ROTATE, inner_mode,
3017 gen_unary (NOT, inner_mode, const1_rtx),
3018 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3019 x = gen_lowpart_for_combine (mode, x);
3023 #if STORE_FLAG_VALUE == -1
3024 /* (not (comparison foo bar)) can be done by reversing the comparison
3026 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3027 && reversible_comparison_p (XEXP (x, 0)))
3028 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3029 mode, XEXP (XEXP (x, 0), 0),
3030 XEXP (XEXP (x, 0), 1));
3033 /* Apply De Morgan's laws to reduce number of patterns for machines
3034 with negating logical insns (and-not, nand, etc.). If result has
3035 only one NOT, put it first, since that is how the patterns are
3038 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3040 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3042 if (GET_CODE (in1) == NOT)
3043 in1 = XEXP (in1, 0);
3045 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3047 if (GET_CODE (in2) == NOT)
3048 in2 = XEXP (in2, 0);
3049 else if (GET_CODE (in2) == CONST_INT
3050 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3051 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3053 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3055 if (GET_CODE (in2) == NOT)
3058 in2 = in1; in1 = tem;
3061 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3068 /* (neg (plus X 1)) can become (not X). */
3069 if (GET_CODE (XEXP (x, 0)) == PLUS
3070 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3072 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3076 /* Similarly, (neg (not X)) is (plus X 1). */
3077 if (GET_CODE (XEXP (x, 0)) == NOT)
3079 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3083 /* (neg (minus X Y)) can become (minus Y X). */
3084 if (GET_CODE (XEXP (x, 0)) == MINUS
3085 && (GET_MODE_CLASS (mode) != MODE_FLOAT
3086 /* x-y != -(y-x) with IEEE floating point. */
3087 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3089 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3090 XEXP (XEXP (x, 0), 0));
3094 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3095 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3096 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3098 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3102 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3103 if we can then eliminate the NEG (e.g.,
3104 if the operand is a constant). */
3106 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3108 temp = simplify_unary_operation (NEG, mode,
3109 XEXP (XEXP (x, 0), 0), mode);
3112 SUBST (XEXP (XEXP (x, 0), 0), temp);
3117 temp = expand_compound_operation (XEXP (x, 0));
3119 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3120 replaced by (lshiftrt X C). This will convert
3121 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3123 if (GET_CODE (temp) == ASHIFTRT
3124 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3125 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3127 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3128 INTVAL (XEXP (temp, 1)));
3132 /* If X has only a single bit that might be nonzero, say, bit I, convert
3133 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3134 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3135 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3136 or a SUBREG of one since we'd be making the expression more
3137 complex if it was just a register. */
3139 if (GET_CODE (temp) != REG
3140 && ! (GET_CODE (temp) == SUBREG
3141 && GET_CODE (SUBREG_REG (temp)) == REG)
3142 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3144 rtx temp1 = simplify_shift_const
3145 (NULL_RTX, ASHIFTRT, mode,
3146 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3147 GET_MODE_BITSIZE (mode) - 1 - i),
3148 GET_MODE_BITSIZE (mode) - 1 - i);
3150 /* If all we did was surround TEMP with the two shifts, we
3151 haven't improved anything, so don't use it. Otherwise,
3152 we are better off with TEMP1. */
3153 if (GET_CODE (temp1) != ASHIFTRT
3154 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3155 || XEXP (XEXP (temp1, 0), 0) != temp)
3163 case FLOAT_TRUNCATE:
3164 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3165 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3166 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3167 return XEXP (XEXP (x, 0), 0);
3172 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3173 using cc0, in which case we want to leave it as a COMPARE
3174 so we can distinguish it from a register-register-copy. */
3175 if (XEXP (x, 1) == const0_rtx)
3178 /* In IEEE floating point, x-0 is not the same as x. */
3179 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3180 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
3181 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3187 /* (const (const X)) can become (const X). Do it this way rather than
3188 returning the inner CONST since CONST can be shared with a
3190 if (GET_CODE (XEXP (x, 0)) == CONST)
3191 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3196 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3197 can add in an offset. find_split_point will split this address up
3198 again if it doesn't match. */
3199 if (GET_CODE (XEXP (x, 0)) == HIGH
3200 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3206 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3207 outermost. That's because that's the way indexed addresses are
3208 supposed to appear. This code used to check many more cases, but
3209 they are now checked elsewhere. */
3210 if (GET_CODE (XEXP (x, 0)) == PLUS
3211 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3212 return gen_binary (PLUS, mode,
3213 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3215 XEXP (XEXP (x, 0), 1));
3217 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3218 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3219 bit-field and can be replaced by either a sign_extend or a
3220 sign_extract. The `and' may be a zero_extend. */
3221 if (GET_CODE (XEXP (x, 0)) == XOR
3222 && GET_CODE (XEXP (x, 1)) == CONST_INT
3223 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3224 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3225 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3226 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3227 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3228 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3229 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3230 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3231 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3232 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3235 x = simplify_shift_const
3236 (NULL_RTX, ASHIFTRT, mode,
3237 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3238 XEXP (XEXP (XEXP (x, 0), 0), 0),
3239 GET_MODE_BITSIZE (mode) - (i + 1)),
3240 GET_MODE_BITSIZE (mode) - (i + 1));
3244 /* If only the low-order bit of X is possible nonzero, (plus x -1)
3245 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3246 the bitsize of the mode - 1. This allows simplification of
3247 "a = (b & 8) == 0;" */
3248 if (XEXP (x, 1) == constm1_rtx
3249 && GET_CODE (XEXP (x, 0)) != REG
3250 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3251 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3252 && nonzero_bits (XEXP (x, 0), mode) == 1)
3254 x = simplify_shift_const
3255 (NULL_RTX, ASHIFTRT, mode,
3256 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3257 gen_rtx_combine (XOR, mode,
3258 XEXP (x, 0), const1_rtx),
3259 GET_MODE_BITSIZE (mode) - 1),
3260 GET_MODE_BITSIZE (mode) - 1);
3264 /* If we are adding two things that have no bits in common, convert
3265 the addition into an IOR. This will often be further simplified,
3266 for example in cases like ((a & 1) + (a & 2)), which can
3269 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3270 && (nonzero_bits (XEXP (x, 0), mode)
3271 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3273 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3279 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3280 (and <foo> (const_int pow2-1)) */
3281 if (GET_CODE (XEXP (x, 1)) == AND
3282 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3283 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3284 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3286 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3287 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3293 /* If we have (mult (plus A B) C), apply the distributive law and then
3294 the inverse distributive law to see if things simplify. This
3295 occurs mostly in addresses, often when unrolling loops. */
3297 if (GET_CODE (XEXP (x, 0)) == PLUS)
3299 x = apply_distributive_law
3300 (gen_binary (PLUS, mode,
3301 gen_binary (MULT, mode,
3302 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3303 gen_binary (MULT, mode,
3304 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3306 if (GET_CODE (x) != MULT)
3310 /* If this is multiplication by a power of two and its first operand is
3311 a shift, treat the multiply as a shift to allow the shifts to
3312 possibly combine. */
3313 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3314 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3315 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3316 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3317 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3318 || GET_CODE (XEXP (x, 0)) == ROTATE
3319 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3321 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3325 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3326 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3327 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3328 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3329 XEXP (XEXP (x, 0), 1));
3333 /* If this is a divide by a power of two, treat it as a shift if
3334 its first operand is a shift. */
3335 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3336 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3337 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3338 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3339 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3340 || GET_CODE (XEXP (x, 0)) == ROTATE
3341 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3343 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3349 case GT: case GTU: case GE: case GEU:
3350 case LT: case LTU: case LE: case LEU:
3351 /* If the first operand is a condition code, we can't do anything
3353 if (GET_CODE (XEXP (x, 0)) == COMPARE
3354 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3356 && XEXP (x, 0) != cc0_rtx
3360 rtx op0 = XEXP (x, 0);
3361 rtx op1 = XEXP (x, 1);
3362 enum rtx_code new_code;
3364 if (GET_CODE (op0) == COMPARE)
3365 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3367 /* Simplify our comparison, if possible. */
3368 new_code = simplify_comparison (code, &op0, &op1);
3370 #if STORE_FLAG_VALUE == 1
3371 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3372 if only the low-order bit is possibly nonzero in X (such as when
3373 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3374 EQ to (xor X 1). Remove any ZERO_EXTRACT we made when thinking
3375 this was a comparison. It may now be simpler to use, e.g., an
3376 AND. If a ZERO_EXTRACT is indeed appropriate, it will
3377 be placed back by the call to make_compound_operation in the
3379 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3380 && op1 == const0_rtx
3381 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3382 return gen_lowpart_for_combine (mode,
3383 expand_compound_operation (op0));
3384 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3385 && op1 == const0_rtx
3386 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3388 op0 = expand_compound_operation (op0);
3390 x = gen_rtx_combine (XOR, mode,
3391 gen_lowpart_for_combine (mode, op0),
3397 #if STORE_FLAG_VALUE == -1
3398 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3399 to (neg x) if only the low-order bit of X can be nonzero.
3400 This converts (ne (zero_extract X 1 Y) 0) to
3401 (sign_extract X 1 Y). */
3402 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3403 && op1 == const0_rtx
3404 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3406 op0 = expand_compound_operation (op0);
3407 x = gen_rtx_combine (NEG, mode,
3408 gen_lowpart_for_combine (mode, op0));
3413 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3414 one bit that might be nonzero, we can convert (ne x 0) to
3415 (ashift x c) where C puts the bit in the sign bit. Remove any
3416 AND with STORE_FLAG_VALUE when we are done, since we are only
3417 going to test the sign bit. */
3418 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3419 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3420 && (STORE_FLAG_VALUE
3421 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3422 && op1 == const0_rtx
3423 && mode == GET_MODE (op0)
3424 && (i = exact_log2 (nonzero_bits (op0, GET_MODE (op0)))) >= 0)
3426 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3427 expand_compound_operation (op0),
3428 GET_MODE_BITSIZE (mode) - 1 - i);
3429 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3435 /* If the code changed, return a whole new comparison. */
3436 if (new_code != code)
3437 return gen_rtx_combine (new_code, mode, op0, op1);
3439 /* Otherwise, keep this operation, but maybe change its operands.
3440 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3441 SUBST (XEXP (x, 0), op0);
3442 SUBST (XEXP (x, 1), op1);
3447 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3448 used in it is being compared against certain values. Get the
3449 true and false comparisons and see if that says anything about the
3450 value of each arm. */
3452 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3453 && reversible_comparison_p (XEXP (x, 0))
3454 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3457 rtx from = XEXP (XEXP (x, 0), 0);
3458 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3459 enum rtx_code false_code = reverse_condition (true_code);
3460 rtx true_val = XEXP (XEXP (x, 0), 1);
3461 rtx false_val = true_val;
3462 rtx true_arm = XEXP (x, 1);
3463 rtx false_arm = XEXP (x, 2);
3466 /* If FALSE_CODE is EQ, swap the codes and arms. */
3468 if (false_code == EQ)
3470 swapped = 1, true_code = EQ, false_code = NE;
3471 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3474 /* If we are comparing against zero and the expression being tested
3475 has only a single bit that might be nonzero, that is its value
3476 when it is not equal to zero. Similarly if it is known to be
3479 if (true_code == EQ && true_val == const0_rtx
3480 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3481 false_code = EQ, false_val = GEN_INT (nzb);
3482 else if (true_code == EQ && true_val == const0_rtx
3483 && (num_sign_bit_copies (from, GET_MODE (from))
3484 == GET_MODE_BITSIZE (GET_MODE (from))))
3485 false_code = EQ, false_val = constm1_rtx;
3487 /* Now simplify an arm if we know the value of the register
3488 in the branch and it is used in the arm. Be carefull due to
3489 the potential of locally-shared RTL. */
3491 if (reg_mentioned_p (from, true_arm))
3492 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3494 pc_rtx, pc_rtx, 0, 0);
3495 if (reg_mentioned_p (from, false_arm))
3496 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3498 pc_rtx, pc_rtx, 0, 0);
3500 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3501 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3504 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3505 reversed, do so to avoid needing two sets of patterns for
3506 subtract-and-branch insns. Similarly if we have a constant in that
3507 position or if the third operand is the same as the first operand
3508 of the comparison. */
3510 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3511 && reversible_comparison_p (XEXP (x, 0))
3512 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3513 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3516 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3517 GET_MODE (XEXP (x, 0)),
3518 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3521 SUBST (XEXP (x, 1), XEXP (x, 2));
3522 SUBST (XEXP (x, 2), temp);
3525 /* If the two arms are identical, we don't need the comparison. */
3527 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3528 && ! side_effects_p (XEXP (x, 0)))
3531 /* Look for cases where we have (abs x) or (neg (abs X)). */
3533 if (GET_MODE_CLASS (mode) == MODE_INT
3534 && GET_CODE (XEXP (x, 2)) == NEG
3535 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3536 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3537 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3538 && ! side_effects_p (XEXP (x, 1)))
3539 switch (GET_CODE (XEXP (x, 0)))
3543 x = gen_unary (ABS, mode, XEXP (x, 1));
3547 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3551 /* Look for MIN or MAX. */
3553 if (GET_MODE_CLASS (mode) == MODE_INT
3554 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3555 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3556 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3557 && ! side_effects_p (XEXP (x, 0)))
3558 switch (GET_CODE (XEXP (x, 0)))
3562 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3566 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3570 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3574 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3578 /* If we have something like (if_then_else (ne A 0) (OP X C) X),
3579 A is known to be either 0 or 1, and OP is an identity when its
3580 second operand is zero, this can be done as (OP X (mult A C)).
3581 Similarly if A is known to be 0 or -1 and also similarly if we have
3582 a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
3583 we don't destroy it). */
3585 if (mode != VOIDmode
3586 && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
3587 && XEXP (XEXP (x, 0), 1) == const0_rtx
3588 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3589 || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3590 == GET_MODE_BITSIZE (mode))))
3592 rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
3593 ? XEXP (x, 1) : XEXP (x, 2));
3594 rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
3595 rtx dir = (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3596 ? const1_rtx : constm1_rtx);
3598 enum machine_mode m = mode;
3599 enum rtx_code op, extend_op = 0;
3601 if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
3602 || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
3603 || GET_CODE (nz) == ASHIFT
3604 || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
3605 && rtx_equal_p (XEXP (nz, 0), z))
3606 c = XEXP (nz, 1), op = GET_CODE (nz);
3607 else if (GET_CODE (nz) == SIGN_EXTEND
3608 && (GET_CODE (XEXP (nz, 0)) == PLUS
3609 || GET_CODE (XEXP (nz, 0)) == MINUS
3610 || GET_CODE (XEXP (nz, 0)) == IOR
3611 || GET_CODE (XEXP (nz, 0)) == XOR
3612 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3613 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3614 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3615 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3616 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3617 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3618 && (num_sign_bit_copies (z, GET_MODE (z))
3619 >= (GET_MODE_BITSIZE (mode)
3620 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
3622 c = XEXP (XEXP (nz, 0), 1);
3623 op = GET_CODE (XEXP (nz, 0));
3624 extend_op = SIGN_EXTEND;
3625 m = GET_MODE (XEXP (nz, 0));
3627 else if (GET_CODE (nz) == ZERO_EXTEND
3628 && (GET_CODE (XEXP (nz, 0)) == PLUS
3629 || GET_CODE (XEXP (nz, 0)) == MINUS
3630 || GET_CODE (XEXP (nz, 0)) == IOR
3631 || GET_CODE (XEXP (nz, 0)) == XOR
3632 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3633 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3634 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3635 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3636 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3637 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3638 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3639 && ((nonzero_bits (z, GET_MODE (z))
3640 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
3643 c = XEXP (XEXP (nz, 0), 1);
3644 op = GET_CODE (XEXP (nz, 0));
3645 extend_op = ZERO_EXTEND;
3646 m = GET_MODE (XEXP (nz, 0));
3649 if (c && ! side_effects_p (c) && ! side_effects_p (z))
3652 = gen_binary (MULT, m,
3653 gen_lowpart_for_combine (m,
3654 XEXP (XEXP (x, 0), 0)),
3655 gen_binary (MULT, m, c, dir));
3657 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3660 temp = gen_unary (extend_op, mode, temp);
3671 /* If we are processing SET_DEST, we are done. */
3675 x = expand_compound_operation (x);
3676 if (GET_CODE (x) != code)
3681 /* (set (pc) (return)) gets written as (return). */
3682 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3685 /* Convert this into a field assignment operation, if possible. */
3686 x = make_field_assignment (x);
3688 /* If we are setting CC0 or if the source is a COMPARE, look for the
3689 use of the comparison result and try to simplify it unless we already
3690 have used undobuf.other_insn. */
3691 if ((GET_CODE (SET_SRC (x)) == COMPARE
3693 || SET_DEST (x) == cc0_rtx
3696 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3698 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3699 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3700 && XEXP (*cc_use, 0) == SET_DEST (x))
3702 enum rtx_code old_code = GET_CODE (*cc_use);
3703 enum rtx_code new_code;
3705 int other_changed = 0;
3706 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3708 if (GET_CODE (SET_SRC (x)) == COMPARE)
3709 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3711 op0 = SET_SRC (x), op1 = const0_rtx;
3713 /* Simplify our comparison, if possible. */
3714 new_code = simplify_comparison (old_code, &op0, &op1);
3716 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3717 /* If this machine has CC modes other than CCmode, check to see
3718 if we need to use a different CC mode here. */
3719 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3721 /* If the mode changed, we have to change SET_DEST, the mode
3722 in the compare, and the mode in the place SET_DEST is used.
3723 If SET_DEST is a hard register, just build new versions with
3724 the proper mode. If it is a pseudo, we lose unless it is only
3725 time we set the pseudo, in which case we can safely change
3727 if (compare_mode != GET_MODE (SET_DEST (x)))
3729 int regno = REGNO (SET_DEST (x));
3730 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3732 if (regno < FIRST_PSEUDO_REGISTER
3733 || (reg_n_sets[regno] == 1
3734 && ! REG_USERVAR_P (SET_DEST (x))))
3736 if (regno >= FIRST_PSEUDO_REGISTER)
3737 SUBST (regno_reg_rtx[regno], new_dest);
3739 SUBST (SET_DEST (x), new_dest);
3740 SUBST (XEXP (*cc_use, 0), new_dest);
3746 /* If the code changed, we have to build a new comparison
3747 in undobuf.other_insn. */
3748 if (new_code != old_code)
3750 unsigned HOST_WIDE_INT mask;
3752 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3753 SET_DEST (x), const0_rtx));
3755 /* If the only change we made was to change an EQ into an
3756 NE or vice versa, OP0 has only one bit that might be nonzero,
3757 and OP1 is zero, check if changing the user of the condition
3758 code will produce a valid insn. If it won't, we can keep
3759 the original code in that insn by surrounding our operation
3762 if (((old_code == NE && new_code == EQ)
3763 || (old_code == EQ && new_code == NE))
3764 && ! other_changed && op1 == const0_rtx
3765 && (GET_MODE_BITSIZE (GET_MODE (op0))
3766 <= HOST_BITS_PER_WIDE_INT)
3767 && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0)))
3770 rtx pat = PATTERN (other_insn), note = 0;
3772 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
3773 && ! check_asm_operands (pat)))
3775 PUT_CODE (*cc_use, old_code);
3778 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3787 undobuf.other_insn = other_insn;
3790 /* If we are now comparing against zero, change our source if
3791 needed. If we do not use cc0, we always have a COMPARE. */
3792 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3793 SUBST (SET_SRC (x), op0);
3797 /* Otherwise, if we didn't previously have a COMPARE in the
3798 correct mode, we need one. */
3799 if (GET_CODE (SET_SRC (x)) != COMPARE
3800 || GET_MODE (SET_SRC (x)) != compare_mode)
3801 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3805 /* Otherwise, update the COMPARE if needed. */
3806 SUBST (XEXP (SET_SRC (x), 0), op0);
3807 SUBST (XEXP (SET_SRC (x), 1), op1);
3812 /* Get SET_SRC in a form where we have placed back any
3813 compound expressions. Then do the checks below. */
3814 temp = make_compound_operation (SET_SRC (x), SET);
3815 SUBST (SET_SRC (x), temp);
3818 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3819 operation, and X being a REG or (subreg (reg)), we may be able to
3820 convert this to (set (subreg:m2 x) (op)).
3822 We can always do this if M1 is narrower than M2 because that
3823 means that we only care about the low bits of the result.
3825 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3826 and BYTES_LOADS_SIGN_EXTEND not defined), we cannot perform a
3827 narrower operation that requested since the high-order bits will
3828 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
3829 however, this transformation is safe as long as M1 and M2 have
3830 the same number of words. */
3832 if (GET_CODE (SET_SRC (x)) == SUBREG
3833 && subreg_lowpart_p (SET_SRC (x))
3834 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3835 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3837 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3838 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3839 #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined (BYTE_LOADS_SIGN_EXTEND)
3840 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3841 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3843 && (GET_CODE (SET_DEST (x)) == REG
3844 || (GET_CODE (SET_DEST (x)) == SUBREG
3845 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3847 SUBST (SET_DEST (x),
3848 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
3850 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3853 #ifdef BYTE_LOADS_ZERO_EXTEND
3854 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3855 M wider than N, this would require a paradoxical subreg.
3856 Replace the subreg with a zero_extend to avoid the reload that
3857 would otherwise be required. */
3858 if (GET_CODE (SET_SRC (x)) == SUBREG
3859 && subreg_lowpart_p (SET_SRC (x))
3860 && SUBREG_WORD (SET_SRC (x)) == 0
3861 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3862 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3863 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3864 SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3865 GET_MODE (SET_SRC (x)),
3866 XEXP (SET_SRC (x), 0)));
3869 #ifndef HAVE_conditional_move
3871 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
3872 and we are comparing an item known to be 0 or -1 against 0, use a
3873 logical operation instead. Check for one of the arms being an IOR
3874 of the other arm with some value. We compute three terms to be
3875 IOR'ed together. In practice, at most two will be nonzero. Then
3878 if (GET_CODE (SET_DEST (x)) != PC
3879 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
3880 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
3881 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
3882 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
3883 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
3884 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
3885 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
3886 && ! side_effects_p (SET_SRC (x)))
3888 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3889 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
3890 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3891 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
3892 rtx term1 = const0_rtx, term2, term3;
3894 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
3895 term1 = false, true = XEXP (true, 1), false = const0_rtx;
3896 else if (GET_CODE (true) == IOR
3897 && rtx_equal_p (XEXP (true, 1), false))
3898 term1 = false, true = XEXP (true, 0), false = const0_rtx;
3899 else if (GET_CODE (false) == IOR
3900 && rtx_equal_p (XEXP (false, 0), true))
3901 term1 = true, false = XEXP (false, 1), true = const0_rtx;
3902 else if (GET_CODE (false) == IOR
3903 && rtx_equal_p (XEXP (false, 1), true))
3904 term1 = true, false = XEXP (false, 0), true = const0_rtx;
3906 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3907 XEXP (XEXP (SET_SRC (x), 0), 0), true);
3908 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
3909 gen_unary (NOT, GET_MODE (SET_SRC (x)),
3910 XEXP (XEXP (SET_SRC (x), 0), 0)),
3914 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3915 gen_binary (IOR, GET_MODE (SET_SRC (x)),
3923 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3925 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3926 INTVAL (XEXP (x, 1)));
3928 /* If we have (ior (and (X C1) C2)) and the next restart would be
3929 the last, simplify this by making C1 as small as possible
3931 if (n_restarts >= 3 && GET_CODE (x) == IOR
3932 && GET_CODE (XEXP (x, 0)) == AND
3933 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3934 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3936 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3937 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
3938 & ~ INTVAL (XEXP (x, 1))));
3939 return gen_binary (IOR, mode, temp, XEXP (x, 1));
3942 if (GET_CODE (x) != AND)
3946 /* Convert (A | B) & A to A. */
3947 if (GET_CODE (XEXP (x, 0)) == IOR
3948 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3949 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3950 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3951 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3954 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3955 insn (and may simplify more). */
3956 else if (GET_CODE (XEXP (x, 0)) == XOR
3957 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3958 && ! side_effects_p (XEXP (x, 1)))
3960 x = gen_binary (AND, mode,
3961 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3965 else if (GET_CODE (XEXP (x, 0)) == XOR
3966 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3967 && ! side_effects_p (XEXP (x, 1)))
3969 x = gen_binary (AND, mode,
3970 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3975 /* Similarly for (~ (A ^ B)) & A. */
3976 else if (GET_CODE (XEXP (x, 0)) == NOT
3977 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3978 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3979 && ! side_effects_p (XEXP (x, 1)))
3981 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3985 else if (GET_CODE (XEXP (x, 0)) == NOT
3986 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3987 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3988 && ! side_effects_p (XEXP (x, 1)))
3990 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3995 /* If we have (and A B) with A not an object but that is known to
3996 be -1 or 0, this is equivalent to the expression
3997 (if_then_else (ne A (const_int 0)) B (const_int 0))
3998 We make this conversion because it may allow further
3999 simplifications and then allow use of conditional move insns.
4000 If the machine doesn't have condition moves, code in case SET
4001 will convert the IF_THEN_ELSE back to the logical operation.
4002 We build the IF_THEN_ELSE here in case further simplification
4003 is possible (e.g., we can convert it to ABS). */
4005 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
4006 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4007 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
4008 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4009 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4011 rtx op0 = XEXP (x, 0);
4012 rtx op1 = const0_rtx;
4013 enum rtx_code comp_code
4014 = simplify_comparison (NE, &op0, &op1);
4016 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4017 gen_binary (comp_code, VOIDmode, op0, op1),
4018 XEXP (x, 1), const0_rtx);
4022 /* In the following group of tests (and those in case IOR below),
4023 we start with some combination of logical operations and apply
4024 the distributive law followed by the inverse distributive law.
4025 Most of the time, this results in no change. However, if some of
4026 the operands are the same or inverses of each other, simplifications
4029 For example, (and (ior A B) (not B)) can occur as the result of
4030 expanding a bit field assignment. When we apply the distributive
4031 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4032 which then simplifies to (and (A (not B))). */
4034 /* If we have (and (ior A B) C), apply the distributive law and then
4035 the inverse distributive law to see if things simplify. */
4037 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4039 x = apply_distributive_law
4040 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4041 gen_binary (AND, mode,
4042 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4043 gen_binary (AND, mode,
4044 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4045 if (GET_CODE (x) != AND)
4049 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4051 x = apply_distributive_law
4052 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4053 gen_binary (AND, mode,
4054 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4055 gen_binary (AND, mode,
4056 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4057 if (GET_CODE (x) != AND)
4061 /* Similarly, taking advantage of the fact that
4062 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4064 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4066 x = apply_distributive_law
4067 (gen_binary (XOR, mode,
4068 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4069 XEXP (XEXP (x, 1), 0)),
4070 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4071 XEXP (XEXP (x, 1), 1))));
4072 if (GET_CODE (x) != AND)
4076 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4078 x = apply_distributive_law
4079 (gen_binary (XOR, mode,
4080 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4081 XEXP (XEXP (x, 0), 0)),
4082 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4083 XEXP (XEXP (x, 0), 1))));
4084 if (GET_CODE (x) != AND)
4090 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4091 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4092 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4093 && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0)
4096 /* Convert (A & B) | A to A. */
4097 if (GET_CODE (XEXP (x, 0)) == AND
4098 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4099 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4100 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4101 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4104 /* If we have (ior (and A B) C), apply the distributive law and then
4105 the inverse distributive law to see if things simplify. */
4107 if (GET_CODE (XEXP (x, 0)) == AND)
4109 x = apply_distributive_law
4110 (gen_binary (AND, mode,
4111 gen_binary (IOR, mode,
4112 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4113 gen_binary (IOR, mode,
4114 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4116 if (GET_CODE (x) != IOR)
4120 if (GET_CODE (XEXP (x, 1)) == AND)
4122 x = apply_distributive_law
4123 (gen_binary (AND, mode,
4124 gen_binary (IOR, mode,
4125 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4126 gen_binary (IOR, mode,
4127 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4129 if (GET_CODE (x) != IOR)
4133 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4134 mode size to (rotate A CX). */
4136 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4137 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4138 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4139 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4140 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4141 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4142 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4143 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4144 == GET_MODE_BITSIZE (mode)))
4148 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4149 shift_count = XEXP (XEXP (x, 0), 1);
4151 shift_count = XEXP (XEXP (x, 1), 1);
4152 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4158 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4159 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4162 int num_negated = 0;
4163 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4165 if (GET_CODE (in1) == NOT)
4166 num_negated++, in1 = XEXP (in1, 0);
4167 if (GET_CODE (in2) == NOT)
4168 num_negated++, in2 = XEXP (in2, 0);
4170 if (num_negated == 2)
4172 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4173 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4175 else if (num_negated == 1)
4177 x = gen_unary (NOT, mode,
4178 gen_binary (XOR, mode, in1, in2));
4183 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4184 correspond to a machine insn or result in further simplifications
4185 if B is a constant. */
4187 if (GET_CODE (XEXP (x, 0)) == AND
4188 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4189 && ! side_effects_p (XEXP (x, 1)))
4191 x = gen_binary (AND, mode,
4192 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4196 else if (GET_CODE (XEXP (x, 0)) == AND
4197 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4198 && ! side_effects_p (XEXP (x, 1)))
4200 x = gen_binary (AND, mode,
4201 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4207 #if STORE_FLAG_VALUE == 1
4208 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4210 if (XEXP (x, 1) == const1_rtx
4211 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4212 && reversible_comparison_p (XEXP (x, 0)))
4213 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4214 mode, XEXP (XEXP (x, 0), 0),
4215 XEXP (XEXP (x, 0), 1));
4218 /* (xor (comparison foo bar) (const_int sign-bit))
4219 when STORE_FLAG_VALUE is the sign bit. */
4220 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4221 && (STORE_FLAG_VALUE
4222 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4223 && XEXP (x, 1) == const_true_rtx
4224 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4225 && reversible_comparison_p (XEXP (x, 0)))
4226 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4227 mode, XEXP (XEXP (x, 0), 0),
4228 XEXP (XEXP (x, 0), 1));
4232 /* (abs (neg <foo>)) -> (abs <foo>) */
4233 if (GET_CODE (XEXP (x, 0)) == NEG)
4234 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4236 /* If operand is something known to be positive, ignore the ABS. */
4237 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4238 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4239 <= HOST_BITS_PER_WIDE_INT)
4240 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4241 & ((HOST_WIDE_INT) 1
4242 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4247 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4248 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4250 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4256 /* (ffs (*_extend <X>)) = (ffs <X>) */
4257 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4258 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4259 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4263 /* (float (sign_extend <X>)) = (float <X>). */
4264 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4265 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4274 /* If this is a shift by a constant amount, simplify it. */
4275 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4277 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4278 INTVAL (XEXP (x, 1)));
4279 if (GET_CODE (x) != code)
4283 #ifdef SHIFT_COUNT_TRUNCATED
4284 else if (GET_CODE (XEXP (x, 1)) != REG)
4286 force_to_mode (XEXP (x, 1), GET_MODE (x),
4287 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4297 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4298 operations" because they can be replaced with two more basic operations.
4299 ZERO_EXTEND is also considered "compound" because it can be replaced with
4300 an AND operation, which is simpler, though only one operation.
4302 The function expand_compound_operation is called with an rtx expression
4303 and will convert it to the appropriate shifts and AND operations,
4304 simplifying at each stage.
4306 The function make_compound_operation is called to convert an expression
4307 consisting of shifts and ANDs into the equivalent compound expression.
4308 It is the inverse of this function, loosely speaking. */
4311 expand_compound_operation (x)
4319 switch (GET_CODE (x))
4324 /* We can't necessarily use a const_int for a multiword mode;
4325 it depends on implicitly extending the value.
4326 Since we don't know the right way to extend it,
4327 we can't tell whether the implicit way is right.
4329 Even for a mode that is no wider than a const_int,
4330 we can't win, because we need to sign extend one of its bits through
4331 the rest of it, and we don't know which bit. */
4332 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4335 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4338 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4339 /* If the inner object has VOIDmode (the only way this can happen
4340 is if it is a ASM_OPERANDS), we can't do anything since we don't
4341 know how much masking to do. */
4350 /* If the operand is a CLOBBER, just return it. */
4351 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4354 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4355 || GET_CODE (XEXP (x, 2)) != CONST_INT
4356 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4359 len = INTVAL (XEXP (x, 1));
4360 pos = INTVAL (XEXP (x, 2));
4362 /* If this goes outside the object being extracted, replace the object
4363 with a (use (mem ...)) construct that only combine understands
4364 and is used only for this purpose. */
4365 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4366 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4369 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4377 /* If we reach here, we want to return a pair of shifts. The inner
4378 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4379 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4380 logical depending on the value of UNSIGNEDP.
4382 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4383 converted into an AND of a shift.
4385 We must check for the case where the left shift would have a negative
4386 count. This can happen in a case like (x >> 31) & 255 on machines
4387 that can't shift by a constant. On those machines, we would first
4388 combine the shift with the AND to produce a variable-position
4389 extraction. Then the constant of 31 would be substituted in to produce
4390 a such a position. */
4392 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4393 if (modewidth >= pos - len)
4394 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4396 simplify_shift_const (NULL_RTX, ASHIFT,
4399 modewidth - pos - len),
4402 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4403 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4404 simplify_shift_const (NULL_RTX, LSHIFTRT,
4407 ((HOST_WIDE_INT) 1 << len) - 1);
4409 /* Any other cases we can't handle. */
4413 /* If we couldn't do this for some reason, return the original
4415 if (GET_CODE (tem) == CLOBBER)
4421 /* X is a SET which contains an assignment of one object into
4422 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4423 or certain SUBREGS). If possible, convert it into a series of
4426 We half-heartedly support variable positions, but do not at all
4427 support variable lengths. */
4430 expand_field_assignment (x)
4434 rtx pos; /* Always counts from low bit. */
4437 enum machine_mode compute_mode;
4439 /* Loop until we find something we can't simplify. */
4442 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4443 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4445 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4446 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4449 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4450 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4452 inner = XEXP (SET_DEST (x), 0);
4453 len = INTVAL (XEXP (SET_DEST (x), 1));
4454 pos = XEXP (SET_DEST (x), 2);
4456 /* If the position is constant and spans the width of INNER,
4457 surround INNER with a USE to indicate this. */
4458 if (GET_CODE (pos) == CONST_INT
4459 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4460 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4463 if (GET_CODE (pos) == CONST_INT)
4464 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4466 else if (GET_CODE (pos) == MINUS
4467 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4468 && (INTVAL (XEXP (pos, 1))
4469 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4470 /* If position is ADJUST - X, new position is X. */
4471 pos = XEXP (pos, 0);
4473 pos = gen_binary (MINUS, GET_MODE (pos),
4474 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4480 /* A SUBREG between two modes that occupy the same numbers of words
4481 can be done by moving the SUBREG to the source. */
4482 else if (GET_CODE (SET_DEST (x)) == SUBREG
4483 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4484 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4485 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4486 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4488 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4489 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4496 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4497 inner = SUBREG_REG (inner);
4499 compute_mode = GET_MODE (inner);
4501 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4502 if (len < HOST_BITS_PER_WIDE_INT)
4503 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4507 /* Now compute the equivalent expression. Make a copy of INNER
4508 for the SET_DEST in case it is a MEM into which we will substitute;
4509 we don't want shared RTL in that case. */
4510 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4511 gen_binary (IOR, compute_mode,
4512 gen_binary (AND, compute_mode,
4513 gen_unary (NOT, compute_mode,
4518 gen_binary (ASHIFT, compute_mode,
4519 gen_binary (AND, compute_mode,
4520 gen_lowpart_for_combine
4530 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
4531 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
4532 the starting bit position.
4534 INNER may be a USE. This will occur when we started with a bitfield
4535 that went outside the boundary of the object in memory, which is
4536 allowed on most machines. To isolate this case, we produce a USE
4537 whose mode is wide enough and surround the MEM with it. The only
4538 code that understands the USE is this routine. If it is not removed,
4539 it will cause the resulting insn not to match.
4541 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4544 IN_DEST is non-zero if this is a reference in the destination of a
4545 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4546 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4549 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4550 ZERO_EXTRACT should be built even for bits starting at bit 0.
4552 MODE is the desired mode of the result (if IN_DEST == 0). */
4555 make_extraction (mode, inner, pos, pos_rtx, len,
4556 unsignedp, in_dest, in_compare)
4557 enum machine_mode mode;
4563 int in_dest, in_compare;
4565 /* This mode describes the size of the storage area
4566 to fetch the overall value from. Within that, we
4567 ignore the POS lowest bits, etc. */
4568 enum machine_mode is_mode = GET_MODE (inner);
4569 enum machine_mode inner_mode;
4570 enum machine_mode wanted_mem_mode = byte_mode;
4571 enum machine_mode pos_mode = word_mode;
4572 enum machine_mode extraction_mode = word_mode;
4573 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4577 /* Get some information about INNER and get the innermost object. */
4578 if (GET_CODE (inner) == USE)
4579 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4580 /* We don't need to adjust the position because we set up the USE
4581 to pretend that it was a full-word object. */
4582 spans_byte = 1, inner = XEXP (inner, 0);
4583 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4585 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4586 consider just the QI as the memory to extract from.
4587 The subreg adds or removes high bits; its mode is
4588 irrelevant to the meaning of this extraction,
4589 since POS and LEN count from the lsb. */
4590 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4591 is_mode = GET_MODE (SUBREG_REG (inner));
4592 inner = SUBREG_REG (inner);
4595 inner_mode = GET_MODE (inner);
4597 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4598 pos = INTVAL (pos_rtx);
4600 /* See if this can be done without an extraction. We never can if the
4601 width of the field is not the same as that of some integer mode. For
4602 registers, we can only avoid the extraction if the position is at the
4603 low-order bit and this is either not in the destination or we have the
4604 appropriate STRICT_LOW_PART operation available.
4606 For MEM, we can avoid an extract if the field starts on an appropriate
4607 boundary and we can change the mode of the memory reference. However,
4608 we cannot directly access the MEM if we have a USE and the underlying
4609 MEM is not TMODE. This combination means that MEM was being used in a
4610 context where bits outside its mode were being referenced; that is only
4611 valid in bit-field insns. */
4613 if (tmode != BLKmode
4614 && ! (spans_byte && inner_mode != tmode)
4615 && ((pos == 0 && GET_CODE (inner) != MEM
4617 || (GET_CODE (inner) == REG
4618 && (movstrict_optab->handlers[(int) tmode].insn_code
4619 != CODE_FOR_nothing))))
4620 || (GET_CODE (inner) == MEM && pos >= 0
4622 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4623 : BITS_PER_UNIT)) == 0
4624 /* We can't do this if we are widening INNER_MODE (it
4625 may not be aligned, for one thing). */
4626 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4627 && (inner_mode == tmode
4628 || (! mode_dependent_address_p (XEXP (inner, 0))
4629 && ! MEM_VOLATILE_P (inner))))))
4631 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4632 field. If the original and current mode are the same, we need not
4633 adjust the offset. Otherwise, we do if bytes big endian.
4635 If INNER is not a MEM, get a piece consisting of the just the field
4636 of interest (in this case POS must be 0). */
4638 if (GET_CODE (inner) == MEM)
4641 /* POS counts from lsb, but make OFFSET count in memory order. */
4642 if (BYTES_BIG_ENDIAN)
4643 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
4645 offset = pos / BITS_PER_UNIT;
4647 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4648 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4649 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4650 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4652 else if (GET_CODE (inner) == REG)
4653 /* We can't call gen_lowpart_for_combine here since we always want
4654 a SUBREG and it would sometimes return a new hard register. */
4655 new = gen_rtx (SUBREG, tmode, inner,
4657 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
4658 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
4662 new = force_to_mode (inner, tmode, len, NULL_RTX);
4664 /* If this extraction is going into the destination of a SET,
4665 make a STRICT_LOW_PART unless we made a MEM. */
4668 return (GET_CODE (new) == MEM ? new
4669 : (GET_CODE (new) != SUBREG
4670 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4671 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4673 /* Otherwise, sign- or zero-extend unless we already are in the
4676 return (mode == tmode ? new
4677 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4681 /* Unless this is a COMPARE or we have a funny memory reference,
4682 don't do anything with zero-extending field extracts starting at
4683 the low-order bit since they are simple AND operations. */
4684 if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte && unsignedp)
4687 /* Get the mode to use should INNER be a MEM, the mode for the position,
4688 and the mode for the result. */
4692 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4693 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4694 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4699 if (! in_dest && unsignedp)
4701 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4702 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4703 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4708 if (! in_dest && ! unsignedp)
4710 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4711 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4712 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4716 /* Never narrow an object, since that might not be safe. */
4718 if (mode != VOIDmode
4719 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4720 extraction_mode = mode;
4722 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4723 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4724 pos_mode = GET_MODE (pos_rtx);
4726 /* If this is not from memory or we have to change the mode of memory and
4727 cannot, the desired mode is EXTRACTION_MODE. */
4728 if (GET_CODE (inner) != MEM
4729 || (inner_mode != wanted_mem_mode
4730 && (mode_dependent_address_p (XEXP (inner, 0))
4731 || MEM_VOLATILE_P (inner))))
4732 wanted_mem_mode = extraction_mode;
4735 /* If position is constant, compute new position. Otherwise, build
4738 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4742 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4743 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
4744 GET_MODE_BITSIZE (wanted_mem_mode))
4749 /* If INNER has a wider mode, make it smaller. If this is a constant
4750 extract, try to adjust the byte to point to the byte containing
4752 if (wanted_mem_mode != VOIDmode
4753 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4754 && ((GET_CODE (inner) == MEM
4755 && (inner_mode == wanted_mem_mode
4756 || (! mode_dependent_address_p (XEXP (inner, 0))
4757 && ! MEM_VOLATILE_P (inner))))))
4761 /* The computations below will be correct if the machine is big
4762 endian in both bits and bytes or little endian in bits and bytes.
4763 If it is mixed, we must adjust. */
4765 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4766 if (! spans_byte && is_mode != wanted_mem_mode)
4767 offset = (GET_MODE_SIZE (is_mode)
4768 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4771 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4772 adjust OFFSET to compensate. */
4773 #if BYTES_BIG_ENDIAN
4775 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4776 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4779 /* If this is a constant position, we can move to the desired byte. */
4782 offset += pos / BITS_PER_UNIT;
4783 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4786 if (offset != 0 || inner_mode != wanted_mem_mode)
4788 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4789 plus_constant (XEXP (inner, 0), offset));
4790 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4791 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4792 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4797 /* If INNER is not memory, we can always get it into the proper mode. */
4798 else if (GET_CODE (inner) != MEM)
4799 inner = force_to_mode (inner, extraction_mode,
4800 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
4804 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4805 have to zero extend. Otherwise, we can just use a SUBREG. */
4807 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4808 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4810 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4811 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4813 /* Make POS_RTX unless we already have it and it is correct. */
4814 if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4815 pos_rtx = GEN_INT (pos);
4817 /* Make the required operation. See if we can use existing rtx. */
4818 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4819 extraction_mode, inner, GEN_INT (len), pos_rtx);
4821 new = gen_lowpart_for_combine (mode, new);
4826 /* Look at the expression rooted at X. Look for expressions
4827 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4828 Form these expressions.
4830 Return the new rtx, usually just X.
4832 Also, for machines like the Vax that don't have logical shift insns,
4833 try to convert logical to arithmetic shift operations in cases where
4834 they are equivalent. This undoes the canonicalizations to logical
4835 shifts done elsewhere.
4837 We try, as much as possible, to re-use rtl expressions to save memory.
4839 IN_CODE says what kind of expression we are processing. Normally, it is
4840 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4841 being kludges), it is MEM. When processing the arguments of a comparison
4842 or a COMPARE against zero, it is COMPARE. */
4845 make_compound_operation (x, in_code)
4847 enum rtx_code in_code;
4849 enum rtx_code code = GET_CODE (x);
4850 enum machine_mode mode = GET_MODE (x);
4851 int mode_width = GET_MODE_BITSIZE (mode);
4852 enum rtx_code next_code;
4857 /* Select the code to be used in recursive calls. Once we are inside an
4858 address, we stay there. If we have a comparison, set to COMPARE,
4859 but once inside, go back to our default of SET. */
4861 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
4862 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4863 && XEXP (x, 1) == const0_rtx) ? COMPARE
4864 : in_code == COMPARE ? SET : in_code);
4866 /* Process depending on the code of this operation. If NEW is set
4867 non-zero, it will be returned. */
4873 /* Convert shifts by constants into multiplications if inside
4875 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4876 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
4877 && INTVAL (XEXP (x, 1)) >= 0)
4878 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4879 GEN_INT ((HOST_WIDE_INT) 1
4880 << INTVAL (XEXP (x, 1))));
4884 /* If the second operand is not a constant, we can't do anything
4886 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4889 /* If the constant is a power of two minus one and the first operand
4890 is a logical right shift, make an extraction. */
4891 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4892 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4893 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4894 XEXP (XEXP (x, 0), 1), i, 1,
4895 0, in_code == COMPARE);
4897 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4898 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4899 && subreg_lowpart_p (XEXP (x, 0))
4900 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4901 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4902 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4903 XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4904 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4905 0, in_code == COMPARE);
4908 /* If we are have (and (rotate X C) M) and C is larger than the number
4909 of bits in M, this is an extraction. */
4911 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4912 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4913 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4914 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4915 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4916 (GET_MODE_BITSIZE (mode)
4917 - INTVAL (XEXP (XEXP (x, 0), 1))),
4918 NULL_RTX, i, 1, 0, in_code == COMPARE);
4920 /* On machines without logical shifts, if the operand of the AND is
4921 a logical shift and our mask turns off all the propagated sign
4922 bits, we can replace the logical shift with an arithmetic shift. */
4923 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
4924 && (lshr_optab->handlers[(int) mode].insn_code
4925 == CODE_FOR_nothing)
4926 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4927 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4928 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4929 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
4930 && mode_width <= HOST_BITS_PER_WIDE_INT)
4932 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
4934 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4935 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4937 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4938 XEXP (XEXP (x, 0), 1)));
4941 /* If the constant is one less than a power of two, this might be
4942 representable by an extraction even if no shift is present.
4943 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4944 we are in a COMPARE. */
4945 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4946 new = make_extraction (mode, XEXP (x, 0), 0, NULL_RTX, i, 1,
4947 0, in_code == COMPARE);
4949 /* If we are in a comparison and this is an AND with a power of two,
4950 convert this into the appropriate bit extract. */
4951 else if (in_code == COMPARE
4952 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4953 new = make_extraction (mode, XEXP (x, 0), i, NULL_RTX, 1, 1, 0, 1);
4958 /* If the sign bit is known to be zero, replace this with an
4959 arithmetic shift. */
4960 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
4961 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
4962 && mode_width <= HOST_BITS_PER_WIDE_INT
4963 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
4965 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4969 /* ... fall through ... */
4972 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4973 this is a SIGN_EXTRACT. */
4974 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4975 && GET_CODE (XEXP (x, 0)) == ASHIFT
4976 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4977 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4978 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4979 (INTVAL (XEXP (x, 1))
4980 - INTVAL (XEXP (XEXP (x, 0), 1))),
4981 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
4982 code == LSHIFTRT, 0, in_code == COMPARE);
4984 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
4985 cases, we are better off returning a SIGN_EXTEND of the operation. */
4987 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4988 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
4989 || GET_CODE (XEXP (x, 0)) == XOR
4990 || GET_CODE (XEXP (x, 0)) == PLUS)
4991 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
4992 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4993 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4994 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
4995 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4996 && (INTVAL (XEXP (XEXP (x, 0), 1))
4997 & (((HOST_WIDE_INT) 1
4998 << INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))) - 1)) == 0)
5000 HOST_WIDE_INT newop1
5001 = (INTVAL (XEXP (XEXP (x, 0), 1))
5002 >> INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
5004 new = make_extraction (mode,
5005 gen_binary (GET_CODE (XEXP (x, 0)), mode,
5006 XEXP (XEXP (XEXP (x, 0), 0), 0),
5008 (INTVAL (XEXP (x, 1))
5009 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5010 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5011 code == LSHIFTRT, 0, in_code == COMPARE);
5014 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5015 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5016 && GET_CODE (XEXP (x, 0)) == NEG
5017 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5018 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5019 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5020 new = make_extraction (mode,
5021 gen_unary (GET_CODE (XEXP (x, 0)), mode,
5022 XEXP (XEXP (XEXP (x, 0), 0), 0)),
5023 (INTVAL (XEXP (x, 1))
5024 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5025 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5026 code == LSHIFTRT, 0, in_code == COMPARE);
5032 x = gen_lowpart_for_combine (mode, new);
5033 code = GET_CODE (x);
5036 /* Now recursively process each operand of this operation. */
5037 fmt = GET_RTX_FORMAT (code);
5038 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5041 new = make_compound_operation (XEXP (x, i), next_code);
5042 SUBST (XEXP (x, i), new);
5048 /* Given M see if it is a value that would select a field of bits
5049 within an item, but not the entire word. Return -1 if not.
5050 Otherwise, return the starting position of the field, where 0 is the
5053 *PLEN is set to the length of the field. */
5056 get_pos_from_mask (m, plen)
5057 unsigned HOST_WIDE_INT m;
5060 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5061 int pos = exact_log2 (m & - m);
5066 /* Now shift off the low-order zero bits and see if we have a power of
5068 *plen = exact_log2 ((m >> pos) + 1);
5076 /* Rewrite X so that it is an expression in MODE. We only care about the
5077 low-order BITS bits so we can ignore AND operations that just clear
5080 Also, if REG is non-zero and X is a register equal in value to REG,
5081 replace X with REG. */
5084 force_to_mode (x, mode, bits, reg)
5086 enum machine_mode mode;
5090 enum rtx_code code = GET_CODE (x);
5091 enum machine_mode op_mode = mode;
5093 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5094 just get X in the proper mode. */
5096 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5097 || bits > GET_MODE_BITSIZE (mode))
5098 return gen_lowpart_for_combine (mode, x);
5106 x = expand_compound_operation (x);
5107 if (GET_CODE (x) != code)
5108 return force_to_mode (x, mode, bits, reg);
5112 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5113 || rtx_equal_p (reg, get_last_value (x))))
5118 if (bits < HOST_BITS_PER_WIDE_INT)
5119 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5123 /* Ignore low-order SUBREGs. */
5124 if (subreg_lowpart_p (x))
5125 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5129 /* If this is an AND with a constant. Otherwise, we fall through to
5130 do the general binary case. */
5132 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5134 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5135 int len = exact_log2 (mask + 1);
5136 rtx op = XEXP (x, 0);
5138 /* If this is masking some low-order bits, we may be able to
5139 impose a stricter constraint on what bits of the operand are
5142 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5145 if (bits < HOST_BITS_PER_WIDE_INT)
5146 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5148 /* If we have no AND in MODE, use the original mode for the
5151 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5152 op_mode = GET_MODE (x);
5154 x = simplify_and_const_int (x, op_mode, op, mask);
5156 /* If X is still an AND, see if it is an AND with a mask that
5157 is just some low-order bits. If so, and it is BITS wide (it
5158 can't be wider), we don't need it. */
5160 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5161 && bits < HOST_BITS_PER_WIDE_INT
5162 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5168 /* ... fall through ... */
5175 /* For most binary operations, just propagate into the operation and
5176 change the mode if we have an operation of that mode. */
5179 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5181 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5182 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5183 == CODE_FOR_nothing))
5185 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5187 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5188 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5189 == CODE_FOR_nothing)))
5190 op_mode = GET_MODE (x);
5192 x = gen_binary (code, op_mode,
5193 gen_lowpart_for_combine (op_mode,
5194 force_to_mode (XEXP (x, 0),
5197 gen_lowpart_for_combine (op_mode,
5198 force_to_mode (XEXP (x, 1),
5205 /* For left shifts, do the same, but just for the first operand.
5206 If the shift count is a constant, we need even fewer bits of the
5209 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5210 bits -= INTVAL (XEXP (x, 1));
5213 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5214 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5215 == CODE_FOR_nothing)))
5216 op_mode = GET_MODE (x);
5218 x = gen_binary (code, op_mode,
5219 gen_lowpart_for_combine (op_mode,
5220 force_to_mode (XEXP (x, 0),
5227 /* Here we can only do something if the shift count is a constant and
5228 the count plus BITS is no larger than the width of MODE, we can do
5229 the shift in MODE. */
5231 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5232 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5234 rtx inner = force_to_mode (XEXP (x, 0), mode,
5235 bits + INTVAL (XEXP (x, 1)), reg);
5237 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5238 op_mode = GET_MODE (x);
5240 x = gen_binary (LSHIFTRT, op_mode,
5241 gen_lowpart_for_combine (op_mode, inner),
5247 /* If this is a sign-extension operation that just affects bits
5248 we don't care about, remove it. */
5250 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5251 && INTVAL (XEXP (x, 1)) >= 0
5252 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5253 && GET_CODE (XEXP (x, 0)) == ASHIFT
5254 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5255 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5256 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5262 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5263 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5264 == CODE_FOR_nothing)))
5265 op_mode = GET_MODE (x);
5267 /* Handle these similarly to the way we handle most binary operations. */
5268 x = gen_unary (code, op_mode,
5269 gen_lowpart_for_combine (op_mode,
5270 force_to_mode (XEXP (x, 0), mode,
5275 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5276 written in a narrower mode. We play it safe and do not do so. */
5279 gen_lowpart_for_combine (GET_MODE (x),
5280 force_to_mode (XEXP (x, 1), mode,
5283 gen_lowpart_for_combine (GET_MODE (x),
5284 force_to_mode (XEXP (x, 2), mode,
5289 /* Ensure we return a value of the proper mode. */
5290 return gen_lowpart_for_combine (mode, x);
5293 /* Return the value of expression X given the fact that condition COND
5294 is known to be true when applied to REG as its first operand and VAL
5295 as its second. X is known to not be shared and so can be modified in
5298 We only handle the simplest cases, and specifically those cases that
5299 arise with IF_THEN_ELSE expressions. */
5302 known_cond (x, cond, reg, val)
5307 enum rtx_code code = GET_CODE (x);
5312 if (side_effects_p (x))
5315 if (cond == EQ && rtx_equal_p (x, reg))
5318 /* If X is (abs REG) and we know something about REG's relationship
5319 with zero, we may be able to simplify this. */
5321 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5324 case GE: case GT: case EQ:
5327 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5330 /* The only other cases we handle are MIN, MAX, and comparisons if the
5331 operands are the same as REG and VAL. */
5333 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5335 if (rtx_equal_p (XEXP (x, 0), val))
5336 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5338 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5340 if (GET_RTX_CLASS (code) == '<')
5341 return (comparison_dominates_p (cond, code) ? const_true_rtx
5342 : (comparison_dominates_p (cond,
5343 reverse_condition (code))
5346 else if (code == SMAX || code == SMIN
5347 || code == UMIN || code == UMAX)
5349 int unsignedp = (code == UMIN || code == UMAX);
5351 if (code == SMAX || code == UMAX)
5352 cond = reverse_condition (cond);
5357 return unsignedp ? x : XEXP (x, 1);
5359 return unsignedp ? x : XEXP (x, 0);
5361 return unsignedp ? XEXP (x, 1) : x;
5363 return unsignedp ? XEXP (x, 0) : x;
5369 fmt = GET_RTX_FORMAT (code);
5370 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5373 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5374 else if (fmt[i] == 'E')
5375 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5376 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5383 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5384 Return that assignment if so.
5386 We only handle the most common cases. */
5389 make_field_assignment (x)
5392 rtx dest = SET_DEST (x);
5393 rtx src = SET_SRC (x);
5399 enum machine_mode mode;
5401 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5402 a clear of a one-bit field. We will have changed it to
5403 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5406 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5407 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5408 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5409 && (rtx_equal_p (dest, XEXP (src, 1))
5410 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5411 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5413 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5415 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5418 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5419 && subreg_lowpart_p (XEXP (src, 0))
5420 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5421 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5422 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5423 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5424 && (rtx_equal_p (dest, XEXP (src, 1))
5425 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5426 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5428 assign = make_extraction (VOIDmode, dest, -1,
5429 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5431 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5434 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5436 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5437 && XEXP (XEXP (src, 0), 0) == const1_rtx
5438 && (rtx_equal_p (dest, XEXP (src, 1))
5439 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5440 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5442 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
5444 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5447 /* The other case we handle is assignments into a constant-position
5448 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5449 a mask that has all one bits except for a group of zero bits and
5450 OTHER is known to have zeros where C1 has ones, this is such an
5451 assignment. Compute the position and length from C1. Shift OTHER
5452 to the appropriate position, force it to the required mode, and
5453 make the extraction. Check for the AND in both operands. */
5455 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5456 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5457 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5458 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5459 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5460 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5461 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5462 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5463 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5464 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5465 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5467 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5471 pos = get_pos_from_mask (~c1, &len);
5472 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5473 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
5474 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
5477 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5479 /* The mode to use for the source is the mode of the assignment, or of
5480 what is inside a possible STRICT_LOW_PART. */
5481 mode = (GET_CODE (assign) == STRICT_LOW_PART
5482 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5484 /* Shift OTHER right POS places and make it the source, restricting it
5485 to the proper length and mode. */
5487 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5488 GET_MODE (src), other, pos),
5491 return gen_rtx_combine (SET, VOIDmode, assign, src);
5494 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5498 apply_distributive_law (x)
5501 enum rtx_code code = GET_CODE (x);
5502 rtx lhs, rhs, other;
5504 enum rtx_code inner_code;
5506 /* The outer operation can only be one of the following: */
5507 if (code != IOR && code != AND && code != XOR
5508 && code != PLUS && code != MINUS)
5511 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5513 /* If either operand is a primitive we can't do anything, so get out fast. */
5514 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5515 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5518 lhs = expand_compound_operation (lhs);
5519 rhs = expand_compound_operation (rhs);
5520 inner_code = GET_CODE (lhs);
5521 if (inner_code != GET_CODE (rhs))
5524 /* See if the inner and outer operations distribute. */
5531 /* These all distribute except over PLUS. */
5532 if (code == PLUS || code == MINUS)
5537 if (code != PLUS && code != MINUS)
5543 /* These are also multiplies, so they distribute over everything. */
5547 /* Non-paradoxical SUBREGs distributes over all operations, provided
5548 the inner modes and word numbers are the same, this is an extraction
5549 of a low-order part, we don't convert an fp operation to int or
5550 vice versa, and we would not be converting a single-word
5551 operation into a multi-word operation. The latter test is not
5552 required, but it prevents generating unneeded multi-word operations.
5553 Some of the previous tests are redundant given the latter test, but
5554 are retained because they are required for correctness.
5556 We produce the result slightly differently in this case. */
5558 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5559 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5560 || ! subreg_lowpart_p (lhs)
5561 || (GET_MODE_CLASS (GET_MODE (lhs))
5562 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5563 || (GET_MODE_SIZE (GET_MODE (lhs))
5564 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5565 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5568 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5569 SUBREG_REG (lhs), SUBREG_REG (rhs));
5570 return gen_lowpart_for_combine (GET_MODE (x), tem);
5576 /* Set LHS and RHS to the inner operands (A and B in the example
5577 above) and set OTHER to the common operand (C in the example).
5578 These is only one way to do this unless the inner operation is
5580 if (GET_RTX_CLASS (inner_code) == 'c'
5581 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5582 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5583 else if (GET_RTX_CLASS (inner_code) == 'c'
5584 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5585 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5586 else if (GET_RTX_CLASS (inner_code) == 'c'
5587 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5588 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5589 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5590 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5594 /* Form the new inner operation, seeing if it simplifies first. */
5595 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5597 /* There is one exception to the general way of distributing:
5598 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5599 if (code == XOR && inner_code == IOR)
5602 other = gen_unary (NOT, GET_MODE (x), other);
5605 /* We may be able to continuing distributing the result, so call
5606 ourselves recursively on the inner operation before forming the
5607 outer operation, which we return. */
5608 return gen_binary (inner_code, GET_MODE (x),
5609 apply_distributive_law (tem), other);
5612 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5615 Return an equivalent form, if different from X. Otherwise, return X. If
5616 X is zero, we are to always construct the equivalent form. */
5619 simplify_and_const_int (x, mode, varop, constop)
5621 enum machine_mode mode;
5623 unsigned HOST_WIDE_INT constop;
5625 register enum machine_mode tmode;
5627 unsigned HOST_WIDE_INT nonzero;
5629 /* There is a large class of optimizations based on the principle that
5630 some operations produce results where certain bits are known to be zero,
5631 and hence are not significant to the AND. For example, if we have just
5632 done a left shift of one bit, the low-order bit is known to be zero and
5633 hence an AND with a mask of ~1 would not do anything.
5635 At the end of the following loop, we set:
5637 VAROP to be the item to be AND'ed with;
5638 CONSTOP to the constant value to AND it with. */
5642 /* If we ever encounter a mode wider than the host machine's widest
5643 integer size, we can't compute the masks accurately, so give up. */
5644 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
5647 /* Unless one of the cases below does a `continue',
5648 a `break' will be executed to exit the loop. */
5650 switch (GET_CODE (varop))
5653 /* If VAROP is a (clobber (const_int)), return it since we know
5654 we are generating something that won't match. */
5657 #if ! BITS_BIG_ENDIAN
5659 /* VAROP is a (use (mem ..)) that was made from a bit-field
5660 extraction that spanned the boundary of the MEM. If we are
5661 now masking so it is within that boundary, we don't need the
5663 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5665 varop = XEXP (varop, 0);
5672 if (subreg_lowpart_p (varop)
5673 /* We can ignore the effect this SUBREG if it narrows the mode
5674 or, on machines where byte operations extend, if the
5675 constant masks to zero all the bits the mode doesn't have. */
5676 && ((GET_MODE_SIZE (GET_MODE (varop))
5677 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
5678 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
5680 & GET_MODE_MASK (GET_MODE (varop))
5681 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5685 varop = SUBREG_REG (varop);
5694 /* Try to expand these into a series of shifts and then work
5695 with that result. If we can't, for example, if the extract
5696 isn't at a fixed position, give up. */
5697 temp = expand_compound_operation (varop);
5706 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5708 constop &= INTVAL (XEXP (varop, 1));
5709 varop = XEXP (varop, 0);
5716 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5717 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5718 operation which may be a bitfield extraction. */
5720 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5721 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5722 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5723 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
5724 && GET_CODE (XEXP (varop, 1)) == CONST_INT
5725 && (INTVAL (XEXP (varop, 1))
5726 & ~ nonzero_bits (XEXP (varop, 0), GET_MODE (varop)) == 0))
5728 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
5729 << INTVAL (XEXP (XEXP (varop, 0), 1)));
5730 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
5731 XEXP (XEXP (varop, 0), 0), temp);
5732 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5733 temp, XEXP (varop, 1));
5737 /* Apply the AND to both branches of the IOR or XOR, then try to
5738 apply the distributive law. This may eliminate operations
5739 if either branch can be simplified because of the AND.
5740 It may also make some cases more complex, but those cases
5741 probably won't match a pattern either with or without this. */
5743 gen_lowpart_for_combine
5744 (mode, apply_distributive_law
5746 (GET_CODE (varop), GET_MODE (varop),
5747 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5748 XEXP (varop, 0), constop),
5749 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5750 XEXP (varop, 1), constop))));
5753 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
5754 LSHIFTRT we can do the same as above. */
5756 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5757 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5758 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5759 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
5761 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
5762 temp = gen_binary (XOR, GET_MODE (varop),
5763 XEXP (XEXP (varop, 0), 0), temp);
5764 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5765 temp, XEXP (XEXP (varop, 0), 1));
5771 /* If we are just looking for the sign bit, we don't need this
5772 shift at all, even if it has a variable count. */
5773 if (constop == ((HOST_WIDE_INT) 1
5774 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
5776 varop = XEXP (varop, 0);
5780 /* If this is a shift by a constant, get a mask that contains
5781 those bits that are not copies of the sign bit. We then have
5782 two cases: If CONSTOP only includes those bits, this can be
5783 a logical shift, which may allow simplifications. If CONSTOP
5784 is a single-bit field not within those bits, we are requesting
5785 a copy of the sign bit and hence can shift the sign bit to
5786 the appropriate location. */
5787 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5788 && INTVAL (XEXP (varop, 1)) >= 0
5789 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
5793 nonzero = GET_MODE_MASK (GET_MODE (varop));
5794 nonzero >>= INTVAL (XEXP (varop, 1));
5796 if ((constop & ~ nonzero) == 0
5797 || (i = exact_log2 (constop)) >= 0)
5799 varop = simplify_shift_const
5800 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5801 i < 0 ? INTVAL (XEXP (varop, 1))
5802 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
5803 if (GET_CODE (varop) != ASHIFTRT)
5808 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
5809 even if the shift count isn't a constant. */
5811 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5812 XEXP (varop, 0), XEXP (varop, 1));
5816 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
5817 included in STORE_FLAG_VALUE and FOO has no bits that might be
5818 nonzero not in CONST. */
5819 if ((constop & ~ STORE_FLAG_VALUE) == 0
5820 && XEXP (varop, 0) == const0_rtx
5821 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5823 varop = XEXP (varop, 0);
5829 /* In (and (plus FOO C1) M), if M is a mask that just turns off
5830 low-order bits (as in an alignment operation) and FOO is already
5831 aligned to that boundary, we can convert remove this AND
5832 and possibly the PLUS if it is now adding zero. */
5833 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5834 && exact_log2 (-constop) >= 0
5835 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
5837 varop = plus_constant (XEXP (varop, 0),
5838 INTVAL (XEXP (varop, 1)) & constop);
5843 /* ... fall through ... */
5846 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
5847 less than powers of two and M2 is narrower than M1, we can
5848 eliminate the inner AND. This occurs when incrementing
5851 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
5852 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
5853 SUBST (XEXP (varop, 0),
5854 expand_compound_operation (XEXP (varop, 0)));
5856 if (GET_CODE (XEXP (varop, 0)) == AND
5857 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5858 && exact_log2 (constop + 1) >= 0
5859 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5860 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5861 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5868 /* If we have reached a constant, this whole thing is constant. */
5869 if (GET_CODE (varop) == CONST_INT)
5870 return GEN_INT (constop & INTVAL (varop));
5872 /* See what bits may be nonzero in VAROP. */
5873 nonzero = nonzero_bits (varop, mode);
5875 /* Turn off all bits in the constant that are known to already be zero.
5876 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
5877 which is tested below. */
5881 /* If we don't have any bits left, return zero. */
5885 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5886 if we already had one (just check for the simplest cases). */
5887 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5888 && GET_MODE (XEXP (x, 0)) == mode
5889 && SUBREG_REG (XEXP (x, 0)) == varop)
5890 varop = XEXP (x, 0);
5892 varop = gen_lowpart_for_combine (mode, varop);
5894 /* If we can't make the SUBREG, try to return what we were given. */
5895 if (GET_CODE (varop) == CLOBBER)
5896 return x ? x : varop;
5898 /* If we are only masking insignificant bits, return VAROP. */
5899 if (constop == nonzero)
5902 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5903 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5904 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
5908 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5909 || INTVAL (XEXP (x, 1)) != constop)
5910 SUBST (XEXP (x, 1), GEN_INT (constop));
5912 SUBST (XEXP (x, 0), varop);
5918 /* Given an expression, X, compute which bits in X can be non-zero.
5919 We don't care about bits outside of those defined in MODE.
5921 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5922 a shift, AND, or zero_extract, we can do better. */
5924 static unsigned HOST_WIDE_INT
5925 nonzero_bits (x, mode)
5927 enum machine_mode mode;
5929 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
5930 unsigned HOST_WIDE_INT inner_nz;
5932 int mode_width = GET_MODE_BITSIZE (mode);
5935 /* If X is wider than MODE, use its mode instead. */
5936 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5938 mode = GET_MODE (x);
5939 nonzero = GET_MODE_MASK (mode);
5940 mode_width = GET_MODE_BITSIZE (mode);
5943 if (mode_width > HOST_BITS_PER_WIDE_INT)
5944 /* Our only callers in this case look for single bit values. So
5945 just return the mode mask. Those tests will then be false. */
5948 code = GET_CODE (x);
5952 #ifdef STACK_BOUNDARY
5953 /* If this is the stack pointer, we may know something about its
5954 alignment. If PUSH_ROUNDING is defined, it is possible for the
5955 stack to be momentarily aligned only to that amount, so we pick
5956 the least alignment. */
5958 if (x == stack_pointer_rtx)
5960 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5962 #ifdef PUSH_ROUNDING
5963 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5966 return nonzero & ~ (sp_alignment - 1);
5970 /* If X is a register whose value we can find, use that value.
5971 Otherwise, use the previously-computed nonzero bits for this
5974 tem = get_last_value (x);
5976 return nonzero_bits (tem, mode);
5977 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
5978 return reg_nonzero_bits[REGNO (x)] & nonzero;
5985 #ifdef BYTE_LOADS_ZERO_EXTEND
5987 /* In many, if not most, RISC machines, reading a byte from memory
5988 zeros the rest of the register. Noticing that fact saves a lot
5989 of extra zero-extends. */
5990 nonzero &= GET_MODE_MASK (GET_MODE (x));
5994 #if STORE_FLAG_VALUE == 1
6001 if (GET_MODE_CLASS (mode) == MODE_INT)
6004 /* A comparison operation only sets the bits given by its mode. The
6005 rest are set undefined. */
6006 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6007 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6012 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6013 == GET_MODE_BITSIZE (GET_MODE (x)))
6016 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6017 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6021 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6022 == GET_MODE_BITSIZE (GET_MODE (x)))
6027 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6031 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6032 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6033 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6037 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6038 Otherwise, show all the bits in the outer mode but not the inner
6040 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6041 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6043 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6046 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6047 inner_nz |= (GET_MODE_MASK (mode)
6048 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6051 nonzero &= inner_nz;
6055 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6056 & nonzero_bits (XEXP (x, 1), mode));
6060 case UMIN: case UMAX: case SMIN: case SMAX:
6061 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6062 | nonzero_bits (XEXP (x, 1), mode));
6065 case PLUS: case MINUS:
6067 case DIV: case UDIV:
6068 case MOD: case UMOD:
6069 /* We can apply the rules of arithmetic to compute the number of
6070 high- and low-order zero bits of these operations. We start by
6071 computing the width (position of the highest-order non-zero bit)
6072 and the number of low-order zero bits for each value. */
6074 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6075 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6076 int width0 = floor_log2 (nz0) + 1;
6077 int width1 = floor_log2 (nz1) + 1;
6078 int low0 = floor_log2 (nz0 & -nz0);
6079 int low1 = floor_log2 (nz1 & -nz1);
6080 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6081 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6082 int result_width = mode_width;
6088 result_width = MAX (width0, width1) + 1;
6089 result_low = MIN (low0, low1);
6092 result_low = MIN (low0, low1);
6095 result_width = width0 + width1;
6096 result_low = low0 + low1;
6099 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6100 result_width = width0;
6103 result_width = width0;
6106 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6107 result_width = MIN (width0, width1);
6108 result_low = MIN (low0, low1);
6111 result_width = MIN (width0, width1);
6112 result_low = MIN (low0, low1);
6116 if (result_width < mode_width)
6117 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6120 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6125 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6126 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6127 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6131 /* If this is a SUBREG formed for a promoted variable that has
6132 been zero-extended, we know that at least the high-order bits
6133 are zero, though others might be too. */
6135 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6136 nonzero = (GET_MODE_MASK (GET_MODE (x))
6137 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6139 /* If the inner mode is a single word for both the host and target
6140 machines, we can compute this from which bits of the inner
6141 object might be nonzero. */
6142 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6143 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6144 <= HOST_BITS_PER_WIDE_INT))
6146 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6147 #if ! defined(BYTE_LOADS_ZERO_EXTEND) && ! defined(BYTE_LOADS_SIGN_EXTEND)
6148 /* On many CISC machines, accessing an object in a wider mode
6149 causes the high-order bits to become undefined. So they are
6150 not known to be zero. */
6151 if (GET_MODE_SIZE (GET_MODE (x))
6152 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6153 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6154 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6164 /* The nonzero bits are in two classes: any bits within MODE
6165 that aren't in GET_MODE (x) are always significant. The rest of the
6166 nonzero bits are those that are significant in the operand of
6167 the shift when shifted the appropriate number of bits. This
6168 shows that high-order bits are cleared by the right shift and
6169 low-order bits by left shifts. */
6170 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6171 && INTVAL (XEXP (x, 1)) >= 0
6172 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6174 enum machine_mode inner_mode = GET_MODE (x);
6175 int width = GET_MODE_BITSIZE (inner_mode);
6176 int count = INTVAL (XEXP (x, 1));
6177 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6178 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6179 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6180 unsigned HOST_WIDE_INT outer = 0;
6182 if (mode_width > width)
6183 outer = (op_nonzero & nonzero & ~ mode_mask);
6185 if (code == LSHIFTRT)
6187 else if (code == ASHIFTRT)
6191 /* If the sign bit may have been nonzero before the shift, we
6192 need to mark all the places it could have been copied to
6193 by the shift as possibly nonzero. */
6194 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6195 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6197 else if (code == LSHIFT || code == ASHIFT)
6200 inner = ((inner << (count % width)
6201 | (inner >> (width - (count % width)))) & mode_mask);
6203 nonzero &= (outer | inner);
6208 /* This is at most the number of bits in the mode. */
6209 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6213 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6214 | nonzero_bits (XEXP (x, 2), mode));
6221 /* Return the number of bits at the high-order end of X that are known to
6222 be equal to the sign bit. This number will always be between 1 and
6223 the number of bits in the mode of X. MODE is the mode to be used
6224 if X is VOIDmode. */
6227 num_sign_bit_copies (x, mode)
6229 enum machine_mode mode;
6231 enum rtx_code code = GET_CODE (x);
6233 int num0, num1, result;
6234 unsigned HOST_WIDE_INT nonzero;
6237 /* If we weren't given a mode, use the mode of X. If the mode is still
6238 VOIDmode, we don't know anything. */
6240 if (mode == VOIDmode)
6241 mode = GET_MODE (x);
6243 if (mode == VOIDmode)
6246 bitwidth = GET_MODE_BITSIZE (mode);
6251 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6252 return reg_sign_bit_copies[REGNO (x)];
6254 tem = get_last_value (x);
6256 return num_sign_bit_copies (tem, mode);
6259 #ifdef BYTE_LOADS_SIGN_EXTEND
6261 /* Some RISC machines sign-extend all loads of smaller than a word. */
6262 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6266 /* If the constant is negative, take its 1's complement and remask.
6267 Then see how many zero bits we have. */
6268 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
6269 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6270 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6271 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
6273 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
6276 /* If this is a SUBREG for a promoted object that is sign-extended
6277 and we are looking at it in a wider mode, we know that at least the
6278 high-order bits are known to be sign bit copies. */
6280 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6281 return (GET_MODE_BITSIZE (mode) - GET_MODE_BITSIZE (GET_MODE (x))
6282 + num_sign_bit_copies (SUBREG_REG (x), GET_MODE (x)));
6284 /* For a smaller object, just ignore the high bits. */
6285 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6287 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6288 return MAX (1, (num0
6289 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6293 #if defined(BYTE_LOADS_ZERO_EXTEND) || defined(BYTE_LOADS_SIGN_EXTEND)
6294 /* For paradoxical SUBREGs, just look inside since, on machines with
6295 one of these defined, we assume that operations are actually
6296 performed on the full register. Note that we are passing MODE
6297 to the recursive call, so the number of sign bit copies will
6298 remain relative to that mode, not the inner mode. */
6300 if (GET_MODE_SIZE (GET_MODE (x))
6301 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6302 return num_sign_bit_copies (SUBREG_REG (x), mode);
6308 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6309 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6313 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6314 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6317 /* For a smaller object, just ignore the high bits. */
6318 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6319 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6323 return num_sign_bit_copies (XEXP (x, 0), mode);
6325 case ROTATE: case ROTATERT:
6326 /* If we are rotating left by a number of bits less than the number
6327 of sign bit copies, we can just subtract that amount from the
6329 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6330 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6332 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6333 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6334 : bitwidth - INTVAL (XEXP (x, 1))));
6339 /* In general, this subtracts one sign bit copy. But if the value
6340 is known to be positive, the number of sign bit copies is the
6341 same as that of the input. Finally, if the input has just one bit
6342 that might be nonzero, all the bits are copies of the sign bit. */
6343 nonzero = nonzero_bits (XEXP (x, 0), mode);
6347 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6349 && bitwidth <= HOST_BITS_PER_WIDE_INT
6350 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
6355 case IOR: case AND: case XOR:
6356 case SMIN: case SMAX: case UMIN: case UMAX:
6357 /* Logical operations will preserve the number of sign-bit copies.
6358 MIN and MAX operations always return one of the operands. */
6359 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6360 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6361 return MIN (num0, num1);
6363 case PLUS: case MINUS:
6364 /* For addition and subtraction, we can have a 1-bit carry. However,
6365 if we are subtracting 1 from a positive number, there will not
6366 be such a carry. Furthermore, if the positive number is known to
6367 be 0 or 1, we know the result is either -1 or 0. */
6369 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6370 && bitwidth <= HOST_BITS_PER_INT)
6372 nonzero = nonzero_bits (XEXP (x, 0), mode);
6373 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
6374 return (nonzero == 1 || nonzero == 0 ? bitwidth
6375 : bitwidth - floor_log2 (nonzero) - 1);
6378 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6379 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6380 return MAX (1, MIN (num0, num1) - 1);
6383 /* The number of bits of the product is the sum of the number of
6384 bits of both terms. However, unless one of the terms if known
6385 to be positive, we must allow for an additional bit since negating
6386 a negative number can remove one sign bit copy. */
6388 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6389 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6391 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6393 && bitwidth <= HOST_BITS_PER_INT
6394 && ((nonzero_bits (XEXP (x, 0), mode)
6395 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6396 && (nonzero_bits (XEXP (x, 1), mode)
6397 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6400 return MAX (1, result);
6403 /* The result must be <= the first operand. */
6404 return num_sign_bit_copies (XEXP (x, 0), mode);
6407 /* The result must be <= the scond operand. */
6408 return num_sign_bit_copies (XEXP (x, 1), mode);
6411 /* Similar to unsigned division, except that we have to worry about
6412 the case where the divisor is negative, in which case we have
6414 result = num_sign_bit_copies (XEXP (x, 0), mode);
6416 && bitwidth <= HOST_BITS_PER_WIDE_INT
6417 && (nonzero_bits (XEXP (x, 1), mode)
6418 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6424 result = num_sign_bit_copies (XEXP (x, 1), mode);
6426 && bitwidth <= HOST_BITS_PER_WIDE_INT
6427 && (nonzero_bits (XEXP (x, 1), mode)
6428 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6434 /* Shifts by a constant add to the number of bits equal to the
6436 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6437 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6438 && INTVAL (XEXP (x, 1)) > 0)
6439 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6445 /* Left shifts destroy copies. */
6446 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6447 || INTVAL (XEXP (x, 1)) < 0
6448 || INTVAL (XEXP (x, 1)) >= bitwidth)
6451 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6452 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6455 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6456 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6457 return MIN (num0, num1);
6459 #if STORE_FLAG_VALUE == -1
6460 case EQ: case NE: case GE: case GT: case LE: case LT:
6461 case GEU: case GTU: case LEU: case LTU:
6466 /* If we haven't been able to figure it out by one of the above rules,
6467 see if some of the high-order bits are known to be zero. If so,
6468 count those bits and return one less than that amount. If we can't
6469 safely compute the mask for this mode, always return BITWIDTH. */
6471 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6474 nonzero = nonzero_bits (x, mode);
6475 return (nonzero == GET_MODE_MASK (mode)
6476 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
6479 /* Return the number of "extended" bits there are in X, when interpreted
6480 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6481 unsigned quantities, this is the number of high-order zero bits.
6482 For signed quantities, this is the number of copies of the sign bit
6483 minus 1. In both case, this function returns the number of "spare"
6484 bits. For example, if two quantities for which this function returns
6485 at least 1 are added, the addition is known not to overflow.
6487 This function will always return 0 unless called during combine, which
6488 implies that it must be called from a define_split. */
6491 extended_count (x, mode, unsignedp)
6493 enum machine_mode mode;
6496 if (nonzero_sign_valid == 0)
6500 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6501 && (GET_MODE_BITSIZE (mode) - 1
6502 - floor_log2 (nonzero_bits (x, mode))))
6503 : num_sign_bit_copies (x, mode) - 1);
6506 /* This function is called from `simplify_shift_const' to merge two
6507 outer operations. Specifically, we have already found that we need
6508 to perform operation *POP0 with constant *PCONST0 at the outermost
6509 position. We would now like to also perform OP1 with constant CONST1
6510 (with *POP0 being done last).
6512 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6513 the resulting operation. *PCOMP_P is set to 1 if we would need to
6514 complement the innermost operand, otherwise it is unchanged.
6516 MODE is the mode in which the operation will be done. No bits outside
6517 the width of this mode matter. It is assumed that the width of this mode
6518 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
6520 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6521 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6522 result is simply *PCONST0.
6524 If the resulting operation cannot be expressed as one operation, we
6525 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6528 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6529 enum rtx_code *pop0;
6530 HOST_WIDE_INT *pconst0;
6532 HOST_WIDE_INT const1;
6533 enum machine_mode mode;
6536 enum rtx_code op0 = *pop0;
6537 HOST_WIDE_INT const0 = *pconst0;
6539 const0 &= GET_MODE_MASK (mode);
6540 const1 &= GET_MODE_MASK (mode);
6542 /* If OP0 is an AND, clear unimportant bits in CONST1. */
6546 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6549 if (op1 == NIL || op0 == SET)
6552 else if (op0 == NIL)
6553 op0 = op1, const0 = const1;
6555 else if (op0 == op1)
6577 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6578 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6581 /* If the two constants aren't the same, we can't do anything. The
6582 remaining six cases can all be done. */
6583 else if (const0 != const1)
6591 /* (a & b) | b == b */
6593 else /* op1 == XOR */
6594 /* (a ^ b) | b == a | b */
6600 /* (a & b) ^ b == (~a) & b */
6601 op0 = AND, *pcomp_p = 1;
6602 else /* op1 == IOR */
6603 /* (a | b) ^ b == a & ~b */
6604 op0 = AND, *pconst0 = ~ const0;
6609 /* (a | b) & b == b */
6611 else /* op1 == XOR */
6612 /* (a ^ b) & b) == (~a) & b */
6617 /* Check for NO-OP cases. */
6618 const0 &= GET_MODE_MASK (mode);
6620 && (op0 == IOR || op0 == XOR || op0 == PLUS))
6622 else if (const0 == 0 && op0 == AND)
6624 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6633 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6634 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6635 that we started with.
6637 The shift is normally computed in the widest mode we find in VAROP, as
6638 long as it isn't a different number of words than RESULT_MODE. Exceptions
6639 are ASHIFTRT and ROTATE, which are always done in their original mode, */
6642 simplify_shift_const (x, code, result_mode, varop, count)
6645 enum machine_mode result_mode;
6649 enum rtx_code orig_code = code;
6650 int orig_count = count;
6651 enum machine_mode mode = result_mode;
6652 enum machine_mode shift_mode, tmode;
6654 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
6655 /* We form (outer_op (code varop count) (outer_const)). */
6656 enum rtx_code outer_op = NIL;
6657 HOST_WIDE_INT outer_const;
6659 int complement_p = 0;
6662 /* If we were given an invalid count, don't do anything except exactly
6663 what was requested. */
6665 if (count < 0 || count > GET_MODE_BITSIZE (mode))
6670 return gen_rtx (code, mode, varop, GEN_INT (count));
6673 /* Unless one of the branches of the `if' in this loop does a `continue',
6674 we will `break' the loop after the `if'. */
6678 /* If we have an operand of (clobber (const_int 0)), just return that
6680 if (GET_CODE (varop) == CLOBBER)
6683 /* If we discovered we had to complement VAROP, leave. Making a NOT
6684 here would cause an infinite loop. */
6688 /* Convert ROTATETRT to ROTATE. */
6689 if (code == ROTATERT)
6690 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
6692 /* Canonicalize LSHIFT to ASHIFT. */
6696 /* We need to determine what mode we will do the shift in. If the
6697 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
6698 was originally done in. Otherwise, we can do it in MODE, the widest
6699 mode encountered. */
6700 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6702 /* Handle cases where the count is greater than the size of the mode
6703 minus 1. For ASHIFT, use the size minus one as the count (this can
6704 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
6705 take the count modulo the size. For other shifts, the result is
6708 Since these shifts are being produced by the compiler by combining
6709 multiple operations, each of which are defined, we know what the
6710 result is supposed to be. */
6712 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
6714 if (code == ASHIFTRT)
6715 count = GET_MODE_BITSIZE (shift_mode) - 1;
6716 else if (code == ROTATE || code == ROTATERT)
6717 count %= GET_MODE_BITSIZE (shift_mode);
6720 /* We can't simply return zero because there may be an
6728 /* Negative counts are invalid and should not have been made (a
6729 programmer-specified negative count should have been handled
6734 /* An arithmetic right shift of a quantity known to be -1 or 0
6736 if (code == ASHIFTRT
6737 && (num_sign_bit_copies (varop, shift_mode)
6738 == GET_MODE_BITSIZE (shift_mode)))
6744 /* We simplify the tests below and elsewhere by converting
6745 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
6746 `make_compound_operation' will convert it to a ASHIFTRT for
6747 those machines (such as Vax) that don't have a LSHIFTRT. */
6748 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
6750 && ((nonzero_bits (varop, shift_mode)
6751 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
6755 switch (GET_CODE (varop))
6761 new = expand_compound_operation (varop);
6770 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
6771 minus the width of a smaller mode, we can do this with a
6772 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
6773 if ((code == ASHIFTRT || code == LSHIFTRT)
6774 && ! mode_dependent_address_p (XEXP (varop, 0))
6775 && ! MEM_VOLATILE_P (varop)
6776 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6777 MODE_INT, 1)) != BLKmode)
6779 #if BYTES_BIG_ENDIAN
6780 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
6782 new = gen_rtx (MEM, tmode,
6783 plus_constant (XEXP (varop, 0),
6784 count / BITS_PER_UNIT));
6785 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
6786 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
6787 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
6789 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6790 : ZERO_EXTEND, mode, new);
6797 /* Similar to the case above, except that we can only do this if
6798 the resulting mode is the same as that of the underlying
6799 MEM and adjust the address depending on the *bits* endianness
6800 because of the way that bit-field extract insns are defined. */
6801 if ((code == ASHIFTRT || code == LSHIFTRT)
6802 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
6803 MODE_INT, 1)) != BLKmode
6804 && tmode == GET_MODE (XEXP (varop, 0)))
6807 new = XEXP (varop, 0);
6809 new = copy_rtx (XEXP (varop, 0));
6810 SUBST (XEXP (new, 0),
6811 plus_constant (XEXP (new, 0),
6812 count / BITS_PER_UNIT));
6815 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
6816 : ZERO_EXTEND, mode, new);
6823 /* If VAROP is a SUBREG, strip it as long as the inner operand has
6824 the same number of words as what we've seen so far. Then store
6825 the widest mode in MODE. */
6826 if (subreg_lowpart_p (varop)
6827 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6828 > GET_MODE_SIZE (GET_MODE (varop)))
6829 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
6830 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6833 varop = SUBREG_REG (varop);
6834 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
6835 mode = GET_MODE (varop);
6841 /* Some machines use MULT instead of ASHIFT because MULT
6842 is cheaper. But it is still better on those machines to
6843 merge two shifts into one. */
6844 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6845 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6847 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
6848 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
6854 /* Similar, for when divides are cheaper. */
6855 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6856 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
6858 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6859 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
6865 /* If we are extracting just the sign bit of an arithmetic right
6866 shift, that shift is not needed. */
6867 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
6869 varop = XEXP (varop, 0);
6873 /* ... fall through ... */
6879 /* Here we have two nested shifts. The result is usually the
6880 AND of a new shift with a mask. We compute the result below. */
6881 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6882 && INTVAL (XEXP (varop, 1)) >= 0
6883 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
6884 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
6885 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6887 enum rtx_code first_code = GET_CODE (varop);
6888 int first_count = INTVAL (XEXP (varop, 1));
6889 unsigned HOST_WIDE_INT mask;
6893 if (first_code == LSHIFT)
6894 first_code = ASHIFT;
6896 /* We have one common special case. We can't do any merging if
6897 the inner code is an ASHIFTRT of a smaller mode. However, if
6898 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
6899 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
6900 we can convert it to
6901 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
6902 This simplifies certain SIGN_EXTEND operations. */
6903 if (code == ASHIFT && first_code == ASHIFTRT
6904 && (GET_MODE_BITSIZE (result_mode)
6905 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
6907 /* C3 has the low-order C1 bits zero. */
6909 mask = (GET_MODE_MASK (mode)
6910 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
6912 varop = simplify_and_const_int (NULL_RTX, result_mode,
6913 XEXP (varop, 0), mask);
6914 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
6916 count = first_count;
6921 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
6922 than C1 high-order bits equal to the sign bit, we can convert
6923 this to either an ASHIFT or a ASHIFTRT depending on the
6926 We cannot do this if VAROP's mode is not SHIFT_MODE. */
6928 if (code == ASHIFTRT && first_code == ASHIFT
6929 && GET_MODE (varop) == shift_mode
6930 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
6933 count -= first_count;
6935 count = - count, code = ASHIFT;
6936 varop = XEXP (varop, 0);
6940 /* There are some cases we can't do. If CODE is ASHIFTRT,
6941 we can only do this if FIRST_CODE is also ASHIFTRT.
6943 We can't do the case when CODE is ROTATE and FIRST_CODE is
6946 If the mode of this shift is not the mode of the outer shift,
6947 we can't do this if either shift is ASHIFTRT or ROTATE.
6949 Finally, we can't do any of these if the mode is too wide
6950 unless the codes are the same.
6952 Handle the case where the shift codes are the same
6955 if (code == first_code)
6957 if (GET_MODE (varop) != result_mode
6958 && (code == ASHIFTRT || code == ROTATE))
6961 count += first_count;
6962 varop = XEXP (varop, 0);
6966 if (code == ASHIFTRT
6967 || (code == ROTATE && first_code == ASHIFTRT)
6968 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
6969 || (GET_MODE (varop) != result_mode
6970 && (first_code == ASHIFTRT || first_code == ROTATE
6971 || code == ROTATE)))
6974 /* To compute the mask to apply after the shift, shift the
6975 nonzero bits of the inner shift the same way the
6976 outer shift will. */
6978 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
6981 = simplify_binary_operation (code, result_mode, mask_rtx,
6984 /* Give up if we can't compute an outer operation to use. */
6986 || GET_CODE (mask_rtx) != CONST_INT
6987 || ! merge_outer_ops (&outer_op, &outer_const, AND,
6989 result_mode, &complement_p))
6992 /* If the shifts are in the same direction, we add the
6993 counts. Otherwise, we subtract them. */
6994 if ((code == ASHIFTRT || code == LSHIFTRT)
6995 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
6996 count += first_count;
6998 count -= first_count;
7000 /* If COUNT is positive, the new shift is usually CODE,
7001 except for the two exceptions below, in which case it is
7002 FIRST_CODE. If the count is negative, FIRST_CODE should
7005 && ((first_code == ROTATE && code == ASHIFT)
7006 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7009 code = first_code, count = - count;
7011 varop = XEXP (varop, 0);
7015 /* If we have (A << B << C) for any shift, we can convert this to
7016 (A << C << B). This wins if A is a constant. Only try this if
7017 B is not a constant. */
7019 else if (GET_CODE (varop) == code
7020 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7022 = simplify_binary_operation (code, mode,
7026 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7033 /* Make this fit the case below. */
7034 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7035 GEN_INT (GET_MODE_MASK (mode)));
7041 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7042 with C the size of VAROP - 1 and the shift is logical if
7043 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7044 we have an (le X 0) operation. If we have an arithmetic shift
7045 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7046 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7048 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7049 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7050 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7051 && (code == LSHIFTRT || code == ASHIFTRT)
7052 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7053 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7056 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7059 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7060 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7065 /* If we have (shift (logical)), move the logical to the outside
7066 to allow it to possibly combine with another logical and the
7067 shift to combine with another shift. This also canonicalizes to
7068 what a ZERO_EXTRACT looks like. Also, some machines have
7069 (and (shift)) insns. */
7071 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7072 && (new = simplify_binary_operation (code, result_mode,
7074 GEN_INT (count))) != 0
7075 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7076 INTVAL (new), result_mode, &complement_p))
7078 varop = XEXP (varop, 0);
7082 /* If we can't do that, try to simplify the shift in each arm of the
7083 logical expression, make a new logical expression, and apply
7084 the inverse distributive law. */
7086 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7087 XEXP (varop, 0), count);
7088 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7089 XEXP (varop, 1), count);
7091 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7092 varop = apply_distributive_law (varop);
7099 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7100 says that the sign bit can be tested, FOO has mode MODE, C is
7101 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7104 && XEXP (varop, 1) == const0_rtx
7105 && GET_MODE (XEXP (varop, 0)) == result_mode
7106 && count == GET_MODE_BITSIZE (result_mode) - 1
7107 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7108 && ((STORE_FLAG_VALUE
7109 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7110 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7111 && merge_outer_ops (&outer_op, &outer_const, XOR,
7112 (HOST_WIDE_INT) 1, result_mode,
7115 varop = XEXP (varop, 0);
7122 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7123 than the number of bits in the mode is equivalent to A. */
7124 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7125 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7127 varop = XEXP (varop, 0);
7132 /* NEG commutes with ASHIFT since it is multiplication. Move the
7133 NEG outside to allow shifts to combine. */
7135 && merge_outer_ops (&outer_op, &outer_const, NEG,
7136 (HOST_WIDE_INT) 0, result_mode,
7139 varop = XEXP (varop, 0);
7145 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7146 is one less than the number of bits in the mode is
7147 equivalent to (xor A 1). */
7148 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7149 && XEXP (varop, 1) == constm1_rtx
7150 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7151 && merge_outer_ops (&outer_op, &outer_const, XOR,
7152 (HOST_WIDE_INT) 1, result_mode,
7156 varop = XEXP (varop, 0);
7160 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7161 that might be nonzero in BAR are those being shifted out and those
7162 bits are known zero in FOO, we can replace the PLUS with FOO.
7163 Similarly in the other operand order. This code occurs when
7164 we are computing the size of a variable-size array. */
7166 if ((code == ASHIFTRT || code == LSHIFTRT)
7167 && count < HOST_BITS_PER_WIDE_INT
7168 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7169 && (nonzero_bits (XEXP (varop, 1), result_mode)
7170 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7172 varop = XEXP (varop, 0);
7175 else if ((code == ASHIFTRT || code == LSHIFTRT)
7176 && count < HOST_BITS_PER_WIDE_INT
7177 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7178 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7180 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7181 & nonzero_bits (XEXP (varop, 1),
7184 varop = XEXP (varop, 1);
7188 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7190 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7191 && (new = simplify_binary_operation (ASHIFT, result_mode,
7193 GEN_INT (count))) != 0
7194 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7195 INTVAL (new), result_mode, &complement_p))
7197 varop = XEXP (varop, 0);
7203 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7204 with C the size of VAROP - 1 and the shift is logical if
7205 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7206 we have a (gt X 0) operation. If the shift is arithmetic with
7207 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7208 we have a (neg (gt X 0)) operation. */
7210 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7211 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7212 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7213 && (code == LSHIFTRT || code == ASHIFTRT)
7214 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7215 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7216 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7219 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7222 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7223 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7233 /* We need to determine what mode to do the shift in. If the shift is
7234 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7235 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7236 The code we care about is that of the shift that will actually be done,
7237 not the shift that was originally requested. */
7238 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7240 /* We have now finished analyzing the shift. The result should be
7241 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7242 OUTER_OP is non-NIL, it is an operation that needs to be applied
7243 to the result of the shift. OUTER_CONST is the relevant constant,
7244 but we must turn off all bits turned off in the shift.
7246 If we were passed a value for X, see if we can use any pieces of
7247 it. If not, make new rtx. */
7249 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7250 && GET_CODE (XEXP (x, 1)) == CONST_INT
7251 && INTVAL (XEXP (x, 1)) == count)
7252 const_rtx = XEXP (x, 1);
7254 const_rtx = GEN_INT (count);
7256 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7257 && GET_MODE (XEXP (x, 0)) == shift_mode
7258 && SUBREG_REG (XEXP (x, 0)) == varop)
7259 varop = XEXP (x, 0);
7260 else if (GET_MODE (varop) != shift_mode)
7261 varop = gen_lowpart_for_combine (shift_mode, varop);
7263 /* If we can't make the SUBREG, try to return what we were given. */
7264 if (GET_CODE (varop) == CLOBBER)
7265 return x ? x : varop;
7267 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7272 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7273 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7275 SUBST (XEXP (x, 0), varop);
7276 SUBST (XEXP (x, 1), const_rtx);
7279 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7280 turn off all the bits that the shift would have turned off. */
7281 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7282 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7283 GET_MODE_MASK (result_mode) >> orig_count);
7285 /* Do the remainder of the processing in RESULT_MODE. */
7286 x = gen_lowpart_for_combine (result_mode, x);
7288 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7291 x = gen_unary (NOT, result_mode, x);
7293 if (outer_op != NIL)
7295 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7296 outer_const &= GET_MODE_MASK (result_mode);
7298 if (outer_op == AND)
7299 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7300 else if (outer_op == SET)
7301 /* This means that we have determined that the result is
7302 equivalent to a constant. This should be rare. */
7303 x = GEN_INT (outer_const);
7304 else if (GET_RTX_CLASS (outer_op) == '1')
7305 x = gen_unary (outer_op, result_mode, x);
7307 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7313 /* Like recog, but we receive the address of a pointer to a new pattern.
7314 We try to match the rtx that the pointer points to.
7315 If that fails, we may try to modify or replace the pattern,
7316 storing the replacement into the same pointer object.
7318 Modifications include deletion or addition of CLOBBERs.
7320 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7321 the CLOBBERs are placed.
7323 The value is the final insn code from the pattern ultimately matched,
7327 recog_for_combine (pnewpat, insn, pnotes)
7332 register rtx pat = *pnewpat;
7333 int insn_code_number;
7334 int num_clobbers_to_add = 0;
7338 /* Is the result of combination a valid instruction? */
7339 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7341 /* If it isn't, there is the possibility that we previously had an insn
7342 that clobbered some register as a side effect, but the combined
7343 insn doesn't need to do that. So try once more without the clobbers
7344 unless this represents an ASM insn. */
7346 if (insn_code_number < 0 && ! check_asm_operands (pat)
7347 && GET_CODE (pat) == PARALLEL)
7351 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7352 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7355 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7359 SUBST_INT (XVECLEN (pat, 0), pos);
7362 pat = XVECEXP (pat, 0, 0);
7364 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7367 /* If we had any clobbers to add, make a new pattern than contains
7368 them. Then check to make sure that all of them are dead. */
7369 if (num_clobbers_to_add)
7371 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7372 gen_rtvec (GET_CODE (pat) == PARALLEL
7373 ? XVECLEN (pat, 0) + num_clobbers_to_add
7374 : num_clobbers_to_add + 1));
7376 if (GET_CODE (pat) == PARALLEL)
7377 for (i = 0; i < XVECLEN (pat, 0); i++)
7378 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7380 XVECEXP (newpat, 0, 0) = pat;
7382 add_clobbers (newpat, insn_code_number);
7384 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7385 i < XVECLEN (newpat, 0); i++)
7387 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7388 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7390 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7391 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7399 return insn_code_number;
7402 /* Like gen_lowpart but for use by combine. In combine it is not possible
7403 to create any new pseudoregs. However, it is safe to create
7404 invalid memory addresses, because combine will try to recognize
7405 them and all they will do is make the combine attempt fail.
7407 If for some reason this cannot do its job, an rtx
7408 (clobber (const_int 0)) is returned.
7409 An insn containing that will not be recognized. */
7414 gen_lowpart_for_combine (mode, x)
7415 enum machine_mode mode;
7420 if (GET_MODE (x) == mode)
7423 /* We can only support MODE being wider than a word if X is a
7424 constant integer or has a mode the same size. */
7426 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7427 && ! ((GET_MODE (x) == VOIDmode
7428 && (GET_CODE (x) == CONST_INT
7429 || GET_CODE (x) == CONST_DOUBLE))
7430 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
7431 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7433 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7434 won't know what to do. So we will strip off the SUBREG here and
7435 process normally. */
7436 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7439 if (GET_MODE (x) == mode)
7443 result = gen_lowpart_common (mode, x);
7447 if (GET_CODE (x) == MEM)
7449 register int offset = 0;
7452 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7454 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7455 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7457 /* If we want to refer to something bigger than the original memref,
7458 generate a perverse subreg instead. That will force a reload
7459 of the original memref X. */
7460 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7461 return gen_rtx (SUBREG, mode, x, 0);
7463 #if WORDS_BIG_ENDIAN
7464 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7465 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7467 #if BYTES_BIG_ENDIAN
7468 /* Adjust the address so that the address-after-the-data
7470 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7471 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7473 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7474 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7475 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7476 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7480 /* If X is a comparison operator, rewrite it in a new mode. This
7481 probably won't match, but may allow further simplifications. */
7482 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7483 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7485 /* If we couldn't simplify X any other way, just enclose it in a
7486 SUBREG. Normally, this SUBREG won't match, but some patterns may
7487 include an explicit SUBREG or we may simplify it further in combine. */
7492 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7493 word = ((GET_MODE_SIZE (GET_MODE (x))
7494 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7496 return gen_rtx (SUBREG, mode, x, word);
7500 /* Make an rtx expression. This is a subset of gen_rtx and only supports
7501 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7503 If the identical expression was previously in the insn (in the undobuf),
7504 it will be returned. Only if it is not found will a new expression
7509 gen_rtx_combine (va_alist)
7514 enum machine_mode mode;
7522 code = va_arg (p, enum rtx_code);
7523 mode = va_arg (p, enum machine_mode);
7524 n_args = GET_RTX_LENGTH (code);
7525 fmt = GET_RTX_FORMAT (code);
7527 if (n_args == 0 || n_args > 3)
7530 /* Get each arg and verify that it is supposed to be an expression. */
7531 for (j = 0; j < n_args; j++)
7536 args[j] = va_arg (p, rtx);
7539 /* See if this is in undobuf. Be sure we don't use objects that came
7540 from another insn; this could produce circular rtl structures. */
7542 for (i = previous_num_undos; i < undobuf.num_undo; i++)
7543 if (!undobuf.undo[i].is_int
7544 && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
7545 && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
7547 for (j = 0; j < n_args; j++)
7548 if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
7552 return undobuf.undo[i].old_contents.rtx;
7555 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7556 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7557 rt = rtx_alloc (code);
7558 PUT_MODE (rt, mode);
7559 XEXP (rt, 0) = args[0];
7562 XEXP (rt, 1) = args[1];
7564 XEXP (rt, 2) = args[2];
7569 /* These routines make binary and unary operations by first seeing if they
7570 fold; if not, a new expression is allocated. */
7573 gen_binary (code, mode, op0, op1)
7575 enum machine_mode mode;
7581 if (GET_RTX_CLASS (code) == 'c'
7582 && (GET_CODE (op0) == CONST_INT
7583 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
7584 tem = op0, op0 = op1, op1 = tem;
7586 if (GET_RTX_CLASS (code) == '<')
7588 enum machine_mode op_mode = GET_MODE (op0);
7589 if (op_mode == VOIDmode)
7590 op_mode = GET_MODE (op1);
7591 result = simplify_relational_operation (code, op_mode, op0, op1);
7594 result = simplify_binary_operation (code, mode, op0, op1);
7599 /* Put complex operands first and constants second. */
7600 if (GET_RTX_CLASS (code) == 'c'
7601 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7602 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7603 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7604 || (GET_CODE (op0) == SUBREG
7605 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7606 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7607 return gen_rtx_combine (code, mode, op1, op0);
7609 return gen_rtx_combine (code, mode, op0, op1);
7613 gen_unary (code, mode, op0)
7615 enum machine_mode mode;
7618 rtx result = simplify_unary_operation (code, mode, op0, mode);
7623 return gen_rtx_combine (code, mode, op0);
7626 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7627 comparison code that will be tested.
7629 The result is a possibly different comparison code to use. *POP0 and
7630 *POP1 may be updated.
7632 It is possible that we might detect that a comparison is either always
7633 true or always false. However, we do not perform general constant
7634 folding in combine, so this knowledge isn't useful. Such tautologies
7635 should have been detected earlier. Hence we ignore all such cases. */
7637 static enum rtx_code
7638 simplify_comparison (code, pop0, pop1)
7647 enum machine_mode mode, tmode;
7649 /* Try a few ways of applying the same transformation to both operands. */
7652 /* If both operands are the same constant shift, see if we can ignore the
7653 shift. We can if the shift is a rotate or if the bits shifted out of
7654 this shift are known to be zero for both inputs and if the type of
7655 comparison is compatible with the shift. */
7656 if (GET_CODE (op0) == GET_CODE (op1)
7657 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
7658 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
7659 || ((GET_CODE (op0) == LSHIFTRT
7660 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7661 && (code != GT && code != LT && code != GE && code != LE))
7662 || (GET_CODE (op0) == ASHIFTRT
7663 && (code != GTU && code != LTU
7664 && code != GEU && code != GEU)))
7665 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7666 && INTVAL (XEXP (op0, 1)) >= 0
7667 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
7668 && XEXP (op0, 1) == XEXP (op1, 1))
7670 enum machine_mode mode = GET_MODE (op0);
7671 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7672 int shift_count = INTVAL (XEXP (op0, 1));
7674 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
7675 mask &= (mask >> shift_count) << shift_count;
7676 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7677 mask = (mask & (mask << shift_count)) >> shift_count;
7679 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
7680 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
7681 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
7686 /* If both operands are AND's of a paradoxical SUBREG by constant, the
7687 SUBREGs are of the same mode, and, in both cases, the AND would
7688 be redundant if the comparison was done in the narrower mode,
7689 do the comparison in the narrower mode (e.g., we are AND'ing with 1
7690 and the operand's possibly nonzero bits are 0xffffff01; in that case
7691 if we only care about QImode, we don't need the AND). This case
7692 occurs if the output mode of an scc insn is not SImode and
7693 STORE_FLAG_VALUE == 1 (e.g., the 386). */
7695 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
7696 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7697 && GET_CODE (XEXP (op1, 1)) == CONST_INT
7698 && GET_CODE (XEXP (op0, 0)) == SUBREG
7699 && GET_CODE (XEXP (op1, 0)) == SUBREG
7700 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
7701 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
7702 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
7703 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7704 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7705 <= HOST_BITS_PER_WIDE_INT)
7706 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
7707 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7708 & ~ INTVAL (XEXP (op0, 1))) == 0
7709 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
7710 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7711 & ~ INTVAL (XEXP (op1, 1))) == 0)
7713 op0 = SUBREG_REG (XEXP (op0, 0));
7714 op1 = SUBREG_REG (XEXP (op1, 0));
7716 /* the resulting comparison is always unsigned since we masked off
7717 the original sign bit. */
7718 code = unsigned_condition (code);
7724 /* If the first operand is a constant, swap the operands and adjust the
7725 comparison code appropriately. */
7726 if (CONSTANT_P (op0))
7728 tem = op0, op0 = op1, op1 = tem;
7729 code = swap_condition (code);
7732 /* We now enter a loop during which we will try to simplify the comparison.
7733 For the most part, we only are concerned with comparisons with zero,
7734 but some things may really be comparisons with zero but not start
7735 out looking that way. */
7737 while (GET_CODE (op1) == CONST_INT)
7739 enum machine_mode mode = GET_MODE (op0);
7740 int mode_width = GET_MODE_BITSIZE (mode);
7741 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7742 int equality_comparison_p;
7743 int sign_bit_comparison_p;
7744 int unsigned_comparison_p;
7745 HOST_WIDE_INT const_op;
7747 /* We only want to handle integral modes. This catches VOIDmode,
7748 CCmode, and the floating-point modes. An exception is that we
7749 can handle VOIDmode if OP0 is a COMPARE or a comparison
7752 if (GET_MODE_CLASS (mode) != MODE_INT
7753 && ! (mode == VOIDmode
7754 && (GET_CODE (op0) == COMPARE
7755 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
7758 /* Get the constant we are comparing against and turn off all bits
7759 not on in our mode. */
7760 const_op = INTVAL (op1);
7761 if (mode_width <= HOST_BITS_PER_WIDE_INT)
7764 /* If we are comparing against a constant power of two and the value
7765 being compared can only have that single bit nonzero (e.g., it was
7766 `and'ed with that bit), we can replace this with a comparison
7769 && (code == EQ || code == NE || code == GE || code == GEU
7770 || code == LT || code == LTU)
7771 && mode_width <= HOST_BITS_PER_WIDE_INT
7772 && exact_log2 (const_op) >= 0
7773 && nonzero_bits (op0, mode) == const_op)
7775 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
7776 op1 = const0_rtx, const_op = 0;
7779 /* Similarly, if we are comparing a value known to be either -1 or
7780 0 with -1, change it to the opposite comparison against zero. */
7783 && (code == EQ || code == NE || code == GT || code == LE
7784 || code == GEU || code == LTU)
7785 && num_sign_bit_copies (op0, mode) == mode_width)
7787 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
7788 op1 = const0_rtx, const_op = 0;
7791 /* Do some canonicalizations based on the comparison code. We prefer
7792 comparisons against zero and then prefer equality comparisons.
7793 If we can reduce the size of a constant, we will do that too. */
7798 /* < C is equivalent to <= (C - 1) */
7802 op1 = GEN_INT (const_op);
7804 /* ... fall through to LE case below. */
7810 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
7814 op1 = GEN_INT (const_op);
7818 /* If we are doing a <= 0 comparison on a value known to have
7819 a zero sign bit, we can replace this with == 0. */
7820 else if (const_op == 0
7821 && mode_width <= HOST_BITS_PER_WIDE_INT
7822 && (nonzero_bits (op0, mode)
7823 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7828 /* >= C is equivalent to > (C - 1). */
7832 op1 = GEN_INT (const_op);
7834 /* ... fall through to GT below. */
7840 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
7844 op1 = GEN_INT (const_op);
7848 /* If we are doing a > 0 comparison on a value known to have
7849 a zero sign bit, we can replace this with != 0. */
7850 else if (const_op == 0
7851 && mode_width <= HOST_BITS_PER_WIDE_INT
7852 && (nonzero_bits (op0, mode)
7853 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
7858 /* < C is equivalent to <= (C - 1). */
7862 op1 = GEN_INT (const_op);
7864 /* ... fall through ... */
7867 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
7868 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7870 const_op = 0, op1 = const0_rtx;
7878 /* unsigned <= 0 is equivalent to == 0 */
7882 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
7883 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7885 const_op = 0, op1 = const0_rtx;
7891 /* >= C is equivalent to < (C - 1). */
7895 op1 = GEN_INT (const_op);
7897 /* ... fall through ... */
7900 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
7901 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
7903 const_op = 0, op1 = const0_rtx;
7910 /* unsigned > 0 is equivalent to != 0 */
7914 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
7915 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
7917 const_op = 0, op1 = const0_rtx;
7923 /* Compute some predicates to simplify code below. */
7925 equality_comparison_p = (code == EQ || code == NE);
7926 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
7927 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
7930 /* Now try cases based on the opcode of OP0. If none of the cases
7931 does a "continue", we exit this loop immediately after the
7934 switch (GET_CODE (op0))
7937 /* If we are extracting a single bit from a variable position in
7938 a constant that has only a single bit set and are comparing it
7939 with zero, we can convert this into an equality comparison
7940 between the position and the location of the single bit. We can't
7941 do this if bit endian and we don't have an extzv since we then
7942 can't know what mode to use for the endianness adjustment. */
7944 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
7945 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
7946 && XEXP (op0, 1) == const1_rtx
7947 && equality_comparison_p && const_op == 0
7948 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
7951 i = (GET_MODE_BITSIZE
7952 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
7955 op0 = XEXP (op0, 2);
7959 /* Result is nonzero iff shift count is equal to I. */
7960 code = reverse_condition (code);
7965 /* ... fall through ... */
7968 tem = expand_compound_operation (op0);
7977 /* If testing for equality, we can take the NOT of the constant. */
7978 if (equality_comparison_p
7979 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
7981 op0 = XEXP (op0, 0);
7986 /* If just looking at the sign bit, reverse the sense of the
7988 if (sign_bit_comparison_p)
7990 op0 = XEXP (op0, 0);
7991 code = (code == GE ? LT : GE);
7997 /* If testing for equality, we can take the NEG of the constant. */
7998 if (equality_comparison_p
7999 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8001 op0 = XEXP (op0, 0);
8006 /* The remaining cases only apply to comparisons with zero. */
8010 /* When X is ABS or is known positive,
8011 (neg X) is < 0 if and only if X != 0. */
8013 if (sign_bit_comparison_p
8014 && (GET_CODE (XEXP (op0, 0)) == ABS
8015 || (mode_width <= HOST_BITS_PER_WIDE_INT
8016 && (nonzero_bits (XEXP (op0, 0), mode)
8017 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8019 op0 = XEXP (op0, 0);
8020 code = (code == LT ? NE : EQ);
8024 /* If we have NEG of something whose two high-order bits are the
8025 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8026 if (num_sign_bit_copies (op0, mode) >= 2)
8028 op0 = XEXP (op0, 0);
8029 code = swap_condition (code);
8035 /* If we are testing equality and our count is a constant, we
8036 can perform the inverse operation on our RHS. */
8037 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8038 && (tem = simplify_binary_operation (ROTATERT, mode,
8039 op1, XEXP (op0, 1))) != 0)
8041 op0 = XEXP (op0, 0);
8046 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8047 a particular bit. Convert it to an AND of a constant of that
8048 bit. This will be converted into a ZERO_EXTRACT. */
8049 if (const_op == 0 && sign_bit_comparison_p
8050 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8051 && mode_width <= HOST_BITS_PER_WIDE_INT)
8053 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8056 - INTVAL (XEXP (op0, 1)))));
8057 code = (code == LT ? NE : EQ);
8061 /* ... fall through ... */
8064 /* ABS is ignorable inside an equality comparison with zero. */
8065 if (const_op == 0 && equality_comparison_p)
8067 op0 = XEXP (op0, 0);
8074 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8075 to (compare FOO CONST) if CONST fits in FOO's mode and we
8076 are either testing inequality or have an unsigned comparison
8077 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8078 if (! unsigned_comparison_p
8079 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8080 <= HOST_BITS_PER_WIDE_INT)
8081 && ((unsigned HOST_WIDE_INT) const_op
8082 < (((HOST_WIDE_INT) 1
8083 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8085 op0 = XEXP (op0, 0);
8091 /* Check for the case where we are comparing A - C1 with C2,
8092 both constants are smaller than 1/2 the maxium positive
8093 value in MODE, and the comparison is equality or unsigned.
8094 In that case, if A is either zero-extended to MODE or has
8095 sufficient sign bits so that the high-order bit in MODE
8096 is a copy of the sign in the inner mode, we can prove that it is
8097 safe to do the operation in the wider mode. This simplifies
8098 many range checks. */
8100 if (mode_width <= HOST_BITS_PER_WIDE_INT
8101 && subreg_lowpart_p (op0)
8102 && GET_CODE (SUBREG_REG (op0)) == PLUS
8103 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8104 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8105 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8106 < GET_MODE_MASK (mode) / 2)
8107 && (unsigned) const_op < GET_MODE_MASK (mode) / 2
8108 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8109 GET_MODE (SUBREG_REG (op0)))
8110 & ~ GET_MODE_MASK (mode))
8111 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8112 GET_MODE (SUBREG_REG (op0)))
8113 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8114 - GET_MODE_BITSIZE (mode)))))
8116 op0 = SUBREG_REG (op0);
8120 /* If the inner mode is narrower and we are extracting the low part,
8121 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8122 if (subreg_lowpart_p (op0)
8123 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8124 /* Fall through */ ;
8128 /* ... fall through ... */
8131 if ((unsigned_comparison_p || equality_comparison_p)
8132 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8133 <= HOST_BITS_PER_WIDE_INT)
8134 && ((unsigned HOST_WIDE_INT) const_op
8135 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8137 op0 = XEXP (op0, 0);
8143 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
8144 this for equality comparisons due to pathological cases involving
8146 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8147 && (tem = simplify_binary_operation (MINUS, mode, op1,
8148 XEXP (op0, 1))) != 0)
8150 op0 = XEXP (op0, 0);
8155 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8156 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8157 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8159 op0 = XEXP (XEXP (op0, 0), 0);
8160 code = (code == LT ? EQ : NE);
8166 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8167 of bits in X minus 1, is one iff X > 0. */
8168 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8169 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8170 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8171 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8173 op0 = XEXP (op0, 1);
8174 code = (code == GE ? LE : GT);
8180 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8181 if C is zero or B is a constant. */
8182 if (equality_comparison_p
8183 && 0 != (tem = simplify_binary_operation (XOR, mode,
8184 XEXP (op0, 1), op1)))
8186 op0 = XEXP (op0, 0);
8193 case LT: case LTU: case LE: case LEU:
8194 case GT: case GTU: case GE: case GEU:
8195 /* We can't do anything if OP0 is a condition code value, rather
8196 than an actual data value. */
8199 || XEXP (op0, 0) == cc0_rtx
8201 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8204 /* Get the two operands being compared. */
8205 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8206 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8208 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8210 /* Check for the cases where we simply want the result of the
8211 earlier test or the opposite of that result. */
8213 || (code == EQ && reversible_comparison_p (op0))
8214 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8215 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8216 && (STORE_FLAG_VALUE
8217 & (((HOST_WIDE_INT) 1
8218 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8220 || (code == GE && reversible_comparison_p (op0)))))
8222 code = (code == LT || code == NE
8223 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8224 op0 = tem, op1 = tem1;
8230 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8232 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8233 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8234 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8236 op0 = XEXP (op0, 1);
8237 code = (code == GE ? GT : LE);
8243 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8244 will be converted to a ZERO_EXTRACT later. */
8245 if (const_op == 0 && equality_comparison_p
8246 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8247 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8248 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8250 op0 = simplify_and_const_int
8251 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8253 XEXP (XEXP (op0, 0), 1)),
8258 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8259 zero and X is a comparison and C1 and C2 describe only bits set
8260 in STORE_FLAG_VALUE, we can compare with X. */
8261 if (const_op == 0 && equality_comparison_p
8262 && mode_width <= HOST_BITS_PER_WIDE_INT
8263 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8264 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8265 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8266 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8267 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8269 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8270 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8271 if ((~ STORE_FLAG_VALUE & mask) == 0
8272 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8273 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8274 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8276 op0 = XEXP (XEXP (op0, 0), 0);
8281 /* If we are doing an equality comparison of an AND of a bit equal
8282 to the sign bit, replace this with a LT or GE comparison of
8283 the underlying value. */
8284 if (equality_comparison_p
8286 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8287 && mode_width <= HOST_BITS_PER_WIDE_INT
8288 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8289 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8291 op0 = XEXP (op0, 0);
8292 code = (code == EQ ? GE : LT);
8296 /* If this AND operation is really a ZERO_EXTEND from a narrower
8297 mode, the constant fits within that mode, and this is either an
8298 equality or unsigned comparison, try to do this comparison in
8299 the narrower mode. */
8300 if ((equality_comparison_p || unsigned_comparison_p)
8301 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8302 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8303 & GET_MODE_MASK (mode))
8305 && const_op >> i == 0
8306 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8308 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8315 /* If we have (compare (xshift FOO N) (const_int C)) and
8316 the high order N bits of FOO (N+1 if an inequality comparison)
8317 are known to be zero, we can do this by comparing FOO with C
8318 shifted right N bits so long as the low-order N bits of C are
8320 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8321 && INTVAL (XEXP (op0, 1)) >= 0
8322 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8323 < HOST_BITS_PER_WIDE_INT)
8325 & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
8326 && mode_width <= HOST_BITS_PER_WIDE_INT
8327 && (nonzero_bits (XEXP (op0, 0), mode)
8328 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8329 + ! equality_comparison_p))) == 0)
8331 const_op >>= INTVAL (XEXP (op0, 1));
8332 op1 = GEN_INT (const_op);
8333 op0 = XEXP (op0, 0);
8337 /* If we are doing a sign bit comparison, it means we are testing
8338 a particular bit. Convert it to the appropriate AND. */
8339 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8340 && mode_width <= HOST_BITS_PER_WIDE_INT)
8342 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8345 - INTVAL (XEXP (op0, 1)))));
8346 code = (code == LT ? NE : EQ);
8350 /* If this an equality comparison with zero and we are shifting
8351 the low bit to the sign bit, we can convert this to an AND of the
8353 if (const_op == 0 && equality_comparison_p
8354 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8355 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8357 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8364 /* If this is an equality comparison with zero, we can do this
8365 as a logical shift, which might be much simpler. */
8366 if (equality_comparison_p && const_op == 0
8367 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8369 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8371 INTVAL (XEXP (op0, 1)));
8375 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8376 do the comparison in a narrower mode. */
8377 if (! unsigned_comparison_p
8378 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8379 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8380 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8381 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8382 MODE_INT, 1)) != BLKmode
8383 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8384 || ((unsigned HOST_WIDE_INT) - const_op
8385 <= GET_MODE_MASK (tmode))))
8387 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8391 /* ... fall through ... */
8393 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8394 the low order N bits of FOO are known to be zero, we can do this
8395 by comparing FOO with C shifted left N bits so long as no
8397 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8398 && INTVAL (XEXP (op0, 1)) >= 0
8399 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8400 && mode_width <= HOST_BITS_PER_WIDE_INT
8401 && (nonzero_bits (XEXP (op0, 0), mode)
8402 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8404 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8407 const_op <<= INTVAL (XEXP (op0, 1));
8408 op1 = GEN_INT (const_op);
8409 op0 = XEXP (op0, 0);
8413 /* If we are using this shift to extract just the sign bit, we
8414 can replace this with an LT or GE comparison. */
8416 && (equality_comparison_p || sign_bit_comparison_p)
8417 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8418 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8420 op0 = XEXP (op0, 0);
8421 code = (code == NE || code == GT ? LT : GE);
8430 /* Now make any compound operations involved in this comparison. Then,
8431 check for an outmost SUBREG on OP0 that isn't doing anything or is
8432 paradoxical. The latter case can only occur when it is known that the
8433 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8434 We can never remove a SUBREG for a non-equality comparison because the
8435 sign bit is in a different place in the underlying object. */
8437 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8438 op1 = make_compound_operation (op1, SET);
8440 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8441 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8442 && (code == NE || code == EQ)
8443 && ((GET_MODE_SIZE (GET_MODE (op0))
8444 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8446 op0 = SUBREG_REG (op0);
8447 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8450 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8451 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8452 && (code == NE || code == EQ)
8453 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8454 <= HOST_BITS_PER_WIDE_INT)
8455 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8456 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8457 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8459 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
8460 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8461 op0 = SUBREG_REG (op0), op1 = tem;
8463 /* We now do the opposite procedure: Some machines don't have compare
8464 insns in all modes. If OP0's mode is an integer mode smaller than a
8465 word and we can't do a compare in that mode, see if there is a larger
8466 mode for which we can do the compare. There are a number of cases in
8467 which we can use the wider mode. */
8469 mode = GET_MODE (op0);
8470 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8471 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8472 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8473 for (tmode = GET_MODE_WIDER_MODE (mode);
8475 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
8476 tmode = GET_MODE_WIDER_MODE (tmode))
8477 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
8479 /* If the only nonzero bits in OP0 and OP1 are those in the
8480 narrower mode and this is an equality or unsigned comparison,
8481 we can use the wider mode. Similarly for sign-extended
8482 values and equality or signed comparisons. */
8483 if (((code == EQ || code == NE
8484 || code == GEU || code == GTU || code == LEU || code == LTU)
8485 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
8486 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
8487 || ((code == EQ || code == NE
8488 || code == GE || code == GT || code == LE || code == LT)
8489 && (num_sign_bit_copies (op0, tmode)
8490 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
8491 && (num_sign_bit_copies (op1, tmode)
8492 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
8494 op0 = gen_lowpart_for_combine (tmode, op0);
8495 op1 = gen_lowpart_for_combine (tmode, op1);
8499 /* If this is a test for negative, we can make an explicit
8500 test of the sign bit. */
8502 if (op1 == const0_rtx && (code == LT || code == GE)
8503 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8505 op0 = gen_binary (AND, tmode,
8506 gen_lowpart_for_combine (tmode, op0),
8507 GEN_INT ((HOST_WIDE_INT) 1
8508 << (GET_MODE_BITSIZE (mode) - 1)));
8509 code = (code == LT) ? NE : EQ;
8520 /* Return 1 if we know that X, a comparison operation, is not operating
8521 on a floating-point value or is EQ or NE, meaning that we can safely
8525 reversible_comparison_p (x)
8528 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8529 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8532 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8538 x = get_last_value (XEXP (x, 0));
8539 return (x && GET_CODE (x) == COMPARE
8540 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
8546 /* Utility function for following routine. Called when X is part of a value
8547 being stored into reg_last_set_value. Sets reg_last_set_table_tick
8548 for each register mentioned. Similar to mention_regs in cse.c */
8551 update_table_tick (x)
8554 register enum rtx_code code = GET_CODE (x);
8555 register char *fmt = GET_RTX_FORMAT (code);
8560 int regno = REGNO (x);
8561 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8562 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8564 for (i = regno; i < endregno; i++)
8565 reg_last_set_table_tick[i] = label_tick;
8570 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8571 /* Note that we can't have an "E" in values stored; see
8572 get_last_value_validate. */
8574 update_table_tick (XEXP (x, i));
8577 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8578 are saying that the register is clobbered and we no longer know its
8579 value. If INSN is zero, don't update reg_last_set; this call is normally
8580 done with VALUE also zero to invalidate the register. */
8583 record_value_for_reg (reg, insn, value)
8588 int regno = REGNO (reg);
8589 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8590 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8593 /* If VALUE contains REG and we have a previous value for REG, substitute
8594 the previous value. */
8595 if (value && insn && reg_overlap_mentioned_p (reg, value))
8599 /* Set things up so get_last_value is allowed to see anything set up to
8601 subst_low_cuid = INSN_CUID (insn);
8602 tem = get_last_value (reg);
8605 value = replace_rtx (copy_rtx (value), reg, tem);
8608 /* For each register modified, show we don't know its value, that
8609 its value has been updated, and that we don't know the location of
8610 the death of the register. */
8611 for (i = regno; i < endregno; i ++)
8614 reg_last_set[i] = insn;
8615 reg_last_set_value[i] = 0;
8616 reg_last_death[i] = 0;
8619 /* Mark registers that are being referenced in this value. */
8621 update_table_tick (value);
8623 /* Now update the status of each register being set.
8624 If someone is using this register in this block, set this register
8625 to invalid since we will get confused between the two lives in this
8626 basic block. This makes using this register always invalid. In cse, we
8627 scan the table to invalidate all entries using this register, but this
8628 is too much work for us. */
8630 for (i = regno; i < endregno; i++)
8632 reg_last_set_label[i] = label_tick;
8633 if (value && reg_last_set_table_tick[i] == label_tick)
8634 reg_last_set_invalid[i] = 1;
8636 reg_last_set_invalid[i] = 0;
8639 /* The value being assigned might refer to X (like in "x++;"). In that
8640 case, we must replace it with (clobber (const_int 0)) to prevent
8642 if (value && ! get_last_value_validate (&value,
8643 reg_last_set_label[regno], 0))
8645 value = copy_rtx (value);
8646 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
8650 /* For the main register being modified, update the value. */
8651 reg_last_set_value[regno] = value;
8655 /* Used for communication between the following two routines. */
8656 static rtx record_dead_insn;
8658 /* Called via note_stores from record_dead_and_set_regs to handle one
8659 SET or CLOBBER in an insn. */
8662 record_dead_and_set_regs_1 (dest, setter)
8665 if (GET_CODE (dest) == REG)
8667 /* If we are setting the whole register, we know its value. Otherwise
8668 show that we don't know the value. We can handle SUBREG in
8670 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
8671 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
8672 else if (GET_CODE (setter) == SET
8673 && GET_CODE (SET_DEST (setter)) == SUBREG
8674 && SUBREG_REG (SET_DEST (setter)) == dest
8675 && subreg_lowpart_p (SET_DEST (setter)))
8676 record_value_for_reg (dest, record_dead_insn,
8677 gen_lowpart_for_combine (GET_MODE (dest),
8680 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
8682 else if (GET_CODE (dest) == MEM
8683 /* Ignore pushes, they clobber nothing. */
8684 && ! push_operand (dest, GET_MODE (dest)))
8685 mem_last_set = INSN_CUID (record_dead_insn);
8688 /* Update the records of when each REG was most recently set or killed
8689 for the things done by INSN. This is the last thing done in processing
8690 INSN in the combiner loop.
8692 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
8693 similar information mem_last_set (which insn most recently modified memory)
8694 and last_call_cuid (which insn was the most recent subroutine call). */
8697 record_dead_and_set_regs (insn)
8701 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
8703 if (REG_NOTE_KIND (link) == REG_DEAD)
8704 reg_last_death[REGNO (XEXP (link, 0))] = insn;
8705 else if (REG_NOTE_KIND (link) == REG_INC)
8706 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
8709 if (GET_CODE (insn) == CALL_INSN)
8710 last_call_cuid = mem_last_set = INSN_CUID (insn);
8712 record_dead_insn = insn;
8713 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
8716 /* Utility routine for the following function. Verify that all the registers
8717 mentioned in *LOC are valid when *LOC was part of a value set when
8718 label_tick == TICK. Return 0 if some are not.
8720 If REPLACE is non-zero, replace the invalid reference with
8721 (clobber (const_int 0)) and return 1. This replacement is useful because
8722 we often can get useful information about the form of a value (e.g., if
8723 it was produced by a shift that always produces -1 or 0) even though
8724 we don't know exactly what registers it was produced from. */
8727 get_last_value_validate (loc, tick, replace)
8733 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
8734 int len = GET_RTX_LENGTH (GET_CODE (x));
8737 if (GET_CODE (x) == REG)
8739 int regno = REGNO (x);
8740 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8741 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8744 for (j = regno; j < endregno; j++)
8745 if (reg_last_set_invalid[j]
8746 /* If this is a pseudo-register that was only set once, it is
8748 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
8749 && reg_last_set_label[j] > tick))
8752 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8759 for (i = 0; i < len; i++)
8761 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
8762 /* Don't bother with these. They shouldn't occur anyway. */
8766 /* If we haven't found a reason for it to be invalid, it is valid. */
8770 /* Get the last value assigned to X, if known. Some registers
8771 in the value may be replaced with (clobber (const_int 0)) if their value
8772 is known longer known reliably. */
8781 /* If this is a non-paradoxical SUBREG, get the value of its operand and
8782 then convert it to the desired mode. If this is a paradoxical SUBREG,
8783 we cannot predict what values the "extra" bits might have. */
8784 if (GET_CODE (x) == SUBREG
8785 && subreg_lowpart_p (x)
8786 && (GET_MODE_SIZE (GET_MODE (x))
8787 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8788 && (value = get_last_value (SUBREG_REG (x))) != 0)
8789 return gen_lowpart_for_combine (GET_MODE (x), value);
8791 if (GET_CODE (x) != REG)
8795 value = reg_last_set_value[regno];
8797 /* If we don't have a value or if it isn't for this basic block, return 0. */
8800 || (reg_n_sets[regno] != 1
8801 && (reg_last_set_label[regno] != label_tick)))
8804 /* If the value was set in a later insn that the ones we are processing,
8805 we can't use it even if the register was only set once, but make a quick
8806 check to see if the previous insn set it to something. This is commonly
8807 the case when the same pseudo is used by repeated insns. */
8809 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
8813 for (insn = prev_nonnote_insn (subst_insn);
8814 insn && INSN_CUID (insn) >= subst_low_cuid;
8815 insn = prev_nonnote_insn (insn))
8819 && (set = single_set (insn)) != 0
8820 && rtx_equal_p (SET_DEST (set), x))
8822 value = SET_SRC (set);
8824 /* Make sure that VALUE doesn't reference X. Replace any
8825 expliit references with a CLOBBER. If there are any remaining
8826 references (rare), don't use the value. */
8828 if (reg_mentioned_p (x, value))
8829 value = replace_rtx (copy_rtx (value), x,
8830 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
8832 if (reg_overlap_mentioned_p (x, value))
8839 /* If the value has all its registers valid, return it. */
8840 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
8843 /* Otherwise, make a copy and replace any invalid register with
8844 (clobber (const_int 0)). If that fails for some reason, return 0. */
8846 value = copy_rtx (value);
8847 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
8853 /* Return nonzero if expression X refers to a REG or to memory
8854 that is set in an instruction more recent than FROM_CUID. */
8857 use_crosses_set_p (x, from_cuid)
8863 register enum rtx_code code = GET_CODE (x);
8867 register int regno = REGNO (x);
8868 #ifdef PUSH_ROUNDING
8869 /* Don't allow uses of the stack pointer to be moved,
8870 because we don't know whether the move crosses a push insn. */
8871 if (regno == STACK_POINTER_REGNUM)
8874 return (reg_last_set[regno]
8875 && INSN_CUID (reg_last_set[regno]) > from_cuid);
8878 if (code == MEM && mem_last_set > from_cuid)
8881 fmt = GET_RTX_FORMAT (code);
8883 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8888 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8889 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
8892 else if (fmt[i] == 'e'
8893 && use_crosses_set_p (XEXP (x, i), from_cuid))
8899 /* Define three variables used for communication between the following
8902 static int reg_dead_regno, reg_dead_endregno;
8903 static int reg_dead_flag;
8905 /* Function called via note_stores from reg_dead_at_p.
8907 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
8908 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
8911 reg_dead_at_p_1 (dest, x)
8915 int regno, endregno;
8917 if (GET_CODE (dest) != REG)
8920 regno = REGNO (dest);
8921 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8922 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
8924 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
8925 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
8928 /* Return non-zero if REG is known to be dead at INSN.
8930 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
8931 referencing REG, it is dead. If we hit a SET referencing REG, it is
8932 live. Otherwise, see if it is live or dead at the start of the basic
8936 reg_dead_at_p (reg, insn)
8942 /* Set variables for reg_dead_at_p_1. */
8943 reg_dead_regno = REGNO (reg);
8944 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
8945 ? HARD_REGNO_NREGS (reg_dead_regno,
8951 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
8952 beginning of function. */
8953 for (; insn && GET_CODE (insn) != CODE_LABEL;
8954 insn = prev_nonnote_insn (insn))
8956 note_stores (PATTERN (insn), reg_dead_at_p_1);
8958 return reg_dead_flag == 1 ? 1 : 0;
8960 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
8964 /* Get the basic block number that we were in. */
8969 for (block = 0; block < n_basic_blocks; block++)
8970 if (insn == basic_block_head[block])
8973 if (block == n_basic_blocks)
8977 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
8978 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
8979 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
8985 /* Remove register number REGNO from the dead registers list of INSN.
8987 Return the note used to record the death, if there was one. */
8990 remove_death (regno, insn)
8994 register rtx note = find_regno_note (insn, REG_DEAD, regno);
8998 reg_n_deaths[regno]--;
8999 remove_note (insn, note);
9005 /* For each register (hardware or pseudo) used within expression X, if its
9006 death is in an instruction with cuid between FROM_CUID (inclusive) and
9007 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9008 list headed by PNOTES.
9010 This is done when X is being merged by combination into TO_INSN. These
9011 notes will then be distributed as needed. */
9014 move_deaths (x, from_cuid, to_insn, pnotes)
9021 register int len, i;
9022 register enum rtx_code code = GET_CODE (x);
9026 register int regno = REGNO (x);
9027 register rtx where_dead = reg_last_death[regno];
9029 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9030 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9032 rtx note = remove_death (regno, reg_last_death[regno]);
9034 /* It is possible for the call above to return 0. This can occur
9035 when reg_last_death points to I2 or I1 that we combined with.
9036 In that case make a new note. */
9040 XEXP (note, 1) = *pnotes;
9044 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9046 reg_n_deaths[regno]++;
9052 else if (GET_CODE (x) == SET)
9054 rtx dest = SET_DEST (x);
9056 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9058 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9059 that accesses one word of a multi-word item, some
9060 piece of everything register in the expression is used by
9061 this insn, so remove any old death. */
9063 if (GET_CODE (dest) == ZERO_EXTRACT
9064 || GET_CODE (dest) == STRICT_LOW_PART
9065 || (GET_CODE (dest) == SUBREG
9066 && (((GET_MODE_SIZE (GET_MODE (dest))
9067 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9068 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9069 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9071 move_deaths (dest, from_cuid, to_insn, pnotes);
9075 /* If this is some other SUBREG, we know it replaces the entire
9076 value, so use that as the destination. */
9077 if (GET_CODE (dest) == SUBREG)
9078 dest = SUBREG_REG (dest);
9080 /* If this is a MEM, adjust deaths of anything used in the address.
9081 For a REG (the only other possibility), the entire value is
9082 being replaced so the old value is not used in this insn. */
9084 if (GET_CODE (dest) == MEM)
9085 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9089 else if (GET_CODE (x) == CLOBBER)
9092 len = GET_RTX_LENGTH (code);
9093 fmt = GET_RTX_FORMAT (code);
9095 for (i = 0; i < len; i++)
9100 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9101 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9103 else if (fmt[i] == 'e')
9104 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9108 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9109 pattern of an insn. X must be a REG. */
9112 reg_bitfield_target_p (x, body)
9118 if (GET_CODE (body) == SET)
9120 rtx dest = SET_DEST (body);
9122 int regno, tregno, endregno, endtregno;
9124 if (GET_CODE (dest) == ZERO_EXTRACT)
9125 target = XEXP (dest, 0);
9126 else if (GET_CODE (dest) == STRICT_LOW_PART)
9127 target = SUBREG_REG (XEXP (dest, 0));
9131 if (GET_CODE (target) == SUBREG)
9132 target = SUBREG_REG (target);
9134 if (GET_CODE (target) != REG)
9137 tregno = REGNO (target), regno = REGNO (x);
9138 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9141 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9142 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9144 return endregno > tregno && regno < endtregno;
9147 else if (GET_CODE (body) == PARALLEL)
9148 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9149 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9155 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9156 as appropriate. I3 and I2 are the insns resulting from the combination
9157 insns including FROM (I2 may be zero).
9159 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9160 not need REG_DEAD notes because they are being substituted for. This
9161 saves searching in the most common cases.
9163 Each note in the list is either ignored or placed on some insns, depending
9164 on the type of note. */
9167 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9171 rtx elim_i2, elim_i1;
9173 rtx note, next_note;
9176 for (note = notes; note; note = next_note)
9178 rtx place = 0, place2 = 0;
9180 /* If this NOTE references a pseudo register, ensure it references
9181 the latest copy of that register. */
9182 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9183 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9184 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9186 next_note = XEXP (note, 1);
9187 switch (REG_NOTE_KIND (note))
9190 /* If this register is set or clobbered in I3, put the note there
9191 unless there is one already. */
9192 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9194 if (! (GET_CODE (XEXP (note, 0)) == REG
9195 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9196 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9199 /* Otherwise, if this register is used by I3, then this register
9200 now dies here, so we must put a REG_DEAD note here unless there
9202 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9203 && ! (GET_CODE (XEXP (note, 0)) == REG
9204 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9205 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9207 PUT_REG_NOTE_KIND (note, REG_DEAD);
9215 /* These notes say something about results of an insn. We can
9216 only support them if they used to be on I3 in which case they
9217 remain on I3. Otherwise they are ignored.
9219 If the note refers to an expression that is not a constant, we
9220 must also ignore the note since we cannot tell whether the
9221 equivalence is still true. It might be possible to do
9222 slightly better than this (we only have a problem if I2DEST
9223 or I1DEST is present in the expression), but it doesn't
9224 seem worth the trouble. */
9227 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9232 case REG_NO_CONFLICT:
9234 /* These notes say something about how a register is used. They must
9235 be present on any use of the register in I2 or I3. */
9236 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9239 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9249 /* It is too much trouble to try to see if this note is still
9250 correct in all situations. It is better to simply delete it. */
9254 /* If the insn previously containing this note still exists,
9255 put it back where it was. Otherwise move it to the previous
9256 insn. Adjust the corresponding REG_LIBCALL note. */
9257 if (GET_CODE (from_insn) != NOTE)
9261 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9262 place = prev_real_insn (from_insn);
9264 XEXP (tem, 0) = place;
9269 /* This is handled similarly to REG_RETVAL. */
9270 if (GET_CODE (from_insn) != NOTE)
9274 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9275 place = next_real_insn (from_insn);
9277 XEXP (tem, 0) = place;
9282 /* If the register is used as an input in I3, it dies there.
9283 Similarly for I2, if it is non-zero and adjacent to I3.
9285 If the register is not used as an input in either I3 or I2
9286 and it is not one of the registers we were supposed to eliminate,
9287 there are two possibilities. We might have a non-adjacent I2
9288 or we might have somehow eliminated an additional register
9289 from a computation. For example, we might have had A & B where
9290 we discover that B will always be zero. In this case we will
9291 eliminate the reference to A.
9293 In both cases, we must search to see if we can find a previous
9294 use of A and put the death note there. */
9296 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9298 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9299 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9302 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9305 /* If the register is used in both I2 and I3 and it dies in I3,
9306 we might have added another reference to it. If reg_n_refs
9307 was 2, bump it to 3. This has to be correct since the
9308 register must have been set somewhere. The reason this is
9309 done is because local-alloc.c treats 2 references as a
9312 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9313 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9314 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9315 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9318 for (tem = prev_nonnote_insn (i3);
9319 tem && (GET_CODE (tem) == INSN
9320 || GET_CODE (tem) == CALL_INSN);
9321 tem = prev_nonnote_insn (tem))
9323 /* If the register is being set at TEM, see if that is all
9324 TEM is doing. If so, delete TEM. Otherwise, make this
9325 into a REG_UNUSED note instead. */
9326 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9328 rtx set = single_set (tem);
9330 /* Verify that it was the set, and not a clobber that
9331 modified the register. */
9333 if (set != 0 && ! side_effects_p (SET_SRC (set))
9334 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9336 /* Move the notes and links of TEM elsewhere.
9337 This might delete other dead insns recursively.
9338 First set the pattern to something that won't use
9341 PATTERN (tem) = pc_rtx;
9343 distribute_notes (REG_NOTES (tem), tem, tem,
9344 NULL_RTX, NULL_RTX, NULL_RTX);
9345 distribute_links (LOG_LINKS (tem));
9347 PUT_CODE (tem, NOTE);
9348 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9349 NOTE_SOURCE_FILE (tem) = 0;
9353 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9355 /* If there isn't already a REG_UNUSED note, put one
9357 if (! find_regno_note (tem, REG_UNUSED,
9358 REGNO (XEXP (note, 0))))
9363 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9370 /* If the register is set or already dead at PLACE, we needn't do
9371 anything with this note if it is still a REG_DEAD note.
9373 Note that we cannot use just `dead_or_set_p' here since we can
9374 convert an assignment to a register into a bit-field assignment.
9375 Therefore, we must also omit the note if the register is the
9376 target of a bitfield assignment. */
9378 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9380 int regno = REGNO (XEXP (note, 0));
9382 if (dead_or_set_p (place, XEXP (note, 0))
9383 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9385 /* Unless the register previously died in PLACE, clear
9386 reg_last_death. [I no longer understand why this is
9388 if (reg_last_death[regno] != place)
9389 reg_last_death[regno] = 0;
9393 reg_last_death[regno] = place;
9395 /* If this is a death note for a hard reg that is occupying
9396 multiple registers, ensure that we are still using all
9397 parts of the object. If we find a piece of the object
9398 that is unused, we must add a USE for that piece before
9399 PLACE and put the appropriate REG_DEAD note on it.
9401 An alternative would be to put a REG_UNUSED for the pieces
9402 on the insn that set the register, but that can't be done if
9403 it is not in the same block. It is simpler, though less
9404 efficient, to add the USE insns. */
9406 if (place && regno < FIRST_PSEUDO_REGISTER
9407 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9410 = regno + HARD_REGNO_NREGS (regno,
9411 GET_MODE (XEXP (note, 0)));
9415 for (i = regno; i < endregno; i++)
9416 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9418 rtx piece = gen_rtx (REG, word_mode, i);
9421 /* See if we already placed a USE note for this
9422 register in front of PLACE. */
9424 GET_CODE (PREV_INSN (p)) == INSN
9425 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9427 if (rtx_equal_p (piece,
9428 XEXP (PATTERN (PREV_INSN (p)), 0)))
9437 = emit_insn_before (gen_rtx (USE, VOIDmode,
9440 REG_NOTES (use_insn)
9441 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9442 REG_NOTES (use_insn));
9450 /* Put only REG_DEAD notes for pieces that are
9451 still used and that are not already dead or set. */
9453 for (i = regno; i < endregno; i++)
9455 rtx piece = gen_rtx (REG, word_mode, i);
9457 if (reg_referenced_p (piece, PATTERN (place))
9458 && ! dead_or_set_p (place, piece)
9459 && ! reg_bitfield_target_p (piece,
9461 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9473 /* Any other notes should not be present at this point in the
9480 XEXP (note, 1) = REG_NOTES (place);
9481 REG_NOTES (place) = note;
9483 else if ((REG_NOTE_KIND (note) == REG_DEAD
9484 || REG_NOTE_KIND (note) == REG_UNUSED)
9485 && GET_CODE (XEXP (note, 0)) == REG)
9486 reg_n_deaths[REGNO (XEXP (note, 0))]--;
9490 if ((REG_NOTE_KIND (note) == REG_DEAD
9491 || REG_NOTE_KIND (note) == REG_UNUSED)
9492 && GET_CODE (XEXP (note, 0)) == REG)
9493 reg_n_deaths[REGNO (XEXP (note, 0))]++;
9495 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
9496 XEXP (note, 0), REG_NOTES (place2));
9501 /* Similarly to above, distribute the LOG_LINKS that used to be present on
9502 I3, I2, and I1 to new locations. This is also called in one case to
9503 add a link pointing at I3 when I3's destination is changed. */
9506 distribute_links (links)
9509 rtx link, next_link;
9511 for (link = links; link; link = next_link)
9517 next_link = XEXP (link, 1);
9519 /* If the insn that this link points to is a NOTE or isn't a single
9520 set, ignore it. In the latter case, it isn't clear what we
9521 can do other than ignore the link, since we can't tell which
9522 register it was for. Such links wouldn't be used by combine
9525 It is not possible for the destination of the target of the link to
9526 have been changed by combine. The only potential of this is if we
9527 replace I3, I2, and I1 by I3 and I2. But in that case the
9528 destination of I2 also remains unchanged. */
9530 if (GET_CODE (XEXP (link, 0)) == NOTE
9531 || (set = single_set (XEXP (link, 0))) == 0)
9534 reg = SET_DEST (set);
9535 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9536 || GET_CODE (reg) == SIGN_EXTRACT
9537 || GET_CODE (reg) == STRICT_LOW_PART)
9538 reg = XEXP (reg, 0);
9540 /* A LOG_LINK is defined as being placed on the first insn that uses
9541 a register and points to the insn that sets the register. Start
9542 searching at the next insn after the target of the link and stop
9543 when we reach a set of the register or the end of the basic block.
9545 Note that this correctly handles the link that used to point from
9546 I3 to I2. Also note that not much searching is typically done here
9547 since most links don't point very far away. */
9549 for (insn = NEXT_INSN (XEXP (link, 0));
9550 (insn && GET_CODE (insn) != CODE_LABEL
9551 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
9552 insn = NEXT_INSN (insn))
9553 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
9554 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9556 if (reg_referenced_p (reg, PATTERN (insn)))
9561 /* If we found a place to put the link, place it there unless there
9562 is already a link to the same insn as LINK at that point. */
9568 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
9569 if (XEXP (link2, 0) == XEXP (link, 0))
9574 XEXP (link, 1) = LOG_LINKS (place);
9575 LOG_LINKS (place) = link;
9582 dump_combine_stats (file)
9587 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
9588 combine_attempts, combine_merges, combine_extras, combine_successes);
9592 dump_combine_total_stats (file)
9597 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
9598 total_attempts, total_merges, total_extras, total_successes);