1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
84 #include "basic-block.h"
85 #include "insn-config.h"
86 #include "insn-flags.h"
87 #include "insn-codes.h"
88 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras;
108 /* Number of instructions combined in this function. */
110 static int combine_successes;
112 /* Totals over entire compilation. */
114 static int total_attempts, total_merges, total_extras, total_successes;
116 /* Vector mapping INSN_UIDs to cuids.
117 The cuids are like uids but increase monotonically always.
118 Combine always uses cuids so that it can compare them.
119 But actually renumbering the uids, which we used to do,
120 proves to be a bad idea because it makes it hard to compare
121 the dumps produced by earlier passes with those from later passes. */
123 static int *uid_cuid;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
129 /* Maximum register number, which is the size of the tables below. */
131 static int combine_max_regno;
133 /* Record last point of death of (hard or pseudo) register n. */
135 static rtx *reg_last_death;
137 /* Record last point of modification of (hard or pseudo) register n. */
139 static rtx *reg_last_set;
141 /* Record the cuid of the last insn that invalidated memory
142 (anything that writes memory, and subroutine calls, but not pushes). */
144 static int mem_last_set;
146 /* Record the cuid of the last CALL_INSN
147 so we can tell whether a potential combination crosses any calls. */
149 static int last_call_cuid;
151 /* When `subst' is called, this is the insn that is being modified
152 (by combining in a previous insn). The PATTERN of this insn
153 is still the old pattern partially modified and it should not be
154 looked at, but this may be used to examine the successors of the insn
155 to judge whether a simplification is valid. */
157 static rtx subst_insn;
159 /* This is the lowest CUID that `subst' is currently dealing with.
160 get_last_value will not return a value if the register was set at or
161 after this CUID. If not for this mechanism, we could get confused if
162 I2 or I1 in try_combine were an insn that used the old value of a register
163 to obtain a new value. In that case, we might erroneously get the
164 new value of the register when we wanted the old one. */
166 static int subst_low_cuid;
168 /* This is the value of undobuf.num_undo when we started processing this
169 substitution. This will prevent gen_rtx_combine from re-used a piece
170 from the previous expression. Doing so can produce circular rtl
173 static int previous_num_undos;
175 /* The next group of arrays allows the recording of the last value assigned
176 to (hard or pseudo) register n. We use this information to see if a
177 operation being processed is redundant given a prior operation performed
178 on the register. For example, an `and' with a constant is redundant if
179 all the zero bits are already known to be turned off.
181 We use an approach similar to that used by cse, but change it in the
184 (1) We do not want to reinitialize at each label.
185 (2) It is useful, but not critical, to know the actual value assigned
186 to a register. Often just its form is helpful.
188 Therefore, we maintain the following arrays:
190 reg_last_set_value the last value assigned
191 reg_last_set_label records the value of label_tick when the
192 register was assigned
193 reg_last_set_table_tick records the value of label_tick when a
194 value using the register is assigned
195 reg_last_set_invalid set to non-zero when it is not valid
196 to use the value of this register in some
199 To understand the usage of these tables, it is important to understand
200 the distinction between the value in reg_last_set_value being valid
201 and the register being validly contained in some other expression in the
204 Entry I in reg_last_set_value is valid if it is non-zero, and either
205 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
207 Register I may validly appear in any expression returned for the value
208 of another register if reg_n_sets[i] is 1. It may also appear in the
209 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
210 reg_last_set_invalid[j] is zero.
212 If an expression is found in the table containing a register which may
213 not validly appear in an expression, the register is replaced by
214 something that won't match, (clobber (const_int 0)).
216 reg_last_set_invalid[i] is set non-zero when register I is being assigned
217 to and reg_last_set_table_tick[i] == label_tick. */
219 /* Record last value assigned to (hard or pseudo) register n. */
221 static rtx *reg_last_set_value;
223 /* Record the value of label_tick when the value for register n is placed in
224 reg_last_set_value[n]. */
226 static short *reg_last_set_label;
228 /* Record the value of label_tick when an expression involving register n
229 is placed in reg_last_set_value. */
231 static short *reg_last_set_table_tick;
233 /* Set non-zero if references to register n in expressions should not be
236 static char *reg_last_set_invalid;
238 /* Incremented for each label. */
240 static short label_tick;
242 /* Some registers that are set more than once and used in more than one
243 basic block are nevertheless always set in similar ways. For example,
244 a QImode register may be loaded from memory in two places on a machine
245 where byte loads zero extend.
247 We record in the following array what we know about the significant
248 bits of a register, specifically which bits are known to be zero.
250 If an entry is zero, it means that we don't know anything special. */
252 static int *reg_significant;
254 /* Mode used to compute significance in reg_significant. It is the largest
255 integer mode that can fit in HOST_BITS_PER_INT. */
257 static enum machine_mode significant_mode;
259 /* Nonzero when reg_significant can be safely used. It is zero while
260 computing reg_significant. This prevents propagating values based
261 on previously set values, which can be incorrect if a variable
262 is modified in a loop. */
264 static int significant_valid;
266 /* Record one modification to rtl structure
267 to be undone by storing old_contents into *where.
268 is_int is 1 if the contents are an int. */
284 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
285 num_undo says how many are currently recorded.
287 storage is nonzero if we must undo the allocation of new storage.
288 The value of storage is what to pass to obfree.
290 other_insn is nonzero if we have modified some other insn in the process
291 of working on subst_insn. It must be verified too. */
299 struct undo undo[MAX_UNDO];
303 static struct undobuf undobuf;
305 /* Substitute NEWVAL, an rtx expression, into INTO, a place in a some
306 insn. The substitution can be undone by undo_all. If INTO is already
307 set to NEWVAL, do not record this change. */
309 #define SUBST(INTO, NEWVAL) \
310 do { if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].where = &INTO; \
313 undobuf.undo[undobuf.num_undo].old_contents = INTO; \
314 undobuf.undo[undobuf.num_undo].is_int = 0; \
316 if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
329 = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \
330 u->where = (int *) &INTO; \
331 u->old_contents = INTO; \
334 if (u->old_contents != INTO) \
335 undobuf.num_undo++; \
339 /* Number of times the pseudo being substituted for
340 was found and replaced. */
342 static int n_occurrences;
344 static void set_significant ();
345 static void move_deaths ();
347 static void record_value_for_reg ();
348 static void record_dead_and_set_regs ();
349 static int use_crosses_set_p ();
350 static rtx try_combine ();
351 static rtx *find_split_point ();
353 static void undo_all ();
354 static int reg_dead_at_p ();
355 static rtx expand_compound_operation ();
356 static rtx expand_field_assignment ();
357 static rtx make_extraction ();
358 static int get_pos_from_mask ();
359 static rtx make_field_assignment ();
360 static rtx make_compound_operation ();
361 static rtx apply_distributive_law ();
362 static rtx simplify_and_const_int ();
363 static unsigned significant_bits ();
364 static int merge_outer_ops ();
365 static rtx simplify_shift_const ();
366 static int recog_for_combine ();
367 static rtx gen_lowpart_for_combine ();
368 static rtx gen_rtx_combine ();
369 static rtx gen_binary ();
370 static rtx gen_unary ();
371 static enum rtx_code simplify_comparison ();
372 static int reversible_comparison_p ();
373 static int get_last_value_validate ();
374 static rtx get_last_value ();
375 static void distribute_notes ();
376 static void distribute_links ();
378 /* Main entry point for combiner. F is the first insn of the function.
379 NREGS is the first unused pseudo-reg number. */
382 combine_instructions (f, nregs)
386 register rtx insn, next, prev;
388 register rtx links, nextlinks;
390 combine_attempts = 0;
393 combine_successes = 0;
395 combine_max_regno = nregs;
397 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
398 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
399 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
400 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
401 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
402 reg_last_set_invalid = (char *) alloca (nregs * sizeof (short));
403 reg_significant = (int *) alloca (nregs * sizeof (int));
405 bzero (reg_last_death, nregs * sizeof (rtx));
406 bzero (reg_last_set, nregs * sizeof (rtx));
407 bzero (reg_last_set_value, nregs * sizeof (rtx));
408 bzero (reg_last_set_table_tick, nregs * sizeof (short));
409 bzero (reg_last_set_invalid, nregs * sizeof (char));
410 bzero (reg_significant, nregs * sizeof (int));
412 init_recog_no_volatile ();
414 /* Compute maximum uid value so uid_cuid can be allocated. */
416 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
417 if (INSN_UID (insn) > i)
420 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
422 significant_mode = mode_for_size (HOST_BITS_PER_INT, MODE_INT, 0);
424 /* Don't use reg_significant when computing it. This can cause problems
425 when, for example, we have j <<= 1 in a loop. */
427 significant_valid = 0;
429 /* Compute the mapping from uids to cuids.
430 Cuids are numbers assigned to insns, like uids,
431 except that cuids increase monotonically through the code.
433 Scan all SETs and see if we can deduce anything about what
434 bits are significant for some registers. */
436 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
438 INSN_CUID (insn) = ++i;
439 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
440 note_stores (PATTERN (insn), set_significant);
443 significant_valid = 1;
445 /* Now scan all the insns in forward order. */
451 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
455 if (GET_CODE (insn) == CODE_LABEL)
458 else if (GET_CODE (insn) == INSN
459 || GET_CODE (insn) == CALL_INSN
460 || GET_CODE (insn) == JUMP_INSN)
462 /* Try this insn with each insn it links back to. */
464 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
465 if ((next = try_combine (insn, XEXP (links, 0), 0)) != 0)
468 /* Try each sequence of three linked insns ending with this one. */
470 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
471 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
472 nextlinks = XEXP (nextlinks, 1))
473 if ((next = try_combine (insn, XEXP (links, 0),
474 XEXP (nextlinks, 0))) != 0)
478 /* Try to combine a jump insn that uses CC0
479 with a preceding insn that sets CC0, and maybe with its
480 logical predecessor as well.
481 This is how we make decrement-and-branch insns.
482 We need this special code because data flow connections
483 via CC0 do not get entered in LOG_LINKS. */
485 if (GET_CODE (insn) == JUMP_INSN
486 && (prev = prev_nonnote_insn (insn)) != 0
487 && GET_CODE (prev) == INSN
488 && sets_cc0_p (PATTERN (prev)))
490 if ((next = try_combine (insn, prev, 0)) != 0)
493 for (nextlinks = LOG_LINKS (prev); nextlinks;
494 nextlinks = XEXP (nextlinks, 1))
495 if ((next = try_combine (insn, prev,
496 XEXP (nextlinks, 0))) != 0)
500 /* Do the same for an insn that explicitly references CC0. */
501 if (GET_CODE (insn) == INSN
502 && (prev = prev_nonnote_insn (insn)) != 0
503 && GET_CODE (prev) == INSN
504 && sets_cc0_p (PATTERN (prev))
505 && GET_CODE (PATTERN (insn)) == SET
506 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
508 if ((next = try_combine (insn, prev, 0)) != 0)
511 for (nextlinks = LOG_LINKS (prev); nextlinks;
512 nextlinks = XEXP (nextlinks, 1))
513 if ((next = try_combine (insn, prev,
514 XEXP (nextlinks, 0))) != 0)
518 /* Finally, see if any of the insns that this insn links to
519 explicitly references CC0. If so, try this insn, that insn,
520 and its predecessor if it sets CC0. */
521 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
522 if (GET_CODE (XEXP (links, 0)) == INSN
523 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
524 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
525 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
526 && GET_CODE (prev) == INSN
527 && sets_cc0_p (PATTERN (prev))
528 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
532 /* Try combining an insn with two different insns whose results it
534 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
535 for (nextlinks = XEXP (links, 1); nextlinks;
536 nextlinks = XEXP (nextlinks, 1))
537 if ((next = try_combine (insn, XEXP (links, 0),
538 XEXP (nextlinks, 0))) != 0)
541 if (GET_CODE (insn) != NOTE)
542 record_dead_and_set_regs (insn);
549 total_attempts += combine_attempts;
550 total_merges += combine_merges;
551 total_extras += combine_extras;
552 total_successes += combine_successes;
555 /* Called via note_stores. If X is a pseudo that is used in more than
556 one basic block, is narrower that HOST_BITS_PER_INT, and is being
557 set, record what bits are significant. If we are clobbering X,
558 ignore this "set" because the clobbered value won't be used.
560 If we are setting only a portion of X and we can't figure out what
561 portion, assume all bits will be used since we don't know what will
565 set_significant (x, set)
569 if (GET_CODE (x) == REG
570 && REGNO (x) >= FIRST_PSEUDO_REGISTER
571 && reg_n_sets[REGNO (x)] > 1
572 && reg_basic_block[REGNO (x)] < 0
573 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_INT)
575 if (GET_CODE (set) == CLOBBER)
578 /* If this is a complex assignment, see if we can convert it into a
579 simple assignment. */
580 set = expand_field_assignment (set);
581 if (SET_DEST (set) == x)
582 reg_significant[REGNO (x)]
583 |= significant_bits (SET_SRC (set), significant_mode);
585 reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
589 /* See if INSN can be combined into I3. PRED and SUCC are optionally
590 insns that were previously combined into I3 or that will be combined
591 into the merger of INSN and I3.
593 Return 0 if the combination is not allowed for any reason.
595 If the combination is allowed, *PDEST will be set to the single
596 destination of INSN and *PSRC to the single source, and this function
600 can_combine_p (insn, i3, pred, succ, pdest, psrc)
607 rtx set = 0, src, dest;
609 int all_adjacent = (succ ? (next_active_insn (insn) == succ
610 && next_active_insn (succ) == i3)
611 : next_active_insn (insn) == i3);
613 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
614 or a PARALLEL consisting of such a SET and CLOBBERs.
616 If INSN has CLOBBER parallel parts, ignore them for our processing.
617 By definition, these happen during the execution of the insn. When it
618 is merged with another insn, all bets are off. If they are, in fact,
619 needed and aren't also supplied in I3, they may be added by
620 recog_for_combine. Otherwise, it won't match.
622 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
625 Get the source and destination of INSN. If more than one, can't
628 if (GET_CODE (PATTERN (insn)) == SET)
629 set = PATTERN (insn);
630 else if (GET_CODE (PATTERN (insn)) == PARALLEL
631 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
633 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
635 rtx elt = XVECEXP (PATTERN (insn), 0, i);
637 switch (GET_CODE (elt))
639 /* We can ignore CLOBBERs. */
644 /* Ignore SETs whose result isn't used but not those that
645 have side-effects. */
646 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
647 && ! side_effects_p (elt))
650 /* If we have already found a SET, this is a second one and
651 so we cannot combine with this insn. */
659 /* Anything else means we can't combine. */
665 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
666 so don't do anything with it. */
667 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
676 set = expand_field_assignment (set);
677 src = SET_SRC (set), dest = SET_DEST (set);
679 /* Don't eliminate a store in the stack pointer. */
680 if (dest == stack_pointer_rtx
681 /* Don't install a subreg involving two modes not tieable.
682 It can worsen register allocation, and can even make invalid reload
683 insns, since the reg inside may need to be copied from in the
684 outside mode, and that may be invalid if it is an fp reg copied in
685 integer mode. As a special exception, we can allow this if
686 I3 is simply copying DEST, a REG, to CC0. */
687 || (GET_CODE (src) == SUBREG
688 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
690 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
691 && SET_DEST (PATTERN (i3)) == cc0_rtx
692 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
695 /* If we couldn't eliminate a field assignment, we can't combine. */
696 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
697 /* Don't combine with an insn that sets a register to itself if it has
698 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
699 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, 0))
700 /* Can't merge a function call. */
701 || GET_CODE (src) == CALL
702 /* Don't substitute into an incremented register. */
703 || FIND_REG_INC_NOTE (i3, dest)
704 || (succ && FIND_REG_INC_NOTE (succ, dest))
705 /* Don't combine the end of a libcall into anything. */
706 || find_reg_note (insn, REG_RETVAL, 0)
707 /* Make sure that DEST is not used after SUCC but before I3. */
708 || (succ && ! all_adjacent
709 && reg_used_between_p (dest, succ, i3))
710 /* Make sure that the value that is to be substituted for the register
711 does not use any registers whose values alter in between. However,
712 If the insns are adjacent, a use can't cross a set even though we
713 think it might (this can happen for a sequence of insns each setting
714 the same destination; reg_last_set of that register might point to
715 a NOTE). Also, don't move a volatile asm across any other insns. */
717 && (use_crosses_set_p (src, INSN_CUID (insn))
718 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
719 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
720 better register allocation by not doing the combine. */
721 || find_reg_note (i3, REG_NO_CONFLICT, dest)
722 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
723 /* Don't combine across a CALL_INSN, because that would possibly
724 change whether the life span of some REGs crosses calls or not,
725 and it is a pain to update that information.
726 Exception: if source is a constant, moving it later can't hurt.
727 Accept that special case, because it helps -fforce-addr a lot. */
728 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
731 /* DEST must either be a REG or CC0. */
732 if (GET_CODE (dest) == REG)
734 /* If register alignment is being enforced for multi-word items in all
735 cases except for parameters, it is possible to have a register copy
736 insn referencing a hard register that is not allowed to contain the
737 mode being copied and which would not be valid as an operand of most
738 insns. Eliminate this problem by not combining with such an insn.
740 Also, on some machines we don't want to extend the life of a hard
743 if (GET_CODE (src) == REG
744 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
745 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
746 #ifdef SMALL_REGISTER_CLASSES
747 /* Don't extend the life of a hard register. */
748 || REGNO (src) < FIRST_PSEUDO_REGISTER
750 || (REGNO (src) < FIRST_PSEUDO_REGISTER
751 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
756 else if (GET_CODE (dest) != CC0)
759 /* Don't substitute for a register intended as a clobberable operand. */
760 if (GET_CODE (PATTERN (i3)) == PARALLEL)
761 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
762 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
763 && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))
766 /* If INSN contains anything volatile, or is an `asm' (whether volatile
767 or not), reject, unless nothing volatile comes between it and I3,
768 with the exception of SUCC. */
770 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
772 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
773 && p != succ && volatile_refs_p (PATTERN (p)))
776 /* If INSN or I2 contains an autoincrement or autodecrement,
777 make sure that register is not used between there and I3,
778 and not already used in I3 either.
779 Also insist that I3 not be a jump; if it were one
780 and the incremented register were spilled, we would lose. */
783 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
784 if (REG_NOTE_KIND (link) == REG_INC
785 && (GET_CODE (i3) == JUMP_INSN
786 || reg_used_between_p (XEXP (link, 0), insn, i3)
787 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
792 /* Don't combine an insn that follows a CC0-setting insn.
793 An insn that uses CC0 must not be separated from the one that sets it.
794 We do, however, allow I2 to follow a CC0-setting insn if that insn
795 is passed as I1; in that case it will be deleted also.
796 We also allow combining in this case if all the insns are adjacent
797 because that would leave the two CC0 insns adjacent as well.
798 It would be more logical to test whether CC0 occurs inside I1 or I2,
799 but that would be much slower, and this ought to be equivalent. */
801 p = prev_nonnote_insn (insn);
802 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
807 /* If we get here, we have passed all the tests and the combination is
816 /* LOC is the location within I3 that contains its pattern or the component
817 of a PARALLEL of the pattern. We validate that it is valid for combining.
819 One problem is if I3 modifies its output, as opposed to replacing it
820 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
821 so would produce an insn that is not equivalent to the original insns.
825 (set (reg:DI 101) (reg:DI 100))
826 (set (subreg:SI (reg:DI 101) 0) <foo>)
828 This is NOT equivalent to:
830 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
831 (set (reg:DI 101) (reg:DI 100))])
833 Not only does this modify 100 (in which case it might still be valid
834 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
836 We can also run into a problem if I2 sets a register that I1
837 uses and I1 gets directly substituted into I3 (not via I2). In that
838 case, we would be getting the wrong value of I2DEST into I3, so we
839 must reject the combination. This case occurs when I2 and I1 both
840 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
841 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
842 of a SET must prevent combination from occurring.
844 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
845 if the destination of a SET is a hard register.
847 Before doing the above check, we first try to expand a field assignment
848 into a set of logical operations.
850 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
851 we place a register that is both set and used within I3. If more than one
852 such register is detected, we fail.
854 Return 1 if the combination is valid, zero otherwise. */
857 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
867 if (GET_CODE (x) == SET)
869 rtx set = expand_field_assignment (x);
870 rtx dest = SET_DEST (set);
871 rtx src = SET_SRC (set);
872 rtx inner_dest = dest, inner_src = src;
876 while (GET_CODE (inner_dest) == STRICT_LOW_PART
877 || GET_CODE (inner_dest) == SUBREG
878 || GET_CODE (inner_dest) == ZERO_EXTRACT)
879 inner_dest = XEXP (inner_dest, 0);
881 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
884 while (GET_CODE (inner_src) == STRICT_LOW_PART
885 || GET_CODE (inner_src) == SUBREG
886 || GET_CODE (inner_src) == ZERO_EXTRACT)
887 inner_src = XEXP (inner_src, 0);
889 /* If it is better that two different modes keep two different pseudos,
890 avoid combining them. This avoids producing the following pattern
892 (set (subreg:SI (reg/v:QI 21) 0)
893 (lshiftrt:SI (reg/v:SI 20)
895 If that were made, reload could not handle the pair of
896 reg 20/21, since it would try to get any GENERAL_REGS
897 but some of them don't handle QImode. */
899 if (rtx_equal_p (inner_src, i2dest)
900 && GET_CODE (inner_dest) == REG
901 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
905 /* Check for the case where I3 modifies its output, as
907 if ((inner_dest != dest
908 && (reg_overlap_mentioned_p (i2dest, inner_dest)
909 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
910 /* This is the same test done in can_combine_p. */
911 || (GET_CODE (inner_dest) == REG
912 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
913 #ifndef SMALL_REGISTER_CLASSES
914 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
915 GET_MODE (inner_dest))
919 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
922 /* If DEST is used in I3, it is being killed in this insn,
923 so record that for later. */
924 if (pi3dest_killed && GET_CODE (dest) == REG
925 && reg_referenced_p (dest, PATTERN (i3)))
930 *pi3dest_killed = dest;
934 else if (GET_CODE (x) == PARALLEL)
938 for (i = 0; i < XVECLEN (x, 0); i++)
939 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
940 i1_not_in_src, pi3dest_killed))
947 /* Try to combine the insns I1 and I2 into I3.
948 Here I1 and I2 appear earlier than I3.
949 I1 can be zero; then we combine just I2 into I3.
951 It we are combining three insns and the resulting insn is not recognized,
952 try splitting it into two insns. If that happens, I2 and I3 are retained
953 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
956 If we created two insns, return I2; otherwise return I3.
957 Return 0 if the combination does not work. Then nothing is changed. */
960 try_combine (i3, i2, i1)
961 register rtx i3, i2, i1;
963 /* New patterns for I3 and I3, respectively. */
964 rtx newpat, newi2pat = 0;
965 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
966 int added_sets_1, added_sets_2;
967 /* Total number of SETs to put into I3. */
969 /* Nonzero is I2's body now appears in I3. */
971 /* INSN_CODEs for new I3, new I2, and user of condition code. */
972 int insn_code_number, i2_code_number, other_code_number;
973 /* Contains I3 if the destination of I3 is used in its source, which means
974 that the old life of I3 is being killed. If that usage is placed into
975 I2 and not in I3, a REG_DEAD note must be made. */
976 rtx i3dest_killed = 0;
977 /* SET_DEST and SET_SRC of I2 and I1. */
978 rtx i2dest, i2src, i1dest = 0, i1src = 0;
979 /* PATTERN (I2), or a copy of it in certain cases. */
981 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
982 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
984 /* Notes that must be added to REG_NOTES in I3 and I2. */
985 rtx new_i3_notes, new_i2_notes;
992 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
993 This can occur when flow deletes an insn that it has merged into an
994 auto-increment address. We also can't do anything if I3 has a
995 REG_LIBCALL note since we don't want to disrupt the contiguity of a
998 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
999 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1000 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1001 || find_reg_note (i3, REG_LIBCALL, 0))
1006 undobuf.num_undo = previous_num_undos = 0;
1007 undobuf.other_insn = 0;
1009 /* Save the current high-water-mark so we can free storage if we didn't
1010 accept this combination. */
1011 undobuf.storage = (char *) oballoc (0);
1013 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1014 code below, set I1 to be the earlier of the two insns. */
1015 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1016 temp = i1, i1 = i2, i2 = temp;
1018 /* First check for one important special-case that the code below will
1019 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1020 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1021 we may be able to replace that destination with the destination of I3.
1022 This occurs in the common code where we compute both a quotient and
1023 remainder into a structure, in which case we want to do the computation
1024 directly into the structure to avoid register-register copies.
1026 We make very conservative checks below and only try to handle the
1027 most common cases of this. For example, we only handle the case
1028 where I2 and I3 are adjacent to avoid making difficult register
1031 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1032 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1033 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1034 #ifdef SMALL_REGISTER_CLASSES
1035 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1036 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1038 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1039 && GET_CODE (PATTERN (i2)) == PARALLEL
1040 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1041 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1042 below would need to check what is inside (and reg_overlap_mentioned_p
1043 doesn't support those codes anyway). Don't allow those destinations;
1044 the resulting insn isn't likely to be recognized anyway. */
1045 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1046 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1047 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1048 SET_DEST (PATTERN (i3)))
1049 && next_real_insn (i2) == i3)
1051 rtx p2 = PATTERN (i2);
1053 /* Make sure that the destination of I3,
1054 which we are going to substitute into one output of I2,
1055 is not used within another output of I2. We must avoid making this:
1056 (parallel [(set (mem (reg 69)) ...)
1057 (set (reg 69) ...)])
1058 which is not well-defined as to order of actions.
1059 (Besides, reload can't handle output reloads for this.)
1061 The problem can also happen if the dest of I3 is a memory ref,
1062 if another dest in I2 is an indirect memory ref. */
1063 for (i = 0; i < XVECLEN (p2, 0); i++)
1064 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1065 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1066 SET_DEST (XVECEXP (p2, 0, i))))
1069 if (i == XVECLEN (p2, 0))
1070 for (i = 0; i < XVECLEN (p2, 0); i++)
1071 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1076 subst_low_cuid = INSN_CUID (i2);
1079 i2dest = SET_SRC (PATTERN (i3));
1081 /* Replace the dest in I2 with our dest and make the resulting
1082 insn the new pattern for I3. Then skip to where we
1083 validate the pattern. Everything was set up above. */
1084 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1085 SET_DEST (PATTERN (i3)));
1088 goto validate_replacement;
1093 /* If we have no I1 and I2 looks like:
1094 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1096 make up a dummy I1 that is
1099 (set (reg:CC X) (compare:CC Y (const_int 0)))
1101 (We can ignore any trailing CLOBBERs.)
1103 This undoes a previous combination and allows us to match a branch-and-
1106 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1107 && XVECLEN (PATTERN (i2), 0) >= 2
1108 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1109 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1111 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1112 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1113 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1114 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1115 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1116 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1118 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1119 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1124 /* We make I1 with the same INSN_UID as I2. This gives it
1125 the same INSN_CUID for value tracking. Our fake I1 will
1126 never appear in the insn stream so giving it the same INSN_UID
1127 as I2 will not cause a problem. */
1129 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1130 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1132 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1133 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1134 SET_DEST (PATTERN (i1)));
1139 /* Verify that I2 and I1 are valid for combining. */
1140 if (! can_combine_p (i2, i3, i1, 0, &i2dest, &i2src)
1141 || (i1 && ! can_combine_p (i1, i3, 0, i2, &i1dest, &i1src)))
1147 /* Record whether I2DEST is used in I2SRC and similarly for the other
1148 cases. Knowing this will help in register status updating below. */
1149 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1150 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1151 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1153 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1155 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1157 /* Ensure that I3's pattern can be the destination of combines. */
1158 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1159 i1 && i2dest_in_i1src && i1_feeds_i3,
1166 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1167 We used to do this EXCEPT in one case: I3 has a post-inc in an
1168 output operand. However, that exception can give rise to insns like
1170 which is a famous insn on the PDP-11 where the value of r3 used as the
1171 source was model-dependent. Avoid this sort of thing. */
1174 if (!(GET_CODE (PATTERN (i3)) == SET
1175 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1176 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1177 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1178 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1179 /* It's not the exception. */
1182 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1183 if (REG_NOTE_KIND (link) == REG_INC
1184 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1186 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1193 /* See if the SETs in I1 or I2 need to be kept around in the merged
1194 instruction: whenever the value set there is still needed past I3.
1195 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1197 For the SET in I1, we have two cases: If I1 and I2 independently
1198 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1199 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1200 in I1 needs to be kept around unless I1DEST dies or is set in either
1201 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1202 I1DEST. If so, we know I1 feeds into I2. */
1204 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1207 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1208 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1210 /* If the set in I2 needs to be kept around, we must make a copy of
1211 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1212 PATTERN (I2), we are only substituting for the original I1DEST, not into
1213 an already-substituted copy. This also prevents making self-referential
1214 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1217 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1218 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1222 i2pat = copy_rtx (i2pat);
1226 /* Substitute in the latest insn for the regs set by the earlier ones. */
1228 maxreg = max_reg_num ();
1231 subst_low_cuid = i1 ? INSN_CUID (i1) : INSN_CUID (i2);
1233 /* It is possible that the source of I2 or I1 may be performing an
1234 unneeded operation, such as a ZERO_EXTEND of something that is known
1235 to have the high part zero. Handle that case by letting subst look at
1236 the innermost one of them.
1238 Another way to do this would be to have a function that tries to
1239 simplify a single insn instead of merging two or more insns. We don't
1240 do this because of the potential of infinite loops and because
1241 of the potential extra memory required. However, doing it the way
1242 we are is a bit of a kludge and doesn't catch all cases.
1244 But only do this if -fexpensive-optimizations since it slows things down
1245 and doesn't usually win. */
1247 if (flag_expensive_optimizations)
1249 /* Pass pc_rtx so no substitutions are done, just simplifications.
1250 The cases that we are interested in here do not involve the few
1251 cases were is_replaced is checked. */
1253 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1255 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1257 previous_num_undos = undobuf.num_undo;
1261 /* Many machines that don't use CC0 have insns that can both perform an
1262 arithmetic operation and set the condition code. These operations will
1263 be represented as a PARALLEL with the first element of the vector
1264 being a COMPARE of an arithmetic operation with the constant zero.
1265 The second element of the vector will set some pseudo to the result
1266 of the same arithmetic operation. If we simplify the COMPARE, we won't
1267 match such a pattern and so will generate an extra insn. Here we test
1268 for this case, where both the comparison and the operation result are
1269 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1270 I2SRC. Later we will make the PARALLEL that contains I2. */
1272 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1273 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1274 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1275 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1278 enum machine_mode compare_mode;
1280 newpat = PATTERN (i3);
1281 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1285 #ifdef EXTRA_CC_MODES
1286 /* See if a COMPARE with the operand we substituted in should be done
1287 with the mode that is currently being used. If not, do the same
1288 processing we do in `subst' for a SET; namely, if the destination
1289 is used only once, try to replace it with a register of the proper
1290 mode and also replace the COMPARE. */
1291 if (undobuf.other_insn == 0
1292 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1293 &undobuf.other_insn))
1294 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), i2src))
1295 != GET_MODE (SET_DEST (newpat))))
1297 int regno = REGNO (SET_DEST (newpat));
1298 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1300 if (regno < FIRST_PSEUDO_REGISTER
1301 || (reg_n_sets[regno] == 1 && ! added_sets_2
1302 && ! REG_USERVAR_P (SET_DEST (newpat))))
1304 if (regno >= FIRST_PSEUDO_REGISTER)
1305 SUBST (regno_reg_rtx[regno], new_dest);
1307 SUBST (SET_DEST (newpat), new_dest);
1308 SUBST (XEXP (*cc_use, 0), new_dest);
1309 SUBST (SET_SRC (newpat),
1310 gen_rtx_combine (COMPARE, compare_mode,
1311 i2src, const0_rtx));
1314 undobuf.other_insn = 0;
1321 n_occurrences = 0; /* `subst' counts here */
1323 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1324 need to make a unique copy of I2SRC each time we substitute it
1325 to avoid self-referential rtl. */
1327 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1328 ! i1_feeds_i3 && i1dest_in_i1src);
1329 previous_num_undos = undobuf.num_undo;
1331 /* Record whether i2's body now appears within i3's body. */
1332 i2_is_used = n_occurrences;
1335 /* If we already got a failure, don't try to do more. Otherwise,
1336 try to substitute in I1 if we have it. */
1338 if (i1 && GET_CODE (newpat) != CLOBBER)
1340 /* Before we can do this substitution, we must redo the test done
1341 above (see detailed comments there) that ensures that I1DEST
1342 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1344 if (! combinable_i3pat (0, &newpat, i1dest, 0, 0, 0))
1351 newpat = subst (newpat, i1dest, i1src, 0, 0);
1352 previous_num_undos = undobuf.num_undo;
1355 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1356 to count all the ways that I2SRC and I1SRC can be used. */
1357 if ((FIND_REG_INC_NOTE (i2, 0) != 0
1358 && i2_is_used + added_sets_2 > 1)
1359 || (i1 != 0 && FIND_REG_INC_NOTE (i1, 0) != 0
1360 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1362 /* Fail if we tried to make a new register (we used to abort, but there's
1363 really no reason to). */
1364 || max_reg_num () != maxreg
1365 /* Fail if we couldn't do something and have a CLOBBER. */
1366 || GET_CODE (newpat) == CLOBBER)
1372 /* If the actions of the earlier insns must be kept
1373 in addition to substituting them into the latest one,
1374 we must make a new PARALLEL for the latest insn
1375 to hold additional the SETs. */
1377 if (added_sets_1 || added_sets_2)
1381 if (GET_CODE (newpat) == PARALLEL)
1383 rtvec old = XVEC (newpat, 0);
1384 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1385 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1386 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1387 sizeof (old->elem[0]) * old->num_elem);
1392 total_sets = 1 + added_sets_1 + added_sets_2;
1393 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1394 XVECEXP (newpat, 0, 0) = old;
1398 XVECEXP (newpat, 0, --total_sets)
1399 = (GET_CODE (PATTERN (i1)) == PARALLEL
1400 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1404 /* If there is no I1, use I2's body as is. We used to also not do
1405 the subst call below if I2 was substituted into I3,
1406 but that could lose a simplification. */
1408 XVECEXP (newpat, 0, --total_sets) = i2pat;
1410 /* See comment where i2pat is assigned. */
1411 XVECEXP (newpat, 0, --total_sets)
1412 = subst (i2pat, i1dest, i1src, 0, 0);
1416 /* We come here when we are replacing a destination in I2 with the
1417 destination of I3. */
1418 validate_replacement:
1420 /* Is the result of combination a valid instruction? */
1421 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1423 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1424 the second SET's destination is a register that is unused. In that case,
1425 we just need the first SET. This can occur when simplifying a divmod
1426 insn. We *must* test for this case here because the code below that
1427 splits two independent SETs doesn't handle this case correctly when it
1428 updates the register status. Also check the case where the first
1429 SET's destination is unused. That would not cause incorrect code, but
1430 does cause an unneeded insn to remain. */
1432 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1433 && XVECLEN (newpat, 0) == 2
1434 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1435 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1436 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1437 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1438 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1439 && asm_noperands (newpat) < 0)
1441 newpat = XVECEXP (newpat, 0, 0);
1442 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1445 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1446 && XVECLEN (newpat, 0) == 2
1447 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1448 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1449 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1450 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1451 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1452 && asm_noperands (newpat) < 0)
1454 newpat = XVECEXP (newpat, 0, 1);
1455 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1458 /* If we were combining three insns and the result is a simple SET
1459 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1460 insns. There are two ways to do this. It can be split using a
1461 machine-specific method (like when you have an addition of a large
1462 constant) or by combine in the function find_split_point. */
1464 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1465 && asm_noperands (newpat) < 0)
1467 rtx m_split, *split;
1469 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1470 use I2DEST as a scratch register will help. */
1472 m_split = split_insns (newpat, i3);
1474 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1475 gen_rtvec (2, newpat,
1476 gen_rtx (CLOBBER, VOIDmode,
1480 if (m_split && GET_CODE (m_split) == SEQUENCE
1481 && XVECLEN (m_split, 0) == 2)
1483 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1484 newpat = PATTERN (XVECEXP (m_split, 0, 1));
1486 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1487 if (i2_code_number >= 0)
1488 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1491 /* If we can split it and use I2DEST, go ahead and see if that
1492 helps things be recognized. Verify that none of the registers
1493 are set between I2 and I3. */
1494 else if ((split = find_split_point (&newpat)) != 0
1496 && GET_CODE (i2dest) == REG
1498 /* We need I2DEST in the proper mode. If it is a hard register
1499 or the only use of a pseudo, we can change its mode. */
1500 && (GET_MODE (*split) == GET_MODE (i2dest)
1501 || GET_MODE (*split) == VOIDmode
1502 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1503 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1504 && ! REG_USERVAR_P (i2dest)))
1505 && (next_real_insn (i2) == i3
1506 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1507 /* We can't overwrite I2DEST if its value is still used by
1509 && ! reg_referenced_p (i2dest, newpat))
1511 rtx newdest = i2dest;
1513 /* Get NEWDEST as a register in the proper mode. We have already
1514 validated that we can do this. */
1515 if (GET_MODE (i2dest) != GET_MODE (*split)
1516 && GET_MODE (*split) != VOIDmode)
1518 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1520 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1521 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1524 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1525 an ASHIFT. This can occur if it was inside a PLUS and hence
1526 appeared to be a memory address. This is a kludge. */
1527 if (GET_CODE (*split) == MULT
1528 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1529 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1530 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1532 gen_rtx (CONST_INT, VOIDmode, i)));
1534 #ifdef INSN_SCHEDULING
1535 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1536 be written as a ZERO_EXTEND. */
1537 if (GET_CODE (*split) == SUBREG
1538 && GET_CODE (SUBREG_REG (*split)) == MEM)
1539 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1543 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1544 SUBST (*split, newdest);
1545 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1546 if (i2_code_number >= 0)
1547 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1551 /* Check for a case where we loaded from memory in a narrow mode and
1552 then sign extended it, but we need both registers. In that case,
1553 we have a PARALLEL with both loads from the same memory location.
1554 We can split this into a load from memory followed by a register-register
1555 copy. This saves at least one insn, more if register allocation can
1556 eliminate the copy. */
1558 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1559 && GET_CODE (newpat) == PARALLEL
1560 && XVECLEN (newpat, 0) == 2
1561 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1562 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1563 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1564 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1565 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1566 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1568 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1569 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1570 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1571 SET_SRC (XVECEXP (newpat, 0, 1)))
1572 && ! find_reg_note (i3, REG_UNUSED,
1573 SET_DEST (XVECEXP (newpat, 0, 0))))
1575 newi2pat = XVECEXP (newpat, 0, 0);
1576 newpat = XVECEXP (newpat, 0, 1);
1577 SUBST (SET_SRC (newpat),
1578 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)),
1579 SET_DEST (newi2pat)));
1580 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1581 if (i2_code_number >= 0)
1582 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1584 if (insn_code_number >= 0)
1589 /* If we will be able to accept this, we have made a change to the
1590 destination of I3. This can invalidate a LOG_LINKS pointing
1591 to I3. No other part of combine.c makes such a transformation.
1593 The new I3 will have a destination that was previously the
1594 destination of I1 or I2 and which was used in i2 or I3. Call
1595 distribute_links to make a LOG_LINK from the next use of
1596 that destination. */
1598 PATTERN (i3) = newpat;
1599 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, 0));
1601 /* I3 now uses what used to be its destination and which is
1602 now I2's destination. That means we need a LOG_LINK from
1603 I3 to I2. But we used to have one, so we still will.
1605 However, some later insn might be using I2's dest and have
1606 a LOG_LINK pointing at I3. We must remove this link.
1607 The simplest way to remove the link is to point it at I1,
1608 which we know will be a NOTE. */
1610 for (insn = NEXT_INSN (i3);
1611 insn && GET_CODE (insn) != CODE_LABEL
1612 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1613 insn = NEXT_INSN (insn))
1615 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1616 && reg_referenced_p (SET_DEST (newi2pat), PATTERN (insn)))
1618 for (link = LOG_LINKS (insn); link;
1619 link = XEXP (link, 1))
1620 if (XEXP (link, 0) == i3)
1621 XEXP (link, 0) = i1;
1629 /* Similarly, check for a case where we have a PARALLEL of two independent
1630 SETs but we started with three insns. In this case, we can do the sets
1631 as two separate insns. This case occurs when some SET allows two
1632 other insns to combine, but the destination of that SET is still live. */
1634 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1635 && GET_CODE (newpat) == PARALLEL
1636 && XVECLEN (newpat, 0) == 2
1637 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1638 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1639 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1640 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1641 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1642 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1643 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1645 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1646 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1647 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1648 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1649 XVECEXP (newpat, 0, 0))
1650 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1651 XVECEXP (newpat, 0, 1)))
1653 newi2pat = XVECEXP (newpat, 0, 1);
1654 newpat = XVECEXP (newpat, 0, 0);
1656 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1657 if (i2_code_number >= 0)
1658 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1661 /* If it still isn't recognized, fail and change things back the way they
1663 if ((insn_code_number < 0
1664 /* Is the result a reasonable ASM_OPERANDS? */
1665 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1671 /* If we had to change another insn, make sure it is valid also. */
1672 if (undobuf.other_insn)
1674 rtx other_notes = REG_NOTES (undobuf.other_insn);
1675 rtx other_pat = PATTERN (undobuf.other_insn);
1676 rtx new_other_notes;
1679 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1682 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1688 PATTERN (undobuf.other_insn) = other_pat;
1690 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1691 are still valid. Then add any non-duplicate notes added by
1692 recog_for_combine. */
1693 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1695 next = XEXP (note, 1);
1697 if (REG_NOTE_KIND (note) == REG_UNUSED
1698 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1699 remove_note (undobuf.other_insn, note);
1702 distribute_notes (new_other_notes, undobuf.other_insn,
1703 undobuf.other_insn, 0, 0, 0);
1706 /* We now know that we can do this combination. Merge the insns and
1707 update the status of registers and LOG_LINKS. */
1710 rtx i3notes, i2notes, i1notes = 0;
1711 rtx i3links, i2links, i1links = 0;
1713 int all_adjacent = (next_real_insn (i2) == i3
1714 && (i1 == 0 || next_real_insn (i1) == i2));
1716 /* Compute which registers we expect to eliminate. */
1717 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1719 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1721 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1723 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1724 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1726 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1728 /* Ensure that we do not have something that should not be shared but
1729 occurs multiple times in the new insns. Check this by first
1730 resetting all the `used' flags and then copying anything is shared. */
1732 reset_used_flags (i3notes);
1733 reset_used_flags (i2notes);
1734 reset_used_flags (i1notes);
1735 reset_used_flags (newpat);
1736 reset_used_flags (newi2pat);
1737 if (undobuf.other_insn)
1738 reset_used_flags (PATTERN (undobuf.other_insn));
1740 i3notes = copy_rtx_if_shared (i3notes);
1741 i2notes = copy_rtx_if_shared (i2notes);
1742 i1notes = copy_rtx_if_shared (i1notes);
1743 newpat = copy_rtx_if_shared (newpat);
1744 newi2pat = copy_rtx_if_shared (newi2pat);
1745 if (undobuf.other_insn)
1746 reset_used_flags (PATTERN (undobuf.other_insn));
1748 INSN_CODE (i3) = insn_code_number;
1749 PATTERN (i3) = newpat;
1750 if (undobuf.other_insn)
1751 INSN_CODE (undobuf.other_insn) = other_code_number;
1753 /* We had one special case above where I2 had more than one set and
1754 we replaced a destination of one of those sets with the destination
1755 of I3. In that case, we have to update LOG_LINKS of insns later
1756 in this basic block. Note that this (expensive) case is rare. */
1758 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1759 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1760 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1761 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1762 && ! find_reg_note (i2, REG_UNUSED,
1763 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1767 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1769 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1770 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1771 if (XEXP (link, 0) == i2)
1772 XEXP (link, 0) = i3;
1774 if (GET_CODE (insn) == CODE_LABEL
1775 || GET_CODE (insn) == JUMP_INSN)
1787 INSN_CODE (i2) = i2_code_number;
1788 PATTERN (i2) = newi2pat;
1792 PUT_CODE (i2, NOTE);
1793 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1794 NOTE_SOURCE_FILE (i2) = 0;
1801 PUT_CODE (i1, NOTE);
1802 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1803 NOTE_SOURCE_FILE (i1) = 0;
1806 /* Get death notes for everything that is now used in either I3 or
1807 I2 and used to die in a previous insn. */
1809 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1811 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1813 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1815 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1817 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1819 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1821 distribute_notes (midnotes, 0, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1823 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1824 know these are REG_UNUSED and want them to go to the desired insn,
1825 so we always pass it as i3. */
1826 if (newi2pat && new_i2_notes)
1827 distribute_notes (new_i2_notes, i2, i2, 0, 0, 0);
1829 distribute_notes (new_i3_notes, i3, i3, 0, 0, 0);
1831 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1832 put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */
1834 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, 0),
1835 0, i3, newi2pat ? i2 : 0, 0, 0);
1836 if (i2dest_in_i2src)
1837 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, 0),
1838 0, i3, newi2pat ? i2 : 0, 0, 0);
1839 if (i1dest_in_i1src)
1840 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, 0),
1841 0, i3, newi2pat ? i2 : 0, 0, 0);
1843 distribute_links (i3links);
1844 distribute_links (i2links);
1845 distribute_links (i1links);
1847 if (GET_CODE (i2dest) == REG)
1849 /* The insn that previously set this register doesn't exist, and
1850 this life of the register may not exist either. Show that
1851 we don't know its value any more. If we don't do this and
1852 I2 set the register to a value that depended on its old
1853 contents, we will get confused. If this insn is used, thing
1854 will be set correctly in combine_instructions. */
1855 record_value_for_reg (i2dest, 0, 0);
1857 /* If the reg formerly set in I2 died only once and that was in I3,
1858 zero its use count so it won't make `reload' do any work. */
1859 if (! added_sets_2 && newi2pat == 0)
1861 regno = REGNO (i2dest);
1862 reg_n_sets[regno]--;
1863 if (reg_n_sets[regno] == 0
1864 && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1865 & (1 << (regno % HOST_BITS_PER_INT))))
1866 reg_n_refs[regno] = 0;
1870 if (i1 && GET_CODE (i1dest) == REG)
1872 record_value_for_reg (i1dest, 0, 0);
1873 regno = REGNO (i1dest);
1876 reg_n_sets[regno]--;
1877 if (reg_n_sets[regno] == 0
1878 && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1879 & (1 << (regno % HOST_BITS_PER_INT))))
1880 reg_n_refs[regno] = 0;
1884 /* If I3 is now an unconditional jump, ensure that it has a
1885 BARRIER following it since it may have initially been a
1886 conditional jump. */
1888 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
1889 && GET_CODE (next_nonnote_insn (i3)) != BARRIER)
1890 emit_barrier_after (i3);
1893 combine_successes++;
1895 return newi2pat ? i2 : i3;
1898 /* Undo all the modifications recorded in undobuf. */
1904 if (undobuf.num_undo > MAX_UNDO)
1905 undobuf.num_undo = MAX_UNDO;
1906 for (i = undobuf.num_undo - 1; i >= 0; i--)
1907 *undobuf.undo[i].where = undobuf.undo[i].old_contents;
1909 obfree (undobuf.storage);
1910 undobuf.num_undo = 0;
1913 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1914 where we have an arithmetic expression and return that point.
1916 try_combine will call this function to see if an insn can be split into
1920 find_split_point (loc)
1924 enum rtx_code code = GET_CODE (x);
1926 int len = 0, pos, unsignedp;
1929 /* First special-case some codes. */
1933 #ifdef INSN_SCHEDULING
1934 /* If we are making a paradoxical SUBREG invalid, it becomes a split
1936 if (GET_CODE (SUBREG_REG (x)) == MEM)
1939 return find_split_point (&SUBREG_REG (x));
1943 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
1944 using LO_SUM and HIGH. */
1945 if (GET_CODE (XEXP (x, 0)) == CONST
1946 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1949 gen_rtx_combine (LO_SUM, Pmode,
1950 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
1952 return &XEXP (XEXP (x, 0), 0);
1956 /* If we have a PLUS whose second operand is a constant and the
1957 address is not valid, perhaps will can split it up using
1958 the machine-specific way to split large constants. We use
1959 the first psuedo-reg (one of the virtual regs) as a placeholder;
1960 it will not remain in the result. */
1961 if (GET_CODE (XEXP (x, 0)) == PLUS
1962 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1963 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
1965 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
1966 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
1969 /* This should have produced two insns, each of which sets our
1970 placeholder. If the source of the second is a valid address,
1971 we can make put both sources together and make a split point
1974 if (seq && XVECLEN (seq, 0) == 2
1975 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
1976 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
1977 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
1978 && ! reg_mentioned_p (reg,
1979 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
1980 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
1981 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
1982 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
1983 && memory_address_p (GET_MODE (x),
1984 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
1986 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
1987 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
1989 /* Replace the placeholder in SRC2 with SRC1. If we can
1990 find where in SRC2 it was placed, that can become our
1991 split point and we can replace this address with SRC2.
1992 Just try two obvious places. */
1994 src2 = replace_rtx (src2, reg, src1);
1996 if (XEXP (src2, 0) == src1)
1997 split = &XEXP (src2, 0);
1998 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
1999 && XEXP (XEXP (src2, 0), 0) == src1)
2000 split = &XEXP (XEXP (src2, 0), 0);
2004 SUBST (XEXP (x, 0), src2);
2013 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2014 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2015 we need to put the operand into a register. So split at that
2018 if (SET_DEST (x) == cc0_rtx
2019 && GET_CODE (SET_SRC (x)) != COMPARE
2020 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2021 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2022 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2023 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2024 return &SET_SRC (x);
2027 /* See if we can split SET_SRC as it stands. */
2028 split = find_split_point (&SET_SRC (x));
2029 if (split && split != &SET_SRC (x))
2032 /* See if this is a bitfield assignment with everything constant. If
2033 so, this is an IOR of an AND, so split it into that. */
2034 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2035 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2036 <= HOST_BITS_PER_INT)
2037 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2038 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2039 && GET_CODE (SET_SRC (x)) == CONST_INT
2040 && ((INTVAL (XEXP (SET_DEST (x), 1))
2041 + INTVAL (XEXP (SET_DEST (x), 2)))
2042 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2043 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2045 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2046 int len = INTVAL (XEXP (SET_DEST (x), 1));
2047 int src = INTVAL (SET_SRC (x));
2048 rtx dest = XEXP (SET_DEST (x), 0);
2049 enum machine_mode mode = GET_MODE (dest);
2050 unsigned int mask = (1 << len) - 1;
2053 pos = GET_MODE_BITSIZE (mode) - len - pos;
2058 gen_binary (IOR, mode, dest,
2059 gen_rtx (CONST_INT, VOIDmode, src << pos)));
2062 gen_binary (IOR, mode,
2063 gen_binary (AND, mode, dest,
2064 gen_rtx (CONST_INT, VOIDmode,
2066 & GET_MODE_MASK (mode)))),
2067 gen_rtx (CONST_INT, VOIDmode, src << pos)));
2069 SUBST (SET_DEST (x), dest);
2071 split = find_split_point (&SET_SRC (x));
2072 if (split && split != &SET_SRC (x))
2076 /* Otherwise, see if this is an operation that we can split into two.
2077 If so, try to split that. */
2078 code = GET_CODE (SET_SRC (x));
2083 inner = XEXP (SET_SRC (x), 0);
2085 len = GET_MODE_BITSIZE (GET_MODE (inner));
2091 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2092 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2094 inner = XEXP (SET_SRC (x), 0);
2095 len = INTVAL (XEXP (SET_SRC (x), 1));
2096 pos = INTVAL (XEXP (SET_SRC (x), 2));
2099 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2101 unsignedp = (code == ZERO_EXTRACT);
2106 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2108 enum machine_mode mode = GET_MODE (SET_SRC (x));
2110 if (unsignedp && len < HOST_BITS_PER_INT)
2115 gen_rtx_combine (LSHIFTRT, mode,
2116 gen_lowpart_for_combine (mode, inner),
2117 gen_rtx (CONST_INT, VOIDmode, pos)),
2118 gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1)));
2120 split = find_split_point (&SET_SRC (x));
2121 if (split && split != &SET_SRC (x))
2129 gen_rtx_combine (ASHIFT, mode,
2130 gen_lowpart_for_combine (mode, inner),
2131 gen_rtx (CONST_INT, VOIDmode,
2132 (GET_MODE_BITSIZE (mode)
2134 gen_rtx (CONST_INT, VOIDmode,
2135 GET_MODE_BITSIZE (mode) - len)));
2137 split = find_split_point (&SET_SRC (x));
2138 if (split && split != &SET_SRC (x))
2143 /* See if this is a simple operation with a constant as the second
2144 operand. It might be that this constant is out of range and hence
2145 could be used as a split point. */
2146 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2147 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2148 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2149 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2150 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2151 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2152 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2154 return &XEXP (SET_SRC (x), 1);
2156 /* Finally, see if this is a simple operation with its first operand
2157 not in a register. The operation might require this operand in a
2158 register, so return it as a split point. We can always do this
2159 because if the first operand were another operation, we would have
2160 already found it as a split point. */
2161 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2162 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2163 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2165 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2166 return &XEXP (SET_SRC (x), 0);
2172 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2173 it is better to write this as (not (ior A B)) so we can split it.
2174 Similarly for IOR. */
2175 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2178 gen_rtx_combine (NOT, GET_MODE (x),
2179 gen_rtx_combine (code == IOR ? AND : IOR,
2181 XEXP (XEXP (x, 0), 0),
2182 XEXP (XEXP (x, 1), 0))));
2183 return find_split_point (loc);
2186 /* Many RISC machines have a large set of logical insns. If the
2187 second operand is a NOT, put it first so we will try to split the
2188 other operand first. */
2189 if (GET_CODE (XEXP (x, 1)) == NOT)
2191 rtx tem = XEXP (x, 0);
2192 SUBST (XEXP (x, 0), XEXP (x, 1));
2193 SUBST (XEXP (x, 1), tem);
2198 /* Otherwise, select our actions depending on our rtx class. */
2199 switch (GET_RTX_CLASS (code))
2201 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2203 split = find_split_point (&XEXP (x, 2));
2206 /* ... fall through ... */
2210 split = find_split_point (&XEXP (x, 1));
2213 /* ... fall through ... */
2215 /* Some machines have (and (shift ...) ...) insns. If X is not
2216 an AND, but XEXP (X, 0) is, use it as our split point. */
2217 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2218 return &XEXP (x, 0);
2220 split = find_split_point (&XEXP (x, 0));
2226 /* Otherwise, we don't have a split point. */
2230 /* Throughout X, replace FROM with TO, and return the result.
2231 The result is TO if X is FROM;
2232 otherwise the result is X, but its contents may have been modified.
2233 If they were modified, a record was made in undobuf so that
2234 undo_all will (among other things) return X to its original state.
2236 If the number of changes necessary is too much to record to undo,
2237 the excess changes are not made, so the result is invalid.
2238 The changes already made can still be undone.
2239 undobuf.num_undo is incremented for such changes, so by testing that
2240 the caller can tell whether the result is valid.
2242 `n_occurrences' is incremented each time FROM is replaced.
2244 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2246 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2247 by copying if `n_occurrences' is non-zero. */
2250 subst (x, from, to, in_dest, unique_copy)
2251 register rtx x, from, to;
2256 register int len, i;
2257 register enum rtx_code code = GET_CODE (x), orig_code = code;
2259 enum machine_mode mode = GET_MODE (x);
2260 enum machine_mode op0_mode = VOIDmode;
2265 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2266 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2267 If it is 0, that cannot be done. We can now do this for any MEM
2268 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2269 If not for that, MEM's would very rarely be safe. */
2271 /* Reject MODEs bigger than a word, because we might not be able
2272 to reference a two-register group starting with an arbitrary register
2273 (and currently gen_lowpart might crash for a SUBREG). */
2275 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2276 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2278 /* Two expressions are equal if they are identical copies of a shared
2279 RTX or if they are both registers with the same register number
2282 #define COMBINE_RTX_EQUAL_P(X,Y) \
2284 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2285 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2287 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2290 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2293 /* If X and FROM are the same register but different modes, they will
2294 not have been seen as equal above. However, flow.c will make a
2295 LOG_LINKS entry for that case. If we do nothing, we will try to
2296 rerecognize our original insn and, when it succeeds, we will
2297 delete the feeding insn, which is incorrect.
2299 So force this insn not to match in this (rare) case. */
2300 if (! in_dest && code == REG && GET_CODE (from) == REG
2301 && REGNO (x) == REGNO (from))
2302 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2304 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2305 of which may contain things that can be combined. */
2306 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2309 /* It is possible to have a subexpression appear twice in the insn.
2310 Suppose that FROM is a register that appears within TO.
2311 Then, after that subexpression has been scanned once by `subst',
2312 the second time it is scanned, TO may be found. If we were
2313 to scan TO here, we would find FROM within it and create a
2314 self-referent rtl structure which is completely wrong. */
2315 if (COMBINE_RTX_EQUAL_P (x, to))
2318 len = GET_RTX_LENGTH (code);
2319 fmt = GET_RTX_FORMAT (code);
2321 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2322 set up to skip this common case. All other cases where we want to
2323 suppress replacing something inside a SET_SRC are handled via the
2326 && (GET_CODE (SET_DEST (x)) == REG
2327 || GET_CODE (SET_DEST (x)) == CC0
2328 || GET_CODE (SET_DEST (x)) == PC))
2331 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2333 op0_mode = GET_MODE (XEXP (x, 0));
2335 for (i = 0; i < len; i++)
2340 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2343 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2345 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2350 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2352 /* If this substitution failed, this whole thing fails. */
2353 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2357 SUBST (XVECEXP (x, i, j), new);
2360 else if (fmt[i] == 'e')
2364 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2366 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2370 /* If we are in a SET_DEST, suppress most cases unless we
2371 have gone inside a MEM, in which case we want to
2372 simplify the address. We assume here that things that
2373 are actually part of the destination have their inner
2374 parts in the first expression. This is true for SUBREG,
2375 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2376 things aside from REG and MEM that should appear in a
2378 new = subst (XEXP (x, i), from, to,
2380 && (code == SUBREG || code == STRICT_LOW_PART
2381 || code == ZERO_EXTRACT))
2383 && i == 0), unique_copy);
2385 /* If we found that we will have to reject this combination,
2386 indicate that by returning the CLOBBER ourselves, rather than
2387 an expression containing it. This will speed things up as
2388 well as prevent accidents where two CLOBBERs are considered
2389 to be equal, thus producing an incorrect simplification. */
2391 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2394 SUBST (XEXP (x, i), new);
2398 /* If this is a commutative operation, put a constant last and a complex
2399 expression first. We don't need to do this for comparisons here. */
2400 if (GET_RTX_CLASS (code) == 'c'
2401 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2402 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2403 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2404 || (GET_CODE (XEXP (x, 0)) == SUBREG
2405 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2406 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2409 SUBST (XEXP (x, 0), XEXP (x, 1));
2410 SUBST (XEXP (x, 1), temp);
2413 /* Try to fold this expression in case we have constants that weren't
2416 switch (GET_RTX_CLASS (code))
2419 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2422 temp = simplify_relational_operation (code, op0_mode,
2423 XEXP (x, 0), XEXP (x, 1));
2427 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2431 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2432 XEXP (x, 1), XEXP (x, 2));
2439 /* We come back to here if we have replaced the expression with one of
2440 a different code and it is likely that further simplification will be
2445 /* If we have restarted more than 4 times, we are probably looping, so
2447 if (++n_restarts > 4)
2450 code = GET_CODE (x);
2452 /* First see if we can apply the inverse distributive law. */
2453 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2455 x = apply_distributive_law (x);
2456 code = GET_CODE (x);
2459 /* If CODE is an associative operation not otherwise handled, see if we
2460 can associate some operands. This can win if they are constants or
2461 if they are logically related (i.e. (a & b) & a. */
2462 if ((code == PLUS || code == MINUS
2463 || code == MULT || code == AND || code == IOR || code == XOR
2464 || code == DIV || code == UDIV
2465 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2466 && GET_MODE_CLASS (mode) == MODE_INT)
2468 if (GET_CODE (XEXP (x, 0)) == code)
2470 rtx other = XEXP (XEXP (x, 0), 0);
2471 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2472 rtx inner_op1 = XEXP (x, 1);
2475 /* Make sure we pass the constant operand if any as the second
2476 one if this is a commutative operation. */
2477 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2479 rtx tem = inner_op0;
2480 inner_op0 = inner_op1;
2483 inner = simplify_binary_operation (code == MINUS ? PLUS
2484 : code == DIV ? MULT
2485 : code == UDIV ? MULT
2487 mode, inner_op0, inner_op1);
2489 /* For commutative operations, try the other pair if that one
2491 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2493 other = XEXP (XEXP (x, 0), 1);
2494 inner = simplify_binary_operation (code, mode,
2495 XEXP (XEXP (x, 0), 0),
2501 x = gen_binary (code, mode, other, inner);
2508 /* A little bit of algebraic simplification here. */
2512 /* Ensure that our address has any ASHIFTs converted to MULT in case
2513 address-recognizing predicates are called later. */
2514 temp = make_compound_operation (XEXP (x, 0), MEM);
2515 SUBST (XEXP (x, 0), temp);
2519 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2520 is paradoxical. If we can't do that safely, then it becomes
2521 something nonsensical so that this combination won't take place. */
2523 if (GET_CODE (SUBREG_REG (x)) == MEM
2524 && (GET_MODE_SIZE (mode)
2525 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2527 rtx inner = SUBREG_REG (x);
2528 int endian_offset = 0;
2529 /* Don't change the mode of the MEM
2530 if that would change the meaning of the address. */
2531 if (MEM_VOLATILE_P (SUBREG_REG (x))
2532 || mode_dependent_address_p (XEXP (inner, 0)))
2533 return gen_rtx (CLOBBER, mode, const0_rtx);
2535 #if BYTES_BIG_ENDIAN
2536 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2537 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2538 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2539 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2541 /* Note if the plus_constant doesn't make a valid address
2542 then this combination won't be accepted. */
2543 x = gen_rtx (MEM, mode,
2544 plus_constant (XEXP (inner, 0),
2545 (SUBREG_WORD (x) * UNITS_PER_WORD
2547 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2548 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2549 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2553 /* If we are in a SET_DEST, these other cases can't apply. */
2557 /* Changing mode twice with SUBREG => just change it once,
2558 or not at all if changing back to starting mode. */
2559 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2561 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2562 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2563 return SUBREG_REG (SUBREG_REG (x));
2565 SUBST_INT (SUBREG_WORD (x),
2566 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2567 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2570 /* SUBREG of a hard register => just change the register number
2571 and/or mode. If the hard register is not valid in that mode,
2572 suppress this combination. */
2574 if (GET_CODE (SUBREG_REG (x)) == REG
2575 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
2577 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2579 return gen_rtx (REG, mode,
2580 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2582 return gen_rtx (CLOBBER, mode, const0_rtx);
2585 /* For a constant, try to pick up the part we want. Handle a full
2586 word and low-order part. Only do this if we are narrowing
2587 the constant; if it is being widened, we have no idea what
2588 the extra bits will have been set to. */
2590 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2591 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2592 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
2593 && GET_MODE_CLASS (mode) == MODE_INT)
2595 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2601 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2602 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
2603 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2605 /* If we are narrowing the object, we need to see if we can simplify
2606 the expression for the object knowing that we only need the
2607 low-order bits. We do this by computing an AND of the object
2608 with only the bits we care about. That will produce any needed
2609 simplifications. If the resulting computation is just the
2610 AND with the significant bits, our operand is the first operand
2611 of the AND. Otherwise, it is the resulting expression. */
2612 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2613 && subreg_lowpart_p (x)
2614 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
2616 temp = simplify_and_const_int (0, GET_MODE (SUBREG_REG (x)),
2617 SUBREG_REG (x), GET_MODE_MASK (mode));
2618 if (GET_CODE (temp) == AND && GET_CODE (XEXP (temp, 1)) == CONST_INT
2619 && INTVAL (XEXP (temp, 1)) == GET_MODE_MASK (mode))
2620 temp = XEXP (temp, 0);
2621 return gen_lowpart_for_combine (mode, temp);
2627 /* (not (plus X -1)) can become (neg X). */
2628 if (GET_CODE (XEXP (x, 0)) == PLUS
2629 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2631 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2635 /* Similarly, (not (neg X)) is (plus X -1). */
2636 if (GET_CODE (XEXP (x, 0)) == NEG)
2638 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2642 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2643 other than 1, but that is not valid. We could do a similar
2644 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2645 but this doesn't seem common enough to bother with. */
2646 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2647 && XEXP (XEXP (x, 0), 0) == const1_rtx)
2649 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
2650 XEXP (XEXP (x, 0), 1));
2654 if (GET_CODE (XEXP (x, 0)) == SUBREG
2655 && subreg_lowpart_p (XEXP (x, 0))
2656 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
2657 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
2658 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
2659 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
2661 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
2663 x = gen_rtx (ROTATE, inner_mode,
2664 gen_unary (NOT, inner_mode, const1_rtx),
2665 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
2666 x = gen_lowpart_for_combine (mode, x);
2670 #if STORE_FLAG_VALUE == -1
2671 /* (not (comparison foo bar)) can be done by reversing the comparison
2673 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
2674 && reversible_comparison_p (XEXP (x, 0)))
2675 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
2676 mode, XEXP (XEXP (x, 0), 0),
2677 XEXP (XEXP (x, 0), 1));
2680 /* Apply De Morgan's laws to reduce number of patterns for machines
2681 with negating logical insns (and-not, nand, etc.). If result has
2682 only one NOT, put it first, since that is how the patterns are
2685 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
2687 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
2689 if (GET_CODE (in1) == NOT)
2690 in1 = XEXP (in1, 0);
2692 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
2694 if (GET_CODE (in2) == NOT)
2695 in2 = XEXP (in2, 0);
2696 else if (GET_CODE (in2) == CONST_INT
2697 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
2698 in2 = gen_rtx (CONST_INT, VOIDmode,
2699 GET_MODE_MASK (mode) & ~ INTVAL (in2));
2701 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
2703 if (GET_CODE (in2) == NOT)
2706 in2 = in1; in1 = tem;
2709 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
2716 /* (neg (plus X 1)) can become (not X). */
2717 if (GET_CODE (XEXP (x, 0)) == PLUS
2718 && XEXP (XEXP (x, 0), 1) == const1_rtx)
2720 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
2724 /* Similarly, (neg (not X)) is (plus X 1). */
2725 if (GET_CODE (XEXP (x, 0)) == NOT)
2727 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
2731 /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */
2732 if (GET_CODE (XEXP (x, 0)) == ABS
2733 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTRACT
2734 && XEXP (XEXP (XEXP (x, 0), 0), 1) == const1_rtx)
2735 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFTRT
2736 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2737 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2738 == GET_MODE_BITSIZE (mode) - 1))
2739 || ((temp = get_last_value (XEXP (XEXP (x, 0), 0))) != 0
2740 && ((GET_CODE (temp) == SIGN_EXTRACT
2741 && XEXP (temp, 1) == const1_rtx)
2742 || (GET_CODE (temp) == ASHIFTRT
2743 && GET_CODE (XEXP (temp, 1)) == CONST_INT
2744 && (INTVAL (XEXP (temp, 1))
2745 == GET_MODE_BITSIZE (mode) - 1))))))
2746 return XEXP (XEXP (x, 0), 0);
2748 /* (neg (minus X Y)) can become (minus Y X). */
2749 if (GET_CODE (XEXP (x, 0)) == MINUS
2750 && (GET_MODE_CLASS (mode) != MODE_FLOAT
2751 /* x-y != -(y-x) with IEEE floating point. */
2752 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
2754 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
2755 XEXP (XEXP (x, 0), 0));
2759 /* NEG commutes with ASHIFT since it is multiplication. Only do this
2760 if we can then eliminate the NEG (e.g.,
2761 if the operand is a constant). */
2763 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
2765 temp = simplify_unary_operation (NEG, mode,
2766 XEXP (XEXP (x, 0), 0), mode);
2769 SUBST (XEXP (XEXP (x, 0), 0), temp);
2774 temp = expand_compound_operation (XEXP (x, 0));
2776 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
2777 replaced by (lshiftrt X C). This will convert
2778 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
2780 if (GET_CODE (temp) == ASHIFTRT
2781 && GET_CODE (XEXP (temp, 1)) == CONST_INT
2782 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
2784 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
2785 INTVAL (XEXP (temp, 1)));
2789 /* If X has only a single bit significant, say, bit I, convert
2790 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
2791 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
2792 (sign_extract X 1 Y). But only do this if TEMP isn't a register
2793 or a SUBREG of one since we'd be making the expression more
2794 complex if it was just a register. */
2796 if (GET_CODE (temp) != REG
2797 && ! (GET_CODE (temp) == SUBREG
2798 && GET_CODE (SUBREG_REG (temp)) == REG)
2799 && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
2801 rtx temp1 = simplify_shift_const
2803 simplify_shift_const (0, ASHIFT, mode, temp,
2804 GET_MODE_BITSIZE (mode) - 1 - i),
2805 GET_MODE_BITSIZE (mode) - 1 - i);
2807 /* If all we did was surround TEMP with the two shifts, we
2808 haven't improved anything, so don't use it. Otherwise,
2809 we are better off with TEMP1. */
2810 if (GET_CODE (temp1) != ASHIFTRT
2811 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
2812 || XEXP (XEXP (temp1, 0), 0) != temp)
2820 case FLOAT_TRUNCATE:
2821 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
2822 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
2823 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
2824 return XEXP (XEXP (x, 0), 0);
2829 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
2830 using cc0, in which case we want to leave it as a COMPARE
2831 so we can distinguish it from a register-register-copy. */
2832 if (XEXP (x, 1) == const0_rtx)
2835 /* In IEEE floating point, x-0 is not the same as x. */
2836 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
2837 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
2838 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
2844 /* (const (const X)) can become (const X). Do it this way rather than
2845 returning the inner CONST since CONST can be shared with a
2847 if (GET_CODE (XEXP (x, 0)) == CONST)
2848 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
2853 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
2854 can add in an offset. find_split_point will split this address up
2855 again if it doesn't match. */
2856 if (GET_CODE (XEXP (x, 0)) == HIGH
2857 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
2863 /* If we have (plus (plus (A const) B)), associate it so that CONST is
2864 outermost. That's because that's the way indexed addresses are
2865 supposed to appear. This code used to check many more cases, but
2866 they are now checked elsewhere. */
2867 if (GET_CODE (XEXP (x, 0)) == PLUS
2868 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
2869 return gen_binary (PLUS, mode,
2870 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
2872 XEXP (XEXP (x, 0), 1));
2874 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
2875 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
2876 bit-field and can be replaced by either a sign_extend or a
2877 sign_extract. The `and' may be a zero_extend. */
2878 if (GET_CODE (XEXP (x, 0)) == XOR
2879 && GET_CODE (XEXP (x, 1)) == CONST_INT
2880 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2881 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
2882 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
2883 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2884 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
2885 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2886 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2887 == (1 << (i + 1)) - 1))
2888 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
2889 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
2892 x = simplify_shift_const
2894 simplify_shift_const (0, ASHIFT, mode,
2895 XEXP (XEXP (XEXP (x, 0), 0), 0),
2896 GET_MODE_BITSIZE (mode) - (i + 1)),
2897 GET_MODE_BITSIZE (mode) - (i + 1));
2901 /* If only the low-order bit of X is significant, (plus x -1)
2902 can become (ashiftrt (ashift (xor x 1) C) C) where C is
2903 the bitsize of the mode - 1. This allows simplification of
2904 "a = (b & 8) == 0;" */
2905 if (XEXP (x, 1) == constm1_rtx
2906 && GET_CODE (XEXP (x, 0)) != REG
2907 && ! (GET_CODE (XEXP (x,0)) == SUBREG
2908 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
2909 && significant_bits (XEXP (x, 0), mode) == 1)
2911 x = simplify_shift_const
2913 simplify_shift_const (0, ASHIFT, mode,
2914 gen_rtx_combine (XOR, mode,
2915 XEXP (x, 0), const1_rtx),
2916 GET_MODE_BITSIZE (mode) - 1),
2917 GET_MODE_BITSIZE (mode) - 1);
2923 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
2924 (and <foo> (const_int pow2-1)) */
2925 if (GET_CODE (XEXP (x, 1)) == AND
2926 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2927 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
2928 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2930 x = simplify_and_const_int (0, mode, XEXP (x, 0),
2931 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
2937 /* If we have (mult (plus A B) C), apply the distributive law and then
2938 the inverse distributive law to see if things simplify. This
2939 occurs mostly in addresses, often when unrolling loops. */
2941 if (GET_CODE (XEXP (x, 0)) == PLUS)
2943 x = apply_distributive_law
2944 (gen_binary (PLUS, mode,
2945 gen_binary (MULT, mode,
2946 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
2947 gen_binary (MULT, mode,
2948 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
2950 if (GET_CODE (x) != MULT)
2954 /* If this is multiplication by a power of two and its first operand is
2955 a shift, treat the multiply as a shift to allow the shifts to
2956 possibly combine. */
2957 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2958 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
2959 && (GET_CODE (XEXP (x, 0)) == ASHIFT
2960 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
2961 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
2962 || GET_CODE (XEXP (x, 0)) == ROTATE
2963 || GET_CODE (XEXP (x, 0)) == ROTATERT))
2965 x = simplify_shift_const (0, ASHIFT, mode, XEXP (x, 0), i);
2969 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
2970 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2971 && XEXP (XEXP (x, 0), 0) == const1_rtx)
2972 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
2973 XEXP (XEXP (x, 0), 1));
2977 /* If this is a divide by a power of two, treat it as a shift if
2978 its first operand is a shift. */
2979 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2980 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
2981 && (GET_CODE (XEXP (x, 0)) == ASHIFT
2982 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
2983 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
2984 || GET_CODE (XEXP (x, 0)) == ROTATE
2985 || GET_CODE (XEXP (x, 0)) == ROTATERT))
2987 x = simplify_shift_const (0, LSHIFTRT, mode, XEXP (x, 0), i);
2993 case GT: case GTU: case GE: case GEU:
2994 case LT: case LTU: case LE: case LEU:
2995 /* If the first operand is a condition code, we can't do anything
2997 if (GET_CODE (XEXP (x, 0)) == COMPARE
2998 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3000 && XEXP (x, 0) != cc0_rtx
3004 rtx op0 = XEXP (x, 0);
3005 rtx op1 = XEXP (x, 1);
3006 enum rtx_code new_code;
3008 if (GET_CODE (op0) == COMPARE)
3009 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3011 /* Simplify our comparison, if possible. */
3012 new_code = simplify_comparison (code, &op0, &op1);
3014 #if STORE_FLAG_VALUE == 1
3015 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3016 if only the low-order bit is significant in X (such as when
3017 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3019 if (new_code == NE && mode != VOIDmode
3020 && op1 == const0_rtx
3021 && significant_bits (op0, GET_MODE (op0)) == 1)
3022 return gen_lowpart_for_combine (mode, op0);
3023 else if (new_code == EQ && mode != VOIDmode
3024 && op1 == const0_rtx
3025 && significant_bits (op0, GET_MODE (op0)) == 1)
3026 return gen_rtx_combine (XOR, mode,
3027 gen_lowpart_for_combine (mode, op0),
3031 #if STORE_FLAG_VALUE == -1
3032 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3033 to (neg x) if only the low-order bit of X is significant.
3034 This converts (ne (zero_extract X 1 Y) 0) to
3035 (sign_extract X 1 Y). */
3036 if (new_code == NE && mode != VOIDmode
3037 && op1 == const0_rtx
3038 && significant_bits (op0, GET_MODE (op0)) == 1)
3040 x = gen_rtx_combine (NEG, mode,
3041 gen_lowpart_for_combine (mode, op0));
3046 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3047 one significant bit, we can convert (ne x 0) to (ashift x c)
3048 where C puts the bit in the sign bit. Remove any AND with
3049 STORE_FLAG_VALUE when we are done, since we are only going to
3050 test the sign bit. */
3051 if (new_code == NE && mode != VOIDmode
3052 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3053 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3054 && op1 == const0_rtx
3055 && mode == GET_MODE (op0)
3056 && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
3058 x = simplify_shift_const (0, ASHIFT, mode, op0,
3059 GET_MODE_BITSIZE (mode) - 1 - i);
3060 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3066 /* If the code changed, return a whole new comparison. */
3067 if (new_code != code)
3068 return gen_rtx_combine (new_code, mode, op0, op1);
3070 /* Otherwise, keep this operation, but maybe change its operands.
3071 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3072 SUBST (XEXP (x, 0), op0);
3073 SUBST (XEXP (x, 1), op1);
3078 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3079 reversed, do so to avoid needing two sets of patterns for
3080 subtract-and-branch insns. */
3081 if (XEXP (x, 1) == pc_rtx && reversible_comparison_p (XEXP (x, 0)))
3084 gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3085 GET_MODE (XEXP (x, 0)),
3086 XEXP (XEXP (x, 0), 0),
3087 XEXP (XEXP (x, 0), 1)));
3088 SUBST (XEXP (x, 1), XEXP (x, 2));
3089 SUBST (XEXP (x, 2), pc_rtx);
3097 /* If we are processing SET_DEST, we are done. */
3101 x = expand_compound_operation (x);
3102 if (GET_CODE (x) != code)
3107 /* (set (pc) (return)) gets written as (return). */
3108 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3111 /* Convert this into a field assignment operation, if possible. */
3112 x = make_field_assignment (x);
3114 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3115 operation, and X being a REG or (subreg (reg)), we may be able to
3116 convert this to (set (subreg:m2 x) (op)).
3118 We can always do this if M1 is narrower than M2 because that
3119 means that we only care about the low bits of the result.
3121 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3122 not defined), we cannot perform a narrower operation that
3123 requested since the high-order bits will be undefined. On
3124 machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this
3125 transformation is safe as long as M1 and M2 have the same number
3128 if (GET_CODE (SET_SRC (x)) == SUBREG
3129 && subreg_lowpart_p (SET_SRC (x))
3130 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3131 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3133 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3134 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3135 #ifndef BYTE_LOADS_ZERO_EXTEND
3136 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3137 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3139 && (GET_CODE (SET_DEST (x)) == REG
3140 || (GET_CODE (SET_DEST (x)) == SUBREG
3141 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3143 /* Get the object that will be the SUBREG_REG of the
3144 SUBREG we are making. Note that SUBREG_WORD will always
3145 be zero because this will either be a paradoxical SUBREG
3146 or a SUBREG with the same number of words on the outside and
3148 rtx object = (GET_CODE (SET_DEST (x)) == REG ? SET_DEST (x)
3149 : SUBREG_REG (SET_DEST (x)));
3151 SUBST (SET_DEST (x),
3152 gen_rtx (SUBREG, GET_MODE (SUBREG_REG (SET_SRC (x))),
3154 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3157 /* If we are setting CC0 or if the source is a COMPARE, look for the
3158 use of the comparison result and try to simplify it unless we already
3159 have used undobuf.other_insn. */
3160 if ((GET_CODE (SET_SRC (x)) == COMPARE
3162 || SET_DEST (x) == cc0_rtx
3165 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3167 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3168 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3169 && XEXP (*cc_use, 0) == SET_DEST (x))
3171 enum rtx_code old_code = GET_CODE (*cc_use);
3172 enum rtx_code new_code;
3174 int other_changed = 0;
3175 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3177 if (GET_CODE (SET_SRC (x)) == COMPARE)
3178 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3180 op0 = SET_SRC (x), op1 = const0_rtx;
3182 /* Simplify our comparison, if possible. */
3183 new_code = simplify_comparison (old_code, &op0, &op1);
3185 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3186 /* If this machine has CC modes other than CCmode, check to see
3187 if we need to use a different CC mode here. */
3188 compare_mode = SELECT_CC_MODE (new_code, op0);
3190 /* If the mode changed, we have to change SET_DEST, the mode
3191 in the compare, and the mode in the place SET_DEST is used.
3192 If SET_DEST is a hard register, just build new versions with
3193 the proper mode. If it is a pseudo, we lose unless it is only
3194 time we set the pseudo, in which case we can safely change
3196 if (compare_mode != GET_MODE (SET_DEST (x)))
3198 int regno = REGNO (SET_DEST (x));
3199 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3201 if (regno < FIRST_PSEUDO_REGISTER
3202 || (reg_n_sets[regno] == 1
3203 && ! REG_USERVAR_P (SET_DEST (x))))
3205 if (regno >= FIRST_PSEUDO_REGISTER)
3206 SUBST (regno_reg_rtx[regno], new_dest);
3208 SUBST (SET_DEST (x), new_dest);
3209 SUBST (XEXP (*cc_use, 0), new_dest);
3215 /* If the code changed, we have to build a new comparison
3216 in undobuf.other_insn. */
3217 if (new_code != old_code)
3221 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3222 SET_DEST (x), const0_rtx));
3224 /* If the only change we made was to change an EQ into an
3225 NE or vice versa, OP0 has only one significant bit,
3226 and OP1 is zero, check if changing the user of the condition
3227 code will produce a valid insn. If it won't, we can keep
3228 the original code in that insn by surrounding our operation
3231 if (((old_code == NE && new_code == EQ)
3232 || (old_code == EQ && new_code == NE))
3233 && ! other_changed && op1 == const0_rtx
3234 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
3235 && (exact_log2 (mask = significant_bits (op0,
3239 rtx pat = PATTERN (other_insn), note = 0;
3241 if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3242 && ! check_asm_operands (pat)))
3244 PUT_CODE (*cc_use, old_code);
3247 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3248 gen_rtx (CONST_INT, VOIDmode, mask));
3256 undobuf.other_insn = other_insn;
3259 /* If we are now comparing against zero, change our source if
3260 needed. If we do not use cc0, we always have a COMPARE. */
3261 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3262 SUBST (SET_SRC (x), op0);
3266 /* Otherwise, if we didn't previously have a COMPARE in the
3267 correct mode, we need one. */
3268 if (GET_CODE (SET_SRC (x)) != COMPARE
3269 || GET_MODE (SET_SRC (x)) != compare_mode)
3270 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3274 /* Otherwise, update the COMPARE if needed. */
3275 SUBST (XEXP (SET_SRC (x), 0), op0);
3276 SUBST (XEXP (SET_SRC (x), 1), op1);
3281 /* Get SET_SRC in a form where we have placed back any
3282 compound expressions. Then do the checks below. */
3283 temp = make_compound_operation (SET_SRC (x), SET);
3284 SUBST (SET_SRC (x), temp);
3287 #ifdef BYTE_LOADS_ZERO_EXTEND
3288 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3289 M wider than N, this would require a paradoxical subreg.
3290 Replace the subreg with a zero_extend to avoid the reload that
3291 would otherwise be required. */
3292 if (GET_CODE (SET_SRC (x)) == SUBREG
3293 && subreg_lowpart_p (SET_SRC (x))
3294 && SUBREG_WORD (SET_SRC (x)) == 0
3295 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3296 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3297 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3298 SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3299 GET_MODE (SET_SRC (x)),
3300 XEXP (SET_SRC (x), 0)));
3306 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3308 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3309 INTVAL (XEXP (x, 1)));
3311 /* If we have (ior (and (X C1) C2)) and the next restart would be
3312 the last, simplify this by making C1 as small as possible
3314 if (n_restarts >= 3 && GET_CODE (x) == IOR
3315 && GET_CODE (XEXP (x, 0)) == AND
3316 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3317 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3319 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3320 gen_rtx (CONST_INT, VOIDmode,
3321 (INTVAL (XEXP (XEXP (x, 0), 1))
3322 & ~ INTVAL (XEXP (x, 1)))));
3323 return gen_binary (IOR, mode, temp, XEXP (x, 1));
3326 if (GET_CODE (x) != AND)
3330 /* Convert (A | B) & A to A. */
3331 if (GET_CODE (XEXP (x, 0)) == IOR
3332 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3333 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3334 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3335 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3338 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3339 insn (and may simplify more). */
3340 else if (GET_CODE (XEXP (x, 0)) == XOR
3341 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3342 && ! side_effects_p (XEXP (x, 1)))
3344 x = gen_binary (AND, mode,
3345 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3349 else if (GET_CODE (XEXP (x, 0)) == XOR
3350 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3351 && ! side_effects_p (XEXP (x, 1)))
3353 x = gen_binary (AND, mode,
3354 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3359 /* Similarly for (~ (A ^ B)) & A. */
3360 else if (GET_CODE (XEXP (x, 0)) == NOT
3361 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3362 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3363 && ! side_effects_p (XEXP (x, 1)))
3365 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3369 else if (GET_CODE (XEXP (x, 0)) == NOT
3370 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3371 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3372 && ! side_effects_p (XEXP (x, 1)))
3374 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3379 /* In the follow group of tests (and those in case IOR below),
3380 we start with some combination of logical operations and apply
3381 the distributive law followed by the inverse distributive law.
3382 Most of the time, this results in no change. However, if some of
3383 the operands are the same or inverses of each other, simplifications
3386 For example, (and (ior A B) (not B)) can occur as the result of
3387 expanding a bit field assignment. When we apply the distributive
3388 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
3389 which then simplifies to (and (A (not B))). */
3391 /* If we have (and (ior A B) C), apply the distributive law and then
3392 the inverse distributive law to see if things simplify. */
3394 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
3396 x = apply_distributive_law
3397 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
3398 gen_binary (AND, mode,
3399 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3400 gen_binary (AND, mode,
3401 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3402 if (GET_CODE (x) != AND)
3406 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
3408 x = apply_distributive_law
3409 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
3410 gen_binary (AND, mode,
3411 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3412 gen_binary (AND, mode,
3413 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3414 if (GET_CODE (x) != AND)
3418 /* Similarly, taking advantage of the fact that
3419 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
3421 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
3423 x = apply_distributive_law
3424 (gen_binary (XOR, mode,
3425 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3426 XEXP (XEXP (x, 1), 0)),
3427 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3428 XEXP (XEXP (x, 1), 1))));
3429 if (GET_CODE (x) != AND)
3433 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
3435 x = apply_distributive_law
3436 (gen_binary (XOR, mode,
3437 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3438 XEXP (XEXP (x, 0), 0)),
3439 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3440 XEXP (XEXP (x, 0), 1))));
3441 if (GET_CODE (x) != AND)
3447 /* Convert (A & B) | A to A. */
3448 if (GET_CODE (XEXP (x, 0)) == AND
3449 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3450 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3451 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3452 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3455 /* If we have (ior (and A B) C), apply the distributive law and then
3456 the inverse distributive law to see if things simplify. */
3458 if (GET_CODE (XEXP (x, 0)) == AND)
3460 x = apply_distributive_law
3461 (gen_binary (AND, mode,
3462 gen_binary (IOR, mode,
3463 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3464 gen_binary (IOR, mode,
3465 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3467 if (GET_CODE (x) != IOR)
3471 if (GET_CODE (XEXP (x, 1)) == AND)
3473 x = apply_distributive_law
3474 (gen_binary (AND, mode,
3475 gen_binary (IOR, mode,
3476 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3477 gen_binary (IOR, mode,
3478 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3480 if (GET_CODE (x) != IOR)
3484 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3485 mode size to (rotate A CX). */
3487 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
3488 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
3489 || (GET_CODE (XEXP (x, 1)) == ASHIFT
3490 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
3491 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
3492 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3493 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3494 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
3495 == GET_MODE_BITSIZE (mode)))
3499 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3500 shift_count = XEXP (XEXP (x, 0), 1);
3502 shift_count = XEXP (XEXP (x, 1), 1);
3503 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
3509 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3510 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3513 int num_negated = 0;
3514 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
3516 if (GET_CODE (in1) == NOT)
3517 num_negated++, in1 = XEXP (in1, 0);
3518 if (GET_CODE (in2) == NOT)
3519 num_negated++, in2 = XEXP (in2, 0);
3521 if (num_negated == 2)
3523 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3524 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3526 else if (num_negated == 1)
3527 return gen_rtx_combine (NOT, mode,
3528 gen_rtx_combine (XOR, mode, in1, in2));
3531 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3532 correspond to a machine insn or result in further simplifications
3533 if B is a constant. */
3535 if (GET_CODE (XEXP (x, 0)) == AND
3536 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3537 && ! side_effects_p (XEXP (x, 1)))
3539 x = gen_binary (AND, mode,
3540 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3544 else if (GET_CODE (XEXP (x, 0)) == AND
3545 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3546 && ! side_effects_p (XEXP (x, 1)))
3548 x = gen_binary (AND, mode,
3549 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3555 #if STORE_FLAG_VALUE == 1
3556 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3558 if (XEXP (x, 1) == const1_rtx
3559 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3560 && reversible_comparison_p (XEXP (x, 0)))
3561 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3562 mode, XEXP (XEXP (x, 0), 0),
3563 XEXP (XEXP (x, 0), 1));
3566 /* (xor (comparison foo bar) (const_int sign-bit))
3567 when STORE_FLAG_VALUE is the sign bit. */
3568 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3569 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3570 && XEXP (x, 1) == const_true_rtx
3571 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3572 && reversible_comparison_p (XEXP (x, 0)))
3573 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3574 mode, XEXP (XEXP (x, 0), 0),
3575 XEXP (XEXP (x, 0), 1));
3579 /* (abs (neg <foo>)) -> (abs <foo>) */
3580 if (GET_CODE (XEXP (x, 0)) == NEG)
3581 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3583 /* If operand is something known to be positive, ignore the ABS. */
3584 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3585 || (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_INT
3586 && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3587 & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3592 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3593 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT
3594 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3595 || (GET_CODE (XEXP (x, 0)) == ASHIFTRT
3596 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3597 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3598 || ((temp = get_last_value (XEXP (x, 0))) != 0
3599 && ((GET_CODE (temp) == SIGN_EXTRACT
3600 && XEXP (temp, 1) == const1_rtx)
3601 || (GET_CODE (temp) == ASHIFTRT
3602 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3603 && (INTVAL (XEXP (temp, 1))
3604 == GET_MODE_BITSIZE (mode) - 1)))))
3606 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
3612 /* (ffs (*_extend <X>)) = (ffs <X>) */
3613 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3614 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3615 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3619 /* (float (sign_extend <X>)) = (float <X>). */
3620 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3621 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3630 #ifdef SHIFT_COUNT_TRUNCATED
3631 /* (*shift <X> (sign_extend <Y>)) = (*shift <X> <Y>) (most machines).
3632 True for all kinds of shifts and also for zero_extend. */
3633 if ((GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
3634 || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
3635 && FAKE_EXTEND_SAFE_P (mode, XEXP (XEXP (x, 1), 0)))
3637 /* This is a perverse SUBREG, wider than its base. */
3638 gen_lowpart_for_combine (mode, XEXP (XEXP (x, 1), 0)));
3640 /* tege: Change (bitshifts ... (and ... mask), c)
3641 to (bitshifts ... c) if mask just masks the bits the bitshift
3642 insns do automatically on this machine. */
3643 if (GET_CODE (XEXP (x, 1)) == AND
3644 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3645 && (~ INTVAL (XEXP (XEXP (x, 1), 1)) & GET_MODE_MASK (mode)) == 0)
3646 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3649 /* If this is a shift by a constant amount, simplify it. */
3650 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3652 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
3653 INTVAL (XEXP (x, 1)));
3654 if (GET_CODE (x) != code)
3663 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
3664 operations" because they can be replaced with two more basic operations.
3665 ZERO_EXTEND is also considered "compound" because it can be replaced with
3666 an AND operation, which is simpler, though only one operation.
3668 The function expand_compound_operation is called with an rtx expression
3669 and will convert it to the appropriate shifts and AND operations,
3670 simplifying at each stage.
3672 The function make_compound_operation is called to convert an expression
3673 consisting of shifts and ANDs into the equivalent compound expression.
3674 It is the inverse of this function, loosely speaking. */
3677 expand_compound_operation (x)
3685 switch (GET_CODE (x))
3690 /* If we somehow managed to end up with (sign/zero_extend (const_int x)),
3691 just return the CONST_INT. We can't know how much masking to do
3693 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3696 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
3699 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
3700 /* If the inner object has VOIDmode (the only way this can happen
3701 is if it is a ASM_OPERANDS), we can't do anything since we don't
3702 know how much masking to do. */
3711 /* If the operand is a CLOBBER, just return it. */
3712 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
3715 if (GET_CODE (XEXP (x, 1)) != CONST_INT
3716 || GET_CODE (XEXP (x, 2)) != CONST_INT
3717 || GET_MODE (XEXP (x, 0)) == VOIDmode)
3720 len = INTVAL (XEXP (x, 1));
3721 pos = INTVAL (XEXP (x, 2));
3723 /* If this goes outside the object being extracted, replace the object
3724 with a (use (mem ...)) construct that only combine understands
3725 and is used only for this purpose. */
3726 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3727 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
3730 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
3738 /* If we reach here, we want to return a pair of shifts. The inner
3739 shift is a left shift of BITSIZE - POS - LEN bits. The outer
3740 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
3741 logical depending on the value of UNSIGNEDP.
3743 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
3744 converted into an AND of a shift.
3746 We must check for the case where the left shift would have a negative
3747 count. This can happen in a case like (x >> 31) & 255 on machines
3748 that can't shift by a constant. On those machines, we would first
3749 combine the shift with the AND to produce a variable-position
3750 extraction. Then the constant of 31 would be substituted in to produce
3751 a such a position. */
3753 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
3754 if (modewidth >= pos - len)
3755 tem = simplify_shift_const (0, unsignedp ? LSHIFTRT : ASHIFTRT,
3757 simplify_shift_const (0, ASHIFT, GET_MODE (x),
3759 modewidth - pos - len),
3762 else if (unsignedp && len < HOST_BITS_PER_INT)
3763 tem = simplify_and_const_int (0, GET_MODE (x),
3764 simplify_shift_const (0, LSHIFTRT,
3769 /* Any other cases we can't handle. */
3773 /* If we couldn't do this for some reason, return the original
3775 if (GET_CODE (tem) == CLOBBER)
3781 /* X is a SET which contains an assignment of one object into
3782 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
3783 or certain SUBREGS). If possible, convert it into a series of
3786 We half-heartedly support variable positions, but do not at all
3787 support variable lengths. */
3790 expand_field_assignment (x)
3794 rtx pos; /* Always counts from low bit. */
3797 enum machine_mode compute_mode;
3799 /* Loop until we find something we can't simplify. */
3802 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
3803 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
3805 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
3806 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
3809 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3810 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
3812 inner = XEXP (SET_DEST (x), 0);
3813 len = INTVAL (XEXP (SET_DEST (x), 1));
3814 pos = XEXP (SET_DEST (x), 2);
3816 /* If the position is constant and spans the width of INNER,
3817 surround INNER with a USE to indicate this. */
3818 if (GET_CODE (pos) == CONST_INT
3819 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
3820 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
3823 if (GET_CODE (pos) == CONST_INT)
3824 pos = gen_rtx (CONST_INT, VOIDmode,
3825 (GET_MODE_BITSIZE (GET_MODE (inner)) - len
3827 else if (GET_CODE (pos) == MINUS
3828 && GET_CODE (XEXP (pos, 1)) == CONST_INT
3829 && (INTVAL (XEXP (pos, 1))
3830 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
3831 /* If position is ADJUST - X, new position is X. */
3832 pos = XEXP (pos, 0);
3834 pos = gen_binary (MINUS, GET_MODE (pos),
3835 gen_rtx (CONST_INT, VOIDmode,
3836 (GET_MODE_BITSIZE (GET_MODE (inner))
3841 /* A SUBREG between two modes that occupy the same numbers of words
3842 can be done by moving the SUBREG to the source. */
3843 else if (GET_CODE (SET_DEST (x)) == SUBREG
3844 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
3845 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
3846 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
3847 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
3849 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
3850 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
3857 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3858 inner = SUBREG_REG (inner);
3860 compute_mode = GET_MODE (inner);
3862 /* Compute a mask of LEN bits, if we can do this on the host machine. */
3863 if (len < HOST_BITS_PER_INT)
3864 mask = gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1);
3868 /* Now compute the equivalent expression. Make a copy of INNER
3869 for the SET_DEST in case it is a MEM into which we will substitute;
3870 we don't want shared RTL in that case. */
3871 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
3872 gen_binary (IOR, compute_mode,
3873 gen_binary (AND, compute_mode,
3874 gen_unary (NOT, compute_mode,
3879 gen_binary (ASHIFT, compute_mode,
3880 gen_binary (AND, compute_mode,
3881 gen_lowpart_for_combine
3891 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
3892 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
3893 the starting bit position.
3895 INNER may be a USE. This will occur when we started with a bitfield
3896 that went outside the boundary of the object in memory, which is
3897 allowed on most machines. To isolate this case, we produce a USE
3898 whose mode is wide enough and surround the MEM with it. The only
3899 code that understands the USE is this routine. If it is not removed,
3900 it will cause the resulting insn not to match.
3902 UNSIGNEDP is non-zero for an unsigned reference and zero for a
3905 IN_DEST is non-zero if this is a reference in the destination of a
3906 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
3907 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
3910 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
3911 ZERO_EXTRACT should be built even for bits starting at bit 0.
3913 MODE is the desired mode of the result (if IN_DEST == 0). */
3916 make_extraction (mode, inner, pos, pos_rtx, len,
3917 unsignedp, in_dest, in_compare)
3918 enum machine_mode mode;
3924 int in_dest, in_compare;
3926 enum machine_mode is_mode = GET_MODE (inner);
3927 enum machine_mode inner_mode;
3928 enum machine_mode wanted_mem_mode = byte_mode;
3929 enum machine_mode pos_mode = word_mode;
3930 enum machine_mode extraction_mode = word_mode;
3931 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
3935 /* Get some information about INNER and get the innermost object. */
3936 if (GET_CODE (inner) == USE)
3937 /* We don't need to adjust the position because we set up the USE
3938 to pretend that it was a full-word object. */
3939 spans_byte = 1, inner = XEXP (inner, 0);
3940 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3941 inner = SUBREG_REG (inner);
3943 inner_mode = GET_MODE (inner);
3945 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
3946 pos = INTVAL (pos_rtx);
3948 /* See if this can be done without an extraction. We never can if the
3949 width of the field is not the same as that of some integer mode. For
3950 registers, we can only avoid the extraction if the position is at the
3951 low-order bit and this is either not in the destination or we have the
3952 appropriate STRICT_LOW_PART operation available.
3954 For MEM, we can avoid an extract if the field starts on an appropriate
3955 boundary and we can change the mode of the memory reference. However,
3956 we cannot directly access the MEM if we have a USE and the underlying
3957 MEM is not TMODE. This combination means that MEM was being used in a
3958 context where bits outside its mode were being referenced; that is only
3959 valid in bit-field insns. */
3961 if (tmode != BLKmode
3962 && ! (spans_byte && inner_mode != tmode)
3963 && ((pos == 0 && GET_CODE (inner) == REG
3965 || (movstrict_optab->handlers[(int) tmode].insn_code
3966 != CODE_FOR_nothing)))
3967 || (GET_CODE (inner) == MEM && pos >= 0
3969 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
3970 : BITS_PER_UNIT)) == 0
3971 /* We can't do this if we are widening INNER_MODE (it
3972 may not be aligned, for one thing). */
3973 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
3974 && (inner_mode == tmode
3975 || (! mode_dependent_address_p (XEXP (inner, 0))
3976 && ! MEM_VOLATILE_P (inner))))))
3978 int offset = pos / BITS_PER_UNIT;
3980 /* If INNER is a MEM, make a new MEM that encompasses just the desired
3981 field. If the original and current mode are the same, we need not
3982 adjust the offset. Otherwise, we do if bytes big endian.
3984 If INNER is not a MEM, get a piece consisting of the just the field
3985 of interest (in this case INNER must be a REG and POS must be 0). */
3987 if (GET_CODE (inner) == MEM)
3989 #if BYTES_BIG_ENDIAN
3990 if (inner_mode != tmode)
3991 offset = (GET_MODE_SIZE (inner_mode)
3992 - GET_MODE_SIZE (tmode) - offset);
3995 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
3996 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
3997 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
3998 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4001 new = gen_lowpart_for_combine (tmode, inner);
4003 /* If this extraction is going into the destination of a SET,
4004 make a STRICT_LOW_PART unless we made a MEM. */
4007 return (GET_CODE (new) == MEM ? new
4008 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new));
4010 /* Otherwise, sign- or zero-extend unless we already are in the
4013 return (mode == tmode ? new
4014 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4018 /* Unless this is in a COMPARE or we have a funny memory reference,
4019 don't do anything with field extracts starting at the low-order
4020 bit since they are simple AND operations. */
4021 if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte)
4024 /* Get the mode to use should INNER be a MEM, the mode for the position,
4025 and the mode for the result. */
4029 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4030 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4031 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4036 if (! in_dest && unsignedp)
4038 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4039 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4040 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4045 if (! in_dest && ! unsignedp)
4047 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4048 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4049 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4053 /* Never narrow an object, since that might not be safe. */
4055 if (mode != VOIDmode
4056 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4057 extraction_mode = mode;
4059 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4060 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4061 pos_mode = GET_MODE (pos_rtx);
4063 /* If this is not from memory or we have to change the mode of memory and
4064 cannot, the desired mode is EXTRACTION_MODE. */
4065 if (GET_CODE (inner) != MEM
4066 || (inner_mode != wanted_mem_mode
4067 && (mode_dependent_address_p (XEXP (inner, 0))
4068 || MEM_VOLATILE_P (inner))))
4069 wanted_mem_mode = extraction_mode;
4072 /* If position is constant, compute new position. Otherwise, build
4075 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4079 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4080 gen_rtx (CONST_INT, VOIDmode,
4081 (MAX (GET_MODE_BITSIZE (is_mode),
4082 GET_MODE_BITSIZE (wanted_mem_mode))
4086 /* If INNER has a wider mode, make it smaller. If this is a constant
4087 extract, try to adjust the byte to point to the byte containing
4089 if (wanted_mem_mode != VOIDmode
4090 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4091 && ((GET_CODE (inner) == MEM
4092 && (inner_mode == wanted_mem_mode
4093 || (! mode_dependent_address_p (XEXP (inner, 0))
4094 && ! MEM_VOLATILE_P (inner))))))
4098 /* The computations below will be correct if the machine is big
4099 endian in both bits and bytes or little endian in bits and bytes.
4100 If it is mixed, we must adjust. */
4102 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4103 if (! spans_byte && is_mode != wanted_mem_mode)
4104 offset = (GET_MODE_SIZE (is_mode)
4105 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4108 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4109 adjust OFFSET to compensate. */
4110 #if BYTES_BIG_ENDIAN
4112 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4113 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4116 /* If this is a constant position, we can move to the desired byte. */
4119 offset += pos / BITS_PER_UNIT;
4120 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4123 if (offset != 0 || inner_mode != wanted_mem_mode)
4125 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4126 plus_constant (XEXP (inner, 0), offset));
4127 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4128 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4129 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4134 /* If INNER is not memory, we can always get it into the proper mode. */
4135 else if (GET_CODE (inner) != MEM)
4136 inner = gen_lowpart_for_combine (extraction_mode, inner);
4138 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4139 have to zero extend. Otherwise, we can just use a SUBREG. */
4141 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4142 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4144 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4145 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4147 /* Make POS_RTX unless we already have it and it is correct. */
4148 if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4149 pos_rtx = gen_rtx (CONST_INT, VOIDmode, pos);
4151 /* Make the required operation. See if we can use existing rtx. */
4152 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4153 extraction_mode, inner,
4154 gen_rtx (CONST_INT, VOIDmode, len), pos_rtx);
4156 new = gen_lowpart_for_combine (mode, new);
4161 /* Look at the expression rooted at X. Look for expressions
4162 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4163 Form these expressions.
4165 Return the new rtx, usually just X.
4167 Also, for machines like the Vax that don't have logical shift insns,
4168 try to convert logical to arithmetic shift operations in cases where
4169 they are equivalent. This undoes the canonicalizations to logical
4170 shifts done elsewhere.
4172 We try, as much as possible, to re-use rtl expressions to save memory.
4174 IN_CODE says what kind of expression we are processing. Normally, it is
4175 SET. In a memory address (inside a MEM or PLUS, the latter being a
4176 kludge), it is MEM. When processing the arguments of a comparison
4177 or a COMPARE against zero, it is COMPARE. */
4180 make_compound_operation (x, in_code)
4182 enum rtx_code in_code;
4184 enum rtx_code code = GET_CODE (x);
4185 enum machine_mode mode = GET_MODE (x);
4186 int mode_width = GET_MODE_BITSIZE (mode);
4187 enum rtx_code next_code;
4192 /* Select the code to be used in recursive calls. Once we are inside an
4193 address, we stay there. If we have a comparison, set to COMPARE,
4194 but once inside, go back to our default of SET. */
4196 next_code = (code == MEM || code == PLUS ? MEM
4197 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4198 && XEXP (x, 1) == const0_rtx) ? COMPARE
4199 : in_code == COMPARE ? SET : in_code);
4201 /* Process depending on the code of this operation. If NEW is set
4202 non-zero, it will be returned. */
4208 /* Convert shifts by constants into multiplications if inside
4210 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4211 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT
4212 && INTVAL (XEXP (x, 1)) >= 0)
4213 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4214 gen_rtx (CONST_INT, VOIDmode,
4215 1 << INTVAL (XEXP (x, 1))));
4219 /* If the second operand is not a constant, we can't do anything
4221 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4224 /* If the constant is a power of two minus one and the first operand
4225 is a logical right shift, make an extraction. */
4226 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4227 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4228 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4229 XEXP (XEXP (x, 0), 1), i, 1,
4230 0, in_code == COMPARE);
4232 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4233 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4234 && subreg_lowpart_p (XEXP (x, 0))
4235 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4236 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4237 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4238 XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4239 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4240 0, in_code == COMPARE);
4243 /* If we are have (and (rotate X C) M) and C is larger than the number
4244 of bits in M, this is an extraction. */
4246 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4247 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4248 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4249 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4250 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4251 (GET_MODE_BITSIZE (mode)
4252 - INTVAL (XEXP (XEXP (x, 0), 1))),
4253 0, i, 1, 0, in_code == COMPARE);
4255 /* On machines without logical shifts, if the operand of the AND is
4256 a logical shift and our mask turns off all the propagated sign
4257 bits, we can replace the logical shift with an arithmetic shift. */
4269 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4270 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4271 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4272 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_INT
4273 && mode_width <= HOST_BITS_PER_INT)
4275 unsigned mask = GET_MODE_MASK (mode);
4277 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4278 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4280 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4281 XEXP (XEXP (x, 0), 1)));
4284 /* If the constant is one less than a power of two, this might be
4285 representable by an extraction even if no shift is present.
4286 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4287 we are in a COMPARE. */
4288 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4289 new = make_extraction (mode, XEXP (x, 0), 0, 0, i, 1,
4290 0, in_code == COMPARE);
4292 /* If we are in a comparison and this is an AND with a power of two,
4293 convert this into the appropriate bit extract. */
4294 else if (in_code == COMPARE
4295 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4296 new = make_extraction (mode, XEXP (x, 0), i, 0, 1, 1, 0, 1);
4301 /* If the sign bit is known to be zero, replace this with an
4302 arithmetic shift. */
4314 && mode_width <= HOST_BITS_PER_INT
4315 && (significant_bits (XEXP (x, 0), mode)
4316 & (1 << (mode_width - 1))) == 0)
4318 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4322 /* ... fall through ... */
4325 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4326 this is a SIGN_EXTRACT. */
4327 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4328 && GET_CODE (XEXP (x, 0)) == ASHIFT
4329 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4330 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4331 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4332 (INTVAL (XEXP (x, 1))
4333 - INTVAL (XEXP (XEXP (x, 0), 1))),
4334 0, mode_width - INTVAL (XEXP (x, 1)),
4335 code == LSHIFTRT, 0, in_code == COMPARE);
4342 code = GET_CODE (x);
4345 /* Now recursively process each operand of this operation. */
4346 fmt = GET_RTX_FORMAT (code);
4347 for (i = 0; i < GET_RTX_LENGTH (code); i++)
4350 new = make_compound_operation (XEXP (x, i), next_code);
4351 SUBST (XEXP (x, i), new);
4357 /* Given M see if it is a value that would select a field of bits
4358 within an item, but not the entire word. Return -1 if not.
4359 Otherwise, return the starting position of the field, where 0 is the
4362 *PLEN is set to the length of the field. */
4365 get_pos_from_mask (m, plen)
4369 /* Get the bit number of the first 1 bit from the right, -1 if none. */
4370 int pos = exact_log2 (m & - m);
4375 /* Now shift off the low-order zero bits and see if we have a power of
4377 *plen = exact_log2 ((m >> pos) + 1);
4385 /* Rewrite X so that it is an expression in MODE. We only care about the
4386 low-order BITS bits so we can ignore AND operations that just clear
4389 Also, if REG is non-zero and X is a register equal in value to REG,
4390 replace X with REG. */
4393 force_to_mode (x, mode, bits, reg)
4395 enum machine_mode mode;
4399 enum rtx_code code = GET_CODE (x);
4401 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
4402 just get X in the proper mode. */
4404 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
4405 || bits > GET_MODE_BITSIZE (mode))
4406 return gen_lowpart_for_combine (mode, x);
4414 x = expand_compound_operation (x);
4415 if (GET_CODE (x) != code)
4416 return force_to_mode (x, mode, bits, reg);
4420 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
4421 || rtx_equal_p (reg, get_last_value (x))))
4426 if (bits < HOST_BITS_PER_INT)
4427 x = gen_rtx (CONST_INT, VOIDmode, INTVAL (x) & ((1 << bits) - 1));
4431 /* Ignore low-order SUBREGs. */
4432 if (subreg_lowpart_p (x))
4433 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
4437 /* If this is an AND with a constant. Otherwise, we fall through to
4438 do the general binary case. */
4440 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4442 int mask = INTVAL (XEXP (x, 1));
4443 int len = exact_log2 (mask + 1);
4444 rtx op = XEXP (x, 0);
4446 /* If this is masking some low-order bits, we may be able to
4447 impose a stricter constraint on what bits of the operand are
4450 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
4453 if (bits < HOST_BITS_PER_INT)
4454 mask &= (1 << bits) - 1;
4456 x = simplify_and_const_int (x, mode, op, mask);
4458 /* If X is still an AND, see if it is an AND with a mask that
4459 is just some low-order bits. If so, and it is BITS wide (it
4460 can't be wider), we don't need it. */
4462 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
4463 && bits < HOST_BITS_PER_INT
4464 && INTVAL (XEXP (x, 1)) == (1 << bits) - 1)
4469 /* ... fall through ... */
4476 /* For most binary operations, just propagate into the operation and
4479 return gen_binary (code, mode,
4480 force_to_mode (XEXP (x, 0), mode, bits, reg),
4481 force_to_mode (XEXP (x, 1), mode, bits, reg));
4485 /* For left shifts, do the same, but just for the first operand.
4486 If the shift count is a constant, we need even fewer bits of the
4489 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
4490 bits -= INTVAL (XEXP (x, 1));
4492 return gen_binary (code, mode,
4493 force_to_mode (XEXP (x, 0), mode, bits, reg),
4497 /* Here we can only do something if the shift count is a constant and
4498 the count plus BITS is no larger than the width of MODE, we can do
4499 the shift in MODE. */
4501 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4502 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
4503 return gen_binary (LSHIFTRT, mode,
4504 force_to_mode (XEXP (x, 0), mode,
4505 bits + INTVAL (XEXP (x, 1)), reg),
4511 /* Handle these similarly to the way we handle most binary operations. */
4512 return gen_unary (code, mode,
4513 force_to_mode (XEXP (x, 0), mode, bits, reg));
4516 /* Otherwise, just do the operation canonically. */
4517 return gen_lowpart_for_combine (mode, x);
4520 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
4521 Return that assignment if so.
4523 We only handle the most common cases. */
4526 make_field_assignment (x)
4529 rtx dest = SET_DEST (x);
4530 rtx src = SET_SRC (x);
4535 enum machine_mode mode;
4537 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
4538 a clear of a one-bit field. We will have changed it to
4539 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
4542 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
4543 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
4544 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
4545 && (rtx_equal_p (dest, XEXP (src, 1))
4546 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4547 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4549 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4551 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
4554 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
4555 && subreg_lowpart_p (XEXP (src, 0))
4556 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
4557 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
4558 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
4559 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
4560 && (rtx_equal_p (dest, XEXP (src, 1))
4561 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4562 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4564 assign = make_extraction (VOIDmode, dest, -1,
4565 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
4567 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
4570 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
4572 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
4573 && XEXP (XEXP (src, 0), 0) == const1_rtx
4574 && (rtx_equal_p (dest, XEXP (src, 1))
4575 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4576 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4578 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4580 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
4583 /* The other case we handle is assignments into a constant-position
4584 field. They look like (ior (and DEST C1) OTHER). If C1 represents
4585 a mask that has all one bits except for a group of zero bits and
4586 OTHER is known to have zeros where C1 has ones, this is such an
4587 assignment. Compute the position and length from C1. Shift OTHER
4588 to the appropriate position, force it to the required mode, and
4589 make the extraction. Check for the AND in both operands. */
4591 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
4592 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
4593 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
4594 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
4595 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
4596 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
4597 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
4598 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
4599 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
4600 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
4601 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
4603 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
4607 pos = get_pos_from_mask (~c1, &len);
4608 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
4609 || (c1 & significant_bits (other, GET_MODE (other))) != 0)
4612 assign = make_extraction (VOIDmode, dest, pos, 0, len, 1, 1, 0);
4614 /* The mode to use for the source is the mode of the assignment, or of
4615 what is inside a possible STRICT_LOW_PART. */
4616 mode = (GET_CODE (assign) == STRICT_LOW_PART
4617 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
4619 /* Shift OTHER right POS places and make it the source, restricting it
4620 to the proper length and mode. */
4622 src = force_to_mode (simplify_shift_const (0, LSHIFTRT, GET_MODE (src),
4626 return gen_rtx_combine (SET, VOIDmode, assign, src);
4629 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
4633 apply_distributive_law (x)
4636 enum rtx_code code = GET_CODE (x);
4637 rtx lhs, rhs, other;
4639 enum rtx_code inner_code;
4641 /* The outer operation can only be one of the following: */
4642 if (code != IOR && code != AND && code != XOR
4643 && code != PLUS && code != MINUS)
4646 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
4648 /* If either operand is a primitive we can't do anything, so get out fast. */
4649 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
4650 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
4653 lhs = expand_compound_operation (lhs);
4654 rhs = expand_compound_operation (rhs);
4655 inner_code = GET_CODE (lhs);
4656 if (inner_code != GET_CODE (rhs))
4659 /* See if the inner and outer operations distribute. */
4666 /* These all distribute except over PLUS. */
4667 if (code == PLUS || code == MINUS)
4672 if (code != PLUS && code != MINUS)
4678 /* These are also multiplies, so they distribute over everything. */
4682 /* Non-paradoxical SUBREGs distributes over all operations, provided
4683 the inner modes and word numbers are the same, this is an extraction
4684 of a low-order part, and we would not be converting a single-word
4685 operation into a multi-word operation. The latter test is not
4686 required, but we prevents generating unneeded multi-word operations.
4687 Some of the previous tests are redundant given the latter test, but
4688 are retained because they are required for correctness.
4690 We produce the result slightly differently in this case. */
4692 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
4693 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
4694 || ! subreg_lowpart_p (lhs)
4695 || (GET_MODE_SIZE (GET_MODE (lhs))
4696 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
4697 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
4700 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
4701 SUBREG_REG (lhs), SUBREG_REG (rhs));
4702 return gen_lowpart_for_combine (GET_MODE (x), tem);
4708 /* Set LHS and RHS to the inner operands (A and B in the example
4709 above) and set OTHER to the common operand (C in the example).
4710 These is only one way to do this unless the inner operation is
4712 if (GET_RTX_CLASS (inner_code) == 'c'
4713 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
4714 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
4715 else if (GET_RTX_CLASS (inner_code) == 'c'
4716 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
4717 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
4718 else if (GET_RTX_CLASS (inner_code) == 'c'
4719 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
4720 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
4721 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
4722 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
4726 /* Form the new inner operation, seeing if it simplifies first. */
4727 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
4729 /* There is one exception to the general way of distributing:
4730 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
4731 if (code == XOR && inner_code == IOR)
4734 other = gen_unary (NOT, GET_MODE (x), other);
4737 /* We may be able to continuing distributing the result, so call
4738 ourselves recursively on the inner operation before forming the
4739 outer operation, which we return. */
4740 return gen_binary (inner_code, GET_MODE (x),
4741 apply_distributive_law (tem), other);
4744 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
4747 Return an equivalent form, if different from X. Otherwise, return X. If
4748 X is zero, we are to always construct the equivalent form. */
4751 simplify_and_const_int (x, mode, varop, constop)
4753 enum machine_mode mode;
4757 register enum machine_mode tmode;
4759 unsigned significant;
4761 /* There is a large class of optimizations based on the principle that
4762 some operations produce results where certain bits are known to be zero,
4763 and hence are not significant to the AND. For example, if we have just
4764 done a left shift of one bit, the low-order bit is known to be zero and
4765 hence an AND with a mask of ~1 would not do anything.
4767 At the end of the following loop, we set:
4769 VAROP to be the item to be AND'ed with;
4770 CONSTOP to the constant value to AND it with. */
4774 /* If we ever encounter a mode wider than the host machine's word
4775 size, we can't compute the masks accurately, so give up. */
4776 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_INT)
4779 /* Unless one of the cases below does a `continue',
4780 a `break' will be executed to exit the loop. */
4782 switch (GET_CODE (varop))
4785 /* If VAROP is a (clobber (const_int)), return it since we know
4786 we are generating something that won't match. */
4789 #if ! BITS_BIG_ENDIAN
4791 /* VAROP is a (use (mem ..)) that was made from a bit-field
4792 extraction that spanned the boundary of the MEM. If we are
4793 now masking so it is within that boundary, we don't need the
4795 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
4797 varop = XEXP (varop, 0);
4804 if (subreg_lowpart_p (varop)
4805 /* We can ignore the effect this SUBREG if it narrows the mode
4806 or, on machines where byte operations zero extend, if the
4807 constant masks to zero all the bits the mode doesn't have. */
4808 && ((GET_MODE_SIZE (GET_MODE (varop))
4809 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
4810 #ifdef BYTE_LOADS_ZERO_EXTEND
4812 & GET_MODE_MASK (GET_MODE (varop))
4813 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
4817 varop = SUBREG_REG (varop);
4826 /* Try to expand these into a series of shifts and then work
4827 with that result. If we can't, for example, if the extract
4828 isn't at a fixed position, give up. */
4829 temp = expand_compound_operation (varop);
4838 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
4840 constop &= INTVAL (XEXP (varop, 1));
4841 varop = XEXP (varop, 0);
4848 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
4849 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
4850 operation which may be a bitfield extraction. */
4852 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4853 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4854 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4855 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT
4856 && GET_CODE (XEXP (varop, 1)) == CONST_INT
4857 && (INTVAL (XEXP (varop, 1))
4858 & ~ significant_bits (XEXP (varop, 0),
4859 GET_MODE (varop)) == 0))
4861 temp = gen_rtx (CONST_INT, VOIDmode,
4862 ((INTVAL (XEXP (varop, 1)) & constop)
4863 << INTVAL (XEXP (XEXP (varop, 0), 1))));
4864 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
4865 XEXP (XEXP (varop, 0), 0), temp);
4866 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4867 temp, XEXP (varop, 1));
4871 /* Apply the AND to both branches of the IOR or XOR, then try to
4872 apply the distributive law. This may eliminate operations
4873 if either branch can be simplified because of the AND.
4874 It may also make some cases more complex, but those cases
4875 probably won't match a pattern either with or without this. */
4877 gen_lowpart_for_combine
4878 (mode, apply_distributive_law
4880 (GET_CODE (varop), GET_MODE (varop),
4881 simplify_and_const_int (0, GET_MODE (varop),
4882 XEXP (varop, 0), constop),
4883 simplify_and_const_int (0, GET_MODE (varop),
4884 XEXP (varop, 1), constop))));
4887 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
4888 LSHIFTRT we can do the same as above. */
4890 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4891 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4892 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4893 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT)
4895 temp = gen_rtx (CONST_INT, VOIDmode,
4896 constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
4897 temp = gen_binary (XOR, GET_MODE (varop),
4898 XEXP (XEXP (varop, 0), 0), temp);
4899 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4900 temp, XEXP (XEXP (varop, 0), 1));
4906 /* If we are just looking for the sign bit, we don't need this
4907 shift at all, even if it has a variable count. */
4908 if (constop == 1 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1))
4910 varop = XEXP (varop, 0);
4914 /* If this is a shift by a constant, get a mask that contains
4915 those bits that are not copies of the sign bit. We then have
4916 two cases: If CONSTOP only includes those bits, this can be
4917 a logical shift, which may allow simplifications. If CONSTOP
4918 is a single-bit field not within those bits, we are requesting
4919 a copy of the sign bit and hence can shift the sign bit to
4920 the appropriate location. */
4921 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4922 && INTVAL (XEXP (varop, 1)) >= 0
4923 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_INT)
4927 significant = GET_MODE_MASK (GET_MODE (varop));
4928 significant >>= INTVAL (XEXP (varop, 1));
4930 if ((constop & ~significant) == 0
4931 || (i = exact_log2 (constop)) >= 0)
4933 varop = simplify_shift_const
4934 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
4935 i < 0 ? INTVAL (XEXP (varop, 1))
4936 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
4937 if (GET_CODE (varop) != ASHIFTRT)
4942 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
4943 even if the shift count isn't a constant. */
4945 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4946 XEXP (varop, 0), XEXP (varop, 1));
4950 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
4951 included in STORE_FLAG_VALUE and FOO has no significant bits
4953 if ((constop & ~ STORE_FLAG_VALUE) == 0
4954 && XEXP (varop, 0) == const0_rtx
4955 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
4957 varop = XEXP (varop, 0);
4963 /* In (and (plus FOO C1) M), if M is a mask that just turns off
4964 low-order bits (as in an alignment operation) and FOO is already
4965 aligned to that boundary, we can convert remove this AND
4966 and possibly the PLUS if it is now adding zero. */
4967 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4968 && exact_log2 (-constop) >= 0
4969 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
4971 varop = plus_constant (XEXP (varop, 0),
4972 INTVAL (XEXP (varop, 1)) & constop);
4977 /* ... fall through ... */
4980 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
4981 less than powers of two and M2 is narrower than M1, we can
4982 eliminate the inner AND. This occurs when incrementing
4985 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
4986 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
4987 SUBST (XEXP (varop, 0),
4988 expand_compound_operation (XEXP (varop, 0)));
4990 if (GET_CODE (XEXP (varop, 0)) == AND
4991 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4992 && exact_log2 (constop + 1) >= 0
4993 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
4994 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
4995 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5002 /* If we have reached a constant, this whole thing is constant. */
5003 if (GET_CODE (varop) == CONST_INT)
5004 return gen_rtx (CONST_INT, VOIDmode, constop & INTVAL (varop));
5006 /* See what bits are significant in VAROP. */
5007 significant = significant_bits (varop, mode);
5009 /* Turn off all bits in the constant that are known to already be zero.
5010 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5011 which is tested below. */
5013 constop &= significant;
5015 /* If we don't have any bits left, return zero. */
5019 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5020 if we already had one (just check for the simplest cases). */
5021 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5022 && GET_MODE (XEXP (x, 0)) == mode
5023 && SUBREG_REG (XEXP (x, 0)) == varop)
5024 varop = XEXP (x, 0);
5026 varop = gen_lowpart_for_combine (mode, varop);
5028 /* If we can't make the SUBREG, try to return what we were given. */
5029 if (GET_CODE (varop) == CLOBBER)
5030 return x ? x : varop;
5032 /* If we are only masking insignificant bits, return VAROP. */
5033 if (constop == significant)
5036 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5037 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5038 x = gen_rtx_combine (AND, mode, varop,
5039 gen_rtx (CONST_INT, VOIDmode, constop));
5043 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5044 || INTVAL (XEXP (x, 1)) != constop)
5045 SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, constop));
5047 SUBST (XEXP (x, 0), varop);
5053 /* Given an expression, X, compute which bits in X can be non-zero.
5054 We don't care about bits outside of those defined in MODE.
5056 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5057 a shift, AND, or zero_extract, we can do better. */
5060 significant_bits (x, mode)
5062 enum machine_mode mode;
5064 unsigned significant = GET_MODE_MASK (mode);
5067 int mode_width = GET_MODE_BITSIZE (mode);
5070 /* If X is wider than MODE, use its mode instead. */
5071 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5073 mode = GET_MODE (x);
5074 significant = GET_MODE_MASK (mode);
5075 mode_width = GET_MODE_BITSIZE (mode);
5078 if (mode_width > HOST_BITS_PER_INT)
5079 /* Our only callers in this case look for single bit values. So
5080 just return the mode mask. Those tests will then be false. */
5083 code = GET_CODE (x);
5087 #ifdef STACK_BOUNDARY
5088 /* If this is the stack pointer, we may know something about its
5089 alignment. If PUSH_ROUNDING is defined, it is possible for the
5090 stack to be momentarily aligned only to that amount, so we pick
5091 the least alignment. */
5093 if (x == stack_pointer_rtx)
5095 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5097 #ifdef PUSH_ROUNDING
5098 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5101 return significant & ~ (sp_alignment - 1);
5105 /* If X is a register whose value we can find, use that value.
5106 Otherwise, use the previously-computed significant bits for this
5109 tem = get_last_value (x);
5111 return significant_bits (tem, mode);
5112 else if (significant_valid && reg_significant[REGNO (x)])
5113 return reg_significant[REGNO (x)] & significant;
5120 #ifdef BYTE_LOADS_ZERO_EXTEND
5122 /* In many, if not most, RISC machines, reading a byte from memory
5123 zeros the rest of the register. Noticing that fact saves a lot
5124 of extra zero-extends. */
5125 significant &= GET_MODE_MASK (GET_MODE (x));
5129 #if STORE_FLAG_VALUE == 1
5137 /* A comparison operation only sets the bits given by its mode. The
5138 rest are set undefined. */
5139 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5140 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5144 #if STORE_FLAG_VALUE == -1
5146 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5147 || ((tem = get_last_value (XEXP (x, 0))) != 0
5148 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))
5151 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5152 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5157 significant &= (significant_bits (XEXP (x, 0), mode)
5158 & GET_MODE_MASK (mode));
5162 significant &= significant_bits (XEXP (x, 0), mode);
5163 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5164 significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5168 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
5169 Otherwise, show all the bits in the outer mode but not the inner
5171 inner_sig = significant_bits (XEXP (x, 0), mode);
5172 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5174 inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5176 (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
5177 inner_sig |= (GET_MODE_MASK (mode)
5178 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
5181 significant &= inner_sig;
5185 significant &= (significant_bits (XEXP (x, 0), mode)
5186 & significant_bits (XEXP (x, 1), mode));
5191 significant &= (significant_bits (XEXP (x, 0), mode)
5192 | significant_bits (XEXP (x, 1), mode));
5195 case PLUS: case MINUS:
5197 case DIV: case UDIV:
5198 case MOD: case UMOD:
5199 /* We can apply the rules of arithmetic to compute the number of
5200 high- and low-order zero bits of these operations. We start by
5201 computing the width (position of the highest-order non-zero bit)
5202 and the number of low-order zero bits for each value. */
5204 unsigned sig0 = significant_bits (XEXP (x, 0), mode);
5205 unsigned sig1 = significant_bits (XEXP (x, 1), mode);
5206 int width0 = floor_log2 (sig0) + 1;
5207 int width1 = floor_log2 (sig1) + 1;
5208 int low0 = floor_log2 (sig0 & -sig0);
5209 int low1 = floor_log2 (sig1 & -sig1);
5210 int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
5211 int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
5212 int result_width = mode_width;
5218 result_width = MAX (width0, width1) + 1;
5219 result_low = MIN (low0, low1);
5222 result_low = MIN (low0, low1);
5225 result_width = width0 + width1;
5226 result_low = low0 + low1;
5229 if (! op0_maybe_minusp && ! op1_maybe_minusp)
5230 result_width = width0;
5233 result_width = width0;
5236 if (! op0_maybe_minusp && ! op1_maybe_minusp)
5237 result_width = MIN (width0, width1);
5238 result_low = MIN (low0, low1);
5241 result_width = MIN (width0, width1);
5242 result_low = MIN (low0, low1);
5246 if (result_width < mode_width)
5247 significant &= (1 << result_width) - 1;
5250 significant &= ~ ((1 << result_low) - 1);
5255 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5256 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5257 significant &= (1 << INTVAL (XEXP (x, 1))) - 1;
5261 /* If the inner mode is a single word for both the host and target
5262 machines, we can compute this from which bits of the inner
5263 object are known significant. */
5264 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5265 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
5267 significant &= significant_bits (SUBREG_REG (x), mode);
5268 #ifndef BYTE_LOADS_ZERO_EXTEND
5269 /* On many CISC machines, accessing an object in a wider mode
5270 causes the high-order bits to become undefined. So they are
5271 not known to be zero. */
5272 if (GET_MODE_SIZE (GET_MODE (x))
5273 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5274 significant |= (GET_MODE_MASK (GET_MODE (x))
5275 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
5285 /* The significant bits are in two classes: any bits within MODE
5286 that aren't in GET_MODE (x) are always significant. The rest of the
5287 significant bits are those that are significant in the operand of
5288 the shift when shifted the appropriate number of bits. This
5289 shows that high-order bits are cleared by the right shift and
5290 low-order bits by left shifts. */
5291 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5292 && INTVAL (XEXP (x, 1)) >= 0
5293 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5295 enum machine_mode inner_mode = GET_MODE (x);
5296 int width = GET_MODE_BITSIZE (inner_mode);
5297 int count = INTVAL (XEXP (x, 1));
5298 unsigned mode_mask = GET_MODE_MASK (inner_mode);
5299 unsigned op_significant = significant_bits (XEXP (x, 0), mode);
5300 unsigned inner = op_significant & mode_mask;
5303 if (mode_width > width)
5304 outer = (op_significant & significant & ~ mode_mask);
5306 if (code == LSHIFTRT)
5308 else if (code == ASHIFTRT)
5312 /* If the sign bit was significant at before the shift, we
5313 need to mark all the places it could have been copied to
5314 by the shift significant. */
5315 if (inner & (1 << (width - 1 - count)))
5316 inner |= ((1 << count) - 1) << (width - count);
5318 else if (code == LSHIFT || code == ASHIFT)
5321 inner = ((inner << (count % width)
5322 | (inner >> (width - (count % width)))) & mode_mask);
5324 significant &= (outer | inner);
5329 /* This is at most the number of bits in the mode. */
5330 significant = (1 << (floor_log2 (mode_width) + 1)) - 1;
5337 /* This function is called from `simplify_shift_const' to merge two
5338 outer operations. Specifically, we have already found that we need
5339 to perform operation *POP0 with constant *PCONST0 at the outermost
5340 position. We would now like to also perform OP1 with constant CONST1
5341 (with *POP0 being done last).
5343 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
5344 the resulting operation. *PCOMP_P is set to 1 if we would need to
5345 complement the innermost operand, otherwise it is unchanged.
5347 MODE is the mode in which the operation will be done. No bits outside
5348 the width of this mode matter. It is assumed that the width of this mode
5349 is smaller than or equal to HOST_BITS_PER_INT.
5351 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
5352 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
5353 result is simply *PCONST0.
5355 If the resulting operation cannot be expressed as one operation, we
5356 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
5359 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
5360 enum rtx_code *pop0;
5364 enum machine_mode mode;
5367 enum rtx_code op0 = *pop0;
5368 int const0 = *pconst0;
5370 const0 &= GET_MODE_MASK (mode);
5371 const1 &= GET_MODE_MASK (mode);
5373 /* If OP0 is an AND, clear unimportant bits in CONST1. */
5377 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
5380 if (op1 == NIL || op0 == SET)
5383 else if (op0 == NIL)
5384 op0 = op1, const0 = const1;
5386 else if (op0 == op1)
5408 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
5409 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
5412 /* If the two constants aren't the same, we can't do anything. The
5413 remaining six cases can all be done. */
5414 else if (const0 != const1)
5422 /* (a & b) | b == b */
5424 else /* op1 == XOR */
5425 /* (a ^ b) | b == a | b */
5431 /* (a & b) ^ b == (~a) & b */
5432 op0 = AND, *pcomp_p = 1;
5433 else /* op1 == IOR */
5434 /* (a | b) ^ b == a & ~b */
5435 op0 = AND, *pconst0 = ~ const0;
5440 /* (a | b) & b == b */
5442 else /* op1 == XOR */
5443 /* (a ^ b) & b) == (~a) & b */
5448 /* Check for NO-OP cases. */
5449 const0 &= GET_MODE_MASK (mode);
5451 && (op0 == IOR || op0 == XOR || op0 == PLUS))
5453 else if (const0 == 0 && op0 == AND)
5455 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
5464 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
5465 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
5466 that we started with.
5468 The shift is normally computed in the widest mode we find in VAROP, as
5469 long as it isn't a different number of words than RESULT_MODE. Exceptions
5470 are ASHIFTRT and ROTATE, which are always done in their original mode, */
5473 simplify_shift_const (x, code, result_mode, varop, count)
5476 enum machine_mode result_mode;
5480 enum rtx_code orig_code = code;
5481 int orig_count = count;
5482 enum machine_mode mode = result_mode;
5483 enum machine_mode shift_mode, tmode;
5485 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
5486 /* We form (outer_op (code varop count) (outer_const)). */
5487 enum rtx_code outer_op = NIL;
5490 int complement_p = 0;
5493 /* If we were given an invalid count, don't do anything except exactly
5494 what was requested. */
5496 if (count < 0 || count > GET_MODE_BITSIZE (mode))
5501 return gen_rtx (code, mode, varop, gen_rtx (CONST_INT, VOIDmode, count));
5504 /* Unless one of the branches of the `if' in this loop does a `continue',
5505 we will `break' the loop after the `if'. */
5509 /* If we have an operand of (clobber (const_int 0)), just return that
5511 if (GET_CODE (varop) == CLOBBER)
5514 /* If we discovered we had to complement VAROP, leave. Making a NOT
5515 here would cause an infinite loop. */
5519 /* Convert ROTATETRT to ROTATE. */
5520 if (code == ROTATERT)
5521 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
5523 /* Canonicalize LSHIFT to ASHIFT. */
5527 /* We need to determine what mode we will do the shift in. If the
5528 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
5529 was originally done in. Otherwise, we can do it in MODE, the widest
5530 mode encountered. */
5531 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
5533 /* Handle cases where the count is greater than the size of the mode
5534 minus 1. For ASHIFT, use the size minus one as the count (this can
5535 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
5536 take the count modulo the size. For other shifts, the result is
5539 Since these shifts are being produced by the compiler by combining
5540 multiple operations, each of which are defined, we know what the
5541 result is supposed to be. */
5543 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
5545 if (code == ASHIFTRT)
5546 count = GET_MODE_BITSIZE (shift_mode) - 1;
5547 else if (code == ROTATE || code == ROTATERT)
5548 count %= GET_MODE_BITSIZE (shift_mode);
5551 /* We can't simply return zero because there may be an
5559 /* Negative counts are invalid and should not have been made (a
5560 programmer-specified negative count should have been handled
5565 /* We simplify the tests below and elsewhere by converting
5566 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
5567 `make_compound_operation' will convert it to a ASHIFTRT for
5568 those machines (such as Vax) that don't have a LSHIFTRT. */
5569 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_INT
5571 && (significant_bits (varop, shift_mode)
5572 & (1 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0)
5575 switch (GET_CODE (varop))
5581 new = expand_compound_operation (varop);
5590 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
5591 minus the width of a smaller mode, we can do this with a
5592 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
5593 if ((code == ASHIFTRT || code == LSHIFTRT)
5594 && ! mode_dependent_address_p (XEXP (varop, 0))
5595 && ! MEM_VOLATILE_P (varop)
5596 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5597 MODE_INT, 1)) != BLKmode)
5599 #if BYTES_BIG_ENDIAN
5600 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
5602 new = gen_rtx (MEM, tmode,
5603 plus_constant (XEXP (varop, 0),
5604 count / BITS_PER_UNIT));
5605 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
5606 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
5607 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
5609 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5610 : ZERO_EXTEND, mode, new);
5617 /* Similar to the case above, except that we can only do this if
5618 the resulting mode is the same as that of the underlying
5619 MEM and adjust the address depending on the *bits* endianness
5620 because of the way that bit-field extract insns are defined. */
5621 if ((code == ASHIFTRT || code == LSHIFTRT)
5622 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5623 MODE_INT, 1)) != BLKmode
5624 && tmode == GET_MODE (XEXP (varop, 0)))
5627 new = XEXP (varop, 0);
5629 new = copy_rtx (XEXP (varop, 0));
5630 SUBST (XEXP (new, 0),
5631 plus_constant (XEXP (new, 0),
5632 count / BITS_PER_UNIT));
5635 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5636 : ZERO_EXTEND, mode, new);
5643 /* If VAROP is a SUBREG, strip it as long as the inner operand has
5644 the same number of words as what we've seen so far. Then store
5645 the widest mode in MODE. */
5646 if (SUBREG_WORD (varop) == 0
5647 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
5648 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5651 varop = SUBREG_REG (varop);
5652 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
5653 mode = GET_MODE (varop);
5659 /* Some machines use MULT instead of ASHIFT because MULT
5660 is cheaper. But it is still better on those machines to
5661 merge two shifts into one. */
5662 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5663 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5665 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5666 gen_rtx (CONST_INT, VOIDmode,
5667 exact_log2 (INTVAL (XEXP (varop, 1)))));
5673 /* Similar, for when divides are cheaper. */
5674 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5675 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5677 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5678 gen_rtx (CONST_INT, VOIDmode,
5679 exact_log2 (INTVAL (XEXP (varop, 1)))));
5685 /* If we are extracting just the sign bit of an arithmetic right
5686 shift, that shift is not needed. */
5687 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
5689 varop = XEXP (varop, 0);
5693 /* ... fall through ... */
5699 /* Here we have two nested shifts. The result is usually the
5700 AND of a new shift with a mask. We compute the result below. */
5701 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5702 && INTVAL (XEXP (varop, 1)) >= 0
5703 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5704 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5705 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
5707 enum rtx_code first_code = GET_CODE (varop);
5708 int first_count = INTVAL (XEXP (varop, 1));
5713 if (first_code == LSHIFT)
5714 first_code = ASHIFT;
5716 /* We have one common special case. We can't do any merging if
5717 the inner code is an ASHIFTRT of a smaller mode. However, if
5718 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
5719 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
5720 we can convert it to
5721 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
5722 This simplifies certain SIGN_EXTEND operations. */
5723 if (code == ASHIFT && first_code == ASHIFTRT
5724 && (GET_MODE_BITSIZE (result_mode)
5725 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
5727 /* C3 has the low-order C1 bits zero. */
5729 mask = GET_MODE_MASK (mode) & ~ ((1 << first_count) - 1);
5731 varop = simplify_and_const_int (0, result_mode,
5732 XEXP (varop, 0), mask);
5733 varop = simplify_shift_const (0, ASHIFT, result_mode,
5735 count = first_count;
5740 /* If this was (ashiftrt (ashift foo C1) C2) and we know
5741 something about FOO's previous value, we may be able to
5742 optimize this even though the code below can't handle this
5745 If FOO has J high-order bits equal to the sign bit with
5746 J > C1, then we can convert this to either an ASHIFT or
5747 a ASHIFTRT depending on the two counts.
5749 We cannot do this if VAROP's mode is not SHIFT_MODE. */
5751 if (code == ASHIFTRT && first_code == ASHIFT
5752 && GET_MODE (varop) == shift_mode
5753 && (inner = get_last_value (XEXP (varop, 0))) != 0)
5755 if ((GET_CODE (inner) == CONST_INT
5756 && (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == 0
5757 || (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == -1)))
5758 || (GET_CODE (inner) == SIGN_EXTEND
5759 && ((GET_MODE_BITSIZE (GET_MODE (inner))
5760 - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner))))
5762 || (GET_CODE (inner) == ASHIFTRT
5763 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5764 && INTVAL (XEXP (inner, 1)) >= first_count))
5766 count -= first_count;
5768 count = - count, code = ASHIFT;
5769 varop = XEXP (varop, 0);
5774 /* There are some cases we can't do. If CODE is ASHIFTRT,
5775 we can only do this if FIRST_CODE is also ASHIFTRT.
5777 We can't do the case when CODE is ROTATE and FIRST_CODE is
5780 If the mode of this shift is not the mode of the outer shift,
5781 we can't do this if either shift is ASHIFTRT or ROTATE.
5783 Finally, we can't do any of these if the mode is too wide
5784 unless the codes are the same.
5786 Handle the case where the shift codes are the same
5789 if (code == first_code)
5791 if (GET_MODE (varop) != result_mode
5792 && (code == ASHIFTRT || code == ROTATE))
5795 count += first_count;
5796 varop = XEXP (varop, 0);
5800 if (code == ASHIFTRT
5801 || (code == ROTATE && first_code == ASHIFTRT)
5802 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_INT
5803 || (GET_MODE (varop) != result_mode
5804 && (first_code == ASHIFTRT || first_code == ROTATE
5805 || code == ROTATE)))
5808 /* To compute the mask to apply after the shift, shift the
5809 significant bits of the inner shift the same way the
5810 outer shift will. */
5812 mask_rtx = gen_rtx (CONST_INT, VOIDmode,
5813 significant_bits (varop, GET_MODE (varop)));
5816 = simplify_binary_operation (code, result_mode, mask_rtx,
5817 gen_rtx (CONST_INT, VOIDmode,
5820 /* Give up if we can't compute an outer operation to use. */
5822 || GET_CODE (mask_rtx) != CONST_INT
5823 || ! merge_outer_ops (&outer_op, &outer_const, AND,
5825 result_mode, &complement_p))
5828 /* If the shifts are in the same direction, we add the
5829 counts. Otherwise, we subtract them. */
5830 if ((code == ASHIFTRT || code == LSHIFTRT)
5831 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
5832 count += first_count;
5834 count -= first_count;
5836 /* If COUNT is positive, the new shift is usually CODE,
5837 except for the two exceptions below, in which case it is
5838 FIRST_CODE. If the count is negative, FIRST_CODE should
5841 && ((first_code == ROTATE && code == ASHIFT)
5842 || (first_code == ASHIFTRT && code == LSHIFTRT)))
5845 code = first_code, count = - count;
5847 varop = XEXP (varop, 0);
5851 /* If we have (A << B << C) for any shift, we can convert this to
5852 (A << C << B). This wins if A is a constant. Only try this if
5853 B is not a constant. */
5855 else if (GET_CODE (varop) == code
5856 && GET_CODE (XEXP (varop, 1)) != CONST_INT
5858 = simplify_binary_operation (code, mode,
5864 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
5871 /* Make this fit the case below. */
5872 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5873 gen_rtx (CONST_INT, VOIDmode,
5874 GET_MODE_MASK (mode)));
5880 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
5881 with C the size of VAROP - 1 and the shift is logical if
5882 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5883 we have an (le X 0) operation. If we have an arithmetic shift
5884 and STORE_FLAG_VALUE is 1 or we have a logical shift with
5885 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
5887 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
5888 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
5889 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5890 && (code == LSHIFTRT || code == ASHIFTRT)
5891 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
5892 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
5895 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
5898 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
5899 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
5904 /* If we have (shift (logical)), move the logical to the outside
5905 to allow it to possibly combine with another logical and the
5906 shift to combine with another shift. This also canonicalizes to
5907 what a ZERO_EXTRACT looks like. Also, some machines have
5908 (and (shift)) insns. */
5910 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5911 && (new = simplify_binary_operation (code, result_mode,
5916 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
5917 INTVAL (new), result_mode, &complement_p))
5919 varop = XEXP (varop, 0);
5923 /* If we can't do that, try to simplify the shift in each arm of the
5924 logical expression, make a new logical expression, and apply
5925 the inverse distributive law. */
5927 rtx lhs = simplify_shift_const (0, code, result_mode,
5928 XEXP (varop, 0), count);
5929 rtx rhs = simplify_shift_const (0, code, result_mode,
5930 XEXP (varop, 1), count);
5932 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
5933 varop = apply_distributive_law (varop);
5940 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
5941 says that the sign bit can be tested, FOO has mode MODE, C is
5942 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
5945 && XEXP (varop, 1) == const0_rtx
5946 && GET_MODE (XEXP (varop, 0)) == result_mode
5947 && count == GET_MODE_BITSIZE (result_mode) - 1
5948 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5949 && ((STORE_FLAG_VALUE
5950 & (1 << (GET_MODE_BITSIZE (result_mode) - 1))))
5951 && significant_bits (XEXP (varop, 0), result_mode) == 1
5952 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
5953 result_mode, &complement_p))
5955 varop = XEXP (varop, 0);
5962 /* If we are doing an arithmetic right shift of something known
5963 to be -1 or 0, we don't need the shift. */
5964 if (code == ASHIFTRT
5965 && significant_bits (XEXP (varop, 0), result_mode) == 1)
5971 /* NEG commutes with ASHIFT since it is multiplication. Move the
5972 NEG outside to allow shifts to combine. */
5974 && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
5975 result_mode, &complement_p))
5977 varop = XEXP (varop, 0);
5983 /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */
5984 if (XEXP (varop, 1) == constm1_rtx && code == ASHIFTRT
5985 && significant_bits (XEXP (varop, 0), result_mode) == 1)
5991 /* If we have the same operands as above but we are shifting the
5992 sign bit into the low-order bit, we are exclusive-or'ing
5993 the operand of the PLUS with a one. */
5994 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
5995 && XEXP (varop, 1) == constm1_rtx
5996 && significant_bits (XEXP (varop, 0), result_mode) == 1
5997 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
5998 result_mode, &complement_p))
6001 varop = XEXP (varop, 0);
6005 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
6007 && GET_CODE (XEXP (varop, 1)) == CONST_INT
6008 && (new = simplify_binary_operation (ASHIFT, result_mode,
6013 && merge_outer_ops (&outer_op, &outer_const, PLUS,
6014 INTVAL (new), result_mode, &complement_p))
6016 varop = XEXP (varop, 0);
6022 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
6023 with C the size of VAROP - 1 and the shift is logical if
6024 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
6025 we have a (gt X 0) operation. If the shift is arithmetic with
6026 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
6027 we have a (neg (gt X 0)) operation. */
6029 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
6030 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
6031 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6032 && (code == LSHIFTRT || code == ASHIFTRT)
6033 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6034 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
6035 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
6038 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
6041 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
6042 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
6052 /* We need to determine what mode to do the shift in. If the shift is
6053 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
6054 done in. Otherwise, we can do it in MODE, the widest mode encountered.
6055 The code we care about is that of the shift that will actually be done,
6056 not the shift that was originally requested. */
6057 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6059 /* We have now finished analyzing the shift. The result should be
6060 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
6061 OUTER_OP is non-NIL, it is an operation that needs to be applied
6062 to the result of the shift. OUTER_CONST is the relevant constant,
6063 but we must turn off all bits turned off in the shift.
6065 If we were passed a value for X, see if we can use any pieces of
6066 it. If not, make new rtx. */
6068 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
6069 && GET_CODE (XEXP (x, 1)) == CONST_INT
6070 && INTVAL (XEXP (x, 1)) == count)
6071 const_rtx = XEXP (x, 1);
6073 const_rtx = gen_rtx (CONST_INT, VOIDmode, count);
6075 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6076 && GET_MODE (XEXP (x, 0)) == shift_mode
6077 && SUBREG_REG (XEXP (x, 0)) == varop)
6078 varop = XEXP (x, 0);
6079 else if (GET_MODE (varop) != shift_mode)
6080 varop = gen_lowpart_for_combine (shift_mode, varop);
6082 /* If we can't make the SUBREG, try to return what we were given. */
6083 if (GET_CODE (varop) == CLOBBER)
6084 return x ? x : varop;
6086 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
6091 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
6092 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
6094 SUBST (XEXP (x, 0), varop);
6095 SUBST (XEXP (x, 1), const_rtx);
6098 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
6099 turn off all the bits that the shift would have turned off. */
6100 if (orig_code == LSHIFTRT && result_mode != shift_mode)
6101 x = simplify_and_const_int (0, shift_mode, x,
6102 GET_MODE_MASK (result_mode) >> orig_count);
6104 /* Do the remainder of the processing in RESULT_MODE. */
6105 x = gen_lowpart_for_combine (result_mode, x);
6107 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
6110 x = gen_unary (NOT, result_mode, x);
6112 if (outer_op != NIL)
6114 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_INT)
6115 outer_const &= GET_MODE_MASK (result_mode);
6117 if (outer_op == AND)
6118 x = simplify_and_const_int (0, result_mode, x, outer_const);
6119 else if (outer_op == SET)
6120 /* This means that we have determined that the result is
6121 equivalent to a constant. This should be rare. */
6122 x = gen_rtx (CONST_INT, VOIDmode, outer_const);
6123 else if (GET_RTX_CLASS (outer_op) == '1')
6124 x = gen_unary (outer_op, result_mode, x);
6126 x = gen_binary (outer_op, result_mode, x,
6127 gen_rtx (CONST_INT, VOIDmode, outer_const));
6133 /* Like recog, but we receive the address of a pointer to a new pattern.
6134 We try to match the rtx that the pointer points to.
6135 If that fails, we may try to modify or replace the pattern,
6136 storing the replacement into the same pointer object.
6138 Modifications include deletion or addition of CLOBBERs.
6140 PNOTES is a pointer to a location where any REG_UNUSED notes added for
6141 the CLOBBERs are placed.
6143 The value is the final insn code from the pattern ultimately matched,
6147 recog_for_combine (pnewpat, insn, pnotes)
6152 register rtx pat = *pnewpat;
6153 int insn_code_number;
6154 int num_clobbers_to_add = 0;
6158 /* Is the result of combination a valid instruction? */
6159 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6161 /* If it isn't, there is the possibility that we previously had an insn
6162 that clobbered some register as a side effect, but the combined
6163 insn doesn't need to do that. So try once more without the clobbers
6164 unless this represents an ASM insn. */
6166 if (insn_code_number < 0 && ! check_asm_operands (pat)
6167 && GET_CODE (pat) == PARALLEL)
6171 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
6172 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
6175 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
6179 SUBST_INT (XVECLEN (pat, 0), pos);
6182 pat = XVECEXP (pat, 0, 0);
6184 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6187 /* If we had any clobbers to add, make a new pattern than contains
6188 them. Then check to make sure that all of them are dead. */
6189 if (num_clobbers_to_add)
6191 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
6192 gen_rtvec (GET_CODE (pat) == PARALLEL
6193 ? XVECLEN (pat, 0) + num_clobbers_to_add
6194 : num_clobbers_to_add + 1));
6196 if (GET_CODE (pat) == PARALLEL)
6197 for (i = 0; i < XVECLEN (pat, 0); i++)
6198 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
6200 XVECEXP (newpat, 0, 0) = pat;
6202 add_clobbers (newpat, insn_code_number);
6204 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
6205 i < XVECLEN (newpat, 0); i++)
6207 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
6208 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
6210 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
6211 XEXP (XVECEXP (newpat, 0, i), 0), notes);
6219 return insn_code_number;
6222 /* Like gen_lowpart but for use by combine. In combine it is not possible
6223 to create any new pseudoregs. However, it is safe to create
6224 invalid memory addresses, because combine will try to recognize
6225 them and all they will do is make the combine attempt fail.
6227 If for some reason this cannot do its job, an rtx
6228 (clobber (const_int 0)) is returned.
6229 An insn containing that will not be recognized. */
6234 gen_lowpart_for_combine (mode, x)
6235 enum machine_mode mode;
6240 if (GET_MODE (x) == mode)
6243 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
6244 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6246 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
6247 won't know what to do. So we will strip off the SUBREG here and
6248 process normally. */
6249 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
6252 if (GET_MODE (x) == mode)
6256 result = gen_lowpart_common (mode, x);
6260 if (GET_CODE (x) == MEM)
6262 register int offset = 0;
6265 /* Refuse to work on a volatile memory ref or one with a mode-dependent
6267 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
6268 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6270 /* If we want to refer to something bigger than the original memref,
6271 generate a perverse subreg instead. That will force a reload
6272 of the original memref X. */
6273 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
6274 return gen_rtx (SUBREG, mode, x, 0);
6276 #if WORDS_BIG_ENDIAN
6277 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
6278 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
6280 #if BYTES_BIG_ENDIAN
6281 /* Adjust the address so that the address-after-the-data
6283 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
6284 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
6286 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
6287 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
6288 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
6289 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
6293 /* If X is a comparison operator, rewrite it in a new mode. This
6294 probably won't match, but may allow further simplifications. */
6295 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
6296 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
6298 /* If we couldn't simplify X any other way, just enclose it in a
6299 SUBREG. Normally, this SUBREG won't match, but some patterns may
6300 include an explicit SUBREG or we may simplify it further in combine. */
6305 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
6306 word = ((GET_MODE_SIZE (GET_MODE (x))
6307 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
6309 return gen_rtx (SUBREG, mode, x, word);
6313 /* Make an rtx expression. This is a subset of gen_rtx and only supports
6314 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
6316 If the identical expression was previously in the insn (in the undobuf),
6317 it will be returned. Only if it is not found will a new expression
6322 gen_rtx_combine (va_alist)
6327 enum machine_mode mode;
6335 code = va_arg (p, enum rtx_code);
6336 mode = va_arg (p, enum machine_mode);
6337 n_args = GET_RTX_LENGTH (code);
6338 fmt = GET_RTX_FORMAT (code);
6340 if (n_args == 0 || n_args > 3)
6343 /* Get each arg and verify that it is supposed to be an expression. */
6344 for (j = 0; j < n_args; j++)
6349 args[j] = va_arg (p, rtx);
6352 /* See if this is in undobuf. Be sure we don't use objects that came
6353 from another insn; this could produce circular rtl structures. */
6355 for (i = previous_num_undos; i < undobuf.num_undo; i++)
6356 if (!undobuf.undo[i].is_int
6357 && GET_CODE (undobuf.undo[i].old_contents) == code
6358 && GET_MODE (undobuf.undo[i].old_contents) == mode)
6360 for (j = 0; j < n_args; j++)
6361 if (XEXP (undobuf.undo[i].old_contents, j) != args[j])
6365 return undobuf.undo[i].old_contents;
6368 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
6369 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
6370 rt = rtx_alloc (code);
6371 PUT_MODE (rt, mode);
6372 XEXP (rt, 0) = args[0];
6375 XEXP (rt, 1) = args[1];
6377 XEXP (rt, 2) = args[2];
6382 /* These routines make binary and unary operations by first seeing if they
6383 fold; if not, a new expression is allocated. */
6386 gen_binary (code, mode, op0, op1)
6388 enum machine_mode mode;
6393 if (GET_RTX_CLASS (code) == '<')
6395 enum machine_mode op_mode = GET_MODE (op0);
6396 if (op_mode == VOIDmode)
6397 op_mode = GET_MODE (op1);
6398 result = simplify_relational_operation (code, op_mode, op0, op1);
6401 result = simplify_binary_operation (code, mode, op0, op1);
6406 /* Put complex operands first and constants second. */
6407 if (GET_RTX_CLASS (code) == 'c'
6408 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
6409 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
6410 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
6411 || (GET_CODE (op0) == SUBREG
6412 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
6413 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
6414 return gen_rtx_combine (code, mode, op1, op0);
6416 return gen_rtx_combine (code, mode, op0, op1);
6420 gen_unary (code, mode, op0)
6422 enum machine_mode mode;
6425 rtx result = simplify_unary_operation (code, mode, op0, mode);
6430 return gen_rtx_combine (code, mode, op0);
6433 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
6434 comparison code that will be tested.
6436 The result is a possibly different comparison code to use. *POP0 and
6437 *POP1 may be updated.
6439 It is possible that we might detect that a comparison is either always
6440 true or always false. However, we do not perform general constant
6441 folding in combine, so this knowledge isn't useful. Such tautologies
6442 should have been detected earlier. Hence we ignore all such cases. */
6444 static enum rtx_code
6445 simplify_comparison (code, pop0, pop1)
6454 enum machine_mode mode, tmode;
6456 /* Try a few ways of applying the same transformation to both operands. */
6459 /* If both operands are the same constant shift, see if we can ignore the
6460 shift. We can if the shift is a rotate or if the bits shifted out of
6461 this shift are not significant for either input and if the type of
6462 comparison is compatible with the shift. */
6463 if (GET_CODE (op0) == GET_CODE (op1)
6464 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6465 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
6466 || ((GET_CODE (op0) == LSHIFTRT
6467 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6468 && (code != GT && code != LT && code != GE && code != LE))
6469 || (GET_CODE (op0) == ASHIFTRT
6470 && (code != GTU && code != LTU
6471 && code != GEU && code != GEU)))
6472 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6473 && INTVAL (XEXP (op0, 1)) >= 0
6474 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
6475 && XEXP (op0, 1) == XEXP (op1, 1))
6477 enum machine_mode mode = GET_MODE (op0);
6478 unsigned mask = GET_MODE_MASK (mode);
6479 int shift_count = INTVAL (XEXP (op0, 1));
6481 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
6482 mask &= (mask >> shift_count) << shift_count;
6483 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6484 mask = (mask & (mask << shift_count)) >> shift_count;
6486 if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
6487 && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
6488 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
6493 /* If both operands are AND's of a paradoxical SUBREG by constant, the
6494 SUBREGs are of the same mode, and, in both cases, the AND would
6495 be redundant if the comparison was done in the narrower mode,
6496 do the comparison in the narrower mode (e.g., we are AND'ing with 1
6497 and the operand's significant bits are 0xffffff01; in that case if
6498 we only care about QImode, we don't need the AND). This case occurs
6499 if the output mode of an scc insn is not SImode and
6500 STORE_FLAG_VALUE == 1 (e.g., the 386). */
6502 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
6503 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6504 && GET_CODE (XEXP (op1, 1)) == CONST_INT
6505 && GET_CODE (XEXP (op0, 0)) == SUBREG
6506 && GET_CODE (XEXP (op1, 0)) == SUBREG
6507 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
6508 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
6509 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
6510 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6511 && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
6512 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
6513 & ~ INTVAL (XEXP (op0, 1))) == 0
6514 && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
6515 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6516 & ~ INTVAL (XEXP (op1, 1))) == 0)
6518 op0 = SUBREG_REG (XEXP (op0, 0));
6519 op1 = SUBREG_REG (XEXP (op1, 0));
6521 /* the resulting comparison is always unsigned since we masked off
6522 the original sign bit. */
6523 code = unsigned_condition (code);
6529 /* If the first operand is a constant, swap the operands and adjust the
6530 comparison code appropriately. */
6531 if (CONSTANT_P (op0))
6533 tem = op0, op0 = op1, op1 = tem;
6534 code = swap_condition (code);
6537 /* We now enter a loop during which we will try to simplify the comparison.
6538 For the most part, we only are concerned with comparisons with zero,
6539 but some things may really be comparisons with zero but not start
6540 out looking that way. */
6542 while (GET_CODE (op1) == CONST_INT)
6544 enum machine_mode mode = GET_MODE (op0);
6545 int mode_width = GET_MODE_BITSIZE (mode);
6546 unsigned mask = GET_MODE_MASK (mode);
6547 int equality_comparison_p;
6548 int sign_bit_comparison_p;
6549 int unsigned_comparison_p;
6552 /* We only want to handle integral modes. This catches VOIDmode,
6553 CCmode, and the floating-point modes. An exception is that we
6554 can handle VOIDmode if OP0 is a COMPARE or a comparison
6557 if (GET_MODE_CLASS (mode) != MODE_INT
6558 && ! (mode == VOIDmode
6559 && (GET_CODE (op0) == COMPARE
6560 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
6563 /* Get the constant we are comparing against and turn off all bits
6564 not on in our mode. */
6565 const_op = INTVAL (op1);
6566 if (mode_width <= HOST_BITS_PER_INT)
6567 const_op &= GET_MODE_MASK (mode);
6569 /* If we are comparing against a constant power of two and the value
6570 being compared has only that single significant bit (e.g., it was
6571 `and'ed with that bit), we can replace this with a comparison
6574 && (code == EQ || code == NE || code == GE || code == GEU
6575 || code == LT || code == LTU)
6576 && mode_width <= HOST_BITS_PER_INT
6577 && exact_log2 (const_op) >= 0
6578 && significant_bits (op0, mode) == const_op)
6580 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
6581 op1 = const0_rtx, const_op = 0;
6584 /* Do some canonicalizations based on the comparison code. We prefer
6585 comparisons against zero and then prefer equality comparisons. */
6590 /* < 1 is equivalent to <= 0 */
6596 /* ... fall through to LE case below. */
6602 /* <= -1 is equivalent to < 0 */
6603 if (op1 == constm1_rtx)
6604 op1 = const0_rtx, const_op = 0, code = LT;
6606 /* If we are doing a <= 0 comparison on a value known to have
6607 a zero sign bit, we can replace this with == 0. */
6608 else if (const_op == 0
6609 && mode_width <= HOST_BITS_PER_INT
6610 && (significant_bits (op0, mode)
6611 & (1 << (mode_width - 1))) == 0)
6616 /* >= 1 is equivalent to > 0. */
6622 /* ... fall through to GT below. */
6628 /* > -1 is equivalent to >= 0. */
6629 if (op1 == constm1_rtx)
6630 op1 = const0_rtx, const_op = 0, code = GE;
6632 /* If we are doing a > 0 comparison on a value known to have
6633 a zero sign bit, we can replace this with != 0. */
6634 else if (const_op == 0
6635 && mode_width <= HOST_BITS_PER_INT
6636 && (significant_bits (op0, mode)
6637 & (1 << (mode_width - 1))) == 0)
6642 /* unsigned >= 1 is equivalent to != 0 */
6644 op1 = const0_rtx, const_op = 0, code = NE;
6648 /* unsigned < 1 is equivalent to == 0 */
6650 op1 = const0_rtx, const_op = 0, code = EQ;
6654 /* unsigned <= 0 is equivalent to == 0 */
6660 /* unsigned > 0 is equivalent to != 0 */
6666 /* Compute some predicates to simplify code below. */
6668 equality_comparison_p = (code == EQ || code == NE);
6669 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
6670 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
6673 /* Now try cases based on the opcode of OP0. If none of the cases
6674 does a "continue", we exit this loop immediately after the
6677 switch (GET_CODE (op0))
6680 /* If we are extracting a single bit from a variable position in
6681 a constant that has only a single bit set and are comparing it
6682 with zero, we can convert this into an equality comparison
6683 between the position and the location of the single bit. We can't
6684 do this if bit endian and we don't have an extzv since we then
6685 can't know what mode to use for the endianness adjustment. */
6687 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
6688 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
6689 && XEXP (op0, 1) == const1_rtx
6690 && equality_comparison_p && const_op == 0
6691 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
6694 i = (GET_MODE_BITSIZE
6695 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
6698 op0 = XEXP (op0, 2);
6699 op1 = gen_rtx (CONST_INT, VOIDmode, i);
6702 /* Result is nonzero iff shift count is equal to I. */
6703 code = reverse_condition (code);
6708 /* ... fall through ... */
6711 tem = expand_compound_operation (op0);
6720 /* If testing for equality, we can take the NOT of the constant. */
6721 if (equality_comparison_p
6722 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
6724 op0 = XEXP (op0, 0);
6729 /* If just looking at the sign bit, reverse the sense of the
6731 if (sign_bit_comparison_p)
6733 op0 = XEXP (op0, 0);
6734 code = (code == GE ? LT : GE);
6740 /* If testing for equality, we can take the NEG of the constant. */
6741 if (equality_comparison_p
6742 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
6744 op0 = XEXP (op0, 0);
6749 /* The remaining cases only apply to comparisons with zero. */
6753 /* When X is ABS or is known positive,
6754 (neg X) is < 0 if and only if X != 0. */
6756 if (sign_bit_comparison_p
6757 && (GET_CODE (XEXP (op0, 0)) == ABS
6758 || (mode_width <= HOST_BITS_PER_INT
6759 && (significant_bits (XEXP (op0, 0), mode)
6760 & (1 << (mode_width - 1))) == 0)))
6762 op0 = XEXP (op0, 0);
6763 code = (code == LT ? NE : EQ);
6767 /* If we have NEG of something that is the result of a
6768 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
6769 two high-order bits must be the same and hence that
6770 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
6772 if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
6773 || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
6774 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6775 && (INTVAL (XEXP (XEXP (op0, 0), 1))
6776 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
6777 || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6778 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6779 && XEXP (XEXP (op0, 0), 1) != const0_rtx)
6780 || ((tem = get_last_value (XEXP (op0, 0))) != 0
6781 && (GET_CODE (tem) == SIGN_EXTEND
6782 || (GET_CODE (tem) == SIGN_EXTRACT
6783 && GET_CODE (XEXP (tem, 1)) == CONST_INT
6784 && (INTVAL (XEXP (tem, 1))
6785 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
6786 || (GET_CODE (tem) == ASHIFTRT
6787 && GET_CODE (XEXP (tem, 1)) == CONST_INT
6788 && XEXP (tem, 1) != const0_rtx))))
6790 op0 = XEXP (op0, 0);
6791 code = swap_condition (code);
6797 /* If we are testing equality and our count is a constant, we
6798 can perform the inverse operation on our RHS. */
6799 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6800 && (tem = simplify_binary_operation (ROTATERT, mode,
6801 op1, XEXP (op0, 1))) != 0)
6803 op0 = XEXP (op0, 0);
6808 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
6809 a particular bit. Convert it to an AND of a constant of that
6810 bit. This will be converted into a ZERO_EXTRACT. */
6811 if (const_op == 0 && sign_bit_comparison_p
6812 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6813 && mode_width <= HOST_BITS_PER_INT)
6815 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
6816 1 << (mode_width - 1
6817 - INTVAL (XEXP (op0, 1))));
6818 code = (code == LT ? NE : EQ);
6822 /* ... fall through ... */
6825 /* ABS is ignorable inside an equality comparison with zero. */
6826 if (const_op == 0 && equality_comparison_p)
6828 op0 = XEXP (op0, 0);
6835 /* Can simplify (compare (zero/sign_extend FOO) CONST)
6836 to (compare FOO CONST) if CONST fits in FOO's mode and we
6837 are either testing inequality or have an unsigned comparison
6838 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
6839 if (! unsigned_comparison_p
6840 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6841 <= HOST_BITS_PER_INT)
6842 && ((unsigned) const_op
6843 < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))
6845 op0 = XEXP (op0, 0);
6851 /* If the inner mode is smaller and we are extracting the low
6852 part, we can treat the SUBREG as if it were a ZERO_EXTEND. */
6853 if (! subreg_lowpart_p (op0)
6854 || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) >= mode_width)
6857 /* ... fall through ... */
6860 if ((unsigned_comparison_p || equality_comparison_p)
6861 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6862 <= HOST_BITS_PER_INT)
6863 && ((unsigned) const_op
6864 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
6866 op0 = XEXP (op0, 0);
6872 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
6873 this for equality comparisons due to pathological cases involving
6875 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6876 && (tem = simplify_binary_operation (MINUS, mode, op1,
6877 XEXP (op0, 1))) != 0)
6879 op0 = XEXP (op0, 0);
6884 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
6885 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
6886 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
6888 op0 = XEXP (XEXP (op0, 0), 0);
6889 code = (code == LT ? EQ : NE);
6895 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
6896 of bits in X minus 1, is one iff X > 0. */
6897 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6898 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6899 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
6900 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
6902 op0 = XEXP (op0, 1);
6903 code = (code == GE ? LE : GT);
6909 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
6910 if C is zero or B is a constant. */
6911 if (equality_comparison_p
6912 && 0 != (tem = simplify_binary_operation (XOR, mode,
6913 XEXP (op0, 1), op1)))
6915 op0 = XEXP (op0, 0);
6922 case LT: case LTU: case LE: case LEU:
6923 case GT: case GTU: case GE: case GEU:
6924 /* We can't do anything if OP0 is a condition code value, rather
6925 than an actual data value. */
6928 || XEXP (op0, 0) == cc0_rtx
6930 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
6933 /* Get the two operands being compared. */
6934 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
6935 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
6937 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
6939 /* Check for the cases where we simply want the result of the
6940 earlier test or the opposite of that result. */
6942 || (code == EQ && reversible_comparison_p (op0))
6943 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6944 && (STORE_FLAG_VALUE
6945 & (1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))
6947 || (code == GE && reversible_comparison_p (op0)))))
6949 code = (code == LT || code == NE
6950 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
6951 op0 = tem, op1 = tem1;
6957 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
6959 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
6960 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
6961 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
6963 op0 = XEXP (op0, 1);
6964 code = (code == GE ? GT : LE);
6970 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
6971 will be converted to a ZERO_EXTRACT later. */
6972 if (const_op == 0 && equality_comparison_p
6973 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
6974 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
6975 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
6977 op0 = simplify_and_const_int
6978 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
6980 XEXP (XEXP (op0, 0), 1)),
6985 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
6986 zero and X is a comparison and C1 and C2 describe only bits set
6987 in STORE_FLAG_VALUE, we can compare with X. */
6988 if (const_op == 0 && equality_comparison_p
6989 && mode_width <= HOST_BITS_PER_INT
6990 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6991 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
6992 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6993 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
6994 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_INT)
6996 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
6997 << INTVAL (XEXP (XEXP (op0, 0), 1)));
6998 if ((~ STORE_FLAG_VALUE & mask) == 0
6999 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
7000 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
7001 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
7003 op0 = XEXP (XEXP (op0, 0), 0);
7008 /* If we are doing an equality comparison of an AND of a bit equal
7009 to the sign bit, replace this with a LT or GE comparison of
7010 the underlying value. */
7011 if (equality_comparison_p
7013 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7014 && mode_width <= HOST_BITS_PER_INT
7015 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
7016 == 1 << (mode_width - 1)))
7018 op0 = XEXP (op0, 0);
7019 code = (code == EQ ? GE : LT);
7023 /* If this AND operation is really a ZERO_EXTEND from a narrower
7024 mode, the constant fits within that mode, and this is either an
7025 equality or unsigned comparison, try to do this comparison in
7026 the narrower mode. */
7027 if ((equality_comparison_p || unsigned_comparison_p)
7028 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7029 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
7030 & GET_MODE_MASK (mode))
7032 && const_op >> i == 0
7033 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
7035 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
7042 /* If we have (compare (xshift FOO N) (const_int C)) and
7043 the high order N bits of FOO (N+1 if an inequality comparison)
7044 are not significant, we can do this by comparing FOO with C
7045 shifted right N bits so long as the low-order N bits of C are
7047 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7048 && INTVAL (XEXP (op0, 1)) >= 0
7049 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
7050 < HOST_BITS_PER_INT)
7051 && (const_op & ~ ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7052 && mode_width <= HOST_BITS_PER_INT
7053 && (significant_bits (XEXP (op0, 0), mode)
7054 & ~ (mask >> (INTVAL (XEXP (op0, 1))
7055 + ! equality_comparison_p))) == 0)
7057 const_op >>= INTVAL (XEXP (op0, 1));
7058 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7059 op0 = XEXP (op0, 0);
7063 /* If we are doing a sign bit comparison, it means we are testing
7064 a particular bit. Convert it to the appropriate AND. */
7065 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
7066 && mode_width <= HOST_BITS_PER_INT)
7068 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
7069 1 << ( mode_width - 1
7070 - INTVAL (XEXP (op0, 1))));
7071 code = (code == LT ? NE : EQ);
7075 /* If this an equality comparison with zero and we are shifting
7076 the low bit to the sign bit, we can convert this to an AND of the
7078 if (const_op == 0 && equality_comparison_p
7079 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7080 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7082 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), 1);
7088 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
7089 do the comparison in a narrower mode. */
7090 if (! unsigned_comparison_p
7091 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7092 && GET_CODE (XEXP (op0, 0)) == ASHIFT
7093 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
7094 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
7095 MODE_INT, 1)) != VOIDmode
7096 && ((unsigned) const_op <= GET_MODE_MASK (tmode)
7097 || (unsigned) - const_op <= GET_MODE_MASK (tmode)))
7099 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
7103 /* ... fall through ... */
7105 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
7106 the low order N bits of FOO are not significant, we can do this
7107 by comparing FOO with C shifted left N bits so long as no
7109 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7110 && INTVAL (XEXP (op0, 1)) >= 0
7111 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
7112 && mode_width <= HOST_BITS_PER_INT
7113 && (significant_bits (XEXP (op0, 0), mode)
7114 & ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7116 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
7119 const_op <<= INTVAL (XEXP (op0, 1));
7120 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7121 op0 = XEXP (op0, 0);
7125 /* If we are using this shift to extract just the sign bit, we
7126 can replace this with an LT or GE comparison. */
7128 && (equality_comparison_p || sign_bit_comparison_p)
7129 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7130 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7132 op0 = XEXP (op0, 0);
7133 code = (code == NE || code == GT ? LT : GE);
7142 /* Now make any compound operations involved in this comparison. Then,
7143 check for an outmost SUBREG on OP0 that isn't doing anything or is
7144 paradoxical. The latter case can only occur when it is known that the
7145 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
7146 We can never remove a SUBREG for a non-equality comparison because the
7147 sign bit is in a different place in the underlying object. */
7149 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
7150 op1 = make_compound_operation (op1, SET);
7152 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7153 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7154 && (code == NE || code == EQ)
7155 && ((GET_MODE_SIZE (GET_MODE (op0))
7156 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
7158 op0 = SUBREG_REG (op0);
7159 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
7162 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7163 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7164 && (code == NE || code == EQ)
7165 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
7166 && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
7167 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
7168 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
7170 (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
7171 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
7172 op0 = SUBREG_REG (op0), op1 = tem;
7174 /* We now do the opposite procedure: Some machines don't have compare
7175 insns in all modes. If OP0's mode is an integer mode smaller than a
7176 word and we can't do a compare in that mode, see if there is a larger
7177 mode for which we can do the compare and where the only significant
7178 bits in OP0 and OP1 are those in the narrower mode. We can do
7179 this if this is an equality comparison, in which case we can
7180 merely widen the operation, or if we are testing the sign bit, in
7181 which case we can explicitly put in the test. */
7183 mode = GET_MODE (op0);
7184 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
7185 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
7186 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
7187 for (tmode = GET_MODE_WIDER_MODE (mode);
7188 tmode != VOIDmode && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_INT;
7189 tmode = GET_MODE_WIDER_MODE (tmode))
7190 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing
7191 && (significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
7192 && (significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0
7193 && (code == EQ || code == NE
7194 || (op1 == const0_rtx && (code == LT || code == GE)
7195 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)))
7197 op0 = gen_lowpart_for_combine (tmode, op0);
7198 op1 = gen_lowpart_for_combine (tmode, op1);
7200 if (code == LT || code == GE)
7202 op0 = gen_binary (AND, tmode, op0,
7203 gen_rtx (CONST_INT, VOIDmode,
7204 1 << (GET_MODE_BITSIZE (mode) - 1)));
7205 code = (code == LT) ? NE : EQ;
7217 /* Return 1 if we know that X, a comparison operation, is not operating
7218 on a floating-point value or is EQ or NE, meaning that we can safely
7222 reversible_comparison_p (x)
7225 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7226 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
7229 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
7235 x = get_last_value (XEXP (x, 0));
7236 return (x && GET_CODE (x) == COMPARE
7237 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
7243 /* Utility function for following routine. Called when X is part of a value
7244 being stored into reg_last_set_value. Sets reg_last_set_table_tick
7245 for each register mentioned. Similar to mention_regs in cse.c */
7248 update_table_tick (x)
7251 register enum rtx_code code = GET_CODE (x);
7252 register char *fmt = GET_RTX_FORMAT (code);
7257 int regno = REGNO (x);
7258 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7259 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7261 for (i = regno; i < endregno; i++)
7262 reg_last_set_table_tick[i] = label_tick;
7267 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7268 /* Note that we can't have an "E" in values stored; see
7269 get_last_value_validate. */
7271 update_table_tick (XEXP (x, i));
7274 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
7275 are saying that the register is clobbered and we no longer know its
7276 value. If INSN is zero, don't update reg_last_set; this call is normally
7277 done with VALUE also zero to invalidate the register. */
7280 record_value_for_reg (reg, insn, value)
7285 int regno = REGNO (reg);
7286 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7287 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
7290 /* If VALUE contains REG and we have a previous value for REG, substitute
7291 the previous value. */
7292 if (value && insn && reg_overlap_mentioned_p (reg, value))
7296 /* Set things up so get_last_value is allowed to see anything set up to
7298 subst_low_cuid = INSN_CUID (insn);
7299 tem = get_last_value (reg);
7302 value = replace_rtx (copy_rtx (value), reg, tem);
7305 /* For each register modified, show we don't know its value, that
7306 its value has been updated, and that we don't know the location of
7307 the death of the register. */
7308 for (i = regno; i < endregno; i ++)
7311 reg_last_set[i] = insn;
7312 reg_last_set_value[i] = 0;
7313 reg_last_death[i] = 0;
7316 /* Mark registers that are being referenced in this value. */
7318 update_table_tick (value);
7320 /* Now update the status of each register being set.
7321 If someone is using this register in this block, set this register
7322 to invalid since we will get confused between the two lives in this
7323 basic block. This makes using this register always invalid. In cse, we
7324 scan the table to invalidate all entries using this register, but this
7325 is too much work for us. */
7327 for (i = regno; i < endregno; i++)
7329 reg_last_set_label[i] = label_tick;
7330 if (value && reg_last_set_table_tick[i] == label_tick)
7331 reg_last_set_invalid[i] = 1;
7333 reg_last_set_invalid[i] = 0;
7336 /* The value being assigned might refer to X (like in "x++;"). In that
7337 case, we must replace it with (clobber (const_int 0)) to prevent
7339 if (value && ! get_last_value_validate (&value,
7340 reg_last_set_label[regno], 0))
7342 value = copy_rtx (value);
7343 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
7347 /* For the main register being modified, update the value. */
7348 reg_last_set_value[regno] = value;
7352 /* Used for communication between the following two routines. */
7353 static rtx record_dead_insn;
7355 /* Called via note_stores from record_dead_and_set_regs to handle one
7356 SET or CLOBBER in an insn. */
7359 record_dead_and_set_regs_1 (dest, setter)
7362 if (GET_CODE (dest) == REG)
7364 /* If we are setting the whole register, we know its value. Otherwise
7365 show that we don't know the value. We can handle SUBREG in
7367 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
7368 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
7369 else if (GET_CODE (setter) == SET
7370 && GET_CODE (SET_DEST (setter)) == SUBREG
7371 && SUBREG_REG (SET_DEST (setter)) == dest
7372 && subreg_lowpart_p (SET_DEST (setter)))
7373 record_value_for_reg
7374 (dest, record_dead_insn,
7375 gen_lowpart_for_combine (GET_MODE (SET_DEST (setter)),
7378 record_value_for_reg (dest, record_dead_insn, 0);
7380 else if (GET_CODE (dest) == MEM
7381 /* Ignore pushes, they clobber nothing. */
7382 && ! push_operand (dest, GET_MODE (dest)))
7383 mem_last_set = INSN_CUID (record_dead_insn);
7386 /* Update the records of when each REG was most recently set or killed
7387 for the things done by INSN. This is the last thing done in processing
7388 INSN in the combiner loop.
7390 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
7391 similar information mem_last_set (which insn most recently modified memory)
7392 and last_call_cuid (which insn was the most recent subroutine call). */
7395 record_dead_and_set_regs (insn)
7399 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7401 if (REG_NOTE_KIND (link) == REG_DEAD)
7402 reg_last_death[REGNO (XEXP (link, 0))] = insn;
7403 else if (REG_NOTE_KIND (link) == REG_INC)
7404 record_value_for_reg (XEXP (link, 0), insn, 0);
7407 if (GET_CODE (insn) == CALL_INSN)
7408 last_call_cuid = mem_last_set = INSN_CUID (insn);
7410 record_dead_insn = insn;
7411 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
7414 /* Utility routine for the following function. Verify that all the registers
7415 mentioned in *LOC are valid when *LOC was part of a value set when
7416 label_tick == TICK. Return 0 if some are not.
7418 If REPLACE is non-zero, replace the invalid reference with
7419 (clobber (const_int 0)) and return 1. This replacement is useful because
7420 we often can get useful information about the form of a value (e.g., if
7421 it was produced by a shift that always produces -1 or 0) even though
7422 we don't know exactly what registers it was produced from. */
7425 get_last_value_validate (loc, tick, replace)
7431 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
7432 int len = GET_RTX_LENGTH (GET_CODE (x));
7435 if (GET_CODE (x) == REG)
7437 int regno = REGNO (x);
7438 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7439 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7442 for (j = regno; j < endregno; j++)
7443 if (reg_last_set_invalid[j]
7444 /* If this is a pseudo-register that was only set once, it is
7446 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
7447 && reg_last_set_label[j] > tick))
7450 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7457 for (i = 0; i < len; i++)
7459 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
7460 /* Don't bother with these. They shouldn't occur anyway. */
7464 /* If we haven't found a reason for it to be invalid, it is valid. */
7468 /* Get the last value assigned to X, if known. Some registers
7469 in the value may be replaced with (clobber (const_int 0)) if their value
7470 is known longer known reliably. */
7479 /* If this is a non-paradoxical SUBREG, get the value of its operand and
7480 then convert it to the desired mode. If this is a paradoxical SUBREG,
7481 we cannot predict what values the "extra" bits might have. */
7482 if (GET_CODE (x) == SUBREG
7483 && subreg_lowpart_p (x)
7484 && (GET_MODE_SIZE (GET_MODE (x))
7485 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7486 && (value = get_last_value (SUBREG_REG (x))) != 0)
7487 return gen_lowpart_for_combine (GET_MODE (x), value);
7489 if (GET_CODE (x) != REG)
7493 value = reg_last_set_value[regno];
7495 /* If we don't have a value, it isn't for this basic block, or if it was
7496 set in a later insn that the ones we are processing, return 0. */
7499 || (reg_n_sets[regno] != 1
7500 && (reg_last_set_label[regno] != label_tick
7501 || INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)))
7504 /* If the value has all its register valid, return it. */
7505 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
7508 /* Otherwise, make a copy and replace any invalid register with
7509 (clobber (const_int 0)). If that fails for some reason, return 0. */
7511 value = copy_rtx (value);
7512 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
7518 /* Return nonzero if expression X refers to a REG or to memory
7519 that is set in an instruction more recent than FROM_CUID. */
7522 use_crosses_set_p (x, from_cuid)
7528 register enum rtx_code code = GET_CODE (x);
7532 register int regno = REGNO (x);
7533 #ifdef PUSH_ROUNDING
7534 /* Don't allow uses of the stack pointer to be moved,
7535 because we don't know whether the move crosses a push insn. */
7536 if (regno == STACK_POINTER_REGNUM)
7539 return (reg_last_set[regno]
7540 && INSN_CUID (reg_last_set[regno]) > from_cuid);
7543 if (code == MEM && mem_last_set > from_cuid)
7546 fmt = GET_RTX_FORMAT (code);
7548 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7553 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7554 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
7557 else if (fmt[i] == 'e'
7558 && use_crosses_set_p (XEXP (x, i), from_cuid))
7564 /* Define three variables used for communication between the following
7567 static int reg_dead_regno, reg_dead_endregno;
7568 static int reg_dead_flag;
7570 /* Function called via note_stores from reg_dead_at_p.
7572 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
7573 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
7576 reg_dead_at_p_1 (dest, x)
7580 int regno, endregno;
7582 if (GET_CODE (dest) != REG)
7585 regno = REGNO (dest);
7586 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7587 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
7589 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
7590 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
7593 /* Return non-zero if REG is known to be dead at INSN.
7595 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
7596 referencing REG, it is dead. If we hit a SET referencing REG, it is
7597 live. Otherwise, see if it is live or dead at the start of the basic
7601 reg_dead_at_p (reg, insn)
7607 /* Set variables for reg_dead_at_p_1. */
7608 reg_dead_regno = REGNO (reg);
7609 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
7610 ? HARD_REGNO_NREGS (reg_dead_regno,
7616 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
7617 beginning of function. */
7618 for (; insn && GET_CODE (insn) != CODE_LABEL;
7619 insn = prev_nonnote_insn (insn))
7621 note_stores (PATTERN (insn), reg_dead_at_p_1);
7623 return reg_dead_flag == 1 ? 1 : 0;
7625 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
7629 /* Get the basic block number that we were in. */
7634 for (block = 0; block < n_basic_blocks; block++)
7635 if (insn == basic_block_head[block])
7638 if (block == n_basic_blocks)
7642 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
7643 if (basic_block_live_at_start[block][i / HOST_BITS_PER_INT]
7644 & (1 << (i % HOST_BITS_PER_INT)))
7650 /* Remove register number REGNO from the dead registers list of INSN.
7652 Return the note used to record the death, if there was one. */
7655 remove_death (regno, insn)
7659 register rtx note = find_regno_note (insn, REG_DEAD, regno);
7662 remove_note (insn, note);
7667 /* For each register (hardware or pseudo) used within expression X, if its
7668 death is in an instruction with cuid between FROM_CUID (inclusive) and
7669 TO_INSN (exclusive), put a REG_DEAD note for that register in the
7670 list headed by PNOTES.
7672 This is done when X is being merged by combination into TO_INSN. These
7673 notes will then be distributed as needed. */
7676 move_deaths (x, from_cuid, to_insn, pnotes)
7683 register int len, i;
7684 register enum rtx_code code = GET_CODE (x);
7688 register int regno = REGNO (x);
7689 register rtx where_dead = reg_last_death[regno];
7691 if (where_dead && INSN_CUID (where_dead) >= from_cuid
7692 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
7694 rtx note = remove_death (regno, reg_last_death[regno]);
7696 /* It is possible for the call above to return 0. This can occur
7697 when reg_last_death points to I2 or I1 that we combined with.
7698 In that case make a new note. */
7702 XEXP (note, 1) = *pnotes;
7706 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
7712 else if (GET_CODE (x) == SET)
7714 rtx dest = SET_DEST (x);
7716 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
7718 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
7719 that accesses one word of a multi-word item, some
7720 piece of everything register in the expression is used by
7721 this insn, so remove any old death. */
7723 if (GET_CODE (dest) == ZERO_EXTRACT
7724 || GET_CODE (dest) == STRICT_LOW_PART
7725 || (GET_CODE (dest) == SUBREG
7726 && (((GET_MODE_SIZE (GET_MODE (dest))
7727 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
7728 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
7729 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
7731 move_deaths (dest, from_cuid, to_insn, pnotes);
7735 /* If this is some other SUBREG, we know it replaces the entire
7736 value, so use that as the destination. */
7737 if (GET_CODE (dest) == SUBREG)
7738 dest = SUBREG_REG (dest);
7740 /* If this is a MEM, adjust deaths of anything used in the address.
7741 For a REG (the only other possibility), the entire value is
7742 being replaced so the old value is not used in this insn. */
7744 if (GET_CODE (dest) == MEM)
7745 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
7749 else if (GET_CODE (x) == CLOBBER)
7752 len = GET_RTX_LENGTH (code);
7753 fmt = GET_RTX_FORMAT (code);
7755 for (i = 0; i < len; i++)
7760 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7761 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
7763 else if (fmt[i] == 'e')
7764 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
7768 /* Return 1 if X is the target of a bit-field assignment in BODY, the
7769 pattern of an insn. X must be a REG. */
7772 reg_bitfield_target_p (x, body)
7778 if (GET_CODE (body) == SET)
7780 rtx dest = SET_DEST (body);
7782 int regno, tregno, endregno, endtregno;
7784 if (GET_CODE (dest) == ZERO_EXTRACT)
7785 target = XEXP (dest, 0);
7786 else if (GET_CODE (dest) == STRICT_LOW_PART)
7787 target = SUBREG_REG (XEXP (dest, 0));
7791 if (GET_CODE (target) == SUBREG)
7792 target = SUBREG_REG (target);
7794 if (GET_CODE (target) != REG)
7797 tregno = REGNO (target), regno = REGNO (x);
7798 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
7801 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
7802 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
7804 return endregno > tregno && regno < endtregno;
7807 else if (GET_CODE (body) == PARALLEL)
7808 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
7809 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
7815 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
7816 as appropriate. I3 and I2 are the insns resulting from the combination
7817 insns including FROM (I2 may be zero).
7819 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
7820 not need REG_DEAD notes because they are being substituted for. This
7821 saves searching in the most common cases.
7823 Each note in the list is either ignored or placed on some insns, depending
7824 on the type of note. */
7827 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
7831 rtx elim_i2, elim_i1;
7833 rtx note, next_note;
7836 for (note = notes; note; note = next_note)
7838 rtx place = 0, place2 = 0;
7840 /* If this NOTE references a pseudo register, ensure it references
7841 the latest copy of that register. */
7842 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
7843 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
7844 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
7846 next_note = XEXP (note, 1);
7847 switch (REG_NOTE_KIND (note))
7850 /* If this register is set or clobbered in I3, put the note there
7851 unless there is one already. */
7852 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
7854 if (! (GET_CODE (XEXP (note, 0)) == REG
7855 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
7856 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
7859 /* Otherwise, if this register is used by I3, then this register
7860 now dies here, so we must put a REG_DEAD note here unless there
7862 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
7863 && ! (GET_CODE (XEXP (note, 0)) == REG
7864 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
7865 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
7867 PUT_REG_NOTE_KIND (note, REG_DEAD);
7875 /* These notes say something about results of an insn. We can
7876 only support them if they used to be on I3 in which case they
7877 remain on I3. Otherwise they are ignored. */
7878 if (from_insn == i3)
7883 case REG_NO_CONFLICT:
7885 /* These notes say something about how a register is used. They must
7886 be present on any use of the register in I2 or I3. */
7887 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
7890 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
7900 /* It is too much trouble to try to see if this note is still
7901 correct in all situations. It is better to simply delete it. */
7905 /* If the insn previously containing this note still exists,
7906 put it back where it was. Otherwise move it to the previous
7907 insn. Adjust the corresponding REG_LIBCALL note. */
7908 if (GET_CODE (from_insn) != NOTE)
7912 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, 0);
7913 place = prev_real_insn (from_insn);
7915 XEXP (tem, 0) = place;
7920 /* This is handled similarly to REG_RETVAL. */
7921 if (GET_CODE (from_insn) != NOTE)
7925 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, 0);
7926 place = next_real_insn (from_insn);
7928 XEXP (tem, 0) = place;
7933 /* If the register is used as an input in I3, it dies there.
7934 Similarly for I2, if it is non-zero and adjacent to I3.
7936 If the register is not used as an input in either I3 or I2
7937 and it is not one of the registers we were supposed to eliminate,
7938 there are two possibilities. We might have a non-adjacent I2
7939 or we might have somehow eliminated an additional register
7940 from a computation. For example, we might have had A & B where
7941 we discover that B will always be zero. In this case we will
7942 eliminate the reference to A.
7944 In both cases, we must search to see if we can find a previous
7945 use of A and put the death note there. */
7947 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
7949 else if (i2 != 0 && next_nonnote_insn (i2) == i3
7950 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
7953 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
7957 for (tem = prev_nonnote_insn (i3);
7958 tem && (GET_CODE (tem) == INSN
7959 || GET_CODE (tem) == CALL_INSN);
7960 tem = prev_nonnote_insn (tem))
7962 /* If the register is being set at TEM, see if that is all
7963 TEM is doing. If so, delete TEM. Otherwise, make this
7964 into a REG_UNUSED note instead. */
7965 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
7967 rtx set = single_set (tem);
7969 /* Verify that it was the set, and not a clobber that
7970 modified the register. */
7972 if (set != 0 && ! side_effects_p (SET_SRC (set))
7973 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
7975 /* Move the notes and links of TEM elsewhere.
7976 This might delete other dead insns recursively.
7977 First set the pattern to something that won't use
7980 PATTERN (tem) = pc_rtx;
7982 distribute_notes (REG_NOTES (tem), tem, tem, 0, 0, 0);
7983 distribute_links (LOG_LINKS (tem));
7985 PUT_CODE (tem, NOTE);
7986 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
7987 NOTE_SOURCE_FILE (tem) = 0;
7991 PUT_REG_NOTE_KIND (note, REG_UNUSED);
7993 /* If there isn't already a REG_UNUSED note, put one
7995 if (! find_regno_note (tem, REG_UNUSED,
7996 REGNO (XEXP (note, 0))))
8001 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
8008 /* If the register is set or already dead at PLACE, we needn't do
8009 anything with this note if it is still a REG_DEAD note.
8011 Note that we cannot use just `dead_or_set_p' here since we can
8012 convert an assignment to a register into a bit-field assignment.
8013 Therefore, we must also omit the note if the register is the
8014 target of a bitfield assignment. */
8016 if (place && REG_NOTE_KIND (note) == REG_DEAD)
8018 int regno = REGNO (XEXP (note, 0));
8020 if (dead_or_set_p (place, XEXP (note, 0))
8021 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
8023 /* Unless the register previously died in PLACE, clear
8024 reg_last_death. [I no longer understand why this is
8026 if (reg_last_death[regno] != place)
8027 reg_last_death[regno] = 0;
8031 reg_last_death[regno] = place;
8033 /* If this is a death note for a hard reg that is occupying
8034 multiple registers, ensure that we are still using all
8035 parts of the object. If we find a piece of the object
8036 that is unused, we must add a USE for that piece before
8037 PLACE and put the appropriate REG_DEAD note on it.
8039 An alternative would be to put a REG_UNUSED for the pieces
8040 on the insn that set the register, but that can't be done if
8041 it is not in the same block. It is simpler, though less
8042 efficient, to add the USE insns. */
8044 if (place && regno < FIRST_PSEUDO_REGISTER
8045 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
8048 = regno + HARD_REGNO_NREGS (regno,
8049 GET_MODE (XEXP (note, 0)));
8053 for (i = regno; i < endregno; i++)
8054 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
8056 rtx piece = gen_rtx (REG, word_mode, i);
8059 /* See if we already placed a USE note for this
8060 register in front of PLACE. */
8062 GET_CODE (PREV_INSN (p)) == INSN
8063 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
8065 if (rtx_equal_p (piece,
8066 XEXP (PATTERN (PREV_INSN (p)), 0)))
8075 = emit_insn_before (gen_rtx (USE, VOIDmode,
8078 REG_NOTES (use_insn)
8079 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
8080 REG_NOTES (use_insn));
8088 /* Put only REG_DEAD notes for pieces that are
8089 still used and that are not already dead or set. */
8091 for (i = regno; i < endregno; i++)
8093 rtx piece = gen_rtx (REG, word_mode, i);
8095 if (reg_referenced_p (piece, PATTERN (place))
8096 && ! dead_or_set_p (place, piece)
8097 && ! reg_bitfield_target_p (piece,
8099 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
8111 /* Any other notes should not be present at this point in the
8118 XEXP (note, 1) = REG_NOTES (place);
8119 REG_NOTES (place) = note;
8123 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
8124 XEXP (note, 0), REG_NOTES (place2));
8128 /* Similarly to above, distribute the LOG_LINKS that used to be present on
8129 I3, I2, and I1 to new locations. This is also called in one case to
8130 add a link pointing at I3 when I3's destination is changed. */
8133 distribute_links (links)
8136 rtx link, next_link;
8138 for (link = links; link; link = next_link)
8144 next_link = XEXP (link, 1);
8146 /* If the insn that this link points to is a NOTE or isn't a single
8147 set, ignore it. In the latter case, it isn't clear what we
8148 can do other than ignore the link, since we can't tell which
8149 register it was for. Such links wouldn't be used by combine
8152 It is not possible for the destination of the target of the link to
8153 have been changed by combine. The only potential of this is if we
8154 replace I3, I2, and I1 by I3 and I2. But in that case the
8155 destination of I2 also remains unchanged. */
8157 if (GET_CODE (XEXP (link, 0)) == NOTE
8158 || (set = single_set (XEXP (link, 0))) == 0)
8161 reg = SET_DEST (set);
8162 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
8163 || GET_CODE (reg) == SIGN_EXTRACT
8164 || GET_CODE (reg) == STRICT_LOW_PART)
8165 reg = XEXP (reg, 0);
8167 /* A LOG_LINK is defined as being placed on the first insn that uses
8168 a register and points to the insn that sets the register. Start
8169 searching at the next insn after the target of the link and stop
8170 when we reach a set of the register or the end of the basic block.
8172 Note that this correctly handles the link that used to point from
8173 I3 to I2. Also note that not much searching is typically done here
8174 since most links don't point very far away. */
8176 for (insn = NEXT_INSN (XEXP (link, 0));
8177 (insn && GET_CODE (insn) != CODE_LABEL
8178 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
8179 insn = NEXT_INSN (insn))
8180 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8181 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8183 if (reg_referenced_p (reg, PATTERN (insn)))
8188 /* If we found a place to put the link, place it there unless there
8189 is already a link to the same insn as LINK at that point. */
8195 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
8196 if (XEXP (link2, 0) == XEXP (link, 0))
8201 XEXP (link, 1) = LOG_LINKS (place);
8202 LOG_LINKS (place) = link;
8209 dump_combine_stats (file)
8214 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
8215 combine_attempts, combine_merges, combine_extras, combine_successes);
8219 dump_combine_total_stats (file)
8224 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
8225 total_attempts, total_merges, total_extras, total_successes);
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