1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
427 /* We'd like to catch as many invalid transformations here as
428 possible. Unfortunately, there are way too many mode changes
429 that are perfectly valid, so we'd waste too much effort for
430 little gain doing the checks here. Focus on catching invalid
431 transformations involving integer constants. */
432 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
433 && GET_CODE (newval) == CONST_INT)
435 /* Sanity check that we're replacing oldval with a CONST_INT
436 that is a valid sign-extension for the original mode. */
437 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
441 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
442 CONST_INT is not valid, because after the replacement, the
443 original mode would be gone. Unfortunately, we can't tell
444 when do_SUBST is called to replace the operand thereof, so we
445 perform this test on oldval instead, checking whether an
446 invalid replacement took place before we got here. */
447 if ((GET_CODE (oldval) == SUBREG
448 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
449 || (GET_CODE (oldval) == ZERO_EXTEND
450 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
455 buf = undobuf.frees, undobuf.frees = buf->next;
457 buf = (struct undo *) xmalloc (sizeof (struct undo));
461 buf->old_contents.r = oldval;
464 buf->next = undobuf.undos, undobuf.undos = buf;
467 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
469 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
470 for the value of a HOST_WIDE_INT value (including CONST_INT) is
474 do_SUBST_INT (into, newval)
475 unsigned int *into, newval;
478 unsigned int oldval = *into;
480 if (oldval == newval)
484 buf = undobuf.frees, undobuf.frees = buf->next;
486 buf = (struct undo *) xmalloc (sizeof (struct undo));
490 buf->old_contents.i = oldval;
493 buf->next = undobuf.undos, undobuf.undos = buf;
496 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
498 /* Main entry point for combiner. F is the first insn of the function.
499 NREGS is the first unused pseudo-reg number.
501 Return non-zero if the combiner has turned an indirect jump
502 instruction into a direct jump. */
504 combine_instructions (f, nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
525 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
527 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
529 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
532 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
534 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
536 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
537 reg_last_set_nonzero_bits
538 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
539 reg_last_set_sign_bit_copies
540 = (char *) xmalloc (nregs * sizeof (char));
542 init_reg_last_arrays ();
544 init_recog_no_volatile ();
546 /* Compute maximum uid value so uid_cuid can be allocated. */
548 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
549 if (INSN_UID (insn) > i)
552 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
555 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
557 /* Don't use reg_nonzero_bits when computing it. This can cause problems
558 when, for example, we have j <<= 1 in a loop. */
560 nonzero_sign_valid = 0;
562 /* Compute the mapping from uids to cuids.
563 Cuids are numbers assigned to insns, like uids,
564 except that cuids increase monotonically through the code.
566 Scan all SETs and see if we can deduce anything about what
567 bits are known to be zero for some registers and how many copies
568 of the sign bit are known to exist for those registers.
570 Also set any known values so that we can use it while searching
571 for what bits are known to be set. */
575 /* We need to initialize it here, because record_dead_and_set_regs may call
577 subst_prev_insn = NULL_RTX;
579 setup_incoming_promotions ();
581 refresh_blocks = sbitmap_alloc (n_basic_blocks);
582 sbitmap_zero (refresh_blocks);
585 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
587 uid_cuid[INSN_UID (insn)] = ++i;
593 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
595 record_dead_and_set_regs (insn);
598 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
599 if (REG_NOTE_KIND (links) == REG_INC)
600 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
605 if (GET_CODE (insn) == CODE_LABEL)
609 nonzero_sign_valid = 1;
611 /* Now scan all the insns in forward order. */
613 this_basic_block = -1;
617 init_reg_last_arrays ();
618 setup_incoming_promotions ();
620 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
624 /* If INSN starts a new basic block, update our basic block number. */
625 if (this_basic_block + 1 < n_basic_blocks
626 && BLOCK_HEAD (this_basic_block + 1) == insn)
629 if (GET_CODE (insn) == CODE_LABEL)
632 else if (INSN_P (insn))
634 /* See if we know about function return values before this
635 insn based upon SUBREG flags. */
636 check_promoted_subreg (insn, PATTERN (insn));
638 /* Try this insn with each insn it links back to. */
640 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
641 if ((next = try_combine (insn, XEXP (links, 0),
642 NULL_RTX, &new_direct_jump_p)) != 0)
645 /* Try each sequence of three linked insns ending with this one. */
647 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
649 rtx link = XEXP (links, 0);
651 /* If the linked insn has been replaced by a note, then there
652 is no point in pursuing this chain any further. */
653 if (GET_CODE (link) == NOTE)
656 for (nextlinks = LOG_LINKS (link);
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, link,
661 &new_direct_jump_p)) != 0)
666 /* Try to combine a jump insn that uses CC0
667 with a preceding insn that sets CC0, and maybe with its
668 logical predecessor as well.
669 This is how we make decrement-and-branch insns.
670 We need this special code because data flow connections
671 via CC0 do not get entered in LOG_LINKS. */
673 if (GET_CODE (insn) == JUMP_INSN
674 && (prev = prev_nonnote_insn (insn)) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev)))
678 if ((next = try_combine (insn, prev,
679 NULL_RTX, &new_direct_jump_p)) != 0)
682 for (nextlinks = LOG_LINKS (prev); nextlinks;
683 nextlinks = XEXP (nextlinks, 1))
684 if ((next = try_combine (insn, prev,
686 &new_direct_jump_p)) != 0)
690 /* Do the same for an insn that explicitly references CC0. */
691 if (GET_CODE (insn) == INSN
692 && (prev = prev_nonnote_insn (insn)) != 0
693 && GET_CODE (prev) == INSN
694 && sets_cc0_p (PATTERN (prev))
695 && GET_CODE (PATTERN (insn)) == SET
696 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
698 if ((next = try_combine (insn, prev,
699 NULL_RTX, &new_direct_jump_p)) != 0)
702 for (nextlinks = LOG_LINKS (prev); nextlinks;
703 nextlinks = XEXP (nextlinks, 1))
704 if ((next = try_combine (insn, prev,
706 &new_direct_jump_p)) != 0)
710 /* Finally, see if any of the insns that this insn links to
711 explicitly references CC0. If so, try this insn, that insn,
712 and its predecessor if it sets CC0. */
713 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
714 if (GET_CODE (XEXP (links, 0)) == INSN
715 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
716 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
717 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
718 && GET_CODE (prev) == INSN
719 && sets_cc0_p (PATTERN (prev))
720 && (next = try_combine (insn, XEXP (links, 0),
721 prev, &new_direct_jump_p)) != 0)
725 /* Try combining an insn with two different insns whose results it
727 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
728 for (nextlinks = XEXP (links, 1); nextlinks;
729 nextlinks = XEXP (nextlinks, 1))
730 if ((next = try_combine (insn, XEXP (links, 0),
732 &new_direct_jump_p)) != 0)
735 if (GET_CODE (insn) != NOTE)
736 record_dead_and_set_regs (insn);
744 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, this_basic_block,
745 BASIC_BLOCK (this_basic_block)->flags |= BB_DIRTY);
746 new_direct_jump_p |= purge_all_dead_edges (0);
747 delete_noop_moves (f);
749 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
750 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
751 | PROP_KILL_DEAD_CODE);
754 sbitmap_free (refresh_blocks);
755 free (reg_nonzero_bits);
756 free (reg_sign_bit_copies);
757 free (reg_last_death);
759 free (reg_last_set_value);
760 free (reg_last_set_table_tick);
761 free (reg_last_set_label);
762 free (reg_last_set_invalid);
763 free (reg_last_set_mode);
764 free (reg_last_set_nonzero_bits);
765 free (reg_last_set_sign_bit_copies);
769 struct undo *undo, *next;
770 for (undo = undobuf.frees; undo; undo = next)
778 total_attempts += combine_attempts;
779 total_merges += combine_merges;
780 total_extras += combine_extras;
781 total_successes += combine_successes;
783 nonzero_sign_valid = 0;
785 /* Make recognizer allow volatile MEMs again. */
788 return new_direct_jump_p;
791 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
794 init_reg_last_arrays ()
796 unsigned int nregs = combine_max_regno;
798 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
800 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
801 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
802 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
803 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
804 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
805 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
806 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
809 /* Set up any promoted values for incoming argument registers. */
812 setup_incoming_promotions ()
814 #ifdef PROMOTE_FUNCTION_ARGS
817 enum machine_mode mode;
819 rtx first = get_insns ();
821 #ifndef OUTGOING_REGNO
822 #define OUTGOING_REGNO(N) N
824 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
825 /* Check whether this register can hold an incoming pointer
826 argument. FUNCTION_ARG_REGNO_P tests outgoing register
827 numbers, so translate if necessary due to register windows. */
828 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
829 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
832 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
835 gen_rtx_CLOBBER (mode, const0_rtx)));
840 /* Called via note_stores. If X is a pseudo that is narrower than
841 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
843 If we are setting only a portion of X and we can't figure out what
844 portion, assume all bits will be used since we don't know what will
847 Similarly, set how many bits of X are known to be copies of the sign bit
848 at all locations in the function. This is the smallest number implied
852 set_nonzero_bits_and_sign_copies (x, set, data)
855 void *data ATTRIBUTE_UNUSED;
859 if (GET_CODE (x) == REG
860 && REGNO (x) >= FIRST_PSEUDO_REGISTER
861 /* If this register is undefined at the start of the file, we can't
862 say what its contents were. */
863 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
864 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
866 if (set == 0 || GET_CODE (set) == CLOBBER)
868 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
869 reg_sign_bit_copies[REGNO (x)] = 1;
873 /* If this is a complex assignment, see if we can convert it into a
874 simple assignment. */
875 set = expand_field_assignment (set);
877 /* If this is a simple assignment, or we have a paradoxical SUBREG,
878 set what we know about X. */
880 if (SET_DEST (set) == x
881 || (GET_CODE (SET_DEST (set)) == SUBREG
882 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
883 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
884 && SUBREG_REG (SET_DEST (set)) == x))
886 rtx src = SET_SRC (set);
888 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
889 /* If X is narrower than a word and SRC is a non-negative
890 constant that would appear negative in the mode of X,
891 sign-extend it for use in reg_nonzero_bits because some
892 machines (maybe most) will actually do the sign-extension
893 and this is the conservative approach.
895 ??? For 2.5, try to tighten up the MD files in this regard
896 instead of this kludge. */
898 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
899 && GET_CODE (src) == CONST_INT
901 && 0 != (INTVAL (src)
903 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
904 src = GEN_INT (INTVAL (src)
905 | ((HOST_WIDE_INT) (-1)
906 << GET_MODE_BITSIZE (GET_MODE (x))));
909 /* Don't call nonzero_bits if it cannot change anything. */
910 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
911 reg_nonzero_bits[REGNO (x)]
912 |= nonzero_bits (src, nonzero_bits_mode);
913 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
914 if (reg_sign_bit_copies[REGNO (x)] == 0
915 || reg_sign_bit_copies[REGNO (x)] > num)
916 reg_sign_bit_copies[REGNO (x)] = num;
920 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
921 reg_sign_bit_copies[REGNO (x)] = 1;
926 /* See if INSN can be combined into I3. PRED and SUCC are optionally
927 insns that were previously combined into I3 or that will be combined
928 into the merger of INSN and I3.
930 Return 0 if the combination is not allowed for any reason.
932 If the combination is allowed, *PDEST will be set to the single
933 destination of INSN and *PSRC to the single source, and this function
937 can_combine_p (insn, i3, pred, succ, pdest, psrc)
940 rtx pred ATTRIBUTE_UNUSED;
945 rtx set = 0, src, dest;
950 int all_adjacent = (succ ? (next_active_insn (insn) == succ
951 && next_active_insn (succ) == i3)
952 : next_active_insn (insn) == i3);
954 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
955 or a PARALLEL consisting of such a SET and CLOBBERs.
957 If INSN has CLOBBER parallel parts, ignore them for our processing.
958 By definition, these happen during the execution of the insn. When it
959 is merged with another insn, all bets are off. If they are, in fact,
960 needed and aren't also supplied in I3, they may be added by
961 recog_for_combine. Otherwise, it won't match.
963 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
966 Get the source and destination of INSN. If more than one, can't
969 if (GET_CODE (PATTERN (insn)) == SET)
970 set = PATTERN (insn);
971 else if (GET_CODE (PATTERN (insn)) == PARALLEL
972 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
974 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
976 rtx elt = XVECEXP (PATTERN (insn), 0, i);
978 switch (GET_CODE (elt))
980 /* This is important to combine floating point insns
983 /* Combining an isolated USE doesn't make sense.
984 We depend here on combinable_i3pat to reject them. */
985 /* The code below this loop only verifies that the inputs of
986 the SET in INSN do not change. We call reg_set_between_p
987 to verify that the REG in the USE does not change between
989 If the USE in INSN was for a pseudo register, the matching
990 insn pattern will likely match any register; combining this
991 with any other USE would only be safe if we knew that the
992 used registers have identical values, or if there was
993 something to tell them apart, e.g. different modes. For
994 now, we forgo such complicated tests and simply disallow
995 combining of USES of pseudo registers with any other USE. */
996 if (GET_CODE (XEXP (elt, 0)) == REG
997 && GET_CODE (PATTERN (i3)) == PARALLEL)
999 rtx i3pat = PATTERN (i3);
1000 int i = XVECLEN (i3pat, 0) - 1;
1001 unsigned int regno = REGNO (XEXP (elt, 0));
1005 rtx i3elt = XVECEXP (i3pat, 0, i);
1007 if (GET_CODE (i3elt) == USE
1008 && GET_CODE (XEXP (i3elt, 0)) == REG
1009 && (REGNO (XEXP (i3elt, 0)) == regno
1010 ? reg_set_between_p (XEXP (elt, 0),
1011 PREV_INSN (insn), i3)
1012 : regno >= FIRST_PSEUDO_REGISTER))
1019 /* We can ignore CLOBBERs. */
1024 /* Ignore SETs whose result isn't used but not those that
1025 have side-effects. */
1026 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1027 && ! side_effects_p (elt))
1030 /* If we have already found a SET, this is a second one and
1031 so we cannot combine with this insn. */
1039 /* Anything else means we can't combine. */
1045 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1046 so don't do anything with it. */
1047 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1056 set = expand_field_assignment (set);
1057 src = SET_SRC (set), dest = SET_DEST (set);
1059 /* Don't eliminate a store in the stack pointer. */
1060 if (dest == stack_pointer_rtx
1061 /* If we couldn't eliminate a field assignment, we can't combine. */
1062 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1063 /* Don't combine with an insn that sets a register to itself if it has
1064 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1065 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1066 /* Can't merge an ASM_OPERANDS. */
1067 || GET_CODE (src) == ASM_OPERANDS
1068 /* Can't merge a function call. */
1069 || GET_CODE (src) == CALL
1070 /* Don't eliminate a function call argument. */
1071 || (GET_CODE (i3) == CALL_INSN
1072 && (find_reg_fusage (i3, USE, dest)
1073 || (GET_CODE (dest) == REG
1074 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1075 && global_regs[REGNO (dest)])))
1076 /* Don't substitute into an incremented register. */
1077 || FIND_REG_INC_NOTE (i3, dest)
1078 || (succ && FIND_REG_INC_NOTE (succ, dest))
1080 /* Don't combine the end of a libcall into anything. */
1081 /* ??? This gives worse code, and appears to be unnecessary, since no
1082 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1083 use REG_RETVAL notes for noconflict blocks, but other code here
1084 makes sure that those insns don't disappear. */
1085 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1087 /* Make sure that DEST is not used after SUCC but before I3. */
1088 || (succ && ! all_adjacent
1089 && reg_used_between_p (dest, succ, i3))
1090 /* Make sure that the value that is to be substituted for the register
1091 does not use any registers whose values alter in between. However,
1092 If the insns are adjacent, a use can't cross a set even though we
1093 think it might (this can happen for a sequence of insns each setting
1094 the same destination; reg_last_set of that register might point to
1095 a NOTE). If INSN has a REG_EQUIV note, the register is always
1096 equivalent to the memory so the substitution is valid even if there
1097 are intervening stores. Also, don't move a volatile asm or
1098 UNSPEC_VOLATILE across any other insns. */
1100 && (((GET_CODE (src) != MEM
1101 || ! find_reg_note (insn, REG_EQUIV, src))
1102 && use_crosses_set_p (src, INSN_CUID (insn)))
1103 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1104 || GET_CODE (src) == UNSPEC_VOLATILE))
1105 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1106 better register allocation by not doing the combine. */
1107 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1108 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1109 /* Don't combine across a CALL_INSN, because that would possibly
1110 change whether the life span of some REGs crosses calls or not,
1111 and it is a pain to update that information.
1112 Exception: if source is a constant, moving it later can't hurt.
1113 Accept that special case, because it helps -fforce-addr a lot. */
1114 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1117 /* DEST must either be a REG or CC0. */
1118 if (GET_CODE (dest) == REG)
1120 /* If register alignment is being enforced for multi-word items in all
1121 cases except for parameters, it is possible to have a register copy
1122 insn referencing a hard register that is not allowed to contain the
1123 mode being copied and which would not be valid as an operand of most
1124 insns. Eliminate this problem by not combining with such an insn.
1126 Also, on some machines we don't want to extend the life of a hard
1129 if (GET_CODE (src) == REG
1130 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1131 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1132 /* Don't extend the life of a hard register unless it is
1133 user variable (if we have few registers) or it can't
1134 fit into the desired register (meaning something special
1136 Also avoid substituting a return register into I3, because
1137 reload can't handle a conflict with constraints of other
1139 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1140 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1143 else if (GET_CODE (dest) != CC0)
1146 /* Don't substitute for a register intended as a clobberable operand.
1147 Similarly, don't substitute an expression containing a register that
1148 will be clobbered in I3. */
1149 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1150 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1151 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1152 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1154 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1157 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1158 or not), reject, unless nothing volatile comes between it and I3 */
1160 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1162 /* Make sure succ doesn't contain a volatile reference. */
1163 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1166 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1167 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1171 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1172 to be an explicit register variable, and was chosen for a reason. */
1174 if (GET_CODE (src) == ASM_OPERANDS
1175 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1178 /* If there are any volatile insns between INSN and I3, reject, because
1179 they might affect machine state. */
1181 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1182 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1185 /* If INSN or I2 contains an autoincrement or autodecrement,
1186 make sure that register is not used between there and I3,
1187 and not already used in I3 either.
1188 Also insist that I3 not be a jump; if it were one
1189 and the incremented register were spilled, we would lose. */
1192 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1193 if (REG_NOTE_KIND (link) == REG_INC
1194 && (GET_CODE (i3) == JUMP_INSN
1195 || reg_used_between_p (XEXP (link, 0), insn, i3)
1196 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1201 /* Don't combine an insn that follows a CC0-setting insn.
1202 An insn that uses CC0 must not be separated from the one that sets it.
1203 We do, however, allow I2 to follow a CC0-setting insn if that insn
1204 is passed as I1; in that case it will be deleted also.
1205 We also allow combining in this case if all the insns are adjacent
1206 because that would leave the two CC0 insns adjacent as well.
1207 It would be more logical to test whether CC0 occurs inside I1 or I2,
1208 but that would be much slower, and this ought to be equivalent. */
1210 p = prev_nonnote_insn (insn);
1211 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1216 /* If we get here, we have passed all the tests and the combination is
1225 /* Check if PAT is an insn - or a part of it - used to set up an
1226 argument for a function in a hard register. */
1229 sets_function_arg_p (pat)
1235 switch (GET_CODE (pat))
1238 return sets_function_arg_p (PATTERN (pat));
1241 for (i = XVECLEN (pat, 0); --i >= 0;)
1242 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1248 inner_dest = SET_DEST (pat);
1249 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1250 || GET_CODE (inner_dest) == SUBREG
1251 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1252 inner_dest = XEXP (inner_dest, 0);
1254 return (GET_CODE (inner_dest) == REG
1255 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1256 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1265 /* LOC is the location within I3 that contains its pattern or the component
1266 of a PARALLEL of the pattern. We validate that it is valid for combining.
1268 One problem is if I3 modifies its output, as opposed to replacing it
1269 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1270 so would produce an insn that is not equivalent to the original insns.
1274 (set (reg:DI 101) (reg:DI 100))
1275 (set (subreg:SI (reg:DI 101) 0) <foo>)
1277 This is NOT equivalent to:
1279 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1280 (set (reg:DI 101) (reg:DI 100))])
1282 Not only does this modify 100 (in which case it might still be valid
1283 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1285 We can also run into a problem if I2 sets a register that I1
1286 uses and I1 gets directly substituted into I3 (not via I2). In that
1287 case, we would be getting the wrong value of I2DEST into I3, so we
1288 must reject the combination. This case occurs when I2 and I1 both
1289 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1290 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1291 of a SET must prevent combination from occurring.
1293 Before doing the above check, we first try to expand a field assignment
1294 into a set of logical operations.
1296 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1297 we place a register that is both set and used within I3. If more than one
1298 such register is detected, we fail.
1300 Return 1 if the combination is valid, zero otherwise. */
1303 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1309 rtx *pi3dest_killed;
1313 if (GET_CODE (x) == SET)
1315 rtx set = expand_field_assignment (x);
1316 rtx dest = SET_DEST (set);
1317 rtx src = SET_SRC (set);
1318 rtx inner_dest = dest;
1321 rtx inner_src = src;
1326 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1327 || GET_CODE (inner_dest) == SUBREG
1328 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1329 inner_dest = XEXP (inner_dest, 0);
1331 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1334 while (GET_CODE (inner_src) == STRICT_LOW_PART
1335 || GET_CODE (inner_src) == SUBREG
1336 || GET_CODE (inner_src) == ZERO_EXTRACT)
1337 inner_src = XEXP (inner_src, 0);
1339 /* If it is better that two different modes keep two different pseudos,
1340 avoid combining them. This avoids producing the following pattern
1342 (set (subreg:SI (reg/v:QI 21) 0)
1343 (lshiftrt:SI (reg/v:SI 20)
1345 If that were made, reload could not handle the pair of
1346 reg 20/21, since it would try to get any GENERAL_REGS
1347 but some of them don't handle QImode. */
1349 if (rtx_equal_p (inner_src, i2dest)
1350 && GET_CODE (inner_dest) == REG
1351 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1355 /* Check for the case where I3 modifies its output, as
1357 if ((inner_dest != dest
1358 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1359 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1361 /* This is the same test done in can_combine_p except we can't test
1362 all_adjacent; we don't have to, since this instruction will stay
1363 in place, thus we are not considering increasing the lifetime of
1366 Also, if this insn sets a function argument, combining it with
1367 something that might need a spill could clobber a previous
1368 function argument; the all_adjacent test in can_combine_p also
1369 checks this; here, we do a more specific test for this case. */
1371 || (GET_CODE (inner_dest) == REG
1372 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1373 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1374 GET_MODE (inner_dest))))
1375 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1378 /* If DEST is used in I3, it is being killed in this insn,
1379 so record that for later.
1380 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1381 STACK_POINTER_REGNUM, since these are always considered to be
1382 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1383 if (pi3dest_killed && GET_CODE (dest) == REG
1384 && reg_referenced_p (dest, PATTERN (i3))
1385 && REGNO (dest) != FRAME_POINTER_REGNUM
1386 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1387 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1389 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1390 && (REGNO (dest) != ARG_POINTER_REGNUM
1391 || ! fixed_regs [REGNO (dest)])
1393 && REGNO (dest) != STACK_POINTER_REGNUM)
1395 if (*pi3dest_killed)
1398 *pi3dest_killed = dest;
1402 else if (GET_CODE (x) == PARALLEL)
1406 for (i = 0; i < XVECLEN (x, 0); i++)
1407 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1408 i1_not_in_src, pi3dest_killed))
1415 /* Return 1 if X is an arithmetic expression that contains a multiplication
1416 and division. We don't count multiplications by powers of two here. */
1422 switch (GET_CODE (x))
1424 case MOD: case DIV: case UMOD: case UDIV:
1428 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1429 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1431 switch (GET_RTX_CLASS (GET_CODE (x)))
1433 case 'c': case '<': case '2':
1434 return contains_muldiv (XEXP (x, 0))
1435 || contains_muldiv (XEXP (x, 1));
1438 return contains_muldiv (XEXP (x, 0));
1446 /* Determine whether INSN can be used in a combination. Return nonzero if
1447 not. This is used in try_combine to detect early some cases where we
1448 can't perform combinations. */
1451 cant_combine_insn_p (insn)
1457 /* If this isn't really an insn, we can't do anything.
1458 This can occur when flow deletes an insn that it has merged into an
1459 auto-increment address. */
1460 if (! INSN_P (insn))
1463 /* Never combine loads and stores involving hard regs. The register
1464 allocator can usually handle such reg-reg moves by tying. If we allow
1465 the combiner to make substitutions of hard regs, we risk aborting in
1466 reload on machines that have SMALL_REGISTER_CLASSES.
1467 As an exception, we allow combinations involving fixed regs; these are
1468 not available to the register allocator so there's no risk involved. */
1470 set = single_set (insn);
1473 src = SET_SRC (set);
1474 dest = SET_DEST (set);
1475 if (GET_CODE (src) == SUBREG)
1476 src = SUBREG_REG (src);
1477 if (GET_CODE (dest) == SUBREG)
1478 dest = SUBREG_REG (dest);
1479 if (REG_P (src) && REG_P (dest)
1480 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (src)])
1482 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1483 && ! fixed_regs[REGNO (dest)])))
1489 /* Try to combine the insns I1 and I2 into I3.
1490 Here I1 and I2 appear earlier than I3.
1491 I1 can be zero; then we combine just I2 into I3.
1493 If we are combining three insns and the resulting insn is not recognized,
1494 try splitting it into two insns. If that happens, I2 and I3 are retained
1495 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1498 Return 0 if the combination does not work. Then nothing is changed.
1499 If we did the combination, return the insn at which combine should
1502 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1503 new direct jump instruction. */
1506 try_combine (i3, i2, i1, new_direct_jump_p)
1508 int *new_direct_jump_p;
1510 /* New patterns for I3 and I2, respectively. */
1511 rtx newpat, newi2pat = 0;
1512 int substed_i2 = 0, substed_i1 = 0;
1513 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1514 int added_sets_1, added_sets_2;
1515 /* Total number of SETs to put into I3. */
1517 /* Nonzero is I2's body now appears in I3. */
1519 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1520 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1521 /* Contains I3 if the destination of I3 is used in its source, which means
1522 that the old life of I3 is being killed. If that usage is placed into
1523 I2 and not in I3, a REG_DEAD note must be made. */
1524 rtx i3dest_killed = 0;
1525 /* SET_DEST and SET_SRC of I2 and I1. */
1526 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1527 /* PATTERN (I2), or a copy of it in certain cases. */
1529 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1530 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1531 int i1_feeds_i3 = 0;
1532 /* Notes that must be added to REG_NOTES in I3 and I2. */
1533 rtx new_i3_notes, new_i2_notes;
1534 /* Notes that we substituted I3 into I2 instead of the normal case. */
1535 int i3_subst_into_i2 = 0;
1536 /* Notes that I1, I2 or I3 is a MULT operation. */
1544 /* Exit early if one of the insns involved can't be used for
1546 if (cant_combine_insn_p (i3)
1547 || cant_combine_insn_p (i2)
1548 || (i1 && cant_combine_insn_p (i1))
1549 /* We also can't do anything if I3 has a
1550 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1553 /* ??? This gives worse code, and appears to be unnecessary, since no
1554 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1555 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1561 undobuf.other_insn = 0;
1563 /* Reset the hard register usage information. */
1564 CLEAR_HARD_REG_SET (newpat_used_regs);
1566 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1567 code below, set I1 to be the earlier of the two insns. */
1568 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1569 temp = i1, i1 = i2, i2 = temp;
1571 added_links_insn = 0;
1573 /* First check for one important special-case that the code below will
1574 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1575 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1576 we may be able to replace that destination with the destination of I3.
1577 This occurs in the common code where we compute both a quotient and
1578 remainder into a structure, in which case we want to do the computation
1579 directly into the structure to avoid register-register copies.
1581 Note that this case handles both multiple sets in I2 and also
1582 cases where I2 has a number of CLOBBER or PARALLELs.
1584 We make very conservative checks below and only try to handle the
1585 most common cases of this. For example, we only handle the case
1586 where I2 and I3 are adjacent to avoid making difficult register
1589 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1590 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1591 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1592 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1593 && GET_CODE (PATTERN (i2)) == PARALLEL
1594 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1595 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1596 below would need to check what is inside (and reg_overlap_mentioned_p
1597 doesn't support those codes anyway). Don't allow those destinations;
1598 the resulting insn isn't likely to be recognized anyway. */
1599 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1600 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1601 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1602 SET_DEST (PATTERN (i3)))
1603 && next_real_insn (i2) == i3)
1605 rtx p2 = PATTERN (i2);
1607 /* Make sure that the destination of I3,
1608 which we are going to substitute into one output of I2,
1609 is not used within another output of I2. We must avoid making this:
1610 (parallel [(set (mem (reg 69)) ...)
1611 (set (reg 69) ...)])
1612 which is not well-defined as to order of actions.
1613 (Besides, reload can't handle output reloads for this.)
1615 The problem can also happen if the dest of I3 is a memory ref,
1616 if another dest in I2 is an indirect memory ref. */
1617 for (i = 0; i < XVECLEN (p2, 0); i++)
1618 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1619 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1620 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1621 SET_DEST (XVECEXP (p2, 0, i))))
1624 if (i == XVECLEN (p2, 0))
1625 for (i = 0; i < XVECLEN (p2, 0); i++)
1626 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1627 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1628 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1633 subst_low_cuid = INSN_CUID (i2);
1635 added_sets_2 = added_sets_1 = 0;
1636 i2dest = SET_SRC (PATTERN (i3));
1638 /* Replace the dest in I2 with our dest and make the resulting
1639 insn the new pattern for I3. Then skip to where we
1640 validate the pattern. Everything was set up above. */
1641 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1642 SET_DEST (PATTERN (i3)));
1645 i3_subst_into_i2 = 1;
1646 goto validate_replacement;
1650 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1651 one of those words to another constant, merge them by making a new
1654 && (temp = single_set (i2)) != 0
1655 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1656 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1657 && GET_CODE (SET_DEST (temp)) == REG
1658 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1659 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1660 && GET_CODE (PATTERN (i3)) == SET
1661 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1662 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1663 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1664 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1665 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1667 HOST_WIDE_INT lo, hi;
1669 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1670 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1673 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1674 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1677 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1679 /* We don't handle the case of the target word being wider
1680 than a host wide int. */
1681 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1684 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1685 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1686 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1688 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1689 hi = INTVAL (SET_SRC (PATTERN (i3)));
1690 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1692 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1693 >> (HOST_BITS_PER_WIDE_INT - 1));
1695 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1697 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1698 (INTVAL (SET_SRC (PATTERN (i3)))));
1700 hi = lo < 0 ? -1 : 0;
1703 /* We don't handle the case of the higher word not fitting
1704 entirely in either hi or lo. */
1709 subst_low_cuid = INSN_CUID (i2);
1710 added_sets_2 = added_sets_1 = 0;
1711 i2dest = SET_DEST (temp);
1713 SUBST (SET_SRC (temp),
1714 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1716 newpat = PATTERN (i2);
1717 goto validate_replacement;
1721 /* If we have no I1 and I2 looks like:
1722 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1724 make up a dummy I1 that is
1727 (set (reg:CC X) (compare:CC Y (const_int 0)))
1729 (We can ignore any trailing CLOBBERs.)
1731 This undoes a previous combination and allows us to match a branch-and-
1734 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1735 && XVECLEN (PATTERN (i2), 0) >= 2
1736 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1737 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1739 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1740 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1741 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1742 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1743 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1744 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1746 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1747 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1752 /* We make I1 with the same INSN_UID as I2. This gives it
1753 the same INSN_CUID for value tracking. Our fake I1 will
1754 never appear in the insn stream so giving it the same INSN_UID
1755 as I2 will not cause a problem. */
1757 subst_prev_insn = i1
1758 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1759 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1762 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1763 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1764 SET_DEST (PATTERN (i1)));
1769 /* Verify that I2 and I1 are valid for combining. */
1770 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1771 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1777 /* Record whether I2DEST is used in I2SRC and similarly for the other
1778 cases. Knowing this will help in register status updating below. */
1779 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1780 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1781 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1783 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1785 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1787 /* Ensure that I3's pattern can be the destination of combines. */
1788 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1789 i1 && i2dest_in_i1src && i1_feeds_i3,
1796 /* See if any of the insns is a MULT operation. Unless one is, we will
1797 reject a combination that is, since it must be slower. Be conservative
1799 if (GET_CODE (i2src) == MULT
1800 || (i1 != 0 && GET_CODE (i1src) == MULT)
1801 || (GET_CODE (PATTERN (i3)) == SET
1802 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1805 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1806 We used to do this EXCEPT in one case: I3 has a post-inc in an
1807 output operand. However, that exception can give rise to insns like
1809 which is a famous insn on the PDP-11 where the value of r3 used as the
1810 source was model-dependent. Avoid this sort of thing. */
1813 if (!(GET_CODE (PATTERN (i3)) == SET
1814 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1815 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1816 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1817 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1818 /* It's not the exception. */
1821 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1822 if (REG_NOTE_KIND (link) == REG_INC
1823 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1825 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1832 /* See if the SETs in I1 or I2 need to be kept around in the merged
1833 instruction: whenever the value set there is still needed past I3.
1834 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1836 For the SET in I1, we have two cases: If I1 and I2 independently
1837 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1838 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1839 in I1 needs to be kept around unless I1DEST dies or is set in either
1840 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1841 I1DEST. If so, we know I1 feeds into I2. */
1843 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1846 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1847 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1849 /* If the set in I2 needs to be kept around, we must make a copy of
1850 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1851 PATTERN (I2), we are only substituting for the original I1DEST, not into
1852 an already-substituted copy. This also prevents making self-referential
1853 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1856 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1857 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1861 i2pat = copy_rtx (i2pat);
1865 /* Substitute in the latest insn for the regs set by the earlier ones. */
1867 maxreg = max_reg_num ();
1871 /* It is possible that the source of I2 or I1 may be performing an
1872 unneeded operation, such as a ZERO_EXTEND of something that is known
1873 to have the high part zero. Handle that case by letting subst look at
1874 the innermost one of them.
1876 Another way to do this would be to have a function that tries to
1877 simplify a single insn instead of merging two or more insns. We don't
1878 do this because of the potential of infinite loops and because
1879 of the potential extra memory required. However, doing it the way
1880 we are is a bit of a kludge and doesn't catch all cases.
1882 But only do this if -fexpensive-optimizations since it slows things down
1883 and doesn't usually win. */
1885 if (flag_expensive_optimizations)
1887 /* Pass pc_rtx so no substitutions are done, just simplifications.
1888 The cases that we are interested in here do not involve the few
1889 cases were is_replaced is checked. */
1892 subst_low_cuid = INSN_CUID (i1);
1893 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1897 subst_low_cuid = INSN_CUID (i2);
1898 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1903 /* Many machines that don't use CC0 have insns that can both perform an
1904 arithmetic operation and set the condition code. These operations will
1905 be represented as a PARALLEL with the first element of the vector
1906 being a COMPARE of an arithmetic operation with the constant zero.
1907 The second element of the vector will set some pseudo to the result
1908 of the same arithmetic operation. If we simplify the COMPARE, we won't
1909 match such a pattern and so will generate an extra insn. Here we test
1910 for this case, where both the comparison and the operation result are
1911 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1912 I2SRC. Later we will make the PARALLEL that contains I2. */
1914 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1915 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1916 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1917 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1919 #ifdef EXTRA_CC_MODES
1921 enum machine_mode compare_mode;
1924 newpat = PATTERN (i3);
1925 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1929 #ifdef EXTRA_CC_MODES
1930 /* See if a COMPARE with the operand we substituted in should be done
1931 with the mode that is currently being used. If not, do the same
1932 processing we do in `subst' for a SET; namely, if the destination
1933 is used only once, try to replace it with a register of the proper
1934 mode and also replace the COMPARE. */
1935 if (undobuf.other_insn == 0
1936 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1937 &undobuf.other_insn))
1938 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1940 != GET_MODE (SET_DEST (newpat))))
1942 unsigned int regno = REGNO (SET_DEST (newpat));
1943 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1945 if (regno < FIRST_PSEUDO_REGISTER
1946 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1947 && ! REG_USERVAR_P (SET_DEST (newpat))))
1949 if (regno >= FIRST_PSEUDO_REGISTER)
1950 SUBST (regno_reg_rtx[regno], new_dest);
1952 SUBST (SET_DEST (newpat), new_dest);
1953 SUBST (XEXP (*cc_use, 0), new_dest);
1954 SUBST (SET_SRC (newpat),
1955 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1958 undobuf.other_insn = 0;
1965 n_occurrences = 0; /* `subst' counts here */
1967 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1968 need to make a unique copy of I2SRC each time we substitute it
1969 to avoid self-referential rtl. */
1971 subst_low_cuid = INSN_CUID (i2);
1972 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1973 ! i1_feeds_i3 && i1dest_in_i1src);
1976 /* Record whether i2's body now appears within i3's body. */
1977 i2_is_used = n_occurrences;
1980 /* If we already got a failure, don't try to do more. Otherwise,
1981 try to substitute in I1 if we have it. */
1983 if (i1 && GET_CODE (newpat) != CLOBBER)
1985 /* Before we can do this substitution, we must redo the test done
1986 above (see detailed comments there) that ensures that I1DEST
1987 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1989 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1997 subst_low_cuid = INSN_CUID (i1);
1998 newpat = subst (newpat, i1dest, i1src, 0, 0);
2002 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2003 to count all the ways that I2SRC and I1SRC can be used. */
2004 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2005 && i2_is_used + added_sets_2 > 1)
2006 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2007 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2009 /* Fail if we tried to make a new register (we used to abort, but there's
2010 really no reason to). */
2011 || max_reg_num () != maxreg
2012 /* Fail if we couldn't do something and have a CLOBBER. */
2013 || GET_CODE (newpat) == CLOBBER
2014 /* Fail if this new pattern is a MULT and we didn't have one before
2015 at the outer level. */
2016 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2023 /* If the actions of the earlier insns must be kept
2024 in addition to substituting them into the latest one,
2025 we must make a new PARALLEL for the latest insn
2026 to hold additional the SETs. */
2028 if (added_sets_1 || added_sets_2)
2032 if (GET_CODE (newpat) == PARALLEL)
2034 rtvec old = XVEC (newpat, 0);
2035 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2036 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2037 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2038 sizeof (old->elem[0]) * old->num_elem);
2043 total_sets = 1 + added_sets_1 + added_sets_2;
2044 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2045 XVECEXP (newpat, 0, 0) = old;
2049 XVECEXP (newpat, 0, --total_sets)
2050 = (GET_CODE (PATTERN (i1)) == PARALLEL
2051 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2055 /* If there is no I1, use I2's body as is. We used to also not do
2056 the subst call below if I2 was substituted into I3,
2057 but that could lose a simplification. */
2059 XVECEXP (newpat, 0, --total_sets) = i2pat;
2061 /* See comment where i2pat is assigned. */
2062 XVECEXP (newpat, 0, --total_sets)
2063 = subst (i2pat, i1dest, i1src, 0, 0);
2067 /* We come here when we are replacing a destination in I2 with the
2068 destination of I3. */
2069 validate_replacement:
2071 /* Note which hard regs this insn has as inputs. */
2072 mark_used_regs_combine (newpat);
2074 /* Is the result of combination a valid instruction? */
2075 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2077 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2078 the second SET's destination is a register that is unused. In that case,
2079 we just need the first SET. This can occur when simplifying a divmod
2080 insn. We *must* test for this case here because the code below that
2081 splits two independent SETs doesn't handle this case correctly when it
2082 updates the register status. Also check the case where the first
2083 SET's destination is unused. That would not cause incorrect code, but
2084 does cause an unneeded insn to remain. */
2086 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2087 && XVECLEN (newpat, 0) == 2
2088 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2089 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2090 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2091 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2092 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2093 && asm_noperands (newpat) < 0)
2095 newpat = XVECEXP (newpat, 0, 0);
2096 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2099 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2100 && XVECLEN (newpat, 0) == 2
2101 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2102 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2103 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2104 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2105 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2106 && asm_noperands (newpat) < 0)
2108 newpat = XVECEXP (newpat, 0, 1);
2109 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2112 /* If we were combining three insns and the result is a simple SET
2113 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2114 insns. There are two ways to do this. It can be split using a
2115 machine-specific method (like when you have an addition of a large
2116 constant) or by combine in the function find_split_point. */
2118 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2119 && asm_noperands (newpat) < 0)
2121 rtx m_split, *split;
2122 rtx ni2dest = i2dest;
2124 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2125 use I2DEST as a scratch register will help. In the latter case,
2126 convert I2DEST to the mode of the source of NEWPAT if we can. */
2128 m_split = split_insns (newpat, i3);
2130 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2131 inputs of NEWPAT. */
2133 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2134 possible to try that as a scratch reg. This would require adding
2135 more code to make it work though. */
2137 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2139 /* If I2DEST is a hard register or the only use of a pseudo,
2140 we can change its mode. */
2141 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2142 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2143 && GET_CODE (i2dest) == REG
2144 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2145 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2146 && ! REG_USERVAR_P (i2dest))))
2147 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2150 m_split = split_insns (gen_rtx_PARALLEL
2152 gen_rtvec (2, newpat,
2153 gen_rtx_CLOBBER (VOIDmode,
2156 /* If the split with the mode-changed register didn't work, try
2157 the original register. */
2158 if (! m_split && ni2dest != i2dest)
2161 m_split = split_insns (gen_rtx_PARALLEL
2163 gen_rtvec (2, newpat,
2164 gen_rtx_CLOBBER (VOIDmode,
2170 /* If we've split a jump pattern, we'll wind up with a sequence even
2171 with one instruction. We can handle that below, so extract it. */
2172 if (m_split && GET_CODE (m_split) == SEQUENCE
2173 && XVECLEN (m_split, 0) == 1)
2174 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2176 if (m_split && GET_CODE (m_split) != SEQUENCE)
2178 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2179 if (insn_code_number >= 0)
2182 else if (m_split && GET_CODE (m_split) == SEQUENCE
2183 && XVECLEN (m_split, 0) == 2
2184 && (next_real_insn (i2) == i3
2185 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2189 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2190 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2192 i3set = single_set (XVECEXP (m_split, 0, 1));
2193 i2set = single_set (XVECEXP (m_split, 0, 0));
2195 /* In case we changed the mode of I2DEST, replace it in the
2196 pseudo-register table here. We can't do it above in case this
2197 code doesn't get executed and we do a split the other way. */
2199 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2200 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2202 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2204 /* If I2 or I3 has multiple SETs, we won't know how to track
2205 register status, so don't use these insns. If I2's destination
2206 is used between I2 and I3, we also can't use these insns. */
2208 if (i2_code_number >= 0 && i2set && i3set
2209 && (next_real_insn (i2) == i3
2210 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2211 insn_code_number = recog_for_combine (&newi3pat, i3,
2213 if (insn_code_number >= 0)
2216 /* It is possible that both insns now set the destination of I3.
2217 If so, we must show an extra use of it. */
2219 if (insn_code_number >= 0)
2221 rtx new_i3_dest = SET_DEST (i3set);
2222 rtx new_i2_dest = SET_DEST (i2set);
2224 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2225 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2226 || GET_CODE (new_i3_dest) == SUBREG)
2227 new_i3_dest = XEXP (new_i3_dest, 0);
2229 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2230 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2231 || GET_CODE (new_i2_dest) == SUBREG)
2232 new_i2_dest = XEXP (new_i2_dest, 0);
2234 if (GET_CODE (new_i3_dest) == REG
2235 && GET_CODE (new_i2_dest) == REG
2236 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2237 REG_N_SETS (REGNO (new_i2_dest))++;
2241 /* If we can split it and use I2DEST, go ahead and see if that
2242 helps things be recognized. Verify that none of the registers
2243 are set between I2 and I3. */
2244 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2246 && GET_CODE (i2dest) == REG
2248 /* We need I2DEST in the proper mode. If it is a hard register
2249 or the only use of a pseudo, we can change its mode. */
2250 && (GET_MODE (*split) == GET_MODE (i2dest)
2251 || GET_MODE (*split) == VOIDmode
2252 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2253 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2254 && ! REG_USERVAR_P (i2dest)))
2255 && (next_real_insn (i2) == i3
2256 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2257 /* We can't overwrite I2DEST if its value is still used by
2259 && ! reg_referenced_p (i2dest, newpat))
2261 rtx newdest = i2dest;
2262 enum rtx_code split_code = GET_CODE (*split);
2263 enum machine_mode split_mode = GET_MODE (*split);
2265 /* Get NEWDEST as a register in the proper mode. We have already
2266 validated that we can do this. */
2267 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2269 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2271 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2272 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2275 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2276 an ASHIFT. This can occur if it was inside a PLUS and hence
2277 appeared to be a memory address. This is a kludge. */
2278 if (split_code == MULT
2279 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2280 && INTVAL (XEXP (*split, 1)) > 0
2281 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2283 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2284 XEXP (*split, 0), GEN_INT (i)));
2285 /* Update split_code because we may not have a multiply
2287 split_code = GET_CODE (*split);
2290 #ifdef INSN_SCHEDULING
2291 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2292 be written as a ZERO_EXTEND. */
2293 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2294 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2295 SUBREG_REG (*split)));
2298 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2299 SUBST (*split, newdest);
2300 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2302 /* If the split point was a MULT and we didn't have one before,
2303 don't use one now. */
2304 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2305 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2309 /* Check for a case where we loaded from memory in a narrow mode and
2310 then sign extended it, but we need both registers. In that case,
2311 we have a PARALLEL with both loads from the same memory location.
2312 We can split this into a load from memory followed by a register-register
2313 copy. This saves at least one insn, more if register allocation can
2316 We cannot do this if the destination of the second assignment is
2317 a register that we have already assumed is zero-extended. Similarly
2318 for a SUBREG of such a register. */
2320 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2321 && GET_CODE (newpat) == PARALLEL
2322 && XVECLEN (newpat, 0) == 2
2323 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2324 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2325 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2326 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2327 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2328 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2330 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2331 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2332 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2333 (GET_CODE (temp) == REG
2334 && reg_nonzero_bits[REGNO (temp)] != 0
2335 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2336 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2337 && (reg_nonzero_bits[REGNO (temp)]
2338 != GET_MODE_MASK (word_mode))))
2339 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2340 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2341 (GET_CODE (temp) == REG
2342 && reg_nonzero_bits[REGNO (temp)] != 0
2343 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2344 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2345 && (reg_nonzero_bits[REGNO (temp)]
2346 != GET_MODE_MASK (word_mode)))))
2347 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2348 SET_SRC (XVECEXP (newpat, 0, 1)))
2349 && ! find_reg_note (i3, REG_UNUSED,
2350 SET_DEST (XVECEXP (newpat, 0, 0))))
2354 newi2pat = XVECEXP (newpat, 0, 0);
2355 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2356 newpat = XVECEXP (newpat, 0, 1);
2357 SUBST (SET_SRC (newpat),
2358 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2359 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2361 if (i2_code_number >= 0)
2362 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2364 if (insn_code_number >= 0)
2369 /* If we will be able to accept this, we have made a change to the
2370 destination of I3. This can invalidate a LOG_LINKS pointing
2371 to I3. No other part of combine.c makes such a transformation.
2373 The new I3 will have a destination that was previously the
2374 destination of I1 or I2 and which was used in i2 or I3. Call
2375 distribute_links to make a LOG_LINK from the next use of
2376 that destination. */
2378 PATTERN (i3) = newpat;
2379 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2381 /* I3 now uses what used to be its destination and which is
2382 now I2's destination. That means we need a LOG_LINK from
2383 I3 to I2. But we used to have one, so we still will.
2385 However, some later insn might be using I2's dest and have
2386 a LOG_LINK pointing at I3. We must remove this link.
2387 The simplest way to remove the link is to point it at I1,
2388 which we know will be a NOTE. */
2390 for (insn = NEXT_INSN (i3);
2391 insn && (this_basic_block == n_basic_blocks - 1
2392 || insn != BLOCK_HEAD (this_basic_block + 1));
2393 insn = NEXT_INSN (insn))
2395 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2397 for (link = LOG_LINKS (insn); link;
2398 link = XEXP (link, 1))
2399 if (XEXP (link, 0) == i3)
2400 XEXP (link, 0) = i1;
2408 /* Similarly, check for a case where we have a PARALLEL of two independent
2409 SETs but we started with three insns. In this case, we can do the sets
2410 as two separate insns. This case occurs when some SET allows two
2411 other insns to combine, but the destination of that SET is still live. */
2413 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2414 && GET_CODE (newpat) == PARALLEL
2415 && XVECLEN (newpat, 0) == 2
2416 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2419 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2420 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2421 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2422 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2424 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2425 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2426 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2427 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2428 XVECEXP (newpat, 0, 0))
2429 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2430 XVECEXP (newpat, 0, 1))
2431 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2432 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2434 /* Normally, it doesn't matter which of the two is done first,
2435 but it does if one references cc0. In that case, it has to
2438 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2440 newi2pat = XVECEXP (newpat, 0, 0);
2441 newpat = XVECEXP (newpat, 0, 1);
2446 newi2pat = XVECEXP (newpat, 0, 1);
2447 newpat = XVECEXP (newpat, 0, 0);
2450 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2452 if (i2_code_number >= 0)
2453 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2456 /* If it still isn't recognized, fail and change things back the way they
2458 if ((insn_code_number < 0
2459 /* Is the result a reasonable ASM_OPERANDS? */
2460 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2466 /* If we had to change another insn, make sure it is valid also. */
2467 if (undobuf.other_insn)
2469 rtx other_pat = PATTERN (undobuf.other_insn);
2470 rtx new_other_notes;
2473 CLEAR_HARD_REG_SET (newpat_used_regs);
2475 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2478 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2484 PATTERN (undobuf.other_insn) = other_pat;
2486 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2487 are still valid. Then add any non-duplicate notes added by
2488 recog_for_combine. */
2489 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2491 next = XEXP (note, 1);
2493 if (REG_NOTE_KIND (note) == REG_UNUSED
2494 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2496 if (GET_CODE (XEXP (note, 0)) == REG)
2497 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2499 remove_note (undobuf.other_insn, note);
2503 for (note = new_other_notes; note; note = XEXP (note, 1))
2504 if (GET_CODE (XEXP (note, 0)) == REG)
2505 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2507 distribute_notes (new_other_notes, undobuf.other_insn,
2508 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2511 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2512 they are adjacent to each other or not. */
2514 rtx p = prev_nonnote_insn (i3);
2515 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2516 && sets_cc0_p (newi2pat))
2524 /* We now know that we can do this combination. Merge the insns and
2525 update the status of registers and LOG_LINKS. */
2528 rtx i3notes, i2notes, i1notes = 0;
2529 rtx i3links, i2links, i1links = 0;
2532 /* Compute which registers we expect to eliminate. newi2pat may be setting
2533 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2534 same as i3dest, in which case newi2pat may be setting i1dest. */
2535 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2536 || i2dest_in_i2src || i2dest_in_i1src
2538 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2539 || (newi2pat && reg_set_p (i1dest, newi2pat))
2542 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2544 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2545 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2547 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2549 /* Ensure that we do not have something that should not be shared but
2550 occurs multiple times in the new insns. Check this by first
2551 resetting all the `used' flags and then copying anything is shared. */
2553 reset_used_flags (i3notes);
2554 reset_used_flags (i2notes);
2555 reset_used_flags (i1notes);
2556 reset_used_flags (newpat);
2557 reset_used_flags (newi2pat);
2558 if (undobuf.other_insn)
2559 reset_used_flags (PATTERN (undobuf.other_insn));
2561 i3notes = copy_rtx_if_shared (i3notes);
2562 i2notes = copy_rtx_if_shared (i2notes);
2563 i1notes = copy_rtx_if_shared (i1notes);
2564 newpat = copy_rtx_if_shared (newpat);
2565 newi2pat = copy_rtx_if_shared (newi2pat);
2566 if (undobuf.other_insn)
2567 reset_used_flags (PATTERN (undobuf.other_insn));
2569 INSN_CODE (i3) = insn_code_number;
2570 PATTERN (i3) = newpat;
2572 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2574 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2576 reset_used_flags (call_usage);
2577 call_usage = copy_rtx (call_usage);
2580 replace_rtx (call_usage, i2dest, i2src);
2583 replace_rtx (call_usage, i1dest, i1src);
2585 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2588 if (undobuf.other_insn)
2589 INSN_CODE (undobuf.other_insn) = other_code_number;
2591 /* We had one special case above where I2 had more than one set and
2592 we replaced a destination of one of those sets with the destination
2593 of I3. In that case, we have to update LOG_LINKS of insns later
2594 in this basic block. Note that this (expensive) case is rare.
2596 Also, in this case, we must pretend that all REG_NOTEs for I2
2597 actually came from I3, so that REG_UNUSED notes from I2 will be
2598 properly handled. */
2600 if (i3_subst_into_i2)
2602 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2603 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2604 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2605 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2606 && ! find_reg_note (i2, REG_UNUSED,
2607 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2608 for (temp = NEXT_INSN (i2);
2609 temp && (this_basic_block == n_basic_blocks - 1
2610 || BLOCK_HEAD (this_basic_block) != temp);
2611 temp = NEXT_INSN (temp))
2612 if (temp != i3 && INSN_P (temp))
2613 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2614 if (XEXP (link, 0) == i2)
2615 XEXP (link, 0) = i3;
2620 while (XEXP (link, 1))
2621 link = XEXP (link, 1);
2622 XEXP (link, 1) = i2notes;
2636 INSN_CODE (i2) = i2_code_number;
2637 PATTERN (i2) = newi2pat;
2641 PUT_CODE (i2, NOTE);
2642 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2643 NOTE_SOURCE_FILE (i2) = 0;
2650 PUT_CODE (i1, NOTE);
2651 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2652 NOTE_SOURCE_FILE (i1) = 0;
2655 /* Get death notes for everything that is now used in either I3 or
2656 I2 and used to die in a previous insn. If we built two new
2657 patterns, move from I1 to I2 then I2 to I3 so that we get the
2658 proper movement on registers that I2 modifies. */
2662 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2663 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2666 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2669 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2671 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2674 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2677 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2680 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2683 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2684 know these are REG_UNUSED and want them to go to the desired insn,
2685 so we always pass it as i3. We have not counted the notes in
2686 reg_n_deaths yet, so we need to do so now. */
2688 if (newi2pat && new_i2_notes)
2690 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2691 if (GET_CODE (XEXP (temp, 0)) == REG)
2692 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2694 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2699 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2700 if (GET_CODE (XEXP (temp, 0)) == REG)
2701 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2703 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2706 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2707 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2708 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2709 in that case, it might delete I2. Similarly for I2 and I1.
2710 Show an additional death due to the REG_DEAD note we make here. If
2711 we discard it in distribute_notes, we will decrement it again. */
2715 if (GET_CODE (i3dest_killed) == REG)
2716 REG_N_DEATHS (REGNO (i3dest_killed))++;
2718 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2719 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2721 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2723 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2725 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2729 if (i2dest_in_i2src)
2731 if (GET_CODE (i2dest) == REG)
2732 REG_N_DEATHS (REGNO (i2dest))++;
2734 if (newi2pat && reg_set_p (i2dest, newi2pat))
2735 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2736 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2738 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2739 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2740 NULL_RTX, NULL_RTX);
2743 if (i1dest_in_i1src)
2745 if (GET_CODE (i1dest) == REG)
2746 REG_N_DEATHS (REGNO (i1dest))++;
2748 if (newi2pat && reg_set_p (i1dest, newi2pat))
2749 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2750 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2752 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2753 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2754 NULL_RTX, NULL_RTX);
2757 distribute_links (i3links);
2758 distribute_links (i2links);
2759 distribute_links (i1links);
2761 if (GET_CODE (i2dest) == REG)
2764 rtx i2_insn = 0, i2_val = 0, set;
2766 /* The insn that used to set this register doesn't exist, and
2767 this life of the register may not exist either. See if one of
2768 I3's links points to an insn that sets I2DEST. If it does,
2769 that is now the last known value for I2DEST. If we don't update
2770 this and I2 set the register to a value that depended on its old
2771 contents, we will get confused. If this insn is used, thing
2772 will be set correctly in combine_instructions. */
2774 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2775 if ((set = single_set (XEXP (link, 0))) != 0
2776 && rtx_equal_p (i2dest, SET_DEST (set)))
2777 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2779 record_value_for_reg (i2dest, i2_insn, i2_val);
2781 /* If the reg formerly set in I2 died only once and that was in I3,
2782 zero its use count so it won't make `reload' do any work. */
2784 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2785 && ! i2dest_in_i2src)
2787 regno = REGNO (i2dest);
2788 REG_N_SETS (regno)--;
2792 if (i1 && GET_CODE (i1dest) == REG)
2795 rtx i1_insn = 0, i1_val = 0, set;
2797 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2798 if ((set = single_set (XEXP (link, 0))) != 0
2799 && rtx_equal_p (i1dest, SET_DEST (set)))
2800 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2802 record_value_for_reg (i1dest, i1_insn, i1_val);
2804 regno = REGNO (i1dest);
2805 if (! added_sets_1 && ! i1dest_in_i1src)
2806 REG_N_SETS (regno)--;
2809 /* Update reg_nonzero_bits et al for any changes that may have been made
2810 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2811 important. Because newi2pat can affect nonzero_bits of newpat */
2813 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2814 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2816 /* Set new_direct_jump_p if a new return or simple jump instruction
2819 If I3 is now an unconditional jump, ensure that it has a
2820 BARRIER following it since it may have initially been a
2821 conditional jump. It may also be the last nonnote insn. */
2823 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2825 *new_direct_jump_p = 1;
2827 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2828 || GET_CODE (temp) != BARRIER)
2829 emit_barrier_after (i3);
2831 /* An NOOP jump does not need barrier, but it does need cleaning up
2833 if (GET_CODE (newpat) == SET
2834 && SET_SRC (newpat) == pc_rtx
2835 && SET_DEST (newpat) == pc_rtx)
2836 *new_direct_jump_p = 1;
2839 combine_successes++;
2842 /* Clear this here, so that subsequent get_last_value calls are not
2844 subst_prev_insn = NULL_RTX;
2846 if (added_links_insn
2847 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2848 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2849 return added_links_insn;
2851 return newi2pat ? i2 : i3;
2854 /* Undo all the modifications recorded in undobuf. */
2859 struct undo *undo, *next;
2861 for (undo = undobuf.undos; undo; undo = next)
2865 *undo->where.i = undo->old_contents.i;
2867 *undo->where.r = undo->old_contents.r;
2869 undo->next = undobuf.frees;
2870 undobuf.frees = undo;
2875 /* Clear this here, so that subsequent get_last_value calls are not
2877 subst_prev_insn = NULL_RTX;
2880 /* We've committed to accepting the changes we made. Move all
2881 of the undos to the free list. */
2886 struct undo *undo, *next;
2888 for (undo = undobuf.undos; undo; undo = next)
2891 undo->next = undobuf.frees;
2892 undobuf.frees = undo;
2898 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2899 where we have an arithmetic expression and return that point. LOC will
2902 try_combine will call this function to see if an insn can be split into
2906 find_split_point (loc, insn)
2911 enum rtx_code code = GET_CODE (x);
2913 unsigned HOST_WIDE_INT len = 0;
2914 HOST_WIDE_INT pos = 0;
2916 rtx inner = NULL_RTX;
2918 /* First special-case some codes. */
2922 #ifdef INSN_SCHEDULING
2923 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2925 if (GET_CODE (SUBREG_REG (x)) == MEM)
2928 return find_split_point (&SUBREG_REG (x), insn);
2932 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2933 using LO_SUM and HIGH. */
2934 if (GET_CODE (XEXP (x, 0)) == CONST
2935 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2938 gen_rtx_LO_SUM (Pmode,
2939 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2941 return &XEXP (XEXP (x, 0), 0);
2945 /* If we have a PLUS whose second operand is a constant and the
2946 address is not valid, perhaps will can split it up using
2947 the machine-specific way to split large constants. We use
2948 the first pseudo-reg (one of the virtual regs) as a placeholder;
2949 it will not remain in the result. */
2950 if (GET_CODE (XEXP (x, 0)) == PLUS
2951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2952 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2954 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2955 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2958 /* This should have produced two insns, each of which sets our
2959 placeholder. If the source of the second is a valid address,
2960 we can make put both sources together and make a split point
2963 if (seq && XVECLEN (seq, 0) == 2
2964 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2965 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2966 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2967 && ! reg_mentioned_p (reg,
2968 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2969 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2970 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2971 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2972 && memory_address_p (GET_MODE (x),
2973 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2975 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2976 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2978 /* Replace the placeholder in SRC2 with SRC1. If we can
2979 find where in SRC2 it was placed, that can become our
2980 split point and we can replace this address with SRC2.
2981 Just try two obvious places. */
2983 src2 = replace_rtx (src2, reg, src1);
2985 if (XEXP (src2, 0) == src1)
2986 split = &XEXP (src2, 0);
2987 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2988 && XEXP (XEXP (src2, 0), 0) == src1)
2989 split = &XEXP (XEXP (src2, 0), 0);
2993 SUBST (XEXP (x, 0), src2);
2998 /* If that didn't work, perhaps the first operand is complex and
2999 needs to be computed separately, so make a split point there.
3000 This will occur on machines that just support REG + CONST
3001 and have a constant moved through some previous computation. */
3003 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
3004 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3005 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3007 return &XEXP (XEXP (x, 0), 0);
3013 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3014 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3015 we need to put the operand into a register. So split at that
3018 if (SET_DEST (x) == cc0_rtx
3019 && GET_CODE (SET_SRC (x)) != COMPARE
3020 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3021 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3022 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3023 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3024 return &SET_SRC (x);
3027 /* See if we can split SET_SRC as it stands. */
3028 split = find_split_point (&SET_SRC (x), insn);
3029 if (split && split != &SET_SRC (x))
3032 /* See if we can split SET_DEST as it stands. */
3033 split = find_split_point (&SET_DEST (x), insn);
3034 if (split && split != &SET_DEST (x))
3037 /* See if this is a bitfield assignment with everything constant. If
3038 so, this is an IOR of an AND, so split it into that. */
3039 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3040 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3041 <= HOST_BITS_PER_WIDE_INT)
3042 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3043 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3044 && GET_CODE (SET_SRC (x)) == CONST_INT
3045 && ((INTVAL (XEXP (SET_DEST (x), 1))
3046 + INTVAL (XEXP (SET_DEST (x), 2)))
3047 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3048 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3050 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3051 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3052 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3053 rtx dest = XEXP (SET_DEST (x), 0);
3054 enum machine_mode mode = GET_MODE (dest);
3055 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3057 if (BITS_BIG_ENDIAN)
3058 pos = GET_MODE_BITSIZE (mode) - len - pos;
3062 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3065 gen_binary (IOR, mode,
3066 gen_binary (AND, mode, dest,
3067 gen_int_mode (~(mask << pos),
3069 GEN_INT (src << pos)));
3071 SUBST (SET_DEST (x), dest);
3073 split = find_split_point (&SET_SRC (x), insn);
3074 if (split && split != &SET_SRC (x))
3078 /* Otherwise, see if this is an operation that we can split into two.
3079 If so, try to split that. */
3080 code = GET_CODE (SET_SRC (x));
3085 /* If we are AND'ing with a large constant that is only a single
3086 bit and the result is only being used in a context where we
3087 need to know if it is zero or non-zero, replace it with a bit
3088 extraction. This will avoid the large constant, which might
3089 have taken more than one insn to make. If the constant were
3090 not a valid argument to the AND but took only one insn to make,
3091 this is no worse, but if it took more than one insn, it will
3094 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3095 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3096 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3097 && GET_CODE (SET_DEST (x)) == REG
3098 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3099 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3100 && XEXP (*split, 0) == SET_DEST (x)
3101 && XEXP (*split, 1) == const0_rtx)
3103 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3104 XEXP (SET_SRC (x), 0),
3105 pos, NULL_RTX, 1, 1, 0, 0);
3106 if (extraction != 0)
3108 SUBST (SET_SRC (x), extraction);
3109 return find_split_point (loc, insn);
3115 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3116 is known to be on, this can be converted into a NEG of a shift. */
3117 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3118 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3119 && 1 <= (pos = exact_log2
3120 (nonzero_bits (XEXP (SET_SRC (x), 0),
3121 GET_MODE (XEXP (SET_SRC (x), 0))))))
3123 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3127 gen_rtx_LSHIFTRT (mode,
3128 XEXP (SET_SRC (x), 0),
3131 split = find_split_point (&SET_SRC (x), insn);
3132 if (split && split != &SET_SRC (x))
3138 inner = XEXP (SET_SRC (x), 0);
3140 /* We can't optimize if either mode is a partial integer
3141 mode as we don't know how many bits are significant
3143 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3144 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3148 len = GET_MODE_BITSIZE (GET_MODE (inner));
3154 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3155 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3157 inner = XEXP (SET_SRC (x), 0);
3158 len = INTVAL (XEXP (SET_SRC (x), 1));
3159 pos = INTVAL (XEXP (SET_SRC (x), 2));
3161 if (BITS_BIG_ENDIAN)
3162 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3163 unsignedp = (code == ZERO_EXTRACT);
3171 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3173 enum machine_mode mode = GET_MODE (SET_SRC (x));
3175 /* For unsigned, we have a choice of a shift followed by an
3176 AND or two shifts. Use two shifts for field sizes where the
3177 constant might be too large. We assume here that we can
3178 always at least get 8-bit constants in an AND insn, which is
3179 true for every current RISC. */
3181 if (unsignedp && len <= 8)
3186 (mode, gen_lowpart_for_combine (mode, inner),
3188 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3190 split = find_split_point (&SET_SRC (x), insn);
3191 if (split && split != &SET_SRC (x))
3198 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3199 gen_rtx_ASHIFT (mode,
3200 gen_lowpart_for_combine (mode, inner),
3201 GEN_INT (GET_MODE_BITSIZE (mode)
3203 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3205 split = find_split_point (&SET_SRC (x), insn);
3206 if (split && split != &SET_SRC (x))
3211 /* See if this is a simple operation with a constant as the second
3212 operand. It might be that this constant is out of range and hence
3213 could be used as a split point. */
3214 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3215 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3216 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3217 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3218 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3219 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3220 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3222 return &XEXP (SET_SRC (x), 1);
3224 /* Finally, see if this is a simple operation with its first operand
3225 not in a register. The operation might require this operand in a
3226 register, so return it as a split point. We can always do this
3227 because if the first operand were another operation, we would have
3228 already found it as a split point. */
3229 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3230 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3231 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3232 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3233 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3234 return &XEXP (SET_SRC (x), 0);
3240 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3241 it is better to write this as (not (ior A B)) so we can split it.
3242 Similarly for IOR. */
3243 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3246 gen_rtx_NOT (GET_MODE (x),
3247 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3249 XEXP (XEXP (x, 0), 0),
3250 XEXP (XEXP (x, 1), 0))));
3251 return find_split_point (loc, insn);
3254 /* Many RISC machines have a large set of logical insns. If the
3255 second operand is a NOT, put it first so we will try to split the
3256 other operand first. */
3257 if (GET_CODE (XEXP (x, 1)) == NOT)
3259 rtx tem = XEXP (x, 0);
3260 SUBST (XEXP (x, 0), XEXP (x, 1));
3261 SUBST (XEXP (x, 1), tem);
3269 /* Otherwise, select our actions depending on our rtx class. */
3270 switch (GET_RTX_CLASS (code))
3272 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3274 split = find_split_point (&XEXP (x, 2), insn);
3277 /* ... fall through ... */
3281 split = find_split_point (&XEXP (x, 1), insn);
3284 /* ... fall through ... */
3286 /* Some machines have (and (shift ...) ...) insns. If X is not
3287 an AND, but XEXP (X, 0) is, use it as our split point. */
3288 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3289 return &XEXP (x, 0);
3291 split = find_split_point (&XEXP (x, 0), insn);
3297 /* Otherwise, we don't have a split point. */
3301 /* Throughout X, replace FROM with TO, and return the result.
3302 The result is TO if X is FROM;
3303 otherwise the result is X, but its contents may have been modified.
3304 If they were modified, a record was made in undobuf so that
3305 undo_all will (among other things) return X to its original state.
3307 If the number of changes necessary is too much to record to undo,
3308 the excess changes are not made, so the result is invalid.
3309 The changes already made can still be undone.
3310 undobuf.num_undo is incremented for such changes, so by testing that
3311 the caller can tell whether the result is valid.
3313 `n_occurrences' is incremented each time FROM is replaced.
3315 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3317 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3318 by copying if `n_occurrences' is non-zero. */
3321 subst (x, from, to, in_dest, unique_copy)
3326 enum rtx_code code = GET_CODE (x);
3327 enum machine_mode op0_mode = VOIDmode;
3332 /* Two expressions are equal if they are identical copies of a shared
3333 RTX or if they are both registers with the same register number
3336 #define COMBINE_RTX_EQUAL_P(X,Y) \
3338 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3339 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3341 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3344 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3347 /* If X and FROM are the same register but different modes, they will
3348 not have been seen as equal above. However, flow.c will make a
3349 LOG_LINKS entry for that case. If we do nothing, we will try to
3350 rerecognize our original insn and, when it succeeds, we will
3351 delete the feeding insn, which is incorrect.
3353 So force this insn not to match in this (rare) case. */
3354 if (! in_dest && code == REG && GET_CODE (from) == REG
3355 && REGNO (x) == REGNO (from))
3356 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3358 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3359 of which may contain things that can be combined. */
3360 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3363 /* It is possible to have a subexpression appear twice in the insn.
3364 Suppose that FROM is a register that appears within TO.
3365 Then, after that subexpression has been scanned once by `subst',
3366 the second time it is scanned, TO may be found. If we were
3367 to scan TO here, we would find FROM within it and create a
3368 self-referent rtl structure which is completely wrong. */
3369 if (COMBINE_RTX_EQUAL_P (x, to))
3372 /* Parallel asm_operands need special attention because all of the
3373 inputs are shared across the arms. Furthermore, unsharing the
3374 rtl results in recognition failures. Failure to handle this case
3375 specially can result in circular rtl.
3377 Solve this by doing a normal pass across the first entry of the
3378 parallel, and only processing the SET_DESTs of the subsequent
3381 if (code == PARALLEL
3382 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3383 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3385 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3387 /* If this substitution failed, this whole thing fails. */
3388 if (GET_CODE (new) == CLOBBER
3389 && XEXP (new, 0) == const0_rtx)
3392 SUBST (XVECEXP (x, 0, 0), new);
3394 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3396 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3398 if (GET_CODE (dest) != REG
3399 && GET_CODE (dest) != CC0
3400 && GET_CODE (dest) != PC)
3402 new = subst (dest, from, to, 0, unique_copy);
3404 /* If this substitution failed, this whole thing fails. */
3405 if (GET_CODE (new) == CLOBBER
3406 && XEXP (new, 0) == const0_rtx)
3409 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3415 len = GET_RTX_LENGTH (code);
3416 fmt = GET_RTX_FORMAT (code);
3418 /* We don't need to process a SET_DEST that is a register, CC0,
3419 or PC, so set up to skip this common case. All other cases
3420 where we want to suppress replacing something inside a
3421 SET_SRC are handled via the IN_DEST operand. */
3423 && (GET_CODE (SET_DEST (x)) == REG
3424 || GET_CODE (SET_DEST (x)) == CC0
3425 || GET_CODE (SET_DEST (x)) == PC))
3428 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3431 op0_mode = GET_MODE (XEXP (x, 0));
3433 for (i = 0; i < len; i++)
3438 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3440 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3442 new = (unique_copy && n_occurrences
3443 ? copy_rtx (to) : to);
3448 new = subst (XVECEXP (x, i, j), from, to, 0,
3451 /* If this substitution failed, this whole thing
3453 if (GET_CODE (new) == CLOBBER
3454 && XEXP (new, 0) == const0_rtx)
3458 SUBST (XVECEXP (x, i, j), new);
3461 else if (fmt[i] == 'e')
3463 /* If this is a register being set, ignore it. */
3466 && (code == SUBREG || code == STRICT_LOW_PART
3467 || code == ZERO_EXTRACT)
3469 && GET_CODE (new) == REG)
3472 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3474 /* In general, don't install a subreg involving two
3475 modes not tieable. It can worsen register
3476 allocation, and can even make invalid reload
3477 insns, since the reg inside may need to be copied
3478 from in the outside mode, and that may be invalid
3479 if it is an fp reg copied in integer mode.
3481 We allow two exceptions to this: It is valid if
3482 it is inside another SUBREG and the mode of that
3483 SUBREG and the mode of the inside of TO is
3484 tieable and it is valid if X is a SET that copies
3487 if (GET_CODE (to) == SUBREG
3488 && ! MODES_TIEABLE_P (GET_MODE (to),
3489 GET_MODE (SUBREG_REG (to)))
3490 && ! (code == SUBREG
3491 && MODES_TIEABLE_P (GET_MODE (x),
3492 GET_MODE (SUBREG_REG (to))))
3494 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3497 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3499 #ifdef CLASS_CANNOT_CHANGE_MODE
3501 && GET_CODE (to) == REG
3502 && REGNO (to) < FIRST_PSEUDO_REGISTER
3503 && (TEST_HARD_REG_BIT
3504 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3506 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3508 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3511 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3515 /* If we are in a SET_DEST, suppress most cases unless we
3516 have gone inside a MEM, in which case we want to
3517 simplify the address. We assume here that things that
3518 are actually part of the destination have their inner
3519 parts in the first expression. This is true for SUBREG,
3520 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3521 things aside from REG and MEM that should appear in a
3523 new = subst (XEXP (x, i), from, to,
3525 && (code == SUBREG || code == STRICT_LOW_PART
3526 || code == ZERO_EXTRACT))
3528 && i == 0), unique_copy);
3530 /* If we found that we will have to reject this combination,
3531 indicate that by returning the CLOBBER ourselves, rather than
3532 an expression containing it. This will speed things up as
3533 well as prevent accidents where two CLOBBERs are considered
3534 to be equal, thus producing an incorrect simplification. */
3536 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3539 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3541 if (VECTOR_MODE_P (GET_MODE (x)))
3542 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3544 x = simplify_subreg (GET_MODE (x), new,
3545 GET_MODE (SUBREG_REG (x)),
3550 else if (GET_CODE (new) == CONST_INT
3551 && GET_CODE (x) == ZERO_EXTEND)
3553 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3554 new, GET_MODE (XEXP (x, 0)));
3559 SUBST (XEXP (x, i), new);
3564 /* Try to simplify X. If the simplification changed the code, it is likely
3565 that further simplification will help, so loop, but limit the number
3566 of repetitions that will be performed. */
3568 for (i = 0; i < 4; i++)
3570 /* If X is sufficiently simple, don't bother trying to do anything
3572 if (code != CONST_INT && code != REG && code != CLOBBER)
3573 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3575 if (GET_CODE (x) == code)
3578 code = GET_CODE (x);
3580 /* We no longer know the original mode of operand 0 since we
3581 have changed the form of X) */
3582 op0_mode = VOIDmode;
3588 /* Simplify X, a piece of RTL. We just operate on the expression at the
3589 outer level; call `subst' to simplify recursively. Return the new
3592 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3593 will be the iteration even if an expression with a code different from
3594 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3597 combine_simplify_rtx (x, op0_mode, last, in_dest)
3599 enum machine_mode op0_mode;
3603 enum rtx_code code = GET_CODE (x);
3604 enum machine_mode mode = GET_MODE (x);
3609 /* If this is a commutative operation, put a constant last and a complex
3610 expression first. We don't need to do this for comparisons here. */
3611 if (GET_RTX_CLASS (code) == 'c'
3612 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3615 SUBST (XEXP (x, 0), XEXP (x, 1));
3616 SUBST (XEXP (x, 1), temp);
3619 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3620 sign extension of a PLUS with a constant, reverse the order of the sign
3621 extension and the addition. Note that this not the same as the original
3622 code, but overflow is undefined for signed values. Also note that the
3623 PLUS will have been partially moved "inside" the sign-extension, so that
3624 the first operand of X will really look like:
3625 (ashiftrt (plus (ashift A C4) C5) C4).
3627 (plus (ashiftrt (ashift A C4) C2) C4)
3628 and replace the first operand of X with that expression. Later parts
3629 of this function may simplify the expression further.
3631 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3632 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3633 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3635 We do this to simplify address expressions. */
3637 if ((code == PLUS || code == MINUS || code == MULT)
3638 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3639 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3640 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3641 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3642 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3643 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3644 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3645 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3646 XEXP (XEXP (XEXP (x, 0), 0), 1),
3647 XEXP (XEXP (x, 0), 1))) != 0)
3650 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3651 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3652 INTVAL (XEXP (XEXP (x, 0), 1)));
3654 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3655 INTVAL (XEXP (XEXP (x, 0), 1)));
3657 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3660 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3661 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3662 things. Check for cases where both arms are testing the same
3665 Don't do anything if all operands are very simple. */
3667 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3668 || GET_RTX_CLASS (code) == '<')
3669 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3670 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3671 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3673 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3674 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3675 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3677 || (GET_RTX_CLASS (code) == '1'
3678 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3679 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3680 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3683 rtx cond, true_rtx, false_rtx;
3685 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3687 /* If everything is a comparison, what we have is highly unlikely
3688 to be simpler, so don't use it. */
3689 && ! (GET_RTX_CLASS (code) == '<'
3690 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3691 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3693 rtx cop1 = const0_rtx;
3694 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3696 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3699 /* Simplify the alternative arms; this may collapse the true and
3700 false arms to store-flag values. */
3701 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3702 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3704 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3705 is unlikely to be simpler. */
3706 if (general_operand (true_rtx, VOIDmode)
3707 && general_operand (false_rtx, VOIDmode))
3709 /* Restarting if we generate a store-flag expression will cause
3710 us to loop. Just drop through in this case. */
3712 /* If the result values are STORE_FLAG_VALUE and zero, we can
3713 just make the comparison operation. */
3714 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3715 x = gen_binary (cond_code, mode, cond, cop1);
3716 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3717 && reverse_condition (cond_code) != UNKNOWN)
3718 x = gen_binary (reverse_condition (cond_code),
3721 /* Likewise, we can make the negate of a comparison operation
3722 if the result values are - STORE_FLAG_VALUE and zero. */
3723 else if (GET_CODE (true_rtx) == CONST_INT
3724 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3725 && false_rtx == const0_rtx)
3726 x = simplify_gen_unary (NEG, mode,
3727 gen_binary (cond_code, mode, cond,
3730 else if (GET_CODE (false_rtx) == CONST_INT
3731 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3732 && true_rtx == const0_rtx)
3733 x = simplify_gen_unary (NEG, mode,
3734 gen_binary (reverse_condition
3739 return gen_rtx_IF_THEN_ELSE (mode,
3740 gen_binary (cond_code, VOIDmode,
3742 true_rtx, false_rtx);
3744 code = GET_CODE (x);
3745 op0_mode = VOIDmode;
3750 /* Try to fold this expression in case we have constants that weren't
3753 switch (GET_RTX_CLASS (code))
3756 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3760 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3761 if (cmp_mode == VOIDmode)
3763 cmp_mode = GET_MODE (XEXP (x, 1));
3764 if (cmp_mode == VOIDmode)
3765 cmp_mode = op0_mode;
3767 temp = simplify_relational_operation (code, cmp_mode,
3768 XEXP (x, 0), XEXP (x, 1));
3770 #ifdef FLOAT_STORE_FLAG_VALUE
3771 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3773 if (temp == const0_rtx)
3774 temp = CONST0_RTX (mode);
3776 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3783 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3787 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3788 XEXP (x, 1), XEXP (x, 2));
3795 code = GET_CODE (temp);
3796 op0_mode = VOIDmode;
3797 mode = GET_MODE (temp);
3800 /* First see if we can apply the inverse distributive law. */
3801 if (code == PLUS || code == MINUS
3802 || code == AND || code == IOR || code == XOR)
3804 x = apply_distributive_law (x);
3805 code = GET_CODE (x);
3806 op0_mode = VOIDmode;
3809 /* If CODE is an associative operation not otherwise handled, see if we
3810 can associate some operands. This can win if they are constants or
3811 if they are logically related (i.e. (a & b) & a). */
3812 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3813 || code == AND || code == IOR || code == XOR
3814 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3815 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3816 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3818 if (GET_CODE (XEXP (x, 0)) == code)
3820 rtx other = XEXP (XEXP (x, 0), 0);
3821 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3822 rtx inner_op1 = XEXP (x, 1);
3825 /* Make sure we pass the constant operand if any as the second
3826 one if this is a commutative operation. */
3827 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3829 rtx tem = inner_op0;
3830 inner_op0 = inner_op1;
3833 inner = simplify_binary_operation (code == MINUS ? PLUS
3834 : code == DIV ? MULT
3836 mode, inner_op0, inner_op1);
3838 /* For commutative operations, try the other pair if that one
3840 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3842 other = XEXP (XEXP (x, 0), 1);
3843 inner = simplify_binary_operation (code, mode,
3844 XEXP (XEXP (x, 0), 0),
3849 return gen_binary (code, mode, other, inner);
3853 /* A little bit of algebraic simplification here. */
3857 /* Ensure that our address has any ASHIFTs converted to MULT in case
3858 address-recognizing predicates are called later. */
3859 temp = make_compound_operation (XEXP (x, 0), MEM);
3860 SUBST (XEXP (x, 0), temp);
3864 if (op0_mode == VOIDmode)
3865 op0_mode = GET_MODE (SUBREG_REG (x));
3867 /* simplify_subreg can't use gen_lowpart_for_combine. */
3868 if (CONSTANT_P (SUBREG_REG (x))
3869 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3870 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3872 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3876 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3882 /* Don't change the mode of the MEM if that would change the meaning
3884 if (GET_CODE (SUBREG_REG (x)) == MEM
3885 && (MEM_VOLATILE_P (SUBREG_REG (x))
3886 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3887 return gen_rtx_CLOBBER (mode, const0_rtx);
3889 /* Note that we cannot do any narrowing for non-constants since
3890 we might have been counting on using the fact that some bits were
3891 zero. We now do this in the SET. */
3896 /* (not (plus X -1)) can become (neg X). */
3897 if (GET_CODE (XEXP (x, 0)) == PLUS
3898 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3899 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3901 /* Similarly, (not (neg X)) is (plus X -1). */
3902 if (GET_CODE (XEXP (x, 0)) == NEG)
3903 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3905 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3906 if (GET_CODE (XEXP (x, 0)) == XOR
3907 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3908 && (temp = simplify_unary_operation (NOT, mode,
3909 XEXP (XEXP (x, 0), 1),
3911 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3913 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3914 other than 1, but that is not valid. We could do a similar
3915 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3916 but this doesn't seem common enough to bother with. */
3917 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3918 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3919 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3921 XEXP (XEXP (x, 0), 1));
3923 if (GET_CODE (XEXP (x, 0)) == SUBREG
3924 && subreg_lowpart_p (XEXP (x, 0))
3925 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3926 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3927 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3928 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3930 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3932 x = gen_rtx_ROTATE (inner_mode,
3933 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3935 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3936 return gen_lowpart_for_combine (mode, x);
3939 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3940 reversing the comparison code if valid. */
3941 if (STORE_FLAG_VALUE == -1
3942 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3943 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3944 XEXP (XEXP (x, 0), 1))))
3947 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3948 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3949 perform the above simplification. */
3951 if (STORE_FLAG_VALUE == -1
3952 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3953 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3954 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3955 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3957 /* Apply De Morgan's laws to reduce number of patterns for machines
3958 with negating logical insns (and-not, nand, etc.). If result has
3959 only one NOT, put it first, since that is how the patterns are
3962 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3964 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3965 enum machine_mode op_mode;
3967 op_mode = GET_MODE (in1);
3968 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3970 op_mode = GET_MODE (in2);
3971 if (op_mode == VOIDmode)
3973 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3975 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3978 in2 = in1; in1 = tem;
3981 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3987 /* (neg (plus X 1)) can become (not X). */
3988 if (GET_CODE (XEXP (x, 0)) == PLUS
3989 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3990 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3992 /* Similarly, (neg (not X)) is (plus X 1). */
3993 if (GET_CODE (XEXP (x, 0)) == NOT)
3994 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3996 /* (neg (minus X Y)) can become (minus Y X). This transformation
3997 isn't safe for modes with signed zeros, since if X and Y are
3998 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3999 mode is towards +infinity (or -infinity) then the two expressions
4000 will be rounded differently. */
4001 if (GET_CODE (XEXP (x, 0)) == MINUS
4002 && !HONOR_SIGNED_ZEROS (mode)
4003 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4004 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4005 XEXP (XEXP (x, 0), 0));
4007 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4008 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4009 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4010 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4012 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4013 if we can then eliminate the NEG (e.g.,
4014 if the operand is a constant). */
4016 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4018 temp = simplify_unary_operation (NEG, mode,
4019 XEXP (XEXP (x, 0), 0), mode);
4021 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4024 temp = expand_compound_operation (XEXP (x, 0));
4026 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4027 replaced by (lshiftrt X C). This will convert
4028 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4030 if (GET_CODE (temp) == ASHIFTRT
4031 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4032 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4033 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4034 INTVAL (XEXP (temp, 1)));
4036 /* If X has only a single bit that might be nonzero, say, bit I, convert
4037 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4038 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4039 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4040 or a SUBREG of one since we'd be making the expression more
4041 complex if it was just a register. */
4043 if (GET_CODE (temp) != REG
4044 && ! (GET_CODE (temp) == SUBREG
4045 && GET_CODE (SUBREG_REG (temp)) == REG)
4046 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4048 rtx temp1 = simplify_shift_const
4049 (NULL_RTX, ASHIFTRT, mode,
4050 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4051 GET_MODE_BITSIZE (mode) - 1 - i),
4052 GET_MODE_BITSIZE (mode) - 1 - i);
4054 /* If all we did was surround TEMP with the two shifts, we
4055 haven't improved anything, so don't use it. Otherwise,
4056 we are better off with TEMP1. */
4057 if (GET_CODE (temp1) != ASHIFTRT
4058 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4059 || XEXP (XEXP (temp1, 0), 0) != temp)
4065 /* We can't handle truncation to a partial integer mode here
4066 because we don't know the real bitsize of the partial
4068 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4071 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4072 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4073 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4075 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4076 GET_MODE_MASK (mode), NULL_RTX, 0));
4078 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4079 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4080 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4081 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4082 return XEXP (XEXP (x, 0), 0);
4084 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4085 (OP:SI foo:SI) if OP is NEG or ABS. */
4086 if ((GET_CODE (XEXP (x, 0)) == ABS
4087 || GET_CODE (XEXP (x, 0)) == NEG)
4088 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4089 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4090 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4091 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4092 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4094 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4096 if (GET_CODE (XEXP (x, 0)) == SUBREG
4097 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4098 && subreg_lowpart_p (XEXP (x, 0)))
4099 return SUBREG_REG (XEXP (x, 0));
4101 /* If we know that the value is already truncated, we can
4102 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4103 is nonzero for the corresponding modes. But don't do this
4104 for an (LSHIFTRT (MULT ...)) since this will cause problems
4105 with the umulXi3_highpart patterns. */
4106 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4107 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4108 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4109 >= GET_MODE_BITSIZE (mode) + 1
4110 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4111 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4112 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4114 /* A truncate of a comparison can be replaced with a subreg if
4115 STORE_FLAG_VALUE permits. This is like the previous test,
4116 but it works even if the comparison is done in a mode larger
4117 than HOST_BITS_PER_WIDE_INT. */
4118 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4119 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4120 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4121 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4123 /* Similarly, a truncate of a register whose value is a
4124 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4126 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4127 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4128 && (temp = get_last_value (XEXP (x, 0)))
4129 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4130 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4134 case FLOAT_TRUNCATE:
4135 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4136 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4137 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4138 return XEXP (XEXP (x, 0), 0);
4140 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4141 (OP:SF foo:SF) if OP is NEG or ABS. */
4142 if ((GET_CODE (XEXP (x, 0)) == ABS
4143 || GET_CODE (XEXP (x, 0)) == NEG)
4144 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4145 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4146 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4147 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4149 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4150 is (float_truncate:SF x). */
4151 if (GET_CODE (XEXP (x, 0)) == SUBREG
4152 && subreg_lowpart_p (XEXP (x, 0))
4153 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4154 return SUBREG_REG (XEXP (x, 0));
4159 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4160 using cc0, in which case we want to leave it as a COMPARE
4161 so we can distinguish it from a register-register-copy. */
4162 if (XEXP (x, 1) == const0_rtx)
4165 /* x - 0 is the same as x unless x's mode has signed zeros and
4166 allows rounding towards -infinity. Under those conditions,
4168 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4169 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4170 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4176 /* (const (const X)) can become (const X). Do it this way rather than
4177 returning the inner CONST since CONST can be shared with a
4179 if (GET_CODE (XEXP (x, 0)) == CONST)
4180 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4185 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4186 can add in an offset. find_split_point will split this address up
4187 again if it doesn't match. */
4188 if (GET_CODE (XEXP (x, 0)) == HIGH
4189 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4195 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4196 outermost. That's because that's the way indexed addresses are
4197 supposed to appear. This code used to check many more cases, but
4198 they are now checked elsewhere. */
4199 if (GET_CODE (XEXP (x, 0)) == PLUS
4200 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4201 return gen_binary (PLUS, mode,
4202 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4204 XEXP (XEXP (x, 0), 1));
4206 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4207 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4208 bit-field and can be replaced by either a sign_extend or a
4209 sign_extract. The `and' may be a zero_extend and the two
4210 <c>, -<c> constants may be reversed. */
4211 if (GET_CODE (XEXP (x, 0)) == XOR
4212 && GET_CODE (XEXP (x, 1)) == CONST_INT
4213 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4214 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4215 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4216 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4217 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4218 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4219 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4220 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4221 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4222 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4223 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4224 == (unsigned int) i + 1))))
4225 return simplify_shift_const
4226 (NULL_RTX, ASHIFTRT, mode,
4227 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4228 XEXP (XEXP (XEXP (x, 0), 0), 0),
4229 GET_MODE_BITSIZE (mode) - (i + 1)),
4230 GET_MODE_BITSIZE (mode) - (i + 1));
4232 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4233 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4234 is 1. This produces better code than the alternative immediately
4236 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4237 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4238 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4239 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4240 XEXP (XEXP (x, 0), 0),
4241 XEXP (XEXP (x, 0), 1))))
4243 simplify_gen_unary (NEG, mode, reversed, mode);
4245 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4246 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4247 the bitsize of the mode - 1. This allows simplification of
4248 "a = (b & 8) == 0;" */
4249 if (XEXP (x, 1) == constm1_rtx
4250 && GET_CODE (XEXP (x, 0)) != REG
4251 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4252 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4253 && nonzero_bits (XEXP (x, 0), mode) == 1)
4254 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4255 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4256 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4257 GET_MODE_BITSIZE (mode) - 1),
4258 GET_MODE_BITSIZE (mode) - 1);
4260 /* If we are adding two things that have no bits in common, convert
4261 the addition into an IOR. This will often be further simplified,
4262 for example in cases like ((a & 1) + (a & 2)), which can
4265 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4266 && (nonzero_bits (XEXP (x, 0), mode)
4267 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4269 /* Try to simplify the expression further. */
4270 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4271 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4273 /* If we could, great. If not, do not go ahead with the IOR
4274 replacement, since PLUS appears in many special purpose
4275 address arithmetic instructions. */
4276 if (GET_CODE (temp) != CLOBBER && temp != tor)
4282 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4283 by reversing the comparison code if valid. */
4284 if (STORE_FLAG_VALUE == 1
4285 && XEXP (x, 0) == const1_rtx
4286 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4287 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4288 XEXP (XEXP (x, 1), 0),
4289 XEXP (XEXP (x, 1), 1))))
4292 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4293 (and <foo> (const_int pow2-1)) */
4294 if (GET_CODE (XEXP (x, 1)) == AND
4295 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4296 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4297 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4298 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4299 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4301 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4303 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4304 return gen_binary (MINUS, mode,
4305 gen_binary (MINUS, mode, XEXP (x, 0),
4306 XEXP (XEXP (x, 1), 0)),
4307 XEXP (XEXP (x, 1), 1));
4311 /* If we have (mult (plus A B) C), apply the distributive law and then
4312 the inverse distributive law to see if things simplify. This
4313 occurs mostly in addresses, often when unrolling loops. */
4315 if (GET_CODE (XEXP (x, 0)) == PLUS)
4317 x = apply_distributive_law
4318 (gen_binary (PLUS, mode,
4319 gen_binary (MULT, mode,
4320 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4321 gen_binary (MULT, mode,
4322 XEXP (XEXP (x, 0), 1),
4323 copy_rtx (XEXP (x, 1)))));
4325 if (GET_CODE (x) != MULT)
4328 /* Try simplify a*(b/c) as (a*b)/c. */
4329 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4330 && GET_CODE (XEXP (x, 0)) == DIV)
4332 rtx tem = simplify_binary_operation (MULT, mode,
4333 XEXP (XEXP (x, 0), 0),
4336 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4341 /* If this is a divide by a power of two, treat it as a shift if
4342 its first operand is a shift. */
4343 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4344 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4345 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4346 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4347 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4348 || GET_CODE (XEXP (x, 0)) == ROTATE
4349 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4350 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4354 case GT: case GTU: case GE: case GEU:
4355 case LT: case LTU: case LE: case LEU:
4356 case UNEQ: case LTGT:
4357 case UNGT: case UNGE:
4358 case UNLT: case UNLE:
4359 case UNORDERED: case ORDERED:
4360 /* If the first operand is a condition code, we can't do anything
4362 if (GET_CODE (XEXP (x, 0)) == COMPARE
4363 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4365 && XEXP (x, 0) != cc0_rtx
4369 rtx op0 = XEXP (x, 0);
4370 rtx op1 = XEXP (x, 1);
4371 enum rtx_code new_code;
4373 if (GET_CODE (op0) == COMPARE)
4374 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4376 /* Simplify our comparison, if possible. */
4377 new_code = simplify_comparison (code, &op0, &op1);
4379 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4380 if only the low-order bit is possibly nonzero in X (such as when
4381 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4382 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4383 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4386 Remove any ZERO_EXTRACT we made when thinking this was a
4387 comparison. It may now be simpler to use, e.g., an AND. If a
4388 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4389 the call to make_compound_operation in the SET case. */
4391 if (STORE_FLAG_VALUE == 1
4392 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4393 && op1 == const0_rtx
4394 && mode == GET_MODE (op0)
4395 && nonzero_bits (op0, mode) == 1)
4396 return gen_lowpart_for_combine (mode,
4397 expand_compound_operation (op0));
4399 else if (STORE_FLAG_VALUE == 1
4400 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4401 && op1 == const0_rtx
4402 && mode == GET_MODE (op0)
4403 && (num_sign_bit_copies (op0, mode)
4404 == GET_MODE_BITSIZE (mode)))
4406 op0 = expand_compound_operation (op0);
4407 return simplify_gen_unary (NEG, mode,
4408 gen_lowpart_for_combine (mode, op0),
4412 else if (STORE_FLAG_VALUE == 1
4413 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4414 && op1 == const0_rtx
4415 && mode == GET_MODE (op0)
4416 && nonzero_bits (op0, mode) == 1)
4418 op0 = expand_compound_operation (op0);
4419 return gen_binary (XOR, mode,
4420 gen_lowpart_for_combine (mode, op0),
4424 else if (STORE_FLAG_VALUE == 1
4425 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4426 && op1 == const0_rtx
4427 && mode == GET_MODE (op0)
4428 && (num_sign_bit_copies (op0, mode)
4429 == GET_MODE_BITSIZE (mode)))
4431 op0 = expand_compound_operation (op0);
4432 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4435 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4437 if (STORE_FLAG_VALUE == -1
4438 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4439 && op1 == const0_rtx
4440 && (num_sign_bit_copies (op0, mode)
4441 == GET_MODE_BITSIZE (mode)))
4442 return gen_lowpart_for_combine (mode,
4443 expand_compound_operation (op0));
4445 else if (STORE_FLAG_VALUE == -1
4446 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4447 && op1 == const0_rtx
4448 && mode == GET_MODE (op0)
4449 && nonzero_bits (op0, mode) == 1)
4451 op0 = expand_compound_operation (op0);
4452 return simplify_gen_unary (NEG, mode,
4453 gen_lowpart_for_combine (mode, op0),
4457 else if (STORE_FLAG_VALUE == -1
4458 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4459 && op1 == const0_rtx
4460 && mode == GET_MODE (op0)
4461 && (num_sign_bit_copies (op0, mode)
4462 == GET_MODE_BITSIZE (mode)))
4464 op0 = expand_compound_operation (op0);
4465 return simplify_gen_unary (NOT, mode,
4466 gen_lowpart_for_combine (mode, op0),
4470 /* If X is 0/1, (eq X 0) is X-1. */
4471 else if (STORE_FLAG_VALUE == -1
4472 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4473 && op1 == const0_rtx
4474 && mode == GET_MODE (op0)
4475 && nonzero_bits (op0, mode) == 1)
4477 op0 = expand_compound_operation (op0);
4478 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4481 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4482 one bit that might be nonzero, we can convert (ne x 0) to
4483 (ashift x c) where C puts the bit in the sign bit. Remove any
4484 AND with STORE_FLAG_VALUE when we are done, since we are only
4485 going to test the sign bit. */
4486 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4487 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4488 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4489 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4490 && op1 == const0_rtx
4491 && mode == GET_MODE (op0)
4492 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4494 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4495 expand_compound_operation (op0),
4496 GET_MODE_BITSIZE (mode) - 1 - i);
4497 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4503 /* If the code changed, return a whole new comparison. */
4504 if (new_code != code)
4505 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4507 /* Otherwise, keep this operation, but maybe change its operands.
4508 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4509 SUBST (XEXP (x, 0), op0);
4510 SUBST (XEXP (x, 1), op1);
4515 return simplify_if_then_else (x);
4521 /* If we are processing SET_DEST, we are done. */
4525 return expand_compound_operation (x);
4528 return simplify_set (x);
4533 return simplify_logical (x, last);
4536 /* (abs (neg <foo>)) -> (abs <foo>) */
4537 if (GET_CODE (XEXP (x, 0)) == NEG)
4538 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4540 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4542 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4545 /* If operand is something known to be positive, ignore the ABS. */
4546 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4547 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4548 <= HOST_BITS_PER_WIDE_INT)
4549 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4550 & ((HOST_WIDE_INT) 1
4551 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4555 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4556 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4557 return gen_rtx_NEG (mode, XEXP (x, 0));
4562 /* (ffs (*_extend <X>)) = (ffs <X>) */
4563 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4564 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4565 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4569 /* (float (sign_extend <X>)) = (float <X>). */
4570 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4571 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4579 /* If this is a shift by a constant amount, simplify it. */
4580 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4581 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4582 INTVAL (XEXP (x, 1)));
4584 #ifdef SHIFT_COUNT_TRUNCATED
4585 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4587 force_to_mode (XEXP (x, 1), GET_MODE (x),
4589 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4598 rtx op0 = XEXP (x, 0);
4599 rtx op1 = XEXP (x, 1);
4602 if (GET_CODE (op1) != PARALLEL)
4604 len = XVECLEN (op1, 0);
4606 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4607 && GET_CODE (op0) == VEC_CONCAT)
4609 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4611 /* Try to find the element in the VEC_CONCAT. */
4614 if (GET_MODE (op0) == GET_MODE (x))
4616 if (GET_CODE (op0) == VEC_CONCAT)
4618 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4619 if (op0_size < offset)
4620 op0 = XEXP (op0, 0);
4624 op0 = XEXP (op0, 1);
4642 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4645 simplify_if_then_else (x)
4648 enum machine_mode mode = GET_MODE (x);
4649 rtx cond = XEXP (x, 0);
4650 rtx true_rtx = XEXP (x, 1);
4651 rtx false_rtx = XEXP (x, 2);
4652 enum rtx_code true_code = GET_CODE (cond);
4653 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4656 enum rtx_code false_code;
4659 /* Simplify storing of the truth value. */
4660 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4661 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4663 /* Also when the truth value has to be reversed. */
4665 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4666 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4670 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4671 in it is being compared against certain values. Get the true and false
4672 comparisons and see if that says anything about the value of each arm. */
4675 && ((false_code = combine_reversed_comparison_code (cond))
4677 && GET_CODE (XEXP (cond, 0)) == REG)
4680 rtx from = XEXP (cond, 0);
4681 rtx true_val = XEXP (cond, 1);
4682 rtx false_val = true_val;
4685 /* If FALSE_CODE is EQ, swap the codes and arms. */
4687 if (false_code == EQ)
4689 swapped = 1, true_code = EQ, false_code = NE;
4690 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4693 /* If we are comparing against zero and the expression being tested has
4694 only a single bit that might be nonzero, that is its value when it is
4695 not equal to zero. Similarly if it is known to be -1 or 0. */
4697 if (true_code == EQ && true_val == const0_rtx
4698 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4699 false_code = EQ, false_val = GEN_INT (nzb);
4700 else if (true_code == EQ && true_val == const0_rtx
4701 && (num_sign_bit_copies (from, GET_MODE (from))
4702 == GET_MODE_BITSIZE (GET_MODE (from))))
4703 false_code = EQ, false_val = constm1_rtx;
4705 /* Now simplify an arm if we know the value of the register in the
4706 branch and it is used in the arm. Be careful due to the potential
4707 of locally-shared RTL. */
4709 if (reg_mentioned_p (from, true_rtx))
4710 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4712 pc_rtx, pc_rtx, 0, 0);
4713 if (reg_mentioned_p (from, false_rtx))
4714 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4716 pc_rtx, pc_rtx, 0, 0);
4718 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4719 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4721 true_rtx = XEXP (x, 1);
4722 false_rtx = XEXP (x, 2);
4723 true_code = GET_CODE (cond);
4726 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4727 reversed, do so to avoid needing two sets of patterns for
4728 subtract-and-branch insns. Similarly if we have a constant in the true
4729 arm, the false arm is the same as the first operand of the comparison, or
4730 the false arm is more complicated than the true arm. */
4733 && combine_reversed_comparison_code (cond) != UNKNOWN
4734 && (true_rtx == pc_rtx
4735 || (CONSTANT_P (true_rtx)
4736 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4737 || true_rtx == const0_rtx
4738 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4739 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4740 || (GET_CODE (true_rtx) == SUBREG
4741 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4742 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4743 || reg_mentioned_p (true_rtx, false_rtx)
4744 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4746 true_code = reversed_comparison_code (cond, NULL);
4748 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4751 SUBST (XEXP (x, 1), false_rtx);
4752 SUBST (XEXP (x, 2), true_rtx);
4754 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4757 /* It is possible that the conditional has been simplified out. */
4758 true_code = GET_CODE (cond);
4759 comparison_p = GET_RTX_CLASS (true_code) == '<';
4762 /* If the two arms are identical, we don't need the comparison. */
4764 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4767 /* Convert a == b ? b : a to "a". */
4768 if (true_code == EQ && ! side_effects_p (cond)
4769 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4770 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4771 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4773 else if (true_code == NE && ! side_effects_p (cond)
4774 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4775 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4776 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4779 /* Look for cases where we have (abs x) or (neg (abs X)). */
4781 if (GET_MODE_CLASS (mode) == MODE_INT
4782 && GET_CODE (false_rtx) == NEG
4783 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4785 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4786 && ! side_effects_p (true_rtx))
4791 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4795 simplify_gen_unary (NEG, mode,
4796 simplify_gen_unary (ABS, mode, true_rtx, mode),
4802 /* Look for MIN or MAX. */
4804 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4806 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4807 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4808 && ! side_effects_p (cond))
4813 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4816 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4819 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4822 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4827 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4828 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4829 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4830 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4831 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4832 neither 1 or -1, but it isn't worth checking for. */
4834 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4835 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4837 rtx t = make_compound_operation (true_rtx, SET);
4838 rtx f = make_compound_operation (false_rtx, SET);
4839 rtx cond_op0 = XEXP (cond, 0);
4840 rtx cond_op1 = XEXP (cond, 1);
4841 enum rtx_code op = NIL, extend_op = NIL;
4842 enum machine_mode m = mode;
4843 rtx z = 0, c1 = NULL_RTX;
4845 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4846 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4847 || GET_CODE (t) == ASHIFT
4848 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4849 && rtx_equal_p (XEXP (t, 0), f))
4850 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4852 /* If an identity-zero op is commutative, check whether there
4853 would be a match if we swapped the operands. */
4854 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4855 || GET_CODE (t) == XOR)
4856 && rtx_equal_p (XEXP (t, 1), f))
4857 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4858 else if (GET_CODE (t) == SIGN_EXTEND
4859 && (GET_CODE (XEXP (t, 0)) == PLUS
4860 || GET_CODE (XEXP (t, 0)) == MINUS
4861 || GET_CODE (XEXP (t, 0)) == IOR
4862 || GET_CODE (XEXP (t, 0)) == XOR
4863 || GET_CODE (XEXP (t, 0)) == ASHIFT
4864 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4865 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4866 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4867 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4868 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4869 && (num_sign_bit_copies (f, GET_MODE (f))
4870 > (GET_MODE_BITSIZE (mode)
4871 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4873 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4874 extend_op = SIGN_EXTEND;
4875 m = GET_MODE (XEXP (t, 0));
4877 else if (GET_CODE (t) == SIGN_EXTEND
4878 && (GET_CODE (XEXP (t, 0)) == PLUS
4879 || GET_CODE (XEXP (t, 0)) == IOR
4880 || GET_CODE (XEXP (t, 0)) == XOR)
4881 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4882 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4883 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4884 && (num_sign_bit_copies (f, GET_MODE (f))
4885 > (GET_MODE_BITSIZE (mode)
4886 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4888 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4889 extend_op = SIGN_EXTEND;
4890 m = GET_MODE (XEXP (t, 0));
4892 else if (GET_CODE (t) == ZERO_EXTEND
4893 && (GET_CODE (XEXP (t, 0)) == PLUS
4894 || GET_CODE (XEXP (t, 0)) == MINUS
4895 || GET_CODE (XEXP (t, 0)) == IOR
4896 || GET_CODE (XEXP (t, 0)) == XOR
4897 || GET_CODE (XEXP (t, 0)) == ASHIFT
4898 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4899 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4900 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4901 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4902 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4903 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4904 && ((nonzero_bits (f, GET_MODE (f))
4905 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4908 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4909 extend_op = ZERO_EXTEND;
4910 m = GET_MODE (XEXP (t, 0));
4912 else if (GET_CODE (t) == ZERO_EXTEND
4913 && (GET_CODE (XEXP (t, 0)) == PLUS
4914 || GET_CODE (XEXP (t, 0)) == IOR
4915 || GET_CODE (XEXP (t, 0)) == XOR)
4916 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4917 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4918 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4919 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4920 && ((nonzero_bits (f, GET_MODE (f))
4921 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4924 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4925 extend_op = ZERO_EXTEND;
4926 m = GET_MODE (XEXP (t, 0));
4931 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4932 pc_rtx, pc_rtx, 0, 0);
4933 temp = gen_binary (MULT, m, temp,
4934 gen_binary (MULT, m, c1, const_true_rtx));
4935 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4936 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4938 if (extend_op != NIL)
4939 temp = simplify_gen_unary (extend_op, mode, temp, m);
4945 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4946 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4947 negation of a single bit, we can convert this operation to a shift. We
4948 can actually do this more generally, but it doesn't seem worth it. */
4950 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4951 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4952 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4953 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4954 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4955 == GET_MODE_BITSIZE (mode))
4956 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4958 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4959 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4964 /* Simplify X, a SET expression. Return the new expression. */
4970 rtx src = SET_SRC (x);
4971 rtx dest = SET_DEST (x);
4972 enum machine_mode mode
4973 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4977 /* (set (pc) (return)) gets written as (return). */
4978 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4981 /* Now that we know for sure which bits of SRC we are using, see if we can
4982 simplify the expression for the object knowing that we only need the
4985 if (GET_MODE_CLASS (mode) == MODE_INT)
4987 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4988 SUBST (SET_SRC (x), src);
4991 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4992 the comparison result and try to simplify it unless we already have used
4993 undobuf.other_insn. */
4994 if ((GET_CODE (src) == COMPARE
4999 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5000 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5001 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5002 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5004 enum rtx_code old_code = GET_CODE (*cc_use);
5005 enum rtx_code new_code;
5007 int other_changed = 0;
5008 enum machine_mode compare_mode = GET_MODE (dest);
5010 if (GET_CODE (src) == COMPARE)
5011 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5013 op0 = src, op1 = const0_rtx;
5015 /* Simplify our comparison, if possible. */
5016 new_code = simplify_comparison (old_code, &op0, &op1);
5018 #ifdef EXTRA_CC_MODES
5019 /* If this machine has CC modes other than CCmode, check to see if we
5020 need to use a different CC mode here. */
5021 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5022 #endif /* EXTRA_CC_MODES */
5024 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5025 /* If the mode changed, we have to change SET_DEST, the mode in the
5026 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5027 a hard register, just build new versions with the proper mode. If it
5028 is a pseudo, we lose unless it is only time we set the pseudo, in
5029 which case we can safely change its mode. */
5030 if (compare_mode != GET_MODE (dest))
5032 unsigned int regno = REGNO (dest);
5033 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5035 if (regno < FIRST_PSEUDO_REGISTER
5036 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5038 if (regno >= FIRST_PSEUDO_REGISTER)
5039 SUBST (regno_reg_rtx[regno], new_dest);
5041 SUBST (SET_DEST (x), new_dest);
5042 SUBST (XEXP (*cc_use, 0), new_dest);
5050 /* If the code changed, we have to build a new comparison in
5051 undobuf.other_insn. */
5052 if (new_code != old_code)
5054 unsigned HOST_WIDE_INT mask;
5056 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5059 /* If the only change we made was to change an EQ into an NE or
5060 vice versa, OP0 has only one bit that might be nonzero, and OP1
5061 is zero, check if changing the user of the condition code will
5062 produce a valid insn. If it won't, we can keep the original code
5063 in that insn by surrounding our operation with an XOR. */
5065 if (((old_code == NE && new_code == EQ)
5066 || (old_code == EQ && new_code == NE))
5067 && ! other_changed && op1 == const0_rtx
5068 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5069 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5071 rtx pat = PATTERN (other_insn), note = 0;
5073 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5074 && ! check_asm_operands (pat)))
5076 PUT_CODE (*cc_use, old_code);
5079 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5087 undobuf.other_insn = other_insn;
5090 /* If we are now comparing against zero, change our source if
5091 needed. If we do not use cc0, we always have a COMPARE. */
5092 if (op1 == const0_rtx && dest == cc0_rtx)
5094 SUBST (SET_SRC (x), op0);
5100 /* Otherwise, if we didn't previously have a COMPARE in the
5101 correct mode, we need one. */
5102 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5104 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5109 /* Otherwise, update the COMPARE if needed. */
5110 SUBST (XEXP (src, 0), op0);
5111 SUBST (XEXP (src, 1), op1);
5116 /* Get SET_SRC in a form where we have placed back any
5117 compound expressions. Then do the checks below. */
5118 src = make_compound_operation (src, SET);
5119 SUBST (SET_SRC (x), src);
5122 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5123 and X being a REG or (subreg (reg)), we may be able to convert this to
5124 (set (subreg:m2 x) (op)).
5126 We can always do this if M1 is narrower than M2 because that means that
5127 we only care about the low bits of the result.
5129 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5130 perform a narrower operation than requested since the high-order bits will
5131 be undefined. On machine where it is defined, this transformation is safe
5132 as long as M1 and M2 have the same number of words. */
5134 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5135 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5136 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5138 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5139 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5140 #ifndef WORD_REGISTER_OPERATIONS
5141 && (GET_MODE_SIZE (GET_MODE (src))
5142 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5144 #ifdef CLASS_CANNOT_CHANGE_MODE
5145 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5146 && (TEST_HARD_REG_BIT
5147 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5149 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5150 GET_MODE (SUBREG_REG (src))))
5152 && (GET_CODE (dest) == REG
5153 || (GET_CODE (dest) == SUBREG
5154 && GET_CODE (SUBREG_REG (dest)) == REG)))
5156 SUBST (SET_DEST (x),
5157 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5159 SUBST (SET_SRC (x), SUBREG_REG (src));
5161 src = SET_SRC (x), dest = SET_DEST (x);
5164 #ifdef LOAD_EXTEND_OP
5165 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5166 would require a paradoxical subreg. Replace the subreg with a
5167 zero_extend to avoid the reload that would otherwise be required. */
5169 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5170 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5171 && SUBREG_BYTE (src) == 0
5172 && (GET_MODE_SIZE (GET_MODE (src))
5173 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5174 && GET_CODE (SUBREG_REG (src)) == MEM)
5177 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5178 GET_MODE (src), SUBREG_REG (src)));
5184 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5185 are comparing an item known to be 0 or -1 against 0, use a logical
5186 operation instead. Check for one of the arms being an IOR of the other
5187 arm with some value. We compute three terms to be IOR'ed together. In
5188 practice, at most two will be nonzero. Then we do the IOR's. */
5190 if (GET_CODE (dest) != PC
5191 && GET_CODE (src) == IF_THEN_ELSE
5192 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5193 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5194 && XEXP (XEXP (src, 0), 1) == const0_rtx
5195 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5196 #ifdef HAVE_conditional_move
5197 && ! can_conditionally_move_p (GET_MODE (src))
5199 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5200 GET_MODE (XEXP (XEXP (src, 0), 0)))
5201 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5202 && ! side_effects_p (src))
5204 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5205 ? XEXP (src, 1) : XEXP (src, 2));
5206 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5207 ? XEXP (src, 2) : XEXP (src, 1));
5208 rtx term1 = const0_rtx, term2, term3;
5210 if (GET_CODE (true_rtx) == IOR
5211 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5212 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5213 else if (GET_CODE (true_rtx) == IOR
5214 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5215 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5216 else if (GET_CODE (false_rtx) == IOR
5217 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5218 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5219 else if (GET_CODE (false_rtx) == IOR
5220 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5221 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5223 term2 = gen_binary (AND, GET_MODE (src),
5224 XEXP (XEXP (src, 0), 0), true_rtx);
5225 term3 = gen_binary (AND, GET_MODE (src),
5226 simplify_gen_unary (NOT, GET_MODE (src),
5227 XEXP (XEXP (src, 0), 0),
5232 gen_binary (IOR, GET_MODE (src),
5233 gen_binary (IOR, GET_MODE (src), term1, term2),
5239 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5240 whole thing fail. */
5241 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5243 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5246 /* Convert this into a field assignment operation, if possible. */
5247 return make_field_assignment (x);
5250 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5251 result. LAST is nonzero if this is the last retry. */
5254 simplify_logical (x, last)
5258 enum machine_mode mode = GET_MODE (x);
5259 rtx op0 = XEXP (x, 0);
5260 rtx op1 = XEXP (x, 1);
5263 switch (GET_CODE (x))
5266 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5267 insn (and may simplify more). */
5268 if (GET_CODE (op0) == XOR
5269 && rtx_equal_p (XEXP (op0, 0), op1)
5270 && ! side_effects_p (op1))
5271 x = gen_binary (AND, mode,
5272 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5275 if (GET_CODE (op0) == XOR
5276 && rtx_equal_p (XEXP (op0, 1), op1)
5277 && ! side_effects_p (op1))
5278 x = gen_binary (AND, mode,
5279 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5282 /* Similarly for (~(A ^ B)) & A. */
5283 if (GET_CODE (op0) == NOT
5284 && GET_CODE (XEXP (op0, 0)) == XOR
5285 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5286 && ! side_effects_p (op1))
5287 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5289 if (GET_CODE (op0) == NOT
5290 && GET_CODE (XEXP (op0, 0)) == XOR
5291 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5292 && ! side_effects_p (op1))
5293 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5295 /* We can call simplify_and_const_int only if we don't lose
5296 any (sign) bits when converting INTVAL (op1) to
5297 "unsigned HOST_WIDE_INT". */
5298 if (GET_CODE (op1) == CONST_INT
5299 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5300 || INTVAL (op1) > 0))
5302 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5304 /* If we have (ior (and (X C1) C2)) and the next restart would be
5305 the last, simplify this by making C1 as small as possible
5308 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5309 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5310 && GET_CODE (op1) == CONST_INT)
5311 return gen_binary (IOR, mode,
5312 gen_binary (AND, mode, XEXP (op0, 0),
5313 GEN_INT (INTVAL (XEXP (op0, 1))
5314 & ~INTVAL (op1))), op1);
5316 if (GET_CODE (x) != AND)
5319 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5320 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5321 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5324 /* Convert (A | B) & A to A. */
5325 if (GET_CODE (op0) == IOR
5326 && (rtx_equal_p (XEXP (op0, 0), op1)
5327 || rtx_equal_p (XEXP (op0, 1), op1))
5328 && ! side_effects_p (XEXP (op0, 0))
5329 && ! side_effects_p (XEXP (op0, 1)))
5332 /* In the following group of tests (and those in case IOR below),
5333 we start with some combination of logical operations and apply
5334 the distributive law followed by the inverse distributive law.
5335 Most of the time, this results in no change. However, if some of
5336 the operands are the same or inverses of each other, simplifications
5339 For example, (and (ior A B) (not B)) can occur as the result of
5340 expanding a bit field assignment. When we apply the distributive
5341 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5342 which then simplifies to (and (A (not B))).
5344 If we have (and (ior A B) C), apply the distributive law and then
5345 the inverse distributive law to see if things simplify. */
5347 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5349 x = apply_distributive_law
5350 (gen_binary (GET_CODE (op0), mode,
5351 gen_binary (AND, mode, XEXP (op0, 0), op1),
5352 gen_binary (AND, mode, XEXP (op0, 1),
5354 if (GET_CODE (x) != AND)
5358 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5359 return apply_distributive_law
5360 (gen_binary (GET_CODE (op1), mode,
5361 gen_binary (AND, mode, XEXP (op1, 0), op0),
5362 gen_binary (AND, mode, XEXP (op1, 1),
5365 /* Similarly, taking advantage of the fact that
5366 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5368 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5369 return apply_distributive_law
5370 (gen_binary (XOR, mode,
5371 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5372 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5375 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5376 return apply_distributive_law
5377 (gen_binary (XOR, mode,
5378 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5379 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5383 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5384 if (GET_CODE (op1) == CONST_INT
5385 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5386 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5389 /* Convert (A & B) | A to A. */
5390 if (GET_CODE (op0) == AND
5391 && (rtx_equal_p (XEXP (op0, 0), op1)
5392 || rtx_equal_p (XEXP (op0, 1), op1))
5393 && ! side_effects_p (XEXP (op0, 0))
5394 && ! side_effects_p (XEXP (op0, 1)))
5397 /* If we have (ior (and A B) C), apply the distributive law and then
5398 the inverse distributive law to see if things simplify. */
5400 if (GET_CODE (op0) == AND)
5402 x = apply_distributive_law
5403 (gen_binary (AND, mode,
5404 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5405 gen_binary (IOR, mode, XEXP (op0, 1),
5408 if (GET_CODE (x) != IOR)
5412 if (GET_CODE (op1) == AND)
5414 x = apply_distributive_law
5415 (gen_binary (AND, mode,
5416 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5417 gen_binary (IOR, mode, XEXP (op1, 1),
5420 if (GET_CODE (x) != IOR)
5424 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5425 mode size to (rotate A CX). */
5427 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5428 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5429 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5430 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5431 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5432 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5433 == GET_MODE_BITSIZE (mode)))
5434 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5435 (GET_CODE (op0) == ASHIFT
5436 ? XEXP (op0, 1) : XEXP (op1, 1)));
5438 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5439 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5440 does not affect any of the bits in OP1, it can really be done
5441 as a PLUS and we can associate. We do this by seeing if OP1
5442 can be safely shifted left C bits. */
5443 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5444 && GET_CODE (XEXP (op0, 0)) == PLUS
5445 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5446 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5447 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5449 int count = INTVAL (XEXP (op0, 1));
5450 HOST_WIDE_INT mask = INTVAL (op1) << count;
5452 if (mask >> count == INTVAL (op1)
5453 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5455 SUBST (XEXP (XEXP (op0, 0), 1),
5456 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5463 /* If we are XORing two things that have no bits in common,
5464 convert them into an IOR. This helps to detect rotation encoded
5465 using those methods and possibly other simplifications. */
5467 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5468 && (nonzero_bits (op0, mode)
5469 & nonzero_bits (op1, mode)) == 0)
5470 return (gen_binary (IOR, mode, op0, op1));
5472 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5473 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5476 int num_negated = 0;
5478 if (GET_CODE (op0) == NOT)
5479 num_negated++, op0 = XEXP (op0, 0);
5480 if (GET_CODE (op1) == NOT)
5481 num_negated++, op1 = XEXP (op1, 0);
5483 if (num_negated == 2)
5485 SUBST (XEXP (x, 0), op0);
5486 SUBST (XEXP (x, 1), op1);
5488 else if (num_negated == 1)
5490 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5494 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5495 correspond to a machine insn or result in further simplifications
5496 if B is a constant. */
5498 if (GET_CODE (op0) == AND
5499 && rtx_equal_p (XEXP (op0, 1), op1)
5500 && ! side_effects_p (op1))
5501 return gen_binary (AND, mode,
5502 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5505 else if (GET_CODE (op0) == AND
5506 && rtx_equal_p (XEXP (op0, 0), op1)
5507 && ! side_effects_p (op1))
5508 return gen_binary (AND, mode,
5509 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5512 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5513 comparison if STORE_FLAG_VALUE is 1. */
5514 if (STORE_FLAG_VALUE == 1
5515 && op1 == const1_rtx
5516 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5517 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5521 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5522 is (lt foo (const_int 0)), so we can perform the above
5523 simplification if STORE_FLAG_VALUE is 1. */
5525 if (STORE_FLAG_VALUE == 1
5526 && op1 == const1_rtx
5527 && GET_CODE (op0) == LSHIFTRT
5528 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5529 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5530 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5532 /* (xor (comparison foo bar) (const_int sign-bit))
5533 when STORE_FLAG_VALUE is the sign bit. */
5534 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5535 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5536 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5537 && op1 == const_true_rtx
5538 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5539 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5552 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5553 operations" because they can be replaced with two more basic operations.
5554 ZERO_EXTEND is also considered "compound" because it can be replaced with
5555 an AND operation, which is simpler, though only one operation.
5557 The function expand_compound_operation is called with an rtx expression
5558 and will convert it to the appropriate shifts and AND operations,
5559 simplifying at each stage.
5561 The function make_compound_operation is called to convert an expression
5562 consisting of shifts and ANDs into the equivalent compound expression.
5563 It is the inverse of this function, loosely speaking. */
5566 expand_compound_operation (x)
5569 unsigned HOST_WIDE_INT pos = 0, len;
5571 unsigned int modewidth;
5574 switch (GET_CODE (x))
5579 /* We can't necessarily use a const_int for a multiword mode;
5580 it depends on implicitly extending the value.
5581 Since we don't know the right way to extend it,
5582 we can't tell whether the implicit way is right.
5584 Even for a mode that is no wider than a const_int,
5585 we can't win, because we need to sign extend one of its bits through
5586 the rest of it, and we don't know which bit. */
5587 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5590 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5591 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5592 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5593 reloaded. If not for that, MEM's would very rarely be safe.
5595 Reject MODEs bigger than a word, because we might not be able
5596 to reference a two-register group starting with an arbitrary register
5597 (and currently gen_lowpart might crash for a SUBREG). */
5599 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5602 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5603 /* If the inner object has VOIDmode (the only way this can happen
5604 is if it is an ASM_OPERANDS), we can't do anything since we don't
5605 know how much masking to do. */
5614 /* If the operand is a CLOBBER, just return it. */
5615 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5618 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5619 || GET_CODE (XEXP (x, 2)) != CONST_INT
5620 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5623 len = INTVAL (XEXP (x, 1));
5624 pos = INTVAL (XEXP (x, 2));
5626 /* If this goes outside the object being extracted, replace the object
5627 with a (use (mem ...)) construct that only combine understands
5628 and is used only for this purpose. */
5629 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5630 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5632 if (BITS_BIG_ENDIAN)
5633 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5640 /* Convert sign extension to zero extension, if we know that the high
5641 bit is not set, as this is easier to optimize. It will be converted
5642 back to cheaper alternative in make_extraction. */
5643 if (GET_CODE (x) == SIGN_EXTEND
5644 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5645 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5646 & ~(((unsigned HOST_WIDE_INT)
5647 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5651 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5652 return expand_compound_operation (temp);
5655 /* We can optimize some special cases of ZERO_EXTEND. */
5656 if (GET_CODE (x) == ZERO_EXTEND)
5658 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5659 know that the last value didn't have any inappropriate bits
5661 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5662 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5663 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5664 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5665 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5666 return XEXP (XEXP (x, 0), 0);
5668 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5669 if (GET_CODE (XEXP (x, 0)) == SUBREG
5670 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5671 && subreg_lowpart_p (XEXP (x, 0))
5672 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5673 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5674 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5675 return SUBREG_REG (XEXP (x, 0));
5677 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5678 is a comparison and STORE_FLAG_VALUE permits. This is like
5679 the first case, but it works even when GET_MODE (x) is larger
5680 than HOST_WIDE_INT. */
5681 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5682 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5683 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5684 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5685 <= HOST_BITS_PER_WIDE_INT)
5686 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5687 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5688 return XEXP (XEXP (x, 0), 0);
5690 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5691 if (GET_CODE (XEXP (x, 0)) == SUBREG
5692 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5693 && subreg_lowpart_p (XEXP (x, 0))
5694 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5695 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5696 <= HOST_BITS_PER_WIDE_INT)
5697 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5698 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5699 return SUBREG_REG (XEXP (x, 0));
5703 /* If we reach here, we want to return a pair of shifts. The inner
5704 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5705 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5706 logical depending on the value of UNSIGNEDP.
5708 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5709 converted into an AND of a shift.
5711 We must check for the case where the left shift would have a negative
5712 count. This can happen in a case like (x >> 31) & 255 on machines
5713 that can't shift by a constant. On those machines, we would first
5714 combine the shift with the AND to produce a variable-position
5715 extraction. Then the constant of 31 would be substituted in to produce
5716 a such a position. */
5718 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5719 if (modewidth + len >= pos)
5720 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5722 simplify_shift_const (NULL_RTX, ASHIFT,
5725 modewidth - pos - len),
5728 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5729 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5730 simplify_shift_const (NULL_RTX, LSHIFTRT,
5733 ((HOST_WIDE_INT) 1 << len) - 1);
5735 /* Any other cases we can't handle. */
5738 /* If we couldn't do this for some reason, return the original
5740 if (GET_CODE (tem) == CLOBBER)
5746 /* X is a SET which contains an assignment of one object into
5747 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5748 or certain SUBREGS). If possible, convert it into a series of
5751 We half-heartedly support variable positions, but do not at all
5752 support variable lengths. */
5755 expand_field_assignment (x)
5759 rtx pos; /* Always counts from low bit. */
5762 enum machine_mode compute_mode;
5764 /* Loop until we find something we can't simplify. */
5767 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5768 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5770 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5771 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5772 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5774 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5775 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5777 inner = XEXP (SET_DEST (x), 0);
5778 len = INTVAL (XEXP (SET_DEST (x), 1));
5779 pos = XEXP (SET_DEST (x), 2);
5781 /* If the position is constant and spans the width of INNER,
5782 surround INNER with a USE to indicate this. */
5783 if (GET_CODE (pos) == CONST_INT
5784 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5785 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5787 if (BITS_BIG_ENDIAN)
5789 if (GET_CODE (pos) == CONST_INT)
5790 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5792 else if (GET_CODE (pos) == MINUS
5793 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5794 && (INTVAL (XEXP (pos, 1))
5795 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5796 /* If position is ADJUST - X, new position is X. */
5797 pos = XEXP (pos, 0);
5799 pos = gen_binary (MINUS, GET_MODE (pos),
5800 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5806 /* A SUBREG between two modes that occupy the same numbers of words
5807 can be done by moving the SUBREG to the source. */
5808 else if (GET_CODE (SET_DEST (x)) == SUBREG
5809 /* We need SUBREGs to compute nonzero_bits properly. */
5810 && nonzero_sign_valid
5811 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5812 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5813 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5814 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5816 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5817 gen_lowpart_for_combine
5818 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5825 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5826 inner = SUBREG_REG (inner);
5828 compute_mode = GET_MODE (inner);
5830 /* Don't attempt bitwise arithmetic on non-integral modes. */
5831 if (! INTEGRAL_MODE_P (compute_mode))
5833 enum machine_mode imode;
5835 /* Something is probably seriously wrong if this matches. */
5836 if (! FLOAT_MODE_P (compute_mode))
5839 /* Try to find an integral mode to pun with. */
5840 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5841 if (imode == BLKmode)
5844 compute_mode = imode;
5845 inner = gen_lowpart_for_combine (imode, inner);
5848 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5849 if (len < HOST_BITS_PER_WIDE_INT)
5850 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5854 /* Now compute the equivalent expression. Make a copy of INNER
5855 for the SET_DEST in case it is a MEM into which we will substitute;
5856 we don't want shared RTL in that case. */
5858 (VOIDmode, copy_rtx (inner),
5859 gen_binary (IOR, compute_mode,
5860 gen_binary (AND, compute_mode,
5861 simplify_gen_unary (NOT, compute_mode,
5867 gen_binary (ASHIFT, compute_mode,
5868 gen_binary (AND, compute_mode,
5869 gen_lowpart_for_combine
5870 (compute_mode, SET_SRC (x)),
5878 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5879 it is an RTX that represents a variable starting position; otherwise,
5880 POS is the (constant) starting bit position (counted from the LSB).
5882 INNER may be a USE. This will occur when we started with a bitfield
5883 that went outside the boundary of the object in memory, which is
5884 allowed on most machines. To isolate this case, we produce a USE
5885 whose mode is wide enough and surround the MEM with it. The only
5886 code that understands the USE is this routine. If it is not removed,
5887 it will cause the resulting insn not to match.
5889 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5892 IN_DEST is non-zero if this is a reference in the destination of a
5893 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5894 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5897 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5898 ZERO_EXTRACT should be built even for bits starting at bit 0.
5900 MODE is the desired mode of the result (if IN_DEST == 0).
5902 The result is an RTX for the extraction or NULL_RTX if the target
5906 make_extraction (mode, inner, pos, pos_rtx, len,
5907 unsignedp, in_dest, in_compare)
5908 enum machine_mode mode;
5912 unsigned HOST_WIDE_INT len;
5914 int in_dest, in_compare;
5916 /* This mode describes the size of the storage area
5917 to fetch the overall value from. Within that, we
5918 ignore the POS lowest bits, etc. */
5919 enum machine_mode is_mode = GET_MODE (inner);
5920 enum machine_mode inner_mode;
5921 enum machine_mode wanted_inner_mode = byte_mode;
5922 enum machine_mode wanted_inner_reg_mode = word_mode;
5923 enum machine_mode pos_mode = word_mode;
5924 enum machine_mode extraction_mode = word_mode;
5925 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5928 rtx orig_pos_rtx = pos_rtx;
5929 HOST_WIDE_INT orig_pos;
5931 /* Get some information about INNER and get the innermost object. */
5932 if (GET_CODE (inner) == USE)
5933 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5934 /* We don't need to adjust the position because we set up the USE
5935 to pretend that it was a full-word object. */
5936 spans_byte = 1, inner = XEXP (inner, 0);
5937 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5939 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5940 consider just the QI as the memory to extract from.
5941 The subreg adds or removes high bits; its mode is
5942 irrelevant to the meaning of this extraction,
5943 since POS and LEN count from the lsb. */
5944 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5945 is_mode = GET_MODE (SUBREG_REG (inner));
5946 inner = SUBREG_REG (inner);
5949 inner_mode = GET_MODE (inner);
5951 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5952 pos = INTVAL (pos_rtx), pos_rtx = 0;
5954 /* See if this can be done without an extraction. We never can if the
5955 width of the field is not the same as that of some integer mode. For
5956 registers, we can only avoid the extraction if the position is at the
5957 low-order bit and this is either not in the destination or we have the
5958 appropriate STRICT_LOW_PART operation available.
5960 For MEM, we can avoid an extract if the field starts on an appropriate
5961 boundary and we can change the mode of the memory reference. However,
5962 we cannot directly access the MEM if we have a USE and the underlying
5963 MEM is not TMODE. This combination means that MEM was being used in a
5964 context where bits outside its mode were being referenced; that is only
5965 valid in bit-field insns. */
5967 if (tmode != BLKmode
5968 && ! (spans_byte && inner_mode != tmode)
5969 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5970 && GET_CODE (inner) != MEM
5972 || (GET_CODE (inner) == REG
5973 && have_insn_for (STRICT_LOW_PART, tmode))))
5974 || (GET_CODE (inner) == MEM && pos_rtx == 0
5976 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5977 : BITS_PER_UNIT)) == 0
5978 /* We can't do this if we are widening INNER_MODE (it
5979 may not be aligned, for one thing). */
5980 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5981 && (inner_mode == tmode
5982 || (! mode_dependent_address_p (XEXP (inner, 0))
5983 && ! MEM_VOLATILE_P (inner))))))
5985 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5986 field. If the original and current mode are the same, we need not
5987 adjust the offset. Otherwise, we do if bytes big endian.
5989 If INNER is not a MEM, get a piece consisting of just the field
5990 of interest (in this case POS % BITS_PER_WORD must be 0). */
5992 if (GET_CODE (inner) == MEM)
5994 HOST_WIDE_INT offset;
5996 /* POS counts from lsb, but make OFFSET count in memory order. */
5997 if (BYTES_BIG_ENDIAN)
5998 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6000 offset = pos / BITS_PER_UNIT;
6002 new = adjust_address_nv (inner, tmode, offset);
6004 else if (GET_CODE (inner) == REG)
6006 /* We can't call gen_lowpart_for_combine here since we always want
6007 a SUBREG and it would sometimes return a new hard register. */
6008 if (tmode != inner_mode)
6010 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6012 if (WORDS_BIG_ENDIAN
6013 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6014 final_word = ((GET_MODE_SIZE (inner_mode)
6015 - GET_MODE_SIZE (tmode))
6016 / UNITS_PER_WORD) - final_word;
6018 final_word *= UNITS_PER_WORD;
6019 if (BYTES_BIG_ENDIAN &&
6020 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6021 final_word += (GET_MODE_SIZE (inner_mode)
6022 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6024 new = gen_rtx_SUBREG (tmode, inner, final_word);
6030 new = force_to_mode (inner, tmode,
6031 len >= HOST_BITS_PER_WIDE_INT
6032 ? ~(unsigned HOST_WIDE_INT) 0
6033 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6036 /* If this extraction is going into the destination of a SET,
6037 make a STRICT_LOW_PART unless we made a MEM. */
6040 return (GET_CODE (new) == MEM ? new
6041 : (GET_CODE (new) != SUBREG
6042 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6043 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6048 if (GET_CODE (new) == CONST_INT)
6049 return gen_int_mode (INTVAL (new), mode);
6051 /* If we know that no extraneous bits are set, and that the high
6052 bit is not set, convert the extraction to the cheaper of
6053 sign and zero extension, that are equivalent in these cases. */
6054 if (flag_expensive_optimizations
6055 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6056 && ((nonzero_bits (new, tmode)
6057 & ~(((unsigned HOST_WIDE_INT)
6058 GET_MODE_MASK (tmode))
6062 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6063 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6065 /* Prefer ZERO_EXTENSION, since it gives more information to
6067 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6072 /* Otherwise, sign- or zero-extend unless we already are in the
6075 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6079 /* Unless this is a COMPARE or we have a funny memory reference,
6080 don't do anything with zero-extending field extracts starting at
6081 the low-order bit since they are simple AND operations. */
6082 if (pos_rtx == 0 && pos == 0 && ! in_dest
6083 && ! in_compare && ! spans_byte && unsignedp)
6086 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6087 we would be spanning bytes or if the position is not a constant and the
6088 length is not 1. In all other cases, we would only be going outside
6089 our object in cases when an original shift would have been
6091 if (! spans_byte && GET_CODE (inner) == MEM
6092 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6093 || (pos_rtx != 0 && len != 1)))
6096 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6097 and the mode for the result. */
6098 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6100 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6101 pos_mode = mode_for_extraction (EP_insv, 2);
6102 extraction_mode = mode_for_extraction (EP_insv, 3);
6105 if (! in_dest && unsignedp
6106 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6108 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6109 pos_mode = mode_for_extraction (EP_extzv, 3);
6110 extraction_mode = mode_for_extraction (EP_extzv, 0);
6113 if (! in_dest && ! unsignedp
6114 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6116 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6117 pos_mode = mode_for_extraction (EP_extv, 3);
6118 extraction_mode = mode_for_extraction (EP_extv, 0);
6121 /* Never narrow an object, since that might not be safe. */
6123 if (mode != VOIDmode
6124 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6125 extraction_mode = mode;
6127 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6128 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6129 pos_mode = GET_MODE (pos_rtx);
6131 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6132 if we have to change the mode of memory and cannot, the desired mode is
6134 if (GET_CODE (inner) != MEM)
6135 wanted_inner_mode = wanted_inner_reg_mode;
6136 else if (inner_mode != wanted_inner_mode
6137 && (mode_dependent_address_p (XEXP (inner, 0))
6138 || MEM_VOLATILE_P (inner)))
6139 wanted_inner_mode = extraction_mode;
6143 if (BITS_BIG_ENDIAN)
6145 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6146 BITS_BIG_ENDIAN style. If position is constant, compute new
6147 position. Otherwise, build subtraction.
6148 Note that POS is relative to the mode of the original argument.
6149 If it's a MEM we need to recompute POS relative to that.
6150 However, if we're extracting from (or inserting into) a register,
6151 we want to recompute POS relative to wanted_inner_mode. */
6152 int width = (GET_CODE (inner) == MEM
6153 ? GET_MODE_BITSIZE (is_mode)
6154 : GET_MODE_BITSIZE (wanted_inner_mode));
6157 pos = width - len - pos;
6160 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6161 /* POS may be less than 0 now, but we check for that below.
6162 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6165 /* If INNER has a wider mode, make it smaller. If this is a constant
6166 extract, try to adjust the byte to point to the byte containing
6168 if (wanted_inner_mode != VOIDmode
6169 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6170 && ((GET_CODE (inner) == MEM
6171 && (inner_mode == wanted_inner_mode
6172 || (! mode_dependent_address_p (XEXP (inner, 0))
6173 && ! MEM_VOLATILE_P (inner))))))
6177 /* The computations below will be correct if the machine is big
6178 endian in both bits and bytes or little endian in bits and bytes.
6179 If it is mixed, we must adjust. */
6181 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6182 adjust OFFSET to compensate. */
6183 if (BYTES_BIG_ENDIAN
6185 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6186 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6188 /* If this is a constant position, we can move to the desired byte. */
6191 offset += pos / BITS_PER_UNIT;
6192 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6195 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6197 && is_mode != wanted_inner_mode)
6198 offset = (GET_MODE_SIZE (is_mode)
6199 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6201 if (offset != 0 || inner_mode != wanted_inner_mode)
6202 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6205 /* If INNER is not memory, we can always get it into the proper mode. If we
6206 are changing its mode, POS must be a constant and smaller than the size
6208 else if (GET_CODE (inner) != MEM)
6210 if (GET_MODE (inner) != wanted_inner_mode
6212 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6215 inner = force_to_mode (inner, wanted_inner_mode,
6217 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6218 ? ~(unsigned HOST_WIDE_INT) 0
6219 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6224 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6225 have to zero extend. Otherwise, we can just use a SUBREG. */
6227 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6229 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6231 /* If we know that no extraneous bits are set, and that the high
6232 bit is not set, convert extraction to cheaper one - either
6233 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6235 if (flag_expensive_optimizations
6236 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6237 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6238 & ~(((unsigned HOST_WIDE_INT)
6239 GET_MODE_MASK (GET_MODE (pos_rtx)))
6243 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6245 /* Prefer ZERO_EXTENSION, since it gives more information to
6247 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6252 else if (pos_rtx != 0
6253 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6254 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6256 /* Make POS_RTX unless we already have it and it is correct. If we don't
6257 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6259 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6260 pos_rtx = orig_pos_rtx;
6262 else if (pos_rtx == 0)
6263 pos_rtx = GEN_INT (pos);
6265 /* Make the required operation. See if we can use existing rtx. */
6266 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6267 extraction_mode, inner, GEN_INT (len), pos_rtx);
6269 new = gen_lowpart_for_combine (mode, new);
6274 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6275 with any other operations in X. Return X without that shift if so. */
6278 extract_left_shift (x, count)
6282 enum rtx_code code = GET_CODE (x);
6283 enum machine_mode mode = GET_MODE (x);
6289 /* This is the shift itself. If it is wide enough, we will return
6290 either the value being shifted if the shift count is equal to
6291 COUNT or a shift for the difference. */
6292 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6293 && INTVAL (XEXP (x, 1)) >= count)
6294 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6295 INTVAL (XEXP (x, 1)) - count);
6299 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6300 return simplify_gen_unary (code, mode, tem, mode);
6304 case PLUS: case IOR: case XOR: case AND:
6305 /* If we can safely shift this constant and we find the inner shift,
6306 make a new operation. */
6307 if (GET_CODE (XEXP (x,1)) == CONST_INT
6308 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6309 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6310 return gen_binary (code, mode, tem,
6311 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6322 /* Look at the expression rooted at X. Look for expressions
6323 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6324 Form these expressions.
6326 Return the new rtx, usually just X.
6328 Also, for machines like the VAX that don't have logical shift insns,
6329 try to convert logical to arithmetic shift operations in cases where
6330 they are equivalent. This undoes the canonicalizations to logical
6331 shifts done elsewhere.
6333 We try, as much as possible, to re-use rtl expressions to save memory.
6335 IN_CODE says what kind of expression we are processing. Normally, it is
6336 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6337 being kludges), it is MEM. When processing the arguments of a comparison
6338 or a COMPARE against zero, it is COMPARE. */
6341 make_compound_operation (x, in_code)
6343 enum rtx_code in_code;
6345 enum rtx_code code = GET_CODE (x);
6346 enum machine_mode mode = GET_MODE (x);
6347 int mode_width = GET_MODE_BITSIZE (mode);
6349 enum rtx_code next_code;
6355 /* Select the code to be used in recursive calls. Once we are inside an
6356 address, we stay there. If we have a comparison, set to COMPARE,
6357 but once inside, go back to our default of SET. */
6359 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6360 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6361 && XEXP (x, 1) == const0_rtx) ? COMPARE
6362 : in_code == COMPARE ? SET : in_code);
6364 /* Process depending on the code of this operation. If NEW is set
6365 non-zero, it will be returned. */
6370 /* Convert shifts by constants into multiplications if inside
6372 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6373 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6374 && INTVAL (XEXP (x, 1)) >= 0)
6376 new = make_compound_operation (XEXP (x, 0), next_code);
6377 new = gen_rtx_MULT (mode, new,
6378 GEN_INT ((HOST_WIDE_INT) 1
6379 << INTVAL (XEXP (x, 1))));
6384 /* If the second operand is not a constant, we can't do anything
6386 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6389 /* If the constant is a power of two minus one and the first operand
6390 is a logical right shift, make an extraction. */
6391 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6392 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6394 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6395 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6396 0, in_code == COMPARE);
6399 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6400 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6401 && subreg_lowpart_p (XEXP (x, 0))
6402 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6403 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6405 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6407 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6408 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6409 0, in_code == COMPARE);
6411 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6412 else if ((GET_CODE (XEXP (x, 0)) == XOR
6413 || GET_CODE (XEXP (x, 0)) == IOR)
6414 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6415 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6416 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6418 /* Apply the distributive law, and then try to make extractions. */
6419 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6420 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6422 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6424 new = make_compound_operation (new, in_code);
6427 /* If we are have (and (rotate X C) M) and C is larger than the number
6428 of bits in M, this is an extraction. */
6430 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6431 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6432 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6433 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6435 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6436 new = make_extraction (mode, new,
6437 (GET_MODE_BITSIZE (mode)
6438 - INTVAL (XEXP (XEXP (x, 0), 1))),
6439 NULL_RTX, i, 1, 0, in_code == COMPARE);
6442 /* On machines without logical shifts, if the operand of the AND is
6443 a logical shift and our mask turns off all the propagated sign
6444 bits, we can replace the logical shift with an arithmetic shift. */
6445 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6446 && !have_insn_for (LSHIFTRT, mode)
6447 && have_insn_for (ASHIFTRT, mode)
6448 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6449 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6450 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6451 && mode_width <= HOST_BITS_PER_WIDE_INT)
6453 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6455 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6456 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6458 gen_rtx_ASHIFTRT (mode,
6459 make_compound_operation
6460 (XEXP (XEXP (x, 0), 0), next_code),
6461 XEXP (XEXP (x, 0), 1)));
6464 /* If the constant is one less than a power of two, this might be
6465 representable by an extraction even if no shift is present.
6466 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6467 we are in a COMPARE. */
6468 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6469 new = make_extraction (mode,
6470 make_compound_operation (XEXP (x, 0),
6472 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6474 /* If we are in a comparison and this is an AND with a power of two,
6475 convert this into the appropriate bit extract. */
6476 else if (in_code == COMPARE
6477 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6478 new = make_extraction (mode,
6479 make_compound_operation (XEXP (x, 0),
6481 i, NULL_RTX, 1, 1, 0, 1);
6486 /* If the sign bit is known to be zero, replace this with an
6487 arithmetic shift. */
6488 if (have_insn_for (ASHIFTRT, mode)
6489 && ! have_insn_for (LSHIFTRT, mode)
6490 && mode_width <= HOST_BITS_PER_WIDE_INT
6491 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6493 new = gen_rtx_ASHIFTRT (mode,
6494 make_compound_operation (XEXP (x, 0),
6500 /* ... fall through ... */
6506 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6507 this is a SIGN_EXTRACT. */
6508 if (GET_CODE (rhs) == CONST_INT
6509 && GET_CODE (lhs) == ASHIFT
6510 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6511 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6513 new = make_compound_operation (XEXP (lhs, 0), next_code);
6514 new = make_extraction (mode, new,
6515 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6516 NULL_RTX, mode_width - INTVAL (rhs),
6517 code == LSHIFTRT, 0, in_code == COMPARE);
6521 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6522 If so, try to merge the shifts into a SIGN_EXTEND. We could
6523 also do this for some cases of SIGN_EXTRACT, but it doesn't
6524 seem worth the effort; the case checked for occurs on Alpha. */
6526 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6527 && ! (GET_CODE (lhs) == SUBREG
6528 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6529 && GET_CODE (rhs) == CONST_INT
6530 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6531 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6532 new = make_extraction (mode, make_compound_operation (new, next_code),
6533 0, NULL_RTX, mode_width - INTVAL (rhs),
6534 code == LSHIFTRT, 0, in_code == COMPARE);
6539 /* Call ourselves recursively on the inner expression. If we are
6540 narrowing the object and it has a different RTL code from
6541 what it originally did, do this SUBREG as a force_to_mode. */
6543 tem = make_compound_operation (SUBREG_REG (x), in_code);
6544 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6545 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6546 && subreg_lowpart_p (x))
6548 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6551 /* If we have something other than a SUBREG, we might have
6552 done an expansion, so rerun ourselves. */
6553 if (GET_CODE (newer) != SUBREG)
6554 newer = make_compound_operation (newer, in_code);
6559 /* If this is a paradoxical subreg, and the new code is a sign or
6560 zero extension, omit the subreg and widen the extension. If it
6561 is a regular subreg, we can still get rid of the subreg by not
6562 widening so much, or in fact removing the extension entirely. */
6563 if ((GET_CODE (tem) == SIGN_EXTEND
6564 || GET_CODE (tem) == ZERO_EXTEND)
6565 && subreg_lowpart_p (x))
6567 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6568 || (GET_MODE_SIZE (mode) >
6569 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6570 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6572 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6583 x = gen_lowpart_for_combine (mode, new);
6584 code = GET_CODE (x);
6587 /* Now recursively process each operand of this operation. */
6588 fmt = GET_RTX_FORMAT (code);
6589 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6592 new = make_compound_operation (XEXP (x, i), next_code);
6593 SUBST (XEXP (x, i), new);
6599 /* Given M see if it is a value that would select a field of bits
6600 within an item, but not the entire word. Return -1 if not.
6601 Otherwise, return the starting position of the field, where 0 is the
6604 *PLEN is set to the length of the field. */
6607 get_pos_from_mask (m, plen)
6608 unsigned HOST_WIDE_INT m;
6609 unsigned HOST_WIDE_INT *plen;
6611 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6612 int pos = exact_log2 (m & -m);
6618 /* Now shift off the low-order zero bits and see if we have a power of
6620 len = exact_log2 ((m >> pos) + 1);
6629 /* See if X can be simplified knowing that we will only refer to it in
6630 MODE and will only refer to those bits that are nonzero in MASK.
6631 If other bits are being computed or if masking operations are done
6632 that select a superset of the bits in MASK, they can sometimes be
6635 Return a possibly simplified expression, but always convert X to
6636 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6638 Also, if REG is non-zero and X is a register equal in value to REG,
6641 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6642 are all off in X. This is used when X will be complemented, by either
6643 NOT, NEG, or XOR. */
6646 force_to_mode (x, mode, mask, reg, just_select)
6648 enum machine_mode mode;
6649 unsigned HOST_WIDE_INT mask;
6653 enum rtx_code code = GET_CODE (x);
6654 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6655 enum machine_mode op_mode;
6656 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6659 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6660 code below will do the wrong thing since the mode of such an
6661 expression is VOIDmode.
6663 Also do nothing if X is a CLOBBER; this can happen if X was
6664 the return value from a call to gen_lowpart_for_combine. */
6665 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6668 /* We want to perform the operation is its present mode unless we know
6669 that the operation is valid in MODE, in which case we do the operation
6671 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6672 && have_insn_for (code, mode))
6673 ? mode : GET_MODE (x));
6675 /* It is not valid to do a right-shift in a narrower mode
6676 than the one it came in with. */
6677 if ((code == LSHIFTRT || code == ASHIFTRT)
6678 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6679 op_mode = GET_MODE (x);
6681 /* Truncate MASK to fit OP_MODE. */
6683 mask &= GET_MODE_MASK (op_mode);
6685 /* When we have an arithmetic operation, or a shift whose count we
6686 do not know, we need to assume that all bit the up to the highest-order
6687 bit in MASK will be needed. This is how we form such a mask. */
6689 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6690 ? GET_MODE_MASK (op_mode)
6691 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6694 fuller_mask = ~(HOST_WIDE_INT) 0;
6696 /* Determine what bits of X are guaranteed to be (non)zero. */
6697 nonzero = nonzero_bits (x, mode);
6699 /* If none of the bits in X are needed, return a zero. */
6700 if (! just_select && (nonzero & mask) == 0)
6703 /* If X is a CONST_INT, return a new one. Do this here since the
6704 test below will fail. */
6705 if (GET_CODE (x) == CONST_INT)
6707 HOST_WIDE_INT cval = INTVAL (x) & mask;
6708 int width = GET_MODE_BITSIZE (mode);
6710 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6711 number, sign extend it. */
6712 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6713 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6714 cval |= (HOST_WIDE_INT) -1 << width;
6716 return GEN_INT (cval);
6719 /* If X is narrower than MODE and we want all the bits in X's mode, just
6720 get X in the proper mode. */
6721 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6722 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6723 return gen_lowpart_for_combine (mode, x);
6725 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6726 MASK are already known to be zero in X, we need not do anything. */
6727 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6733 /* If X is a (clobber (const_int)), return it since we know we are
6734 generating something that won't match. */
6738 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6739 spanned the boundary of the MEM. If we are now masking so it is
6740 within that boundary, we don't need the USE any more. */
6741 if (! BITS_BIG_ENDIAN
6742 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6743 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6750 x = expand_compound_operation (x);
6751 if (GET_CODE (x) != code)
6752 return force_to_mode (x, mode, mask, reg, next_select);
6756 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6757 || rtx_equal_p (reg, get_last_value (x))))
6762 if (subreg_lowpart_p (x)
6763 /* We can ignore the effect of this SUBREG if it narrows the mode or
6764 if the constant masks to zero all the bits the mode doesn't
6766 && ((GET_MODE_SIZE (GET_MODE (x))
6767 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6769 & GET_MODE_MASK (GET_MODE (x))
6770 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6771 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6775 /* If this is an AND with a constant, convert it into an AND
6776 whose constant is the AND of that constant with MASK. If it
6777 remains an AND of MASK, delete it since it is redundant. */
6779 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6781 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6782 mask & INTVAL (XEXP (x, 1)));
6784 /* If X is still an AND, see if it is an AND with a mask that
6785 is just some low-order bits. If so, and it is MASK, we don't
6788 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6789 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6790 == (HOST_WIDE_INT) mask))
6793 /* If it remains an AND, try making another AND with the bits
6794 in the mode mask that aren't in MASK turned on. If the
6795 constant in the AND is wide enough, this might make a
6796 cheaper constant. */
6798 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6799 && GET_MODE_MASK (GET_MODE (x)) != mask
6800 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6802 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6803 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6804 int width = GET_MODE_BITSIZE (GET_MODE (x));
6807 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6808 number, sign extend it. */
6809 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6810 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6811 cval |= (HOST_WIDE_INT) -1 << width;
6813 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6814 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6824 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6825 low-order bits (as in an alignment operation) and FOO is already
6826 aligned to that boundary, mask C1 to that boundary as well.
6827 This may eliminate that PLUS and, later, the AND. */
6830 unsigned int width = GET_MODE_BITSIZE (mode);
6831 unsigned HOST_WIDE_INT smask = mask;
6833 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6834 number, sign extend it. */
6836 if (width < HOST_BITS_PER_WIDE_INT
6837 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6838 smask |= (HOST_WIDE_INT) -1 << width;
6840 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6841 && exact_log2 (- smask) >= 0
6842 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6843 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6844 return force_to_mode (plus_constant (XEXP (x, 0),
6845 (INTVAL (XEXP (x, 1)) & smask)),
6846 mode, smask, reg, next_select);
6849 /* ... fall through ... */
6852 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6853 most significant bit in MASK since carries from those bits will
6854 affect the bits we are interested in. */
6859 /* If X is (minus C Y) where C's least set bit is larger than any bit
6860 in the mask, then we may replace with (neg Y). */
6861 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6862 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6863 & -INTVAL (XEXP (x, 0))))
6866 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6868 return force_to_mode (x, mode, mask, reg, next_select);
6871 /* Similarly, if C contains every bit in the mask, then we may
6872 replace with (not Y). */
6873 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6874 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6875 == INTVAL (XEXP (x, 0))))
6877 x = simplify_gen_unary (NOT, GET_MODE (x),
6878 XEXP (x, 1), GET_MODE (x));
6879 return force_to_mode (x, mode, mask, reg, next_select);
6887 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6888 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6889 operation which may be a bitfield extraction. Ensure that the
6890 constant we form is not wider than the mode of X. */
6892 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6893 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6894 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6895 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6896 && GET_CODE (XEXP (x, 1)) == CONST_INT
6897 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6898 + floor_log2 (INTVAL (XEXP (x, 1))))
6899 < GET_MODE_BITSIZE (GET_MODE (x)))
6900 && (INTVAL (XEXP (x, 1))
6901 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6903 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6904 << INTVAL (XEXP (XEXP (x, 0), 1)));
6905 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6906 XEXP (XEXP (x, 0), 0), temp);
6907 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6908 XEXP (XEXP (x, 0), 1));
6909 return force_to_mode (x, mode, mask, reg, next_select);
6913 /* For most binary operations, just propagate into the operation and
6914 change the mode if we have an operation of that mode. */
6916 op0 = gen_lowpart_for_combine (op_mode,
6917 force_to_mode (XEXP (x, 0), mode, mask,
6919 op1 = gen_lowpart_for_combine (op_mode,
6920 force_to_mode (XEXP (x, 1), mode, mask,
6923 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6924 MASK since OP1 might have been sign-extended but we never want
6925 to turn on extra bits, since combine might have previously relied
6926 on them being off. */
6927 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6928 && (INTVAL (op1) & mask) != 0)
6929 op1 = GEN_INT (INTVAL (op1) & mask);
6931 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6932 x = gen_binary (code, op_mode, op0, op1);
6936 /* For left shifts, do the same, but just for the first operand.
6937 However, we cannot do anything with shifts where we cannot
6938 guarantee that the counts are smaller than the size of the mode
6939 because such a count will have a different meaning in a
6942 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6943 && INTVAL (XEXP (x, 1)) >= 0
6944 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6945 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6946 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6947 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6950 /* If the shift count is a constant and we can do arithmetic in
6951 the mode of the shift, refine which bits we need. Otherwise, use the
6952 conservative form of the mask. */
6953 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6954 && INTVAL (XEXP (x, 1)) >= 0
6955 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6956 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6957 mask >>= INTVAL (XEXP (x, 1));
6961 op0 = gen_lowpart_for_combine (op_mode,
6962 force_to_mode (XEXP (x, 0), op_mode,
6963 mask, reg, next_select));
6965 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6966 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6970 /* Here we can only do something if the shift count is a constant,
6971 this shift constant is valid for the host, and we can do arithmetic
6974 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6975 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6976 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6978 rtx inner = XEXP (x, 0);
6979 unsigned HOST_WIDE_INT inner_mask;
6981 /* Select the mask of the bits we need for the shift operand. */
6982 inner_mask = mask << INTVAL (XEXP (x, 1));
6984 /* We can only change the mode of the shift if we can do arithmetic
6985 in the mode of the shift and INNER_MASK is no wider than the
6986 width of OP_MODE. */
6987 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6988 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6989 op_mode = GET_MODE (x);
6991 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6993 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6994 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6997 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6998 shift and AND produces only copies of the sign bit (C2 is one less
6999 than a power of two), we can do this with just a shift. */
7001 if (GET_CODE (x) == LSHIFTRT
7002 && GET_CODE (XEXP (x, 1)) == CONST_INT
7003 /* The shift puts one of the sign bit copies in the least significant
7005 && ((INTVAL (XEXP (x, 1))
7006 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7007 >= GET_MODE_BITSIZE (GET_MODE (x)))
7008 && exact_log2 (mask + 1) >= 0
7009 /* Number of bits left after the shift must be more than the mask
7011 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7012 <= GET_MODE_BITSIZE (GET_MODE (x)))
7013 /* Must be more sign bit copies than the mask needs. */
7014 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7015 >= exact_log2 (mask + 1)))
7016 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7017 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7018 - exact_log2 (mask + 1)));
7023 /* If we are just looking for the sign bit, we don't need this shift at
7024 all, even if it has a variable count. */
7025 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7026 && (mask == ((unsigned HOST_WIDE_INT) 1
7027 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7028 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7030 /* If this is a shift by a constant, get a mask that contains those bits
7031 that are not copies of the sign bit. We then have two cases: If
7032 MASK only includes those bits, this can be a logical shift, which may
7033 allow simplifications. If MASK is a single-bit field not within
7034 those bits, we are requesting a copy of the sign bit and hence can
7035 shift the sign bit to the appropriate location. */
7037 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7038 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7042 /* If the considered data is wider than HOST_WIDE_INT, we can't
7043 represent a mask for all its bits in a single scalar.
7044 But we only care about the lower bits, so calculate these. */
7046 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7048 nonzero = ~(HOST_WIDE_INT) 0;
7050 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7051 is the number of bits a full-width mask would have set.
7052 We need only shift if these are fewer than nonzero can
7053 hold. If not, we must keep all bits set in nonzero. */
7055 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7056 < HOST_BITS_PER_WIDE_INT)
7057 nonzero >>= INTVAL (XEXP (x, 1))
7058 + HOST_BITS_PER_WIDE_INT
7059 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7063 nonzero = GET_MODE_MASK (GET_MODE (x));
7064 nonzero >>= INTVAL (XEXP (x, 1));
7067 if ((mask & ~nonzero) == 0
7068 || (i = exact_log2 (mask)) >= 0)
7070 x = simplify_shift_const
7071 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7072 i < 0 ? INTVAL (XEXP (x, 1))
7073 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7075 if (GET_CODE (x) != ASHIFTRT)
7076 return force_to_mode (x, mode, mask, reg, next_select);
7080 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7081 even if the shift count isn't a constant. */
7083 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7087 /* If this is a zero- or sign-extension operation that just affects bits
7088 we don't care about, remove it. Be sure the call above returned
7089 something that is still a shift. */
7091 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7092 && GET_CODE (XEXP (x, 1)) == CONST_INT
7093 && INTVAL (XEXP (x, 1)) >= 0
7094 && (INTVAL (XEXP (x, 1))
7095 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7096 && GET_CODE (XEXP (x, 0)) == ASHIFT
7097 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7098 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7099 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7106 /* If the shift count is constant and we can do computations
7107 in the mode of X, compute where the bits we care about are.
7108 Otherwise, we can't do anything. Don't change the mode of
7109 the shift or propagate MODE into the shift, though. */
7110 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7111 && INTVAL (XEXP (x, 1)) >= 0)
7113 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7114 GET_MODE (x), GEN_INT (mask),
7116 if (temp && GET_CODE(temp) == CONST_INT)
7118 force_to_mode (XEXP (x, 0), GET_MODE (x),
7119 INTVAL (temp), reg, next_select));
7124 /* If we just want the low-order bit, the NEG isn't needed since it
7125 won't change the low-order bit. */
7127 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7129 /* We need any bits less significant than the most significant bit in
7130 MASK since carries from those bits will affect the bits we are
7136 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7137 same as the XOR case above. Ensure that the constant we form is not
7138 wider than the mode of X. */
7140 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7141 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7142 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7143 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7144 < GET_MODE_BITSIZE (GET_MODE (x)))
7145 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7147 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7148 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7149 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7151 return force_to_mode (x, mode, mask, reg, next_select);
7154 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7155 use the full mask inside the NOT. */
7159 op0 = gen_lowpart_for_combine (op_mode,
7160 force_to_mode (XEXP (x, 0), mode, mask,
7162 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7163 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7167 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7168 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7169 which is equal to STORE_FLAG_VALUE. */
7170 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7171 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7172 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7173 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7178 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7179 written in a narrower mode. We play it safe and do not do so. */
7182 gen_lowpart_for_combine (GET_MODE (x),
7183 force_to_mode (XEXP (x, 1), mode,
7184 mask, reg, next_select)));
7186 gen_lowpart_for_combine (GET_MODE (x),
7187 force_to_mode (XEXP (x, 2), mode,
7188 mask, reg,next_select)));
7195 /* Ensure we return a value of the proper mode. */
7196 return gen_lowpart_for_combine (mode, x);
7199 /* Return nonzero if X is an expression that has one of two values depending on
7200 whether some other value is zero or nonzero. In that case, we return the
7201 value that is being tested, *PTRUE is set to the value if the rtx being
7202 returned has a nonzero value, and *PFALSE is set to the other alternative.
7204 If we return zero, we set *PTRUE and *PFALSE to X. */
7207 if_then_else_cond (x, ptrue, pfalse)
7209 rtx *ptrue, *pfalse;
7211 enum machine_mode mode = GET_MODE (x);
7212 enum rtx_code code = GET_CODE (x);
7213 rtx cond0, cond1, true0, true1, false0, false1;
7214 unsigned HOST_WIDE_INT nz;
7216 /* If we are comparing a value against zero, we are done. */
7217 if ((code == NE || code == EQ)
7218 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7220 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7221 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7225 /* If this is a unary operation whose operand has one of two values, apply
7226 our opcode to compute those values. */
7227 else if (GET_RTX_CLASS (code) == '1'
7228 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7230 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7231 *pfalse = simplify_gen_unary (code, mode, false0,
7232 GET_MODE (XEXP (x, 0)));
7236 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7237 make can't possibly match and would suppress other optimizations. */
7238 else if (code == COMPARE)
7241 /* If this is a binary operation, see if either side has only one of two
7242 values. If either one does or if both do and they are conditional on
7243 the same value, compute the new true and false values. */
7244 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7245 || GET_RTX_CLASS (code) == '<')
7247 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7248 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7250 if ((cond0 != 0 || cond1 != 0)
7251 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7253 /* If if_then_else_cond returned zero, then true/false are the
7254 same rtl. We must copy one of them to prevent invalid rtl
7257 true0 = copy_rtx (true0);
7258 else if (cond1 == 0)
7259 true1 = copy_rtx (true1);
7261 *ptrue = gen_binary (code, mode, true0, true1);
7262 *pfalse = gen_binary (code, mode, false0, false1);
7263 return cond0 ? cond0 : cond1;
7266 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7267 operands is zero when the other is non-zero, and vice-versa,
7268 and STORE_FLAG_VALUE is 1 or -1. */
7270 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7271 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7273 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7275 rtx op0 = XEXP (XEXP (x, 0), 1);
7276 rtx op1 = XEXP (XEXP (x, 1), 1);
7278 cond0 = XEXP (XEXP (x, 0), 0);
7279 cond1 = XEXP (XEXP (x, 1), 0);
7281 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7282 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7283 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7284 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7285 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7286 || ((swap_condition (GET_CODE (cond0))
7287 == combine_reversed_comparison_code (cond1))
7288 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7289 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7290 && ! side_effects_p (x))
7292 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7293 *pfalse = gen_binary (MULT, mode,
7295 ? simplify_gen_unary (NEG, mode, op1,
7303 /* Similarly for MULT, AND and UMIN, except that for these the result
7305 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7306 && (code == MULT || code == AND || code == UMIN)
7307 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7309 cond0 = XEXP (XEXP (x, 0), 0);
7310 cond1 = XEXP (XEXP (x, 1), 0);
7312 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7313 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7314 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7315 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7316 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7317 || ((swap_condition (GET_CODE (cond0))
7318 == combine_reversed_comparison_code (cond1))
7319 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7320 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7321 && ! side_effects_p (x))
7323 *ptrue = *pfalse = const0_rtx;
7329 else if (code == IF_THEN_ELSE)
7331 /* If we have IF_THEN_ELSE already, extract the condition and
7332 canonicalize it if it is NE or EQ. */
7333 cond0 = XEXP (x, 0);
7334 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7335 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7336 return XEXP (cond0, 0);
7337 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7339 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7340 return XEXP (cond0, 0);
7346 /* If X is a SUBREG, we can narrow both the true and false values
7347 if the inner expression, if there is a condition. */
7348 else if (code == SUBREG
7349 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7352 *ptrue = simplify_gen_subreg (mode, true0,
7353 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7354 *pfalse = simplify_gen_subreg (mode, false0,
7355 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7360 /* If X is a constant, this isn't special and will cause confusions
7361 if we treat it as such. Likewise if it is equivalent to a constant. */
7362 else if (CONSTANT_P (x)
7363 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7366 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7367 will be least confusing to the rest of the compiler. */
7368 else if (mode == BImode)
7370 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7374 /* If X is known to be either 0 or -1, those are the true and
7375 false values when testing X. */
7376 else if (x == constm1_rtx || x == const0_rtx
7377 || (mode != VOIDmode
7378 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7380 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7384 /* Likewise for 0 or a single bit. */
7385 else if (mode != VOIDmode
7386 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7387 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7389 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7393 /* Otherwise fail; show no condition with true and false values the same. */
7394 *ptrue = *pfalse = x;
7398 /* Return the value of expression X given the fact that condition COND
7399 is known to be true when applied to REG as its first operand and VAL
7400 as its second. X is known to not be shared and so can be modified in
7403 We only handle the simplest cases, and specifically those cases that
7404 arise with IF_THEN_ELSE expressions. */
7407 known_cond (x, cond, reg, val)
7412 enum rtx_code code = GET_CODE (x);
7417 if (side_effects_p (x))
7420 /* If either operand of the condition is a floating point value,
7421 then we have to avoid collapsing an EQ comparison. */
7423 && rtx_equal_p (x, reg)
7424 && ! FLOAT_MODE_P (GET_MODE (x))
7425 && ! FLOAT_MODE_P (GET_MODE (val)))
7428 if (cond == UNEQ && rtx_equal_p (x, reg))
7431 /* If X is (abs REG) and we know something about REG's relationship
7432 with zero, we may be able to simplify this. */
7434 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7437 case GE: case GT: case EQ:
7440 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7442 GET_MODE (XEXP (x, 0)));
7447 /* The only other cases we handle are MIN, MAX, and comparisons if the
7448 operands are the same as REG and VAL. */
7450 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7452 if (rtx_equal_p (XEXP (x, 0), val))
7453 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7455 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7457 if (GET_RTX_CLASS (code) == '<')
7459 if (comparison_dominates_p (cond, code))
7460 return const_true_rtx;
7462 code = combine_reversed_comparison_code (x);
7464 && comparison_dominates_p (cond, code))
7469 else if (code == SMAX || code == SMIN
7470 || code == UMIN || code == UMAX)
7472 int unsignedp = (code == UMIN || code == UMAX);
7474 /* Do not reverse the condition when it is NE or EQ.
7475 This is because we cannot conclude anything about
7476 the value of 'SMAX (x, y)' when x is not equal to y,
7477 but we can when x equals y. */
7478 if ((code == SMAX || code == UMAX)
7479 && ! (cond == EQ || cond == NE))
7480 cond = reverse_condition (cond);
7485 return unsignedp ? x : XEXP (x, 1);
7487 return unsignedp ? x : XEXP (x, 0);
7489 return unsignedp ? XEXP (x, 1) : x;
7491 return unsignedp ? XEXP (x, 0) : x;
7498 else if (code == SUBREG)
7500 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7501 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7503 if (SUBREG_REG (x) != r)
7505 /* We must simplify subreg here, before we lose track of the
7506 original inner_mode. */
7507 new = simplify_subreg (GET_MODE (x), r,
7508 inner_mode, SUBREG_BYTE (x));
7512 SUBST (SUBREG_REG (x), r);
7517 /* We don't have to handle SIGN_EXTEND here, because even in the
7518 case of replacing something with a modeless CONST_INT, a
7519 CONST_INT is already (supposed to be) a valid sign extension for
7520 its narrower mode, which implies it's already properly
7521 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7522 story is different. */
7523 else if (code == ZERO_EXTEND)
7525 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7526 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7528 if (XEXP (x, 0) != r)
7530 /* We must simplify the zero_extend here, before we lose
7531 track of the original inner_mode. */
7532 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7537 SUBST (XEXP (x, 0), r);
7543 fmt = GET_RTX_FORMAT (code);
7544 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7547 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7548 else if (fmt[i] == 'E')
7549 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7550 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7557 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7558 assignment as a field assignment. */
7561 rtx_equal_for_field_assignment_p (x, y)
7565 if (x == y || rtx_equal_p (x, y))
7568 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7571 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7572 Note that all SUBREGs of MEM are paradoxical; otherwise they
7573 would have been rewritten. */
7574 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7575 && GET_CODE (SUBREG_REG (y)) == MEM
7576 && rtx_equal_p (SUBREG_REG (y),
7577 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7580 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7581 && GET_CODE (SUBREG_REG (x)) == MEM
7582 && rtx_equal_p (SUBREG_REG (x),
7583 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7586 /* We used to see if get_last_value of X and Y were the same but that's
7587 not correct. In one direction, we'll cause the assignment to have
7588 the wrong destination and in the case, we'll import a register into this
7589 insn that might have already have been dead. So fail if none of the
7590 above cases are true. */
7594 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7595 Return that assignment if so.
7597 We only handle the most common cases. */
7600 make_field_assignment (x)
7603 rtx dest = SET_DEST (x);
7604 rtx src = SET_SRC (x);
7609 unsigned HOST_WIDE_INT len;
7611 enum machine_mode mode;
7613 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7614 a clear of a one-bit field. We will have changed it to
7615 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7618 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7619 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7620 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7621 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7623 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7626 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7630 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7631 && subreg_lowpart_p (XEXP (src, 0))
7632 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7633 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7634 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7635 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7636 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7638 assign = make_extraction (VOIDmode, dest, 0,
7639 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7642 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7646 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7648 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7649 && XEXP (XEXP (src, 0), 0) == const1_rtx
7650 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7652 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7655 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7659 /* The other case we handle is assignments into a constant-position
7660 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7661 a mask that has all one bits except for a group of zero bits and
7662 OTHER is known to have zeros where C1 has ones, this is such an
7663 assignment. Compute the position and length from C1. Shift OTHER
7664 to the appropriate position, force it to the required mode, and
7665 make the extraction. Check for the AND in both operands. */
7667 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7670 rhs = expand_compound_operation (XEXP (src, 0));
7671 lhs = expand_compound_operation (XEXP (src, 1));
7673 if (GET_CODE (rhs) == AND
7674 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7675 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7676 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7677 else if (GET_CODE (lhs) == AND
7678 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7679 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7680 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7684 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7685 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7686 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7687 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7690 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7694 /* The mode to use for the source is the mode of the assignment, or of
7695 what is inside a possible STRICT_LOW_PART. */
7696 mode = (GET_CODE (assign) == STRICT_LOW_PART
7697 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7699 /* Shift OTHER right POS places and make it the source, restricting it
7700 to the proper length and mode. */
7702 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7703 GET_MODE (src), other, pos),
7705 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7706 ? ~(unsigned HOST_WIDE_INT) 0
7707 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7710 return gen_rtx_SET (VOIDmode, assign, src);
7713 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7717 apply_distributive_law (x)
7720 enum rtx_code code = GET_CODE (x);
7721 rtx lhs, rhs, other;
7723 enum rtx_code inner_code;
7725 /* Distributivity is not true for floating point.
7726 It can change the value. So don't do it.
7727 -- rms and moshier@world.std.com. */
7728 if (FLOAT_MODE_P (GET_MODE (x)))
7731 /* The outer operation can only be one of the following: */
7732 if (code != IOR && code != AND && code != XOR
7733 && code != PLUS && code != MINUS)
7736 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7738 /* If either operand is a primitive we can't do anything, so get out
7740 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7741 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7744 lhs = expand_compound_operation (lhs);
7745 rhs = expand_compound_operation (rhs);
7746 inner_code = GET_CODE (lhs);
7747 if (inner_code != GET_CODE (rhs))
7750 /* See if the inner and outer operations distribute. */
7757 /* These all distribute except over PLUS. */
7758 if (code == PLUS || code == MINUS)
7763 if (code != PLUS && code != MINUS)
7768 /* This is also a multiply, so it distributes over everything. */
7772 /* Non-paradoxical SUBREGs distributes over all operations, provided
7773 the inner modes and byte offsets are the same, this is an extraction
7774 of a low-order part, we don't convert an fp operation to int or
7775 vice versa, and we would not be converting a single-word
7776 operation into a multi-word operation. The latter test is not
7777 required, but it prevents generating unneeded multi-word operations.
7778 Some of the previous tests are redundant given the latter test, but
7779 are retained because they are required for correctness.
7781 We produce the result slightly differently in this case. */
7783 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7784 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7785 || ! subreg_lowpart_p (lhs)
7786 || (GET_MODE_CLASS (GET_MODE (lhs))
7787 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7788 || (GET_MODE_SIZE (GET_MODE (lhs))
7789 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7790 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7793 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7794 SUBREG_REG (lhs), SUBREG_REG (rhs));
7795 return gen_lowpart_for_combine (GET_MODE (x), tem);
7801 /* Set LHS and RHS to the inner operands (A and B in the example
7802 above) and set OTHER to the common operand (C in the example).
7803 These is only one way to do this unless the inner operation is
7805 if (GET_RTX_CLASS (inner_code) == 'c'
7806 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7807 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7808 else if (GET_RTX_CLASS (inner_code) == 'c'
7809 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7810 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7811 else if (GET_RTX_CLASS (inner_code) == 'c'
7812 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7813 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7814 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7815 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7819 /* Form the new inner operation, seeing if it simplifies first. */
7820 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7822 /* There is one exception to the general way of distributing:
7823 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7824 if (code == XOR && inner_code == IOR)
7827 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7830 /* We may be able to continuing distributing the result, so call
7831 ourselves recursively on the inner operation before forming the
7832 outer operation, which we return. */
7833 return gen_binary (inner_code, GET_MODE (x),
7834 apply_distributive_law (tem), other);
7837 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7840 Return an equivalent form, if different from X. Otherwise, return X. If
7841 X is zero, we are to always construct the equivalent form. */
7844 simplify_and_const_int (x, mode, varop, constop)
7846 enum machine_mode mode;
7848 unsigned HOST_WIDE_INT constop;
7850 unsigned HOST_WIDE_INT nonzero;
7853 /* Simplify VAROP knowing that we will be only looking at some of the
7856 Note by passing in CONSTOP, we guarantee that the bits not set in
7857 CONSTOP are not significant and will never be examined. We must
7858 ensure that is the case by explicitly masking out those bits
7859 before returning. */
7860 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7862 /* If VAROP is a CLOBBER, we will fail so return it. */
7863 if (GET_CODE (varop) == CLOBBER)
7866 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7867 to VAROP and return the new constant. */
7868 if (GET_CODE (varop) == CONST_INT)
7869 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7871 /* See what bits may be nonzero in VAROP. Unlike the general case of
7872 a call to nonzero_bits, here we don't care about bits outside
7875 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7877 /* Turn off all bits in the constant that are known to already be zero.
7878 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7879 which is tested below. */
7883 /* If we don't have any bits left, return zero. */
7887 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7888 a power of two, we can replace this with an ASHIFT. */
7889 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7890 && (i = exact_log2 (constop)) >= 0)
7891 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7893 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7894 or XOR, then try to apply the distributive law. This may eliminate
7895 operations if either branch can be simplified because of the AND.
7896 It may also make some cases more complex, but those cases probably
7897 won't match a pattern either with or without this. */
7899 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7901 gen_lowpart_for_combine
7903 apply_distributive_law
7904 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7905 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7906 XEXP (varop, 0), constop),
7907 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7908 XEXP (varop, 1), constop))));
7910 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7911 the AND and see if one of the operands simplifies to zero. If so, we
7912 may eliminate it. */
7914 if (GET_CODE (varop) == PLUS
7915 && exact_log2 (constop + 1) >= 0)
7919 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7920 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7921 if (o0 == const0_rtx)
7923 if (o1 == const0_rtx)
7927 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7928 if we already had one (just check for the simplest cases). */
7929 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7930 && GET_MODE (XEXP (x, 0)) == mode
7931 && SUBREG_REG (XEXP (x, 0)) == varop)
7932 varop = XEXP (x, 0);
7934 varop = gen_lowpart_for_combine (mode, varop);
7936 /* If we can't make the SUBREG, try to return what we were given. */
7937 if (GET_CODE (varop) == CLOBBER)
7938 return x ? x : varop;
7940 /* If we are only masking insignificant bits, return VAROP. */
7941 if (constop == nonzero)
7945 /* Otherwise, return an AND. */
7946 constop = trunc_int_for_mode (constop, mode);
7947 /* See how much, if any, of X we can use. */
7948 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7949 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7953 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7954 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7955 SUBST (XEXP (x, 1), GEN_INT (constop));
7957 SUBST (XEXP (x, 0), varop);
7964 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7965 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7966 is less useful. We can't allow both, because that results in exponential
7967 run time recursion. There is a nullstone testcase that triggered
7968 this. This macro avoids accidental uses of num_sign_bit_copies. */
7969 #define num_sign_bit_copies()
7971 /* Given an expression, X, compute which bits in X can be non-zero.
7972 We don't care about bits outside of those defined in MODE.
7974 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7975 a shift, AND, or zero_extract, we can do better. */
7977 static unsigned HOST_WIDE_INT
7978 nonzero_bits (x, mode)
7980 enum machine_mode mode;
7982 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7983 unsigned HOST_WIDE_INT inner_nz;
7985 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7988 /* For floating-point values, assume all bits are needed. */
7989 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7992 /* If X is wider than MODE, use its mode instead. */
7993 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7995 mode = GET_MODE (x);
7996 nonzero = GET_MODE_MASK (mode);
7997 mode_width = GET_MODE_BITSIZE (mode);
8000 if (mode_width > HOST_BITS_PER_WIDE_INT)
8001 /* Our only callers in this case look for single bit values. So
8002 just return the mode mask. Those tests will then be false. */
8005 #ifndef WORD_REGISTER_OPERATIONS
8006 /* If MODE is wider than X, but both are a single word for both the host
8007 and target machines, we can compute this from which bits of the
8008 object might be nonzero in its own mode, taking into account the fact
8009 that on many CISC machines, accessing an object in a wider mode
8010 causes the high-order bits to become undefined. So they are
8011 not known to be zero. */
8013 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8014 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8015 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8016 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8018 nonzero &= nonzero_bits (x, GET_MODE (x));
8019 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8024 code = GET_CODE (x);
8028 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8029 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8030 all the bits above ptr_mode are known to be zero. */
8031 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8033 nonzero &= GET_MODE_MASK (ptr_mode);
8036 /* Include declared information about alignment of pointers. */
8037 /* ??? We don't properly preserve REG_POINTER changes across
8038 pointer-to-integer casts, so we can't trust it except for
8039 things that we know must be pointers. See execute/960116-1.c. */
8040 if ((x == stack_pointer_rtx
8041 || x == frame_pointer_rtx
8042 || x == arg_pointer_rtx)
8043 && REGNO_POINTER_ALIGN (REGNO (x)))
8045 unsigned HOST_WIDE_INT alignment
8046 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8048 #ifdef PUSH_ROUNDING
8049 /* If PUSH_ROUNDING is defined, it is possible for the
8050 stack to be momentarily aligned only to that amount,
8051 so we pick the least alignment. */
8052 if (x == stack_pointer_rtx && PUSH_ARGS)
8053 alignment = MIN (PUSH_ROUNDING (1), alignment);
8056 nonzero &= ~(alignment - 1);
8059 /* If X is a register whose nonzero bits value is current, use it.
8060 Otherwise, if X is a register whose value we can find, use that
8061 value. Otherwise, use the previously-computed global nonzero bits
8062 for this register. */
8064 if (reg_last_set_value[REGNO (x)] != 0
8065 && (reg_last_set_mode[REGNO (x)] == mode
8066 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8067 && GET_MODE_CLASS (mode) == MODE_INT))
8068 && (reg_last_set_label[REGNO (x)] == label_tick
8069 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8070 && REG_N_SETS (REGNO (x)) == 1
8071 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8073 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8074 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8076 tem = get_last_value (x);
8080 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8081 /* If X is narrower than MODE and TEM is a non-negative
8082 constant that would appear negative in the mode of X,
8083 sign-extend it for use in reg_nonzero_bits because some
8084 machines (maybe most) will actually do the sign-extension
8085 and this is the conservative approach.
8087 ??? For 2.5, try to tighten up the MD files in this regard
8088 instead of this kludge. */
8090 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8091 && GET_CODE (tem) == CONST_INT
8093 && 0 != (INTVAL (tem)
8094 & ((HOST_WIDE_INT) 1
8095 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8096 tem = GEN_INT (INTVAL (tem)
8097 | ((HOST_WIDE_INT) (-1)
8098 << GET_MODE_BITSIZE (GET_MODE (x))));
8100 return nonzero_bits (tem, mode) & nonzero;
8102 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8104 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8106 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8107 /* We don't know anything about the upper bits. */
8108 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8109 return nonzero & mask;
8115 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8116 /* If X is negative in MODE, sign-extend the value. */
8117 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8118 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8119 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8125 #ifdef LOAD_EXTEND_OP
8126 /* In many, if not most, RISC machines, reading a byte from memory
8127 zeros the rest of the register. Noticing that fact saves a lot
8128 of extra zero-extends. */
8129 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8130 nonzero &= GET_MODE_MASK (GET_MODE (x));
8135 case UNEQ: case LTGT:
8136 case GT: case GTU: case UNGT:
8137 case LT: case LTU: case UNLT:
8138 case GE: case GEU: case UNGE:
8139 case LE: case LEU: case UNLE:
8140 case UNORDERED: case ORDERED:
8142 /* If this produces an integer result, we know which bits are set.
8143 Code here used to clear bits outside the mode of X, but that is
8146 if (GET_MODE_CLASS (mode) == MODE_INT
8147 && mode_width <= HOST_BITS_PER_WIDE_INT)
8148 nonzero = STORE_FLAG_VALUE;
8153 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8154 and num_sign_bit_copies. */
8155 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8156 == GET_MODE_BITSIZE (GET_MODE (x)))
8160 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8161 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8166 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8167 and num_sign_bit_copies. */
8168 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8169 == GET_MODE_BITSIZE (GET_MODE (x)))
8175 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8179 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8180 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8181 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8185 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8186 Otherwise, show all the bits in the outer mode but not the inner
8188 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8189 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8191 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8193 & (((HOST_WIDE_INT) 1
8194 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8195 inner_nz |= (GET_MODE_MASK (mode)
8196 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8199 nonzero &= inner_nz;
8203 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8204 & nonzero_bits (XEXP (x, 1), mode));
8208 case UMIN: case UMAX: case SMIN: case SMAX:
8210 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8212 /* Don't call nonzero_bits for the second time if it cannot change
8214 if ((nonzero & nonzero0) != nonzero)
8215 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8219 case PLUS: case MINUS:
8221 case DIV: case UDIV:
8222 case MOD: case UMOD:
8223 /* We can apply the rules of arithmetic to compute the number of
8224 high- and low-order zero bits of these operations. We start by
8225 computing the width (position of the highest-order non-zero bit)
8226 and the number of low-order zero bits for each value. */
8228 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8229 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8230 int width0 = floor_log2 (nz0) + 1;
8231 int width1 = floor_log2 (nz1) + 1;
8232 int low0 = floor_log2 (nz0 & -nz0);
8233 int low1 = floor_log2 (nz1 & -nz1);
8234 HOST_WIDE_INT op0_maybe_minusp
8235 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8236 HOST_WIDE_INT op1_maybe_minusp
8237 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8238 unsigned int result_width = mode_width;
8244 result_width = MAX (width0, width1) + 1;
8245 result_low = MIN (low0, low1);
8248 result_low = MIN (low0, low1);
8251 result_width = width0 + width1;
8252 result_low = low0 + low1;
8257 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8258 result_width = width0;
8263 result_width = width0;
8268 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8269 result_width = MIN (width0, width1);
8270 result_low = MIN (low0, low1);
8275 result_width = MIN (width0, width1);
8276 result_low = MIN (low0, low1);
8282 if (result_width < mode_width)
8283 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8286 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8288 #ifdef POINTERS_EXTEND_UNSIGNED
8289 /* If pointers extend unsigned and this is an addition or subtraction
8290 to a pointer in Pmode, all the bits above ptr_mode are known to be
8292 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8293 && (code == PLUS || code == MINUS)
8294 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8295 nonzero &= GET_MODE_MASK (ptr_mode);
8301 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8302 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8303 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8307 /* If this is a SUBREG formed for a promoted variable that has
8308 been zero-extended, we know that at least the high-order bits
8309 are zero, though others might be too. */
8311 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8312 nonzero = (GET_MODE_MASK (GET_MODE (x))
8313 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8315 /* If the inner mode is a single word for both the host and target
8316 machines, we can compute this from which bits of the inner
8317 object might be nonzero. */
8318 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8319 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8320 <= HOST_BITS_PER_WIDE_INT))
8322 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8324 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8325 /* If this is a typical RISC machine, we only have to worry
8326 about the way loads are extended. */
8327 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8329 & (((unsigned HOST_WIDE_INT) 1
8330 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8332 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8335 /* On many CISC machines, accessing an object in a wider mode
8336 causes the high-order bits to become undefined. So they are
8337 not known to be zero. */
8338 if (GET_MODE_SIZE (GET_MODE (x))
8339 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8340 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8341 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8350 /* The nonzero bits are in two classes: any bits within MODE
8351 that aren't in GET_MODE (x) are always significant. The rest of the
8352 nonzero bits are those that are significant in the operand of
8353 the shift when shifted the appropriate number of bits. This
8354 shows that high-order bits are cleared by the right shift and
8355 low-order bits by left shifts. */
8356 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8357 && INTVAL (XEXP (x, 1)) >= 0
8358 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8360 enum machine_mode inner_mode = GET_MODE (x);
8361 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8362 int count = INTVAL (XEXP (x, 1));
8363 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8364 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8365 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8366 unsigned HOST_WIDE_INT outer = 0;
8368 if (mode_width > width)
8369 outer = (op_nonzero & nonzero & ~mode_mask);
8371 if (code == LSHIFTRT)
8373 else if (code == ASHIFTRT)
8377 /* If the sign bit may have been nonzero before the shift, we
8378 need to mark all the places it could have been copied to
8379 by the shift as possibly nonzero. */
8380 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8381 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8383 else if (code == ASHIFT)
8386 inner = ((inner << (count % width)
8387 | (inner >> (width - (count % width)))) & mode_mask);
8389 nonzero &= (outer | inner);
8394 /* This is at most the number of bits in the mode. */
8395 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8399 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8400 | nonzero_bits (XEXP (x, 2), mode));
8410 /* See the macro definition above. */
8411 #undef num_sign_bit_copies
8413 /* Return the number of bits at the high-order end of X that are known to
8414 be equal to the sign bit. X will be used in mode MODE; if MODE is
8415 VOIDmode, X will be used in its own mode. The returned value will always
8416 be between 1 and the number of bits in MODE. */
8419 num_sign_bit_copies (x, mode)
8421 enum machine_mode mode;
8423 enum rtx_code code = GET_CODE (x);
8424 unsigned int bitwidth;
8425 int num0, num1, result;
8426 unsigned HOST_WIDE_INT nonzero;
8429 /* If we weren't given a mode, use the mode of X. If the mode is still
8430 VOIDmode, we don't know anything. Likewise if one of the modes is
8433 if (mode == VOIDmode)
8434 mode = GET_MODE (x);
8436 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8439 bitwidth = GET_MODE_BITSIZE (mode);
8441 /* For a smaller object, just ignore the high bits. */
8442 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8444 num0 = num_sign_bit_copies (x, GET_MODE (x));
8446 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8449 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8451 #ifndef WORD_REGISTER_OPERATIONS
8452 /* If this machine does not do all register operations on the entire
8453 register and MODE is wider than the mode of X, we can say nothing
8454 at all about the high-order bits. */
8457 /* Likewise on machines that do, if the mode of the object is smaller
8458 than a word and loads of that size don't sign extend, we can say
8459 nothing about the high order bits. */
8460 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8461 #ifdef LOAD_EXTEND_OP
8462 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8473 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8474 /* If pointers extend signed and this is a pointer in Pmode, say that
8475 all the bits above ptr_mode are known to be sign bit copies. */
8476 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8478 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8481 if (reg_last_set_value[REGNO (x)] != 0
8482 && reg_last_set_mode[REGNO (x)] == mode
8483 && (reg_last_set_label[REGNO (x)] == label_tick
8484 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8485 && REG_N_SETS (REGNO (x)) == 1
8486 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8488 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8489 return reg_last_set_sign_bit_copies[REGNO (x)];
8491 tem = get_last_value (x);
8493 return num_sign_bit_copies (tem, mode);
8495 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8496 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8497 return reg_sign_bit_copies[REGNO (x)];
8501 #ifdef LOAD_EXTEND_OP
8502 /* Some RISC machines sign-extend all loads of smaller than a word. */
8503 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8504 return MAX (1, ((int) bitwidth
8505 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8510 /* If the constant is negative, take its 1's complement and remask.
8511 Then see how many zero bits we have. */
8512 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8513 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8514 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8515 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8517 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8520 /* If this is a SUBREG for a promoted object that is sign-extended
8521 and we are looking at it in a wider mode, we know that at least the
8522 high-order bits are known to be sign bit copies. */
8524 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8526 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8527 return MAX ((int) bitwidth
8528 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8532 /* For a smaller object, just ignore the high bits. */
8533 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8535 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8536 return MAX (1, (num0
8537 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8541 #ifdef WORD_REGISTER_OPERATIONS
8542 #ifdef LOAD_EXTEND_OP
8543 /* For paradoxical SUBREGs on machines where all register operations
8544 affect the entire register, just look inside. Note that we are
8545 passing MODE to the recursive call, so the number of sign bit copies
8546 will remain relative to that mode, not the inner mode. */
8548 /* This works only if loads sign extend. Otherwise, if we get a
8549 reload for the inner part, it may be loaded from the stack, and
8550 then we lose all sign bit copies that existed before the store
8553 if ((GET_MODE_SIZE (GET_MODE (x))
8554 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8555 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8556 return num_sign_bit_copies (SUBREG_REG (x), mode);
8562 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8563 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8567 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8568 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8571 /* For a smaller object, just ignore the high bits. */
8572 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8573 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8577 return num_sign_bit_copies (XEXP (x, 0), mode);
8579 case ROTATE: case ROTATERT:
8580 /* If we are rotating left by a number of bits less than the number
8581 of sign bit copies, we can just subtract that amount from the
8583 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8584 && INTVAL (XEXP (x, 1)) >= 0
8585 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8587 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8588 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8589 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8594 /* In general, this subtracts one sign bit copy. But if the value
8595 is known to be positive, the number of sign bit copies is the
8596 same as that of the input. Finally, if the input has just one bit
8597 that might be nonzero, all the bits are copies of the sign bit. */
8598 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8599 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8600 return num0 > 1 ? num0 - 1 : 1;
8602 nonzero = nonzero_bits (XEXP (x, 0), mode);
8607 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8612 case IOR: case AND: case XOR:
8613 case SMIN: case SMAX: case UMIN: case UMAX:
8614 /* Logical operations will preserve the number of sign-bit copies.
8615 MIN and MAX operations always return one of the operands. */
8616 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8617 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8618 return MIN (num0, num1);
8620 case PLUS: case MINUS:
8621 /* For addition and subtraction, we can have a 1-bit carry. However,
8622 if we are subtracting 1 from a positive number, there will not
8623 be such a carry. Furthermore, if the positive number is known to
8624 be 0 or 1, we know the result is either -1 or 0. */
8626 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8627 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8629 nonzero = nonzero_bits (XEXP (x, 0), mode);
8630 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8631 return (nonzero == 1 || nonzero == 0 ? bitwidth
8632 : bitwidth - floor_log2 (nonzero) - 1);
8635 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8636 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8637 result = MAX (1, MIN (num0, num1) - 1);
8639 #ifdef POINTERS_EXTEND_UNSIGNED
8640 /* If pointers extend signed and this is an addition or subtraction
8641 to a pointer in Pmode, all the bits above ptr_mode are known to be
8643 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8644 && (code == PLUS || code == MINUS)
8645 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8646 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8647 - GET_MODE_BITSIZE (ptr_mode) + 1),
8653 /* The number of bits of the product is the sum of the number of
8654 bits of both terms. However, unless one of the terms if known
8655 to be positive, we must allow for an additional bit since negating
8656 a negative number can remove one sign bit copy. */
8658 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8659 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8661 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8663 && (bitwidth > HOST_BITS_PER_WIDE_INT
8664 || (((nonzero_bits (XEXP (x, 0), mode)
8665 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8666 && ((nonzero_bits (XEXP (x, 1), mode)
8667 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8670 return MAX (1, result);
8673 /* The result must be <= the first operand. If the first operand
8674 has the high bit set, we know nothing about the number of sign
8676 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8678 else if ((nonzero_bits (XEXP (x, 0), mode)
8679 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8682 return num_sign_bit_copies (XEXP (x, 0), mode);
8685 /* The result must be <= the second operand. */
8686 return num_sign_bit_copies (XEXP (x, 1), mode);
8689 /* Similar to unsigned division, except that we have to worry about
8690 the case where the divisor is negative, in which case we have
8692 result = num_sign_bit_copies (XEXP (x, 0), mode);
8694 && (bitwidth > HOST_BITS_PER_WIDE_INT
8695 || (nonzero_bits (XEXP (x, 1), mode)
8696 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8702 result = num_sign_bit_copies (XEXP (x, 1), mode);
8704 && (bitwidth > HOST_BITS_PER_WIDE_INT
8705 || (nonzero_bits (XEXP (x, 1), mode)
8706 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8712 /* Shifts by a constant add to the number of bits equal to the
8714 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8715 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8716 && INTVAL (XEXP (x, 1)) > 0)
8717 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8722 /* Left shifts destroy copies. */
8723 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8724 || INTVAL (XEXP (x, 1)) < 0
8725 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8728 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8729 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8732 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8733 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8734 return MIN (num0, num1);
8736 case EQ: case NE: case GE: case GT: case LE: case LT:
8737 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8738 case GEU: case GTU: case LEU: case LTU:
8739 case UNORDERED: case ORDERED:
8740 /* If the constant is negative, take its 1's complement and remask.
8741 Then see how many zero bits we have. */
8742 nonzero = STORE_FLAG_VALUE;
8743 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8744 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8745 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8747 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8754 /* If we haven't been able to figure it out by one of the above rules,
8755 see if some of the high-order bits are known to be zero. If so,
8756 count those bits and return one less than that amount. If we can't
8757 safely compute the mask for this mode, always return BITWIDTH. */
8759 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8762 nonzero = nonzero_bits (x, mode);
8763 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8764 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8767 /* Return the number of "extended" bits there are in X, when interpreted
8768 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8769 unsigned quantities, this is the number of high-order zero bits.
8770 For signed quantities, this is the number of copies of the sign bit
8771 minus 1. In both case, this function returns the number of "spare"
8772 bits. For example, if two quantities for which this function returns
8773 at least 1 are added, the addition is known not to overflow.
8775 This function will always return 0 unless called during combine, which
8776 implies that it must be called from a define_split. */
8779 extended_count (x, mode, unsignedp)
8781 enum machine_mode mode;
8784 if (nonzero_sign_valid == 0)
8788 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8789 ? (GET_MODE_BITSIZE (mode) - 1
8790 - floor_log2 (nonzero_bits (x, mode)))
8792 : num_sign_bit_copies (x, mode) - 1);
8795 /* This function is called from `simplify_shift_const' to merge two
8796 outer operations. Specifically, we have already found that we need
8797 to perform operation *POP0 with constant *PCONST0 at the outermost
8798 position. We would now like to also perform OP1 with constant CONST1
8799 (with *POP0 being done last).
8801 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8802 the resulting operation. *PCOMP_P is set to 1 if we would need to
8803 complement the innermost operand, otherwise it is unchanged.
8805 MODE is the mode in which the operation will be done. No bits outside
8806 the width of this mode matter. It is assumed that the width of this mode
8807 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8809 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8810 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8811 result is simply *PCONST0.
8813 If the resulting operation cannot be expressed as one operation, we
8814 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8817 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8818 enum rtx_code *pop0;
8819 HOST_WIDE_INT *pconst0;
8821 HOST_WIDE_INT const1;
8822 enum machine_mode mode;
8825 enum rtx_code op0 = *pop0;
8826 HOST_WIDE_INT const0 = *pconst0;
8828 const0 &= GET_MODE_MASK (mode);
8829 const1 &= GET_MODE_MASK (mode);
8831 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8835 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8838 if (op1 == NIL || op0 == SET)
8841 else if (op0 == NIL)
8842 op0 = op1, const0 = const1;
8844 else if (op0 == op1)
8868 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8869 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8872 /* If the two constants aren't the same, we can't do anything. The
8873 remaining six cases can all be done. */
8874 else if (const0 != const1)
8882 /* (a & b) | b == b */
8884 else /* op1 == XOR */
8885 /* (a ^ b) | b == a | b */
8891 /* (a & b) ^ b == (~a) & b */
8892 op0 = AND, *pcomp_p = 1;
8893 else /* op1 == IOR */
8894 /* (a | b) ^ b == a & ~b */
8895 op0 = AND, *pconst0 = ~const0;
8900 /* (a | b) & b == b */
8902 else /* op1 == XOR */
8903 /* (a ^ b) & b) == (~a) & b */
8910 /* Check for NO-OP cases. */
8911 const0 &= GET_MODE_MASK (mode);
8913 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8915 else if (const0 == 0 && op0 == AND)
8917 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8921 /* ??? Slightly redundant with the above mask, but not entirely.
8922 Moving this above means we'd have to sign-extend the mode mask
8923 for the final test. */
8924 const0 = trunc_int_for_mode (const0, mode);
8932 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8933 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8934 that we started with.
8936 The shift is normally computed in the widest mode we find in VAROP, as
8937 long as it isn't a different number of words than RESULT_MODE. Exceptions
8938 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8941 simplify_shift_const (x, code, result_mode, varop, orig_count)
8944 enum machine_mode result_mode;
8948 enum rtx_code orig_code = code;
8951 enum machine_mode mode = result_mode;
8952 enum machine_mode shift_mode, tmode;
8953 unsigned int mode_words
8954 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8955 /* We form (outer_op (code varop count) (outer_const)). */
8956 enum rtx_code outer_op = NIL;
8957 HOST_WIDE_INT outer_const = 0;
8959 int complement_p = 0;
8962 /* Make sure and truncate the "natural" shift on the way in. We don't
8963 want to do this inside the loop as it makes it more difficult to
8965 #ifdef SHIFT_COUNT_TRUNCATED
8966 if (SHIFT_COUNT_TRUNCATED)
8967 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8970 /* If we were given an invalid count, don't do anything except exactly
8971 what was requested. */
8973 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8978 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8983 /* Unless one of the branches of the `if' in this loop does a `continue',
8984 we will `break' the loop after the `if'. */
8988 /* If we have an operand of (clobber (const_int 0)), just return that
8990 if (GET_CODE (varop) == CLOBBER)
8993 /* If we discovered we had to complement VAROP, leave. Making a NOT
8994 here would cause an infinite loop. */
8998 /* Convert ROTATERT to ROTATE. */
8999 if (code == ROTATERT)
9000 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
9002 /* We need to determine what mode we will do the shift in. If the
9003 shift is a right shift or a ROTATE, we must always do it in the mode
9004 it was originally done in. Otherwise, we can do it in MODE, the
9005 widest mode encountered. */
9007 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9008 ? result_mode : mode);
9010 /* Handle cases where the count is greater than the size of the mode
9011 minus 1. For ASHIFT, use the size minus one as the count (this can
9012 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9013 take the count modulo the size. For other shifts, the result is
9016 Since these shifts are being produced by the compiler by combining
9017 multiple operations, each of which are defined, we know what the
9018 result is supposed to be. */
9020 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
9022 if (code == ASHIFTRT)
9023 count = GET_MODE_BITSIZE (shift_mode) - 1;
9024 else if (code == ROTATE || code == ROTATERT)
9025 count %= GET_MODE_BITSIZE (shift_mode);
9028 /* We can't simply return zero because there may be an
9036 /* An arithmetic right shift of a quantity known to be -1 or 0
9038 if (code == ASHIFTRT
9039 && (num_sign_bit_copies (varop, shift_mode)
9040 == GET_MODE_BITSIZE (shift_mode)))
9046 /* If we are doing an arithmetic right shift and discarding all but
9047 the sign bit copies, this is equivalent to doing a shift by the
9048 bitsize minus one. Convert it into that shift because it will often
9049 allow other simplifications. */
9051 if (code == ASHIFTRT
9052 && (count + num_sign_bit_copies (varop, shift_mode)
9053 >= GET_MODE_BITSIZE (shift_mode)))
9054 count = GET_MODE_BITSIZE (shift_mode) - 1;
9056 /* We simplify the tests below and elsewhere by converting
9057 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9058 `make_compound_operation' will convert it to an ASHIFTRT for
9059 those machines (such as VAX) that don't have an LSHIFTRT. */
9060 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9062 && ((nonzero_bits (varop, shift_mode)
9063 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9067 switch (GET_CODE (varop))
9073 new = expand_compound_operation (varop);
9082 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9083 minus the width of a smaller mode, we can do this with a
9084 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9085 if ((code == ASHIFTRT || code == LSHIFTRT)
9086 && ! mode_dependent_address_p (XEXP (varop, 0))
9087 && ! MEM_VOLATILE_P (varop)
9088 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9089 MODE_INT, 1)) != BLKmode)
9091 new = adjust_address_nv (varop, tmode,
9092 BYTES_BIG_ENDIAN ? 0
9093 : count / BITS_PER_UNIT);
9095 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9096 : ZERO_EXTEND, mode, new);
9103 /* Similar to the case above, except that we can only do this if
9104 the resulting mode is the same as that of the underlying
9105 MEM and adjust the address depending on the *bits* endianness
9106 because of the way that bit-field extract insns are defined. */
9107 if ((code == ASHIFTRT || code == LSHIFTRT)
9108 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9109 MODE_INT, 1)) != BLKmode
9110 && tmode == GET_MODE (XEXP (varop, 0)))
9112 if (BITS_BIG_ENDIAN)
9113 new = XEXP (varop, 0);
9116 new = copy_rtx (XEXP (varop, 0));
9117 SUBST (XEXP (new, 0),
9118 plus_constant (XEXP (new, 0),
9119 count / BITS_PER_UNIT));
9122 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9123 : ZERO_EXTEND, mode, new);
9130 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9131 the same number of words as what we've seen so far. Then store
9132 the widest mode in MODE. */
9133 if (subreg_lowpart_p (varop)
9134 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9135 > GET_MODE_SIZE (GET_MODE (varop)))
9136 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9137 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9140 varop = SUBREG_REG (varop);
9141 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9142 mode = GET_MODE (varop);
9148 /* Some machines use MULT instead of ASHIFT because MULT
9149 is cheaper. But it is still better on those machines to
9150 merge two shifts into one. */
9151 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9152 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9155 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9156 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9162 /* Similar, for when divides are cheaper. */
9163 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9164 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9167 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9168 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9174 /* If we are extracting just the sign bit of an arithmetic
9175 right shift, that shift is not needed. However, the sign
9176 bit of a wider mode may be different from what would be
9177 interpreted as the sign bit in a narrower mode, so, if
9178 the result is narrower, don't discard the shift. */
9179 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9180 && (GET_MODE_BITSIZE (result_mode)
9181 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9183 varop = XEXP (varop, 0);
9187 /* ... fall through ... */
9192 /* Here we have two nested shifts. The result is usually the
9193 AND of a new shift with a mask. We compute the result below. */
9194 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9195 && INTVAL (XEXP (varop, 1)) >= 0
9196 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9197 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9198 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9200 enum rtx_code first_code = GET_CODE (varop);
9201 unsigned int first_count = INTVAL (XEXP (varop, 1));
9202 unsigned HOST_WIDE_INT mask;
9205 /* We have one common special case. We can't do any merging if
9206 the inner code is an ASHIFTRT of a smaller mode. However, if
9207 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9208 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9209 we can convert it to
9210 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9211 This simplifies certain SIGN_EXTEND operations. */
9212 if (code == ASHIFT && first_code == ASHIFTRT
9213 && (GET_MODE_BITSIZE (result_mode)
9214 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9216 /* C3 has the low-order C1 bits zero. */
9218 mask = (GET_MODE_MASK (mode)
9219 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9221 varop = simplify_and_const_int (NULL_RTX, result_mode,
9222 XEXP (varop, 0), mask);
9223 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9225 count = first_count;
9230 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9231 than C1 high-order bits equal to the sign bit, we can convert
9232 this to either an ASHIFT or an ASHIFTRT depending on the
9235 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9237 if (code == ASHIFTRT && first_code == ASHIFT
9238 && GET_MODE (varop) == shift_mode
9239 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9242 varop = XEXP (varop, 0);
9244 signed_count = count - first_count;
9245 if (signed_count < 0)
9246 count = -signed_count, code = ASHIFT;
9248 count = signed_count;
9253 /* There are some cases we can't do. If CODE is ASHIFTRT,
9254 we can only do this if FIRST_CODE is also ASHIFTRT.
9256 We can't do the case when CODE is ROTATE and FIRST_CODE is
9259 If the mode of this shift is not the mode of the outer shift,
9260 we can't do this if either shift is a right shift or ROTATE.
9262 Finally, we can't do any of these if the mode is too wide
9263 unless the codes are the same.
9265 Handle the case where the shift codes are the same
9268 if (code == first_code)
9270 if (GET_MODE (varop) != result_mode
9271 && (code == ASHIFTRT || code == LSHIFTRT
9275 count += first_count;
9276 varop = XEXP (varop, 0);
9280 if (code == ASHIFTRT
9281 || (code == ROTATE && first_code == ASHIFTRT)
9282 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9283 || (GET_MODE (varop) != result_mode
9284 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9285 || first_code == ROTATE
9286 || code == ROTATE)))
9289 /* To compute the mask to apply after the shift, shift the
9290 nonzero bits of the inner shift the same way the
9291 outer shift will. */
9293 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9296 = simplify_binary_operation (code, result_mode, mask_rtx,
9299 /* Give up if we can't compute an outer operation to use. */
9301 || GET_CODE (mask_rtx) != CONST_INT
9302 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9304 result_mode, &complement_p))
9307 /* If the shifts are in the same direction, we add the
9308 counts. Otherwise, we subtract them. */
9309 signed_count = count;
9310 if ((code == ASHIFTRT || code == LSHIFTRT)
9311 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9312 signed_count += first_count;
9314 signed_count -= first_count;
9316 /* If COUNT is positive, the new shift is usually CODE,
9317 except for the two exceptions below, in which case it is
9318 FIRST_CODE. If the count is negative, FIRST_CODE should
9320 if (signed_count > 0
9321 && ((first_code == ROTATE && code == ASHIFT)
9322 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9323 code = first_code, count = signed_count;
9324 else if (signed_count < 0)
9325 code = first_code, count = -signed_count;
9327 count = signed_count;
9329 varop = XEXP (varop, 0);
9333 /* If we have (A << B << C) for any shift, we can convert this to
9334 (A << C << B). This wins if A is a constant. Only try this if
9335 B is not a constant. */
9337 else if (GET_CODE (varop) == code
9338 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9340 = simplify_binary_operation (code, mode,
9344 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9351 /* Make this fit the case below. */
9352 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9353 GEN_INT (GET_MODE_MASK (mode)));
9359 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9360 with C the size of VAROP - 1 and the shift is logical if
9361 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9362 we have an (le X 0) operation. If we have an arithmetic shift
9363 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9364 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9366 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9367 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9368 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9369 && (code == LSHIFTRT || code == ASHIFTRT)
9370 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9371 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9374 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9377 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9378 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9383 /* If we have (shift (logical)), move the logical to the outside
9384 to allow it to possibly combine with another logical and the
9385 shift to combine with another shift. This also canonicalizes to
9386 what a ZERO_EXTRACT looks like. Also, some machines have
9387 (and (shift)) insns. */
9389 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9390 && (new = simplify_binary_operation (code, result_mode,
9392 GEN_INT (count))) != 0
9393 && GET_CODE (new) == CONST_INT
9394 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9395 INTVAL (new), result_mode, &complement_p))
9397 varop = XEXP (varop, 0);
9401 /* If we can't do that, try to simplify the shift in each arm of the
9402 logical expression, make a new logical expression, and apply
9403 the inverse distributive law. */
9405 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9406 XEXP (varop, 0), count);
9407 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9408 XEXP (varop, 1), count);
9410 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9411 varop = apply_distributive_law (varop);
9418 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9419 says that the sign bit can be tested, FOO has mode MODE, C is
9420 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9421 that may be nonzero. */
9422 if (code == LSHIFTRT
9423 && XEXP (varop, 1) == const0_rtx
9424 && GET_MODE (XEXP (varop, 0)) == result_mode
9425 && count == GET_MODE_BITSIZE (result_mode) - 1
9426 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9427 && ((STORE_FLAG_VALUE
9428 & ((HOST_WIDE_INT) 1
9429 < (GET_MODE_BITSIZE (result_mode) - 1))))
9430 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9431 && merge_outer_ops (&outer_op, &outer_const, XOR,
9432 (HOST_WIDE_INT) 1, result_mode,
9435 varop = XEXP (varop, 0);
9442 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9443 than the number of bits in the mode is equivalent to A. */
9444 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9445 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9447 varop = XEXP (varop, 0);
9452 /* NEG commutes with ASHIFT since it is multiplication. Move the
9453 NEG outside to allow shifts to combine. */
9455 && merge_outer_ops (&outer_op, &outer_const, NEG,
9456 (HOST_WIDE_INT) 0, result_mode,
9459 varop = XEXP (varop, 0);
9465 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9466 is one less than the number of bits in the mode is
9467 equivalent to (xor A 1). */
9468 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9469 && XEXP (varop, 1) == constm1_rtx
9470 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9471 && merge_outer_ops (&outer_op, &outer_const, XOR,
9472 (HOST_WIDE_INT) 1, result_mode,
9476 varop = XEXP (varop, 0);
9480 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9481 that might be nonzero in BAR are those being shifted out and those
9482 bits are known zero in FOO, we can replace the PLUS with FOO.
9483 Similarly in the other operand order. This code occurs when
9484 we are computing the size of a variable-size array. */
9486 if ((code == ASHIFTRT || code == LSHIFTRT)
9487 && count < HOST_BITS_PER_WIDE_INT
9488 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9489 && (nonzero_bits (XEXP (varop, 1), result_mode)
9490 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9492 varop = XEXP (varop, 0);
9495 else if ((code == ASHIFTRT || code == LSHIFTRT)
9496 && count < HOST_BITS_PER_WIDE_INT
9497 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9498 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9500 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9501 & nonzero_bits (XEXP (varop, 1),
9504 varop = XEXP (varop, 1);
9508 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9510 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9511 && (new = simplify_binary_operation (ASHIFT, result_mode,
9513 GEN_INT (count))) != 0
9514 && GET_CODE (new) == CONST_INT
9515 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9516 INTVAL (new), result_mode, &complement_p))
9518 varop = XEXP (varop, 0);
9524 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9525 with C the size of VAROP - 1 and the shift is logical if
9526 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9527 we have a (gt X 0) operation. If the shift is arithmetic with
9528 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9529 we have a (neg (gt X 0)) operation. */
9531 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9532 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9533 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9534 && (code == LSHIFTRT || code == ASHIFTRT)
9535 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9536 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9537 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9540 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9543 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9544 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9551 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9552 if the truncate does not affect the value. */
9553 if (code == LSHIFTRT
9554 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9555 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9556 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9557 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9558 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9560 rtx varop_inner = XEXP (varop, 0);
9563 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9564 XEXP (varop_inner, 0),
9566 (count + INTVAL (XEXP (varop_inner, 1))));
9567 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9580 /* We need to determine what mode to do the shift in. If the shift is
9581 a right shift or ROTATE, we must always do it in the mode it was
9582 originally done in. Otherwise, we can do it in MODE, the widest mode
9583 encountered. The code we care about is that of the shift that will
9584 actually be done, not the shift that was originally requested. */
9586 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9587 ? result_mode : mode);
9589 /* We have now finished analyzing the shift. The result should be
9590 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9591 OUTER_OP is non-NIL, it is an operation that needs to be applied
9592 to the result of the shift. OUTER_CONST is the relevant constant,
9593 but we must turn off all bits turned off in the shift.
9595 If we were passed a value for X, see if we can use any pieces of
9596 it. If not, make new rtx. */
9598 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9599 && GET_CODE (XEXP (x, 1)) == CONST_INT
9600 && INTVAL (XEXP (x, 1)) == count)
9601 const_rtx = XEXP (x, 1);
9603 const_rtx = GEN_INT (count);
9605 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9606 && GET_MODE (XEXP (x, 0)) == shift_mode
9607 && SUBREG_REG (XEXP (x, 0)) == varop)
9608 varop = XEXP (x, 0);
9609 else if (GET_MODE (varop) != shift_mode)
9610 varop = gen_lowpart_for_combine (shift_mode, varop);
9612 /* If we can't make the SUBREG, try to return what we were given. */
9613 if (GET_CODE (varop) == CLOBBER)
9614 return x ? x : varop;
9616 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9620 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9622 /* If we have an outer operation and we just made a shift, it is
9623 possible that we could have simplified the shift were it not
9624 for the outer operation. So try to do the simplification
9627 if (outer_op != NIL && GET_CODE (x) == code
9628 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9629 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9630 INTVAL (XEXP (x, 1)));
9632 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9633 turn off all the bits that the shift would have turned off. */
9634 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9635 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9636 GET_MODE_MASK (result_mode) >> orig_count);
9638 /* Do the remainder of the processing in RESULT_MODE. */
9639 x = gen_lowpart_for_combine (result_mode, x);
9641 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9644 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9646 if (outer_op != NIL)
9648 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9649 outer_const = trunc_int_for_mode (outer_const, result_mode);
9651 if (outer_op == AND)
9652 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9653 else if (outer_op == SET)
9654 /* This means that we have determined that the result is
9655 equivalent to a constant. This should be rare. */
9656 x = GEN_INT (outer_const);
9657 else if (GET_RTX_CLASS (outer_op) == '1')
9658 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9660 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9666 /* Like recog, but we receive the address of a pointer to a new pattern.
9667 We try to match the rtx that the pointer points to.
9668 If that fails, we may try to modify or replace the pattern,
9669 storing the replacement into the same pointer object.
9671 Modifications include deletion or addition of CLOBBERs.
9673 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9674 the CLOBBERs are placed.
9676 The value is the final insn code from the pattern ultimately matched,
9680 recog_for_combine (pnewpat, insn, pnotes)
9686 int insn_code_number;
9687 int num_clobbers_to_add = 0;
9692 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9693 we use to indicate that something didn't match. If we find such a
9694 thing, force rejection. */
9695 if (GET_CODE (pat) == PARALLEL)
9696 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9697 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9698 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9701 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9702 instruction for pattern recognition. */
9703 dummy_insn = shallow_copy_rtx (insn);
9704 PATTERN (dummy_insn) = pat;
9705 REG_NOTES (dummy_insn) = 0;
9707 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9709 /* If it isn't, there is the possibility that we previously had an insn
9710 that clobbered some register as a side effect, but the combined
9711 insn doesn't need to do that. So try once more without the clobbers
9712 unless this represents an ASM insn. */
9714 if (insn_code_number < 0 && ! check_asm_operands (pat)
9715 && GET_CODE (pat) == PARALLEL)
9719 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9720 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9723 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9727 SUBST_INT (XVECLEN (pat, 0), pos);
9730 pat = XVECEXP (pat, 0, 0);
9732 PATTERN (dummy_insn) = pat;
9733 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9736 /* Recognize all noop sets, these will be killed by followup pass. */
9737 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9738 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9740 /* If we had any clobbers to add, make a new pattern than contains
9741 them. Then check to make sure that all of them are dead. */
9742 if (num_clobbers_to_add)
9744 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9745 rtvec_alloc (GET_CODE (pat) == PARALLEL
9747 + num_clobbers_to_add)
9748 : num_clobbers_to_add + 1));
9750 if (GET_CODE (pat) == PARALLEL)
9751 for (i = 0; i < XVECLEN (pat, 0); i++)
9752 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9754 XVECEXP (newpat, 0, 0) = pat;
9756 add_clobbers (newpat, insn_code_number);
9758 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9759 i < XVECLEN (newpat, 0); i++)
9761 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9762 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9764 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9765 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9773 return insn_code_number;
9776 /* Like gen_lowpart but for use by combine. In combine it is not possible
9777 to create any new pseudoregs. However, it is safe to create
9778 invalid memory addresses, because combine will try to recognize
9779 them and all they will do is make the combine attempt fail.
9781 If for some reason this cannot do its job, an rtx
9782 (clobber (const_int 0)) is returned.
9783 An insn containing that will not be recognized. */
9788 gen_lowpart_for_combine (mode, x)
9789 enum machine_mode mode;
9794 if (GET_MODE (x) == mode)
9797 /* We can only support MODE being wider than a word if X is a
9798 constant integer or has a mode the same size. */
9800 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9801 && ! ((GET_MODE (x) == VOIDmode
9802 && (GET_CODE (x) == CONST_INT
9803 || GET_CODE (x) == CONST_DOUBLE))
9804 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9805 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9807 /* simplify_gen_subreg does not know how to handle the case where we try
9808 to convert an integer constant to a vector.
9809 ??? We could try to teach it to generate CONST_VECTORs. */
9810 if (GET_MODE (x) == VOIDmode && VECTOR_MODE_P (mode))
9811 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9813 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9814 won't know what to do. So we will strip off the SUBREG here and
9815 process normally. */
9816 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9819 if (GET_MODE (x) == mode)
9823 result = gen_lowpart_common (mode, x);
9824 #ifdef CLASS_CANNOT_CHANGE_MODE
9826 && GET_CODE (result) == SUBREG
9827 && GET_CODE (SUBREG_REG (result)) == REG
9828 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9829 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9830 GET_MODE (SUBREG_REG (result))))
9831 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9837 if (GET_CODE (x) == MEM)
9841 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9843 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9844 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9846 /* If we want to refer to something bigger than the original memref,
9847 generate a perverse subreg instead. That will force a reload
9848 of the original memref X. */
9849 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9850 return gen_rtx_SUBREG (mode, x, 0);
9852 if (WORDS_BIG_ENDIAN)
9853 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9854 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9856 if (BYTES_BIG_ENDIAN)
9858 /* Adjust the address so that the address-after-the-data is
9860 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9861 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9864 return adjust_address_nv (x, mode, offset);
9867 /* If X is a comparison operator, rewrite it in a new mode. This
9868 probably won't match, but may allow further simplifications. */
9869 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9870 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9872 /* If we couldn't simplify X any other way, just enclose it in a
9873 SUBREG. Normally, this SUBREG won't match, but some patterns may
9874 include an explicit SUBREG or we may simplify it further in combine. */
9880 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9881 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9884 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9888 /* These routines make binary and unary operations by first seeing if they
9889 fold; if not, a new expression is allocated. */
9892 gen_binary (code, mode, op0, op1)
9894 enum machine_mode mode;
9900 if (GET_RTX_CLASS (code) == 'c'
9901 && swap_commutative_operands_p (op0, op1))
9902 tem = op0, op0 = op1, op1 = tem;
9904 if (GET_RTX_CLASS (code) == '<')
9906 enum machine_mode op_mode = GET_MODE (op0);
9908 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9909 just (REL_OP X Y). */
9910 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9912 op1 = XEXP (op0, 1);
9913 op0 = XEXP (op0, 0);
9914 op_mode = GET_MODE (op0);
9917 if (op_mode == VOIDmode)
9918 op_mode = GET_MODE (op1);
9919 result = simplify_relational_operation (code, op_mode, op0, op1);
9922 result = simplify_binary_operation (code, mode, op0, op1);
9927 /* Put complex operands first and constants second. */
9928 if (GET_RTX_CLASS (code) == 'c'
9929 && swap_commutative_operands_p (op0, op1))
9930 return gen_rtx_fmt_ee (code, mode, op1, op0);
9932 /* If we are turning off bits already known off in OP0, we need not do
9934 else if (code == AND && GET_CODE (op1) == CONST_INT
9935 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9936 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9939 return gen_rtx_fmt_ee (code, mode, op0, op1);
9942 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9943 comparison code that will be tested.
9945 The result is a possibly different comparison code to use. *POP0 and
9946 *POP1 may be updated.
9948 It is possible that we might detect that a comparison is either always
9949 true or always false. However, we do not perform general constant
9950 folding in combine, so this knowledge isn't useful. Such tautologies
9951 should have been detected earlier. Hence we ignore all such cases. */
9953 static enum rtx_code
9954 simplify_comparison (code, pop0, pop1)
9963 enum machine_mode mode, tmode;
9965 /* Try a few ways of applying the same transformation to both operands. */
9968 #ifndef WORD_REGISTER_OPERATIONS
9969 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9970 so check specially. */
9971 if (code != GTU && code != GEU && code != LTU && code != LEU
9972 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9973 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9974 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9975 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9976 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9977 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9978 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9979 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9980 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9981 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9982 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9983 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9984 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9985 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9986 && (INTVAL (XEXP (op0, 1))
9987 == (GET_MODE_BITSIZE (GET_MODE (op0))
9989 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9991 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9992 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9996 /* If both operands are the same constant shift, see if we can ignore the
9997 shift. We can if the shift is a rotate or if the bits shifted out of
9998 this shift are known to be zero for both inputs and if the type of
9999 comparison is compatible with the shift. */
10000 if (GET_CODE (op0) == GET_CODE (op1)
10001 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10002 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10003 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10004 && (code != GT && code != LT && code != GE && code != LE))
10005 || (GET_CODE (op0) == ASHIFTRT
10006 && (code != GTU && code != LTU
10007 && code != GEU && code != LEU)))
10008 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10009 && INTVAL (XEXP (op0, 1)) >= 0
10010 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10011 && XEXP (op0, 1) == XEXP (op1, 1))
10013 enum machine_mode mode = GET_MODE (op0);
10014 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10015 int shift_count = INTVAL (XEXP (op0, 1));
10017 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10018 mask &= (mask >> shift_count) << shift_count;
10019 else if (GET_CODE (op0) == ASHIFT)
10020 mask = (mask & (mask << shift_count)) >> shift_count;
10022 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10023 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10024 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10029 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10030 SUBREGs are of the same mode, and, in both cases, the AND would
10031 be redundant if the comparison was done in the narrower mode,
10032 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10033 and the operand's possibly nonzero bits are 0xffffff01; in that case
10034 if we only care about QImode, we don't need the AND). This case
10035 occurs if the output mode of an scc insn is not SImode and
10036 STORE_FLAG_VALUE == 1 (e.g., the 386).
10038 Similarly, check for a case where the AND's are ZERO_EXTEND
10039 operations from some narrower mode even though a SUBREG is not
10042 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10043 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10044 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10046 rtx inner_op0 = XEXP (op0, 0);
10047 rtx inner_op1 = XEXP (op1, 0);
10048 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10049 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10052 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10053 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10054 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10055 && (GET_MODE (SUBREG_REG (inner_op0))
10056 == GET_MODE (SUBREG_REG (inner_op1)))
10057 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10058 <= HOST_BITS_PER_WIDE_INT)
10059 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10060 GET_MODE (SUBREG_REG (inner_op0)))))
10061 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10062 GET_MODE (SUBREG_REG (inner_op1))))))
10064 op0 = SUBREG_REG (inner_op0);
10065 op1 = SUBREG_REG (inner_op1);
10067 /* The resulting comparison is always unsigned since we masked
10068 off the original sign bit. */
10069 code = unsigned_condition (code);
10075 for (tmode = GET_CLASS_NARROWEST_MODE
10076 (GET_MODE_CLASS (GET_MODE (op0)));
10077 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10078 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10080 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10081 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10082 code = unsigned_condition (code);
10091 /* If both operands are NOT, we can strip off the outer operation
10092 and adjust the comparison code for swapped operands; similarly for
10093 NEG, except that this must be an equality comparison. */
10094 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10095 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10096 && (code == EQ || code == NE)))
10097 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10103 /* If the first operand is a constant, swap the operands and adjust the
10104 comparison code appropriately, but don't do this if the second operand
10105 is already a constant integer. */
10106 if (swap_commutative_operands_p (op0, op1))
10108 tem = op0, op0 = op1, op1 = tem;
10109 code = swap_condition (code);
10112 /* We now enter a loop during which we will try to simplify the comparison.
10113 For the most part, we only are concerned with comparisons with zero,
10114 but some things may really be comparisons with zero but not start
10115 out looking that way. */
10117 while (GET_CODE (op1) == CONST_INT)
10119 enum machine_mode mode = GET_MODE (op0);
10120 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10121 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10122 int equality_comparison_p;
10123 int sign_bit_comparison_p;
10124 int unsigned_comparison_p;
10125 HOST_WIDE_INT const_op;
10127 /* We only want to handle integral modes. This catches VOIDmode,
10128 CCmode, and the floating-point modes. An exception is that we
10129 can handle VOIDmode if OP0 is a COMPARE or a comparison
10132 if (GET_MODE_CLASS (mode) != MODE_INT
10133 && ! (mode == VOIDmode
10134 && (GET_CODE (op0) == COMPARE
10135 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10138 /* Get the constant we are comparing against and turn off all bits
10139 not on in our mode. */
10140 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10141 op1 = GEN_INT (const_op);
10143 /* If we are comparing against a constant power of two and the value
10144 being compared can only have that single bit nonzero (e.g., it was
10145 `and'ed with that bit), we can replace this with a comparison
10148 && (code == EQ || code == NE || code == GE || code == GEU
10149 || code == LT || code == LTU)
10150 && mode_width <= HOST_BITS_PER_WIDE_INT
10151 && exact_log2 (const_op) >= 0
10152 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10154 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10155 op1 = const0_rtx, const_op = 0;
10158 /* Similarly, if we are comparing a value known to be either -1 or
10159 0 with -1, change it to the opposite comparison against zero. */
10162 && (code == EQ || code == NE || code == GT || code == LE
10163 || code == GEU || code == LTU)
10164 && num_sign_bit_copies (op0, mode) == mode_width)
10166 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10167 op1 = const0_rtx, const_op = 0;
10170 /* Do some canonicalizations based on the comparison code. We prefer
10171 comparisons against zero and then prefer equality comparisons.
10172 If we can reduce the size of a constant, we will do that too. */
10177 /* < C is equivalent to <= (C - 1) */
10181 op1 = GEN_INT (const_op);
10183 /* ... fall through to LE case below. */
10189 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10193 op1 = GEN_INT (const_op);
10197 /* If we are doing a <= 0 comparison on a value known to have
10198 a zero sign bit, we can replace this with == 0. */
10199 else if (const_op == 0
10200 && mode_width <= HOST_BITS_PER_WIDE_INT
10201 && (nonzero_bits (op0, mode)
10202 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10207 /* >= C is equivalent to > (C - 1). */
10211 op1 = GEN_INT (const_op);
10213 /* ... fall through to GT below. */
10219 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10223 op1 = GEN_INT (const_op);
10227 /* If we are doing a > 0 comparison on a value known to have
10228 a zero sign bit, we can replace this with != 0. */
10229 else if (const_op == 0
10230 && mode_width <= HOST_BITS_PER_WIDE_INT
10231 && (nonzero_bits (op0, mode)
10232 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10237 /* < C is equivalent to <= (C - 1). */
10241 op1 = GEN_INT (const_op);
10243 /* ... fall through ... */
10246 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10247 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10248 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10250 const_op = 0, op1 = const0_rtx;
10258 /* unsigned <= 0 is equivalent to == 0 */
10262 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10263 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10264 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10266 const_op = 0, op1 = const0_rtx;
10272 /* >= C is equivalent to < (C - 1). */
10276 op1 = GEN_INT (const_op);
10278 /* ... fall through ... */
10281 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10282 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10283 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10285 const_op = 0, op1 = const0_rtx;
10293 /* unsigned > 0 is equivalent to != 0 */
10297 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10298 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10299 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10301 const_op = 0, op1 = const0_rtx;
10310 /* Compute some predicates to simplify code below. */
10312 equality_comparison_p = (code == EQ || code == NE);
10313 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10314 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10317 /* If this is a sign bit comparison and we can do arithmetic in
10318 MODE, say that we will only be needing the sign bit of OP0. */
10319 if (sign_bit_comparison_p
10320 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10321 op0 = force_to_mode (op0, mode,
10323 << (GET_MODE_BITSIZE (mode) - 1)),
10326 /* Now try cases based on the opcode of OP0. If none of the cases
10327 does a "continue", we exit this loop immediately after the
10330 switch (GET_CODE (op0))
10333 /* If we are extracting a single bit from a variable position in
10334 a constant that has only a single bit set and are comparing it
10335 with zero, we can convert this into an equality comparison
10336 between the position and the location of the single bit. */
10338 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10339 && XEXP (op0, 1) == const1_rtx
10340 && equality_comparison_p && const_op == 0
10341 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10343 if (BITS_BIG_ENDIAN)
10345 enum machine_mode new_mode
10346 = mode_for_extraction (EP_extzv, 1);
10347 if (new_mode == MAX_MACHINE_MODE)
10348 i = BITS_PER_WORD - 1 - i;
10352 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10356 op0 = XEXP (op0, 2);
10360 /* Result is nonzero iff shift count is equal to I. */
10361 code = reverse_condition (code);
10365 /* ... fall through ... */
10368 tem = expand_compound_operation (op0);
10377 /* If testing for equality, we can take the NOT of the constant. */
10378 if (equality_comparison_p
10379 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10381 op0 = XEXP (op0, 0);
10386 /* If just looking at the sign bit, reverse the sense of the
10388 if (sign_bit_comparison_p)
10390 op0 = XEXP (op0, 0);
10391 code = (code == GE ? LT : GE);
10397 /* If testing for equality, we can take the NEG of the constant. */
10398 if (equality_comparison_p
10399 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10401 op0 = XEXP (op0, 0);
10406 /* The remaining cases only apply to comparisons with zero. */
10410 /* When X is ABS or is known positive,
10411 (neg X) is < 0 if and only if X != 0. */
10413 if (sign_bit_comparison_p
10414 && (GET_CODE (XEXP (op0, 0)) == ABS
10415 || (mode_width <= HOST_BITS_PER_WIDE_INT
10416 && (nonzero_bits (XEXP (op0, 0), mode)
10417 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10419 op0 = XEXP (op0, 0);
10420 code = (code == LT ? NE : EQ);
10424 /* If we have NEG of something whose two high-order bits are the
10425 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10426 if (num_sign_bit_copies (op0, mode) >= 2)
10428 op0 = XEXP (op0, 0);
10429 code = swap_condition (code);
10435 /* If we are testing equality and our count is a constant, we
10436 can perform the inverse operation on our RHS. */
10437 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10438 && (tem = simplify_binary_operation (ROTATERT, mode,
10439 op1, XEXP (op0, 1))) != 0)
10441 op0 = XEXP (op0, 0);
10446 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10447 a particular bit. Convert it to an AND of a constant of that
10448 bit. This will be converted into a ZERO_EXTRACT. */
10449 if (const_op == 0 && sign_bit_comparison_p
10450 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10451 && mode_width <= HOST_BITS_PER_WIDE_INT)
10453 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10456 - INTVAL (XEXP (op0, 1)))));
10457 code = (code == LT ? NE : EQ);
10461 /* Fall through. */
10464 /* ABS is ignorable inside an equality comparison with zero. */
10465 if (const_op == 0 && equality_comparison_p)
10467 op0 = XEXP (op0, 0);
10473 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10474 to (compare FOO CONST) if CONST fits in FOO's mode and we
10475 are either testing inequality or have an unsigned comparison
10476 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10477 if (! unsigned_comparison_p
10478 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10479 <= HOST_BITS_PER_WIDE_INT)
10480 && ((unsigned HOST_WIDE_INT) const_op
10481 < (((unsigned HOST_WIDE_INT) 1
10482 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10484 op0 = XEXP (op0, 0);
10490 /* Check for the case where we are comparing A - C1 with C2,
10491 both constants are smaller than 1/2 the maximum positive
10492 value in MODE, and the comparison is equality or unsigned.
10493 In that case, if A is either zero-extended to MODE or has
10494 sufficient sign bits so that the high-order bit in MODE
10495 is a copy of the sign in the inner mode, we can prove that it is
10496 safe to do the operation in the wider mode. This simplifies
10497 many range checks. */
10499 if (mode_width <= HOST_BITS_PER_WIDE_INT
10500 && subreg_lowpart_p (op0)
10501 && GET_CODE (SUBREG_REG (op0)) == PLUS
10502 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10503 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10504 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10505 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10506 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10507 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10508 GET_MODE (SUBREG_REG (op0)))
10509 & ~GET_MODE_MASK (mode))
10510 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10511 GET_MODE (SUBREG_REG (op0)))
10512 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10513 - GET_MODE_BITSIZE (mode)))))
10515 op0 = SUBREG_REG (op0);
10519 /* If the inner mode is narrower and we are extracting the low part,
10520 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10521 if (subreg_lowpart_p (op0)
10522 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10523 /* Fall through */ ;
10527 /* ... fall through ... */
10530 if ((unsigned_comparison_p || equality_comparison_p)
10531 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10532 <= HOST_BITS_PER_WIDE_INT)
10533 && ((unsigned HOST_WIDE_INT) const_op
10534 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10536 op0 = XEXP (op0, 0);
10542 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10543 this for equality comparisons due to pathological cases involving
10545 if (equality_comparison_p
10546 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10547 op1, XEXP (op0, 1))))
10549 op0 = XEXP (op0, 0);
10554 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10555 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10556 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10558 op0 = XEXP (XEXP (op0, 0), 0);
10559 code = (code == LT ? EQ : NE);
10565 /* We used to optimize signed comparisons against zero, but that
10566 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10567 arrive here as equality comparisons, or (GEU, LTU) are
10568 optimized away. No need to special-case them. */
10570 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10571 (eq B (minus A C)), whichever simplifies. We can only do
10572 this for equality comparisons due to pathological cases involving
10574 if (equality_comparison_p
10575 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10576 XEXP (op0, 1), op1)))
10578 op0 = XEXP (op0, 0);
10583 if (equality_comparison_p
10584 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10585 XEXP (op0, 0), op1)))
10587 op0 = XEXP (op0, 1);
10592 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10593 of bits in X minus 1, is one iff X > 0. */
10594 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10595 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10596 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10597 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10599 op0 = XEXP (op0, 1);
10600 code = (code == GE ? LE : GT);
10606 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10607 if C is zero or B is a constant. */
10608 if (equality_comparison_p
10609 && 0 != (tem = simplify_binary_operation (XOR, mode,
10610 XEXP (op0, 1), op1)))
10612 op0 = XEXP (op0, 0);
10619 case UNEQ: case LTGT:
10620 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10621 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10622 case UNORDERED: case ORDERED:
10623 /* We can't do anything if OP0 is a condition code value, rather
10624 than an actual data value. */
10627 || XEXP (op0, 0) == cc0_rtx
10629 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10632 /* Get the two operands being compared. */
10633 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10634 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10636 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10638 /* Check for the cases where we simply want the result of the
10639 earlier test or the opposite of that result. */
10640 if (code == NE || code == EQ
10641 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10642 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10643 && (STORE_FLAG_VALUE
10644 & (((HOST_WIDE_INT) 1
10645 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10646 && (code == LT || code == GE)))
10648 enum rtx_code new_code;
10649 if (code == LT || code == NE)
10650 new_code = GET_CODE (op0);
10652 new_code = combine_reversed_comparison_code (op0);
10654 if (new_code != UNKNOWN)
10665 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10667 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10668 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10669 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10671 op0 = XEXP (op0, 1);
10672 code = (code == GE ? GT : LE);
10678 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10679 will be converted to a ZERO_EXTRACT later. */
10680 if (const_op == 0 && equality_comparison_p
10681 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10682 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10684 op0 = simplify_and_const_int
10685 (op0, mode, gen_rtx_LSHIFTRT (mode,
10687 XEXP (XEXP (op0, 0), 1)),
10688 (HOST_WIDE_INT) 1);
10692 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10693 zero and X is a comparison and C1 and C2 describe only bits set
10694 in STORE_FLAG_VALUE, we can compare with X. */
10695 if (const_op == 0 && equality_comparison_p
10696 && mode_width <= HOST_BITS_PER_WIDE_INT
10697 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10698 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10699 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10700 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10701 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10703 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10704 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10705 if ((~STORE_FLAG_VALUE & mask) == 0
10706 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10707 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10708 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10710 op0 = XEXP (XEXP (op0, 0), 0);
10715 /* If we are doing an equality comparison of an AND of a bit equal
10716 to the sign bit, replace this with a LT or GE comparison of
10717 the underlying value. */
10718 if (equality_comparison_p
10720 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10721 && mode_width <= HOST_BITS_PER_WIDE_INT
10722 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10723 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10725 op0 = XEXP (op0, 0);
10726 code = (code == EQ ? GE : LT);
10730 /* If this AND operation is really a ZERO_EXTEND from a narrower
10731 mode, the constant fits within that mode, and this is either an
10732 equality or unsigned comparison, try to do this comparison in
10733 the narrower mode. */
10734 if ((equality_comparison_p || unsigned_comparison_p)
10735 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10736 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10737 & GET_MODE_MASK (mode))
10739 && const_op >> i == 0
10740 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10742 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10746 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10747 in both M1 and M2 and the SUBREG is either paradoxical or
10748 represents the low part, permute the SUBREG and the AND and
10750 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10752 #ifdef WORD_REGISTER_OPERATIONS
10754 > (GET_MODE_BITSIZE
10755 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10756 && mode_width <= BITS_PER_WORD)
10759 <= (GET_MODE_BITSIZE
10760 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10761 && subreg_lowpart_p (XEXP (op0, 0))))
10762 #ifndef WORD_REGISTER_OPERATIONS
10763 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10764 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10765 As originally written the upper bits have a defined value
10766 due to the AND operation. However, if we commute the AND
10767 inside the SUBREG then they no longer have defined values
10768 and the meaning of the code has been changed. */
10769 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10770 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10772 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10773 && mode_width <= HOST_BITS_PER_WIDE_INT
10774 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10775 <= HOST_BITS_PER_WIDE_INT)
10776 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10777 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10778 & INTVAL (XEXP (op0, 1)))
10779 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10780 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10781 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10785 = gen_lowpart_for_combine
10787 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10788 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10792 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10793 (eq (and (lshiftrt X) 1) 0). */
10794 if (const_op == 0 && equality_comparison_p
10795 && XEXP (op0, 1) == const1_rtx
10796 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10797 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10799 op0 = simplify_and_const_int
10801 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10802 XEXP (XEXP (op0, 0), 1)),
10803 (HOST_WIDE_INT) 1);
10804 code = (code == NE ? EQ : NE);
10810 /* If we have (compare (ashift FOO N) (const_int C)) and
10811 the high order N bits of FOO (N+1 if an inequality comparison)
10812 are known to be zero, we can do this by comparing FOO with C
10813 shifted right N bits so long as the low-order N bits of C are
10815 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10816 && INTVAL (XEXP (op0, 1)) >= 0
10817 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10818 < HOST_BITS_PER_WIDE_INT)
10820 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10821 && mode_width <= HOST_BITS_PER_WIDE_INT
10822 && (nonzero_bits (XEXP (op0, 0), mode)
10823 & ~(mask >> (INTVAL (XEXP (op0, 1))
10824 + ! equality_comparison_p))) == 0)
10826 /* We must perform a logical shift, not an arithmetic one,
10827 as we want the top N bits of C to be zero. */
10828 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10830 temp >>= INTVAL (XEXP (op0, 1));
10831 op1 = gen_int_mode (temp, mode);
10832 op0 = XEXP (op0, 0);
10836 /* If we are doing a sign bit comparison, it means we are testing
10837 a particular bit. Convert it to the appropriate AND. */
10838 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10839 && mode_width <= HOST_BITS_PER_WIDE_INT)
10841 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10844 - INTVAL (XEXP (op0, 1)))));
10845 code = (code == LT ? NE : EQ);
10849 /* If this an equality comparison with zero and we are shifting
10850 the low bit to the sign bit, we can convert this to an AND of the
10852 if (const_op == 0 && equality_comparison_p
10853 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10854 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10856 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10857 (HOST_WIDE_INT) 1);
10863 /* If this is an equality comparison with zero, we can do this
10864 as a logical shift, which might be much simpler. */
10865 if (equality_comparison_p && const_op == 0
10866 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10868 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10870 INTVAL (XEXP (op0, 1)));
10874 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10875 do the comparison in a narrower mode. */
10876 if (! unsigned_comparison_p
10877 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10878 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10879 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10880 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10881 MODE_INT, 1)) != BLKmode
10882 && (((unsigned HOST_WIDE_INT) const_op
10883 + (GET_MODE_MASK (tmode) >> 1) + 1)
10884 <= GET_MODE_MASK (tmode)))
10886 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10890 /* Likewise if OP0 is a PLUS of a sign extension with a
10891 constant, which is usually represented with the PLUS
10892 between the shifts. */
10893 if (! unsigned_comparison_p
10894 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10895 && GET_CODE (XEXP (op0, 0)) == PLUS
10896 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10897 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10898 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10899 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10900 MODE_INT, 1)) != BLKmode
10901 && (((unsigned HOST_WIDE_INT) const_op
10902 + (GET_MODE_MASK (tmode) >> 1) + 1)
10903 <= GET_MODE_MASK (tmode)))
10905 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10906 rtx add_const = XEXP (XEXP (op0, 0), 1);
10907 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10910 op0 = gen_binary (PLUS, tmode,
10911 gen_lowpart_for_combine (tmode, inner),
10916 /* ... fall through ... */
10918 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10919 the low order N bits of FOO are known to be zero, we can do this
10920 by comparing FOO with C shifted left N bits so long as no
10921 overflow occurs. */
10922 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10923 && INTVAL (XEXP (op0, 1)) >= 0
10924 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10925 && mode_width <= HOST_BITS_PER_WIDE_INT
10926 && (nonzero_bits (XEXP (op0, 0), mode)
10927 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10928 && (((unsigned HOST_WIDE_INT) const_op
10929 + (GET_CODE (op0) != LSHIFTRT
10930 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10933 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10935 /* If the shift was logical, then we must make the condition
10937 if (GET_CODE (op0) == LSHIFTRT)
10938 code = unsigned_condition (code);
10940 const_op <<= INTVAL (XEXP (op0, 1));
10941 op1 = GEN_INT (const_op);
10942 op0 = XEXP (op0, 0);
10946 /* If we are using this shift to extract just the sign bit, we
10947 can replace this with an LT or GE comparison. */
10949 && (equality_comparison_p || sign_bit_comparison_p)
10950 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10951 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10953 op0 = XEXP (op0, 0);
10954 code = (code == NE || code == GT ? LT : GE);
10966 /* Now make any compound operations involved in this comparison. Then,
10967 check for an outmost SUBREG on OP0 that is not doing anything or is
10968 paradoxical. The latter transformation must only be performed when
10969 it is known that the "extra" bits will be the same in op0 and op1 or
10970 that they don't matter. There are three cases to consider:
10972 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10973 care bits and we can assume they have any convenient value. So
10974 making the transformation is safe.
10976 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10977 In this case the upper bits of op0 are undefined. We should not make
10978 the simplification in that case as we do not know the contents of
10981 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10982 NIL. In that case we know those bits are zeros or ones. We must
10983 also be sure that they are the same as the upper bits of op1.
10985 We can never remove a SUBREG for a non-equality comparison because
10986 the sign bit is in a different place in the underlying object. */
10988 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10989 op1 = make_compound_operation (op1, SET);
10991 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10992 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
10994 && GET_CODE (SUBREG_REG (op0)) == REG
10995 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10996 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10997 && (code == NE || code == EQ))
10999 if (GET_MODE_SIZE (GET_MODE (op0))
11000 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11002 op0 = SUBREG_REG (op0);
11003 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11005 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11006 <= HOST_BITS_PER_WIDE_INT)
11007 && (nonzero_bits (SUBREG_REG (op0),
11008 GET_MODE (SUBREG_REG (op0)))
11009 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11011 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11013 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11014 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11015 op0 = SUBREG_REG (op0), op1 = tem;
11019 /* We now do the opposite procedure: Some machines don't have compare
11020 insns in all modes. If OP0's mode is an integer mode smaller than a
11021 word and we can't do a compare in that mode, see if there is a larger
11022 mode for which we can do the compare. There are a number of cases in
11023 which we can use the wider mode. */
11025 mode = GET_MODE (op0);
11026 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11027 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11028 && ! have_insn_for (COMPARE, mode))
11029 for (tmode = GET_MODE_WIDER_MODE (mode);
11031 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11032 tmode = GET_MODE_WIDER_MODE (tmode))
11033 if (have_insn_for (COMPARE, tmode))
11037 /* If the only nonzero bits in OP0 and OP1 are those in the
11038 narrower mode and this is an equality or unsigned comparison,
11039 we can use the wider mode. Similarly for sign-extended
11040 values, in which case it is true for all comparisons. */
11041 zero_extended = ((code == EQ || code == NE
11042 || code == GEU || code == GTU
11043 || code == LEU || code == LTU)
11044 && (nonzero_bits (op0, tmode)
11045 & ~GET_MODE_MASK (mode)) == 0
11046 && ((GET_CODE (op1) == CONST_INT
11047 || (nonzero_bits (op1, tmode)
11048 & ~GET_MODE_MASK (mode)) == 0)));
11051 || ((num_sign_bit_copies (op0, tmode)
11052 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11053 && (num_sign_bit_copies (op1, tmode)
11054 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11056 /* If OP0 is an AND and we don't have an AND in MODE either,
11057 make a new AND in the proper mode. */
11058 if (GET_CODE (op0) == AND
11059 && !have_insn_for (AND, mode))
11060 op0 = gen_binary (AND, tmode,
11061 gen_lowpart_for_combine (tmode,
11063 gen_lowpart_for_combine (tmode,
11066 op0 = gen_lowpart_for_combine (tmode, op0);
11067 if (zero_extended && GET_CODE (op1) == CONST_INT)
11068 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11069 op1 = gen_lowpart_for_combine (tmode, op1);
11073 /* If this is a test for negative, we can make an explicit
11074 test of the sign bit. */
11076 if (op1 == const0_rtx && (code == LT || code == GE)
11077 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11079 op0 = gen_binary (AND, tmode,
11080 gen_lowpart_for_combine (tmode, op0),
11081 GEN_INT ((HOST_WIDE_INT) 1
11082 << (GET_MODE_BITSIZE (mode) - 1)));
11083 code = (code == LT) ? NE : EQ;
11088 #ifdef CANONICALIZE_COMPARISON
11089 /* If this machine only supports a subset of valid comparisons, see if we
11090 can convert an unsupported one into a supported one. */
11091 CANONICALIZE_COMPARISON (code, op0, op1);
11100 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11101 searching backward. */
11102 static enum rtx_code
11103 combine_reversed_comparison_code (exp)
11106 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11109 if (code1 != UNKNOWN
11110 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11112 /* Otherwise try and find where the condition codes were last set and
11114 x = get_last_value (XEXP (exp, 0));
11115 if (!x || GET_CODE (x) != COMPARE)
11117 return reversed_comparison_code_parts (GET_CODE (exp),
11118 XEXP (x, 0), XEXP (x, 1), NULL);
11120 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11121 Return NULL_RTX in case we fail to do the reversal. */
11123 reversed_comparison (exp, mode, op0, op1)
11125 enum machine_mode mode;
11127 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11128 if (reversed_code == UNKNOWN)
11131 return gen_binary (reversed_code, mode, op0, op1);
11134 /* Utility function for following routine. Called when X is part of a value
11135 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11136 for each register mentioned. Similar to mention_regs in cse.c */
11139 update_table_tick (x)
11142 enum rtx_code code = GET_CODE (x);
11143 const char *fmt = GET_RTX_FORMAT (code);
11148 unsigned int regno = REGNO (x);
11149 unsigned int endregno
11150 = regno + (regno < FIRST_PSEUDO_REGISTER
11151 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11154 for (r = regno; r < endregno; r++)
11155 reg_last_set_table_tick[r] = label_tick;
11160 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11161 /* Note that we can't have an "E" in values stored; see
11162 get_last_value_validate. */
11164 update_table_tick (XEXP (x, i));
11167 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11168 are saying that the register is clobbered and we no longer know its
11169 value. If INSN is zero, don't update reg_last_set; this is only permitted
11170 with VALUE also zero and is used to invalidate the register. */
11173 record_value_for_reg (reg, insn, value)
11178 unsigned int regno = REGNO (reg);
11179 unsigned int endregno
11180 = regno + (regno < FIRST_PSEUDO_REGISTER
11181 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11184 /* If VALUE contains REG and we have a previous value for REG, substitute
11185 the previous value. */
11186 if (value && insn && reg_overlap_mentioned_p (reg, value))
11190 /* Set things up so get_last_value is allowed to see anything set up to
11192 subst_low_cuid = INSN_CUID (insn);
11193 tem = get_last_value (reg);
11195 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11196 it isn't going to be useful and will take a lot of time to process,
11197 so just use the CLOBBER. */
11201 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11202 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11203 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11204 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11205 tem = XEXP (tem, 0);
11207 value = replace_rtx (copy_rtx (value), reg, tem);
11211 /* For each register modified, show we don't know its value, that
11212 we don't know about its bitwise content, that its value has been
11213 updated, and that we don't know the location of the death of the
11215 for (i = regno; i < endregno; i++)
11218 reg_last_set[i] = insn;
11220 reg_last_set_value[i] = 0;
11221 reg_last_set_mode[i] = 0;
11222 reg_last_set_nonzero_bits[i] = 0;
11223 reg_last_set_sign_bit_copies[i] = 0;
11224 reg_last_death[i] = 0;
11227 /* Mark registers that are being referenced in this value. */
11229 update_table_tick (value);
11231 /* Now update the status of each register being set.
11232 If someone is using this register in this block, set this register
11233 to invalid since we will get confused between the two lives in this
11234 basic block. This makes using this register always invalid. In cse, we
11235 scan the table to invalidate all entries using this register, but this
11236 is too much work for us. */
11238 for (i = regno; i < endregno; i++)
11240 reg_last_set_label[i] = label_tick;
11241 if (value && reg_last_set_table_tick[i] == label_tick)
11242 reg_last_set_invalid[i] = 1;
11244 reg_last_set_invalid[i] = 0;
11247 /* The value being assigned might refer to X (like in "x++;"). In that
11248 case, we must replace it with (clobber (const_int 0)) to prevent
11250 if (value && ! get_last_value_validate (&value, insn,
11251 reg_last_set_label[regno], 0))
11253 value = copy_rtx (value);
11254 if (! get_last_value_validate (&value, insn,
11255 reg_last_set_label[regno], 1))
11259 /* For the main register being modified, update the value, the mode, the
11260 nonzero bits, and the number of sign bit copies. */
11262 reg_last_set_value[regno] = value;
11266 enum machine_mode mode = GET_MODE (reg);
11267 subst_low_cuid = INSN_CUID (insn);
11268 reg_last_set_mode[regno] = mode;
11269 if (GET_MODE_CLASS (mode) == MODE_INT
11270 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11271 mode = nonzero_bits_mode;
11272 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11273 reg_last_set_sign_bit_copies[regno]
11274 = num_sign_bit_copies (value, GET_MODE (reg));
11278 /* Called via note_stores from record_dead_and_set_regs to handle one
11279 SET or CLOBBER in an insn. DATA is the instruction in which the
11280 set is occurring. */
11283 record_dead_and_set_regs_1 (dest, setter, data)
11287 rtx record_dead_insn = (rtx) data;
11289 if (GET_CODE (dest) == SUBREG)
11290 dest = SUBREG_REG (dest);
11292 if (GET_CODE (dest) == REG)
11294 /* If we are setting the whole register, we know its value. Otherwise
11295 show that we don't know the value. We can handle SUBREG in
11297 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11298 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11299 else if (GET_CODE (setter) == SET
11300 && GET_CODE (SET_DEST (setter)) == SUBREG
11301 && SUBREG_REG (SET_DEST (setter)) == dest
11302 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11303 && subreg_lowpart_p (SET_DEST (setter)))
11304 record_value_for_reg (dest, record_dead_insn,
11305 gen_lowpart_for_combine (GET_MODE (dest),
11306 SET_SRC (setter)));
11308 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11310 else if (GET_CODE (dest) == MEM
11311 /* Ignore pushes, they clobber nothing. */
11312 && ! push_operand (dest, GET_MODE (dest)))
11313 mem_last_set = INSN_CUID (record_dead_insn);
11316 /* Update the records of when each REG was most recently set or killed
11317 for the things done by INSN. This is the last thing done in processing
11318 INSN in the combiner loop.
11320 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11321 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11322 and also the similar information mem_last_set (which insn most recently
11323 modified memory) and last_call_cuid (which insn was the most recent
11324 subroutine call). */
11327 record_dead_and_set_regs (insn)
11333 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11335 if (REG_NOTE_KIND (link) == REG_DEAD
11336 && GET_CODE (XEXP (link, 0)) == REG)
11338 unsigned int regno = REGNO (XEXP (link, 0));
11339 unsigned int endregno
11340 = regno + (regno < FIRST_PSEUDO_REGISTER
11341 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11344 for (i = regno; i < endregno; i++)
11345 reg_last_death[i] = insn;
11347 else if (REG_NOTE_KIND (link) == REG_INC)
11348 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11351 if (GET_CODE (insn) == CALL_INSN)
11353 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11354 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11356 reg_last_set_value[i] = 0;
11357 reg_last_set_mode[i] = 0;
11358 reg_last_set_nonzero_bits[i] = 0;
11359 reg_last_set_sign_bit_copies[i] = 0;
11360 reg_last_death[i] = 0;
11363 last_call_cuid = mem_last_set = INSN_CUID (insn);
11365 /* Don't bother recording what this insn does. It might set the
11366 return value register, but we can't combine into a call
11367 pattern anyway, so there's no point trying (and it may cause
11368 a crash, if e.g. we wind up asking for last_set_value of a
11369 SUBREG of the return value register). */
11373 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11376 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11377 register present in the SUBREG, so for each such SUBREG go back and
11378 adjust nonzero and sign bit information of the registers that are
11379 known to have some zero/sign bits set.
11381 This is needed because when combine blows the SUBREGs away, the
11382 information on zero/sign bits is lost and further combines can be
11383 missed because of that. */
11386 record_promoted_value (insn, subreg)
11391 unsigned int regno = REGNO (SUBREG_REG (subreg));
11392 enum machine_mode mode = GET_MODE (subreg);
11394 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11397 for (links = LOG_LINKS (insn); links;)
11399 insn = XEXP (links, 0);
11400 set = single_set (insn);
11402 if (! set || GET_CODE (SET_DEST (set)) != REG
11403 || REGNO (SET_DEST (set)) != regno
11404 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11406 links = XEXP (links, 1);
11410 if (reg_last_set[regno] == insn)
11412 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11413 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11416 if (GET_CODE (SET_SRC (set)) == REG)
11418 regno = REGNO (SET_SRC (set));
11419 links = LOG_LINKS (insn);
11426 /* Scan X for promoted SUBREGs. For each one found,
11427 note what it implies to the registers used in it. */
11430 check_promoted_subreg (insn, x)
11434 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11435 && GET_CODE (SUBREG_REG (x)) == REG)
11436 record_promoted_value (insn, x);
11439 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11442 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11446 check_promoted_subreg (insn, XEXP (x, i));
11450 if (XVEC (x, i) != 0)
11451 for (j = 0; j < XVECLEN (x, i); j++)
11452 check_promoted_subreg (insn, XVECEXP (x, i, j));
11458 /* Utility routine for the following function. Verify that all the registers
11459 mentioned in *LOC are valid when *LOC was part of a value set when
11460 label_tick == TICK. Return 0 if some are not.
11462 If REPLACE is non-zero, replace the invalid reference with
11463 (clobber (const_int 0)) and return 1. This replacement is useful because
11464 we often can get useful information about the form of a value (e.g., if
11465 it was produced by a shift that always produces -1 or 0) even though
11466 we don't know exactly what registers it was produced from. */
11469 get_last_value_validate (loc, insn, tick, replace)
11476 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11477 int len = GET_RTX_LENGTH (GET_CODE (x));
11480 if (GET_CODE (x) == REG)
11482 unsigned int regno = REGNO (x);
11483 unsigned int endregno
11484 = regno + (regno < FIRST_PSEUDO_REGISTER
11485 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11488 for (j = regno; j < endregno; j++)
11489 if (reg_last_set_invalid[j]
11490 /* If this is a pseudo-register that was only set once and not
11491 live at the beginning of the function, it is always valid. */
11492 || (! (regno >= FIRST_PSEUDO_REGISTER
11493 && REG_N_SETS (regno) == 1
11494 && (! REGNO_REG_SET_P
11495 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11496 && reg_last_set_label[j] > tick))
11499 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11505 /* If this is a memory reference, make sure that there were
11506 no stores after it that might have clobbered the value. We don't
11507 have alias info, so we assume any store invalidates it. */
11508 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11509 && INSN_CUID (insn) <= mem_last_set)
11512 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11516 for (i = 0; i < len; i++)
11518 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11519 /* Don't bother with these. They shouldn't occur anyway. */
11523 /* If we haven't found a reason for it to be invalid, it is valid. */
11527 /* Get the last value assigned to X, if known. Some registers
11528 in the value may be replaced with (clobber (const_int 0)) if their value
11529 is known longer known reliably. */
11535 unsigned int regno;
11538 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11539 then convert it to the desired mode. If this is a paradoxical SUBREG,
11540 we cannot predict what values the "extra" bits might have. */
11541 if (GET_CODE (x) == SUBREG
11542 && subreg_lowpart_p (x)
11543 && (GET_MODE_SIZE (GET_MODE (x))
11544 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11545 && (value = get_last_value (SUBREG_REG (x))) != 0)
11546 return gen_lowpart_for_combine (GET_MODE (x), value);
11548 if (GET_CODE (x) != REG)
11552 value = reg_last_set_value[regno];
11554 /* If we don't have a value, or if it isn't for this basic block and
11555 it's either a hard register, set more than once, or it's a live
11556 at the beginning of the function, return 0.
11558 Because if it's not live at the beginning of the function then the reg
11559 is always set before being used (is never used without being set).
11560 And, if it's set only once, and it's always set before use, then all
11561 uses must have the same last value, even if it's not from this basic
11565 || (reg_last_set_label[regno] != label_tick
11566 && (regno < FIRST_PSEUDO_REGISTER
11567 || REG_N_SETS (regno) != 1
11568 || (REGNO_REG_SET_P
11569 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11572 /* If the value was set in a later insn than the ones we are processing,
11573 we can't use it even if the register was only set once. */
11574 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11577 /* If the value has all its registers valid, return it. */
11578 if (get_last_value_validate (&value, reg_last_set[regno],
11579 reg_last_set_label[regno], 0))
11582 /* Otherwise, make a copy and replace any invalid register with
11583 (clobber (const_int 0)). If that fails for some reason, return 0. */
11585 value = copy_rtx (value);
11586 if (get_last_value_validate (&value, reg_last_set[regno],
11587 reg_last_set_label[regno], 1))
11593 /* Return nonzero if expression X refers to a REG or to memory
11594 that is set in an instruction more recent than FROM_CUID. */
11597 use_crosses_set_p (x, from_cuid)
11603 enum rtx_code code = GET_CODE (x);
11607 unsigned int regno = REGNO (x);
11608 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11609 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11611 #ifdef PUSH_ROUNDING
11612 /* Don't allow uses of the stack pointer to be moved,
11613 because we don't know whether the move crosses a push insn. */
11614 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11617 for (; regno < endreg; regno++)
11618 if (reg_last_set[regno]
11619 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11624 if (code == MEM && mem_last_set > from_cuid)
11627 fmt = GET_RTX_FORMAT (code);
11629 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11634 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11635 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11638 else if (fmt[i] == 'e'
11639 && use_crosses_set_p (XEXP (x, i), from_cuid))
11645 /* Define three variables used for communication between the following
11648 static unsigned int reg_dead_regno, reg_dead_endregno;
11649 static int reg_dead_flag;
11651 /* Function called via note_stores from reg_dead_at_p.
11653 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11654 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11657 reg_dead_at_p_1 (dest, x, data)
11660 void *data ATTRIBUTE_UNUSED;
11662 unsigned int regno, endregno;
11664 if (GET_CODE (dest) != REG)
11667 regno = REGNO (dest);
11668 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11669 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11671 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11672 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11675 /* Return non-zero if REG is known to be dead at INSN.
11677 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11678 referencing REG, it is dead. If we hit a SET referencing REG, it is
11679 live. Otherwise, see if it is live or dead at the start of the basic
11680 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11681 must be assumed to be always live. */
11684 reg_dead_at_p (reg, insn)
11691 /* Set variables for reg_dead_at_p_1. */
11692 reg_dead_regno = REGNO (reg);
11693 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11694 ? HARD_REGNO_NREGS (reg_dead_regno,
11700 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11701 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11703 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11704 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11708 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11709 beginning of function. */
11710 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11711 insn = prev_nonnote_insn (insn))
11713 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11715 return reg_dead_flag == 1 ? 1 : 0;
11717 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11721 /* Get the basic block number that we were in. */
11726 for (block = 0; block < n_basic_blocks; block++)
11727 if (insn == BLOCK_HEAD (block))
11730 if (block == n_basic_blocks)
11734 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11735 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11741 /* Note hard registers in X that are used. This code is similar to
11742 that in flow.c, but much simpler since we don't care about pseudos. */
11745 mark_used_regs_combine (x)
11748 RTX_CODE code = GET_CODE (x);
11749 unsigned int regno;
11762 case ADDR_DIFF_VEC:
11765 /* CC0 must die in the insn after it is set, so we don't need to take
11766 special note of it here. */
11772 /* If we are clobbering a MEM, mark any hard registers inside the
11773 address as used. */
11774 if (GET_CODE (XEXP (x, 0)) == MEM)
11775 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11780 /* A hard reg in a wide mode may really be multiple registers.
11781 If so, mark all of them just like the first. */
11782 if (regno < FIRST_PSEUDO_REGISTER)
11784 unsigned int endregno, r;
11786 /* None of this applies to the stack, frame or arg pointers */
11787 if (regno == STACK_POINTER_REGNUM
11788 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11789 || regno == HARD_FRAME_POINTER_REGNUM
11791 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11792 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11794 || regno == FRAME_POINTER_REGNUM)
11797 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11798 for (r = regno; r < endregno; r++)
11799 SET_HARD_REG_BIT (newpat_used_regs, r);
11805 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11807 rtx testreg = SET_DEST (x);
11809 while (GET_CODE (testreg) == SUBREG
11810 || GET_CODE (testreg) == ZERO_EXTRACT
11811 || GET_CODE (testreg) == SIGN_EXTRACT
11812 || GET_CODE (testreg) == STRICT_LOW_PART)
11813 testreg = XEXP (testreg, 0);
11815 if (GET_CODE (testreg) == MEM)
11816 mark_used_regs_combine (XEXP (testreg, 0));
11818 mark_used_regs_combine (SET_SRC (x));
11826 /* Recursively scan the operands of this expression. */
11829 const char *fmt = GET_RTX_FORMAT (code);
11831 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11834 mark_used_regs_combine (XEXP (x, i));
11835 else if (fmt[i] == 'E')
11839 for (j = 0; j < XVECLEN (x, i); j++)
11840 mark_used_regs_combine (XVECEXP (x, i, j));
11846 /* Remove register number REGNO from the dead registers list of INSN.
11848 Return the note used to record the death, if there was one. */
11851 remove_death (regno, insn)
11852 unsigned int regno;
11855 rtx note = find_regno_note (insn, REG_DEAD, regno);
11859 REG_N_DEATHS (regno)--;
11860 remove_note (insn, note);
11866 /* For each register (hardware or pseudo) used within expression X, if its
11867 death is in an instruction with cuid between FROM_CUID (inclusive) and
11868 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11869 list headed by PNOTES.
11871 That said, don't move registers killed by maybe_kill_insn.
11873 This is done when X is being merged by combination into TO_INSN. These
11874 notes will then be distributed as needed. */
11877 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11879 rtx maybe_kill_insn;
11886 enum rtx_code code = GET_CODE (x);
11890 unsigned int regno = REGNO (x);
11891 rtx where_dead = reg_last_death[regno];
11892 rtx before_dead, after_dead;
11894 /* Don't move the register if it gets killed in between from and to */
11895 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11896 && ! reg_referenced_p (x, maybe_kill_insn))
11899 /* WHERE_DEAD could be a USE insn made by combine, so first we
11900 make sure that we have insns with valid INSN_CUID values. */
11901 before_dead = where_dead;
11902 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11903 before_dead = PREV_INSN (before_dead);
11905 after_dead = where_dead;
11906 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11907 after_dead = NEXT_INSN (after_dead);
11909 if (before_dead && after_dead
11910 && INSN_CUID (before_dead) >= from_cuid
11911 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11912 || (where_dead != after_dead
11913 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11915 rtx note = remove_death (regno, where_dead);
11917 /* It is possible for the call above to return 0. This can occur
11918 when reg_last_death points to I2 or I1 that we combined with.
11919 In that case make a new note.
11921 We must also check for the case where X is a hard register
11922 and NOTE is a death note for a range of hard registers
11923 including X. In that case, we must put REG_DEAD notes for
11924 the remaining registers in place of NOTE. */
11926 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11927 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11928 > GET_MODE_SIZE (GET_MODE (x))))
11930 unsigned int deadregno = REGNO (XEXP (note, 0));
11931 unsigned int deadend
11932 = (deadregno + HARD_REGNO_NREGS (deadregno,
11933 GET_MODE (XEXP (note, 0))));
11934 unsigned int ourend
11935 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11938 for (i = deadregno; i < deadend; i++)
11939 if (i < regno || i >= ourend)
11940 REG_NOTES (where_dead)
11941 = gen_rtx_EXPR_LIST (REG_DEAD,
11942 gen_rtx_REG (reg_raw_mode[i], i),
11943 REG_NOTES (where_dead));
11946 /* If we didn't find any note, or if we found a REG_DEAD note that
11947 covers only part of the given reg, and we have a multi-reg hard
11948 register, then to be safe we must check for REG_DEAD notes
11949 for each register other than the first. They could have
11950 their own REG_DEAD notes lying around. */
11951 else if ((note == 0
11953 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11954 < GET_MODE_SIZE (GET_MODE (x)))))
11955 && regno < FIRST_PSEUDO_REGISTER
11956 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11958 unsigned int ourend
11959 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11960 unsigned int i, offset;
11964 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11968 for (i = regno + offset; i < ourend; i++)
11969 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11970 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11973 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11975 XEXP (note, 1) = *pnotes;
11979 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11981 REG_N_DEATHS (regno)++;
11987 else if (GET_CODE (x) == SET)
11989 rtx dest = SET_DEST (x);
11991 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11993 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11994 that accesses one word of a multi-word item, some
11995 piece of everything register in the expression is used by
11996 this insn, so remove any old death. */
11997 /* ??? So why do we test for equality of the sizes? */
11999 if (GET_CODE (dest) == ZERO_EXTRACT
12000 || GET_CODE (dest) == STRICT_LOW_PART
12001 || (GET_CODE (dest) == SUBREG
12002 && (((GET_MODE_SIZE (GET_MODE (dest))
12003 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12004 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12005 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12007 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12011 /* If this is some other SUBREG, we know it replaces the entire
12012 value, so use that as the destination. */
12013 if (GET_CODE (dest) == SUBREG)
12014 dest = SUBREG_REG (dest);
12016 /* If this is a MEM, adjust deaths of anything used in the address.
12017 For a REG (the only other possibility), the entire value is
12018 being replaced so the old value is not used in this insn. */
12020 if (GET_CODE (dest) == MEM)
12021 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12026 else if (GET_CODE (x) == CLOBBER)
12029 len = GET_RTX_LENGTH (code);
12030 fmt = GET_RTX_FORMAT (code);
12032 for (i = 0; i < len; i++)
12037 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12038 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12041 else if (fmt[i] == 'e')
12042 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12046 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12047 pattern of an insn. X must be a REG. */
12050 reg_bitfield_target_p (x, body)
12056 if (GET_CODE (body) == SET)
12058 rtx dest = SET_DEST (body);
12060 unsigned int regno, tregno, endregno, endtregno;
12062 if (GET_CODE (dest) == ZERO_EXTRACT)
12063 target = XEXP (dest, 0);
12064 else if (GET_CODE (dest) == STRICT_LOW_PART)
12065 target = SUBREG_REG (XEXP (dest, 0));
12069 if (GET_CODE (target) == SUBREG)
12070 target = SUBREG_REG (target);
12072 if (GET_CODE (target) != REG)
12075 tregno = REGNO (target), regno = REGNO (x);
12076 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12077 return target == x;
12079 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12080 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12082 return endregno > tregno && regno < endtregno;
12085 else if (GET_CODE (body) == PARALLEL)
12086 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12087 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12093 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12094 as appropriate. I3 and I2 are the insns resulting from the combination
12095 insns including FROM (I2 may be zero).
12097 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12098 not need REG_DEAD notes because they are being substituted for. This
12099 saves searching in the most common cases.
12101 Each note in the list is either ignored or placed on some insns, depending
12102 on the type of note. */
12105 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12109 rtx elim_i2, elim_i1;
12111 rtx note, next_note;
12114 for (note = notes; note; note = next_note)
12116 rtx place = 0, place2 = 0;
12118 /* If this NOTE references a pseudo register, ensure it references
12119 the latest copy of that register. */
12120 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12121 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12122 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12124 next_note = XEXP (note, 1);
12125 switch (REG_NOTE_KIND (note))
12129 case REG_EXEC_COUNT:
12130 /* Doesn't matter much where we put this, as long as it's somewhere.
12131 It is preferable to keep these notes on branches, which is most
12132 likely to be i3. */
12136 case REG_VTABLE_REF:
12137 /* ??? Should remain with *a particular* memory load. Given the
12138 nature of vtable data, the last insn seems relatively safe. */
12142 case REG_NON_LOCAL_GOTO:
12143 if (GET_CODE (i3) == JUMP_INSN)
12145 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12151 case REG_EH_REGION:
12152 /* These notes must remain with the call or trapping instruction. */
12153 if (GET_CODE (i3) == CALL_INSN)
12155 else if (i2 && GET_CODE (i2) == CALL_INSN)
12157 else if (flag_non_call_exceptions)
12159 if (may_trap_p (i3))
12161 else if (i2 && may_trap_p (i2))
12163 /* ??? Otherwise assume we've combined things such that we
12164 can now prove that the instructions can't trap. Drop the
12165 note in this case. */
12173 /* These notes must remain with the call. It should not be
12174 possible for both I2 and I3 to be a call. */
12175 if (GET_CODE (i3) == CALL_INSN)
12177 else if (i2 && GET_CODE (i2) == CALL_INSN)
12184 /* Any clobbers for i3 may still exist, and so we must process
12185 REG_UNUSED notes from that insn.
12187 Any clobbers from i2 or i1 can only exist if they were added by
12188 recog_for_combine. In that case, recog_for_combine created the
12189 necessary REG_UNUSED notes. Trying to keep any original
12190 REG_UNUSED notes from these insns can cause incorrect output
12191 if it is for the same register as the original i3 dest.
12192 In that case, we will notice that the register is set in i3,
12193 and then add a REG_UNUSED note for the destination of i3, which
12194 is wrong. However, it is possible to have REG_UNUSED notes from
12195 i2 or i1 for register which were both used and clobbered, so
12196 we keep notes from i2 or i1 if they will turn into REG_DEAD
12199 /* If this register is set or clobbered in I3, put the note there
12200 unless there is one already. */
12201 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12203 if (from_insn != i3)
12206 if (! (GET_CODE (XEXP (note, 0)) == REG
12207 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12208 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12211 /* Otherwise, if this register is used by I3, then this register
12212 now dies here, so we must put a REG_DEAD note here unless there
12214 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12215 && ! (GET_CODE (XEXP (note, 0)) == REG
12216 ? find_regno_note (i3, REG_DEAD,
12217 REGNO (XEXP (note, 0)))
12218 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12220 PUT_REG_NOTE_KIND (note, REG_DEAD);
12228 /* These notes say something about results of an insn. We can
12229 only support them if they used to be on I3 in which case they
12230 remain on I3. Otherwise they are ignored.
12232 If the note refers to an expression that is not a constant, we
12233 must also ignore the note since we cannot tell whether the
12234 equivalence is still true. It might be possible to do
12235 slightly better than this (we only have a problem if I2DEST
12236 or I1DEST is present in the expression), but it doesn't
12237 seem worth the trouble. */
12239 if (from_insn == i3
12240 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12245 case REG_NO_CONFLICT:
12246 /* These notes say something about how a register is used. They must
12247 be present on any use of the register in I2 or I3. */
12248 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12251 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12261 /* This can show up in several ways -- either directly in the
12262 pattern, or hidden off in the constant pool with (or without?)
12263 a REG_EQUAL note. */
12264 /* ??? Ignore the without-reg_equal-note problem for now. */
12265 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12266 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12267 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12268 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12272 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12273 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12274 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12275 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12283 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12284 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12285 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12287 if (JUMP_LABEL (place) != XEXP (note, 0))
12289 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12290 LABEL_NUSES (JUMP_LABEL (place))--;
12293 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12295 if (JUMP_LABEL (place2) != XEXP (note, 0))
12297 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12298 LABEL_NUSES (JUMP_LABEL (place2))--;
12305 /* These notes say something about the value of a register prior
12306 to the execution of an insn. It is too much trouble to see
12307 if the note is still correct in all situations. It is better
12308 to simply delete it. */
12312 /* If the insn previously containing this note still exists,
12313 put it back where it was. Otherwise move it to the previous
12314 insn. Adjust the corresponding REG_LIBCALL note. */
12315 if (GET_CODE (from_insn) != NOTE)
12319 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12320 place = prev_real_insn (from_insn);
12322 XEXP (tem, 0) = place;
12323 /* If we're deleting the last remaining instruction of a
12324 libcall sequence, don't add the notes. */
12325 else if (XEXP (note, 0) == from_insn)
12331 /* This is handled similarly to REG_RETVAL. */
12332 if (GET_CODE (from_insn) != NOTE)
12336 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12337 place = next_real_insn (from_insn);
12339 XEXP (tem, 0) = place;
12340 /* If we're deleting the last remaining instruction of a
12341 libcall sequence, don't add the notes. */
12342 else if (XEXP (note, 0) == from_insn)
12348 /* If the register is used as an input in I3, it dies there.
12349 Similarly for I2, if it is non-zero and adjacent to I3.
12351 If the register is not used as an input in either I3 or I2
12352 and it is not one of the registers we were supposed to eliminate,
12353 there are two possibilities. We might have a non-adjacent I2
12354 or we might have somehow eliminated an additional register
12355 from a computation. For example, we might have had A & B where
12356 we discover that B will always be zero. In this case we will
12357 eliminate the reference to A.
12359 In both cases, we must search to see if we can find a previous
12360 use of A and put the death note there. */
12363 && GET_CODE (from_insn) == CALL_INSN
12364 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12366 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12368 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12369 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12372 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12373 || rtx_equal_p (XEXP (note, 0), elim_i1))
12378 basic_block bb = BASIC_BLOCK (this_basic_block);
12380 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12382 if (! INSN_P (tem))
12384 if (tem == bb->head)
12389 /* If the register is being set at TEM, see if that is all
12390 TEM is doing. If so, delete TEM. Otherwise, make this
12391 into a REG_UNUSED note instead. */
12392 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12394 rtx set = single_set (tem);
12395 rtx inner_dest = 0;
12397 rtx cc0_setter = NULL_RTX;
12401 for (inner_dest = SET_DEST (set);
12402 (GET_CODE (inner_dest) == STRICT_LOW_PART
12403 || GET_CODE (inner_dest) == SUBREG
12404 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12405 inner_dest = XEXP (inner_dest, 0))
12408 /* Verify that it was the set, and not a clobber that
12409 modified the register.
12411 CC0 targets must be careful to maintain setter/user
12412 pairs. If we cannot delete the setter due to side
12413 effects, mark the user with an UNUSED note instead
12416 if (set != 0 && ! side_effects_p (SET_SRC (set))
12417 && rtx_equal_p (XEXP (note, 0), inner_dest)
12419 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12420 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12421 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12425 /* Move the notes and links of TEM elsewhere.
12426 This might delete other dead insns recursively.
12427 First set the pattern to something that won't use
12430 PATTERN (tem) = pc_rtx;
12432 distribute_notes (REG_NOTES (tem), tem, tem,
12433 NULL_RTX, NULL_RTX, NULL_RTX);
12434 distribute_links (LOG_LINKS (tem));
12436 PUT_CODE (tem, NOTE);
12437 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12438 NOTE_SOURCE_FILE (tem) = 0;
12441 /* Delete the setter too. */
12444 PATTERN (cc0_setter) = pc_rtx;
12446 distribute_notes (REG_NOTES (cc0_setter),
12447 cc0_setter, cc0_setter,
12448 NULL_RTX, NULL_RTX, NULL_RTX);
12449 distribute_links (LOG_LINKS (cc0_setter));
12451 PUT_CODE (cc0_setter, NOTE);
12452 NOTE_LINE_NUMBER (cc0_setter)
12453 = NOTE_INSN_DELETED;
12454 NOTE_SOURCE_FILE (cc0_setter) = 0;
12458 /* If the register is both set and used here, put the
12459 REG_DEAD note here, but place a REG_UNUSED note
12460 here too unless there already is one. */
12461 else if (reg_referenced_p (XEXP (note, 0),
12466 if (! find_regno_note (tem, REG_UNUSED,
12467 REGNO (XEXP (note, 0))))
12469 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12474 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12476 /* If there isn't already a REG_UNUSED note, put one
12478 if (! find_regno_note (tem, REG_UNUSED,
12479 REGNO (XEXP (note, 0))))
12484 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12485 || (GET_CODE (tem) == CALL_INSN
12486 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12490 /* If we are doing a 3->2 combination, and we have a
12491 register which formerly died in i3 and was not used
12492 by i2, which now no longer dies in i3 and is used in
12493 i2 but does not die in i2, and place is between i2
12494 and i3, then we may need to move a link from place to
12496 if (i2 && INSN_UID (place) <= max_uid_cuid
12497 && INSN_CUID (place) > INSN_CUID (i2)
12499 && INSN_CUID (from_insn) > INSN_CUID (i2)
12500 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12502 rtx links = LOG_LINKS (place);
12503 LOG_LINKS (place) = 0;
12504 distribute_links (links);
12509 if (tem == bb->head)
12513 /* We haven't found an insn for the death note and it
12514 is still a REG_DEAD note, but we have hit the beginning
12515 of the block. If the existing life info says the reg
12516 was dead, there's nothing left to do. Otherwise, we'll
12517 need to do a global life update after combine. */
12518 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12519 && REGNO_REG_SET_P (bb->global_live_at_start,
12520 REGNO (XEXP (note, 0))))
12522 SET_BIT (refresh_blocks, this_basic_block);
12527 /* If the register is set or already dead at PLACE, we needn't do
12528 anything with this note if it is still a REG_DEAD note.
12529 We can here if it is set at all, not if is it totally replace,
12530 which is what `dead_or_set_p' checks, so also check for it being
12533 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12535 unsigned int regno = REGNO (XEXP (note, 0));
12537 /* Similarly, if the instruction on which we want to place
12538 the note is a noop, we'll need do a global live update
12539 after we remove them in delete_noop_moves. */
12540 if (noop_move_p (place))
12542 SET_BIT (refresh_blocks, this_basic_block);
12546 if (dead_or_set_p (place, XEXP (note, 0))
12547 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12549 /* Unless the register previously died in PLACE, clear
12550 reg_last_death. [I no longer understand why this is
12552 if (reg_last_death[regno] != place)
12553 reg_last_death[regno] = 0;
12557 reg_last_death[regno] = place;
12559 /* If this is a death note for a hard reg that is occupying
12560 multiple registers, ensure that we are still using all
12561 parts of the object. If we find a piece of the object
12562 that is unused, we must arrange for an appropriate REG_DEAD
12563 note to be added for it. However, we can't just emit a USE
12564 and tag the note to it, since the register might actually
12565 be dead; so we recourse, and the recursive call then finds
12566 the previous insn that used this register. */
12568 if (place && regno < FIRST_PSEUDO_REGISTER
12569 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12571 unsigned int endregno
12572 = regno + HARD_REGNO_NREGS (regno,
12573 GET_MODE (XEXP (note, 0)));
12577 for (i = regno; i < endregno; i++)
12578 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12579 && ! find_regno_fusage (place, USE, i))
12580 || dead_or_set_regno_p (place, i))
12585 /* Put only REG_DEAD notes for pieces that are
12586 not already dead or set. */
12588 for (i = regno; i < endregno;
12589 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12591 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12592 basic_block bb = BASIC_BLOCK (this_basic_block);
12594 if (! dead_or_set_p (place, piece)
12595 && ! reg_bitfield_target_p (piece,
12599 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12601 distribute_notes (new_note, place, place,
12602 NULL_RTX, NULL_RTX, NULL_RTX);
12604 else if (! refers_to_regno_p (i, i + 1,
12605 PATTERN (place), 0)
12606 && ! find_regno_fusage (place, USE, i))
12607 for (tem = PREV_INSN (place); ;
12608 tem = PREV_INSN (tem))
12610 if (! INSN_P (tem))
12612 if (tem == bb->head)
12614 SET_BIT (refresh_blocks,
12621 if (dead_or_set_p (tem, piece)
12622 || reg_bitfield_target_p (piece,
12626 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12641 /* Any other notes should not be present at this point in the
12648 XEXP (note, 1) = REG_NOTES (place);
12649 REG_NOTES (place) = note;
12651 else if ((REG_NOTE_KIND (note) == REG_DEAD
12652 || REG_NOTE_KIND (note) == REG_UNUSED)
12653 && GET_CODE (XEXP (note, 0)) == REG)
12654 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12658 if ((REG_NOTE_KIND (note) == REG_DEAD
12659 || REG_NOTE_KIND (note) == REG_UNUSED)
12660 && GET_CODE (XEXP (note, 0)) == REG)
12661 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12663 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12664 REG_NOTE_KIND (note),
12666 REG_NOTES (place2));
12671 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12672 I3, I2, and I1 to new locations. This is also called in one case to
12673 add a link pointing at I3 when I3's destination is changed. */
12676 distribute_links (links)
12679 rtx link, next_link;
12681 for (link = links; link; link = next_link)
12687 next_link = XEXP (link, 1);
12689 /* If the insn that this link points to is a NOTE or isn't a single
12690 set, ignore it. In the latter case, it isn't clear what we
12691 can do other than ignore the link, since we can't tell which
12692 register it was for. Such links wouldn't be used by combine
12695 It is not possible for the destination of the target of the link to
12696 have been changed by combine. The only potential of this is if we
12697 replace I3, I2, and I1 by I3 and I2. But in that case the
12698 destination of I2 also remains unchanged. */
12700 if (GET_CODE (XEXP (link, 0)) == NOTE
12701 || (set = single_set (XEXP (link, 0))) == 0)
12704 reg = SET_DEST (set);
12705 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12706 || GET_CODE (reg) == SIGN_EXTRACT
12707 || GET_CODE (reg) == STRICT_LOW_PART)
12708 reg = XEXP (reg, 0);
12710 /* A LOG_LINK is defined as being placed on the first insn that uses
12711 a register and points to the insn that sets the register. Start
12712 searching at the next insn after the target of the link and stop
12713 when we reach a set of the register or the end of the basic block.
12715 Note that this correctly handles the link that used to point from
12716 I3 to I2. Also note that not much searching is typically done here
12717 since most links don't point very far away. */
12719 for (insn = NEXT_INSN (XEXP (link, 0));
12720 (insn && (this_basic_block == n_basic_blocks - 1
12721 || BLOCK_HEAD (this_basic_block + 1) != insn));
12722 insn = NEXT_INSN (insn))
12723 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12725 if (reg_referenced_p (reg, PATTERN (insn)))
12729 else if (GET_CODE (insn) == CALL_INSN
12730 && find_reg_fusage (insn, USE, reg))
12736 /* If we found a place to put the link, place it there unless there
12737 is already a link to the same insn as LINK at that point. */
12743 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12744 if (XEXP (link2, 0) == XEXP (link, 0))
12749 XEXP (link, 1) = LOG_LINKS (place);
12750 LOG_LINKS (place) = link;
12752 /* Set added_links_insn to the earliest insn we added a
12754 if (added_links_insn == 0
12755 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12756 added_links_insn = place;
12762 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12768 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12769 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12770 insn = NEXT_INSN (insn);
12772 if (INSN_UID (insn) > max_uid_cuid)
12775 return INSN_CUID (insn);
12779 dump_combine_stats (file)
12784 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12785 combine_attempts, combine_merges, combine_extras, combine_successes);
12789 dump_combine_total_stats (file)
12794 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12795 total_attempts, total_merges, total_extras, total_successes);
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