1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx, bool);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
778 rtx newi2pat, rtx newotherpat)
780 int i0_cost, i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
793 i0_cost = INSN_COST (i0);
794 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
795 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
799 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
800 ? i1_cost + i2_cost + i3_cost : 0);
806 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
807 i1_cost = i0_cost = 0;
810 /* Calculate the replacement insn_rtx_costs. */
811 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
814 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
815 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
816 ? new_i2_cost + new_i3_cost : 0;
820 new_cost = new_i3_cost;
824 if (undobuf.other_insn)
826 int old_other_cost, new_other_cost;
828 old_other_cost = INSN_COST (undobuf.other_insn);
829 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
830 if (old_other_cost > 0 && new_other_cost > 0)
832 old_cost += old_other_cost;
833 new_cost += new_other_cost;
839 /* Disallow this recombination if both new_cost and old_cost are
840 greater than zero, and new_cost is greater than old cost. */
842 && new_cost > old_cost)
849 "rejecting combination of insns %d, %d, %d and %d\n",
850 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
852 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
853 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
858 "rejecting combination of insns %d, %d and %d\n",
859 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
860 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
861 i1_cost, i2_cost, i3_cost, old_cost);
866 "rejecting combination of insns %d and %d\n",
867 INSN_UID (i2), INSN_UID (i3));
868 fprintf (dump_file, "original costs %d + %d = %d\n",
869 i2_cost, i3_cost, old_cost);
874 fprintf (dump_file, "replacement costs %d + %d = %d\n",
875 new_i2_cost, new_i3_cost, new_cost);
878 fprintf (dump_file, "replacement cost %d\n", new_cost);
884 /* Update the uid_insn_cost array with the replacement costs. */
885 INSN_COST (i2) = new_i2_cost;
886 INSN_COST (i3) = new_i3_cost;
894 /* Delete any insns that copy a register to itself. */
897 delete_noop_moves (void)
904 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
906 next = NEXT_INSN (insn);
907 if (INSN_P (insn) && noop_move_p (insn))
910 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
912 delete_insn_and_edges (insn);
919 /* Fill in log links field for all insns. */
922 create_log_links (void)
926 df_ref *def_vec, *use_vec;
928 next_use = XCNEWVEC (rtx, max_reg_num ());
930 /* Pass through each block from the end, recording the uses of each
931 register and establishing log links when def is encountered.
932 Note that we do not clear next_use array in order to save time,
933 so we have to test whether the use is in the same basic block as def.
935 There are a few cases below when we do not consider the definition or
936 usage -- these are taken from original flow.c did. Don't ask me why it is
937 done this way; I don't know and if it works, I don't want to know. */
941 FOR_BB_INSNS_REVERSE (bb, insn)
943 if (!NONDEBUG_INSN_P (insn))
946 /* Log links are created only once. */
947 gcc_assert (!LOG_LINKS (insn));
949 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
951 df_ref def = *def_vec;
952 int regno = DF_REF_REGNO (def);
955 if (!next_use[regno])
958 /* Do not consider if it is pre/post modification in MEM. */
959 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
962 /* Do not make the log link for frame pointer. */
963 if ((regno == FRAME_POINTER_REGNUM
964 && (! reload_completed || frame_pointer_needed))
965 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
966 || (regno == HARD_FRAME_POINTER_REGNUM
967 && (! reload_completed || frame_pointer_needed))
969 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
970 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
975 use_insn = next_use[regno];
976 if (BLOCK_FOR_INSN (use_insn) == bb)
980 We don't build a LOG_LINK for hard registers contained
981 in ASM_OPERANDs. If these registers get replaced,
982 we might wind up changing the semantics of the insn,
983 even if reload can make what appear to be valid
984 assignments later. */
985 if (regno >= FIRST_PSEUDO_REGISTER
986 || asm_noperands (PATTERN (use_insn)) < 0)
988 /* Don't add duplicate links between instructions. */
990 for (links = LOG_LINKS (use_insn); links;
991 links = XEXP (links, 1))
992 if (insn == XEXP (links, 0))
996 LOG_LINKS (use_insn) =
997 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
1000 next_use[regno] = NULL_RTX;
1003 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1005 df_ref use = *use_vec;
1006 int regno = DF_REF_REGNO (use);
1008 /* Do not consider the usage of the stack pointer
1009 by function call. */
1010 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1013 next_use[regno] = insn;
1021 /* Clear LOG_LINKS fields of insns. */
1024 clear_log_links (void)
1028 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1030 free_INSN_LIST_list (&LOG_LINKS (insn));
1033 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1034 true if we found a LOG_LINK that proves that A feeds B. This only works
1035 if there are no instructions between A and B which could have a link
1036 depending on A, since in that case we would not record a link for B. */
1039 insn_a_feeds_b (rtx a, rtx b)
1042 for (links = LOG_LINKS (b); links; links = XEXP (links, 1))
1043 if (XEXP (links, 0) == a)
1048 /* Main entry point for combiner. F is the first insn of the function.
1049 NREGS is the first unused pseudo-reg number.
1051 Return nonzero if the combiner has turned an indirect jump
1052 instruction into a direct jump. */
1054 combine_instructions (rtx f, unsigned int nregs)
1060 rtx links, nextlinks;
1062 basic_block last_bb;
1064 int new_direct_jump_p = 0;
1066 for (first = f; first && !INSN_P (first); )
1067 first = NEXT_INSN (first);
1071 combine_attempts = 0;
1074 combine_successes = 0;
1076 rtl_hooks = combine_rtl_hooks;
1078 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1080 init_recog_no_volatile ();
1082 /* Allocate array for insn info. */
1083 max_uid_known = get_max_uid ();
1084 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1085 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1087 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1089 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1090 problems when, for example, we have j <<= 1 in a loop. */
1092 nonzero_sign_valid = 0;
1093 label_tick = label_tick_ebb_start = 1;
1095 /* Scan all SETs and see if we can deduce anything about what
1096 bits are known to be zero for some registers and how many copies
1097 of the sign bit are known to exist for those registers.
1099 Also set any known values so that we can use it while searching
1100 for what bits are known to be set. */
1102 setup_incoming_promotions (first);
1103 /* Allow the entry block and the first block to fall into the same EBB.
1104 Conceptually the incoming promotions are assigned to the entry block. */
1105 last_bb = ENTRY_BLOCK_PTR;
1107 create_log_links ();
1108 FOR_EACH_BB (this_basic_block)
1110 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1115 if (!single_pred_p (this_basic_block)
1116 || single_pred (this_basic_block) != last_bb)
1117 label_tick_ebb_start = label_tick;
1118 last_bb = this_basic_block;
1120 FOR_BB_INSNS (this_basic_block, insn)
1121 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1123 subst_low_luid = DF_INSN_LUID (insn);
1126 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1128 record_dead_and_set_regs (insn);
1131 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1132 if (REG_NOTE_KIND (links) == REG_INC)
1133 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1137 /* Record the current insn_rtx_cost of this instruction. */
1138 if (NONJUMP_INSN_P (insn))
1139 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1140 optimize_this_for_speed_p);
1142 fprintf(dump_file, "insn_cost %d: %d\n",
1143 INSN_UID (insn), INSN_COST (insn));
1147 nonzero_sign_valid = 1;
1149 /* Now scan all the insns in forward order. */
1150 label_tick = label_tick_ebb_start = 1;
1152 setup_incoming_promotions (first);
1153 last_bb = ENTRY_BLOCK_PTR;
1155 FOR_EACH_BB (this_basic_block)
1157 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1162 if (!single_pred_p (this_basic_block)
1163 || single_pred (this_basic_block) != last_bb)
1164 label_tick_ebb_start = label_tick;
1165 last_bb = this_basic_block;
1167 rtl_profile_for_bb (this_basic_block);
1168 for (insn = BB_HEAD (this_basic_block);
1169 insn != NEXT_INSN (BB_END (this_basic_block));
1170 insn = next ? next : NEXT_INSN (insn))
1173 if (NONDEBUG_INSN_P (insn))
1175 /* See if we know about function return values before this
1176 insn based upon SUBREG flags. */
1177 check_promoted_subreg (insn, PATTERN (insn));
1179 /* See if we can find hardregs and subreg of pseudos in
1180 narrower modes. This could help turning TRUNCATEs
1182 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1184 /* Try this insn with each insn it links back to. */
1186 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1187 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX,
1188 NULL_RTX, &new_direct_jump_p)) != 0)
1191 /* Try each sequence of three linked insns ending with this one. */
1193 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1195 rtx link = XEXP (links, 0);
1197 /* If the linked insn has been replaced by a note, then there
1198 is no point in pursuing this chain any further. */
1202 for (nextlinks = LOG_LINKS (link);
1204 nextlinks = XEXP (nextlinks, 1))
1205 if ((next = try_combine (insn, link, XEXP (nextlinks, 0),
1207 &new_direct_jump_p)) != 0)
1212 /* Try to combine a jump insn that uses CC0
1213 with a preceding insn that sets CC0, and maybe with its
1214 logical predecessor as well.
1215 This is how we make decrement-and-branch insns.
1216 We need this special code because data flow connections
1217 via CC0 do not get entered in LOG_LINKS. */
1220 && (prev = prev_nonnote_insn (insn)) != 0
1221 && NONJUMP_INSN_P (prev)
1222 && sets_cc0_p (PATTERN (prev)))
1224 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1225 &new_direct_jump_p)) != 0)
1228 for (nextlinks = LOG_LINKS (prev); nextlinks;
1229 nextlinks = XEXP (nextlinks, 1))
1230 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1232 &new_direct_jump_p)) != 0)
1236 /* Do the same for an insn that explicitly references CC0. */
1237 if (NONJUMP_INSN_P (insn)
1238 && (prev = prev_nonnote_insn (insn)) != 0
1239 && NONJUMP_INSN_P (prev)
1240 && sets_cc0_p (PATTERN (prev))
1241 && GET_CODE (PATTERN (insn)) == SET
1242 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1244 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1245 &new_direct_jump_p)) != 0)
1248 for (nextlinks = LOG_LINKS (prev); nextlinks;
1249 nextlinks = XEXP (nextlinks, 1))
1250 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1252 &new_direct_jump_p)) != 0)
1256 /* Finally, see if any of the insns that this insn links to
1257 explicitly references CC0. If so, try this insn, that insn,
1258 and its predecessor if it sets CC0. */
1259 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1260 if (NONJUMP_INSN_P (XEXP (links, 0))
1261 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1262 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1263 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1264 && NONJUMP_INSN_P (prev)
1265 && sets_cc0_p (PATTERN (prev))
1266 && (next = try_combine (insn, XEXP (links, 0),
1268 &new_direct_jump_p)) != 0)
1272 /* Try combining an insn with two different insns whose results it
1274 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1275 for (nextlinks = XEXP (links, 1); nextlinks;
1276 nextlinks = XEXP (nextlinks, 1))
1277 if ((next = try_combine (insn, XEXP (links, 0),
1278 XEXP (nextlinks, 0), NULL_RTX,
1279 &new_direct_jump_p)) != 0)
1282 /* Try four-instruction combinations. */
1283 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1286 rtx link = XEXP (links, 0);
1288 /* If the linked insn has been replaced by a note, then there
1289 is no point in pursuing this chain any further. */
1293 for (next1 = LOG_LINKS (link); next1; next1 = XEXP (next1, 1))
1295 rtx link1 = XEXP (next1, 0);
1298 /* I0 -> I1 -> I2 -> I3. */
1299 for (nextlinks = LOG_LINKS (link1); nextlinks;
1300 nextlinks = XEXP (nextlinks, 1))
1301 if ((next = try_combine (insn, link, link1,
1302 XEXP (nextlinks, 0),
1303 &new_direct_jump_p)) != 0)
1305 /* I0, I1 -> I2, I2 -> I3. */
1306 for (nextlinks = XEXP (next1, 1); nextlinks;
1307 nextlinks = XEXP (nextlinks, 1))
1308 if ((next = try_combine (insn, link, link1,
1309 XEXP (nextlinks, 0),
1310 &new_direct_jump_p)) != 0)
1314 for (next1 = XEXP (links, 1); next1; next1 = XEXP (next1, 1))
1316 rtx link1 = XEXP (next1, 0);
1319 /* I0 -> I2; I1, I2 -> I3. */
1320 for (nextlinks = LOG_LINKS (link); nextlinks;
1321 nextlinks = XEXP (nextlinks, 1))
1322 if ((next = try_combine (insn, link, link1,
1323 XEXP (nextlinks, 0),
1324 &new_direct_jump_p)) != 0)
1326 /* I0 -> I1; I1, I2 -> I3. */
1327 for (nextlinks = LOG_LINKS (link1); nextlinks;
1328 nextlinks = XEXP (nextlinks, 1))
1329 if ((next = try_combine (insn, link, link1,
1330 XEXP (nextlinks, 0),
1331 &new_direct_jump_p)) != 0)
1336 /* Try this insn with each REG_EQUAL note it links back to. */
1337 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1340 rtx temp = XEXP (links, 0);
1341 if ((set = single_set (temp)) != 0
1342 && (note = find_reg_equal_equiv_note (temp)) != 0
1343 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1344 /* Avoid using a register that may already been marked
1345 dead by an earlier instruction. */
1346 && ! unmentioned_reg_p (note, SET_SRC (set))
1347 && (GET_MODE (note) == VOIDmode
1348 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1349 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1351 /* Temporarily replace the set's source with the
1352 contents of the REG_EQUAL note. The insn will
1353 be deleted or recognized by try_combine. */
1354 rtx orig = SET_SRC (set);
1355 SET_SRC (set) = note;
1357 i2mod_old_rhs = copy_rtx (orig);
1358 i2mod_new_rhs = copy_rtx (note);
1359 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1360 &new_direct_jump_p);
1364 SET_SRC (set) = orig;
1369 record_dead_and_set_regs (insn);
1377 default_rtl_profile ();
1380 new_direct_jump_p |= purge_all_dead_edges ();
1381 delete_noop_moves ();
1384 free (uid_log_links);
1385 free (uid_insn_cost);
1386 VEC_free (reg_stat_type, heap, reg_stat);
1389 struct undo *undo, *next;
1390 for (undo = undobuf.frees; undo; undo = next)
1398 total_attempts += combine_attempts;
1399 total_merges += combine_merges;
1400 total_extras += combine_extras;
1401 total_successes += combine_successes;
1403 nonzero_sign_valid = 0;
1404 rtl_hooks = general_rtl_hooks;
1406 /* Make recognizer allow volatile MEMs again. */
1409 return new_direct_jump_p;
1412 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1415 init_reg_last (void)
1420 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1421 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1424 /* Set up any promoted values for incoming argument registers. */
1427 setup_incoming_promotions (rtx first)
1430 bool strictly_local = false;
1432 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1433 arg = DECL_CHAIN (arg))
1435 rtx x, reg = DECL_INCOMING_RTL (arg);
1437 enum machine_mode mode1, mode2, mode3, mode4;
1439 /* Only continue if the incoming argument is in a register. */
1443 /* Determine, if possible, whether all call sites of the current
1444 function lie within the current compilation unit. (This does
1445 take into account the exporting of a function via taking its
1446 address, and so forth.) */
1447 strictly_local = cgraph_local_info (current_function_decl)->local;
1449 /* The mode and signedness of the argument before any promotions happen
1450 (equal to the mode of the pseudo holding it at that stage). */
1451 mode1 = TYPE_MODE (TREE_TYPE (arg));
1452 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1454 /* The mode and signedness of the argument after any source language and
1455 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1456 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1457 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1459 /* The mode and signedness of the argument as it is actually passed,
1460 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1461 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1462 TREE_TYPE (cfun->decl), 0);
1464 /* The mode of the register in which the argument is being passed. */
1465 mode4 = GET_MODE (reg);
1467 /* Eliminate sign extensions in the callee when:
1468 (a) A mode promotion has occurred; */
1471 /* (b) The mode of the register is the same as the mode of
1472 the argument as it is passed; */
1475 /* (c) There's no language level extension; */
1478 /* (c.1) All callers are from the current compilation unit. If that's
1479 the case we don't have to rely on an ABI, we only have to know
1480 what we're generating right now, and we know that we will do the
1481 mode1 to mode2 promotion with the given sign. */
1482 else if (!strictly_local)
1484 /* (c.2) The combination of the two promotions is useful. This is
1485 true when the signs match, or if the first promotion is unsigned.
1486 In the later case, (sign_extend (zero_extend x)) is the same as
1487 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1493 /* Record that the value was promoted from mode1 to mode3,
1494 so that any sign extension at the head of the current
1495 function may be eliminated. */
1496 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1497 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1498 record_value_for_reg (reg, first, x);
1502 /* Called via note_stores. If X is a pseudo that is narrower than
1503 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1505 If we are setting only a portion of X and we can't figure out what
1506 portion, assume all bits will be used since we don't know what will
1509 Similarly, set how many bits of X are known to be copies of the sign bit
1510 at all locations in the function. This is the smallest number implied
1514 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1516 rtx insn = (rtx) data;
1520 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1521 /* If this register is undefined at the start of the file, we can't
1522 say what its contents were. */
1523 && ! REGNO_REG_SET_P
1524 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1525 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1527 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1529 if (set == 0 || GET_CODE (set) == CLOBBER)
1531 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1532 rsp->sign_bit_copies = 1;
1536 /* If this register is being initialized using itself, and the
1537 register is uninitialized in this basic block, and there are
1538 no LOG_LINKS which set the register, then part of the
1539 register is uninitialized. In that case we can't assume
1540 anything about the number of nonzero bits.
1542 ??? We could do better if we checked this in
1543 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1544 could avoid making assumptions about the insn which initially
1545 sets the register, while still using the information in other
1546 insns. We would have to be careful to check every insn
1547 involved in the combination. */
1550 && reg_referenced_p (x, PATTERN (insn))
1551 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1556 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1558 if (dead_or_set_p (XEXP (link, 0), x))
1563 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1564 rsp->sign_bit_copies = 1;
1569 /* If this is a complex assignment, see if we can convert it into a
1570 simple assignment. */
1571 set = expand_field_assignment (set);
1573 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1574 set what we know about X. */
1576 if (SET_DEST (set) == x
1577 || (GET_CODE (SET_DEST (set)) == SUBREG
1578 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1579 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1580 && SUBREG_REG (SET_DEST (set)) == x))
1582 rtx src = SET_SRC (set);
1584 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1585 /* If X is narrower than a word and SRC is a non-negative
1586 constant that would appear negative in the mode of X,
1587 sign-extend it for use in reg_stat[].nonzero_bits because some
1588 machines (maybe most) will actually do the sign-extension
1589 and this is the conservative approach.
1591 ??? For 2.5, try to tighten up the MD files in this regard
1592 instead of this kludge. */
1594 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1595 && CONST_INT_P (src)
1597 && 0 != (INTVAL (src)
1598 & ((HOST_WIDE_INT) 1
1599 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1600 src = GEN_INT (INTVAL (src)
1601 | ((HOST_WIDE_INT) (-1)
1602 << GET_MODE_BITSIZE (GET_MODE (x))));
1605 /* Don't call nonzero_bits if it cannot change anything. */
1606 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1607 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1608 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1609 if (rsp->sign_bit_copies == 0
1610 || rsp->sign_bit_copies > num)
1611 rsp->sign_bit_copies = num;
1615 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1616 rsp->sign_bit_copies = 1;
1621 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1622 optionally insns that were previously combined into I3 or that will be
1623 combined into the merger of INSN and I3. The order is PRED, PRED2,
1624 INSN, SUCC, SUCC2, I3.
1626 Return 0 if the combination is not allowed for any reason.
1628 If the combination is allowed, *PDEST will be set to the single
1629 destination of INSN and *PSRC to the single source, and this function
1633 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1634 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1635 rtx *pdest, rtx *psrc)
1644 bool all_adjacent = true;
1650 if (next_active_insn (succ2) != i3)
1651 all_adjacent = false;
1652 if (next_active_insn (succ) != succ2)
1653 all_adjacent = false;
1655 else if (next_active_insn (succ) != i3)
1656 all_adjacent = false;
1657 if (next_active_insn (insn) != succ)
1658 all_adjacent = false;
1660 else if (next_active_insn (insn) != i3)
1661 all_adjacent = false;
1663 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1664 or a PARALLEL consisting of such a SET and CLOBBERs.
1666 If INSN has CLOBBER parallel parts, ignore them for our processing.
1667 By definition, these happen during the execution of the insn. When it
1668 is merged with another insn, all bets are off. If they are, in fact,
1669 needed and aren't also supplied in I3, they may be added by
1670 recog_for_combine. Otherwise, it won't match.
1672 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1675 Get the source and destination of INSN. If more than one, can't
1678 if (GET_CODE (PATTERN (insn)) == SET)
1679 set = PATTERN (insn);
1680 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1681 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1683 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1685 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1687 switch (GET_CODE (elt))
1689 /* This is important to combine floating point insns
1690 for the SH4 port. */
1692 /* Combining an isolated USE doesn't make sense.
1693 We depend here on combinable_i3pat to reject them. */
1694 /* The code below this loop only verifies that the inputs of
1695 the SET in INSN do not change. We call reg_set_between_p
1696 to verify that the REG in the USE does not change between
1698 If the USE in INSN was for a pseudo register, the matching
1699 insn pattern will likely match any register; combining this
1700 with any other USE would only be safe if we knew that the
1701 used registers have identical values, or if there was
1702 something to tell them apart, e.g. different modes. For
1703 now, we forgo such complicated tests and simply disallow
1704 combining of USES of pseudo registers with any other USE. */
1705 if (REG_P (XEXP (elt, 0))
1706 && GET_CODE (PATTERN (i3)) == PARALLEL)
1708 rtx i3pat = PATTERN (i3);
1709 int i = XVECLEN (i3pat, 0) - 1;
1710 unsigned int regno = REGNO (XEXP (elt, 0));
1714 rtx i3elt = XVECEXP (i3pat, 0, i);
1716 if (GET_CODE (i3elt) == USE
1717 && REG_P (XEXP (i3elt, 0))
1718 && (REGNO (XEXP (i3elt, 0)) == regno
1719 ? reg_set_between_p (XEXP (elt, 0),
1720 PREV_INSN (insn), i3)
1721 : regno >= FIRST_PSEUDO_REGISTER))
1728 /* We can ignore CLOBBERs. */
1733 /* Ignore SETs whose result isn't used but not those that
1734 have side-effects. */
1735 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1736 && insn_nothrow_p (insn)
1737 && !side_effects_p (elt))
1740 /* If we have already found a SET, this is a second one and
1741 so we cannot combine with this insn. */
1749 /* Anything else means we can't combine. */
1755 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1756 so don't do anything with it. */
1757 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1766 set = expand_field_assignment (set);
1767 src = SET_SRC (set), dest = SET_DEST (set);
1769 /* Don't eliminate a store in the stack pointer. */
1770 if (dest == stack_pointer_rtx
1771 /* Don't combine with an insn that sets a register to itself if it has
1772 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1773 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1774 /* Can't merge an ASM_OPERANDS. */
1775 || GET_CODE (src) == ASM_OPERANDS
1776 /* Can't merge a function call. */
1777 || GET_CODE (src) == CALL
1778 /* Don't eliminate a function call argument. */
1780 && (find_reg_fusage (i3, USE, dest)
1782 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1783 && global_regs[REGNO (dest)])))
1784 /* Don't substitute into an incremented register. */
1785 || FIND_REG_INC_NOTE (i3, dest)
1786 || (succ && FIND_REG_INC_NOTE (succ, dest))
1787 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1788 /* Don't substitute into a non-local goto, this confuses CFG. */
1789 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1790 /* Make sure that DEST is not used after SUCC but before I3. */
1793 && (reg_used_between_p (dest, succ2, i3)
1794 || reg_used_between_p (dest, succ, succ2)))
1795 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1796 /* Make sure that the value that is to be substituted for the register
1797 does not use any registers whose values alter in between. However,
1798 If the insns are adjacent, a use can't cross a set even though we
1799 think it might (this can happen for a sequence of insns each setting
1800 the same destination; last_set of that register might point to
1801 a NOTE). If INSN has a REG_EQUIV note, the register is always
1802 equivalent to the memory so the substitution is valid even if there
1803 are intervening stores. Also, don't move a volatile asm or
1804 UNSPEC_VOLATILE across any other insns. */
1807 || ! find_reg_note (insn, REG_EQUIV, src))
1808 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1809 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1810 || GET_CODE (src) == UNSPEC_VOLATILE))
1811 /* Don't combine across a CALL_INSN, because that would possibly
1812 change whether the life span of some REGs crosses calls or not,
1813 and it is a pain to update that information.
1814 Exception: if source is a constant, moving it later can't hurt.
1815 Accept that as a special case. */
1816 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1819 /* DEST must either be a REG or CC0. */
1822 /* If register alignment is being enforced for multi-word items in all
1823 cases except for parameters, it is possible to have a register copy
1824 insn referencing a hard register that is not allowed to contain the
1825 mode being copied and which would not be valid as an operand of most
1826 insns. Eliminate this problem by not combining with such an insn.
1828 Also, on some machines we don't want to extend the life of a hard
1832 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1833 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1834 /* Don't extend the life of a hard register unless it is
1835 user variable (if we have few registers) or it can't
1836 fit into the desired register (meaning something special
1838 Also avoid substituting a return register into I3, because
1839 reload can't handle a conflict with constraints of other
1841 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1842 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1845 else if (GET_CODE (dest) != CC0)
1849 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1850 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1851 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1853 /* Don't substitute for a register intended as a clobberable
1855 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1856 if (rtx_equal_p (reg, dest))
1859 /* If the clobber represents an earlyclobber operand, we must not
1860 substitute an expression containing the clobbered register.
1861 As we do not analyze the constraint strings here, we have to
1862 make the conservative assumption. However, if the register is
1863 a fixed hard reg, the clobber cannot represent any operand;
1864 we leave it up to the machine description to either accept or
1865 reject use-and-clobber patterns. */
1867 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1868 || !fixed_regs[REGNO (reg)])
1869 if (reg_overlap_mentioned_p (reg, src))
1873 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1874 or not), reject, unless nothing volatile comes between it and I3 */
1876 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1878 /* Make sure neither succ nor succ2 contains a volatile reference. */
1879 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1881 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1883 /* We'll check insns between INSN and I3 below. */
1886 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1887 to be an explicit register variable, and was chosen for a reason. */
1889 if (GET_CODE (src) == ASM_OPERANDS
1890 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1893 /* If there are any volatile insns between INSN and I3, reject, because
1894 they might affect machine state. */
1896 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1897 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1900 /* If INSN contains an autoincrement or autodecrement, make sure that
1901 register is not used between there and I3, and not already used in
1902 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1903 Also insist that I3 not be a jump; if it were one
1904 and the incremented register were spilled, we would lose. */
1907 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1908 if (REG_NOTE_KIND (link) == REG_INC
1910 || reg_used_between_p (XEXP (link, 0), insn, i3)
1911 || (pred != NULL_RTX
1912 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1913 || (pred2 != NULL_RTX
1914 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1915 || (succ != NULL_RTX
1916 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1917 || (succ2 != NULL_RTX
1918 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1919 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1924 /* Don't combine an insn that follows a CC0-setting insn.
1925 An insn that uses CC0 must not be separated from the one that sets it.
1926 We do, however, allow I2 to follow a CC0-setting insn if that insn
1927 is passed as I1; in that case it will be deleted also.
1928 We also allow combining in this case if all the insns are adjacent
1929 because that would leave the two CC0 insns adjacent as well.
1930 It would be more logical to test whether CC0 occurs inside I1 or I2,
1931 but that would be much slower, and this ought to be equivalent. */
1933 p = prev_nonnote_insn (insn);
1934 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1939 /* If we get here, we have passed all the tests and the combination is
1948 /* LOC is the location within I3 that contains its pattern or the component
1949 of a PARALLEL of the pattern. We validate that it is valid for combining.
1951 One problem is if I3 modifies its output, as opposed to replacing it
1952 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1953 doing so would produce an insn that is not equivalent to the original insns.
1957 (set (reg:DI 101) (reg:DI 100))
1958 (set (subreg:SI (reg:DI 101) 0) <foo>)
1960 This is NOT equivalent to:
1962 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1963 (set (reg:DI 101) (reg:DI 100))])
1965 Not only does this modify 100 (in which case it might still be valid
1966 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1968 We can also run into a problem if I2 sets a register that I1
1969 uses and I1 gets directly substituted into I3 (not via I2). In that
1970 case, we would be getting the wrong value of I2DEST into I3, so we
1971 must reject the combination. This case occurs when I2 and I1 both
1972 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1973 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1974 of a SET must prevent combination from occurring. The same situation
1975 can occur for I0, in which case I0_NOT_IN_SRC is set.
1977 Before doing the above check, we first try to expand a field assignment
1978 into a set of logical operations.
1980 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1981 we place a register that is both set and used within I3. If more than one
1982 such register is detected, we fail.
1984 Return 1 if the combination is valid, zero otherwise. */
1987 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
1988 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
1992 if (GET_CODE (x) == SET)
1995 rtx dest = SET_DEST (set);
1996 rtx src = SET_SRC (set);
1997 rtx inner_dest = dest;
2000 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2001 || GET_CODE (inner_dest) == SUBREG
2002 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2003 inner_dest = XEXP (inner_dest, 0);
2005 /* Check for the case where I3 modifies its output, as discussed
2006 above. We don't want to prevent pseudos from being combined
2007 into the address of a MEM, so only prevent the combination if
2008 i1 or i2 set the same MEM. */
2009 if ((inner_dest != dest &&
2010 (!MEM_P (inner_dest)
2011 || rtx_equal_p (i2dest, inner_dest)
2012 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2013 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2014 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2015 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2016 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2018 /* This is the same test done in can_combine_p except we can't test
2019 all_adjacent; we don't have to, since this instruction will stay
2020 in place, thus we are not considering increasing the lifetime of
2023 Also, if this insn sets a function argument, combining it with
2024 something that might need a spill could clobber a previous
2025 function argument; the all_adjacent test in can_combine_p also
2026 checks this; here, we do a more specific test for this case. */
2028 || (REG_P (inner_dest)
2029 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2030 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2031 GET_MODE (inner_dest))))
2032 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2033 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2036 /* If DEST is used in I3, it is being killed in this insn, so
2037 record that for later. We have to consider paradoxical
2038 subregs here, since they kill the whole register, but we
2039 ignore partial subregs, STRICT_LOW_PART, etc.
2040 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2041 STACK_POINTER_REGNUM, since these are always considered to be
2042 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2044 if (GET_CODE (subdest) == SUBREG
2045 && (GET_MODE_SIZE (GET_MODE (subdest))
2046 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2047 subdest = SUBREG_REG (subdest);
2050 && reg_referenced_p (subdest, PATTERN (i3))
2051 && REGNO (subdest) != FRAME_POINTER_REGNUM
2052 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2053 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2055 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2056 && (REGNO (subdest) != ARG_POINTER_REGNUM
2057 || ! fixed_regs [REGNO (subdest)])
2059 && REGNO (subdest) != STACK_POINTER_REGNUM)
2061 if (*pi3dest_killed)
2064 *pi3dest_killed = subdest;
2068 else if (GET_CODE (x) == PARALLEL)
2072 for (i = 0; i < XVECLEN (x, 0); i++)
2073 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2074 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2081 /* Return 1 if X is an arithmetic expression that contains a multiplication
2082 and division. We don't count multiplications by powers of two here. */
2085 contains_muldiv (rtx x)
2087 switch (GET_CODE (x))
2089 case MOD: case DIV: case UMOD: case UDIV:
2093 return ! (CONST_INT_P (XEXP (x, 1))
2094 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
2097 return contains_muldiv (XEXP (x, 0))
2098 || contains_muldiv (XEXP (x, 1));
2101 return contains_muldiv (XEXP (x, 0));
2107 /* Determine whether INSN can be used in a combination. Return nonzero if
2108 not. This is used in try_combine to detect early some cases where we
2109 can't perform combinations. */
2112 cant_combine_insn_p (rtx insn)
2117 /* If this isn't really an insn, we can't do anything.
2118 This can occur when flow deletes an insn that it has merged into an
2119 auto-increment address. */
2120 if (! INSN_P (insn))
2123 /* Never combine loads and stores involving hard regs that are likely
2124 to be spilled. The register allocator can usually handle such
2125 reg-reg moves by tying. If we allow the combiner to make
2126 substitutions of likely-spilled regs, reload might die.
2127 As an exception, we allow combinations involving fixed regs; these are
2128 not available to the register allocator so there's no risk involved. */
2130 set = single_set (insn);
2133 src = SET_SRC (set);
2134 dest = SET_DEST (set);
2135 if (GET_CODE (src) == SUBREG)
2136 src = SUBREG_REG (src);
2137 if (GET_CODE (dest) == SUBREG)
2138 dest = SUBREG_REG (dest);
2139 if (REG_P (src) && REG_P (dest)
2140 && ((HARD_REGISTER_P (src)
2141 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2142 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2143 || (HARD_REGISTER_P (dest)
2144 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2145 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2151 struct likely_spilled_retval_info
2153 unsigned regno, nregs;
2157 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2158 hard registers that are known to be written to / clobbered in full. */
2160 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2162 struct likely_spilled_retval_info *const info =
2163 (struct likely_spilled_retval_info *) data;
2164 unsigned regno, nregs;
2167 if (!REG_P (XEXP (set, 0)))
2170 if (regno >= info->regno + info->nregs)
2172 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2173 if (regno + nregs <= info->regno)
2175 new_mask = (2U << (nregs - 1)) - 1;
2176 if (regno < info->regno)
2177 new_mask >>= info->regno - regno;
2179 new_mask <<= regno - info->regno;
2180 info->mask &= ~new_mask;
2183 /* Return nonzero iff part of the return value is live during INSN, and
2184 it is likely spilled. This can happen when more than one insn is needed
2185 to copy the return value, e.g. when we consider to combine into the
2186 second copy insn for a complex value. */
2189 likely_spilled_retval_p (rtx insn)
2191 rtx use = BB_END (this_basic_block);
2193 unsigned regno, nregs;
2194 /* We assume here that no machine mode needs more than
2195 32 hard registers when the value overlaps with a register
2196 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2198 struct likely_spilled_retval_info info;
2200 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2202 reg = XEXP (PATTERN (use), 0);
2203 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2205 regno = REGNO (reg);
2206 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2209 mask = (2U << (nregs - 1)) - 1;
2211 /* Disregard parts of the return value that are set later. */
2215 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2217 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2220 /* Check if any of the (probably) live return value registers is
2225 if ((mask & 1 << nregs)
2226 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2232 /* Adjust INSN after we made a change to its destination.
2234 Changing the destination can invalidate notes that say something about
2235 the results of the insn and a LOG_LINK pointing to the insn. */
2238 adjust_for_new_dest (rtx insn)
2240 /* For notes, be conservative and simply remove them. */
2241 remove_reg_equal_equiv_notes (insn);
2243 /* The new insn will have a destination that was previously the destination
2244 of an insn just above it. Call distribute_links to make a LOG_LINK from
2245 the next use of that destination. */
2246 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2248 df_insn_rescan (insn);
2251 /* Return TRUE if combine can reuse reg X in mode MODE.
2252 ADDED_SETS is nonzero if the original set is still required. */
2254 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2262 /* Allow hard registers if the new mode is legal, and occupies no more
2263 registers than the old mode. */
2264 if (regno < FIRST_PSEUDO_REGISTER)
2265 return (HARD_REGNO_MODE_OK (regno, mode)
2266 && (hard_regno_nregs[regno][GET_MODE (x)]
2267 >= hard_regno_nregs[regno][mode]));
2269 /* Or a pseudo that is only used once. */
2270 return (REG_N_SETS (regno) == 1 && !added_sets
2271 && !REG_USERVAR_P (x));
2275 /* Check whether X, the destination of a set, refers to part of
2276 the register specified by REG. */
2279 reg_subword_p (rtx x, rtx reg)
2281 /* Check that reg is an integer mode register. */
2282 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2285 if (GET_CODE (x) == STRICT_LOW_PART
2286 || GET_CODE (x) == ZERO_EXTRACT)
2289 return GET_CODE (x) == SUBREG
2290 && SUBREG_REG (x) == reg
2291 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2295 /* Replace auto-increment addressing modes with explicit operations to
2296 access the same addresses without modifying the corresponding
2297 registers. If AFTER holds, SRC is meant to be reused after the
2298 side effect, otherwise it is to be reused before that. */
2301 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2304 const RTX_CODE code = GET_CODE (x);
2320 /* SCRATCH must be shared because they represent distinct values. */
2323 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2328 if (shared_const_p (x))
2333 mem_mode = GET_MODE (x);
2340 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2341 if (after == (code == PRE_INC || code == PRE_DEC))
2342 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2344 x = gen_rtx_PLUS (GET_MODE (x),
2345 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2346 GEN_INT ((code == PRE_INC || code == POST_INC)
2347 ? GET_MODE_SIZE (mem_mode)
2348 : -GET_MODE_SIZE (mem_mode)));
2353 if (after == (code == PRE_MODIFY))
2357 return cleanup_auto_inc_dec (x, after, mem_mode);
2363 /* Copy the various flags, fields, and other information. We assume
2364 that all fields need copying, and then clear the fields that should
2365 not be copied. That is the sensible default behavior, and forces
2366 us to explicitly document why we are *not* copying a flag. */
2367 x = shallow_copy_rtx (x);
2369 /* We do not copy the USED flag, which is used as a mark bit during
2370 walks over the RTL. */
2371 RTX_FLAG (x, used) = 0;
2373 /* We do not copy FRAME_RELATED for INSNs. */
2375 RTX_FLAG (x, frame_related) = 0;
2377 fmt = GET_RTX_FORMAT (code);
2378 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2380 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2381 else if (fmt[i] == 'E' || fmt[i] == 'V')
2384 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2385 for (j = 0; j < XVECLEN (x, i); j++)
2387 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2394 /* Auxiliary data structure for propagate_for_debug_stmt. */
2396 struct rtx_subst_pair
2403 /* DATA points to an rtx_subst_pair. Return the value that should be
2407 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2409 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2411 if (!rtx_equal_p (from, old_rtx))
2413 if (!pair->adjusted)
2415 pair->adjusted = true;
2417 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2419 pair->to = copy_rtx (pair->to);
2421 pair->to = make_compound_operation (pair->to, SET);
2424 return copy_rtx (pair->to);
2427 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2428 and LAST. If MOVE holds, debug insns must also be moved past
2432 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2434 rtx next, move_pos = move ? last : NULL_RTX, loc;
2436 struct rtx_subst_pair p;
2441 next = NEXT_INSN (insn);
2442 while (next != last)
2445 next = NEXT_INSN (insn);
2446 if (DEBUG_INSN_P (insn))
2448 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2449 dest, propagate_for_debug_subst, &p);
2450 if (loc == INSN_VAR_LOCATION_LOC (insn))
2452 INSN_VAR_LOCATION_LOC (insn) = loc;
2456 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2457 move_pos = emit_debug_insn_after (insn, move_pos);
2460 df_insn_rescan (insn);
2465 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2466 Note that the INSN should be deleted *after* removing dead edges, so
2467 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2468 but not for a (set (pc) (label_ref FOO)). */
2471 update_cfg_for_uncondjump (rtx insn)
2473 basic_block bb = BLOCK_FOR_INSN (insn);
2474 bool at_end = (BB_END (bb) == insn);
2477 purge_dead_edges (bb);
2480 if (at_end && EDGE_COUNT (bb->succs) == 1)
2481 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2484 /* Try to combine the insns I0, I1 and I2 into I3.
2485 Here I0, I1 and I2 appear earlier than I3.
2486 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2489 If we are combining more than two insns and the resulting insn is not
2490 recognized, try splitting it into two insns. If that happens, I2 and I3
2491 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2492 Otherwise, I0, I1 and I2 are pseudo-deleted.
2494 Return 0 if the combination does not work. Then nothing is changed.
2495 If we did the combination, return the insn at which combine should
2498 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2499 new direct jump instruction. */
2502 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p)
2504 /* New patterns for I3 and I2, respectively. */
2505 rtx newpat, newi2pat = 0;
2506 rtvec newpat_vec_with_clobbers = 0;
2507 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2508 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2510 int added_sets_0, added_sets_1, added_sets_2;
2511 /* Total number of SETs to put into I3. */
2513 /* Nonzero if I2's or I1's body now appears in I3. */
2514 int i2_is_used = 0, i1_is_used = 0;
2515 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2516 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2517 /* Contains I3 if the destination of I3 is used in its source, which means
2518 that the old life of I3 is being killed. If that usage is placed into
2519 I2 and not in I3, a REG_DEAD note must be made. */
2520 rtx i3dest_killed = 0;
2521 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2522 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2523 /* Set if I2DEST was reused as a scratch register. */
2524 bool i2scratch = false;
2525 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2526 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2529 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2530 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2531 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2532 /* Notes that must be added to REG_NOTES in I3 and I2. */
2533 rtx new_i3_notes, new_i2_notes;
2534 /* Notes that we substituted I3 into I2 instead of the normal case. */
2535 int i3_subst_into_i2 = 0;
2536 /* Notes that I1, I2 or I3 is a MULT operation. */
2539 int changed_i3_dest = 0;
2545 rtx new_other_notes;
2548 /* Only try four-insn combinations when there's high likelihood of
2549 success. Look for simple insns, such as loads of constants or
2550 binary operations involving a constant. */
2557 if (!flag_expensive_optimizations)
2560 for (i = 0; i < 4; i++)
2562 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2563 rtx set = single_set (insn);
2567 src = SET_SRC (set);
2568 if (CONSTANT_P (src))
2573 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2575 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2576 || GET_CODE (src) == LSHIFTRT)
2579 if (ngood < 2 && nshift < 2)
2583 /* Exit early if one of the insns involved can't be used for
2585 if (cant_combine_insn_p (i3)
2586 || cant_combine_insn_p (i2)
2587 || (i1 && cant_combine_insn_p (i1))
2588 || (i0 && cant_combine_insn_p (i0))
2589 || likely_spilled_retval_p (i3))
2593 undobuf.other_insn = 0;
2595 /* Reset the hard register usage information. */
2596 CLEAR_HARD_REG_SET (newpat_used_regs);
2598 if (dump_file && (dump_flags & TDF_DETAILS))
2601 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2602 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2604 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2605 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2607 fprintf (dump_file, "\nTrying %d -> %d:\n",
2608 INSN_UID (i2), INSN_UID (i3));
2611 /* If multiple insns feed into one of I2 or I3, they can be in any
2612 order. To simplify the code below, reorder them in sequence. */
2613 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2614 temp = i2, i2 = i0, i0 = temp;
2615 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2616 temp = i1, i1 = i0, i0 = temp;
2617 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2618 temp = i1, i1 = i2, i2 = temp;
2620 added_links_insn = 0;
2622 /* First check for one important special-case that the code below will
2623 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2624 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2625 we may be able to replace that destination with the destination of I3.
2626 This occurs in the common code where we compute both a quotient and
2627 remainder into a structure, in which case we want to do the computation
2628 directly into the structure to avoid register-register copies.
2630 Note that this case handles both multiple sets in I2 and also
2631 cases where I2 has a number of CLOBBER or PARALLELs.
2633 We make very conservative checks below and only try to handle the
2634 most common cases of this. For example, we only handle the case
2635 where I2 and I3 are adjacent to avoid making difficult register
2638 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2639 && REG_P (SET_SRC (PATTERN (i3)))
2640 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2641 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2642 && GET_CODE (PATTERN (i2)) == PARALLEL
2643 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2644 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2645 below would need to check what is inside (and reg_overlap_mentioned_p
2646 doesn't support those codes anyway). Don't allow those destinations;
2647 the resulting insn isn't likely to be recognized anyway. */
2648 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2649 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2650 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2651 SET_DEST (PATTERN (i3)))
2652 && next_active_insn (i2) == i3)
2654 rtx p2 = PATTERN (i2);
2656 /* Make sure that the destination of I3,
2657 which we are going to substitute into one output of I2,
2658 is not used within another output of I2. We must avoid making this:
2659 (parallel [(set (mem (reg 69)) ...)
2660 (set (reg 69) ...)])
2661 which is not well-defined as to order of actions.
2662 (Besides, reload can't handle output reloads for this.)
2664 The problem can also happen if the dest of I3 is a memory ref,
2665 if another dest in I2 is an indirect memory ref. */
2666 for (i = 0; i < XVECLEN (p2, 0); i++)
2667 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2668 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2669 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2670 SET_DEST (XVECEXP (p2, 0, i))))
2673 if (i == XVECLEN (p2, 0))
2674 for (i = 0; i < XVECLEN (p2, 0); i++)
2675 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2676 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2677 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2682 subst_low_luid = DF_INSN_LUID (i2);
2684 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2685 i2src = SET_DEST (PATTERN (i3));
2686 i2dest = SET_SRC (PATTERN (i3));
2687 i2dest_killed = dead_or_set_p (i2, i2dest);
2689 /* Replace the dest in I2 with our dest and make the resulting
2690 insn the new pattern for I3. Then skip to where we
2691 validate the pattern. Everything was set up above. */
2692 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2693 SET_DEST (PATTERN (i3)));
2696 i3_subst_into_i2 = 1;
2697 goto validate_replacement;
2701 /* If I2 is setting a pseudo to a constant and I3 is setting some
2702 sub-part of it to another constant, merge them by making a new
2705 && (temp = single_set (i2)) != 0
2706 && (CONST_INT_P (SET_SRC (temp))
2707 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2708 && GET_CODE (PATTERN (i3)) == SET
2709 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2710 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2711 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2713 rtx dest = SET_DEST (PATTERN (i3));
2717 if (GET_CODE (dest) == ZERO_EXTRACT)
2719 if (CONST_INT_P (XEXP (dest, 1))
2720 && CONST_INT_P (XEXP (dest, 2)))
2722 width = INTVAL (XEXP (dest, 1));
2723 offset = INTVAL (XEXP (dest, 2));
2724 dest = XEXP (dest, 0);
2725 if (BITS_BIG_ENDIAN)
2726 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2731 if (GET_CODE (dest) == STRICT_LOW_PART)
2732 dest = XEXP (dest, 0);
2733 width = GET_MODE_BITSIZE (GET_MODE (dest));
2739 /* If this is the low part, we're done. */
2740 if (subreg_lowpart_p (dest))
2742 /* Handle the case where inner is twice the size of outer. */
2743 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2744 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2745 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2746 /* Otherwise give up for now. */
2752 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2753 <= HOST_BITS_PER_DOUBLE_INT))
2756 rtx inner = SET_SRC (PATTERN (i3));
2757 rtx outer = SET_SRC (temp);
2759 o = rtx_to_double_int (outer);
2760 i = rtx_to_double_int (inner);
2762 m = double_int_mask (width);
2763 i = double_int_and (i, m);
2764 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2765 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2766 o = double_int_ior (double_int_and_not (o, m), i);
2770 subst_low_luid = DF_INSN_LUID (i2);
2771 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2772 i2dest = SET_DEST (temp);
2773 i2dest_killed = dead_or_set_p (i2, i2dest);
2775 /* Replace the source in I2 with the new constant and make the
2776 resulting insn the new pattern for I3. Then skip to where we
2777 validate the pattern. Everything was set up above. */
2778 SUBST (SET_SRC (temp),
2779 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2781 newpat = PATTERN (i2);
2783 /* The dest of I3 has been replaced with the dest of I2. */
2784 changed_i3_dest = 1;
2785 goto validate_replacement;
2790 /* If we have no I1 and I2 looks like:
2791 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2793 make up a dummy I1 that is
2796 (set (reg:CC X) (compare:CC Y (const_int 0)))
2798 (We can ignore any trailing CLOBBERs.)
2800 This undoes a previous combination and allows us to match a branch-and-
2803 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2804 && XVECLEN (PATTERN (i2), 0) >= 2
2805 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2806 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2808 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2809 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2810 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2811 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2812 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2813 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2815 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2816 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2821 /* We make I1 with the same INSN_UID as I2. This gives it
2822 the same DF_INSN_LUID for value tracking. Our fake I1 will
2823 never appear in the insn stream so giving it the same INSN_UID
2824 as I2 will not cause a problem. */
2826 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2827 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2828 INSN_LOCATOR (i2), -1, NULL_RTX);
2830 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2831 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2832 SET_DEST (PATTERN (i1)));
2837 /* Verify that I2 and I1 are valid for combining. */
2838 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2839 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2841 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2848 /* Record whether I2DEST is used in I2SRC and similarly for the other
2849 cases. Knowing this will help in register status updating below. */
2850 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2851 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2852 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2853 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2854 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2855 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2856 i2dest_killed = dead_or_set_p (i2, i2dest);
2857 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2858 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2860 /* For the earlier insns, determine which of the subsequent ones they
2862 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2863 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2864 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2865 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2866 && reg_overlap_mentioned_p (i0dest, i2src))));
2868 /* Ensure that I3's pattern can be the destination of combines. */
2869 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2870 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2871 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2872 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2879 /* See if any of the insns is a MULT operation. Unless one is, we will
2880 reject a combination that is, since it must be slower. Be conservative
2882 if (GET_CODE (i2src) == MULT
2883 || (i1 != 0 && GET_CODE (i1src) == MULT)
2884 || (i0 != 0 && GET_CODE (i0src) == MULT)
2885 || (GET_CODE (PATTERN (i3)) == SET
2886 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2889 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2890 We used to do this EXCEPT in one case: I3 has a post-inc in an
2891 output operand. However, that exception can give rise to insns like
2893 which is a famous insn on the PDP-11 where the value of r3 used as the
2894 source was model-dependent. Avoid this sort of thing. */
2897 if (!(GET_CODE (PATTERN (i3)) == SET
2898 && REG_P (SET_SRC (PATTERN (i3)))
2899 && MEM_P (SET_DEST (PATTERN (i3)))
2900 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2901 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2902 /* It's not the exception. */
2905 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2906 if (REG_NOTE_KIND (link) == REG_INC
2907 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2909 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2916 /* See if the SETs in I1 or I2 need to be kept around in the merged
2917 instruction: whenever the value set there is still needed past I3.
2918 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2920 For the SET in I1, we have two cases: If I1 and I2 independently
2921 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2922 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2923 in I1 needs to be kept around unless I1DEST dies or is set in either
2924 I2 or I3. The same consideration applies to I0. */
2926 added_sets_2 = !dead_or_set_p (i3, i2dest);
2929 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2930 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2935 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2936 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2937 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2941 /* If the set in I2 needs to be kept around, we must make a copy of
2942 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2943 PATTERN (I2), we are only substituting for the original I1DEST, not into
2944 an already-substituted copy. This also prevents making self-referential
2945 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2950 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2951 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2953 i2pat = copy_rtx (PATTERN (i2));
2958 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2959 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2961 i1pat = copy_rtx (PATTERN (i1));
2966 if (GET_CODE (PATTERN (i0)) == PARALLEL)
2967 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2969 i0pat = copy_rtx (PATTERN (i0));
2974 /* Substitute in the latest insn for the regs set by the earlier ones. */
2976 maxreg = max_reg_num ();
2981 /* Many machines that don't use CC0 have insns that can both perform an
2982 arithmetic operation and set the condition code. These operations will
2983 be represented as a PARALLEL with the first element of the vector
2984 being a COMPARE of an arithmetic operation with the constant zero.
2985 The second element of the vector will set some pseudo to the result
2986 of the same arithmetic operation. If we simplify the COMPARE, we won't
2987 match such a pattern and so will generate an extra insn. Here we test
2988 for this case, where both the comparison and the operation result are
2989 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2990 I2SRC. Later we will make the PARALLEL that contains I2. */
2992 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2993 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2994 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2995 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2997 #ifdef SELECT_CC_MODE
2999 enum machine_mode compare_mode;
3002 newpat = PATTERN (i3);
3003 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3007 #ifdef SELECT_CC_MODE
3008 /* See if a COMPARE with the operand we substituted in should be done
3009 with the mode that is currently being used. If not, do the same
3010 processing we do in `subst' for a SET; namely, if the destination
3011 is used only once, try to replace it with a register of the proper
3012 mode and also replace the COMPARE. */
3013 if (undobuf.other_insn == 0
3014 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3015 &undobuf.other_insn))
3016 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3018 != GET_MODE (SET_DEST (newpat))))
3020 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3023 unsigned int regno = REGNO (SET_DEST (newpat));
3026 if (regno < FIRST_PSEUDO_REGISTER)
3027 new_dest = gen_rtx_REG (compare_mode, regno);
3030 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3031 new_dest = regno_reg_rtx[regno];
3034 SUBST (SET_DEST (newpat), new_dest);
3035 SUBST (XEXP (*cc_use, 0), new_dest);
3036 SUBST (SET_SRC (newpat),
3037 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3040 undobuf.other_insn = 0;
3047 /* It is possible that the source of I2 or I1 may be performing
3048 an unneeded operation, such as a ZERO_EXTEND of something
3049 that is known to have the high part zero. Handle that case
3050 by letting subst look at the innermost one of them.
3052 Another way to do this would be to have a function that tries
3053 to simplify a single insn instead of merging two or more
3054 insns. We don't do this because of the potential of infinite
3055 loops and because of the potential extra memory required.
3056 However, doing it the way we are is a bit of a kludge and
3057 doesn't catch all cases.
3059 But only do this if -fexpensive-optimizations since it slows
3060 things down and doesn't usually win.
3062 This is not done in the COMPARE case above because the
3063 unmodified I2PAT is used in the PARALLEL and so a pattern
3064 with a modified I2SRC would not match. */
3066 if (flag_expensive_optimizations)
3068 /* Pass pc_rtx so no substitutions are done, just
3072 subst_low_luid = DF_INSN_LUID (i1);
3073 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3077 subst_low_luid = DF_INSN_LUID (i2);
3078 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3082 n_occurrences = 0; /* `subst' counts here */
3084 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a
3085 unique copy of I2SRC each time we substitute it to avoid
3086 self-referential rtl. */
3088 subst_low_luid = DF_INSN_LUID (i2);
3089 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3090 ((i1_feeds_i2_n && i1dest_in_i1src)
3091 || (i0_feeds_i2_n && i0dest_in_i0src)));
3094 /* Record whether i2's body now appears within i3's body. */
3095 i2_is_used = n_occurrences;
3098 /* If we already got a failure, don't try to do more. Otherwise,
3099 try to substitute in I1 if we have it. */
3101 if (i1 && GET_CODE (newpat) != CLOBBER)
3103 /* Check that an autoincrement side-effect on I1 has not been lost.
3104 This happens if I1DEST is mentioned in I2 and dies there, and
3105 has disappeared from the new pattern. */
3106 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3108 && dead_or_set_p (i2, i1dest)
3109 && !reg_overlap_mentioned_p (i1dest, newpat))
3110 /* Before we can do this substitution, we must redo the test done
3111 above (see detailed comments there) that ensures that I1DEST
3112 isn't mentioned in any SETs in NEWPAT that are field assignments. */
3113 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3121 subst_low_luid = DF_INSN_LUID (i1);
3122 newpat = subst (newpat, i1dest, i1src, 0,
3123 i0_feeds_i1_n && i0dest_in_i0src);
3125 i1_is_used = n_occurrences;
3127 if (i0 && GET_CODE (newpat) != CLOBBER)
3129 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3130 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3131 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3132 && !reg_overlap_mentioned_p (i0dest, newpat))
3133 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3141 subst_low_luid = DF_INSN_LUID (i1);
3142 newpat = subst (newpat, i0dest, i0src, 0,
3143 i0_feeds_i1_n && i0dest_in_i0src);
3147 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3148 to count all the ways that I2SRC and I1SRC can be used. */
3149 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3150 && i2_is_used + added_sets_2 > 1)
3151 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3152 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3154 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3155 && (n_occurrences + added_sets_0
3156 + (added_sets_1 && i0_feeds_i1_n)
3157 + (added_sets_2 && i0_feeds_i2_n)
3159 /* Fail if we tried to make a new register. */
3160 || max_reg_num () != maxreg
3161 /* Fail if we couldn't do something and have a CLOBBER. */
3162 || GET_CODE (newpat) == CLOBBER
3163 /* Fail if this new pattern is a MULT and we didn't have one before
3164 at the outer level. */
3165 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3172 /* If the actions of the earlier insns must be kept
3173 in addition to substituting them into the latest one,
3174 we must make a new PARALLEL for the latest insn
3175 to hold additional the SETs. */
3177 if (added_sets_0 || added_sets_1 || added_sets_2)
3179 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3182 if (GET_CODE (newpat) == PARALLEL)
3184 rtvec old = XVEC (newpat, 0);
3185 total_sets = XVECLEN (newpat, 0) + extra_sets;
3186 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3187 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3188 sizeof (old->elem[0]) * old->num_elem);
3193 total_sets = 1 + extra_sets;
3194 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3195 XVECEXP (newpat, 0, 0) = old;
3199 XVECEXP (newpat, 0, --total_sets) = i0pat;
3205 t = subst (t, i0dest, i0src, 0, 0);
3207 XVECEXP (newpat, 0, --total_sets) = t;
3213 t = subst (t, i0dest, i0src, 0, 0);
3215 t = subst (t, i1dest, i1src, 0, 0);
3217 XVECEXP (newpat, 0, --total_sets) = t;
3221 validate_replacement:
3223 /* Note which hard regs this insn has as inputs. */
3224 mark_used_regs_combine (newpat);
3226 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3227 consider splitting this pattern, we might need these clobbers. */
3228 if (i1 && GET_CODE (newpat) == PARALLEL
3229 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3231 int len = XVECLEN (newpat, 0);
3233 newpat_vec_with_clobbers = rtvec_alloc (len);
3234 for (i = 0; i < len; i++)
3235 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3238 /* Is the result of combination a valid instruction? */
3239 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3241 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3242 the second SET's destination is a register that is unused and isn't
3243 marked as an instruction that might trap in an EH region. In that case,
3244 we just need the first SET. This can occur when simplifying a divmod
3245 insn. We *must* test for this case here because the code below that
3246 splits two independent SETs doesn't handle this case correctly when it
3247 updates the register status.
3249 It's pointless doing this if we originally had two sets, one from
3250 i3, and one from i2. Combining then splitting the parallel results
3251 in the original i2 again plus an invalid insn (which we delete).
3252 The net effect is only to move instructions around, which makes
3253 debug info less accurate.
3255 Also check the case where the first SET's destination is unused.
3256 That would not cause incorrect code, but does cause an unneeded
3259 if (insn_code_number < 0
3260 && !(added_sets_2 && i1 == 0)
3261 && GET_CODE (newpat) == PARALLEL
3262 && XVECLEN (newpat, 0) == 2
3263 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3264 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3265 && asm_noperands (newpat) < 0)
3267 rtx set0 = XVECEXP (newpat, 0, 0);
3268 rtx set1 = XVECEXP (newpat, 0, 1);
3270 if (((REG_P (SET_DEST (set1))
3271 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3272 || (GET_CODE (SET_DEST (set1)) == SUBREG
3273 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3274 && insn_nothrow_p (i3)
3275 && !side_effects_p (SET_SRC (set1)))
3278 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3281 else if (((REG_P (SET_DEST (set0))
3282 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3283 || (GET_CODE (SET_DEST (set0)) == SUBREG
3284 && find_reg_note (i3, REG_UNUSED,
3285 SUBREG_REG (SET_DEST (set0)))))
3286 && insn_nothrow_p (i3)
3287 && !side_effects_p (SET_SRC (set0)))
3290 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3292 if (insn_code_number >= 0)
3293 changed_i3_dest = 1;
3297 /* If we were combining three insns and the result is a simple SET
3298 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3299 insns. There are two ways to do this. It can be split using a
3300 machine-specific method (like when you have an addition of a large
3301 constant) or by combine in the function find_split_point. */
3303 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3304 && asm_noperands (newpat) < 0)
3306 rtx parallel, m_split, *split;
3308 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3309 use I2DEST as a scratch register will help. In the latter case,
3310 convert I2DEST to the mode of the source of NEWPAT if we can. */
3312 m_split = combine_split_insns (newpat, i3);
3314 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3315 inputs of NEWPAT. */
3317 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3318 possible to try that as a scratch reg. This would require adding
3319 more code to make it work though. */
3321 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3323 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3325 /* First try to split using the original register as a
3326 scratch register. */
3327 parallel = gen_rtx_PARALLEL (VOIDmode,
3328 gen_rtvec (2, newpat,
3329 gen_rtx_CLOBBER (VOIDmode,
3331 m_split = combine_split_insns (parallel, i3);
3333 /* If that didn't work, try changing the mode of I2DEST if
3336 && new_mode != GET_MODE (i2dest)
3337 && new_mode != VOIDmode
3338 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3340 enum machine_mode old_mode = GET_MODE (i2dest);
3343 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3344 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3347 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3348 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3351 parallel = (gen_rtx_PARALLEL
3353 gen_rtvec (2, newpat,
3354 gen_rtx_CLOBBER (VOIDmode,
3356 m_split = combine_split_insns (parallel, i3);
3359 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3363 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3364 buf = undobuf.undos;
3365 undobuf.undos = buf->next;
3366 buf->next = undobuf.frees;
3367 undobuf.frees = buf;
3371 i2scratch = m_split != 0;
3374 /* If recog_for_combine has discarded clobbers, try to use them
3375 again for the split. */
3376 if (m_split == 0 && newpat_vec_with_clobbers)
3378 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3379 m_split = combine_split_insns (parallel, i3);
3382 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3384 m_split = PATTERN (m_split);
3385 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3386 if (insn_code_number >= 0)
3389 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3390 && (next_real_insn (i2) == i3
3391 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3394 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3395 newi2pat = PATTERN (m_split);
3397 i3set = single_set (NEXT_INSN (m_split));
3398 i2set = single_set (m_split);
3400 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3402 /* If I2 or I3 has multiple SETs, we won't know how to track
3403 register status, so don't use these insns. If I2's destination
3404 is used between I2 and I3, we also can't use these insns. */
3406 if (i2_code_number >= 0 && i2set && i3set
3407 && (next_real_insn (i2) == i3
3408 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3409 insn_code_number = recog_for_combine (&newi3pat, i3,
3411 if (insn_code_number >= 0)
3414 /* It is possible that both insns now set the destination of I3.
3415 If so, we must show an extra use of it. */
3417 if (insn_code_number >= 0)
3419 rtx new_i3_dest = SET_DEST (i3set);
3420 rtx new_i2_dest = SET_DEST (i2set);
3422 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3423 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3424 || GET_CODE (new_i3_dest) == SUBREG)
3425 new_i3_dest = XEXP (new_i3_dest, 0);
3427 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3428 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3429 || GET_CODE (new_i2_dest) == SUBREG)
3430 new_i2_dest = XEXP (new_i2_dest, 0);
3432 if (REG_P (new_i3_dest)
3433 && REG_P (new_i2_dest)
3434 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3435 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3439 /* If we can split it and use I2DEST, go ahead and see if that
3440 helps things be recognized. Verify that none of the registers
3441 are set between I2 and I3. */
3442 if (insn_code_number < 0
3443 && (split = find_split_point (&newpat, i3, false)) != 0
3447 /* We need I2DEST in the proper mode. If it is a hard register
3448 or the only use of a pseudo, we can change its mode.
3449 Make sure we don't change a hard register to have a mode that
3450 isn't valid for it, or change the number of registers. */
3451 && (GET_MODE (*split) == GET_MODE (i2dest)
3452 || GET_MODE (*split) == VOIDmode
3453 || can_change_dest_mode (i2dest, added_sets_2,
3455 && (next_real_insn (i2) == i3
3456 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3457 /* We can't overwrite I2DEST if its value is still used by
3459 && ! reg_referenced_p (i2dest, newpat))
3461 rtx newdest = i2dest;
3462 enum rtx_code split_code = GET_CODE (*split);
3463 enum machine_mode split_mode = GET_MODE (*split);
3464 bool subst_done = false;
3465 newi2pat = NULL_RTX;
3469 /* *SPLIT may be part of I2SRC, so make sure we have the
3470 original expression around for later debug processing.
3471 We should not need I2SRC any more in other cases. */
3472 if (MAY_HAVE_DEBUG_INSNS)
3473 i2src = copy_rtx (i2src);
3477 /* Get NEWDEST as a register in the proper mode. We have already
3478 validated that we can do this. */
3479 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3481 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3482 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3485 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3486 newdest = regno_reg_rtx[REGNO (i2dest)];
3490 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3491 an ASHIFT. This can occur if it was inside a PLUS and hence
3492 appeared to be a memory address. This is a kludge. */
3493 if (split_code == MULT
3494 && CONST_INT_P (XEXP (*split, 1))
3495 && INTVAL (XEXP (*split, 1)) > 0
3496 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3498 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3499 XEXP (*split, 0), GEN_INT (i)));
3500 /* Update split_code because we may not have a multiply
3502 split_code = GET_CODE (*split);
3505 #ifdef INSN_SCHEDULING
3506 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3507 be written as a ZERO_EXTEND. */
3508 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3510 #ifdef LOAD_EXTEND_OP
3511 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3512 what it really is. */
3513 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3515 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3516 SUBREG_REG (*split)));
3519 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3520 SUBREG_REG (*split)));
3524 /* Attempt to split binary operators using arithmetic identities. */
3525 if (BINARY_P (SET_SRC (newpat))
3526 && split_mode == GET_MODE (SET_SRC (newpat))
3527 && ! side_effects_p (SET_SRC (newpat)))
3529 rtx setsrc = SET_SRC (newpat);
3530 enum machine_mode mode = GET_MODE (setsrc);
3531 enum rtx_code code = GET_CODE (setsrc);
3532 rtx src_op0 = XEXP (setsrc, 0);
3533 rtx src_op1 = XEXP (setsrc, 1);
3535 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3536 if (rtx_equal_p (src_op0, src_op1))
3538 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3539 SUBST (XEXP (setsrc, 0), newdest);
3540 SUBST (XEXP (setsrc, 1), newdest);
3543 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3544 else if ((code == PLUS || code == MULT)
3545 && GET_CODE (src_op0) == code
3546 && GET_CODE (XEXP (src_op0, 0)) == code
3547 && (INTEGRAL_MODE_P (mode)
3548 || (FLOAT_MODE_P (mode)
3549 && flag_unsafe_math_optimizations)))
3551 rtx p = XEXP (XEXP (src_op0, 0), 0);
3552 rtx q = XEXP (XEXP (src_op0, 0), 1);
3553 rtx r = XEXP (src_op0, 1);
3556 /* Split both "((X op Y) op X) op Y" and
3557 "((X op Y) op Y) op X" as "T op T" where T is
3559 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3560 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3562 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3564 SUBST (XEXP (setsrc, 0), newdest);
3565 SUBST (XEXP (setsrc, 1), newdest);
3568 /* Split "((X op X) op Y) op Y)" as "T op T" where
3570 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3572 rtx tmp = simplify_gen_binary (code, mode, p, r);
3573 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3574 SUBST (XEXP (setsrc, 0), newdest);
3575 SUBST (XEXP (setsrc, 1), newdest);
3583 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3584 SUBST (*split, newdest);
3587 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3589 /* recog_for_combine might have added CLOBBERs to newi2pat.
3590 Make sure NEWPAT does not depend on the clobbered regs. */
3591 if (GET_CODE (newi2pat) == PARALLEL)
3592 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3593 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3595 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3596 if (reg_overlap_mentioned_p (reg, newpat))
3603 /* If the split point was a MULT and we didn't have one before,
3604 don't use one now. */
3605 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3606 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3610 /* Check for a case where we loaded from memory in a narrow mode and
3611 then sign extended it, but we need both registers. In that case,
3612 we have a PARALLEL with both loads from the same memory location.
3613 We can split this into a load from memory followed by a register-register
3614 copy. This saves at least one insn, more if register allocation can
3617 We cannot do this if the destination of the first assignment is a
3618 condition code register or cc0. We eliminate this case by making sure
3619 the SET_DEST and SET_SRC have the same mode.
3621 We cannot do this if the destination of the second assignment is
3622 a register that we have already assumed is zero-extended. Similarly
3623 for a SUBREG of such a register. */
3625 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3626 && GET_CODE (newpat) == PARALLEL
3627 && XVECLEN (newpat, 0) == 2
3628 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3629 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3630 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3631 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3632 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3633 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3634 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3635 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3637 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3638 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3639 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3641 && VEC_index (reg_stat_type, reg_stat,
3642 REGNO (temp))->nonzero_bits != 0
3643 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3644 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3645 && (VEC_index (reg_stat_type, reg_stat,
3646 REGNO (temp))->nonzero_bits
3647 != GET_MODE_MASK (word_mode))))
3648 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3649 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3651 && VEC_index (reg_stat_type, reg_stat,
3652 REGNO (temp))->nonzero_bits != 0
3653 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3654 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3655 && (VEC_index (reg_stat_type, reg_stat,
3656 REGNO (temp))->nonzero_bits
3657 != GET_MODE_MASK (word_mode)))))
3658 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3659 SET_SRC (XVECEXP (newpat, 0, 1)))
3660 && ! find_reg_note (i3, REG_UNUSED,
3661 SET_DEST (XVECEXP (newpat, 0, 0))))
3665 newi2pat = XVECEXP (newpat, 0, 0);
3666 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3667 newpat = XVECEXP (newpat, 0, 1);
3668 SUBST (SET_SRC (newpat),
3669 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3670 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3672 if (i2_code_number >= 0)
3673 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3675 if (insn_code_number >= 0)
3679 /* Similarly, check for a case where we have a PARALLEL of two independent
3680 SETs but we started with three insns. In this case, we can do the sets
3681 as two separate insns. This case occurs when some SET allows two
3682 other insns to combine, but the destination of that SET is still live. */
3684 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3685 && GET_CODE (newpat) == PARALLEL
3686 && XVECLEN (newpat, 0) == 2
3687 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3688 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3689 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3690 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3691 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3692 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3693 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3695 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3696 XVECEXP (newpat, 0, 0))
3697 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3698 XVECEXP (newpat, 0, 1))
3699 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3700 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3702 /* We cannot split the parallel into two sets if both sets
3704 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3705 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3709 /* Normally, it doesn't matter which of the two is done first,
3710 but it does if one references cc0. In that case, it has to
3713 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3715 newi2pat = XVECEXP (newpat, 0, 0);
3716 newpat = XVECEXP (newpat, 0, 1);
3721 newi2pat = XVECEXP (newpat, 0, 1);
3722 newpat = XVECEXP (newpat, 0, 0);
3725 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3727 if (i2_code_number >= 0)
3729 /* recog_for_combine might have added CLOBBERs to newi2pat.
3730 Make sure NEWPAT does not depend on the clobbered regs. */
3731 if (GET_CODE (newi2pat) == PARALLEL)
3733 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3734 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3736 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3737 if (reg_overlap_mentioned_p (reg, newpat))
3743 /* CLOBBERs on newi2pat prevent it going first.
3744 Try the other order of the insns if possible. */
3746 newpat = XVECEXP (newi2pat, 0, 0);
3749 if (reg_referenced_p (cc0_rtx, newpat))
3756 i2_code_number = recog_for_combine (&newi2pat, i2,
3758 if (i2_code_number < 0)
3764 if (GET_CODE (newi2pat) == PARALLEL)
3765 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3766 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3768 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3769 if (reg_overlap_mentioned_p (reg, newpat))
3778 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3782 /* If it still isn't recognized, fail and change things back the way they
3784 if ((insn_code_number < 0
3785 /* Is the result a reasonable ASM_OPERANDS? */
3786 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3792 /* If we had to change another insn, make sure it is valid also. */
3793 if (undobuf.other_insn)
3795 CLEAR_HARD_REG_SET (newpat_used_regs);
3797 other_pat = PATTERN (undobuf.other_insn);
3798 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3801 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3809 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3810 they are adjacent to each other or not. */
3812 rtx p = prev_nonnote_insn (i3);
3813 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3814 && sets_cc0_p (newi2pat))
3822 /* Only allow this combination if insn_rtx_costs reports that the
3823 replacement instructions are cheaper than the originals. */
3824 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3830 if (MAY_HAVE_DEBUG_INSNS)
3834 for (undo = undobuf.undos; undo; undo = undo->next)
3835 if (undo->kind == UNDO_MODE)
3837 rtx reg = *undo->where.r;
3838 enum machine_mode new_mode = GET_MODE (reg);
3839 enum machine_mode old_mode = undo->old_contents.m;
3841 /* Temporarily revert mode back. */
3842 adjust_reg_mode (reg, old_mode);
3844 if (reg == i2dest && i2scratch)
3846 /* If we used i2dest as a scratch register with a
3847 different mode, substitute it for the original
3848 i2src while its original mode is temporarily
3849 restored, and then clear i2scratch so that we don't
3850 do it again later. */
3851 propagate_for_debug (i2, i3, reg, i2src, false);
3853 /* Put back the new mode. */
3854 adjust_reg_mode (reg, new_mode);
3858 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3869 last = undobuf.other_insn;
3873 /* We're dealing with a reg that changed mode but not
3874 meaning, so we want to turn it into a subreg for
3875 the new mode. However, because of REG sharing and
3876 because its mode had already changed, we have to do
3877 it in two steps. First, replace any debug uses of
3878 reg, with its original mode temporarily restored,
3879 with this copy we have created; then, replace the
3880 copy with the SUBREG of the original shared reg,
3881 once again changed to the new mode. */
3882 propagate_for_debug (first, last, reg, tempreg, false);
3883 adjust_reg_mode (reg, new_mode);
3884 propagate_for_debug (first, last, tempreg,
3885 lowpart_subreg (old_mode, reg, new_mode),
3891 /* If we will be able to accept this, we have made a
3892 change to the destination of I3. This requires us to
3893 do a few adjustments. */
3895 if (changed_i3_dest)
3897 PATTERN (i3) = newpat;
3898 adjust_for_new_dest (i3);
3901 /* We now know that we can do this combination. Merge the insns and
3902 update the status of registers and LOG_LINKS. */
3904 if (undobuf.other_insn)
3908 PATTERN (undobuf.other_insn) = other_pat;
3910 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3911 are still valid. Then add any non-duplicate notes added by
3912 recog_for_combine. */
3913 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3915 next = XEXP (note, 1);
3917 if (REG_NOTE_KIND (note) == REG_UNUSED
3918 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3919 remove_note (undobuf.other_insn, note);
3922 distribute_notes (new_other_notes, undobuf.other_insn,
3923 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3933 /* I3 now uses what used to be its destination and which is now
3934 I2's destination. This requires us to do a few adjustments. */
3935 PATTERN (i3) = newpat;
3936 adjust_for_new_dest (i3);
3938 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3941 However, some later insn might be using I2's dest and have
3942 a LOG_LINK pointing at I3. We must remove this link.
3943 The simplest way to remove the link is to point it at I1,
3944 which we know will be a NOTE. */
3946 /* newi2pat is usually a SET here; however, recog_for_combine might
3947 have added some clobbers. */
3948 if (GET_CODE (newi2pat) == PARALLEL)
3949 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3951 ni2dest = SET_DEST (newi2pat);
3953 for (insn = NEXT_INSN (i3);
3954 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3955 || insn != BB_HEAD (this_basic_block->next_bb));
3956 insn = NEXT_INSN (insn))
3958 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3960 for (link = LOG_LINKS (insn); link;
3961 link = XEXP (link, 1))
3962 if (XEXP (link, 0) == i3)
3963 XEXP (link, 0) = i1;
3971 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
3972 rtx i3links, i2links, i1links = 0, i0links = 0;
3976 /* Compute which registers we expect to eliminate. newi2pat may be setting
3977 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3978 same as i3dest, in which case newi2pat may be setting i1dest. */
3979 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3980 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
3983 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
3984 || (newi2pat && reg_set_p (i1dest, newi2pat))
3987 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
3988 || (newi2pat && reg_set_p (i0dest, newi2pat))
3992 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3994 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3995 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3997 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3999 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4001 /* Ensure that we do not have something that should not be shared but
4002 occurs multiple times in the new insns. Check this by first
4003 resetting all the `used' flags and then copying anything is shared. */
4005 reset_used_flags (i3notes);
4006 reset_used_flags (i2notes);
4007 reset_used_flags (i1notes);
4008 reset_used_flags (i0notes);
4009 reset_used_flags (newpat);
4010 reset_used_flags (newi2pat);
4011 if (undobuf.other_insn)
4012 reset_used_flags (PATTERN (undobuf.other_insn));
4014 i3notes = copy_rtx_if_shared (i3notes);
4015 i2notes = copy_rtx_if_shared (i2notes);
4016 i1notes = copy_rtx_if_shared (i1notes);
4017 i0notes = copy_rtx_if_shared (i0notes);
4018 newpat = copy_rtx_if_shared (newpat);
4019 newi2pat = copy_rtx_if_shared (newi2pat);
4020 if (undobuf.other_insn)
4021 reset_used_flags (PATTERN (undobuf.other_insn));
4023 INSN_CODE (i3) = insn_code_number;
4024 PATTERN (i3) = newpat;
4026 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4028 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4030 reset_used_flags (call_usage);
4031 call_usage = copy_rtx (call_usage);
4035 /* I2SRC must still be meaningful at this point. Some splitting
4036 operations can invalidate I2SRC, but those operations do not
4039 replace_rtx (call_usage, i2dest, i2src);
4043 replace_rtx (call_usage, i1dest, i1src);
4045 replace_rtx (call_usage, i0dest, i0src);
4047 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4050 if (undobuf.other_insn)
4051 INSN_CODE (undobuf.other_insn) = other_code_number;
4053 /* We had one special case above where I2 had more than one set and
4054 we replaced a destination of one of those sets with the destination
4055 of I3. In that case, we have to update LOG_LINKS of insns later
4056 in this basic block. Note that this (expensive) case is rare.
4058 Also, in this case, we must pretend that all REG_NOTEs for I2
4059 actually came from I3, so that REG_UNUSED notes from I2 will be
4060 properly handled. */
4062 if (i3_subst_into_i2)
4064 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4065 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4066 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4067 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4068 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4069 && ! find_reg_note (i2, REG_UNUSED,
4070 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4071 for (temp = NEXT_INSN (i2);
4072 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4073 || BB_HEAD (this_basic_block) != temp);
4074 temp = NEXT_INSN (temp))
4075 if (temp != i3 && INSN_P (temp))
4076 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
4077 if (XEXP (link, 0) == i2)
4078 XEXP (link, 0) = i3;
4083 while (XEXP (link, 1))
4084 link = XEXP (link, 1);
4085 XEXP (link, 1) = i2notes;
4099 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4100 propagate_for_debug (i2, i3, i2dest, i2src, false);
4101 INSN_CODE (i2) = i2_code_number;
4102 PATTERN (i2) = newi2pat;
4106 if (MAY_HAVE_DEBUG_INSNS && i2src)
4107 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
4108 SET_INSN_DELETED (i2);
4115 if (MAY_HAVE_DEBUG_INSNS)
4116 propagate_for_debug (i1, i3, i1dest, i1src, false);
4117 SET_INSN_DELETED (i1);
4124 if (MAY_HAVE_DEBUG_INSNS)
4125 propagate_for_debug (i0, i3, i0dest, i0src, false);
4126 SET_INSN_DELETED (i0);
4129 /* Get death notes for everything that is now used in either I3 or
4130 I2 and used to die in a previous insn. If we built two new
4131 patterns, move from I1 to I2 then I2 to I3 so that we get the
4132 proper movement on registers that I2 modifies. */
4135 from_luid = DF_INSN_LUID (i0);
4137 from_luid = DF_INSN_LUID (i1);
4139 from_luid = DF_INSN_LUID (i2);
4141 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4142 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4144 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4146 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4147 elim_i2, elim_i1, elim_i0);
4149 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4150 elim_i2, elim_i1, elim_i0);
4152 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4153 elim_i2, elim_i1, elim_i0);
4155 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4156 elim_i2, elim_i1, elim_i0);
4158 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4159 elim_i2, elim_i1, elim_i0);
4161 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4162 know these are REG_UNUSED and want them to go to the desired insn,
4163 so we always pass it as i3. */
4165 if (newi2pat && new_i2_notes)
4166 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4170 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4173 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4174 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4175 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4176 in that case, it might delete I2. Similarly for I2 and I1.
4177 Show an additional death due to the REG_DEAD note we make here. If
4178 we discard it in distribute_notes, we will decrement it again. */
4182 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4183 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4185 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4187 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4189 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4190 elim_i2, elim_i1, elim_i0);
4193 if (i2dest_in_i2src)
4195 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4196 if (newi2pat && reg_set_p (i2dest, newi2pat))
4197 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4198 NULL_RTX, NULL_RTX);
4200 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4201 NULL_RTX, NULL_RTX, NULL_RTX);
4204 if (i1dest_in_i1src)
4206 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4207 if (newi2pat && reg_set_p (i1dest, newi2pat))
4208 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4209 NULL_RTX, NULL_RTX);
4211 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4212 NULL_RTX, NULL_RTX, NULL_RTX);
4215 if (i0dest_in_i0src)
4217 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4218 if (newi2pat && reg_set_p (i0dest, newi2pat))
4219 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4220 NULL_RTX, NULL_RTX);
4222 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4223 NULL_RTX, NULL_RTX, NULL_RTX);
4226 distribute_links (i3links);
4227 distribute_links (i2links);
4228 distribute_links (i1links);
4229 distribute_links (i0links);
4234 rtx i2_insn = 0, i2_val = 0, set;
4236 /* The insn that used to set this register doesn't exist, and
4237 this life of the register may not exist either. See if one of
4238 I3's links points to an insn that sets I2DEST. If it does,
4239 that is now the last known value for I2DEST. If we don't update
4240 this and I2 set the register to a value that depended on its old
4241 contents, we will get confused. If this insn is used, thing
4242 will be set correctly in combine_instructions. */
4244 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4245 if ((set = single_set (XEXP (link, 0))) != 0
4246 && rtx_equal_p (i2dest, SET_DEST (set)))
4247 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
4249 record_value_for_reg (i2dest, i2_insn, i2_val);
4251 /* If the reg formerly set in I2 died only once and that was in I3,
4252 zero its use count so it won't make `reload' do any work. */
4254 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4255 && ! i2dest_in_i2src)
4257 regno = REGNO (i2dest);
4258 INC_REG_N_SETS (regno, -1);
4262 if (i1 && REG_P (i1dest))
4265 rtx i1_insn = 0, i1_val = 0, set;
4267 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4268 if ((set = single_set (XEXP (link, 0))) != 0
4269 && rtx_equal_p (i1dest, SET_DEST (set)))
4270 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4272 record_value_for_reg (i1dest, i1_insn, i1_val);
4274 regno = REGNO (i1dest);
4275 if (! added_sets_1 && ! i1dest_in_i1src)
4276 INC_REG_N_SETS (regno, -1);
4279 if (i0 && REG_P (i0dest))
4282 rtx i0_insn = 0, i0_val = 0, set;
4284 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4285 if ((set = single_set (XEXP (link, 0))) != 0
4286 && rtx_equal_p (i0dest, SET_DEST (set)))
4287 i0_insn = XEXP (link, 0), i0_val = SET_SRC (set);
4289 record_value_for_reg (i0dest, i0_insn, i0_val);
4291 regno = REGNO (i0dest);
4292 if (! added_sets_0 && ! i0dest_in_i0src)
4293 INC_REG_N_SETS (regno, -1);
4296 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4297 been made to this insn. The order of
4298 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4299 can affect nonzero_bits of newpat */
4301 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4302 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4305 if (undobuf.other_insn != NULL_RTX)
4309 fprintf (dump_file, "modifying other_insn ");
4310 dump_insn_slim (dump_file, undobuf.other_insn);
4312 df_insn_rescan (undobuf.other_insn);
4315 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4319 fprintf (dump_file, "modifying insn i1 ");
4320 dump_insn_slim (dump_file, i0);
4322 df_insn_rescan (i0);
4325 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4329 fprintf (dump_file, "modifying insn i1 ");
4330 dump_insn_slim (dump_file, i1);
4332 df_insn_rescan (i1);
4335 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4339 fprintf (dump_file, "modifying insn i2 ");
4340 dump_insn_slim (dump_file, i2);
4342 df_insn_rescan (i2);
4345 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4349 fprintf (dump_file, "modifying insn i3 ");
4350 dump_insn_slim (dump_file, i3);
4352 df_insn_rescan (i3);
4355 /* Set new_direct_jump_p if a new return or simple jump instruction
4356 has been created. Adjust the CFG accordingly. */
4358 if (returnjump_p (i3) || any_uncondjump_p (i3))
4360 *new_direct_jump_p = 1;
4361 mark_jump_label (PATTERN (i3), i3, 0);
4362 update_cfg_for_uncondjump (i3);
4365 if (undobuf.other_insn != NULL_RTX
4366 && (returnjump_p (undobuf.other_insn)
4367 || any_uncondjump_p (undobuf.other_insn)))
4369 *new_direct_jump_p = 1;
4370 update_cfg_for_uncondjump (undobuf.other_insn);
4373 /* A noop might also need cleaning up of CFG, if it comes from the
4374 simplification of a jump. */
4375 if (GET_CODE (newpat) == SET
4376 && SET_SRC (newpat) == pc_rtx
4377 && SET_DEST (newpat) == pc_rtx)
4379 *new_direct_jump_p = 1;
4380 update_cfg_for_uncondjump (i3);
4383 combine_successes++;
4386 if (added_links_insn
4387 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4388 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4389 return added_links_insn;
4391 return newi2pat ? i2 : i3;
4394 /* Undo all the modifications recorded in undobuf. */
4399 struct undo *undo, *next;
4401 for (undo = undobuf.undos; undo; undo = next)
4407 *undo->where.r = undo->old_contents.r;
4410 *undo->where.i = undo->old_contents.i;
4413 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4419 undo->next = undobuf.frees;
4420 undobuf.frees = undo;
4426 /* We've committed to accepting the changes we made. Move all
4427 of the undos to the free list. */
4432 struct undo *undo, *next;
4434 for (undo = undobuf.undos; undo; undo = next)
4437 undo->next = undobuf.frees;
4438 undobuf.frees = undo;
4443 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4444 where we have an arithmetic expression and return that point. LOC will
4447 try_combine will call this function to see if an insn can be split into
4451 find_split_point (rtx *loc, rtx insn, bool set_src)
4454 enum rtx_code code = GET_CODE (x);
4456 unsigned HOST_WIDE_INT len = 0;
4457 HOST_WIDE_INT pos = 0;
4459 rtx inner = NULL_RTX;
4461 /* First special-case some codes. */
4465 #ifdef INSN_SCHEDULING
4466 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4468 if (MEM_P (SUBREG_REG (x)))
4471 return find_split_point (&SUBREG_REG (x), insn, false);
4475 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4476 using LO_SUM and HIGH. */
4477 if (GET_CODE (XEXP (x, 0)) == CONST
4478 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4480 enum machine_mode address_mode
4481 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4484 gen_rtx_LO_SUM (address_mode,
4485 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4487 return &XEXP (XEXP (x, 0), 0);
4491 /* If we have a PLUS whose second operand is a constant and the
4492 address is not valid, perhaps will can split it up using
4493 the machine-specific way to split large constants. We use
4494 the first pseudo-reg (one of the virtual regs) as a placeholder;
4495 it will not remain in the result. */
4496 if (GET_CODE (XEXP (x, 0)) == PLUS
4497 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4498 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4499 MEM_ADDR_SPACE (x)))
4501 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4502 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4506 /* This should have produced two insns, each of which sets our
4507 placeholder. If the source of the second is a valid address,
4508 we can make put both sources together and make a split point
4512 && NEXT_INSN (seq) != NULL_RTX
4513 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4514 && NONJUMP_INSN_P (seq)
4515 && GET_CODE (PATTERN (seq)) == SET
4516 && SET_DEST (PATTERN (seq)) == reg
4517 && ! reg_mentioned_p (reg,
4518 SET_SRC (PATTERN (seq)))
4519 && NONJUMP_INSN_P (NEXT_INSN (seq))
4520 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4521 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4522 && memory_address_addr_space_p
4523 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4524 MEM_ADDR_SPACE (x)))
4526 rtx src1 = SET_SRC (PATTERN (seq));
4527 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4529 /* Replace the placeholder in SRC2 with SRC1. If we can
4530 find where in SRC2 it was placed, that can become our
4531 split point and we can replace this address with SRC2.
4532 Just try two obvious places. */
4534 src2 = replace_rtx (src2, reg, src1);
4536 if (XEXP (src2, 0) == src1)
4537 split = &XEXP (src2, 0);
4538 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4539 && XEXP (XEXP (src2, 0), 0) == src1)
4540 split = &XEXP (XEXP (src2, 0), 0);
4544 SUBST (XEXP (x, 0), src2);
4549 /* If that didn't work, perhaps the first operand is complex and
4550 needs to be computed separately, so make a split point there.
4551 This will occur on machines that just support REG + CONST
4552 and have a constant moved through some previous computation. */
4554 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4555 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4556 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4557 return &XEXP (XEXP (x, 0), 0);
4560 /* If we have a PLUS whose first operand is complex, try computing it
4561 separately by making a split there. */
4562 if (GET_CODE (XEXP (x, 0)) == PLUS
4563 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4565 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4566 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4567 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4568 return &XEXP (XEXP (x, 0), 0);
4573 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4574 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4575 we need to put the operand into a register. So split at that
4578 if (SET_DEST (x) == cc0_rtx
4579 && GET_CODE (SET_SRC (x)) != COMPARE
4580 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4581 && !OBJECT_P (SET_SRC (x))
4582 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4583 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4584 return &SET_SRC (x);
4587 /* See if we can split SET_SRC as it stands. */
4588 split = find_split_point (&SET_SRC (x), insn, true);
4589 if (split && split != &SET_SRC (x))
4592 /* See if we can split SET_DEST as it stands. */
4593 split = find_split_point (&SET_DEST (x), insn, false);
4594 if (split && split != &SET_DEST (x))
4597 /* See if this is a bitfield assignment with everything constant. If
4598 so, this is an IOR of an AND, so split it into that. */
4599 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4600 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4601 <= HOST_BITS_PER_WIDE_INT)
4602 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4603 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4604 && CONST_INT_P (SET_SRC (x))
4605 && ((INTVAL (XEXP (SET_DEST (x), 1))
4606 + INTVAL (XEXP (SET_DEST (x), 2)))
4607 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4608 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4610 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4611 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4612 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4613 rtx dest = XEXP (SET_DEST (x), 0);
4614 enum machine_mode mode = GET_MODE (dest);
4615 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4618 if (BITS_BIG_ENDIAN)
4619 pos = GET_MODE_BITSIZE (mode) - len - pos;
4621 or_mask = gen_int_mode (src << pos, mode);
4624 simplify_gen_binary (IOR, mode, dest, or_mask));
4627 rtx negmask = gen_int_mode (~(mask << pos), mode);
4629 simplify_gen_binary (IOR, mode,
4630 simplify_gen_binary (AND, mode,
4635 SUBST (SET_DEST (x), dest);
4637 split = find_split_point (&SET_SRC (x), insn, true);
4638 if (split && split != &SET_SRC (x))
4642 /* Otherwise, see if this is an operation that we can split into two.
4643 If so, try to split that. */
4644 code = GET_CODE (SET_SRC (x));
4649 /* If we are AND'ing with a large constant that is only a single
4650 bit and the result is only being used in a context where we
4651 need to know if it is zero or nonzero, replace it with a bit
4652 extraction. This will avoid the large constant, which might
4653 have taken more than one insn to make. If the constant were
4654 not a valid argument to the AND but took only one insn to make,
4655 this is no worse, but if it took more than one insn, it will
4658 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4659 && REG_P (XEXP (SET_SRC (x), 0))
4660 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4661 && REG_P (SET_DEST (x))
4662 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4663 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4664 && XEXP (*split, 0) == SET_DEST (x)
4665 && XEXP (*split, 1) == const0_rtx)
4667 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4668 XEXP (SET_SRC (x), 0),
4669 pos, NULL_RTX, 1, 1, 0, 0);
4670 if (extraction != 0)
4672 SUBST (SET_SRC (x), extraction);
4673 return find_split_point (loc, insn, false);
4679 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4680 is known to be on, this can be converted into a NEG of a shift. */
4681 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4682 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4683 && 1 <= (pos = exact_log2
4684 (nonzero_bits (XEXP (SET_SRC (x), 0),
4685 GET_MODE (XEXP (SET_SRC (x), 0))))))
4687 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4691 gen_rtx_LSHIFTRT (mode,
4692 XEXP (SET_SRC (x), 0),
4695 split = find_split_point (&SET_SRC (x), insn, true);
4696 if (split && split != &SET_SRC (x))
4702 inner = XEXP (SET_SRC (x), 0);
4704 /* We can't optimize if either mode is a partial integer
4705 mode as we don't know how many bits are significant
4707 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4708 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4712 len = GET_MODE_BITSIZE (GET_MODE (inner));
4718 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4719 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4721 inner = XEXP (SET_SRC (x), 0);
4722 len = INTVAL (XEXP (SET_SRC (x), 1));
4723 pos = INTVAL (XEXP (SET_SRC (x), 2));
4725 if (BITS_BIG_ENDIAN)
4726 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4727 unsignedp = (code == ZERO_EXTRACT);
4735 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4737 enum machine_mode mode = GET_MODE (SET_SRC (x));
4739 /* For unsigned, we have a choice of a shift followed by an
4740 AND or two shifts. Use two shifts for field sizes where the
4741 constant might be too large. We assume here that we can
4742 always at least get 8-bit constants in an AND insn, which is
4743 true for every current RISC. */
4745 if (unsignedp && len <= 8)
4750 (mode, gen_lowpart (mode, inner),
4752 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4754 split = find_split_point (&SET_SRC (x), insn, true);
4755 if (split && split != &SET_SRC (x))
4762 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4763 gen_rtx_ASHIFT (mode,
4764 gen_lowpart (mode, inner),
4765 GEN_INT (GET_MODE_BITSIZE (mode)
4767 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4769 split = find_split_point (&SET_SRC (x), insn, true);
4770 if (split && split != &SET_SRC (x))
4775 /* See if this is a simple operation with a constant as the second
4776 operand. It might be that this constant is out of range and hence
4777 could be used as a split point. */
4778 if (BINARY_P (SET_SRC (x))
4779 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4780 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4781 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4782 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4783 return &XEXP (SET_SRC (x), 1);
4785 /* Finally, see if this is a simple operation with its first operand
4786 not in a register. The operation might require this operand in a
4787 register, so return it as a split point. We can always do this
4788 because if the first operand were another operation, we would have
4789 already found it as a split point. */
4790 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4791 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4792 return &XEXP (SET_SRC (x), 0);
4798 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4799 it is better to write this as (not (ior A B)) so we can split it.
4800 Similarly for IOR. */
4801 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4804 gen_rtx_NOT (GET_MODE (x),
4805 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4807 XEXP (XEXP (x, 0), 0),
4808 XEXP (XEXP (x, 1), 0))));
4809 return find_split_point (loc, insn, set_src);
4812 /* Many RISC machines have a large set of logical insns. If the
4813 second operand is a NOT, put it first so we will try to split the
4814 other operand first. */
4815 if (GET_CODE (XEXP (x, 1)) == NOT)
4817 rtx tem = XEXP (x, 0);
4818 SUBST (XEXP (x, 0), XEXP (x, 1));
4819 SUBST (XEXP (x, 1), tem);
4825 /* Canonicalization can produce (minus A (mult B C)), where C is a
4826 constant. It may be better to try splitting (plus (mult B -C) A)
4827 instead if this isn't a multiply by a power of two. */
4828 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4829 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4830 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4832 enum machine_mode mode = GET_MODE (x);
4833 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4834 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4835 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4836 XEXP (XEXP (x, 1), 0),
4837 GEN_INT (other_int)),
4839 return find_split_point (loc, insn, set_src);
4842 /* Split at a multiply-accumulate instruction. However if this is
4843 the SET_SRC, we likely do not have such an instruction and it's
4844 worthless to try this split. */
4845 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4852 /* Otherwise, select our actions depending on our rtx class. */
4853 switch (GET_RTX_CLASS (code))
4855 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4857 split = find_split_point (&XEXP (x, 2), insn, false);
4860 /* ... fall through ... */
4862 case RTX_COMM_ARITH:
4864 case RTX_COMM_COMPARE:
4865 split = find_split_point (&XEXP (x, 1), insn, false);
4868 /* ... fall through ... */
4870 /* Some machines have (and (shift ...) ...) insns. If X is not
4871 an AND, but XEXP (X, 0) is, use it as our split point. */
4872 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4873 return &XEXP (x, 0);
4875 split = find_split_point (&XEXP (x, 0), insn, false);
4881 /* Otherwise, we don't have a split point. */
4886 /* Throughout X, replace FROM with TO, and return the result.
4887 The result is TO if X is FROM;
4888 otherwise the result is X, but its contents may have been modified.
4889 If they were modified, a record was made in undobuf so that
4890 undo_all will (among other things) return X to its original state.
4892 If the number of changes necessary is too much to record to undo,
4893 the excess changes are not made, so the result is invalid.
4894 The changes already made can still be undone.
4895 undobuf.num_undo is incremented for such changes, so by testing that
4896 the caller can tell whether the result is valid.
4898 `n_occurrences' is incremented each time FROM is replaced.
4900 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4902 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4903 by copying if `n_occurrences' is nonzero. */
4906 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4908 enum rtx_code code = GET_CODE (x);
4909 enum machine_mode op0_mode = VOIDmode;
4914 /* Two expressions are equal if they are identical copies of a shared
4915 RTX or if they are both registers with the same register number
4918 #define COMBINE_RTX_EQUAL_P(X,Y) \
4920 || (REG_P (X) && REG_P (Y) \
4921 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4923 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4926 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4929 /* If X and FROM are the same register but different modes, they
4930 will not have been seen as equal above. However, the log links code
4931 will make a LOG_LINKS entry for that case. If we do nothing, we
4932 will try to rerecognize our original insn and, when it succeeds,
4933 we will delete the feeding insn, which is incorrect.
4935 So force this insn not to match in this (rare) case. */
4936 if (! in_dest && code == REG && REG_P (from)
4937 && reg_overlap_mentioned_p (x, from))
4938 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4940 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4941 of which may contain things that can be combined. */
4942 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4945 /* It is possible to have a subexpression appear twice in the insn.
4946 Suppose that FROM is a register that appears within TO.
4947 Then, after that subexpression has been scanned once by `subst',
4948 the second time it is scanned, TO may be found. If we were
4949 to scan TO here, we would find FROM within it and create a
4950 self-referent rtl structure which is completely wrong. */
4951 if (COMBINE_RTX_EQUAL_P (x, to))
4954 /* Parallel asm_operands need special attention because all of the
4955 inputs are shared across the arms. Furthermore, unsharing the
4956 rtl results in recognition failures. Failure to handle this case
4957 specially can result in circular rtl.
4959 Solve this by doing a normal pass across the first entry of the
4960 parallel, and only processing the SET_DESTs of the subsequent
4963 if (code == PARALLEL
4964 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4965 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4967 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4969 /* If this substitution failed, this whole thing fails. */
4970 if (GET_CODE (new_rtx) == CLOBBER
4971 && XEXP (new_rtx, 0) == const0_rtx)
4974 SUBST (XVECEXP (x, 0, 0), new_rtx);
4976 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4978 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4981 && GET_CODE (dest) != CC0
4982 && GET_CODE (dest) != PC)
4984 new_rtx = subst (dest, from, to, 0, unique_copy);
4986 /* If this substitution failed, this whole thing fails. */
4987 if (GET_CODE (new_rtx) == CLOBBER
4988 && XEXP (new_rtx, 0) == const0_rtx)
4991 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4997 len = GET_RTX_LENGTH (code);
4998 fmt = GET_RTX_FORMAT (code);
5000 /* We don't need to process a SET_DEST that is a register, CC0,
5001 or PC, so set up to skip this common case. All other cases
5002 where we want to suppress replacing something inside a
5003 SET_SRC are handled via the IN_DEST operand. */
5005 && (REG_P (SET_DEST (x))
5006 || GET_CODE (SET_DEST (x)) == CC0
5007 || GET_CODE (SET_DEST (x)) == PC))
5010 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5013 op0_mode = GET_MODE (XEXP (x, 0));
5015 for (i = 0; i < len; i++)
5020 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5022 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5024 new_rtx = (unique_copy && n_occurrences
5025 ? copy_rtx (to) : to);
5030 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
5033 /* If this substitution failed, this whole thing
5035 if (GET_CODE (new_rtx) == CLOBBER
5036 && XEXP (new_rtx, 0) == const0_rtx)
5040 SUBST (XVECEXP (x, i, j), new_rtx);
5043 else if (fmt[i] == 'e')
5045 /* If this is a register being set, ignore it. */
5046 new_rtx = XEXP (x, i);
5049 && (((code == SUBREG || code == ZERO_EXTRACT)
5051 || code == STRICT_LOW_PART))
5054 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5056 /* In general, don't install a subreg involving two
5057 modes not tieable. It can worsen register
5058 allocation, and can even make invalid reload
5059 insns, since the reg inside may need to be copied
5060 from in the outside mode, and that may be invalid
5061 if it is an fp reg copied in integer mode.
5063 We allow two exceptions to this: It is valid if
5064 it is inside another SUBREG and the mode of that
5065 SUBREG and the mode of the inside of TO is
5066 tieable and it is valid if X is a SET that copies
5069 if (GET_CODE (to) == SUBREG
5070 && ! MODES_TIEABLE_P (GET_MODE (to),
5071 GET_MODE (SUBREG_REG (to)))
5072 && ! (code == SUBREG
5073 && MODES_TIEABLE_P (GET_MODE (x),
5074 GET_MODE (SUBREG_REG (to))))
5076 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5079 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5081 #ifdef CANNOT_CHANGE_MODE_CLASS
5084 && REGNO (to) < FIRST_PSEUDO_REGISTER
5085 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5088 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5091 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5095 /* If we are in a SET_DEST, suppress most cases unless we
5096 have gone inside a MEM, in which case we want to
5097 simplify the address. We assume here that things that
5098 are actually part of the destination have their inner
5099 parts in the first expression. This is true for SUBREG,
5100 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5101 things aside from REG and MEM that should appear in a
5103 new_rtx = subst (XEXP (x, i), from, to,
5105 && (code == SUBREG || code == STRICT_LOW_PART
5106 || code == ZERO_EXTRACT))
5108 && i == 0), unique_copy);
5110 /* If we found that we will have to reject this combination,
5111 indicate that by returning the CLOBBER ourselves, rather than
5112 an expression containing it. This will speed things up as
5113 well as prevent accidents where two CLOBBERs are considered
5114 to be equal, thus producing an incorrect simplification. */
5116 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5119 if (GET_CODE (x) == SUBREG
5120 && (CONST_INT_P (new_rtx)
5121 || GET_CODE (new_rtx) == CONST_DOUBLE))
5123 enum machine_mode mode = GET_MODE (x);
5125 x = simplify_subreg (GET_MODE (x), new_rtx,
5126 GET_MODE (SUBREG_REG (x)),
5129 x = gen_rtx_CLOBBER (mode, const0_rtx);
5131 else if (CONST_INT_P (new_rtx)
5132 && GET_CODE (x) == ZERO_EXTEND)
5134 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5135 new_rtx, GET_MODE (XEXP (x, 0)));
5139 SUBST (XEXP (x, i), new_rtx);
5144 /* Check if we are loading something from the constant pool via float
5145 extension; in this case we would undo compress_float_constant
5146 optimization and degenerate constant load to an immediate value. */
5147 if (GET_CODE (x) == FLOAT_EXTEND
5148 && MEM_P (XEXP (x, 0))
5149 && MEM_READONLY_P (XEXP (x, 0)))
5151 rtx tmp = avoid_constant_pool_reference (x);
5156 /* Try to simplify X. If the simplification changed the code, it is likely
5157 that further simplification will help, so loop, but limit the number
5158 of repetitions that will be performed. */
5160 for (i = 0; i < 4; i++)
5162 /* If X is sufficiently simple, don't bother trying to do anything
5164 if (code != CONST_INT && code != REG && code != CLOBBER)
5165 x = combine_simplify_rtx (x, op0_mode, in_dest);
5167 if (GET_CODE (x) == code)
5170 code = GET_CODE (x);
5172 /* We no longer know the original mode of operand 0 since we
5173 have changed the form of X) */
5174 op0_mode = VOIDmode;
5180 /* Simplify X, a piece of RTL. We just operate on the expression at the
5181 outer level; call `subst' to simplify recursively. Return the new
5184 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5185 if we are inside a SET_DEST. */
5188 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5190 enum rtx_code code = GET_CODE (x);
5191 enum machine_mode mode = GET_MODE (x);
5195 /* If this is a commutative operation, put a constant last and a complex
5196 expression first. We don't need to do this for comparisons here. */
5197 if (COMMUTATIVE_ARITH_P (x)
5198 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5201 SUBST (XEXP (x, 0), XEXP (x, 1));
5202 SUBST (XEXP (x, 1), temp);
5205 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5206 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5207 things. Check for cases where both arms are testing the same
5210 Don't do anything if all operands are very simple. */
5213 && ((!OBJECT_P (XEXP (x, 0))
5214 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5215 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5216 || (!OBJECT_P (XEXP (x, 1))
5217 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5218 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5220 && (!OBJECT_P (XEXP (x, 0))
5221 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5222 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5224 rtx cond, true_rtx, false_rtx;
5226 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5228 /* If everything is a comparison, what we have is highly unlikely
5229 to be simpler, so don't use it. */
5230 && ! (COMPARISON_P (x)
5231 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5233 rtx cop1 = const0_rtx;
5234 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5236 if (cond_code == NE && COMPARISON_P (cond))
5239 /* Simplify the alternative arms; this may collapse the true and
5240 false arms to store-flag values. Be careful to use copy_rtx
5241 here since true_rtx or false_rtx might share RTL with x as a
5242 result of the if_then_else_cond call above. */
5243 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5244 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5246 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5247 is unlikely to be simpler. */
5248 if (general_operand (true_rtx, VOIDmode)
5249 && general_operand (false_rtx, VOIDmode))
5251 enum rtx_code reversed;
5253 /* Restarting if we generate a store-flag expression will cause
5254 us to loop. Just drop through in this case. */
5256 /* If the result values are STORE_FLAG_VALUE and zero, we can
5257 just make the comparison operation. */
5258 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5259 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5261 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5262 && ((reversed = reversed_comparison_code_parts
5263 (cond_code, cond, cop1, NULL))
5265 x = simplify_gen_relational (reversed, mode, VOIDmode,
5268 /* Likewise, we can make the negate of a comparison operation
5269 if the result values are - STORE_FLAG_VALUE and zero. */
5270 else if (CONST_INT_P (true_rtx)
5271 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5272 && false_rtx == const0_rtx)
5273 x = simplify_gen_unary (NEG, mode,
5274 simplify_gen_relational (cond_code,
5278 else if (CONST_INT_P (false_rtx)
5279 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5280 && true_rtx == const0_rtx
5281 && ((reversed = reversed_comparison_code_parts
5282 (cond_code, cond, cop1, NULL))
5284 x = simplify_gen_unary (NEG, mode,
5285 simplify_gen_relational (reversed,
5290 return gen_rtx_IF_THEN_ELSE (mode,
5291 simplify_gen_relational (cond_code,
5296 true_rtx, false_rtx);
5298 code = GET_CODE (x);
5299 op0_mode = VOIDmode;
5304 /* Try to fold this expression in case we have constants that weren't
5307 switch (GET_RTX_CLASS (code))
5310 if (op0_mode == VOIDmode)
5311 op0_mode = GET_MODE (XEXP (x, 0));
5312 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5315 case RTX_COMM_COMPARE:
5317 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5318 if (cmp_mode == VOIDmode)
5320 cmp_mode = GET_MODE (XEXP (x, 1));
5321 if (cmp_mode == VOIDmode)
5322 cmp_mode = op0_mode;
5324 temp = simplify_relational_operation (code, mode, cmp_mode,
5325 XEXP (x, 0), XEXP (x, 1));
5328 case RTX_COMM_ARITH:
5330 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5332 case RTX_BITFIELD_OPS:
5334 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5335 XEXP (x, 1), XEXP (x, 2));
5344 code = GET_CODE (temp);
5345 op0_mode = VOIDmode;
5346 mode = GET_MODE (temp);
5349 /* First see if we can apply the inverse distributive law. */
5350 if (code == PLUS || code == MINUS
5351 || code == AND || code == IOR || code == XOR)
5353 x = apply_distributive_law (x);
5354 code = GET_CODE (x);
5355 op0_mode = VOIDmode;
5358 /* If CODE is an associative operation not otherwise handled, see if we
5359 can associate some operands. This can win if they are constants or
5360 if they are logically related (i.e. (a & b) & a). */
5361 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5362 || code == AND || code == IOR || code == XOR
5363 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5364 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5365 || (flag_associative_math && FLOAT_MODE_P (mode))))
5367 if (GET_CODE (XEXP (x, 0)) == code)
5369 rtx other = XEXP (XEXP (x, 0), 0);
5370 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5371 rtx inner_op1 = XEXP (x, 1);
5374 /* Make sure we pass the constant operand if any as the second
5375 one if this is a commutative operation. */
5376 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5378 rtx tem = inner_op0;
5379 inner_op0 = inner_op1;
5382 inner = simplify_binary_operation (code == MINUS ? PLUS
5383 : code == DIV ? MULT
5385 mode, inner_op0, inner_op1);
5387 /* For commutative operations, try the other pair if that one
5389 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5391 other = XEXP (XEXP (x, 0), 1);
5392 inner = simplify_binary_operation (code, mode,
5393 XEXP (XEXP (x, 0), 0),
5398 return simplify_gen_binary (code, mode, other, inner);
5402 /* A little bit of algebraic simplification here. */
5406 /* Ensure that our address has any ASHIFTs converted to MULT in case
5407 address-recognizing predicates are called later. */
5408 temp = make_compound_operation (XEXP (x, 0), MEM);
5409 SUBST (XEXP (x, 0), temp);
5413 if (op0_mode == VOIDmode)
5414 op0_mode = GET_MODE (SUBREG_REG (x));
5416 /* See if this can be moved to simplify_subreg. */
5417 if (CONSTANT_P (SUBREG_REG (x))
5418 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5419 /* Don't call gen_lowpart if the inner mode
5420 is VOIDmode and we cannot simplify it, as SUBREG without
5421 inner mode is invalid. */
5422 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5423 || gen_lowpart_common (mode, SUBREG_REG (x))))
5424 return gen_lowpart (mode, SUBREG_REG (x));
5426 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5430 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5436 /* Don't change the mode of the MEM if that would change the meaning
5438 if (MEM_P (SUBREG_REG (x))
5439 && (MEM_VOLATILE_P (SUBREG_REG (x))
5440 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5441 return gen_rtx_CLOBBER (mode, const0_rtx);
5443 /* Note that we cannot do any narrowing for non-constants since
5444 we might have been counting on using the fact that some bits were
5445 zero. We now do this in the SET. */
5450 temp = expand_compound_operation (XEXP (x, 0));
5452 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5453 replaced by (lshiftrt X C). This will convert
5454 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5456 if (GET_CODE (temp) == ASHIFTRT
5457 && CONST_INT_P (XEXP (temp, 1))
5458 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5459 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5460 INTVAL (XEXP (temp, 1)));
5462 /* If X has only a single bit that might be nonzero, say, bit I, convert
5463 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5464 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5465 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5466 or a SUBREG of one since we'd be making the expression more
5467 complex if it was just a register. */
5470 && ! (GET_CODE (temp) == SUBREG
5471 && REG_P (SUBREG_REG (temp)))
5472 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5474 rtx temp1 = simplify_shift_const
5475 (NULL_RTX, ASHIFTRT, mode,
5476 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5477 GET_MODE_BITSIZE (mode) - 1 - i),
5478 GET_MODE_BITSIZE (mode) - 1 - i);
5480 /* If all we did was surround TEMP with the two shifts, we
5481 haven't improved anything, so don't use it. Otherwise,
5482 we are better off with TEMP1. */
5483 if (GET_CODE (temp1) != ASHIFTRT
5484 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5485 || XEXP (XEXP (temp1, 0), 0) != temp)
5491 /* We can't handle truncation to a partial integer mode here
5492 because we don't know the real bitsize of the partial
5494 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5497 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5499 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5500 GET_MODE_MASK (mode), 0));
5502 /* We can truncate a constant value and return it. */
5503 if (CONST_INT_P (XEXP (x, 0)))
5504 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5506 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5507 whose value is a comparison can be replaced with a subreg if
5508 STORE_FLAG_VALUE permits. */
5509 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5510 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5511 && (temp = get_last_value (XEXP (x, 0)))
5512 && COMPARISON_P (temp))
5513 return gen_lowpart (mode, XEXP (x, 0));
5517 /* (const (const X)) can become (const X). Do it this way rather than
5518 returning the inner CONST since CONST can be shared with a
5520 if (GET_CODE (XEXP (x, 0)) == CONST)
5521 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5526 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5527 can add in an offset. find_split_point will split this address up
5528 again if it doesn't match. */
5529 if (GET_CODE (XEXP (x, 0)) == HIGH
5530 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5536 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5537 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5538 bit-field and can be replaced by either a sign_extend or a
5539 sign_extract. The `and' may be a zero_extend and the two
5540 <c>, -<c> constants may be reversed. */
5541 if (GET_CODE (XEXP (x, 0)) == XOR
5542 && CONST_INT_P (XEXP (x, 1))
5543 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5544 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5545 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5546 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5547 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5548 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5549 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5550 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5551 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5552 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5553 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5554 == (unsigned int) i + 1))))
5555 return simplify_shift_const
5556 (NULL_RTX, ASHIFTRT, mode,
5557 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5558 XEXP (XEXP (XEXP (x, 0), 0), 0),
5559 GET_MODE_BITSIZE (mode) - (i + 1)),
5560 GET_MODE_BITSIZE (mode) - (i + 1));
5562 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5563 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5564 the bitsize of the mode - 1. This allows simplification of
5565 "a = (b & 8) == 0;" */
5566 if (XEXP (x, 1) == constm1_rtx
5567 && !REG_P (XEXP (x, 0))
5568 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5569 && REG_P (SUBREG_REG (XEXP (x, 0))))
5570 && nonzero_bits (XEXP (x, 0), mode) == 1)
5571 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5572 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5573 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5574 GET_MODE_BITSIZE (mode) - 1),
5575 GET_MODE_BITSIZE (mode) - 1);
5577 /* If we are adding two things that have no bits in common, convert
5578 the addition into an IOR. This will often be further simplified,
5579 for example in cases like ((a & 1) + (a & 2)), which can
5582 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5583 && (nonzero_bits (XEXP (x, 0), mode)
5584 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5586 /* Try to simplify the expression further. */
5587 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5588 temp = combine_simplify_rtx (tor, mode, in_dest);
5590 /* If we could, great. If not, do not go ahead with the IOR
5591 replacement, since PLUS appears in many special purpose
5592 address arithmetic instructions. */
5593 if (GET_CODE (temp) != CLOBBER && temp != tor)
5599 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5600 (and <foo> (const_int pow2-1)) */
5601 if (GET_CODE (XEXP (x, 1)) == AND
5602 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5603 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5604 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5605 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5606 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5610 /* If we have (mult (plus A B) C), apply the distributive law and then
5611 the inverse distributive law to see if things simplify. This
5612 occurs mostly in addresses, often when unrolling loops. */
5614 if (GET_CODE (XEXP (x, 0)) == PLUS)
5616 rtx result = distribute_and_simplify_rtx (x, 0);
5621 /* Try simplify a*(b/c) as (a*b)/c. */
5622 if (FLOAT_MODE_P (mode) && flag_associative_math
5623 && GET_CODE (XEXP (x, 0)) == DIV)
5625 rtx tem = simplify_binary_operation (MULT, mode,
5626 XEXP (XEXP (x, 0), 0),
5629 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5634 /* If this is a divide by a power of two, treat it as a shift if
5635 its first operand is a shift. */
5636 if (CONST_INT_P (XEXP (x, 1))
5637 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5638 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5639 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5640 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5641 || GET_CODE (XEXP (x, 0)) == ROTATE
5642 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5643 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5647 case GT: case GTU: case GE: case GEU:
5648 case LT: case LTU: case LE: case LEU:
5649 case UNEQ: case LTGT:
5650 case UNGT: case UNGE:
5651 case UNLT: case UNLE:
5652 case UNORDERED: case ORDERED:
5653 /* If the first operand is a condition code, we can't do anything
5655 if (GET_CODE (XEXP (x, 0)) == COMPARE
5656 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5657 && ! CC0_P (XEXP (x, 0))))
5659 rtx op0 = XEXP (x, 0);
5660 rtx op1 = XEXP (x, 1);
5661 enum rtx_code new_code;
5663 if (GET_CODE (op0) == COMPARE)
5664 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5666 /* Simplify our comparison, if possible. */
5667 new_code = simplify_comparison (code, &op0, &op1);
5669 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5670 if only the low-order bit is possibly nonzero in X (such as when
5671 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5672 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5673 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5676 Remove any ZERO_EXTRACT we made when thinking this was a
5677 comparison. It may now be simpler to use, e.g., an AND. If a
5678 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5679 the call to make_compound_operation in the SET case. */
5681 if (STORE_FLAG_VALUE == 1
5682 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5683 && op1 == const0_rtx
5684 && mode == GET_MODE (op0)
5685 && nonzero_bits (op0, mode) == 1)
5686 return gen_lowpart (mode,
5687 expand_compound_operation (op0));
5689 else if (STORE_FLAG_VALUE == 1
5690 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5691 && op1 == const0_rtx
5692 && mode == GET_MODE (op0)
5693 && (num_sign_bit_copies (op0, mode)
5694 == GET_MODE_BITSIZE (mode)))
5696 op0 = expand_compound_operation (op0);
5697 return simplify_gen_unary (NEG, mode,
5698 gen_lowpart (mode, op0),
5702 else if (STORE_FLAG_VALUE == 1
5703 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5704 && op1 == const0_rtx
5705 && mode == GET_MODE (op0)
5706 && nonzero_bits (op0, mode) == 1)
5708 op0 = expand_compound_operation (op0);
5709 return simplify_gen_binary (XOR, mode,
5710 gen_lowpart (mode, op0),
5714 else if (STORE_FLAG_VALUE == 1
5715 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5716 && op1 == const0_rtx
5717 && mode == GET_MODE (op0)
5718 && (num_sign_bit_copies (op0, mode)
5719 == GET_MODE_BITSIZE (mode)))
5721 op0 = expand_compound_operation (op0);
5722 return plus_constant (gen_lowpart (mode, op0), 1);
5725 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5727 if (STORE_FLAG_VALUE == -1
5728 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5729 && op1 == const0_rtx
5730 && (num_sign_bit_copies (op0, mode)
5731 == GET_MODE_BITSIZE (mode)))
5732 return gen_lowpart (mode,
5733 expand_compound_operation (op0));
5735 else if (STORE_FLAG_VALUE == -1
5736 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5737 && op1 == const0_rtx
5738 && mode == GET_MODE (op0)
5739 && nonzero_bits (op0, mode) == 1)
5741 op0 = expand_compound_operation (op0);
5742 return simplify_gen_unary (NEG, mode,
5743 gen_lowpart (mode, op0),
5747 else if (STORE_FLAG_VALUE == -1
5748 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5749 && op1 == const0_rtx
5750 && mode == GET_MODE (op0)
5751 && (num_sign_bit_copies (op0, mode)
5752 == GET_MODE_BITSIZE (mode)))
5754 op0 = expand_compound_operation (op0);
5755 return simplify_gen_unary (NOT, mode,
5756 gen_lowpart (mode, op0),
5760 /* If X is 0/1, (eq X 0) is X-1. */
5761 else if (STORE_FLAG_VALUE == -1
5762 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5763 && op1 == const0_rtx
5764 && mode == GET_MODE (op0)
5765 && nonzero_bits (op0, mode) == 1)
5767 op0 = expand_compound_operation (op0);
5768 return plus_constant (gen_lowpart (mode, op0), -1);
5771 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5772 one bit that might be nonzero, we can convert (ne x 0) to
5773 (ashift x c) where C puts the bit in the sign bit. Remove any
5774 AND with STORE_FLAG_VALUE when we are done, since we are only
5775 going to test the sign bit. */
5776 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5777 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5778 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5779 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5780 && op1 == const0_rtx
5781 && mode == GET_MODE (op0)
5782 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5784 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5785 expand_compound_operation (op0),
5786 GET_MODE_BITSIZE (mode) - 1 - i);
5787 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5793 /* If the code changed, return a whole new comparison. */
5794 if (new_code != code)
5795 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5797 /* Otherwise, keep this operation, but maybe change its operands.
5798 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5799 SUBST (XEXP (x, 0), op0);
5800 SUBST (XEXP (x, 1), op1);
5805 return simplify_if_then_else (x);
5811 /* If we are processing SET_DEST, we are done. */
5815 return expand_compound_operation (x);
5818 return simplify_set (x);
5822 return simplify_logical (x);
5829 /* If this is a shift by a constant amount, simplify it. */
5830 if (CONST_INT_P (XEXP (x, 1)))
5831 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5832 INTVAL (XEXP (x, 1)));
5834 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5836 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5838 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5850 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5853 simplify_if_then_else (rtx x)
5855 enum machine_mode mode = GET_MODE (x);
5856 rtx cond = XEXP (x, 0);
5857 rtx true_rtx = XEXP (x, 1);
5858 rtx false_rtx = XEXP (x, 2);
5859 enum rtx_code true_code = GET_CODE (cond);
5860 int comparison_p = COMPARISON_P (cond);
5863 enum rtx_code false_code;
5866 /* Simplify storing of the truth value. */
5867 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5868 return simplify_gen_relational (true_code, mode, VOIDmode,
5869 XEXP (cond, 0), XEXP (cond, 1));
5871 /* Also when the truth value has to be reversed. */
5873 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5874 && (reversed = reversed_comparison (cond, mode)))
5877 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5878 in it is being compared against certain values. Get the true and false
5879 comparisons and see if that says anything about the value of each arm. */
5882 && ((false_code = reversed_comparison_code (cond, NULL))
5884 && REG_P (XEXP (cond, 0)))
5887 rtx from = XEXP (cond, 0);
5888 rtx true_val = XEXP (cond, 1);
5889 rtx false_val = true_val;
5892 /* If FALSE_CODE is EQ, swap the codes and arms. */
5894 if (false_code == EQ)
5896 swapped = 1, true_code = EQ, false_code = NE;
5897 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5900 /* If we are comparing against zero and the expression being tested has
5901 only a single bit that might be nonzero, that is its value when it is
5902 not equal to zero. Similarly if it is known to be -1 or 0. */
5904 if (true_code == EQ && true_val == const0_rtx
5905 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5908 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5910 else if (true_code == EQ && true_val == const0_rtx
5911 && (num_sign_bit_copies (from, GET_MODE (from))
5912 == GET_MODE_BITSIZE (GET_MODE (from))))
5915 false_val = constm1_rtx;
5918 /* Now simplify an arm if we know the value of the register in the
5919 branch and it is used in the arm. Be careful due to the potential
5920 of locally-shared RTL. */
5922 if (reg_mentioned_p (from, true_rtx))
5923 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5925 pc_rtx, pc_rtx, 0, 0);
5926 if (reg_mentioned_p (from, false_rtx))
5927 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5929 pc_rtx, pc_rtx, 0, 0);
5931 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5932 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5934 true_rtx = XEXP (x, 1);
5935 false_rtx = XEXP (x, 2);
5936 true_code = GET_CODE (cond);
5939 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5940 reversed, do so to avoid needing two sets of patterns for
5941 subtract-and-branch insns. Similarly if we have a constant in the true
5942 arm, the false arm is the same as the first operand of the comparison, or
5943 the false arm is more complicated than the true arm. */
5946 && reversed_comparison_code (cond, NULL) != UNKNOWN
5947 && (true_rtx == pc_rtx
5948 || (CONSTANT_P (true_rtx)
5949 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5950 || true_rtx == const0_rtx
5951 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5952 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5953 && !OBJECT_P (false_rtx))
5954 || reg_mentioned_p (true_rtx, false_rtx)
5955 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5957 true_code = reversed_comparison_code (cond, NULL);
5958 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5959 SUBST (XEXP (x, 1), false_rtx);
5960 SUBST (XEXP (x, 2), true_rtx);
5962 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5965 /* It is possible that the conditional has been simplified out. */
5966 true_code = GET_CODE (cond);
5967 comparison_p = COMPARISON_P (cond);
5970 /* If the two arms are identical, we don't need the comparison. */
5972 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5975 /* Convert a == b ? b : a to "a". */
5976 if (true_code == EQ && ! side_effects_p (cond)
5977 && !HONOR_NANS (mode)
5978 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5979 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5981 else if (true_code == NE && ! side_effects_p (cond)
5982 && !HONOR_NANS (mode)
5983 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5984 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5987 /* Look for cases where we have (abs x) or (neg (abs X)). */
5989 if (GET_MODE_CLASS (mode) == MODE_INT
5991 && XEXP (cond, 1) == const0_rtx
5992 && GET_CODE (false_rtx) == NEG
5993 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5994 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5995 && ! side_effects_p (true_rtx))
6000 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6004 simplify_gen_unary (NEG, mode,
6005 simplify_gen_unary (ABS, mode, true_rtx, mode),
6011 /* Look for MIN or MAX. */
6013 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6015 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6016 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6017 && ! side_effects_p (cond))
6022 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6025 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6028 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6031 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6036 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6037 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6038 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6039 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6040 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6041 neither 1 or -1, but it isn't worth checking for. */
6043 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6045 && GET_MODE_CLASS (mode) == MODE_INT
6046 && ! side_effects_p (x))
6048 rtx t = make_compound_operation (true_rtx, SET);
6049 rtx f = make_compound_operation (false_rtx, SET);
6050 rtx cond_op0 = XEXP (cond, 0);
6051 rtx cond_op1 = XEXP (cond, 1);
6052 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6053 enum machine_mode m = mode;
6054 rtx z = 0, c1 = NULL_RTX;
6056 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6057 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6058 || GET_CODE (t) == ASHIFT
6059 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6060 && rtx_equal_p (XEXP (t, 0), f))
6061 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6063 /* If an identity-zero op is commutative, check whether there
6064 would be a match if we swapped the operands. */
6065 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6066 || GET_CODE (t) == XOR)
6067 && rtx_equal_p (XEXP (t, 1), f))
6068 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6069 else if (GET_CODE (t) == SIGN_EXTEND
6070 && (GET_CODE (XEXP (t, 0)) == PLUS
6071 || GET_CODE (XEXP (t, 0)) == MINUS
6072 || GET_CODE (XEXP (t, 0)) == IOR
6073 || GET_CODE (XEXP (t, 0)) == XOR
6074 || GET_CODE (XEXP (t, 0)) == ASHIFT
6075 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6076 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6077 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6078 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6079 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6080 && (num_sign_bit_copies (f, GET_MODE (f))
6082 (GET_MODE_BITSIZE (mode)
6083 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6085 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6086 extend_op = SIGN_EXTEND;
6087 m = GET_MODE (XEXP (t, 0));
6089 else if (GET_CODE (t) == SIGN_EXTEND
6090 && (GET_CODE (XEXP (t, 0)) == PLUS
6091 || GET_CODE (XEXP (t, 0)) == IOR
6092 || GET_CODE (XEXP (t, 0)) == XOR)
6093 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6094 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6095 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6096 && (num_sign_bit_copies (f, GET_MODE (f))
6098 (GET_MODE_BITSIZE (mode)
6099 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6101 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6102 extend_op = SIGN_EXTEND;
6103 m = GET_MODE (XEXP (t, 0));
6105 else if (GET_CODE (t) == ZERO_EXTEND
6106 && (GET_CODE (XEXP (t, 0)) == PLUS
6107 || GET_CODE (XEXP (t, 0)) == MINUS
6108 || GET_CODE (XEXP (t, 0)) == IOR
6109 || GET_CODE (XEXP (t, 0)) == XOR
6110 || GET_CODE (XEXP (t, 0)) == ASHIFT
6111 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6112 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6113 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6114 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6115 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6116 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6117 && ((nonzero_bits (f, GET_MODE (f))
6118 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6121 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6122 extend_op = ZERO_EXTEND;
6123 m = GET_MODE (XEXP (t, 0));
6125 else if (GET_CODE (t) == ZERO_EXTEND
6126 && (GET_CODE (XEXP (t, 0)) == PLUS
6127 || GET_CODE (XEXP (t, 0)) == IOR
6128 || GET_CODE (XEXP (t, 0)) == XOR)
6129 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6130 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6131 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6132 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6133 && ((nonzero_bits (f, GET_MODE (f))
6134 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6137 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6138 extend_op = ZERO_EXTEND;
6139 m = GET_MODE (XEXP (t, 0));
6144 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6145 cond_op0, cond_op1),
6146 pc_rtx, pc_rtx, 0, 0);
6147 temp = simplify_gen_binary (MULT, m, temp,
6148 simplify_gen_binary (MULT, m, c1,
6150 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6151 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6153 if (extend_op != UNKNOWN)
6154 temp = simplify_gen_unary (extend_op, mode, temp, m);
6160 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6161 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6162 negation of a single bit, we can convert this operation to a shift. We
6163 can actually do this more generally, but it doesn't seem worth it. */
6165 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6166 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6167 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6168 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
6169 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6170 == GET_MODE_BITSIZE (mode))
6171 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
6173 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6174 gen_lowpart (mode, XEXP (cond, 0)), i);
6176 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6177 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6178 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6179 && GET_MODE (XEXP (cond, 0)) == mode
6180 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
6181 == nonzero_bits (XEXP (cond, 0), mode)
6182 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6183 return XEXP (cond, 0);
6188 /* Simplify X, a SET expression. Return the new expression. */
6191 simplify_set (rtx x)
6193 rtx src = SET_SRC (x);
6194 rtx dest = SET_DEST (x);
6195 enum machine_mode mode
6196 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6200 /* (set (pc) (return)) gets written as (return). */
6201 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6204 /* Now that we know for sure which bits of SRC we are using, see if we can
6205 simplify the expression for the object knowing that we only need the
6208 if (GET_MODE_CLASS (mode) == MODE_INT
6209 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6211 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
6212 SUBST (SET_SRC (x), src);
6215 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6216 the comparison result and try to simplify it unless we already have used
6217 undobuf.other_insn. */
6218 if ((GET_MODE_CLASS (mode) == MODE_CC
6219 || GET_CODE (src) == COMPARE
6221 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6222 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6223 && COMPARISON_P (*cc_use)
6224 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6226 enum rtx_code old_code = GET_CODE (*cc_use);
6227 enum rtx_code new_code;
6229 int other_changed = 0;
6230 enum machine_mode compare_mode = GET_MODE (dest);
6232 if (GET_CODE (src) == COMPARE)
6233 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6235 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6237 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6240 new_code = old_code;
6241 else if (!CONSTANT_P (tmp))
6243 new_code = GET_CODE (tmp);
6244 op0 = XEXP (tmp, 0);
6245 op1 = XEXP (tmp, 1);
6249 rtx pat = PATTERN (other_insn);
6250 undobuf.other_insn = other_insn;
6251 SUBST (*cc_use, tmp);
6253 /* Attempt to simplify CC user. */
6254 if (GET_CODE (pat) == SET)
6256 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6257 if (new_rtx != NULL_RTX)
6258 SUBST (SET_SRC (pat), new_rtx);
6261 /* Convert X into a no-op move. */
6262 SUBST (SET_DEST (x), pc_rtx);
6263 SUBST (SET_SRC (x), pc_rtx);
6267 /* Simplify our comparison, if possible. */
6268 new_code = simplify_comparison (new_code, &op0, &op1);
6270 #ifdef SELECT_CC_MODE
6271 /* If this machine has CC modes other than CCmode, check to see if we
6272 need to use a different CC mode here. */
6273 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6274 compare_mode = GET_MODE (op0);
6276 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6279 /* If the mode changed, we have to change SET_DEST, the mode in the
6280 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6281 a hard register, just build new versions with the proper mode. If it
6282 is a pseudo, we lose unless it is only time we set the pseudo, in
6283 which case we can safely change its mode. */
6284 if (compare_mode != GET_MODE (dest))
6286 if (can_change_dest_mode (dest, 0, compare_mode))
6288 unsigned int regno = REGNO (dest);
6291 if (regno < FIRST_PSEUDO_REGISTER)
6292 new_dest = gen_rtx_REG (compare_mode, regno);
6295 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6296 new_dest = regno_reg_rtx[regno];
6299 SUBST (SET_DEST (x), new_dest);
6300 SUBST (XEXP (*cc_use, 0), new_dest);
6307 #endif /* SELECT_CC_MODE */
6309 /* If the code changed, we have to build a new comparison in
6310 undobuf.other_insn. */
6311 if (new_code != old_code)
6313 int other_changed_previously = other_changed;
6314 unsigned HOST_WIDE_INT mask;
6315 rtx old_cc_use = *cc_use;
6317 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6321 /* If the only change we made was to change an EQ into an NE or
6322 vice versa, OP0 has only one bit that might be nonzero, and OP1
6323 is zero, check if changing the user of the condition code will
6324 produce a valid insn. If it won't, we can keep the original code
6325 in that insn by surrounding our operation with an XOR. */
6327 if (((old_code == NE && new_code == EQ)
6328 || (old_code == EQ && new_code == NE))
6329 && ! other_changed_previously && op1 == const0_rtx
6330 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6331 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6333 rtx pat = PATTERN (other_insn), note = 0;
6335 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6336 && ! check_asm_operands (pat)))
6338 *cc_use = old_cc_use;
6341 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6342 op0, GEN_INT (mask));
6348 undobuf.other_insn = other_insn;
6350 /* Otherwise, if we didn't previously have a COMPARE in the
6351 correct mode, we need one. */
6352 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6354 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6357 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6359 SUBST (SET_SRC (x), op0);
6362 /* Otherwise, update the COMPARE if needed. */
6363 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6365 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6371 /* Get SET_SRC in a form where we have placed back any
6372 compound expressions. Then do the checks below. */
6373 src = make_compound_operation (src, SET);
6374 SUBST (SET_SRC (x), src);
6377 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6378 and X being a REG or (subreg (reg)), we may be able to convert this to
6379 (set (subreg:m2 x) (op)).
6381 We can always do this if M1 is narrower than M2 because that means that
6382 we only care about the low bits of the result.
6384 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6385 perform a narrower operation than requested since the high-order bits will
6386 be undefined. On machine where it is defined, this transformation is safe
6387 as long as M1 and M2 have the same number of words. */
6389 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6390 && !OBJECT_P (SUBREG_REG (src))
6391 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6393 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6394 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6395 #ifndef WORD_REGISTER_OPERATIONS
6396 && (GET_MODE_SIZE (GET_MODE (src))
6397 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6399 #ifdef CANNOT_CHANGE_MODE_CLASS
6400 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6401 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6402 GET_MODE (SUBREG_REG (src)),
6406 || (GET_CODE (dest) == SUBREG
6407 && REG_P (SUBREG_REG (dest)))))
6409 SUBST (SET_DEST (x),
6410 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6412 SUBST (SET_SRC (x), SUBREG_REG (src));
6414 src = SET_SRC (x), dest = SET_DEST (x);
6418 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6421 && GET_CODE (src) == SUBREG
6422 && subreg_lowpart_p (src)
6423 && (GET_MODE_BITSIZE (GET_MODE (src))
6424 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6426 rtx inner = SUBREG_REG (src);
6427 enum machine_mode inner_mode = GET_MODE (inner);
6429 /* Here we make sure that we don't have a sign bit on. */
6430 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6431 && (nonzero_bits (inner, inner_mode)
6432 < ((unsigned HOST_WIDE_INT) 1
6433 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6435 SUBST (SET_SRC (x), inner);
6441 #ifdef LOAD_EXTEND_OP
6442 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6443 would require a paradoxical subreg. Replace the subreg with a
6444 zero_extend to avoid the reload that would otherwise be required. */
6446 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6447 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6448 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6449 && SUBREG_BYTE (src) == 0
6450 && (GET_MODE_SIZE (GET_MODE (src))
6451 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6452 && MEM_P (SUBREG_REG (src)))
6455 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6456 GET_MODE (src), SUBREG_REG (src)));
6462 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6463 are comparing an item known to be 0 or -1 against 0, use a logical
6464 operation instead. Check for one of the arms being an IOR of the other
6465 arm with some value. We compute three terms to be IOR'ed together. In
6466 practice, at most two will be nonzero. Then we do the IOR's. */
6468 if (GET_CODE (dest) != PC
6469 && GET_CODE (src) == IF_THEN_ELSE
6470 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6471 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6472 && XEXP (XEXP (src, 0), 1) == const0_rtx
6473 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6474 #ifdef HAVE_conditional_move
6475 && ! can_conditionally_move_p (GET_MODE (src))
6477 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6478 GET_MODE (XEXP (XEXP (src, 0), 0)))
6479 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6480 && ! side_effects_p (src))
6482 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6483 ? XEXP (src, 1) : XEXP (src, 2));
6484 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6485 ? XEXP (src, 2) : XEXP (src, 1));
6486 rtx term1 = const0_rtx, term2, term3;
6488 if (GET_CODE (true_rtx) == IOR
6489 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6490 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6491 else if (GET_CODE (true_rtx) == IOR
6492 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6493 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6494 else if (GET_CODE (false_rtx) == IOR
6495 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6496 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6497 else if (GET_CODE (false_rtx) == IOR
6498 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6499 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6501 term2 = simplify_gen_binary (AND, GET_MODE (src),
6502 XEXP (XEXP (src, 0), 0), true_rtx);
6503 term3 = simplify_gen_binary (AND, GET_MODE (src),
6504 simplify_gen_unary (NOT, GET_MODE (src),
6505 XEXP (XEXP (src, 0), 0),
6510 simplify_gen_binary (IOR, GET_MODE (src),
6511 simplify_gen_binary (IOR, GET_MODE (src),
6518 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6519 whole thing fail. */
6520 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6522 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6525 /* Convert this into a field assignment operation, if possible. */
6526 return make_field_assignment (x);
6529 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6533 simplify_logical (rtx x)
6535 enum machine_mode mode = GET_MODE (x);
6536 rtx op0 = XEXP (x, 0);
6537 rtx op1 = XEXP (x, 1);
6539 switch (GET_CODE (x))
6542 /* We can call simplify_and_const_int only if we don't lose
6543 any (sign) bits when converting INTVAL (op1) to
6544 "unsigned HOST_WIDE_INT". */
6545 if (CONST_INT_P (op1)
6546 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6547 || INTVAL (op1) > 0))
6549 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6550 if (GET_CODE (x) != AND)
6557 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6558 apply the distributive law and then the inverse distributive
6559 law to see if things simplify. */
6560 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6562 rtx result = distribute_and_simplify_rtx (x, 0);
6566 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6568 rtx result = distribute_and_simplify_rtx (x, 1);
6575 /* If we have (ior (and A B) C), apply the distributive law and then
6576 the inverse distributive law to see if things simplify. */
6578 if (GET_CODE (op0) == AND)
6580 rtx result = distribute_and_simplify_rtx (x, 0);
6585 if (GET_CODE (op1) == AND)
6587 rtx result = distribute_and_simplify_rtx (x, 1);
6600 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6601 operations" because they can be replaced with two more basic operations.
6602 ZERO_EXTEND is also considered "compound" because it can be replaced with
6603 an AND operation, which is simpler, though only one operation.
6605 The function expand_compound_operation is called with an rtx expression
6606 and will convert it to the appropriate shifts and AND operations,
6607 simplifying at each stage.
6609 The function make_compound_operation is called to convert an expression
6610 consisting of shifts and ANDs into the equivalent compound expression.
6611 It is the inverse of this function, loosely speaking. */
6614 expand_compound_operation (rtx x)
6616 unsigned HOST_WIDE_INT pos = 0, len;
6618 unsigned int modewidth;
6621 switch (GET_CODE (x))
6626 /* We can't necessarily use a const_int for a multiword mode;
6627 it depends on implicitly extending the value.
6628 Since we don't know the right way to extend it,
6629 we can't tell whether the implicit way is right.
6631 Even for a mode that is no wider than a const_int,
6632 we can't win, because we need to sign extend one of its bits through
6633 the rest of it, and we don't know which bit. */
6634 if (CONST_INT_P (XEXP (x, 0)))
6637 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6638 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6639 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6640 reloaded. If not for that, MEM's would very rarely be safe.
6642 Reject MODEs bigger than a word, because we might not be able
6643 to reference a two-register group starting with an arbitrary register
6644 (and currently gen_lowpart might crash for a SUBREG). */
6646 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6649 /* Reject MODEs that aren't scalar integers because turning vector
6650 or complex modes into shifts causes problems. */
6652 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6655 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6656 /* If the inner object has VOIDmode (the only way this can happen
6657 is if it is an ASM_OPERANDS), we can't do anything since we don't
6658 know how much masking to do. */
6667 /* ... fall through ... */
6670 /* If the operand is a CLOBBER, just return it. */
6671 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6674 if (!CONST_INT_P (XEXP (x, 1))
6675 || !CONST_INT_P (XEXP (x, 2))
6676 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6679 /* Reject MODEs that aren't scalar integers because turning vector
6680 or complex modes into shifts causes problems. */
6682 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6685 len = INTVAL (XEXP (x, 1));
6686 pos = INTVAL (XEXP (x, 2));
6688 /* This should stay within the object being extracted, fail otherwise. */
6689 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6692 if (BITS_BIG_ENDIAN)
6693 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6700 /* Convert sign extension to zero extension, if we know that the high
6701 bit is not set, as this is easier to optimize. It will be converted
6702 back to cheaper alternative in make_extraction. */
6703 if (GET_CODE (x) == SIGN_EXTEND
6704 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6705 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6706 & ~(((unsigned HOST_WIDE_INT)
6707 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6711 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6712 rtx temp2 = expand_compound_operation (temp);
6714 /* Make sure this is a profitable operation. */
6715 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6716 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6718 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6719 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6725 /* We can optimize some special cases of ZERO_EXTEND. */
6726 if (GET_CODE (x) == ZERO_EXTEND)
6728 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6729 know that the last value didn't have any inappropriate bits
6731 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6732 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6733 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6734 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6735 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6736 return XEXP (XEXP (x, 0), 0);
6738 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6739 if (GET_CODE (XEXP (x, 0)) == SUBREG
6740 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6741 && subreg_lowpart_p (XEXP (x, 0))
6742 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6743 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6744 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6745 return SUBREG_REG (XEXP (x, 0));
6747 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6748 is a comparison and STORE_FLAG_VALUE permits. This is like
6749 the first case, but it works even when GET_MODE (x) is larger
6750 than HOST_WIDE_INT. */
6751 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6752 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6753 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6754 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6755 <= HOST_BITS_PER_WIDE_INT)
6756 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6757 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6758 return XEXP (XEXP (x, 0), 0);
6760 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6761 if (GET_CODE (XEXP (x, 0)) == SUBREG
6762 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6763 && subreg_lowpart_p (XEXP (x, 0))
6764 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6765 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6766 <= HOST_BITS_PER_WIDE_INT)
6767 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6768 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6769 return SUBREG_REG (XEXP (x, 0));
6773 /* If we reach here, we want to return a pair of shifts. The inner
6774 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6775 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6776 logical depending on the value of UNSIGNEDP.
6778 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6779 converted into an AND of a shift.
6781 We must check for the case where the left shift would have a negative
6782 count. This can happen in a case like (x >> 31) & 255 on machines
6783 that can't shift by a constant. On those machines, we would first
6784 combine the shift with the AND to produce a variable-position
6785 extraction. Then the constant of 31 would be substituted in to produce
6786 a such a position. */
6788 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6789 if (modewidth + len >= pos)
6791 enum machine_mode mode = GET_MODE (x);
6792 tem = gen_lowpart (mode, XEXP (x, 0));
6793 if (!tem || GET_CODE (tem) == CLOBBER)
6795 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6796 tem, modewidth - pos - len);
6797 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6798 mode, tem, modewidth - len);
6800 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6801 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6802 simplify_shift_const (NULL_RTX, LSHIFTRT,
6805 ((HOST_WIDE_INT) 1 << len) - 1);
6807 /* Any other cases we can't handle. */
6810 /* If we couldn't do this for some reason, return the original
6812 if (GET_CODE (tem) == CLOBBER)
6818 /* X is a SET which contains an assignment of one object into
6819 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6820 or certain SUBREGS). If possible, convert it into a series of
6823 We half-heartedly support variable positions, but do not at all
6824 support variable lengths. */
6827 expand_field_assignment (const_rtx x)
6830 rtx pos; /* Always counts from low bit. */
6832 rtx mask, cleared, masked;
6833 enum machine_mode compute_mode;
6835 /* Loop until we find something we can't simplify. */
6838 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6839 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6841 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6842 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6843 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6845 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6846 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6848 inner = XEXP (SET_DEST (x), 0);
6849 len = INTVAL (XEXP (SET_DEST (x), 1));
6850 pos = XEXP (SET_DEST (x), 2);
6852 /* A constant position should stay within the width of INNER. */
6853 if (CONST_INT_P (pos)
6854 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6857 if (BITS_BIG_ENDIAN)
6859 if (CONST_INT_P (pos))
6860 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6862 else if (GET_CODE (pos) == MINUS
6863 && CONST_INT_P (XEXP (pos, 1))
6864 && (INTVAL (XEXP (pos, 1))
6865 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6866 /* If position is ADJUST - X, new position is X. */
6867 pos = XEXP (pos, 0);
6869 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6870 GEN_INT (GET_MODE_BITSIZE (
6877 /* A SUBREG between two modes that occupy the same numbers of words
6878 can be done by moving the SUBREG to the source. */
6879 else if (GET_CODE (SET_DEST (x)) == SUBREG
6880 /* We need SUBREGs to compute nonzero_bits properly. */
6881 && nonzero_sign_valid
6882 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6883 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6884 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6885 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6887 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6889 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6896 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6897 inner = SUBREG_REG (inner);
6899 compute_mode = GET_MODE (inner);
6901 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6902 if (! SCALAR_INT_MODE_P (compute_mode))
6904 enum machine_mode imode;
6906 /* Don't do anything for vector or complex integral types. */
6907 if (! FLOAT_MODE_P (compute_mode))
6910 /* Try to find an integral mode to pun with. */
6911 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6912 if (imode == BLKmode)
6915 compute_mode = imode;
6916 inner = gen_lowpart (imode, inner);
6919 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6920 if (len >= HOST_BITS_PER_WIDE_INT)
6923 /* Now compute the equivalent expression. Make a copy of INNER
6924 for the SET_DEST in case it is a MEM into which we will substitute;
6925 we don't want shared RTL in that case. */
6926 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6927 cleared = simplify_gen_binary (AND, compute_mode,
6928 simplify_gen_unary (NOT, compute_mode,
6929 simplify_gen_binary (ASHIFT,
6934 masked = simplify_gen_binary (ASHIFT, compute_mode,
6935 simplify_gen_binary (
6937 gen_lowpart (compute_mode, SET_SRC (x)),
6941 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6942 simplify_gen_binary (IOR, compute_mode,
6949 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6950 it is an RTX that represents a variable starting position; otherwise,
6951 POS is the (constant) starting bit position (counted from the LSB).
6953 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6956 IN_DEST is nonzero if this is a reference in the destination of a
6957 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6958 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6961 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6962 ZERO_EXTRACT should be built even for bits starting at bit 0.
6964 MODE is the desired mode of the result (if IN_DEST == 0).
6966 The result is an RTX for the extraction or NULL_RTX if the target
6970 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6971 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6972 int in_dest, int in_compare)
6974 /* This mode describes the size of the storage area
6975 to fetch the overall value from. Within that, we
6976 ignore the POS lowest bits, etc. */
6977 enum machine_mode is_mode = GET_MODE (inner);
6978 enum machine_mode inner_mode;
6979 enum machine_mode wanted_inner_mode;
6980 enum machine_mode wanted_inner_reg_mode = word_mode;
6981 enum machine_mode pos_mode = word_mode;
6982 enum machine_mode extraction_mode = word_mode;
6983 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6985 rtx orig_pos_rtx = pos_rtx;
6986 HOST_WIDE_INT orig_pos;
6988 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6990 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6991 consider just the QI as the memory to extract from.
6992 The subreg adds or removes high bits; its mode is
6993 irrelevant to the meaning of this extraction,
6994 since POS and LEN count from the lsb. */
6995 if (MEM_P (SUBREG_REG (inner)))
6996 is_mode = GET_MODE (SUBREG_REG (inner));
6997 inner = SUBREG_REG (inner);
6999 else if (GET_CODE (inner) == ASHIFT
7000 && CONST_INT_P (XEXP (inner, 1))
7001 && pos_rtx == 0 && pos == 0
7002 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
7004 /* We're extracting the least significant bits of an rtx
7005 (ashift X (const_int C)), where LEN > C. Extract the
7006 least significant (LEN - C) bits of X, giving an rtx
7007 whose mode is MODE, then shift it left C times. */
7008 new_rtx = make_extraction (mode, XEXP (inner, 0),
7009 0, 0, len - INTVAL (XEXP (inner, 1)),
7010 unsignedp, in_dest, in_compare);
7012 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7015 inner_mode = GET_MODE (inner);
7017 if (pos_rtx && CONST_INT_P (pos_rtx))
7018 pos = INTVAL (pos_rtx), pos_rtx = 0;
7020 /* See if this can be done without an extraction. We never can if the
7021 width of the field is not the same as that of some integer mode. For
7022 registers, we can only avoid the extraction if the position is at the
7023 low-order bit and this is either not in the destination or we have the
7024 appropriate STRICT_LOW_PART operation available.
7026 For MEM, we can avoid an extract if the field starts on an appropriate
7027 boundary and we can change the mode of the memory reference. */
7029 if (tmode != BLKmode
7030 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7032 && (inner_mode == tmode
7034 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7035 GET_MODE_BITSIZE (inner_mode))
7036 || reg_truncated_to_mode (tmode, inner))
7039 && have_insn_for (STRICT_LOW_PART, tmode))))
7040 || (MEM_P (inner) && pos_rtx == 0
7042 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7043 : BITS_PER_UNIT)) == 0
7044 /* We can't do this if we are widening INNER_MODE (it
7045 may not be aligned, for one thing). */
7046 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7047 && (inner_mode == tmode
7048 || (! mode_dependent_address_p (XEXP (inner, 0))
7049 && ! MEM_VOLATILE_P (inner))))))
7051 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7052 field. If the original and current mode are the same, we need not
7053 adjust the offset. Otherwise, we do if bytes big endian.
7055 If INNER is not a MEM, get a piece consisting of just the field
7056 of interest (in this case POS % BITS_PER_WORD must be 0). */
7060 HOST_WIDE_INT offset;
7062 /* POS counts from lsb, but make OFFSET count in memory order. */
7063 if (BYTES_BIG_ENDIAN)
7064 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7066 offset = pos / BITS_PER_UNIT;
7068 new_rtx = adjust_address_nv (inner, tmode, offset);
7070 else if (REG_P (inner))
7072 if (tmode != inner_mode)
7074 /* We can't call gen_lowpart in a DEST since we
7075 always want a SUBREG (see below) and it would sometimes
7076 return a new hard register. */
7079 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7081 if (WORDS_BIG_ENDIAN
7082 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7083 final_word = ((GET_MODE_SIZE (inner_mode)
7084 - GET_MODE_SIZE (tmode))
7085 / UNITS_PER_WORD) - final_word;
7087 final_word *= UNITS_PER_WORD;
7088 if (BYTES_BIG_ENDIAN &&
7089 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7090 final_word += (GET_MODE_SIZE (inner_mode)
7091 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7093 /* Avoid creating invalid subregs, for example when
7094 simplifying (x>>32)&255. */
7095 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7098 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7101 new_rtx = gen_lowpart (tmode, inner);
7107 new_rtx = force_to_mode (inner, tmode,
7108 len >= HOST_BITS_PER_WIDE_INT
7109 ? ~(unsigned HOST_WIDE_INT) 0
7110 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7113 /* If this extraction is going into the destination of a SET,
7114 make a STRICT_LOW_PART unless we made a MEM. */
7117 return (MEM_P (new_rtx) ? new_rtx
7118 : (GET_CODE (new_rtx) != SUBREG
7119 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7120 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7125 if (CONST_INT_P (new_rtx)
7126 || GET_CODE (new_rtx) == CONST_DOUBLE)
7127 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7128 mode, new_rtx, tmode);
7130 /* If we know that no extraneous bits are set, and that the high
7131 bit is not set, convert the extraction to the cheaper of
7132 sign and zero extension, that are equivalent in these cases. */
7133 if (flag_expensive_optimizations
7134 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7135 && ((nonzero_bits (new_rtx, tmode)
7136 & ~(((unsigned HOST_WIDE_INT)
7137 GET_MODE_MASK (tmode))
7141 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7142 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7144 /* Prefer ZERO_EXTENSION, since it gives more information to
7146 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7147 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7152 /* Otherwise, sign- or zero-extend unless we already are in the
7155 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7159 /* Unless this is a COMPARE or we have a funny memory reference,
7160 don't do anything with zero-extending field extracts starting at
7161 the low-order bit since they are simple AND operations. */
7162 if (pos_rtx == 0 && pos == 0 && ! in_dest
7163 && ! in_compare && unsignedp)
7166 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7167 if the position is not a constant and the length is not 1. In all
7168 other cases, we would only be going outside our object in cases when
7169 an original shift would have been undefined. */
7171 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7172 || (pos_rtx != 0 && len != 1)))
7175 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7176 and the mode for the result. */
7177 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7179 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7180 pos_mode = mode_for_extraction (EP_insv, 2);
7181 extraction_mode = mode_for_extraction (EP_insv, 3);
7184 if (! in_dest && unsignedp
7185 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7187 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7188 pos_mode = mode_for_extraction (EP_extzv, 3);
7189 extraction_mode = mode_for_extraction (EP_extzv, 0);
7192 if (! in_dest && ! unsignedp
7193 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7195 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7196 pos_mode = mode_for_extraction (EP_extv, 3);
7197 extraction_mode = mode_for_extraction (EP_extv, 0);
7200 /* Never narrow an object, since that might not be safe. */
7202 if (mode != VOIDmode
7203 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7204 extraction_mode = mode;
7206 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7207 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7208 pos_mode = GET_MODE (pos_rtx);
7210 /* If this is not from memory, the desired mode is the preferred mode
7211 for an extraction pattern's first input operand, or word_mode if there
7214 wanted_inner_mode = wanted_inner_reg_mode;
7217 /* Be careful not to go beyond the extracted object and maintain the
7218 natural alignment of the memory. */
7219 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7220 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7221 > GET_MODE_BITSIZE (wanted_inner_mode))
7223 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7224 gcc_assert (wanted_inner_mode != VOIDmode);
7227 /* If we have to change the mode of memory and cannot, the desired mode
7228 is EXTRACTION_MODE. */
7229 if (inner_mode != wanted_inner_mode
7230 && (mode_dependent_address_p (XEXP (inner, 0))
7231 || MEM_VOLATILE_P (inner)
7233 wanted_inner_mode = extraction_mode;
7238 if (BITS_BIG_ENDIAN)
7240 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7241 BITS_BIG_ENDIAN style. If position is constant, compute new
7242 position. Otherwise, build subtraction.
7243 Note that POS is relative to the mode of the original argument.
7244 If it's a MEM we need to recompute POS relative to that.
7245 However, if we're extracting from (or inserting into) a register,
7246 we want to recompute POS relative to wanted_inner_mode. */
7247 int width = (MEM_P (inner)
7248 ? GET_MODE_BITSIZE (is_mode)
7249 : GET_MODE_BITSIZE (wanted_inner_mode));
7252 pos = width - len - pos;
7255 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7256 /* POS may be less than 0 now, but we check for that below.
7257 Note that it can only be less than 0 if !MEM_P (inner). */
7260 /* If INNER has a wider mode, and this is a constant extraction, try to
7261 make it smaller and adjust the byte to point to the byte containing
7263 if (wanted_inner_mode != VOIDmode
7264 && inner_mode != wanted_inner_mode
7266 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7268 && ! mode_dependent_address_p (XEXP (inner, 0))
7269 && ! MEM_VOLATILE_P (inner))
7273 /* The computations below will be correct if the machine is big
7274 endian in both bits and bytes or little endian in bits and bytes.
7275 If it is mixed, we must adjust. */
7277 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7278 adjust OFFSET to compensate. */
7279 if (BYTES_BIG_ENDIAN
7280 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7281 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7283 /* We can now move to the desired byte. */
7284 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7285 * GET_MODE_SIZE (wanted_inner_mode);
7286 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7288 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7289 && is_mode != wanted_inner_mode)
7290 offset = (GET_MODE_SIZE (is_mode)
7291 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7293 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7296 /* If INNER is not memory, get it into the proper mode. If we are changing
7297 its mode, POS must be a constant and smaller than the size of the new
7299 else if (!MEM_P (inner))
7301 /* On the LHS, don't create paradoxical subregs implicitely truncating
7302 the register unless TRULY_NOOP_TRUNCATION. */
7304 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7305 GET_MODE_BITSIZE (wanted_inner_mode)))
7308 if (GET_MODE (inner) != wanted_inner_mode
7310 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7316 inner = force_to_mode (inner, wanted_inner_mode,
7318 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7319 ? ~(unsigned HOST_WIDE_INT) 0
7320 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7325 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7326 have to zero extend. Otherwise, we can just use a SUBREG. */
7328 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7330 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7332 /* If we know that no extraneous bits are set, and that the high
7333 bit is not set, convert extraction to cheaper one - either
7334 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7336 if (flag_expensive_optimizations
7337 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7338 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7339 & ~(((unsigned HOST_WIDE_INT)
7340 GET_MODE_MASK (GET_MODE (pos_rtx)))
7344 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7346 /* Prefer ZERO_EXTENSION, since it gives more information to
7348 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7349 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7354 else if (pos_rtx != 0
7355 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7356 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7358 /* Make POS_RTX unless we already have it and it is correct. If we don't
7359 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7361 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7362 pos_rtx = orig_pos_rtx;
7364 else if (pos_rtx == 0)
7365 pos_rtx = GEN_INT (pos);
7367 /* Make the required operation. See if we can use existing rtx. */
7368 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7369 extraction_mode, inner, GEN_INT (len), pos_rtx);
7371 new_rtx = gen_lowpart (mode, new_rtx);
7376 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7377 with any other operations in X. Return X without that shift if so. */
7380 extract_left_shift (rtx x, int count)
7382 enum rtx_code code = GET_CODE (x);
7383 enum machine_mode mode = GET_MODE (x);
7389 /* This is the shift itself. If it is wide enough, we will return
7390 either the value being shifted if the shift count is equal to
7391 COUNT or a shift for the difference. */
7392 if (CONST_INT_P (XEXP (x, 1))
7393 && INTVAL (XEXP (x, 1)) >= count)
7394 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7395 INTVAL (XEXP (x, 1)) - count);
7399 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7400 return simplify_gen_unary (code, mode, tem, mode);
7404 case PLUS: case IOR: case XOR: case AND:
7405 /* If we can safely shift this constant and we find the inner shift,
7406 make a new operation. */
7407 if (CONST_INT_P (XEXP (x, 1))
7408 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7409 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7410 return simplify_gen_binary (code, mode, tem,
7411 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7422 /* Look at the expression rooted at X. Look for expressions
7423 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7424 Form these expressions.
7426 Return the new rtx, usually just X.
7428 Also, for machines like the VAX that don't have logical shift insns,
7429 try to convert logical to arithmetic shift operations in cases where
7430 they are equivalent. This undoes the canonicalizations to logical
7431 shifts done elsewhere.
7433 We try, as much as possible, to re-use rtl expressions to save memory.
7435 IN_CODE says what kind of expression we are processing. Normally, it is
7436 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7437 being kludges), it is MEM. When processing the arguments of a comparison
7438 or a COMPARE against zero, it is COMPARE. */
7441 make_compound_operation (rtx x, enum rtx_code in_code)
7443 enum rtx_code code = GET_CODE (x);
7444 enum machine_mode mode = GET_MODE (x);
7445 int mode_width = GET_MODE_BITSIZE (mode);
7447 enum rtx_code next_code;
7453 /* Select the code to be used in recursive calls. Once we are inside an
7454 address, we stay there. If we have a comparison, set to COMPARE,
7455 but once inside, go back to our default of SET. */
7457 next_code = (code == MEM ? MEM
7458 : ((code == PLUS || code == MINUS)
7459 && SCALAR_INT_MODE_P (mode)) ? MEM
7460 : ((code == COMPARE || COMPARISON_P (x))
7461 && XEXP (x, 1) == const0_rtx) ? COMPARE
7462 : in_code == COMPARE ? SET : in_code);
7464 /* Process depending on the code of this operation. If NEW is set
7465 nonzero, it will be returned. */
7470 /* Convert shifts by constants into multiplications if inside
7472 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7473 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7474 && INTVAL (XEXP (x, 1)) >= 0)
7476 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7477 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7479 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7480 if (GET_CODE (new_rtx) == NEG)
7482 new_rtx = XEXP (new_rtx, 0);
7485 multval = trunc_int_for_mode (multval, mode);
7486 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7493 lhs = make_compound_operation (lhs, next_code);
7494 rhs = make_compound_operation (rhs, next_code);
7495 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7496 && SCALAR_INT_MODE_P (mode))
7498 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7500 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7502 else if (GET_CODE (lhs) == MULT
7503 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7505 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7506 simplify_gen_unary (NEG, mode,
7509 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7513 SUBST (XEXP (x, 0), lhs);
7514 SUBST (XEXP (x, 1), rhs);
7517 x = gen_lowpart (mode, new_rtx);
7523 lhs = make_compound_operation (lhs, next_code);
7524 rhs = make_compound_operation (rhs, next_code);
7525 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7526 && SCALAR_INT_MODE_P (mode))
7528 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7530 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7532 else if (GET_CODE (rhs) == MULT
7533 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7535 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7536 simplify_gen_unary (NEG, mode,
7539 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7543 SUBST (XEXP (x, 0), lhs);
7544 SUBST (XEXP (x, 1), rhs);
7547 return gen_lowpart (mode, new_rtx);
7550 /* If the second operand is not a constant, we can't do anything
7552 if (!CONST_INT_P (XEXP (x, 1)))
7555 /* If the constant is a power of two minus one and the first operand
7556 is a logical right shift, make an extraction. */
7557 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7558 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7560 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7561 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7562 0, in_code == COMPARE);
7565 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7566 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7567 && subreg_lowpart_p (XEXP (x, 0))
7568 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7569 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7571 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7573 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7574 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7575 0, in_code == COMPARE);
7577 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7578 else if ((GET_CODE (XEXP (x, 0)) == XOR
7579 || GET_CODE (XEXP (x, 0)) == IOR)
7580 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7581 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7582 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7584 /* Apply the distributive law, and then try to make extractions. */
7585 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7586 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7588 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7590 new_rtx = make_compound_operation (new_rtx, in_code);
7593 /* If we are have (and (rotate X C) M) and C is larger than the number
7594 of bits in M, this is an extraction. */
7596 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7597 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7598 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7599 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7601 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7602 new_rtx = make_extraction (mode, new_rtx,
7603 (GET_MODE_BITSIZE (mode)
7604 - INTVAL (XEXP (XEXP (x, 0), 1))),
7605 NULL_RTX, i, 1, 0, in_code == COMPARE);
7608 /* On machines without logical shifts, if the operand of the AND is
7609 a logical shift and our mask turns off all the propagated sign
7610 bits, we can replace the logical shift with an arithmetic shift. */
7611 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7612 && !have_insn_for (LSHIFTRT, mode)
7613 && have_insn_for (ASHIFTRT, mode)
7614 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7615 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7616 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7617 && mode_width <= HOST_BITS_PER_WIDE_INT)
7619 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7621 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7622 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7624 gen_rtx_ASHIFTRT (mode,
7625 make_compound_operation
7626 (XEXP (XEXP (x, 0), 0), next_code),
7627 XEXP (XEXP (x, 0), 1)));
7630 /* If the constant is one less than a power of two, this might be
7631 representable by an extraction even if no shift is present.
7632 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7633 we are in a COMPARE. */
7634 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7635 new_rtx = make_extraction (mode,
7636 make_compound_operation (XEXP (x, 0),
7638 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7640 /* If we are in a comparison and this is an AND with a power of two,
7641 convert this into the appropriate bit extract. */
7642 else if (in_code == COMPARE
7643 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7644 new_rtx = make_extraction (mode,
7645 make_compound_operation (XEXP (x, 0),
7647 i, NULL_RTX, 1, 1, 0, 1);
7652 /* If the sign bit is known to be zero, replace this with an
7653 arithmetic shift. */
7654 if (have_insn_for (ASHIFTRT, mode)
7655 && ! have_insn_for (LSHIFTRT, mode)
7656 && mode_width <= HOST_BITS_PER_WIDE_INT
7657 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7659 new_rtx = gen_rtx_ASHIFTRT (mode,
7660 make_compound_operation (XEXP (x, 0),
7666 /* ... fall through ... */
7672 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7673 this is a SIGN_EXTRACT. */
7674 if (CONST_INT_P (rhs)
7675 && GET_CODE (lhs) == ASHIFT
7676 && CONST_INT_P (XEXP (lhs, 1))
7677 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7678 && INTVAL (rhs) < mode_width)
7680 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7681 new_rtx = make_extraction (mode, new_rtx,
7682 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7683 NULL_RTX, mode_width - INTVAL (rhs),
7684 code == LSHIFTRT, 0, in_code == COMPARE);
7688 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7689 If so, try to merge the shifts into a SIGN_EXTEND. We could
7690 also do this for some cases of SIGN_EXTRACT, but it doesn't
7691 seem worth the effort; the case checked for occurs on Alpha. */
7694 && ! (GET_CODE (lhs) == SUBREG
7695 && (OBJECT_P (SUBREG_REG (lhs))))
7696 && CONST_INT_P (rhs)
7697 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7698 && INTVAL (rhs) < mode_width
7699 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7700 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7701 0, NULL_RTX, mode_width - INTVAL (rhs),
7702 code == LSHIFTRT, 0, in_code == COMPARE);
7707 /* Call ourselves recursively on the inner expression. If we are
7708 narrowing the object and it has a different RTL code from
7709 what it originally did, do this SUBREG as a force_to_mode. */
7711 rtx inner = SUBREG_REG (x), simplified;
7713 tem = make_compound_operation (inner, in_code);
7716 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7720 if (GET_CODE (tem) != GET_CODE (inner)
7721 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7722 && subreg_lowpart_p (x))
7724 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0, 0);
7726 /* If we have something other than a SUBREG, we might have
7727 done an expansion, so rerun ourselves. */
7728 if (GET_CODE (newer) != SUBREG)
7729 newer = make_compound_operation (newer, in_code);
7731 /* force_to_mode can expand compounds. If it just re-expanded the
7732 compound, use gen_lowpart to convert to the desired mode. */
7733 if (rtx_equal_p (newer, x)
7734 /* Likewise if it re-expanded the compound only partially.
7735 This happens for SUBREG of ZERO_EXTRACT if they extract
7736 the same number of bits. */
7737 || (GET_CODE (newer) == SUBREG
7738 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7739 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7740 && GET_CODE (inner) == AND
7741 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7742 return gen_lowpart (GET_MODE (x), tem);
7758 x = gen_lowpart (mode, new_rtx);
7759 code = GET_CODE (x);
7762 /* Now recursively process each operand of this operation. */
7763 fmt = GET_RTX_FORMAT (code);
7764 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7767 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7768 SUBST (XEXP (x, i), new_rtx);
7770 else if (fmt[i] == 'E')
7771 for (j = 0; j < XVECLEN (x, i); j++)
7773 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7774 SUBST (XVECEXP (x, i, j), new_rtx);
7778 /* If this is a commutative operation, the changes to the operands
7779 may have made it noncanonical. */
7780 if (COMMUTATIVE_ARITH_P (x)
7781 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7784 SUBST (XEXP (x, 0), XEXP (x, 1));
7785 SUBST (XEXP (x, 1), tem);
7791 /* Given M see if it is a value that would select a field of bits
7792 within an item, but not the entire word. Return -1 if not.
7793 Otherwise, return the starting position of the field, where 0 is the
7796 *PLEN is set to the length of the field. */
7799 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7801 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7802 int pos = m ? ctz_hwi (m) : -1;
7806 /* Now shift off the low-order zero bits and see if we have a
7807 power of two minus 1. */
7808 len = exact_log2 ((m >> pos) + 1);
7817 /* If X refers to a register that equals REG in value, replace these
7818 references with REG. */
7820 canon_reg_for_combine (rtx x, rtx reg)
7827 enum rtx_code code = GET_CODE (x);
7828 switch (GET_RTX_CLASS (code))
7831 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7832 if (op0 != XEXP (x, 0))
7833 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7838 case RTX_COMM_ARITH:
7839 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7840 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7841 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7842 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7846 case RTX_COMM_COMPARE:
7847 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7848 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7849 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7850 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7851 GET_MODE (op0), op0, op1);
7855 case RTX_BITFIELD_OPS:
7856 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7857 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7858 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7859 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7860 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7861 GET_MODE (op0), op0, op1, op2);
7866 if (rtx_equal_p (get_last_value (reg), x)
7867 || rtx_equal_p (reg, get_last_value (x)))
7876 fmt = GET_RTX_FORMAT (code);
7878 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7881 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7882 if (op != XEXP (x, i))
7892 else if (fmt[i] == 'E')
7895 for (j = 0; j < XVECLEN (x, i); j++)
7897 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7898 if (op != XVECEXP (x, i, j))
7905 XVECEXP (x, i, j) = op;
7916 /* Return X converted to MODE. If the value is already truncated to
7917 MODE we can just return a subreg even though in the general case we
7918 would need an explicit truncation. */
7921 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7923 if (!CONST_INT_P (x)
7924 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7925 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7926 GET_MODE_BITSIZE (GET_MODE (x)))
7927 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7929 /* Bit-cast X into an integer mode. */
7930 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7931 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7932 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7936 return gen_lowpart (mode, x);
7939 /* See if X can be simplified knowing that we will only refer to it in
7940 MODE and will only refer to those bits that are nonzero in MASK.
7941 If other bits are being computed or if masking operations are done
7942 that select a superset of the bits in MASK, they can sometimes be
7945 Return a possibly simplified expression, but always convert X to
7946 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7948 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7949 are all off in X. This is used when X will be complemented, by either
7950 NOT, NEG, or XOR. */
7953 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7956 enum rtx_code code = GET_CODE (x);
7957 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7958 enum machine_mode op_mode;
7959 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7962 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7963 code below will do the wrong thing since the mode of such an
7964 expression is VOIDmode.
7966 Also do nothing if X is a CLOBBER; this can happen if X was
7967 the return value from a call to gen_lowpart. */
7968 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7971 /* We want to perform the operation is its present mode unless we know
7972 that the operation is valid in MODE, in which case we do the operation
7974 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7975 && have_insn_for (code, mode))
7976 ? mode : GET_MODE (x));
7978 /* It is not valid to do a right-shift in a narrower mode
7979 than the one it came in with. */
7980 if ((code == LSHIFTRT || code == ASHIFTRT)
7981 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7982 op_mode = GET_MODE (x);
7984 /* Truncate MASK to fit OP_MODE. */
7986 mask &= GET_MODE_MASK (op_mode);
7988 /* When we have an arithmetic operation, or a shift whose count we
7989 do not know, we need to assume that all bits up to the highest-order
7990 bit in MASK will be needed. This is how we form such a mask. */
7991 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7992 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7994 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7997 /* Determine what bits of X are guaranteed to be (non)zero. */
7998 nonzero = nonzero_bits (x, mode);
8000 /* If none of the bits in X are needed, return a zero. */
8001 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8004 /* If X is a CONST_INT, return a new one. Do this here since the
8005 test below will fail. */
8006 if (CONST_INT_P (x))
8008 if (SCALAR_INT_MODE_P (mode))
8009 return gen_int_mode (INTVAL (x) & mask, mode);
8012 x = GEN_INT (INTVAL (x) & mask);
8013 return gen_lowpart_common (mode, x);
8017 /* If X is narrower than MODE and we want all the bits in X's mode, just
8018 get X in the proper mode. */
8019 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8020 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8021 return gen_lowpart (mode, x);
8023 /* We can ignore the effect of a SUBREG if it narrows the mode or
8024 if the constant masks to zero all the bits the mode doesn't have. */
8025 if (GET_CODE (x) == SUBREG
8026 && subreg_lowpart_p (x)
8027 && ((GET_MODE_SIZE (GET_MODE (x))
8028 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8030 & GET_MODE_MASK (GET_MODE (x))
8031 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8032 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8034 /* The arithmetic simplifications here only work for scalar integer modes. */
8035 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8036 return gen_lowpart_or_truncate (mode, x);
8041 /* If X is a (clobber (const_int)), return it since we know we are
8042 generating something that won't match. */
8049 x = expand_compound_operation (x);
8050 if (GET_CODE (x) != code)
8051 return force_to_mode (x, mode, mask, next_select);
8055 /* Similarly for a truncate. */
8056 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8059 /* If this is an AND with a constant, convert it into an AND
8060 whose constant is the AND of that constant with MASK. If it
8061 remains an AND of MASK, delete it since it is redundant. */
8063 if (CONST_INT_P (XEXP (x, 1)))
8065 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8066 mask & INTVAL (XEXP (x, 1)));
8068 /* If X is still an AND, see if it is an AND with a mask that
8069 is just some low-order bits. If so, and it is MASK, we don't
8072 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8073 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8077 /* If it remains an AND, try making another AND with the bits
8078 in the mode mask that aren't in MASK turned on. If the
8079 constant in the AND is wide enough, this might make a
8080 cheaper constant. */
8082 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8083 && GET_MODE_MASK (GET_MODE (x)) != mask
8084 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8086 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
8087 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
8088 int width = GET_MODE_BITSIZE (GET_MODE (x));
8091 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8092 number, sign extend it. */
8093 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8094 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8095 cval |= (HOST_WIDE_INT) -1 << width;
8097 y = simplify_gen_binary (AND, GET_MODE (x),
8098 XEXP (x, 0), GEN_INT (cval));
8099 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8100 < rtx_cost (x, SET, optimize_this_for_speed_p))
8110 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8111 low-order bits (as in an alignment operation) and FOO is already
8112 aligned to that boundary, mask C1 to that boundary as well.
8113 This may eliminate that PLUS and, later, the AND. */
8116 unsigned int width = GET_MODE_BITSIZE (mode);
8117 unsigned HOST_WIDE_INT smask = mask;
8119 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8120 number, sign extend it. */
8122 if (width < HOST_BITS_PER_WIDE_INT
8123 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8124 smask |= (HOST_WIDE_INT) -1 << width;
8126 if (CONST_INT_P (XEXP (x, 1))
8127 && exact_log2 (- smask) >= 0
8128 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8129 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8130 return force_to_mode (plus_constant (XEXP (x, 0),
8131 (INTVAL (XEXP (x, 1)) & smask)),
8132 mode, smask, next_select);
8135 /* ... fall through ... */
8138 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8139 most significant bit in MASK since carries from those bits will
8140 affect the bits we are interested in. */
8145 /* If X is (minus C Y) where C's least set bit is larger than any bit
8146 in the mask, then we may replace with (neg Y). */
8147 if (CONST_INT_P (XEXP (x, 0))
8148 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8149 & -INTVAL (XEXP (x, 0))))
8152 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8154 return force_to_mode (x, mode, mask, next_select);
8157 /* Similarly, if C contains every bit in the fuller_mask, then we may
8158 replace with (not Y). */
8159 if (CONST_INT_P (XEXP (x, 0))
8160 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
8161 == INTVAL (XEXP (x, 0))))
8163 x = simplify_gen_unary (NOT, GET_MODE (x),
8164 XEXP (x, 1), GET_MODE (x));
8165 return force_to_mode (x, mode, mask, next_select);
8173 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8174 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8175 operation which may be a bitfield extraction. Ensure that the
8176 constant we form is not wider than the mode of X. */
8178 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8179 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8180 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8181 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8182 && CONST_INT_P (XEXP (x, 1))
8183 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8184 + floor_log2 (INTVAL (XEXP (x, 1))))
8185 < GET_MODE_BITSIZE (GET_MODE (x)))
8186 && (INTVAL (XEXP (x, 1))
8187 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8189 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8190 << INTVAL (XEXP (XEXP (x, 0), 1)));
8191 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8192 XEXP (XEXP (x, 0), 0), temp);
8193 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8194 XEXP (XEXP (x, 0), 1));
8195 return force_to_mode (x, mode, mask, next_select);
8199 /* For most binary operations, just propagate into the operation and
8200 change the mode if we have an operation of that mode. */
8202 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8203 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8205 /* If we ended up truncating both operands, truncate the result of the
8206 operation instead. */
8207 if (GET_CODE (op0) == TRUNCATE
8208 && GET_CODE (op1) == TRUNCATE)
8210 op0 = XEXP (op0, 0);
8211 op1 = XEXP (op1, 0);
8214 op0 = gen_lowpart_or_truncate (op_mode, op0);
8215 op1 = gen_lowpart_or_truncate (op_mode, op1);
8217 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8218 x = simplify_gen_binary (code, op_mode, op0, op1);
8222 /* For left shifts, do the same, but just for the first operand.
8223 However, we cannot do anything with shifts where we cannot
8224 guarantee that the counts are smaller than the size of the mode
8225 because such a count will have a different meaning in a
8228 if (! (CONST_INT_P (XEXP (x, 1))
8229 && INTVAL (XEXP (x, 1)) >= 0
8230 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8231 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8232 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8233 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8236 /* If the shift count is a constant and we can do arithmetic in
8237 the mode of the shift, refine which bits we need. Otherwise, use the
8238 conservative form of the mask. */
8239 if (CONST_INT_P (XEXP (x, 1))
8240 && INTVAL (XEXP (x, 1)) >= 0
8241 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8242 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8243 mask >>= INTVAL (XEXP (x, 1));
8247 op0 = gen_lowpart_or_truncate (op_mode,
8248 force_to_mode (XEXP (x, 0), op_mode,
8249 mask, next_select));
8251 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8252 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8256 /* Here we can only do something if the shift count is a constant,
8257 this shift constant is valid for the host, and we can do arithmetic
8260 if (CONST_INT_P (XEXP (x, 1))
8261 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8262 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8264 rtx inner = XEXP (x, 0);
8265 unsigned HOST_WIDE_INT inner_mask;
8267 /* Select the mask of the bits we need for the shift operand. */
8268 inner_mask = mask << INTVAL (XEXP (x, 1));
8270 /* We can only change the mode of the shift if we can do arithmetic
8271 in the mode of the shift and INNER_MASK is no wider than the
8272 width of X's mode. */
8273 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8274 op_mode = GET_MODE (x);
8276 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8278 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8279 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8282 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8283 shift and AND produces only copies of the sign bit (C2 is one less
8284 than a power of two), we can do this with just a shift. */
8286 if (GET_CODE (x) == LSHIFTRT
8287 && CONST_INT_P (XEXP (x, 1))
8288 /* The shift puts one of the sign bit copies in the least significant
8290 && ((INTVAL (XEXP (x, 1))
8291 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8292 >= GET_MODE_BITSIZE (GET_MODE (x)))
8293 && exact_log2 (mask + 1) >= 0
8294 /* Number of bits left after the shift must be more than the mask
8296 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8297 <= GET_MODE_BITSIZE (GET_MODE (x)))
8298 /* Must be more sign bit copies than the mask needs. */
8299 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8300 >= exact_log2 (mask + 1)))
8301 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8302 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8303 - exact_log2 (mask + 1)));
8308 /* If we are just looking for the sign bit, we don't need this shift at
8309 all, even if it has a variable count. */
8310 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8311 && (mask == ((unsigned HOST_WIDE_INT) 1
8312 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8313 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8315 /* If this is a shift by a constant, get a mask that contains those bits
8316 that are not copies of the sign bit. We then have two cases: If
8317 MASK only includes those bits, this can be a logical shift, which may
8318 allow simplifications. If MASK is a single-bit field not within
8319 those bits, we are requesting a copy of the sign bit and hence can
8320 shift the sign bit to the appropriate location. */
8322 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8323 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8327 /* If the considered data is wider than HOST_WIDE_INT, we can't
8328 represent a mask for all its bits in a single scalar.
8329 But we only care about the lower bits, so calculate these. */
8331 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8333 nonzero = ~(HOST_WIDE_INT) 0;
8335 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8336 is the number of bits a full-width mask would have set.
8337 We need only shift if these are fewer than nonzero can
8338 hold. If not, we must keep all bits set in nonzero. */
8340 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8341 < HOST_BITS_PER_WIDE_INT)
8342 nonzero >>= INTVAL (XEXP (x, 1))
8343 + HOST_BITS_PER_WIDE_INT
8344 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8348 nonzero = GET_MODE_MASK (GET_MODE (x));
8349 nonzero >>= INTVAL (XEXP (x, 1));
8352 if ((mask & ~nonzero) == 0)
8354 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8355 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8356 if (GET_CODE (x) != ASHIFTRT)
8357 return force_to_mode (x, mode, mask, next_select);
8360 else if ((i = exact_log2 (mask)) >= 0)
8362 x = simplify_shift_const
8363 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8364 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8366 if (GET_CODE (x) != ASHIFTRT)
8367 return force_to_mode (x, mode, mask, next_select);
8371 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8372 even if the shift count isn't a constant. */
8374 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8375 XEXP (x, 0), XEXP (x, 1));
8379 /* If this is a zero- or sign-extension operation that just affects bits
8380 we don't care about, remove it. Be sure the call above returned
8381 something that is still a shift. */
8383 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8384 && CONST_INT_P (XEXP (x, 1))
8385 && INTVAL (XEXP (x, 1)) >= 0
8386 && (INTVAL (XEXP (x, 1))
8387 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8388 && GET_CODE (XEXP (x, 0)) == ASHIFT
8389 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8390 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8397 /* If the shift count is constant and we can do computations
8398 in the mode of X, compute where the bits we care about are.
8399 Otherwise, we can't do anything. Don't change the mode of
8400 the shift or propagate MODE into the shift, though. */
8401 if (CONST_INT_P (XEXP (x, 1))
8402 && INTVAL (XEXP (x, 1)) >= 0)
8404 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8405 GET_MODE (x), GEN_INT (mask),
8407 if (temp && CONST_INT_P (temp))
8409 force_to_mode (XEXP (x, 0), GET_MODE (x),
8410 INTVAL (temp), next_select));
8415 /* If we just want the low-order bit, the NEG isn't needed since it
8416 won't change the low-order bit. */
8418 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8420 /* We need any bits less significant than the most significant bit in
8421 MASK since carries from those bits will affect the bits we are
8427 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8428 same as the XOR case above. Ensure that the constant we form is not
8429 wider than the mode of X. */
8431 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8432 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8433 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8434 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8435 < GET_MODE_BITSIZE (GET_MODE (x)))
8436 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8438 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8440 temp = simplify_gen_binary (XOR, GET_MODE (x),
8441 XEXP (XEXP (x, 0), 0), temp);
8442 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8443 temp, XEXP (XEXP (x, 0), 1));
8445 return force_to_mode (x, mode, mask, next_select);
8448 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8449 use the full mask inside the NOT. */
8453 op0 = gen_lowpart_or_truncate (op_mode,
8454 force_to_mode (XEXP (x, 0), mode, mask,
8456 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8457 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8461 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8462 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8463 which is equal to STORE_FLAG_VALUE. */
8464 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8465 && GET_MODE (XEXP (x, 0)) == mode
8466 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8467 && (nonzero_bits (XEXP (x, 0), mode)
8468 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8469 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8474 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8475 written in a narrower mode. We play it safe and do not do so. */
8478 gen_lowpart_or_truncate (GET_MODE (x),
8479 force_to_mode (XEXP (x, 1), mode,
8480 mask, next_select)));
8482 gen_lowpart_or_truncate (GET_MODE (x),
8483 force_to_mode (XEXP (x, 2), mode,
8484 mask, next_select)));
8491 /* Ensure we return a value of the proper mode. */
8492 return gen_lowpart_or_truncate (mode, x);
8495 /* Return nonzero if X is an expression that has one of two values depending on
8496 whether some other value is zero or nonzero. In that case, we return the
8497 value that is being tested, *PTRUE is set to the value if the rtx being
8498 returned has a nonzero value, and *PFALSE is set to the other alternative.
8500 If we return zero, we set *PTRUE and *PFALSE to X. */
8503 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8505 enum machine_mode mode = GET_MODE (x);
8506 enum rtx_code code = GET_CODE (x);
8507 rtx cond0, cond1, true0, true1, false0, false1;
8508 unsigned HOST_WIDE_INT nz;
8510 /* If we are comparing a value against zero, we are done. */
8511 if ((code == NE || code == EQ)
8512 && XEXP (x, 1) == const0_rtx)
8514 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8515 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8519 /* If this is a unary operation whose operand has one of two values, apply
8520 our opcode to compute those values. */
8521 else if (UNARY_P (x)
8522 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8524 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8525 *pfalse = simplify_gen_unary (code, mode, false0,
8526 GET_MODE (XEXP (x, 0)));
8530 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8531 make can't possibly match and would suppress other optimizations. */
8532 else if (code == COMPARE)
8535 /* If this is a binary operation, see if either side has only one of two
8536 values. If either one does or if both do and they are conditional on
8537 the same value, compute the new true and false values. */
8538 else if (BINARY_P (x))
8540 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8541 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8543 if ((cond0 != 0 || cond1 != 0)
8544 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8546 /* If if_then_else_cond returned zero, then true/false are the
8547 same rtl. We must copy one of them to prevent invalid rtl
8550 true0 = copy_rtx (true0);
8551 else if (cond1 == 0)
8552 true1 = copy_rtx (true1);
8554 if (COMPARISON_P (x))
8556 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8558 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8563 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8564 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8567 return cond0 ? cond0 : cond1;
8570 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8571 operands is zero when the other is nonzero, and vice-versa,
8572 and STORE_FLAG_VALUE is 1 or -1. */
8574 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8575 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8577 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8579 rtx op0 = XEXP (XEXP (x, 0), 1);
8580 rtx op1 = XEXP (XEXP (x, 1), 1);
8582 cond0 = XEXP (XEXP (x, 0), 0);
8583 cond1 = XEXP (XEXP (x, 1), 0);
8585 if (COMPARISON_P (cond0)
8586 && COMPARISON_P (cond1)
8587 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8588 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8589 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8590 || ((swap_condition (GET_CODE (cond0))
8591 == reversed_comparison_code (cond1, NULL))
8592 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8593 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8594 && ! side_effects_p (x))
8596 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8597 *pfalse = simplify_gen_binary (MULT, mode,
8599 ? simplify_gen_unary (NEG, mode,
8607 /* Similarly for MULT, AND and UMIN, except that for these the result
8609 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8610 && (code == MULT || code == AND || code == UMIN)
8611 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8613 cond0 = XEXP (XEXP (x, 0), 0);
8614 cond1 = XEXP (XEXP (x, 1), 0);
8616 if (COMPARISON_P (cond0)
8617 && COMPARISON_P (cond1)
8618 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8619 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8620 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8621 || ((swap_condition (GET_CODE (cond0))
8622 == reversed_comparison_code (cond1, NULL))
8623 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8624 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8625 && ! side_effects_p (x))
8627 *ptrue = *pfalse = const0_rtx;
8633 else if (code == IF_THEN_ELSE)
8635 /* If we have IF_THEN_ELSE already, extract the condition and
8636 canonicalize it if it is NE or EQ. */
8637 cond0 = XEXP (x, 0);
8638 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8639 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8640 return XEXP (cond0, 0);
8641 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8643 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8644 return XEXP (cond0, 0);
8650 /* If X is a SUBREG, we can narrow both the true and false values
8651 if the inner expression, if there is a condition. */
8652 else if (code == SUBREG
8653 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8656 true0 = simplify_gen_subreg (mode, true0,
8657 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8658 false0 = simplify_gen_subreg (mode, false0,
8659 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8660 if (true0 && false0)
8668 /* If X is a constant, this isn't special and will cause confusions
8669 if we treat it as such. Likewise if it is equivalent to a constant. */
8670 else if (CONSTANT_P (x)
8671 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8674 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8675 will be least confusing to the rest of the compiler. */
8676 else if (mode == BImode)
8678 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8682 /* If X is known to be either 0 or -1, those are the true and
8683 false values when testing X. */
8684 else if (x == constm1_rtx || x == const0_rtx
8685 || (mode != VOIDmode
8686 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8688 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8692 /* Likewise for 0 or a single bit. */
8693 else if (SCALAR_INT_MODE_P (mode)
8694 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8695 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8697 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8701 /* Otherwise fail; show no condition with true and false values the same. */
8702 *ptrue = *pfalse = x;
8706 /* Return the value of expression X given the fact that condition COND
8707 is known to be true when applied to REG as its first operand and VAL
8708 as its second. X is known to not be shared and so can be modified in
8711 We only handle the simplest cases, and specifically those cases that
8712 arise with IF_THEN_ELSE expressions. */
8715 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8717 enum rtx_code code = GET_CODE (x);
8722 if (side_effects_p (x))
8725 /* If either operand of the condition is a floating point value,
8726 then we have to avoid collapsing an EQ comparison. */
8728 && rtx_equal_p (x, reg)
8729 && ! FLOAT_MODE_P (GET_MODE (x))
8730 && ! FLOAT_MODE_P (GET_MODE (val)))
8733 if (cond == UNEQ && rtx_equal_p (x, reg))
8736 /* If X is (abs REG) and we know something about REG's relationship
8737 with zero, we may be able to simplify this. */
8739 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8742 case GE: case GT: case EQ:
8745 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8747 GET_MODE (XEXP (x, 0)));
8752 /* The only other cases we handle are MIN, MAX, and comparisons if the
8753 operands are the same as REG and VAL. */
8755 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8757 if (rtx_equal_p (XEXP (x, 0), val))
8758 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8760 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8762 if (COMPARISON_P (x))
8764 if (comparison_dominates_p (cond, code))
8765 return const_true_rtx;
8767 code = reversed_comparison_code (x, NULL);
8769 && comparison_dominates_p (cond, code))
8774 else if (code == SMAX || code == SMIN
8775 || code == UMIN || code == UMAX)
8777 int unsignedp = (code == UMIN || code == UMAX);
8779 /* Do not reverse the condition when it is NE or EQ.
8780 This is because we cannot conclude anything about
8781 the value of 'SMAX (x, y)' when x is not equal to y,
8782 but we can when x equals y. */
8783 if ((code == SMAX || code == UMAX)
8784 && ! (cond == EQ || cond == NE))
8785 cond = reverse_condition (cond);
8790 return unsignedp ? x : XEXP (x, 1);
8792 return unsignedp ? x : XEXP (x, 0);
8794 return unsignedp ? XEXP (x, 1) : x;
8796 return unsignedp ? XEXP (x, 0) : x;
8803 else if (code == SUBREG)
8805 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8806 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8808 if (SUBREG_REG (x) != r)
8810 /* We must simplify subreg here, before we lose track of the
8811 original inner_mode. */
8812 new_rtx = simplify_subreg (GET_MODE (x), r,
8813 inner_mode, SUBREG_BYTE (x));
8817 SUBST (SUBREG_REG (x), r);
8822 /* We don't have to handle SIGN_EXTEND here, because even in the
8823 case of replacing something with a modeless CONST_INT, a
8824 CONST_INT is already (supposed to be) a valid sign extension for
8825 its narrower mode, which implies it's already properly
8826 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8827 story is different. */
8828 else if (code == ZERO_EXTEND)
8830 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8831 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8833 if (XEXP (x, 0) != r)
8835 /* We must simplify the zero_extend here, before we lose
8836 track of the original inner_mode. */
8837 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8842 SUBST (XEXP (x, 0), r);
8848 fmt = GET_RTX_FORMAT (code);
8849 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8852 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8853 else if (fmt[i] == 'E')
8854 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8855 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8862 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8863 assignment as a field assignment. */
8866 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8868 if (x == y || rtx_equal_p (x, y))
8871 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8874 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8875 Note that all SUBREGs of MEM are paradoxical; otherwise they
8876 would have been rewritten. */
8877 if (MEM_P (x) && GET_CODE (y) == SUBREG
8878 && MEM_P (SUBREG_REG (y))
8879 && rtx_equal_p (SUBREG_REG (y),
8880 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8883 if (MEM_P (y) && GET_CODE (x) == SUBREG
8884 && MEM_P (SUBREG_REG (x))
8885 && rtx_equal_p (SUBREG_REG (x),
8886 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8889 /* We used to see if get_last_value of X and Y were the same but that's
8890 not correct. In one direction, we'll cause the assignment to have
8891 the wrong destination and in the case, we'll import a register into this
8892 insn that might have already have been dead. So fail if none of the
8893 above cases are true. */
8897 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8898 Return that assignment if so.
8900 We only handle the most common cases. */
8903 make_field_assignment (rtx x)
8905 rtx dest = SET_DEST (x);
8906 rtx src = SET_SRC (x);
8911 unsigned HOST_WIDE_INT len;
8913 enum machine_mode mode;
8915 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8916 a clear of a one-bit field. We will have changed it to
8917 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8920 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8921 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8922 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8923 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8925 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8928 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8932 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8933 && subreg_lowpart_p (XEXP (src, 0))
8934 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8935 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8936 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8937 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8938 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8939 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8941 assign = make_extraction (VOIDmode, dest, 0,
8942 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8945 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8949 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8951 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8952 && XEXP (XEXP (src, 0), 0) == const1_rtx
8953 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8955 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8958 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8962 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8963 SRC is an AND with all bits of that field set, then we can discard
8965 if (GET_CODE (dest) == ZERO_EXTRACT
8966 && CONST_INT_P (XEXP (dest, 1))
8967 && GET_CODE (src) == AND
8968 && CONST_INT_P (XEXP (src, 1)))
8970 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8971 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8972 unsigned HOST_WIDE_INT ze_mask;
8974 if (width >= HOST_BITS_PER_WIDE_INT)
8977 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8979 /* Complete overlap. We can remove the source AND. */
8980 if ((and_mask & ze_mask) == ze_mask)
8981 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8983 /* Partial overlap. We can reduce the source AND. */
8984 if ((and_mask & ze_mask) != and_mask)
8986 mode = GET_MODE (src);
8987 src = gen_rtx_AND (mode, XEXP (src, 0),
8988 gen_int_mode (and_mask & ze_mask, mode));
8989 return gen_rtx_SET (VOIDmode, dest, src);
8993 /* The other case we handle is assignments into a constant-position
8994 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8995 a mask that has all one bits except for a group of zero bits and
8996 OTHER is known to have zeros where C1 has ones, this is such an
8997 assignment. Compute the position and length from C1. Shift OTHER
8998 to the appropriate position, force it to the required mode, and
8999 make the extraction. Check for the AND in both operands. */
9001 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9004 rhs = expand_compound_operation (XEXP (src, 0));
9005 lhs = expand_compound_operation (XEXP (src, 1));
9007 if (GET_CODE (rhs) == AND
9008 && CONST_INT_P (XEXP (rhs, 1))
9009 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9010 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9011 else if (GET_CODE (lhs) == AND
9012 && CONST_INT_P (XEXP (lhs, 1))
9013 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9014 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9018 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9019 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9020 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9021 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9024 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9028 /* The mode to use for the source is the mode of the assignment, or of
9029 what is inside a possible STRICT_LOW_PART. */
9030 mode = (GET_CODE (assign) == STRICT_LOW_PART
9031 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9033 /* Shift OTHER right POS places and make it the source, restricting it
9034 to the proper length and mode. */
9036 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9040 src = force_to_mode (src, mode,
9041 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9042 ? ~(unsigned HOST_WIDE_INT) 0
9043 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9046 /* If SRC is masked by an AND that does not make a difference in
9047 the value being stored, strip it. */
9048 if (GET_CODE (assign) == ZERO_EXTRACT
9049 && CONST_INT_P (XEXP (assign, 1))
9050 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9051 && GET_CODE (src) == AND
9052 && CONST_INT_P (XEXP (src, 1))
9053 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
9054 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
9055 src = XEXP (src, 0);
9057 return gen_rtx_SET (VOIDmode, assign, src);
9060 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9064 apply_distributive_law (rtx x)
9066 enum rtx_code code = GET_CODE (x);
9067 enum rtx_code inner_code;
9068 rtx lhs, rhs, other;
9071 /* Distributivity is not true for floating point as it can change the
9072 value. So we don't do it unless -funsafe-math-optimizations. */
9073 if (FLOAT_MODE_P (GET_MODE (x))
9074 && ! flag_unsafe_math_optimizations)
9077 /* The outer operation can only be one of the following: */
9078 if (code != IOR && code != AND && code != XOR
9079 && code != PLUS && code != MINUS)
9085 /* If either operand is a primitive we can't do anything, so get out
9087 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9090 lhs = expand_compound_operation (lhs);
9091 rhs = expand_compound_operation (rhs);
9092 inner_code = GET_CODE (lhs);
9093 if (inner_code != GET_CODE (rhs))
9096 /* See if the inner and outer operations distribute. */
9103 /* These all distribute except over PLUS. */
9104 if (code == PLUS || code == MINUS)
9109 if (code != PLUS && code != MINUS)
9114 /* This is also a multiply, so it distributes over everything. */
9118 /* Non-paradoxical SUBREGs distributes over all operations,
9119 provided the inner modes and byte offsets are the same, this
9120 is an extraction of a low-order part, we don't convert an fp
9121 operation to int or vice versa, this is not a vector mode,
9122 and we would not be converting a single-word operation into a
9123 multi-word operation. The latter test is not required, but
9124 it prevents generating unneeded multi-word operations. Some
9125 of the previous tests are redundant given the latter test,
9126 but are retained because they are required for correctness.
9128 We produce the result slightly differently in this case. */
9130 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9131 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9132 || ! subreg_lowpart_p (lhs)
9133 || (GET_MODE_CLASS (GET_MODE (lhs))
9134 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9135 || (GET_MODE_SIZE (GET_MODE (lhs))
9136 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9137 || VECTOR_MODE_P (GET_MODE (lhs))
9138 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9139 /* Result might need to be truncated. Don't change mode if
9140 explicit truncation is needed. */
9141 || !TRULY_NOOP_TRUNCATION
9142 (GET_MODE_BITSIZE (GET_MODE (x)),
9143 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9146 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9147 SUBREG_REG (lhs), SUBREG_REG (rhs));
9148 return gen_lowpart (GET_MODE (x), tem);
9154 /* Set LHS and RHS to the inner operands (A and B in the example
9155 above) and set OTHER to the common operand (C in the example).
9156 There is only one way to do this unless the inner operation is
9158 if (COMMUTATIVE_ARITH_P (lhs)
9159 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9160 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9161 else if (COMMUTATIVE_ARITH_P (lhs)
9162 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9163 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9164 else if (COMMUTATIVE_ARITH_P (lhs)
9165 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9166 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9167 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9168 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9172 /* Form the new inner operation, seeing if it simplifies first. */
9173 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9175 /* There is one exception to the general way of distributing:
9176 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9177 if (code == XOR && inner_code == IOR)
9180 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9183 /* We may be able to continuing distributing the result, so call
9184 ourselves recursively on the inner operation before forming the
9185 outer operation, which we return. */
9186 return simplify_gen_binary (inner_code, GET_MODE (x),
9187 apply_distributive_law (tem), other);
9190 /* See if X is of the form (* (+ A B) C), and if so convert to
9191 (+ (* A C) (* B C)) and try to simplify.
9193 Most of the time, this results in no change. However, if some of
9194 the operands are the same or inverses of each other, simplifications
9197 For example, (and (ior A B) (not B)) can occur as the result of
9198 expanding a bit field assignment. When we apply the distributive
9199 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9200 which then simplifies to (and (A (not B))).
9202 Note that no checks happen on the validity of applying the inverse
9203 distributive law. This is pointless since we can do it in the
9204 few places where this routine is called.
9206 N is the index of the term that is decomposed (the arithmetic operation,
9207 i.e. (+ A B) in the first example above). !N is the index of the term that
9208 is distributed, i.e. of C in the first example above. */
9210 distribute_and_simplify_rtx (rtx x, int n)
9212 enum machine_mode mode;
9213 enum rtx_code outer_code, inner_code;
9214 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9216 /* Distributivity is not true for floating point as it can change the
9217 value. So we don't do it unless -funsafe-math-optimizations. */
9218 if (FLOAT_MODE_P (GET_MODE (x))
9219 && ! flag_unsafe_math_optimizations)
9222 decomposed = XEXP (x, n);
9223 if (!ARITHMETIC_P (decomposed))
9226 mode = GET_MODE (x);
9227 outer_code = GET_CODE (x);
9228 distributed = XEXP (x, !n);
9230 inner_code = GET_CODE (decomposed);
9231 inner_op0 = XEXP (decomposed, 0);
9232 inner_op1 = XEXP (decomposed, 1);
9234 /* Special case (and (xor B C) (not A)), which is equivalent to
9235 (xor (ior A B) (ior A C)) */
9236 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9238 distributed = XEXP (distributed, 0);
9244 /* Distribute the second term. */
9245 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9246 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9250 /* Distribute the first term. */
9251 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9252 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9255 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9257 if (GET_CODE (tmp) != outer_code
9258 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9259 < rtx_cost (x, SET, optimize_this_for_speed_p))
9265 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9266 in MODE. Return an equivalent form, if different from (and VAROP
9267 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9270 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9271 unsigned HOST_WIDE_INT constop)
9273 unsigned HOST_WIDE_INT nonzero;
9274 unsigned HOST_WIDE_INT orig_constop;
9279 orig_constop = constop;
9280 if (GET_CODE (varop) == CLOBBER)
9283 /* Simplify VAROP knowing that we will be only looking at some of the
9286 Note by passing in CONSTOP, we guarantee that the bits not set in
9287 CONSTOP are not significant and will never be examined. We must
9288 ensure that is the case by explicitly masking out those bits
9289 before returning. */
9290 varop = force_to_mode (varop, mode, constop, 0);
9292 /* If VAROP is a CLOBBER, we will fail so return it. */
9293 if (GET_CODE (varop) == CLOBBER)
9296 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9297 to VAROP and return the new constant. */
9298 if (CONST_INT_P (varop))
9299 return gen_int_mode (INTVAL (varop) & constop, mode);
9301 /* See what bits may be nonzero in VAROP. Unlike the general case of
9302 a call to nonzero_bits, here we don't care about bits outside
9305 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9307 /* Turn off all bits in the constant that are known to already be zero.
9308 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9309 which is tested below. */
9313 /* If we don't have any bits left, return zero. */
9317 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9318 a power of two, we can replace this with an ASHIFT. */
9319 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9320 && (i = exact_log2 (constop)) >= 0)
9321 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9323 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9324 or XOR, then try to apply the distributive law. This may eliminate
9325 operations if either branch can be simplified because of the AND.
9326 It may also make some cases more complex, but those cases probably
9327 won't match a pattern either with or without this. */
9329 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9333 apply_distributive_law
9334 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9335 simplify_and_const_int (NULL_RTX,
9339 simplify_and_const_int (NULL_RTX,
9344 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9345 the AND and see if one of the operands simplifies to zero. If so, we
9346 may eliminate it. */
9348 if (GET_CODE (varop) == PLUS
9349 && exact_log2 (constop + 1) >= 0)
9353 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9354 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9355 if (o0 == const0_rtx)
9357 if (o1 == const0_rtx)
9361 /* Make a SUBREG if necessary. If we can't make it, fail. */
9362 varop = gen_lowpart (mode, varop);
9363 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9366 /* If we are only masking insignificant bits, return VAROP. */
9367 if (constop == nonzero)
9370 if (varop == orig_varop && constop == orig_constop)
9373 /* Otherwise, return an AND. */
9374 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9378 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9381 Return an equivalent form, if different from X. Otherwise, return X. If
9382 X is zero, we are to always construct the equivalent form. */
9385 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9386 unsigned HOST_WIDE_INT constop)
9388 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9393 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9394 gen_int_mode (constop, mode));
9395 if (GET_MODE (x) != mode)
9396 x = gen_lowpart (mode, x);
9400 /* Given a REG, X, compute which bits in X can be nonzero.
9401 We don't care about bits outside of those defined in MODE.
9403 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9404 a shift, AND, or zero_extract, we can do better. */
9407 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9408 const_rtx known_x ATTRIBUTE_UNUSED,
9409 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9410 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9411 unsigned HOST_WIDE_INT *nonzero)
9416 /* If X is a register whose nonzero bits value is current, use it.
9417 Otherwise, if X is a register whose value we can find, use that
9418 value. Otherwise, use the previously-computed global nonzero bits
9419 for this register. */
9421 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9422 if (rsp->last_set_value != 0
9423 && (rsp->last_set_mode == mode
9424 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9425 && GET_MODE_CLASS (mode) == MODE_INT))
9426 && ((rsp->last_set_label >= label_tick_ebb_start
9427 && rsp->last_set_label < label_tick)
9428 || (rsp->last_set_label == label_tick
9429 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9430 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9431 && REG_N_SETS (REGNO (x)) == 1
9433 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9435 *nonzero &= rsp->last_set_nonzero_bits;
9439 tem = get_last_value (x);
9443 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9444 /* If X is narrower than MODE and TEM is a non-negative
9445 constant that would appear negative in the mode of X,
9446 sign-extend it for use in reg_nonzero_bits because some
9447 machines (maybe most) will actually do the sign-extension
9448 and this is the conservative approach.
9450 ??? For 2.5, try to tighten up the MD files in this regard
9451 instead of this kludge. */
9453 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9454 && CONST_INT_P (tem)
9456 && 0 != (INTVAL (tem)
9457 & ((HOST_WIDE_INT) 1
9458 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9459 tem = GEN_INT (INTVAL (tem)
9460 | ((HOST_WIDE_INT) (-1)
9461 << GET_MODE_BITSIZE (GET_MODE (x))));
9465 else if (nonzero_sign_valid && rsp->nonzero_bits)
9467 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9469 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9470 /* We don't know anything about the upper bits. */
9471 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9478 /* Return the number of bits at the high-order end of X that are known to
9479 be equal to the sign bit. X will be used in mode MODE; if MODE is
9480 VOIDmode, X will be used in its own mode. The returned value will always
9481 be between 1 and the number of bits in MODE. */
9484 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9485 const_rtx known_x ATTRIBUTE_UNUSED,
9486 enum machine_mode known_mode
9488 unsigned int known_ret ATTRIBUTE_UNUSED,
9489 unsigned int *result)
9494 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9495 if (rsp->last_set_value != 0
9496 && rsp->last_set_mode == mode
9497 && ((rsp->last_set_label >= label_tick_ebb_start
9498 && rsp->last_set_label < label_tick)
9499 || (rsp->last_set_label == label_tick
9500 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9501 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9502 && REG_N_SETS (REGNO (x)) == 1
9504 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9506 *result = rsp->last_set_sign_bit_copies;
9510 tem = get_last_value (x);
9514 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9515 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9516 *result = rsp->sign_bit_copies;
9521 /* Return the number of "extended" bits there are in X, when interpreted
9522 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9523 unsigned quantities, this is the number of high-order zero bits.
9524 For signed quantities, this is the number of copies of the sign bit
9525 minus 1. In both case, this function returns the number of "spare"
9526 bits. For example, if two quantities for which this function returns
9527 at least 1 are added, the addition is known not to overflow.
9529 This function will always return 0 unless called during combine, which
9530 implies that it must be called from a define_split. */
9533 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9535 if (nonzero_sign_valid == 0)
9539 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9540 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9541 - floor_log2 (nonzero_bits (x, mode)))
9543 : num_sign_bit_copies (x, mode) - 1);
9546 /* This function is called from `simplify_shift_const' to merge two
9547 outer operations. Specifically, we have already found that we need
9548 to perform operation *POP0 with constant *PCONST0 at the outermost
9549 position. We would now like to also perform OP1 with constant CONST1
9550 (with *POP0 being done last).
9552 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9553 the resulting operation. *PCOMP_P is set to 1 if we would need to
9554 complement the innermost operand, otherwise it is unchanged.
9556 MODE is the mode in which the operation will be done. No bits outside
9557 the width of this mode matter. It is assumed that the width of this mode
9558 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9560 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9561 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9562 result is simply *PCONST0.
9564 If the resulting operation cannot be expressed as one operation, we
9565 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9568 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9570 enum rtx_code op0 = *pop0;
9571 HOST_WIDE_INT const0 = *pconst0;
9573 const0 &= GET_MODE_MASK (mode);
9574 const1 &= GET_MODE_MASK (mode);
9576 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9580 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9583 if (op1 == UNKNOWN || op0 == SET)
9586 else if (op0 == UNKNOWN)
9587 op0 = op1, const0 = const1;
9589 else if (op0 == op1)
9613 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9614 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9617 /* If the two constants aren't the same, we can't do anything. The
9618 remaining six cases can all be done. */
9619 else if (const0 != const1)
9627 /* (a & b) | b == b */
9629 else /* op1 == XOR */
9630 /* (a ^ b) | b == a | b */
9636 /* (a & b) ^ b == (~a) & b */
9637 op0 = AND, *pcomp_p = 1;
9638 else /* op1 == IOR */
9639 /* (a | b) ^ b == a & ~b */
9640 op0 = AND, const0 = ~const0;
9645 /* (a | b) & b == b */
9647 else /* op1 == XOR */
9648 /* (a ^ b) & b) == (~a) & b */
9655 /* Check for NO-OP cases. */
9656 const0 &= GET_MODE_MASK (mode);
9658 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9660 else if (const0 == 0 && op0 == AND)
9662 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9668 /* ??? Slightly redundant with the above mask, but not entirely.
9669 Moving this above means we'd have to sign-extend the mode mask
9670 for the final test. */
9671 if (op0 != UNKNOWN && op0 != NEG)
9672 *pconst0 = trunc_int_for_mode (const0, mode);
9677 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9678 the shift in. The original shift operation CODE is performed on OP in
9679 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9680 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9681 result of the shift is subject to operation OUTER_CODE with operand
9684 static enum machine_mode
9685 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9686 enum machine_mode orig_mode, enum machine_mode mode,
9687 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9689 if (orig_mode == mode)
9691 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9693 /* In general we can't perform in wider mode for right shift and rotate. */
9697 /* We can still widen if the bits brought in from the left are identical
9698 to the sign bit of ORIG_MODE. */
9699 if (num_sign_bit_copies (op, mode)
9700 > (unsigned) (GET_MODE_BITSIZE (mode)
9701 - GET_MODE_BITSIZE (orig_mode)))
9706 /* Similarly here but with zero bits. */
9707 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9708 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9711 /* We can also widen if the bits brought in will be masked off. This
9712 operation is performed in ORIG_MODE. */
9713 if (outer_code == AND)
9715 int care_bits = low_bitmask_len (orig_mode, outer_const);
9718 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9734 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9735 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9736 simplify it. Otherwise, return a simplified value.
9738 The shift is normally computed in the widest mode we find in VAROP, as
9739 long as it isn't a different number of words than RESULT_MODE. Exceptions
9740 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9743 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9744 rtx varop, int orig_count)
9746 enum rtx_code orig_code = code;
9747 rtx orig_varop = varop;
9749 enum machine_mode mode = result_mode;
9750 enum machine_mode shift_mode, tmode;
9751 unsigned int mode_words
9752 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9753 /* We form (outer_op (code varop count) (outer_const)). */
9754 enum rtx_code outer_op = UNKNOWN;
9755 HOST_WIDE_INT outer_const = 0;
9756 int complement_p = 0;
9759 /* Make sure and truncate the "natural" shift on the way in. We don't
9760 want to do this inside the loop as it makes it more difficult to
9762 if (SHIFT_COUNT_TRUNCATED)
9763 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9765 /* If we were given an invalid count, don't do anything except exactly
9766 what was requested. */
9768 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9773 /* Unless one of the branches of the `if' in this loop does a `continue',
9774 we will `break' the loop after the `if'. */
9778 /* If we have an operand of (clobber (const_int 0)), fail. */
9779 if (GET_CODE (varop) == CLOBBER)
9782 /* Convert ROTATERT to ROTATE. */
9783 if (code == ROTATERT)
9785 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9787 if (VECTOR_MODE_P (result_mode))
9788 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9790 count = bitsize - count;
9793 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9794 mode, outer_op, outer_const);
9796 /* Handle cases where the count is greater than the size of the mode
9797 minus 1. For ASHIFT, use the size minus one as the count (this can
9798 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9799 take the count modulo the size. For other shifts, the result is
9802 Since these shifts are being produced by the compiler by combining
9803 multiple operations, each of which are defined, we know what the
9804 result is supposed to be. */
9806 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9808 if (code == ASHIFTRT)
9809 count = GET_MODE_BITSIZE (shift_mode) - 1;
9810 else if (code == ROTATE || code == ROTATERT)
9811 count %= GET_MODE_BITSIZE (shift_mode);
9814 /* We can't simply return zero because there may be an
9822 /* If we discovered we had to complement VAROP, leave. Making a NOT
9823 here would cause an infinite loop. */
9827 /* An arithmetic right shift of a quantity known to be -1 or 0
9829 if (code == ASHIFTRT
9830 && (num_sign_bit_copies (varop, shift_mode)
9831 == GET_MODE_BITSIZE (shift_mode)))
9837 /* If we are doing an arithmetic right shift and discarding all but
9838 the sign bit copies, this is equivalent to doing a shift by the
9839 bitsize minus one. Convert it into that shift because it will often
9840 allow other simplifications. */
9842 if (code == ASHIFTRT
9843 && (count + num_sign_bit_copies (varop, shift_mode)
9844 >= GET_MODE_BITSIZE (shift_mode)))
9845 count = GET_MODE_BITSIZE (shift_mode) - 1;
9847 /* We simplify the tests below and elsewhere by converting
9848 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9849 `make_compound_operation' will convert it to an ASHIFTRT for
9850 those machines (such as VAX) that don't have an LSHIFTRT. */
9851 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9853 && ((nonzero_bits (varop, shift_mode)
9854 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9858 if (((code == LSHIFTRT
9859 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9860 && !(nonzero_bits (varop, shift_mode) >> count))
9862 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9863 && !((nonzero_bits (varop, shift_mode) << count)
9864 & GET_MODE_MASK (shift_mode))))
9865 && !side_effects_p (varop))
9868 switch (GET_CODE (varop))
9874 new_rtx = expand_compound_operation (varop);
9875 if (new_rtx != varop)
9883 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9884 minus the width of a smaller mode, we can do this with a
9885 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9886 if ((code == ASHIFTRT || code == LSHIFTRT)
9887 && ! mode_dependent_address_p (XEXP (varop, 0))
9888 && ! MEM_VOLATILE_P (varop)
9889 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9890 MODE_INT, 1)) != BLKmode)
9892 new_rtx = adjust_address_nv (varop, tmode,
9893 BYTES_BIG_ENDIAN ? 0
9894 : count / BITS_PER_UNIT);
9896 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9897 : ZERO_EXTEND, mode, new_rtx);
9904 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9905 the same number of words as what we've seen so far. Then store
9906 the widest mode in MODE. */
9907 if (subreg_lowpart_p (varop)
9908 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9909 > GET_MODE_SIZE (GET_MODE (varop)))
9910 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9911 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9913 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9914 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9916 varop = SUBREG_REG (varop);
9917 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9918 mode = GET_MODE (varop);
9924 /* Some machines use MULT instead of ASHIFT because MULT
9925 is cheaper. But it is still better on those machines to
9926 merge two shifts into one. */
9927 if (CONST_INT_P (XEXP (varop, 1))
9928 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9931 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9933 GEN_INT (exact_log2 (
9934 INTVAL (XEXP (varop, 1)))));
9940 /* Similar, for when divides are cheaper. */
9941 if (CONST_INT_P (XEXP (varop, 1))
9942 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9945 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9947 GEN_INT (exact_log2 (
9948 INTVAL (XEXP (varop, 1)))));
9954 /* If we are extracting just the sign bit of an arithmetic
9955 right shift, that shift is not needed. However, the sign
9956 bit of a wider mode may be different from what would be
9957 interpreted as the sign bit in a narrower mode, so, if
9958 the result is narrower, don't discard the shift. */
9959 if (code == LSHIFTRT
9960 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9961 && (GET_MODE_BITSIZE (result_mode)
9962 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9964 varop = XEXP (varop, 0);
9968 /* ... fall through ... */
9973 /* Here we have two nested shifts. The result is usually the
9974 AND of a new shift with a mask. We compute the result below. */
9975 if (CONST_INT_P (XEXP (varop, 1))
9976 && INTVAL (XEXP (varop, 1)) >= 0
9977 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9978 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9979 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9980 && !VECTOR_MODE_P (result_mode))
9982 enum rtx_code first_code = GET_CODE (varop);
9983 unsigned int first_count = INTVAL (XEXP (varop, 1));
9984 unsigned HOST_WIDE_INT mask;
9987 /* We have one common special case. We can't do any merging if
9988 the inner code is an ASHIFTRT of a smaller mode. However, if
9989 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9990 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9991 we can convert it to
9992 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9993 This simplifies certain SIGN_EXTEND operations. */
9994 if (code == ASHIFT && first_code == ASHIFTRT
9995 && count == (GET_MODE_BITSIZE (result_mode)
9996 - GET_MODE_BITSIZE (GET_MODE (varop))))
9998 /* C3 has the low-order C1 bits zero. */
10000 mask = (GET_MODE_MASK (mode)
10001 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
10003 varop = simplify_and_const_int (NULL_RTX, result_mode,
10004 XEXP (varop, 0), mask);
10005 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10007 count = first_count;
10012 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10013 than C1 high-order bits equal to the sign bit, we can convert
10014 this to either an ASHIFT or an ASHIFTRT depending on the
10017 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10019 if (code == ASHIFTRT && first_code == ASHIFT
10020 && GET_MODE (varop) == shift_mode
10021 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10024 varop = XEXP (varop, 0);
10025 count -= first_count;
10035 /* There are some cases we can't do. If CODE is ASHIFTRT,
10036 we can only do this if FIRST_CODE is also ASHIFTRT.
10038 We can't do the case when CODE is ROTATE and FIRST_CODE is
10041 If the mode of this shift is not the mode of the outer shift,
10042 we can't do this if either shift is a right shift or ROTATE.
10044 Finally, we can't do any of these if the mode is too wide
10045 unless the codes are the same.
10047 Handle the case where the shift codes are the same
10050 if (code == first_code)
10052 if (GET_MODE (varop) != result_mode
10053 && (code == ASHIFTRT || code == LSHIFTRT
10054 || code == ROTATE))
10057 count += first_count;
10058 varop = XEXP (varop, 0);
10062 if (code == ASHIFTRT
10063 || (code == ROTATE && first_code == ASHIFTRT)
10064 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10065 || (GET_MODE (varop) != result_mode
10066 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10067 || first_code == ROTATE
10068 || code == ROTATE)))
10071 /* To compute the mask to apply after the shift, shift the
10072 nonzero bits of the inner shift the same way the
10073 outer shift will. */
10075 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10078 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10081 /* Give up if we can't compute an outer operation to use. */
10083 || !CONST_INT_P (mask_rtx)
10084 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10086 result_mode, &complement_p))
10089 /* If the shifts are in the same direction, we add the
10090 counts. Otherwise, we subtract them. */
10091 if ((code == ASHIFTRT || code == LSHIFTRT)
10092 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10093 count += first_count;
10095 count -= first_count;
10097 /* If COUNT is positive, the new shift is usually CODE,
10098 except for the two exceptions below, in which case it is
10099 FIRST_CODE. If the count is negative, FIRST_CODE should
10102 && ((first_code == ROTATE && code == ASHIFT)
10103 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10105 else if (count < 0)
10106 code = first_code, count = -count;
10108 varop = XEXP (varop, 0);
10112 /* If we have (A << B << C) for any shift, we can convert this to
10113 (A << C << B). This wins if A is a constant. Only try this if
10114 B is not a constant. */
10116 else if (GET_CODE (varop) == code
10117 && CONST_INT_P (XEXP (varop, 0))
10118 && !CONST_INT_P (XEXP (varop, 1)))
10120 rtx new_rtx = simplify_const_binary_operation (code, mode,
10123 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10130 if (VECTOR_MODE_P (mode))
10133 /* Make this fit the case below. */
10134 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10135 GEN_INT (GET_MODE_MASK (mode)));
10141 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10142 with C the size of VAROP - 1 and the shift is logical if
10143 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10144 we have an (le X 0) operation. If we have an arithmetic shift
10145 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10146 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10148 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10149 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10150 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10151 && (code == LSHIFTRT || code == ASHIFTRT)
10152 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10153 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10156 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10159 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10160 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10165 /* If we have (shift (logical)), move the logical to the outside
10166 to allow it to possibly combine with another logical and the
10167 shift to combine with another shift. This also canonicalizes to
10168 what a ZERO_EXTRACT looks like. Also, some machines have
10169 (and (shift)) insns. */
10171 if (CONST_INT_P (XEXP (varop, 1))
10172 /* We can't do this if we have (ashiftrt (xor)) and the
10173 constant has its sign bit set in shift_mode. */
10174 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10175 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10177 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10179 GEN_INT (count))) != 0
10180 && CONST_INT_P (new_rtx)
10181 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10182 INTVAL (new_rtx), result_mode, &complement_p))
10184 varop = XEXP (varop, 0);
10188 /* If we can't do that, try to simplify the shift in each arm of the
10189 logical expression, make a new logical expression, and apply
10190 the inverse distributive law. This also can't be done
10191 for some (ashiftrt (xor)). */
10192 if (CONST_INT_P (XEXP (varop, 1))
10193 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10194 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10197 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10198 XEXP (varop, 0), count);
10199 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10200 XEXP (varop, 1), count);
10202 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10204 varop = apply_distributive_law (varop);
10212 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10213 says that the sign bit can be tested, FOO has mode MODE, C is
10214 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10215 that may be nonzero. */
10216 if (code == LSHIFTRT
10217 && XEXP (varop, 1) == const0_rtx
10218 && GET_MODE (XEXP (varop, 0)) == result_mode
10219 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10220 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10221 && STORE_FLAG_VALUE == -1
10222 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10223 && merge_outer_ops (&outer_op, &outer_const, XOR,
10224 (HOST_WIDE_INT) 1, result_mode,
10227 varop = XEXP (varop, 0);
10234 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10235 than the number of bits in the mode is equivalent to A. */
10236 if (code == LSHIFTRT
10237 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10238 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10240 varop = XEXP (varop, 0);
10245 /* NEG commutes with ASHIFT since it is multiplication. Move the
10246 NEG outside to allow shifts to combine. */
10248 && merge_outer_ops (&outer_op, &outer_const, NEG,
10249 (HOST_WIDE_INT) 0, result_mode,
10252 varop = XEXP (varop, 0);
10258 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10259 is one less than the number of bits in the mode is
10260 equivalent to (xor A 1). */
10261 if (code == LSHIFTRT
10262 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10263 && XEXP (varop, 1) == constm1_rtx
10264 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10265 && merge_outer_ops (&outer_op, &outer_const, XOR,
10266 (HOST_WIDE_INT) 1, result_mode,
10270 varop = XEXP (varop, 0);
10274 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10275 that might be nonzero in BAR are those being shifted out and those
10276 bits are known zero in FOO, we can replace the PLUS with FOO.
10277 Similarly in the other operand order. This code occurs when
10278 we are computing the size of a variable-size array. */
10280 if ((code == ASHIFTRT || code == LSHIFTRT)
10281 && count < HOST_BITS_PER_WIDE_INT
10282 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10283 && (nonzero_bits (XEXP (varop, 1), result_mode)
10284 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10286 varop = XEXP (varop, 0);
10289 else if ((code == ASHIFTRT || code == LSHIFTRT)
10290 && count < HOST_BITS_PER_WIDE_INT
10291 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10292 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10294 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10295 & nonzero_bits (XEXP (varop, 1),
10298 varop = XEXP (varop, 1);
10302 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10304 && CONST_INT_P (XEXP (varop, 1))
10305 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10307 GEN_INT (count))) != 0
10308 && CONST_INT_P (new_rtx)
10309 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10310 INTVAL (new_rtx), result_mode, &complement_p))
10312 varop = XEXP (varop, 0);
10316 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10317 signbit', and attempt to change the PLUS to an XOR and move it to
10318 the outer operation as is done above in the AND/IOR/XOR case
10319 leg for shift(logical). See details in logical handling above
10320 for reasoning in doing so. */
10321 if (code == LSHIFTRT
10322 && CONST_INT_P (XEXP (varop, 1))
10323 && mode_signbit_p (result_mode, XEXP (varop, 1))
10324 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10326 GEN_INT (count))) != 0
10327 && CONST_INT_P (new_rtx)
10328 && merge_outer_ops (&outer_op, &outer_const, XOR,
10329 INTVAL (new_rtx), result_mode, &complement_p))
10331 varop = XEXP (varop, 0);
10338 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10339 with C the size of VAROP - 1 and the shift is logical if
10340 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10341 we have a (gt X 0) operation. If the shift is arithmetic with
10342 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10343 we have a (neg (gt X 0)) operation. */
10345 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10346 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10347 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10348 && (code == LSHIFTRT || code == ASHIFTRT)
10349 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10350 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10351 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10354 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10357 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10358 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10365 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10366 if the truncate does not affect the value. */
10367 if (code == LSHIFTRT
10368 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10369 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10370 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10371 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10372 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10374 rtx varop_inner = XEXP (varop, 0);
10377 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10378 XEXP (varop_inner, 0),
10380 (count + INTVAL (XEXP (varop_inner, 1))));
10381 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10394 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10395 outer_op, outer_const);
10397 /* We have now finished analyzing the shift. The result should be
10398 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10399 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10400 to the result of the shift. OUTER_CONST is the relevant constant,
10401 but we must turn off all bits turned off in the shift. */
10403 if (outer_op == UNKNOWN
10404 && orig_code == code && orig_count == count
10405 && varop == orig_varop
10406 && shift_mode == GET_MODE (varop))
10409 /* Make a SUBREG if necessary. If we can't make it, fail. */
10410 varop = gen_lowpart (shift_mode, varop);
10411 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10414 /* If we have an outer operation and we just made a shift, it is
10415 possible that we could have simplified the shift were it not
10416 for the outer operation. So try to do the simplification
10419 if (outer_op != UNKNOWN)
10420 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10425 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10427 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10428 turn off all the bits that the shift would have turned off. */
10429 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10430 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10431 GET_MODE_MASK (result_mode) >> orig_count);
10433 /* Do the remainder of the processing in RESULT_MODE. */
10434 x = gen_lowpart_or_truncate (result_mode, x);
10436 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10439 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10441 if (outer_op != UNKNOWN)
10443 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10444 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10445 outer_const = trunc_int_for_mode (outer_const, result_mode);
10447 if (outer_op == AND)
10448 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10449 else if (outer_op == SET)
10451 /* This means that we have determined that the result is
10452 equivalent to a constant. This should be rare. */
10453 if (!side_effects_p (x))
10454 x = GEN_INT (outer_const);
10456 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10457 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10459 x = simplify_gen_binary (outer_op, result_mode, x,
10460 GEN_INT (outer_const));
10466 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10467 The result of the shift is RESULT_MODE. If we cannot simplify it,
10468 return X or, if it is NULL, synthesize the expression with
10469 simplify_gen_binary. Otherwise, return a simplified value.
10471 The shift is normally computed in the widest mode we find in VAROP, as
10472 long as it isn't a different number of words than RESULT_MODE. Exceptions
10473 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10476 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10477 rtx varop, int count)
10479 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10484 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10485 if (GET_MODE (x) != result_mode)
10486 x = gen_lowpart (result_mode, x);
10491 /* Like recog, but we receive the address of a pointer to a new pattern.
10492 We try to match the rtx that the pointer points to.
10493 If that fails, we may try to modify or replace the pattern,
10494 storing the replacement into the same pointer object.
10496 Modifications include deletion or addition of CLOBBERs.
10498 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10499 the CLOBBERs are placed.
10501 The value is the final insn code from the pattern ultimately matched,
10505 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10507 rtx pat = *pnewpat;
10508 int insn_code_number;
10509 int num_clobbers_to_add = 0;
10512 rtx old_notes, old_pat;
10514 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10515 we use to indicate that something didn't match. If we find such a
10516 thing, force rejection. */
10517 if (GET_CODE (pat) == PARALLEL)
10518 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10519 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10520 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10523 old_pat = PATTERN (insn);
10524 old_notes = REG_NOTES (insn);
10525 PATTERN (insn) = pat;
10526 REG_NOTES (insn) = 0;
10528 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10529 if (dump_file && (dump_flags & TDF_DETAILS))
10531 if (insn_code_number < 0)
10532 fputs ("Failed to match this instruction:\n", dump_file);
10534 fputs ("Successfully matched this instruction:\n", dump_file);
10535 print_rtl_single (dump_file, pat);
10538 /* If it isn't, there is the possibility that we previously had an insn
10539 that clobbered some register as a side effect, but the combined
10540 insn doesn't need to do that. So try once more without the clobbers
10541 unless this represents an ASM insn. */
10543 if (insn_code_number < 0 && ! check_asm_operands (pat)
10544 && GET_CODE (pat) == PARALLEL)
10548 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10549 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10552 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10556 SUBST_INT (XVECLEN (pat, 0), pos);
10559 pat = XVECEXP (pat, 0, 0);
10561 PATTERN (insn) = pat;
10562 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10563 if (dump_file && (dump_flags & TDF_DETAILS))
10565 if (insn_code_number < 0)
10566 fputs ("Failed to match this instruction:\n", dump_file);
10568 fputs ("Successfully matched this instruction:\n", dump_file);
10569 print_rtl_single (dump_file, pat);
10572 PATTERN (insn) = old_pat;
10573 REG_NOTES (insn) = old_notes;
10575 /* Recognize all noop sets, these will be killed by followup pass. */
10576 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10577 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10579 /* If we had any clobbers to add, make a new pattern than contains
10580 them. Then check to make sure that all of them are dead. */
10581 if (num_clobbers_to_add)
10583 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10584 rtvec_alloc (GET_CODE (pat) == PARALLEL
10585 ? (XVECLEN (pat, 0)
10586 + num_clobbers_to_add)
10587 : num_clobbers_to_add + 1));
10589 if (GET_CODE (pat) == PARALLEL)
10590 for (i = 0; i < XVECLEN (pat, 0); i++)
10591 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10593 XVECEXP (newpat, 0, 0) = pat;
10595 add_clobbers (newpat, insn_code_number);
10597 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10598 i < XVECLEN (newpat, 0); i++)
10600 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10601 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10603 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10605 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10606 notes = alloc_reg_note (REG_UNUSED,
10607 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10616 return insn_code_number;
10619 /* Like gen_lowpart_general but for use by combine. In combine it
10620 is not possible to create any new pseudoregs. However, it is
10621 safe to create invalid memory addresses, because combine will
10622 try to recognize them and all they will do is make the combine
10625 If for some reason this cannot do its job, an rtx
10626 (clobber (const_int 0)) is returned.
10627 An insn containing that will not be recognized. */
10630 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10632 enum machine_mode imode = GET_MODE (x);
10633 unsigned int osize = GET_MODE_SIZE (omode);
10634 unsigned int isize = GET_MODE_SIZE (imode);
10637 if (omode == imode)
10640 /* Return identity if this is a CONST or symbolic reference. */
10642 && (GET_CODE (x) == CONST
10643 || GET_CODE (x) == SYMBOL_REF
10644 || GET_CODE (x) == LABEL_REF))
10647 /* We can only support MODE being wider than a word if X is a
10648 constant integer or has a mode the same size. */
10649 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10650 && ! ((imode == VOIDmode
10651 && (CONST_INT_P (x)
10652 || GET_CODE (x) == CONST_DOUBLE))
10653 || isize == osize))
10656 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10657 won't know what to do. So we will strip off the SUBREG here and
10658 process normally. */
10659 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10661 x = SUBREG_REG (x);
10663 /* For use in case we fall down into the address adjustments
10664 further below, we need to adjust the known mode and size of
10665 x; imode and isize, since we just adjusted x. */
10666 imode = GET_MODE (x);
10668 if (imode == omode)
10671 isize = GET_MODE_SIZE (imode);
10674 result = gen_lowpart_common (omode, x);
10683 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10685 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10688 /* If we want to refer to something bigger than the original memref,
10689 generate a paradoxical subreg instead. That will force a reload
10690 of the original memref X. */
10692 return gen_rtx_SUBREG (omode, x, 0);
10694 if (WORDS_BIG_ENDIAN)
10695 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10697 /* Adjust the address so that the address-after-the-data is
10699 if (BYTES_BIG_ENDIAN)
10700 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10702 return adjust_address_nv (x, omode, offset);
10705 /* If X is a comparison operator, rewrite it in a new mode. This
10706 probably won't match, but may allow further simplifications. */
10707 else if (COMPARISON_P (x))
10708 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10710 /* If we couldn't simplify X any other way, just enclose it in a
10711 SUBREG. Normally, this SUBREG won't match, but some patterns may
10712 include an explicit SUBREG or we may simplify it further in combine. */
10718 offset = subreg_lowpart_offset (omode, imode);
10719 if (imode == VOIDmode)
10721 imode = int_mode_for_mode (omode);
10722 x = gen_lowpart_common (imode, x);
10726 res = simplify_gen_subreg (omode, x, imode, offset);
10732 return gen_rtx_CLOBBER (omode, const0_rtx);
10735 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10736 comparison code that will be tested.
10738 The result is a possibly different comparison code to use. *POP0 and
10739 *POP1 may be updated.
10741 It is possible that we might detect that a comparison is either always
10742 true or always false. However, we do not perform general constant
10743 folding in combine, so this knowledge isn't useful. Such tautologies
10744 should have been detected earlier. Hence we ignore all such cases. */
10746 static enum rtx_code
10747 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10753 enum machine_mode mode, tmode;
10755 /* Try a few ways of applying the same transformation to both operands. */
10758 #ifndef WORD_REGISTER_OPERATIONS
10759 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10760 so check specially. */
10761 if (code != GTU && code != GEU && code != LTU && code != LEU
10762 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10763 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10764 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10765 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10766 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10767 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10768 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10769 && CONST_INT_P (XEXP (op0, 1))
10770 && XEXP (op0, 1) == XEXP (op1, 1)
10771 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10772 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10773 && (INTVAL (XEXP (op0, 1))
10774 == (GET_MODE_BITSIZE (GET_MODE (op0))
10775 - (GET_MODE_BITSIZE
10776 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10778 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10779 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10783 /* If both operands are the same constant shift, see if we can ignore the
10784 shift. We can if the shift is a rotate or if the bits shifted out of
10785 this shift are known to be zero for both inputs and if the type of
10786 comparison is compatible with the shift. */
10787 if (GET_CODE (op0) == GET_CODE (op1)
10788 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10789 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10790 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10791 && (code != GT && code != LT && code != GE && code != LE))
10792 || (GET_CODE (op0) == ASHIFTRT
10793 && (code != GTU && code != LTU
10794 && code != GEU && code != LEU)))
10795 && CONST_INT_P (XEXP (op0, 1))
10796 && INTVAL (XEXP (op0, 1)) >= 0
10797 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10798 && XEXP (op0, 1) == XEXP (op1, 1))
10800 enum machine_mode mode = GET_MODE (op0);
10801 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10802 int shift_count = INTVAL (XEXP (op0, 1));
10804 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10805 mask &= (mask >> shift_count) << shift_count;
10806 else if (GET_CODE (op0) == ASHIFT)
10807 mask = (mask & (mask << shift_count)) >> shift_count;
10809 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10810 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10811 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10816 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10817 SUBREGs are of the same mode, and, in both cases, the AND would
10818 be redundant if the comparison was done in the narrower mode,
10819 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10820 and the operand's possibly nonzero bits are 0xffffff01; in that case
10821 if we only care about QImode, we don't need the AND). This case
10822 occurs if the output mode of an scc insn is not SImode and
10823 STORE_FLAG_VALUE == 1 (e.g., the 386).
10825 Similarly, check for a case where the AND's are ZERO_EXTEND
10826 operations from some narrower mode even though a SUBREG is not
10829 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10830 && CONST_INT_P (XEXP (op0, 1))
10831 && CONST_INT_P (XEXP (op1, 1)))
10833 rtx inner_op0 = XEXP (op0, 0);
10834 rtx inner_op1 = XEXP (op1, 0);
10835 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10836 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10839 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10840 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10841 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10842 && (GET_MODE (SUBREG_REG (inner_op0))
10843 == GET_MODE (SUBREG_REG (inner_op1)))
10844 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10845 <= HOST_BITS_PER_WIDE_INT)
10846 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10847 GET_MODE (SUBREG_REG (inner_op0)))))
10848 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10849 GET_MODE (SUBREG_REG (inner_op1))))))
10851 op0 = SUBREG_REG (inner_op0);
10852 op1 = SUBREG_REG (inner_op1);
10854 /* The resulting comparison is always unsigned since we masked
10855 off the original sign bit. */
10856 code = unsigned_condition (code);
10862 for (tmode = GET_CLASS_NARROWEST_MODE
10863 (GET_MODE_CLASS (GET_MODE (op0)));
10864 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10865 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10867 op0 = gen_lowpart (tmode, inner_op0);
10868 op1 = gen_lowpart (tmode, inner_op1);
10869 code = unsigned_condition (code);
10878 /* If both operands are NOT, we can strip off the outer operation
10879 and adjust the comparison code for swapped operands; similarly for
10880 NEG, except that this must be an equality comparison. */
10881 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10882 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10883 && (code == EQ || code == NE)))
10884 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10890 /* If the first operand is a constant, swap the operands and adjust the
10891 comparison code appropriately, but don't do this if the second operand
10892 is already a constant integer. */
10893 if (swap_commutative_operands_p (op0, op1))
10895 tem = op0, op0 = op1, op1 = tem;
10896 code = swap_condition (code);
10899 /* We now enter a loop during which we will try to simplify the comparison.
10900 For the most part, we only are concerned with comparisons with zero,
10901 but some things may really be comparisons with zero but not start
10902 out looking that way. */
10904 while (CONST_INT_P (op1))
10906 enum machine_mode mode = GET_MODE (op0);
10907 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10908 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10909 int equality_comparison_p;
10910 int sign_bit_comparison_p;
10911 int unsigned_comparison_p;
10912 HOST_WIDE_INT const_op;
10914 /* We only want to handle integral modes. This catches VOIDmode,
10915 CCmode, and the floating-point modes. An exception is that we
10916 can handle VOIDmode if OP0 is a COMPARE or a comparison
10919 if (GET_MODE_CLASS (mode) != MODE_INT
10920 && ! (mode == VOIDmode
10921 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10924 /* Get the constant we are comparing against and turn off all bits
10925 not on in our mode. */
10926 const_op = INTVAL (op1);
10927 if (mode != VOIDmode)
10928 const_op = trunc_int_for_mode (const_op, mode);
10929 op1 = GEN_INT (const_op);
10931 /* If we are comparing against a constant power of two and the value
10932 being compared can only have that single bit nonzero (e.g., it was
10933 `and'ed with that bit), we can replace this with a comparison
10936 && (code == EQ || code == NE || code == GE || code == GEU
10937 || code == LT || code == LTU)
10938 && mode_width <= HOST_BITS_PER_WIDE_INT
10939 && exact_log2 (const_op) >= 0
10940 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10942 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10943 op1 = const0_rtx, const_op = 0;
10946 /* Similarly, if we are comparing a value known to be either -1 or
10947 0 with -1, change it to the opposite comparison against zero. */
10950 && (code == EQ || code == NE || code == GT || code == LE
10951 || code == GEU || code == LTU)
10952 && num_sign_bit_copies (op0, mode) == mode_width)
10954 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10955 op1 = const0_rtx, const_op = 0;
10958 /* Do some canonicalizations based on the comparison code. We prefer
10959 comparisons against zero and then prefer equality comparisons.
10960 If we can reduce the size of a constant, we will do that too. */
10965 /* < C is equivalent to <= (C - 1) */
10969 op1 = GEN_INT (const_op);
10971 /* ... fall through to LE case below. */
10977 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10981 op1 = GEN_INT (const_op);
10985 /* If we are doing a <= 0 comparison on a value known to have
10986 a zero sign bit, we can replace this with == 0. */
10987 else if (const_op == 0
10988 && mode_width <= HOST_BITS_PER_WIDE_INT
10989 && (nonzero_bits (op0, mode)
10990 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10995 /* >= C is equivalent to > (C - 1). */
10999 op1 = GEN_INT (const_op);
11001 /* ... fall through to GT below. */
11007 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11011 op1 = GEN_INT (const_op);
11015 /* If we are doing a > 0 comparison on a value known to have
11016 a zero sign bit, we can replace this with != 0. */
11017 else if (const_op == 0
11018 && mode_width <= HOST_BITS_PER_WIDE_INT
11019 && (nonzero_bits (op0, mode)
11020 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
11025 /* < C is equivalent to <= (C - 1). */
11029 op1 = GEN_INT (const_op);
11031 /* ... fall through ... */
11034 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11035 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11036 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
11038 const_op = 0, op1 = const0_rtx;
11046 /* unsigned <= 0 is equivalent to == 0 */
11050 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11051 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11052 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
11054 const_op = 0, op1 = const0_rtx;
11060 /* >= C is equivalent to > (C - 1). */
11064 op1 = GEN_INT (const_op);
11066 /* ... fall through ... */
11069 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11070 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11071 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
11073 const_op = 0, op1 = const0_rtx;
11081 /* unsigned > 0 is equivalent to != 0 */
11085 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11086 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
11087 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
11089 const_op = 0, op1 = const0_rtx;
11098 /* Compute some predicates to simplify code below. */
11100 equality_comparison_p = (code == EQ || code == NE);
11101 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11102 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11105 /* If this is a sign bit comparison and we can do arithmetic in
11106 MODE, say that we will only be needing the sign bit of OP0. */
11107 if (sign_bit_comparison_p
11108 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11109 op0 = force_to_mode (op0, mode,
11111 << (GET_MODE_BITSIZE (mode) - 1)),
11114 /* Now try cases based on the opcode of OP0. If none of the cases
11115 does a "continue", we exit this loop immediately after the
11118 switch (GET_CODE (op0))
11121 /* If we are extracting a single bit from a variable position in
11122 a constant that has only a single bit set and are comparing it
11123 with zero, we can convert this into an equality comparison
11124 between the position and the location of the single bit. */
11125 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11126 have already reduced the shift count modulo the word size. */
11127 if (!SHIFT_COUNT_TRUNCATED
11128 && CONST_INT_P (XEXP (op0, 0))
11129 && XEXP (op0, 1) == const1_rtx
11130 && equality_comparison_p && const_op == 0
11131 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
11133 if (BITS_BIG_ENDIAN)
11135 enum machine_mode new_mode
11136 = mode_for_extraction (EP_extzv, 1);
11137 if (new_mode == MAX_MACHINE_MODE)
11138 i = BITS_PER_WORD - 1 - i;
11142 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11146 op0 = XEXP (op0, 2);
11150 /* Result is nonzero iff shift count is equal to I. */
11151 code = reverse_condition (code);
11155 /* ... fall through ... */
11158 tem = expand_compound_operation (op0);
11167 /* If testing for equality, we can take the NOT of the constant. */
11168 if (equality_comparison_p
11169 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11171 op0 = XEXP (op0, 0);
11176 /* If just looking at the sign bit, reverse the sense of the
11178 if (sign_bit_comparison_p)
11180 op0 = XEXP (op0, 0);
11181 code = (code == GE ? LT : GE);
11187 /* If testing for equality, we can take the NEG of the constant. */
11188 if (equality_comparison_p
11189 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11191 op0 = XEXP (op0, 0);
11196 /* The remaining cases only apply to comparisons with zero. */
11200 /* When X is ABS or is known positive,
11201 (neg X) is < 0 if and only if X != 0. */
11203 if (sign_bit_comparison_p
11204 && (GET_CODE (XEXP (op0, 0)) == ABS
11205 || (mode_width <= HOST_BITS_PER_WIDE_INT
11206 && (nonzero_bits (XEXP (op0, 0), mode)
11207 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
11209 op0 = XEXP (op0, 0);
11210 code = (code == LT ? NE : EQ);
11214 /* If we have NEG of something whose two high-order bits are the
11215 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11216 if (num_sign_bit_copies (op0, mode) >= 2)
11218 op0 = XEXP (op0, 0);
11219 code = swap_condition (code);
11225 /* If we are testing equality and our count is a constant, we
11226 can perform the inverse operation on our RHS. */
11227 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11228 && (tem = simplify_binary_operation (ROTATERT, mode,
11229 op1, XEXP (op0, 1))) != 0)
11231 op0 = XEXP (op0, 0);
11236 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11237 a particular bit. Convert it to an AND of a constant of that
11238 bit. This will be converted into a ZERO_EXTRACT. */
11239 if (const_op == 0 && sign_bit_comparison_p
11240 && CONST_INT_P (XEXP (op0, 1))
11241 && mode_width <= HOST_BITS_PER_WIDE_INT)
11243 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11246 - INTVAL (XEXP (op0, 1)))));
11247 code = (code == LT ? NE : EQ);
11251 /* Fall through. */
11254 /* ABS is ignorable inside an equality comparison with zero. */
11255 if (const_op == 0 && equality_comparison_p)
11257 op0 = XEXP (op0, 0);
11263 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11264 (compare FOO CONST) if CONST fits in FOO's mode and we
11265 are either testing inequality or have an unsigned
11266 comparison with ZERO_EXTEND or a signed comparison with
11267 SIGN_EXTEND. But don't do it if we don't have a compare
11268 insn of the given mode, since we'd have to revert it
11269 later on, and then we wouldn't know whether to sign- or
11271 mode = GET_MODE (XEXP (op0, 0));
11272 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11273 && ! unsigned_comparison_p
11274 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11275 && ((unsigned HOST_WIDE_INT) const_op
11276 < (((unsigned HOST_WIDE_INT) 1
11277 << (GET_MODE_BITSIZE (mode) - 1))))
11278 && have_insn_for (COMPARE, mode))
11280 op0 = XEXP (op0, 0);
11286 /* Check for the case where we are comparing A - C1 with C2, that is
11288 (subreg:MODE (plus (A) (-C1))) op (C2)
11290 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11291 comparison in the wider mode. One of the following two conditions
11292 must be true in order for this to be valid:
11294 1. The mode extension results in the same bit pattern being added
11295 on both sides and the comparison is equality or unsigned. As
11296 C2 has been truncated to fit in MODE, the pattern can only be
11299 2. The mode extension results in the sign bit being copied on
11302 The difficulty here is that we have predicates for A but not for
11303 (A - C1) so we need to check that C1 is within proper bounds so
11304 as to perturbate A as little as possible. */
11306 if (mode_width <= HOST_BITS_PER_WIDE_INT
11307 && subreg_lowpart_p (op0)
11308 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11309 && GET_CODE (SUBREG_REG (op0)) == PLUS
11310 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11312 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11313 rtx a = XEXP (SUBREG_REG (op0), 0);
11314 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11317 && (unsigned HOST_WIDE_INT) c1
11318 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11319 && (equality_comparison_p || unsigned_comparison_p)
11320 /* (A - C1) zero-extends if it is positive and sign-extends
11321 if it is negative, C2 both zero- and sign-extends. */
11322 && ((0 == (nonzero_bits (a, inner_mode)
11323 & ~GET_MODE_MASK (mode))
11325 /* (A - C1) sign-extends if it is positive and 1-extends
11326 if it is negative, C2 both sign- and 1-extends. */
11327 || (num_sign_bit_copies (a, inner_mode)
11328 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11331 || ((unsigned HOST_WIDE_INT) c1
11332 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11333 /* (A - C1) always sign-extends, like C2. */
11334 && num_sign_bit_copies (a, inner_mode)
11335 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11336 - (mode_width - 1))))
11338 op0 = SUBREG_REG (op0);
11343 /* If the inner mode is narrower and we are extracting the low part,
11344 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11345 if (subreg_lowpart_p (op0)
11346 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11347 /* Fall through */ ;
11351 /* ... fall through ... */
11354 mode = GET_MODE (XEXP (op0, 0));
11355 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11356 && (unsigned_comparison_p || equality_comparison_p)
11357 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11358 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11359 && have_insn_for (COMPARE, mode))
11361 op0 = XEXP (op0, 0);
11367 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11368 this for equality comparisons due to pathological cases involving
11370 if (equality_comparison_p
11371 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11372 op1, XEXP (op0, 1))))
11374 op0 = XEXP (op0, 0);
11379 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11380 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11381 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11383 op0 = XEXP (XEXP (op0, 0), 0);
11384 code = (code == LT ? EQ : NE);
11390 /* We used to optimize signed comparisons against zero, but that
11391 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11392 arrive here as equality comparisons, or (GEU, LTU) are
11393 optimized away. No need to special-case them. */
11395 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11396 (eq B (minus A C)), whichever simplifies. We can only do
11397 this for equality comparisons due to pathological cases involving
11399 if (equality_comparison_p
11400 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11401 XEXP (op0, 1), op1)))
11403 op0 = XEXP (op0, 0);
11408 if (equality_comparison_p
11409 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11410 XEXP (op0, 0), op1)))
11412 op0 = XEXP (op0, 1);
11417 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11418 of bits in X minus 1, is one iff X > 0. */
11419 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11420 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11421 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11423 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11425 op0 = XEXP (op0, 1);
11426 code = (code == GE ? LE : GT);
11432 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11433 if C is zero or B is a constant. */
11434 if (equality_comparison_p
11435 && 0 != (tem = simplify_binary_operation (XOR, mode,
11436 XEXP (op0, 1), op1)))
11438 op0 = XEXP (op0, 0);
11445 case UNEQ: case LTGT:
11446 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11447 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11448 case UNORDERED: case ORDERED:
11449 /* We can't do anything if OP0 is a condition code value, rather
11450 than an actual data value. */
11452 || CC0_P (XEXP (op0, 0))
11453 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11456 /* Get the two operands being compared. */
11457 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11458 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11460 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11462 /* Check for the cases where we simply want the result of the
11463 earlier test or the opposite of that result. */
11464 if (code == NE || code == EQ
11465 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11466 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11467 && (STORE_FLAG_VALUE
11468 & (((HOST_WIDE_INT) 1
11469 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11470 && (code == LT || code == GE)))
11472 enum rtx_code new_code;
11473 if (code == LT || code == NE)
11474 new_code = GET_CODE (op0);
11476 new_code = reversed_comparison_code (op0, NULL);
11478 if (new_code != UNKNOWN)
11489 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11491 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11492 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11493 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11495 op0 = XEXP (op0, 1);
11496 code = (code == GE ? GT : LE);
11502 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11503 will be converted to a ZERO_EXTRACT later. */
11504 if (const_op == 0 && equality_comparison_p
11505 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11506 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11508 op0 = simplify_and_const_int
11509 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11511 XEXP (XEXP (op0, 0), 1)),
11512 (HOST_WIDE_INT) 1);
11516 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11517 zero and X is a comparison and C1 and C2 describe only bits set
11518 in STORE_FLAG_VALUE, we can compare with X. */
11519 if (const_op == 0 && equality_comparison_p
11520 && mode_width <= HOST_BITS_PER_WIDE_INT
11521 && CONST_INT_P (XEXP (op0, 1))
11522 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11523 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11524 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11525 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11527 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11528 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11529 if ((~STORE_FLAG_VALUE & mask) == 0
11530 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11531 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11532 && COMPARISON_P (tem))))
11534 op0 = XEXP (XEXP (op0, 0), 0);
11539 /* If we are doing an equality comparison of an AND of a bit equal
11540 to the sign bit, replace this with a LT or GE comparison of
11541 the underlying value. */
11542 if (equality_comparison_p
11544 && CONST_INT_P (XEXP (op0, 1))
11545 && mode_width <= HOST_BITS_PER_WIDE_INT
11546 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11547 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11549 op0 = XEXP (op0, 0);
11550 code = (code == EQ ? GE : LT);
11554 /* If this AND operation is really a ZERO_EXTEND from a narrower
11555 mode, the constant fits within that mode, and this is either an
11556 equality or unsigned comparison, try to do this comparison in
11561 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11562 -> (ne:DI (reg:SI 4) (const_int 0))
11564 unless TRULY_NOOP_TRUNCATION allows it or the register is
11565 known to hold a value of the required mode the
11566 transformation is invalid. */
11567 if ((equality_comparison_p || unsigned_comparison_p)
11568 && CONST_INT_P (XEXP (op0, 1))
11569 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11570 & GET_MODE_MASK (mode))
11572 && const_op >> i == 0
11573 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11574 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11575 GET_MODE_BITSIZE (GET_MODE (op0)))
11576 || (REG_P (XEXP (op0, 0))
11577 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11579 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11583 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11584 fits in both M1 and M2 and the SUBREG is either paradoxical
11585 or represents the low part, permute the SUBREG and the AND
11587 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11589 unsigned HOST_WIDE_INT c1;
11590 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11591 /* Require an integral mode, to avoid creating something like
11593 if (SCALAR_INT_MODE_P (tmode)
11594 /* It is unsafe to commute the AND into the SUBREG if the
11595 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11596 not defined. As originally written the upper bits
11597 have a defined value due to the AND operation.
11598 However, if we commute the AND inside the SUBREG then
11599 they no longer have defined values and the meaning of
11600 the code has been changed. */
11602 #ifdef WORD_REGISTER_OPERATIONS
11603 || (mode_width > GET_MODE_BITSIZE (tmode)
11604 && mode_width <= BITS_PER_WORD)
11606 || (mode_width <= GET_MODE_BITSIZE (tmode)
11607 && subreg_lowpart_p (XEXP (op0, 0))))
11608 && CONST_INT_P (XEXP (op0, 1))
11609 && mode_width <= HOST_BITS_PER_WIDE_INT
11610 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11611 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11612 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11614 && c1 != GET_MODE_MASK (tmode))
11616 op0 = simplify_gen_binary (AND, tmode,
11617 SUBREG_REG (XEXP (op0, 0)),
11618 gen_int_mode (c1, tmode));
11619 op0 = gen_lowpart (mode, op0);
11624 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11625 if (const_op == 0 && equality_comparison_p
11626 && XEXP (op0, 1) == const1_rtx
11627 && GET_CODE (XEXP (op0, 0)) == NOT)
11629 op0 = simplify_and_const_int
11630 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11631 code = (code == NE ? EQ : NE);
11635 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11636 (eq (and (lshiftrt X) 1) 0).
11637 Also handle the case where (not X) is expressed using xor. */
11638 if (const_op == 0 && equality_comparison_p
11639 && XEXP (op0, 1) == const1_rtx
11640 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11642 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11643 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11645 if (GET_CODE (shift_op) == NOT
11646 || (GET_CODE (shift_op) == XOR
11647 && CONST_INT_P (XEXP (shift_op, 1))
11648 && CONST_INT_P (shift_count)
11649 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11650 && (INTVAL (XEXP (shift_op, 1))
11651 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11653 op0 = simplify_and_const_int
11655 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11656 (HOST_WIDE_INT) 1);
11657 code = (code == NE ? EQ : NE);
11664 /* If we have (compare (ashift FOO N) (const_int C)) and
11665 the high order N bits of FOO (N+1 if an inequality comparison)
11666 are known to be zero, we can do this by comparing FOO with C
11667 shifted right N bits so long as the low-order N bits of C are
11669 if (CONST_INT_P (XEXP (op0, 1))
11670 && INTVAL (XEXP (op0, 1)) >= 0
11671 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11672 < HOST_BITS_PER_WIDE_INT)
11674 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11675 && mode_width <= HOST_BITS_PER_WIDE_INT
11676 && (nonzero_bits (XEXP (op0, 0), mode)
11677 & ~(mask >> (INTVAL (XEXP (op0, 1))
11678 + ! equality_comparison_p))) == 0)
11680 /* We must perform a logical shift, not an arithmetic one,
11681 as we want the top N bits of C to be zero. */
11682 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11684 temp >>= INTVAL (XEXP (op0, 1));
11685 op1 = gen_int_mode (temp, mode);
11686 op0 = XEXP (op0, 0);
11690 /* If we are doing a sign bit comparison, it means we are testing
11691 a particular bit. Convert it to the appropriate AND. */
11692 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11693 && mode_width <= HOST_BITS_PER_WIDE_INT)
11695 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11698 - INTVAL (XEXP (op0, 1)))));
11699 code = (code == LT ? NE : EQ);
11703 /* If this an equality comparison with zero and we are shifting
11704 the low bit to the sign bit, we can convert this to an AND of the
11706 if (const_op == 0 && equality_comparison_p
11707 && CONST_INT_P (XEXP (op0, 1))
11708 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11711 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11712 (HOST_WIDE_INT) 1);
11718 /* If this is an equality comparison with zero, we can do this
11719 as a logical shift, which might be much simpler. */
11720 if (equality_comparison_p && const_op == 0
11721 && CONST_INT_P (XEXP (op0, 1)))
11723 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11725 INTVAL (XEXP (op0, 1)));
11729 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11730 do the comparison in a narrower mode. */
11731 if (! unsigned_comparison_p
11732 && CONST_INT_P (XEXP (op0, 1))
11733 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11734 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11735 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11736 MODE_INT, 1)) != BLKmode
11737 && (((unsigned HOST_WIDE_INT) const_op
11738 + (GET_MODE_MASK (tmode) >> 1) + 1)
11739 <= GET_MODE_MASK (tmode)))
11741 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11745 /* Likewise if OP0 is a PLUS of a sign extension with a
11746 constant, which is usually represented with the PLUS
11747 between the shifts. */
11748 if (! unsigned_comparison_p
11749 && CONST_INT_P (XEXP (op0, 1))
11750 && GET_CODE (XEXP (op0, 0)) == PLUS
11751 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11752 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11753 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11754 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11755 MODE_INT, 1)) != BLKmode
11756 && (((unsigned HOST_WIDE_INT) const_op
11757 + (GET_MODE_MASK (tmode) >> 1) + 1)
11758 <= GET_MODE_MASK (tmode)))
11760 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11761 rtx add_const = XEXP (XEXP (op0, 0), 1);
11762 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11763 add_const, XEXP (op0, 1));
11765 op0 = simplify_gen_binary (PLUS, tmode,
11766 gen_lowpart (tmode, inner),
11771 /* ... fall through ... */
11773 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11774 the low order N bits of FOO are known to be zero, we can do this
11775 by comparing FOO with C shifted left N bits so long as no
11776 overflow occurs. */
11777 if (CONST_INT_P (XEXP (op0, 1))
11778 && INTVAL (XEXP (op0, 1)) >= 0
11779 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11780 && mode_width <= HOST_BITS_PER_WIDE_INT
11781 && (nonzero_bits (XEXP (op0, 0), mode)
11782 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11783 && (((unsigned HOST_WIDE_INT) const_op
11784 + (GET_CODE (op0) != LSHIFTRT
11785 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11788 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11790 /* If the shift was logical, then we must make the condition
11792 if (GET_CODE (op0) == LSHIFTRT)
11793 code = unsigned_condition (code);
11795 const_op <<= INTVAL (XEXP (op0, 1));
11796 op1 = GEN_INT (const_op);
11797 op0 = XEXP (op0, 0);
11801 /* If we are using this shift to extract just the sign bit, we
11802 can replace this with an LT or GE comparison. */
11804 && (equality_comparison_p || sign_bit_comparison_p)
11805 && CONST_INT_P (XEXP (op0, 1))
11806 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11809 op0 = XEXP (op0, 0);
11810 code = (code == NE || code == GT ? LT : GE);
11822 /* Now make any compound operations involved in this comparison. Then,
11823 check for an outmost SUBREG on OP0 that is not doing anything or is
11824 paradoxical. The latter transformation must only be performed when
11825 it is known that the "extra" bits will be the same in op0 and op1 or
11826 that they don't matter. There are three cases to consider:
11828 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11829 care bits and we can assume they have any convenient value. So
11830 making the transformation is safe.
11832 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11833 In this case the upper bits of op0 are undefined. We should not make
11834 the simplification in that case as we do not know the contents of
11837 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11838 UNKNOWN. In that case we know those bits are zeros or ones. We must
11839 also be sure that they are the same as the upper bits of op1.
11841 We can never remove a SUBREG for a non-equality comparison because
11842 the sign bit is in a different place in the underlying object. */
11844 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11845 op1 = make_compound_operation (op1, SET);
11847 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11848 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11849 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11850 && (code == NE || code == EQ))
11852 if (GET_MODE_SIZE (GET_MODE (op0))
11853 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11855 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11857 if (REG_P (SUBREG_REG (op0)))
11859 op0 = SUBREG_REG (op0);
11860 op1 = gen_lowpart (GET_MODE (op0), op1);
11863 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11864 <= HOST_BITS_PER_WIDE_INT)
11865 && (nonzero_bits (SUBREG_REG (op0),
11866 GET_MODE (SUBREG_REG (op0)))
11867 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11869 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11871 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11872 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11873 op0 = SUBREG_REG (op0), op1 = tem;
11877 /* We now do the opposite procedure: Some machines don't have compare
11878 insns in all modes. If OP0's mode is an integer mode smaller than a
11879 word and we can't do a compare in that mode, see if there is a larger
11880 mode for which we can do the compare. There are a number of cases in
11881 which we can use the wider mode. */
11883 mode = GET_MODE (op0);
11884 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11885 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11886 && ! have_insn_for (COMPARE, mode))
11887 for (tmode = GET_MODE_WIDER_MODE (mode);
11889 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11890 tmode = GET_MODE_WIDER_MODE (tmode))
11891 if (have_insn_for (COMPARE, tmode))
11895 /* If this is a test for negative, we can make an explicit
11896 test of the sign bit. Test this first so we can use
11897 a paradoxical subreg to extend OP0. */
11899 if (op1 == const0_rtx && (code == LT || code == GE)
11900 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11902 op0 = simplify_gen_binary (AND, tmode,
11903 gen_lowpart (tmode, op0),
11904 GEN_INT ((HOST_WIDE_INT) 1
11905 << (GET_MODE_BITSIZE (mode)
11907 code = (code == LT) ? NE : EQ;
11911 /* If the only nonzero bits in OP0 and OP1 are those in the
11912 narrower mode and this is an equality or unsigned comparison,
11913 we can use the wider mode. Similarly for sign-extended
11914 values, in which case it is true for all comparisons. */
11915 zero_extended = ((code == EQ || code == NE
11916 || code == GEU || code == GTU
11917 || code == LEU || code == LTU)
11918 && (nonzero_bits (op0, tmode)
11919 & ~GET_MODE_MASK (mode)) == 0
11920 && ((CONST_INT_P (op1)
11921 || (nonzero_bits (op1, tmode)
11922 & ~GET_MODE_MASK (mode)) == 0)));
11925 || ((num_sign_bit_copies (op0, tmode)
11926 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11927 - GET_MODE_BITSIZE (mode)))
11928 && (num_sign_bit_copies (op1, tmode)
11929 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11930 - GET_MODE_BITSIZE (mode)))))
11932 /* If OP0 is an AND and we don't have an AND in MODE either,
11933 make a new AND in the proper mode. */
11934 if (GET_CODE (op0) == AND
11935 && !have_insn_for (AND, mode))
11936 op0 = simplify_gen_binary (AND, tmode,
11937 gen_lowpart (tmode,
11939 gen_lowpart (tmode,
11945 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11946 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11950 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11951 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11958 #ifdef CANONICALIZE_COMPARISON
11959 /* If this machine only supports a subset of valid comparisons, see if we
11960 can convert an unsupported one into a supported one. */
11961 CANONICALIZE_COMPARISON (code, op0, op1);
11970 /* Utility function for record_value_for_reg. Count number of
11975 enum rtx_code code = GET_CODE (x);
11979 if (GET_RTX_CLASS (code) == '2'
11980 || GET_RTX_CLASS (code) == 'c')
11982 rtx x0 = XEXP (x, 0);
11983 rtx x1 = XEXP (x, 1);
11986 return 1 + 2 * count_rtxs (x0);
11988 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11989 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11990 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11991 return 2 + 2 * count_rtxs (x0)
11992 + count_rtxs (x == XEXP (x1, 0)
11993 ? XEXP (x1, 1) : XEXP (x1, 0));
11995 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11996 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11997 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11998 return 2 + 2 * count_rtxs (x1)
11999 + count_rtxs (x == XEXP (x0, 0)
12000 ? XEXP (x0, 1) : XEXP (x0, 0));
12003 fmt = GET_RTX_FORMAT (code);
12004 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12006 ret += count_rtxs (XEXP (x, i));
12007 else if (fmt[i] == 'E')
12008 for (j = 0; j < XVECLEN (x, i); j++)
12009 ret += count_rtxs (XVECEXP (x, i, j));
12014 /* Utility function for following routine. Called when X is part of a value
12015 being stored into last_set_value. Sets last_set_table_tick
12016 for each register mentioned. Similar to mention_regs in cse.c */
12019 update_table_tick (rtx x)
12021 enum rtx_code code = GET_CODE (x);
12022 const char *fmt = GET_RTX_FORMAT (code);
12027 unsigned int regno = REGNO (x);
12028 unsigned int endregno = END_REGNO (x);
12031 for (r = regno; r < endregno; r++)
12033 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12034 rsp->last_set_table_tick = label_tick;
12040 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12043 /* Check for identical subexpressions. If x contains
12044 identical subexpression we only have to traverse one of
12046 if (i == 0 && ARITHMETIC_P (x))
12048 /* Note that at this point x1 has already been
12050 rtx x0 = XEXP (x, 0);
12051 rtx x1 = XEXP (x, 1);
12053 /* If x0 and x1 are identical then there is no need to
12058 /* If x0 is identical to a subexpression of x1 then while
12059 processing x1, x0 has already been processed. Thus we
12060 are done with x. */
12061 if (ARITHMETIC_P (x1)
12062 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12065 /* If x1 is identical to a subexpression of x0 then we
12066 still have to process the rest of x0. */
12067 if (ARITHMETIC_P (x0)
12068 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12070 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12075 update_table_tick (XEXP (x, i));
12077 else if (fmt[i] == 'E')
12078 for (j = 0; j < XVECLEN (x, i); j++)
12079 update_table_tick (XVECEXP (x, i, j));
12082 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12083 are saying that the register is clobbered and we no longer know its
12084 value. If INSN is zero, don't update reg_stat[].last_set; this is
12085 only permitted with VALUE also zero and is used to invalidate the
12089 record_value_for_reg (rtx reg, rtx insn, rtx value)
12091 unsigned int regno = REGNO (reg);
12092 unsigned int endregno = END_REGNO (reg);
12094 reg_stat_type *rsp;
12096 /* If VALUE contains REG and we have a previous value for REG, substitute
12097 the previous value. */
12098 if (value && insn && reg_overlap_mentioned_p (reg, value))
12102 /* Set things up so get_last_value is allowed to see anything set up to
12104 subst_low_luid = DF_INSN_LUID (insn);
12105 tem = get_last_value (reg);
12107 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12108 it isn't going to be useful and will take a lot of time to process,
12109 so just use the CLOBBER. */
12113 if (ARITHMETIC_P (tem)
12114 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12115 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12116 tem = XEXP (tem, 0);
12117 else if (count_occurrences (value, reg, 1) >= 2)
12119 /* If there are two or more occurrences of REG in VALUE,
12120 prevent the value from growing too much. */
12121 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12122 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12125 value = replace_rtx (copy_rtx (value), reg, tem);
12129 /* For each register modified, show we don't know its value, that
12130 we don't know about its bitwise content, that its value has been
12131 updated, and that we don't know the location of the death of the
12133 for (i = regno; i < endregno; i++)
12135 rsp = VEC_index (reg_stat_type, reg_stat, i);
12138 rsp->last_set = insn;
12140 rsp->last_set_value = 0;
12141 rsp->last_set_mode = VOIDmode;
12142 rsp->last_set_nonzero_bits = 0;
12143 rsp->last_set_sign_bit_copies = 0;
12144 rsp->last_death = 0;
12145 rsp->truncated_to_mode = VOIDmode;
12148 /* Mark registers that are being referenced in this value. */
12150 update_table_tick (value);
12152 /* Now update the status of each register being set.
12153 If someone is using this register in this block, set this register
12154 to invalid since we will get confused between the two lives in this
12155 basic block. This makes using this register always invalid. In cse, we
12156 scan the table to invalidate all entries using this register, but this
12157 is too much work for us. */
12159 for (i = regno; i < endregno; i++)
12161 rsp = VEC_index (reg_stat_type, reg_stat, i);
12162 rsp->last_set_label = label_tick;
12164 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12165 rsp->last_set_invalid = 1;
12167 rsp->last_set_invalid = 0;
12170 /* The value being assigned might refer to X (like in "x++;"). In that
12171 case, we must replace it with (clobber (const_int 0)) to prevent
12173 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12174 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12176 value = copy_rtx (value);
12177 if (!get_last_value_validate (&value, insn, label_tick, 1))
12181 /* For the main register being modified, update the value, the mode, the
12182 nonzero bits, and the number of sign bit copies. */
12184 rsp->last_set_value = value;
12188 enum machine_mode mode = GET_MODE (reg);
12189 subst_low_luid = DF_INSN_LUID (insn);
12190 rsp->last_set_mode = mode;
12191 if (GET_MODE_CLASS (mode) == MODE_INT
12192 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12193 mode = nonzero_bits_mode;
12194 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12195 rsp->last_set_sign_bit_copies
12196 = num_sign_bit_copies (value, GET_MODE (reg));
12200 /* Called via note_stores from record_dead_and_set_regs to handle one
12201 SET or CLOBBER in an insn. DATA is the instruction in which the
12202 set is occurring. */
12205 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12207 rtx record_dead_insn = (rtx) data;
12209 if (GET_CODE (dest) == SUBREG)
12210 dest = SUBREG_REG (dest);
12212 if (!record_dead_insn)
12215 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12221 /* If we are setting the whole register, we know its value. Otherwise
12222 show that we don't know the value. We can handle SUBREG in
12224 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12225 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12226 else if (GET_CODE (setter) == SET
12227 && GET_CODE (SET_DEST (setter)) == SUBREG
12228 && SUBREG_REG (SET_DEST (setter)) == dest
12229 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12230 && subreg_lowpart_p (SET_DEST (setter)))
12231 record_value_for_reg (dest, record_dead_insn,
12232 gen_lowpart (GET_MODE (dest),
12233 SET_SRC (setter)));
12235 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12237 else if (MEM_P (dest)
12238 /* Ignore pushes, they clobber nothing. */
12239 && ! push_operand (dest, GET_MODE (dest)))
12240 mem_last_set = DF_INSN_LUID (record_dead_insn);
12243 /* Update the records of when each REG was most recently set or killed
12244 for the things done by INSN. This is the last thing done in processing
12245 INSN in the combiner loop.
12247 We update reg_stat[], in particular fields last_set, last_set_value,
12248 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12249 last_death, and also the similar information mem_last_set (which insn
12250 most recently modified memory) and last_call_luid (which insn was the
12251 most recent subroutine call). */
12254 record_dead_and_set_regs (rtx insn)
12259 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12261 if (REG_NOTE_KIND (link) == REG_DEAD
12262 && REG_P (XEXP (link, 0)))
12264 unsigned int regno = REGNO (XEXP (link, 0));
12265 unsigned int endregno = END_REGNO (XEXP (link, 0));
12267 for (i = regno; i < endregno; i++)
12269 reg_stat_type *rsp;
12271 rsp = VEC_index (reg_stat_type, reg_stat, i);
12272 rsp->last_death = insn;
12275 else if (REG_NOTE_KIND (link) == REG_INC)
12276 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12281 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12282 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12284 reg_stat_type *rsp;
12286 rsp = VEC_index (reg_stat_type, reg_stat, i);
12287 rsp->last_set_invalid = 1;
12288 rsp->last_set = insn;
12289 rsp->last_set_value = 0;
12290 rsp->last_set_mode = VOIDmode;
12291 rsp->last_set_nonzero_bits = 0;
12292 rsp->last_set_sign_bit_copies = 0;
12293 rsp->last_death = 0;
12294 rsp->truncated_to_mode = VOIDmode;
12297 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12299 /* We can't combine into a call pattern. Remember, though, that
12300 the return value register is set at this LUID. We could
12301 still replace a register with the return value from the
12302 wrong subroutine call! */
12303 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12306 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12309 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12310 register present in the SUBREG, so for each such SUBREG go back and
12311 adjust nonzero and sign bit information of the registers that are
12312 known to have some zero/sign bits set.
12314 This is needed because when combine blows the SUBREGs away, the
12315 information on zero/sign bits is lost and further combines can be
12316 missed because of that. */
12319 record_promoted_value (rtx insn, rtx subreg)
12322 unsigned int regno = REGNO (SUBREG_REG (subreg));
12323 enum machine_mode mode = GET_MODE (subreg);
12325 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12328 for (links = LOG_LINKS (insn); links;)
12330 reg_stat_type *rsp;
12332 insn = XEXP (links, 0);
12333 set = single_set (insn);
12335 if (! set || !REG_P (SET_DEST (set))
12336 || REGNO (SET_DEST (set)) != regno
12337 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12339 links = XEXP (links, 1);
12343 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12344 if (rsp->last_set == insn)
12346 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12347 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12350 if (REG_P (SET_SRC (set)))
12352 regno = REGNO (SET_SRC (set));
12353 links = LOG_LINKS (insn);
12360 /* Check if X, a register, is known to contain a value already
12361 truncated to MODE. In this case we can use a subreg to refer to
12362 the truncated value even though in the generic case we would need
12363 an explicit truncation. */
12366 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12368 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12369 enum machine_mode truncated = rsp->truncated_to_mode;
12372 || rsp->truncation_label < label_tick_ebb_start)
12374 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12376 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12377 GET_MODE_BITSIZE (truncated)))
12382 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12383 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12384 might be able to turn a truncate into a subreg using this information.
12385 Return -1 if traversing *P is complete or 0 otherwise. */
12388 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12391 enum machine_mode truncated_mode;
12392 reg_stat_type *rsp;
12394 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12396 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12397 truncated_mode = GET_MODE (x);
12399 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12402 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12403 GET_MODE_BITSIZE (original_mode)))
12406 x = SUBREG_REG (x);
12408 /* ??? For hard-regs we now record everything. We might be able to
12409 optimize this using last_set_mode. */
12410 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12411 truncated_mode = GET_MODE (x);
12415 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12416 if (rsp->truncated_to_mode == 0
12417 || rsp->truncation_label < label_tick_ebb_start
12418 || (GET_MODE_SIZE (truncated_mode)
12419 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12421 rsp->truncated_to_mode = truncated_mode;
12422 rsp->truncation_label = label_tick;
12428 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12429 the modes they are used in. This can help truning TRUNCATEs into
12433 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12435 for_each_rtx (x, record_truncated_value, NULL);
12438 /* Scan X for promoted SUBREGs. For each one found,
12439 note what it implies to the registers used in it. */
12442 check_promoted_subreg (rtx insn, rtx x)
12444 if (GET_CODE (x) == SUBREG
12445 && SUBREG_PROMOTED_VAR_P (x)
12446 && REG_P (SUBREG_REG (x)))
12447 record_promoted_value (insn, x);
12450 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12453 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12457 check_promoted_subreg (insn, XEXP (x, i));
12461 if (XVEC (x, i) != 0)
12462 for (j = 0; j < XVECLEN (x, i); j++)
12463 check_promoted_subreg (insn, XVECEXP (x, i, j));
12469 /* Verify that all the registers and memory references mentioned in *LOC are
12470 still valid. *LOC was part of a value set in INSN when label_tick was
12471 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12472 the invalid references with (clobber (const_int 0)) and return 1. This
12473 replacement is useful because we often can get useful information about
12474 the form of a value (e.g., if it was produced by a shift that always
12475 produces -1 or 0) even though we don't know exactly what registers it
12476 was produced from. */
12479 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12482 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12483 int len = GET_RTX_LENGTH (GET_CODE (x));
12488 unsigned int regno = REGNO (x);
12489 unsigned int endregno = END_REGNO (x);
12492 for (j = regno; j < endregno; j++)
12494 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12495 if (rsp->last_set_invalid
12496 /* If this is a pseudo-register that was only set once and not
12497 live at the beginning of the function, it is always valid. */
12498 || (! (regno >= FIRST_PSEUDO_REGISTER
12499 && REG_N_SETS (regno) == 1
12500 && (!REGNO_REG_SET_P
12501 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12502 && rsp->last_set_label > tick))
12505 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12512 /* If this is a memory reference, make sure that there were no stores after
12513 it that might have clobbered the value. We don't have alias info, so we
12514 assume any store invalidates it. Moreover, we only have local UIDs, so
12515 we also assume that there were stores in the intervening basic blocks. */
12516 else if (MEM_P (x) && !MEM_READONLY_P (x)
12517 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12520 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12524 for (i = 0; i < len; i++)
12528 /* Check for identical subexpressions. If x contains
12529 identical subexpression we only have to traverse one of
12531 if (i == 1 && ARITHMETIC_P (x))
12533 /* Note that at this point x0 has already been checked
12534 and found valid. */
12535 rtx x0 = XEXP (x, 0);
12536 rtx x1 = XEXP (x, 1);
12538 /* If x0 and x1 are identical then x is also valid. */
12542 /* If x1 is identical to a subexpression of x0 then
12543 while checking x0, x1 has already been checked. Thus
12544 it is valid and so as x. */
12545 if (ARITHMETIC_P (x0)
12546 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12549 /* If x0 is identical to a subexpression of x1 then x is
12550 valid iff the rest of x1 is valid. */
12551 if (ARITHMETIC_P (x1)
12552 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12554 get_last_value_validate (&XEXP (x1,
12555 x0 == XEXP (x1, 0) ? 1 : 0),
12556 insn, tick, replace);
12559 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12563 else if (fmt[i] == 'E')
12564 for (j = 0; j < XVECLEN (x, i); j++)
12565 if (get_last_value_validate (&XVECEXP (x, i, j),
12566 insn, tick, replace) == 0)
12570 /* If we haven't found a reason for it to be invalid, it is valid. */
12574 /* Get the last value assigned to X, if known. Some registers
12575 in the value may be replaced with (clobber (const_int 0)) if their value
12576 is known longer known reliably. */
12579 get_last_value (const_rtx x)
12581 unsigned int regno;
12583 reg_stat_type *rsp;
12585 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12586 then convert it to the desired mode. If this is a paradoxical SUBREG,
12587 we cannot predict what values the "extra" bits might have. */
12588 if (GET_CODE (x) == SUBREG
12589 && subreg_lowpart_p (x)
12590 && (GET_MODE_SIZE (GET_MODE (x))
12591 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12592 && (value = get_last_value (SUBREG_REG (x))) != 0)
12593 return gen_lowpart (GET_MODE (x), value);
12599 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12600 value = rsp->last_set_value;
12602 /* If we don't have a value, or if it isn't for this basic block and
12603 it's either a hard register, set more than once, or it's a live
12604 at the beginning of the function, return 0.
12606 Because if it's not live at the beginning of the function then the reg
12607 is always set before being used (is never used without being set).
12608 And, if it's set only once, and it's always set before use, then all
12609 uses must have the same last value, even if it's not from this basic
12613 || (rsp->last_set_label < label_tick_ebb_start
12614 && (regno < FIRST_PSEUDO_REGISTER
12615 || REG_N_SETS (regno) != 1
12617 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12620 /* If the value was set in a later insn than the ones we are processing,
12621 we can't use it even if the register was only set once. */
12622 if (rsp->last_set_label == label_tick
12623 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12626 /* If the value has all its registers valid, return it. */
12627 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12630 /* Otherwise, make a copy and replace any invalid register with
12631 (clobber (const_int 0)). If that fails for some reason, return 0. */
12633 value = copy_rtx (value);
12634 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12640 /* Return nonzero if expression X refers to a REG or to memory
12641 that is set in an instruction more recent than FROM_LUID. */
12644 use_crosses_set_p (const_rtx x, int from_luid)
12648 enum rtx_code code = GET_CODE (x);
12652 unsigned int regno = REGNO (x);
12653 unsigned endreg = END_REGNO (x);
12655 #ifdef PUSH_ROUNDING
12656 /* Don't allow uses of the stack pointer to be moved,
12657 because we don't know whether the move crosses a push insn. */
12658 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12661 for (; regno < endreg; regno++)
12663 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12665 && rsp->last_set_label == label_tick
12666 && DF_INSN_LUID (rsp->last_set) > from_luid)
12672 if (code == MEM && mem_last_set > from_luid)
12675 fmt = GET_RTX_FORMAT (code);
12677 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12682 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12683 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12686 else if (fmt[i] == 'e'
12687 && use_crosses_set_p (XEXP (x, i), from_luid))
12693 /* Define three variables used for communication between the following
12696 static unsigned int reg_dead_regno, reg_dead_endregno;
12697 static int reg_dead_flag;
12699 /* Function called via note_stores from reg_dead_at_p.
12701 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12702 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12705 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12707 unsigned int regno, endregno;
12712 regno = REGNO (dest);
12713 endregno = END_REGNO (dest);
12714 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12715 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12718 /* Return nonzero if REG is known to be dead at INSN.
12720 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12721 referencing REG, it is dead. If we hit a SET referencing REG, it is
12722 live. Otherwise, see if it is live or dead at the start of the basic
12723 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12724 must be assumed to be always live. */
12727 reg_dead_at_p (rtx reg, rtx insn)
12732 /* Set variables for reg_dead_at_p_1. */
12733 reg_dead_regno = REGNO (reg);
12734 reg_dead_endregno = END_REGNO (reg);
12738 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12739 we allow the machine description to decide whether use-and-clobber
12740 patterns are OK. */
12741 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12743 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12744 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12748 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12749 beginning of basic block. */
12750 block = BLOCK_FOR_INSN (insn);
12755 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12757 return reg_dead_flag == 1 ? 1 : 0;
12759 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12763 if (insn == BB_HEAD (block))
12766 insn = PREV_INSN (insn);
12769 /* Look at live-in sets for the basic block that we were in. */
12770 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12771 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12777 /* Note hard registers in X that are used. */
12780 mark_used_regs_combine (rtx x)
12782 RTX_CODE code = GET_CODE (x);
12783 unsigned int regno;
12796 case ADDR_DIFF_VEC:
12799 /* CC0 must die in the insn after it is set, so we don't need to take
12800 special note of it here. */
12806 /* If we are clobbering a MEM, mark any hard registers inside the
12807 address as used. */
12808 if (MEM_P (XEXP (x, 0)))
12809 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12814 /* A hard reg in a wide mode may really be multiple registers.
12815 If so, mark all of them just like the first. */
12816 if (regno < FIRST_PSEUDO_REGISTER)
12818 /* None of this applies to the stack, frame or arg pointers. */
12819 if (regno == STACK_POINTER_REGNUM
12820 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12821 || regno == HARD_FRAME_POINTER_REGNUM
12823 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12824 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12826 || regno == FRAME_POINTER_REGNUM)
12829 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12835 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12837 rtx testreg = SET_DEST (x);
12839 while (GET_CODE (testreg) == SUBREG
12840 || GET_CODE (testreg) == ZERO_EXTRACT
12841 || GET_CODE (testreg) == STRICT_LOW_PART)
12842 testreg = XEXP (testreg, 0);
12844 if (MEM_P (testreg))
12845 mark_used_regs_combine (XEXP (testreg, 0));
12847 mark_used_regs_combine (SET_SRC (x));
12855 /* Recursively scan the operands of this expression. */
12858 const char *fmt = GET_RTX_FORMAT (code);
12860 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12863 mark_used_regs_combine (XEXP (x, i));
12864 else if (fmt[i] == 'E')
12868 for (j = 0; j < XVECLEN (x, i); j++)
12869 mark_used_regs_combine (XVECEXP (x, i, j));
12875 /* Remove register number REGNO from the dead registers list of INSN.
12877 Return the note used to record the death, if there was one. */
12880 remove_death (unsigned int regno, rtx insn)
12882 rtx note = find_regno_note (insn, REG_DEAD, regno);
12885 remove_note (insn, note);
12890 /* For each register (hardware or pseudo) used within expression X, if its
12891 death is in an instruction with luid between FROM_LUID (inclusive) and
12892 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12893 list headed by PNOTES.
12895 That said, don't move registers killed by maybe_kill_insn.
12897 This is done when X is being merged by combination into TO_INSN. These
12898 notes will then be distributed as needed. */
12901 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12906 enum rtx_code code = GET_CODE (x);
12910 unsigned int regno = REGNO (x);
12911 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12913 /* Don't move the register if it gets killed in between from and to. */
12914 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12915 && ! reg_referenced_p (x, maybe_kill_insn))
12919 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12920 && DF_INSN_LUID (where_dead) >= from_luid
12921 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12923 rtx note = remove_death (regno, where_dead);
12925 /* It is possible for the call above to return 0. This can occur
12926 when last_death points to I2 or I1 that we combined with.
12927 In that case make a new note.
12929 We must also check for the case where X is a hard register
12930 and NOTE is a death note for a range of hard registers
12931 including X. In that case, we must put REG_DEAD notes for
12932 the remaining registers in place of NOTE. */
12934 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12935 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12936 > GET_MODE_SIZE (GET_MODE (x))))
12938 unsigned int deadregno = REGNO (XEXP (note, 0));
12939 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12940 unsigned int ourend = END_HARD_REGNO (x);
12943 for (i = deadregno; i < deadend; i++)
12944 if (i < regno || i >= ourend)
12945 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12948 /* If we didn't find any note, or if we found a REG_DEAD note that
12949 covers only part of the given reg, and we have a multi-reg hard
12950 register, then to be safe we must check for REG_DEAD notes
12951 for each register other than the first. They could have
12952 their own REG_DEAD notes lying around. */
12953 else if ((note == 0
12955 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12956 < GET_MODE_SIZE (GET_MODE (x)))))
12957 && regno < FIRST_PSEUDO_REGISTER
12958 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12960 unsigned int ourend = END_HARD_REGNO (x);
12961 unsigned int i, offset;
12965 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12969 for (i = regno + offset; i < ourend; i++)
12970 move_deaths (regno_reg_rtx[i],
12971 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12974 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12976 XEXP (note, 1) = *pnotes;
12980 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12986 else if (GET_CODE (x) == SET)
12988 rtx dest = SET_DEST (x);
12990 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12992 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12993 that accesses one word of a multi-word item, some
12994 piece of everything register in the expression is used by
12995 this insn, so remove any old death. */
12996 /* ??? So why do we test for equality of the sizes? */
12998 if (GET_CODE (dest) == ZERO_EXTRACT
12999 || GET_CODE (dest) == STRICT_LOW_PART
13000 || (GET_CODE (dest) == SUBREG
13001 && (((GET_MODE_SIZE (GET_MODE (dest))
13002 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13003 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13004 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13006 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13010 /* If this is some other SUBREG, we know it replaces the entire
13011 value, so use that as the destination. */
13012 if (GET_CODE (dest) == SUBREG)
13013 dest = SUBREG_REG (dest);
13015 /* If this is a MEM, adjust deaths of anything used in the address.
13016 For a REG (the only other possibility), the entire value is
13017 being replaced so the old value is not used in this insn. */
13020 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13025 else if (GET_CODE (x) == CLOBBER)
13028 len = GET_RTX_LENGTH (code);
13029 fmt = GET_RTX_FORMAT (code);
13031 for (i = 0; i < len; i++)
13036 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13037 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13040 else if (fmt[i] == 'e')
13041 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13045 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13046 pattern of an insn. X must be a REG. */
13049 reg_bitfield_target_p (rtx x, rtx body)
13053 if (GET_CODE (body) == SET)
13055 rtx dest = SET_DEST (body);
13057 unsigned int regno, tregno, endregno, endtregno;
13059 if (GET_CODE (dest) == ZERO_EXTRACT)
13060 target = XEXP (dest, 0);
13061 else if (GET_CODE (dest) == STRICT_LOW_PART)
13062 target = SUBREG_REG (XEXP (dest, 0));
13066 if (GET_CODE (target) == SUBREG)
13067 target = SUBREG_REG (target);
13069 if (!REG_P (target))
13072 tregno = REGNO (target), regno = REGNO (x);
13073 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13074 return target == x;
13076 endtregno = end_hard_regno (GET_MODE (target), tregno);
13077 endregno = end_hard_regno (GET_MODE (x), regno);
13079 return endregno > tregno && regno < endtregno;
13082 else if (GET_CODE (body) == PARALLEL)
13083 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13084 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13090 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13091 as appropriate. I3 and I2 are the insns resulting from the combination
13092 insns including FROM (I2 may be zero).
13094 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13095 not need REG_DEAD notes because they are being substituted for. This
13096 saves searching in the most common cases.
13098 Each note in the list is either ignored or placed on some insns, depending
13099 on the type of note. */
13102 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13103 rtx elim_i1, rtx elim_i0)
13105 rtx note, next_note;
13108 for (note = notes; note; note = next_note)
13110 rtx place = 0, place2 = 0;
13112 next_note = XEXP (note, 1);
13113 switch (REG_NOTE_KIND (note))
13117 /* Doesn't matter much where we put this, as long as it's somewhere.
13118 It is preferable to keep these notes on branches, which is most
13119 likely to be i3. */
13123 case REG_VALUE_PROFILE:
13124 /* Just get rid of this note, as it is unused later anyway. */
13127 case REG_NON_LOCAL_GOTO:
13132 gcc_assert (i2 && JUMP_P (i2));
13137 case REG_EH_REGION:
13138 /* These notes must remain with the call or trapping instruction. */
13141 else if (i2 && CALL_P (i2))
13145 gcc_assert (cfun->can_throw_non_call_exceptions);
13146 if (may_trap_p (i3))
13148 else if (i2 && may_trap_p (i2))
13150 /* ??? Otherwise assume we've combined things such that we
13151 can now prove that the instructions can't trap. Drop the
13152 note in this case. */
13158 /* These notes must remain with the call. It should not be
13159 possible for both I2 and I3 to be a call. */
13164 gcc_assert (i2 && CALL_P (i2));
13170 /* Any clobbers for i3 may still exist, and so we must process
13171 REG_UNUSED notes from that insn.
13173 Any clobbers from i2 or i1 can only exist if they were added by
13174 recog_for_combine. In that case, recog_for_combine created the
13175 necessary REG_UNUSED notes. Trying to keep any original
13176 REG_UNUSED notes from these insns can cause incorrect output
13177 if it is for the same register as the original i3 dest.
13178 In that case, we will notice that the register is set in i3,
13179 and then add a REG_UNUSED note for the destination of i3, which
13180 is wrong. However, it is possible to have REG_UNUSED notes from
13181 i2 or i1 for register which were both used and clobbered, so
13182 we keep notes from i2 or i1 if they will turn into REG_DEAD
13185 /* If this register is set or clobbered in I3, put the note there
13186 unless there is one already. */
13187 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13189 if (from_insn != i3)
13192 if (! (REG_P (XEXP (note, 0))
13193 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13194 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13197 /* Otherwise, if this register is used by I3, then this register
13198 now dies here, so we must put a REG_DEAD note here unless there
13200 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13201 && ! (REG_P (XEXP (note, 0))
13202 ? find_regno_note (i3, REG_DEAD,
13203 REGNO (XEXP (note, 0)))
13204 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13206 PUT_REG_NOTE_KIND (note, REG_DEAD);
13214 /* These notes say something about results of an insn. We can
13215 only support them if they used to be on I3 in which case they
13216 remain on I3. Otherwise they are ignored.
13218 If the note refers to an expression that is not a constant, we
13219 must also ignore the note since we cannot tell whether the
13220 equivalence is still true. It might be possible to do
13221 slightly better than this (we only have a problem if I2DEST
13222 or I1DEST is present in the expression), but it doesn't
13223 seem worth the trouble. */
13225 if (from_insn == i3
13226 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13231 /* These notes say something about how a register is used. They must
13232 be present on any use of the register in I2 or I3. */
13233 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13236 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13245 case REG_LABEL_TARGET:
13246 case REG_LABEL_OPERAND:
13247 /* This can show up in several ways -- either directly in the
13248 pattern, or hidden off in the constant pool with (or without?)
13249 a REG_EQUAL note. */
13250 /* ??? Ignore the without-reg_equal-note problem for now. */
13251 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13252 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13253 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13254 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13258 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13259 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13260 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13261 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13269 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13270 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13272 if (place && JUMP_P (place)
13273 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13274 && (JUMP_LABEL (place) == NULL
13275 || JUMP_LABEL (place) == XEXP (note, 0)))
13277 rtx label = JUMP_LABEL (place);
13280 JUMP_LABEL (place) = XEXP (note, 0);
13281 else if (LABEL_P (label))
13282 LABEL_NUSES (label)--;
13285 if (place2 && JUMP_P (place2)
13286 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13287 && (JUMP_LABEL (place2) == NULL
13288 || JUMP_LABEL (place2) == XEXP (note, 0)))
13290 rtx label = JUMP_LABEL (place2);
13293 JUMP_LABEL (place2) = XEXP (note, 0);
13294 else if (LABEL_P (label))
13295 LABEL_NUSES (label)--;
13301 /* This note says something about the value of a register prior
13302 to the execution of an insn. It is too much trouble to see
13303 if the note is still correct in all situations. It is better
13304 to simply delete it. */
13308 /* If we replaced the right hand side of FROM_INSN with a
13309 REG_EQUAL note, the original use of the dying register
13310 will not have been combined into I3 and I2. In such cases,
13311 FROM_INSN is guaranteed to be the first of the combined
13312 instructions, so we simply need to search back before
13313 FROM_INSN for the previous use or set of this register,
13314 then alter the notes there appropriately.
13316 If the register is used as an input in I3, it dies there.
13317 Similarly for I2, if it is nonzero and adjacent to I3.
13319 If the register is not used as an input in either I3 or I2
13320 and it is not one of the registers we were supposed to eliminate,
13321 there are two possibilities. We might have a non-adjacent I2
13322 or we might have somehow eliminated an additional register
13323 from a computation. For example, we might have had A & B where
13324 we discover that B will always be zero. In this case we will
13325 eliminate the reference to A.
13327 In both cases, we must search to see if we can find a previous
13328 use of A and put the death note there. */
13331 && from_insn == i2mod
13332 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13337 && CALL_P (from_insn)
13338 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13340 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13342 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13343 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13345 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13347 && reg_overlap_mentioned_p (XEXP (note, 0),
13349 || rtx_equal_p (XEXP (note, 0), elim_i1)
13350 || rtx_equal_p (XEXP (note, 0), elim_i0))
13357 basic_block bb = this_basic_block;
13359 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13361 if (!NONDEBUG_INSN_P (tem))
13363 if (tem == BB_HEAD (bb))
13368 /* If the register is being set at TEM, see if that is all
13369 TEM is doing. If so, delete TEM. Otherwise, make this
13370 into a REG_UNUSED note instead. Don't delete sets to
13371 global register vars. */
13372 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13373 || !global_regs[REGNO (XEXP (note, 0))])
13374 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13376 rtx set = single_set (tem);
13377 rtx inner_dest = 0;
13379 rtx cc0_setter = NULL_RTX;
13383 for (inner_dest = SET_DEST (set);
13384 (GET_CODE (inner_dest) == STRICT_LOW_PART
13385 || GET_CODE (inner_dest) == SUBREG
13386 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13387 inner_dest = XEXP (inner_dest, 0))
13390 /* Verify that it was the set, and not a clobber that
13391 modified the register.
13393 CC0 targets must be careful to maintain setter/user
13394 pairs. If we cannot delete the setter due to side
13395 effects, mark the user with an UNUSED note instead
13398 if (set != 0 && ! side_effects_p (SET_SRC (set))
13399 && rtx_equal_p (XEXP (note, 0), inner_dest)
13401 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13402 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13403 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13407 /* Move the notes and links of TEM elsewhere.
13408 This might delete other dead insns recursively.
13409 First set the pattern to something that won't use
13411 rtx old_notes = REG_NOTES (tem);
13413 PATTERN (tem) = pc_rtx;
13414 REG_NOTES (tem) = NULL;
13416 distribute_notes (old_notes, tem, tem, NULL_RTX,
13417 NULL_RTX, NULL_RTX, NULL_RTX);
13418 distribute_links (LOG_LINKS (tem));
13420 SET_INSN_DELETED (tem);
13425 /* Delete the setter too. */
13428 PATTERN (cc0_setter) = pc_rtx;
13429 old_notes = REG_NOTES (cc0_setter);
13430 REG_NOTES (cc0_setter) = NULL;
13432 distribute_notes (old_notes, cc0_setter,
13433 cc0_setter, NULL_RTX,
13434 NULL_RTX, NULL_RTX, NULL_RTX);
13435 distribute_links (LOG_LINKS (cc0_setter));
13437 SET_INSN_DELETED (cc0_setter);
13438 if (cc0_setter == i2)
13445 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13447 /* If there isn't already a REG_UNUSED note, put one
13448 here. Do not place a REG_DEAD note, even if
13449 the register is also used here; that would not
13450 match the algorithm used in lifetime analysis
13451 and can cause the consistency check in the
13452 scheduler to fail. */
13453 if (! find_regno_note (tem, REG_UNUSED,
13454 REGNO (XEXP (note, 0))))
13459 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13461 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13465 /* If we are doing a 3->2 combination, and we have a
13466 register which formerly died in i3 and was not used
13467 by i2, which now no longer dies in i3 and is used in
13468 i2 but does not die in i2, and place is between i2
13469 and i3, then we may need to move a link from place to
13471 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13473 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13474 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13476 rtx links = LOG_LINKS (place);
13477 LOG_LINKS (place) = 0;
13478 distribute_links (links);
13483 if (tem == BB_HEAD (bb))
13489 /* If the register is set or already dead at PLACE, we needn't do
13490 anything with this note if it is still a REG_DEAD note.
13491 We check here if it is set at all, not if is it totally replaced,
13492 which is what `dead_or_set_p' checks, so also check for it being
13495 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13497 unsigned int regno = REGNO (XEXP (note, 0));
13498 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13500 if (dead_or_set_p (place, XEXP (note, 0))
13501 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13503 /* Unless the register previously died in PLACE, clear
13504 last_death. [I no longer understand why this is
13506 if (rsp->last_death != place)
13507 rsp->last_death = 0;
13511 rsp->last_death = place;
13513 /* If this is a death note for a hard reg that is occupying
13514 multiple registers, ensure that we are still using all
13515 parts of the object. If we find a piece of the object
13516 that is unused, we must arrange for an appropriate REG_DEAD
13517 note to be added for it. However, we can't just emit a USE
13518 and tag the note to it, since the register might actually
13519 be dead; so we recourse, and the recursive call then finds
13520 the previous insn that used this register. */
13522 if (place && regno < FIRST_PSEUDO_REGISTER
13523 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13525 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13529 for (i = regno; i < endregno; i++)
13530 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13531 && ! find_regno_fusage (place, USE, i))
13532 || dead_or_set_regno_p (place, i))
13537 /* Put only REG_DEAD notes for pieces that are
13538 not already dead or set. */
13540 for (i = regno; i < endregno;
13541 i += hard_regno_nregs[i][reg_raw_mode[i]])
13543 rtx piece = regno_reg_rtx[i];
13544 basic_block bb = this_basic_block;
13546 if (! dead_or_set_p (place, piece)
13547 && ! reg_bitfield_target_p (piece,
13550 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13553 distribute_notes (new_note, place, place,
13554 NULL_RTX, NULL_RTX, NULL_RTX,
13557 else if (! refers_to_regno_p (i, i + 1,
13558 PATTERN (place), 0)
13559 && ! find_regno_fusage (place, USE, i))
13560 for (tem = PREV_INSN (place); ;
13561 tem = PREV_INSN (tem))
13563 if (!NONDEBUG_INSN_P (tem))
13565 if (tem == BB_HEAD (bb))
13569 if (dead_or_set_p (tem, piece)
13570 || reg_bitfield_target_p (piece,
13573 add_reg_note (tem, REG_UNUSED, piece);
13587 /* Any other notes should not be present at this point in the
13589 gcc_unreachable ();
13594 XEXP (note, 1) = REG_NOTES (place);
13595 REG_NOTES (place) = note;
13599 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13603 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13604 I3, I2, and I1 to new locations. This is also called to add a link
13605 pointing at I3 when I3's destination is changed. */
13608 distribute_links (rtx links)
13610 rtx link, next_link;
13612 for (link = links; link; link = next_link)
13618 next_link = XEXP (link, 1);
13620 /* If the insn that this link points to is a NOTE or isn't a single
13621 set, ignore it. In the latter case, it isn't clear what we
13622 can do other than ignore the link, since we can't tell which
13623 register it was for. Such links wouldn't be used by combine
13626 It is not possible for the destination of the target of the link to
13627 have been changed by combine. The only potential of this is if we
13628 replace I3, I2, and I1 by I3 and I2. But in that case the
13629 destination of I2 also remains unchanged. */
13631 if (NOTE_P (XEXP (link, 0))
13632 || (set = single_set (XEXP (link, 0))) == 0)
13635 reg = SET_DEST (set);
13636 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13637 || GET_CODE (reg) == STRICT_LOW_PART)
13638 reg = XEXP (reg, 0);
13640 /* A LOG_LINK is defined as being placed on the first insn that uses
13641 a register and points to the insn that sets the register. Start
13642 searching at the next insn after the target of the link and stop
13643 when we reach a set of the register or the end of the basic block.
13645 Note that this correctly handles the link that used to point from
13646 I3 to I2. Also note that not much searching is typically done here
13647 since most links don't point very far away. */
13649 for (insn = NEXT_INSN (XEXP (link, 0));
13650 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13651 || BB_HEAD (this_basic_block->next_bb) != insn));
13652 insn = NEXT_INSN (insn))
13653 if (DEBUG_INSN_P (insn))
13655 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13657 if (reg_referenced_p (reg, PATTERN (insn)))
13661 else if (CALL_P (insn)
13662 && find_reg_fusage (insn, USE, reg))
13667 else if (INSN_P (insn) && reg_set_p (reg, insn))
13670 /* If we found a place to put the link, place it there unless there
13671 is already a link to the same insn as LINK at that point. */
13677 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13678 if (XEXP (link2, 0) == XEXP (link, 0))
13683 XEXP (link, 1) = LOG_LINKS (place);
13684 LOG_LINKS (place) = link;
13686 /* Set added_links_insn to the earliest insn we added a
13688 if (added_links_insn == 0
13689 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13690 added_links_insn = place;
13696 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13697 Check whether the expression pointer to by LOC is a register or
13698 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13699 Otherwise return zero. */
13702 unmentioned_reg_p_1 (rtx *loc, void *expr)
13707 && (REG_P (x) || MEM_P (x))
13708 && ! reg_mentioned_p (x, (rtx) expr))
13713 /* Check for any register or memory mentioned in EQUIV that is not
13714 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13715 of EXPR where some registers may have been replaced by constants. */
13718 unmentioned_reg_p (rtx equiv, rtx expr)
13720 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13724 dump_combine_stats (FILE *file)
13728 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13729 combine_attempts, combine_merges, combine_extras, combine_successes);
13733 dump_combine_total_stats (FILE *file)
13737 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13738 total_attempts, total_merges, total_extras, total_successes);
13742 gate_handle_combine (void)
13744 return (optimize > 0);
13747 /* Try combining insns through substitution. */
13748 static unsigned int
13749 rest_of_handle_combine (void)
13751 int rebuild_jump_labels_after_combine;
13753 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13754 df_note_add_problem ();
13757 regstat_init_n_sets_and_refs ();
13759 rebuild_jump_labels_after_combine
13760 = combine_instructions (get_insns (), max_reg_num ());
13762 /* Combining insns may have turned an indirect jump into a
13763 direct jump. Rebuild the JUMP_LABEL fields of jumping
13765 if (rebuild_jump_labels_after_combine)
13767 timevar_push (TV_JUMP);
13768 rebuild_jump_labels (get_insns ());
13770 timevar_pop (TV_JUMP);
13773 regstat_free_n_sets_and_refs ();
13777 struct rtl_opt_pass pass_combine =
13781 "combine", /* name */
13782 gate_handle_combine, /* gate */
13783 rest_of_handle_combine, /* execute */
13786 0, /* static_pass_number */
13787 TV_COMBINE, /* tv_id */
13788 PROP_cfglayout, /* properties_required */
13789 0, /* properties_provided */
13790 0, /* properties_destroyed */
13791 0, /* todo_flags_start */
13793 TODO_df_finish | TODO_verify_rtl_sharing |
13794 TODO_ggc_collect, /* todo_flags_finish */