1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid;
129 static int max_uid_cuid;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
242 static struct reg_stat *reg_stat;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks;
290 /* The following array records the insn_rtx_cost for every insn
291 in the instruction stream. */
293 static int *uid_insn_cost;
295 /* Length of the currently allocated uid_insn_cost array. */
297 static int last_insn_cost;
299 /* Incremented for each label. */
301 static int label_tick;
303 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
304 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
306 static enum machine_mode nonzero_bits_mode;
308 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
309 be safely used. It is zero while computing them and after combine has
310 completed. This former test prevents propagating values based on
311 previously set values, which can be incorrect if a variable is modified
314 static int nonzero_sign_valid;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
325 union {rtx r; int i;} old_contents;
326 union {rtx *r; int *i;} where;
329 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
330 num_undo says how many are currently recorded.
332 other_insn is nonzero if we have modified some other insn in the process
333 of working on subst_insn. It must be verified too. */
342 static struct undobuf undobuf;
344 /* Number of times the pseudo being substituted for
345 was found and replaced. */
347 static int n_occurrences;
349 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
351 unsigned HOST_WIDE_INT,
352 unsigned HOST_WIDE_INT *);
353 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
355 unsigned int, unsigned int *);
356 static void do_SUBST (rtx *, rtx);
357 static void do_SUBST_INT (int *, int);
358 static void init_reg_last (void);
359 static void setup_incoming_promotions (void);
360 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
361 static int cant_combine_insn_p (rtx);
362 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
363 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
364 static int contains_muldiv (rtx);
365 static rtx try_combine (rtx, rtx, rtx, int *);
366 static void undo_all (void);
367 static void undo_commit (void);
368 static rtx *find_split_point (rtx *, rtx);
369 static rtx subst (rtx, rtx, rtx, int, int);
370 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
371 static rtx simplify_if_then_else (rtx);
372 static rtx simplify_set (rtx);
373 static rtx simplify_logical (rtx);
374 static rtx expand_compound_operation (rtx);
375 static rtx expand_field_assignment (rtx);
376 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
377 rtx, unsigned HOST_WIDE_INT, int, int, int);
378 static rtx extract_left_shift (rtx, int);
379 static rtx make_compound_operation (rtx, enum rtx_code);
380 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
381 unsigned HOST_WIDE_INT *);
382 static rtx force_to_mode (rtx, enum machine_mode,
383 unsigned HOST_WIDE_INT, rtx, int);
384 static rtx if_then_else_cond (rtx, rtx *, rtx *);
385 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
386 static int rtx_equal_for_field_assignment_p (rtx, rtx);
387 static rtx make_field_assignment (rtx);
388 static rtx apply_distributive_law (rtx);
389 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
390 unsigned HOST_WIDE_INT);
391 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
392 HOST_WIDE_INT, enum machine_mode, int *);
393 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
395 static int recog_for_combine (rtx *, rtx, rtx *);
396 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
397 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
398 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
399 static void update_table_tick (rtx);
400 static void record_value_for_reg (rtx, rtx, rtx);
401 static void check_promoted_subreg (rtx, rtx);
402 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
403 static void record_dead_and_set_regs (rtx);
404 static int get_last_value_validate (rtx *, rtx, int, int);
405 static rtx get_last_value (rtx);
406 static int use_crosses_set_p (rtx, int);
407 static void reg_dead_at_p_1 (rtx, rtx, void *);
408 static int reg_dead_at_p (rtx, rtx);
409 static void move_deaths (rtx, rtx, int, rtx, rtx *);
410 static int reg_bitfield_target_p (rtx, rtx);
411 static void distribute_notes (rtx, rtx, rtx, rtx);
412 static void distribute_links (rtx);
413 static void mark_used_regs_combine (rtx);
414 static int insn_cuid (rtx);
415 static void record_promoted_value (rtx, rtx);
416 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
417 static enum rtx_code combine_reversed_comparison_code (rtx);
418 static int unmentioned_reg_p_1 (rtx *, void *);
419 static bool unmentioned_reg_p (rtx, rtx);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
428 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
430 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
431 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
433 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (rtx *into, rtx newval)
448 if (oldval == newval)
451 /* We'd like to catch as many invalid transformations here as
452 possible. Unfortunately, there are way too many mode changes
453 that are perfectly valid, so we'd waste too much effort for
454 little gain doing the checks here. Focus on catching invalid
455 transformations involving integer constants. */
456 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
457 && GET_CODE (newval) == CONST_INT)
459 /* Sanity check that we're replacing oldval with a CONST_INT
460 that is a valid sign-extension for the original mode. */
461 gcc_assert (INTVAL (newval)
462 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
464 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
465 CONST_INT is not valid, because after the replacement, the
466 original mode would be gone. Unfortunately, we can't tell
467 when do_SUBST is called to replace the operand thereof, so we
468 perform this test on oldval instead, checking whether an
469 invalid replacement took place before we got here. */
470 gcc_assert (!(GET_CODE (oldval) == SUBREG
471 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
472 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
473 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
477 buf = undobuf.frees, undobuf.frees = buf->next;
479 buf = xmalloc (sizeof (struct undo));
483 buf->old_contents.r = oldval;
486 buf->next = undobuf.undos, undobuf.undos = buf;
489 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
491 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
492 for the value of a HOST_WIDE_INT value (including CONST_INT) is
496 do_SUBST_INT (int *into, int newval)
501 if (oldval == newval)
505 buf = undobuf.frees, undobuf.frees = buf->next;
507 buf = xmalloc (sizeof (struct undo));
511 buf->old_contents.i = oldval;
514 buf->next = undobuf.undos, undobuf.undos = buf;
517 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
519 /* Subroutine of try_combine. Determine whether the combine replacement
520 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
521 that the original instruction sequence I1, I2 and I3. Note that I1
522 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
523 costs of all instructions can be estimated, and the replacements are
524 more expensive than the original sequence. */
527 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
529 int i1_cost, i2_cost, i3_cost;
530 int new_i2_cost, new_i3_cost;
531 int old_cost, new_cost;
533 /* Lookup the original insn_rtx_costs. */
534 i2_cost = INSN_UID (i2) <= last_insn_cost
535 ? uid_insn_cost[INSN_UID (i2)] : 0;
536 i3_cost = INSN_UID (i3) <= last_insn_cost
537 ? uid_insn_cost[INSN_UID (i3)] : 0;
541 i1_cost = INSN_UID (i1) <= last_insn_cost
542 ? uid_insn_cost[INSN_UID (i1)] : 0;
543 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
544 ? i1_cost + i2_cost + i3_cost : 0;
548 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
552 /* Calculate the replacement insn_rtx_costs. */
553 new_i3_cost = insn_rtx_cost (newpat);
556 new_i2_cost = insn_rtx_cost (newi2pat);
557 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
558 ? new_i2_cost + new_i3_cost : 0;
562 new_cost = new_i3_cost;
566 if (undobuf.other_insn)
568 int old_other_cost, new_other_cost;
570 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
571 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
572 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
573 if (old_other_cost > 0 && new_other_cost > 0)
575 old_cost += old_other_cost;
576 new_cost += new_other_cost;
582 /* Disallow this recombination if both new_cost and old_cost are
583 greater than zero, and new_cost is greater than old cost. */
585 && new_cost > old_cost)
592 "rejecting combination of insns %d, %d and %d\n",
593 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
594 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
595 i1_cost, i2_cost, i3_cost, old_cost);
600 "rejecting combination of insns %d and %d\n",
601 INSN_UID (i2), INSN_UID (i3));
602 fprintf (dump_file, "original costs %d + %d = %d\n",
603 i2_cost, i3_cost, old_cost);
608 fprintf (dump_file, "replacement costs %d + %d = %d\n",
609 new_i2_cost, new_i3_cost, new_cost);
612 fprintf (dump_file, "replacement cost %d\n", new_cost);
618 /* Update the uid_insn_cost array with the replacement costs. */
619 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
620 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
622 uid_insn_cost[INSN_UID (i1)] = 0;
627 /* Main entry point for combiner. F is the first insn of the function.
628 NREGS is the first unused pseudo-reg number.
630 Return nonzero if the combiner has turned an indirect jump
631 instruction into a direct jump. */
633 combine_instructions (rtx f, unsigned int nregs)
640 rtx links, nextlinks;
642 int new_direct_jump_p = 0;
644 combine_attempts = 0;
647 combine_successes = 0;
649 combine_max_regno = nregs;
651 rtl_hooks = combine_rtl_hooks;
653 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
655 init_recog_no_volatile ();
657 /* Compute maximum uid value so uid_cuid can be allocated. */
659 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
660 if (INSN_UID (insn) > i)
663 uid_cuid = xmalloc ((i + 1) * sizeof (int));
666 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
668 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
669 problems when, for example, we have j <<= 1 in a loop. */
671 nonzero_sign_valid = 0;
673 /* Compute the mapping from uids to cuids.
674 Cuids are numbers assigned to insns, like uids,
675 except that cuids increase monotonically through the code.
677 Scan all SETs and see if we can deduce anything about what
678 bits are known to be zero for some registers and how many copies
679 of the sign bit are known to exist for those registers.
681 Also set any known values so that we can use it while searching
682 for what bits are known to be set. */
686 setup_incoming_promotions ();
688 refresh_blocks = sbitmap_alloc (last_basic_block);
689 sbitmap_zero (refresh_blocks);
691 /* Allocate array of current insn_rtx_costs. */
692 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
693 last_insn_cost = max_uid_cuid;
695 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
697 uid_cuid[INSN_UID (insn)] = ++i;
703 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
705 record_dead_and_set_regs (insn);
708 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
709 if (REG_NOTE_KIND (links) == REG_INC)
710 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
714 /* Record the current insn_rtx_cost of this instruction. */
715 if (NONJUMP_INSN_P (insn))
716 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
718 fprintf(dump_file, "insn_cost %d: %d\n",
719 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
726 nonzero_sign_valid = 1;
728 /* Now scan all the insns in forward order. */
734 setup_incoming_promotions ();
736 FOR_EACH_BB (this_basic_block)
738 for (insn = BB_HEAD (this_basic_block);
739 insn != NEXT_INSN (BB_END (this_basic_block));
740 insn = next ? next : NEXT_INSN (insn))
747 else if (INSN_P (insn))
749 /* See if we know about function return values before this
750 insn based upon SUBREG flags. */
751 check_promoted_subreg (insn, PATTERN (insn));
753 /* Try this insn with each insn it links back to. */
755 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
756 if ((next = try_combine (insn, XEXP (links, 0),
757 NULL_RTX, &new_direct_jump_p)) != 0)
760 /* Try each sequence of three linked insns ending with this one. */
762 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
764 rtx link = XEXP (links, 0);
766 /* If the linked insn has been replaced by a note, then there
767 is no point in pursuing this chain any further. */
771 for (nextlinks = LOG_LINKS (link);
773 nextlinks = XEXP (nextlinks, 1))
774 if ((next = try_combine (insn, link,
776 &new_direct_jump_p)) != 0)
781 /* Try to combine a jump insn that uses CC0
782 with a preceding insn that sets CC0, and maybe with its
783 logical predecessor as well.
784 This is how we make decrement-and-branch insns.
785 We need this special code because data flow connections
786 via CC0 do not get entered in LOG_LINKS. */
789 && (prev = prev_nonnote_insn (insn)) != 0
790 && NONJUMP_INSN_P (prev)
791 && sets_cc0_p (PATTERN (prev)))
793 if ((next = try_combine (insn, prev,
794 NULL_RTX, &new_direct_jump_p)) != 0)
797 for (nextlinks = LOG_LINKS (prev); nextlinks;
798 nextlinks = XEXP (nextlinks, 1))
799 if ((next = try_combine (insn, prev,
801 &new_direct_jump_p)) != 0)
805 /* Do the same for an insn that explicitly references CC0. */
806 if (NONJUMP_INSN_P (insn)
807 && (prev = prev_nonnote_insn (insn)) != 0
808 && NONJUMP_INSN_P (prev)
809 && sets_cc0_p (PATTERN (prev))
810 && GET_CODE (PATTERN (insn)) == SET
811 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
813 if ((next = try_combine (insn, prev,
814 NULL_RTX, &new_direct_jump_p)) != 0)
817 for (nextlinks = LOG_LINKS (prev); nextlinks;
818 nextlinks = XEXP (nextlinks, 1))
819 if ((next = try_combine (insn, prev,
821 &new_direct_jump_p)) != 0)
825 /* Finally, see if any of the insns that this insn links to
826 explicitly references CC0. If so, try this insn, that insn,
827 and its predecessor if it sets CC0. */
828 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
829 if (NONJUMP_INSN_P (XEXP (links, 0))
830 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
831 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
832 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
833 && NONJUMP_INSN_P (prev)
834 && sets_cc0_p (PATTERN (prev))
835 && (next = try_combine (insn, XEXP (links, 0),
836 prev, &new_direct_jump_p)) != 0)
840 /* Try combining an insn with two different insns whose results it
842 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
843 for (nextlinks = XEXP (links, 1); nextlinks;
844 nextlinks = XEXP (nextlinks, 1))
845 if ((next = try_combine (insn, XEXP (links, 0),
847 &new_direct_jump_p)) != 0)
850 /* Try this insn with each REG_EQUAL note it links back to. */
851 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
854 rtx temp = XEXP (links, 0);
855 if ((set = single_set (temp)) != 0
856 && (note = find_reg_equal_equiv_note (temp)) != 0
857 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
858 /* Avoid using a register that may already been marked
859 dead by an earlier instruction. */
860 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
862 /* Temporarily replace the set's source with the
863 contents of the REG_EQUAL note. The insn will
864 be deleted or recognized by try_combine. */
865 rtx orig = SET_SRC (set);
866 SET_SRC (set) = XEXP (note, 0);
867 next = try_combine (insn, temp, NULL_RTX,
871 SET_SRC (set) = orig;
876 record_dead_and_set_regs (insn);
885 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
886 BASIC_BLOCK (i)->flags |= BB_DIRTY);
887 new_direct_jump_p |= purge_all_dead_edges (0);
888 delete_noop_moves ();
890 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
891 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
892 | PROP_KILL_DEAD_CODE);
895 sbitmap_free (refresh_blocks);
896 free (uid_insn_cost);
901 struct undo *undo, *next;
902 for (undo = undobuf.frees; undo; undo = next)
910 total_attempts += combine_attempts;
911 total_merges += combine_merges;
912 total_extras += combine_extras;
913 total_successes += combine_successes;
915 nonzero_sign_valid = 0;
916 rtl_hooks = general_rtl_hooks;
918 /* Make recognizer allow volatile MEMs again. */
921 return new_direct_jump_p;
924 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
930 for (i = 0; i < combine_max_regno; i++)
931 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
934 /* Set up any promoted values for incoming argument registers. */
937 setup_incoming_promotions (void)
941 enum machine_mode mode;
943 rtx first = get_insns ();
945 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
947 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
948 /* Check whether this register can hold an incoming pointer
949 argument. FUNCTION_ARG_REGNO_P tests outgoing register
950 numbers, so translate if necessary due to register windows. */
951 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
952 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
955 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
958 gen_rtx_CLOBBER (mode, const0_rtx)));
963 /* Called via note_stores. If X is a pseudo that is narrower than
964 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
966 If we are setting only a portion of X and we can't figure out what
967 portion, assume all bits will be used since we don't know what will
970 Similarly, set how many bits of X are known to be copies of the sign bit
971 at all locations in the function. This is the smallest number implied
975 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
976 void *data ATTRIBUTE_UNUSED)
981 && REGNO (x) >= FIRST_PSEUDO_REGISTER
982 /* If this register is undefined at the start of the file, we can't
983 say what its contents were. */
984 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
985 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
987 if (set == 0 || GET_CODE (set) == CLOBBER)
989 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
990 reg_stat[REGNO (x)].sign_bit_copies = 1;
994 /* If this is a complex assignment, see if we can convert it into a
995 simple assignment. */
996 set = expand_field_assignment (set);
998 /* If this is a simple assignment, or we have a paradoxical SUBREG,
999 set what we know about X. */
1001 if (SET_DEST (set) == x
1002 || (GET_CODE (SET_DEST (set)) == SUBREG
1003 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1004 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1005 && SUBREG_REG (SET_DEST (set)) == x))
1007 rtx src = SET_SRC (set);
1009 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1010 /* If X is narrower than a word and SRC is a non-negative
1011 constant that would appear negative in the mode of X,
1012 sign-extend it for use in reg_stat[].nonzero_bits because some
1013 machines (maybe most) will actually do the sign-extension
1014 and this is the conservative approach.
1016 ??? For 2.5, try to tighten up the MD files in this regard
1017 instead of this kludge. */
1019 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1020 && GET_CODE (src) == CONST_INT
1022 && 0 != (INTVAL (src)
1023 & ((HOST_WIDE_INT) 1
1024 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1025 src = GEN_INT (INTVAL (src)
1026 | ((HOST_WIDE_INT) (-1)
1027 << GET_MODE_BITSIZE (GET_MODE (x))));
1030 /* Don't call nonzero_bits if it cannot change anything. */
1031 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1032 reg_stat[REGNO (x)].nonzero_bits
1033 |= nonzero_bits (src, nonzero_bits_mode);
1034 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1035 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1036 || reg_stat[REGNO (x)].sign_bit_copies > num)
1037 reg_stat[REGNO (x)].sign_bit_copies = num;
1041 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1042 reg_stat[REGNO (x)].sign_bit_copies = 1;
1047 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1048 insns that were previously combined into I3 or that will be combined
1049 into the merger of INSN and I3.
1051 Return 0 if the combination is not allowed for any reason.
1053 If the combination is allowed, *PDEST will be set to the single
1054 destination of INSN and *PSRC to the single source, and this function
1058 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1059 rtx *pdest, rtx *psrc)
1062 rtx set = 0, src, dest;
1067 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1068 && next_active_insn (succ) == i3)
1069 : next_active_insn (insn) == i3);
1071 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1072 or a PARALLEL consisting of such a SET and CLOBBERs.
1074 If INSN has CLOBBER parallel parts, ignore them for our processing.
1075 By definition, these happen during the execution of the insn. When it
1076 is merged with another insn, all bets are off. If they are, in fact,
1077 needed and aren't also supplied in I3, they may be added by
1078 recog_for_combine. Otherwise, it won't match.
1080 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1083 Get the source and destination of INSN. If more than one, can't
1086 if (GET_CODE (PATTERN (insn)) == SET)
1087 set = PATTERN (insn);
1088 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1089 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1091 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1093 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1096 switch (GET_CODE (elt))
1098 /* This is important to combine floating point insns
1099 for the SH4 port. */
1101 /* Combining an isolated USE doesn't make sense.
1102 We depend here on combinable_i3pat to reject them. */
1103 /* The code below this loop only verifies that the inputs of
1104 the SET in INSN do not change. We call reg_set_between_p
1105 to verify that the REG in the USE does not change between
1107 If the USE in INSN was for a pseudo register, the matching
1108 insn pattern will likely match any register; combining this
1109 with any other USE would only be safe if we knew that the
1110 used registers have identical values, or if there was
1111 something to tell them apart, e.g. different modes. For
1112 now, we forgo such complicated tests and simply disallow
1113 combining of USES of pseudo registers with any other USE. */
1114 if (REG_P (XEXP (elt, 0))
1115 && GET_CODE (PATTERN (i3)) == PARALLEL)
1117 rtx i3pat = PATTERN (i3);
1118 int i = XVECLEN (i3pat, 0) - 1;
1119 unsigned int regno = REGNO (XEXP (elt, 0));
1123 rtx i3elt = XVECEXP (i3pat, 0, i);
1125 if (GET_CODE (i3elt) == USE
1126 && REG_P (XEXP (i3elt, 0))
1127 && (REGNO (XEXP (i3elt, 0)) == regno
1128 ? reg_set_between_p (XEXP (elt, 0),
1129 PREV_INSN (insn), i3)
1130 : regno >= FIRST_PSEUDO_REGISTER))
1137 /* We can ignore CLOBBERs. */
1142 /* Ignore SETs whose result isn't used but not those that
1143 have side-effects. */
1144 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1145 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1146 || INTVAL (XEXP (note, 0)) <= 0)
1147 && ! side_effects_p (elt))
1150 /* If we have already found a SET, this is a second one and
1151 so we cannot combine with this insn. */
1159 /* Anything else means we can't combine. */
1165 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1166 so don't do anything with it. */
1167 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1176 set = expand_field_assignment (set);
1177 src = SET_SRC (set), dest = SET_DEST (set);
1179 /* Don't eliminate a store in the stack pointer. */
1180 if (dest == stack_pointer_rtx
1181 /* Don't combine with an insn that sets a register to itself if it has
1182 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1183 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1184 /* Can't merge an ASM_OPERANDS. */
1185 || GET_CODE (src) == ASM_OPERANDS
1186 /* Can't merge a function call. */
1187 || GET_CODE (src) == CALL
1188 /* Don't eliminate a function call argument. */
1190 && (find_reg_fusage (i3, USE, dest)
1192 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1193 && global_regs[REGNO (dest)])))
1194 /* Don't substitute into an incremented register. */
1195 || FIND_REG_INC_NOTE (i3, dest)
1196 || (succ && FIND_REG_INC_NOTE (succ, dest))
1197 /* Don't substitute into a non-local goto, this confuses CFG. */
1198 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1200 /* Don't combine the end of a libcall into anything. */
1201 /* ??? This gives worse code, and appears to be unnecessary, since no
1202 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1203 use REG_RETVAL notes for noconflict blocks, but other code here
1204 makes sure that those insns don't disappear. */
1205 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1207 /* Make sure that DEST is not used after SUCC but before I3. */
1208 || (succ && ! all_adjacent
1209 && reg_used_between_p (dest, succ, i3))
1210 /* Make sure that the value that is to be substituted for the register
1211 does not use any registers whose values alter in between. However,
1212 If the insns are adjacent, a use can't cross a set even though we
1213 think it might (this can happen for a sequence of insns each setting
1214 the same destination; last_set of that register might point to
1215 a NOTE). If INSN has a REG_EQUIV note, the register is always
1216 equivalent to the memory so the substitution is valid even if there
1217 are intervening stores. Also, don't move a volatile asm or
1218 UNSPEC_VOLATILE across any other insns. */
1221 || ! find_reg_note (insn, REG_EQUIV, src))
1222 && use_crosses_set_p (src, INSN_CUID (insn)))
1223 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1224 || GET_CODE (src) == UNSPEC_VOLATILE))
1225 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1226 better register allocation by not doing the combine. */
1227 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1228 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1229 /* Don't combine across a CALL_INSN, because that would possibly
1230 change whether the life span of some REGs crosses calls or not,
1231 and it is a pain to update that information.
1232 Exception: if source is a constant, moving it later can't hurt.
1233 Accept that special case, because it helps -fforce-addr a lot. */
1234 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1237 /* DEST must either be a REG or CC0. */
1240 /* If register alignment is being enforced for multi-word items in all
1241 cases except for parameters, it is possible to have a register copy
1242 insn referencing a hard register that is not allowed to contain the
1243 mode being copied and which would not be valid as an operand of most
1244 insns. Eliminate this problem by not combining with such an insn.
1246 Also, on some machines we don't want to extend the life of a hard
1250 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1251 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1252 /* Don't extend the life of a hard register unless it is
1253 user variable (if we have few registers) or it can't
1254 fit into the desired register (meaning something special
1256 Also avoid substituting a return register into I3, because
1257 reload can't handle a conflict with constraints of other
1259 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1260 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1263 else if (GET_CODE (dest) != CC0)
1267 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1268 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1269 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1271 /* Don't substitute for a register intended as a clobberable
1273 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1274 if (rtx_equal_p (reg, dest))
1277 /* If the clobber represents an earlyclobber operand, we must not
1278 substitute an expression containing the clobbered register.
1279 As we do not analyze the constraint strings here, we have to
1280 make the conservative assumption. However, if the register is
1281 a fixed hard reg, the clobber cannot represent any operand;
1282 we leave it up to the machine description to either accept or
1283 reject use-and-clobber patterns. */
1285 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1286 || !fixed_regs[REGNO (reg)])
1287 if (reg_overlap_mentioned_p (reg, src))
1291 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1292 or not), reject, unless nothing volatile comes between it and I3 */
1294 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1296 /* Make sure succ doesn't contain a volatile reference. */
1297 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1300 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1301 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1305 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1306 to be an explicit register variable, and was chosen for a reason. */
1308 if (GET_CODE (src) == ASM_OPERANDS
1309 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1312 /* If there are any volatile insns between INSN and I3, reject, because
1313 they might affect machine state. */
1315 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1316 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1319 /* If INSN or I2 contains an autoincrement or autodecrement,
1320 make sure that register is not used between there and I3,
1321 and not already used in I3 either.
1322 Also insist that I3 not be a jump; if it were one
1323 and the incremented register were spilled, we would lose. */
1326 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1327 if (REG_NOTE_KIND (link) == REG_INC
1329 || reg_used_between_p (XEXP (link, 0), insn, i3)
1330 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1335 /* Don't combine an insn that follows a CC0-setting insn.
1336 An insn that uses CC0 must not be separated from the one that sets it.
1337 We do, however, allow I2 to follow a CC0-setting insn if that insn
1338 is passed as I1; in that case it will be deleted also.
1339 We also allow combining in this case if all the insns are adjacent
1340 because that would leave the two CC0 insns adjacent as well.
1341 It would be more logical to test whether CC0 occurs inside I1 or I2,
1342 but that would be much slower, and this ought to be equivalent. */
1344 p = prev_nonnote_insn (insn);
1345 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1350 /* If we get here, we have passed all the tests and the combination is
1359 /* LOC is the location within I3 that contains its pattern or the component
1360 of a PARALLEL of the pattern. We validate that it is valid for combining.
1362 One problem is if I3 modifies its output, as opposed to replacing it
1363 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1364 so would produce an insn that is not equivalent to the original insns.
1368 (set (reg:DI 101) (reg:DI 100))
1369 (set (subreg:SI (reg:DI 101) 0) <foo>)
1371 This is NOT equivalent to:
1373 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1374 (set (reg:DI 101) (reg:DI 100))])
1376 Not only does this modify 100 (in which case it might still be valid
1377 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1379 We can also run into a problem if I2 sets a register that I1
1380 uses and I1 gets directly substituted into I3 (not via I2). In that
1381 case, we would be getting the wrong value of I2DEST into I3, so we
1382 must reject the combination. This case occurs when I2 and I1 both
1383 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1384 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1385 of a SET must prevent combination from occurring.
1387 Before doing the above check, we first try to expand a field assignment
1388 into a set of logical operations.
1390 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1391 we place a register that is both set and used within I3. If more than one
1392 such register is detected, we fail.
1394 Return 1 if the combination is valid, zero otherwise. */
1397 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1398 int i1_not_in_src, rtx *pi3dest_killed)
1402 if (GET_CODE (x) == SET)
1405 rtx dest = SET_DEST (set);
1406 rtx src = SET_SRC (set);
1407 rtx inner_dest = dest;
1409 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1410 || GET_CODE (inner_dest) == SUBREG
1411 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1412 inner_dest = XEXP (inner_dest, 0);
1414 /* Check for the case where I3 modifies its output, as discussed
1415 above. We don't want to prevent pseudos from being combined
1416 into the address of a MEM, so only prevent the combination if
1417 i1 or i2 set the same MEM. */
1418 if ((inner_dest != dest &&
1419 (!MEM_P (inner_dest)
1420 || rtx_equal_p (i2dest, inner_dest)
1421 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1422 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1423 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1425 /* This is the same test done in can_combine_p except we can't test
1426 all_adjacent; we don't have to, since this instruction will stay
1427 in place, thus we are not considering increasing the lifetime of
1430 Also, if this insn sets a function argument, combining it with
1431 something that might need a spill could clobber a previous
1432 function argument; the all_adjacent test in can_combine_p also
1433 checks this; here, we do a more specific test for this case. */
1435 || (REG_P (inner_dest)
1436 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1437 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1438 GET_MODE (inner_dest))))
1439 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1442 /* If DEST is used in I3, it is being killed in this insn,
1443 so record that for later.
1444 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1445 STACK_POINTER_REGNUM, since these are always considered to be
1446 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1447 if (pi3dest_killed && REG_P (dest)
1448 && reg_referenced_p (dest, PATTERN (i3))
1449 && REGNO (dest) != FRAME_POINTER_REGNUM
1450 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1451 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1453 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1454 && (REGNO (dest) != ARG_POINTER_REGNUM
1455 || ! fixed_regs [REGNO (dest)])
1457 && REGNO (dest) != STACK_POINTER_REGNUM)
1459 if (*pi3dest_killed)
1462 *pi3dest_killed = dest;
1466 else if (GET_CODE (x) == PARALLEL)
1470 for (i = 0; i < XVECLEN (x, 0); i++)
1471 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1472 i1_not_in_src, pi3dest_killed))
1479 /* Return 1 if X is an arithmetic expression that contains a multiplication
1480 and division. We don't count multiplications by powers of two here. */
1483 contains_muldiv (rtx x)
1485 switch (GET_CODE (x))
1487 case MOD: case DIV: case UMOD: case UDIV:
1491 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1492 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1495 return contains_muldiv (XEXP (x, 0))
1496 || contains_muldiv (XEXP (x, 1));
1499 return contains_muldiv (XEXP (x, 0));
1505 /* Determine whether INSN can be used in a combination. Return nonzero if
1506 not. This is used in try_combine to detect early some cases where we
1507 can't perform combinations. */
1510 cant_combine_insn_p (rtx insn)
1515 /* If this isn't really an insn, we can't do anything.
1516 This can occur when flow deletes an insn that it has merged into an
1517 auto-increment address. */
1518 if (! INSN_P (insn))
1521 /* Never combine loads and stores involving hard regs that are likely
1522 to be spilled. The register allocator can usually handle such
1523 reg-reg moves by tying. If we allow the combiner to make
1524 substitutions of likely-spilled regs, we may abort in reload.
1525 As an exception, we allow combinations involving fixed regs; these are
1526 not available to the register allocator so there's no risk involved. */
1528 set = single_set (insn);
1531 src = SET_SRC (set);
1532 dest = SET_DEST (set);
1533 if (GET_CODE (src) == SUBREG)
1534 src = SUBREG_REG (src);
1535 if (GET_CODE (dest) == SUBREG)
1536 dest = SUBREG_REG (dest);
1537 if (REG_P (src) && REG_P (dest)
1538 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1539 && ! fixed_regs[REGNO (src)]
1540 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1541 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1542 && ! fixed_regs[REGNO (dest)]
1543 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1549 /* Adjust INSN after we made a change to its destination.
1551 Changing the destination can invalidate notes that say something about
1552 the results of the insn and a LOG_LINK pointing to the insn. */
1555 adjust_for_new_dest (rtx insn)
1559 /* For notes, be conservative and simply remove them. */
1560 loc = ®_NOTES (insn);
1563 enum reg_note kind = REG_NOTE_KIND (*loc);
1564 if (kind == REG_EQUAL || kind == REG_EQUIV)
1565 *loc = XEXP (*loc, 1);
1567 loc = &XEXP (*loc, 1);
1570 /* The new insn will have a destination that was previously the destination
1571 of an insn just above it. Call distribute_links to make a LOG_LINK from
1572 the next use of that destination. */
1573 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1576 /* Try to combine the insns I1 and I2 into I3.
1577 Here I1 and I2 appear earlier than I3.
1578 I1 can be zero; then we combine just I2 into I3.
1580 If we are combining three insns and the resulting insn is not recognized,
1581 try splitting it into two insns. If that happens, I2 and I3 are retained
1582 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1585 Return 0 if the combination does not work. Then nothing is changed.
1586 If we did the combination, return the insn at which combine should
1589 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1590 new direct jump instruction. */
1593 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1595 /* New patterns for I3 and I2, respectively. */
1596 rtx newpat, newi2pat = 0;
1597 int substed_i2 = 0, substed_i1 = 0;
1598 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1599 int added_sets_1, added_sets_2;
1600 /* Total number of SETs to put into I3. */
1602 /* Nonzero if I2's body now appears in I3. */
1604 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1605 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1606 /* Contains I3 if the destination of I3 is used in its source, which means
1607 that the old life of I3 is being killed. If that usage is placed into
1608 I2 and not in I3, a REG_DEAD note must be made. */
1609 rtx i3dest_killed = 0;
1610 /* SET_DEST and SET_SRC of I2 and I1. */
1611 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1612 /* PATTERN (I2), or a copy of it in certain cases. */
1614 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1615 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1616 int i1_feeds_i3 = 0;
1617 /* Notes that must be added to REG_NOTES in I3 and I2. */
1618 rtx new_i3_notes, new_i2_notes;
1619 /* Notes that we substituted I3 into I2 instead of the normal case. */
1620 int i3_subst_into_i2 = 0;
1621 /* Notes that I1, I2 or I3 is a MULT operation. */
1630 /* Exit early if one of the insns involved can't be used for
1632 if (cant_combine_insn_p (i3)
1633 || cant_combine_insn_p (i2)
1634 || (i1 && cant_combine_insn_p (i1))
1635 /* We also can't do anything if I3 has a
1636 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1639 /* ??? This gives worse code, and appears to be unnecessary, since no
1640 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1641 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1647 undobuf.other_insn = 0;
1649 /* Reset the hard register usage information. */
1650 CLEAR_HARD_REG_SET (newpat_used_regs);
1652 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1653 code below, set I1 to be the earlier of the two insns. */
1654 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1655 temp = i1, i1 = i2, i2 = temp;
1657 added_links_insn = 0;
1659 /* First check for one important special-case that the code below will
1660 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1661 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1662 we may be able to replace that destination with the destination of I3.
1663 This occurs in the common code where we compute both a quotient and
1664 remainder into a structure, in which case we want to do the computation
1665 directly into the structure to avoid register-register copies.
1667 Note that this case handles both multiple sets in I2 and also
1668 cases where I2 has a number of CLOBBER or PARALLELs.
1670 We make very conservative checks below and only try to handle the
1671 most common cases of this. For example, we only handle the case
1672 where I2 and I3 are adjacent to avoid making difficult register
1675 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1676 && REG_P (SET_SRC (PATTERN (i3)))
1677 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1678 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1679 && GET_CODE (PATTERN (i2)) == PARALLEL
1680 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1681 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1682 below would need to check what is inside (and reg_overlap_mentioned_p
1683 doesn't support those codes anyway). Don't allow those destinations;
1684 the resulting insn isn't likely to be recognized anyway. */
1685 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1686 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1687 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1688 SET_DEST (PATTERN (i3)))
1689 && next_real_insn (i2) == i3)
1691 rtx p2 = PATTERN (i2);
1693 /* Make sure that the destination of I3,
1694 which we are going to substitute into one output of I2,
1695 is not used within another output of I2. We must avoid making this:
1696 (parallel [(set (mem (reg 69)) ...)
1697 (set (reg 69) ...)])
1698 which is not well-defined as to order of actions.
1699 (Besides, reload can't handle output reloads for this.)
1701 The problem can also happen if the dest of I3 is a memory ref,
1702 if another dest in I2 is an indirect memory ref. */
1703 for (i = 0; i < XVECLEN (p2, 0); i++)
1704 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1705 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1706 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1707 SET_DEST (XVECEXP (p2, 0, i))))
1710 if (i == XVECLEN (p2, 0))
1711 for (i = 0; i < XVECLEN (p2, 0); i++)
1712 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1713 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1714 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1719 subst_low_cuid = INSN_CUID (i2);
1721 added_sets_2 = added_sets_1 = 0;
1722 i2dest = SET_SRC (PATTERN (i3));
1724 /* Replace the dest in I2 with our dest and make the resulting
1725 insn the new pattern for I3. Then skip to where we
1726 validate the pattern. Everything was set up above. */
1727 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1728 SET_DEST (PATTERN (i3)));
1731 i3_subst_into_i2 = 1;
1732 goto validate_replacement;
1736 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1737 one of those words to another constant, merge them by making a new
1740 && (temp = single_set (i2)) != 0
1741 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1742 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1743 && REG_P (SET_DEST (temp))
1744 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1745 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1746 && GET_CODE (PATTERN (i3)) == SET
1747 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1748 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1749 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1750 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1751 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1753 HOST_WIDE_INT lo, hi;
1755 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1756 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1759 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1760 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1763 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1765 /* We don't handle the case of the target word being wider
1766 than a host wide int. */
1767 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1769 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1770 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1771 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1773 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1774 hi = INTVAL (SET_SRC (PATTERN (i3)));
1775 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1777 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1778 >> (HOST_BITS_PER_WIDE_INT - 1));
1780 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1781 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1782 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1783 (INTVAL (SET_SRC (PATTERN (i3)))));
1785 hi = lo < 0 ? -1 : 0;
1788 /* We don't handle the case of the higher word not fitting
1789 entirely in either hi or lo. */
1794 subst_low_cuid = INSN_CUID (i2);
1795 added_sets_2 = added_sets_1 = 0;
1796 i2dest = SET_DEST (temp);
1798 SUBST (SET_SRC (temp),
1799 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1801 newpat = PATTERN (i2);
1802 goto validate_replacement;
1806 /* If we have no I1 and I2 looks like:
1807 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1809 make up a dummy I1 that is
1812 (set (reg:CC X) (compare:CC Y (const_int 0)))
1814 (We can ignore any trailing CLOBBERs.)
1816 This undoes a previous combination and allows us to match a branch-and-
1819 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1820 && XVECLEN (PATTERN (i2), 0) >= 2
1821 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1822 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1824 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1825 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1826 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1827 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1828 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1829 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1831 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1832 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1837 /* We make I1 with the same INSN_UID as I2. This gives it
1838 the same INSN_CUID for value tracking. Our fake I1 will
1839 never appear in the insn stream so giving it the same INSN_UID
1840 as I2 will not cause a problem. */
1842 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1843 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1844 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1847 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1848 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1849 SET_DEST (PATTERN (i1)));
1854 /* Verify that I2 and I1 are valid for combining. */
1855 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1856 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1862 /* Record whether I2DEST is used in I2SRC and similarly for the other
1863 cases. Knowing this will help in register status updating below. */
1864 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1865 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1866 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1868 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1870 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1872 /* Ensure that I3's pattern can be the destination of combines. */
1873 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1874 i1 && i2dest_in_i1src && i1_feeds_i3,
1881 /* See if any of the insns is a MULT operation. Unless one is, we will
1882 reject a combination that is, since it must be slower. Be conservative
1884 if (GET_CODE (i2src) == MULT
1885 || (i1 != 0 && GET_CODE (i1src) == MULT)
1886 || (GET_CODE (PATTERN (i3)) == SET
1887 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1890 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1891 We used to do this EXCEPT in one case: I3 has a post-inc in an
1892 output operand. However, that exception can give rise to insns like
1894 which is a famous insn on the PDP-11 where the value of r3 used as the
1895 source was model-dependent. Avoid this sort of thing. */
1898 if (!(GET_CODE (PATTERN (i3)) == SET
1899 && REG_P (SET_SRC (PATTERN (i3)))
1900 && MEM_P (SET_DEST (PATTERN (i3)))
1901 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1902 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1903 /* It's not the exception. */
1906 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1907 if (REG_NOTE_KIND (link) == REG_INC
1908 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1910 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1917 /* See if the SETs in I1 or I2 need to be kept around in the merged
1918 instruction: whenever the value set there is still needed past I3.
1919 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1921 For the SET in I1, we have two cases: If I1 and I2 independently
1922 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1923 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1924 in I1 needs to be kept around unless I1DEST dies or is set in either
1925 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1926 I1DEST. If so, we know I1 feeds into I2. */
1928 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1931 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1932 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1934 /* If the set in I2 needs to be kept around, we must make a copy of
1935 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1936 PATTERN (I2), we are only substituting for the original I1DEST, not into
1937 an already-substituted copy. This also prevents making self-referential
1938 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1941 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1942 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1946 i2pat = copy_rtx (i2pat);
1950 /* Substitute in the latest insn for the regs set by the earlier ones. */
1952 maxreg = max_reg_num ();
1956 /* It is possible that the source of I2 or I1 may be performing an
1957 unneeded operation, such as a ZERO_EXTEND of something that is known
1958 to have the high part zero. Handle that case by letting subst look at
1959 the innermost one of them.
1961 Another way to do this would be to have a function that tries to
1962 simplify a single insn instead of merging two or more insns. We don't
1963 do this because of the potential of infinite loops and because
1964 of the potential extra memory required. However, doing it the way
1965 we are is a bit of a kludge and doesn't catch all cases.
1967 But only do this if -fexpensive-optimizations since it slows things down
1968 and doesn't usually win. */
1970 if (flag_expensive_optimizations)
1972 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1975 subst_low_cuid = INSN_CUID (i1);
1976 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1980 subst_low_cuid = INSN_CUID (i2);
1981 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1986 /* Many machines that don't use CC0 have insns that can both perform an
1987 arithmetic operation and set the condition code. These operations will
1988 be represented as a PARALLEL with the first element of the vector
1989 being a COMPARE of an arithmetic operation with the constant zero.
1990 The second element of the vector will set some pseudo to the result
1991 of the same arithmetic operation. If we simplify the COMPARE, we won't
1992 match such a pattern and so will generate an extra insn. Here we test
1993 for this case, where both the comparison and the operation result are
1994 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1995 I2SRC. Later we will make the PARALLEL that contains I2. */
1997 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1998 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1999 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2000 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2002 #ifdef SELECT_CC_MODE
2004 enum machine_mode compare_mode;
2007 newpat = PATTERN (i3);
2008 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2012 #ifdef SELECT_CC_MODE
2013 /* See if a COMPARE with the operand we substituted in should be done
2014 with the mode that is currently being used. If not, do the same
2015 processing we do in `subst' for a SET; namely, if the destination
2016 is used only once, try to replace it with a register of the proper
2017 mode and also replace the COMPARE. */
2018 if (undobuf.other_insn == 0
2019 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2020 &undobuf.other_insn))
2021 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2023 != GET_MODE (SET_DEST (newpat))))
2025 unsigned int regno = REGNO (SET_DEST (newpat));
2026 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2028 if (regno < FIRST_PSEUDO_REGISTER
2029 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2030 && ! REG_USERVAR_P (SET_DEST (newpat))))
2032 if (regno >= FIRST_PSEUDO_REGISTER)
2033 SUBST (regno_reg_rtx[regno], new_dest);
2035 SUBST (SET_DEST (newpat), new_dest);
2036 SUBST (XEXP (*cc_use, 0), new_dest);
2037 SUBST (SET_SRC (newpat),
2038 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2041 undobuf.other_insn = 0;
2048 n_occurrences = 0; /* `subst' counts here */
2050 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2051 need to make a unique copy of I2SRC each time we substitute it
2052 to avoid self-referential rtl. */
2054 subst_low_cuid = INSN_CUID (i2);
2055 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2056 ! i1_feeds_i3 && i1dest_in_i1src);
2059 /* Record whether i2's body now appears within i3's body. */
2060 i2_is_used = n_occurrences;
2063 /* If we already got a failure, don't try to do more. Otherwise,
2064 try to substitute in I1 if we have it. */
2066 if (i1 && GET_CODE (newpat) != CLOBBER)
2068 /* Before we can do this substitution, we must redo the test done
2069 above (see detailed comments there) that ensures that I1DEST
2070 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2072 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2080 subst_low_cuid = INSN_CUID (i1);
2081 newpat = subst (newpat, i1dest, i1src, 0, 0);
2085 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2086 to count all the ways that I2SRC and I1SRC can be used. */
2087 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2088 && i2_is_used + added_sets_2 > 1)
2089 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2090 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2092 /* Fail if we tried to make a new register (we used to abort, but there's
2093 really no reason to). */
2094 || max_reg_num () != maxreg
2095 /* Fail if we couldn't do something and have a CLOBBER. */
2096 || GET_CODE (newpat) == CLOBBER
2097 /* Fail if this new pattern is a MULT and we didn't have one before
2098 at the outer level. */
2099 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2106 /* If the actions of the earlier insns must be kept
2107 in addition to substituting them into the latest one,
2108 we must make a new PARALLEL for the latest insn
2109 to hold additional the SETs. */
2111 if (added_sets_1 || added_sets_2)
2115 if (GET_CODE (newpat) == PARALLEL)
2117 rtvec old = XVEC (newpat, 0);
2118 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2119 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2120 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2121 sizeof (old->elem[0]) * old->num_elem);
2126 total_sets = 1 + added_sets_1 + added_sets_2;
2127 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2128 XVECEXP (newpat, 0, 0) = old;
2132 XVECEXP (newpat, 0, --total_sets)
2133 = (GET_CODE (PATTERN (i1)) == PARALLEL
2134 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2138 /* If there is no I1, use I2's body as is. We used to also not do
2139 the subst call below if I2 was substituted into I3,
2140 but that could lose a simplification. */
2142 XVECEXP (newpat, 0, --total_sets) = i2pat;
2144 /* See comment where i2pat is assigned. */
2145 XVECEXP (newpat, 0, --total_sets)
2146 = subst (i2pat, i1dest, i1src, 0, 0);
2150 /* We come here when we are replacing a destination in I2 with the
2151 destination of I3. */
2152 validate_replacement:
2154 /* Note which hard regs this insn has as inputs. */
2155 mark_used_regs_combine (newpat);
2157 /* Is the result of combination a valid instruction? */
2158 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2160 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2161 the second SET's destination is a register that is unused and isn't
2162 marked as an instruction that might trap in an EH region. In that case,
2163 we just need the first SET. This can occur when simplifying a divmod
2164 insn. We *must* test for this case here because the code below that
2165 splits two independent SETs doesn't handle this case correctly when it
2166 updates the register status.
2168 It's pointless doing this if we originally had two sets, one from
2169 i3, and one from i2. Combining then splitting the parallel results
2170 in the original i2 again plus an invalid insn (which we delete).
2171 The net effect is only to move instructions around, which makes
2172 debug info less accurate.
2174 Also check the case where the first SET's destination is unused.
2175 That would not cause incorrect code, but does cause an unneeded
2178 if (insn_code_number < 0
2179 && !(added_sets_2 && i1 == 0)
2180 && GET_CODE (newpat) == PARALLEL
2181 && XVECLEN (newpat, 0) == 2
2182 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2183 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2184 && asm_noperands (newpat) < 0)
2186 rtx set0 = XVECEXP (newpat, 0, 0);
2187 rtx set1 = XVECEXP (newpat, 0, 1);
2190 if (((REG_P (SET_DEST (set1))
2191 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2192 || (GET_CODE (SET_DEST (set1)) == SUBREG
2193 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2194 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2195 || INTVAL (XEXP (note, 0)) <= 0)
2196 && ! side_effects_p (SET_SRC (set1)))
2199 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2202 else if (((REG_P (SET_DEST (set0))
2203 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2204 || (GET_CODE (SET_DEST (set0)) == SUBREG
2205 && find_reg_note (i3, REG_UNUSED,
2206 SUBREG_REG (SET_DEST (set0)))))
2207 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2208 || INTVAL (XEXP (note, 0)) <= 0)
2209 && ! side_effects_p (SET_SRC (set0)))
2212 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2214 if (insn_code_number >= 0)
2216 /* If we will be able to accept this, we have made a
2217 change to the destination of I3. This requires us to
2218 do a few adjustments. */
2220 PATTERN (i3) = newpat;
2221 adjust_for_new_dest (i3);
2226 /* If we were combining three insns and the result is a simple SET
2227 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2228 insns. There are two ways to do this. It can be split using a
2229 machine-specific method (like when you have an addition of a large
2230 constant) or by combine in the function find_split_point. */
2232 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2233 && asm_noperands (newpat) < 0)
2235 rtx m_split, *split;
2236 rtx ni2dest = i2dest;
2238 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2239 use I2DEST as a scratch register will help. In the latter case,
2240 convert I2DEST to the mode of the source of NEWPAT if we can. */
2242 m_split = split_insns (newpat, i3);
2244 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2245 inputs of NEWPAT. */
2247 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2248 possible to try that as a scratch reg. This would require adding
2249 more code to make it work though. */
2251 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2253 /* If I2DEST is a hard register or the only use of a pseudo,
2254 we can change its mode. */
2255 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2256 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2258 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2259 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2260 && ! REG_USERVAR_P (i2dest))))
2261 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2264 m_split = split_insns (gen_rtx_PARALLEL
2266 gen_rtvec (2, newpat,
2267 gen_rtx_CLOBBER (VOIDmode,
2270 /* If the split with the mode-changed register didn't work, try
2271 the original register. */
2272 if (! m_split && ni2dest != i2dest)
2275 m_split = split_insns (gen_rtx_PARALLEL
2277 gen_rtvec (2, newpat,
2278 gen_rtx_CLOBBER (VOIDmode,
2284 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2286 m_split = PATTERN (m_split);
2287 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2288 if (insn_code_number >= 0)
2291 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2292 && (next_real_insn (i2) == i3
2293 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2296 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2297 newi2pat = PATTERN (m_split);
2299 i3set = single_set (NEXT_INSN (m_split));
2300 i2set = single_set (m_split);
2302 /* In case we changed the mode of I2DEST, replace it in the
2303 pseudo-register table here. We can't do it above in case this
2304 code doesn't get executed and we do a split the other way. */
2306 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2307 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2309 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2311 /* If I2 or I3 has multiple SETs, we won't know how to track
2312 register status, so don't use these insns. If I2's destination
2313 is used between I2 and I3, we also can't use these insns. */
2315 if (i2_code_number >= 0 && i2set && i3set
2316 && (next_real_insn (i2) == i3
2317 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2318 insn_code_number = recog_for_combine (&newi3pat, i3,
2320 if (insn_code_number >= 0)
2323 /* It is possible that both insns now set the destination of I3.
2324 If so, we must show an extra use of it. */
2326 if (insn_code_number >= 0)
2328 rtx new_i3_dest = SET_DEST (i3set);
2329 rtx new_i2_dest = SET_DEST (i2set);
2331 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2332 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2333 || GET_CODE (new_i3_dest) == SUBREG)
2334 new_i3_dest = XEXP (new_i3_dest, 0);
2336 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2337 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2338 || GET_CODE (new_i2_dest) == SUBREG)
2339 new_i2_dest = XEXP (new_i2_dest, 0);
2341 if (REG_P (new_i3_dest)
2342 && REG_P (new_i2_dest)
2343 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2344 REG_N_SETS (REGNO (new_i2_dest))++;
2348 /* If we can split it and use I2DEST, go ahead and see if that
2349 helps things be recognized. Verify that none of the registers
2350 are set between I2 and I3. */
2351 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2355 /* We need I2DEST in the proper mode. If it is a hard register
2356 or the only use of a pseudo, we can change its mode. */
2357 && (GET_MODE (*split) == GET_MODE (i2dest)
2358 || GET_MODE (*split) == VOIDmode
2359 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2360 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2361 && ! REG_USERVAR_P (i2dest)))
2362 && (next_real_insn (i2) == i3
2363 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2364 /* We can't overwrite I2DEST if its value is still used by
2366 && ! reg_referenced_p (i2dest, newpat))
2368 rtx newdest = i2dest;
2369 enum rtx_code split_code = GET_CODE (*split);
2370 enum machine_mode split_mode = GET_MODE (*split);
2372 /* Get NEWDEST as a register in the proper mode. We have already
2373 validated that we can do this. */
2374 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2376 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2378 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2379 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2382 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2383 an ASHIFT. This can occur if it was inside a PLUS and hence
2384 appeared to be a memory address. This is a kludge. */
2385 if (split_code == MULT
2386 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2387 && INTVAL (XEXP (*split, 1)) > 0
2388 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2390 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2391 XEXP (*split, 0), GEN_INT (i)));
2392 /* Update split_code because we may not have a multiply
2394 split_code = GET_CODE (*split);
2397 #ifdef INSN_SCHEDULING
2398 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2399 be written as a ZERO_EXTEND. */
2400 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2402 #ifdef LOAD_EXTEND_OP
2403 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2404 what it really is. */
2405 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2407 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2408 SUBREG_REG (*split)));
2411 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2412 SUBREG_REG (*split)));
2416 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2417 SUBST (*split, newdest);
2418 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2420 /* If the split point was a MULT and we didn't have one before,
2421 don't use one now. */
2422 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2423 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2427 /* Check for a case where we loaded from memory in a narrow mode and
2428 then sign extended it, but we need both registers. In that case,
2429 we have a PARALLEL with both loads from the same memory location.
2430 We can split this into a load from memory followed by a register-register
2431 copy. This saves at least one insn, more if register allocation can
2434 We cannot do this if the destination of the first assignment is a
2435 condition code register or cc0. We eliminate this case by making sure
2436 the SET_DEST and SET_SRC have the same mode.
2438 We cannot do this if the destination of the second assignment is
2439 a register that we have already assumed is zero-extended. Similarly
2440 for a SUBREG of such a register. */
2442 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2443 && GET_CODE (newpat) == PARALLEL
2444 && XVECLEN (newpat, 0) == 2
2445 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2446 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2447 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2448 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2449 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2450 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2451 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2452 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2454 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2455 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2456 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2458 && reg_stat[REGNO (temp)].nonzero_bits != 0
2459 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2460 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2461 && (reg_stat[REGNO (temp)].nonzero_bits
2462 != GET_MODE_MASK (word_mode))))
2463 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2464 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2466 && reg_stat[REGNO (temp)].nonzero_bits != 0
2467 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2468 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2469 && (reg_stat[REGNO (temp)].nonzero_bits
2470 != GET_MODE_MASK (word_mode)))))
2471 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2472 SET_SRC (XVECEXP (newpat, 0, 1)))
2473 && ! find_reg_note (i3, REG_UNUSED,
2474 SET_DEST (XVECEXP (newpat, 0, 0))))
2478 newi2pat = XVECEXP (newpat, 0, 0);
2479 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2480 newpat = XVECEXP (newpat, 0, 1);
2481 SUBST (SET_SRC (newpat),
2482 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2483 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2485 if (i2_code_number >= 0)
2486 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2488 if (insn_code_number >= 0)
2492 /* Similarly, check for a case where we have a PARALLEL of two independent
2493 SETs but we started with three insns. In this case, we can do the sets
2494 as two separate insns. This case occurs when some SET allows two
2495 other insns to combine, but the destination of that SET is still live. */
2497 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2498 && GET_CODE (newpat) == PARALLEL
2499 && XVECLEN (newpat, 0) == 2
2500 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2501 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2502 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2503 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2504 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2505 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2506 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2508 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2509 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2510 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2511 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2512 XVECEXP (newpat, 0, 0))
2513 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2514 XVECEXP (newpat, 0, 1))
2515 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2516 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2518 /* Normally, it doesn't matter which of the two is done first,
2519 but it does if one references cc0. In that case, it has to
2522 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2524 newi2pat = XVECEXP (newpat, 0, 0);
2525 newpat = XVECEXP (newpat, 0, 1);
2530 newi2pat = XVECEXP (newpat, 0, 1);
2531 newpat = XVECEXP (newpat, 0, 0);
2534 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2536 if (i2_code_number >= 0)
2537 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2540 /* If it still isn't recognized, fail and change things back the way they
2542 if ((insn_code_number < 0
2543 /* Is the result a reasonable ASM_OPERANDS? */
2544 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2550 /* If we had to change another insn, make sure it is valid also. */
2551 if (undobuf.other_insn)
2553 rtx other_pat = PATTERN (undobuf.other_insn);
2554 rtx new_other_notes;
2557 CLEAR_HARD_REG_SET (newpat_used_regs);
2559 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2562 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2568 PATTERN (undobuf.other_insn) = other_pat;
2570 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2571 are still valid. Then add any non-duplicate notes added by
2572 recog_for_combine. */
2573 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2575 next = XEXP (note, 1);
2577 if (REG_NOTE_KIND (note) == REG_UNUSED
2578 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2580 if (REG_P (XEXP (note, 0)))
2581 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2583 remove_note (undobuf.other_insn, note);
2587 for (note = new_other_notes; note; note = XEXP (note, 1))
2588 if (REG_P (XEXP (note, 0)))
2589 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2591 distribute_notes (new_other_notes, undobuf.other_insn,
2592 undobuf.other_insn, NULL_RTX);
2595 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2596 they are adjacent to each other or not. */
2598 rtx p = prev_nonnote_insn (i3);
2599 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2600 && sets_cc0_p (newi2pat))
2608 /* Only allow this combination if insn_rtx_costs reports that the
2609 replacement instructions are cheaper than the originals. */
2610 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2616 /* We now know that we can do this combination. Merge the insns and
2617 update the status of registers and LOG_LINKS. */
2625 /* I3 now uses what used to be its destination and which is now
2626 I2's destination. This requires us to do a few adjustments. */
2627 PATTERN (i3) = newpat;
2628 adjust_for_new_dest (i3);
2630 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2633 However, some later insn might be using I2's dest and have
2634 a LOG_LINK pointing at I3. We must remove this link.
2635 The simplest way to remove the link is to point it at I1,
2636 which we know will be a NOTE. */
2638 /* newi2pat is usually a SET here; however, recog_for_combine might
2639 have added some clobbers. */
2640 if (GET_CODE (newi2pat) == PARALLEL)
2641 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2643 ni2dest = SET_DEST (newi2pat);
2645 for (insn = NEXT_INSN (i3);
2646 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2647 || insn != BB_HEAD (this_basic_block->next_bb));
2648 insn = NEXT_INSN (insn))
2650 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2652 for (link = LOG_LINKS (insn); link;
2653 link = XEXP (link, 1))
2654 if (XEXP (link, 0) == i3)
2655 XEXP (link, 0) = i1;
2663 rtx i3notes, i2notes, i1notes = 0;
2664 rtx i3links, i2links, i1links = 0;
2668 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2670 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2671 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2673 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2675 /* Ensure that we do not have something that should not be shared but
2676 occurs multiple times in the new insns. Check this by first
2677 resetting all the `used' flags and then copying anything is shared. */
2679 reset_used_flags (i3notes);
2680 reset_used_flags (i2notes);
2681 reset_used_flags (i1notes);
2682 reset_used_flags (newpat);
2683 reset_used_flags (newi2pat);
2684 if (undobuf.other_insn)
2685 reset_used_flags (PATTERN (undobuf.other_insn));
2687 i3notes = copy_rtx_if_shared (i3notes);
2688 i2notes = copy_rtx_if_shared (i2notes);
2689 i1notes = copy_rtx_if_shared (i1notes);
2690 newpat = copy_rtx_if_shared (newpat);
2691 newi2pat = copy_rtx_if_shared (newi2pat);
2692 if (undobuf.other_insn)
2693 reset_used_flags (PATTERN (undobuf.other_insn));
2695 INSN_CODE (i3) = insn_code_number;
2696 PATTERN (i3) = newpat;
2698 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2700 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2702 reset_used_flags (call_usage);
2703 call_usage = copy_rtx (call_usage);
2706 replace_rtx (call_usage, i2dest, i2src);
2709 replace_rtx (call_usage, i1dest, i1src);
2711 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2714 if (undobuf.other_insn)
2715 INSN_CODE (undobuf.other_insn) = other_code_number;
2717 /* We had one special case above where I2 had more than one set and
2718 we replaced a destination of one of those sets with the destination
2719 of I3. In that case, we have to update LOG_LINKS of insns later
2720 in this basic block. Note that this (expensive) case is rare.
2722 Also, in this case, we must pretend that all REG_NOTEs for I2
2723 actually came from I3, so that REG_UNUSED notes from I2 will be
2724 properly handled. */
2726 if (i3_subst_into_i2)
2728 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2729 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2730 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2731 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2732 && ! find_reg_note (i2, REG_UNUSED,
2733 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2734 for (temp = NEXT_INSN (i2);
2735 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2736 || BB_HEAD (this_basic_block) != temp);
2737 temp = NEXT_INSN (temp))
2738 if (temp != i3 && INSN_P (temp))
2739 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2740 if (XEXP (link, 0) == i2)
2741 XEXP (link, 0) = i3;
2746 while (XEXP (link, 1))
2747 link = XEXP (link, 1);
2748 XEXP (link, 1) = i2notes;
2762 INSN_CODE (i2) = i2_code_number;
2763 PATTERN (i2) = newi2pat;
2766 SET_INSN_DELETED (i2);
2772 SET_INSN_DELETED (i1);
2775 /* Get death notes for everything that is now used in either I3 or
2776 I2 and used to die in a previous insn. If we built two new
2777 patterns, move from I1 to I2 then I2 to I3 so that we get the
2778 proper movement on registers that I2 modifies. */
2782 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2783 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2786 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2789 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2791 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2793 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2795 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2797 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2799 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2800 know these are REG_UNUSED and want them to go to the desired insn,
2801 so we always pass it as i3. We have not counted the notes in
2802 reg_n_deaths yet, so we need to do so now. */
2804 if (newi2pat && new_i2_notes)
2806 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2807 if (REG_P (XEXP (temp, 0)))
2808 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2810 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2815 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2816 if (REG_P (XEXP (temp, 0)))
2817 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2819 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2822 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2823 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2824 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2825 in that case, it might delete I2. Similarly for I2 and I1.
2826 Show an additional death due to the REG_DEAD note we make here. If
2827 we discard it in distribute_notes, we will decrement it again. */
2831 if (REG_P (i3dest_killed))
2832 REG_N_DEATHS (REGNO (i3dest_killed))++;
2834 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2835 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2837 NULL_RTX, i2, NULL_RTX);
2839 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2841 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2844 if (i2dest_in_i2src)
2847 REG_N_DEATHS (REGNO (i2dest))++;
2849 if (newi2pat && reg_set_p (i2dest, newi2pat))
2850 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2851 NULL_RTX, i2, NULL_RTX);
2853 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2854 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2857 if (i1dest_in_i1src)
2860 REG_N_DEATHS (REGNO (i1dest))++;
2862 if (newi2pat && reg_set_p (i1dest, newi2pat))
2863 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2864 NULL_RTX, i2, NULL_RTX);
2866 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2867 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2870 distribute_links (i3links);
2871 distribute_links (i2links);
2872 distribute_links (i1links);
2877 rtx i2_insn = 0, i2_val = 0, set;
2879 /* The insn that used to set this register doesn't exist, and
2880 this life of the register may not exist either. See if one of
2881 I3's links points to an insn that sets I2DEST. If it does,
2882 that is now the last known value for I2DEST. If we don't update
2883 this and I2 set the register to a value that depended on its old
2884 contents, we will get confused. If this insn is used, thing
2885 will be set correctly in combine_instructions. */
2887 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2888 if ((set = single_set (XEXP (link, 0))) != 0
2889 && rtx_equal_p (i2dest, SET_DEST (set)))
2890 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2892 record_value_for_reg (i2dest, i2_insn, i2_val);
2894 /* If the reg formerly set in I2 died only once and that was in I3,
2895 zero its use count so it won't make `reload' do any work. */
2897 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2898 && ! i2dest_in_i2src)
2900 regno = REGNO (i2dest);
2901 REG_N_SETS (regno)--;
2905 if (i1 && REG_P (i1dest))
2908 rtx i1_insn = 0, i1_val = 0, set;
2910 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2911 if ((set = single_set (XEXP (link, 0))) != 0
2912 && rtx_equal_p (i1dest, SET_DEST (set)))
2913 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2915 record_value_for_reg (i1dest, i1_insn, i1_val);
2917 regno = REGNO (i1dest);
2918 if (! added_sets_1 && ! i1dest_in_i1src)
2919 REG_N_SETS (regno)--;
2922 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2923 been made to this insn. The order of
2924 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2925 can affect nonzero_bits of newpat */
2927 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2928 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2930 /* Set new_direct_jump_p if a new return or simple jump instruction
2933 If I3 is now an unconditional jump, ensure that it has a
2934 BARRIER following it since it may have initially been a
2935 conditional jump. It may also be the last nonnote insn. */
2937 if (returnjump_p (i3) || any_uncondjump_p (i3))
2939 *new_direct_jump_p = 1;
2940 mark_jump_label (PATTERN (i3), i3, 0);
2942 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2943 || !BARRIER_P (temp))
2944 emit_barrier_after (i3);
2947 if (undobuf.other_insn != NULL_RTX
2948 && (returnjump_p (undobuf.other_insn)
2949 || any_uncondjump_p (undobuf.other_insn)))
2951 *new_direct_jump_p = 1;
2953 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2954 || !BARRIER_P (temp))
2955 emit_barrier_after (undobuf.other_insn);
2958 /* An NOOP jump does not need barrier, but it does need cleaning up
2960 if (GET_CODE (newpat) == SET
2961 && SET_SRC (newpat) == pc_rtx
2962 && SET_DEST (newpat) == pc_rtx)
2963 *new_direct_jump_p = 1;
2966 combine_successes++;
2969 if (added_links_insn
2970 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2971 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2972 return added_links_insn;
2974 return newi2pat ? i2 : i3;
2977 /* Undo all the modifications recorded in undobuf. */
2982 struct undo *undo, *next;
2984 for (undo = undobuf.undos; undo; undo = next)
2988 *undo->where.i = undo->old_contents.i;
2990 *undo->where.r = undo->old_contents.r;
2992 undo->next = undobuf.frees;
2993 undobuf.frees = undo;
2999 /* We've committed to accepting the changes we made. Move all
3000 of the undos to the free list. */
3005 struct undo *undo, *next;
3007 for (undo = undobuf.undos; undo; undo = next)
3010 undo->next = undobuf.frees;
3011 undobuf.frees = undo;
3017 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3018 where we have an arithmetic expression and return that point. LOC will
3021 try_combine will call this function to see if an insn can be split into
3025 find_split_point (rtx *loc, rtx insn)
3028 enum rtx_code code = GET_CODE (x);
3030 unsigned HOST_WIDE_INT len = 0;
3031 HOST_WIDE_INT pos = 0;
3033 rtx inner = NULL_RTX;
3035 /* First special-case some codes. */
3039 #ifdef INSN_SCHEDULING
3040 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3042 if (MEM_P (SUBREG_REG (x)))
3045 return find_split_point (&SUBREG_REG (x), insn);
3049 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3050 using LO_SUM and HIGH. */
3051 if (GET_CODE (XEXP (x, 0)) == CONST
3052 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3055 gen_rtx_LO_SUM (Pmode,
3056 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3058 return &XEXP (XEXP (x, 0), 0);
3062 /* If we have a PLUS whose second operand is a constant and the
3063 address is not valid, perhaps will can split it up using
3064 the machine-specific way to split large constants. We use
3065 the first pseudo-reg (one of the virtual regs) as a placeholder;
3066 it will not remain in the result. */
3067 if (GET_CODE (XEXP (x, 0)) == PLUS
3068 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3069 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3071 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3072 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3075 /* This should have produced two insns, each of which sets our
3076 placeholder. If the source of the second is a valid address,
3077 we can make put both sources together and make a split point
3081 && NEXT_INSN (seq) != NULL_RTX
3082 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3083 && NONJUMP_INSN_P (seq)
3084 && GET_CODE (PATTERN (seq)) == SET
3085 && SET_DEST (PATTERN (seq)) == reg
3086 && ! reg_mentioned_p (reg,
3087 SET_SRC (PATTERN (seq)))
3088 && NONJUMP_INSN_P (NEXT_INSN (seq))
3089 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3090 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3091 && memory_address_p (GET_MODE (x),
3092 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3094 rtx src1 = SET_SRC (PATTERN (seq));
3095 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3097 /* Replace the placeholder in SRC2 with SRC1. If we can
3098 find where in SRC2 it was placed, that can become our
3099 split point and we can replace this address with SRC2.
3100 Just try two obvious places. */
3102 src2 = replace_rtx (src2, reg, src1);
3104 if (XEXP (src2, 0) == src1)
3105 split = &XEXP (src2, 0);
3106 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3107 && XEXP (XEXP (src2, 0), 0) == src1)
3108 split = &XEXP (XEXP (src2, 0), 0);
3112 SUBST (XEXP (x, 0), src2);
3117 /* If that didn't work, perhaps the first operand is complex and
3118 needs to be computed separately, so make a split point there.
3119 This will occur on machines that just support REG + CONST
3120 and have a constant moved through some previous computation. */
3122 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3123 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3124 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3125 return &XEXP (XEXP (x, 0), 0);
3131 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3132 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3133 we need to put the operand into a register. So split at that
3136 if (SET_DEST (x) == cc0_rtx
3137 && GET_CODE (SET_SRC (x)) != COMPARE
3138 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3139 && !OBJECT_P (SET_SRC (x))
3140 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3141 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3142 return &SET_SRC (x);
3145 /* See if we can split SET_SRC as it stands. */
3146 split = find_split_point (&SET_SRC (x), insn);
3147 if (split && split != &SET_SRC (x))
3150 /* See if we can split SET_DEST as it stands. */
3151 split = find_split_point (&SET_DEST (x), insn);
3152 if (split && split != &SET_DEST (x))
3155 /* See if this is a bitfield assignment with everything constant. If
3156 so, this is an IOR of an AND, so split it into that. */
3157 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3158 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3159 <= HOST_BITS_PER_WIDE_INT)
3160 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3161 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3162 && GET_CODE (SET_SRC (x)) == CONST_INT
3163 && ((INTVAL (XEXP (SET_DEST (x), 1))
3164 + INTVAL (XEXP (SET_DEST (x), 2)))
3165 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3166 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3168 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3169 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3170 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3171 rtx dest = XEXP (SET_DEST (x), 0);
3172 enum machine_mode mode = GET_MODE (dest);
3173 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3175 if (BITS_BIG_ENDIAN)
3176 pos = GET_MODE_BITSIZE (mode) - len - pos;
3180 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3183 gen_binary (IOR, mode,
3184 gen_binary (AND, mode, dest,
3185 gen_int_mode (~(mask << pos),
3187 GEN_INT (src << pos)));
3189 SUBST (SET_DEST (x), dest);
3191 split = find_split_point (&SET_SRC (x), insn);
3192 if (split && split != &SET_SRC (x))
3196 /* Otherwise, see if this is an operation that we can split into two.
3197 If so, try to split that. */
3198 code = GET_CODE (SET_SRC (x));
3203 /* If we are AND'ing with a large constant that is only a single
3204 bit and the result is only being used in a context where we
3205 need to know if it is zero or nonzero, replace it with a bit
3206 extraction. This will avoid the large constant, which might
3207 have taken more than one insn to make. If the constant were
3208 not a valid argument to the AND but took only one insn to make,
3209 this is no worse, but if it took more than one insn, it will
3212 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3213 && REG_P (XEXP (SET_SRC (x), 0))
3214 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3215 && REG_P (SET_DEST (x))
3216 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3217 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3218 && XEXP (*split, 0) == SET_DEST (x)
3219 && XEXP (*split, 1) == const0_rtx)
3221 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3222 XEXP (SET_SRC (x), 0),
3223 pos, NULL_RTX, 1, 1, 0, 0);
3224 if (extraction != 0)
3226 SUBST (SET_SRC (x), extraction);
3227 return find_split_point (loc, insn);
3233 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3234 is known to be on, this can be converted into a NEG of a shift. */
3235 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3236 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3237 && 1 <= (pos = exact_log2
3238 (nonzero_bits (XEXP (SET_SRC (x), 0),
3239 GET_MODE (XEXP (SET_SRC (x), 0))))))
3241 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3245 gen_rtx_LSHIFTRT (mode,
3246 XEXP (SET_SRC (x), 0),
3249 split = find_split_point (&SET_SRC (x), insn);
3250 if (split && split != &SET_SRC (x))
3256 inner = XEXP (SET_SRC (x), 0);
3258 /* We can't optimize if either mode is a partial integer
3259 mode as we don't know how many bits are significant
3261 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3262 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3266 len = GET_MODE_BITSIZE (GET_MODE (inner));
3272 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3273 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3275 inner = XEXP (SET_SRC (x), 0);
3276 len = INTVAL (XEXP (SET_SRC (x), 1));
3277 pos = INTVAL (XEXP (SET_SRC (x), 2));
3279 if (BITS_BIG_ENDIAN)
3280 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3281 unsignedp = (code == ZERO_EXTRACT);
3289 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3291 enum machine_mode mode = GET_MODE (SET_SRC (x));
3293 /* For unsigned, we have a choice of a shift followed by an
3294 AND or two shifts. Use two shifts for field sizes where the
3295 constant might be too large. We assume here that we can
3296 always at least get 8-bit constants in an AND insn, which is
3297 true for every current RISC. */
3299 if (unsignedp && len <= 8)
3304 (mode, gen_lowpart (mode, inner),
3306 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3308 split = find_split_point (&SET_SRC (x), insn);
3309 if (split && split != &SET_SRC (x))
3316 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3317 gen_rtx_ASHIFT (mode,
3318 gen_lowpart (mode, inner),
3319 GEN_INT (GET_MODE_BITSIZE (mode)
3321 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3323 split = find_split_point (&SET_SRC (x), insn);
3324 if (split && split != &SET_SRC (x))
3329 /* See if this is a simple operation with a constant as the second
3330 operand. It might be that this constant is out of range and hence
3331 could be used as a split point. */
3332 if (BINARY_P (SET_SRC (x))
3333 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3334 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3335 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3336 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3337 return &XEXP (SET_SRC (x), 1);
3339 /* Finally, see if this is a simple operation with its first operand
3340 not in a register. The operation might require this operand in a
3341 register, so return it as a split point. We can always do this
3342 because if the first operand were another operation, we would have
3343 already found it as a split point. */
3344 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3345 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3346 return &XEXP (SET_SRC (x), 0);
3352 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3353 it is better to write this as (not (ior A B)) so we can split it.
3354 Similarly for IOR. */
3355 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3358 gen_rtx_NOT (GET_MODE (x),
3359 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3361 XEXP (XEXP (x, 0), 0),
3362 XEXP (XEXP (x, 1), 0))));
3363 return find_split_point (loc, insn);
3366 /* Many RISC machines have a large set of logical insns. If the
3367 second operand is a NOT, put it first so we will try to split the
3368 other operand first. */
3369 if (GET_CODE (XEXP (x, 1)) == NOT)
3371 rtx tem = XEXP (x, 0);
3372 SUBST (XEXP (x, 0), XEXP (x, 1));
3373 SUBST (XEXP (x, 1), tem);
3381 /* Otherwise, select our actions depending on our rtx class. */
3382 switch (GET_RTX_CLASS (code))
3384 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3386 split = find_split_point (&XEXP (x, 2), insn);
3389 /* ... fall through ... */
3391 case RTX_COMM_ARITH:
3393 case RTX_COMM_COMPARE:
3394 split = find_split_point (&XEXP (x, 1), insn);
3397 /* ... fall through ... */
3399 /* Some machines have (and (shift ...) ...) insns. If X is not
3400 an AND, but XEXP (X, 0) is, use it as our split point. */
3401 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3402 return &XEXP (x, 0);
3404 split = find_split_point (&XEXP (x, 0), insn);
3410 /* Otherwise, we don't have a split point. */
3415 /* Throughout X, replace FROM with TO, and return the result.
3416 The result is TO if X is FROM;
3417 otherwise the result is X, but its contents may have been modified.
3418 If they were modified, a record was made in undobuf so that
3419 undo_all will (among other things) return X to its original state.
3421 If the number of changes necessary is too much to record to undo,
3422 the excess changes are not made, so the result is invalid.
3423 The changes already made can still be undone.
3424 undobuf.num_undo is incremented for such changes, so by testing that
3425 the caller can tell whether the result is valid.
3427 `n_occurrences' is incremented each time FROM is replaced.
3429 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3431 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3432 by copying if `n_occurrences' is nonzero. */
3435 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3437 enum rtx_code code = GET_CODE (x);
3438 enum machine_mode op0_mode = VOIDmode;
3443 /* Two expressions are equal if they are identical copies of a shared
3444 RTX or if they are both registers with the same register number
3447 #define COMBINE_RTX_EQUAL_P(X,Y) \
3449 || (REG_P (X) && REG_P (Y) \
3450 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3452 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3455 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3458 /* If X and FROM are the same register but different modes, they will
3459 not have been seen as equal above. However, flow.c will make a
3460 LOG_LINKS entry for that case. If we do nothing, we will try to
3461 rerecognize our original insn and, when it succeeds, we will
3462 delete the feeding insn, which is incorrect.
3464 So force this insn not to match in this (rare) case. */
3465 if (! in_dest && code == REG && REG_P (from)
3466 && REGNO (x) == REGNO (from))
3467 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3469 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3470 of which may contain things that can be combined. */
3471 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3474 /* It is possible to have a subexpression appear twice in the insn.
3475 Suppose that FROM is a register that appears within TO.
3476 Then, after that subexpression has been scanned once by `subst',
3477 the second time it is scanned, TO may be found. If we were
3478 to scan TO here, we would find FROM within it and create a
3479 self-referent rtl structure which is completely wrong. */
3480 if (COMBINE_RTX_EQUAL_P (x, to))
3483 /* Parallel asm_operands need special attention because all of the
3484 inputs are shared across the arms. Furthermore, unsharing the
3485 rtl results in recognition failures. Failure to handle this case
3486 specially can result in circular rtl.
3488 Solve this by doing a normal pass across the first entry of the
3489 parallel, and only processing the SET_DESTs of the subsequent
3492 if (code == PARALLEL
3493 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3494 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3496 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3498 /* If this substitution failed, this whole thing fails. */
3499 if (GET_CODE (new) == CLOBBER
3500 && XEXP (new, 0) == const0_rtx)
3503 SUBST (XVECEXP (x, 0, 0), new);
3505 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3507 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3510 && GET_CODE (dest) != CC0
3511 && GET_CODE (dest) != PC)
3513 new = subst (dest, from, to, 0, unique_copy);
3515 /* If this substitution failed, this whole thing fails. */
3516 if (GET_CODE (new) == CLOBBER
3517 && XEXP (new, 0) == const0_rtx)
3520 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3526 len = GET_RTX_LENGTH (code);
3527 fmt = GET_RTX_FORMAT (code);
3529 /* We don't need to process a SET_DEST that is a register, CC0,
3530 or PC, so set up to skip this common case. All other cases
3531 where we want to suppress replacing something inside a
3532 SET_SRC are handled via the IN_DEST operand. */
3534 && (REG_P (SET_DEST (x))
3535 || GET_CODE (SET_DEST (x)) == CC0
3536 || GET_CODE (SET_DEST (x)) == PC))
3539 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3542 op0_mode = GET_MODE (XEXP (x, 0));
3544 for (i = 0; i < len; i++)
3549 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3551 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3553 new = (unique_copy && n_occurrences
3554 ? copy_rtx (to) : to);
3559 new = subst (XVECEXP (x, i, j), from, to, 0,
3562 /* If this substitution failed, this whole thing
3564 if (GET_CODE (new) == CLOBBER
3565 && XEXP (new, 0) == const0_rtx)
3569 SUBST (XVECEXP (x, i, j), new);
3572 else if (fmt[i] == 'e')
3574 /* If this is a register being set, ignore it. */
3578 && (((code == SUBREG || code == ZERO_EXTRACT)
3580 || code == STRICT_LOW_PART))
3583 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3585 /* In general, don't install a subreg involving two
3586 modes not tieable. It can worsen register
3587 allocation, and can even make invalid reload
3588 insns, since the reg inside may need to be copied
3589 from in the outside mode, and that may be invalid
3590 if it is an fp reg copied in integer mode.
3592 We allow two exceptions to this: It is valid if
3593 it is inside another SUBREG and the mode of that
3594 SUBREG and the mode of the inside of TO is
3595 tieable and it is valid if X is a SET that copies
3598 if (GET_CODE (to) == SUBREG
3599 && ! MODES_TIEABLE_P (GET_MODE (to),
3600 GET_MODE (SUBREG_REG (to)))
3601 && ! (code == SUBREG
3602 && MODES_TIEABLE_P (GET_MODE (x),
3603 GET_MODE (SUBREG_REG (to))))
3605 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3608 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3610 #ifdef CANNOT_CHANGE_MODE_CLASS
3613 && REGNO (to) < FIRST_PSEUDO_REGISTER
3614 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3617 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3620 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3624 /* If we are in a SET_DEST, suppress most cases unless we
3625 have gone inside a MEM, in which case we want to
3626 simplify the address. We assume here that things that
3627 are actually part of the destination have their inner
3628 parts in the first expression. This is true for SUBREG,
3629 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3630 things aside from REG and MEM that should appear in a
3632 new = subst (XEXP (x, i), from, to,
3634 && (code == SUBREG || code == STRICT_LOW_PART
3635 || code == ZERO_EXTRACT))
3637 && i == 0), unique_copy);
3639 /* If we found that we will have to reject this combination,
3640 indicate that by returning the CLOBBER ourselves, rather than
3641 an expression containing it. This will speed things up as
3642 well as prevent accidents where two CLOBBERs are considered
3643 to be equal, thus producing an incorrect simplification. */
3645 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3648 if (GET_CODE (x) == SUBREG
3649 && (GET_CODE (new) == CONST_INT
3650 || GET_CODE (new) == CONST_DOUBLE))
3652 enum machine_mode mode = GET_MODE (x);
3654 x = simplify_subreg (GET_MODE (x), new,
3655 GET_MODE (SUBREG_REG (x)),
3658 x = gen_rtx_CLOBBER (mode, const0_rtx);
3660 else if (GET_CODE (new) == CONST_INT
3661 && GET_CODE (x) == ZERO_EXTEND)
3663 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3664 new, GET_MODE (XEXP (x, 0)));
3668 SUBST (XEXP (x, i), new);
3673 /* Try to simplify X. If the simplification changed the code, it is likely
3674 that further simplification will help, so loop, but limit the number
3675 of repetitions that will be performed. */
3677 for (i = 0; i < 4; i++)
3679 /* If X is sufficiently simple, don't bother trying to do anything
3681 if (code != CONST_INT && code != REG && code != CLOBBER)
3682 x = combine_simplify_rtx (x, op0_mode, in_dest);
3684 if (GET_CODE (x) == code)
3687 code = GET_CODE (x);
3689 /* We no longer know the original mode of operand 0 since we
3690 have changed the form of X) */
3691 op0_mode = VOIDmode;
3697 /* Simplify X, a piece of RTL. We just operate on the expression at the
3698 outer level; call `subst' to simplify recursively. Return the new
3701 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3702 if we are inside a SET_DEST. */
3705 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3707 enum rtx_code code = GET_CODE (x);
3708 enum machine_mode mode = GET_MODE (x);
3713 /* If this is a commutative operation, put a constant last and a complex
3714 expression first. We don't need to do this for comparisons here. */
3715 if (COMMUTATIVE_ARITH_P (x)
3716 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3719 SUBST (XEXP (x, 0), XEXP (x, 1));
3720 SUBST (XEXP (x, 1), temp);
3723 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3724 sign extension of a PLUS with a constant, reverse the order of the sign
3725 extension and the addition. Note that this not the same as the original
3726 code, but overflow is undefined for signed values. Also note that the
3727 PLUS will have been partially moved "inside" the sign-extension, so that
3728 the first operand of X will really look like:
3729 (ashiftrt (plus (ashift A C4) C5) C4).
3731 (plus (ashiftrt (ashift A C4) C2) C4)
3732 and replace the first operand of X with that expression. Later parts
3733 of this function may simplify the expression further.
3735 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3736 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3737 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3739 We do this to simplify address expressions. */
3741 if ((code == PLUS || code == MINUS || code == MULT)
3742 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3743 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3744 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3745 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3746 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3747 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3748 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3749 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3750 XEXP (XEXP (XEXP (x, 0), 0), 1),
3751 XEXP (XEXP (x, 0), 1))) != 0)
3754 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3755 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3756 INTVAL (XEXP (XEXP (x, 0), 1)));
3758 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3759 INTVAL (XEXP (XEXP (x, 0), 1)));
3761 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3764 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3765 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3766 things. Check for cases where both arms are testing the same
3769 Don't do anything if all operands are very simple. */
3772 && ((!OBJECT_P (XEXP (x, 0))
3773 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3774 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3775 || (!OBJECT_P (XEXP (x, 1))
3776 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3777 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3779 && (!OBJECT_P (XEXP (x, 0))
3780 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3781 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3783 rtx cond, true_rtx, false_rtx;
3785 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3787 /* If everything is a comparison, what we have is highly unlikely
3788 to be simpler, so don't use it. */
3789 && ! (COMPARISON_P (x)
3790 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3792 rtx cop1 = const0_rtx;
3793 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3795 if (cond_code == NE && COMPARISON_P (cond))
3798 /* Simplify the alternative arms; this may collapse the true and
3799 false arms to store-flag values. Be careful to use copy_rtx
3800 here since true_rtx or false_rtx might share RTL with x as a
3801 result of the if_then_else_cond call above. */
3802 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3803 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3805 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3806 is unlikely to be simpler. */
3807 if (general_operand (true_rtx, VOIDmode)
3808 && general_operand (false_rtx, VOIDmode))
3810 enum rtx_code reversed;
3812 /* Restarting if we generate a store-flag expression will cause
3813 us to loop. Just drop through in this case. */
3815 /* If the result values are STORE_FLAG_VALUE and zero, we can
3816 just make the comparison operation. */
3817 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3818 x = gen_binary (cond_code, mode, cond, cop1);
3819 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3820 && ((reversed = reversed_comparison_code_parts
3821 (cond_code, cond, cop1, NULL))
3823 x = gen_binary (reversed, mode, cond, cop1);
3825 /* Likewise, we can make the negate of a comparison operation
3826 if the result values are - STORE_FLAG_VALUE and zero. */
3827 else if (GET_CODE (true_rtx) == CONST_INT
3828 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3829 && false_rtx == const0_rtx)
3830 x = simplify_gen_unary (NEG, mode,
3831 gen_binary (cond_code, mode, cond,
3834 else if (GET_CODE (false_rtx) == CONST_INT
3835 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3836 && true_rtx == const0_rtx
3837 && ((reversed = reversed_comparison_code_parts
3838 (cond_code, cond, cop1, NULL))
3840 x = simplify_gen_unary (NEG, mode,
3841 gen_binary (reversed, mode,
3845 return gen_rtx_IF_THEN_ELSE (mode,
3846 gen_binary (cond_code, VOIDmode,
3848 true_rtx, false_rtx);
3850 code = GET_CODE (x);
3851 op0_mode = VOIDmode;
3856 /* Try to fold this expression in case we have constants that weren't
3859 switch (GET_RTX_CLASS (code))
3862 if (op0_mode == VOIDmode)
3863 op0_mode = GET_MODE (XEXP (x, 0));
3864 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3867 case RTX_COMM_COMPARE:
3869 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3870 if (cmp_mode == VOIDmode)
3872 cmp_mode = GET_MODE (XEXP (x, 1));
3873 if (cmp_mode == VOIDmode)
3874 cmp_mode = op0_mode;
3876 temp = simplify_relational_operation (code, mode, cmp_mode,
3877 XEXP (x, 0), XEXP (x, 1));
3880 case RTX_COMM_ARITH:
3882 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3884 case RTX_BITFIELD_OPS:
3886 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3887 XEXP (x, 1), XEXP (x, 2));
3896 code = GET_CODE (temp);
3897 op0_mode = VOIDmode;
3898 mode = GET_MODE (temp);
3901 /* First see if we can apply the inverse distributive law. */
3902 if (code == PLUS || code == MINUS
3903 || code == AND || code == IOR || code == XOR)
3905 x = apply_distributive_law (x);
3906 code = GET_CODE (x);
3907 op0_mode = VOIDmode;
3910 /* If CODE is an associative operation not otherwise handled, see if we
3911 can associate some operands. This can win if they are constants or
3912 if they are logically related (i.e. (a & b) & a). */
3913 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3914 || code == AND || code == IOR || code == XOR
3915 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3916 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3917 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3919 if (GET_CODE (XEXP (x, 0)) == code)
3921 rtx other = XEXP (XEXP (x, 0), 0);
3922 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3923 rtx inner_op1 = XEXP (x, 1);
3926 /* Make sure we pass the constant operand if any as the second
3927 one if this is a commutative operation. */
3928 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3930 rtx tem = inner_op0;
3931 inner_op0 = inner_op1;
3934 inner = simplify_binary_operation (code == MINUS ? PLUS
3935 : code == DIV ? MULT
3937 mode, inner_op0, inner_op1);
3939 /* For commutative operations, try the other pair if that one
3941 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3943 other = XEXP (XEXP (x, 0), 1);
3944 inner = simplify_binary_operation (code, mode,
3945 XEXP (XEXP (x, 0), 0),
3950 return gen_binary (code, mode, other, inner);
3954 /* A little bit of algebraic simplification here. */
3958 /* Ensure that our address has any ASHIFTs converted to MULT in case
3959 address-recognizing predicates are called later. */
3960 temp = make_compound_operation (XEXP (x, 0), MEM);
3961 SUBST (XEXP (x, 0), temp);
3965 if (op0_mode == VOIDmode)
3966 op0_mode = GET_MODE (SUBREG_REG (x));
3968 /* See if this can be moved to simplify_subreg. */
3969 if (CONSTANT_P (SUBREG_REG (x))
3970 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3971 /* Don't call gen_lowpart if the inner mode
3972 is VOIDmode and we cannot simplify it, as SUBREG without
3973 inner mode is invalid. */
3974 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3975 || gen_lowpart_common (mode, SUBREG_REG (x))))
3976 return gen_lowpart (mode, SUBREG_REG (x));
3978 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3982 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3988 /* Don't change the mode of the MEM if that would change the meaning
3990 if (MEM_P (SUBREG_REG (x))
3991 && (MEM_VOLATILE_P (SUBREG_REG (x))
3992 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3993 return gen_rtx_CLOBBER (mode, const0_rtx);
3995 /* Note that we cannot do any narrowing for non-constants since
3996 we might have been counting on using the fact that some bits were
3997 zero. We now do this in the SET. */
4002 if (GET_CODE (XEXP (x, 0)) == SUBREG
4003 && subreg_lowpart_p (XEXP (x, 0))
4004 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4005 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4006 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4007 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4009 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4011 x = gen_rtx_ROTATE (inner_mode,
4012 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4014 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4015 return gen_lowpart (mode, x);
4018 /* Apply De Morgan's laws to reduce number of patterns for machines
4019 with negating logical insns (and-not, nand, etc.). If result has
4020 only one NOT, put it first, since that is how the patterns are
4023 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4025 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4026 enum machine_mode op_mode;
4028 op_mode = GET_MODE (in1);
4029 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4031 op_mode = GET_MODE (in2);
4032 if (op_mode == VOIDmode)
4034 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4036 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4039 in2 = in1; in1 = tem;
4042 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4048 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4049 if (GET_CODE (XEXP (x, 0)) == XOR
4050 && XEXP (XEXP (x, 0), 1) == const1_rtx
4051 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4052 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4054 temp = expand_compound_operation (XEXP (x, 0));
4056 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4057 replaced by (lshiftrt X C). This will convert
4058 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4060 if (GET_CODE (temp) == ASHIFTRT
4061 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4062 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4063 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4064 INTVAL (XEXP (temp, 1)));
4066 /* If X has only a single bit that might be nonzero, say, bit I, convert
4067 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4068 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4069 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4070 or a SUBREG of one since we'd be making the expression more
4071 complex if it was just a register. */
4074 && ! (GET_CODE (temp) == SUBREG
4075 && REG_P (SUBREG_REG (temp)))
4076 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4078 rtx temp1 = simplify_shift_const
4079 (NULL_RTX, ASHIFTRT, mode,
4080 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4081 GET_MODE_BITSIZE (mode) - 1 - i),
4082 GET_MODE_BITSIZE (mode) - 1 - i);
4084 /* If all we did was surround TEMP with the two shifts, we
4085 haven't improved anything, so don't use it. Otherwise,
4086 we are better off with TEMP1. */
4087 if (GET_CODE (temp1) != ASHIFTRT
4088 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4089 || XEXP (XEXP (temp1, 0), 0) != temp)
4095 /* We can't handle truncation to a partial integer mode here
4096 because we don't know the real bitsize of the partial
4098 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4101 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4102 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4103 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4105 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4106 GET_MODE_MASK (mode), NULL_RTX, 0));
4108 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4109 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4110 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4111 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4112 return XEXP (XEXP (x, 0), 0);
4114 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4115 (OP:SI foo:SI) if OP is NEG or ABS. */
4116 if ((GET_CODE (XEXP (x, 0)) == ABS
4117 || GET_CODE (XEXP (x, 0)) == NEG)
4118 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4119 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4120 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4121 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4122 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4124 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4126 if (GET_CODE (XEXP (x, 0)) == SUBREG
4127 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4128 && subreg_lowpart_p (XEXP (x, 0)))
4129 return SUBREG_REG (XEXP (x, 0));
4131 /* If we know that the value is already truncated, we can
4132 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4133 is nonzero for the corresponding modes. But don't do this
4134 for an (LSHIFTRT (MULT ...)) since this will cause problems
4135 with the umulXi3_highpart patterns. */
4136 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4137 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4138 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4139 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4140 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4141 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4142 return gen_lowpart (mode, XEXP (x, 0));
4144 /* A truncate of a comparison can be replaced with a subreg if
4145 STORE_FLAG_VALUE permits. This is like the previous test,
4146 but it works even if the comparison is done in a mode larger
4147 than HOST_BITS_PER_WIDE_INT. */
4148 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4149 && COMPARISON_P (XEXP (x, 0))
4150 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4151 return gen_lowpart (mode, XEXP (x, 0));
4153 /* Similarly, a truncate of a register whose value is a
4154 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4156 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4157 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4158 && (temp = get_last_value (XEXP (x, 0)))
4159 && COMPARISON_P (temp))
4160 return gen_lowpart (mode, XEXP (x, 0));
4164 case FLOAT_TRUNCATE:
4165 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4166 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4167 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4168 return XEXP (XEXP (x, 0), 0);
4170 /* (float_truncate:SF (float_truncate:DF foo:XF))
4171 = (float_truncate:SF foo:XF).
4172 This may eliminate double rounding, so it is unsafe.
4174 (float_truncate:SF (float_extend:XF foo:DF))
4175 = (float_truncate:SF foo:DF).
4177 (float_truncate:DF (float_extend:XF foo:SF))
4178 = (float_extend:SF foo:DF). */
4179 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4180 && flag_unsafe_math_optimizations)
4181 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4182 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4184 > GET_MODE_SIZE (mode)
4185 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4187 XEXP (XEXP (x, 0), 0), mode);
4189 /* (float_truncate (float x)) is (float x) */
4190 if (GET_CODE (XEXP (x, 0)) == FLOAT
4191 && (flag_unsafe_math_optimizations
4192 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4193 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4194 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4195 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4196 return simplify_gen_unary (FLOAT, mode,
4197 XEXP (XEXP (x, 0), 0),
4198 GET_MODE (XEXP (XEXP (x, 0), 0)));
4200 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4201 (OP:SF foo:SF) if OP is NEG or ABS. */
4202 if ((GET_CODE (XEXP (x, 0)) == ABS
4203 || GET_CODE (XEXP (x, 0)) == NEG)
4204 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4205 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4206 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4207 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4209 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4210 is (float_truncate:SF x). */
4211 if (GET_CODE (XEXP (x, 0)) == SUBREG
4212 && subreg_lowpart_p (XEXP (x, 0))
4213 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4214 return SUBREG_REG (XEXP (x, 0));
4217 /* (float_extend (float_extend x)) is (float_extend x)
4219 (float_extend (float x)) is (float x) assuming that double
4220 rounding can't happen.
4222 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4223 || (GET_CODE (XEXP (x, 0)) == FLOAT
4224 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4225 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4226 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4227 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4228 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4229 XEXP (XEXP (x, 0), 0),
4230 GET_MODE (XEXP (XEXP (x, 0), 0)));
4235 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4236 using cc0, in which case we want to leave it as a COMPARE
4237 so we can distinguish it from a register-register-copy. */
4238 if (XEXP (x, 1) == const0_rtx)
4241 /* x - 0 is the same as x unless x's mode has signed zeros and
4242 allows rounding towards -infinity. Under those conditions,
4244 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4245 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4246 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4252 /* (const (const X)) can become (const X). Do it this way rather than
4253 returning the inner CONST since CONST can be shared with a
4255 if (GET_CODE (XEXP (x, 0)) == CONST)
4256 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4261 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4262 can add in an offset. find_split_point will split this address up
4263 again if it doesn't match. */
4264 if (GET_CODE (XEXP (x, 0)) == HIGH
4265 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4271 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4273 if (GET_CODE (XEXP (x, 0)) == MULT
4274 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4278 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4279 in2 = XEXP (XEXP (x, 0), 1);
4280 return gen_binary (MINUS, mode, XEXP (x, 1),
4281 gen_binary (MULT, mode, in1, in2));
4284 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4285 outermost. That's because that's the way indexed addresses are
4286 supposed to appear. This code used to check many more cases, but
4287 they are now checked elsewhere. */
4288 if (GET_CODE (XEXP (x, 0)) == PLUS
4289 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4290 return gen_binary (PLUS, mode,
4291 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4293 XEXP (XEXP (x, 0), 1));
4295 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4296 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4297 bit-field and can be replaced by either a sign_extend or a
4298 sign_extract. The `and' may be a zero_extend and the two
4299 <c>, -<c> constants may be reversed. */
4300 if (GET_CODE (XEXP (x, 0)) == XOR
4301 && GET_CODE (XEXP (x, 1)) == CONST_INT
4302 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4303 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4304 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4305 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4306 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4307 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4308 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4309 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4310 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4311 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4312 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4313 == (unsigned int) i + 1))))
4314 return simplify_shift_const
4315 (NULL_RTX, ASHIFTRT, mode,
4316 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4317 XEXP (XEXP (XEXP (x, 0), 0), 0),
4318 GET_MODE_BITSIZE (mode) - (i + 1)),
4319 GET_MODE_BITSIZE (mode) - (i + 1));
4321 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4322 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4323 is 1. This produces better code than the alternative immediately
4325 if (COMPARISON_P (XEXP (x, 0))
4326 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4327 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4328 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4329 XEXP (XEXP (x, 0), 0),
4330 XEXP (XEXP (x, 0), 1))))
4332 simplify_gen_unary (NEG, mode, reversed, mode);
4334 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4335 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4336 the bitsize of the mode - 1. This allows simplification of
4337 "a = (b & 8) == 0;" */
4338 if (XEXP (x, 1) == constm1_rtx
4339 && !REG_P (XEXP (x, 0))
4340 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4341 && REG_P (SUBREG_REG (XEXP (x, 0))))
4342 && nonzero_bits (XEXP (x, 0), mode) == 1)
4343 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4344 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4345 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4346 GET_MODE_BITSIZE (mode) - 1),
4347 GET_MODE_BITSIZE (mode) - 1);
4349 /* If we are adding two things that have no bits in common, convert
4350 the addition into an IOR. This will often be further simplified,
4351 for example in cases like ((a & 1) + (a & 2)), which can
4354 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4355 && (nonzero_bits (XEXP (x, 0), mode)
4356 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4358 /* Try to simplify the expression further. */
4359 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4360 temp = combine_simplify_rtx (tor, mode, in_dest);
4362 /* If we could, great. If not, do not go ahead with the IOR
4363 replacement, since PLUS appears in many special purpose
4364 address arithmetic instructions. */
4365 if (GET_CODE (temp) != CLOBBER && temp != tor)
4371 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4372 by reversing the comparison code if valid. */
4373 if (STORE_FLAG_VALUE == 1
4374 && XEXP (x, 0) == const1_rtx
4375 && COMPARISON_P (XEXP (x, 1))
4376 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4377 XEXP (XEXP (x, 1), 0),
4378 XEXP (XEXP (x, 1), 1))))
4381 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4382 (and <foo> (const_int pow2-1)) */
4383 if (GET_CODE (XEXP (x, 1)) == AND
4384 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4385 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4386 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4387 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4388 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4390 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4392 if (GET_CODE (XEXP (x, 1)) == MULT
4393 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4397 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4398 in2 = XEXP (XEXP (x, 1), 1);
4399 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4403 /* Canonicalize (minus (neg A) (mult B C)) to
4404 (minus (mult (neg B) C) A). */
4405 if (GET_CODE (XEXP (x, 1)) == MULT
4406 && GET_CODE (XEXP (x, 0)) == NEG)
4410 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4411 in2 = XEXP (XEXP (x, 1), 1);
4412 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4413 XEXP (XEXP (x, 0), 0));
4416 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4418 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4419 return gen_binary (MINUS, mode,
4420 gen_binary (MINUS, mode, XEXP (x, 0),
4421 XEXP (XEXP (x, 1), 0)),
4422 XEXP (XEXP (x, 1), 1));
4426 /* If we have (mult (plus A B) C), apply the distributive law and then
4427 the inverse distributive law to see if things simplify. This
4428 occurs mostly in addresses, often when unrolling loops. */
4430 if (GET_CODE (XEXP (x, 0)) == PLUS)
4432 x = apply_distributive_law
4433 (gen_binary (PLUS, mode,
4434 gen_binary (MULT, mode,
4435 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4436 gen_binary (MULT, mode,
4437 XEXP (XEXP (x, 0), 1),
4438 copy_rtx (XEXP (x, 1)))));
4440 if (GET_CODE (x) != MULT)
4443 /* Try simplify a*(b/c) as (a*b)/c. */
4444 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4445 && GET_CODE (XEXP (x, 0)) == DIV)
4447 rtx tem = simplify_binary_operation (MULT, mode,
4448 XEXP (XEXP (x, 0), 0),
4451 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4456 /* If this is a divide by a power of two, treat it as a shift if
4457 its first operand is a shift. */
4458 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4459 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4460 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4461 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4462 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4463 || GET_CODE (XEXP (x, 0)) == ROTATE
4464 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4465 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4469 case GT: case GTU: case GE: case GEU:
4470 case LT: case LTU: case LE: case LEU:
4471 case UNEQ: case LTGT:
4472 case UNGT: case UNGE:
4473 case UNLT: case UNLE:
4474 case UNORDERED: case ORDERED:
4475 /* If the first operand is a condition code, we can't do anything
4477 if (GET_CODE (XEXP (x, 0)) == COMPARE
4478 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4479 && ! CC0_P (XEXP (x, 0))))
4481 rtx op0 = XEXP (x, 0);
4482 rtx op1 = XEXP (x, 1);
4483 enum rtx_code new_code;
4485 if (GET_CODE (op0) == COMPARE)
4486 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4488 /* Simplify our comparison, if possible. */
4489 new_code = simplify_comparison (code, &op0, &op1);
4491 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4492 if only the low-order bit is possibly nonzero in X (such as when
4493 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4494 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4495 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4498 Remove any ZERO_EXTRACT we made when thinking this was a
4499 comparison. It may now be simpler to use, e.g., an AND. If a
4500 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4501 the call to make_compound_operation in the SET case. */
4503 if (STORE_FLAG_VALUE == 1
4504 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4505 && op1 == const0_rtx
4506 && mode == GET_MODE (op0)
4507 && nonzero_bits (op0, mode) == 1)
4508 return gen_lowpart (mode,
4509 expand_compound_operation (op0));
4511 else if (STORE_FLAG_VALUE == 1
4512 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4513 && op1 == const0_rtx
4514 && mode == GET_MODE (op0)
4515 && (num_sign_bit_copies (op0, mode)
4516 == GET_MODE_BITSIZE (mode)))
4518 op0 = expand_compound_operation (op0);
4519 return simplify_gen_unary (NEG, mode,
4520 gen_lowpart (mode, op0),
4524 else if (STORE_FLAG_VALUE == 1
4525 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4526 && op1 == const0_rtx
4527 && mode == GET_MODE (op0)
4528 && nonzero_bits (op0, mode) == 1)
4530 op0 = expand_compound_operation (op0);
4531 return gen_binary (XOR, mode,
4532 gen_lowpart (mode, op0),
4536 else if (STORE_FLAG_VALUE == 1
4537 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4538 && op1 == const0_rtx
4539 && mode == GET_MODE (op0)
4540 && (num_sign_bit_copies (op0, mode)
4541 == GET_MODE_BITSIZE (mode)))
4543 op0 = expand_compound_operation (op0);
4544 return plus_constant (gen_lowpart (mode, op0), 1);
4547 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4549 if (STORE_FLAG_VALUE == -1
4550 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4551 && op1 == const0_rtx
4552 && (num_sign_bit_copies (op0, mode)
4553 == GET_MODE_BITSIZE (mode)))
4554 return gen_lowpart (mode,
4555 expand_compound_operation (op0));
4557 else if (STORE_FLAG_VALUE == -1
4558 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4559 && op1 == const0_rtx
4560 && mode == GET_MODE (op0)
4561 && nonzero_bits (op0, mode) == 1)
4563 op0 = expand_compound_operation (op0);
4564 return simplify_gen_unary (NEG, mode,
4565 gen_lowpart (mode, op0),
4569 else if (STORE_FLAG_VALUE == -1
4570 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4571 && op1 == const0_rtx
4572 && mode == GET_MODE (op0)
4573 && (num_sign_bit_copies (op0, mode)
4574 == GET_MODE_BITSIZE (mode)))
4576 op0 = expand_compound_operation (op0);
4577 return simplify_gen_unary (NOT, mode,
4578 gen_lowpart (mode, op0),
4582 /* If X is 0/1, (eq X 0) is X-1. */
4583 else if (STORE_FLAG_VALUE == -1
4584 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4585 && op1 == const0_rtx
4586 && mode == GET_MODE (op0)
4587 && nonzero_bits (op0, mode) == 1)
4589 op0 = expand_compound_operation (op0);
4590 return plus_constant (gen_lowpart (mode, op0), -1);
4593 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4594 one bit that might be nonzero, we can convert (ne x 0) to
4595 (ashift x c) where C puts the bit in the sign bit. Remove any
4596 AND with STORE_FLAG_VALUE when we are done, since we are only
4597 going to test the sign bit. */
4598 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4599 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4600 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4601 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4602 && op1 == const0_rtx
4603 && mode == GET_MODE (op0)
4604 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4606 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4607 expand_compound_operation (op0),
4608 GET_MODE_BITSIZE (mode) - 1 - i);
4609 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4615 /* If the code changed, return a whole new comparison. */
4616 if (new_code != code)
4617 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4619 /* Otherwise, keep this operation, but maybe change its operands.
4620 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4621 SUBST (XEXP (x, 0), op0);
4622 SUBST (XEXP (x, 1), op1);
4627 return simplify_if_then_else (x);
4633 /* If we are processing SET_DEST, we are done. */
4637 return expand_compound_operation (x);
4640 return simplify_set (x);
4645 return simplify_logical (x);
4648 /* (abs (neg <foo>)) -> (abs <foo>) */
4649 if (GET_CODE (XEXP (x, 0)) == NEG)
4650 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4652 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4654 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4657 /* If operand is something known to be positive, ignore the ABS. */
4658 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4659 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4660 <= HOST_BITS_PER_WIDE_INT)
4661 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4662 & ((HOST_WIDE_INT) 1
4663 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4667 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4668 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4669 return gen_rtx_NEG (mode, XEXP (x, 0));
4674 /* (ffs (*_extend <X>)) = (ffs <X>) */
4675 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4676 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4677 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4682 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4683 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4684 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4688 /* (float (sign_extend <X>)) = (float <X>). */
4689 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4690 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4698 /* If this is a shift by a constant amount, simplify it. */
4699 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4700 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4701 INTVAL (XEXP (x, 1)));
4703 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4705 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4707 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4714 rtx op0 = XEXP (x, 0);
4715 rtx op1 = XEXP (x, 1);
4718 gcc_assert (GET_CODE (op1) == PARALLEL);
4719 len = XVECLEN (op1, 0);
4721 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4722 && GET_CODE (op0) == VEC_CONCAT)
4724 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4726 /* Try to find the element in the VEC_CONCAT. */
4729 if (GET_MODE (op0) == GET_MODE (x))
4731 if (GET_CODE (op0) == VEC_CONCAT)
4733 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4734 if (op0_size < offset)
4735 op0 = XEXP (op0, 0);
4739 op0 = XEXP (op0, 1);
4757 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4760 simplify_if_then_else (rtx x)
4762 enum machine_mode mode = GET_MODE (x);
4763 rtx cond = XEXP (x, 0);
4764 rtx true_rtx = XEXP (x, 1);
4765 rtx false_rtx = XEXP (x, 2);
4766 enum rtx_code true_code = GET_CODE (cond);
4767 int comparison_p = COMPARISON_P (cond);
4770 enum rtx_code false_code;
4773 /* Simplify storing of the truth value. */
4774 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4775 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4777 /* Also when the truth value has to be reversed. */
4779 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4780 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4784 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4785 in it is being compared against certain values. Get the true and false
4786 comparisons and see if that says anything about the value of each arm. */
4789 && ((false_code = combine_reversed_comparison_code (cond))
4791 && REG_P (XEXP (cond, 0)))
4794 rtx from = XEXP (cond, 0);
4795 rtx true_val = XEXP (cond, 1);
4796 rtx false_val = true_val;
4799 /* If FALSE_CODE is EQ, swap the codes and arms. */
4801 if (false_code == EQ)
4803 swapped = 1, true_code = EQ, false_code = NE;
4804 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4807 /* If we are comparing against zero and the expression being tested has
4808 only a single bit that might be nonzero, that is its value when it is
4809 not equal to zero. Similarly if it is known to be -1 or 0. */
4811 if (true_code == EQ && true_val == const0_rtx
4812 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4813 false_code = EQ, false_val = GEN_INT (nzb);
4814 else if (true_code == EQ && true_val == const0_rtx
4815 && (num_sign_bit_copies (from, GET_MODE (from))
4816 == GET_MODE_BITSIZE (GET_MODE (from))))
4817 false_code = EQ, false_val = constm1_rtx;
4819 /* Now simplify an arm if we know the value of the register in the
4820 branch and it is used in the arm. Be careful due to the potential
4821 of locally-shared RTL. */
4823 if (reg_mentioned_p (from, true_rtx))
4824 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4826 pc_rtx, pc_rtx, 0, 0);
4827 if (reg_mentioned_p (from, false_rtx))
4828 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4830 pc_rtx, pc_rtx, 0, 0);
4832 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4833 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4835 true_rtx = XEXP (x, 1);
4836 false_rtx = XEXP (x, 2);
4837 true_code = GET_CODE (cond);
4840 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4841 reversed, do so to avoid needing two sets of patterns for
4842 subtract-and-branch insns. Similarly if we have a constant in the true
4843 arm, the false arm is the same as the first operand of the comparison, or
4844 the false arm is more complicated than the true arm. */
4847 && combine_reversed_comparison_code (cond) != UNKNOWN
4848 && (true_rtx == pc_rtx
4849 || (CONSTANT_P (true_rtx)
4850 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4851 || true_rtx == const0_rtx
4852 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4853 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4854 && !OBJECT_P (false_rtx))
4855 || reg_mentioned_p (true_rtx, false_rtx)
4856 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4858 true_code = reversed_comparison_code (cond, NULL);
4860 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4863 SUBST (XEXP (x, 1), false_rtx);
4864 SUBST (XEXP (x, 2), true_rtx);
4866 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4869 /* It is possible that the conditional has been simplified out. */
4870 true_code = GET_CODE (cond);
4871 comparison_p = COMPARISON_P (cond);
4874 /* If the two arms are identical, we don't need the comparison. */
4876 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4879 /* Convert a == b ? b : a to "a". */
4880 if (true_code == EQ && ! side_effects_p (cond)
4881 && !HONOR_NANS (mode)
4882 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4883 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4885 else if (true_code == NE && ! side_effects_p (cond)
4886 && !HONOR_NANS (mode)
4887 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4888 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4891 /* Look for cases where we have (abs x) or (neg (abs X)). */
4893 if (GET_MODE_CLASS (mode) == MODE_INT
4894 && GET_CODE (false_rtx) == NEG
4895 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4897 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4898 && ! side_effects_p (true_rtx))
4903 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4907 simplify_gen_unary (NEG, mode,
4908 simplify_gen_unary (ABS, mode, true_rtx, mode),
4914 /* Look for MIN or MAX. */
4916 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4918 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4919 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4920 && ! side_effects_p (cond))
4925 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4928 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4931 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4934 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4939 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4940 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4941 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4942 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4943 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4944 neither 1 or -1, but it isn't worth checking for. */
4946 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4948 && GET_MODE_CLASS (mode) == MODE_INT
4949 && ! side_effects_p (x))
4951 rtx t = make_compound_operation (true_rtx, SET);
4952 rtx f = make_compound_operation (false_rtx, SET);
4953 rtx cond_op0 = XEXP (cond, 0);
4954 rtx cond_op1 = XEXP (cond, 1);
4955 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4956 enum machine_mode m = mode;
4957 rtx z = 0, c1 = NULL_RTX;
4959 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4960 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4961 || GET_CODE (t) == ASHIFT
4962 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4963 && rtx_equal_p (XEXP (t, 0), f))
4964 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4966 /* If an identity-zero op is commutative, check whether there
4967 would be a match if we swapped the operands. */
4968 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4969 || GET_CODE (t) == XOR)
4970 && rtx_equal_p (XEXP (t, 1), f))
4971 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4972 else if (GET_CODE (t) == SIGN_EXTEND
4973 && (GET_CODE (XEXP (t, 0)) == PLUS
4974 || GET_CODE (XEXP (t, 0)) == MINUS
4975 || GET_CODE (XEXP (t, 0)) == IOR
4976 || GET_CODE (XEXP (t, 0)) == XOR
4977 || GET_CODE (XEXP (t, 0)) == ASHIFT
4978 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4979 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4980 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4981 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4982 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4983 && (num_sign_bit_copies (f, GET_MODE (f))
4985 (GET_MODE_BITSIZE (mode)
4986 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4988 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4989 extend_op = SIGN_EXTEND;
4990 m = GET_MODE (XEXP (t, 0));
4992 else if (GET_CODE (t) == SIGN_EXTEND
4993 && (GET_CODE (XEXP (t, 0)) == PLUS
4994 || GET_CODE (XEXP (t, 0)) == IOR
4995 || GET_CODE (XEXP (t, 0)) == XOR)
4996 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4997 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4998 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4999 && (num_sign_bit_copies (f, GET_MODE (f))
5001 (GET_MODE_BITSIZE (mode)
5002 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5004 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5005 extend_op = SIGN_EXTEND;
5006 m = GET_MODE (XEXP (t, 0));
5008 else if (GET_CODE (t) == ZERO_EXTEND
5009 && (GET_CODE (XEXP (t, 0)) == PLUS
5010 || GET_CODE (XEXP (t, 0)) == MINUS
5011 || GET_CODE (XEXP (t, 0)) == IOR
5012 || GET_CODE (XEXP (t, 0)) == XOR
5013 || GET_CODE (XEXP (t, 0)) == ASHIFT
5014 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5015 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5016 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5017 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5018 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5019 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5020 && ((nonzero_bits (f, GET_MODE (f))
5021 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5024 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5025 extend_op = ZERO_EXTEND;
5026 m = GET_MODE (XEXP (t, 0));
5028 else if (GET_CODE (t) == ZERO_EXTEND
5029 && (GET_CODE (XEXP (t, 0)) == PLUS
5030 || GET_CODE (XEXP (t, 0)) == IOR
5031 || GET_CODE (XEXP (t, 0)) == XOR)
5032 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5033 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5034 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5035 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5036 && ((nonzero_bits (f, GET_MODE (f))
5037 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5040 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5041 extend_op = ZERO_EXTEND;
5042 m = GET_MODE (XEXP (t, 0));
5047 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5048 pc_rtx, pc_rtx, 0, 0);
5049 temp = gen_binary (MULT, m, temp,
5050 gen_binary (MULT, m, c1, const_true_rtx));
5051 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5052 temp = gen_binary (op, m, gen_lowpart (m, z), temp);
5054 if (extend_op != UNKNOWN)
5055 temp = simplify_gen_unary (extend_op, mode, temp, m);
5061 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5062 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5063 negation of a single bit, we can convert this operation to a shift. We
5064 can actually do this more generally, but it doesn't seem worth it. */
5066 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5067 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5068 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5069 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5070 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5071 == GET_MODE_BITSIZE (mode))
5072 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5074 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5075 gen_lowpart (mode, XEXP (cond, 0)), i);
5077 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5078 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5079 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5080 && GET_MODE (XEXP (cond, 0)) == mode
5081 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5082 == nonzero_bits (XEXP (cond, 0), mode)
5083 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5084 return XEXP (cond, 0);
5089 /* Simplify X, a SET expression. Return the new expression. */
5092 simplify_set (rtx x)
5094 rtx src = SET_SRC (x);
5095 rtx dest = SET_DEST (x);
5096 enum machine_mode mode
5097 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5101 /* (set (pc) (return)) gets written as (return). */
5102 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5105 /* Now that we know for sure which bits of SRC we are using, see if we can
5106 simplify the expression for the object knowing that we only need the
5109 if (GET_MODE_CLASS (mode) == MODE_INT
5110 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5112 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5113 SUBST (SET_SRC (x), src);
5116 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5117 the comparison result and try to simplify it unless we already have used
5118 undobuf.other_insn. */
5119 if ((GET_MODE_CLASS (mode) == MODE_CC
5120 || GET_CODE (src) == COMPARE
5122 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5123 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5124 && COMPARISON_P (*cc_use)
5125 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5127 enum rtx_code old_code = GET_CODE (*cc_use);
5128 enum rtx_code new_code;
5130 int other_changed = 0;
5131 enum machine_mode compare_mode = GET_MODE (dest);
5133 if (GET_CODE (src) == COMPARE)
5134 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5136 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5138 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5141 new_code = old_code;
5142 else if (!CONSTANT_P (tmp))
5144 new_code = GET_CODE (tmp);
5145 op0 = XEXP (tmp, 0);
5146 op1 = XEXP (tmp, 1);
5150 rtx pat = PATTERN (other_insn);
5151 undobuf.other_insn = other_insn;
5152 SUBST (*cc_use, tmp);
5154 /* Attempt to simplify CC user. */
5155 if (GET_CODE (pat) == SET)
5157 rtx new = simplify_rtx (SET_SRC (pat));
5158 if (new != NULL_RTX)
5159 SUBST (SET_SRC (pat), new);
5162 /* Convert X into a no-op move. */
5163 SUBST (SET_DEST (x), pc_rtx);
5164 SUBST (SET_SRC (x), pc_rtx);
5168 /* Simplify our comparison, if possible. */
5169 new_code = simplify_comparison (new_code, &op0, &op1);
5171 #ifdef SELECT_CC_MODE
5172 /* If this machine has CC modes other than CCmode, check to see if we
5173 need to use a different CC mode here. */
5174 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5175 compare_mode = GET_MODE (op0);
5177 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5180 /* If the mode changed, we have to change SET_DEST, the mode in the
5181 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5182 a hard register, just build new versions with the proper mode. If it
5183 is a pseudo, we lose unless it is only time we set the pseudo, in
5184 which case we can safely change its mode. */
5185 if (compare_mode != GET_MODE (dest))
5187 unsigned int regno = REGNO (dest);
5188 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5190 if (regno < FIRST_PSEUDO_REGISTER
5191 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5193 if (regno >= FIRST_PSEUDO_REGISTER)
5194 SUBST (regno_reg_rtx[regno], new_dest);
5196 SUBST (SET_DEST (x), new_dest);
5197 SUBST (XEXP (*cc_use, 0), new_dest);
5204 #endif /* SELECT_CC_MODE */
5206 /* If the code changed, we have to build a new comparison in
5207 undobuf.other_insn. */
5208 if (new_code != old_code)
5210 int other_changed_previously = other_changed;
5211 unsigned HOST_WIDE_INT mask;
5213 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5217 /* If the only change we made was to change an EQ into an NE or
5218 vice versa, OP0 has only one bit that might be nonzero, and OP1
5219 is zero, check if changing the user of the condition code will
5220 produce a valid insn. If it won't, we can keep the original code
5221 in that insn by surrounding our operation with an XOR. */
5223 if (((old_code == NE && new_code == EQ)
5224 || (old_code == EQ && new_code == NE))
5225 && ! other_changed_previously && op1 == const0_rtx
5226 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5227 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5229 rtx pat = PATTERN (other_insn), note = 0;
5231 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5232 && ! check_asm_operands (pat)))
5234 PUT_CODE (*cc_use, old_code);
5237 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5243 undobuf.other_insn = other_insn;
5246 /* If we are now comparing against zero, change our source if
5247 needed. If we do not use cc0, we always have a COMPARE. */
5248 if (op1 == const0_rtx && dest == cc0_rtx)
5250 SUBST (SET_SRC (x), op0);
5256 /* Otherwise, if we didn't previously have a COMPARE in the
5257 correct mode, we need one. */
5258 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5260 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5265 /* Otherwise, update the COMPARE if needed. */
5266 SUBST (XEXP (src, 0), op0);
5267 SUBST (XEXP (src, 1), op1);
5272 /* Get SET_SRC in a form where we have placed back any
5273 compound expressions. Then do the checks below. */
5274 src = make_compound_operation (src, SET);
5275 SUBST (SET_SRC (x), src);
5278 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5279 and X being a REG or (subreg (reg)), we may be able to convert this to
5280 (set (subreg:m2 x) (op)).
5282 We can always do this if M1 is narrower than M2 because that means that
5283 we only care about the low bits of the result.
5285 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5286 perform a narrower operation than requested since the high-order bits will
5287 be undefined. On machine where it is defined, this transformation is safe
5288 as long as M1 and M2 have the same number of words. */
5290 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5291 && !OBJECT_P (SUBREG_REG (src))
5292 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5294 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5295 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5296 #ifndef WORD_REGISTER_OPERATIONS
5297 && (GET_MODE_SIZE (GET_MODE (src))
5298 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5300 #ifdef CANNOT_CHANGE_MODE_CLASS
5301 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5302 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5303 GET_MODE (SUBREG_REG (src)),
5307 || (GET_CODE (dest) == SUBREG
5308 && REG_P (SUBREG_REG (dest)))))
5310 SUBST (SET_DEST (x),
5311 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5313 SUBST (SET_SRC (x), SUBREG_REG (src));
5315 src = SET_SRC (x), dest = SET_DEST (x);
5319 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5322 && GET_CODE (src) == SUBREG
5323 && subreg_lowpart_p (src)
5324 && (GET_MODE_BITSIZE (GET_MODE (src))
5325 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5327 rtx inner = SUBREG_REG (src);
5328 enum machine_mode inner_mode = GET_MODE (inner);
5330 /* Here we make sure that we don't have a sign bit on. */
5331 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5332 && (nonzero_bits (inner, inner_mode)
5333 < ((unsigned HOST_WIDE_INT) 1
5334 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5336 SUBST (SET_SRC (x), inner);
5342 #ifdef LOAD_EXTEND_OP
5343 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5344 would require a paradoxical subreg. Replace the subreg with a
5345 zero_extend to avoid the reload that would otherwise be required. */
5347 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5348 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5349 && SUBREG_BYTE (src) == 0
5350 && (GET_MODE_SIZE (GET_MODE (src))
5351 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5352 && MEM_P (SUBREG_REG (src)))
5355 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5356 GET_MODE (src), SUBREG_REG (src)));
5362 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5363 are comparing an item known to be 0 or -1 against 0, use a logical
5364 operation instead. Check for one of the arms being an IOR of the other
5365 arm with some value. We compute three terms to be IOR'ed together. In
5366 practice, at most two will be nonzero. Then we do the IOR's. */
5368 if (GET_CODE (dest) != PC
5369 && GET_CODE (src) == IF_THEN_ELSE
5370 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5371 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5372 && XEXP (XEXP (src, 0), 1) == const0_rtx
5373 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5374 #ifdef HAVE_conditional_move
5375 && ! can_conditionally_move_p (GET_MODE (src))
5377 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5378 GET_MODE (XEXP (XEXP (src, 0), 0)))
5379 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5380 && ! side_effects_p (src))
5382 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5383 ? XEXP (src, 1) : XEXP (src, 2));
5384 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5385 ? XEXP (src, 2) : XEXP (src, 1));
5386 rtx term1 = const0_rtx, term2, term3;
5388 if (GET_CODE (true_rtx) == IOR
5389 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5390 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5391 else if (GET_CODE (true_rtx) == IOR
5392 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5393 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5394 else if (GET_CODE (false_rtx) == IOR
5395 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5396 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5397 else if (GET_CODE (false_rtx) == IOR
5398 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5399 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5401 term2 = gen_binary (AND, GET_MODE (src),
5402 XEXP (XEXP (src, 0), 0), true_rtx);
5403 term3 = gen_binary (AND, GET_MODE (src),
5404 simplify_gen_unary (NOT, GET_MODE (src),
5405 XEXP (XEXP (src, 0), 0),
5410 gen_binary (IOR, GET_MODE (src),
5411 gen_binary (IOR, GET_MODE (src), term1, term2),
5417 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5418 whole thing fail. */
5419 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5421 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5424 /* Convert this into a field assignment operation, if possible. */
5425 return make_field_assignment (x);
5428 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5432 simplify_logical (rtx x)
5434 enum machine_mode mode = GET_MODE (x);
5435 rtx op0 = XEXP (x, 0);
5436 rtx op1 = XEXP (x, 1);
5439 switch (GET_CODE (x))
5442 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5443 insn (and may simplify more). */
5444 if (GET_CODE (op0) == XOR
5445 && rtx_equal_p (XEXP (op0, 0), op1)
5446 && ! side_effects_p (op1))
5447 x = gen_binary (AND, mode,
5448 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5451 if (GET_CODE (op0) == XOR
5452 && rtx_equal_p (XEXP (op0, 1), op1)
5453 && ! side_effects_p (op1))
5454 x = gen_binary (AND, mode,
5455 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5458 /* Similarly for (~(A ^ B)) & A. */
5459 if (GET_CODE (op0) == NOT
5460 && GET_CODE (XEXP (op0, 0)) == XOR
5461 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5462 && ! side_effects_p (op1))
5463 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5465 if (GET_CODE (op0) == NOT
5466 && GET_CODE (XEXP (op0, 0)) == XOR
5467 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5468 && ! side_effects_p (op1))
5469 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5471 /* We can call simplify_and_const_int only if we don't lose
5472 any (sign) bits when converting INTVAL (op1) to
5473 "unsigned HOST_WIDE_INT". */
5474 if (GET_CODE (op1) == CONST_INT
5475 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5476 || INTVAL (op1) > 0))
5478 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5480 /* If we have (ior (and (X C1) C2)) and the next restart would be
5481 the last, simplify this by making C1 as small as possible
5482 and then exit. Only do this if C1 actually changes: for now
5483 this only saves memory but, should this transformation be
5484 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5485 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5486 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5487 && GET_CODE (op1) == CONST_INT
5488 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5489 return gen_binary (IOR, mode,
5490 gen_binary (AND, mode, XEXP (op0, 0),
5491 GEN_INT (INTVAL (XEXP (op0, 1))
5492 & ~INTVAL (op1))), op1);
5494 if (GET_CODE (x) != AND)
5501 /* Convert (A | B) & A to A. */
5502 if (GET_CODE (op0) == IOR
5503 && (rtx_equal_p (XEXP (op0, 0), op1)
5504 || rtx_equal_p (XEXP (op0, 1), op1))
5505 && ! side_effects_p (XEXP (op0, 0))
5506 && ! side_effects_p (XEXP (op0, 1)))
5509 /* In the following group of tests (and those in case IOR below),
5510 we start with some combination of logical operations and apply
5511 the distributive law followed by the inverse distributive law.
5512 Most of the time, this results in no change. However, if some of
5513 the operands are the same or inverses of each other, simplifications
5516 For example, (and (ior A B) (not B)) can occur as the result of
5517 expanding a bit field assignment. When we apply the distributive
5518 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5519 which then simplifies to (and (A (not B))).
5521 If we have (and (ior A B) C), apply the distributive law and then
5522 the inverse distributive law to see if things simplify. */
5524 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5526 x = apply_distributive_law
5527 (gen_binary (GET_CODE (op0), mode,
5528 gen_binary (AND, mode, XEXP (op0, 0), op1),
5529 gen_binary (AND, mode, XEXP (op0, 1),
5531 if (GET_CODE (x) != AND)
5535 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5536 return apply_distributive_law
5537 (gen_binary (GET_CODE (op1), mode,
5538 gen_binary (AND, mode, XEXP (op1, 0), op0),
5539 gen_binary (AND, mode, XEXP (op1, 1),
5542 /* Similarly, taking advantage of the fact that
5543 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5545 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5546 return apply_distributive_law
5547 (gen_binary (XOR, mode,
5548 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5549 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5552 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5553 return apply_distributive_law
5554 (gen_binary (XOR, mode,
5555 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5556 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5560 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5561 if (GET_CODE (op1) == CONST_INT
5562 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5563 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5566 /* Convert (A & B) | A to A. */
5567 if (GET_CODE (op0) == AND
5568 && (rtx_equal_p (XEXP (op0, 0), op1)
5569 || rtx_equal_p (XEXP (op0, 1), op1))
5570 && ! side_effects_p (XEXP (op0, 0))
5571 && ! side_effects_p (XEXP (op0, 1)))
5574 /* If we have (ior (and A B) C), apply the distributive law and then
5575 the inverse distributive law to see if things simplify. */
5577 if (GET_CODE (op0) == AND)
5579 rtx tmp = apply_distributive_law
5580 (gen_binary (AND, mode,
5581 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5582 gen_binary (IOR, mode, XEXP (op0, 1),
5585 if (GET_CODE (tmp) != IOR
5586 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
5590 if (GET_CODE (op1) == AND)
5592 rtx tmp = apply_distributive_law
5593 (gen_binary (AND, mode,
5594 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5595 gen_binary (IOR, mode, XEXP (op1, 1),
5598 if (GET_CODE (tmp) != IOR
5599 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
5603 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5604 mode size to (rotate A CX). */
5606 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5607 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5608 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5609 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5610 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5611 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5612 == GET_MODE_BITSIZE (mode)))
5613 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5614 (GET_CODE (op0) == ASHIFT
5615 ? XEXP (op0, 1) : XEXP (op1, 1)));
5617 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5618 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5619 does not affect any of the bits in OP1, it can really be done
5620 as a PLUS and we can associate. We do this by seeing if OP1
5621 can be safely shifted left C bits. */
5622 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5623 && GET_CODE (XEXP (op0, 0)) == PLUS
5624 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5625 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5626 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5628 int count = INTVAL (XEXP (op0, 1));
5629 HOST_WIDE_INT mask = INTVAL (op1) << count;
5631 if (mask >> count == INTVAL (op1)
5632 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5634 SUBST (XEXP (XEXP (op0, 0), 1),
5635 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5642 /* If we are XORing two things that have no bits in common,
5643 convert them into an IOR. This helps to detect rotation encoded
5644 using those methods and possibly other simplifications. */
5646 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5647 && (nonzero_bits (op0, mode)
5648 & nonzero_bits (op1, mode)) == 0)
5649 return (gen_binary (IOR, mode, op0, op1));
5651 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5652 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5655 int num_negated = 0;
5657 if (GET_CODE (op0) == NOT)
5658 num_negated++, op0 = XEXP (op0, 0);
5659 if (GET_CODE (op1) == NOT)
5660 num_negated++, op1 = XEXP (op1, 0);
5662 if (num_negated == 2)
5664 SUBST (XEXP (x, 0), op0);
5665 SUBST (XEXP (x, 1), op1);
5667 else if (num_negated == 1)
5669 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5673 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5674 correspond to a machine insn or result in further simplifications
5675 if B is a constant. */
5677 if (GET_CODE (op0) == AND
5678 && rtx_equal_p (XEXP (op0, 1), op1)
5679 && ! side_effects_p (op1))
5680 return gen_binary (AND, mode,
5681 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5684 else if (GET_CODE (op0) == AND
5685 && rtx_equal_p (XEXP (op0, 0), op1)
5686 && ! side_effects_p (op1))
5687 return gen_binary (AND, mode,
5688 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5691 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5692 comparison if STORE_FLAG_VALUE is 1. */
5693 if (STORE_FLAG_VALUE == 1
5694 && op1 == const1_rtx
5695 && COMPARISON_P (op0)
5696 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5700 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5701 is (lt foo (const_int 0)), so we can perform the above
5702 simplification if STORE_FLAG_VALUE is 1. */
5704 if (STORE_FLAG_VALUE == 1
5705 && op1 == const1_rtx
5706 && GET_CODE (op0) == LSHIFTRT
5707 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5708 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5709 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5711 /* (xor (comparison foo bar) (const_int sign-bit))
5712 when STORE_FLAG_VALUE is the sign bit. */
5713 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5714 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5715 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5716 && op1 == const_true_rtx
5717 && COMPARISON_P (op0)
5718 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5731 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5732 operations" because they can be replaced with two more basic operations.
5733 ZERO_EXTEND is also considered "compound" because it can be replaced with
5734 an AND operation, which is simpler, though only one operation.
5736 The function expand_compound_operation is called with an rtx expression
5737 and will convert it to the appropriate shifts and AND operations,
5738 simplifying at each stage.
5740 The function make_compound_operation is called to convert an expression
5741 consisting of shifts and ANDs into the equivalent compound expression.
5742 It is the inverse of this function, loosely speaking. */
5745 expand_compound_operation (rtx x)
5747 unsigned HOST_WIDE_INT pos = 0, len;
5749 unsigned int modewidth;
5752 switch (GET_CODE (x))
5757 /* We can't necessarily use a const_int for a multiword mode;
5758 it depends on implicitly extending the value.
5759 Since we don't know the right way to extend it,
5760 we can't tell whether the implicit way is right.
5762 Even for a mode that is no wider than a const_int,
5763 we can't win, because we need to sign extend one of its bits through
5764 the rest of it, and we don't know which bit. */
5765 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5768 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5769 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5770 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5771 reloaded. If not for that, MEM's would very rarely be safe.
5773 Reject MODEs bigger than a word, because we might not be able
5774 to reference a two-register group starting with an arbitrary register
5775 (and currently gen_lowpart might crash for a SUBREG). */
5777 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5780 /* Reject MODEs that aren't scalar integers because turning vector
5781 or complex modes into shifts causes problems. */
5783 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5786 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5787 /* If the inner object has VOIDmode (the only way this can happen
5788 is if it is an ASM_OPERANDS), we can't do anything since we don't
5789 know how much masking to do. */
5798 /* ... fall through ... */
5801 /* If the operand is a CLOBBER, just return it. */
5802 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5805 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5806 || GET_CODE (XEXP (x, 2)) != CONST_INT
5807 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5810 /* Reject MODEs that aren't scalar integers because turning vector
5811 or complex modes into shifts causes problems. */
5813 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5816 len = INTVAL (XEXP (x, 1));
5817 pos = INTVAL (XEXP (x, 2));
5819 /* If this goes outside the object being extracted, replace the object
5820 with a (use (mem ...)) construct that only combine understands
5821 and is used only for this purpose. */
5822 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5823 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5825 if (BITS_BIG_ENDIAN)
5826 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5833 /* Convert sign extension to zero extension, if we know that the high
5834 bit is not set, as this is easier to optimize. It will be converted
5835 back to cheaper alternative in make_extraction. */
5836 if (GET_CODE (x) == SIGN_EXTEND
5837 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5838 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5839 & ~(((unsigned HOST_WIDE_INT)
5840 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5844 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5845 rtx temp2 = expand_compound_operation (temp);
5847 /* Make sure this is a profitable operation. */
5848 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5850 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5856 /* We can optimize some special cases of ZERO_EXTEND. */
5857 if (GET_CODE (x) == ZERO_EXTEND)
5859 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5860 know that the last value didn't have any inappropriate bits
5862 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5863 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5864 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5865 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5866 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5867 return XEXP (XEXP (x, 0), 0);
5869 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5870 if (GET_CODE (XEXP (x, 0)) == SUBREG
5871 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5872 && subreg_lowpart_p (XEXP (x, 0))
5873 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5874 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5875 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5876 return SUBREG_REG (XEXP (x, 0));
5878 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5879 is a comparison and STORE_FLAG_VALUE permits. This is like
5880 the first case, but it works even when GET_MODE (x) is larger
5881 than HOST_WIDE_INT. */
5882 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5883 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5884 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5885 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5886 <= HOST_BITS_PER_WIDE_INT)
5887 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5888 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5889 return XEXP (XEXP (x, 0), 0);
5891 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5892 if (GET_CODE (XEXP (x, 0)) == SUBREG
5893 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5894 && subreg_lowpart_p (XEXP (x, 0))
5895 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5896 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5897 <= HOST_BITS_PER_WIDE_INT)
5898 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5899 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5900 return SUBREG_REG (XEXP (x, 0));
5904 /* If we reach here, we want to return a pair of shifts. The inner
5905 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5906 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5907 logical depending on the value of UNSIGNEDP.
5909 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5910 converted into an AND of a shift.
5912 We must check for the case where the left shift would have a negative
5913 count. This can happen in a case like (x >> 31) & 255 on machines
5914 that can't shift by a constant. On those machines, we would first
5915 combine the shift with the AND to produce a variable-position
5916 extraction. Then the constant of 31 would be substituted in to produce
5917 a such a position. */
5919 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5920 if (modewidth + len >= pos)
5921 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5923 simplify_shift_const (NULL_RTX, ASHIFT,
5926 modewidth - pos - len),
5929 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5930 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5931 simplify_shift_const (NULL_RTX, LSHIFTRT,
5934 ((HOST_WIDE_INT) 1 << len) - 1);
5936 /* Any other cases we can't handle. */
5939 /* If we couldn't do this for some reason, return the original
5941 if (GET_CODE (tem) == CLOBBER)
5947 /* X is a SET which contains an assignment of one object into
5948 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5949 or certain SUBREGS). If possible, convert it into a series of
5952 We half-heartedly support variable positions, but do not at all
5953 support variable lengths. */
5956 expand_field_assignment (rtx x)
5959 rtx pos; /* Always counts from low bit. */
5962 enum machine_mode compute_mode;
5964 /* Loop until we find something we can't simplify. */
5967 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5968 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5970 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5971 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5972 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5974 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5975 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5977 inner = XEXP (SET_DEST (x), 0);
5978 len = INTVAL (XEXP (SET_DEST (x), 1));
5979 pos = XEXP (SET_DEST (x), 2);
5981 /* If the position is constant and spans the width of INNER,
5982 surround INNER with a USE to indicate this. */
5983 if (GET_CODE (pos) == CONST_INT
5984 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5985 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5987 if (BITS_BIG_ENDIAN)
5989 if (GET_CODE (pos) == CONST_INT)
5990 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5992 else if (GET_CODE (pos) == MINUS
5993 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5994 && (INTVAL (XEXP (pos, 1))
5995 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5996 /* If position is ADJUST - X, new position is X. */
5997 pos = XEXP (pos, 0);
5999 pos = gen_binary (MINUS, GET_MODE (pos),
6000 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
6006 /* A SUBREG between two modes that occupy the same numbers of words
6007 can be done by moving the SUBREG to the source. */
6008 else if (GET_CODE (SET_DEST (x)) == SUBREG
6009 /* We need SUBREGs to compute nonzero_bits properly. */
6010 && nonzero_sign_valid
6011 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6012 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6013 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6014 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6016 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6018 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6025 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6026 inner = SUBREG_REG (inner);
6028 compute_mode = GET_MODE (inner);
6030 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6031 if (! SCALAR_INT_MODE_P (compute_mode))
6033 enum machine_mode imode;
6035 /* Don't do anything for vector or complex integral types. */
6036 if (! FLOAT_MODE_P (compute_mode))
6039 /* Try to find an integral mode to pun with. */
6040 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6041 if (imode == BLKmode)
6044 compute_mode = imode;
6045 inner = gen_lowpart (imode, inner);
6048 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6049 if (len < HOST_BITS_PER_WIDE_INT)
6050 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6054 /* Now compute the equivalent expression. Make a copy of INNER
6055 for the SET_DEST in case it is a MEM into which we will substitute;
6056 we don't want shared RTL in that case. */
6058 (VOIDmode, copy_rtx (inner),
6059 gen_binary (IOR, compute_mode,
6060 gen_binary (AND, compute_mode,
6061 simplify_gen_unary (NOT, compute_mode,
6067 gen_binary (ASHIFT, compute_mode,
6068 gen_binary (AND, compute_mode,
6070 (compute_mode, SET_SRC (x)),
6078 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6079 it is an RTX that represents a variable starting position; otherwise,
6080 POS is the (constant) starting bit position (counted from the LSB).
6082 INNER may be a USE. This will occur when we started with a bitfield
6083 that went outside the boundary of the object in memory, which is
6084 allowed on most machines. To isolate this case, we produce a USE
6085 whose mode is wide enough and surround the MEM with it. The only
6086 code that understands the USE is this routine. If it is not removed,
6087 it will cause the resulting insn not to match.
6089 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6092 IN_DEST is nonzero if this is a reference in the destination of a
6093 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6094 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6097 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6098 ZERO_EXTRACT should be built even for bits starting at bit 0.
6100 MODE is the desired mode of the result (if IN_DEST == 0).
6102 The result is an RTX for the extraction or NULL_RTX if the target
6106 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6107 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6108 int in_dest, int in_compare)
6110 /* This mode describes the size of the storage area
6111 to fetch the overall value from. Within that, we
6112 ignore the POS lowest bits, etc. */
6113 enum machine_mode is_mode = GET_MODE (inner);
6114 enum machine_mode inner_mode;
6115 enum machine_mode wanted_inner_mode = byte_mode;
6116 enum machine_mode wanted_inner_reg_mode = word_mode;
6117 enum machine_mode pos_mode = word_mode;
6118 enum machine_mode extraction_mode = word_mode;
6119 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6122 rtx orig_pos_rtx = pos_rtx;
6123 HOST_WIDE_INT orig_pos;
6125 /* Get some information about INNER and get the innermost object. */
6126 if (GET_CODE (inner) == USE)
6127 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6128 /* We don't need to adjust the position because we set up the USE
6129 to pretend that it was a full-word object. */
6130 spans_byte = 1, inner = XEXP (inner, 0);
6131 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6133 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6134 consider just the QI as the memory to extract from.
6135 The subreg adds or removes high bits; its mode is
6136 irrelevant to the meaning of this extraction,
6137 since POS and LEN count from the lsb. */
6138 if (MEM_P (SUBREG_REG (inner)))
6139 is_mode = GET_MODE (SUBREG_REG (inner));
6140 inner = SUBREG_REG (inner);
6142 else if (GET_CODE (inner) == ASHIFT
6143 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6144 && pos_rtx == 0 && pos == 0
6145 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6147 /* We're extracting the least significant bits of an rtx
6148 (ashift X (const_int C)), where LEN > C. Extract the
6149 least significant (LEN - C) bits of X, giving an rtx
6150 whose mode is MODE, then shift it left C times. */
6151 new = make_extraction (mode, XEXP (inner, 0),
6152 0, 0, len - INTVAL (XEXP (inner, 1)),
6153 unsignedp, in_dest, in_compare);
6155 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6158 inner_mode = GET_MODE (inner);
6160 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6161 pos = INTVAL (pos_rtx), pos_rtx = 0;
6163 /* See if this can be done without an extraction. We never can if the
6164 width of the field is not the same as that of some integer mode. For
6165 registers, we can only avoid the extraction if the position is at the
6166 low-order bit and this is either not in the destination or we have the
6167 appropriate STRICT_LOW_PART operation available.
6169 For MEM, we can avoid an extract if the field starts on an appropriate
6170 boundary and we can change the mode of the memory reference. However,
6171 we cannot directly access the MEM if we have a USE and the underlying
6172 MEM is not TMODE. This combination means that MEM was being used in a
6173 context where bits outside its mode were being referenced; that is only
6174 valid in bit-field insns. */
6176 if (tmode != BLKmode
6177 && ! (spans_byte && inner_mode != tmode)
6178 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6182 && have_insn_for (STRICT_LOW_PART, tmode))))
6183 || (MEM_P (inner) && pos_rtx == 0
6185 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6186 : BITS_PER_UNIT)) == 0
6187 /* We can't do this if we are widening INNER_MODE (it
6188 may not be aligned, for one thing). */
6189 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6190 && (inner_mode == tmode
6191 || (! mode_dependent_address_p (XEXP (inner, 0))
6192 && ! MEM_VOLATILE_P (inner))))))
6194 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6195 field. If the original and current mode are the same, we need not
6196 adjust the offset. Otherwise, we do if bytes big endian.
6198 If INNER is not a MEM, get a piece consisting of just the field
6199 of interest (in this case POS % BITS_PER_WORD must be 0). */
6203 HOST_WIDE_INT offset;
6205 /* POS counts from lsb, but make OFFSET count in memory order. */
6206 if (BYTES_BIG_ENDIAN)
6207 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6209 offset = pos / BITS_PER_UNIT;
6211 new = adjust_address_nv (inner, tmode, offset);
6213 else if (REG_P (inner))
6215 if (tmode != inner_mode)
6217 /* We can't call gen_lowpart in a DEST since we
6218 always want a SUBREG (see below) and it would sometimes
6219 return a new hard register. */
6222 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6224 if (WORDS_BIG_ENDIAN
6225 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6226 final_word = ((GET_MODE_SIZE (inner_mode)
6227 - GET_MODE_SIZE (tmode))
6228 / UNITS_PER_WORD) - final_word;
6230 final_word *= UNITS_PER_WORD;
6231 if (BYTES_BIG_ENDIAN &&
6232 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6233 final_word += (GET_MODE_SIZE (inner_mode)
6234 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6236 /* Avoid creating invalid subregs, for example when
6237 simplifying (x>>32)&255. */
6238 if (final_word >= GET_MODE_SIZE (inner_mode))
6241 new = gen_rtx_SUBREG (tmode, inner, final_word);
6244 new = gen_lowpart (tmode, inner);
6250 new = force_to_mode (inner, tmode,
6251 len >= HOST_BITS_PER_WIDE_INT
6252 ? ~(unsigned HOST_WIDE_INT) 0
6253 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6256 /* If this extraction is going into the destination of a SET,
6257 make a STRICT_LOW_PART unless we made a MEM. */
6260 return (MEM_P (new) ? new
6261 : (GET_CODE (new) != SUBREG
6262 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6263 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6268 if (GET_CODE (new) == CONST_INT)
6269 return gen_int_mode (INTVAL (new), mode);
6271 /* If we know that no extraneous bits are set, and that the high
6272 bit is not set, convert the extraction to the cheaper of
6273 sign and zero extension, that are equivalent in these cases. */
6274 if (flag_expensive_optimizations
6275 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6276 && ((nonzero_bits (new, tmode)
6277 & ~(((unsigned HOST_WIDE_INT)
6278 GET_MODE_MASK (tmode))
6282 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6283 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6285 /* Prefer ZERO_EXTENSION, since it gives more information to
6287 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6292 /* Otherwise, sign- or zero-extend unless we already are in the
6295 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6299 /* Unless this is a COMPARE or we have a funny memory reference,
6300 don't do anything with zero-extending field extracts starting at
6301 the low-order bit since they are simple AND operations. */
6302 if (pos_rtx == 0 && pos == 0 && ! in_dest
6303 && ! in_compare && ! spans_byte && unsignedp)
6306 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6307 we would be spanning bytes or if the position is not a constant and the
6308 length is not 1. In all other cases, we would only be going outside
6309 our object in cases when an original shift would have been
6311 if (! spans_byte && MEM_P (inner)
6312 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6313 || (pos_rtx != 0 && len != 1)))
6316 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6317 and the mode for the result. */
6318 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6320 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6321 pos_mode = mode_for_extraction (EP_insv, 2);
6322 extraction_mode = mode_for_extraction (EP_insv, 3);
6325 if (! in_dest && unsignedp
6326 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6328 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6329 pos_mode = mode_for_extraction (EP_extzv, 3);
6330 extraction_mode = mode_for_extraction (EP_extzv, 0);
6333 if (! in_dest && ! unsignedp
6334 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6336 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6337 pos_mode = mode_for_extraction (EP_extv, 3);
6338 extraction_mode = mode_for_extraction (EP_extv, 0);
6341 /* Never narrow an object, since that might not be safe. */
6343 if (mode != VOIDmode
6344 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6345 extraction_mode = mode;
6347 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6348 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6349 pos_mode = GET_MODE (pos_rtx);
6351 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6352 if we have to change the mode of memory and cannot, the desired mode is
6355 wanted_inner_mode = wanted_inner_reg_mode;
6356 else if (inner_mode != wanted_inner_mode
6357 && (mode_dependent_address_p (XEXP (inner, 0))
6358 || MEM_VOLATILE_P (inner)))
6359 wanted_inner_mode = extraction_mode;
6363 if (BITS_BIG_ENDIAN)
6365 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6366 BITS_BIG_ENDIAN style. If position is constant, compute new
6367 position. Otherwise, build subtraction.
6368 Note that POS is relative to the mode of the original argument.
6369 If it's a MEM we need to recompute POS relative to that.
6370 However, if we're extracting from (or inserting into) a register,
6371 we want to recompute POS relative to wanted_inner_mode. */
6372 int width = (MEM_P (inner)
6373 ? GET_MODE_BITSIZE (is_mode)
6374 : GET_MODE_BITSIZE (wanted_inner_mode));
6377 pos = width - len - pos;
6380 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6381 /* POS may be less than 0 now, but we check for that below.
6382 Note that it can only be less than 0 if !MEM_P (inner). */
6385 /* If INNER has a wider mode, make it smaller. If this is a constant
6386 extract, try to adjust the byte to point to the byte containing
6388 if (wanted_inner_mode != VOIDmode
6389 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6391 && (inner_mode == wanted_inner_mode
6392 || (! mode_dependent_address_p (XEXP (inner, 0))
6393 && ! MEM_VOLATILE_P (inner))))))
6397 /* The computations below will be correct if the machine is big
6398 endian in both bits and bytes or little endian in bits and bytes.
6399 If it is mixed, we must adjust. */
6401 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6402 adjust OFFSET to compensate. */
6403 if (BYTES_BIG_ENDIAN
6405 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6406 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6408 /* If this is a constant position, we can move to the desired byte. */
6411 offset += pos / BITS_PER_UNIT;
6412 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6415 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6417 && is_mode != wanted_inner_mode)
6418 offset = (GET_MODE_SIZE (is_mode)
6419 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6421 if (offset != 0 || inner_mode != wanted_inner_mode)
6422 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6425 /* If INNER is not memory, we can always get it into the proper mode. If we
6426 are changing its mode, POS must be a constant and smaller than the size
6428 else if (!MEM_P (inner))
6430 if (GET_MODE (inner) != wanted_inner_mode
6432 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6435 inner = force_to_mode (inner, wanted_inner_mode,
6437 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6438 ? ~(unsigned HOST_WIDE_INT) 0
6439 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6444 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6445 have to zero extend. Otherwise, we can just use a SUBREG. */
6447 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6449 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6451 /* If we know that no extraneous bits are set, and that the high
6452 bit is not set, convert extraction to cheaper one - either
6453 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6455 if (flag_expensive_optimizations
6456 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6457 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6458 & ~(((unsigned HOST_WIDE_INT)
6459 GET_MODE_MASK (GET_MODE (pos_rtx)))
6463 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6465 /* Prefer ZERO_EXTENSION, since it gives more information to
6467 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6472 else if (pos_rtx != 0
6473 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6474 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6476 /* Make POS_RTX unless we already have it and it is correct. If we don't
6477 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6479 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6480 pos_rtx = orig_pos_rtx;
6482 else if (pos_rtx == 0)
6483 pos_rtx = GEN_INT (pos);
6485 /* Make the required operation. See if we can use existing rtx. */
6486 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6487 extraction_mode, inner, GEN_INT (len), pos_rtx);
6489 new = gen_lowpart (mode, new);
6494 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6495 with any other operations in X. Return X without that shift if so. */
6498 extract_left_shift (rtx x, int count)
6500 enum rtx_code code = GET_CODE (x);
6501 enum machine_mode mode = GET_MODE (x);
6507 /* This is the shift itself. If it is wide enough, we will return
6508 either the value being shifted if the shift count is equal to
6509 COUNT or a shift for the difference. */
6510 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6511 && INTVAL (XEXP (x, 1)) >= count)
6512 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6513 INTVAL (XEXP (x, 1)) - count);
6517 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6518 return simplify_gen_unary (code, mode, tem, mode);
6522 case PLUS: case IOR: case XOR: case AND:
6523 /* If we can safely shift this constant and we find the inner shift,
6524 make a new operation. */
6525 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6526 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6527 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6528 return gen_binary (code, mode, tem,
6529 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6540 /* Look at the expression rooted at X. Look for expressions
6541 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6542 Form these expressions.
6544 Return the new rtx, usually just X.
6546 Also, for machines like the VAX that don't have logical shift insns,
6547 try to convert logical to arithmetic shift operations in cases where
6548 they are equivalent. This undoes the canonicalizations to logical
6549 shifts done elsewhere.
6551 We try, as much as possible, to re-use rtl expressions to save memory.
6553 IN_CODE says what kind of expression we are processing. Normally, it is
6554 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6555 being kludges), it is MEM. When processing the arguments of a comparison
6556 or a COMPARE against zero, it is COMPARE. */
6559 make_compound_operation (rtx x, enum rtx_code in_code)
6561 enum rtx_code code = GET_CODE (x);
6562 enum machine_mode mode = GET_MODE (x);
6563 int mode_width = GET_MODE_BITSIZE (mode);
6565 enum rtx_code next_code;
6571 /* Select the code to be used in recursive calls. Once we are inside an
6572 address, we stay there. If we have a comparison, set to COMPARE,
6573 but once inside, go back to our default of SET. */
6575 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6576 : ((code == COMPARE || COMPARISON_P (x))
6577 && XEXP (x, 1) == const0_rtx) ? COMPARE
6578 : in_code == COMPARE ? SET : in_code);
6580 /* Process depending on the code of this operation. If NEW is set
6581 nonzero, it will be returned. */
6586 /* Convert shifts by constants into multiplications if inside
6588 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6589 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6590 && INTVAL (XEXP (x, 1)) >= 0)
6592 new = make_compound_operation (XEXP (x, 0), next_code);
6593 new = gen_rtx_MULT (mode, new,
6594 GEN_INT ((HOST_WIDE_INT) 1
6595 << INTVAL (XEXP (x, 1))));
6600 /* If the second operand is not a constant, we can't do anything
6602 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6605 /* If the constant is a power of two minus one and the first operand
6606 is a logical right shift, make an extraction. */
6607 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6608 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6610 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6611 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6612 0, in_code == COMPARE);
6615 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6616 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6617 && subreg_lowpart_p (XEXP (x, 0))
6618 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6619 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6621 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6623 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6624 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6625 0, in_code == COMPARE);
6627 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6628 else if ((GET_CODE (XEXP (x, 0)) == XOR
6629 || GET_CODE (XEXP (x, 0)) == IOR)
6630 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6631 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6632 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6634 /* Apply the distributive law, and then try to make extractions. */
6635 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6636 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6638 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6640 new = make_compound_operation (new, in_code);
6643 /* If we are have (and (rotate X C) M) and C is larger than the number
6644 of bits in M, this is an extraction. */
6646 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6647 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6648 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6649 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6651 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6652 new = make_extraction (mode, new,
6653 (GET_MODE_BITSIZE (mode)
6654 - INTVAL (XEXP (XEXP (x, 0), 1))),
6655 NULL_RTX, i, 1, 0, in_code == COMPARE);
6658 /* On machines without logical shifts, if the operand of the AND is
6659 a logical shift and our mask turns off all the propagated sign
6660 bits, we can replace the logical shift with an arithmetic shift. */
6661 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6662 && !have_insn_for (LSHIFTRT, mode)
6663 && have_insn_for (ASHIFTRT, mode)
6664 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6665 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6666 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6667 && mode_width <= HOST_BITS_PER_WIDE_INT)
6669 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6671 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6672 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6674 gen_rtx_ASHIFTRT (mode,
6675 make_compound_operation
6676 (XEXP (XEXP (x, 0), 0), next_code),
6677 XEXP (XEXP (x, 0), 1)));
6680 /* If the constant is one less than a power of two, this might be
6681 representable by an extraction even if no shift is present.
6682 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6683 we are in a COMPARE. */
6684 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6685 new = make_extraction (mode,
6686 make_compound_operation (XEXP (x, 0),
6688 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6690 /* If we are in a comparison and this is an AND with a power of two,
6691 convert this into the appropriate bit extract. */
6692 else if (in_code == COMPARE
6693 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6694 new = make_extraction (mode,
6695 make_compound_operation (XEXP (x, 0),
6697 i, NULL_RTX, 1, 1, 0, 1);
6702 /* If the sign bit is known to be zero, replace this with an
6703 arithmetic shift. */
6704 if (have_insn_for (ASHIFTRT, mode)
6705 && ! have_insn_for (LSHIFTRT, mode)
6706 && mode_width <= HOST_BITS_PER_WIDE_INT
6707 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6709 new = gen_rtx_ASHIFTRT (mode,
6710 make_compound_operation (XEXP (x, 0),
6716 /* ... fall through ... */
6722 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6723 this is a SIGN_EXTRACT. */
6724 if (GET_CODE (rhs) == CONST_INT
6725 && GET_CODE (lhs) == ASHIFT
6726 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6727 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6729 new = make_compound_operation (XEXP (lhs, 0), next_code);
6730 new = make_extraction (mode, new,
6731 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6732 NULL_RTX, mode_width - INTVAL (rhs),
6733 code == LSHIFTRT, 0, in_code == COMPARE);
6737 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6738 If so, try to merge the shifts into a SIGN_EXTEND. We could
6739 also do this for some cases of SIGN_EXTRACT, but it doesn't
6740 seem worth the effort; the case checked for occurs on Alpha. */
6743 && ! (GET_CODE (lhs) == SUBREG
6744 && (OBJECT_P (SUBREG_REG (lhs))))
6745 && GET_CODE (rhs) == CONST_INT
6746 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6747 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6748 new = make_extraction (mode, make_compound_operation (new, next_code),
6749 0, NULL_RTX, mode_width - INTVAL (rhs),
6750 code == LSHIFTRT, 0, in_code == COMPARE);
6755 /* Call ourselves recursively on the inner expression. If we are
6756 narrowing the object and it has a different RTL code from
6757 what it originally did, do this SUBREG as a force_to_mode. */
6759 tem = make_compound_operation (SUBREG_REG (x), in_code);
6760 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6761 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6762 && subreg_lowpart_p (x))
6764 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6767 /* If we have something other than a SUBREG, we might have
6768 done an expansion, so rerun ourselves. */
6769 if (GET_CODE (newer) != SUBREG)
6770 newer = make_compound_operation (newer, in_code);
6775 /* If this is a paradoxical subreg, and the new code is a sign or
6776 zero extension, omit the subreg and widen the extension. If it
6777 is a regular subreg, we can still get rid of the subreg by not
6778 widening so much, or in fact removing the extension entirely. */
6779 if ((GET_CODE (tem) == SIGN_EXTEND
6780 || GET_CODE (tem) == ZERO_EXTEND)
6781 && subreg_lowpart_p (x))
6783 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6784 || (GET_MODE_SIZE (mode) >
6785 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6787 if (! SCALAR_INT_MODE_P (mode))
6789 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6792 tem = gen_lowpart (mode, XEXP (tem, 0));
6803 x = gen_lowpart (mode, new);
6804 code = GET_CODE (x);
6807 /* Now recursively process each operand of this operation. */
6808 fmt = GET_RTX_FORMAT (code);
6809 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6812 new = make_compound_operation (XEXP (x, i), next_code);
6813 SUBST (XEXP (x, i), new);
6819 /* Given M see if it is a value that would select a field of bits
6820 within an item, but not the entire word. Return -1 if not.
6821 Otherwise, return the starting position of the field, where 0 is the
6824 *PLEN is set to the length of the field. */
6827 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6829 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6830 int pos = exact_log2 (m & -m);
6834 /* Now shift off the low-order zero bits and see if we have a
6835 power of two minus 1. */
6836 len = exact_log2 ((m >> pos) + 1);
6845 /* See if X can be simplified knowing that we will only refer to it in
6846 MODE and will only refer to those bits that are nonzero in MASK.
6847 If other bits are being computed or if masking operations are done
6848 that select a superset of the bits in MASK, they can sometimes be
6851 Return a possibly simplified expression, but always convert X to
6852 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6854 Also, if REG is nonzero and X is a register equal in value to REG,
6857 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6858 are all off in X. This is used when X will be complemented, by either
6859 NOT, NEG, or XOR. */
6862 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6863 rtx reg, int just_select)
6865 enum rtx_code code = GET_CODE (x);
6866 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6867 enum machine_mode op_mode;
6868 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6871 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6872 code below will do the wrong thing since the mode of such an
6873 expression is VOIDmode.
6875 Also do nothing if X is a CLOBBER; this can happen if X was
6876 the return value from a call to gen_lowpart. */
6877 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6880 /* We want to perform the operation is its present mode unless we know
6881 that the operation is valid in MODE, in which case we do the operation
6883 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6884 && have_insn_for (code, mode))
6885 ? mode : GET_MODE (x));
6887 /* It is not valid to do a right-shift in a narrower mode
6888 than the one it came in with. */
6889 if ((code == LSHIFTRT || code == ASHIFTRT)
6890 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6891 op_mode = GET_MODE (x);
6893 /* Truncate MASK to fit OP_MODE. */
6895 mask &= GET_MODE_MASK (op_mode);
6897 /* When we have an arithmetic operation, or a shift whose count we
6898 do not know, we need to assume that all bits up to the highest-order
6899 bit in MASK will be needed. This is how we form such a mask. */
6900 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6901 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6903 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6906 /* Determine what bits of X are guaranteed to be (non)zero. */
6907 nonzero = nonzero_bits (x, mode);
6909 /* If none of the bits in X are needed, return a zero. */
6910 if (! just_select && (nonzero & mask) == 0)
6913 /* If X is a CONST_INT, return a new one. Do this here since the
6914 test below will fail. */
6915 if (GET_CODE (x) == CONST_INT)
6917 if (SCALAR_INT_MODE_P (mode))
6918 return gen_int_mode (INTVAL (x) & mask, mode);
6921 x = GEN_INT (INTVAL (x) & mask);
6922 return gen_lowpart_common (mode, x);
6926 /* If X is narrower than MODE and we want all the bits in X's mode, just
6927 get X in the proper mode. */
6928 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6929 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6930 return gen_lowpart (mode, x);
6935 /* If X is a (clobber (const_int)), return it since we know we are
6936 generating something that won't match. */
6940 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6941 spanned the boundary of the MEM. If we are now masking so it is
6942 within that boundary, we don't need the USE any more. */
6943 if (! BITS_BIG_ENDIAN
6944 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6945 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6952 x = expand_compound_operation (x);
6953 if (GET_CODE (x) != code)
6954 return force_to_mode (x, mode, mask, reg, next_select);
6958 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6959 || rtx_equal_p (reg, get_last_value (x))))
6964 if (subreg_lowpart_p (x)
6965 /* We can ignore the effect of this SUBREG if it narrows the mode or
6966 if the constant masks to zero all the bits the mode doesn't
6968 && ((GET_MODE_SIZE (GET_MODE (x))
6969 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6971 & GET_MODE_MASK (GET_MODE (x))
6972 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6973 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6977 /* If this is an AND with a constant, convert it into an AND
6978 whose constant is the AND of that constant with MASK. If it
6979 remains an AND of MASK, delete it since it is redundant. */
6981 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6983 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6984 mask & INTVAL (XEXP (x, 1)));
6986 /* If X is still an AND, see if it is an AND with a mask that
6987 is just some low-order bits. If so, and it is MASK, we don't
6990 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6991 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6995 /* If it remains an AND, try making another AND with the bits
6996 in the mode mask that aren't in MASK turned on. If the
6997 constant in the AND is wide enough, this might make a
6998 cheaper constant. */
7000 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7001 && GET_MODE_MASK (GET_MODE (x)) != mask
7002 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7004 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7005 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7006 int width = GET_MODE_BITSIZE (GET_MODE (x));
7009 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7010 number, sign extend it. */
7011 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7012 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7013 cval |= (HOST_WIDE_INT) -1 << width;
7015 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
7016 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7026 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7027 low-order bits (as in an alignment operation) and FOO is already
7028 aligned to that boundary, mask C1 to that boundary as well.
7029 This may eliminate that PLUS and, later, the AND. */
7032 unsigned int width = GET_MODE_BITSIZE (mode);
7033 unsigned HOST_WIDE_INT smask = mask;
7035 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7036 number, sign extend it. */
7038 if (width < HOST_BITS_PER_WIDE_INT
7039 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7040 smask |= (HOST_WIDE_INT) -1 << width;
7042 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7043 && exact_log2 (- smask) >= 0
7044 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7045 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7046 return force_to_mode (plus_constant (XEXP (x, 0),
7047 (INTVAL (XEXP (x, 1)) & smask)),
7048 mode, smask, reg, next_select);
7051 /* ... fall through ... */
7054 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7055 most significant bit in MASK since carries from those bits will
7056 affect the bits we are interested in. */
7061 /* If X is (minus C Y) where C's least set bit is larger than any bit
7062 in the mask, then we may replace with (neg Y). */
7063 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7064 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7065 & -INTVAL (XEXP (x, 0))))
7068 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7070 return force_to_mode (x, mode, mask, reg, next_select);
7073 /* Similarly, if C contains every bit in the fuller_mask, then we may
7074 replace with (not Y). */
7075 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7076 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7077 == INTVAL (XEXP (x, 0))))
7079 x = simplify_gen_unary (NOT, GET_MODE (x),
7080 XEXP (x, 1), GET_MODE (x));
7081 return force_to_mode (x, mode, mask, reg, next_select);
7089 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7090 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7091 operation which may be a bitfield extraction. Ensure that the
7092 constant we form is not wider than the mode of X. */
7094 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7095 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7096 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7097 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7098 && GET_CODE (XEXP (x, 1)) == CONST_INT
7099 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7100 + floor_log2 (INTVAL (XEXP (x, 1))))
7101 < GET_MODE_BITSIZE (GET_MODE (x)))
7102 && (INTVAL (XEXP (x, 1))
7103 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7105 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7106 << INTVAL (XEXP (XEXP (x, 0), 1)));
7107 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7108 XEXP (XEXP (x, 0), 0), temp);
7109 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7110 XEXP (XEXP (x, 0), 1));
7111 return force_to_mode (x, mode, mask, reg, next_select);
7115 /* For most binary operations, just propagate into the operation and
7116 change the mode if we have an operation of that mode. */
7118 op0 = gen_lowpart (op_mode,
7119 force_to_mode (XEXP (x, 0), mode, mask,
7121 op1 = gen_lowpart (op_mode,
7122 force_to_mode (XEXP (x, 1), mode, mask,
7125 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7126 x = gen_binary (code, op_mode, op0, op1);
7130 /* For left shifts, do the same, but just for the first operand.
7131 However, we cannot do anything with shifts where we cannot
7132 guarantee that the counts are smaller than the size of the mode
7133 because such a count will have a different meaning in a
7136 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7137 && INTVAL (XEXP (x, 1)) >= 0
7138 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7139 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7140 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7141 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7144 /* If the shift count is a constant and we can do arithmetic in
7145 the mode of the shift, refine which bits we need. Otherwise, use the
7146 conservative form of the mask. */
7147 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7148 && INTVAL (XEXP (x, 1)) >= 0
7149 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7150 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7151 mask >>= INTVAL (XEXP (x, 1));
7155 op0 = gen_lowpart (op_mode,
7156 force_to_mode (XEXP (x, 0), op_mode,
7157 mask, reg, next_select));
7159 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7160 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7164 /* Here we can only do something if the shift count is a constant,
7165 this shift constant is valid for the host, and we can do arithmetic
7168 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7169 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7170 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7172 rtx inner = XEXP (x, 0);
7173 unsigned HOST_WIDE_INT inner_mask;
7175 /* Select the mask of the bits we need for the shift operand. */
7176 inner_mask = mask << INTVAL (XEXP (x, 1));
7178 /* We can only change the mode of the shift if we can do arithmetic
7179 in the mode of the shift and INNER_MASK is no wider than the
7180 width of X's mode. */
7181 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7182 op_mode = GET_MODE (x);
7184 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7186 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7187 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7190 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7191 shift and AND produces only copies of the sign bit (C2 is one less
7192 than a power of two), we can do this with just a shift. */
7194 if (GET_CODE (x) == LSHIFTRT
7195 && GET_CODE (XEXP (x, 1)) == CONST_INT
7196 /* The shift puts one of the sign bit copies in the least significant
7198 && ((INTVAL (XEXP (x, 1))
7199 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7200 >= GET_MODE_BITSIZE (GET_MODE (x)))
7201 && exact_log2 (mask + 1) >= 0
7202 /* Number of bits left after the shift must be more than the mask
7204 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7205 <= GET_MODE_BITSIZE (GET_MODE (x)))
7206 /* Must be more sign bit copies than the mask needs. */
7207 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7208 >= exact_log2 (mask + 1)))
7209 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7210 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7211 - exact_log2 (mask + 1)));
7216 /* If we are just looking for the sign bit, we don't need this shift at
7217 all, even if it has a variable count. */
7218 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7219 && (mask == ((unsigned HOST_WIDE_INT) 1
7220 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7221 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7223 /* If this is a shift by a constant, get a mask that contains those bits
7224 that are not copies of the sign bit. We then have two cases: If
7225 MASK only includes those bits, this can be a logical shift, which may
7226 allow simplifications. If MASK is a single-bit field not within
7227 those bits, we are requesting a copy of the sign bit and hence can
7228 shift the sign bit to the appropriate location. */
7230 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7231 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7235 /* If the considered data is wider than HOST_WIDE_INT, we can't
7236 represent a mask for all its bits in a single scalar.
7237 But we only care about the lower bits, so calculate these. */
7239 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7241 nonzero = ~(HOST_WIDE_INT) 0;
7243 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7244 is the number of bits a full-width mask would have set.
7245 We need only shift if these are fewer than nonzero can
7246 hold. If not, we must keep all bits set in nonzero. */
7248 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7249 < HOST_BITS_PER_WIDE_INT)
7250 nonzero >>= INTVAL (XEXP (x, 1))
7251 + HOST_BITS_PER_WIDE_INT
7252 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7256 nonzero = GET_MODE_MASK (GET_MODE (x));
7257 nonzero >>= INTVAL (XEXP (x, 1));
7260 if ((mask & ~nonzero) == 0
7261 || (i = exact_log2 (mask)) >= 0)
7263 x = simplify_shift_const
7264 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7265 i < 0 ? INTVAL (XEXP (x, 1))
7266 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7268 if (GET_CODE (x) != ASHIFTRT)
7269 return force_to_mode (x, mode, mask, reg, next_select);
7273 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7274 even if the shift count isn't a constant. */
7276 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7280 /* If this is a zero- or sign-extension operation that just affects bits
7281 we don't care about, remove it. Be sure the call above returned
7282 something that is still a shift. */
7284 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7285 && GET_CODE (XEXP (x, 1)) == CONST_INT
7286 && INTVAL (XEXP (x, 1)) >= 0
7287 && (INTVAL (XEXP (x, 1))
7288 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7289 && GET_CODE (XEXP (x, 0)) == ASHIFT
7290 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7291 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7298 /* If the shift count is constant and we can do computations
7299 in the mode of X, compute where the bits we care about are.
7300 Otherwise, we can't do anything. Don't change the mode of
7301 the shift or propagate MODE into the shift, though. */
7302 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7303 && INTVAL (XEXP (x, 1)) >= 0)
7305 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7306 GET_MODE (x), GEN_INT (mask),
7308 if (temp && GET_CODE (temp) == CONST_INT)
7310 force_to_mode (XEXP (x, 0), GET_MODE (x),
7311 INTVAL (temp), reg, next_select));
7316 /* If we just want the low-order bit, the NEG isn't needed since it
7317 won't change the low-order bit. */
7319 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7321 /* We need any bits less significant than the most significant bit in
7322 MASK since carries from those bits will affect the bits we are
7328 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7329 same as the XOR case above. Ensure that the constant we form is not
7330 wider than the mode of X. */
7332 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7333 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7334 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7335 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7336 < GET_MODE_BITSIZE (GET_MODE (x)))
7337 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7339 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7341 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7342 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7344 return force_to_mode (x, mode, mask, reg, next_select);
7347 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7348 use the full mask inside the NOT. */
7352 op0 = gen_lowpart (op_mode,
7353 force_to_mode (XEXP (x, 0), mode, mask,
7355 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7356 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7360 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7361 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7362 which is equal to STORE_FLAG_VALUE. */
7363 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7364 && GET_MODE (XEXP (x, 0)) == mode
7365 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7366 && (nonzero_bits (XEXP (x, 0), mode)
7367 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7368 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7373 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7374 written in a narrower mode. We play it safe and do not do so. */
7377 gen_lowpart (GET_MODE (x),
7378 force_to_mode (XEXP (x, 1), mode,
7379 mask, reg, next_select)));
7381 gen_lowpart (GET_MODE (x),
7382 force_to_mode (XEXP (x, 2), mode,
7383 mask, reg, next_select)));
7390 /* Ensure we return a value of the proper mode. */
7391 return gen_lowpart (mode, x);
7394 /* Return nonzero if X is an expression that has one of two values depending on
7395 whether some other value is zero or nonzero. In that case, we return the
7396 value that is being tested, *PTRUE is set to the value if the rtx being
7397 returned has a nonzero value, and *PFALSE is set to the other alternative.
7399 If we return zero, we set *PTRUE and *PFALSE to X. */
7402 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7404 enum machine_mode mode = GET_MODE (x);
7405 enum rtx_code code = GET_CODE (x);
7406 rtx cond0, cond1, true0, true1, false0, false1;
7407 unsigned HOST_WIDE_INT nz;
7409 /* If we are comparing a value against zero, we are done. */
7410 if ((code == NE || code == EQ)
7411 && XEXP (x, 1) == const0_rtx)
7413 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7414 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7418 /* If this is a unary operation whose operand has one of two values, apply
7419 our opcode to compute those values. */
7420 else if (UNARY_P (x)
7421 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7423 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7424 *pfalse = simplify_gen_unary (code, mode, false0,
7425 GET_MODE (XEXP (x, 0)));
7429 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7430 make can't possibly match and would suppress other optimizations. */
7431 else if (code == COMPARE)
7434 /* If this is a binary operation, see if either side has only one of two
7435 values. If either one does or if both do and they are conditional on
7436 the same value, compute the new true and false values. */
7437 else if (BINARY_P (x))
7439 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7440 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7442 if ((cond0 != 0 || cond1 != 0)
7443 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7445 /* If if_then_else_cond returned zero, then true/false are the
7446 same rtl. We must copy one of them to prevent invalid rtl
7449 true0 = copy_rtx (true0);
7450 else if (cond1 == 0)
7451 true1 = copy_rtx (true1);
7453 *ptrue = gen_binary (code, mode, true0, true1);
7454 *pfalse = gen_binary (code, mode, false0, false1);
7455 return cond0 ? cond0 : cond1;
7458 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7459 operands is zero when the other is nonzero, and vice-versa,
7460 and STORE_FLAG_VALUE is 1 or -1. */
7462 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7463 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7465 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7467 rtx op0 = XEXP (XEXP (x, 0), 1);
7468 rtx op1 = XEXP (XEXP (x, 1), 1);
7470 cond0 = XEXP (XEXP (x, 0), 0);
7471 cond1 = XEXP (XEXP (x, 1), 0);
7473 if (COMPARISON_P (cond0)
7474 && COMPARISON_P (cond1)
7475 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7476 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7477 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7478 || ((swap_condition (GET_CODE (cond0))
7479 == combine_reversed_comparison_code (cond1))
7480 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7481 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7482 && ! side_effects_p (x))
7484 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7485 *pfalse = gen_binary (MULT, mode,
7487 ? simplify_gen_unary (NEG, mode, op1,
7495 /* Similarly for MULT, AND and UMIN, except that for these the result
7497 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7498 && (code == MULT || code == AND || code == UMIN)
7499 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7501 cond0 = XEXP (XEXP (x, 0), 0);
7502 cond1 = XEXP (XEXP (x, 1), 0);
7504 if (COMPARISON_P (cond0)
7505 && COMPARISON_P (cond1)
7506 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7507 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7508 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7509 || ((swap_condition (GET_CODE (cond0))
7510 == combine_reversed_comparison_code (cond1))
7511 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7512 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7513 && ! side_effects_p (x))
7515 *ptrue = *pfalse = const0_rtx;
7521 else if (code == IF_THEN_ELSE)
7523 /* If we have IF_THEN_ELSE already, extract the condition and
7524 canonicalize it if it is NE or EQ. */
7525 cond0 = XEXP (x, 0);
7526 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7527 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7528 return XEXP (cond0, 0);
7529 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7531 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7532 return XEXP (cond0, 0);
7538 /* If X is a SUBREG, we can narrow both the true and false values
7539 if the inner expression, if there is a condition. */
7540 else if (code == SUBREG
7541 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7544 true0 = simplify_gen_subreg (mode, true0,
7545 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7546 false0 = simplify_gen_subreg (mode, false0,
7547 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7548 if (true0 && false0)
7556 /* If X is a constant, this isn't special and will cause confusions
7557 if we treat it as such. Likewise if it is equivalent to a constant. */
7558 else if (CONSTANT_P (x)
7559 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7562 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7563 will be least confusing to the rest of the compiler. */
7564 else if (mode == BImode)
7566 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7570 /* If X is known to be either 0 or -1, those are the true and
7571 false values when testing X. */
7572 else if (x == constm1_rtx || x == const0_rtx
7573 || (mode != VOIDmode
7574 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7576 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7580 /* Likewise for 0 or a single bit. */
7581 else if (SCALAR_INT_MODE_P (mode)
7582 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7583 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7585 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7589 /* Otherwise fail; show no condition with true and false values the same. */
7590 *ptrue = *pfalse = x;
7594 /* Return the value of expression X given the fact that condition COND
7595 is known to be true when applied to REG as its first operand and VAL
7596 as its second. X is known to not be shared and so can be modified in
7599 We only handle the simplest cases, and specifically those cases that
7600 arise with IF_THEN_ELSE expressions. */
7603 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7605 enum rtx_code code = GET_CODE (x);
7610 if (side_effects_p (x))
7613 /* If either operand of the condition is a floating point value,
7614 then we have to avoid collapsing an EQ comparison. */
7616 && rtx_equal_p (x, reg)
7617 && ! FLOAT_MODE_P (GET_MODE (x))
7618 && ! FLOAT_MODE_P (GET_MODE (val)))
7621 if (cond == UNEQ && rtx_equal_p (x, reg))
7624 /* If X is (abs REG) and we know something about REG's relationship
7625 with zero, we may be able to simplify this. */
7627 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7630 case GE: case GT: case EQ:
7633 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7635 GET_MODE (XEXP (x, 0)));
7640 /* The only other cases we handle are MIN, MAX, and comparisons if the
7641 operands are the same as REG and VAL. */
7643 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7645 if (rtx_equal_p (XEXP (x, 0), val))
7646 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7648 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7650 if (COMPARISON_P (x))
7652 if (comparison_dominates_p (cond, code))
7653 return const_true_rtx;
7655 code = combine_reversed_comparison_code (x);
7657 && comparison_dominates_p (cond, code))
7662 else if (code == SMAX || code == SMIN
7663 || code == UMIN || code == UMAX)
7665 int unsignedp = (code == UMIN || code == UMAX);
7667 /* Do not reverse the condition when it is NE or EQ.
7668 This is because we cannot conclude anything about
7669 the value of 'SMAX (x, y)' when x is not equal to y,
7670 but we can when x equals y. */
7671 if ((code == SMAX || code == UMAX)
7672 && ! (cond == EQ || cond == NE))
7673 cond = reverse_condition (cond);
7678 return unsignedp ? x : XEXP (x, 1);
7680 return unsignedp ? x : XEXP (x, 0);
7682 return unsignedp ? XEXP (x, 1) : x;
7684 return unsignedp ? XEXP (x, 0) : x;
7691 else if (code == SUBREG)
7693 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7694 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7696 if (SUBREG_REG (x) != r)
7698 /* We must simplify subreg here, before we lose track of the
7699 original inner_mode. */
7700 new = simplify_subreg (GET_MODE (x), r,
7701 inner_mode, SUBREG_BYTE (x));
7705 SUBST (SUBREG_REG (x), r);
7710 /* We don't have to handle SIGN_EXTEND here, because even in the
7711 case of replacing something with a modeless CONST_INT, a
7712 CONST_INT is already (supposed to be) a valid sign extension for
7713 its narrower mode, which implies it's already properly
7714 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7715 story is different. */
7716 else if (code == ZERO_EXTEND)
7718 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7719 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7721 if (XEXP (x, 0) != r)
7723 /* We must simplify the zero_extend here, before we lose
7724 track of the original inner_mode. */
7725 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7730 SUBST (XEXP (x, 0), r);
7736 fmt = GET_RTX_FORMAT (code);
7737 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7740 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7741 else if (fmt[i] == 'E')
7742 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7743 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7750 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7751 assignment as a field assignment. */
7754 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7756 if (x == y || rtx_equal_p (x, y))
7759 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7762 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7763 Note that all SUBREGs of MEM are paradoxical; otherwise they
7764 would have been rewritten. */
7765 if (MEM_P (x) && GET_CODE (y) == SUBREG
7766 && MEM_P (SUBREG_REG (y))
7767 && rtx_equal_p (SUBREG_REG (y),
7768 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7771 if (MEM_P (y) && GET_CODE (x) == SUBREG
7772 && MEM_P (SUBREG_REG (x))
7773 && rtx_equal_p (SUBREG_REG (x),
7774 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7777 /* We used to see if get_last_value of X and Y were the same but that's
7778 not correct. In one direction, we'll cause the assignment to have
7779 the wrong destination and in the case, we'll import a register into this
7780 insn that might have already have been dead. So fail if none of the
7781 above cases are true. */
7785 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7786 Return that assignment if so.
7788 We only handle the most common cases. */
7791 make_field_assignment (rtx x)
7793 rtx dest = SET_DEST (x);
7794 rtx src = SET_SRC (x);
7799 unsigned HOST_WIDE_INT len;
7801 enum machine_mode mode;
7803 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7804 a clear of a one-bit field. We will have changed it to
7805 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7808 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7809 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7810 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7811 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7813 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7816 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7820 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7821 && subreg_lowpart_p (XEXP (src, 0))
7822 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7823 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7824 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7825 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7826 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7827 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7829 assign = make_extraction (VOIDmode, dest, 0,
7830 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7833 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7837 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7839 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7840 && XEXP (XEXP (src, 0), 0) == const1_rtx
7841 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7843 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7846 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7850 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7851 SRC is an AND with all bits of that field set, then we can discard
7853 if (GET_CODE (dest) == ZERO_EXTRACT
7854 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7855 && GET_CODE (src) == AND
7856 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7858 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7859 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7860 unsigned HOST_WIDE_INT ze_mask;
7862 if (width >= HOST_BITS_PER_WIDE_INT)
7865 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7867 /* Complete overlap. We can remove the source AND. */
7868 if ((and_mask & ze_mask) == ze_mask)
7869 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7871 /* Partial overlap. We can reduce the source AND. */
7872 if ((and_mask & ze_mask) != and_mask)
7874 mode = GET_MODE (src);
7875 src = gen_rtx_AND (mode, XEXP (src, 0),
7876 gen_int_mode (and_mask & ze_mask, mode));
7877 return gen_rtx_SET (VOIDmode, dest, src);
7881 /* The other case we handle is assignments into a constant-position
7882 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7883 a mask that has all one bits except for a group of zero bits and
7884 OTHER is known to have zeros where C1 has ones, this is such an
7885 assignment. Compute the position and length from C1. Shift OTHER
7886 to the appropriate position, force it to the required mode, and
7887 make the extraction. Check for the AND in both operands. */
7889 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7892 rhs = expand_compound_operation (XEXP (src, 0));
7893 lhs = expand_compound_operation (XEXP (src, 1));
7895 if (GET_CODE (rhs) == AND
7896 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7897 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7898 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7899 else if (GET_CODE (lhs) == AND
7900 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7901 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7902 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7906 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7907 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7908 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7909 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7912 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7916 /* The mode to use for the source is the mode of the assignment, or of
7917 what is inside a possible STRICT_LOW_PART. */
7918 mode = (GET_CODE (assign) == STRICT_LOW_PART
7919 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7921 /* Shift OTHER right POS places and make it the source, restricting it
7922 to the proper length and mode. */
7924 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7925 GET_MODE (src), other, pos),
7927 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7928 ? ~(unsigned HOST_WIDE_INT) 0
7929 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7932 /* If SRC is masked by an AND that does not make a difference in
7933 the value being stored, strip it. */
7934 if (GET_CODE (assign) == ZERO_EXTRACT
7935 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7936 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7937 && GET_CODE (src) == AND
7938 && GET_CODE (XEXP (src, 1)) == CONST_INT
7939 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7940 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7941 src = XEXP (src, 0);
7943 return gen_rtx_SET (VOIDmode, assign, src);
7946 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7950 apply_distributive_law (rtx x)
7952 enum rtx_code code = GET_CODE (x);
7953 enum rtx_code inner_code;
7954 rtx lhs, rhs, other;
7957 /* Distributivity is not true for floating point as it can change the
7958 value. So we don't do it unless -funsafe-math-optimizations. */
7959 if (FLOAT_MODE_P (GET_MODE (x))
7960 && ! flag_unsafe_math_optimizations)
7963 /* The outer operation can only be one of the following: */
7964 if (code != IOR && code != AND && code != XOR
7965 && code != PLUS && code != MINUS)
7971 /* If either operand is a primitive we can't do anything, so get out
7973 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7976 lhs = expand_compound_operation (lhs);
7977 rhs = expand_compound_operation (rhs);
7978 inner_code = GET_CODE (lhs);
7979 if (inner_code != GET_CODE (rhs))
7982 /* See if the inner and outer operations distribute. */
7989 /* These all distribute except over PLUS. */
7990 if (code == PLUS || code == MINUS)
7995 if (code != PLUS && code != MINUS)
8000 /* This is also a multiply, so it distributes over everything. */
8004 /* Non-paradoxical SUBREGs distributes over all operations, provided
8005 the inner modes and byte offsets are the same, this is an extraction
8006 of a low-order part, we don't convert an fp operation to int or
8007 vice versa, and we would not be converting a single-word
8008 operation into a multi-word operation. The latter test is not
8009 required, but it prevents generating unneeded multi-word operations.
8010 Some of the previous tests are redundant given the latter test, but
8011 are retained because they are required for correctness.
8013 We produce the result slightly differently in this case. */
8015 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8016 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8017 || ! subreg_lowpart_p (lhs)
8018 || (GET_MODE_CLASS (GET_MODE (lhs))
8019 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8020 || (GET_MODE_SIZE (GET_MODE (lhs))
8021 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8022 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8025 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8026 SUBREG_REG (lhs), SUBREG_REG (rhs));
8027 return gen_lowpart (GET_MODE (x), tem);
8033 /* Set LHS and RHS to the inner operands (A and B in the example
8034 above) and set OTHER to the common operand (C in the example).
8035 There is only one way to do this unless the inner operation is
8037 if (COMMUTATIVE_ARITH_P (lhs)
8038 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8039 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8040 else if (COMMUTATIVE_ARITH_P (lhs)
8041 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8042 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8043 else if (COMMUTATIVE_ARITH_P (lhs)
8044 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8045 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8046 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8047 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8051 /* Form the new inner operation, seeing if it simplifies first. */
8052 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
8054 /* There is one exception to the general way of distributing:
8055 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8056 if (code == XOR && inner_code == IOR)
8059 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8062 /* We may be able to continuing distributing the result, so call
8063 ourselves recursively on the inner operation before forming the
8064 outer operation, which we return. */
8065 return gen_binary (inner_code, GET_MODE (x),
8066 apply_distributive_law (tem), other);
8069 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8072 Return an equivalent form, if different from X. Otherwise, return X. If
8073 X is zero, we are to always construct the equivalent form. */
8076 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8077 unsigned HOST_WIDE_INT constop)
8079 unsigned HOST_WIDE_INT nonzero;
8082 /* Simplify VAROP knowing that we will be only looking at some of the
8085 Note by passing in CONSTOP, we guarantee that the bits not set in
8086 CONSTOP are not significant and will never be examined. We must
8087 ensure that is the case by explicitly masking out those bits
8088 before returning. */
8089 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8091 /* If VAROP is a CLOBBER, we will fail so return it. */
8092 if (GET_CODE (varop) == CLOBBER)
8095 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8096 to VAROP and return the new constant. */
8097 if (GET_CODE (varop) == CONST_INT)
8098 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8100 /* See what bits may be nonzero in VAROP. Unlike the general case of
8101 a call to nonzero_bits, here we don't care about bits outside
8104 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8106 /* Turn off all bits in the constant that are known to already be zero.
8107 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8108 which is tested below. */
8112 /* If we don't have any bits left, return zero. */
8116 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8117 a power of two, we can replace this with an ASHIFT. */
8118 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8119 && (i = exact_log2 (constop)) >= 0)
8120 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8122 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8123 or XOR, then try to apply the distributive law. This may eliminate
8124 operations if either branch can be simplified because of the AND.
8125 It may also make some cases more complex, but those cases probably
8126 won't match a pattern either with or without this. */
8128 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8132 apply_distributive_law
8133 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8134 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8135 XEXP (varop, 0), constop),
8136 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8137 XEXP (varop, 1), constop))));
8139 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8140 the AND and see if one of the operands simplifies to zero. If so, we
8141 may eliminate it. */
8143 if (GET_CODE (varop) == PLUS
8144 && exact_log2 (constop + 1) >= 0)
8148 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8149 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8150 if (o0 == const0_rtx)
8152 if (o1 == const0_rtx)
8156 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8157 if we already had one (just check for the simplest cases). */
8158 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8159 && GET_MODE (XEXP (x, 0)) == mode
8160 && SUBREG_REG (XEXP (x, 0)) == varop)
8161 varop = XEXP (x, 0);
8163 varop = gen_lowpart (mode, varop);
8165 /* If we can't make the SUBREG, try to return what we were given. */
8166 if (GET_CODE (varop) == CLOBBER)
8167 return x ? x : varop;
8169 /* If we are only masking insignificant bits, return VAROP. */
8170 if (constop == nonzero)
8174 /* Otherwise, return an AND. */
8175 constop = trunc_int_for_mode (constop, mode);
8176 /* See how much, if any, of X we can use. */
8177 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8178 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8182 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8183 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8184 SUBST (XEXP (x, 1), GEN_INT (constop));
8186 SUBST (XEXP (x, 0), varop);
8193 /* Given a REG, X, compute which bits in X can be nonzero.
8194 We don't care about bits outside of those defined in MODE.
8196 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8197 a shift, AND, or zero_extract, we can do better. */
8200 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8201 rtx known_x ATTRIBUTE_UNUSED,
8202 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8203 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8204 unsigned HOST_WIDE_INT *nonzero)
8208 /* If X is a register whose nonzero bits value is current, use it.
8209 Otherwise, if X is a register whose value we can find, use that
8210 value. Otherwise, use the previously-computed global nonzero bits
8211 for this register. */
8213 if (reg_stat[REGNO (x)].last_set_value != 0
8214 && (reg_stat[REGNO (x)].last_set_mode == mode
8215 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8216 && GET_MODE_CLASS (mode) == MODE_INT))
8217 && (reg_stat[REGNO (x)].last_set_label == label_tick
8218 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8219 && REG_N_SETS (REGNO (x)) == 1
8220 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8222 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8224 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8228 tem = get_last_value (x);
8232 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8233 /* If X is narrower than MODE and TEM is a non-negative
8234 constant that would appear negative in the mode of X,
8235 sign-extend it for use in reg_nonzero_bits because some
8236 machines (maybe most) will actually do the sign-extension
8237 and this is the conservative approach.
8239 ??? For 2.5, try to tighten up the MD files in this regard
8240 instead of this kludge. */
8242 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8243 && GET_CODE (tem) == CONST_INT
8245 && 0 != (INTVAL (tem)
8246 & ((HOST_WIDE_INT) 1
8247 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8248 tem = GEN_INT (INTVAL (tem)
8249 | ((HOST_WIDE_INT) (-1)
8250 << GET_MODE_BITSIZE (GET_MODE (x))));
8254 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8256 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8258 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8259 /* We don't know anything about the upper bits. */
8260 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8267 /* Return the number of bits at the high-order end of X that are known to
8268 be equal to the sign bit. X will be used in mode MODE; if MODE is
8269 VOIDmode, X will be used in its own mode. The returned value will always
8270 be between 1 and the number of bits in MODE. */
8273 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8274 rtx known_x ATTRIBUTE_UNUSED,
8275 enum machine_mode known_mode
8277 unsigned int known_ret ATTRIBUTE_UNUSED,
8278 unsigned int *result)
8282 if (reg_stat[REGNO (x)].last_set_value != 0
8283 && reg_stat[REGNO (x)].last_set_mode == mode
8284 && (reg_stat[REGNO (x)].last_set_label == label_tick
8285 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8286 && REG_N_SETS (REGNO (x)) == 1
8287 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8289 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8291 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8295 tem = get_last_value (x);
8299 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8300 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8301 *result = reg_stat[REGNO (x)].sign_bit_copies;
8306 /* Return the number of "extended" bits there are in X, when interpreted
8307 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8308 unsigned quantities, this is the number of high-order zero bits.
8309 For signed quantities, this is the number of copies of the sign bit
8310 minus 1. In both case, this function returns the number of "spare"
8311 bits. For example, if two quantities for which this function returns
8312 at least 1 are added, the addition is known not to overflow.
8314 This function will always return 0 unless called during combine, which
8315 implies that it must be called from a define_split. */
8318 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8320 if (nonzero_sign_valid == 0)
8324 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8325 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8326 - floor_log2 (nonzero_bits (x, mode)))
8328 : num_sign_bit_copies (x, mode) - 1);
8331 /* This function is called from `simplify_shift_const' to merge two
8332 outer operations. Specifically, we have already found that we need
8333 to perform operation *POP0 with constant *PCONST0 at the outermost
8334 position. We would now like to also perform OP1 with constant CONST1
8335 (with *POP0 being done last).
8337 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8338 the resulting operation. *PCOMP_P is set to 1 if we would need to
8339 complement the innermost operand, otherwise it is unchanged.
8341 MODE is the mode in which the operation will be done. No bits outside
8342 the width of this mode matter. It is assumed that the width of this mode
8343 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8345 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8346 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8347 result is simply *PCONST0.
8349 If the resulting operation cannot be expressed as one operation, we
8350 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8353 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8355 enum rtx_code op0 = *pop0;
8356 HOST_WIDE_INT const0 = *pconst0;
8358 const0 &= GET_MODE_MASK (mode);
8359 const1 &= GET_MODE_MASK (mode);
8361 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8365 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8368 if (op1 == UNKNOWN || op0 == SET)
8371 else if (op0 == UNKNOWN)
8372 op0 = op1, const0 = const1;
8374 else if (op0 == op1)
8398 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8399 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8402 /* If the two constants aren't the same, we can't do anything. The
8403 remaining six cases can all be done. */
8404 else if (const0 != const1)
8412 /* (a & b) | b == b */
8414 else /* op1 == XOR */
8415 /* (a ^ b) | b == a | b */
8421 /* (a & b) ^ b == (~a) & b */
8422 op0 = AND, *pcomp_p = 1;
8423 else /* op1 == IOR */
8424 /* (a | b) ^ b == a & ~b */
8425 op0 = AND, const0 = ~const0;
8430 /* (a | b) & b == b */
8432 else /* op1 == XOR */
8433 /* (a ^ b) & b) == (~a) & b */
8440 /* Check for NO-OP cases. */
8441 const0 &= GET_MODE_MASK (mode);
8443 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8445 else if (const0 == 0 && op0 == AND)
8447 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8451 /* ??? Slightly redundant with the above mask, but not entirely.
8452 Moving this above means we'd have to sign-extend the mode mask
8453 for the final test. */
8454 const0 = trunc_int_for_mode (const0, mode);
8462 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8463 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8464 that we started with.
8466 The shift is normally computed in the widest mode we find in VAROP, as
8467 long as it isn't a different number of words than RESULT_MODE. Exceptions
8468 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8471 simplify_shift_const (rtx x, enum rtx_code code,
8472 enum machine_mode result_mode, rtx varop,
8475 enum rtx_code orig_code = code;
8478 enum machine_mode mode = result_mode;
8479 enum machine_mode shift_mode, tmode;
8480 unsigned int mode_words
8481 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8482 /* We form (outer_op (code varop count) (outer_const)). */
8483 enum rtx_code outer_op = UNKNOWN;
8484 HOST_WIDE_INT outer_const = 0;
8486 int complement_p = 0;
8489 /* Make sure and truncate the "natural" shift on the way in. We don't
8490 want to do this inside the loop as it makes it more difficult to
8492 if (SHIFT_COUNT_TRUNCATED)
8493 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8495 /* If we were given an invalid count, don't do anything except exactly
8496 what was requested. */
8498 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8503 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8508 /* Unless one of the branches of the `if' in this loop does a `continue',
8509 we will `break' the loop after the `if'. */
8513 /* If we have an operand of (clobber (const_int 0)), just return that
8515 if (GET_CODE (varop) == CLOBBER)
8518 /* If we discovered we had to complement VAROP, leave. Making a NOT
8519 here would cause an infinite loop. */
8523 /* Convert ROTATERT to ROTATE. */
8524 if (code == ROTATERT)
8526 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8528 if (VECTOR_MODE_P (result_mode))
8529 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8531 count = bitsize - count;
8534 /* We need to determine what mode we will do the shift in. If the
8535 shift is a right shift or a ROTATE, we must always do it in the mode
8536 it was originally done in. Otherwise, we can do it in MODE, the
8537 widest mode encountered. */
8539 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8540 ? result_mode : mode);
8542 /* Handle cases where the count is greater than the size of the mode
8543 minus 1. For ASHIFT, use the size minus one as the count (this can
8544 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8545 take the count modulo the size. For other shifts, the result is
8548 Since these shifts are being produced by the compiler by combining
8549 multiple operations, each of which are defined, we know what the
8550 result is supposed to be. */
8552 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8554 if (code == ASHIFTRT)
8555 count = GET_MODE_BITSIZE (shift_mode) - 1;
8556 else if (code == ROTATE || code == ROTATERT)
8557 count %= GET_MODE_BITSIZE (shift_mode);
8560 /* We can't simply return zero because there may be an
8568 /* An arithmetic right shift of a quantity known to be -1 or 0
8570 if (code == ASHIFTRT
8571 && (num_sign_bit_copies (varop, shift_mode)
8572 == GET_MODE_BITSIZE (shift_mode)))
8578 /* If we are doing an arithmetic right shift and discarding all but
8579 the sign bit copies, this is equivalent to doing a shift by the
8580 bitsize minus one. Convert it into that shift because it will often
8581 allow other simplifications. */
8583 if (code == ASHIFTRT
8584 && (count + num_sign_bit_copies (varop, shift_mode)
8585 >= GET_MODE_BITSIZE (shift_mode)))
8586 count = GET_MODE_BITSIZE (shift_mode) - 1;
8588 /* We simplify the tests below and elsewhere by converting
8589 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8590 `make_compound_operation' will convert it to an ASHIFTRT for
8591 those machines (such as VAX) that don't have an LSHIFTRT. */
8592 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8594 && ((nonzero_bits (varop, shift_mode)
8595 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8599 if (code == LSHIFTRT
8600 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8601 && !(nonzero_bits (varop, shift_mode) >> count))
8604 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8605 && !((nonzero_bits (varop, shift_mode) << count)
8606 & GET_MODE_MASK (shift_mode)))
8609 switch (GET_CODE (varop))
8615 new = expand_compound_operation (varop);
8624 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8625 minus the width of a smaller mode, we can do this with a
8626 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8627 if ((code == ASHIFTRT || code == LSHIFTRT)
8628 && ! mode_dependent_address_p (XEXP (varop, 0))
8629 && ! MEM_VOLATILE_P (varop)
8630 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8631 MODE_INT, 1)) != BLKmode)
8633 new = adjust_address_nv (varop, tmode,
8634 BYTES_BIG_ENDIAN ? 0
8635 : count / BITS_PER_UNIT);
8637 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8638 : ZERO_EXTEND, mode, new);
8645 /* Similar to the case above, except that we can only do this if
8646 the resulting mode is the same as that of the underlying
8647 MEM and adjust the address depending on the *bits* endianness
8648 because of the way that bit-field extract insns are defined. */
8649 if ((code == ASHIFTRT || code == LSHIFTRT)
8650 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8651 MODE_INT, 1)) != BLKmode
8652 && tmode == GET_MODE (XEXP (varop, 0)))
8654 if (BITS_BIG_ENDIAN)
8655 new = XEXP (varop, 0);
8658 new = copy_rtx (XEXP (varop, 0));
8659 SUBST (XEXP (new, 0),
8660 plus_constant (XEXP (new, 0),
8661 count / BITS_PER_UNIT));
8664 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8665 : ZERO_EXTEND, mode, new);
8672 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8673 the same number of words as what we've seen so far. Then store
8674 the widest mode in MODE. */
8675 if (subreg_lowpart_p (varop)
8676 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8677 > GET_MODE_SIZE (GET_MODE (varop)))
8678 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8679 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8682 varop = SUBREG_REG (varop);
8683 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8684 mode = GET_MODE (varop);
8690 /* Some machines use MULT instead of ASHIFT because MULT
8691 is cheaper. But it is still better on those machines to
8692 merge two shifts into one. */
8693 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8694 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8697 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8698 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8704 /* Similar, for when divides are cheaper. */
8705 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8706 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8709 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8710 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8716 /* If we are extracting just the sign bit of an arithmetic
8717 right shift, that shift is not needed. However, the sign
8718 bit of a wider mode may be different from what would be
8719 interpreted as the sign bit in a narrower mode, so, if
8720 the result is narrower, don't discard the shift. */
8721 if (code == LSHIFTRT
8722 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8723 && (GET_MODE_BITSIZE (result_mode)
8724 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8726 varop = XEXP (varop, 0);
8730 /* ... fall through ... */
8735 /* Here we have two nested shifts. The result is usually the
8736 AND of a new shift with a mask. We compute the result below. */
8737 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8738 && INTVAL (XEXP (varop, 1)) >= 0
8739 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8740 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8741 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8743 enum rtx_code first_code = GET_CODE (varop);
8744 unsigned int first_count = INTVAL (XEXP (varop, 1));
8745 unsigned HOST_WIDE_INT mask;
8748 /* We have one common special case. We can't do any merging if
8749 the inner code is an ASHIFTRT of a smaller mode. However, if
8750 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8751 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8752 we can convert it to
8753 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8754 This simplifies certain SIGN_EXTEND operations. */
8755 if (code == ASHIFT && first_code == ASHIFTRT
8756 && count == (unsigned int)
8757 (GET_MODE_BITSIZE (result_mode)
8758 - GET_MODE_BITSIZE (GET_MODE (varop))))
8760 /* C3 has the low-order C1 bits zero. */
8762 mask = (GET_MODE_MASK (mode)
8763 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8765 varop = simplify_and_const_int (NULL_RTX, result_mode,
8766 XEXP (varop, 0), mask);
8767 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8769 count = first_count;
8774 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8775 than C1 high-order bits equal to the sign bit, we can convert
8776 this to either an ASHIFT or an ASHIFTRT depending on the
8779 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8781 if (code == ASHIFTRT && first_code == ASHIFT
8782 && GET_MODE (varop) == shift_mode
8783 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8786 varop = XEXP (varop, 0);
8788 signed_count = count - first_count;
8789 if (signed_count < 0)
8790 count = -signed_count, code = ASHIFT;
8792 count = signed_count;
8797 /* There are some cases we can't do. If CODE is ASHIFTRT,
8798 we can only do this if FIRST_CODE is also ASHIFTRT.
8800 We can't do the case when CODE is ROTATE and FIRST_CODE is
8803 If the mode of this shift is not the mode of the outer shift,
8804 we can't do this if either shift is a right shift or ROTATE.
8806 Finally, we can't do any of these if the mode is too wide
8807 unless the codes are the same.
8809 Handle the case where the shift codes are the same
8812 if (code == first_code)
8814 if (GET_MODE (varop) != result_mode
8815 && (code == ASHIFTRT || code == LSHIFTRT
8819 count += first_count;
8820 varop = XEXP (varop, 0);
8824 if (code == ASHIFTRT
8825 || (code == ROTATE && first_code == ASHIFTRT)
8826 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8827 || (GET_MODE (varop) != result_mode
8828 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8829 || first_code == ROTATE
8830 || code == ROTATE)))
8833 /* To compute the mask to apply after the shift, shift the
8834 nonzero bits of the inner shift the same way the
8835 outer shift will. */
8837 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8840 = simplify_binary_operation (code, result_mode, mask_rtx,
8843 /* Give up if we can't compute an outer operation to use. */
8845 || GET_CODE (mask_rtx) != CONST_INT
8846 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8848 result_mode, &complement_p))
8851 /* If the shifts are in the same direction, we add the
8852 counts. Otherwise, we subtract them. */
8853 signed_count = count;
8854 if ((code == ASHIFTRT || code == LSHIFTRT)
8855 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8856 signed_count += first_count;
8858 signed_count -= first_count;
8860 /* If COUNT is positive, the new shift is usually CODE,
8861 except for the two exceptions below, in which case it is
8862 FIRST_CODE. If the count is negative, FIRST_CODE should
8864 if (signed_count > 0
8865 && ((first_code == ROTATE && code == ASHIFT)
8866 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8867 code = first_code, count = signed_count;
8868 else if (signed_count < 0)
8869 code = first_code, count = -signed_count;
8871 count = signed_count;
8873 varop = XEXP (varop, 0);
8877 /* If we have (A << B << C) for any shift, we can convert this to
8878 (A << C << B). This wins if A is a constant. Only try this if
8879 B is not a constant. */
8881 else if (GET_CODE (varop) == code
8882 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8884 = simplify_binary_operation (code, mode,
8888 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8895 /* Make this fit the case below. */
8896 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8897 GEN_INT (GET_MODE_MASK (mode)));
8903 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8904 with C the size of VAROP - 1 and the shift is logical if
8905 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8906 we have an (le X 0) operation. If we have an arithmetic shift
8907 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8908 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8910 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8911 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8912 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8913 && (code == LSHIFTRT || code == ASHIFTRT)
8914 && count == (unsigned int)
8915 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8916 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8919 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8922 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8923 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8928 /* If we have (shift (logical)), move the logical to the outside
8929 to allow it to possibly combine with another logical and the
8930 shift to combine with another shift. This also canonicalizes to
8931 what a ZERO_EXTRACT looks like. Also, some machines have
8932 (and (shift)) insns. */
8934 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8935 /* We can't do this if we have (ashiftrt (xor)) and the
8936 constant has its sign bit set in shift_mode. */
8937 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8938 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8940 && (new = simplify_binary_operation (code, result_mode,
8942 GEN_INT (count))) != 0
8943 && GET_CODE (new) == CONST_INT
8944 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8945 INTVAL (new), result_mode, &complement_p))
8947 varop = XEXP (varop, 0);
8951 /* If we can't do that, try to simplify the shift in each arm of the
8952 logical expression, make a new logical expression, and apply
8953 the inverse distributive law. This also can't be done
8954 for some (ashiftrt (xor)). */
8955 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8956 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8957 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8960 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8961 XEXP (varop, 0), count);
8962 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8963 XEXP (varop, 1), count);
8965 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8966 varop = apply_distributive_law (varop);
8974 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8975 says that the sign bit can be tested, FOO has mode MODE, C is
8976 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8977 that may be nonzero. */
8978 if (code == LSHIFTRT
8979 && XEXP (varop, 1) == const0_rtx
8980 && GET_MODE (XEXP (varop, 0)) == result_mode
8981 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8982 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8983 && ((STORE_FLAG_VALUE
8984 & ((HOST_WIDE_INT) 1
8985 < (GET_MODE_BITSIZE (result_mode) - 1))))
8986 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8987 && merge_outer_ops (&outer_op, &outer_const, XOR,
8988 (HOST_WIDE_INT) 1, result_mode,
8991 varop = XEXP (varop, 0);
8998 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8999 than the number of bits in the mode is equivalent to A. */
9000 if (code == LSHIFTRT
9001 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9002 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9004 varop = XEXP (varop, 0);
9009 /* NEG commutes with ASHIFT since it is multiplication. Move the
9010 NEG outside to allow shifts to combine. */
9012 && merge_outer_ops (&outer_op, &outer_const, NEG,
9013 (HOST_WIDE_INT) 0, result_mode,
9016 varop = XEXP (varop, 0);
9022 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9023 is one less than the number of bits in the mode is
9024 equivalent to (xor A 1). */
9025 if (code == LSHIFTRT
9026 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9027 && XEXP (varop, 1) == constm1_rtx
9028 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9029 && merge_outer_ops (&outer_op, &outer_const, XOR,
9030 (HOST_WIDE_INT) 1, result_mode,
9034 varop = XEXP (varop, 0);
9038 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9039 that might be nonzero in BAR are those being shifted out and those
9040 bits are known zero in FOO, we can replace the PLUS with FOO.
9041 Similarly in the other operand order. This code occurs when
9042 we are computing the size of a variable-size array. */
9044 if ((code == ASHIFTRT || code == LSHIFTRT)
9045 && count < HOST_BITS_PER_WIDE_INT
9046 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9047 && (nonzero_bits (XEXP (varop, 1), result_mode)
9048 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9050 varop = XEXP (varop, 0);
9053 else if ((code == ASHIFTRT || code == LSHIFTRT)
9054 && count < HOST_BITS_PER_WIDE_INT
9055 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9056 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9058 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9059 & nonzero_bits (XEXP (varop, 1),
9062 varop = XEXP (varop, 1);
9066 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9068 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9069 && (new = simplify_binary_operation (ASHIFT, result_mode,
9071 GEN_INT (count))) != 0
9072 && GET_CODE (new) == CONST_INT
9073 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9074 INTVAL (new), result_mode, &complement_p))
9076 varop = XEXP (varop, 0);
9080 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9081 signbit', and attempt to change the PLUS to an XOR and move it to
9082 the outer operation as is done above in the AND/IOR/XOR case
9083 leg for shift(logical). See details in logical handling above
9084 for reasoning in doing so. */
9085 if (code == LSHIFTRT
9086 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9087 && mode_signbit_p (result_mode, XEXP (varop, 1))
9088 && (new = simplify_binary_operation (code, result_mode,
9090 GEN_INT (count))) != 0
9091 && GET_CODE (new) == CONST_INT
9092 && merge_outer_ops (&outer_op, &outer_const, XOR,
9093 INTVAL (new), result_mode, &complement_p))
9095 varop = XEXP (varop, 0);
9102 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9103 with C the size of VAROP - 1 and the shift is logical if
9104 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9105 we have a (gt X 0) operation. If the shift is arithmetic with
9106 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9107 we have a (neg (gt X 0)) operation. */
9109 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9110 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9111 && count == (unsigned int)
9112 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9113 && (code == LSHIFTRT || code == ASHIFTRT)
9114 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9115 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9117 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9120 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9123 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9124 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9131 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9132 if the truncate does not affect the value. */
9133 if (code == LSHIFTRT
9134 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9135 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9136 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9137 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9138 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9140 rtx varop_inner = XEXP (varop, 0);
9143 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9144 XEXP (varop_inner, 0),
9146 (count + INTVAL (XEXP (varop_inner, 1))));
9147 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9160 /* We need to determine what mode to do the shift in. If the shift is
9161 a right shift or ROTATE, we must always do it in the mode it was
9162 originally done in. Otherwise, we can do it in MODE, the widest mode
9163 encountered. The code we care about is that of the shift that will
9164 actually be done, not the shift that was originally requested. */
9166 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9167 ? result_mode : mode);
9169 /* We have now finished analyzing the shift. The result should be
9170 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9171 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9172 to the result of the shift. OUTER_CONST is the relevant constant,
9173 but we must turn off all bits turned off in the shift.
9175 If we were passed a value for X, see if we can use any pieces of
9176 it. If not, make new rtx. */
9178 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9179 && GET_CODE (XEXP (x, 1)) == CONST_INT
9180 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9181 const_rtx = XEXP (x, 1);
9183 const_rtx = GEN_INT (count);
9185 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9186 && GET_MODE (XEXP (x, 0)) == shift_mode
9187 && SUBREG_REG (XEXP (x, 0)) == varop)
9188 varop = XEXP (x, 0);
9189 else if (GET_MODE (varop) != shift_mode)
9190 varop = gen_lowpart (shift_mode, varop);
9192 /* If we can't make the SUBREG, try to return what we were given. */
9193 if (GET_CODE (varop) == CLOBBER)
9194 return x ? x : varop;
9196 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9200 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9202 /* If we have an outer operation and we just made a shift, it is
9203 possible that we could have simplified the shift were it not
9204 for the outer operation. So try to do the simplification
9207 if (outer_op != UNKNOWN && GET_CODE (x) == code
9208 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9209 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9210 INTVAL (XEXP (x, 1)));
9212 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9213 turn off all the bits that the shift would have turned off. */
9214 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9215 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9216 GET_MODE_MASK (result_mode) >> orig_count);
9218 /* Do the remainder of the processing in RESULT_MODE. */
9219 x = gen_lowpart (result_mode, x);
9221 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9224 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9226 if (outer_op != UNKNOWN)
9228 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9229 outer_const = trunc_int_for_mode (outer_const, result_mode);
9231 if (outer_op == AND)
9232 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9233 else if (outer_op == SET)
9234 /* This means that we have determined that the result is
9235 equivalent to a constant. This should be rare. */
9236 x = GEN_INT (outer_const);
9237 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9238 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9240 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9246 /* Like recog, but we receive the address of a pointer to a new pattern.
9247 We try to match the rtx that the pointer points to.
9248 If that fails, we may try to modify or replace the pattern,
9249 storing the replacement into the same pointer object.
9251 Modifications include deletion or addition of CLOBBERs.
9253 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9254 the CLOBBERs are placed.
9256 The value is the final insn code from the pattern ultimately matched,
9260 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9263 int insn_code_number;
9264 int num_clobbers_to_add = 0;
9267 rtx old_notes, old_pat;
9269 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9270 we use to indicate that something didn't match. If we find such a
9271 thing, force rejection. */
9272 if (GET_CODE (pat) == PARALLEL)
9273 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9274 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9275 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9278 old_pat = PATTERN (insn);
9279 old_notes = REG_NOTES (insn);
9280 PATTERN (insn) = pat;
9281 REG_NOTES (insn) = 0;
9283 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9285 /* If it isn't, there is the possibility that we previously had an insn
9286 that clobbered some register as a side effect, but the combined
9287 insn doesn't need to do that. So try once more without the clobbers
9288 unless this represents an ASM insn. */
9290 if (insn_code_number < 0 && ! check_asm_operands (pat)
9291 && GET_CODE (pat) == PARALLEL)
9295 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9296 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9299 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9303 SUBST_INT (XVECLEN (pat, 0), pos);
9306 pat = XVECEXP (pat, 0, 0);
9308 PATTERN (insn) = pat;
9309 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9311 PATTERN (insn) = old_pat;
9312 REG_NOTES (insn) = old_notes;
9314 /* Recognize all noop sets, these will be killed by followup pass. */
9315 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9316 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9318 /* If we had any clobbers to add, make a new pattern than contains
9319 them. Then check to make sure that all of them are dead. */
9320 if (num_clobbers_to_add)
9322 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9323 rtvec_alloc (GET_CODE (pat) == PARALLEL
9325 + num_clobbers_to_add)
9326 : num_clobbers_to_add + 1));
9328 if (GET_CODE (pat) == PARALLEL)
9329 for (i = 0; i < XVECLEN (pat, 0); i++)
9330 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9332 XVECEXP (newpat, 0, 0) = pat;
9334 add_clobbers (newpat, insn_code_number);
9336 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9337 i < XVECLEN (newpat, 0); i++)
9339 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9340 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9342 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9343 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9351 return insn_code_number;
9354 /* Like gen_lowpart_general but for use by combine. In combine it
9355 is not possible to create any new pseudoregs. However, it is
9356 safe to create invalid memory addresses, because combine will
9357 try to recognize them and all they will do is make the combine
9360 If for some reason this cannot do its job, an rtx
9361 (clobber (const_int 0)) is returned.
9362 An insn containing that will not be recognized. */
9365 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9367 enum machine_mode imode = GET_MODE (x);
9368 unsigned int osize = GET_MODE_SIZE (omode);
9369 unsigned int isize = GET_MODE_SIZE (imode);
9375 /* Return identity if this is a CONST or symbolic reference. */
9377 && (GET_CODE (x) == CONST
9378 || GET_CODE (x) == SYMBOL_REF
9379 || GET_CODE (x) == LABEL_REF))
9382 /* We can only support MODE being wider than a word if X is a
9383 constant integer or has a mode the same size. */
9384 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9385 && ! ((imode == VOIDmode
9386 && (GET_CODE (x) == CONST_INT
9387 || GET_CODE (x) == CONST_DOUBLE))
9391 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9392 won't know what to do. So we will strip off the SUBREG here and
9393 process normally. */
9394 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9398 /* For use in case we fall down into the address adjustments
9399 further below, we need to adjust the known mode and size of
9400 x; imode and isize, since we just adjusted x. */
9401 imode = GET_MODE (x);
9406 isize = GET_MODE_SIZE (imode);
9409 result = gen_lowpart_common (omode, x);
9411 #ifdef CANNOT_CHANGE_MODE_CLASS
9412 if (result != 0 && GET_CODE (result) == SUBREG)
9413 record_subregs_of_mode (result);
9423 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9425 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9428 /* If we want to refer to something bigger than the original memref,
9429 generate a paradoxical subreg instead. That will force a reload
9430 of the original memref X. */
9432 return gen_rtx_SUBREG (omode, x, 0);
9434 if (WORDS_BIG_ENDIAN)
9435 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9437 /* Adjust the address so that the address-after-the-data is unchanged. */
9438 if (BYTES_BIG_ENDIAN)
9439 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9441 return adjust_address_nv (x, omode, offset);
9444 /* If X is a comparison operator, rewrite it in a new mode. This
9445 probably won't match, but may allow further simplifications. */
9446 else if (COMPARISON_P (x))
9447 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9449 /* If we couldn't simplify X any other way, just enclose it in a
9450 SUBREG. Normally, this SUBREG won't match, but some patterns may
9451 include an explicit SUBREG or we may simplify it further in combine. */
9457 offset = subreg_lowpart_offset (omode, imode);
9458 if (imode == VOIDmode)
9460 imode = int_mode_for_mode (omode);
9461 x = gen_lowpart_common (imode, x);
9465 res = simplify_gen_subreg (omode, x, imode, offset);
9471 return gen_rtx_CLOBBER (imode, const0_rtx);
9474 /* These routines make binary and unary operations by first seeing if they
9475 fold; if not, a new expression is allocated. */
9478 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
9483 if (GET_CODE (op0) == CLOBBER)
9485 else if (GET_CODE (op1) == CLOBBER)
9488 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9489 && swap_commutative_operands_p (op0, op1))
9490 tem = op0, op0 = op1, op1 = tem;
9492 if (GET_RTX_CLASS (code) == RTX_COMPARE
9493 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9495 enum machine_mode op_mode = GET_MODE (op0);
9497 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9498 just (REL_OP X Y). */
9499 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9501 op1 = XEXP (op0, 1);
9502 op0 = XEXP (op0, 0);
9503 op_mode = GET_MODE (op0);
9506 if (op_mode == VOIDmode)
9507 op_mode = GET_MODE (op1);
9508 result = simplify_relational_operation (code, mode, op_mode, op0, op1);
9511 result = simplify_binary_operation (code, mode, op0, op1);
9516 /* Put complex operands first and constants second. */
9517 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9518 && swap_commutative_operands_p (op0, op1))
9519 return gen_rtx_fmt_ee (code, mode, op1, op0);
9521 /* If we are turning off bits already known off in OP0, we need not do
9523 else if (code == AND && GET_CODE (op1) == CONST_INT
9524 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9525 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9528 return gen_rtx_fmt_ee (code, mode, op0, op1);
9531 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9532 comparison code that will be tested.
9534 The result is a possibly different comparison code to use. *POP0 and
9535 *POP1 may be updated.
9537 It is possible that we might detect that a comparison is either always
9538 true or always false. However, we do not perform general constant
9539 folding in combine, so this knowledge isn't useful. Such tautologies
9540 should have been detected earlier. Hence we ignore all such cases. */
9542 static enum rtx_code
9543 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9549 enum machine_mode mode, tmode;
9551 /* Try a few ways of applying the same transformation to both operands. */
9554 #ifndef WORD_REGISTER_OPERATIONS
9555 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9556 so check specially. */
9557 if (code != GTU && code != GEU && code != LTU && code != LEU
9558 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9559 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9560 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9561 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9562 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9563 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9564 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9565 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9566 && XEXP (op0, 1) == XEXP (op1, 1)
9567 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9568 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9569 && (INTVAL (XEXP (op0, 1))
9570 == (GET_MODE_BITSIZE (GET_MODE (op0))
9572 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9574 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9575 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9579 /* If both operands are the same constant shift, see if we can ignore the
9580 shift. We can if the shift is a rotate or if the bits shifted out of
9581 this shift are known to be zero for both inputs and if the type of
9582 comparison is compatible with the shift. */
9583 if (GET_CODE (op0) == GET_CODE (op1)
9584 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9585 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9586 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9587 && (code != GT && code != LT && code != GE && code != LE))
9588 || (GET_CODE (op0) == ASHIFTRT
9589 && (code != GTU && code != LTU
9590 && code != GEU && code != LEU)))
9591 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9592 && INTVAL (XEXP (op0, 1)) >= 0
9593 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9594 && XEXP (op0, 1) == XEXP (op1, 1))
9596 enum machine_mode mode = GET_MODE (op0);
9597 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9598 int shift_count = INTVAL (XEXP (op0, 1));
9600 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9601 mask &= (mask >> shift_count) << shift_count;
9602 else if (GET_CODE (op0) == ASHIFT)
9603 mask = (mask & (mask << shift_count)) >> shift_count;
9605 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9606 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9607 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9612 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9613 SUBREGs are of the same mode, and, in both cases, the AND would
9614 be redundant if the comparison was done in the narrower mode,
9615 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9616 and the operand's possibly nonzero bits are 0xffffff01; in that case
9617 if we only care about QImode, we don't need the AND). This case
9618 occurs if the output mode of an scc insn is not SImode and
9619 STORE_FLAG_VALUE == 1 (e.g., the 386).
9621 Similarly, check for a case where the AND's are ZERO_EXTEND
9622 operations from some narrower mode even though a SUBREG is not
9625 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9626 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9627 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9629 rtx inner_op0 = XEXP (op0, 0);
9630 rtx inner_op1 = XEXP (op1, 0);
9631 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9632 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9635 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9636 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9637 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9638 && (GET_MODE (SUBREG_REG (inner_op0))
9639 == GET_MODE (SUBREG_REG (inner_op1)))
9640 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9641 <= HOST_BITS_PER_WIDE_INT)
9642 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9643 GET_MODE (SUBREG_REG (inner_op0)))))
9644 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9645 GET_MODE (SUBREG_REG (inner_op1))))))
9647 op0 = SUBREG_REG (inner_op0);
9648 op1 = SUBREG_REG (inner_op1);
9650 /* The resulting comparison is always unsigned since we masked
9651 off the original sign bit. */
9652 code = unsigned_condition (code);
9658 for (tmode = GET_CLASS_NARROWEST_MODE
9659 (GET_MODE_CLASS (GET_MODE (op0)));
9660 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9661 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9663 op0 = gen_lowpart (tmode, inner_op0);
9664 op1 = gen_lowpart (tmode, inner_op1);
9665 code = unsigned_condition (code);
9674 /* If both operands are NOT, we can strip off the outer operation
9675 and adjust the comparison code for swapped operands; similarly for
9676 NEG, except that this must be an equality comparison. */
9677 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9678 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9679 && (code == EQ || code == NE)))
9680 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9686 /* If the first operand is a constant, swap the operands and adjust the
9687 comparison code appropriately, but don't do this if the second operand
9688 is already a constant integer. */
9689 if (swap_commutative_operands_p (op0, op1))
9691 tem = op0, op0 = op1, op1 = tem;
9692 code = swap_condition (code);
9695 /* We now enter a loop during which we will try to simplify the comparison.
9696 For the most part, we only are concerned with comparisons with zero,
9697 but some things may really be comparisons with zero but not start
9698 out looking that way. */
9700 while (GET_CODE (op1) == CONST_INT)
9702 enum machine_mode mode = GET_MODE (op0);
9703 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9704 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9705 int equality_comparison_p;
9706 int sign_bit_comparison_p;
9707 int unsigned_comparison_p;
9708 HOST_WIDE_INT const_op;
9710 /* We only want to handle integral modes. This catches VOIDmode,
9711 CCmode, and the floating-point modes. An exception is that we
9712 can handle VOIDmode if OP0 is a COMPARE or a comparison
9715 if (GET_MODE_CLASS (mode) != MODE_INT
9716 && ! (mode == VOIDmode
9717 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9720 /* Get the constant we are comparing against and turn off all bits
9721 not on in our mode. */
9722 const_op = INTVAL (op1);
9723 if (mode != VOIDmode)
9724 const_op = trunc_int_for_mode (const_op, mode);
9725 op1 = GEN_INT (const_op);
9727 /* If we are comparing against a constant power of two and the value
9728 being compared can only have that single bit nonzero (e.g., it was
9729 `and'ed with that bit), we can replace this with a comparison
9732 && (code == EQ || code == NE || code == GE || code == GEU
9733 || code == LT || code == LTU)
9734 && mode_width <= HOST_BITS_PER_WIDE_INT
9735 && exact_log2 (const_op) >= 0
9736 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9738 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9739 op1 = const0_rtx, const_op = 0;
9742 /* Similarly, if we are comparing a value known to be either -1 or
9743 0 with -1, change it to the opposite comparison against zero. */
9746 && (code == EQ || code == NE || code == GT || code == LE
9747 || code == GEU || code == LTU)
9748 && num_sign_bit_copies (op0, mode) == mode_width)
9750 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9751 op1 = const0_rtx, const_op = 0;
9754 /* Do some canonicalizations based on the comparison code. We prefer
9755 comparisons against zero and then prefer equality comparisons.
9756 If we can reduce the size of a constant, we will do that too. */
9761 /* < C is equivalent to <= (C - 1) */
9765 op1 = GEN_INT (const_op);
9767 /* ... fall through to LE case below. */
9773 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9777 op1 = GEN_INT (const_op);
9781 /* If we are doing a <= 0 comparison on a value known to have
9782 a zero sign bit, we can replace this with == 0. */
9783 else if (const_op == 0
9784 && mode_width <= HOST_BITS_PER_WIDE_INT
9785 && (nonzero_bits (op0, mode)
9786 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9791 /* >= C is equivalent to > (C - 1). */
9795 op1 = GEN_INT (const_op);
9797 /* ... fall through to GT below. */
9803 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9807 op1 = GEN_INT (const_op);
9811 /* If we are doing a > 0 comparison on a value known to have
9812 a zero sign bit, we can replace this with != 0. */
9813 else if (const_op == 0
9814 && mode_width <= HOST_BITS_PER_WIDE_INT
9815 && (nonzero_bits (op0, mode)
9816 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9821 /* < C is equivalent to <= (C - 1). */
9825 op1 = GEN_INT (const_op);
9827 /* ... fall through ... */
9830 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9831 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9832 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9834 const_op = 0, op1 = const0_rtx;
9842 /* unsigned <= 0 is equivalent to == 0 */
9846 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9847 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9848 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9850 const_op = 0, op1 = const0_rtx;
9856 /* >= C is equivalent to > (C - 1). */
9860 op1 = GEN_INT (const_op);
9862 /* ... fall through ... */
9865 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9866 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9867 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9869 const_op = 0, op1 = const0_rtx;
9877 /* unsigned > 0 is equivalent to != 0 */
9881 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9882 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9883 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9885 const_op = 0, op1 = const0_rtx;
9894 /* Compute some predicates to simplify code below. */
9896 equality_comparison_p = (code == EQ || code == NE);
9897 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9898 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9901 /* If this is a sign bit comparison and we can do arithmetic in
9902 MODE, say that we will only be needing the sign bit of OP0. */
9903 if (sign_bit_comparison_p
9904 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9905 op0 = force_to_mode (op0, mode,
9907 << (GET_MODE_BITSIZE (mode) - 1)),
9910 /* Now try cases based on the opcode of OP0. If none of the cases
9911 does a "continue", we exit this loop immediately after the
9914 switch (GET_CODE (op0))
9917 /* If we are extracting a single bit from a variable position in
9918 a constant that has only a single bit set and are comparing it
9919 with zero, we can convert this into an equality comparison
9920 between the position and the location of the single bit. */
9921 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9922 have already reduced the shift count modulo the word size. */
9923 if (!SHIFT_COUNT_TRUNCATED
9924 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9925 && XEXP (op0, 1) == const1_rtx
9926 && equality_comparison_p && const_op == 0
9927 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9929 if (BITS_BIG_ENDIAN)
9931 enum machine_mode new_mode
9932 = mode_for_extraction (EP_extzv, 1);
9933 if (new_mode == MAX_MACHINE_MODE)
9934 i = BITS_PER_WORD - 1 - i;
9938 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9942 op0 = XEXP (op0, 2);
9946 /* Result is nonzero iff shift count is equal to I. */
9947 code = reverse_condition (code);
9951 /* ... fall through ... */
9954 tem = expand_compound_operation (op0);
9963 /* If testing for equality, we can take the NOT of the constant. */
9964 if (equality_comparison_p
9965 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9967 op0 = XEXP (op0, 0);
9972 /* If just looking at the sign bit, reverse the sense of the
9974 if (sign_bit_comparison_p)
9976 op0 = XEXP (op0, 0);
9977 code = (code == GE ? LT : GE);
9983 /* If testing for equality, we can take the NEG of the constant. */
9984 if (equality_comparison_p
9985 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9987 op0 = XEXP (op0, 0);
9992 /* The remaining cases only apply to comparisons with zero. */
9996 /* When X is ABS or is known positive,
9997 (neg X) is < 0 if and only if X != 0. */
9999 if (sign_bit_comparison_p
10000 && (GET_CODE (XEXP (op0, 0)) == ABS
10001 || (mode_width <= HOST_BITS_PER_WIDE_INT
10002 && (nonzero_bits (XEXP (op0, 0), mode)
10003 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10005 op0 = XEXP (op0, 0);
10006 code = (code == LT ? NE : EQ);
10010 /* If we have NEG of something whose two high-order bits are the
10011 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10012 if (num_sign_bit_copies (op0, mode) >= 2)
10014 op0 = XEXP (op0, 0);
10015 code = swap_condition (code);
10021 /* If we are testing equality and our count is a constant, we
10022 can perform the inverse operation on our RHS. */
10023 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10024 && (tem = simplify_binary_operation (ROTATERT, mode,
10025 op1, XEXP (op0, 1))) != 0)
10027 op0 = XEXP (op0, 0);
10032 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10033 a particular bit. Convert it to an AND of a constant of that
10034 bit. This will be converted into a ZERO_EXTRACT. */
10035 if (const_op == 0 && sign_bit_comparison_p
10036 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10037 && mode_width <= HOST_BITS_PER_WIDE_INT)
10039 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10042 - INTVAL (XEXP (op0, 1)))));
10043 code = (code == LT ? NE : EQ);
10047 /* Fall through. */
10050 /* ABS is ignorable inside an equality comparison with zero. */
10051 if (const_op == 0 && equality_comparison_p)
10053 op0 = XEXP (op0, 0);
10059 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10060 (compare FOO CONST) if CONST fits in FOO's mode and we
10061 are either testing inequality or have an unsigned
10062 comparison with ZERO_EXTEND or a signed comparison with
10063 SIGN_EXTEND. But don't do it if we don't have a compare
10064 insn of the given mode, since we'd have to revert it
10065 later on, and then we wouldn't know whether to sign- or
10067 mode = GET_MODE (XEXP (op0, 0));
10068 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10069 && ! unsigned_comparison_p
10070 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10071 && ((unsigned HOST_WIDE_INT) const_op
10072 < (((unsigned HOST_WIDE_INT) 1
10073 << (GET_MODE_BITSIZE (mode) - 1))))
10074 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10076 op0 = XEXP (op0, 0);
10082 /* Check for the case where we are comparing A - C1 with C2, that is
10084 (subreg:MODE (plus (A) (-C1))) op (C2)
10086 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10087 comparison in the wider mode. One of the following two conditions
10088 must be true in order for this to be valid:
10090 1. The mode extension results in the same bit pattern being added
10091 on both sides and the comparison is equality or unsigned. As
10092 C2 has been truncated to fit in MODE, the pattern can only be
10095 2. The mode extension results in the sign bit being copied on
10098 The difficulty here is that we have predicates for A but not for
10099 (A - C1) so we need to check that C1 is within proper bounds so
10100 as to perturbate A as little as possible. */
10102 if (mode_width <= HOST_BITS_PER_WIDE_INT
10103 && subreg_lowpart_p (op0)
10104 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10105 && GET_CODE (SUBREG_REG (op0)) == PLUS
10106 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10108 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10109 rtx a = XEXP (SUBREG_REG (op0), 0);
10110 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10113 && (unsigned HOST_WIDE_INT) c1
10114 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10115 && (equality_comparison_p || unsigned_comparison_p)
10116 /* (A - C1) zero-extends if it is positive and sign-extends
10117 if it is negative, C2 both zero- and sign-extends. */
10118 && ((0 == (nonzero_bits (a, inner_mode)
10119 & ~GET_MODE_MASK (mode))
10121 /* (A - C1) sign-extends if it is positive and 1-extends
10122 if it is negative, C2 both sign- and 1-extends. */
10123 || (num_sign_bit_copies (a, inner_mode)
10124 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10127 || ((unsigned HOST_WIDE_INT) c1
10128 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10129 /* (A - C1) always sign-extends, like C2. */
10130 && num_sign_bit_copies (a, inner_mode)
10131 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10132 - mode_width - 1)))
10134 op0 = SUBREG_REG (op0);
10139 /* If the inner mode is narrower and we are extracting the low part,
10140 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10141 if (subreg_lowpart_p (op0)
10142 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10143 /* Fall through */ ;
10147 /* ... fall through ... */
10150 mode = GET_MODE (XEXP (op0, 0));
10151 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10152 && (unsigned_comparison_p || equality_comparison_p)
10153 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10154 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10155 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10157 op0 = XEXP (op0, 0);
10163 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10164 this for equality comparisons due to pathological cases involving
10166 if (equality_comparison_p
10167 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10168 op1, XEXP (op0, 1))))
10170 op0 = XEXP (op0, 0);
10175 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10176 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10177 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10179 op0 = XEXP (XEXP (op0, 0), 0);
10180 code = (code == LT ? EQ : NE);
10186 /* We used to optimize signed comparisons against zero, but that
10187 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10188 arrive here as equality comparisons, or (GEU, LTU) are
10189 optimized away. No need to special-case them. */
10191 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10192 (eq B (minus A C)), whichever simplifies. We can only do
10193 this for equality comparisons due to pathological cases involving
10195 if (equality_comparison_p
10196 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10197 XEXP (op0, 1), op1)))
10199 op0 = XEXP (op0, 0);
10204 if (equality_comparison_p
10205 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10206 XEXP (op0, 0), op1)))
10208 op0 = XEXP (op0, 1);
10213 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10214 of bits in X minus 1, is one iff X > 0. */
10215 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10216 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10217 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10219 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10221 op0 = XEXP (op0, 1);
10222 code = (code == GE ? LE : GT);
10228 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10229 if C is zero or B is a constant. */
10230 if (equality_comparison_p
10231 && 0 != (tem = simplify_binary_operation (XOR, mode,
10232 XEXP (op0, 1), op1)))
10234 op0 = XEXP (op0, 0);
10241 case UNEQ: case LTGT:
10242 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10243 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10244 case UNORDERED: case ORDERED:
10245 /* We can't do anything if OP0 is a condition code value, rather
10246 than an actual data value. */
10248 || CC0_P (XEXP (op0, 0))
10249 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10252 /* Get the two operands being compared. */
10253 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10254 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10256 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10258 /* Check for the cases where we simply want the result of the
10259 earlier test or the opposite of that result. */
10260 if (code == NE || code == EQ
10261 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10262 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10263 && (STORE_FLAG_VALUE
10264 & (((HOST_WIDE_INT) 1
10265 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10266 && (code == LT || code == GE)))
10268 enum rtx_code new_code;
10269 if (code == LT || code == NE)
10270 new_code = GET_CODE (op0);
10272 new_code = combine_reversed_comparison_code (op0);
10274 if (new_code != UNKNOWN)
10285 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10287 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10288 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10289 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10291 op0 = XEXP (op0, 1);
10292 code = (code == GE ? GT : LE);
10298 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10299 will be converted to a ZERO_EXTRACT later. */
10300 if (const_op == 0 && equality_comparison_p
10301 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10302 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10304 op0 = simplify_and_const_int
10305 (op0, mode, gen_rtx_LSHIFTRT (mode,
10307 XEXP (XEXP (op0, 0), 1)),
10308 (HOST_WIDE_INT) 1);
10312 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10313 zero and X is a comparison and C1 and C2 describe only bits set
10314 in STORE_FLAG_VALUE, we can compare with X. */
10315 if (const_op == 0 && equality_comparison_p
10316 && mode_width <= HOST_BITS_PER_WIDE_INT
10317 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10318 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10319 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10320 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10321 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10323 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10324 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10325 if ((~STORE_FLAG_VALUE & mask) == 0
10326 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10327 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10328 && COMPARISON_P (tem))))
10330 op0 = XEXP (XEXP (op0, 0), 0);
10335 /* If we are doing an equality comparison of an AND of a bit equal
10336 to the sign bit, replace this with a LT or GE comparison of
10337 the underlying value. */
10338 if (equality_comparison_p
10340 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10341 && mode_width <= HOST_BITS_PER_WIDE_INT
10342 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10343 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10345 op0 = XEXP (op0, 0);
10346 code = (code == EQ ? GE : LT);
10350 /* If this AND operation is really a ZERO_EXTEND from a narrower
10351 mode, the constant fits within that mode, and this is either an
10352 equality or unsigned comparison, try to do this comparison in
10353 the narrower mode. */
10354 if ((equality_comparison_p || unsigned_comparison_p)
10355 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10356 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10357 & GET_MODE_MASK (mode))
10359 && const_op >> i == 0
10360 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10362 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10366 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10367 fits in both M1 and M2 and the SUBREG is either paradoxical
10368 or represents the low part, permute the SUBREG and the AND
10370 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10372 unsigned HOST_WIDE_INT c1;
10373 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10374 /* Require an integral mode, to avoid creating something like
10376 if (SCALAR_INT_MODE_P (tmode)
10377 /* It is unsafe to commute the AND into the SUBREG if the
10378 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10379 not defined. As originally written the upper bits
10380 have a defined value due to the AND operation.
10381 However, if we commute the AND inside the SUBREG then
10382 they no longer have defined values and the meaning of
10383 the code has been changed. */
10385 #ifdef WORD_REGISTER_OPERATIONS
10386 || (mode_width > GET_MODE_BITSIZE (tmode)
10387 && mode_width <= BITS_PER_WORD)
10389 || (mode_width <= GET_MODE_BITSIZE (tmode)
10390 && subreg_lowpart_p (XEXP (op0, 0))))
10391 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10392 && mode_width <= HOST_BITS_PER_WIDE_INT
10393 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10394 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10395 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10397 && c1 != GET_MODE_MASK (tmode))
10399 op0 = gen_binary (AND, tmode,
10400 SUBREG_REG (XEXP (op0, 0)),
10401 gen_int_mode (c1, tmode));
10402 op0 = gen_lowpart (mode, op0);
10407 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10408 if (const_op == 0 && equality_comparison_p
10409 && XEXP (op0, 1) == const1_rtx
10410 && GET_CODE (XEXP (op0, 0)) == NOT)
10412 op0 = simplify_and_const_int
10413 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10414 code = (code == NE ? EQ : NE);
10418 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10419 (eq (and (lshiftrt X) 1) 0).
10420 Also handle the case where (not X) is expressed using xor. */
10421 if (const_op == 0 && equality_comparison_p
10422 && XEXP (op0, 1) == const1_rtx
10423 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10425 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10426 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10428 if (GET_CODE (shift_op) == NOT
10429 || (GET_CODE (shift_op) == XOR
10430 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10431 && GET_CODE (shift_count) == CONST_INT
10432 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10433 && (INTVAL (XEXP (shift_op, 1))
10434 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10436 op0 = simplify_and_const_int
10438 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10439 (HOST_WIDE_INT) 1);
10440 code = (code == NE ? EQ : NE);
10447 /* If we have (compare (ashift FOO N) (const_int C)) and
10448 the high order N bits of FOO (N+1 if an inequality comparison)
10449 are known to be zero, we can do this by comparing FOO with C
10450 shifted right N bits so long as the low-order N bits of C are
10452 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10453 && INTVAL (XEXP (op0, 1)) >= 0
10454 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10455 < HOST_BITS_PER_WIDE_INT)
10457 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10458 && mode_width <= HOST_BITS_PER_WIDE_INT
10459 && (nonzero_bits (XEXP (op0, 0), mode)
10460 & ~(mask >> (INTVAL (XEXP (op0, 1))
10461 + ! equality_comparison_p))) == 0)
10463 /* We must perform a logical shift, not an arithmetic one,
10464 as we want the top N bits of C to be zero. */
10465 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10467 temp >>= INTVAL (XEXP (op0, 1));
10468 op1 = gen_int_mode (temp, mode);
10469 op0 = XEXP (op0, 0);
10473 /* If we are doing a sign bit comparison, it means we are testing
10474 a particular bit. Convert it to the appropriate AND. */
10475 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10476 && mode_width <= HOST_BITS_PER_WIDE_INT)
10478 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10481 - INTVAL (XEXP (op0, 1)))));
10482 code = (code == LT ? NE : EQ);
10486 /* If this an equality comparison with zero and we are shifting
10487 the low bit to the sign bit, we can convert this to an AND of the
10489 if (const_op == 0 && equality_comparison_p
10490 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10491 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10494 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10495 (HOST_WIDE_INT) 1);
10501 /* If this is an equality comparison with zero, we can do this
10502 as a logical shift, which might be much simpler. */
10503 if (equality_comparison_p && const_op == 0
10504 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10506 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10508 INTVAL (XEXP (op0, 1)));
10512 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10513 do the comparison in a narrower mode. */
10514 if (! unsigned_comparison_p
10515 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10516 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10517 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10518 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10519 MODE_INT, 1)) != BLKmode
10520 && (((unsigned HOST_WIDE_INT) const_op
10521 + (GET_MODE_MASK (tmode) >> 1) + 1)
10522 <= GET_MODE_MASK (tmode)))
10524 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10528 /* Likewise if OP0 is a PLUS of a sign extension with a
10529 constant, which is usually represented with the PLUS
10530 between the shifts. */
10531 if (! unsigned_comparison_p
10532 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10533 && GET_CODE (XEXP (op0, 0)) == PLUS
10534 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10535 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10536 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10537 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10538 MODE_INT, 1)) != BLKmode
10539 && (((unsigned HOST_WIDE_INT) const_op
10540 + (GET_MODE_MASK (tmode) >> 1) + 1)
10541 <= GET_MODE_MASK (tmode)))
10543 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10544 rtx add_const = XEXP (XEXP (op0, 0), 1);
10545 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10548 op0 = gen_binary (PLUS, tmode,
10549 gen_lowpart (tmode, inner),
10554 /* ... fall through ... */
10556 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10557 the low order N bits of FOO are known to be zero, we can do this
10558 by comparing FOO with C shifted left N bits so long as no
10559 overflow occurs. */
10560 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10561 && INTVAL (XEXP (op0, 1)) >= 0
10562 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10563 && mode_width <= HOST_BITS_PER_WIDE_INT
10564 && (nonzero_bits (XEXP (op0, 0), mode)
10565 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10566 && (((unsigned HOST_WIDE_INT) const_op
10567 + (GET_CODE (op0) != LSHIFTRT
10568 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10571 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10573 /* If the shift was logical, then we must make the condition
10575 if (GET_CODE (op0) == LSHIFTRT)
10576 code = unsigned_condition (code);
10578 const_op <<= INTVAL (XEXP (op0, 1));
10579 op1 = GEN_INT (const_op);
10580 op0 = XEXP (op0, 0);
10584 /* If we are using this shift to extract just the sign bit, we
10585 can replace this with an LT or GE comparison. */
10587 && (equality_comparison_p || sign_bit_comparison_p)
10588 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10589 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10592 op0 = XEXP (op0, 0);
10593 code = (code == NE || code == GT ? LT : GE);
10605 /* Now make any compound operations involved in this comparison. Then,
10606 check for an outmost SUBREG on OP0 that is not doing anything or is
10607 paradoxical. The latter transformation must only be performed when
10608 it is known that the "extra" bits will be the same in op0 and op1 or
10609 that they don't matter. There are three cases to consider:
10611 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10612 care bits and we can assume they have any convenient value. So
10613 making the transformation is safe.
10615 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10616 In this case the upper bits of op0 are undefined. We should not make
10617 the simplification in that case as we do not know the contents of
10620 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10621 UNKNOWN. In that case we know those bits are zeros or ones. We must
10622 also be sure that they are the same as the upper bits of op1.
10624 We can never remove a SUBREG for a non-equality comparison because
10625 the sign bit is in a different place in the underlying object. */
10627 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10628 op1 = make_compound_operation (op1, SET);
10630 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10631 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10632 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10633 && (code == NE || code == EQ))
10635 if (GET_MODE_SIZE (GET_MODE (op0))
10636 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10638 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10640 if (REG_P (SUBREG_REG (op0)))
10642 op0 = SUBREG_REG (op0);
10643 op1 = gen_lowpart (GET_MODE (op0), op1);
10646 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10647 <= HOST_BITS_PER_WIDE_INT)
10648 && (nonzero_bits (SUBREG_REG (op0),
10649 GET_MODE (SUBREG_REG (op0)))
10650 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10652 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10654 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10655 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10656 op0 = SUBREG_REG (op0), op1 = tem;
10660 /* We now do the opposite procedure: Some machines don't have compare
10661 insns in all modes. If OP0's mode is an integer mode smaller than a
10662 word and we can't do a compare in that mode, see if there is a larger
10663 mode for which we can do the compare. There are a number of cases in
10664 which we can use the wider mode. */
10666 mode = GET_MODE (op0);
10667 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10668 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10669 && ! have_insn_for (COMPARE, mode))
10670 for (tmode = GET_MODE_WIDER_MODE (mode);
10672 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10673 tmode = GET_MODE_WIDER_MODE (tmode))
10674 if (have_insn_for (COMPARE, tmode))
10678 /* If the only nonzero bits in OP0 and OP1 are those in the
10679 narrower mode and this is an equality or unsigned comparison,
10680 we can use the wider mode. Similarly for sign-extended
10681 values, in which case it is true for all comparisons. */
10682 zero_extended = ((code == EQ || code == NE
10683 || code == GEU || code == GTU
10684 || code == LEU || code == LTU)
10685 && (nonzero_bits (op0, tmode)
10686 & ~GET_MODE_MASK (mode)) == 0
10687 && ((GET_CODE (op1) == CONST_INT
10688 || (nonzero_bits (op1, tmode)
10689 & ~GET_MODE_MASK (mode)) == 0)));
10692 || ((num_sign_bit_copies (op0, tmode)
10693 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10694 - GET_MODE_BITSIZE (mode)))
10695 && (num_sign_bit_copies (op1, tmode)
10696 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10697 - GET_MODE_BITSIZE (mode)))))
10699 /* If OP0 is an AND and we don't have an AND in MODE either,
10700 make a new AND in the proper mode. */
10701 if (GET_CODE (op0) == AND
10702 && !have_insn_for (AND, mode))
10703 op0 = gen_binary (AND, tmode,
10704 gen_lowpart (tmode,
10706 gen_lowpart (tmode,
10709 op0 = gen_lowpart (tmode, op0);
10710 if (zero_extended && GET_CODE (op1) == CONST_INT)
10711 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10712 op1 = gen_lowpart (tmode, op1);
10716 /* If this is a test for negative, we can make an explicit
10717 test of the sign bit. */
10719 if (op1 == const0_rtx && (code == LT || code == GE)
10720 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10722 op0 = gen_binary (AND, tmode,
10723 gen_lowpart (tmode, op0),
10724 GEN_INT ((HOST_WIDE_INT) 1
10725 << (GET_MODE_BITSIZE (mode) - 1)));
10726 code = (code == LT) ? NE : EQ;
10731 #ifdef CANONICALIZE_COMPARISON
10732 /* If this machine only supports a subset of valid comparisons, see if we
10733 can convert an unsupported one into a supported one. */
10734 CANONICALIZE_COMPARISON (code, op0, op1);
10743 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10744 searching backward. */
10745 static enum rtx_code
10746 combine_reversed_comparison_code (rtx exp)
10748 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10751 if (code1 != UNKNOWN
10752 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10754 /* Otherwise try and find where the condition codes were last set and
10756 x = get_last_value (XEXP (exp, 0));
10757 if (!x || GET_CODE (x) != COMPARE)
10759 return reversed_comparison_code_parts (GET_CODE (exp),
10760 XEXP (x, 0), XEXP (x, 1), NULL);
10763 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10764 Return NULL_RTX in case we fail to do the reversal. */
10766 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
10768 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10769 if (reversed_code == UNKNOWN)
10772 return gen_binary (reversed_code, mode, op0, op1);
10775 /* Utility function for record_value_for_reg. Count number of
10780 enum rtx_code code = GET_CODE (x);
10784 if (GET_RTX_CLASS (code) == '2'
10785 || GET_RTX_CLASS (code) == 'c')
10787 rtx x0 = XEXP (x, 0);
10788 rtx x1 = XEXP (x, 1);
10791 return 1 + 2 * count_rtxs (x0);
10793 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10794 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10795 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10796 return 2 + 2 * count_rtxs (x0)
10797 + count_rtxs (x == XEXP (x1, 0)
10798 ? XEXP (x1, 1) : XEXP (x1, 0));
10800 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10801 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10802 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10803 return 2 + 2 * count_rtxs (x1)
10804 + count_rtxs (x == XEXP (x0, 0)
10805 ? XEXP (x0, 1) : XEXP (x0, 0));
10808 fmt = GET_RTX_FORMAT (code);
10809 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10811 ret += count_rtxs (XEXP (x, i));
10816 /* Utility function for following routine. Called when X is part of a value
10817 being stored into last_set_value. Sets last_set_table_tick
10818 for each register mentioned. Similar to mention_regs in cse.c */
10821 update_table_tick (rtx x)
10823 enum rtx_code code = GET_CODE (x);
10824 const char *fmt = GET_RTX_FORMAT (code);
10829 unsigned int regno = REGNO (x);
10830 unsigned int endregno
10831 = regno + (regno < FIRST_PSEUDO_REGISTER
10832 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10835 for (r = regno; r < endregno; r++)
10836 reg_stat[r].last_set_table_tick = label_tick;
10841 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10842 /* Note that we can't have an "E" in values stored; see
10843 get_last_value_validate. */
10846 /* Check for identical subexpressions. If x contains
10847 identical subexpression we only have to traverse one of
10849 if (i == 0 && ARITHMETIC_P (x))
10851 /* Note that at this point x1 has already been
10853 rtx x0 = XEXP (x, 0);
10854 rtx x1 = XEXP (x, 1);
10856 /* If x0 and x1 are identical then there is no need to
10861 /* If x0 is identical to a subexpression of x1 then while
10862 processing x1, x0 has already been processed. Thus we
10863 are done with x. */
10864 if (ARITHMETIC_P (x1)
10865 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10868 /* If x1 is identical to a subexpression of x0 then we
10869 still have to process the rest of x0. */
10870 if (ARITHMETIC_P (x0)
10871 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10873 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10878 update_table_tick (XEXP (x, i));
10882 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10883 are saying that the register is clobbered and we no longer know its
10884 value. If INSN is zero, don't update reg_stat[].last_set; this is
10885 only permitted with VALUE also zero and is used to invalidate the
10889 record_value_for_reg (rtx reg, rtx insn, rtx value)
10891 unsigned int regno = REGNO (reg);
10892 unsigned int endregno
10893 = regno + (regno < FIRST_PSEUDO_REGISTER
10894 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10897 /* If VALUE contains REG and we have a previous value for REG, substitute
10898 the previous value. */
10899 if (value && insn && reg_overlap_mentioned_p (reg, value))
10903 /* Set things up so get_last_value is allowed to see anything set up to
10905 subst_low_cuid = INSN_CUID (insn);
10906 tem = get_last_value (reg);
10908 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10909 it isn't going to be useful and will take a lot of time to process,
10910 so just use the CLOBBER. */
10914 if (ARITHMETIC_P (tem)
10915 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10916 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10917 tem = XEXP (tem, 0);
10918 else if (count_occurrences (value, reg, 1) >= 2)
10920 /* If there are two or more occurrences of REG in VALUE,
10921 prevent the value from growing too much. */
10922 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10923 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10926 value = replace_rtx (copy_rtx (value), reg, tem);
10930 /* For each register modified, show we don't know its value, that
10931 we don't know about its bitwise content, that its value has been
10932 updated, and that we don't know the location of the death of the
10934 for (i = regno; i < endregno; i++)
10937 reg_stat[i].last_set = insn;
10939 reg_stat[i].last_set_value = 0;
10940 reg_stat[i].last_set_mode = 0;
10941 reg_stat[i].last_set_nonzero_bits = 0;
10942 reg_stat[i].last_set_sign_bit_copies = 0;
10943 reg_stat[i].last_death = 0;
10946 /* Mark registers that are being referenced in this value. */
10948 update_table_tick (value);
10950 /* Now update the status of each register being set.
10951 If someone is using this register in this block, set this register
10952 to invalid since we will get confused between the two lives in this
10953 basic block. This makes using this register always invalid. In cse, we
10954 scan the table to invalidate all entries using this register, but this
10955 is too much work for us. */
10957 for (i = regno; i < endregno; i++)
10959 reg_stat[i].last_set_label = label_tick;
10960 if (value && reg_stat[i].last_set_table_tick == label_tick)
10961 reg_stat[i].last_set_invalid = 1;
10963 reg_stat[i].last_set_invalid = 0;
10966 /* The value being assigned might refer to X (like in "x++;"). In that
10967 case, we must replace it with (clobber (const_int 0)) to prevent
10969 if (value && ! get_last_value_validate (&value, insn,
10970 reg_stat[regno].last_set_label, 0))
10972 value = copy_rtx (value);
10973 if (! get_last_value_validate (&value, insn,
10974 reg_stat[regno].last_set_label, 1))
10978 /* For the main register being modified, update the value, the mode, the
10979 nonzero bits, and the number of sign bit copies. */
10981 reg_stat[regno].last_set_value = value;
10985 enum machine_mode mode = GET_MODE (reg);
10986 subst_low_cuid = INSN_CUID (insn);
10987 reg_stat[regno].last_set_mode = mode;
10988 if (GET_MODE_CLASS (mode) == MODE_INT
10989 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10990 mode = nonzero_bits_mode;
10991 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10992 reg_stat[regno].last_set_sign_bit_copies
10993 = num_sign_bit_copies (value, GET_MODE (reg));
10997 /* Called via note_stores from record_dead_and_set_regs to handle one
10998 SET or CLOBBER in an insn. DATA is the instruction in which the
10999 set is occurring. */
11002 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11004 rtx record_dead_insn = (rtx) data;
11006 if (GET_CODE (dest) == SUBREG)
11007 dest = SUBREG_REG (dest);
11011 /* If we are setting the whole register, we know its value. Otherwise
11012 show that we don't know the value. We can handle SUBREG in
11014 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11015 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11016 else if (GET_CODE (setter) == SET
11017 && GET_CODE (SET_DEST (setter)) == SUBREG
11018 && SUBREG_REG (SET_DEST (setter)) == dest
11019 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11020 && subreg_lowpart_p (SET_DEST (setter)))
11021 record_value_for_reg (dest, record_dead_insn,
11022 gen_lowpart (GET_MODE (dest),
11023 SET_SRC (setter)));
11025 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11027 else if (MEM_P (dest)
11028 /* Ignore pushes, they clobber nothing. */
11029 && ! push_operand (dest, GET_MODE (dest)))
11030 mem_last_set = INSN_CUID (record_dead_insn);
11033 /* Update the records of when each REG was most recently set or killed
11034 for the things done by INSN. This is the last thing done in processing
11035 INSN in the combiner loop.
11037 We update reg_stat[], in particular fields last_set, last_set_value,
11038 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11039 last_death, and also the similar information mem_last_set (which insn
11040 most recently modified memory) and last_call_cuid (which insn was the
11041 most recent subroutine call). */
11044 record_dead_and_set_regs (rtx insn)
11049 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11051 if (REG_NOTE_KIND (link) == REG_DEAD
11052 && REG_P (XEXP (link, 0)))
11054 unsigned int regno = REGNO (XEXP (link, 0));
11055 unsigned int endregno
11056 = regno + (regno < FIRST_PSEUDO_REGISTER
11057 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11060 for (i = regno; i < endregno; i++)
11061 reg_stat[i].last_death = insn;
11063 else if (REG_NOTE_KIND (link) == REG_INC)
11064 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11069 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11070 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11072 reg_stat[i].last_set_value = 0;
11073 reg_stat[i].last_set_mode = 0;
11074 reg_stat[i].last_set_nonzero_bits = 0;
11075 reg_stat[i].last_set_sign_bit_copies = 0;
11076 reg_stat[i].last_death = 0;
11079 last_call_cuid = mem_last_set = INSN_CUID (insn);
11081 /* Don't bother recording what this insn does. It might set the
11082 return value register, but we can't combine into a call
11083 pattern anyway, so there's no point trying (and it may cause
11084 a crash, if e.g. we wind up asking for last_set_value of a
11085 SUBREG of the return value register). */
11089 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11092 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11093 register present in the SUBREG, so for each such SUBREG go back and
11094 adjust nonzero and sign bit information of the registers that are
11095 known to have some zero/sign bits set.
11097 This is needed because when combine blows the SUBREGs away, the
11098 information on zero/sign bits is lost and further combines can be
11099 missed because of that. */
11102 record_promoted_value (rtx insn, rtx subreg)
11105 unsigned int regno = REGNO (SUBREG_REG (subreg));
11106 enum machine_mode mode = GET_MODE (subreg);
11108 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11111 for (links = LOG_LINKS (insn); links;)
11113 insn = XEXP (links, 0);
11114 set = single_set (insn);
11116 if (! set || !REG_P (SET_DEST (set))
11117 || REGNO (SET_DEST (set)) != regno
11118 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11120 links = XEXP (links, 1);
11124 if (reg_stat[regno].last_set == insn)
11126 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11127 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11130 if (REG_P (SET_SRC (set)))
11132 regno = REGNO (SET_SRC (set));
11133 links = LOG_LINKS (insn);
11140 /* Scan X for promoted SUBREGs. For each one found,
11141 note what it implies to the registers used in it. */
11144 check_promoted_subreg (rtx insn, rtx x)
11146 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11147 && REG_P (SUBREG_REG (x)))
11148 record_promoted_value (insn, x);
11151 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11154 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11158 check_promoted_subreg (insn, XEXP (x, i));
11162 if (XVEC (x, i) != 0)
11163 for (j = 0; j < XVECLEN (x, i); j++)
11164 check_promoted_subreg (insn, XVECEXP (x, i, j));
11170 /* Utility routine for the following function. Verify that all the registers
11171 mentioned in *LOC are valid when *LOC was part of a value set when
11172 label_tick == TICK. Return 0 if some are not.
11174 If REPLACE is nonzero, replace the invalid reference with
11175 (clobber (const_int 0)) and return 1. This replacement is useful because
11176 we often can get useful information about the form of a value (e.g., if
11177 it was produced by a shift that always produces -1 or 0) even though
11178 we don't know exactly what registers it was produced from. */
11181 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11184 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11185 int len = GET_RTX_LENGTH (GET_CODE (x));
11190 unsigned int regno = REGNO (x);
11191 unsigned int endregno
11192 = regno + (regno < FIRST_PSEUDO_REGISTER
11193 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11196 for (j = regno; j < endregno; j++)
11197 if (reg_stat[j].last_set_invalid
11198 /* If this is a pseudo-register that was only set once and not
11199 live at the beginning of the function, it is always valid. */
11200 || (! (regno >= FIRST_PSEUDO_REGISTER
11201 && REG_N_SETS (regno) == 1
11202 && (! REGNO_REG_SET_P
11203 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11204 && reg_stat[j].last_set_label > tick))
11207 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11213 /* If this is a memory reference, make sure that there were
11214 no stores after it that might have clobbered the value. We don't
11215 have alias info, so we assume any store invalidates it. */
11216 else if (MEM_P (x) && !MEM_READONLY_P (x)
11217 && INSN_CUID (insn) <= mem_last_set)
11220 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11224 for (i = 0; i < len; i++)
11228 /* Check for identical subexpressions. If x contains
11229 identical subexpression we only have to traverse one of
11231 if (i == 1 && ARITHMETIC_P (x))
11233 /* Note that at this point x0 has already been checked
11234 and found valid. */
11235 rtx x0 = XEXP (x, 0);
11236 rtx x1 = XEXP (x, 1);
11238 /* If x0 and x1 are identical then x is also valid. */
11242 /* If x1 is identical to a subexpression of x0 then
11243 while checking x0, x1 has already been checked. Thus
11244 it is valid and so as x. */
11245 if (ARITHMETIC_P (x0)
11246 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11249 /* If x0 is identical to a subexpression of x1 then x is
11250 valid iff the rest of x1 is valid. */
11251 if (ARITHMETIC_P (x1)
11252 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11254 get_last_value_validate (&XEXP (x1,
11255 x0 == XEXP (x1, 0) ? 1 : 0),
11256 insn, tick, replace);
11259 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11263 /* Don't bother with these. They shouldn't occur anyway. */
11264 else if (fmt[i] == 'E')
11268 /* If we haven't found a reason for it to be invalid, it is valid. */
11272 /* Get the last value assigned to X, if known. Some registers
11273 in the value may be replaced with (clobber (const_int 0)) if their value
11274 is known longer known reliably. */
11277 get_last_value (rtx x)
11279 unsigned int regno;
11282 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11283 then convert it to the desired mode. If this is a paradoxical SUBREG,
11284 we cannot predict what values the "extra" bits might have. */
11285 if (GET_CODE (x) == SUBREG
11286 && subreg_lowpart_p (x)
11287 && (GET_MODE_SIZE (GET_MODE (x))
11288 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11289 && (value = get_last_value (SUBREG_REG (x))) != 0)
11290 return gen_lowpart (GET_MODE (x), value);
11296 value = reg_stat[regno].last_set_value;
11298 /* If we don't have a value, or if it isn't for this basic block and
11299 it's either a hard register, set more than once, or it's a live
11300 at the beginning of the function, return 0.
11302 Because if it's not live at the beginning of the function then the reg
11303 is always set before being used (is never used without being set).
11304 And, if it's set only once, and it's always set before use, then all
11305 uses must have the same last value, even if it's not from this basic
11309 || (reg_stat[regno].last_set_label != label_tick
11310 && (regno < FIRST_PSEUDO_REGISTER
11311 || REG_N_SETS (regno) != 1
11312 || (REGNO_REG_SET_P
11313 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11316 /* If the value was set in a later insn than the ones we are processing,
11317 we can't use it even if the register was only set once. */
11318 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11321 /* If the value has all its registers valid, return it. */
11322 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11323 reg_stat[regno].last_set_label, 0))
11326 /* Otherwise, make a copy and replace any invalid register with
11327 (clobber (const_int 0)). If that fails for some reason, return 0. */
11329 value = copy_rtx (value);
11330 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11331 reg_stat[regno].last_set_label, 1))
11337 /* Return nonzero if expression X refers to a REG or to memory
11338 that is set in an instruction more recent than FROM_CUID. */
11341 use_crosses_set_p (rtx x, int from_cuid)
11345 enum rtx_code code = GET_CODE (x);
11349 unsigned int regno = REGNO (x);
11350 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11351 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11353 #ifdef PUSH_ROUNDING
11354 /* Don't allow uses of the stack pointer to be moved,
11355 because we don't know whether the move crosses a push insn. */
11356 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11359 for (; regno < endreg; regno++)
11360 if (reg_stat[regno].last_set
11361 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11366 if (code == MEM && mem_last_set > from_cuid)
11369 fmt = GET_RTX_FORMAT (code);
11371 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11376 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11377 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11380 else if (fmt[i] == 'e'
11381 && use_crosses_set_p (XEXP (x, i), from_cuid))
11387 /* Define three variables used for communication between the following
11390 static unsigned int reg_dead_regno, reg_dead_endregno;
11391 static int reg_dead_flag;
11393 /* Function called via note_stores from reg_dead_at_p.
11395 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11396 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11399 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11401 unsigned int regno, endregno;
11406 regno = REGNO (dest);
11407 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11408 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11410 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11411 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11414 /* Return nonzero if REG is known to be dead at INSN.
11416 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11417 referencing REG, it is dead. If we hit a SET referencing REG, it is
11418 live. Otherwise, see if it is live or dead at the start of the basic
11419 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11420 must be assumed to be always live. */
11423 reg_dead_at_p (rtx reg, rtx insn)
11428 /* Set variables for reg_dead_at_p_1. */
11429 reg_dead_regno = REGNO (reg);
11430 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11431 ? hard_regno_nregs[reg_dead_regno]
11437 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11438 we allow the machine description to decide whether use-and-clobber
11439 patterns are OK. */
11440 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11442 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11443 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11447 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11448 beginning of function. */
11449 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11450 insn = prev_nonnote_insn (insn))
11452 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11454 return reg_dead_flag == 1 ? 1 : 0;
11456 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11460 /* Get the basic block that we were in. */
11462 block = ENTRY_BLOCK_PTR->next_bb;
11465 FOR_EACH_BB (block)
11466 if (insn == BB_HEAD (block))
11469 if (block == EXIT_BLOCK_PTR)
11473 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11474 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11480 /* Note hard registers in X that are used. This code is similar to
11481 that in flow.c, but much simpler since we don't care about pseudos. */
11484 mark_used_regs_combine (rtx x)
11486 RTX_CODE code = GET_CODE (x);
11487 unsigned int regno;
11500 case ADDR_DIFF_VEC:
11503 /* CC0 must die in the insn after it is set, so we don't need to take
11504 special note of it here. */
11510 /* If we are clobbering a MEM, mark any hard registers inside the
11511 address as used. */
11512 if (MEM_P (XEXP (x, 0)))
11513 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11518 /* A hard reg in a wide mode may really be multiple registers.
11519 If so, mark all of them just like the first. */
11520 if (regno < FIRST_PSEUDO_REGISTER)
11522 unsigned int endregno, r;
11524 /* None of this applies to the stack, frame or arg pointers. */
11525 if (regno == STACK_POINTER_REGNUM
11526 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11527 || regno == HARD_FRAME_POINTER_REGNUM
11529 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11530 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11532 || regno == FRAME_POINTER_REGNUM)
11535 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11536 for (r = regno; r < endregno; r++)
11537 SET_HARD_REG_BIT (newpat_used_regs, r);
11543 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11545 rtx testreg = SET_DEST (x);
11547 while (GET_CODE (testreg) == SUBREG
11548 || GET_CODE (testreg) == ZERO_EXTRACT
11549 || GET_CODE (testreg) == STRICT_LOW_PART)
11550 testreg = XEXP (testreg, 0);
11552 if (MEM_P (testreg))
11553 mark_used_regs_combine (XEXP (testreg, 0));
11555 mark_used_regs_combine (SET_SRC (x));
11563 /* Recursively scan the operands of this expression. */
11566 const char *fmt = GET_RTX_FORMAT (code);
11568 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11571 mark_used_regs_combine (XEXP (x, i));
11572 else if (fmt[i] == 'E')
11576 for (j = 0; j < XVECLEN (x, i); j++)
11577 mark_used_regs_combine (XVECEXP (x, i, j));
11583 /* Remove register number REGNO from the dead registers list of INSN.
11585 Return the note used to record the death, if there was one. */
11588 remove_death (unsigned int regno, rtx insn)
11590 rtx note = find_regno_note (insn, REG_DEAD, regno);
11594 REG_N_DEATHS (regno)--;
11595 remove_note (insn, note);
11601 /* For each register (hardware or pseudo) used within expression X, if its
11602 death is in an instruction with cuid between FROM_CUID (inclusive) and
11603 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11604 list headed by PNOTES.
11606 That said, don't move registers killed by maybe_kill_insn.
11608 This is done when X is being merged by combination into TO_INSN. These
11609 notes will then be distributed as needed. */
11612 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11617 enum rtx_code code = GET_CODE (x);
11621 unsigned int regno = REGNO (x);
11622 rtx where_dead = reg_stat[regno].last_death;
11623 rtx before_dead, after_dead;
11625 /* Don't move the register if it gets killed in between from and to. */
11626 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11627 && ! reg_referenced_p (x, maybe_kill_insn))
11630 /* WHERE_DEAD could be a USE insn made by combine, so first we
11631 make sure that we have insns with valid INSN_CUID values. */
11632 before_dead = where_dead;
11633 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11634 before_dead = PREV_INSN (before_dead);
11636 after_dead = where_dead;
11637 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11638 after_dead = NEXT_INSN (after_dead);
11640 if (before_dead && after_dead
11641 && INSN_CUID (before_dead) >= from_cuid
11642 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11643 || (where_dead != after_dead
11644 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11646 rtx note = remove_death (regno, where_dead);
11648 /* It is possible for the call above to return 0. This can occur
11649 when last_death points to I2 or I1 that we combined with.
11650 In that case make a new note.
11652 We must also check for the case where X is a hard register
11653 and NOTE is a death note for a range of hard registers
11654 including X. In that case, we must put REG_DEAD notes for
11655 the remaining registers in place of NOTE. */
11657 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11658 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11659 > GET_MODE_SIZE (GET_MODE (x))))
11661 unsigned int deadregno = REGNO (XEXP (note, 0));
11662 unsigned int deadend
11663 = (deadregno + hard_regno_nregs[deadregno]
11664 [GET_MODE (XEXP (note, 0))]);
11665 unsigned int ourend
11666 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11669 for (i = deadregno; i < deadend; i++)
11670 if (i < regno || i >= ourend)
11671 REG_NOTES (where_dead)
11672 = gen_rtx_EXPR_LIST (REG_DEAD,
11674 REG_NOTES (where_dead));
11677 /* If we didn't find any note, or if we found a REG_DEAD note that
11678 covers only part of the given reg, and we have a multi-reg hard
11679 register, then to be safe we must check for REG_DEAD notes
11680 for each register other than the first. They could have
11681 their own REG_DEAD notes lying around. */
11682 else if ((note == 0
11684 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11685 < GET_MODE_SIZE (GET_MODE (x)))))
11686 && regno < FIRST_PSEUDO_REGISTER
11687 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11689 unsigned int ourend
11690 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11691 unsigned int i, offset;
11695 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11699 for (i = regno + offset; i < ourend; i++)
11700 move_deaths (regno_reg_rtx[i],
11701 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11704 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11706 XEXP (note, 1) = *pnotes;
11710 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11712 REG_N_DEATHS (regno)++;
11718 else if (GET_CODE (x) == SET)
11720 rtx dest = SET_DEST (x);
11722 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11724 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11725 that accesses one word of a multi-word item, some
11726 piece of everything register in the expression is used by
11727 this insn, so remove any old death. */
11728 /* ??? So why do we test for equality of the sizes? */
11730 if (GET_CODE (dest) == ZERO_EXTRACT
11731 || GET_CODE (dest) == STRICT_LOW_PART
11732 || (GET_CODE (dest) == SUBREG
11733 && (((GET_MODE_SIZE (GET_MODE (dest))
11734 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11735 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11736 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11738 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11742 /* If this is some other SUBREG, we know it replaces the entire
11743 value, so use that as the destination. */
11744 if (GET_CODE (dest) == SUBREG)
11745 dest = SUBREG_REG (dest);
11747 /* If this is a MEM, adjust deaths of anything used in the address.
11748 For a REG (the only other possibility), the entire value is
11749 being replaced so the old value is not used in this insn. */
11752 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11757 else if (GET_CODE (x) == CLOBBER)
11760 len = GET_RTX_LENGTH (code);
11761 fmt = GET_RTX_FORMAT (code);
11763 for (i = 0; i < len; i++)
11768 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11769 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11772 else if (fmt[i] == 'e')
11773 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11777 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11778 pattern of an insn. X must be a REG. */
11781 reg_bitfield_target_p (rtx x, rtx body)
11785 if (GET_CODE (body) == SET)
11787 rtx dest = SET_DEST (body);
11789 unsigned int regno, tregno, endregno, endtregno;
11791 if (GET_CODE (dest) == ZERO_EXTRACT)
11792 target = XEXP (dest, 0);
11793 else if (GET_CODE (dest) == STRICT_LOW_PART)
11794 target = SUBREG_REG (XEXP (dest, 0));
11798 if (GET_CODE (target) == SUBREG)
11799 target = SUBREG_REG (target);
11801 if (!REG_P (target))
11804 tregno = REGNO (target), regno = REGNO (x);
11805 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11806 return target == x;
11808 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11809 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11811 return endregno > tregno && regno < endtregno;
11814 else if (GET_CODE (body) == PARALLEL)
11815 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11816 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11822 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11823 as appropriate. I3 and I2 are the insns resulting from the combination
11824 insns including FROM (I2 may be zero).
11826 Each note in the list is either ignored or placed on some insns, depending
11827 on the type of note. */
11830 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11832 rtx note, next_note;
11835 for (note = notes; note; note = next_note)
11837 rtx place = 0, place2 = 0;
11839 /* If this NOTE references a pseudo register, ensure it references
11840 the latest copy of that register. */
11841 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11842 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11843 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11845 next_note = XEXP (note, 1);
11846 switch (REG_NOTE_KIND (note))
11850 /* Doesn't matter much where we put this, as long as it's somewhere.
11851 It is preferable to keep these notes on branches, which is most
11852 likely to be i3. */
11856 case REG_VALUE_PROFILE:
11857 /* Just get rid of this note, as it is unused later anyway. */
11860 case REG_NON_LOCAL_GOTO:
11865 gcc_assert (i2 && JUMP_P (i2));
11870 case REG_EH_REGION:
11871 /* These notes must remain with the call or trapping instruction. */
11874 else if (i2 && CALL_P (i2))
11878 gcc_assert (flag_non_call_exceptions);
11879 if (may_trap_p (i3))
11881 else if (i2 && may_trap_p (i2))
11883 /* ??? Otherwise assume we've combined things such that we
11884 can now prove that the instructions can't trap. Drop the
11885 note in this case. */
11891 /* These notes must remain with the call. It should not be
11892 possible for both I2 and I3 to be a call. */
11897 gcc_assert (i2 && CALL_P (i2));
11903 /* Any clobbers for i3 may still exist, and so we must process
11904 REG_UNUSED notes from that insn.
11906 Any clobbers from i2 or i1 can only exist if they were added by
11907 recog_for_combine. In that case, recog_for_combine created the
11908 necessary REG_UNUSED notes. Trying to keep any original
11909 REG_UNUSED notes from these insns can cause incorrect output
11910 if it is for the same register as the original i3 dest.
11911 In that case, we will notice that the register is set in i3,
11912 and then add a REG_UNUSED note for the destination of i3, which
11913 is wrong. However, it is possible to have REG_UNUSED notes from
11914 i2 or i1 for register which were both used and clobbered, so
11915 we keep notes from i2 or i1 if they will turn into REG_DEAD
11918 /* If this register is set or clobbered in I3, put the note there
11919 unless there is one already. */
11920 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11922 if (from_insn != i3)
11925 if (! (REG_P (XEXP (note, 0))
11926 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11927 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11930 /* Otherwise, if this register is used by I3, then this register
11931 now dies here, so we must put a REG_DEAD note here unless there
11933 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11934 && ! (REG_P (XEXP (note, 0))
11935 ? find_regno_note (i3, REG_DEAD,
11936 REGNO (XEXP (note, 0)))
11937 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11939 PUT_REG_NOTE_KIND (note, REG_DEAD);
11947 /* These notes say something about results of an insn. We can
11948 only support them if they used to be on I3 in which case they
11949 remain on I3. Otherwise they are ignored.
11951 If the note refers to an expression that is not a constant, we
11952 must also ignore the note since we cannot tell whether the
11953 equivalence is still true. It might be possible to do
11954 slightly better than this (we only have a problem if I2DEST
11955 or I1DEST is present in the expression), but it doesn't
11956 seem worth the trouble. */
11958 if (from_insn == i3
11959 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11964 case REG_NO_CONFLICT:
11965 /* These notes say something about how a register is used. They must
11966 be present on any use of the register in I2 or I3. */
11967 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11970 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11980 /* This can show up in several ways -- either directly in the
11981 pattern, or hidden off in the constant pool with (or without?)
11982 a REG_EQUAL note. */
11983 /* ??? Ignore the without-reg_equal-note problem for now. */
11984 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11985 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11986 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11987 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11991 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11992 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11993 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11994 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12002 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12003 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12004 if (place && JUMP_P (place))
12006 rtx label = JUMP_LABEL (place);
12009 JUMP_LABEL (place) = XEXP (note, 0);
12012 gcc_assert (label == XEXP (note, 0));
12013 if (LABEL_P (label))
12014 LABEL_NUSES (label)--;
12018 if (place2 && JUMP_P (place2))
12020 rtx label = JUMP_LABEL (place2);
12023 JUMP_LABEL (place2) = XEXP (note, 0);
12026 gcc_assert (label == XEXP (note, 0));
12027 if (LABEL_P (label))
12028 LABEL_NUSES (label)--;
12035 /* This note says something about the value of a register prior
12036 to the execution of an insn. It is too much trouble to see
12037 if the note is still correct in all situations. It is better
12038 to simply delete it. */
12042 /* If the insn previously containing this note still exists,
12043 put it back where it was. Otherwise move it to the previous
12044 insn. Adjust the corresponding REG_LIBCALL note. */
12045 if (!NOTE_P (from_insn))
12049 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12050 place = prev_real_insn (from_insn);
12052 XEXP (tem, 0) = place;
12053 /* If we're deleting the last remaining instruction of a
12054 libcall sequence, don't add the notes. */
12055 else if (XEXP (note, 0) == from_insn)
12057 /* Don't add the dangling REG_RETVAL note. */
12064 /* This is handled similarly to REG_RETVAL. */
12065 if (!NOTE_P (from_insn))
12069 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12070 place = next_real_insn (from_insn);
12072 XEXP (tem, 0) = place;
12073 /* If we're deleting the last remaining instruction of a
12074 libcall sequence, don't add the notes. */
12075 else if (XEXP (note, 0) == from_insn)
12077 /* Don't add the dangling REG_LIBCALL note. */
12084 /* If the register is used as an input in I3, it dies there.
12085 Similarly for I2, if it is nonzero and adjacent to I3.
12087 If the register is not used as an input in either I3 or I2
12088 and it is not one of the registers we were supposed to eliminate,
12089 there are two possibilities. We might have a non-adjacent I2
12090 or we might have somehow eliminated an additional register
12091 from a computation. For example, we might have had A & B where
12092 we discover that B will always be zero. In this case we will
12093 eliminate the reference to A.
12095 In both cases, we must search to see if we can find a previous
12096 use of A and put the death note there. */
12099 && CALL_P (from_insn)
12100 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12102 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12104 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12105 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12110 basic_block bb = this_basic_block;
12112 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12114 if (! INSN_P (tem))
12116 if (tem == BB_HEAD (bb))
12121 /* If the register is being set at TEM, see if that is all
12122 TEM is doing. If so, delete TEM. Otherwise, make this
12123 into a REG_UNUSED note instead. Don't delete sets to
12124 global register vars. */
12125 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12126 || !global_regs[REGNO (XEXP (note, 0))])
12127 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12129 rtx set = single_set (tem);
12130 rtx inner_dest = 0;
12132 rtx cc0_setter = NULL_RTX;
12136 for (inner_dest = SET_DEST (set);
12137 (GET_CODE (inner_dest) == STRICT_LOW_PART
12138 || GET_CODE (inner_dest) == SUBREG
12139 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12140 inner_dest = XEXP (inner_dest, 0))
12143 /* Verify that it was the set, and not a clobber that
12144 modified the register.
12146 CC0 targets must be careful to maintain setter/user
12147 pairs. If we cannot delete the setter due to side
12148 effects, mark the user with an UNUSED note instead
12151 if (set != 0 && ! side_effects_p (SET_SRC (set))
12152 && rtx_equal_p (XEXP (note, 0), inner_dest)
12154 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12155 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12156 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12160 /* Move the notes and links of TEM elsewhere.
12161 This might delete other dead insns recursively.
12162 First set the pattern to something that won't use
12164 rtx old_notes = REG_NOTES (tem);
12166 PATTERN (tem) = pc_rtx;
12167 REG_NOTES (tem) = NULL;
12169 distribute_notes (old_notes, tem, tem, NULL_RTX);
12170 distribute_links (LOG_LINKS (tem));
12172 SET_INSN_DELETED (tem);
12175 /* Delete the setter too. */
12178 PATTERN (cc0_setter) = pc_rtx;
12179 old_notes = REG_NOTES (cc0_setter);
12180 REG_NOTES (cc0_setter) = NULL;
12182 distribute_notes (old_notes, cc0_setter,
12183 cc0_setter, NULL_RTX);
12184 distribute_links (LOG_LINKS (cc0_setter));
12186 SET_INSN_DELETED (cc0_setter);
12192 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12194 /* If there isn't already a REG_UNUSED note, put one
12195 here. Do not place a REG_DEAD note, even if
12196 the register is also used here; that would not
12197 match the algorithm used in lifetime analysis
12198 and can cause the consistency check in the
12199 scheduler to fail. */
12200 if (! find_regno_note (tem, REG_UNUSED,
12201 REGNO (XEXP (note, 0))))
12206 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12208 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12212 /* If we are doing a 3->2 combination, and we have a
12213 register which formerly died in i3 and was not used
12214 by i2, which now no longer dies in i3 and is used in
12215 i2 but does not die in i2, and place is between i2
12216 and i3, then we may need to move a link from place to
12218 if (i2 && INSN_UID (place) <= max_uid_cuid
12219 && INSN_CUID (place) > INSN_CUID (i2)
12221 && INSN_CUID (from_insn) > INSN_CUID (i2)
12222 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12224 rtx links = LOG_LINKS (place);
12225 LOG_LINKS (place) = 0;
12226 distribute_links (links);
12231 if (tem == BB_HEAD (bb))
12235 /* We haven't found an insn for the death note and it
12236 is still a REG_DEAD note, but we have hit the beginning
12237 of the block. If the existing life info says the reg
12238 was dead, there's nothing left to do. Otherwise, we'll
12239 need to do a global life update after combine. */
12240 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12241 && REGNO_REG_SET_P (bb->global_live_at_start,
12242 REGNO (XEXP (note, 0))))
12243 SET_BIT (refresh_blocks, this_basic_block->index);
12246 /* If the register is set or already dead at PLACE, we needn't do
12247 anything with this note if it is still a REG_DEAD note.
12248 We check here if it is set at all, not if is it totally replaced,
12249 which is what `dead_or_set_p' checks, so also check for it being
12252 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12254 unsigned int regno = REGNO (XEXP (note, 0));
12256 /* Similarly, if the instruction on which we want to place
12257 the note is a noop, we'll need do a global live update
12258 after we remove them in delete_noop_moves. */
12259 if (noop_move_p (place))
12260 SET_BIT (refresh_blocks, this_basic_block->index);
12262 if (dead_or_set_p (place, XEXP (note, 0))
12263 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12265 /* Unless the register previously died in PLACE, clear
12266 last_death. [I no longer understand why this is
12268 if (reg_stat[regno].last_death != place)
12269 reg_stat[regno].last_death = 0;
12273 reg_stat[regno].last_death = place;
12275 /* If this is a death note for a hard reg that is occupying
12276 multiple registers, ensure that we are still using all
12277 parts of the object. If we find a piece of the object
12278 that is unused, we must arrange for an appropriate REG_DEAD
12279 note to be added for it. However, we can't just emit a USE
12280 and tag the note to it, since the register might actually
12281 be dead; so we recourse, and the recursive call then finds
12282 the previous insn that used this register. */
12284 if (place && regno < FIRST_PSEUDO_REGISTER
12285 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12287 unsigned int endregno
12288 = regno + hard_regno_nregs[regno]
12289 [GET_MODE (XEXP (note, 0))];
12293 for (i = regno; i < endregno; i++)
12294 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12295 && ! find_regno_fusage (place, USE, i))
12296 || dead_or_set_regno_p (place, i))
12301 /* Put only REG_DEAD notes for pieces that are
12302 not already dead or set. */
12304 for (i = regno; i < endregno;
12305 i += hard_regno_nregs[i][reg_raw_mode[i]])
12307 rtx piece = regno_reg_rtx[i];
12308 basic_block bb = this_basic_block;
12310 if (! dead_or_set_p (place, piece)
12311 && ! reg_bitfield_target_p (piece,
12315 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12317 distribute_notes (new_note, place, place,
12320 else if (! refers_to_regno_p (i, i + 1,
12321 PATTERN (place), 0)
12322 && ! find_regno_fusage (place, USE, i))
12323 for (tem = PREV_INSN (place); ;
12324 tem = PREV_INSN (tem))
12326 if (! INSN_P (tem))
12328 if (tem == BB_HEAD (bb))
12330 SET_BIT (refresh_blocks,
12331 this_basic_block->index);
12336 if (dead_or_set_p (tem, piece)
12337 || reg_bitfield_target_p (piece,
12341 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12356 /* Any other notes should not be present at this point in the
12358 gcc_unreachable ();
12363 XEXP (note, 1) = REG_NOTES (place);
12364 REG_NOTES (place) = note;
12366 else if ((REG_NOTE_KIND (note) == REG_DEAD
12367 || REG_NOTE_KIND (note) == REG_UNUSED)
12368 && REG_P (XEXP (note, 0)))
12369 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12373 if ((REG_NOTE_KIND (note) == REG_DEAD
12374 || REG_NOTE_KIND (note) == REG_UNUSED)
12375 && REG_P (XEXP (note, 0)))
12376 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12378 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12379 REG_NOTE_KIND (note),
12381 REG_NOTES (place2));
12386 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12387 I3, I2, and I1 to new locations. This is also called to add a link
12388 pointing at I3 when I3's destination is changed. */
12391 distribute_links (rtx links)
12393 rtx link, next_link;
12395 for (link = links; link; link = next_link)
12401 next_link = XEXP (link, 1);
12403 /* If the insn that this link points to is a NOTE or isn't a single
12404 set, ignore it. In the latter case, it isn't clear what we
12405 can do other than ignore the link, since we can't tell which
12406 register it was for. Such links wouldn't be used by combine
12409 It is not possible for the destination of the target of the link to
12410 have been changed by combine. The only potential of this is if we
12411 replace I3, I2, and I1 by I3 and I2. But in that case the
12412 destination of I2 also remains unchanged. */
12414 if (NOTE_P (XEXP (link, 0))
12415 || (set = single_set (XEXP (link, 0))) == 0)
12418 reg = SET_DEST (set);
12419 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12420 || GET_CODE (reg) == STRICT_LOW_PART)
12421 reg = XEXP (reg, 0);
12423 /* A LOG_LINK is defined as being placed on the first insn that uses
12424 a register and points to the insn that sets the register. Start
12425 searching at the next insn after the target of the link and stop
12426 when we reach a set of the register or the end of the basic block.
12428 Note that this correctly handles the link that used to point from
12429 I3 to I2. Also note that not much searching is typically done here
12430 since most links don't point very far away. */
12432 for (insn = NEXT_INSN (XEXP (link, 0));
12433 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12434 || BB_HEAD (this_basic_block->next_bb) != insn));
12435 insn = NEXT_INSN (insn))
12436 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12438 if (reg_referenced_p (reg, PATTERN (insn)))
12442 else if (CALL_P (insn)
12443 && find_reg_fusage (insn, USE, reg))
12448 else if (INSN_P (insn) && reg_set_p (reg, insn))
12451 /* If we found a place to put the link, place it there unless there
12452 is already a link to the same insn as LINK at that point. */
12458 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12459 if (XEXP (link2, 0) == XEXP (link, 0))
12464 XEXP (link, 1) = LOG_LINKS (place);
12465 LOG_LINKS (place) = link;
12467 /* Set added_links_insn to the earliest insn we added a
12469 if (added_links_insn == 0
12470 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12471 added_links_insn = place;
12477 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12478 Check whether the expression pointer to by LOC is a register or
12479 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12480 Otherwise return zero. */
12483 unmentioned_reg_p_1 (rtx *loc, void *expr)
12488 && (REG_P (x) || MEM_P (x))
12489 && ! reg_mentioned_p (x, (rtx) expr))
12494 /* Check for any register or memory mentioned in EQUIV that is not
12495 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12496 of EXPR where some registers may have been replaced by constants. */
12499 unmentioned_reg_p (rtx equiv, rtx expr)
12501 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12504 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12507 insn_cuid (rtx insn)
12509 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12510 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12511 insn = NEXT_INSN (insn);
12513 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12515 return INSN_CUID (insn);
12519 dump_combine_stats (FILE *file)
12523 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12524 combine_attempts, combine_merges, combine_extras, combine_successes);
12528 dump_combine_total_stats (FILE *file)
12532 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12533 total_attempts, total_merges, total_extras, total_successes);
OSDN Git Service
