1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_notes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
143 BITS_PER_WORD would invoke undefined behavior. Work around it. */
145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
146 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno;
153 /* Record last point of death of (hard or pseudo) register n. */
156 /* Record last point of modification of (hard or pseudo) register n. */
159 /* The next group of fields allows the recording of the last value assigned
160 to (hard or pseudo) register n. We use this information to see if an
161 operation being processed is redundant given a prior operation performed
162 on the register. For example, an `and' with a constant is redundant if
163 all the zero bits are already known to be turned off.
165 We use an approach similar to that used by cse, but change it in the
168 (1) We do not want to reinitialize at each label.
169 (2) It is useful, but not critical, to know the actual value assigned
170 to a register. Often just its form is helpful.
172 Therefore, we maintain the following fields:
174 last_set_value the last value assigned
175 last_set_label records the value of label_tick when the
176 register was assigned
177 last_set_table_tick records the value of label_tick when a
178 value using the register is assigned
179 last_set_invalid set to nonzero when it is not valid
180 to use the value of this register in some
183 To understand the usage of these tables, it is important to understand
184 the distinction between the value in last_set_value being valid and
185 the register being validly contained in some other expression in the
188 (The next two parameters are out of date).
190 reg_stat[i].last_set_value is valid if it is nonzero, and either
191 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
193 Register I may validly appear in any expression returned for the value
194 of another register if reg_n_sets[i] is 1. It may also appear in the
195 value for register J if reg_stat[j].last_set_invalid is zero, or
196 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
198 If an expression is found in the table containing a register which may
199 not validly appear in an expression, the register is replaced by
200 something that won't match, (clobber (const_int 0)). */
202 /* Record last value assigned to (hard or pseudo) register n. */
206 /* Record the value of label_tick when an expression involving register n
207 is placed in last_set_value. */
209 int last_set_table_tick;
211 /* Record the value of label_tick when the value for register n is placed in
216 /* These fields are maintained in parallel with last_set_value and are
217 used to store the mode in which the register was last set, the bits
218 that were known to be zero when it was last set, and the number of
219 sign bits copies it was known to have when it was last set. */
221 unsigned HOST_WIDE_INT last_set_nonzero_bits;
222 char last_set_sign_bit_copies;
223 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
225 /* Set nonzero if references to register n in expressions should not be
226 used. last_set_invalid is set nonzero when this register is being
227 assigned to and last_set_table_tick == label_tick. */
229 char last_set_invalid;
231 /* Some registers that are set more than once and used in more than one
232 basic block are nevertheless always set in similar ways. For example,
233 a QImode register may be loaded from memory in two places on a machine
234 where byte loads zero extend.
236 We record in the following fields if a register has some leading bits
237 that are always equal to the sign bit, and what we know about the
238 nonzero bits of a register, specifically which bits are known to be
241 If an entry is zero, it means that we don't know anything special. */
243 unsigned char sign_bit_copies;
245 unsigned HOST_WIDE_INT nonzero_bits;
248 static struct reg_stat *reg_stat;
250 /* Record the cuid of the last insn that invalidated memory
251 (anything that writes memory, and subroutine calls, but not pushes). */
253 static int mem_last_set;
255 /* Record the cuid of the last CALL_INSN
256 so we can tell whether a potential combination crosses any calls. */
258 static int last_call_cuid;
260 /* When `subst' is called, this is the insn that is being modified
261 (by combining in a previous insn). The PATTERN of this insn
262 is still the old pattern partially modified and it should not be
263 looked at, but this may be used to examine the successors of the insn
264 to judge whether a simplification is valid. */
266 static rtx subst_insn;
268 /* This is the lowest CUID that `subst' is currently dealing with.
269 get_last_value will not return a value if the register was set at or
270 after this CUID. If not for this mechanism, we could get confused if
271 I2 or I1 in try_combine were an insn that used the old value of a register
272 to obtain a new value. In that case, we might erroneously get the
273 new value of the register when we wanted the old one. */
275 static int subst_low_cuid;
277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 must consider all these registers to be always live. */
280 static HARD_REG_SET newpat_used_regs;
282 /* This is an insn to which a LOG_LINKS entry has been added. If this
283 insn is the earlier than I2 or I3, combine should rescan starting at
286 static rtx added_links_insn;
288 /* Basic block in which we are performing combines. */
289 static basic_block this_basic_block;
291 /* A bitmap indicating which blocks had registers go dead at entry.
292 After combine, we'll need to re-do global life analysis with
293 those blocks as starting points. */
294 static sbitmap refresh_blocks;
296 /* The following array records the insn_rtx_cost for every insn
297 in the instruction stream. */
299 static int *uid_insn_cost;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int last_insn_cost;
305 /* Incremented for each label. */
307 static int label_tick;
309 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
310 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
312 static enum machine_mode nonzero_bits_mode;
314 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
315 be safely used. It is zero while computing them and after combine has
316 completed. This former test prevents propagating values based on
317 previously set values, which can be incorrect if a variable is modified
320 static int nonzero_sign_valid;
323 /* Record one modification to rtl structure
324 to be undone by storing old_contents into *where.
325 is_int is 1 if the contents are an int. */
331 union {rtx r; int i;} old_contents;
332 union {rtx *r; int *i;} where;
335 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
336 num_undo says how many are currently recorded.
338 other_insn is nonzero if we have modified some other insn in the process
339 of working on subst_insn. It must be verified too. */
348 static struct undobuf undobuf;
350 /* Number of times the pseudo being substituted for
351 was found and replaced. */
353 static int n_occurrences;
355 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
357 unsigned HOST_WIDE_INT,
358 unsigned HOST_WIDE_INT *);
359 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
361 unsigned int, unsigned int *);
362 static void do_SUBST (rtx *, rtx);
363 static void do_SUBST_INT (int *, int);
364 static void init_reg_last (void);
365 static void setup_incoming_promotions (void);
366 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
367 static int cant_combine_insn_p (rtx);
368 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
369 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
370 static int contains_muldiv (rtx);
371 static rtx try_combine (rtx, rtx, rtx, int *);
372 static void undo_all (void);
373 static void undo_commit (void);
374 static rtx *find_split_point (rtx *, rtx);
375 static rtx subst (rtx, rtx, rtx, int, int);
376 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
377 static rtx simplify_if_then_else (rtx);
378 static rtx simplify_set (rtx);
379 static rtx simplify_logical (rtx);
380 static rtx expand_compound_operation (rtx);
381 static rtx expand_field_assignment (rtx);
382 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
383 rtx, unsigned HOST_WIDE_INT, int, int, int);
384 static rtx extract_left_shift (rtx, int);
385 static rtx make_compound_operation (rtx, enum rtx_code);
386 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
387 unsigned HOST_WIDE_INT *);
388 static rtx canon_reg_for_combine (rtx, rtx);
389 static rtx force_to_mode (rtx, enum machine_mode,
390 unsigned HOST_WIDE_INT, int);
391 static rtx if_then_else_cond (rtx, rtx *, rtx *);
392 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
393 static int rtx_equal_for_field_assignment_p (rtx, rtx);
394 static rtx make_field_assignment (rtx);
395 static rtx apply_distributive_law (rtx);
396 static rtx distribute_and_simplify_rtx (rtx, int);
397 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
398 unsigned HOST_WIDE_INT);
399 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
400 unsigned HOST_WIDE_INT);
401 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
402 HOST_WIDE_INT, enum machine_mode, int *);
403 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
404 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
406 static int recog_for_combine (rtx *, rtx, rtx *);
407 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
408 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
409 static void update_table_tick (rtx);
410 static void record_value_for_reg (rtx, rtx, rtx);
411 static void check_promoted_subreg (rtx, rtx);
412 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
413 static void record_dead_and_set_regs (rtx);
414 static int get_last_value_validate (rtx *, rtx, int, int);
415 static rtx get_last_value (rtx);
416 static int use_crosses_set_p (rtx, int);
417 static void reg_dead_at_p_1 (rtx, rtx, void *);
418 static int reg_dead_at_p (rtx, rtx);
419 static void move_deaths (rtx, rtx, int, rtx, rtx *);
420 static int reg_bitfield_target_p (rtx, rtx);
421 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
422 static void distribute_links (rtx);
423 static void mark_used_regs_combine (rtx);
424 static int insn_cuid (rtx);
425 static void record_promoted_value (rtx, rtx);
426 static int unmentioned_reg_p_1 (rtx *, void *);
427 static bool unmentioned_reg_p (rtx, rtx);
430 /* It is not safe to use ordinary gen_lowpart in combine.
431 See comments in gen_lowpart_for_combine. */
432 #undef RTL_HOOKS_GEN_LOWPART
433 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
435 /* Our implementation of gen_lowpart never emits a new pseudo. */
436 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
437 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
439 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
440 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
442 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
443 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
445 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
448 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
449 insn. The substitution can be undone by undo_all. If INTO is already
450 set to NEWVAL, do not record this change. Because computing NEWVAL might
451 also call SUBST, we have to compute it before we put anything into
455 do_SUBST (rtx *into, rtx newval)
460 if (oldval == newval)
463 /* We'd like to catch as many invalid transformations here as
464 possible. Unfortunately, there are way too many mode changes
465 that are perfectly valid, so we'd waste too much effort for
466 little gain doing the checks here. Focus on catching invalid
467 transformations involving integer constants. */
468 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
469 && GET_CODE (newval) == CONST_INT)
471 /* Sanity check that we're replacing oldval with a CONST_INT
472 that is a valid sign-extension for the original mode. */
473 gcc_assert (INTVAL (newval)
474 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
476 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
477 CONST_INT is not valid, because after the replacement, the
478 original mode would be gone. Unfortunately, we can't tell
479 when do_SUBST is called to replace the operand thereof, so we
480 perform this test on oldval instead, checking whether an
481 invalid replacement took place before we got here. */
482 gcc_assert (!(GET_CODE (oldval) == SUBREG
483 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
484 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
485 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
489 buf = undobuf.frees, undobuf.frees = buf->next;
491 buf = xmalloc (sizeof (struct undo));
495 buf->old_contents.r = oldval;
498 buf->next = undobuf.undos, undobuf.undos = buf;
501 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
503 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
504 for the value of a HOST_WIDE_INT value (including CONST_INT) is
508 do_SUBST_INT (int *into, int newval)
513 if (oldval == newval)
517 buf = undobuf.frees, undobuf.frees = buf->next;
519 buf = xmalloc (sizeof (struct undo));
523 buf->old_contents.i = oldval;
526 buf->next = undobuf.undos, undobuf.undos = buf;
529 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
531 /* Subroutine of try_combine. Determine whether the combine replacement
532 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
533 that the original instruction sequence I1, I2 and I3. Note that I1
534 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
535 costs of all instructions can be estimated, and the replacements are
536 more expensive than the original sequence. */
539 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
541 int i1_cost, i2_cost, i3_cost;
542 int new_i2_cost, new_i3_cost;
543 int old_cost, new_cost;
545 /* Lookup the original insn_rtx_costs. */
546 i2_cost = INSN_UID (i2) <= last_insn_cost
547 ? uid_insn_cost[INSN_UID (i2)] : 0;
548 i3_cost = INSN_UID (i3) <= last_insn_cost
549 ? uid_insn_cost[INSN_UID (i3)] : 0;
553 i1_cost = INSN_UID (i1) <= last_insn_cost
554 ? uid_insn_cost[INSN_UID (i1)] : 0;
555 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
556 ? i1_cost + i2_cost + i3_cost : 0;
560 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
564 /* Calculate the replacement insn_rtx_costs. */
565 new_i3_cost = insn_rtx_cost (newpat);
568 new_i2_cost = insn_rtx_cost (newi2pat);
569 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
570 ? new_i2_cost + new_i3_cost : 0;
574 new_cost = new_i3_cost;
578 if (undobuf.other_insn)
580 int old_other_cost, new_other_cost;
582 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
583 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
584 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
585 if (old_other_cost > 0 && new_other_cost > 0)
587 old_cost += old_other_cost;
588 new_cost += new_other_cost;
594 /* Disallow this recombination if both new_cost and old_cost are
595 greater than zero, and new_cost is greater than old cost. */
597 && new_cost > old_cost)
604 "rejecting combination of insns %d, %d and %d\n",
605 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
606 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
607 i1_cost, i2_cost, i3_cost, old_cost);
612 "rejecting combination of insns %d and %d\n",
613 INSN_UID (i2), INSN_UID (i3));
614 fprintf (dump_file, "original costs %d + %d = %d\n",
615 i2_cost, i3_cost, old_cost);
620 fprintf (dump_file, "replacement costs %d + %d = %d\n",
621 new_i2_cost, new_i3_cost, new_cost);
624 fprintf (dump_file, "replacement cost %d\n", new_cost);
630 /* Update the uid_insn_cost array with the replacement costs. */
631 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
632 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
634 uid_insn_cost[INSN_UID (i1)] = 0;
639 /* Main entry point for combiner. F is the first insn of the function.
640 NREGS is the first unused pseudo-reg number.
642 Return nonzero if the combiner has turned an indirect jump
643 instruction into a direct jump. */
645 combine_instructions (rtx f, unsigned int nregs)
653 rtx links, nextlinks;
654 sbitmap_iterator sbi;
656 int new_direct_jump_p = 0;
658 combine_attempts = 0;
661 combine_successes = 0;
663 combine_max_regno = nregs;
665 rtl_hooks = combine_rtl_hooks;
667 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
669 init_recog_no_volatile ();
671 /* Compute maximum uid value so uid_cuid can be allocated. */
673 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
674 if (INSN_UID (insn) > i)
677 uid_cuid = xmalloc ((i + 1) * sizeof (int));
680 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
682 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
683 problems when, for example, we have j <<= 1 in a loop. */
685 nonzero_sign_valid = 0;
687 /* Compute the mapping from uids to cuids.
688 Cuids are numbers assigned to insns, like uids,
689 except that cuids increase monotonically through the code.
691 Scan all SETs and see if we can deduce anything about what
692 bits are known to be zero for some registers and how many copies
693 of the sign bit are known to exist for those registers.
695 Also set any known values so that we can use it while searching
696 for what bits are known to be set. */
700 setup_incoming_promotions ();
702 refresh_blocks = sbitmap_alloc (last_basic_block);
703 sbitmap_zero (refresh_blocks);
705 /* Allocate array of current insn_rtx_costs. */
706 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
707 last_insn_cost = max_uid_cuid;
709 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
711 uid_cuid[INSN_UID (insn)] = ++i;
717 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
719 record_dead_and_set_regs (insn);
722 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
723 if (REG_NOTE_KIND (links) == REG_INC)
724 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
728 /* Record the current insn_rtx_cost of this instruction. */
729 if (NONJUMP_INSN_P (insn))
730 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
732 fprintf(dump_file, "insn_cost %d: %d\n",
733 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
740 nonzero_sign_valid = 1;
742 /* Now scan all the insns in forward order. */
748 setup_incoming_promotions ();
750 FOR_EACH_BB (this_basic_block)
752 for (insn = BB_HEAD (this_basic_block);
753 insn != NEXT_INSN (BB_END (this_basic_block));
754 insn = next ? next : NEXT_INSN (insn))
761 else if (INSN_P (insn))
763 /* See if we know about function return values before this
764 insn based upon SUBREG flags. */
765 check_promoted_subreg (insn, PATTERN (insn));
767 /* Try this insn with each insn it links back to. */
769 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
770 if ((next = try_combine (insn, XEXP (links, 0),
771 NULL_RTX, &new_direct_jump_p)) != 0)
774 /* Try each sequence of three linked insns ending with this one. */
776 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
778 rtx link = XEXP (links, 0);
780 /* If the linked insn has been replaced by a note, then there
781 is no point in pursuing this chain any further. */
785 for (nextlinks = LOG_LINKS (link);
787 nextlinks = XEXP (nextlinks, 1))
788 if ((next = try_combine (insn, link,
790 &new_direct_jump_p)) != 0)
795 /* Try to combine a jump insn that uses CC0
796 with a preceding insn that sets CC0, and maybe with its
797 logical predecessor as well.
798 This is how we make decrement-and-branch insns.
799 We need this special code because data flow connections
800 via CC0 do not get entered in LOG_LINKS. */
803 && (prev = prev_nonnote_insn (insn)) != 0
804 && NONJUMP_INSN_P (prev)
805 && sets_cc0_p (PATTERN (prev)))
807 if ((next = try_combine (insn, prev,
808 NULL_RTX, &new_direct_jump_p)) != 0)
811 for (nextlinks = LOG_LINKS (prev); nextlinks;
812 nextlinks = XEXP (nextlinks, 1))
813 if ((next = try_combine (insn, prev,
815 &new_direct_jump_p)) != 0)
819 /* Do the same for an insn that explicitly references CC0. */
820 if (NONJUMP_INSN_P (insn)
821 && (prev = prev_nonnote_insn (insn)) != 0
822 && NONJUMP_INSN_P (prev)
823 && sets_cc0_p (PATTERN (prev))
824 && GET_CODE (PATTERN (insn)) == SET
825 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
827 if ((next = try_combine (insn, prev,
828 NULL_RTX, &new_direct_jump_p)) != 0)
831 for (nextlinks = LOG_LINKS (prev); nextlinks;
832 nextlinks = XEXP (nextlinks, 1))
833 if ((next = try_combine (insn, prev,
835 &new_direct_jump_p)) != 0)
839 /* Finally, see if any of the insns that this insn links to
840 explicitly references CC0. If so, try this insn, that insn,
841 and its predecessor if it sets CC0. */
842 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
843 if (NONJUMP_INSN_P (XEXP (links, 0))
844 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
845 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
846 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
847 && NONJUMP_INSN_P (prev)
848 && sets_cc0_p (PATTERN (prev))
849 && (next = try_combine (insn, XEXP (links, 0),
850 prev, &new_direct_jump_p)) != 0)
854 /* Try combining an insn with two different insns whose results it
856 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
857 for (nextlinks = XEXP (links, 1); nextlinks;
858 nextlinks = XEXP (nextlinks, 1))
859 if ((next = try_combine (insn, XEXP (links, 0),
861 &new_direct_jump_p)) != 0)
864 /* Try this insn with each REG_EQUAL note it links back to. */
865 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
868 rtx temp = XEXP (links, 0);
869 if ((set = single_set (temp)) != 0
870 && (note = find_reg_equal_equiv_note (temp)) != 0
871 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
872 /* Avoid using a register that may already been marked
873 dead by an earlier instruction. */
874 && ! unmentioned_reg_p (note, SET_SRC (set))
875 && (GET_MODE (note) == VOIDmode
876 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
877 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
879 /* Temporarily replace the set's source with the
880 contents of the REG_EQUAL note. The insn will
881 be deleted or recognized by try_combine. */
882 rtx orig = SET_SRC (set);
883 SET_SRC (set) = note;
884 next = try_combine (insn, temp, NULL_RTX,
888 SET_SRC (set) = orig;
893 record_dead_and_set_regs (insn);
902 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
903 BASIC_BLOCK (j)->flags |= BB_DIRTY;
904 new_direct_jump_p |= purge_all_dead_edges ();
905 delete_noop_moves ();
907 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
908 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
909 | PROP_KILL_DEAD_CODE);
912 sbitmap_free (refresh_blocks);
913 free (uid_insn_cost);
918 struct undo *undo, *next;
919 for (undo = undobuf.frees; undo; undo = next)
927 total_attempts += combine_attempts;
928 total_merges += combine_merges;
929 total_extras += combine_extras;
930 total_successes += combine_successes;
932 nonzero_sign_valid = 0;
933 rtl_hooks = general_rtl_hooks;
935 /* Make recognizer allow volatile MEMs again. */
938 return new_direct_jump_p;
941 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
947 for (i = 0; i < combine_max_regno; i++)
948 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
951 /* Set up any promoted values for incoming argument registers. */
954 setup_incoming_promotions (void)
958 enum machine_mode mode;
960 rtx first = get_insns ();
962 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
964 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
965 /* Check whether this register can hold an incoming pointer
966 argument. FUNCTION_ARG_REGNO_P tests outgoing register
967 numbers, so translate if necessary due to register windows. */
968 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
969 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
972 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
975 gen_rtx_CLOBBER (mode, const0_rtx)));
980 /* Called via note_stores. If X is a pseudo that is narrower than
981 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
983 If we are setting only a portion of X and we can't figure out what
984 portion, assume all bits will be used since we don't know what will
987 Similarly, set how many bits of X are known to be copies of the sign bit
988 at all locations in the function. This is the smallest number implied
992 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
993 void *data ATTRIBUTE_UNUSED)
998 && REGNO (x) >= FIRST_PSEUDO_REGISTER
999 /* If this register is undefined at the start of the file, we can't
1000 say what its contents were. */
1001 && ! REGNO_REG_SET_P
1002 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1003 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1005 if (set == 0 || GET_CODE (set) == CLOBBER)
1007 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1008 reg_stat[REGNO (x)].sign_bit_copies = 1;
1012 /* If this is a complex assignment, see if we can convert it into a
1013 simple assignment. */
1014 set = expand_field_assignment (set);
1016 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1017 set what we know about X. */
1019 if (SET_DEST (set) == x
1020 || (GET_CODE (SET_DEST (set)) == SUBREG
1021 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1022 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1023 && SUBREG_REG (SET_DEST (set)) == x))
1025 rtx src = SET_SRC (set);
1027 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1028 /* If X is narrower than a word and SRC is a non-negative
1029 constant that would appear negative in the mode of X,
1030 sign-extend it for use in reg_stat[].nonzero_bits because some
1031 machines (maybe most) will actually do the sign-extension
1032 and this is the conservative approach.
1034 ??? For 2.5, try to tighten up the MD files in this regard
1035 instead of this kludge. */
1037 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1038 && GET_CODE (src) == CONST_INT
1040 && 0 != (INTVAL (src)
1041 & ((HOST_WIDE_INT) 1
1042 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1043 src = GEN_INT (INTVAL (src)
1044 | ((HOST_WIDE_INT) (-1)
1045 << GET_MODE_BITSIZE (GET_MODE (x))));
1048 /* Don't call nonzero_bits if it cannot change anything. */
1049 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1050 reg_stat[REGNO (x)].nonzero_bits
1051 |= nonzero_bits (src, nonzero_bits_mode);
1052 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1053 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1054 || reg_stat[REGNO (x)].sign_bit_copies > num)
1055 reg_stat[REGNO (x)].sign_bit_copies = num;
1059 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1060 reg_stat[REGNO (x)].sign_bit_copies = 1;
1065 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1066 insns that were previously combined into I3 or that will be combined
1067 into the merger of INSN and I3.
1069 Return 0 if the combination is not allowed for any reason.
1071 If the combination is allowed, *PDEST will be set to the single
1072 destination of INSN and *PSRC to the single source, and this function
1076 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1077 rtx *pdest, rtx *psrc)
1080 rtx set = 0, src, dest;
1085 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1086 && next_active_insn (succ) == i3)
1087 : next_active_insn (insn) == i3);
1089 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1090 or a PARALLEL consisting of such a SET and CLOBBERs.
1092 If INSN has CLOBBER parallel parts, ignore them for our processing.
1093 By definition, these happen during the execution of the insn. When it
1094 is merged with another insn, all bets are off. If they are, in fact,
1095 needed and aren't also supplied in I3, they may be added by
1096 recog_for_combine. Otherwise, it won't match.
1098 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1101 Get the source and destination of INSN. If more than one, can't
1104 if (GET_CODE (PATTERN (insn)) == SET)
1105 set = PATTERN (insn);
1106 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1107 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1109 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1111 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1114 switch (GET_CODE (elt))
1116 /* This is important to combine floating point insns
1117 for the SH4 port. */
1119 /* Combining an isolated USE doesn't make sense.
1120 We depend here on combinable_i3pat to reject them. */
1121 /* The code below this loop only verifies that the inputs of
1122 the SET in INSN do not change. We call reg_set_between_p
1123 to verify that the REG in the USE does not change between
1125 If the USE in INSN was for a pseudo register, the matching
1126 insn pattern will likely match any register; combining this
1127 with any other USE would only be safe if we knew that the
1128 used registers have identical values, or if there was
1129 something to tell them apart, e.g. different modes. For
1130 now, we forgo such complicated tests and simply disallow
1131 combining of USES of pseudo registers with any other USE. */
1132 if (REG_P (XEXP (elt, 0))
1133 && GET_CODE (PATTERN (i3)) == PARALLEL)
1135 rtx i3pat = PATTERN (i3);
1136 int i = XVECLEN (i3pat, 0) - 1;
1137 unsigned int regno = REGNO (XEXP (elt, 0));
1141 rtx i3elt = XVECEXP (i3pat, 0, i);
1143 if (GET_CODE (i3elt) == USE
1144 && REG_P (XEXP (i3elt, 0))
1145 && (REGNO (XEXP (i3elt, 0)) == regno
1146 ? reg_set_between_p (XEXP (elt, 0),
1147 PREV_INSN (insn), i3)
1148 : regno >= FIRST_PSEUDO_REGISTER))
1155 /* We can ignore CLOBBERs. */
1160 /* Ignore SETs whose result isn't used but not those that
1161 have side-effects. */
1162 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1163 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1164 || INTVAL (XEXP (note, 0)) <= 0)
1165 && ! side_effects_p (elt))
1168 /* If we have already found a SET, this is a second one and
1169 so we cannot combine with this insn. */
1177 /* Anything else means we can't combine. */
1183 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1184 so don't do anything with it. */
1185 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1194 set = expand_field_assignment (set);
1195 src = SET_SRC (set), dest = SET_DEST (set);
1197 /* Don't eliminate a store in the stack pointer. */
1198 if (dest == stack_pointer_rtx
1199 /* Don't combine with an insn that sets a register to itself if it has
1200 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1201 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1202 /* Can't merge an ASM_OPERANDS. */
1203 || GET_CODE (src) == ASM_OPERANDS
1204 /* Can't merge a function call. */
1205 || GET_CODE (src) == CALL
1206 /* Don't eliminate a function call argument. */
1208 && (find_reg_fusage (i3, USE, dest)
1210 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1211 && global_regs[REGNO (dest)])))
1212 /* Don't substitute into an incremented register. */
1213 || FIND_REG_INC_NOTE (i3, dest)
1214 || (succ && FIND_REG_INC_NOTE (succ, dest))
1215 /* Don't substitute into a non-local goto, this confuses CFG. */
1216 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1218 /* Don't combine the end of a libcall into anything. */
1219 /* ??? This gives worse code, and appears to be unnecessary, since no
1220 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1221 use REG_RETVAL notes for noconflict blocks, but other code here
1222 makes sure that those insns don't disappear. */
1223 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1225 /* Make sure that DEST is not used after SUCC but before I3. */
1226 || (succ && ! all_adjacent
1227 && reg_used_between_p (dest, succ, i3))
1228 /* Make sure that the value that is to be substituted for the register
1229 does not use any registers whose values alter in between. However,
1230 If the insns are adjacent, a use can't cross a set even though we
1231 think it might (this can happen for a sequence of insns each setting
1232 the same destination; last_set of that register might point to
1233 a NOTE). If INSN has a REG_EQUIV note, the register is always
1234 equivalent to the memory so the substitution is valid even if there
1235 are intervening stores. Also, don't move a volatile asm or
1236 UNSPEC_VOLATILE across any other insns. */
1239 || ! find_reg_note (insn, REG_EQUIV, src))
1240 && use_crosses_set_p (src, INSN_CUID (insn)))
1241 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1242 || GET_CODE (src) == UNSPEC_VOLATILE))
1243 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1244 better register allocation by not doing the combine. */
1245 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1246 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1247 /* Don't combine across a CALL_INSN, because that would possibly
1248 change whether the life span of some REGs crosses calls or not,
1249 and it is a pain to update that information.
1250 Exception: if source is a constant, moving it later can't hurt.
1251 Accept that special case, because it helps -fforce-addr a lot. */
1252 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1255 /* DEST must either be a REG or CC0. */
1258 /* If register alignment is being enforced for multi-word items in all
1259 cases except for parameters, it is possible to have a register copy
1260 insn referencing a hard register that is not allowed to contain the
1261 mode being copied and which would not be valid as an operand of most
1262 insns. Eliminate this problem by not combining with such an insn.
1264 Also, on some machines we don't want to extend the life of a hard
1268 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1269 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1270 /* Don't extend the life of a hard register unless it is
1271 user variable (if we have few registers) or it can't
1272 fit into the desired register (meaning something special
1274 Also avoid substituting a return register into I3, because
1275 reload can't handle a conflict with constraints of other
1277 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1278 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1281 else if (GET_CODE (dest) != CC0)
1285 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1286 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1287 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1289 /* Don't substitute for a register intended as a clobberable
1291 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1292 if (rtx_equal_p (reg, dest))
1295 /* If the clobber represents an earlyclobber operand, we must not
1296 substitute an expression containing the clobbered register.
1297 As we do not analyze the constraint strings here, we have to
1298 make the conservative assumption. However, if the register is
1299 a fixed hard reg, the clobber cannot represent any operand;
1300 we leave it up to the machine description to either accept or
1301 reject use-and-clobber patterns. */
1303 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1304 || !fixed_regs[REGNO (reg)])
1305 if (reg_overlap_mentioned_p (reg, src))
1309 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1310 or not), reject, unless nothing volatile comes between it and I3 */
1312 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1314 /* Make sure succ doesn't contain a volatile reference. */
1315 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1318 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1319 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1323 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1324 to be an explicit register variable, and was chosen for a reason. */
1326 if (GET_CODE (src) == ASM_OPERANDS
1327 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1330 /* If there are any volatile insns between INSN and I3, reject, because
1331 they might affect machine state. */
1333 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1334 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1337 /* If INSN contains an autoincrement or autodecrement, make sure that
1338 register is not used between there and I3, and not already used in
1339 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1340 Also insist that I3 not be a jump; if it were one
1341 and the incremented register were spilled, we would lose. */
1344 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1345 if (REG_NOTE_KIND (link) == REG_INC
1347 || reg_used_between_p (XEXP (link, 0), insn, i3)
1348 || (pred != NULL_RTX
1349 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1350 || (succ != NULL_RTX
1351 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1352 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1357 /* Don't combine an insn that follows a CC0-setting insn.
1358 An insn that uses CC0 must not be separated from the one that sets it.
1359 We do, however, allow I2 to follow a CC0-setting insn if that insn
1360 is passed as I1; in that case it will be deleted also.
1361 We also allow combining in this case if all the insns are adjacent
1362 because that would leave the two CC0 insns adjacent as well.
1363 It would be more logical to test whether CC0 occurs inside I1 or I2,
1364 but that would be much slower, and this ought to be equivalent. */
1366 p = prev_nonnote_insn (insn);
1367 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1372 /* If we get here, we have passed all the tests and the combination is
1381 /* LOC is the location within I3 that contains its pattern or the component
1382 of a PARALLEL of the pattern. We validate that it is valid for combining.
1384 One problem is if I3 modifies its output, as opposed to replacing it
1385 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1386 so would produce an insn that is not equivalent to the original insns.
1390 (set (reg:DI 101) (reg:DI 100))
1391 (set (subreg:SI (reg:DI 101) 0) <foo>)
1393 This is NOT equivalent to:
1395 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1396 (set (reg:DI 101) (reg:DI 100))])
1398 Not only does this modify 100 (in which case it might still be valid
1399 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1401 We can also run into a problem if I2 sets a register that I1
1402 uses and I1 gets directly substituted into I3 (not via I2). In that
1403 case, we would be getting the wrong value of I2DEST into I3, so we
1404 must reject the combination. This case occurs when I2 and I1 both
1405 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1406 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1407 of a SET must prevent combination from occurring.
1409 Before doing the above check, we first try to expand a field assignment
1410 into a set of logical operations.
1412 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1413 we place a register that is both set and used within I3. If more than one
1414 such register is detected, we fail.
1416 Return 1 if the combination is valid, zero otherwise. */
1419 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1420 int i1_not_in_src, rtx *pi3dest_killed)
1424 if (GET_CODE (x) == SET)
1427 rtx dest = SET_DEST (set);
1428 rtx src = SET_SRC (set);
1429 rtx inner_dest = dest;
1432 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1433 || GET_CODE (inner_dest) == SUBREG
1434 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1435 inner_dest = XEXP (inner_dest, 0);
1437 /* Check for the case where I3 modifies its output, as discussed
1438 above. We don't want to prevent pseudos from being combined
1439 into the address of a MEM, so only prevent the combination if
1440 i1 or i2 set the same MEM. */
1441 if ((inner_dest != dest &&
1442 (!MEM_P (inner_dest)
1443 || rtx_equal_p (i2dest, inner_dest)
1444 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1445 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1446 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1448 /* This is the same test done in can_combine_p except we can't test
1449 all_adjacent; we don't have to, since this instruction will stay
1450 in place, thus we are not considering increasing the lifetime of
1453 Also, if this insn sets a function argument, combining it with
1454 something that might need a spill could clobber a previous
1455 function argument; the all_adjacent test in can_combine_p also
1456 checks this; here, we do a more specific test for this case. */
1458 || (REG_P (inner_dest)
1459 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1460 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1461 GET_MODE (inner_dest))))
1462 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1465 /* If DEST is used in I3, it is being killed in this insn, so
1466 record that for later. We have to consider paradoxical
1467 subregs here, since they kill the whole register, but we
1468 ignore partial subregs, STRICT_LOW_PART, etc.
1469 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1470 STACK_POINTER_REGNUM, since these are always considered to be
1471 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1473 if (GET_CODE (subdest) == SUBREG
1474 && (GET_MODE_SIZE (GET_MODE (subdest))
1475 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1476 subdest = SUBREG_REG (subdest);
1479 && reg_referenced_p (subdest, PATTERN (i3))
1480 && REGNO (subdest) != FRAME_POINTER_REGNUM
1481 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1482 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1484 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1485 && (REGNO (subdest) != ARG_POINTER_REGNUM
1486 || ! fixed_regs [REGNO (subdest)])
1488 && REGNO (subdest) != STACK_POINTER_REGNUM)
1490 if (*pi3dest_killed)
1493 *pi3dest_killed = subdest;
1497 else if (GET_CODE (x) == PARALLEL)
1501 for (i = 0; i < XVECLEN (x, 0); i++)
1502 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1503 i1_not_in_src, pi3dest_killed))
1510 /* Return 1 if X is an arithmetic expression that contains a multiplication
1511 and division. We don't count multiplications by powers of two here. */
1514 contains_muldiv (rtx x)
1516 switch (GET_CODE (x))
1518 case MOD: case DIV: case UMOD: case UDIV:
1522 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1523 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1526 return contains_muldiv (XEXP (x, 0))
1527 || contains_muldiv (XEXP (x, 1));
1530 return contains_muldiv (XEXP (x, 0));
1536 /* Determine whether INSN can be used in a combination. Return nonzero if
1537 not. This is used in try_combine to detect early some cases where we
1538 can't perform combinations. */
1541 cant_combine_insn_p (rtx insn)
1546 /* If this isn't really an insn, we can't do anything.
1547 This can occur when flow deletes an insn that it has merged into an
1548 auto-increment address. */
1549 if (! INSN_P (insn))
1552 /* Never combine loads and stores involving hard regs that are likely
1553 to be spilled. The register allocator can usually handle such
1554 reg-reg moves by tying. If we allow the combiner to make
1555 substitutions of likely-spilled regs, reload might die.
1556 As an exception, we allow combinations involving fixed regs; these are
1557 not available to the register allocator so there's no risk involved. */
1559 set = single_set (insn);
1562 src = SET_SRC (set);
1563 dest = SET_DEST (set);
1564 if (GET_CODE (src) == SUBREG)
1565 src = SUBREG_REG (src);
1566 if (GET_CODE (dest) == SUBREG)
1567 dest = SUBREG_REG (dest);
1568 if (REG_P (src) && REG_P (dest)
1569 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1570 && ! fixed_regs[REGNO (src)]
1571 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1572 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1573 && ! fixed_regs[REGNO (dest)]
1574 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1580 struct likely_spilled_retval_info
1582 unsigned regno, nregs;
1586 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1587 hard registers that are known to be written to / clobbered in full. */
1589 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1591 struct likely_spilled_retval_info *info = data;
1592 unsigned regno, nregs;
1595 if (!REG_P (XEXP (set, 0)))
1598 if (regno >= info->regno + info->nregs)
1600 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1601 if (regno + nregs <= info->regno)
1603 new_mask = (2U << (nregs - 1)) - 1;
1604 if (regno < info->regno)
1605 new_mask >>= info->regno - regno;
1607 new_mask <<= regno - info->regno;
1608 info->mask &= new_mask;
1611 /* Return nonzero iff part of the return value is live during INSN, and
1612 it is likely spilled. This can happen when more than one insn is needed
1613 to copy the return value, e.g. when we consider to combine into the
1614 second copy insn for a complex value. */
1617 likely_spilled_retval_p (rtx insn)
1619 rtx use = BB_END (this_basic_block);
1621 unsigned regno, nregs;
1622 /* We assume here that no machine mode needs more than
1623 32 hard registers when the value overlaps with a register
1624 for which FUNCTION_VALUE_REGNO_P is true. */
1626 struct likely_spilled_retval_info info;
1628 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1630 reg = XEXP (PATTERN (use), 0);
1631 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1633 regno = REGNO (reg);
1634 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1637 mask = (2U << (nregs - 1)) - 1;
1639 /* Disregard parts of the return value that are set later. */
1643 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1644 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1647 /* Check if any of the (probably) live return value registers is
1652 if ((mask & 1 << nregs)
1653 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1659 /* Adjust INSN after we made a change to its destination.
1661 Changing the destination can invalidate notes that say something about
1662 the results of the insn and a LOG_LINK pointing to the insn. */
1665 adjust_for_new_dest (rtx insn)
1669 /* For notes, be conservative and simply remove them. */
1670 loc = ®_NOTES (insn);
1673 enum reg_note kind = REG_NOTE_KIND (*loc);
1674 if (kind == REG_EQUAL || kind == REG_EQUIV)
1675 *loc = XEXP (*loc, 1);
1677 loc = &XEXP (*loc, 1);
1680 /* The new insn will have a destination that was previously the destination
1681 of an insn just above it. Call distribute_links to make a LOG_LINK from
1682 the next use of that destination. */
1683 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1686 /* Return TRUE if combine can reuse reg X in mode MODE.
1687 ADDED_SETS is nonzero if the original set is still required. */
1689 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1697 /* Allow hard registers if the new mode is legal, and occupies no more
1698 registers than the old mode. */
1699 if (regno < FIRST_PSEUDO_REGISTER)
1700 return (HARD_REGNO_MODE_OK (regno, mode)
1701 && (hard_regno_nregs[regno][GET_MODE (x)]
1702 >= hard_regno_nregs[regno][mode]));
1704 /* Or a pseudo that is only used once. */
1705 return (REG_N_SETS (regno) == 1 && !added_sets
1706 && !REG_USERVAR_P (x));
1709 /* Try to combine the insns I1 and I2 into I3.
1710 Here I1 and I2 appear earlier than I3.
1711 I1 can be zero; then we combine just I2 into I3.
1713 If we are combining three insns and the resulting insn is not recognized,
1714 try splitting it into two insns. If that happens, I2 and I3 are retained
1715 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1718 Return 0 if the combination does not work. Then nothing is changed.
1719 If we did the combination, return the insn at which combine should
1722 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1723 new direct jump instruction. */
1726 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1728 /* New patterns for I3 and I2, respectively. */
1729 rtx newpat, newi2pat = 0;
1730 rtvec newpat_vec_with_clobbers = 0;
1731 int substed_i2 = 0, substed_i1 = 0;
1732 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1733 int added_sets_1, added_sets_2;
1734 /* Total number of SETs to put into I3. */
1736 /* Nonzero if I2's body now appears in I3. */
1738 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1739 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1740 /* Contains I3 if the destination of I3 is used in its source, which means
1741 that the old life of I3 is being killed. If that usage is placed into
1742 I2 and not in I3, a REG_DEAD note must be made. */
1743 rtx i3dest_killed = 0;
1744 /* SET_DEST and SET_SRC of I2 and I1. */
1745 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1746 /* PATTERN (I2), or a copy of it in certain cases. */
1748 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1749 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1750 int i2dest_killed = 0, i1dest_killed = 0;
1751 int i1_feeds_i3 = 0;
1752 /* Notes that must be added to REG_NOTES in I3 and I2. */
1753 rtx new_i3_notes, new_i2_notes;
1754 /* Notes that we substituted I3 into I2 instead of the normal case. */
1755 int i3_subst_into_i2 = 0;
1756 /* Notes that I1, I2 or I3 is a MULT operation. */
1765 /* Exit early if one of the insns involved can't be used for
1767 if (cant_combine_insn_p (i3)
1768 || cant_combine_insn_p (i2)
1769 || (i1 && cant_combine_insn_p (i1))
1770 || likely_spilled_retval_p (i3)
1771 /* We also can't do anything if I3 has a
1772 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1775 /* ??? This gives worse code, and appears to be unnecessary, since no
1776 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1777 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1783 undobuf.other_insn = 0;
1785 /* Reset the hard register usage information. */
1786 CLEAR_HARD_REG_SET (newpat_used_regs);
1788 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1789 code below, set I1 to be the earlier of the two insns. */
1790 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1791 temp = i1, i1 = i2, i2 = temp;
1793 added_links_insn = 0;
1795 /* First check for one important special-case that the code below will
1796 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1797 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1798 we may be able to replace that destination with the destination of I3.
1799 This occurs in the common code where we compute both a quotient and
1800 remainder into a structure, in which case we want to do the computation
1801 directly into the structure to avoid register-register copies.
1803 Note that this case handles both multiple sets in I2 and also
1804 cases where I2 has a number of CLOBBER or PARALLELs.
1806 We make very conservative checks below and only try to handle the
1807 most common cases of this. For example, we only handle the case
1808 where I2 and I3 are adjacent to avoid making difficult register
1811 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1812 && REG_P (SET_SRC (PATTERN (i3)))
1813 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1814 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1815 && GET_CODE (PATTERN (i2)) == PARALLEL
1816 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1817 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1818 below would need to check what is inside (and reg_overlap_mentioned_p
1819 doesn't support those codes anyway). Don't allow those destinations;
1820 the resulting insn isn't likely to be recognized anyway. */
1821 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1822 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1823 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1824 SET_DEST (PATTERN (i3)))
1825 && next_real_insn (i2) == i3)
1827 rtx p2 = PATTERN (i2);
1829 /* Make sure that the destination of I3,
1830 which we are going to substitute into one output of I2,
1831 is not used within another output of I2. We must avoid making this:
1832 (parallel [(set (mem (reg 69)) ...)
1833 (set (reg 69) ...)])
1834 which is not well-defined as to order of actions.
1835 (Besides, reload can't handle output reloads for this.)
1837 The problem can also happen if the dest of I3 is a memory ref,
1838 if another dest in I2 is an indirect memory ref. */
1839 for (i = 0; i < XVECLEN (p2, 0); i++)
1840 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1841 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1842 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1843 SET_DEST (XVECEXP (p2, 0, i))))
1846 if (i == XVECLEN (p2, 0))
1847 for (i = 0; i < XVECLEN (p2, 0); i++)
1848 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1849 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1850 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1855 subst_low_cuid = INSN_CUID (i2);
1857 added_sets_2 = added_sets_1 = 0;
1858 i2dest = SET_SRC (PATTERN (i3));
1859 i2dest_killed = dead_or_set_p (i2, i2dest);
1861 /* Replace the dest in I2 with our dest and make the resulting
1862 insn the new pattern for I3. Then skip to where we
1863 validate the pattern. Everything was set up above. */
1864 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1865 SET_DEST (PATTERN (i3)));
1868 i3_subst_into_i2 = 1;
1869 goto validate_replacement;
1873 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1874 one of those words to another constant, merge them by making a new
1877 && (temp = single_set (i2)) != 0
1878 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1879 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1880 && REG_P (SET_DEST (temp))
1881 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1882 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1883 && GET_CODE (PATTERN (i3)) == SET
1884 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1885 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1886 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1887 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1888 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1890 HOST_WIDE_INT lo, hi;
1892 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1893 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1896 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1897 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1900 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1902 /* We don't handle the case of the target word being wider
1903 than a host wide int. */
1904 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1906 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1907 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1908 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1910 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1911 hi = INTVAL (SET_SRC (PATTERN (i3)));
1912 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1914 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1915 >> (HOST_BITS_PER_WIDE_INT - 1));
1917 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1918 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1919 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1920 (INTVAL (SET_SRC (PATTERN (i3)))));
1922 hi = lo < 0 ? -1 : 0;
1925 /* We don't handle the case of the higher word not fitting
1926 entirely in either hi or lo. */
1931 subst_low_cuid = INSN_CUID (i2);
1932 added_sets_2 = added_sets_1 = 0;
1933 i2dest = SET_DEST (temp);
1934 i2dest_killed = dead_or_set_p (i2, i2dest);
1936 SUBST (SET_SRC (temp),
1937 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1939 newpat = PATTERN (i2);
1940 goto validate_replacement;
1944 /* If we have no I1 and I2 looks like:
1945 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1947 make up a dummy I1 that is
1950 (set (reg:CC X) (compare:CC Y (const_int 0)))
1952 (We can ignore any trailing CLOBBERs.)
1954 This undoes a previous combination and allows us to match a branch-and-
1957 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1958 && XVECLEN (PATTERN (i2), 0) >= 2
1959 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1960 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1962 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1963 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1964 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1965 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1966 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1967 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1969 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1970 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1975 /* We make I1 with the same INSN_UID as I2. This gives it
1976 the same INSN_CUID for value tracking. Our fake I1 will
1977 never appear in the insn stream so giving it the same INSN_UID
1978 as I2 will not cause a problem. */
1980 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1981 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1982 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1985 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1986 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1987 SET_DEST (PATTERN (i1)));
1992 /* Verify that I2 and I1 are valid for combining. */
1993 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1994 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2000 /* Record whether I2DEST is used in I2SRC and similarly for the other
2001 cases. Knowing this will help in register status updating below. */
2002 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2003 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2004 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2005 i2dest_killed = dead_or_set_p (i2, i2dest);
2006 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2008 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2010 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2012 /* Ensure that I3's pattern can be the destination of combines. */
2013 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2014 i1 && i2dest_in_i1src && i1_feeds_i3,
2021 /* See if any of the insns is a MULT operation. Unless one is, we will
2022 reject a combination that is, since it must be slower. Be conservative
2024 if (GET_CODE (i2src) == MULT
2025 || (i1 != 0 && GET_CODE (i1src) == MULT)
2026 || (GET_CODE (PATTERN (i3)) == SET
2027 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2030 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2031 We used to do this EXCEPT in one case: I3 has a post-inc in an
2032 output operand. However, that exception can give rise to insns like
2034 which is a famous insn on the PDP-11 where the value of r3 used as the
2035 source was model-dependent. Avoid this sort of thing. */
2038 if (!(GET_CODE (PATTERN (i3)) == SET
2039 && REG_P (SET_SRC (PATTERN (i3)))
2040 && MEM_P (SET_DEST (PATTERN (i3)))
2041 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2042 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2043 /* It's not the exception. */
2046 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2047 if (REG_NOTE_KIND (link) == REG_INC
2048 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2050 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2057 /* See if the SETs in I1 or I2 need to be kept around in the merged
2058 instruction: whenever the value set there is still needed past I3.
2059 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2061 For the SET in I1, we have two cases: If I1 and I2 independently
2062 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2063 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2064 in I1 needs to be kept around unless I1DEST dies or is set in either
2065 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2066 I1DEST. If so, we know I1 feeds into I2. */
2068 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2071 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2072 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2074 /* If the set in I2 needs to be kept around, we must make a copy of
2075 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2076 PATTERN (I2), we are only substituting for the original I1DEST, not into
2077 an already-substituted copy. This also prevents making self-referential
2078 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2081 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2082 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2086 i2pat = copy_rtx (i2pat);
2090 /* Substitute in the latest insn for the regs set by the earlier ones. */
2092 maxreg = max_reg_num ();
2097 /* Many machines that don't use CC0 have insns that can both perform an
2098 arithmetic operation and set the condition code. These operations will
2099 be represented as a PARALLEL with the first element of the vector
2100 being a COMPARE of an arithmetic operation with the constant zero.
2101 The second element of the vector will set some pseudo to the result
2102 of the same arithmetic operation. If we simplify the COMPARE, we won't
2103 match such a pattern and so will generate an extra insn. Here we test
2104 for this case, where both the comparison and the operation result are
2105 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2106 I2SRC. Later we will make the PARALLEL that contains I2. */
2108 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2109 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2110 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2111 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2113 #ifdef SELECT_CC_MODE
2115 enum machine_mode compare_mode;
2118 newpat = PATTERN (i3);
2119 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2123 #ifdef SELECT_CC_MODE
2124 /* See if a COMPARE with the operand we substituted in should be done
2125 with the mode that is currently being used. If not, do the same
2126 processing we do in `subst' for a SET; namely, if the destination
2127 is used only once, try to replace it with a register of the proper
2128 mode and also replace the COMPARE. */
2129 if (undobuf.other_insn == 0
2130 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2131 &undobuf.other_insn))
2132 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2134 != GET_MODE (SET_DEST (newpat))))
2136 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2139 unsigned int regno = REGNO (SET_DEST (newpat));
2140 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2142 if (regno >= FIRST_PSEUDO_REGISTER)
2143 SUBST (regno_reg_rtx[regno], new_dest);
2145 SUBST (SET_DEST (newpat), new_dest);
2146 SUBST (XEXP (*cc_use, 0), new_dest);
2147 SUBST (SET_SRC (newpat),
2148 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2151 undobuf.other_insn = 0;
2158 /* It is possible that the source of I2 or I1 may be performing
2159 an unneeded operation, such as a ZERO_EXTEND of something
2160 that is known to have the high part zero. Handle that case
2161 by letting subst look at the innermost one of them.
2163 Another way to do this would be to have a function that tries
2164 to simplify a single insn instead of merging two or more
2165 insns. We don't do this because of the potential of infinite
2166 loops and because of the potential extra memory required.
2167 However, doing it the way we are is a bit of a kludge and
2168 doesn't catch all cases.
2170 But only do this if -fexpensive-optimizations since it slows
2171 things down and doesn't usually win.
2173 This is not done in the COMPARE case above because the
2174 unmodified I2PAT is used in the PARALLEL and so a pattern
2175 with a modified I2SRC would not match. */
2177 if (flag_expensive_optimizations)
2179 /* Pass pc_rtx so no substitutions are done, just
2183 subst_low_cuid = INSN_CUID (i1);
2184 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2188 subst_low_cuid = INSN_CUID (i2);
2189 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2193 n_occurrences = 0; /* `subst' counts here */
2195 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2196 need to make a unique copy of I2SRC each time we substitute it
2197 to avoid self-referential rtl. */
2199 subst_low_cuid = INSN_CUID (i2);
2200 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2201 ! i1_feeds_i3 && i1dest_in_i1src);
2204 /* Record whether i2's body now appears within i3's body. */
2205 i2_is_used = n_occurrences;
2208 /* If we already got a failure, don't try to do more. Otherwise,
2209 try to substitute in I1 if we have it. */
2211 if (i1 && GET_CODE (newpat) != CLOBBER)
2213 /* Before we can do this substitution, we must redo the test done
2214 above (see detailed comments there) that ensures that I1DEST
2215 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2217 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2225 subst_low_cuid = INSN_CUID (i1);
2226 newpat = subst (newpat, i1dest, i1src, 0, 0);
2230 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2231 to count all the ways that I2SRC and I1SRC can be used. */
2232 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2233 && i2_is_used + added_sets_2 > 1)
2234 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2235 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2237 /* Fail if we tried to make a new register. */
2238 || max_reg_num () != maxreg
2239 /* Fail if we couldn't do something and have a CLOBBER. */
2240 || GET_CODE (newpat) == CLOBBER
2241 /* Fail if this new pattern is a MULT and we didn't have one before
2242 at the outer level. */
2243 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2250 /* If the actions of the earlier insns must be kept
2251 in addition to substituting them into the latest one,
2252 we must make a new PARALLEL for the latest insn
2253 to hold additional the SETs. */
2255 if (added_sets_1 || added_sets_2)
2259 if (GET_CODE (newpat) == PARALLEL)
2261 rtvec old = XVEC (newpat, 0);
2262 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2263 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2264 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2265 sizeof (old->elem[0]) * old->num_elem);
2270 total_sets = 1 + added_sets_1 + added_sets_2;
2271 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2272 XVECEXP (newpat, 0, 0) = old;
2276 XVECEXP (newpat, 0, --total_sets)
2277 = (GET_CODE (PATTERN (i1)) == PARALLEL
2278 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2282 /* If there is no I1, use I2's body as is. We used to also not do
2283 the subst call below if I2 was substituted into I3,
2284 but that could lose a simplification. */
2286 XVECEXP (newpat, 0, --total_sets) = i2pat;
2288 /* See comment where i2pat is assigned. */
2289 XVECEXP (newpat, 0, --total_sets)
2290 = subst (i2pat, i1dest, i1src, 0, 0);
2294 /* We come here when we are replacing a destination in I2 with the
2295 destination of I3. */
2296 validate_replacement:
2298 /* Note which hard regs this insn has as inputs. */
2299 mark_used_regs_combine (newpat);
2301 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2302 consider splitting this pattern, we might need these clobbers. */
2303 if (i1 && GET_CODE (newpat) == PARALLEL
2304 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2306 int len = XVECLEN (newpat, 0);
2308 newpat_vec_with_clobbers = rtvec_alloc (len);
2309 for (i = 0; i < len; i++)
2310 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2313 /* Is the result of combination a valid instruction? */
2314 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2316 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2317 the second SET's destination is a register that is unused and isn't
2318 marked as an instruction that might trap in an EH region. In that case,
2319 we just need the first SET. This can occur when simplifying a divmod
2320 insn. We *must* test for this case here because the code below that
2321 splits two independent SETs doesn't handle this case correctly when it
2322 updates the register status.
2324 It's pointless doing this if we originally had two sets, one from
2325 i3, and one from i2. Combining then splitting the parallel results
2326 in the original i2 again plus an invalid insn (which we delete).
2327 The net effect is only to move instructions around, which makes
2328 debug info less accurate.
2330 Also check the case where the first SET's destination is unused.
2331 That would not cause incorrect code, but does cause an unneeded
2334 if (insn_code_number < 0
2335 && !(added_sets_2 && i1 == 0)
2336 && GET_CODE (newpat) == PARALLEL
2337 && XVECLEN (newpat, 0) == 2
2338 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2339 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2340 && asm_noperands (newpat) < 0)
2342 rtx set0 = XVECEXP (newpat, 0, 0);
2343 rtx set1 = XVECEXP (newpat, 0, 1);
2346 if (((REG_P (SET_DEST (set1))
2347 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2348 || (GET_CODE (SET_DEST (set1)) == SUBREG
2349 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2350 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2351 || INTVAL (XEXP (note, 0)) <= 0)
2352 && ! side_effects_p (SET_SRC (set1)))
2355 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2358 else if (((REG_P (SET_DEST (set0))
2359 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2360 || (GET_CODE (SET_DEST (set0)) == SUBREG
2361 && find_reg_note (i3, REG_UNUSED,
2362 SUBREG_REG (SET_DEST (set0)))))
2363 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2364 || INTVAL (XEXP (note, 0)) <= 0)
2365 && ! side_effects_p (SET_SRC (set0)))
2368 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2370 if (insn_code_number >= 0)
2372 /* If we will be able to accept this, we have made a
2373 change to the destination of I3. This requires us to
2374 do a few adjustments. */
2376 PATTERN (i3) = newpat;
2377 adjust_for_new_dest (i3);
2382 /* If we were combining three insns and the result is a simple SET
2383 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2384 insns. There are two ways to do this. It can be split using a
2385 machine-specific method (like when you have an addition of a large
2386 constant) or by combine in the function find_split_point. */
2388 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2389 && asm_noperands (newpat) < 0)
2391 rtx m_split, *split;
2392 rtx ni2dest = i2dest;
2394 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2395 use I2DEST as a scratch register will help. In the latter case,
2396 convert I2DEST to the mode of the source of NEWPAT if we can. */
2398 m_split = split_insns (newpat, i3);
2400 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2401 inputs of NEWPAT. */
2403 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2404 possible to try that as a scratch reg. This would require adding
2405 more code to make it work though. */
2407 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2409 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2410 /* If I2DEST is a hard register or the only use of a pseudo,
2411 we can change its mode. */
2412 if (new_mode != GET_MODE (i2dest)
2413 && new_mode != VOIDmode
2414 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2415 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2418 m_split = split_insns (gen_rtx_PARALLEL
2420 gen_rtvec (2, newpat,
2421 gen_rtx_CLOBBER (VOIDmode,
2424 /* If the split with the mode-changed register didn't work, try
2425 the original register. */
2426 if (! m_split && ni2dest != i2dest)
2429 m_split = split_insns (gen_rtx_PARALLEL
2431 gen_rtvec (2, newpat,
2432 gen_rtx_CLOBBER (VOIDmode,
2438 /* If recog_for_combine has discarded clobbers, try to use them
2439 again for the split. */
2440 if (m_split == 0 && newpat_vec_with_clobbers)
2442 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2443 newpat_vec_with_clobbers), i3);
2445 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2447 m_split = PATTERN (m_split);
2448 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2449 if (insn_code_number >= 0)
2452 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2453 && (next_real_insn (i2) == i3
2454 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2457 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2458 newi2pat = PATTERN (m_split);
2460 i3set = single_set (NEXT_INSN (m_split));
2461 i2set = single_set (m_split);
2463 /* In case we changed the mode of I2DEST, replace it in the
2464 pseudo-register table here. We can't do it above in case this
2465 code doesn't get executed and we do a split the other way. */
2467 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2468 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2470 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2472 /* If I2 or I3 has multiple SETs, we won't know how to track
2473 register status, so don't use these insns. If I2's destination
2474 is used between I2 and I3, we also can't use these insns. */
2476 if (i2_code_number >= 0 && i2set && i3set
2477 && (next_real_insn (i2) == i3
2478 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2479 insn_code_number = recog_for_combine (&newi3pat, i3,
2481 if (insn_code_number >= 0)
2484 /* It is possible that both insns now set the destination of I3.
2485 If so, we must show an extra use of it. */
2487 if (insn_code_number >= 0)
2489 rtx new_i3_dest = SET_DEST (i3set);
2490 rtx new_i2_dest = SET_DEST (i2set);
2492 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2493 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2494 || GET_CODE (new_i3_dest) == SUBREG)
2495 new_i3_dest = XEXP (new_i3_dest, 0);
2497 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2498 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2499 || GET_CODE (new_i2_dest) == SUBREG)
2500 new_i2_dest = XEXP (new_i2_dest, 0);
2502 if (REG_P (new_i3_dest)
2503 && REG_P (new_i2_dest)
2504 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2505 REG_N_SETS (REGNO (new_i2_dest))++;
2509 /* If we can split it and use I2DEST, go ahead and see if that
2510 helps things be recognized. Verify that none of the registers
2511 are set between I2 and I3. */
2512 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2516 /* We need I2DEST in the proper mode. If it is a hard register
2517 or the only use of a pseudo, we can change its mode.
2518 Make sure we don't change a hard register to have a mode that
2519 isn't valid for it, or change the number of registers. */
2520 && (GET_MODE (*split) == GET_MODE (i2dest)
2521 || GET_MODE (*split) == VOIDmode
2522 || can_change_dest_mode (i2dest, added_sets_2,
2524 && (next_real_insn (i2) == i3
2525 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2526 /* We can't overwrite I2DEST if its value is still used by
2528 && ! reg_referenced_p (i2dest, newpat))
2530 rtx newdest = i2dest;
2531 enum rtx_code split_code = GET_CODE (*split);
2532 enum machine_mode split_mode = GET_MODE (*split);
2533 bool subst_done = false;
2534 newi2pat = NULL_RTX;
2536 /* Get NEWDEST as a register in the proper mode. We have already
2537 validated that we can do this. */
2538 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2540 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2542 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2543 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2546 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2547 an ASHIFT. This can occur if it was inside a PLUS and hence
2548 appeared to be a memory address. This is a kludge. */
2549 if (split_code == MULT
2550 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2551 && INTVAL (XEXP (*split, 1)) > 0
2552 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2554 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2555 XEXP (*split, 0), GEN_INT (i)));
2556 /* Update split_code because we may not have a multiply
2558 split_code = GET_CODE (*split);
2561 #ifdef INSN_SCHEDULING
2562 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2563 be written as a ZERO_EXTEND. */
2564 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2566 #ifdef LOAD_EXTEND_OP
2567 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2568 what it really is. */
2569 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2571 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2572 SUBREG_REG (*split)));
2575 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2576 SUBREG_REG (*split)));
2580 /* Attempt to split binary operators using arithmetic identities. */
2581 if (BINARY_P (SET_SRC (newpat))
2582 && split_mode == GET_MODE (SET_SRC (newpat))
2583 && ! side_effects_p (SET_SRC (newpat)))
2585 rtx setsrc = SET_SRC (newpat);
2586 enum machine_mode mode = GET_MODE (setsrc);
2587 enum rtx_code code = GET_CODE (setsrc);
2588 rtx src_op0 = XEXP (setsrc, 0);
2589 rtx src_op1 = XEXP (setsrc, 1);
2591 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
2592 if (rtx_equal_p (src_op0, src_op1))
2594 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
2595 SUBST (XEXP (setsrc, 0), newdest);
2596 SUBST (XEXP (setsrc, 1), newdest);
2599 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
2600 else if ((code == PLUS || code == MULT)
2601 && GET_CODE (src_op0) == code
2602 && GET_CODE (XEXP (src_op0, 0)) == code
2603 && (INTEGRAL_MODE_P (mode)
2604 || (FLOAT_MODE_P (mode)
2605 && flag_unsafe_math_optimizations)))
2607 rtx p = XEXP (XEXP (src_op0, 0), 0);
2608 rtx q = XEXP (XEXP (src_op0, 0), 1);
2609 rtx r = XEXP (src_op0, 1);
2612 /* Split both "((X op Y) op X) op Y" and
2613 "((X op Y) op Y) op X" as "T op T" where T is
2615 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
2616 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
2618 newi2pat = gen_rtx_SET (VOIDmode, newdest,
2620 SUBST (XEXP (setsrc, 0), newdest);
2621 SUBST (XEXP (setsrc, 1), newdest);
2624 /* Split "((X op X) op Y) op Y)" as "T op T" where
2626 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
2628 rtx tmp = simplify_gen_binary (code, mode, p, r);
2629 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
2630 SUBST (XEXP (setsrc, 0), newdest);
2631 SUBST (XEXP (setsrc, 1), newdest);
2639 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2640 SUBST (*split, newdest);
2643 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2645 /* recog_for_combine might have added CLOBBERs to newi2pat.
2646 Make sure NEWPAT does not depend on the clobbered regs. */
2647 if (GET_CODE (newi2pat) == PARALLEL)
2648 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2649 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2651 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2652 if (reg_overlap_mentioned_p (reg, newpat))
2659 /* If the split point was a MULT and we didn't have one before,
2660 don't use one now. */
2661 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2662 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2666 /* Check for a case where we loaded from memory in a narrow mode and
2667 then sign extended it, but we need both registers. In that case,
2668 we have a PARALLEL with both loads from the same memory location.
2669 We can split this into a load from memory followed by a register-register
2670 copy. This saves at least one insn, more if register allocation can
2673 We cannot do this if the destination of the first assignment is a
2674 condition code register or cc0. We eliminate this case by making sure
2675 the SET_DEST and SET_SRC have the same mode.
2677 We cannot do this if the destination of the second assignment is
2678 a register that we have already assumed is zero-extended. Similarly
2679 for a SUBREG of such a register. */
2681 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2682 && GET_CODE (newpat) == PARALLEL
2683 && XVECLEN (newpat, 0) == 2
2684 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2685 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2686 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2687 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2688 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2689 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2690 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2691 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2693 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2694 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2695 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2697 && reg_stat[REGNO (temp)].nonzero_bits != 0
2698 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2699 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2700 && (reg_stat[REGNO (temp)].nonzero_bits
2701 != GET_MODE_MASK (word_mode))))
2702 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2703 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2705 && reg_stat[REGNO (temp)].nonzero_bits != 0
2706 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2707 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2708 && (reg_stat[REGNO (temp)].nonzero_bits
2709 != GET_MODE_MASK (word_mode)))))
2710 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2711 SET_SRC (XVECEXP (newpat, 0, 1)))
2712 && ! find_reg_note (i3, REG_UNUSED,
2713 SET_DEST (XVECEXP (newpat, 0, 0))))
2717 newi2pat = XVECEXP (newpat, 0, 0);
2718 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2719 newpat = XVECEXP (newpat, 0, 1);
2720 SUBST (SET_SRC (newpat),
2721 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2722 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2724 if (i2_code_number >= 0)
2725 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2727 if (insn_code_number >= 0)
2731 /* Similarly, check for a case where we have a PARALLEL of two independent
2732 SETs but we started with three insns. In this case, we can do the sets
2733 as two separate insns. This case occurs when some SET allows two
2734 other insns to combine, but the destination of that SET is still live. */
2736 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2737 && GET_CODE (newpat) == PARALLEL
2738 && XVECLEN (newpat, 0) == 2
2739 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2740 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2741 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2742 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2743 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2744 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2745 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2747 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2748 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2749 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2750 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2751 XVECEXP (newpat, 0, 0))
2752 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2753 XVECEXP (newpat, 0, 1))
2754 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2755 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2757 /* Normally, it doesn't matter which of the two is done first,
2758 but it does if one references cc0. In that case, it has to
2761 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2763 newi2pat = XVECEXP (newpat, 0, 0);
2764 newpat = XVECEXP (newpat, 0, 1);
2769 newi2pat = XVECEXP (newpat, 0, 1);
2770 newpat = XVECEXP (newpat, 0, 0);
2773 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2775 if (i2_code_number >= 0)
2776 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2779 /* If it still isn't recognized, fail and change things back the way they
2781 if ((insn_code_number < 0
2782 /* Is the result a reasonable ASM_OPERANDS? */
2783 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2789 /* If we had to change another insn, make sure it is valid also. */
2790 if (undobuf.other_insn)
2792 rtx other_pat = PATTERN (undobuf.other_insn);
2793 rtx new_other_notes;
2796 CLEAR_HARD_REG_SET (newpat_used_regs);
2798 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2801 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2807 PATTERN (undobuf.other_insn) = other_pat;
2809 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2810 are still valid. Then add any non-duplicate notes added by
2811 recog_for_combine. */
2812 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2814 next = XEXP (note, 1);
2816 if (REG_NOTE_KIND (note) == REG_UNUSED
2817 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2819 if (REG_P (XEXP (note, 0)))
2820 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2822 remove_note (undobuf.other_insn, note);
2826 for (note = new_other_notes; note; note = XEXP (note, 1))
2827 if (REG_P (XEXP (note, 0)))
2828 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2830 distribute_notes (new_other_notes, undobuf.other_insn,
2831 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2834 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2835 they are adjacent to each other or not. */
2837 rtx p = prev_nonnote_insn (i3);
2838 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2839 && sets_cc0_p (newi2pat))
2847 /* Only allow this combination if insn_rtx_costs reports that the
2848 replacement instructions are cheaper than the originals. */
2849 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2855 /* We now know that we can do this combination. Merge the insns and
2856 update the status of registers and LOG_LINKS. */
2864 /* I3 now uses what used to be its destination and which is now
2865 I2's destination. This requires us to do a few adjustments. */
2866 PATTERN (i3) = newpat;
2867 adjust_for_new_dest (i3);
2869 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2872 However, some later insn might be using I2's dest and have
2873 a LOG_LINK pointing at I3. We must remove this link.
2874 The simplest way to remove the link is to point it at I1,
2875 which we know will be a NOTE. */
2877 /* newi2pat is usually a SET here; however, recog_for_combine might
2878 have added some clobbers. */
2879 if (GET_CODE (newi2pat) == PARALLEL)
2880 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2882 ni2dest = SET_DEST (newi2pat);
2884 for (insn = NEXT_INSN (i3);
2885 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2886 || insn != BB_HEAD (this_basic_block->next_bb));
2887 insn = NEXT_INSN (insn))
2889 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2891 for (link = LOG_LINKS (insn); link;
2892 link = XEXP (link, 1))
2893 if (XEXP (link, 0) == i3)
2894 XEXP (link, 0) = i1;
2902 rtx i3notes, i2notes, i1notes = 0;
2903 rtx i3links, i2links, i1links = 0;
2906 /* Compute which registers we expect to eliminate. newi2pat may be setting
2907 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2908 same as i3dest, in which case newi2pat may be setting i1dest. */
2909 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2910 || i2dest_in_i2src || i2dest_in_i1src
2913 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2914 || (newi2pat && reg_set_p (i1dest, newi2pat))
2918 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2920 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2921 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2923 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2925 /* Ensure that we do not have something that should not be shared but
2926 occurs multiple times in the new insns. Check this by first
2927 resetting all the `used' flags and then copying anything is shared. */
2929 reset_used_flags (i3notes);
2930 reset_used_flags (i2notes);
2931 reset_used_flags (i1notes);
2932 reset_used_flags (newpat);
2933 reset_used_flags (newi2pat);
2934 if (undobuf.other_insn)
2935 reset_used_flags (PATTERN (undobuf.other_insn));
2937 i3notes = copy_rtx_if_shared (i3notes);
2938 i2notes = copy_rtx_if_shared (i2notes);
2939 i1notes = copy_rtx_if_shared (i1notes);
2940 newpat = copy_rtx_if_shared (newpat);
2941 newi2pat = copy_rtx_if_shared (newi2pat);
2942 if (undobuf.other_insn)
2943 reset_used_flags (PATTERN (undobuf.other_insn));
2945 INSN_CODE (i3) = insn_code_number;
2946 PATTERN (i3) = newpat;
2948 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2950 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2952 reset_used_flags (call_usage);
2953 call_usage = copy_rtx (call_usage);
2956 replace_rtx (call_usage, i2dest, i2src);
2959 replace_rtx (call_usage, i1dest, i1src);
2961 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2964 if (undobuf.other_insn)
2965 INSN_CODE (undobuf.other_insn) = other_code_number;
2967 /* We had one special case above where I2 had more than one set and
2968 we replaced a destination of one of those sets with the destination
2969 of I3. In that case, we have to update LOG_LINKS of insns later
2970 in this basic block. Note that this (expensive) case is rare.
2972 Also, in this case, we must pretend that all REG_NOTEs for I2
2973 actually came from I3, so that REG_UNUSED notes from I2 will be
2974 properly handled. */
2976 if (i3_subst_into_i2)
2978 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2979 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2980 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2981 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2982 && ! find_reg_note (i2, REG_UNUSED,
2983 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2984 for (temp = NEXT_INSN (i2);
2985 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2986 || BB_HEAD (this_basic_block) != temp);
2987 temp = NEXT_INSN (temp))
2988 if (temp != i3 && INSN_P (temp))
2989 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2990 if (XEXP (link, 0) == i2)
2991 XEXP (link, 0) = i3;
2996 while (XEXP (link, 1))
2997 link = XEXP (link, 1);
2998 XEXP (link, 1) = i2notes;
3012 INSN_CODE (i2) = i2_code_number;
3013 PATTERN (i2) = newi2pat;
3016 SET_INSN_DELETED (i2);
3022 SET_INSN_DELETED (i1);
3025 /* Get death notes for everything that is now used in either I3 or
3026 I2 and used to die in a previous insn. If we built two new
3027 patterns, move from I1 to I2 then I2 to I3 so that we get the
3028 proper movement on registers that I2 modifies. */
3032 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
3033 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
3036 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
3039 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3041 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3044 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3047 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3050 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3053 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3054 know these are REG_UNUSED and want them to go to the desired insn,
3055 so we always pass it as i3. We have not counted the notes in
3056 reg_n_deaths yet, so we need to do so now. */
3058 if (newi2pat && new_i2_notes)
3060 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
3061 if (REG_P (XEXP (temp, 0)))
3062 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3064 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3069 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3070 if (REG_P (XEXP (temp, 0)))
3071 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3073 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3076 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3077 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3078 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3079 in that case, it might delete I2. Similarly for I2 and I1.
3080 Show an additional death due to the REG_DEAD note we make here. If
3081 we discard it in distribute_notes, we will decrement it again. */
3085 if (REG_P (i3dest_killed))
3086 REG_N_DEATHS (REGNO (i3dest_killed))++;
3088 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3089 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3091 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3093 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3095 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3099 if (i2dest_in_i2src)
3102 REG_N_DEATHS (REGNO (i2dest))++;
3104 if (newi2pat && reg_set_p (i2dest, newi2pat))
3105 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3106 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3108 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3109 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3110 NULL_RTX, NULL_RTX);
3113 if (i1dest_in_i1src)
3116 REG_N_DEATHS (REGNO (i1dest))++;
3118 if (newi2pat && reg_set_p (i1dest, newi2pat))
3119 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3120 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3122 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3123 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3124 NULL_RTX, NULL_RTX);
3127 distribute_links (i3links);
3128 distribute_links (i2links);
3129 distribute_links (i1links);
3134 rtx i2_insn = 0, i2_val = 0, set;
3136 /* The insn that used to set this register doesn't exist, and
3137 this life of the register may not exist either. See if one of
3138 I3's links points to an insn that sets I2DEST. If it does,
3139 that is now the last known value for I2DEST. If we don't update
3140 this and I2 set the register to a value that depended on its old
3141 contents, we will get confused. If this insn is used, thing
3142 will be set correctly in combine_instructions. */
3144 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3145 if ((set = single_set (XEXP (link, 0))) != 0
3146 && rtx_equal_p (i2dest, SET_DEST (set)))
3147 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3149 record_value_for_reg (i2dest, i2_insn, i2_val);
3151 /* If the reg formerly set in I2 died only once and that was in I3,
3152 zero its use count so it won't make `reload' do any work. */
3154 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3155 && ! i2dest_in_i2src)
3157 regno = REGNO (i2dest);
3158 REG_N_SETS (regno)--;
3162 if (i1 && REG_P (i1dest))
3165 rtx i1_insn = 0, i1_val = 0, set;
3167 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3168 if ((set = single_set (XEXP (link, 0))) != 0
3169 && rtx_equal_p (i1dest, SET_DEST (set)))
3170 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3172 record_value_for_reg (i1dest, i1_insn, i1_val);
3174 regno = REGNO (i1dest);
3175 if (! added_sets_1 && ! i1dest_in_i1src)
3176 REG_N_SETS (regno)--;
3179 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3180 been made to this insn. The order of
3181 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3182 can affect nonzero_bits of newpat */
3184 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3185 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3187 /* Set new_direct_jump_p if a new return or simple jump instruction
3190 If I3 is now an unconditional jump, ensure that it has a
3191 BARRIER following it since it may have initially been a
3192 conditional jump. It may also be the last nonnote insn. */
3194 if (returnjump_p (i3) || any_uncondjump_p (i3))
3196 *new_direct_jump_p = 1;
3197 mark_jump_label (PATTERN (i3), i3, 0);
3199 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3200 || !BARRIER_P (temp))
3201 emit_barrier_after (i3);
3204 if (undobuf.other_insn != NULL_RTX
3205 && (returnjump_p (undobuf.other_insn)
3206 || any_uncondjump_p (undobuf.other_insn)))
3208 *new_direct_jump_p = 1;
3210 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3211 || !BARRIER_P (temp))
3212 emit_barrier_after (undobuf.other_insn);
3215 /* An NOOP jump does not need barrier, but it does need cleaning up
3217 if (GET_CODE (newpat) == SET
3218 && SET_SRC (newpat) == pc_rtx
3219 && SET_DEST (newpat) == pc_rtx)
3220 *new_direct_jump_p = 1;
3223 combine_successes++;
3226 if (added_links_insn
3227 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3228 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3229 return added_links_insn;
3231 return newi2pat ? i2 : i3;
3234 /* Undo all the modifications recorded in undobuf. */
3239 struct undo *undo, *next;
3241 for (undo = undobuf.undos; undo; undo = next)
3245 *undo->where.i = undo->old_contents.i;
3247 *undo->where.r = undo->old_contents.r;
3249 undo->next = undobuf.frees;
3250 undobuf.frees = undo;
3256 /* We've committed to accepting the changes we made. Move all
3257 of the undos to the free list. */
3262 struct undo *undo, *next;
3264 for (undo = undobuf.undos; undo; undo = next)
3267 undo->next = undobuf.frees;
3268 undobuf.frees = undo;
3274 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3275 where we have an arithmetic expression and return that point. LOC will
3278 try_combine will call this function to see if an insn can be split into
3282 find_split_point (rtx *loc, rtx insn)
3285 enum rtx_code code = GET_CODE (x);
3287 unsigned HOST_WIDE_INT len = 0;
3288 HOST_WIDE_INT pos = 0;
3290 rtx inner = NULL_RTX;
3292 /* First special-case some codes. */
3296 #ifdef INSN_SCHEDULING
3297 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3299 if (MEM_P (SUBREG_REG (x)))
3302 return find_split_point (&SUBREG_REG (x), insn);
3306 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3307 using LO_SUM and HIGH. */
3308 if (GET_CODE (XEXP (x, 0)) == CONST
3309 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3312 gen_rtx_LO_SUM (Pmode,
3313 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3315 return &XEXP (XEXP (x, 0), 0);
3319 /* If we have a PLUS whose second operand is a constant and the
3320 address is not valid, perhaps will can split it up using
3321 the machine-specific way to split large constants. We use
3322 the first pseudo-reg (one of the virtual regs) as a placeholder;
3323 it will not remain in the result. */
3324 if (GET_CODE (XEXP (x, 0)) == PLUS
3325 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3326 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3328 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3329 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3332 /* This should have produced two insns, each of which sets our
3333 placeholder. If the source of the second is a valid address,
3334 we can make put both sources together and make a split point
3338 && NEXT_INSN (seq) != NULL_RTX
3339 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3340 && NONJUMP_INSN_P (seq)
3341 && GET_CODE (PATTERN (seq)) == SET
3342 && SET_DEST (PATTERN (seq)) == reg
3343 && ! reg_mentioned_p (reg,
3344 SET_SRC (PATTERN (seq)))
3345 && NONJUMP_INSN_P (NEXT_INSN (seq))
3346 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3347 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3348 && memory_address_p (GET_MODE (x),
3349 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3351 rtx src1 = SET_SRC (PATTERN (seq));
3352 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3354 /* Replace the placeholder in SRC2 with SRC1. If we can
3355 find where in SRC2 it was placed, that can become our
3356 split point and we can replace this address with SRC2.
3357 Just try two obvious places. */
3359 src2 = replace_rtx (src2, reg, src1);
3361 if (XEXP (src2, 0) == src1)
3362 split = &XEXP (src2, 0);
3363 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3364 && XEXP (XEXP (src2, 0), 0) == src1)
3365 split = &XEXP (XEXP (src2, 0), 0);
3369 SUBST (XEXP (x, 0), src2);
3374 /* If that didn't work, perhaps the first operand is complex and
3375 needs to be computed separately, so make a split point there.
3376 This will occur on machines that just support REG + CONST
3377 and have a constant moved through some previous computation. */
3379 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3380 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3381 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3382 return &XEXP (XEXP (x, 0), 0);
3388 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3389 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3390 we need to put the operand into a register. So split at that
3393 if (SET_DEST (x) == cc0_rtx
3394 && GET_CODE (SET_SRC (x)) != COMPARE
3395 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3396 && !OBJECT_P (SET_SRC (x))
3397 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3398 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3399 return &SET_SRC (x);
3402 /* See if we can split SET_SRC as it stands. */
3403 split = find_split_point (&SET_SRC (x), insn);
3404 if (split && split != &SET_SRC (x))
3407 /* See if we can split SET_DEST as it stands. */
3408 split = find_split_point (&SET_DEST (x), insn);
3409 if (split && split != &SET_DEST (x))
3412 /* See if this is a bitfield assignment with everything constant. If
3413 so, this is an IOR of an AND, so split it into that. */
3414 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3415 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3416 <= HOST_BITS_PER_WIDE_INT)
3417 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3418 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3419 && GET_CODE (SET_SRC (x)) == CONST_INT
3420 && ((INTVAL (XEXP (SET_DEST (x), 1))
3421 + INTVAL (XEXP (SET_DEST (x), 2)))
3422 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3423 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3425 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3426 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3427 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3428 rtx dest = XEXP (SET_DEST (x), 0);
3429 enum machine_mode mode = GET_MODE (dest);
3430 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3433 if (BITS_BIG_ENDIAN)
3434 pos = GET_MODE_BITSIZE (mode) - len - pos;
3436 or_mask = gen_int_mode (src << pos, mode);
3439 simplify_gen_binary (IOR, mode, dest, or_mask));
3442 rtx negmask = gen_int_mode (~(mask << pos), mode);
3444 simplify_gen_binary (IOR, mode,
3445 simplify_gen_binary (AND, mode,
3450 SUBST (SET_DEST (x), dest);
3452 split = find_split_point (&SET_SRC (x), insn);
3453 if (split && split != &SET_SRC (x))
3457 /* Otherwise, see if this is an operation that we can split into two.
3458 If so, try to split that. */
3459 code = GET_CODE (SET_SRC (x));
3464 /* If we are AND'ing with a large constant that is only a single
3465 bit and the result is only being used in a context where we
3466 need to know if it is zero or nonzero, replace it with a bit
3467 extraction. This will avoid the large constant, which might
3468 have taken more than one insn to make. If the constant were
3469 not a valid argument to the AND but took only one insn to make,
3470 this is no worse, but if it took more than one insn, it will
3473 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3474 && REG_P (XEXP (SET_SRC (x), 0))
3475 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3476 && REG_P (SET_DEST (x))
3477 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3478 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3479 && XEXP (*split, 0) == SET_DEST (x)
3480 && XEXP (*split, 1) == const0_rtx)
3482 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3483 XEXP (SET_SRC (x), 0),
3484 pos, NULL_RTX, 1, 1, 0, 0);
3485 if (extraction != 0)
3487 SUBST (SET_SRC (x), extraction);
3488 return find_split_point (loc, insn);
3494 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3495 is known to be on, this can be converted into a NEG of a shift. */
3496 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3497 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3498 && 1 <= (pos = exact_log2
3499 (nonzero_bits (XEXP (SET_SRC (x), 0),
3500 GET_MODE (XEXP (SET_SRC (x), 0))))))
3502 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3506 gen_rtx_LSHIFTRT (mode,
3507 XEXP (SET_SRC (x), 0),
3510 split = find_split_point (&SET_SRC (x), insn);
3511 if (split && split != &SET_SRC (x))
3517 inner = XEXP (SET_SRC (x), 0);
3519 /* We can't optimize if either mode is a partial integer
3520 mode as we don't know how many bits are significant
3522 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3523 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3527 len = GET_MODE_BITSIZE (GET_MODE (inner));
3533 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3534 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3536 inner = XEXP (SET_SRC (x), 0);
3537 len = INTVAL (XEXP (SET_SRC (x), 1));
3538 pos = INTVAL (XEXP (SET_SRC (x), 2));
3540 if (BITS_BIG_ENDIAN)
3541 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3542 unsignedp = (code == ZERO_EXTRACT);
3550 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3552 enum machine_mode mode = GET_MODE (SET_SRC (x));
3554 /* For unsigned, we have a choice of a shift followed by an
3555 AND or two shifts. Use two shifts for field sizes where the
3556 constant might be too large. We assume here that we can
3557 always at least get 8-bit constants in an AND insn, which is
3558 true for every current RISC. */
3560 if (unsignedp && len <= 8)
3565 (mode, gen_lowpart (mode, inner),
3567 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3569 split = find_split_point (&SET_SRC (x), insn);
3570 if (split && split != &SET_SRC (x))
3577 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3578 gen_rtx_ASHIFT (mode,
3579 gen_lowpart (mode, inner),
3580 GEN_INT (GET_MODE_BITSIZE (mode)
3582 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3584 split = find_split_point (&SET_SRC (x), insn);
3585 if (split && split != &SET_SRC (x))
3590 /* See if this is a simple operation with a constant as the second
3591 operand. It might be that this constant is out of range and hence
3592 could be used as a split point. */
3593 if (BINARY_P (SET_SRC (x))
3594 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3595 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3596 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3597 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3598 return &XEXP (SET_SRC (x), 1);
3600 /* Finally, see if this is a simple operation with its first operand
3601 not in a register. The operation might require this operand in a
3602 register, so return it as a split point. We can always do this
3603 because if the first operand were another operation, we would have
3604 already found it as a split point. */
3605 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3606 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3607 return &XEXP (SET_SRC (x), 0);
3613 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3614 it is better to write this as (not (ior A B)) so we can split it.
3615 Similarly for IOR. */
3616 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3619 gen_rtx_NOT (GET_MODE (x),
3620 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3622 XEXP (XEXP (x, 0), 0),
3623 XEXP (XEXP (x, 1), 0))));
3624 return find_split_point (loc, insn);
3627 /* Many RISC machines have a large set of logical insns. If the
3628 second operand is a NOT, put it first so we will try to split the
3629 other operand first. */
3630 if (GET_CODE (XEXP (x, 1)) == NOT)
3632 rtx tem = XEXP (x, 0);
3633 SUBST (XEXP (x, 0), XEXP (x, 1));
3634 SUBST (XEXP (x, 1), tem);
3642 /* Otherwise, select our actions depending on our rtx class. */
3643 switch (GET_RTX_CLASS (code))
3645 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3647 split = find_split_point (&XEXP (x, 2), insn);
3650 /* ... fall through ... */
3652 case RTX_COMM_ARITH:
3654 case RTX_COMM_COMPARE:
3655 split = find_split_point (&XEXP (x, 1), insn);
3658 /* ... fall through ... */
3660 /* Some machines have (and (shift ...) ...) insns. If X is not
3661 an AND, but XEXP (X, 0) is, use it as our split point. */
3662 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3663 return &XEXP (x, 0);
3665 split = find_split_point (&XEXP (x, 0), insn);
3671 /* Otherwise, we don't have a split point. */
3676 /* Throughout X, replace FROM with TO, and return the result.
3677 The result is TO if X is FROM;
3678 otherwise the result is X, but its contents may have been modified.
3679 If they were modified, a record was made in undobuf so that
3680 undo_all will (among other things) return X to its original state.
3682 If the number of changes necessary is too much to record to undo,
3683 the excess changes are not made, so the result is invalid.
3684 The changes already made can still be undone.
3685 undobuf.num_undo is incremented for such changes, so by testing that
3686 the caller can tell whether the result is valid.
3688 `n_occurrences' is incremented each time FROM is replaced.
3690 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3692 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3693 by copying if `n_occurrences' is nonzero. */
3696 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3698 enum rtx_code code = GET_CODE (x);
3699 enum machine_mode op0_mode = VOIDmode;
3704 /* Two expressions are equal if they are identical copies of a shared
3705 RTX or if they are both registers with the same register number
3708 #define COMBINE_RTX_EQUAL_P(X,Y) \
3710 || (REG_P (X) && REG_P (Y) \
3711 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3713 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3716 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3719 /* If X and FROM are the same register but different modes, they will
3720 not have been seen as equal above. However, flow.c will make a
3721 LOG_LINKS entry for that case. If we do nothing, we will try to
3722 rerecognize our original insn and, when it succeeds, we will
3723 delete the feeding insn, which is incorrect.
3725 So force this insn not to match in this (rare) case. */
3726 if (! in_dest && code == REG && REG_P (from)
3727 && REGNO (x) == REGNO (from))
3728 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3730 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3731 of which may contain things that can be combined. */
3732 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3735 /* It is possible to have a subexpression appear twice in the insn.
3736 Suppose that FROM is a register that appears within TO.
3737 Then, after that subexpression has been scanned once by `subst',
3738 the second time it is scanned, TO may be found. If we were
3739 to scan TO here, we would find FROM within it and create a
3740 self-referent rtl structure which is completely wrong. */
3741 if (COMBINE_RTX_EQUAL_P (x, to))
3744 /* Parallel asm_operands need special attention because all of the
3745 inputs are shared across the arms. Furthermore, unsharing the
3746 rtl results in recognition failures. Failure to handle this case
3747 specially can result in circular rtl.
3749 Solve this by doing a normal pass across the first entry of the
3750 parallel, and only processing the SET_DESTs of the subsequent
3753 if (code == PARALLEL
3754 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3755 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3757 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3759 /* If this substitution failed, this whole thing fails. */
3760 if (GET_CODE (new) == CLOBBER
3761 && XEXP (new, 0) == const0_rtx)
3764 SUBST (XVECEXP (x, 0, 0), new);
3766 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3768 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3771 && GET_CODE (dest) != CC0
3772 && GET_CODE (dest) != PC)
3774 new = subst (dest, from, to, 0, unique_copy);
3776 /* If this substitution failed, this whole thing fails. */
3777 if (GET_CODE (new) == CLOBBER
3778 && XEXP (new, 0) == const0_rtx)
3781 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3787 len = GET_RTX_LENGTH (code);
3788 fmt = GET_RTX_FORMAT (code);
3790 /* We don't need to process a SET_DEST that is a register, CC0,
3791 or PC, so set up to skip this common case. All other cases
3792 where we want to suppress replacing something inside a
3793 SET_SRC are handled via the IN_DEST operand. */
3795 && (REG_P (SET_DEST (x))
3796 || GET_CODE (SET_DEST (x)) == CC0
3797 || GET_CODE (SET_DEST (x)) == PC))
3800 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3803 op0_mode = GET_MODE (XEXP (x, 0));
3805 for (i = 0; i < len; i++)
3810 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3812 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3814 new = (unique_copy && n_occurrences
3815 ? copy_rtx (to) : to);
3820 new = subst (XVECEXP (x, i, j), from, to, 0,
3823 /* If this substitution failed, this whole thing
3825 if (GET_CODE (new) == CLOBBER
3826 && XEXP (new, 0) == const0_rtx)
3830 SUBST (XVECEXP (x, i, j), new);
3833 else if (fmt[i] == 'e')
3835 /* If this is a register being set, ignore it. */
3839 && (((code == SUBREG || code == ZERO_EXTRACT)
3841 || code == STRICT_LOW_PART))
3844 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3846 /* In general, don't install a subreg involving two
3847 modes not tieable. It can worsen register
3848 allocation, and can even make invalid reload
3849 insns, since the reg inside may need to be copied
3850 from in the outside mode, and that may be invalid
3851 if it is an fp reg copied in integer mode.
3853 We allow two exceptions to this: It is valid if
3854 it is inside another SUBREG and the mode of that
3855 SUBREG and the mode of the inside of TO is
3856 tieable and it is valid if X is a SET that copies
3859 if (GET_CODE (to) == SUBREG
3860 && ! MODES_TIEABLE_P (GET_MODE (to),
3861 GET_MODE (SUBREG_REG (to)))
3862 && ! (code == SUBREG
3863 && MODES_TIEABLE_P (GET_MODE (x),
3864 GET_MODE (SUBREG_REG (to))))
3866 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3869 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3871 #ifdef CANNOT_CHANGE_MODE_CLASS
3874 && REGNO (to) < FIRST_PSEUDO_REGISTER
3875 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3878 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3881 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3885 /* If we are in a SET_DEST, suppress most cases unless we
3886 have gone inside a MEM, in which case we want to
3887 simplify the address. We assume here that things that
3888 are actually part of the destination have their inner
3889 parts in the first expression. This is true for SUBREG,
3890 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3891 things aside from REG and MEM that should appear in a
3893 new = subst (XEXP (x, i), from, to,
3895 && (code == SUBREG || code == STRICT_LOW_PART
3896 || code == ZERO_EXTRACT))
3898 && i == 0), unique_copy);
3900 /* If we found that we will have to reject this combination,
3901 indicate that by returning the CLOBBER ourselves, rather than
3902 an expression containing it. This will speed things up as
3903 well as prevent accidents where two CLOBBERs are considered
3904 to be equal, thus producing an incorrect simplification. */
3906 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3909 if (GET_CODE (x) == SUBREG
3910 && (GET_CODE (new) == CONST_INT
3911 || GET_CODE (new) == CONST_DOUBLE))
3913 enum machine_mode mode = GET_MODE (x);
3915 x = simplify_subreg (GET_MODE (x), new,
3916 GET_MODE (SUBREG_REG (x)),
3919 x = gen_rtx_CLOBBER (mode, const0_rtx);
3921 else if (GET_CODE (new) == CONST_INT
3922 && GET_CODE (x) == ZERO_EXTEND)
3924 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3925 new, GET_MODE (XEXP (x, 0)));
3929 SUBST (XEXP (x, i), new);
3934 /* Try to simplify X. If the simplification changed the code, it is likely
3935 that further simplification will help, so loop, but limit the number
3936 of repetitions that will be performed. */
3938 for (i = 0; i < 4; i++)
3940 /* If X is sufficiently simple, don't bother trying to do anything
3942 if (code != CONST_INT && code != REG && code != CLOBBER)
3943 x = combine_simplify_rtx (x, op0_mode, in_dest);
3945 if (GET_CODE (x) == code)
3948 code = GET_CODE (x);
3950 /* We no longer know the original mode of operand 0 since we
3951 have changed the form of X) */
3952 op0_mode = VOIDmode;
3958 /* Simplify X, a piece of RTL. We just operate on the expression at the
3959 outer level; call `subst' to simplify recursively. Return the new
3962 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3963 if we are inside a SET_DEST. */
3966 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3968 enum rtx_code code = GET_CODE (x);
3969 enum machine_mode mode = GET_MODE (x);
3973 /* If this is a commutative operation, put a constant last and a complex
3974 expression first. We don't need to do this for comparisons here. */
3975 if (COMMUTATIVE_ARITH_P (x)
3976 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3979 SUBST (XEXP (x, 0), XEXP (x, 1));
3980 SUBST (XEXP (x, 1), temp);
3983 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3984 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3985 things. Check for cases where both arms are testing the same
3988 Don't do anything if all operands are very simple. */
3991 && ((!OBJECT_P (XEXP (x, 0))
3992 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3993 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3994 || (!OBJECT_P (XEXP (x, 1))
3995 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3996 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3998 && (!OBJECT_P (XEXP (x, 0))
3999 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4000 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4002 rtx cond, true_rtx, false_rtx;
4004 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4006 /* If everything is a comparison, what we have is highly unlikely
4007 to be simpler, so don't use it. */
4008 && ! (COMPARISON_P (x)
4009 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4011 rtx cop1 = const0_rtx;
4012 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4014 if (cond_code == NE && COMPARISON_P (cond))
4017 /* Simplify the alternative arms; this may collapse the true and
4018 false arms to store-flag values. Be careful to use copy_rtx
4019 here since true_rtx or false_rtx might share RTL with x as a
4020 result of the if_then_else_cond call above. */
4021 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4022 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4024 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4025 is unlikely to be simpler. */
4026 if (general_operand (true_rtx, VOIDmode)
4027 && general_operand (false_rtx, VOIDmode))
4029 enum rtx_code reversed;
4031 /* Restarting if we generate a store-flag expression will cause
4032 us to loop. Just drop through in this case. */
4034 /* If the result values are STORE_FLAG_VALUE and zero, we can
4035 just make the comparison operation. */
4036 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4037 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4039 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4040 && ((reversed = reversed_comparison_code_parts
4041 (cond_code, cond, cop1, NULL))
4043 x = simplify_gen_relational (reversed, mode, VOIDmode,
4046 /* Likewise, we can make the negate of a comparison operation
4047 if the result values are - STORE_FLAG_VALUE and zero. */
4048 else if (GET_CODE (true_rtx) == CONST_INT
4049 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4050 && false_rtx == const0_rtx)
4051 x = simplify_gen_unary (NEG, mode,
4052 simplify_gen_relational (cond_code,
4056 else if (GET_CODE (false_rtx) == CONST_INT
4057 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4058 && true_rtx == const0_rtx
4059 && ((reversed = reversed_comparison_code_parts
4060 (cond_code, cond, cop1, NULL))
4062 x = simplify_gen_unary (NEG, mode,
4063 simplify_gen_relational (reversed,
4068 return gen_rtx_IF_THEN_ELSE (mode,
4069 simplify_gen_relational (cond_code,
4074 true_rtx, false_rtx);
4076 code = GET_CODE (x);
4077 op0_mode = VOIDmode;
4082 /* Try to fold this expression in case we have constants that weren't
4085 switch (GET_RTX_CLASS (code))
4088 if (op0_mode == VOIDmode)
4089 op0_mode = GET_MODE (XEXP (x, 0));
4090 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4093 case RTX_COMM_COMPARE:
4095 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4096 if (cmp_mode == VOIDmode)
4098 cmp_mode = GET_MODE (XEXP (x, 1));
4099 if (cmp_mode == VOIDmode)
4100 cmp_mode = op0_mode;
4102 temp = simplify_relational_operation (code, mode, cmp_mode,
4103 XEXP (x, 0), XEXP (x, 1));
4106 case RTX_COMM_ARITH:
4108 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4110 case RTX_BITFIELD_OPS:
4112 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4113 XEXP (x, 1), XEXP (x, 2));
4122 code = GET_CODE (temp);
4123 op0_mode = VOIDmode;
4124 mode = GET_MODE (temp);
4127 /* First see if we can apply the inverse distributive law. */
4128 if (code == PLUS || code == MINUS
4129 || code == AND || code == IOR || code == XOR)
4131 x = apply_distributive_law (x);
4132 code = GET_CODE (x);
4133 op0_mode = VOIDmode;
4136 /* If CODE is an associative operation not otherwise handled, see if we
4137 can associate some operands. This can win if they are constants or
4138 if they are logically related (i.e. (a & b) & a). */
4139 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4140 || code == AND || code == IOR || code == XOR
4141 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4142 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4143 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4145 if (GET_CODE (XEXP (x, 0)) == code)
4147 rtx other = XEXP (XEXP (x, 0), 0);
4148 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4149 rtx inner_op1 = XEXP (x, 1);
4152 /* Make sure we pass the constant operand if any as the second
4153 one if this is a commutative operation. */
4154 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4156 rtx tem = inner_op0;
4157 inner_op0 = inner_op1;
4160 inner = simplify_binary_operation (code == MINUS ? PLUS
4161 : code == DIV ? MULT
4163 mode, inner_op0, inner_op1);
4165 /* For commutative operations, try the other pair if that one
4167 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4169 other = XEXP (XEXP (x, 0), 1);
4170 inner = simplify_binary_operation (code, mode,
4171 XEXP (XEXP (x, 0), 0),
4176 return simplify_gen_binary (code, mode, other, inner);
4180 /* A little bit of algebraic simplification here. */
4184 /* Ensure that our address has any ASHIFTs converted to MULT in case
4185 address-recognizing predicates are called later. */
4186 temp = make_compound_operation (XEXP (x, 0), MEM);
4187 SUBST (XEXP (x, 0), temp);
4191 if (op0_mode == VOIDmode)
4192 op0_mode = GET_MODE (SUBREG_REG (x));
4194 /* See if this can be moved to simplify_subreg. */
4195 if (CONSTANT_P (SUBREG_REG (x))
4196 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4197 /* Don't call gen_lowpart if the inner mode
4198 is VOIDmode and we cannot simplify it, as SUBREG without
4199 inner mode is invalid. */
4200 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4201 || gen_lowpart_common (mode, SUBREG_REG (x))))
4202 return gen_lowpart (mode, SUBREG_REG (x));
4204 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4208 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4214 /* Don't change the mode of the MEM if that would change the meaning
4216 if (MEM_P (SUBREG_REG (x))
4217 && (MEM_VOLATILE_P (SUBREG_REG (x))
4218 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4219 return gen_rtx_CLOBBER (mode, const0_rtx);
4221 /* Note that we cannot do any narrowing for non-constants since
4222 we might have been counting on using the fact that some bits were
4223 zero. We now do this in the SET. */
4228 temp = expand_compound_operation (XEXP (x, 0));
4230 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4231 replaced by (lshiftrt X C). This will convert
4232 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4234 if (GET_CODE (temp) == ASHIFTRT
4235 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4236 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4237 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4238 INTVAL (XEXP (temp, 1)));
4240 /* If X has only a single bit that might be nonzero, say, bit I, convert
4241 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4242 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4243 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4244 or a SUBREG of one since we'd be making the expression more
4245 complex if it was just a register. */
4248 && ! (GET_CODE (temp) == SUBREG
4249 && REG_P (SUBREG_REG (temp)))
4250 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4252 rtx temp1 = simplify_shift_const
4253 (NULL_RTX, ASHIFTRT, mode,
4254 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4255 GET_MODE_BITSIZE (mode) - 1 - i),
4256 GET_MODE_BITSIZE (mode) - 1 - i);
4258 /* If all we did was surround TEMP with the two shifts, we
4259 haven't improved anything, so don't use it. Otherwise,
4260 we are better off with TEMP1. */
4261 if (GET_CODE (temp1) != ASHIFTRT
4262 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4263 || XEXP (XEXP (temp1, 0), 0) != temp)
4269 /* We can't handle truncation to a partial integer mode here
4270 because we don't know the real bitsize of the partial
4272 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4275 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4276 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4277 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4279 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4280 GET_MODE_MASK (mode), 0));
4282 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4283 whose value is a comparison can be replaced with a subreg if
4284 STORE_FLAG_VALUE permits. */
4285 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4286 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4287 && (temp = get_last_value (XEXP (x, 0)))
4288 && COMPARISON_P (temp))
4289 return gen_lowpart (mode, XEXP (x, 0));
4294 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4295 using cc0, in which case we want to leave it as a COMPARE
4296 so we can distinguish it from a register-register-copy. */
4297 if (XEXP (x, 1) == const0_rtx)
4300 /* x - 0 is the same as x unless x's mode has signed zeros and
4301 allows rounding towards -infinity. Under those conditions,
4303 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4304 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4305 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4311 /* (const (const X)) can become (const X). Do it this way rather than
4312 returning the inner CONST since CONST can be shared with a
4314 if (GET_CODE (XEXP (x, 0)) == CONST)
4315 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4320 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4321 can add in an offset. find_split_point will split this address up
4322 again if it doesn't match. */
4323 if (GET_CODE (XEXP (x, 0)) == HIGH
4324 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4330 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4331 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4332 bit-field and can be replaced by either a sign_extend or a
4333 sign_extract. The `and' may be a zero_extend and the two
4334 <c>, -<c> constants may be reversed. */
4335 if (GET_CODE (XEXP (x, 0)) == XOR
4336 && GET_CODE (XEXP (x, 1)) == CONST_INT
4337 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4338 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4339 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4340 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4341 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4342 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4343 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4344 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4345 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4346 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4347 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4348 == (unsigned int) i + 1))))
4349 return simplify_shift_const
4350 (NULL_RTX, ASHIFTRT, mode,
4351 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4352 XEXP (XEXP (XEXP (x, 0), 0), 0),
4353 GET_MODE_BITSIZE (mode) - (i + 1)),
4354 GET_MODE_BITSIZE (mode) - (i + 1));
4356 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4357 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4358 the bitsize of the mode - 1. This allows simplification of
4359 "a = (b & 8) == 0;" */
4360 if (XEXP (x, 1) == constm1_rtx
4361 && !REG_P (XEXP (x, 0))
4362 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4363 && REG_P (SUBREG_REG (XEXP (x, 0))))
4364 && nonzero_bits (XEXP (x, 0), mode) == 1)
4365 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4366 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4367 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4368 GET_MODE_BITSIZE (mode) - 1),
4369 GET_MODE_BITSIZE (mode) - 1);
4371 /* If we are adding two things that have no bits in common, convert
4372 the addition into an IOR. This will often be further simplified,
4373 for example in cases like ((a & 1) + (a & 2)), which can
4376 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4377 && (nonzero_bits (XEXP (x, 0), mode)
4378 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4380 /* Try to simplify the expression further. */
4381 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4382 temp = combine_simplify_rtx (tor, mode, in_dest);
4384 /* If we could, great. If not, do not go ahead with the IOR
4385 replacement, since PLUS appears in many special purpose
4386 address arithmetic instructions. */
4387 if (GET_CODE (temp) != CLOBBER && temp != tor)
4393 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4394 (and <foo> (const_int pow2-1)) */
4395 if (GET_CODE (XEXP (x, 1)) == AND
4396 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4397 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4398 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4399 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4400 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4404 /* If we have (mult (plus A B) C), apply the distributive law and then
4405 the inverse distributive law to see if things simplify. This
4406 occurs mostly in addresses, often when unrolling loops. */
4408 if (GET_CODE (XEXP (x, 0)) == PLUS)
4410 rtx result = distribute_and_simplify_rtx (x, 0);
4415 /* Try simplify a*(b/c) as (a*b)/c. */
4416 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4417 && GET_CODE (XEXP (x, 0)) == DIV)
4419 rtx tem = simplify_binary_operation (MULT, mode,
4420 XEXP (XEXP (x, 0), 0),
4423 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4428 /* If this is a divide by a power of two, treat it as a shift if
4429 its first operand is a shift. */
4430 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4431 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4432 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4433 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4434 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4435 || GET_CODE (XEXP (x, 0)) == ROTATE
4436 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4437 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4441 case GT: case GTU: case GE: case GEU:
4442 case LT: case LTU: case LE: case LEU:
4443 case UNEQ: case LTGT:
4444 case UNGT: case UNGE:
4445 case UNLT: case UNLE:
4446 case UNORDERED: case ORDERED:
4447 /* If the first operand is a condition code, we can't do anything
4449 if (GET_CODE (XEXP (x, 0)) == COMPARE
4450 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4451 && ! CC0_P (XEXP (x, 0))))
4453 rtx op0 = XEXP (x, 0);
4454 rtx op1 = XEXP (x, 1);
4455 enum rtx_code new_code;
4457 if (GET_CODE (op0) == COMPARE)
4458 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4460 /* Simplify our comparison, if possible. */
4461 new_code = simplify_comparison (code, &op0, &op1);
4463 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4464 if only the low-order bit is possibly nonzero in X (such as when
4465 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4466 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4467 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4470 Remove any ZERO_EXTRACT we made when thinking this was a
4471 comparison. It may now be simpler to use, e.g., an AND. If a
4472 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4473 the call to make_compound_operation in the SET case. */
4475 if (STORE_FLAG_VALUE == 1
4476 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4477 && op1 == const0_rtx
4478 && mode == GET_MODE (op0)
4479 && nonzero_bits (op0, mode) == 1)
4480 return gen_lowpart (mode,
4481 expand_compound_operation (op0));
4483 else if (STORE_FLAG_VALUE == 1
4484 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4485 && op1 == const0_rtx
4486 && mode == GET_MODE (op0)
4487 && (num_sign_bit_copies (op0, mode)
4488 == GET_MODE_BITSIZE (mode)))
4490 op0 = expand_compound_operation (op0);
4491 return simplify_gen_unary (NEG, mode,
4492 gen_lowpart (mode, op0),
4496 else if (STORE_FLAG_VALUE == 1
4497 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4498 && op1 == const0_rtx
4499 && mode == GET_MODE (op0)
4500 && nonzero_bits (op0, mode) == 1)
4502 op0 = expand_compound_operation (op0);
4503 return simplify_gen_binary (XOR, mode,
4504 gen_lowpart (mode, op0),
4508 else if (STORE_FLAG_VALUE == 1
4509 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4510 && op1 == const0_rtx
4511 && mode == GET_MODE (op0)
4512 && (num_sign_bit_copies (op0, mode)
4513 == GET_MODE_BITSIZE (mode)))
4515 op0 = expand_compound_operation (op0);
4516 return plus_constant (gen_lowpart (mode, op0), 1);
4519 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4521 if (STORE_FLAG_VALUE == -1
4522 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4523 && op1 == const0_rtx
4524 && (num_sign_bit_copies (op0, mode)
4525 == GET_MODE_BITSIZE (mode)))
4526 return gen_lowpart (mode,
4527 expand_compound_operation (op0));
4529 else if (STORE_FLAG_VALUE == -1
4530 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4531 && op1 == const0_rtx
4532 && mode == GET_MODE (op0)
4533 && nonzero_bits (op0, mode) == 1)
4535 op0 = expand_compound_operation (op0);
4536 return simplify_gen_unary (NEG, mode,
4537 gen_lowpart (mode, op0),
4541 else if (STORE_FLAG_VALUE == -1
4542 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4543 && op1 == const0_rtx
4544 && mode == GET_MODE (op0)
4545 && (num_sign_bit_copies (op0, mode)
4546 == GET_MODE_BITSIZE (mode)))
4548 op0 = expand_compound_operation (op0);
4549 return simplify_gen_unary (NOT, mode,
4550 gen_lowpart (mode, op0),
4554 /* If X is 0/1, (eq X 0) is X-1. */
4555 else if (STORE_FLAG_VALUE == -1
4556 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4557 && op1 == const0_rtx
4558 && mode == GET_MODE (op0)
4559 && nonzero_bits (op0, mode) == 1)
4561 op0 = expand_compound_operation (op0);
4562 return plus_constant (gen_lowpart (mode, op0), -1);
4565 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4566 one bit that might be nonzero, we can convert (ne x 0) to
4567 (ashift x c) where C puts the bit in the sign bit. Remove any
4568 AND with STORE_FLAG_VALUE when we are done, since we are only
4569 going to test the sign bit. */
4570 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4571 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4572 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4573 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4574 && op1 == const0_rtx
4575 && mode == GET_MODE (op0)
4576 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4578 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4579 expand_compound_operation (op0),
4580 GET_MODE_BITSIZE (mode) - 1 - i);
4581 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4587 /* If the code changed, return a whole new comparison. */
4588 if (new_code != code)
4589 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4591 /* Otherwise, keep this operation, but maybe change its operands.
4592 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4593 SUBST (XEXP (x, 0), op0);
4594 SUBST (XEXP (x, 1), op1);
4599 return simplify_if_then_else (x);
4605 /* If we are processing SET_DEST, we are done. */
4609 return expand_compound_operation (x);
4612 return simplify_set (x);
4616 return simplify_logical (x);
4623 /* If this is a shift by a constant amount, simplify it. */
4624 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4625 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4626 INTVAL (XEXP (x, 1)));
4628 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4630 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4632 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4644 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4647 simplify_if_then_else (rtx x)
4649 enum machine_mode mode = GET_MODE (x);
4650 rtx cond = XEXP (x, 0);
4651 rtx true_rtx = XEXP (x, 1);
4652 rtx false_rtx = XEXP (x, 2);
4653 enum rtx_code true_code = GET_CODE (cond);
4654 int comparison_p = COMPARISON_P (cond);
4657 enum rtx_code false_code;
4660 /* Simplify storing of the truth value. */
4661 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4662 return simplify_gen_relational (true_code, mode, VOIDmode,
4663 XEXP (cond, 0), XEXP (cond, 1));
4665 /* Also when the truth value has to be reversed. */
4667 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4668 && (reversed = reversed_comparison (cond, mode)))
4671 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4672 in it is being compared against certain values. Get the true and false
4673 comparisons and see if that says anything about the value of each arm. */
4676 && ((false_code = reversed_comparison_code (cond, NULL))
4678 && REG_P (XEXP (cond, 0)))
4681 rtx from = XEXP (cond, 0);
4682 rtx true_val = XEXP (cond, 1);
4683 rtx false_val = true_val;
4686 /* If FALSE_CODE is EQ, swap the codes and arms. */
4688 if (false_code == EQ)
4690 swapped = 1, true_code = EQ, false_code = NE;
4691 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4694 /* If we are comparing against zero and the expression being tested has
4695 only a single bit that might be nonzero, that is its value when it is
4696 not equal to zero. Similarly if it is known to be -1 or 0. */
4698 if (true_code == EQ && true_val == const0_rtx
4699 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4700 false_code = EQ, false_val = GEN_INT (nzb);
4701 else if (true_code == EQ && true_val == const0_rtx
4702 && (num_sign_bit_copies (from, GET_MODE (from))
4703 == GET_MODE_BITSIZE (GET_MODE (from))))
4704 false_code = EQ, false_val = constm1_rtx;
4706 /* Now simplify an arm if we know the value of the register in the
4707 branch and it is used in the arm. Be careful due to the potential
4708 of locally-shared RTL. */
4710 if (reg_mentioned_p (from, true_rtx))
4711 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4713 pc_rtx, pc_rtx, 0, 0);
4714 if (reg_mentioned_p (from, false_rtx))
4715 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4717 pc_rtx, pc_rtx, 0, 0);
4719 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4720 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4722 true_rtx = XEXP (x, 1);
4723 false_rtx = XEXP (x, 2);
4724 true_code = GET_CODE (cond);
4727 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4728 reversed, do so to avoid needing two sets of patterns for
4729 subtract-and-branch insns. Similarly if we have a constant in the true
4730 arm, the false arm is the same as the first operand of the comparison, or
4731 the false arm is more complicated than the true arm. */
4734 && reversed_comparison_code (cond, NULL) != UNKNOWN
4735 && (true_rtx == pc_rtx
4736 || (CONSTANT_P (true_rtx)
4737 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4738 || true_rtx == const0_rtx
4739 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4740 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4741 && !OBJECT_P (false_rtx))
4742 || reg_mentioned_p (true_rtx, false_rtx)
4743 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4745 true_code = reversed_comparison_code (cond, NULL);
4746 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4747 SUBST (XEXP (x, 1), false_rtx);
4748 SUBST (XEXP (x, 2), true_rtx);
4750 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4753 /* It is possible that the conditional has been simplified out. */
4754 true_code = GET_CODE (cond);
4755 comparison_p = COMPARISON_P (cond);
4758 /* If the two arms are identical, we don't need the comparison. */
4760 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4763 /* Convert a == b ? b : a to "a". */
4764 if (true_code == EQ && ! side_effects_p (cond)
4765 && !HONOR_NANS (mode)
4766 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4767 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4769 else if (true_code == NE && ! side_effects_p (cond)
4770 && !HONOR_NANS (mode)
4771 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4772 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4775 /* Look for cases where we have (abs x) or (neg (abs X)). */
4777 if (GET_MODE_CLASS (mode) == MODE_INT
4778 && GET_CODE (false_rtx) == NEG
4779 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4781 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4782 && ! side_effects_p (true_rtx))
4787 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4791 simplify_gen_unary (NEG, mode,
4792 simplify_gen_unary (ABS, mode, true_rtx, mode),
4798 /* Look for MIN or MAX. */
4800 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4802 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4803 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4804 && ! side_effects_p (cond))
4809 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4812 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4815 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4818 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4823 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4824 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4825 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4826 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4827 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4828 neither 1 or -1, but it isn't worth checking for. */
4830 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4832 && GET_MODE_CLASS (mode) == MODE_INT
4833 && ! side_effects_p (x))
4835 rtx t = make_compound_operation (true_rtx, SET);
4836 rtx f = make_compound_operation (false_rtx, SET);
4837 rtx cond_op0 = XEXP (cond, 0);
4838 rtx cond_op1 = XEXP (cond, 1);
4839 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4840 enum machine_mode m = mode;
4841 rtx z = 0, c1 = NULL_RTX;
4843 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4844 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4845 || GET_CODE (t) == ASHIFT
4846 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4847 && rtx_equal_p (XEXP (t, 0), f))
4848 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4850 /* If an identity-zero op is commutative, check whether there
4851 would be a match if we swapped the operands. */
4852 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4853 || GET_CODE (t) == XOR)
4854 && rtx_equal_p (XEXP (t, 1), f))
4855 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4856 else if (GET_CODE (t) == SIGN_EXTEND
4857 && (GET_CODE (XEXP (t, 0)) == PLUS
4858 || GET_CODE (XEXP (t, 0)) == MINUS
4859 || GET_CODE (XEXP (t, 0)) == IOR
4860 || GET_CODE (XEXP (t, 0)) == XOR
4861 || GET_CODE (XEXP (t, 0)) == ASHIFT
4862 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4863 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4864 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4865 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4866 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4867 && (num_sign_bit_copies (f, GET_MODE (f))
4869 (GET_MODE_BITSIZE (mode)
4870 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4872 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4873 extend_op = SIGN_EXTEND;
4874 m = GET_MODE (XEXP (t, 0));
4876 else if (GET_CODE (t) == SIGN_EXTEND
4877 && (GET_CODE (XEXP (t, 0)) == PLUS
4878 || GET_CODE (XEXP (t, 0)) == IOR
4879 || GET_CODE (XEXP (t, 0)) == XOR)
4880 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4881 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4882 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4883 && (num_sign_bit_copies (f, GET_MODE (f))
4885 (GET_MODE_BITSIZE (mode)
4886 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4888 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4889 extend_op = SIGN_EXTEND;
4890 m = GET_MODE (XEXP (t, 0));
4892 else if (GET_CODE (t) == ZERO_EXTEND
4893 && (GET_CODE (XEXP (t, 0)) == PLUS
4894 || GET_CODE (XEXP (t, 0)) == MINUS
4895 || GET_CODE (XEXP (t, 0)) == IOR
4896 || GET_CODE (XEXP (t, 0)) == XOR
4897 || GET_CODE (XEXP (t, 0)) == ASHIFT
4898 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4899 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4900 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4901 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4902 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4903 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4904 && ((nonzero_bits (f, GET_MODE (f))
4905 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4908 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4909 extend_op = ZERO_EXTEND;
4910 m = GET_MODE (XEXP (t, 0));
4912 else if (GET_CODE (t) == ZERO_EXTEND
4913 && (GET_CODE (XEXP (t, 0)) == PLUS
4914 || GET_CODE (XEXP (t, 0)) == IOR
4915 || GET_CODE (XEXP (t, 0)) == XOR)
4916 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4917 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4918 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4919 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4920 && ((nonzero_bits (f, GET_MODE (f))
4921 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4924 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4925 extend_op = ZERO_EXTEND;
4926 m = GET_MODE (XEXP (t, 0));
4931 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
4932 cond_op0, cond_op1),
4933 pc_rtx, pc_rtx, 0, 0);
4934 temp = simplify_gen_binary (MULT, m, temp,
4935 simplify_gen_binary (MULT, m, c1,
4937 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4938 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
4940 if (extend_op != UNKNOWN)
4941 temp = simplify_gen_unary (extend_op, mode, temp, m);
4947 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4948 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4949 negation of a single bit, we can convert this operation to a shift. We
4950 can actually do this more generally, but it doesn't seem worth it. */
4952 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4953 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4954 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4955 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4956 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4957 == GET_MODE_BITSIZE (mode))
4958 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4960 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4961 gen_lowpart (mode, XEXP (cond, 0)), i);
4963 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4964 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4965 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4966 && GET_MODE (XEXP (cond, 0)) == mode
4967 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4968 == nonzero_bits (XEXP (cond, 0), mode)
4969 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4970 return XEXP (cond, 0);
4975 /* Simplify X, a SET expression. Return the new expression. */
4978 simplify_set (rtx x)
4980 rtx src = SET_SRC (x);
4981 rtx dest = SET_DEST (x);
4982 enum machine_mode mode
4983 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4987 /* (set (pc) (return)) gets written as (return). */
4988 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4991 /* Now that we know for sure which bits of SRC we are using, see if we can
4992 simplify the expression for the object knowing that we only need the
4995 if (GET_MODE_CLASS (mode) == MODE_INT
4996 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4998 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
4999 SUBST (SET_SRC (x), src);
5002 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5003 the comparison result and try to simplify it unless we already have used
5004 undobuf.other_insn. */
5005 if ((GET_MODE_CLASS (mode) == MODE_CC
5006 || GET_CODE (src) == COMPARE
5008 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5009 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5010 && COMPARISON_P (*cc_use)
5011 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5013 enum rtx_code old_code = GET_CODE (*cc_use);
5014 enum rtx_code new_code;
5016 int other_changed = 0;
5017 enum machine_mode compare_mode = GET_MODE (dest);
5019 if (GET_CODE (src) == COMPARE)
5020 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5022 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5024 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5027 new_code = old_code;
5028 else if (!CONSTANT_P (tmp))
5030 new_code = GET_CODE (tmp);
5031 op0 = XEXP (tmp, 0);
5032 op1 = XEXP (tmp, 1);
5036 rtx pat = PATTERN (other_insn);
5037 undobuf.other_insn = other_insn;
5038 SUBST (*cc_use, tmp);
5040 /* Attempt to simplify CC user. */
5041 if (GET_CODE (pat) == SET)
5043 rtx new = simplify_rtx (SET_SRC (pat));
5044 if (new != NULL_RTX)
5045 SUBST (SET_SRC (pat), new);
5048 /* Convert X into a no-op move. */
5049 SUBST (SET_DEST (x), pc_rtx);
5050 SUBST (SET_SRC (x), pc_rtx);
5054 /* Simplify our comparison, if possible. */
5055 new_code = simplify_comparison (new_code, &op0, &op1);
5057 #ifdef SELECT_CC_MODE
5058 /* If this machine has CC modes other than CCmode, check to see if we
5059 need to use a different CC mode here. */
5060 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5061 compare_mode = GET_MODE (op0);
5063 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5066 /* If the mode changed, we have to change SET_DEST, the mode in the
5067 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5068 a hard register, just build new versions with the proper mode. If it
5069 is a pseudo, we lose unless it is only time we set the pseudo, in
5070 which case we can safely change its mode. */
5071 if (compare_mode != GET_MODE (dest))
5073 if (can_change_dest_mode (dest, 0, compare_mode))
5075 unsigned int regno = REGNO (dest);
5076 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5078 if (regno >= FIRST_PSEUDO_REGISTER)
5079 SUBST (regno_reg_rtx[regno], new_dest);
5081 SUBST (SET_DEST (x), new_dest);
5082 SUBST (XEXP (*cc_use, 0), new_dest);
5089 #endif /* SELECT_CC_MODE */
5091 /* If the code changed, we have to build a new comparison in
5092 undobuf.other_insn. */
5093 if (new_code != old_code)
5095 int other_changed_previously = other_changed;
5096 unsigned HOST_WIDE_INT mask;
5098 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5102 /* If the only change we made was to change an EQ into an NE or
5103 vice versa, OP0 has only one bit that might be nonzero, and OP1
5104 is zero, check if changing the user of the condition code will
5105 produce a valid insn. If it won't, we can keep the original code
5106 in that insn by surrounding our operation with an XOR. */
5108 if (((old_code == NE && new_code == EQ)
5109 || (old_code == EQ && new_code == NE))
5110 && ! other_changed_previously && op1 == const0_rtx
5111 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5112 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5114 rtx pat = PATTERN (other_insn), note = 0;
5116 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5117 && ! check_asm_operands (pat)))
5119 PUT_CODE (*cc_use, old_code);
5122 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5123 op0, GEN_INT (mask));
5129 undobuf.other_insn = other_insn;
5132 /* If we are now comparing against zero, change our source if
5133 needed. If we do not use cc0, we always have a COMPARE. */
5134 if (op1 == const0_rtx && dest == cc0_rtx)
5136 SUBST (SET_SRC (x), op0);
5142 /* Otherwise, if we didn't previously have a COMPARE in the
5143 correct mode, we need one. */
5144 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5146 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5149 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5151 SUBST(SET_SRC (x), op0);
5156 /* Otherwise, update the COMPARE if needed. */
5157 SUBST (XEXP (src, 0), op0);
5158 SUBST (XEXP (src, 1), op1);
5163 /* Get SET_SRC in a form where we have placed back any
5164 compound expressions. Then do the checks below. */
5165 src = make_compound_operation (src, SET);
5166 SUBST (SET_SRC (x), src);
5169 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5170 and X being a REG or (subreg (reg)), we may be able to convert this to
5171 (set (subreg:m2 x) (op)).
5173 We can always do this if M1 is narrower than M2 because that means that
5174 we only care about the low bits of the result.
5176 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5177 perform a narrower operation than requested since the high-order bits will
5178 be undefined. On machine where it is defined, this transformation is safe
5179 as long as M1 and M2 have the same number of words. */
5181 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5182 && !OBJECT_P (SUBREG_REG (src))
5183 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5185 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5186 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5187 #ifndef WORD_REGISTER_OPERATIONS
5188 && (GET_MODE_SIZE (GET_MODE (src))
5189 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5191 #ifdef CANNOT_CHANGE_MODE_CLASS
5192 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5193 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5194 GET_MODE (SUBREG_REG (src)),
5198 || (GET_CODE (dest) == SUBREG
5199 && REG_P (SUBREG_REG (dest)))))
5201 SUBST (SET_DEST (x),
5202 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5204 SUBST (SET_SRC (x), SUBREG_REG (src));
5206 src = SET_SRC (x), dest = SET_DEST (x);
5210 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5213 && GET_CODE (src) == SUBREG
5214 && subreg_lowpart_p (src)
5215 && (GET_MODE_BITSIZE (GET_MODE (src))
5216 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5218 rtx inner = SUBREG_REG (src);
5219 enum machine_mode inner_mode = GET_MODE (inner);
5221 /* Here we make sure that we don't have a sign bit on. */
5222 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5223 && (nonzero_bits (inner, inner_mode)
5224 < ((unsigned HOST_WIDE_INT) 1
5225 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5227 SUBST (SET_SRC (x), inner);
5233 #ifdef LOAD_EXTEND_OP
5234 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5235 would require a paradoxical subreg. Replace the subreg with a
5236 zero_extend to avoid the reload that would otherwise be required. */
5238 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5239 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5240 && SUBREG_BYTE (src) == 0
5241 && (GET_MODE_SIZE (GET_MODE (src))
5242 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5243 && MEM_P (SUBREG_REG (src)))
5246 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5247 GET_MODE (src), SUBREG_REG (src)));
5253 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5254 are comparing an item known to be 0 or -1 against 0, use a logical
5255 operation instead. Check for one of the arms being an IOR of the other
5256 arm with some value. We compute three terms to be IOR'ed together. In
5257 practice, at most two will be nonzero. Then we do the IOR's. */
5259 if (GET_CODE (dest) != PC
5260 && GET_CODE (src) == IF_THEN_ELSE
5261 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5262 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5263 && XEXP (XEXP (src, 0), 1) == const0_rtx
5264 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5265 #ifdef HAVE_conditional_move
5266 && ! can_conditionally_move_p (GET_MODE (src))
5268 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5269 GET_MODE (XEXP (XEXP (src, 0), 0)))
5270 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5271 && ! side_effects_p (src))
5273 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5274 ? XEXP (src, 1) : XEXP (src, 2));
5275 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5276 ? XEXP (src, 2) : XEXP (src, 1));
5277 rtx term1 = const0_rtx, term2, term3;
5279 if (GET_CODE (true_rtx) == IOR
5280 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5281 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5282 else if (GET_CODE (true_rtx) == IOR
5283 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5284 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5285 else if (GET_CODE (false_rtx) == IOR
5286 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5287 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5288 else if (GET_CODE (false_rtx) == IOR
5289 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5290 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5292 term2 = simplify_gen_binary (AND, GET_MODE (src),
5293 XEXP (XEXP (src, 0), 0), true_rtx);
5294 term3 = simplify_gen_binary (AND, GET_MODE (src),
5295 simplify_gen_unary (NOT, GET_MODE (src),
5296 XEXP (XEXP (src, 0), 0),
5301 simplify_gen_binary (IOR, GET_MODE (src),
5302 simplify_gen_binary (IOR, GET_MODE (src),
5309 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5310 whole thing fail. */
5311 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5313 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5316 /* Convert this into a field assignment operation, if possible. */
5317 return make_field_assignment (x);
5320 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5324 simplify_logical (rtx x)
5326 enum machine_mode mode = GET_MODE (x);
5327 rtx op0 = XEXP (x, 0);
5328 rtx op1 = XEXP (x, 1);
5330 switch (GET_CODE (x))
5333 /* We can call simplify_and_const_int only if we don't lose
5334 any (sign) bits when converting INTVAL (op1) to
5335 "unsigned HOST_WIDE_INT". */
5336 if (GET_CODE (op1) == CONST_INT
5337 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5338 || INTVAL (op1) > 0))
5340 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5341 if (GET_CODE (x) != AND)
5348 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5349 apply the distributive law and then the inverse distributive
5350 law to see if things simplify. */
5351 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5353 rtx result = distribute_and_simplify_rtx (x, 0);
5357 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5359 rtx result = distribute_and_simplify_rtx (x, 1);
5366 /* If we have (ior (and A B) C), apply the distributive law and then
5367 the inverse distributive law to see if things simplify. */
5369 if (GET_CODE (op0) == AND)
5371 rtx result = distribute_and_simplify_rtx (x, 0);
5376 if (GET_CODE (op1) == AND)
5378 rtx result = distribute_and_simplify_rtx (x, 1);
5391 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5392 operations" because they can be replaced with two more basic operations.
5393 ZERO_EXTEND is also considered "compound" because it can be replaced with
5394 an AND operation, which is simpler, though only one operation.
5396 The function expand_compound_operation is called with an rtx expression
5397 and will convert it to the appropriate shifts and AND operations,
5398 simplifying at each stage.
5400 The function make_compound_operation is called to convert an expression
5401 consisting of shifts and ANDs into the equivalent compound expression.
5402 It is the inverse of this function, loosely speaking. */
5405 expand_compound_operation (rtx x)
5407 unsigned HOST_WIDE_INT pos = 0, len;
5409 unsigned int modewidth;
5412 switch (GET_CODE (x))
5417 /* We can't necessarily use a const_int for a multiword mode;
5418 it depends on implicitly extending the value.
5419 Since we don't know the right way to extend it,
5420 we can't tell whether the implicit way is right.
5422 Even for a mode that is no wider than a const_int,
5423 we can't win, because we need to sign extend one of its bits through
5424 the rest of it, and we don't know which bit. */
5425 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5428 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5429 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5430 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5431 reloaded. If not for that, MEM's would very rarely be safe.
5433 Reject MODEs bigger than a word, because we might not be able
5434 to reference a two-register group starting with an arbitrary register
5435 (and currently gen_lowpart might crash for a SUBREG). */
5437 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5440 /* Reject MODEs that aren't scalar integers because turning vector
5441 or complex modes into shifts causes problems. */
5443 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5446 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5447 /* If the inner object has VOIDmode (the only way this can happen
5448 is if it is an ASM_OPERANDS), we can't do anything since we don't
5449 know how much masking to do. */
5458 /* ... fall through ... */
5461 /* If the operand is a CLOBBER, just return it. */
5462 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5465 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5466 || GET_CODE (XEXP (x, 2)) != CONST_INT
5467 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5470 /* Reject MODEs that aren't scalar integers because turning vector
5471 or complex modes into shifts causes problems. */
5473 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5476 len = INTVAL (XEXP (x, 1));
5477 pos = INTVAL (XEXP (x, 2));
5479 /* If this goes outside the object being extracted, replace the object
5480 with a (use (mem ...)) construct that only combine understands
5481 and is used only for this purpose. */
5482 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5483 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5485 if (BITS_BIG_ENDIAN)
5486 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5493 /* Convert sign extension to zero extension, if we know that the high
5494 bit is not set, as this is easier to optimize. It will be converted
5495 back to cheaper alternative in make_extraction. */
5496 if (GET_CODE (x) == SIGN_EXTEND
5497 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5498 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5499 & ~(((unsigned HOST_WIDE_INT)
5500 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5504 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5505 rtx temp2 = expand_compound_operation (temp);
5507 /* Make sure this is a profitable operation. */
5508 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5510 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5516 /* We can optimize some special cases of ZERO_EXTEND. */
5517 if (GET_CODE (x) == ZERO_EXTEND)
5519 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5520 know that the last value didn't have any inappropriate bits
5522 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5523 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5524 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5525 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5526 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5527 return XEXP (XEXP (x, 0), 0);
5529 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5530 if (GET_CODE (XEXP (x, 0)) == SUBREG
5531 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5532 && subreg_lowpart_p (XEXP (x, 0))
5533 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5534 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5535 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5536 return SUBREG_REG (XEXP (x, 0));
5538 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5539 is a comparison and STORE_FLAG_VALUE permits. This is like
5540 the first case, but it works even when GET_MODE (x) is larger
5541 than HOST_WIDE_INT. */
5542 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5543 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5544 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5545 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5546 <= HOST_BITS_PER_WIDE_INT)
5547 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5548 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5549 return XEXP (XEXP (x, 0), 0);
5551 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5552 if (GET_CODE (XEXP (x, 0)) == SUBREG
5553 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5554 && subreg_lowpart_p (XEXP (x, 0))
5555 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5556 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5557 <= HOST_BITS_PER_WIDE_INT)
5558 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5559 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5560 return SUBREG_REG (XEXP (x, 0));
5564 /* If we reach here, we want to return a pair of shifts. The inner
5565 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5566 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5567 logical depending on the value of UNSIGNEDP.
5569 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5570 converted into an AND of a shift.
5572 We must check for the case where the left shift would have a negative
5573 count. This can happen in a case like (x >> 31) & 255 on machines
5574 that can't shift by a constant. On those machines, we would first
5575 combine the shift with the AND to produce a variable-position
5576 extraction. Then the constant of 31 would be substituted in to produce
5577 a such a position. */
5579 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5580 if (modewidth + len >= pos)
5581 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5583 simplify_shift_const (NULL_RTX, ASHIFT,
5586 modewidth - pos - len),
5589 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5590 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5591 simplify_shift_const (NULL_RTX, LSHIFTRT,
5594 ((HOST_WIDE_INT) 1 << len) - 1);
5596 /* Any other cases we can't handle. */
5599 /* If we couldn't do this for some reason, return the original
5601 if (GET_CODE (tem) == CLOBBER)
5607 /* X is a SET which contains an assignment of one object into
5608 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5609 or certain SUBREGS). If possible, convert it into a series of
5612 We half-heartedly support variable positions, but do not at all
5613 support variable lengths. */
5616 expand_field_assignment (rtx x)
5619 rtx pos; /* Always counts from low bit. */
5621 rtx mask, cleared, masked;
5622 enum machine_mode compute_mode;
5624 /* Loop until we find something we can't simplify. */
5627 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5628 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5630 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5631 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5632 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5634 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5635 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5637 inner = XEXP (SET_DEST (x), 0);
5638 len = INTVAL (XEXP (SET_DEST (x), 1));
5639 pos = XEXP (SET_DEST (x), 2);
5641 /* If the position is constant and spans the width of INNER,
5642 surround INNER with a USE to indicate this. */
5643 if (GET_CODE (pos) == CONST_INT
5644 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5645 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5647 if (BITS_BIG_ENDIAN)
5649 if (GET_CODE (pos) == CONST_INT)
5650 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5652 else if (GET_CODE (pos) == MINUS
5653 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5654 && (INTVAL (XEXP (pos, 1))
5655 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5656 /* If position is ADJUST - X, new position is X. */
5657 pos = XEXP (pos, 0);
5659 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5660 GEN_INT (GET_MODE_BITSIZE (
5667 /* A SUBREG between two modes that occupy the same numbers of words
5668 can be done by moving the SUBREG to the source. */
5669 else if (GET_CODE (SET_DEST (x)) == SUBREG
5670 /* We need SUBREGs to compute nonzero_bits properly. */
5671 && nonzero_sign_valid
5672 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5673 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5674 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5675 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5677 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5679 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5686 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5687 inner = SUBREG_REG (inner);
5689 compute_mode = GET_MODE (inner);
5691 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5692 if (! SCALAR_INT_MODE_P (compute_mode))
5694 enum machine_mode imode;
5696 /* Don't do anything for vector or complex integral types. */
5697 if (! FLOAT_MODE_P (compute_mode))
5700 /* Try to find an integral mode to pun with. */
5701 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5702 if (imode == BLKmode)
5705 compute_mode = imode;
5706 inner = gen_lowpart (imode, inner);
5709 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5710 if (len >= HOST_BITS_PER_WIDE_INT)
5713 /* Now compute the equivalent expression. Make a copy of INNER
5714 for the SET_DEST in case it is a MEM into which we will substitute;
5715 we don't want shared RTL in that case. */
5716 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5717 cleared = simplify_gen_binary (AND, compute_mode,
5718 simplify_gen_unary (NOT, compute_mode,
5719 simplify_gen_binary (ASHIFT,
5724 masked = simplify_gen_binary (ASHIFT, compute_mode,
5725 simplify_gen_binary (
5727 gen_lowpart (compute_mode, SET_SRC (x)),
5731 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5732 simplify_gen_binary (IOR, compute_mode,
5739 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5740 it is an RTX that represents a variable starting position; otherwise,
5741 POS is the (constant) starting bit position (counted from the LSB).
5743 INNER may be a USE. This will occur when we started with a bitfield
5744 that went outside the boundary of the object in memory, which is
5745 allowed on most machines. To isolate this case, we produce a USE
5746 whose mode is wide enough and surround the MEM with it. The only
5747 code that understands the USE is this routine. If it is not removed,
5748 it will cause the resulting insn not to match.
5750 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5753 IN_DEST is nonzero if this is a reference in the destination of a
5754 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5755 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5758 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5759 ZERO_EXTRACT should be built even for bits starting at bit 0.
5761 MODE is the desired mode of the result (if IN_DEST == 0).
5763 The result is an RTX for the extraction or NULL_RTX if the target
5767 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5768 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5769 int in_dest, int in_compare)
5771 /* This mode describes the size of the storage area
5772 to fetch the overall value from. Within that, we
5773 ignore the POS lowest bits, etc. */
5774 enum machine_mode is_mode = GET_MODE (inner);
5775 enum machine_mode inner_mode;
5776 enum machine_mode wanted_inner_mode = byte_mode;
5777 enum machine_mode wanted_inner_reg_mode = word_mode;
5778 enum machine_mode pos_mode = word_mode;
5779 enum machine_mode extraction_mode = word_mode;
5780 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5783 rtx orig_pos_rtx = pos_rtx;
5784 HOST_WIDE_INT orig_pos;
5786 /* Get some information about INNER and get the innermost object. */
5787 if (GET_CODE (inner) == USE)
5788 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5789 /* We don't need to adjust the position because we set up the USE
5790 to pretend that it was a full-word object. */
5791 spans_byte = 1, inner = XEXP (inner, 0);
5792 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5794 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5795 consider just the QI as the memory to extract from.
5796 The subreg adds or removes high bits; its mode is
5797 irrelevant to the meaning of this extraction,
5798 since POS and LEN count from the lsb. */
5799 if (MEM_P (SUBREG_REG (inner)))
5800 is_mode = GET_MODE (SUBREG_REG (inner));
5801 inner = SUBREG_REG (inner);
5803 else if (GET_CODE (inner) == ASHIFT
5804 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5805 && pos_rtx == 0 && pos == 0
5806 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5808 /* We're extracting the least significant bits of an rtx
5809 (ashift X (const_int C)), where LEN > C. Extract the
5810 least significant (LEN - C) bits of X, giving an rtx
5811 whose mode is MODE, then shift it left C times. */
5812 new = make_extraction (mode, XEXP (inner, 0),
5813 0, 0, len - INTVAL (XEXP (inner, 1)),
5814 unsignedp, in_dest, in_compare);
5816 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5819 inner_mode = GET_MODE (inner);
5821 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5822 pos = INTVAL (pos_rtx), pos_rtx = 0;
5824 /* See if this can be done without an extraction. We never can if the
5825 width of the field is not the same as that of some integer mode. For
5826 registers, we can only avoid the extraction if the position is at the
5827 low-order bit and this is either not in the destination or we have the
5828 appropriate STRICT_LOW_PART operation available.
5830 For MEM, we can avoid an extract if the field starts on an appropriate
5831 boundary and we can change the mode of the memory reference. However,
5832 we cannot directly access the MEM if we have a USE and the underlying
5833 MEM is not TMODE. This combination means that MEM was being used in a
5834 context where bits outside its mode were being referenced; that is only
5835 valid in bit-field insns. */
5837 if (tmode != BLKmode
5838 && ! (spans_byte && inner_mode != tmode)
5839 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5843 && have_insn_for (STRICT_LOW_PART, tmode))))
5844 || (MEM_P (inner) && pos_rtx == 0
5846 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5847 : BITS_PER_UNIT)) == 0
5848 /* We can't do this if we are widening INNER_MODE (it
5849 may not be aligned, for one thing). */
5850 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5851 && (inner_mode == tmode
5852 || (! mode_dependent_address_p (XEXP (inner, 0))
5853 && ! MEM_VOLATILE_P (inner))))))
5855 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5856 field. If the original and current mode are the same, we need not
5857 adjust the offset. Otherwise, we do if bytes big endian.
5859 If INNER is not a MEM, get a piece consisting of just the field
5860 of interest (in this case POS % BITS_PER_WORD must be 0). */
5864 HOST_WIDE_INT offset;
5866 /* POS counts from lsb, but make OFFSET count in memory order. */
5867 if (BYTES_BIG_ENDIAN)
5868 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5870 offset = pos / BITS_PER_UNIT;
5872 new = adjust_address_nv (inner, tmode, offset);
5874 else if (REG_P (inner))
5876 if (tmode != inner_mode)
5878 /* We can't call gen_lowpart in a DEST since we
5879 always want a SUBREG (see below) and it would sometimes
5880 return a new hard register. */
5883 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5885 if (WORDS_BIG_ENDIAN
5886 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5887 final_word = ((GET_MODE_SIZE (inner_mode)
5888 - GET_MODE_SIZE (tmode))
5889 / UNITS_PER_WORD) - final_word;
5891 final_word *= UNITS_PER_WORD;
5892 if (BYTES_BIG_ENDIAN &&
5893 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5894 final_word += (GET_MODE_SIZE (inner_mode)
5895 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5897 /* Avoid creating invalid subregs, for example when
5898 simplifying (x>>32)&255. */
5899 if (!validate_subreg (tmode, inner_mode, inner, final_word))
5902 new = gen_rtx_SUBREG (tmode, inner, final_word);
5905 new = gen_lowpart (tmode, inner);
5911 new = force_to_mode (inner, tmode,
5912 len >= HOST_BITS_PER_WIDE_INT
5913 ? ~(unsigned HOST_WIDE_INT) 0
5914 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5917 /* If this extraction is going into the destination of a SET,
5918 make a STRICT_LOW_PART unless we made a MEM. */
5921 return (MEM_P (new) ? new
5922 : (GET_CODE (new) != SUBREG
5923 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5924 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
5929 if (GET_CODE (new) == CONST_INT)
5930 return gen_int_mode (INTVAL (new), mode);
5932 /* If we know that no extraneous bits are set, and that the high
5933 bit is not set, convert the extraction to the cheaper of
5934 sign and zero extension, that are equivalent in these cases. */
5935 if (flag_expensive_optimizations
5936 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5937 && ((nonzero_bits (new, tmode)
5938 & ~(((unsigned HOST_WIDE_INT)
5939 GET_MODE_MASK (tmode))
5943 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5944 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5946 /* Prefer ZERO_EXTENSION, since it gives more information to
5948 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
5953 /* Otherwise, sign- or zero-extend unless we already are in the
5956 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5960 /* Unless this is a COMPARE or we have a funny memory reference,
5961 don't do anything with zero-extending field extracts starting at
5962 the low-order bit since they are simple AND operations. */
5963 if (pos_rtx == 0 && pos == 0 && ! in_dest
5964 && ! in_compare && ! spans_byte && unsignedp)
5967 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5968 we would be spanning bytes or if the position is not a constant and the
5969 length is not 1. In all other cases, we would only be going outside
5970 our object in cases when an original shift would have been
5972 if (! spans_byte && MEM_P (inner)
5973 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5974 || (pos_rtx != 0 && len != 1)))
5977 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5978 and the mode for the result. */
5979 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
5981 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
5982 pos_mode = mode_for_extraction (EP_insv, 2);
5983 extraction_mode = mode_for_extraction (EP_insv, 3);
5986 if (! in_dest && unsignedp
5987 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
5989 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
5990 pos_mode = mode_for_extraction (EP_extzv, 3);
5991 extraction_mode = mode_for_extraction (EP_extzv, 0);
5994 if (! in_dest && ! unsignedp
5995 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
5997 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
5998 pos_mode = mode_for_extraction (EP_extv, 3);
5999 extraction_mode = mode_for_extraction (EP_extv, 0);
6002 /* Never narrow an object, since that might not be safe. */
6004 if (mode != VOIDmode
6005 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6006 extraction_mode = mode;
6008 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6009 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6010 pos_mode = GET_MODE (pos_rtx);
6012 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6013 if we have to change the mode of memory and cannot, the desired mode is
6016 wanted_inner_mode = wanted_inner_reg_mode;
6017 else if (inner_mode != wanted_inner_mode
6018 && (mode_dependent_address_p (XEXP (inner, 0))
6019 || MEM_VOLATILE_P (inner)))
6020 wanted_inner_mode = extraction_mode;
6024 if (BITS_BIG_ENDIAN)
6026 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6027 BITS_BIG_ENDIAN style. If position is constant, compute new
6028 position. Otherwise, build subtraction.
6029 Note that POS is relative to the mode of the original argument.
6030 If it's a MEM we need to recompute POS relative to that.
6031 However, if we're extracting from (or inserting into) a register,
6032 we want to recompute POS relative to wanted_inner_mode. */
6033 int width = (MEM_P (inner)
6034 ? GET_MODE_BITSIZE (is_mode)
6035 : GET_MODE_BITSIZE (wanted_inner_mode));
6038 pos = width - len - pos;
6041 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6042 /* POS may be less than 0 now, but we check for that below.
6043 Note that it can only be less than 0 if !MEM_P (inner). */
6046 /* If INNER has a wider mode, make it smaller. If this is a constant
6047 extract, try to adjust the byte to point to the byte containing
6049 if (wanted_inner_mode != VOIDmode
6050 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6052 && (inner_mode == wanted_inner_mode
6053 || (! mode_dependent_address_p (XEXP (inner, 0))
6054 && ! MEM_VOLATILE_P (inner))))))
6058 /* The computations below will be correct if the machine is big
6059 endian in both bits and bytes or little endian in bits and bytes.
6060 If it is mixed, we must adjust. */
6062 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6063 adjust OFFSET to compensate. */
6064 if (BYTES_BIG_ENDIAN
6066 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6067 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6069 /* If this is a constant position, we can move to the desired byte.
6070 Be careful not to go beyond the original object and maintain the
6071 natural alignment of the memory. */
6074 enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6075 offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6076 pos %= GET_MODE_BITSIZE (bfmode);
6079 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6081 && is_mode != wanted_inner_mode)
6082 offset = (GET_MODE_SIZE (is_mode)
6083 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6085 if (offset != 0 || inner_mode != wanted_inner_mode)
6086 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6089 /* If INNER is not memory, we can always get it into the proper mode. If we
6090 are changing its mode, POS must be a constant and smaller than the size
6092 else if (!MEM_P (inner))
6094 if (GET_MODE (inner) != wanted_inner_mode
6096 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6099 inner = force_to_mode (inner, wanted_inner_mode,
6101 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6102 ? ~(unsigned HOST_WIDE_INT) 0
6103 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6108 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6109 have to zero extend. Otherwise, we can just use a SUBREG. */
6111 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6113 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6115 /* If we know that no extraneous bits are set, and that the high
6116 bit is not set, convert extraction to cheaper one - either
6117 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6119 if (flag_expensive_optimizations
6120 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6121 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6122 & ~(((unsigned HOST_WIDE_INT)
6123 GET_MODE_MASK (GET_MODE (pos_rtx)))
6127 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6129 /* Prefer ZERO_EXTENSION, since it gives more information to
6131 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6136 else if (pos_rtx != 0
6137 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6138 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6140 /* Make POS_RTX unless we already have it and it is correct. If we don't
6141 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6143 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6144 pos_rtx = orig_pos_rtx;
6146 else if (pos_rtx == 0)
6147 pos_rtx = GEN_INT (pos);
6149 /* Make the required operation. See if we can use existing rtx. */
6150 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6151 extraction_mode, inner, GEN_INT (len), pos_rtx);
6153 new = gen_lowpart (mode, new);
6158 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6159 with any other operations in X. Return X without that shift if so. */
6162 extract_left_shift (rtx x, int count)
6164 enum rtx_code code = GET_CODE (x);
6165 enum machine_mode mode = GET_MODE (x);
6171 /* This is the shift itself. If it is wide enough, we will return
6172 either the value being shifted if the shift count is equal to
6173 COUNT or a shift for the difference. */
6174 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6175 && INTVAL (XEXP (x, 1)) >= count)
6176 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6177 INTVAL (XEXP (x, 1)) - count);
6181 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6182 return simplify_gen_unary (code, mode, tem, mode);
6186 case PLUS: case IOR: case XOR: case AND:
6187 /* If we can safely shift this constant and we find the inner shift,
6188 make a new operation. */
6189 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6190 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6191 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6192 return simplify_gen_binary (code, mode, tem,
6193 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6204 /* Look at the expression rooted at X. Look for expressions
6205 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6206 Form these expressions.
6208 Return the new rtx, usually just X.
6210 Also, for machines like the VAX that don't have logical shift insns,
6211 try to convert logical to arithmetic shift operations in cases where
6212 they are equivalent. This undoes the canonicalizations to logical
6213 shifts done elsewhere.
6215 We try, as much as possible, to re-use rtl expressions to save memory.
6217 IN_CODE says what kind of expression we are processing. Normally, it is
6218 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6219 being kludges), it is MEM. When processing the arguments of a comparison
6220 or a COMPARE against zero, it is COMPARE. */
6223 make_compound_operation (rtx x, enum rtx_code in_code)
6225 enum rtx_code code = GET_CODE (x);
6226 enum machine_mode mode = GET_MODE (x);
6227 int mode_width = GET_MODE_BITSIZE (mode);
6229 enum rtx_code next_code;
6235 /* Select the code to be used in recursive calls. Once we are inside an
6236 address, we stay there. If we have a comparison, set to COMPARE,
6237 but once inside, go back to our default of SET. */
6239 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6240 : ((code == COMPARE || COMPARISON_P (x))
6241 && XEXP (x, 1) == const0_rtx) ? COMPARE
6242 : in_code == COMPARE ? SET : in_code);
6244 /* Process depending on the code of this operation. If NEW is set
6245 nonzero, it will be returned. */
6250 /* Convert shifts by constants into multiplications if inside
6252 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6253 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6254 && INTVAL (XEXP (x, 1)) >= 0)
6256 new = make_compound_operation (XEXP (x, 0), next_code);
6257 new = gen_rtx_MULT (mode, new,
6258 GEN_INT ((HOST_WIDE_INT) 1
6259 << INTVAL (XEXP (x, 1))));
6264 /* If the second operand is not a constant, we can't do anything
6266 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6269 /* If the constant is a power of two minus one and the first operand
6270 is a logical right shift, make an extraction. */
6271 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6272 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6274 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6275 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6276 0, in_code == COMPARE);
6279 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6280 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6281 && subreg_lowpart_p (XEXP (x, 0))
6282 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6283 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6285 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6287 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6288 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6289 0, in_code == COMPARE);
6291 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6292 else if ((GET_CODE (XEXP (x, 0)) == XOR
6293 || GET_CODE (XEXP (x, 0)) == IOR)
6294 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6295 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6296 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6298 /* Apply the distributive law, and then try to make extractions. */
6299 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6300 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6302 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6304 new = make_compound_operation (new, in_code);
6307 /* If we are have (and (rotate X C) M) and C is larger than the number
6308 of bits in M, this is an extraction. */
6310 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6311 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6312 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6313 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6315 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6316 new = make_extraction (mode, new,
6317 (GET_MODE_BITSIZE (mode)
6318 - INTVAL (XEXP (XEXP (x, 0), 1))),
6319 NULL_RTX, i, 1, 0, in_code == COMPARE);
6322 /* On machines without logical shifts, if the operand of the AND is
6323 a logical shift and our mask turns off all the propagated sign
6324 bits, we can replace the logical shift with an arithmetic shift. */
6325 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6326 && !have_insn_for (LSHIFTRT, mode)
6327 && have_insn_for (ASHIFTRT, mode)
6328 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6329 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6330 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6331 && mode_width <= HOST_BITS_PER_WIDE_INT)
6333 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6335 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6336 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6338 gen_rtx_ASHIFTRT (mode,
6339 make_compound_operation
6340 (XEXP (XEXP (x, 0), 0), next_code),
6341 XEXP (XEXP (x, 0), 1)));
6344 /* If the constant is one less than a power of two, this might be
6345 representable by an extraction even if no shift is present.
6346 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6347 we are in a COMPARE. */
6348 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6349 new = make_extraction (mode,
6350 make_compound_operation (XEXP (x, 0),
6352 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6354 /* If we are in a comparison and this is an AND with a power of two,
6355 convert this into the appropriate bit extract. */
6356 else if (in_code == COMPARE
6357 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6358 new = make_extraction (mode,
6359 make_compound_operation (XEXP (x, 0),
6361 i, NULL_RTX, 1, 1, 0, 1);
6366 /* If the sign bit is known to be zero, replace this with an
6367 arithmetic shift. */
6368 if (have_insn_for (ASHIFTRT, mode)
6369 && ! have_insn_for (LSHIFTRT, mode)
6370 && mode_width <= HOST_BITS_PER_WIDE_INT
6371 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6373 new = gen_rtx_ASHIFTRT (mode,
6374 make_compound_operation (XEXP (x, 0),
6380 /* ... fall through ... */
6386 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6387 this is a SIGN_EXTRACT. */
6388 if (GET_CODE (rhs) == CONST_INT
6389 && GET_CODE (lhs) == ASHIFT
6390 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6391 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6393 new = make_compound_operation (XEXP (lhs, 0), next_code);
6394 new = make_extraction (mode, new,
6395 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6396 NULL_RTX, mode_width - INTVAL (rhs),
6397 code == LSHIFTRT, 0, in_code == COMPARE);
6401 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6402 If so, try to merge the shifts into a SIGN_EXTEND. We could
6403 also do this for some cases of SIGN_EXTRACT, but it doesn't
6404 seem worth the effort; the case checked for occurs on Alpha. */
6407 && ! (GET_CODE (lhs) == SUBREG
6408 && (OBJECT_P (SUBREG_REG (lhs))))
6409 && GET_CODE (rhs) == CONST_INT
6410 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6411 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6412 new = make_extraction (mode, make_compound_operation (new, next_code),
6413 0, NULL_RTX, mode_width - INTVAL (rhs),
6414 code == LSHIFTRT, 0, in_code == COMPARE);
6419 /* Call ourselves recursively on the inner expression. If we are
6420 narrowing the object and it has a different RTL code from
6421 what it originally did, do this SUBREG as a force_to_mode. */
6423 tem = make_compound_operation (SUBREG_REG (x), in_code);
6427 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6433 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6434 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6435 && subreg_lowpart_p (x))
6437 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6440 /* If we have something other than a SUBREG, we might have
6441 done an expansion, so rerun ourselves. */
6442 if (GET_CODE (newer) != SUBREG)
6443 newer = make_compound_operation (newer, in_code);
6459 x = gen_lowpart (mode, new);
6460 code = GET_CODE (x);
6463 /* Now recursively process each operand of this operation. */
6464 fmt = GET_RTX_FORMAT (code);
6465 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6468 new = make_compound_operation (XEXP (x, i), next_code);
6469 SUBST (XEXP (x, i), new);
6472 /* If this is a commutative operation, the changes to the operands
6473 may have made it noncanonical. */
6474 if (COMMUTATIVE_ARITH_P (x)
6475 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6478 SUBST (XEXP (x, 0), XEXP (x, 1));
6479 SUBST (XEXP (x, 1), tem);
6485 /* Given M see if it is a value that would select a field of bits
6486 within an item, but not the entire word. Return -1 if not.
6487 Otherwise, return the starting position of the field, where 0 is the
6490 *PLEN is set to the length of the field. */
6493 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6495 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6496 int pos = exact_log2 (m & -m);
6500 /* Now shift off the low-order zero bits and see if we have a
6501 power of two minus 1. */
6502 len = exact_log2 ((m >> pos) + 1);
6511 /* If X refers to a register that equals REG in value, replace these
6512 references with REG. */
6514 canon_reg_for_combine (rtx x, rtx reg)
6521 enum rtx_code code = GET_CODE (x);
6522 switch (GET_RTX_CLASS (code))
6525 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6526 if (op0 != XEXP (x, 0))
6527 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6532 case RTX_COMM_ARITH:
6533 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6534 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6535 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6536 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6540 case RTX_COMM_COMPARE:
6541 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6542 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6543 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6544 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6545 GET_MODE (op0), op0, op1);
6549 case RTX_BITFIELD_OPS:
6550 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6551 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6552 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6553 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6554 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6555 GET_MODE (op0), op0, op1, op2);
6560 if (rtx_equal_p (get_last_value (reg), x)
6561 || rtx_equal_p (reg, get_last_value (x)))
6570 fmt = GET_RTX_FORMAT (code);
6572 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6575 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6576 if (op != XEXP (x, i))
6586 else if (fmt[i] == 'E')
6589 for (j = 0; j < XVECLEN (x, i); j++)
6591 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6592 if (op != XVECEXP (x, i, j))
6599 XVECEXP (x, i, j) = op;
6610 /* See if X can be simplified knowing that we will only refer to it in
6611 MODE and will only refer to those bits that are nonzero in MASK.
6612 If other bits are being computed or if masking operations are done
6613 that select a superset of the bits in MASK, they can sometimes be
6616 Return a possibly simplified expression, but always convert X to
6617 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6619 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6620 are all off in X. This is used when X will be complemented, by either
6621 NOT, NEG, or XOR. */
6624 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6627 enum rtx_code code = GET_CODE (x);
6628 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6629 enum machine_mode op_mode;
6630 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6633 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6634 code below will do the wrong thing since the mode of such an
6635 expression is VOIDmode.
6637 Also do nothing if X is a CLOBBER; this can happen if X was
6638 the return value from a call to gen_lowpart. */
6639 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6642 /* We want to perform the operation is its present mode unless we know
6643 that the operation is valid in MODE, in which case we do the operation
6645 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6646 && have_insn_for (code, mode))
6647 ? mode : GET_MODE (x));
6649 /* It is not valid to do a right-shift in a narrower mode
6650 than the one it came in with. */
6651 if ((code == LSHIFTRT || code == ASHIFTRT)
6652 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6653 op_mode = GET_MODE (x);
6655 /* Truncate MASK to fit OP_MODE. */
6657 mask &= GET_MODE_MASK (op_mode);
6659 /* When we have an arithmetic operation, or a shift whose count we
6660 do not know, we need to assume that all bits up to the highest-order
6661 bit in MASK will be needed. This is how we form such a mask. */
6662 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6663 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6665 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6668 /* Determine what bits of X are guaranteed to be (non)zero. */
6669 nonzero = nonzero_bits (x, mode);
6671 /* If none of the bits in X are needed, return a zero. */
6672 if (! just_select && (nonzero & mask) == 0)
6675 /* If X is a CONST_INT, return a new one. Do this here since the
6676 test below will fail. */
6677 if (GET_CODE (x) == CONST_INT)
6679 if (SCALAR_INT_MODE_P (mode))
6680 return gen_int_mode (INTVAL (x) & mask, mode);
6683 x = GEN_INT (INTVAL (x) & mask);
6684 return gen_lowpart_common (mode, x);
6688 /* If X is narrower than MODE and we want all the bits in X's mode, just
6689 get X in the proper mode. */
6690 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6691 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6692 return gen_lowpart (mode, x);
6697 /* If X is a (clobber (const_int)), return it since we know we are
6698 generating something that won't match. */
6702 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6703 spanned the boundary of the MEM. If we are now masking so it is
6704 within that boundary, we don't need the USE any more. */
6705 if (! BITS_BIG_ENDIAN
6706 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6707 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6714 x = expand_compound_operation (x);
6715 if (GET_CODE (x) != code)
6716 return force_to_mode (x, mode, mask, next_select);
6720 if (subreg_lowpart_p (x)
6721 /* We can ignore the effect of this SUBREG if it narrows the mode or
6722 if the constant masks to zero all the bits the mode doesn't
6724 && ((GET_MODE_SIZE (GET_MODE (x))
6725 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6727 & GET_MODE_MASK (GET_MODE (x))
6728 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6729 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6733 /* If this is an AND with a constant, convert it into an AND
6734 whose constant is the AND of that constant with MASK. If it
6735 remains an AND of MASK, delete it since it is redundant. */
6737 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6739 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6740 mask & INTVAL (XEXP (x, 1)));
6742 /* If X is still an AND, see if it is an AND with a mask that
6743 is just some low-order bits. If so, and it is MASK, we don't
6746 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6747 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6751 /* If it remains an AND, try making another AND with the bits
6752 in the mode mask that aren't in MASK turned on. If the
6753 constant in the AND is wide enough, this might make a
6754 cheaper constant. */
6756 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6757 && GET_MODE_MASK (GET_MODE (x)) != mask
6758 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6760 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6761 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6762 int width = GET_MODE_BITSIZE (GET_MODE (x));
6765 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6766 number, sign extend it. */
6767 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6768 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6769 cval |= (HOST_WIDE_INT) -1 << width;
6771 y = simplify_gen_binary (AND, GET_MODE (x),
6772 XEXP (x, 0), GEN_INT (cval));
6773 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6783 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6784 low-order bits (as in an alignment operation) and FOO is already
6785 aligned to that boundary, mask C1 to that boundary as well.
6786 This may eliminate that PLUS and, later, the AND. */
6789 unsigned int width = GET_MODE_BITSIZE (mode);
6790 unsigned HOST_WIDE_INT smask = mask;
6792 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6793 number, sign extend it. */
6795 if (width < HOST_BITS_PER_WIDE_INT
6796 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6797 smask |= (HOST_WIDE_INT) -1 << width;
6799 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6800 && exact_log2 (- smask) >= 0
6801 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6802 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6803 return force_to_mode (plus_constant (XEXP (x, 0),
6804 (INTVAL (XEXP (x, 1)) & smask)),
6805 mode, smask, next_select);
6808 /* ... fall through ... */
6811 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6812 most significant bit in MASK since carries from those bits will
6813 affect the bits we are interested in. */
6818 /* If X is (minus C Y) where C's least set bit is larger than any bit
6819 in the mask, then we may replace with (neg Y). */
6820 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6821 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6822 & -INTVAL (XEXP (x, 0))))
6825 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6827 return force_to_mode (x, mode, mask, next_select);
6830 /* Similarly, if C contains every bit in the fuller_mask, then we may
6831 replace with (not Y). */
6832 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6833 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6834 == INTVAL (XEXP (x, 0))))
6836 x = simplify_gen_unary (NOT, GET_MODE (x),
6837 XEXP (x, 1), GET_MODE (x));
6838 return force_to_mode (x, mode, mask, next_select);
6846 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6847 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6848 operation which may be a bitfield extraction. Ensure that the
6849 constant we form is not wider than the mode of X. */
6851 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6852 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6853 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6854 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6855 && GET_CODE (XEXP (x, 1)) == CONST_INT
6856 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6857 + floor_log2 (INTVAL (XEXP (x, 1))))
6858 < GET_MODE_BITSIZE (GET_MODE (x)))
6859 && (INTVAL (XEXP (x, 1))
6860 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6862 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6863 << INTVAL (XEXP (XEXP (x, 0), 1)));
6864 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
6865 XEXP (XEXP (x, 0), 0), temp);
6866 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
6867 XEXP (XEXP (x, 0), 1));
6868 return force_to_mode (x, mode, mask, next_select);
6872 /* For most binary operations, just propagate into the operation and
6873 change the mode if we have an operation of that mode. */
6875 op0 = gen_lowpart (op_mode,
6876 force_to_mode (XEXP (x, 0), mode, mask,
6878 op1 = gen_lowpart (op_mode,
6879 force_to_mode (XEXP (x, 1), mode, mask,
6882 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6883 x = simplify_gen_binary (code, op_mode, op0, op1);
6887 /* For left shifts, do the same, but just for the first operand.
6888 However, we cannot do anything with shifts where we cannot
6889 guarantee that the counts are smaller than the size of the mode
6890 because such a count will have a different meaning in a
6893 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6894 && INTVAL (XEXP (x, 1)) >= 0
6895 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6896 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6897 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6898 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6901 /* If the shift count is a constant and we can do arithmetic in
6902 the mode of the shift, refine which bits we need. Otherwise, use the
6903 conservative form of the mask. */
6904 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6905 && INTVAL (XEXP (x, 1)) >= 0
6906 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6907 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6908 mask >>= INTVAL (XEXP (x, 1));
6912 op0 = gen_lowpart (op_mode,
6913 force_to_mode (XEXP (x, 0), op_mode,
6914 mask, next_select));
6916 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6917 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
6921 /* Here we can only do something if the shift count is a constant,
6922 this shift constant is valid for the host, and we can do arithmetic
6925 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6926 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6927 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6929 rtx inner = XEXP (x, 0);
6930 unsigned HOST_WIDE_INT inner_mask;
6932 /* Select the mask of the bits we need for the shift operand. */
6933 inner_mask = mask << INTVAL (XEXP (x, 1));
6935 /* We can only change the mode of the shift if we can do arithmetic
6936 in the mode of the shift and INNER_MASK is no wider than the
6937 width of X's mode. */
6938 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
6939 op_mode = GET_MODE (x);
6941 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
6943 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6944 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6947 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6948 shift and AND produces only copies of the sign bit (C2 is one less
6949 than a power of two), we can do this with just a shift. */
6951 if (GET_CODE (x) == LSHIFTRT
6952 && GET_CODE (XEXP (x, 1)) == CONST_INT
6953 /* The shift puts one of the sign bit copies in the least significant
6955 && ((INTVAL (XEXP (x, 1))
6956 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6957 >= GET_MODE_BITSIZE (GET_MODE (x)))
6958 && exact_log2 (mask + 1) >= 0
6959 /* Number of bits left after the shift must be more than the mask
6961 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6962 <= GET_MODE_BITSIZE (GET_MODE (x)))
6963 /* Must be more sign bit copies than the mask needs. */
6964 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6965 >= exact_log2 (mask + 1)))
6966 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6967 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6968 - exact_log2 (mask + 1)));
6973 /* If we are just looking for the sign bit, we don't need this shift at
6974 all, even if it has a variable count. */
6975 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6976 && (mask == ((unsigned HOST_WIDE_INT) 1
6977 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6978 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6980 /* If this is a shift by a constant, get a mask that contains those bits
6981 that are not copies of the sign bit. We then have two cases: If
6982 MASK only includes those bits, this can be a logical shift, which may
6983 allow simplifications. If MASK is a single-bit field not within
6984 those bits, we are requesting a copy of the sign bit and hence can
6985 shift the sign bit to the appropriate location. */
6987 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6988 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6992 /* If the considered data is wider than HOST_WIDE_INT, we can't
6993 represent a mask for all its bits in a single scalar.
6994 But we only care about the lower bits, so calculate these. */
6996 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6998 nonzero = ~(HOST_WIDE_INT) 0;
7000 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7001 is the number of bits a full-width mask would have set.
7002 We need only shift if these are fewer than nonzero can
7003 hold. If not, we must keep all bits set in nonzero. */
7005 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7006 < HOST_BITS_PER_WIDE_INT)
7007 nonzero >>= INTVAL (XEXP (x, 1))
7008 + HOST_BITS_PER_WIDE_INT
7009 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7013 nonzero = GET_MODE_MASK (GET_MODE (x));
7014 nonzero >>= INTVAL (XEXP (x, 1));
7017 if ((mask & ~nonzero) == 0)
7019 x = simplify_shift_const (x, LSHIFTRT, GET_MODE (x),
7020 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7021 if (GET_CODE (x) != ASHIFTRT)
7022 return force_to_mode (x, mode, mask, next_select);
7025 else if ((i = exact_log2 (mask)) >= 0)
7027 x = simplify_shift_const
7028 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7029 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7031 if (GET_CODE (x) != ASHIFTRT)
7032 return force_to_mode (x, mode, mask, next_select);
7036 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7037 even if the shift count isn't a constant. */
7039 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7040 XEXP (x, 0), XEXP (x, 1));
7044 /* If this is a zero- or sign-extension operation that just affects bits
7045 we don't care about, remove it. Be sure the call above returned
7046 something that is still a shift. */
7048 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7049 && GET_CODE (XEXP (x, 1)) == CONST_INT
7050 && INTVAL (XEXP (x, 1)) >= 0
7051 && (INTVAL (XEXP (x, 1))
7052 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7053 && GET_CODE (XEXP (x, 0)) == ASHIFT
7054 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7055 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7062 /* If the shift count is constant and we can do computations
7063 in the mode of X, compute where the bits we care about are.
7064 Otherwise, we can't do anything. Don't change the mode of
7065 the shift or propagate MODE into the shift, though. */
7066 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7067 && INTVAL (XEXP (x, 1)) >= 0)
7069 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7070 GET_MODE (x), GEN_INT (mask),
7072 if (temp && GET_CODE (temp) == CONST_INT)
7074 force_to_mode (XEXP (x, 0), GET_MODE (x),
7075 INTVAL (temp), next_select));
7080 /* If we just want the low-order bit, the NEG isn't needed since it
7081 won't change the low-order bit. */
7083 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7085 /* We need any bits less significant than the most significant bit in
7086 MASK since carries from those bits will affect the bits we are
7092 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7093 same as the XOR case above. Ensure that the constant we form is not
7094 wider than the mode of X. */
7096 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7097 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7098 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7099 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7100 < GET_MODE_BITSIZE (GET_MODE (x)))
7101 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7103 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7105 temp = simplify_gen_binary (XOR, GET_MODE (x),
7106 XEXP (XEXP (x, 0), 0), temp);
7107 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7108 temp, XEXP (XEXP (x, 0), 1));
7110 return force_to_mode (x, mode, mask, next_select);
7113 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7114 use the full mask inside the NOT. */
7118 op0 = gen_lowpart (op_mode,
7119 force_to_mode (XEXP (x, 0), mode, mask,
7121 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7122 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7126 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7127 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7128 which is equal to STORE_FLAG_VALUE. */
7129 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7130 && GET_MODE (XEXP (x, 0)) == mode
7131 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7132 && (nonzero_bits (XEXP (x, 0), mode)
7133 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7134 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7139 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7140 written in a narrower mode. We play it safe and do not do so. */
7143 gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 1), mode,
7144 mask, next_select)));
7146 gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 2), mode,
7147 mask, next_select)));
7154 /* Ensure we return a value of the proper mode. */
7155 return gen_lowpart (mode, x);
7158 /* Return nonzero if X is an expression that has one of two values depending on
7159 whether some other value is zero or nonzero. In that case, we return the
7160 value that is being tested, *PTRUE is set to the value if the rtx being
7161 returned has a nonzero value, and *PFALSE is set to the other alternative.
7163 If we return zero, we set *PTRUE and *PFALSE to X. */
7166 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7168 enum machine_mode mode = GET_MODE (x);
7169 enum rtx_code code = GET_CODE (x);
7170 rtx cond0, cond1, true0, true1, false0, false1;
7171 unsigned HOST_WIDE_INT nz;
7173 /* If we are comparing a value against zero, we are done. */
7174 if ((code == NE || code == EQ)
7175 && XEXP (x, 1) == const0_rtx)
7177 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7178 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7182 /* If this is a unary operation whose operand has one of two values, apply
7183 our opcode to compute those values. */
7184 else if (UNARY_P (x)
7185 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7187 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7188 *pfalse = simplify_gen_unary (code, mode, false0,
7189 GET_MODE (XEXP (x, 0)));
7193 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7194 make can't possibly match and would suppress other optimizations. */
7195 else if (code == COMPARE)
7198 /* If this is a binary operation, see if either side has only one of two
7199 values. If either one does or if both do and they are conditional on
7200 the same value, compute the new true and false values. */
7201 else if (BINARY_P (x))
7203 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7204 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7206 if ((cond0 != 0 || cond1 != 0)
7207 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7209 /* If if_then_else_cond returned zero, then true/false are the
7210 same rtl. We must copy one of them to prevent invalid rtl
7213 true0 = copy_rtx (true0);
7214 else if (cond1 == 0)
7215 true1 = copy_rtx (true1);
7217 if (COMPARISON_P (x))
7219 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7221 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7226 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7227 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7230 return cond0 ? cond0 : cond1;
7233 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7234 operands is zero when the other is nonzero, and vice-versa,
7235 and STORE_FLAG_VALUE is 1 or -1. */
7237 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7238 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7240 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7242 rtx op0 = XEXP (XEXP (x, 0), 1);
7243 rtx op1 = XEXP (XEXP (x, 1), 1);
7245 cond0 = XEXP (XEXP (x, 0), 0);
7246 cond1 = XEXP (XEXP (x, 1), 0);
7248 if (COMPARISON_P (cond0)
7249 && COMPARISON_P (cond1)
7250 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7251 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7252 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7253 || ((swap_condition (GET_CODE (cond0))
7254 == reversed_comparison_code (cond1, NULL))
7255 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7256 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7257 && ! side_effects_p (x))
7259 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7260 *pfalse = simplify_gen_binary (MULT, mode,
7262 ? simplify_gen_unary (NEG, mode,
7270 /* Similarly for MULT, AND and UMIN, except that for these the result
7272 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7273 && (code == MULT || code == AND || code == UMIN)
7274 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7276 cond0 = XEXP (XEXP (x, 0), 0);
7277 cond1 = XEXP (XEXP (x, 1), 0);
7279 if (COMPARISON_P (cond0)
7280 && COMPARISON_P (cond1)
7281 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7282 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7283 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7284 || ((swap_condition (GET_CODE (cond0))
7285 == reversed_comparison_code (cond1, NULL))
7286 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7287 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7288 && ! side_effects_p (x))
7290 *ptrue = *pfalse = const0_rtx;
7296 else if (code == IF_THEN_ELSE)
7298 /* If we have IF_THEN_ELSE already, extract the condition and
7299 canonicalize it if it is NE or EQ. */
7300 cond0 = XEXP (x, 0);
7301 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7302 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7303 return XEXP (cond0, 0);
7304 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7306 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7307 return XEXP (cond0, 0);
7313 /* If X is a SUBREG, we can narrow both the true and false values
7314 if the inner expression, if there is a condition. */
7315 else if (code == SUBREG
7316 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7319 true0 = simplify_gen_subreg (mode, true0,
7320 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7321 false0 = simplify_gen_subreg (mode, false0,
7322 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7323 if (true0 && false0)
7331 /* If X is a constant, this isn't special and will cause confusions
7332 if we treat it as such. Likewise if it is equivalent to a constant. */
7333 else if (CONSTANT_P (x)
7334 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7337 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7338 will be least confusing to the rest of the compiler. */
7339 else if (mode == BImode)
7341 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7345 /* If X is known to be either 0 or -1, those are the true and
7346 false values when testing X. */
7347 else if (x == constm1_rtx || x == const0_rtx
7348 || (mode != VOIDmode
7349 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7351 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7355 /* Likewise for 0 or a single bit. */
7356 else if (SCALAR_INT_MODE_P (mode)
7357 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7358 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7360 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7364 /* Otherwise fail; show no condition with true and false values the same. */
7365 *ptrue = *pfalse = x;
7369 /* Return the value of expression X given the fact that condition COND
7370 is known to be true when applied to REG as its first operand and VAL
7371 as its second. X is known to not be shared and so can be modified in
7374 We only handle the simplest cases, and specifically those cases that
7375 arise with IF_THEN_ELSE expressions. */
7378 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7380 enum rtx_code code = GET_CODE (x);
7385 if (side_effects_p (x))
7388 /* If either operand of the condition is a floating point value,
7389 then we have to avoid collapsing an EQ comparison. */
7391 && rtx_equal_p (x, reg)
7392 && ! FLOAT_MODE_P (GET_MODE (x))
7393 && ! FLOAT_MODE_P (GET_MODE (val)))
7396 if (cond == UNEQ && rtx_equal_p (x, reg))
7399 /* If X is (abs REG) and we know something about REG's relationship
7400 with zero, we may be able to simplify this. */
7402 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7405 case GE: case GT: case EQ:
7408 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7410 GET_MODE (XEXP (x, 0)));
7415 /* The only other cases we handle are MIN, MAX, and comparisons if the
7416 operands are the same as REG and VAL. */
7418 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7420 if (rtx_equal_p (XEXP (x, 0), val))
7421 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7423 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7425 if (COMPARISON_P (x))
7427 if (comparison_dominates_p (cond, code))
7428 return const_true_rtx;
7430 code = reversed_comparison_code (x, NULL);
7432 && comparison_dominates_p (cond, code))
7437 else if (code == SMAX || code == SMIN
7438 || code == UMIN || code == UMAX)
7440 int unsignedp = (code == UMIN || code == UMAX);
7442 /* Do not reverse the condition when it is NE or EQ.
7443 This is because we cannot conclude anything about
7444 the value of 'SMAX (x, y)' when x is not equal to y,
7445 but we can when x equals y. */
7446 if ((code == SMAX || code == UMAX)
7447 && ! (cond == EQ || cond == NE))
7448 cond = reverse_condition (cond);
7453 return unsignedp ? x : XEXP (x, 1);
7455 return unsignedp ? x : XEXP (x, 0);
7457 return unsignedp ? XEXP (x, 1) : x;
7459 return unsignedp ? XEXP (x, 0) : x;
7466 else if (code == SUBREG)
7468 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7469 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7471 if (SUBREG_REG (x) != r)
7473 /* We must simplify subreg here, before we lose track of the
7474 original inner_mode. */
7475 new = simplify_subreg (GET_MODE (x), r,
7476 inner_mode, SUBREG_BYTE (x));
7480 SUBST (SUBREG_REG (x), r);
7485 /* We don't have to handle SIGN_EXTEND here, because even in the
7486 case of replacing something with a modeless CONST_INT, a
7487 CONST_INT is already (supposed to be) a valid sign extension for
7488 its narrower mode, which implies it's already properly
7489 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7490 story is different. */
7491 else if (code == ZERO_EXTEND)
7493 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7494 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7496 if (XEXP (x, 0) != r)
7498 /* We must simplify the zero_extend here, before we lose
7499 track of the original inner_mode. */
7500 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7505 SUBST (XEXP (x, 0), r);
7511 fmt = GET_RTX_FORMAT (code);
7512 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7515 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7516 else if (fmt[i] == 'E')
7517 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7518 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7525 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7526 assignment as a field assignment. */
7529 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7531 if (x == y || rtx_equal_p (x, y))
7534 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7537 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7538 Note that all SUBREGs of MEM are paradoxical; otherwise they
7539 would have been rewritten. */
7540 if (MEM_P (x) && GET_CODE (y) == SUBREG
7541 && MEM_P (SUBREG_REG (y))
7542 && rtx_equal_p (SUBREG_REG (y),
7543 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7546 if (MEM_P (y) && GET_CODE (x) == SUBREG
7547 && MEM_P (SUBREG_REG (x))
7548 && rtx_equal_p (SUBREG_REG (x),
7549 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7552 /* We used to see if get_last_value of X and Y were the same but that's
7553 not correct. In one direction, we'll cause the assignment to have
7554 the wrong destination and in the case, we'll import a register into this
7555 insn that might have already have been dead. So fail if none of the
7556 above cases are true. */
7560 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7561 Return that assignment if so.
7563 We only handle the most common cases. */
7566 make_field_assignment (rtx x)
7568 rtx dest = SET_DEST (x);
7569 rtx src = SET_SRC (x);
7574 unsigned HOST_WIDE_INT len;
7576 enum machine_mode mode;
7578 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7579 a clear of a one-bit field. We will have changed it to
7580 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7583 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7584 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7585 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7586 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7588 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7591 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7595 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7596 && subreg_lowpart_p (XEXP (src, 0))
7597 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7598 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7599 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7600 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7601 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7602 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7604 assign = make_extraction (VOIDmode, dest, 0,
7605 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7608 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7612 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7614 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7615 && XEXP (XEXP (src, 0), 0) == const1_rtx
7616 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7618 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7621 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7625 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7626 SRC is an AND with all bits of that field set, then we can discard
7628 if (GET_CODE (dest) == ZERO_EXTRACT
7629 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7630 && GET_CODE (src) == AND
7631 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7633 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7634 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7635 unsigned HOST_WIDE_INT ze_mask;
7637 if (width >= HOST_BITS_PER_WIDE_INT)
7640 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7642 /* Complete overlap. We can remove the source AND. */
7643 if ((and_mask & ze_mask) == ze_mask)
7644 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7646 /* Partial overlap. We can reduce the source AND. */
7647 if ((and_mask & ze_mask) != and_mask)
7649 mode = GET_MODE (src);
7650 src = gen_rtx_AND (mode, XEXP (src, 0),
7651 gen_int_mode (and_mask & ze_mask, mode));
7652 return gen_rtx_SET (VOIDmode, dest, src);
7656 /* The other case we handle is assignments into a constant-position
7657 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7658 a mask that has all one bits except for a group of zero bits and
7659 OTHER is known to have zeros where C1 has ones, this is such an
7660 assignment. Compute the position and length from C1. Shift OTHER
7661 to the appropriate position, force it to the required mode, and
7662 make the extraction. Check for the AND in both operands. */
7664 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7667 rhs = expand_compound_operation (XEXP (src, 0));
7668 lhs = expand_compound_operation (XEXP (src, 1));
7670 if (GET_CODE (rhs) == AND
7671 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7672 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7673 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7674 else if (GET_CODE (lhs) == AND
7675 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7676 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7677 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7681 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7682 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7683 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7684 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7687 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7691 /* The mode to use for the source is the mode of the assignment, or of
7692 what is inside a possible STRICT_LOW_PART. */
7693 mode = (GET_CODE (assign) == STRICT_LOW_PART
7694 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7696 /* Shift OTHER right POS places and make it the source, restricting it
7697 to the proper length and mode. */
7699 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7703 src = force_to_mode (src, mode,
7704 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7705 ? ~(unsigned HOST_WIDE_INT) 0
7706 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7709 /* If SRC is masked by an AND that does not make a difference in
7710 the value being stored, strip it. */
7711 if (GET_CODE (assign) == ZERO_EXTRACT
7712 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7713 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7714 && GET_CODE (src) == AND
7715 && GET_CODE (XEXP (src, 1)) == CONST_INT
7716 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7717 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7718 src = XEXP (src, 0);
7720 return gen_rtx_SET (VOIDmode, assign, src);
7723 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7727 apply_distributive_law (rtx x)
7729 enum rtx_code code = GET_CODE (x);
7730 enum rtx_code inner_code;
7731 rtx lhs, rhs, other;
7734 /* Distributivity is not true for floating point as it can change the
7735 value. So we don't do it unless -funsafe-math-optimizations. */
7736 if (FLOAT_MODE_P (GET_MODE (x))
7737 && ! flag_unsafe_math_optimizations)
7740 /* The outer operation can only be one of the following: */
7741 if (code != IOR && code != AND && code != XOR
7742 && code != PLUS && code != MINUS)
7748 /* If either operand is a primitive we can't do anything, so get out
7750 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7753 lhs = expand_compound_operation (lhs);
7754 rhs = expand_compound_operation (rhs);
7755 inner_code = GET_CODE (lhs);
7756 if (inner_code != GET_CODE (rhs))
7759 /* See if the inner and outer operations distribute. */
7766 /* These all distribute except over PLUS. */
7767 if (code == PLUS || code == MINUS)
7772 if (code != PLUS && code != MINUS)
7777 /* This is also a multiply, so it distributes over everything. */
7781 /* Non-paradoxical SUBREGs distributes over all operations,
7782 provided the inner modes and byte offsets are the same, this
7783 is an extraction of a low-order part, we don't convert an fp
7784 operation to int or vice versa, this is not a vector mode,
7785 and we would not be converting a single-word operation into a
7786 multi-word operation. The latter test is not required, but
7787 it prevents generating unneeded multi-word operations. Some
7788 of the previous tests are redundant given the latter test,
7789 but are retained because they are required for correctness.
7791 We produce the result slightly differently in this case. */
7793 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7794 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7795 || ! subreg_lowpart_p (lhs)
7796 || (GET_MODE_CLASS (GET_MODE (lhs))
7797 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7798 || (GET_MODE_SIZE (GET_MODE (lhs))
7799 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7800 || VECTOR_MODE_P (GET_MODE (lhs))
7801 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7804 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7805 SUBREG_REG (lhs), SUBREG_REG (rhs));
7806 return gen_lowpart (GET_MODE (x), tem);
7812 /* Set LHS and RHS to the inner operands (A and B in the example
7813 above) and set OTHER to the common operand (C in the example).
7814 There is only one way to do this unless the inner operation is
7816 if (COMMUTATIVE_ARITH_P (lhs)
7817 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7818 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7819 else if (COMMUTATIVE_ARITH_P (lhs)
7820 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7821 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7822 else if (COMMUTATIVE_ARITH_P (lhs)
7823 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7824 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7825 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7826 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7830 /* Form the new inner operation, seeing if it simplifies first. */
7831 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
7833 /* There is one exception to the general way of distributing:
7834 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7835 if (code == XOR && inner_code == IOR)
7838 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7841 /* We may be able to continuing distributing the result, so call
7842 ourselves recursively on the inner operation before forming the
7843 outer operation, which we return. */
7844 return simplify_gen_binary (inner_code, GET_MODE (x),
7845 apply_distributive_law (tem), other);
7848 /* See if X is of the form (* (+ A B) C), and if so convert to
7849 (+ (* A C) (* B C)) and try to simplify.
7851 Most of the time, this results in no change. However, if some of
7852 the operands are the same or inverses of each other, simplifications
7855 For example, (and (ior A B) (not B)) can occur as the result of
7856 expanding a bit field assignment. When we apply the distributive
7857 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
7858 which then simplifies to (and (A (not B))).
7860 Note that no checks happen on the validity of applying the inverse
7861 distributive law. This is pointless since we can do it in the
7862 few places where this routine is called.
7864 N is the index of the term that is decomposed (the arithmetic operation,
7865 i.e. (+ A B) in the first example above). !N is the index of the term that
7866 is distributed, i.e. of C in the first example above. */
7868 distribute_and_simplify_rtx (rtx x, int n)
7870 enum machine_mode mode;
7871 enum rtx_code outer_code, inner_code;
7872 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
7874 decomposed = XEXP (x, n);
7875 if (!ARITHMETIC_P (decomposed))
7878 mode = GET_MODE (x);
7879 outer_code = GET_CODE (x);
7880 distributed = XEXP (x, !n);
7882 inner_code = GET_CODE (decomposed);
7883 inner_op0 = XEXP (decomposed, 0);
7884 inner_op1 = XEXP (decomposed, 1);
7886 /* Special case (and (xor B C) (not A)), which is equivalent to
7887 (xor (ior A B) (ior A C)) */
7888 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
7890 distributed = XEXP (distributed, 0);
7896 /* Distribute the second term. */
7897 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
7898 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
7902 /* Distribute the first term. */
7903 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
7904 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
7907 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
7909 if (GET_CODE (tmp) != outer_code
7910 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
7916 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
7917 in MODE. Return an equivalent form, if different from (and VAROP
7918 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
7921 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
7922 unsigned HOST_WIDE_INT constop)
7924 unsigned HOST_WIDE_INT nonzero;
7925 unsigned HOST_WIDE_INT orig_constop;
7930 orig_constop = constop;
7931 if (GET_CODE (varop) == CLOBBER)
7934 /* Simplify VAROP knowing that we will be only looking at some of the
7937 Note by passing in CONSTOP, we guarantee that the bits not set in
7938 CONSTOP are not significant and will never be examined. We must
7939 ensure that is the case by explicitly masking out those bits
7940 before returning. */
7941 varop = force_to_mode (varop, mode, constop, 0);
7943 /* If VAROP is a CLOBBER, we will fail so return it. */
7944 if (GET_CODE (varop) == CLOBBER)
7947 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7948 to VAROP and return the new constant. */
7949 if (GET_CODE (varop) == CONST_INT)
7950 return gen_int_mode (INTVAL (varop) & constop, mode);
7952 /* See what bits may be nonzero in VAROP. Unlike the general case of
7953 a call to nonzero_bits, here we don't care about bits outside
7956 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7958 /* Turn off all bits in the constant that are known to already be zero.
7959 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7960 which is tested below. */
7964 /* If we don't have any bits left, return zero. */
7968 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7969 a power of two, we can replace this with an ASHIFT. */
7970 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7971 && (i = exact_log2 (constop)) >= 0)
7972 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7974 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7975 or XOR, then try to apply the distributive law. This may eliminate
7976 operations if either branch can be simplified because of the AND.
7977 It may also make some cases more complex, but those cases probably
7978 won't match a pattern either with or without this. */
7980 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7984 apply_distributive_law
7985 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
7986 simplify_and_const_int (NULL_RTX,
7990 simplify_and_const_int (NULL_RTX,
7995 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
7996 the AND and see if one of the operands simplifies to zero. If so, we
7997 may eliminate it. */
7999 if (GET_CODE (varop) == PLUS
8000 && exact_log2 (constop + 1) >= 0)
8004 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8005 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8006 if (o0 == const0_rtx)
8008 if (o1 == const0_rtx)
8012 /* Make a SUBREG if necessary. If we can't make it, fail. */
8013 varop = gen_lowpart (mode, varop);
8014 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8017 /* If we are only masking insignificant bits, return VAROP. */
8018 if (constop == nonzero)
8021 if (varop == orig_varop && constop == orig_constop)
8024 /* Otherwise, return an AND. */
8025 constop = trunc_int_for_mode (constop, mode);
8026 return simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8030 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8033 Return an equivalent form, if different from X. Otherwise, return X. If
8034 X is zero, we are to always construct the equivalent form. */
8037 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8038 unsigned HOST_WIDE_INT constop)
8040 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8045 x = simplify_gen_binary (AND, GET_MODE (varop), varop, GEN_INT (constop));
8046 if (GET_MODE (x) != mode)
8047 x = gen_lowpart (mode, x);
8051 /* Given a REG, X, compute which bits in X can be nonzero.
8052 We don't care about bits outside of those defined in MODE.
8054 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8055 a shift, AND, or zero_extract, we can do better. */
8058 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8059 rtx known_x ATTRIBUTE_UNUSED,
8060 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8061 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8062 unsigned HOST_WIDE_INT *nonzero)
8066 /* If X is a register whose nonzero bits value is current, use it.
8067 Otherwise, if X is a register whose value we can find, use that
8068 value. Otherwise, use the previously-computed global nonzero bits
8069 for this register. */
8071 if (reg_stat[REGNO (x)].last_set_value != 0
8072 && (reg_stat[REGNO (x)].last_set_mode == mode
8073 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8074 && GET_MODE_CLASS (mode) == MODE_INT))
8075 && (reg_stat[REGNO (x)].last_set_label == label_tick
8076 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8077 && REG_N_SETS (REGNO (x)) == 1
8078 && ! REGNO_REG_SET_P
8079 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8081 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8083 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8087 tem = get_last_value (x);
8091 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8092 /* If X is narrower than MODE and TEM is a non-negative
8093 constant that would appear negative in the mode of X,
8094 sign-extend it for use in reg_nonzero_bits because some
8095 machines (maybe most) will actually do the sign-extension
8096 and this is the conservative approach.
8098 ??? For 2.5, try to tighten up the MD files in this regard
8099 instead of this kludge. */
8101 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8102 && GET_CODE (tem) == CONST_INT
8104 && 0 != (INTVAL (tem)
8105 & ((HOST_WIDE_INT) 1
8106 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8107 tem = GEN_INT (INTVAL (tem)
8108 | ((HOST_WIDE_INT) (-1)
8109 << GET_MODE_BITSIZE (GET_MODE (x))));
8113 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8115 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8117 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8118 /* We don't know anything about the upper bits. */
8119 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8126 /* Return the number of bits at the high-order end of X that are known to
8127 be equal to the sign bit. X will be used in mode MODE; if MODE is
8128 VOIDmode, X will be used in its own mode. The returned value will always
8129 be between 1 and the number of bits in MODE. */
8132 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8133 rtx known_x ATTRIBUTE_UNUSED,
8134 enum machine_mode known_mode
8136 unsigned int known_ret ATTRIBUTE_UNUSED,
8137 unsigned int *result)
8141 if (reg_stat[REGNO (x)].last_set_value != 0
8142 && reg_stat[REGNO (x)].last_set_mode == mode
8143 && (reg_stat[REGNO (x)].last_set_label == label_tick
8144 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8145 && REG_N_SETS (REGNO (x)) == 1
8146 && ! REGNO_REG_SET_P
8147 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8149 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8151 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8155 tem = get_last_value (x);
8159 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8160 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8161 *result = reg_stat[REGNO (x)].sign_bit_copies;
8166 /* Return the number of "extended" bits there are in X, when interpreted
8167 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8168 unsigned quantities, this is the number of high-order zero bits.
8169 For signed quantities, this is the number of copies of the sign bit
8170 minus 1. In both case, this function returns the number of "spare"
8171 bits. For example, if two quantities for which this function returns
8172 at least 1 are added, the addition is known not to overflow.
8174 This function will always return 0 unless called during combine, which
8175 implies that it must be called from a define_split. */
8178 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8180 if (nonzero_sign_valid == 0)
8184 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8185 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8186 - floor_log2 (nonzero_bits (x, mode)))
8188 : num_sign_bit_copies (x, mode) - 1);
8191 /* This function is called from `simplify_shift_const' to merge two
8192 outer operations. Specifically, we have already found that we need
8193 to perform operation *POP0 with constant *PCONST0 at the outermost
8194 position. We would now like to also perform OP1 with constant CONST1
8195 (with *POP0 being done last).
8197 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8198 the resulting operation. *PCOMP_P is set to 1 if we would need to
8199 complement the innermost operand, otherwise it is unchanged.
8201 MODE is the mode in which the operation will be done. No bits outside
8202 the width of this mode matter. It is assumed that the width of this mode
8203 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8205 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8206 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8207 result is simply *PCONST0.
8209 If the resulting operation cannot be expressed as one operation, we
8210 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8213 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8215 enum rtx_code op0 = *pop0;
8216 HOST_WIDE_INT const0 = *pconst0;
8218 const0 &= GET_MODE_MASK (mode);
8219 const1 &= GET_MODE_MASK (mode);
8221 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8225 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8228 if (op1 == UNKNOWN || op0 == SET)
8231 else if (op0 == UNKNOWN)
8232 op0 = op1, const0 = const1;
8234 else if (op0 == op1)
8258 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8259 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8262 /* If the two constants aren't the same, we can't do anything. The
8263 remaining six cases can all be done. */
8264 else if (const0 != const1)
8272 /* (a & b) | b == b */
8274 else /* op1 == XOR */
8275 /* (a ^ b) | b == a | b */
8281 /* (a & b) ^ b == (~a) & b */
8282 op0 = AND, *pcomp_p = 1;
8283 else /* op1 == IOR */
8284 /* (a | b) ^ b == a & ~b */
8285 op0 = AND, const0 = ~const0;
8290 /* (a | b) & b == b */
8292 else /* op1 == XOR */
8293 /* (a ^ b) & b) == (~a) & b */
8300 /* Check for NO-OP cases. */
8301 const0 &= GET_MODE_MASK (mode);
8303 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8305 else if (const0 == 0 && op0 == AND)
8307 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8311 /* ??? Slightly redundant with the above mask, but not entirely.
8312 Moving this above means we'd have to sign-extend the mode mask
8313 for the final test. */
8314 const0 = trunc_int_for_mode (const0, mode);
8322 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8323 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8324 simplify it. Otherwise, return a simplified value.
8326 The shift is normally computed in the widest mode we find in VAROP, as
8327 long as it isn't a different number of words than RESULT_MODE. Exceptions
8328 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8331 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8332 rtx varop, int orig_count)
8334 enum rtx_code orig_code = code;
8335 rtx orig_varop = varop;
8337 enum machine_mode mode = result_mode;
8338 enum machine_mode shift_mode, tmode;
8339 unsigned int mode_words
8340 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8341 /* We form (outer_op (code varop count) (outer_const)). */
8342 enum rtx_code outer_op = UNKNOWN;
8343 HOST_WIDE_INT outer_const = 0;
8344 int complement_p = 0;
8347 /* Make sure and truncate the "natural" shift on the way in. We don't
8348 want to do this inside the loop as it makes it more difficult to
8350 if (SHIFT_COUNT_TRUNCATED)
8351 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8353 /* If we were given an invalid count, don't do anything except exactly
8354 what was requested. */
8356 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8361 /* Unless one of the branches of the `if' in this loop does a `continue',
8362 we will `break' the loop after the `if'. */
8366 /* If we have an operand of (clobber (const_int 0)), fail. */
8367 if (GET_CODE (varop) == CLOBBER)
8370 /* If we discovered we had to complement VAROP, leave. Making a NOT
8371 here would cause an infinite loop. */
8375 /* Convert ROTATERT to ROTATE. */
8376 if (code == ROTATERT)
8378 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8380 if (VECTOR_MODE_P (result_mode))
8381 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8383 count = bitsize - count;
8386 /* We need to determine what mode we will do the shift in. If the
8387 shift is a right shift or a ROTATE, we must always do it in the mode
8388 it was originally done in. Otherwise, we can do it in MODE, the
8389 widest mode encountered. */
8391 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8392 ? result_mode : mode);
8394 /* Handle cases where the count is greater than the size of the mode
8395 minus 1. For ASHIFT, use the size minus one as the count (this can
8396 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8397 take the count modulo the size. For other shifts, the result is
8400 Since these shifts are being produced by the compiler by combining
8401 multiple operations, each of which are defined, we know what the
8402 result is supposed to be. */
8404 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8406 if (code == ASHIFTRT)
8407 count = GET_MODE_BITSIZE (shift_mode) - 1;
8408 else if (code == ROTATE || code == ROTATERT)
8409 count %= GET_MODE_BITSIZE (shift_mode);
8412 /* We can't simply return zero because there may be an
8420 /* An arithmetic right shift of a quantity known to be -1 or 0
8422 if (code == ASHIFTRT
8423 && (num_sign_bit_copies (varop, shift_mode)
8424 == GET_MODE_BITSIZE (shift_mode)))
8430 /* If we are doing an arithmetic right shift and discarding all but
8431 the sign bit copies, this is equivalent to doing a shift by the
8432 bitsize minus one. Convert it into that shift because it will often
8433 allow other simplifications. */
8435 if (code == ASHIFTRT
8436 && (count + num_sign_bit_copies (varop, shift_mode)
8437 >= GET_MODE_BITSIZE (shift_mode)))
8438 count = GET_MODE_BITSIZE (shift_mode) - 1;
8440 /* We simplify the tests below and elsewhere by converting
8441 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8442 `make_compound_operation' will convert it to an ASHIFTRT for
8443 those machines (such as VAX) that don't have an LSHIFTRT. */
8444 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8446 && ((nonzero_bits (varop, shift_mode)
8447 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8451 if (code == LSHIFTRT
8452 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8453 && !(nonzero_bits (varop, shift_mode) >> count))
8456 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8457 && !((nonzero_bits (varop, shift_mode) << count)
8458 & GET_MODE_MASK (shift_mode)))
8461 switch (GET_CODE (varop))
8467 new = expand_compound_operation (varop);
8476 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8477 minus the width of a smaller mode, we can do this with a
8478 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8479 if ((code == ASHIFTRT || code == LSHIFTRT)
8480 && ! mode_dependent_address_p (XEXP (varop, 0))
8481 && ! MEM_VOLATILE_P (varop)
8482 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8483 MODE_INT, 1)) != BLKmode)
8485 new = adjust_address_nv (varop, tmode,
8486 BYTES_BIG_ENDIAN ? 0
8487 : count / BITS_PER_UNIT);
8489 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8490 : ZERO_EXTEND, mode, new);
8497 /* Similar to the case above, except that we can only do this if
8498 the resulting mode is the same as that of the underlying
8499 MEM and adjust the address depending on the *bits* endianness
8500 because of the way that bit-field extract insns are defined. */
8501 if ((code == ASHIFTRT || code == LSHIFTRT)
8502 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8503 MODE_INT, 1)) != BLKmode
8504 && tmode == GET_MODE (XEXP (varop, 0)))
8506 if (BITS_BIG_ENDIAN)
8507 new = XEXP (varop, 0);
8510 new = copy_rtx (XEXP (varop, 0));
8511 SUBST (XEXP (new, 0),
8512 plus_constant (XEXP (new, 0),
8513 count / BITS_PER_UNIT));
8516 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8517 : ZERO_EXTEND, mode, new);
8524 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8525 the same number of words as what we've seen so far. Then store
8526 the widest mode in MODE. */
8527 if (subreg_lowpart_p (varop)
8528 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8529 > GET_MODE_SIZE (GET_MODE (varop)))
8530 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8534 varop = SUBREG_REG (varop);
8535 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8536 mode = GET_MODE (varop);
8542 /* Some machines use MULT instead of ASHIFT because MULT
8543 is cheaper. But it is still better on those machines to
8544 merge two shifts into one. */
8545 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8546 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8549 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8551 GEN_INT (exact_log2 (
8552 INTVAL (XEXP (varop, 1)))));
8558 /* Similar, for when divides are cheaper. */
8559 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8560 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8563 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8565 GEN_INT (exact_log2 (
8566 INTVAL (XEXP (varop, 1)))));
8572 /* If we are extracting just the sign bit of an arithmetic
8573 right shift, that shift is not needed. However, the sign
8574 bit of a wider mode may be different from what would be
8575 interpreted as the sign bit in a narrower mode, so, if
8576 the result is narrower, don't discard the shift. */
8577 if (code == LSHIFTRT
8578 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8579 && (GET_MODE_BITSIZE (result_mode)
8580 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8582 varop = XEXP (varop, 0);
8586 /* ... fall through ... */
8591 /* Here we have two nested shifts. The result is usually the
8592 AND of a new shift with a mask. We compute the result below. */
8593 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8594 && INTVAL (XEXP (varop, 1)) >= 0
8595 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8596 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8597 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8599 enum rtx_code first_code = GET_CODE (varop);
8600 unsigned int first_count = INTVAL (XEXP (varop, 1));
8601 unsigned HOST_WIDE_INT mask;
8604 /* We have one common special case. We can't do any merging if
8605 the inner code is an ASHIFTRT of a smaller mode. However, if
8606 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8607 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8608 we can convert it to
8609 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8610 This simplifies certain SIGN_EXTEND operations. */
8611 if (code == ASHIFT && first_code == ASHIFTRT
8612 && count == (GET_MODE_BITSIZE (result_mode)
8613 - GET_MODE_BITSIZE (GET_MODE (varop))))
8615 /* C3 has the low-order C1 bits zero. */
8617 mask = (GET_MODE_MASK (mode)
8618 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8620 varop = simplify_and_const_int (NULL_RTX, result_mode,
8621 XEXP (varop, 0), mask);
8622 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8624 count = first_count;
8629 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8630 than C1 high-order bits equal to the sign bit, we can convert
8631 this to either an ASHIFT or an ASHIFTRT depending on the
8634 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8636 if (code == ASHIFTRT && first_code == ASHIFT
8637 && GET_MODE (varop) == shift_mode
8638 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8641 varop = XEXP (varop, 0);
8642 count -= first_count;
8652 /* There are some cases we can't do. If CODE is ASHIFTRT,
8653 we can only do this if FIRST_CODE is also ASHIFTRT.
8655 We can't do the case when CODE is ROTATE and FIRST_CODE is
8658 If the mode of this shift is not the mode of the outer shift,
8659 we can't do this if either shift is a right shift or ROTATE.
8661 Finally, we can't do any of these if the mode is too wide
8662 unless the codes are the same.
8664 Handle the case where the shift codes are the same
8667 if (code == first_code)
8669 if (GET_MODE (varop) != result_mode
8670 && (code == ASHIFTRT || code == LSHIFTRT
8674 count += first_count;
8675 varop = XEXP (varop, 0);
8679 if (code == ASHIFTRT
8680 || (code == ROTATE && first_code == ASHIFTRT)
8681 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8682 || (GET_MODE (varop) != result_mode
8683 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8684 || first_code == ROTATE
8685 || code == ROTATE)))
8688 /* To compute the mask to apply after the shift, shift the
8689 nonzero bits of the inner shift the same way the
8690 outer shift will. */
8692 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8695 = simplify_const_binary_operation (code, result_mode, mask_rtx,
8698 /* Give up if we can't compute an outer operation to use. */
8700 || GET_CODE (mask_rtx) != CONST_INT
8701 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8703 result_mode, &complement_p))
8706 /* If the shifts are in the same direction, we add the
8707 counts. Otherwise, we subtract them. */
8708 if ((code == ASHIFTRT || code == LSHIFTRT)
8709 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8710 count += first_count;
8712 count -= first_count;
8714 /* If COUNT is positive, the new shift is usually CODE,
8715 except for the two exceptions below, in which case it is
8716 FIRST_CODE. If the count is negative, FIRST_CODE should
8719 && ((first_code == ROTATE && code == ASHIFT)
8720 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8723 code = first_code, count = -count;
8725 varop = XEXP (varop, 0);
8729 /* If we have (A << B << C) for any shift, we can convert this to
8730 (A << C << B). This wins if A is a constant. Only try this if
8731 B is not a constant. */
8733 else if (GET_CODE (varop) == code
8734 && GET_CODE (XEXP (varop, 0)) == CONST_INT
8735 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
8737 rtx new = simplify_const_binary_operation (code, mode,
8740 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8747 /* Make this fit the case below. */
8748 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8749 GEN_INT (GET_MODE_MASK (mode)));
8755 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8756 with C the size of VAROP - 1 and the shift is logical if
8757 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8758 we have an (le X 0) operation. If we have an arithmetic shift
8759 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8760 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8762 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8763 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8764 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8765 && (code == LSHIFTRT || code == ASHIFTRT)
8766 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8767 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8770 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8773 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8774 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8779 /* If we have (shift (logical)), move the logical to the outside
8780 to allow it to possibly combine with another logical and the
8781 shift to combine with another shift. This also canonicalizes to
8782 what a ZERO_EXTRACT looks like. Also, some machines have
8783 (and (shift)) insns. */
8785 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8786 /* We can't do this if we have (ashiftrt (xor)) and the
8787 constant has its sign bit set in shift_mode. */
8788 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8789 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8791 && (new = simplify_const_binary_operation (code, result_mode,
8793 GEN_INT (count))) != 0
8794 && GET_CODE (new) == CONST_INT
8795 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8796 INTVAL (new), result_mode, &complement_p))
8798 varop = XEXP (varop, 0);
8802 /* If we can't do that, try to simplify the shift in each arm of the
8803 logical expression, make a new logical expression, and apply
8804 the inverse distributive law. This also can't be done
8805 for some (ashiftrt (xor)). */
8806 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8807 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8808 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8811 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8812 XEXP (varop, 0), count);
8813 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8814 XEXP (varop, 1), count);
8816 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8818 varop = apply_distributive_law (varop);
8826 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8827 says that the sign bit can be tested, FOO has mode MODE, C is
8828 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8829 that may be nonzero. */
8830 if (code == LSHIFTRT
8831 && XEXP (varop, 1) == const0_rtx
8832 && GET_MODE (XEXP (varop, 0)) == result_mode
8833 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8834 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8835 && STORE_FLAG_VALUE == -1
8836 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8837 && merge_outer_ops (&outer_op, &outer_const, XOR,
8838 (HOST_WIDE_INT) 1, result_mode,
8841 varop = XEXP (varop, 0);
8848 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8849 than the number of bits in the mode is equivalent to A. */
8850 if (code == LSHIFTRT
8851 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8852 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8854 varop = XEXP (varop, 0);
8859 /* NEG commutes with ASHIFT since it is multiplication. Move the
8860 NEG outside to allow shifts to combine. */
8862 && merge_outer_ops (&outer_op, &outer_const, NEG,
8863 (HOST_WIDE_INT) 0, result_mode,
8866 varop = XEXP (varop, 0);
8872 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8873 is one less than the number of bits in the mode is
8874 equivalent to (xor A 1). */
8875 if (code == LSHIFTRT
8876 && count == (GET_MODE_BITSIZE (result_mode) - 1)
8877 && XEXP (varop, 1) == constm1_rtx
8878 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8879 && merge_outer_ops (&outer_op, &outer_const, XOR,
8880 (HOST_WIDE_INT) 1, result_mode,
8884 varop = XEXP (varop, 0);
8888 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8889 that might be nonzero in BAR are those being shifted out and those
8890 bits are known zero in FOO, we can replace the PLUS with FOO.
8891 Similarly in the other operand order. This code occurs when
8892 we are computing the size of a variable-size array. */
8894 if ((code == ASHIFTRT || code == LSHIFTRT)
8895 && count < HOST_BITS_PER_WIDE_INT
8896 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8897 && (nonzero_bits (XEXP (varop, 1), result_mode)
8898 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8900 varop = XEXP (varop, 0);
8903 else if ((code == ASHIFTRT || code == LSHIFTRT)
8904 && count < HOST_BITS_PER_WIDE_INT
8905 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8906 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8908 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8909 & nonzero_bits (XEXP (varop, 1),
8912 varop = XEXP (varop, 1);
8916 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8918 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8919 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
8921 GEN_INT (count))) != 0
8922 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8923 INTVAL (new), result_mode, &complement_p))
8925 varop = XEXP (varop, 0);
8929 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
8930 signbit', and attempt to change the PLUS to an XOR and move it to
8931 the outer operation as is done above in the AND/IOR/XOR case
8932 leg for shift(logical). See details in logical handling above
8933 for reasoning in doing so. */
8934 if (code == LSHIFTRT
8935 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8936 && mode_signbit_p (result_mode, XEXP (varop, 1))
8937 && (new = simplify_const_binary_operation (code, result_mode,
8939 GEN_INT (count))) != 0
8940 && merge_outer_ops (&outer_op, &outer_const, XOR,
8941 INTVAL (new), result_mode, &complement_p))
8943 varop = XEXP (varop, 0);
8950 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8951 with C the size of VAROP - 1 and the shift is logical if
8952 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8953 we have a (gt X 0) operation. If the shift is arithmetic with
8954 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8955 we have a (neg (gt X 0)) operation. */
8957 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8958 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8959 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8960 && (code == LSHIFTRT || code == ASHIFTRT)
8961 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8962 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8963 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8966 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
8969 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8970 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8977 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8978 if the truncate does not affect the value. */
8979 if (code == LSHIFTRT
8980 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8981 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8982 && (INTVAL (XEXP (XEXP (varop, 0), 1))
8983 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8984 - GET_MODE_BITSIZE (GET_MODE (varop)))))
8986 rtx varop_inner = XEXP (varop, 0);
8989 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
8990 XEXP (varop_inner, 0),
8992 (count + INTVAL (XEXP (varop_inner, 1))));
8993 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9006 /* We need to determine what mode to do the shift in. If the shift is
9007 a right shift or ROTATE, we must always do it in the mode it was
9008 originally done in. Otherwise, we can do it in MODE, the widest mode
9009 encountered. The code we care about is that of the shift that will
9010 actually be done, not the shift that was originally requested. */
9012 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9013 ? result_mode : mode);
9015 /* We have now finished analyzing the shift. The result should be
9016 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9017 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9018 to the result of the shift. OUTER_CONST is the relevant constant,
9019 but we must turn off all bits turned off in the shift. */
9021 if (outer_op == UNKNOWN
9022 && orig_code == code && orig_count == count
9023 && varop == orig_varop
9024 && shift_mode == GET_MODE (varop))
9027 /* Make a SUBREG if necessary. If we can't make it, fail. */
9028 varop = gen_lowpart (shift_mode, varop);
9029 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9032 /* If we have an outer operation and we just made a shift, it is
9033 possible that we could have simplified the shift were it not
9034 for the outer operation. So try to do the simplification
9037 if (outer_op != UNKNOWN)
9038 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9043 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9045 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9046 turn off all the bits that the shift would have turned off. */
9047 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9048 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9049 GET_MODE_MASK (result_mode) >> orig_count);
9051 /* Do the remainder of the processing in RESULT_MODE. */
9052 x = gen_lowpart (result_mode, x);
9054 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9057 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9059 if (outer_op != UNKNOWN)
9061 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9062 outer_const = trunc_int_for_mode (outer_const, result_mode);
9064 if (outer_op == AND)
9065 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9066 else if (outer_op == SET)
9067 /* This means that we have determined that the result is
9068 equivalent to a constant. This should be rare. */
9069 x = GEN_INT (outer_const);
9070 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9071 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9073 x = simplify_gen_binary (outer_op, result_mode, x,
9074 GEN_INT (outer_const));
9080 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9081 The result of the shift is RESULT_MODE. If we cannot simplify it,
9082 return X or, if it is NULL, synthesize the expression with
9083 simplify_gen_binary. Otherwise, return a simplified value.
9085 The shift is normally computed in the widest mode we find in VAROP, as
9086 long as it isn't a different number of words than RESULT_MODE. Exceptions
9087 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9090 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9091 rtx varop, int count)
9093 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9098 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9099 if (GET_MODE (x) != result_mode)
9100 x = gen_lowpart (result_mode, x);
9105 /* Like recog, but we receive the address of a pointer to a new pattern.
9106 We try to match the rtx that the pointer points to.
9107 If that fails, we may try to modify or replace the pattern,
9108 storing the replacement into the same pointer object.
9110 Modifications include deletion or addition of CLOBBERs.
9112 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9113 the CLOBBERs are placed.
9115 The value is the final insn code from the pattern ultimately matched,
9119 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9122 int insn_code_number;
9123 int num_clobbers_to_add = 0;
9126 rtx old_notes, old_pat;
9128 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9129 we use to indicate that something didn't match. If we find such a
9130 thing, force rejection. */
9131 if (GET_CODE (pat) == PARALLEL)
9132 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9133 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9134 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9137 old_pat = PATTERN (insn);
9138 old_notes = REG_NOTES (insn);
9139 PATTERN (insn) = pat;
9140 REG_NOTES (insn) = 0;
9142 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9144 /* If it isn't, there is the possibility that we previously had an insn
9145 that clobbered some register as a side effect, but the combined
9146 insn doesn't need to do that. So try once more without the clobbers
9147 unless this represents an ASM insn. */
9149 if (insn_code_number < 0 && ! check_asm_operands (pat)
9150 && GET_CODE (pat) == PARALLEL)
9154 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9155 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9158 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9162 SUBST_INT (XVECLEN (pat, 0), pos);
9165 pat = XVECEXP (pat, 0, 0);
9167 PATTERN (insn) = pat;
9168 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9170 PATTERN (insn) = old_pat;
9171 REG_NOTES (insn) = old_notes;
9173 /* Recognize all noop sets, these will be killed by followup pass. */
9174 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9175 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9177 /* If we had any clobbers to add, make a new pattern than contains
9178 them. Then check to make sure that all of them are dead. */
9179 if (num_clobbers_to_add)
9181 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9182 rtvec_alloc (GET_CODE (pat) == PARALLEL
9184 + num_clobbers_to_add)
9185 : num_clobbers_to_add + 1));
9187 if (GET_CODE (pat) == PARALLEL)
9188 for (i = 0; i < XVECLEN (pat, 0); i++)
9189 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9191 XVECEXP (newpat, 0, 0) = pat;
9193 add_clobbers (newpat, insn_code_number);
9195 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9196 i < XVECLEN (newpat, 0); i++)
9198 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9199 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9201 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9202 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9210 return insn_code_number;
9213 /* Like gen_lowpart_general but for use by combine. In combine it
9214 is not possible to create any new pseudoregs. However, it is
9215 safe to create invalid memory addresses, because combine will
9216 try to recognize them and all they will do is make the combine
9219 If for some reason this cannot do its job, an rtx
9220 (clobber (const_int 0)) is returned.
9221 An insn containing that will not be recognized. */
9224 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9226 enum machine_mode imode = GET_MODE (x);
9227 unsigned int osize = GET_MODE_SIZE (omode);
9228 unsigned int isize = GET_MODE_SIZE (imode);
9234 /* Return identity if this is a CONST or symbolic reference. */
9236 && (GET_CODE (x) == CONST
9237 || GET_CODE (x) == SYMBOL_REF
9238 || GET_CODE (x) == LABEL_REF))
9241 /* We can only support MODE being wider than a word if X is a
9242 constant integer or has a mode the same size. */
9243 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9244 && ! ((imode == VOIDmode
9245 && (GET_CODE (x) == CONST_INT
9246 || GET_CODE (x) == CONST_DOUBLE))
9250 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9251 won't know what to do. So we will strip off the SUBREG here and
9252 process normally. */
9253 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9257 /* For use in case we fall down into the address adjustments
9258 further below, we need to adjust the known mode and size of
9259 x; imode and isize, since we just adjusted x. */
9260 imode = GET_MODE (x);
9265 isize = GET_MODE_SIZE (imode);
9268 result = gen_lowpart_common (omode, x);
9270 #ifdef CANNOT_CHANGE_MODE_CLASS
9271 if (result != 0 && GET_CODE (result) == SUBREG)
9272 record_subregs_of_mode (result);
9282 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9284 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9287 /* If we want to refer to something bigger than the original memref,
9288 generate a paradoxical subreg instead. That will force a reload
9289 of the original memref X. */
9291 return gen_rtx_SUBREG (omode, x, 0);
9293 if (WORDS_BIG_ENDIAN)
9294 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9296 /* Adjust the address so that the address-after-the-data is
9298 if (BYTES_BIG_ENDIAN)
9299 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9301 return adjust_address_nv (x, omode, offset);
9304 /* If X is a comparison operator, rewrite it in a new mode. This
9305 probably won't match, but may allow further simplifications. */
9306 else if (COMPARISON_P (x))
9307 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9309 /* If we couldn't simplify X any other way, just enclose it in a
9310 SUBREG. Normally, this SUBREG won't match, but some patterns may
9311 include an explicit SUBREG or we may simplify it further in combine. */
9317 offset = subreg_lowpart_offset (omode, imode);
9318 if (imode == VOIDmode)
9320 imode = int_mode_for_mode (omode);
9321 x = gen_lowpart_common (imode, x);
9325 res = simplify_gen_subreg (omode, x, imode, offset);
9331 return gen_rtx_CLOBBER (imode, const0_rtx);
9334 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9335 comparison code that will be tested.
9337 The result is a possibly different comparison code to use. *POP0 and
9338 *POP1 may be updated.
9340 It is possible that we might detect that a comparison is either always
9341 true or always false. However, we do not perform general constant
9342 folding in combine, so this knowledge isn't useful. Such tautologies
9343 should have been detected earlier. Hence we ignore all such cases. */
9345 static enum rtx_code
9346 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9352 enum machine_mode mode, tmode;
9354 /* Try a few ways of applying the same transformation to both operands. */
9357 #ifndef WORD_REGISTER_OPERATIONS
9358 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9359 so check specially. */
9360 if (code != GTU && code != GEU && code != LTU && code != LEU
9361 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9362 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9363 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9364 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9365 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9366 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9367 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9368 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9369 && XEXP (op0, 1) == XEXP (op1, 1)
9370 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9371 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9372 && (INTVAL (XEXP (op0, 1))
9373 == (GET_MODE_BITSIZE (GET_MODE (op0))
9375 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9377 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9378 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9382 /* If both operands are the same constant shift, see if we can ignore the
9383 shift. We can if the shift is a rotate or if the bits shifted out of
9384 this shift are known to be zero for both inputs and if the type of
9385 comparison is compatible with the shift. */
9386 if (GET_CODE (op0) == GET_CODE (op1)
9387 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9388 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9389 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9390 && (code != GT && code != LT && code != GE && code != LE))
9391 || (GET_CODE (op0) == ASHIFTRT
9392 && (code != GTU && code != LTU
9393 && code != GEU && code != LEU)))
9394 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9395 && INTVAL (XEXP (op0, 1)) >= 0
9396 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9397 && XEXP (op0, 1) == XEXP (op1, 1))
9399 enum machine_mode mode = GET_MODE (op0);
9400 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9401 int shift_count = INTVAL (XEXP (op0, 1));
9403 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9404 mask &= (mask >> shift_count) << shift_count;
9405 else if (GET_CODE (op0) == ASHIFT)
9406 mask = (mask & (mask << shift_count)) >> shift_count;
9408 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9409 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9410 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9415 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9416 SUBREGs are of the same mode, and, in both cases, the AND would
9417 be redundant if the comparison was done in the narrower mode,
9418 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9419 and the operand's possibly nonzero bits are 0xffffff01; in that case
9420 if we only care about QImode, we don't need the AND). This case
9421 occurs if the output mode of an scc insn is not SImode and
9422 STORE_FLAG_VALUE == 1 (e.g., the 386).
9424 Similarly, check for a case where the AND's are ZERO_EXTEND
9425 operations from some narrower mode even though a SUBREG is not
9428 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9429 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9430 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9432 rtx inner_op0 = XEXP (op0, 0);
9433 rtx inner_op1 = XEXP (op1, 0);
9434 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9435 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9438 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9439 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9440 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9441 && (GET_MODE (SUBREG_REG (inner_op0))
9442 == GET_MODE (SUBREG_REG (inner_op1)))
9443 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9444 <= HOST_BITS_PER_WIDE_INT)
9445 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9446 GET_MODE (SUBREG_REG (inner_op0)))))
9447 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9448 GET_MODE (SUBREG_REG (inner_op1))))))
9450 op0 = SUBREG_REG (inner_op0);
9451 op1 = SUBREG_REG (inner_op1);
9453 /* The resulting comparison is always unsigned since we masked
9454 off the original sign bit. */
9455 code = unsigned_condition (code);
9461 for (tmode = GET_CLASS_NARROWEST_MODE
9462 (GET_MODE_CLASS (GET_MODE (op0)));
9463 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9464 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9466 op0 = gen_lowpart (tmode, inner_op0);
9467 op1 = gen_lowpart (tmode, inner_op1);
9468 code = unsigned_condition (code);
9477 /* If both operands are NOT, we can strip off the outer operation
9478 and adjust the comparison code for swapped operands; similarly for
9479 NEG, except that this must be an equality comparison. */
9480 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9481 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9482 && (code == EQ || code == NE)))
9483 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9489 /* If the first operand is a constant, swap the operands and adjust the
9490 comparison code appropriately, but don't do this if the second operand
9491 is already a constant integer. */
9492 if (swap_commutative_operands_p (op0, op1))
9494 tem = op0, op0 = op1, op1 = tem;
9495 code = swap_condition (code);
9498 /* We now enter a loop during which we will try to simplify the comparison.
9499 For the most part, we only are concerned with comparisons with zero,
9500 but some things may really be comparisons with zero but not start
9501 out looking that way. */
9503 while (GET_CODE (op1) == CONST_INT)
9505 enum machine_mode mode = GET_MODE (op0);
9506 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9507 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9508 int equality_comparison_p;
9509 int sign_bit_comparison_p;
9510 int unsigned_comparison_p;
9511 HOST_WIDE_INT const_op;
9513 /* We only want to handle integral modes. This catches VOIDmode,
9514 CCmode, and the floating-point modes. An exception is that we
9515 can handle VOIDmode if OP0 is a COMPARE or a comparison
9518 if (GET_MODE_CLASS (mode) != MODE_INT
9519 && ! (mode == VOIDmode
9520 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9523 /* Get the constant we are comparing against and turn off all bits
9524 not on in our mode. */
9525 const_op = INTVAL (op1);
9526 if (mode != VOIDmode)
9527 const_op = trunc_int_for_mode (const_op, mode);
9528 op1 = GEN_INT (const_op);
9530 /* If we are comparing against a constant power of two and the value
9531 being compared can only have that single bit nonzero (e.g., it was
9532 `and'ed with that bit), we can replace this with a comparison
9535 && (code == EQ || code == NE || code == GE || code == GEU
9536 || code == LT || code == LTU)
9537 && mode_width <= HOST_BITS_PER_WIDE_INT
9538 && exact_log2 (const_op) >= 0
9539 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9541 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9542 op1 = const0_rtx, const_op = 0;
9545 /* Similarly, if we are comparing a value known to be either -1 or
9546 0 with -1, change it to the opposite comparison against zero. */
9549 && (code == EQ || code == NE || code == GT || code == LE
9550 || code == GEU || code == LTU)
9551 && num_sign_bit_copies (op0, mode) == mode_width)
9553 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9554 op1 = const0_rtx, const_op = 0;
9557 /* Do some canonicalizations based on the comparison code. We prefer
9558 comparisons against zero and then prefer equality comparisons.
9559 If we can reduce the size of a constant, we will do that too. */
9564 /* < C is equivalent to <= (C - 1) */
9568 op1 = GEN_INT (const_op);
9570 /* ... fall through to LE case below. */
9576 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9580 op1 = GEN_INT (const_op);
9584 /* If we are doing a <= 0 comparison on a value known to have
9585 a zero sign bit, we can replace this with == 0. */
9586 else if (const_op == 0
9587 && mode_width <= HOST_BITS_PER_WIDE_INT
9588 && (nonzero_bits (op0, mode)
9589 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9594 /* >= C is equivalent to > (C - 1). */
9598 op1 = GEN_INT (const_op);
9600 /* ... fall through to GT below. */
9606 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9610 op1 = GEN_INT (const_op);
9614 /* If we are doing a > 0 comparison on a value known to have
9615 a zero sign bit, we can replace this with != 0. */
9616 else if (const_op == 0
9617 && mode_width <= HOST_BITS_PER_WIDE_INT
9618 && (nonzero_bits (op0, mode)
9619 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9624 /* < C is equivalent to <= (C - 1). */
9628 op1 = GEN_INT (const_op);
9630 /* ... fall through ... */
9633 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9634 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9635 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9637 const_op = 0, op1 = const0_rtx;
9645 /* unsigned <= 0 is equivalent to == 0 */
9649 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9650 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9651 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9653 const_op = 0, op1 = const0_rtx;
9659 /* >= C is equivalent to > (C - 1). */
9663 op1 = GEN_INT (const_op);
9665 /* ... fall through ... */
9668 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9669 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9670 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9672 const_op = 0, op1 = const0_rtx;
9680 /* unsigned > 0 is equivalent to != 0 */
9684 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9685 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9686 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9688 const_op = 0, op1 = const0_rtx;
9697 /* Compute some predicates to simplify code below. */
9699 equality_comparison_p = (code == EQ || code == NE);
9700 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9701 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9704 /* If this is a sign bit comparison and we can do arithmetic in
9705 MODE, say that we will only be needing the sign bit of OP0. */
9706 if (sign_bit_comparison_p
9707 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9708 op0 = force_to_mode (op0, mode,
9710 << (GET_MODE_BITSIZE (mode) - 1)),
9713 /* Now try cases based on the opcode of OP0. If none of the cases
9714 does a "continue", we exit this loop immediately after the
9717 switch (GET_CODE (op0))
9720 /* If we are extracting a single bit from a variable position in
9721 a constant that has only a single bit set and are comparing it
9722 with zero, we can convert this into an equality comparison
9723 between the position and the location of the single bit. */
9724 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9725 have already reduced the shift count modulo the word size. */
9726 if (!SHIFT_COUNT_TRUNCATED
9727 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9728 && XEXP (op0, 1) == const1_rtx
9729 && equality_comparison_p && const_op == 0
9730 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9732 if (BITS_BIG_ENDIAN)
9734 enum machine_mode new_mode
9735 = mode_for_extraction (EP_extzv, 1);
9736 if (new_mode == MAX_MACHINE_MODE)
9737 i = BITS_PER_WORD - 1 - i;
9741 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9745 op0 = XEXP (op0, 2);
9749 /* Result is nonzero iff shift count is equal to I. */
9750 code = reverse_condition (code);
9754 /* ... fall through ... */
9757 tem = expand_compound_operation (op0);
9766 /* If testing for equality, we can take the NOT of the constant. */
9767 if (equality_comparison_p
9768 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9770 op0 = XEXP (op0, 0);
9775 /* If just looking at the sign bit, reverse the sense of the
9777 if (sign_bit_comparison_p)
9779 op0 = XEXP (op0, 0);
9780 code = (code == GE ? LT : GE);
9786 /* If testing for equality, we can take the NEG of the constant. */
9787 if (equality_comparison_p
9788 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9790 op0 = XEXP (op0, 0);
9795 /* The remaining cases only apply to comparisons with zero. */
9799 /* When X is ABS or is known positive,
9800 (neg X) is < 0 if and only if X != 0. */
9802 if (sign_bit_comparison_p
9803 && (GET_CODE (XEXP (op0, 0)) == ABS
9804 || (mode_width <= HOST_BITS_PER_WIDE_INT
9805 && (nonzero_bits (XEXP (op0, 0), mode)
9806 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9808 op0 = XEXP (op0, 0);
9809 code = (code == LT ? NE : EQ);
9813 /* If we have NEG of something whose two high-order bits are the
9814 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9815 if (num_sign_bit_copies (op0, mode) >= 2)
9817 op0 = XEXP (op0, 0);
9818 code = swap_condition (code);
9824 /* If we are testing equality and our count is a constant, we
9825 can perform the inverse operation on our RHS. */
9826 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9827 && (tem = simplify_binary_operation (ROTATERT, mode,
9828 op1, XEXP (op0, 1))) != 0)
9830 op0 = XEXP (op0, 0);
9835 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9836 a particular bit. Convert it to an AND of a constant of that
9837 bit. This will be converted into a ZERO_EXTRACT. */
9838 if (const_op == 0 && sign_bit_comparison_p
9839 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9840 && mode_width <= HOST_BITS_PER_WIDE_INT)
9842 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9845 - INTVAL (XEXP (op0, 1)))));
9846 code = (code == LT ? NE : EQ);
9853 /* ABS is ignorable inside an equality comparison with zero. */
9854 if (const_op == 0 && equality_comparison_p)
9856 op0 = XEXP (op0, 0);
9862 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
9863 (compare FOO CONST) if CONST fits in FOO's mode and we
9864 are either testing inequality or have an unsigned
9865 comparison with ZERO_EXTEND or a signed comparison with
9866 SIGN_EXTEND. But don't do it if we don't have a compare
9867 insn of the given mode, since we'd have to revert it
9868 later on, and then we wouldn't know whether to sign- or
9870 mode = GET_MODE (XEXP (op0, 0));
9871 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9872 && ! unsigned_comparison_p
9873 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9874 && ((unsigned HOST_WIDE_INT) const_op
9875 < (((unsigned HOST_WIDE_INT) 1
9876 << (GET_MODE_BITSIZE (mode) - 1))))
9877 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9879 op0 = XEXP (op0, 0);
9885 /* Check for the case where we are comparing A - C1 with C2, that is
9887 (subreg:MODE (plus (A) (-C1))) op (C2)
9889 with C1 a constant, and try to lift the SUBREG, i.e. to do the
9890 comparison in the wider mode. One of the following two conditions
9891 must be true in order for this to be valid:
9893 1. The mode extension results in the same bit pattern being added
9894 on both sides and the comparison is equality or unsigned. As
9895 C2 has been truncated to fit in MODE, the pattern can only be
9898 2. The mode extension results in the sign bit being copied on
9901 The difficulty here is that we have predicates for A but not for
9902 (A - C1) so we need to check that C1 is within proper bounds so
9903 as to perturbate A as little as possible. */
9905 if (mode_width <= HOST_BITS_PER_WIDE_INT
9906 && subreg_lowpart_p (op0)
9907 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
9908 && GET_CODE (SUBREG_REG (op0)) == PLUS
9909 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
9911 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
9912 rtx a = XEXP (SUBREG_REG (op0), 0);
9913 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
9916 && (unsigned HOST_WIDE_INT) c1
9917 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
9918 && (equality_comparison_p || unsigned_comparison_p)
9919 /* (A - C1) zero-extends if it is positive and sign-extends
9920 if it is negative, C2 both zero- and sign-extends. */
9921 && ((0 == (nonzero_bits (a, inner_mode)
9922 & ~GET_MODE_MASK (mode))
9924 /* (A - C1) sign-extends if it is positive and 1-extends
9925 if it is negative, C2 both sign- and 1-extends. */
9926 || (num_sign_bit_copies (a, inner_mode)
9927 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
9930 || ((unsigned HOST_WIDE_INT) c1
9931 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
9932 /* (A - C1) always sign-extends, like C2. */
9933 && num_sign_bit_copies (a, inner_mode)
9934 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
9935 - (mode_width - 1))))
9937 op0 = SUBREG_REG (op0);
9942 /* If the inner mode is narrower and we are extracting the low part,
9943 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9944 if (subreg_lowpart_p (op0)
9945 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9946 /* Fall through */ ;
9950 /* ... fall through ... */
9953 mode = GET_MODE (XEXP (op0, 0));
9954 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9955 && (unsigned_comparison_p || equality_comparison_p)
9956 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9957 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
9958 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9960 op0 = XEXP (op0, 0);
9966 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9967 this for equality comparisons due to pathological cases involving
9969 if (equality_comparison_p
9970 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9971 op1, XEXP (op0, 1))))
9973 op0 = XEXP (op0, 0);
9978 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9979 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9980 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9982 op0 = XEXP (XEXP (op0, 0), 0);
9983 code = (code == LT ? EQ : NE);
9989 /* We used to optimize signed comparisons against zero, but that
9990 was incorrect. Unsigned comparisons against zero (GTU, LEU)
9991 arrive here as equality comparisons, or (GEU, LTU) are
9992 optimized away. No need to special-case them. */
9994 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9995 (eq B (minus A C)), whichever simplifies. We can only do
9996 this for equality comparisons due to pathological cases involving
9998 if (equality_comparison_p
9999 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10000 XEXP (op0, 1), op1)))
10002 op0 = XEXP (op0, 0);
10007 if (equality_comparison_p
10008 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10009 XEXP (op0, 0), op1)))
10011 op0 = XEXP (op0, 1);
10016 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10017 of bits in X minus 1, is one iff X > 0. */
10018 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10019 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10020 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10022 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10024 op0 = XEXP (op0, 1);
10025 code = (code == GE ? LE : GT);
10031 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10032 if C is zero or B is a constant. */
10033 if (equality_comparison_p
10034 && 0 != (tem = simplify_binary_operation (XOR, mode,
10035 XEXP (op0, 1), op1)))
10037 op0 = XEXP (op0, 0);
10044 case UNEQ: case LTGT:
10045 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10046 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10047 case UNORDERED: case ORDERED:
10048 /* We can't do anything if OP0 is a condition code value, rather
10049 than an actual data value. */
10051 || CC0_P (XEXP (op0, 0))
10052 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10055 /* Get the two operands being compared. */
10056 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10057 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10059 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10061 /* Check for the cases where we simply want the result of the
10062 earlier test or the opposite of that result. */
10063 if (code == NE || code == EQ
10064 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10065 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10066 && (STORE_FLAG_VALUE
10067 & (((HOST_WIDE_INT) 1
10068 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10069 && (code == LT || code == GE)))
10071 enum rtx_code new_code;
10072 if (code == LT || code == NE)
10073 new_code = GET_CODE (op0);
10075 new_code = reversed_comparison_code (op0, NULL);
10077 if (new_code != UNKNOWN)
10088 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10090 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10091 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10092 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10094 op0 = XEXP (op0, 1);
10095 code = (code == GE ? GT : LE);
10101 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10102 will be converted to a ZERO_EXTRACT later. */
10103 if (const_op == 0 && equality_comparison_p
10104 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10105 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10107 op0 = simplify_and_const_int
10108 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10110 XEXP (XEXP (op0, 0), 1)),
10111 (HOST_WIDE_INT) 1);
10115 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10116 zero and X is a comparison and C1 and C2 describe only bits set
10117 in STORE_FLAG_VALUE, we can compare with X. */
10118 if (const_op == 0 && equality_comparison_p
10119 && mode_width <= HOST_BITS_PER_WIDE_INT
10120 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10121 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10122 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10123 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10124 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10126 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10127 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10128 if ((~STORE_FLAG_VALUE & mask) == 0
10129 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10130 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10131 && COMPARISON_P (tem))))
10133 op0 = XEXP (XEXP (op0, 0), 0);
10138 /* If we are doing an equality comparison of an AND of a bit equal
10139 to the sign bit, replace this with a LT or GE comparison of
10140 the underlying value. */
10141 if (equality_comparison_p
10143 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10144 && mode_width <= HOST_BITS_PER_WIDE_INT
10145 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10146 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10148 op0 = XEXP (op0, 0);
10149 code = (code == EQ ? GE : LT);
10153 /* If this AND operation is really a ZERO_EXTEND from a narrower
10154 mode, the constant fits within that mode, and this is either an
10155 equality or unsigned comparison, try to do this comparison in
10156 the narrower mode. */
10157 if ((equality_comparison_p || unsigned_comparison_p)
10158 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10159 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10160 & GET_MODE_MASK (mode))
10162 && const_op >> i == 0
10163 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10165 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10169 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10170 fits in both M1 and M2 and the SUBREG is either paradoxical
10171 or represents the low part, permute the SUBREG and the AND
10173 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10175 unsigned HOST_WIDE_INT c1;
10176 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10177 /* Require an integral mode, to avoid creating something like
10179 if (SCALAR_INT_MODE_P (tmode)
10180 /* It is unsafe to commute the AND into the SUBREG if the
10181 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10182 not defined. As originally written the upper bits
10183 have a defined value due to the AND operation.
10184 However, if we commute the AND inside the SUBREG then
10185 they no longer have defined values and the meaning of
10186 the code has been changed. */
10188 #ifdef WORD_REGISTER_OPERATIONS
10189 || (mode_width > GET_MODE_BITSIZE (tmode)
10190 && mode_width <= BITS_PER_WORD)
10192 || (mode_width <= GET_MODE_BITSIZE (tmode)
10193 && subreg_lowpart_p (XEXP (op0, 0))))
10194 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10195 && mode_width <= HOST_BITS_PER_WIDE_INT
10196 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10197 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10198 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10200 && c1 != GET_MODE_MASK (tmode))
10202 op0 = simplify_gen_binary (AND, tmode,
10203 SUBREG_REG (XEXP (op0, 0)),
10204 gen_int_mode (c1, tmode));
10205 op0 = gen_lowpart (mode, op0);
10210 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10211 if (const_op == 0 && equality_comparison_p
10212 && XEXP (op0, 1) == const1_rtx
10213 && GET_CODE (XEXP (op0, 0)) == NOT)
10215 op0 = simplify_and_const_int
10216 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10217 code = (code == NE ? EQ : NE);
10221 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10222 (eq (and (lshiftrt X) 1) 0).
10223 Also handle the case where (not X) is expressed using xor. */
10224 if (const_op == 0 && equality_comparison_p
10225 && XEXP (op0, 1) == const1_rtx
10226 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10228 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10229 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10231 if (GET_CODE (shift_op) == NOT
10232 || (GET_CODE (shift_op) == XOR
10233 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10234 && GET_CODE (shift_count) == CONST_INT
10235 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10236 && (INTVAL (XEXP (shift_op, 1))
10237 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10239 op0 = simplify_and_const_int
10241 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10242 (HOST_WIDE_INT) 1);
10243 code = (code == NE ? EQ : NE);
10250 /* If we have (compare (ashift FOO N) (const_int C)) and
10251 the high order N bits of FOO (N+1 if an inequality comparison)
10252 are known to be zero, we can do this by comparing FOO with C
10253 shifted right N bits so long as the low-order N bits of C are
10255 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10256 && INTVAL (XEXP (op0, 1)) >= 0
10257 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10258 < HOST_BITS_PER_WIDE_INT)
10260 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10261 && mode_width <= HOST_BITS_PER_WIDE_INT
10262 && (nonzero_bits (XEXP (op0, 0), mode)
10263 & ~(mask >> (INTVAL (XEXP (op0, 1))
10264 + ! equality_comparison_p))) == 0)
10266 /* We must perform a logical shift, not an arithmetic one,
10267 as we want the top N bits of C to be zero. */
10268 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10270 temp >>= INTVAL (XEXP (op0, 1));
10271 op1 = gen_int_mode (temp, mode);
10272 op0 = XEXP (op0, 0);
10276 /* If we are doing a sign bit comparison, it means we are testing
10277 a particular bit. Convert it to the appropriate AND. */
10278 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10279 && mode_width <= HOST_BITS_PER_WIDE_INT)
10281 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10284 - INTVAL (XEXP (op0, 1)))));
10285 code = (code == LT ? NE : EQ);
10289 /* If this an equality comparison with zero and we are shifting
10290 the low bit to the sign bit, we can convert this to an AND of the
10292 if (const_op == 0 && equality_comparison_p
10293 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10294 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10297 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10298 (HOST_WIDE_INT) 1);
10304 /* If this is an equality comparison with zero, we can do this
10305 as a logical shift, which might be much simpler. */
10306 if (equality_comparison_p && const_op == 0
10307 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10309 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10311 INTVAL (XEXP (op0, 1)));
10315 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10316 do the comparison in a narrower mode. */
10317 if (! unsigned_comparison_p
10318 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10319 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10320 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10321 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10322 MODE_INT, 1)) != BLKmode
10323 && (((unsigned HOST_WIDE_INT) const_op
10324 + (GET_MODE_MASK (tmode) >> 1) + 1)
10325 <= GET_MODE_MASK (tmode)))
10327 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10331 /* Likewise if OP0 is a PLUS of a sign extension with a
10332 constant, which is usually represented with the PLUS
10333 between the shifts. */
10334 if (! unsigned_comparison_p
10335 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10336 && GET_CODE (XEXP (op0, 0)) == PLUS
10337 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10338 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10339 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10340 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10341 MODE_INT, 1)) != BLKmode
10342 && (((unsigned HOST_WIDE_INT) const_op
10343 + (GET_MODE_MASK (tmode) >> 1) + 1)
10344 <= GET_MODE_MASK (tmode)))
10346 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10347 rtx add_const = XEXP (XEXP (op0, 0), 1);
10348 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10349 add_const, XEXP (op0, 1));
10351 op0 = simplify_gen_binary (PLUS, tmode,
10352 gen_lowpart (tmode, inner),
10357 /* ... fall through ... */
10359 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10360 the low order N bits of FOO are known to be zero, we can do this
10361 by comparing FOO with C shifted left N bits so long as no
10362 overflow occurs. */
10363 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10364 && INTVAL (XEXP (op0, 1)) >= 0
10365 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10366 && mode_width <= HOST_BITS_PER_WIDE_INT
10367 && (nonzero_bits (XEXP (op0, 0), mode)
10368 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10369 && (((unsigned HOST_WIDE_INT) const_op
10370 + (GET_CODE (op0) != LSHIFTRT
10371 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10374 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10376 /* If the shift was logical, then we must make the condition
10378 if (GET_CODE (op0) == LSHIFTRT)
10379 code = unsigned_condition (code);
10381 const_op <<= INTVAL (XEXP (op0, 1));
10382 op1 = GEN_INT (const_op);
10383 op0 = XEXP (op0, 0);
10387 /* If we are using this shift to extract just the sign bit, we
10388 can replace this with an LT or GE comparison. */
10390 && (equality_comparison_p || sign_bit_comparison_p)
10391 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10392 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10395 op0 = XEXP (op0, 0);
10396 code = (code == NE || code == GT ? LT : GE);
10408 /* Now make any compound operations involved in this comparison. Then,
10409 check for an outmost SUBREG on OP0 that is not doing anything or is
10410 paradoxical. The latter transformation must only be performed when
10411 it is known that the "extra" bits will be the same in op0 and op1 or
10412 that they don't matter. There are three cases to consider:
10414 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10415 care bits and we can assume they have any convenient value. So
10416 making the transformation is safe.
10418 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10419 In this case the upper bits of op0 are undefined. We should not make
10420 the simplification in that case as we do not know the contents of
10423 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10424 UNKNOWN. In that case we know those bits are zeros or ones. We must
10425 also be sure that they are the same as the upper bits of op1.
10427 We can never remove a SUBREG for a non-equality comparison because
10428 the sign bit is in a different place in the underlying object. */
10430 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10431 op1 = make_compound_operation (op1, SET);
10433 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10434 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10435 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10436 && (code == NE || code == EQ))
10438 if (GET_MODE_SIZE (GET_MODE (op0))
10439 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10441 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10443 if (REG_P (SUBREG_REG (op0)))
10445 op0 = SUBREG_REG (op0);
10446 op1 = gen_lowpart (GET_MODE (op0), op1);
10449 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10450 <= HOST_BITS_PER_WIDE_INT)
10451 && (nonzero_bits (SUBREG_REG (op0),
10452 GET_MODE (SUBREG_REG (op0)))
10453 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10455 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10457 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10458 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10459 op0 = SUBREG_REG (op0), op1 = tem;
10463 /* We now do the opposite procedure: Some machines don't have compare
10464 insns in all modes. If OP0's mode is an integer mode smaller than a
10465 word and we can't do a compare in that mode, see if there is a larger
10466 mode for which we can do the compare. There are a number of cases in
10467 which we can use the wider mode. */
10469 mode = GET_MODE (op0);
10470 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10471 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10472 && ! have_insn_for (COMPARE, mode))
10473 for (tmode = GET_MODE_WIDER_MODE (mode);
10475 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10476 tmode = GET_MODE_WIDER_MODE (tmode))
10477 if (have_insn_for (COMPARE, tmode))
10481 /* If the only nonzero bits in OP0 and OP1 are those in the
10482 narrower mode and this is an equality or unsigned comparison,
10483 we can use the wider mode. Similarly for sign-extended
10484 values, in which case it is true for all comparisons. */
10485 zero_extended = ((code == EQ || code == NE
10486 || code == GEU || code == GTU
10487 || code == LEU || code == LTU)
10488 && (nonzero_bits (op0, tmode)
10489 & ~GET_MODE_MASK (mode)) == 0
10490 && ((GET_CODE (op1) == CONST_INT
10491 || (nonzero_bits (op1, tmode)
10492 & ~GET_MODE_MASK (mode)) == 0)));
10495 || ((num_sign_bit_copies (op0, tmode)
10496 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10497 - GET_MODE_BITSIZE (mode)))
10498 && (num_sign_bit_copies (op1, tmode)
10499 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10500 - GET_MODE_BITSIZE (mode)))))
10502 /* If OP0 is an AND and we don't have an AND in MODE either,
10503 make a new AND in the proper mode. */
10504 if (GET_CODE (op0) == AND
10505 && !have_insn_for (AND, mode))
10506 op0 = simplify_gen_binary (AND, tmode,
10507 gen_lowpart (tmode,
10509 gen_lowpart (tmode,
10512 op0 = gen_lowpart (tmode, op0);
10513 if (zero_extended && GET_CODE (op1) == CONST_INT)
10514 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10515 op1 = gen_lowpart (tmode, op1);
10519 /* If this is a test for negative, we can make an explicit
10520 test of the sign bit. */
10522 if (op1 == const0_rtx && (code == LT || code == GE)
10523 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10525 op0 = simplify_gen_binary (AND, tmode,
10526 gen_lowpart (tmode, op0),
10527 GEN_INT ((HOST_WIDE_INT) 1
10528 << (GET_MODE_BITSIZE (mode)
10530 code = (code == LT) ? NE : EQ;
10535 #ifdef CANONICALIZE_COMPARISON
10536 /* If this machine only supports a subset of valid comparisons, see if we
10537 can convert an unsupported one into a supported one. */
10538 CANONICALIZE_COMPARISON (code, op0, op1);
10547 /* Utility function for record_value_for_reg. Count number of
10552 enum rtx_code code = GET_CODE (x);
10556 if (GET_RTX_CLASS (code) == '2'
10557 || GET_RTX_CLASS (code) == 'c')
10559 rtx x0 = XEXP (x, 0);
10560 rtx x1 = XEXP (x, 1);
10563 return 1 + 2 * count_rtxs (x0);
10565 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10566 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10567 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10568 return 2 + 2 * count_rtxs (x0)
10569 + count_rtxs (x == XEXP (x1, 0)
10570 ? XEXP (x1, 1) : XEXP (x1, 0));
10572 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10573 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10574 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10575 return 2 + 2 * count_rtxs (x1)
10576 + count_rtxs (x == XEXP (x0, 0)
10577 ? XEXP (x0, 1) : XEXP (x0, 0));
10580 fmt = GET_RTX_FORMAT (code);
10581 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10583 ret += count_rtxs (XEXP (x, i));
10588 /* Utility function for following routine. Called when X is part of a value
10589 being stored into last_set_value. Sets last_set_table_tick
10590 for each register mentioned. Similar to mention_regs in cse.c */
10593 update_table_tick (rtx x)
10595 enum rtx_code code = GET_CODE (x);
10596 const char *fmt = GET_RTX_FORMAT (code);
10601 unsigned int regno = REGNO (x);
10602 unsigned int endregno
10603 = regno + (regno < FIRST_PSEUDO_REGISTER
10604 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10607 for (r = regno; r < endregno; r++)
10608 reg_stat[r].last_set_table_tick = label_tick;
10613 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10614 /* Note that we can't have an "E" in values stored; see
10615 get_last_value_validate. */
10618 /* Check for identical subexpressions. If x contains
10619 identical subexpression we only have to traverse one of
10621 if (i == 0 && ARITHMETIC_P (x))
10623 /* Note that at this point x1 has already been
10625 rtx x0 = XEXP (x, 0);
10626 rtx x1 = XEXP (x, 1);
10628 /* If x0 and x1 are identical then there is no need to
10633 /* If x0 is identical to a subexpression of x1 then while
10634 processing x1, x0 has already been processed. Thus we
10635 are done with x. */
10636 if (ARITHMETIC_P (x1)
10637 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10640 /* If x1 is identical to a subexpression of x0 then we
10641 still have to process the rest of x0. */
10642 if (ARITHMETIC_P (x0)
10643 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10645 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10650 update_table_tick (XEXP (x, i));
10654 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10655 are saying that the register is clobbered and we no longer know its
10656 value. If INSN is zero, don't update reg_stat[].last_set; this is
10657 only permitted with VALUE also zero and is used to invalidate the
10661 record_value_for_reg (rtx reg, rtx insn, rtx value)
10663 unsigned int regno = REGNO (reg);
10664 unsigned int endregno
10665 = regno + (regno < FIRST_PSEUDO_REGISTER
10666 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10669 /* If VALUE contains REG and we have a previous value for REG, substitute
10670 the previous value. */
10671 if (value && insn && reg_overlap_mentioned_p (reg, value))
10675 /* Set things up so get_last_value is allowed to see anything set up to
10677 subst_low_cuid = INSN_CUID (insn);
10678 tem = get_last_value (reg);
10680 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10681 it isn't going to be useful and will take a lot of time to process,
10682 so just use the CLOBBER. */
10686 if (ARITHMETIC_P (tem)
10687 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10688 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10689 tem = XEXP (tem, 0);
10690 else if (count_occurrences (value, reg, 1) >= 2)
10692 /* If there are two or more occurrences of REG in VALUE,
10693 prevent the value from growing too much. */
10694 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10695 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10698 value = replace_rtx (copy_rtx (value), reg, tem);
10702 /* For each register modified, show we don't know its value, that
10703 we don't know about its bitwise content, that its value has been
10704 updated, and that we don't know the location of the death of the
10706 for (i = regno; i < endregno; i++)
10709 reg_stat[i].last_set = insn;
10711 reg_stat[i].last_set_value = 0;
10712 reg_stat[i].last_set_mode = 0;
10713 reg_stat[i].last_set_nonzero_bits = 0;
10714 reg_stat[i].last_set_sign_bit_copies = 0;
10715 reg_stat[i].last_death = 0;
10718 /* Mark registers that are being referenced in this value. */
10720 update_table_tick (value);
10722 /* Now update the status of each register being set.
10723 If someone is using this register in this block, set this register
10724 to invalid since we will get confused between the two lives in this
10725 basic block. This makes using this register always invalid. In cse, we
10726 scan the table to invalidate all entries using this register, but this
10727 is too much work for us. */
10729 for (i = regno; i < endregno; i++)
10731 reg_stat[i].last_set_label = label_tick;
10732 if (value && reg_stat[i].last_set_table_tick == label_tick)
10733 reg_stat[i].last_set_invalid = 1;
10735 reg_stat[i].last_set_invalid = 0;
10738 /* The value being assigned might refer to X (like in "x++;"). In that
10739 case, we must replace it with (clobber (const_int 0)) to prevent
10741 if (value && ! get_last_value_validate (&value, insn,
10742 reg_stat[regno].last_set_label, 0))
10744 value = copy_rtx (value);
10745 if (! get_last_value_validate (&value, insn,
10746 reg_stat[regno].last_set_label, 1))
10750 /* For the main register being modified, update the value, the mode, the
10751 nonzero bits, and the number of sign bit copies. */
10753 reg_stat[regno].last_set_value = value;
10757 enum machine_mode mode = GET_MODE (reg);
10758 subst_low_cuid = INSN_CUID (insn);
10759 reg_stat[regno].last_set_mode = mode;
10760 if (GET_MODE_CLASS (mode) == MODE_INT
10761 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10762 mode = nonzero_bits_mode;
10763 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10764 reg_stat[regno].last_set_sign_bit_copies
10765 = num_sign_bit_copies (value, GET_MODE (reg));
10769 /* Called via note_stores from record_dead_and_set_regs to handle one
10770 SET or CLOBBER in an insn. DATA is the instruction in which the
10771 set is occurring. */
10774 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10776 rtx record_dead_insn = (rtx) data;
10778 if (GET_CODE (dest) == SUBREG)
10779 dest = SUBREG_REG (dest);
10783 /* If we are setting the whole register, we know its value. Otherwise
10784 show that we don't know the value. We can handle SUBREG in
10786 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10787 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10788 else if (GET_CODE (setter) == SET
10789 && GET_CODE (SET_DEST (setter)) == SUBREG
10790 && SUBREG_REG (SET_DEST (setter)) == dest
10791 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10792 && subreg_lowpart_p (SET_DEST (setter)))
10793 record_value_for_reg (dest, record_dead_insn,
10794 gen_lowpart (GET_MODE (dest),
10795 SET_SRC (setter)));
10797 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10799 else if (MEM_P (dest)
10800 /* Ignore pushes, they clobber nothing. */
10801 && ! push_operand (dest, GET_MODE (dest)))
10802 mem_last_set = INSN_CUID (record_dead_insn);
10805 /* Update the records of when each REG was most recently set or killed
10806 for the things done by INSN. This is the last thing done in processing
10807 INSN in the combiner loop.
10809 We update reg_stat[], in particular fields last_set, last_set_value,
10810 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10811 last_death, and also the similar information mem_last_set (which insn
10812 most recently modified memory) and last_call_cuid (which insn was the
10813 most recent subroutine call). */
10816 record_dead_and_set_regs (rtx insn)
10821 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10823 if (REG_NOTE_KIND (link) == REG_DEAD
10824 && REG_P (XEXP (link, 0)))
10826 unsigned int regno = REGNO (XEXP (link, 0));
10827 unsigned int endregno
10828 = regno + (regno < FIRST_PSEUDO_REGISTER
10829 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10832 for (i = regno; i < endregno; i++)
10833 reg_stat[i].last_death = insn;
10835 else if (REG_NOTE_KIND (link) == REG_INC)
10836 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10841 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10842 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10844 reg_stat[i].last_set_value = 0;
10845 reg_stat[i].last_set_mode = 0;
10846 reg_stat[i].last_set_nonzero_bits = 0;
10847 reg_stat[i].last_set_sign_bit_copies = 0;
10848 reg_stat[i].last_death = 0;
10851 last_call_cuid = mem_last_set = INSN_CUID (insn);
10853 /* Don't bother recording what this insn does. It might set the
10854 return value register, but we can't combine into a call
10855 pattern anyway, so there's no point trying (and it may cause
10856 a crash, if e.g. we wind up asking for last_set_value of a
10857 SUBREG of the return value register). */
10861 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10864 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10865 register present in the SUBREG, so for each such SUBREG go back and
10866 adjust nonzero and sign bit information of the registers that are
10867 known to have some zero/sign bits set.
10869 This is needed because when combine blows the SUBREGs away, the
10870 information on zero/sign bits is lost and further combines can be
10871 missed because of that. */
10874 record_promoted_value (rtx insn, rtx subreg)
10877 unsigned int regno = REGNO (SUBREG_REG (subreg));
10878 enum machine_mode mode = GET_MODE (subreg);
10880 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10883 for (links = LOG_LINKS (insn); links;)
10885 insn = XEXP (links, 0);
10886 set = single_set (insn);
10888 if (! set || !REG_P (SET_DEST (set))
10889 || REGNO (SET_DEST (set)) != regno
10890 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10892 links = XEXP (links, 1);
10896 if (reg_stat[regno].last_set == insn)
10898 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
10899 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
10902 if (REG_P (SET_SRC (set)))
10904 regno = REGNO (SET_SRC (set));
10905 links = LOG_LINKS (insn);
10912 /* Scan X for promoted SUBREGs. For each one found,
10913 note what it implies to the registers used in it. */
10916 check_promoted_subreg (rtx insn, rtx x)
10918 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
10919 && REG_P (SUBREG_REG (x)))
10920 record_promoted_value (insn, x);
10923 const char *format = GET_RTX_FORMAT (GET_CODE (x));
10926 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
10930 check_promoted_subreg (insn, XEXP (x, i));
10934 if (XVEC (x, i) != 0)
10935 for (j = 0; j < XVECLEN (x, i); j++)
10936 check_promoted_subreg (insn, XVECEXP (x, i, j));
10942 /* Utility routine for the following function. Verify that all the registers
10943 mentioned in *LOC are valid when *LOC was part of a value set when
10944 label_tick == TICK. Return 0 if some are not.
10946 If REPLACE is nonzero, replace the invalid reference with
10947 (clobber (const_int 0)) and return 1. This replacement is useful because
10948 we often can get useful information about the form of a value (e.g., if
10949 it was produced by a shift that always produces -1 or 0) even though
10950 we don't know exactly what registers it was produced from. */
10953 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
10956 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10957 int len = GET_RTX_LENGTH (GET_CODE (x));
10962 unsigned int regno = REGNO (x);
10963 unsigned int endregno
10964 = regno + (regno < FIRST_PSEUDO_REGISTER
10965 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10968 for (j = regno; j < endregno; j++)
10969 if (reg_stat[j].last_set_invalid
10970 /* If this is a pseudo-register that was only set once and not
10971 live at the beginning of the function, it is always valid. */
10972 || (! (regno >= FIRST_PSEUDO_REGISTER
10973 && REG_N_SETS (regno) == 1
10974 && (! REGNO_REG_SET_P
10975 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
10977 && reg_stat[j].last_set_label > tick))
10980 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10986 /* If this is a memory reference, make sure that there were
10987 no stores after it that might have clobbered the value. We don't
10988 have alias info, so we assume any store invalidates it. */
10989 else if (MEM_P (x) && !MEM_READONLY_P (x)
10990 && INSN_CUID (insn) <= mem_last_set)
10993 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10997 for (i = 0; i < len; i++)
11001 /* Check for identical subexpressions. If x contains
11002 identical subexpression we only have to traverse one of
11004 if (i == 1 && ARITHMETIC_P (x))
11006 /* Note that at this point x0 has already been checked
11007 and found valid. */
11008 rtx x0 = XEXP (x, 0);
11009 rtx x1 = XEXP (x, 1);
11011 /* If x0 and x1 are identical then x is also valid. */
11015 /* If x1 is identical to a subexpression of x0 then
11016 while checking x0, x1 has already been checked. Thus
11017 it is valid and so as x. */
11018 if (ARITHMETIC_P (x0)
11019 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11022 /* If x0 is identical to a subexpression of x1 then x is
11023 valid iff the rest of x1 is valid. */
11024 if (ARITHMETIC_P (x1)
11025 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11027 get_last_value_validate (&XEXP (x1,
11028 x0 == XEXP (x1, 0) ? 1 : 0),
11029 insn, tick, replace);
11032 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11036 /* Don't bother with these. They shouldn't occur anyway. */
11037 else if (fmt[i] == 'E')
11041 /* If we haven't found a reason for it to be invalid, it is valid. */
11045 /* Get the last value assigned to X, if known. Some registers
11046 in the value may be replaced with (clobber (const_int 0)) if their value
11047 is known longer known reliably. */
11050 get_last_value (rtx x)
11052 unsigned int regno;
11055 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11056 then convert it to the desired mode. If this is a paradoxical SUBREG,
11057 we cannot predict what values the "extra" bits might have. */
11058 if (GET_CODE (x) == SUBREG
11059 && subreg_lowpart_p (x)
11060 && (GET_MODE_SIZE (GET_MODE (x))
11061 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11062 && (value = get_last_value (SUBREG_REG (x))) != 0)
11063 return gen_lowpart (GET_MODE (x), value);
11069 value = reg_stat[regno].last_set_value;
11071 /* If we don't have a value, or if it isn't for this basic block and
11072 it's either a hard register, set more than once, or it's a live
11073 at the beginning of the function, return 0.
11075 Because if it's not live at the beginning of the function then the reg
11076 is always set before being used (is never used without being set).
11077 And, if it's set only once, and it's always set before use, then all
11078 uses must have the same last value, even if it's not from this basic
11082 || (reg_stat[regno].last_set_label != label_tick
11083 && (regno < FIRST_PSEUDO_REGISTER
11084 || REG_N_SETS (regno) != 1
11085 || (REGNO_REG_SET_P
11086 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11090 /* If the value was set in a later insn than the ones we are processing,
11091 we can't use it even if the register was only set once. */
11092 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11095 /* If the value has all its registers valid, return it. */
11096 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11097 reg_stat[regno].last_set_label, 0))
11100 /* Otherwise, make a copy and replace any invalid register with
11101 (clobber (const_int 0)). If that fails for some reason, return 0. */
11103 value = copy_rtx (value);
11104 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11105 reg_stat[regno].last_set_label, 1))
11111 /* Return nonzero if expression X refers to a REG or to memory
11112 that is set in an instruction more recent than FROM_CUID. */
11115 use_crosses_set_p (rtx x, int from_cuid)
11119 enum rtx_code code = GET_CODE (x);
11123 unsigned int regno = REGNO (x);
11124 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11125 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11127 #ifdef PUSH_ROUNDING
11128 /* Don't allow uses of the stack pointer to be moved,
11129 because we don't know whether the move crosses a push insn. */
11130 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11133 for (; regno < endreg; regno++)
11134 if (reg_stat[regno].last_set
11135 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11140 if (code == MEM && mem_last_set > from_cuid)
11143 fmt = GET_RTX_FORMAT (code);
11145 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11150 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11151 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11154 else if (fmt[i] == 'e'
11155 && use_crosses_set_p (XEXP (x, i), from_cuid))
11161 /* Define three variables used for communication between the following
11164 static unsigned int reg_dead_regno, reg_dead_endregno;
11165 static int reg_dead_flag;
11167 /* Function called via note_stores from reg_dead_at_p.
11169 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11170 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11173 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11175 unsigned int regno, endregno;
11180 regno = REGNO (dest);
11181 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11182 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11184 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11185 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11188 /* Return nonzero if REG is known to be dead at INSN.
11190 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11191 referencing REG, it is dead. If we hit a SET referencing REG, it is
11192 live. Otherwise, see if it is live or dead at the start of the basic
11193 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11194 must be assumed to be always live. */
11197 reg_dead_at_p (rtx reg, rtx insn)
11202 /* Set variables for reg_dead_at_p_1. */
11203 reg_dead_regno = REGNO (reg);
11204 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11205 ? hard_regno_nregs[reg_dead_regno]
11211 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11212 we allow the machine description to decide whether use-and-clobber
11213 patterns are OK. */
11214 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11216 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11217 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11221 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11222 beginning of function. */
11223 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11224 insn = prev_nonnote_insn (insn))
11226 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11228 return reg_dead_flag == 1 ? 1 : 0;
11230 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11234 /* Get the basic block that we were in. */
11236 block = ENTRY_BLOCK_PTR->next_bb;
11239 FOR_EACH_BB (block)
11240 if (insn == BB_HEAD (block))
11243 if (block == EXIT_BLOCK_PTR)
11247 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11248 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11254 /* Note hard registers in X that are used. This code is similar to
11255 that in flow.c, but much simpler since we don't care about pseudos. */
11258 mark_used_regs_combine (rtx x)
11260 RTX_CODE code = GET_CODE (x);
11261 unsigned int regno;
11274 case ADDR_DIFF_VEC:
11277 /* CC0 must die in the insn after it is set, so we don't need to take
11278 special note of it here. */
11284 /* If we are clobbering a MEM, mark any hard registers inside the
11285 address as used. */
11286 if (MEM_P (XEXP (x, 0)))
11287 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11292 /* A hard reg in a wide mode may really be multiple registers.
11293 If so, mark all of them just like the first. */
11294 if (regno < FIRST_PSEUDO_REGISTER)
11296 unsigned int endregno, r;
11298 /* None of this applies to the stack, frame or arg pointers. */
11299 if (regno == STACK_POINTER_REGNUM
11300 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11301 || regno == HARD_FRAME_POINTER_REGNUM
11303 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11304 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11306 || regno == FRAME_POINTER_REGNUM)
11309 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11310 for (r = regno; r < endregno; r++)
11311 SET_HARD_REG_BIT (newpat_used_regs, r);
11317 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11319 rtx testreg = SET_DEST (x);
11321 while (GET_CODE (testreg) == SUBREG
11322 || GET_CODE (testreg) == ZERO_EXTRACT
11323 || GET_CODE (testreg) == STRICT_LOW_PART)
11324 testreg = XEXP (testreg, 0);
11326 if (MEM_P (testreg))
11327 mark_used_regs_combine (XEXP (testreg, 0));
11329 mark_used_regs_combine (SET_SRC (x));
11337 /* Recursively scan the operands of this expression. */
11340 const char *fmt = GET_RTX_FORMAT (code);
11342 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11345 mark_used_regs_combine (XEXP (x, i));
11346 else if (fmt[i] == 'E')
11350 for (j = 0; j < XVECLEN (x, i); j++)
11351 mark_used_regs_combine (XVECEXP (x, i, j));
11357 /* Remove register number REGNO from the dead registers list of INSN.
11359 Return the note used to record the death, if there was one. */
11362 remove_death (unsigned int regno, rtx insn)
11364 rtx note = find_regno_note (insn, REG_DEAD, regno);
11368 REG_N_DEATHS (regno)--;
11369 remove_note (insn, note);
11375 /* For each register (hardware or pseudo) used within expression X, if its
11376 death is in an instruction with cuid between FROM_CUID (inclusive) and
11377 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11378 list headed by PNOTES.
11380 That said, don't move registers killed by maybe_kill_insn.
11382 This is done when X is being merged by combination into TO_INSN. These
11383 notes will then be distributed as needed. */
11386 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11391 enum rtx_code code = GET_CODE (x);
11395 unsigned int regno = REGNO (x);
11396 rtx where_dead = reg_stat[regno].last_death;
11397 rtx before_dead, after_dead;
11399 /* Don't move the register if it gets killed in between from and to. */
11400 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11401 && ! reg_referenced_p (x, maybe_kill_insn))
11404 /* WHERE_DEAD could be a USE insn made by combine, so first we
11405 make sure that we have insns with valid INSN_CUID values. */
11406 before_dead = where_dead;
11407 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11408 before_dead = PREV_INSN (before_dead);
11410 after_dead = where_dead;
11411 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11412 after_dead = NEXT_INSN (after_dead);
11414 if (before_dead && after_dead
11415 && INSN_CUID (before_dead) >= from_cuid
11416 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11417 || (where_dead != after_dead
11418 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11420 rtx note = remove_death (regno, where_dead);
11422 /* It is possible for the call above to return 0. This can occur
11423 when last_death points to I2 or I1 that we combined with.
11424 In that case make a new note.
11426 We must also check for the case where X is a hard register
11427 and NOTE is a death note for a range of hard registers
11428 including X. In that case, we must put REG_DEAD notes for
11429 the remaining registers in place of NOTE. */
11431 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11432 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11433 > GET_MODE_SIZE (GET_MODE (x))))
11435 unsigned int deadregno = REGNO (XEXP (note, 0));
11436 unsigned int deadend
11437 = (deadregno + hard_regno_nregs[deadregno]
11438 [GET_MODE (XEXP (note, 0))]);
11439 unsigned int ourend
11440 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11443 for (i = deadregno; i < deadend; i++)
11444 if (i < regno || i >= ourend)
11445 REG_NOTES (where_dead)
11446 = gen_rtx_EXPR_LIST (REG_DEAD,
11448 REG_NOTES (where_dead));
11451 /* If we didn't find any note, or if we found a REG_DEAD note that
11452 covers only part of the given reg, and we have a multi-reg hard
11453 register, then to be safe we must check for REG_DEAD notes
11454 for each register other than the first. They could have
11455 their own REG_DEAD notes lying around. */
11456 else if ((note == 0
11458 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11459 < GET_MODE_SIZE (GET_MODE (x)))))
11460 && regno < FIRST_PSEUDO_REGISTER
11461 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11463 unsigned int ourend
11464 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11465 unsigned int i, offset;
11469 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11473 for (i = regno + offset; i < ourend; i++)
11474 move_deaths (regno_reg_rtx[i],
11475 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11478 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11480 XEXP (note, 1) = *pnotes;
11484 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11486 REG_N_DEATHS (regno)++;
11492 else if (GET_CODE (x) == SET)
11494 rtx dest = SET_DEST (x);
11496 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11498 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11499 that accesses one word of a multi-word item, some
11500 piece of everything register in the expression is used by
11501 this insn, so remove any old death. */
11502 /* ??? So why do we test for equality of the sizes? */
11504 if (GET_CODE (dest) == ZERO_EXTRACT
11505 || GET_CODE (dest) == STRICT_LOW_PART
11506 || (GET_CODE (dest) == SUBREG
11507 && (((GET_MODE_SIZE (GET_MODE (dest))
11508 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11509 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11510 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11512 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11516 /* If this is some other SUBREG, we know it replaces the entire
11517 value, so use that as the destination. */
11518 if (GET_CODE (dest) == SUBREG)
11519 dest = SUBREG_REG (dest);
11521 /* If this is a MEM, adjust deaths of anything used in the address.
11522 For a REG (the only other possibility), the entire value is
11523 being replaced so the old value is not used in this insn. */
11526 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11531 else if (GET_CODE (x) == CLOBBER)
11534 len = GET_RTX_LENGTH (code);
11535 fmt = GET_RTX_FORMAT (code);
11537 for (i = 0; i < len; i++)
11542 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11543 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11546 else if (fmt[i] == 'e')
11547 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11551 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11552 pattern of an insn. X must be a REG. */
11555 reg_bitfield_target_p (rtx x, rtx body)
11559 if (GET_CODE (body) == SET)
11561 rtx dest = SET_DEST (body);
11563 unsigned int regno, tregno, endregno, endtregno;
11565 if (GET_CODE (dest) == ZERO_EXTRACT)
11566 target = XEXP (dest, 0);
11567 else if (GET_CODE (dest) == STRICT_LOW_PART)
11568 target = SUBREG_REG (XEXP (dest, 0));
11572 if (GET_CODE (target) == SUBREG)
11573 target = SUBREG_REG (target);
11575 if (!REG_P (target))
11578 tregno = REGNO (target), regno = REGNO (x);
11579 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11580 return target == x;
11582 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11583 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11585 return endregno > tregno && regno < endtregno;
11588 else if (GET_CODE (body) == PARALLEL)
11589 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11590 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11596 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11597 as appropriate. I3 and I2 are the insns resulting from the combination
11598 insns including FROM (I2 may be zero).
11600 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11601 not need REG_DEAD notes because they are being substituted for. This
11602 saves searching in the most common cases.
11604 Each note in the list is either ignored or placed on some insns, depending
11605 on the type of note. */
11608 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11611 rtx note, next_note;
11614 for (note = notes; note; note = next_note)
11616 rtx place = 0, place2 = 0;
11618 /* If this NOTE references a pseudo register, ensure it references
11619 the latest copy of that register. */
11620 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11621 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11622 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11624 next_note = XEXP (note, 1);
11625 switch (REG_NOTE_KIND (note))
11629 /* Doesn't matter much where we put this, as long as it's somewhere.
11630 It is preferable to keep these notes on branches, which is most
11631 likely to be i3. */
11635 case REG_VALUE_PROFILE:
11636 /* Just get rid of this note, as it is unused later anyway. */
11639 case REG_NON_LOCAL_GOTO:
11644 gcc_assert (i2 && JUMP_P (i2));
11649 case REG_EH_REGION:
11650 /* These notes must remain with the call or trapping instruction. */
11653 else if (i2 && CALL_P (i2))
11657 gcc_assert (flag_non_call_exceptions);
11658 if (may_trap_p (i3))
11660 else if (i2 && may_trap_p (i2))
11662 /* ??? Otherwise assume we've combined things such that we
11663 can now prove that the instructions can't trap. Drop the
11664 note in this case. */
11670 /* These notes must remain with the call. It should not be
11671 possible for both I2 and I3 to be a call. */
11676 gcc_assert (i2 && CALL_P (i2));
11682 /* Any clobbers for i3 may still exist, and so we must process
11683 REG_UNUSED notes from that insn.
11685 Any clobbers from i2 or i1 can only exist if they were added by
11686 recog_for_combine. In that case, recog_for_combine created the
11687 necessary REG_UNUSED notes. Trying to keep any original
11688 REG_UNUSED notes from these insns can cause incorrect output
11689 if it is for the same register as the original i3 dest.
11690 In that case, we will notice that the register is set in i3,
11691 and then add a REG_UNUSED note for the destination of i3, which
11692 is wrong. However, it is possible to have REG_UNUSED notes from
11693 i2 or i1 for register which were both used and clobbered, so
11694 we keep notes from i2 or i1 if they will turn into REG_DEAD
11697 /* If this register is set or clobbered in I3, put the note there
11698 unless there is one already. */
11699 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11701 if (from_insn != i3)
11704 if (! (REG_P (XEXP (note, 0))
11705 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11706 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11709 /* Otherwise, if this register is used by I3, then this register
11710 now dies here, so we must put a REG_DEAD note here unless there
11712 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11713 && ! (REG_P (XEXP (note, 0))
11714 ? find_regno_note (i3, REG_DEAD,
11715 REGNO (XEXP (note, 0)))
11716 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11718 PUT_REG_NOTE_KIND (note, REG_DEAD);
11726 /* These notes say something about results of an insn. We can
11727 only support them if they used to be on I3 in which case they
11728 remain on I3. Otherwise they are ignored.
11730 If the note refers to an expression that is not a constant, we
11731 must also ignore the note since we cannot tell whether the
11732 equivalence is still true. It might be possible to do
11733 slightly better than this (we only have a problem if I2DEST
11734 or I1DEST is present in the expression), but it doesn't
11735 seem worth the trouble. */
11737 if (from_insn == i3
11738 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11743 case REG_NO_CONFLICT:
11744 /* These notes say something about how a register is used. They must
11745 be present on any use of the register in I2 or I3. */
11746 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11749 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11759 /* This can show up in several ways -- either directly in the
11760 pattern, or hidden off in the constant pool with (or without?)
11761 a REG_EQUAL note. */
11762 /* ??? Ignore the without-reg_equal-note problem for now. */
11763 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11764 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11765 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11766 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11770 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11771 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11772 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11773 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11781 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11782 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11783 if (place && JUMP_P (place))
11785 rtx label = JUMP_LABEL (place);
11788 JUMP_LABEL (place) = XEXP (note, 0);
11791 gcc_assert (label == XEXP (note, 0));
11792 if (LABEL_P (label))
11793 LABEL_NUSES (label)--;
11797 if (place2 && JUMP_P (place2))
11799 rtx label = JUMP_LABEL (place2);
11802 JUMP_LABEL (place2) = XEXP (note, 0);
11805 gcc_assert (label == XEXP (note, 0));
11806 if (LABEL_P (label))
11807 LABEL_NUSES (label)--;
11814 /* This note says something about the value of a register prior
11815 to the execution of an insn. It is too much trouble to see
11816 if the note is still correct in all situations. It is better
11817 to simply delete it. */
11821 /* If the insn previously containing this note still exists,
11822 put it back where it was. Otherwise move it to the previous
11823 insn. Adjust the corresponding REG_LIBCALL note. */
11824 if (!NOTE_P (from_insn))
11828 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11829 place = prev_real_insn (from_insn);
11831 XEXP (tem, 0) = place;
11832 /* If we're deleting the last remaining instruction of a
11833 libcall sequence, don't add the notes. */
11834 else if (XEXP (note, 0) == from_insn)
11836 /* Don't add the dangling REG_RETVAL note. */
11843 /* This is handled similarly to REG_RETVAL. */
11844 if (!NOTE_P (from_insn))
11848 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11849 place = next_real_insn (from_insn);
11851 XEXP (tem, 0) = place;
11852 /* If we're deleting the last remaining instruction of a
11853 libcall sequence, don't add the notes. */
11854 else if (XEXP (note, 0) == from_insn)
11856 /* Don't add the dangling REG_LIBCALL note. */
11863 /* If the register is used as an input in I3, it dies there.
11864 Similarly for I2, if it is nonzero and adjacent to I3.
11866 If the register is not used as an input in either I3 or I2
11867 and it is not one of the registers we were supposed to eliminate,
11868 there are two possibilities. We might have a non-adjacent I2
11869 or we might have somehow eliminated an additional register
11870 from a computation. For example, we might have had A & B where
11871 we discover that B will always be zero. In this case we will
11872 eliminate the reference to A.
11874 In both cases, we must search to see if we can find a previous
11875 use of A and put the death note there. */
11878 && CALL_P (from_insn)
11879 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11881 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11883 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11884 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11888 && (rtx_equal_p (XEXP (note, 0), elim_i2)
11889 || rtx_equal_p (XEXP (note, 0), elim_i1)))
11894 basic_block bb = this_basic_block;
11896 /* You might think you could search back from FROM_INSN
11897 rather than from I3, but combine tries to split invalid
11898 combined instructions. This can result in the old I2
11899 or I1 moving later in the insn sequence. */
11900 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11902 if (! INSN_P (tem))
11904 if (tem == BB_HEAD (bb))
11909 /* If the register is being set at TEM, see if that is all
11910 TEM is doing. If so, delete TEM. Otherwise, make this
11911 into a REG_UNUSED note instead. Don't delete sets to
11912 global register vars. */
11913 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
11914 || !global_regs[REGNO (XEXP (note, 0))])
11915 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
11917 rtx set = single_set (tem);
11918 rtx inner_dest = 0;
11920 rtx cc0_setter = NULL_RTX;
11924 for (inner_dest = SET_DEST (set);
11925 (GET_CODE (inner_dest) == STRICT_LOW_PART
11926 || GET_CODE (inner_dest) == SUBREG
11927 || GET_CODE (inner_dest) == ZERO_EXTRACT);
11928 inner_dest = XEXP (inner_dest, 0))
11931 /* Verify that it was the set, and not a clobber that
11932 modified the register.
11934 CC0 targets must be careful to maintain setter/user
11935 pairs. If we cannot delete the setter due to side
11936 effects, mark the user with an UNUSED note instead
11939 if (set != 0 && ! side_effects_p (SET_SRC (set))
11940 && rtx_equal_p (XEXP (note, 0), inner_dest)
11942 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11943 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11944 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11948 /* Move the notes and links of TEM elsewhere.
11949 This might delete other dead insns recursively.
11950 First set the pattern to something that won't use
11952 rtx old_notes = REG_NOTES (tem);
11954 PATTERN (tem) = pc_rtx;
11955 REG_NOTES (tem) = NULL;
11957 distribute_notes (old_notes, tem, tem, NULL_RTX,
11958 NULL_RTX, NULL_RTX);
11959 distribute_links (LOG_LINKS (tem));
11961 SET_INSN_DELETED (tem);
11964 /* Delete the setter too. */
11967 PATTERN (cc0_setter) = pc_rtx;
11968 old_notes = REG_NOTES (cc0_setter);
11969 REG_NOTES (cc0_setter) = NULL;
11971 distribute_notes (old_notes, cc0_setter,
11972 cc0_setter, NULL_RTX,
11973 NULL_RTX, NULL_RTX);
11974 distribute_links (LOG_LINKS (cc0_setter));
11976 SET_INSN_DELETED (cc0_setter);
11982 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11984 /* If there isn't already a REG_UNUSED note, put one
11985 here. Do not place a REG_DEAD note, even if
11986 the register is also used here; that would not
11987 match the algorithm used in lifetime analysis
11988 and can cause the consistency check in the
11989 scheduler to fail. */
11990 if (! find_regno_note (tem, REG_UNUSED,
11991 REGNO (XEXP (note, 0))))
11996 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11998 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12000 /* This may not be the correct place for the death
12001 note if FROM_INSN is before TEM, and the reg is
12002 set between FROM_INSN and TEM. The reg might
12003 die two or more times. An existing death note
12004 means we are looking at the wrong live range. */
12006 && INSN_CUID (from_insn) < INSN_CUID (tem)
12007 && find_regno_note (tem, REG_DEAD,
12008 REGNO (XEXP (note, 0))))
12011 if (tem == BB_HEAD (bb))
12018 /* If we are doing a 3->2 combination, and we have a
12019 register which formerly died in i3 and was not used
12020 by i2, which now no longer dies in i3 and is used in
12021 i2 but does not die in i2, and place is between i2
12022 and i3, then we may need to move a link from place to
12024 if (i2 && INSN_UID (place) <= max_uid_cuid
12025 && INSN_CUID (place) > INSN_CUID (i2)
12027 && INSN_CUID (from_insn) > INSN_CUID (i2)
12028 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12030 rtx links = LOG_LINKS (place);
12031 LOG_LINKS (place) = 0;
12032 distribute_links (links);
12037 if (tem == BB_HEAD (bb))
12041 /* We haven't found an insn for the death note and it
12042 is still a REG_DEAD note, but we have hit the beginning
12043 of the block. If the existing life info says the reg
12044 was dead, there's nothing left to do. Otherwise, we'll
12045 need to do a global life update after combine. */
12046 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12047 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12048 REGNO (XEXP (note, 0))))
12049 SET_BIT (refresh_blocks, this_basic_block->index);
12052 /* If the register is set or already dead at PLACE, we needn't do
12053 anything with this note if it is still a REG_DEAD note.
12054 We check here if it is set at all, not if is it totally replaced,
12055 which is what `dead_or_set_p' checks, so also check for it being
12058 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12060 unsigned int regno = REGNO (XEXP (note, 0));
12062 /* Similarly, if the instruction on which we want to place
12063 the note is a noop, we'll need do a global live update
12064 after we remove them in delete_noop_moves. */
12065 if (noop_move_p (place))
12066 SET_BIT (refresh_blocks, this_basic_block->index);
12068 if (dead_or_set_p (place, XEXP (note, 0))
12069 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12071 /* Unless the register previously died in PLACE, clear
12072 last_death. [I no longer understand why this is
12074 if (reg_stat[regno].last_death != place)
12075 reg_stat[regno].last_death = 0;
12079 reg_stat[regno].last_death = place;
12081 /* If this is a death note for a hard reg that is occupying
12082 multiple registers, ensure that we are still using all
12083 parts of the object. If we find a piece of the object
12084 that is unused, we must arrange for an appropriate REG_DEAD
12085 note to be added for it. However, we can't just emit a USE
12086 and tag the note to it, since the register might actually
12087 be dead; so we recourse, and the recursive call then finds
12088 the previous insn that used this register. */
12090 if (place && regno < FIRST_PSEUDO_REGISTER
12091 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12093 unsigned int endregno
12094 = regno + hard_regno_nregs[regno]
12095 [GET_MODE (XEXP (note, 0))];
12099 for (i = regno; i < endregno; i++)
12100 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12101 && ! find_regno_fusage (place, USE, i))
12102 || dead_or_set_regno_p (place, i))
12107 /* Put only REG_DEAD notes for pieces that are
12108 not already dead or set. */
12110 for (i = regno; i < endregno;
12111 i += hard_regno_nregs[i][reg_raw_mode[i]])
12113 rtx piece = regno_reg_rtx[i];
12114 basic_block bb = this_basic_block;
12116 if (! dead_or_set_p (place, piece)
12117 && ! reg_bitfield_target_p (piece,
12121 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12123 distribute_notes (new_note, place, place,
12124 NULL_RTX, NULL_RTX, NULL_RTX);
12126 else if (! refers_to_regno_p (i, i + 1,
12127 PATTERN (place), 0)
12128 && ! find_regno_fusage (place, USE, i))
12129 for (tem = PREV_INSN (place); ;
12130 tem = PREV_INSN (tem))
12132 if (! INSN_P (tem))
12134 if (tem == BB_HEAD (bb))
12136 SET_BIT (refresh_blocks,
12137 this_basic_block->index);
12142 if (dead_or_set_p (tem, piece)
12143 || reg_bitfield_target_p (piece,
12147 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12162 /* Any other notes should not be present at this point in the
12164 gcc_unreachable ();
12169 XEXP (note, 1) = REG_NOTES (place);
12170 REG_NOTES (place) = note;
12172 else if ((REG_NOTE_KIND (note) == REG_DEAD
12173 || REG_NOTE_KIND (note) == REG_UNUSED)
12174 && REG_P (XEXP (note, 0)))
12175 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12179 if ((REG_NOTE_KIND (note) == REG_DEAD
12180 || REG_NOTE_KIND (note) == REG_UNUSED)
12181 && REG_P (XEXP (note, 0)))
12182 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12184 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12185 REG_NOTE_KIND (note),
12187 REG_NOTES (place2));
12192 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12193 I3, I2, and I1 to new locations. This is also called to add a link
12194 pointing at I3 when I3's destination is changed. */
12197 distribute_links (rtx links)
12199 rtx link, next_link;
12201 for (link = links; link; link = next_link)
12207 next_link = XEXP (link, 1);
12209 /* If the insn that this link points to is a NOTE or isn't a single
12210 set, ignore it. In the latter case, it isn't clear what we
12211 can do other than ignore the link, since we can't tell which
12212 register it was for. Such links wouldn't be used by combine
12215 It is not possible for the destination of the target of the link to
12216 have been changed by combine. The only potential of this is if we
12217 replace I3, I2, and I1 by I3 and I2. But in that case the
12218 destination of I2 also remains unchanged. */
12220 if (NOTE_P (XEXP (link, 0))
12221 || (set = single_set (XEXP (link, 0))) == 0)
12224 reg = SET_DEST (set);
12225 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12226 || GET_CODE (reg) == STRICT_LOW_PART)
12227 reg = XEXP (reg, 0);
12229 /* A LOG_LINK is defined as being placed on the first insn that uses
12230 a register and points to the insn that sets the register. Start
12231 searching at the next insn after the target of the link and stop
12232 when we reach a set of the register or the end of the basic block.
12234 Note that this correctly handles the link that used to point from
12235 I3 to I2. Also note that not much searching is typically done here
12236 since most links don't point very far away. */
12238 for (insn = NEXT_INSN (XEXP (link, 0));
12239 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12240 || BB_HEAD (this_basic_block->next_bb) != insn));
12241 insn = NEXT_INSN (insn))
12242 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12244 if (reg_referenced_p (reg, PATTERN (insn)))
12248 else if (CALL_P (insn)
12249 && find_reg_fusage (insn, USE, reg))
12254 else if (INSN_P (insn) && reg_set_p (reg, insn))
12257 /* If we found a place to put the link, place it there unless there
12258 is already a link to the same insn as LINK at that point. */
12264 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12265 if (XEXP (link2, 0) == XEXP (link, 0))
12270 XEXP (link, 1) = LOG_LINKS (place);
12271 LOG_LINKS (place) = link;
12273 /* Set added_links_insn to the earliest insn we added a
12275 if (added_links_insn == 0
12276 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12277 added_links_insn = place;
12283 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12284 Check whether the expression pointer to by LOC is a register or
12285 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12286 Otherwise return zero. */
12289 unmentioned_reg_p_1 (rtx *loc, void *expr)
12294 && (REG_P (x) || MEM_P (x))
12295 && ! reg_mentioned_p (x, (rtx) expr))
12300 /* Check for any register or memory mentioned in EQUIV that is not
12301 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12302 of EXPR where some registers may have been replaced by constants. */
12305 unmentioned_reg_p (rtx equiv, rtx expr)
12307 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12310 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12313 insn_cuid (rtx insn)
12315 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12316 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12317 insn = NEXT_INSN (insn);
12319 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12321 return INSN_CUID (insn);
12325 dump_combine_stats (FILE *file)
12329 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12330 combine_attempts, combine_merges, combine_extras, combine_successes);
12334 dump_combine_total_stats (FILE *file)
12338 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12339 total_attempts, total_merges, total_extras, total_successes);
12344 gate_handle_combine (void)
12346 return (optimize > 0);
12349 /* Try combining insns through substitution. */
12351 rest_of_handle_combine (void)
12353 int rebuild_jump_labels_after_combine
12354 = combine_instructions (get_insns (), max_reg_num ());
12356 /* Combining insns may have turned an indirect jump into a
12357 direct jump. Rebuild the JUMP_LABEL fields of jumping
12359 if (rebuild_jump_labels_after_combine)
12361 timevar_push (TV_JUMP);
12362 rebuild_jump_labels (get_insns ());
12363 timevar_pop (TV_JUMP);
12365 delete_dead_jumptables ();
12366 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12370 struct tree_opt_pass pass_combine =
12372 "combine", /* name */
12373 gate_handle_combine, /* gate */
12374 rest_of_handle_combine, /* execute */
12377 0, /* static_pass_number */
12378 TV_COMBINE, /* tv_id */
12379 0, /* properties_required */
12380 0, /* properties_provided */
12381 0, /* properties_destroyed */
12382 0, /* todo_flags_start */
12384 TODO_ggc_collect, /* todo_flags_finish */
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