1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
121 /* Vector mapping INSN_UIDs to cuids.
122 The cuids are like uids but increase monotonically always.
123 Combine always uses cuids so that it can compare them.
124 But actually renumbering the uids, which we used to do,
125 proves to be a bad idea because it makes it hard to compare
126 the dumps produced by earlier passes with those from later passes. */
128 static int *uid_cuid;
129 static int max_uid_cuid;
131 /* Get the cuid of an insn. */
133 #define INSN_CUID(INSN) \
134 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
136 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
137 BITS_PER_WORD would invoke undefined behavior. Work around it. */
139 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
140 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
142 /* Maximum register number, which is the size of the tables below. */
144 static unsigned int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
242 static struct reg_stat *reg_stat;
244 /* Record the cuid of the last insn that invalidated memory
245 (anything that writes memory, and subroutine calls, but not pushes). */
247 static int mem_last_set;
249 /* Record the cuid of the last CALL_INSN
250 so we can tell whether a potential combination crosses any calls. */
252 static int last_call_cuid;
254 /* When `subst' is called, this is the insn that is being modified
255 (by combining in a previous insn). The PATTERN of this insn
256 is still the old pattern partially modified and it should not be
257 looked at, but this may be used to examine the successors of the insn
258 to judge whether a simplification is valid. */
260 static rtx subst_insn;
262 /* This is the lowest CUID that `subst' is currently dealing with.
263 get_last_value will not return a value if the register was set at or
264 after this CUID. If not for this mechanism, we could get confused if
265 I2 or I1 in try_combine were an insn that used the old value of a register
266 to obtain a new value. In that case, we might erroneously get the
267 new value of the register when we wanted the old one. */
269 static int subst_low_cuid;
271 /* This contains any hard registers that are used in newpat; reg_dead_at_p
272 must consider all these registers to be always live. */
274 static HARD_REG_SET newpat_used_regs;
276 /* This is an insn to which a LOG_LINKS entry has been added. If this
277 insn is the earlier than I2 or I3, combine should rescan starting at
280 static rtx added_links_insn;
282 /* Basic block in which we are performing combines. */
283 static basic_block this_basic_block;
285 /* A bitmap indicating which blocks had registers go dead at entry.
286 After combine, we'll need to re-do global life analysis with
287 those blocks as starting points. */
288 static sbitmap refresh_blocks;
290 /* The following array records the insn_rtx_cost for every insn
291 in the instruction stream. */
293 static int *uid_insn_cost;
295 /* Length of the currently allocated uid_insn_cost array. */
297 static int last_insn_cost;
299 /* Incremented for each label. */
301 static int label_tick;
303 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
304 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
306 static enum machine_mode nonzero_bits_mode;
308 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
309 be safely used. It is zero while computing them and after combine has
310 completed. This former test prevents propagating values based on
311 previously set values, which can be incorrect if a variable is modified
314 static int nonzero_sign_valid;
317 /* Record one modification to rtl structure
318 to be undone by storing old_contents into *where.
319 is_int is 1 if the contents are an int. */
325 union {rtx r; int i;} old_contents;
326 union {rtx *r; int *i;} where;
329 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
330 num_undo says how many are currently recorded.
332 other_insn is nonzero if we have modified some other insn in the process
333 of working on subst_insn. It must be verified too. */
342 static struct undobuf undobuf;
344 /* Number of times the pseudo being substituted for
345 was found and replaced. */
347 static int n_occurrences;
349 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
351 unsigned HOST_WIDE_INT,
352 unsigned HOST_WIDE_INT *);
353 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
355 unsigned int, unsigned int *);
356 static void do_SUBST (rtx *, rtx);
357 static void do_SUBST_INT (int *, int);
358 static void init_reg_last (void);
359 static void setup_incoming_promotions (void);
360 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
361 static int cant_combine_insn_p (rtx);
362 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
363 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
364 static int contains_muldiv (rtx);
365 static rtx try_combine (rtx, rtx, rtx, int *);
366 static void undo_all (void);
367 static void undo_commit (void);
368 static rtx *find_split_point (rtx *, rtx);
369 static rtx subst (rtx, rtx, rtx, int, int);
370 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
371 static rtx simplify_if_then_else (rtx);
372 static rtx simplify_set (rtx);
373 static rtx simplify_logical (rtx);
374 static rtx expand_compound_operation (rtx);
375 static rtx expand_field_assignment (rtx);
376 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
377 rtx, unsigned HOST_WIDE_INT, int, int, int);
378 static rtx extract_left_shift (rtx, int);
379 static rtx make_compound_operation (rtx, enum rtx_code);
380 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
381 unsigned HOST_WIDE_INT *);
382 static rtx force_to_mode (rtx, enum machine_mode,
383 unsigned HOST_WIDE_INT, rtx, int);
384 static rtx if_then_else_cond (rtx, rtx *, rtx *);
385 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
386 static int rtx_equal_for_field_assignment_p (rtx, rtx);
387 static rtx make_field_assignment (rtx);
388 static rtx apply_distributive_law (rtx);
389 static rtx distribute_and_simplify_rtx (rtx, int);
390 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
391 unsigned HOST_WIDE_INT);
392 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
393 HOST_WIDE_INT, enum machine_mode, int *);
394 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
396 static int recog_for_combine (rtx *, rtx, rtx *);
397 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
398 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
399 static void update_table_tick (rtx);
400 static void record_value_for_reg (rtx, rtx, rtx);
401 static void check_promoted_subreg (rtx, rtx);
402 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
403 static void record_dead_and_set_regs (rtx);
404 static int get_last_value_validate (rtx *, rtx, int, int);
405 static rtx get_last_value (rtx);
406 static int use_crosses_set_p (rtx, int);
407 static void reg_dead_at_p_1 (rtx, rtx, void *);
408 static int reg_dead_at_p (rtx, rtx);
409 static void move_deaths (rtx, rtx, int, rtx, rtx *);
410 static int reg_bitfield_target_p (rtx, rtx);
411 static void distribute_notes (rtx, rtx, rtx, rtx);
412 static void distribute_links (rtx);
413 static void mark_used_regs_combine (rtx);
414 static int insn_cuid (rtx);
415 static void record_promoted_value (rtx, rtx);
416 static int unmentioned_reg_p_1 (rtx *, void *);
417 static bool unmentioned_reg_p (rtx, rtx);
420 /* It is not safe to use ordinary gen_lowpart in combine.
421 See comments in gen_lowpart_for_combine. */
422 #undef RTL_HOOKS_GEN_LOWPART
423 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
425 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
426 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
428 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
429 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
431 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
434 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
435 insn. The substitution can be undone by undo_all. If INTO is already
436 set to NEWVAL, do not record this change. Because computing NEWVAL might
437 also call SUBST, we have to compute it before we put anything into
441 do_SUBST (rtx *into, rtx newval)
446 if (oldval == newval)
449 /* We'd like to catch as many invalid transformations here as
450 possible. Unfortunately, there are way too many mode changes
451 that are perfectly valid, so we'd waste too much effort for
452 little gain doing the checks here. Focus on catching invalid
453 transformations involving integer constants. */
454 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
455 && GET_CODE (newval) == CONST_INT)
457 /* Sanity check that we're replacing oldval with a CONST_INT
458 that is a valid sign-extension for the original mode. */
459 gcc_assert (INTVAL (newval)
460 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
462 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
463 CONST_INT is not valid, because after the replacement, the
464 original mode would be gone. Unfortunately, we can't tell
465 when do_SUBST is called to replace the operand thereof, so we
466 perform this test on oldval instead, checking whether an
467 invalid replacement took place before we got here. */
468 gcc_assert (!(GET_CODE (oldval) == SUBREG
469 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
470 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
471 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
475 buf = undobuf.frees, undobuf.frees = buf->next;
477 buf = xmalloc (sizeof (struct undo));
481 buf->old_contents.r = oldval;
484 buf->next = undobuf.undos, undobuf.undos = buf;
487 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
489 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
490 for the value of a HOST_WIDE_INT value (including CONST_INT) is
494 do_SUBST_INT (int *into, int newval)
499 if (oldval == newval)
503 buf = undobuf.frees, undobuf.frees = buf->next;
505 buf = xmalloc (sizeof (struct undo));
509 buf->old_contents.i = oldval;
512 buf->next = undobuf.undos, undobuf.undos = buf;
515 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
517 /* Subroutine of try_combine. Determine whether the combine replacement
518 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
519 that the original instruction sequence I1, I2 and I3. Note that I1
520 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
521 costs of all instructions can be estimated, and the replacements are
522 more expensive than the original sequence. */
525 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
527 int i1_cost, i2_cost, i3_cost;
528 int new_i2_cost, new_i3_cost;
529 int old_cost, new_cost;
531 /* Lookup the original insn_rtx_costs. */
532 i2_cost = INSN_UID (i2) <= last_insn_cost
533 ? uid_insn_cost[INSN_UID (i2)] : 0;
534 i3_cost = INSN_UID (i3) <= last_insn_cost
535 ? uid_insn_cost[INSN_UID (i3)] : 0;
539 i1_cost = INSN_UID (i1) <= last_insn_cost
540 ? uid_insn_cost[INSN_UID (i1)] : 0;
541 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
542 ? i1_cost + i2_cost + i3_cost : 0;
546 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
550 /* Calculate the replacement insn_rtx_costs. */
551 new_i3_cost = insn_rtx_cost (newpat);
554 new_i2_cost = insn_rtx_cost (newi2pat);
555 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
556 ? new_i2_cost + new_i3_cost : 0;
560 new_cost = new_i3_cost;
564 if (undobuf.other_insn)
566 int old_other_cost, new_other_cost;
568 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
569 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
570 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
571 if (old_other_cost > 0 && new_other_cost > 0)
573 old_cost += old_other_cost;
574 new_cost += new_other_cost;
580 /* Disallow this recombination if both new_cost and old_cost are
581 greater than zero, and new_cost is greater than old cost. */
583 && new_cost > old_cost)
590 "rejecting combination of insns %d, %d and %d\n",
591 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
592 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
593 i1_cost, i2_cost, i3_cost, old_cost);
598 "rejecting combination of insns %d and %d\n",
599 INSN_UID (i2), INSN_UID (i3));
600 fprintf (dump_file, "original costs %d + %d = %d\n",
601 i2_cost, i3_cost, old_cost);
606 fprintf (dump_file, "replacement costs %d + %d = %d\n",
607 new_i2_cost, new_i3_cost, new_cost);
610 fprintf (dump_file, "replacement cost %d\n", new_cost);
616 /* Update the uid_insn_cost array with the replacement costs. */
617 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
618 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
620 uid_insn_cost[INSN_UID (i1)] = 0;
625 /* Main entry point for combiner. F is the first insn of the function.
626 NREGS is the first unused pseudo-reg number.
628 Return nonzero if the combiner has turned an indirect jump
629 instruction into a direct jump. */
631 combine_instructions (rtx f, unsigned int nregs)
638 rtx links, nextlinks;
640 int new_direct_jump_p = 0;
642 combine_attempts = 0;
645 combine_successes = 0;
647 combine_max_regno = nregs;
649 rtl_hooks = combine_rtl_hooks;
651 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
653 init_recog_no_volatile ();
655 /* Compute maximum uid value so uid_cuid can be allocated. */
657 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
658 if (INSN_UID (insn) > i)
661 uid_cuid = xmalloc ((i + 1) * sizeof (int));
664 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
666 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
667 problems when, for example, we have j <<= 1 in a loop. */
669 nonzero_sign_valid = 0;
671 /* Compute the mapping from uids to cuids.
672 Cuids are numbers assigned to insns, like uids,
673 except that cuids increase monotonically through the code.
675 Scan all SETs and see if we can deduce anything about what
676 bits are known to be zero for some registers and how many copies
677 of the sign bit are known to exist for those registers.
679 Also set any known values so that we can use it while searching
680 for what bits are known to be set. */
684 setup_incoming_promotions ();
686 refresh_blocks = sbitmap_alloc (last_basic_block);
687 sbitmap_zero (refresh_blocks);
689 /* Allocate array of current insn_rtx_costs. */
690 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
691 last_insn_cost = max_uid_cuid;
693 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
695 uid_cuid[INSN_UID (insn)] = ++i;
701 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
703 record_dead_and_set_regs (insn);
706 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
707 if (REG_NOTE_KIND (links) == REG_INC)
708 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
712 /* Record the current insn_rtx_cost of this instruction. */
713 if (NONJUMP_INSN_P (insn))
714 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
716 fprintf(dump_file, "insn_cost %d: %d\n",
717 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
724 nonzero_sign_valid = 1;
726 /* Now scan all the insns in forward order. */
732 setup_incoming_promotions ();
734 FOR_EACH_BB (this_basic_block)
736 for (insn = BB_HEAD (this_basic_block);
737 insn != NEXT_INSN (BB_END (this_basic_block));
738 insn = next ? next : NEXT_INSN (insn))
745 else if (INSN_P (insn))
747 /* See if we know about function return values before this
748 insn based upon SUBREG flags. */
749 check_promoted_subreg (insn, PATTERN (insn));
751 /* Try this insn with each insn it links back to. */
753 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
754 if ((next = try_combine (insn, XEXP (links, 0),
755 NULL_RTX, &new_direct_jump_p)) != 0)
758 /* Try each sequence of three linked insns ending with this one. */
760 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
762 rtx link = XEXP (links, 0);
764 /* If the linked insn has been replaced by a note, then there
765 is no point in pursuing this chain any further. */
769 for (nextlinks = LOG_LINKS (link);
771 nextlinks = XEXP (nextlinks, 1))
772 if ((next = try_combine (insn, link,
774 &new_direct_jump_p)) != 0)
779 /* Try to combine a jump insn that uses CC0
780 with a preceding insn that sets CC0, and maybe with its
781 logical predecessor as well.
782 This is how we make decrement-and-branch insns.
783 We need this special code because data flow connections
784 via CC0 do not get entered in LOG_LINKS. */
787 && (prev = prev_nonnote_insn (insn)) != 0
788 && NONJUMP_INSN_P (prev)
789 && sets_cc0_p (PATTERN (prev)))
791 if ((next = try_combine (insn, prev,
792 NULL_RTX, &new_direct_jump_p)) != 0)
795 for (nextlinks = LOG_LINKS (prev); nextlinks;
796 nextlinks = XEXP (nextlinks, 1))
797 if ((next = try_combine (insn, prev,
799 &new_direct_jump_p)) != 0)
803 /* Do the same for an insn that explicitly references CC0. */
804 if (NONJUMP_INSN_P (insn)
805 && (prev = prev_nonnote_insn (insn)) != 0
806 && NONJUMP_INSN_P (prev)
807 && sets_cc0_p (PATTERN (prev))
808 && GET_CODE (PATTERN (insn)) == SET
809 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
811 if ((next = try_combine (insn, prev,
812 NULL_RTX, &new_direct_jump_p)) != 0)
815 for (nextlinks = LOG_LINKS (prev); nextlinks;
816 nextlinks = XEXP (nextlinks, 1))
817 if ((next = try_combine (insn, prev,
819 &new_direct_jump_p)) != 0)
823 /* Finally, see if any of the insns that this insn links to
824 explicitly references CC0. If so, try this insn, that insn,
825 and its predecessor if it sets CC0. */
826 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
827 if (NONJUMP_INSN_P (XEXP (links, 0))
828 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
829 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
830 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
831 && NONJUMP_INSN_P (prev)
832 && sets_cc0_p (PATTERN (prev))
833 && (next = try_combine (insn, XEXP (links, 0),
834 prev, &new_direct_jump_p)) != 0)
838 /* Try combining an insn with two different insns whose results it
840 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
841 for (nextlinks = XEXP (links, 1); nextlinks;
842 nextlinks = XEXP (nextlinks, 1))
843 if ((next = try_combine (insn, XEXP (links, 0),
845 &new_direct_jump_p)) != 0)
848 /* Try this insn with each REG_EQUAL note it links back to. */
849 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
852 rtx temp = XEXP (links, 0);
853 if ((set = single_set (temp)) != 0
854 && (note = find_reg_equal_equiv_note (temp)) != 0
855 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
856 /* Avoid using a register that may already been marked
857 dead by an earlier instruction. */
858 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
860 /* Temporarily replace the set's source with the
861 contents of the REG_EQUAL note. The insn will
862 be deleted or recognized by try_combine. */
863 rtx orig = SET_SRC (set);
864 SET_SRC (set) = XEXP (note, 0);
865 next = try_combine (insn, temp, NULL_RTX,
869 SET_SRC (set) = orig;
874 record_dead_and_set_regs (insn);
883 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
884 BASIC_BLOCK (i)->flags |= BB_DIRTY);
885 new_direct_jump_p |= purge_all_dead_edges (0);
886 delete_noop_moves ();
888 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
889 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
890 | PROP_KILL_DEAD_CODE);
893 sbitmap_free (refresh_blocks);
894 free (uid_insn_cost);
899 struct undo *undo, *next;
900 for (undo = undobuf.frees; undo; undo = next)
908 total_attempts += combine_attempts;
909 total_merges += combine_merges;
910 total_extras += combine_extras;
911 total_successes += combine_successes;
913 nonzero_sign_valid = 0;
914 rtl_hooks = general_rtl_hooks;
916 /* Make recognizer allow volatile MEMs again. */
919 return new_direct_jump_p;
922 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
928 for (i = 0; i < combine_max_regno; i++)
929 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
932 /* Set up any promoted values for incoming argument registers. */
935 setup_incoming_promotions (void)
939 enum machine_mode mode;
941 rtx first = get_insns ();
943 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
945 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
946 /* Check whether this register can hold an incoming pointer
947 argument. FUNCTION_ARG_REGNO_P tests outgoing register
948 numbers, so translate if necessary due to register windows. */
949 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
950 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
953 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
956 gen_rtx_CLOBBER (mode, const0_rtx)));
961 /* Called via note_stores. If X is a pseudo that is narrower than
962 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
964 If we are setting only a portion of X and we can't figure out what
965 portion, assume all bits will be used since we don't know what will
968 Similarly, set how many bits of X are known to be copies of the sign bit
969 at all locations in the function. This is the smallest number implied
973 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
974 void *data ATTRIBUTE_UNUSED)
979 && REGNO (x) >= FIRST_PSEUDO_REGISTER
980 /* If this register is undefined at the start of the file, we can't
981 say what its contents were. */
982 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
983 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
985 if (set == 0 || GET_CODE (set) == CLOBBER)
987 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
988 reg_stat[REGNO (x)].sign_bit_copies = 1;
992 /* If this is a complex assignment, see if we can convert it into a
993 simple assignment. */
994 set = expand_field_assignment (set);
996 /* If this is a simple assignment, or we have a paradoxical SUBREG,
997 set what we know about X. */
999 if (SET_DEST (set) == x
1000 || (GET_CODE (SET_DEST (set)) == SUBREG
1001 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1002 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1003 && SUBREG_REG (SET_DEST (set)) == x))
1005 rtx src = SET_SRC (set);
1007 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1008 /* If X is narrower than a word and SRC is a non-negative
1009 constant that would appear negative in the mode of X,
1010 sign-extend it for use in reg_stat[].nonzero_bits because some
1011 machines (maybe most) will actually do the sign-extension
1012 and this is the conservative approach.
1014 ??? For 2.5, try to tighten up the MD files in this regard
1015 instead of this kludge. */
1017 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1018 && GET_CODE (src) == CONST_INT
1020 && 0 != (INTVAL (src)
1021 & ((HOST_WIDE_INT) 1
1022 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1023 src = GEN_INT (INTVAL (src)
1024 | ((HOST_WIDE_INT) (-1)
1025 << GET_MODE_BITSIZE (GET_MODE (x))));
1028 /* Don't call nonzero_bits if it cannot change anything. */
1029 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1030 reg_stat[REGNO (x)].nonzero_bits
1031 |= nonzero_bits (src, nonzero_bits_mode);
1032 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1033 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1034 || reg_stat[REGNO (x)].sign_bit_copies > num)
1035 reg_stat[REGNO (x)].sign_bit_copies = num;
1039 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1040 reg_stat[REGNO (x)].sign_bit_copies = 1;
1045 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1046 insns that were previously combined into I3 or that will be combined
1047 into the merger of INSN and I3.
1049 Return 0 if the combination is not allowed for any reason.
1051 If the combination is allowed, *PDEST will be set to the single
1052 destination of INSN and *PSRC to the single source, and this function
1056 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1057 rtx *pdest, rtx *psrc)
1060 rtx set = 0, src, dest;
1065 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1066 && next_active_insn (succ) == i3)
1067 : next_active_insn (insn) == i3);
1069 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1070 or a PARALLEL consisting of such a SET and CLOBBERs.
1072 If INSN has CLOBBER parallel parts, ignore them for our processing.
1073 By definition, these happen during the execution of the insn. When it
1074 is merged with another insn, all bets are off. If they are, in fact,
1075 needed and aren't also supplied in I3, they may be added by
1076 recog_for_combine. Otherwise, it won't match.
1078 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1081 Get the source and destination of INSN. If more than one, can't
1084 if (GET_CODE (PATTERN (insn)) == SET)
1085 set = PATTERN (insn);
1086 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1087 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1089 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1091 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1094 switch (GET_CODE (elt))
1096 /* This is important to combine floating point insns
1097 for the SH4 port. */
1099 /* Combining an isolated USE doesn't make sense.
1100 We depend here on combinable_i3pat to reject them. */
1101 /* The code below this loop only verifies that the inputs of
1102 the SET in INSN do not change. We call reg_set_between_p
1103 to verify that the REG in the USE does not change between
1105 If the USE in INSN was for a pseudo register, the matching
1106 insn pattern will likely match any register; combining this
1107 with any other USE would only be safe if we knew that the
1108 used registers have identical values, or if there was
1109 something to tell them apart, e.g. different modes. For
1110 now, we forgo such complicated tests and simply disallow
1111 combining of USES of pseudo registers with any other USE. */
1112 if (REG_P (XEXP (elt, 0))
1113 && GET_CODE (PATTERN (i3)) == PARALLEL)
1115 rtx i3pat = PATTERN (i3);
1116 int i = XVECLEN (i3pat, 0) - 1;
1117 unsigned int regno = REGNO (XEXP (elt, 0));
1121 rtx i3elt = XVECEXP (i3pat, 0, i);
1123 if (GET_CODE (i3elt) == USE
1124 && REG_P (XEXP (i3elt, 0))
1125 && (REGNO (XEXP (i3elt, 0)) == regno
1126 ? reg_set_between_p (XEXP (elt, 0),
1127 PREV_INSN (insn), i3)
1128 : regno >= FIRST_PSEUDO_REGISTER))
1135 /* We can ignore CLOBBERs. */
1140 /* Ignore SETs whose result isn't used but not those that
1141 have side-effects. */
1142 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1143 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1144 || INTVAL (XEXP (note, 0)) <= 0)
1145 && ! side_effects_p (elt))
1148 /* If we have already found a SET, this is a second one and
1149 so we cannot combine with this insn. */
1157 /* Anything else means we can't combine. */
1163 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1164 so don't do anything with it. */
1165 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1174 set = expand_field_assignment (set);
1175 src = SET_SRC (set), dest = SET_DEST (set);
1177 /* Don't eliminate a store in the stack pointer. */
1178 if (dest == stack_pointer_rtx
1179 /* Don't combine with an insn that sets a register to itself if it has
1180 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1181 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1182 /* Can't merge an ASM_OPERANDS. */
1183 || GET_CODE (src) == ASM_OPERANDS
1184 /* Can't merge a function call. */
1185 || GET_CODE (src) == CALL
1186 /* Don't eliminate a function call argument. */
1188 && (find_reg_fusage (i3, USE, dest)
1190 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1191 && global_regs[REGNO (dest)])))
1192 /* Don't substitute into an incremented register. */
1193 || FIND_REG_INC_NOTE (i3, dest)
1194 || (succ && FIND_REG_INC_NOTE (succ, dest))
1195 /* Don't substitute into a non-local goto, this confuses CFG. */
1196 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1198 /* Don't combine the end of a libcall into anything. */
1199 /* ??? This gives worse code, and appears to be unnecessary, since no
1200 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1201 use REG_RETVAL notes for noconflict blocks, but other code here
1202 makes sure that those insns don't disappear. */
1203 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1205 /* Make sure that DEST is not used after SUCC but before I3. */
1206 || (succ && ! all_adjacent
1207 && reg_used_between_p (dest, succ, i3))
1208 /* Make sure that the value that is to be substituted for the register
1209 does not use any registers whose values alter in between. However,
1210 If the insns are adjacent, a use can't cross a set even though we
1211 think it might (this can happen for a sequence of insns each setting
1212 the same destination; last_set of that register might point to
1213 a NOTE). If INSN has a REG_EQUIV note, the register is always
1214 equivalent to the memory so the substitution is valid even if there
1215 are intervening stores. Also, don't move a volatile asm or
1216 UNSPEC_VOLATILE across any other insns. */
1219 || ! find_reg_note (insn, REG_EQUIV, src))
1220 && use_crosses_set_p (src, INSN_CUID (insn)))
1221 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1222 || GET_CODE (src) == UNSPEC_VOLATILE))
1223 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1224 better register allocation by not doing the combine. */
1225 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1226 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1227 /* Don't combine across a CALL_INSN, because that would possibly
1228 change whether the life span of some REGs crosses calls or not,
1229 and it is a pain to update that information.
1230 Exception: if source is a constant, moving it later can't hurt.
1231 Accept that special case, because it helps -fforce-addr a lot. */
1232 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1235 /* DEST must either be a REG or CC0. */
1238 /* If register alignment is being enforced for multi-word items in all
1239 cases except for parameters, it is possible to have a register copy
1240 insn referencing a hard register that is not allowed to contain the
1241 mode being copied and which would not be valid as an operand of most
1242 insns. Eliminate this problem by not combining with such an insn.
1244 Also, on some machines we don't want to extend the life of a hard
1248 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1249 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1250 /* Don't extend the life of a hard register unless it is
1251 user variable (if we have few registers) or it can't
1252 fit into the desired register (meaning something special
1254 Also avoid substituting a return register into I3, because
1255 reload can't handle a conflict with constraints of other
1257 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1258 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1261 else if (GET_CODE (dest) != CC0)
1265 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1266 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1267 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1269 /* Don't substitute for a register intended as a clobberable
1271 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1272 if (rtx_equal_p (reg, dest))
1275 /* If the clobber represents an earlyclobber operand, we must not
1276 substitute an expression containing the clobbered register.
1277 As we do not analyze the constraint strings here, we have to
1278 make the conservative assumption. However, if the register is
1279 a fixed hard reg, the clobber cannot represent any operand;
1280 we leave it up to the machine description to either accept or
1281 reject use-and-clobber patterns. */
1283 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1284 || !fixed_regs[REGNO (reg)])
1285 if (reg_overlap_mentioned_p (reg, src))
1289 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1290 or not), reject, unless nothing volatile comes between it and I3 */
1292 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1294 /* Make sure succ doesn't contain a volatile reference. */
1295 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1298 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1299 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1303 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1304 to be an explicit register variable, and was chosen for a reason. */
1306 if (GET_CODE (src) == ASM_OPERANDS
1307 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1310 /* If there are any volatile insns between INSN and I3, reject, because
1311 they might affect machine state. */
1313 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1314 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1317 /* If INSN or I2 contains an autoincrement or autodecrement,
1318 make sure that register is not used between there and I3,
1319 and not already used in I3 either.
1320 Also insist that I3 not be a jump; if it were one
1321 and the incremented register were spilled, we would lose. */
1324 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1325 if (REG_NOTE_KIND (link) == REG_INC
1327 || reg_used_between_p (XEXP (link, 0), insn, i3)
1328 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1333 /* Don't combine an insn that follows a CC0-setting insn.
1334 An insn that uses CC0 must not be separated from the one that sets it.
1335 We do, however, allow I2 to follow a CC0-setting insn if that insn
1336 is passed as I1; in that case it will be deleted also.
1337 We also allow combining in this case if all the insns are adjacent
1338 because that would leave the two CC0 insns adjacent as well.
1339 It would be more logical to test whether CC0 occurs inside I1 or I2,
1340 but that would be much slower, and this ought to be equivalent. */
1342 p = prev_nonnote_insn (insn);
1343 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1348 /* If we get here, we have passed all the tests and the combination is
1357 /* LOC is the location within I3 that contains its pattern or the component
1358 of a PARALLEL of the pattern. We validate that it is valid for combining.
1360 One problem is if I3 modifies its output, as opposed to replacing it
1361 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1362 so would produce an insn that is not equivalent to the original insns.
1366 (set (reg:DI 101) (reg:DI 100))
1367 (set (subreg:SI (reg:DI 101) 0) <foo>)
1369 This is NOT equivalent to:
1371 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1372 (set (reg:DI 101) (reg:DI 100))])
1374 Not only does this modify 100 (in which case it might still be valid
1375 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1377 We can also run into a problem if I2 sets a register that I1
1378 uses and I1 gets directly substituted into I3 (not via I2). In that
1379 case, we would be getting the wrong value of I2DEST into I3, so we
1380 must reject the combination. This case occurs when I2 and I1 both
1381 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1382 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1383 of a SET must prevent combination from occurring.
1385 Before doing the above check, we first try to expand a field assignment
1386 into a set of logical operations.
1388 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1389 we place a register that is both set and used within I3. If more than one
1390 such register is detected, we fail.
1392 Return 1 if the combination is valid, zero otherwise. */
1395 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1396 int i1_not_in_src, rtx *pi3dest_killed)
1400 if (GET_CODE (x) == SET)
1403 rtx dest = SET_DEST (set);
1404 rtx src = SET_SRC (set);
1405 rtx inner_dest = dest;
1407 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1408 || GET_CODE (inner_dest) == SUBREG
1409 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1410 inner_dest = XEXP (inner_dest, 0);
1412 /* Check for the case where I3 modifies its output, as discussed
1413 above. We don't want to prevent pseudos from being combined
1414 into the address of a MEM, so only prevent the combination if
1415 i1 or i2 set the same MEM. */
1416 if ((inner_dest != dest &&
1417 (!MEM_P (inner_dest)
1418 || rtx_equal_p (i2dest, inner_dest)
1419 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1420 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1421 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1423 /* This is the same test done in can_combine_p except we can't test
1424 all_adjacent; we don't have to, since this instruction will stay
1425 in place, thus we are not considering increasing the lifetime of
1428 Also, if this insn sets a function argument, combining it with
1429 something that might need a spill could clobber a previous
1430 function argument; the all_adjacent test in can_combine_p also
1431 checks this; here, we do a more specific test for this case. */
1433 || (REG_P (inner_dest)
1434 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1435 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1436 GET_MODE (inner_dest))))
1437 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1440 /* If DEST is used in I3, it is being killed in this insn,
1441 so record that for later.
1442 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1443 STACK_POINTER_REGNUM, since these are always considered to be
1444 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1445 if (pi3dest_killed && REG_P (dest)
1446 && reg_referenced_p (dest, PATTERN (i3))
1447 && REGNO (dest) != FRAME_POINTER_REGNUM
1448 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1449 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1451 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1452 && (REGNO (dest) != ARG_POINTER_REGNUM
1453 || ! fixed_regs [REGNO (dest)])
1455 && REGNO (dest) != STACK_POINTER_REGNUM)
1457 if (*pi3dest_killed)
1460 *pi3dest_killed = dest;
1464 else if (GET_CODE (x) == PARALLEL)
1468 for (i = 0; i < XVECLEN (x, 0); i++)
1469 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1470 i1_not_in_src, pi3dest_killed))
1477 /* Return 1 if X is an arithmetic expression that contains a multiplication
1478 and division. We don't count multiplications by powers of two here. */
1481 contains_muldiv (rtx x)
1483 switch (GET_CODE (x))
1485 case MOD: case DIV: case UMOD: case UDIV:
1489 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1490 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1493 return contains_muldiv (XEXP (x, 0))
1494 || contains_muldiv (XEXP (x, 1));
1497 return contains_muldiv (XEXP (x, 0));
1503 /* Determine whether INSN can be used in a combination. Return nonzero if
1504 not. This is used in try_combine to detect early some cases where we
1505 can't perform combinations. */
1508 cant_combine_insn_p (rtx insn)
1513 /* If this isn't really an insn, we can't do anything.
1514 This can occur when flow deletes an insn that it has merged into an
1515 auto-increment address. */
1516 if (! INSN_P (insn))
1519 /* Never combine loads and stores involving hard regs that are likely
1520 to be spilled. The register allocator can usually handle such
1521 reg-reg moves by tying. If we allow the combiner to make
1522 substitutions of likely-spilled regs, we may abort in reload.
1523 As an exception, we allow combinations involving fixed regs; these are
1524 not available to the register allocator so there's no risk involved. */
1526 set = single_set (insn);
1529 src = SET_SRC (set);
1530 dest = SET_DEST (set);
1531 if (GET_CODE (src) == SUBREG)
1532 src = SUBREG_REG (src);
1533 if (GET_CODE (dest) == SUBREG)
1534 dest = SUBREG_REG (dest);
1535 if (REG_P (src) && REG_P (dest)
1536 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1537 && ! fixed_regs[REGNO (src)]
1538 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1539 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1540 && ! fixed_regs[REGNO (dest)]
1541 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1547 /* Adjust INSN after we made a change to its destination.
1549 Changing the destination can invalidate notes that say something about
1550 the results of the insn and a LOG_LINK pointing to the insn. */
1553 adjust_for_new_dest (rtx insn)
1557 /* For notes, be conservative and simply remove them. */
1558 loc = ®_NOTES (insn);
1561 enum reg_note kind = REG_NOTE_KIND (*loc);
1562 if (kind == REG_EQUAL || kind == REG_EQUIV)
1563 *loc = XEXP (*loc, 1);
1565 loc = &XEXP (*loc, 1);
1568 /* The new insn will have a destination that was previously the destination
1569 of an insn just above it. Call distribute_links to make a LOG_LINK from
1570 the next use of that destination. */
1571 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1574 /* Try to combine the insns I1 and I2 into I3.
1575 Here I1 and I2 appear earlier than I3.
1576 I1 can be zero; then we combine just I2 into I3.
1578 If we are combining three insns and the resulting insn is not recognized,
1579 try splitting it into two insns. If that happens, I2 and I3 are retained
1580 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1583 Return 0 if the combination does not work. Then nothing is changed.
1584 If we did the combination, return the insn at which combine should
1587 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1588 new direct jump instruction. */
1591 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1593 /* New patterns for I3 and I2, respectively. */
1594 rtx newpat, newi2pat = 0;
1595 rtvec newpat_vec_with_clobbers = 0;
1596 int substed_i2 = 0, substed_i1 = 0;
1597 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1598 int added_sets_1, added_sets_2;
1599 /* Total number of SETs to put into I3. */
1601 /* Nonzero if I2's body now appears in I3. */
1603 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1604 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1605 /* Contains I3 if the destination of I3 is used in its source, which means
1606 that the old life of I3 is being killed. If that usage is placed into
1607 I2 and not in I3, a REG_DEAD note must be made. */
1608 rtx i3dest_killed = 0;
1609 /* SET_DEST and SET_SRC of I2 and I1. */
1610 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1611 /* PATTERN (I2), or a copy of it in certain cases. */
1613 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1614 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1615 int i1_feeds_i3 = 0;
1616 /* Notes that must be added to REG_NOTES in I3 and I2. */
1617 rtx new_i3_notes, new_i2_notes;
1618 /* Notes that we substituted I3 into I2 instead of the normal case. */
1619 int i3_subst_into_i2 = 0;
1620 /* Notes that I1, I2 or I3 is a MULT operation. */
1629 /* Exit early if one of the insns involved can't be used for
1631 if (cant_combine_insn_p (i3)
1632 || cant_combine_insn_p (i2)
1633 || (i1 && cant_combine_insn_p (i1))
1634 /* We also can't do anything if I3 has a
1635 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1638 /* ??? This gives worse code, and appears to be unnecessary, since no
1639 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1640 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1646 undobuf.other_insn = 0;
1648 /* Reset the hard register usage information. */
1649 CLEAR_HARD_REG_SET (newpat_used_regs);
1651 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1652 code below, set I1 to be the earlier of the two insns. */
1653 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1654 temp = i1, i1 = i2, i2 = temp;
1656 added_links_insn = 0;
1658 /* First check for one important special-case that the code below will
1659 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1660 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1661 we may be able to replace that destination with the destination of I3.
1662 This occurs in the common code where we compute both a quotient and
1663 remainder into a structure, in which case we want to do the computation
1664 directly into the structure to avoid register-register copies.
1666 Note that this case handles both multiple sets in I2 and also
1667 cases where I2 has a number of CLOBBER or PARALLELs.
1669 We make very conservative checks below and only try to handle the
1670 most common cases of this. For example, we only handle the case
1671 where I2 and I3 are adjacent to avoid making difficult register
1674 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1675 && REG_P (SET_SRC (PATTERN (i3)))
1676 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1677 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1678 && GET_CODE (PATTERN (i2)) == PARALLEL
1679 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1680 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1681 below would need to check what is inside (and reg_overlap_mentioned_p
1682 doesn't support those codes anyway). Don't allow those destinations;
1683 the resulting insn isn't likely to be recognized anyway. */
1684 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1685 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1686 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1687 SET_DEST (PATTERN (i3)))
1688 && next_real_insn (i2) == i3)
1690 rtx p2 = PATTERN (i2);
1692 /* Make sure that the destination of I3,
1693 which we are going to substitute into one output of I2,
1694 is not used within another output of I2. We must avoid making this:
1695 (parallel [(set (mem (reg 69)) ...)
1696 (set (reg 69) ...)])
1697 which is not well-defined as to order of actions.
1698 (Besides, reload can't handle output reloads for this.)
1700 The problem can also happen if the dest of I3 is a memory ref,
1701 if another dest in I2 is an indirect memory ref. */
1702 for (i = 0; i < XVECLEN (p2, 0); i++)
1703 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1704 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1705 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1706 SET_DEST (XVECEXP (p2, 0, i))))
1709 if (i == XVECLEN (p2, 0))
1710 for (i = 0; i < XVECLEN (p2, 0); i++)
1711 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1712 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1713 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1718 subst_low_cuid = INSN_CUID (i2);
1720 added_sets_2 = added_sets_1 = 0;
1721 i2dest = SET_SRC (PATTERN (i3));
1723 /* Replace the dest in I2 with our dest and make the resulting
1724 insn the new pattern for I3. Then skip to where we
1725 validate the pattern. Everything was set up above. */
1726 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1727 SET_DEST (PATTERN (i3)));
1730 i3_subst_into_i2 = 1;
1731 goto validate_replacement;
1735 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1736 one of those words to another constant, merge them by making a new
1739 && (temp = single_set (i2)) != 0
1740 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1741 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1742 && REG_P (SET_DEST (temp))
1743 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1744 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1745 && GET_CODE (PATTERN (i3)) == SET
1746 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1747 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1748 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1749 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1750 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1752 HOST_WIDE_INT lo, hi;
1754 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1755 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1758 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1759 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1762 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1764 /* We don't handle the case of the target word being wider
1765 than a host wide int. */
1766 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1768 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1769 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1770 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1772 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1773 hi = INTVAL (SET_SRC (PATTERN (i3)));
1774 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1776 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1777 >> (HOST_BITS_PER_WIDE_INT - 1));
1779 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1780 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1781 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1782 (INTVAL (SET_SRC (PATTERN (i3)))));
1784 hi = lo < 0 ? -1 : 0;
1787 /* We don't handle the case of the higher word not fitting
1788 entirely in either hi or lo. */
1793 subst_low_cuid = INSN_CUID (i2);
1794 added_sets_2 = added_sets_1 = 0;
1795 i2dest = SET_DEST (temp);
1797 SUBST (SET_SRC (temp),
1798 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1800 newpat = PATTERN (i2);
1801 goto validate_replacement;
1805 /* If we have no I1 and I2 looks like:
1806 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1808 make up a dummy I1 that is
1811 (set (reg:CC X) (compare:CC Y (const_int 0)))
1813 (We can ignore any trailing CLOBBERs.)
1815 This undoes a previous combination and allows us to match a branch-and-
1818 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1819 && XVECLEN (PATTERN (i2), 0) >= 2
1820 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1821 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1823 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1824 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1825 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1826 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1827 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1828 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1830 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1831 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1836 /* We make I1 with the same INSN_UID as I2. This gives it
1837 the same INSN_CUID for value tracking. Our fake I1 will
1838 never appear in the insn stream so giving it the same INSN_UID
1839 as I2 will not cause a problem. */
1841 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1842 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1843 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1846 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1847 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1848 SET_DEST (PATTERN (i1)));
1853 /* Verify that I2 and I1 are valid for combining. */
1854 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1855 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1861 /* Record whether I2DEST is used in I2SRC and similarly for the other
1862 cases. Knowing this will help in register status updating below. */
1863 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1864 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1865 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1867 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1869 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1871 /* Ensure that I3's pattern can be the destination of combines. */
1872 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1873 i1 && i2dest_in_i1src && i1_feeds_i3,
1880 /* See if any of the insns is a MULT operation. Unless one is, we will
1881 reject a combination that is, since it must be slower. Be conservative
1883 if (GET_CODE (i2src) == MULT
1884 || (i1 != 0 && GET_CODE (i1src) == MULT)
1885 || (GET_CODE (PATTERN (i3)) == SET
1886 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1889 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1890 We used to do this EXCEPT in one case: I3 has a post-inc in an
1891 output operand. However, that exception can give rise to insns like
1893 which is a famous insn on the PDP-11 where the value of r3 used as the
1894 source was model-dependent. Avoid this sort of thing. */
1897 if (!(GET_CODE (PATTERN (i3)) == SET
1898 && REG_P (SET_SRC (PATTERN (i3)))
1899 && MEM_P (SET_DEST (PATTERN (i3)))
1900 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1901 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1902 /* It's not the exception. */
1905 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1906 if (REG_NOTE_KIND (link) == REG_INC
1907 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1909 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1916 /* See if the SETs in I1 or I2 need to be kept around in the merged
1917 instruction: whenever the value set there is still needed past I3.
1918 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1920 For the SET in I1, we have two cases: If I1 and I2 independently
1921 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1922 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1923 in I1 needs to be kept around unless I1DEST dies or is set in either
1924 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1925 I1DEST. If so, we know I1 feeds into I2. */
1927 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1930 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1931 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1933 /* If the set in I2 needs to be kept around, we must make a copy of
1934 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1935 PATTERN (I2), we are only substituting for the original I1DEST, not into
1936 an already-substituted copy. This also prevents making self-referential
1937 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1940 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1941 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1945 i2pat = copy_rtx (i2pat);
1949 /* Substitute in the latest insn for the regs set by the earlier ones. */
1951 maxreg = max_reg_num ();
1955 /* It is possible that the source of I2 or I1 may be performing an
1956 unneeded operation, such as a ZERO_EXTEND of something that is known
1957 to have the high part zero. Handle that case by letting subst look at
1958 the innermost one of them.
1960 Another way to do this would be to have a function that tries to
1961 simplify a single insn instead of merging two or more insns. We don't
1962 do this because of the potential of infinite loops and because
1963 of the potential extra memory required. However, doing it the way
1964 we are is a bit of a kludge and doesn't catch all cases.
1966 But only do this if -fexpensive-optimizations since it slows things down
1967 and doesn't usually win. */
1969 if (flag_expensive_optimizations)
1971 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1974 subst_low_cuid = INSN_CUID (i1);
1975 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1979 subst_low_cuid = INSN_CUID (i2);
1980 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1985 /* Many machines that don't use CC0 have insns that can both perform an
1986 arithmetic operation and set the condition code. These operations will
1987 be represented as a PARALLEL with the first element of the vector
1988 being a COMPARE of an arithmetic operation with the constant zero.
1989 The second element of the vector will set some pseudo to the result
1990 of the same arithmetic operation. If we simplify the COMPARE, we won't
1991 match such a pattern and so will generate an extra insn. Here we test
1992 for this case, where both the comparison and the operation result are
1993 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1994 I2SRC. Later we will make the PARALLEL that contains I2. */
1996 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1997 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1998 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1999 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2001 #ifdef SELECT_CC_MODE
2003 enum machine_mode compare_mode;
2006 newpat = PATTERN (i3);
2007 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2011 #ifdef SELECT_CC_MODE
2012 /* See if a COMPARE with the operand we substituted in should be done
2013 with the mode that is currently being used. If not, do the same
2014 processing we do in `subst' for a SET; namely, if the destination
2015 is used only once, try to replace it with a register of the proper
2016 mode and also replace the COMPARE. */
2017 if (undobuf.other_insn == 0
2018 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2019 &undobuf.other_insn))
2020 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2022 != GET_MODE (SET_DEST (newpat))))
2024 unsigned int regno = REGNO (SET_DEST (newpat));
2025 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2027 if (regno < FIRST_PSEUDO_REGISTER
2028 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2029 && ! REG_USERVAR_P (SET_DEST (newpat))))
2031 if (regno >= FIRST_PSEUDO_REGISTER)
2032 SUBST (regno_reg_rtx[regno], new_dest);
2034 SUBST (SET_DEST (newpat), new_dest);
2035 SUBST (XEXP (*cc_use, 0), new_dest);
2036 SUBST (SET_SRC (newpat),
2037 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2040 undobuf.other_insn = 0;
2047 n_occurrences = 0; /* `subst' counts here */
2049 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2050 need to make a unique copy of I2SRC each time we substitute it
2051 to avoid self-referential rtl. */
2053 subst_low_cuid = INSN_CUID (i2);
2054 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2055 ! i1_feeds_i3 && i1dest_in_i1src);
2058 /* Record whether i2's body now appears within i3's body. */
2059 i2_is_used = n_occurrences;
2062 /* If we already got a failure, don't try to do more. Otherwise,
2063 try to substitute in I1 if we have it. */
2065 if (i1 && GET_CODE (newpat) != CLOBBER)
2067 /* Before we can do this substitution, we must redo the test done
2068 above (see detailed comments there) that ensures that I1DEST
2069 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2071 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2079 subst_low_cuid = INSN_CUID (i1);
2080 newpat = subst (newpat, i1dest, i1src, 0, 0);
2084 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2085 to count all the ways that I2SRC and I1SRC can be used. */
2086 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2087 && i2_is_used + added_sets_2 > 1)
2088 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2089 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2091 /* Fail if we tried to make a new register (we used to abort, but there's
2092 really no reason to). */
2093 || max_reg_num () != maxreg
2094 /* Fail if we couldn't do something and have a CLOBBER. */
2095 || GET_CODE (newpat) == CLOBBER
2096 /* Fail if this new pattern is a MULT and we didn't have one before
2097 at the outer level. */
2098 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2105 /* If the actions of the earlier insns must be kept
2106 in addition to substituting them into the latest one,
2107 we must make a new PARALLEL for the latest insn
2108 to hold additional the SETs. */
2110 if (added_sets_1 || added_sets_2)
2114 if (GET_CODE (newpat) == PARALLEL)
2116 rtvec old = XVEC (newpat, 0);
2117 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2118 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2119 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2120 sizeof (old->elem[0]) * old->num_elem);
2125 total_sets = 1 + added_sets_1 + added_sets_2;
2126 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2127 XVECEXP (newpat, 0, 0) = old;
2131 XVECEXP (newpat, 0, --total_sets)
2132 = (GET_CODE (PATTERN (i1)) == PARALLEL
2133 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2137 /* If there is no I1, use I2's body as is. We used to also not do
2138 the subst call below if I2 was substituted into I3,
2139 but that could lose a simplification. */
2141 XVECEXP (newpat, 0, --total_sets) = i2pat;
2143 /* See comment where i2pat is assigned. */
2144 XVECEXP (newpat, 0, --total_sets)
2145 = subst (i2pat, i1dest, i1src, 0, 0);
2149 /* We come here when we are replacing a destination in I2 with the
2150 destination of I3. */
2151 validate_replacement:
2153 /* Note which hard regs this insn has as inputs. */
2154 mark_used_regs_combine (newpat);
2156 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2157 consider splitting this pattern, we might need these clobbers. */
2158 if (i1 && GET_CODE (newpat) == PARALLEL
2159 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2161 int len = XVECLEN (newpat, 0);
2163 newpat_vec_with_clobbers = rtvec_alloc (len);
2164 for (i = 0; i < len; i++)
2165 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2168 /* Is the result of combination a valid instruction? */
2169 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2171 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2172 the second SET's destination is a register that is unused and isn't
2173 marked as an instruction that might trap in an EH region. In that case,
2174 we just need the first SET. This can occur when simplifying a divmod
2175 insn. We *must* test for this case here because the code below that
2176 splits two independent SETs doesn't handle this case correctly when it
2177 updates the register status.
2179 It's pointless doing this if we originally had two sets, one from
2180 i3, and one from i2. Combining then splitting the parallel results
2181 in the original i2 again plus an invalid insn (which we delete).
2182 The net effect is only to move instructions around, which makes
2183 debug info less accurate.
2185 Also check the case where the first SET's destination is unused.
2186 That would not cause incorrect code, but does cause an unneeded
2189 if (insn_code_number < 0
2190 && !(added_sets_2 && i1 == 0)
2191 && GET_CODE (newpat) == PARALLEL
2192 && XVECLEN (newpat, 0) == 2
2193 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2194 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2195 && asm_noperands (newpat) < 0)
2197 rtx set0 = XVECEXP (newpat, 0, 0);
2198 rtx set1 = XVECEXP (newpat, 0, 1);
2201 if (((REG_P (SET_DEST (set1))
2202 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2203 || (GET_CODE (SET_DEST (set1)) == SUBREG
2204 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2205 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2206 || INTVAL (XEXP (note, 0)) <= 0)
2207 && ! side_effects_p (SET_SRC (set1)))
2210 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2213 else if (((REG_P (SET_DEST (set0))
2214 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2215 || (GET_CODE (SET_DEST (set0)) == SUBREG
2216 && find_reg_note (i3, REG_UNUSED,
2217 SUBREG_REG (SET_DEST (set0)))))
2218 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2219 || INTVAL (XEXP (note, 0)) <= 0)
2220 && ! side_effects_p (SET_SRC (set0)))
2223 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2225 if (insn_code_number >= 0)
2227 /* If we will be able to accept this, we have made a
2228 change to the destination of I3. This requires us to
2229 do a few adjustments. */
2231 PATTERN (i3) = newpat;
2232 adjust_for_new_dest (i3);
2237 /* If we were combining three insns and the result is a simple SET
2238 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2239 insns. There are two ways to do this. It can be split using a
2240 machine-specific method (like when you have an addition of a large
2241 constant) or by combine in the function find_split_point. */
2243 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2244 && asm_noperands (newpat) < 0)
2246 rtx m_split, *split;
2247 rtx ni2dest = i2dest;
2249 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2250 use I2DEST as a scratch register will help. In the latter case,
2251 convert I2DEST to the mode of the source of NEWPAT if we can. */
2253 m_split = split_insns (newpat, i3);
2255 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2256 inputs of NEWPAT. */
2258 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2259 possible to try that as a scratch reg. This would require adding
2260 more code to make it work though. */
2262 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2264 /* If I2DEST is a hard register or the only use of a pseudo,
2265 we can change its mode. */
2266 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2267 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2269 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2270 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2271 && ! REG_USERVAR_P (i2dest))))
2272 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2275 m_split = split_insns (gen_rtx_PARALLEL
2277 gen_rtvec (2, newpat,
2278 gen_rtx_CLOBBER (VOIDmode,
2281 /* If the split with the mode-changed register didn't work, try
2282 the original register. */
2283 if (! m_split && ni2dest != i2dest)
2286 m_split = split_insns (gen_rtx_PARALLEL
2288 gen_rtvec (2, newpat,
2289 gen_rtx_CLOBBER (VOIDmode,
2295 /* If recog_for_combine has discarded clobbers, try to use them
2296 again for the split. */
2297 if (m_split == 0 && newpat_vec_with_clobbers)
2299 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2300 newpat_vec_with_clobbers), i3);
2302 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2304 m_split = PATTERN (m_split);
2305 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2306 if (insn_code_number >= 0)
2309 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2310 && (next_real_insn (i2) == i3
2311 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2314 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2315 newi2pat = PATTERN (m_split);
2317 i3set = single_set (NEXT_INSN (m_split));
2318 i2set = single_set (m_split);
2320 /* In case we changed the mode of I2DEST, replace it in the
2321 pseudo-register table here. We can't do it above in case this
2322 code doesn't get executed and we do a split the other way. */
2324 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2325 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2327 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2329 /* If I2 or I3 has multiple SETs, we won't know how to track
2330 register status, so don't use these insns. If I2's destination
2331 is used between I2 and I3, we also can't use these insns. */
2333 if (i2_code_number >= 0 && i2set && i3set
2334 && (next_real_insn (i2) == i3
2335 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2336 insn_code_number = recog_for_combine (&newi3pat, i3,
2338 if (insn_code_number >= 0)
2341 /* It is possible that both insns now set the destination of I3.
2342 If so, we must show an extra use of it. */
2344 if (insn_code_number >= 0)
2346 rtx new_i3_dest = SET_DEST (i3set);
2347 rtx new_i2_dest = SET_DEST (i2set);
2349 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2350 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2351 || GET_CODE (new_i3_dest) == SUBREG)
2352 new_i3_dest = XEXP (new_i3_dest, 0);
2354 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2355 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2356 || GET_CODE (new_i2_dest) == SUBREG)
2357 new_i2_dest = XEXP (new_i2_dest, 0);
2359 if (REG_P (new_i3_dest)
2360 && REG_P (new_i2_dest)
2361 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2362 REG_N_SETS (REGNO (new_i2_dest))++;
2366 /* If we can split it and use I2DEST, go ahead and see if that
2367 helps things be recognized. Verify that none of the registers
2368 are set between I2 and I3. */
2369 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2373 /* We need I2DEST in the proper mode. If it is a hard register
2374 or the only use of a pseudo, we can change its mode.
2375 Make sure we don't change a hard register to have a mode that
2376 isn't valid for it, or change the number of registers. */
2377 && (GET_MODE (*split) == GET_MODE (i2dest)
2378 || GET_MODE (*split) == VOIDmode
2379 || (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2380 && HARD_REGNO_MODE_OK (REGNO (i2dest), GET_MODE (*split))
2381 && (HARD_REGNO_NREGS (REGNO (i2dest), GET_MODE (i2dest))
2382 == HARD_REGNO_NREGS (REGNO (i2dest), GET_MODE (*split))))
2383 || (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER
2384 && REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2385 && ! REG_USERVAR_P (i2dest)))
2386 && (next_real_insn (i2) == i3
2387 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2388 /* We can't overwrite I2DEST if its value is still used by
2390 && ! reg_referenced_p (i2dest, newpat))
2392 rtx newdest = i2dest;
2393 enum rtx_code split_code = GET_CODE (*split);
2394 enum machine_mode split_mode = GET_MODE (*split);
2396 /* Get NEWDEST as a register in the proper mode. We have already
2397 validated that we can do this. */
2398 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2400 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2402 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2403 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2406 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2407 an ASHIFT. This can occur if it was inside a PLUS and hence
2408 appeared to be a memory address. This is a kludge. */
2409 if (split_code == MULT
2410 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2411 && INTVAL (XEXP (*split, 1)) > 0
2412 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2414 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2415 XEXP (*split, 0), GEN_INT (i)));
2416 /* Update split_code because we may not have a multiply
2418 split_code = GET_CODE (*split);
2421 #ifdef INSN_SCHEDULING
2422 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2423 be written as a ZERO_EXTEND. */
2424 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2426 #ifdef LOAD_EXTEND_OP
2427 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2428 what it really is. */
2429 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2431 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2432 SUBREG_REG (*split)));
2435 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2436 SUBREG_REG (*split)));
2440 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2441 SUBST (*split, newdest);
2442 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2444 /* recog_for_combine might have added CLOBBERs to newi2pat.
2445 Make sure NEWPAT does not depend on the clobbered regs. */
2446 if (GET_CODE (newi2pat) == PARALLEL)
2447 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2448 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2450 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2451 if (reg_overlap_mentioned_p (reg, newpat))
2458 /* If the split point was a MULT and we didn't have one before,
2459 don't use one now. */
2460 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2461 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2465 /* Check for a case where we loaded from memory in a narrow mode and
2466 then sign extended it, but we need both registers. In that case,
2467 we have a PARALLEL with both loads from the same memory location.
2468 We can split this into a load from memory followed by a register-register
2469 copy. This saves at least one insn, more if register allocation can
2472 We cannot do this if the destination of the first assignment is a
2473 condition code register or cc0. We eliminate this case by making sure
2474 the SET_DEST and SET_SRC have the same mode.
2476 We cannot do this if the destination of the second assignment is
2477 a register that we have already assumed is zero-extended. Similarly
2478 for a SUBREG of such a register. */
2480 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2481 && GET_CODE (newpat) == PARALLEL
2482 && XVECLEN (newpat, 0) == 2
2483 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2484 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2485 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2486 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2487 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2488 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2489 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2490 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2492 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2493 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2494 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2496 && reg_stat[REGNO (temp)].nonzero_bits != 0
2497 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2498 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2499 && (reg_stat[REGNO (temp)].nonzero_bits
2500 != GET_MODE_MASK (word_mode))))
2501 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2502 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2504 && reg_stat[REGNO (temp)].nonzero_bits != 0
2505 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2506 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2507 && (reg_stat[REGNO (temp)].nonzero_bits
2508 != GET_MODE_MASK (word_mode)))))
2509 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2510 SET_SRC (XVECEXP (newpat, 0, 1)))
2511 && ! find_reg_note (i3, REG_UNUSED,
2512 SET_DEST (XVECEXP (newpat, 0, 0))))
2516 newi2pat = XVECEXP (newpat, 0, 0);
2517 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2518 newpat = XVECEXP (newpat, 0, 1);
2519 SUBST (SET_SRC (newpat),
2520 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2521 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2523 if (i2_code_number >= 0)
2524 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2526 if (insn_code_number >= 0)
2530 /* Similarly, check for a case where we have a PARALLEL of two independent
2531 SETs but we started with three insns. In this case, we can do the sets
2532 as two separate insns. This case occurs when some SET allows two
2533 other insns to combine, but the destination of that SET is still live. */
2535 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2536 && GET_CODE (newpat) == PARALLEL
2537 && XVECLEN (newpat, 0) == 2
2538 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2539 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2540 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2541 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2542 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2543 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2544 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2546 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2547 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2548 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2549 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2550 XVECEXP (newpat, 0, 0))
2551 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2552 XVECEXP (newpat, 0, 1))
2553 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2554 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2556 /* Normally, it doesn't matter which of the two is done first,
2557 but it does if one references cc0. In that case, it has to
2560 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2562 newi2pat = XVECEXP (newpat, 0, 0);
2563 newpat = XVECEXP (newpat, 0, 1);
2568 newi2pat = XVECEXP (newpat, 0, 1);
2569 newpat = XVECEXP (newpat, 0, 0);
2572 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2574 if (i2_code_number >= 0)
2575 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2578 /* If it still isn't recognized, fail and change things back the way they
2580 if ((insn_code_number < 0
2581 /* Is the result a reasonable ASM_OPERANDS? */
2582 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2588 /* If we had to change another insn, make sure it is valid also. */
2589 if (undobuf.other_insn)
2591 rtx other_pat = PATTERN (undobuf.other_insn);
2592 rtx new_other_notes;
2595 CLEAR_HARD_REG_SET (newpat_used_regs);
2597 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2600 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2606 PATTERN (undobuf.other_insn) = other_pat;
2608 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2609 are still valid. Then add any non-duplicate notes added by
2610 recog_for_combine. */
2611 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2613 next = XEXP (note, 1);
2615 if (REG_NOTE_KIND (note) == REG_UNUSED
2616 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2618 if (REG_P (XEXP (note, 0)))
2619 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2621 remove_note (undobuf.other_insn, note);
2625 for (note = new_other_notes; note; note = XEXP (note, 1))
2626 if (REG_P (XEXP (note, 0)))
2627 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2629 distribute_notes (new_other_notes, undobuf.other_insn,
2630 undobuf.other_insn, NULL_RTX);
2633 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2634 they are adjacent to each other or not. */
2636 rtx p = prev_nonnote_insn (i3);
2637 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2638 && sets_cc0_p (newi2pat))
2646 /* Only allow this combination if insn_rtx_costs reports that the
2647 replacement instructions are cheaper than the originals. */
2648 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2654 /* We now know that we can do this combination. Merge the insns and
2655 update the status of registers and LOG_LINKS. */
2663 /* I3 now uses what used to be its destination and which is now
2664 I2's destination. This requires us to do a few adjustments. */
2665 PATTERN (i3) = newpat;
2666 adjust_for_new_dest (i3);
2668 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2671 However, some later insn might be using I2's dest and have
2672 a LOG_LINK pointing at I3. We must remove this link.
2673 The simplest way to remove the link is to point it at I1,
2674 which we know will be a NOTE. */
2676 /* newi2pat is usually a SET here; however, recog_for_combine might
2677 have added some clobbers. */
2678 if (GET_CODE (newi2pat) == PARALLEL)
2679 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2681 ni2dest = SET_DEST (newi2pat);
2683 for (insn = NEXT_INSN (i3);
2684 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2685 || insn != BB_HEAD (this_basic_block->next_bb));
2686 insn = NEXT_INSN (insn))
2688 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2690 for (link = LOG_LINKS (insn); link;
2691 link = XEXP (link, 1))
2692 if (XEXP (link, 0) == i3)
2693 XEXP (link, 0) = i1;
2701 rtx i3notes, i2notes, i1notes = 0;
2702 rtx i3links, i2links, i1links = 0;
2706 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2708 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2709 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2711 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2713 /* Ensure that we do not have something that should not be shared but
2714 occurs multiple times in the new insns. Check this by first
2715 resetting all the `used' flags and then copying anything is shared. */
2717 reset_used_flags (i3notes);
2718 reset_used_flags (i2notes);
2719 reset_used_flags (i1notes);
2720 reset_used_flags (newpat);
2721 reset_used_flags (newi2pat);
2722 if (undobuf.other_insn)
2723 reset_used_flags (PATTERN (undobuf.other_insn));
2725 i3notes = copy_rtx_if_shared (i3notes);
2726 i2notes = copy_rtx_if_shared (i2notes);
2727 i1notes = copy_rtx_if_shared (i1notes);
2728 newpat = copy_rtx_if_shared (newpat);
2729 newi2pat = copy_rtx_if_shared (newi2pat);
2730 if (undobuf.other_insn)
2731 reset_used_flags (PATTERN (undobuf.other_insn));
2733 INSN_CODE (i3) = insn_code_number;
2734 PATTERN (i3) = newpat;
2736 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2738 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2740 reset_used_flags (call_usage);
2741 call_usage = copy_rtx (call_usage);
2744 replace_rtx (call_usage, i2dest, i2src);
2747 replace_rtx (call_usage, i1dest, i1src);
2749 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2752 if (undobuf.other_insn)
2753 INSN_CODE (undobuf.other_insn) = other_code_number;
2755 /* We had one special case above where I2 had more than one set and
2756 we replaced a destination of one of those sets with the destination
2757 of I3. In that case, we have to update LOG_LINKS of insns later
2758 in this basic block. Note that this (expensive) case is rare.
2760 Also, in this case, we must pretend that all REG_NOTEs for I2
2761 actually came from I3, so that REG_UNUSED notes from I2 will be
2762 properly handled. */
2764 if (i3_subst_into_i2)
2766 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2767 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2768 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2769 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2770 && ! find_reg_note (i2, REG_UNUSED,
2771 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2772 for (temp = NEXT_INSN (i2);
2773 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2774 || BB_HEAD (this_basic_block) != temp);
2775 temp = NEXT_INSN (temp))
2776 if (temp != i3 && INSN_P (temp))
2777 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2778 if (XEXP (link, 0) == i2)
2779 XEXP (link, 0) = i3;
2784 while (XEXP (link, 1))
2785 link = XEXP (link, 1);
2786 XEXP (link, 1) = i2notes;
2800 INSN_CODE (i2) = i2_code_number;
2801 PATTERN (i2) = newi2pat;
2804 SET_INSN_DELETED (i2);
2810 SET_INSN_DELETED (i1);
2813 /* Get death notes for everything that is now used in either I3 or
2814 I2 and used to die in a previous insn. If we built two new
2815 patterns, move from I1 to I2 then I2 to I3 so that we get the
2816 proper movement on registers that I2 modifies. */
2820 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2821 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2824 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2827 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2829 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2831 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2833 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2835 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2837 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2838 know these are REG_UNUSED and want them to go to the desired insn,
2839 so we always pass it as i3. We have not counted the notes in
2840 reg_n_deaths yet, so we need to do so now. */
2842 if (newi2pat && new_i2_notes)
2844 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2845 if (REG_P (XEXP (temp, 0)))
2846 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2848 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2853 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2854 if (REG_P (XEXP (temp, 0)))
2855 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2857 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2860 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2861 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2862 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2863 in that case, it might delete I2. Similarly for I2 and I1.
2864 Show an additional death due to the REG_DEAD note we make here. If
2865 we discard it in distribute_notes, we will decrement it again. */
2869 if (REG_P (i3dest_killed))
2870 REG_N_DEATHS (REGNO (i3dest_killed))++;
2872 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2873 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2875 NULL_RTX, i2, NULL_RTX);
2877 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2879 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2882 if (i2dest_in_i2src)
2885 REG_N_DEATHS (REGNO (i2dest))++;
2887 if (newi2pat && reg_set_p (i2dest, newi2pat))
2888 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2889 NULL_RTX, i2, NULL_RTX);
2891 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2892 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2895 if (i1dest_in_i1src)
2898 REG_N_DEATHS (REGNO (i1dest))++;
2900 if (newi2pat && reg_set_p (i1dest, newi2pat))
2901 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2902 NULL_RTX, i2, NULL_RTX);
2904 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2905 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2908 distribute_links (i3links);
2909 distribute_links (i2links);
2910 distribute_links (i1links);
2915 rtx i2_insn = 0, i2_val = 0, set;
2917 /* The insn that used to set this register doesn't exist, and
2918 this life of the register may not exist either. See if one of
2919 I3's links points to an insn that sets I2DEST. If it does,
2920 that is now the last known value for I2DEST. If we don't update
2921 this and I2 set the register to a value that depended on its old
2922 contents, we will get confused. If this insn is used, thing
2923 will be set correctly in combine_instructions. */
2925 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2926 if ((set = single_set (XEXP (link, 0))) != 0
2927 && rtx_equal_p (i2dest, SET_DEST (set)))
2928 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2930 record_value_for_reg (i2dest, i2_insn, i2_val);
2932 /* If the reg formerly set in I2 died only once and that was in I3,
2933 zero its use count so it won't make `reload' do any work. */
2935 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2936 && ! i2dest_in_i2src)
2938 regno = REGNO (i2dest);
2939 REG_N_SETS (regno)--;
2943 if (i1 && REG_P (i1dest))
2946 rtx i1_insn = 0, i1_val = 0, set;
2948 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2949 if ((set = single_set (XEXP (link, 0))) != 0
2950 && rtx_equal_p (i1dest, SET_DEST (set)))
2951 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2953 record_value_for_reg (i1dest, i1_insn, i1_val);
2955 regno = REGNO (i1dest);
2956 if (! added_sets_1 && ! i1dest_in_i1src)
2957 REG_N_SETS (regno)--;
2960 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2961 been made to this insn. The order of
2962 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2963 can affect nonzero_bits of newpat */
2965 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2966 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2968 /* Set new_direct_jump_p if a new return or simple jump instruction
2971 If I3 is now an unconditional jump, ensure that it has a
2972 BARRIER following it since it may have initially been a
2973 conditional jump. It may also be the last nonnote insn. */
2975 if (returnjump_p (i3) || any_uncondjump_p (i3))
2977 *new_direct_jump_p = 1;
2978 mark_jump_label (PATTERN (i3), i3, 0);
2980 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2981 || !BARRIER_P (temp))
2982 emit_barrier_after (i3);
2985 if (undobuf.other_insn != NULL_RTX
2986 && (returnjump_p (undobuf.other_insn)
2987 || any_uncondjump_p (undobuf.other_insn)))
2989 *new_direct_jump_p = 1;
2991 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2992 || !BARRIER_P (temp))
2993 emit_barrier_after (undobuf.other_insn);
2996 /* An NOOP jump does not need barrier, but it does need cleaning up
2998 if (GET_CODE (newpat) == SET
2999 && SET_SRC (newpat) == pc_rtx
3000 && SET_DEST (newpat) == pc_rtx)
3001 *new_direct_jump_p = 1;
3004 combine_successes++;
3007 if (added_links_insn
3008 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3009 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3010 return added_links_insn;
3012 return newi2pat ? i2 : i3;
3015 /* Undo all the modifications recorded in undobuf. */
3020 struct undo *undo, *next;
3022 for (undo = undobuf.undos; undo; undo = next)
3026 *undo->where.i = undo->old_contents.i;
3028 *undo->where.r = undo->old_contents.r;
3030 undo->next = undobuf.frees;
3031 undobuf.frees = undo;
3037 /* We've committed to accepting the changes we made. Move all
3038 of the undos to the free list. */
3043 struct undo *undo, *next;
3045 for (undo = undobuf.undos; undo; undo = next)
3048 undo->next = undobuf.frees;
3049 undobuf.frees = undo;
3055 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3056 where we have an arithmetic expression and return that point. LOC will
3059 try_combine will call this function to see if an insn can be split into
3063 find_split_point (rtx *loc, rtx insn)
3066 enum rtx_code code = GET_CODE (x);
3068 unsigned HOST_WIDE_INT len = 0;
3069 HOST_WIDE_INT pos = 0;
3071 rtx inner = NULL_RTX;
3073 /* First special-case some codes. */
3077 #ifdef INSN_SCHEDULING
3078 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3080 if (MEM_P (SUBREG_REG (x)))
3083 return find_split_point (&SUBREG_REG (x), insn);
3087 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3088 using LO_SUM and HIGH. */
3089 if (GET_CODE (XEXP (x, 0)) == CONST
3090 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3093 gen_rtx_LO_SUM (Pmode,
3094 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3096 return &XEXP (XEXP (x, 0), 0);
3100 /* If we have a PLUS whose second operand is a constant and the
3101 address is not valid, perhaps will can split it up using
3102 the machine-specific way to split large constants. We use
3103 the first pseudo-reg (one of the virtual regs) as a placeholder;
3104 it will not remain in the result. */
3105 if (GET_CODE (XEXP (x, 0)) == PLUS
3106 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3107 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3109 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3110 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3113 /* This should have produced two insns, each of which sets our
3114 placeholder. If the source of the second is a valid address,
3115 we can make put both sources together and make a split point
3119 && NEXT_INSN (seq) != NULL_RTX
3120 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3121 && NONJUMP_INSN_P (seq)
3122 && GET_CODE (PATTERN (seq)) == SET
3123 && SET_DEST (PATTERN (seq)) == reg
3124 && ! reg_mentioned_p (reg,
3125 SET_SRC (PATTERN (seq)))
3126 && NONJUMP_INSN_P (NEXT_INSN (seq))
3127 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3128 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3129 && memory_address_p (GET_MODE (x),
3130 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3132 rtx src1 = SET_SRC (PATTERN (seq));
3133 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3135 /* Replace the placeholder in SRC2 with SRC1. If we can
3136 find where in SRC2 it was placed, that can become our
3137 split point and we can replace this address with SRC2.
3138 Just try two obvious places. */
3140 src2 = replace_rtx (src2, reg, src1);
3142 if (XEXP (src2, 0) == src1)
3143 split = &XEXP (src2, 0);
3144 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3145 && XEXP (XEXP (src2, 0), 0) == src1)
3146 split = &XEXP (XEXP (src2, 0), 0);
3150 SUBST (XEXP (x, 0), src2);
3155 /* If that didn't work, perhaps the first operand is complex and
3156 needs to be computed separately, so make a split point there.
3157 This will occur on machines that just support REG + CONST
3158 and have a constant moved through some previous computation. */
3160 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3161 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3162 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3163 return &XEXP (XEXP (x, 0), 0);
3169 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3170 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3171 we need to put the operand into a register. So split at that
3174 if (SET_DEST (x) == cc0_rtx
3175 && GET_CODE (SET_SRC (x)) != COMPARE
3176 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3177 && !OBJECT_P (SET_SRC (x))
3178 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3179 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3180 return &SET_SRC (x);
3183 /* See if we can split SET_SRC as it stands. */
3184 split = find_split_point (&SET_SRC (x), insn);
3185 if (split && split != &SET_SRC (x))
3188 /* See if we can split SET_DEST as it stands. */
3189 split = find_split_point (&SET_DEST (x), insn);
3190 if (split && split != &SET_DEST (x))
3193 /* See if this is a bitfield assignment with everything constant. If
3194 so, this is an IOR of an AND, so split it into that. */
3195 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3196 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3197 <= HOST_BITS_PER_WIDE_INT)
3198 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3199 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3200 && GET_CODE (SET_SRC (x)) == CONST_INT
3201 && ((INTVAL (XEXP (SET_DEST (x), 1))
3202 + INTVAL (XEXP (SET_DEST (x), 2)))
3203 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3204 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3206 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3207 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3208 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3209 rtx dest = XEXP (SET_DEST (x), 0);
3210 enum machine_mode mode = GET_MODE (dest);
3211 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3213 if (BITS_BIG_ENDIAN)
3214 pos = GET_MODE_BITSIZE (mode) - len - pos;
3218 simplify_gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3221 rtx negmask = gen_int_mode (~(mask << pos), mode);
3223 simplify_gen_binary (IOR, mode,
3224 simplify_gen_binary (AND, mode,
3226 GEN_INT (src << pos)));
3229 SUBST (SET_DEST (x), dest);
3231 split = find_split_point (&SET_SRC (x), insn);
3232 if (split && split != &SET_SRC (x))
3236 /* Otherwise, see if this is an operation that we can split into two.
3237 If so, try to split that. */
3238 code = GET_CODE (SET_SRC (x));
3243 /* If we are AND'ing with a large constant that is only a single
3244 bit and the result is only being used in a context where we
3245 need to know if it is zero or nonzero, replace it with a bit
3246 extraction. This will avoid the large constant, which might
3247 have taken more than one insn to make. If the constant were
3248 not a valid argument to the AND but took only one insn to make,
3249 this is no worse, but if it took more than one insn, it will
3252 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3253 && REG_P (XEXP (SET_SRC (x), 0))
3254 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3255 && REG_P (SET_DEST (x))
3256 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3257 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3258 && XEXP (*split, 0) == SET_DEST (x)
3259 && XEXP (*split, 1) == const0_rtx)
3261 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3262 XEXP (SET_SRC (x), 0),
3263 pos, NULL_RTX, 1, 1, 0, 0);
3264 if (extraction != 0)
3266 SUBST (SET_SRC (x), extraction);
3267 return find_split_point (loc, insn);
3273 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3274 is known to be on, this can be converted into a NEG of a shift. */
3275 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3276 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3277 && 1 <= (pos = exact_log2
3278 (nonzero_bits (XEXP (SET_SRC (x), 0),
3279 GET_MODE (XEXP (SET_SRC (x), 0))))))
3281 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3285 gen_rtx_LSHIFTRT (mode,
3286 XEXP (SET_SRC (x), 0),
3289 split = find_split_point (&SET_SRC (x), insn);
3290 if (split && split != &SET_SRC (x))
3296 inner = XEXP (SET_SRC (x), 0);
3298 /* We can't optimize if either mode is a partial integer
3299 mode as we don't know how many bits are significant
3301 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3302 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3306 len = GET_MODE_BITSIZE (GET_MODE (inner));
3312 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3313 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3315 inner = XEXP (SET_SRC (x), 0);
3316 len = INTVAL (XEXP (SET_SRC (x), 1));
3317 pos = INTVAL (XEXP (SET_SRC (x), 2));
3319 if (BITS_BIG_ENDIAN)
3320 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3321 unsignedp = (code == ZERO_EXTRACT);
3329 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3331 enum machine_mode mode = GET_MODE (SET_SRC (x));
3333 /* For unsigned, we have a choice of a shift followed by an
3334 AND or two shifts. Use two shifts for field sizes where the
3335 constant might be too large. We assume here that we can
3336 always at least get 8-bit constants in an AND insn, which is
3337 true for every current RISC. */
3339 if (unsignedp && len <= 8)
3344 (mode, gen_lowpart (mode, inner),
3346 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3348 split = find_split_point (&SET_SRC (x), insn);
3349 if (split && split != &SET_SRC (x))
3356 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3357 gen_rtx_ASHIFT (mode,
3358 gen_lowpart (mode, inner),
3359 GEN_INT (GET_MODE_BITSIZE (mode)
3361 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3363 split = find_split_point (&SET_SRC (x), insn);
3364 if (split && split != &SET_SRC (x))
3369 /* See if this is a simple operation with a constant as the second
3370 operand. It might be that this constant is out of range and hence
3371 could be used as a split point. */
3372 if (BINARY_P (SET_SRC (x))
3373 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3374 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3375 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3376 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3377 return &XEXP (SET_SRC (x), 1);
3379 /* Finally, see if this is a simple operation with its first operand
3380 not in a register. The operation might require this operand in a
3381 register, so return it as a split point. We can always do this
3382 because if the first operand were another operation, we would have
3383 already found it as a split point. */
3384 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3385 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3386 return &XEXP (SET_SRC (x), 0);
3392 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3393 it is better to write this as (not (ior A B)) so we can split it.
3394 Similarly for IOR. */
3395 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3398 gen_rtx_NOT (GET_MODE (x),
3399 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3401 XEXP (XEXP (x, 0), 0),
3402 XEXP (XEXP (x, 1), 0))));
3403 return find_split_point (loc, insn);
3406 /* Many RISC machines have a large set of logical insns. If the
3407 second operand is a NOT, put it first so we will try to split the
3408 other operand first. */
3409 if (GET_CODE (XEXP (x, 1)) == NOT)
3411 rtx tem = XEXP (x, 0);
3412 SUBST (XEXP (x, 0), XEXP (x, 1));
3413 SUBST (XEXP (x, 1), tem);
3421 /* Otherwise, select our actions depending on our rtx class. */
3422 switch (GET_RTX_CLASS (code))
3424 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3426 split = find_split_point (&XEXP (x, 2), insn);
3429 /* ... fall through ... */
3431 case RTX_COMM_ARITH:
3433 case RTX_COMM_COMPARE:
3434 split = find_split_point (&XEXP (x, 1), insn);
3437 /* ... fall through ... */
3439 /* Some machines have (and (shift ...) ...) insns. If X is not
3440 an AND, but XEXP (X, 0) is, use it as our split point. */
3441 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3442 return &XEXP (x, 0);
3444 split = find_split_point (&XEXP (x, 0), insn);
3450 /* Otherwise, we don't have a split point. */
3455 /* Throughout X, replace FROM with TO, and return the result.
3456 The result is TO if X is FROM;
3457 otherwise the result is X, but its contents may have been modified.
3458 If they were modified, a record was made in undobuf so that
3459 undo_all will (among other things) return X to its original state.
3461 If the number of changes necessary is too much to record to undo,
3462 the excess changes are not made, so the result is invalid.
3463 The changes already made can still be undone.
3464 undobuf.num_undo is incremented for such changes, so by testing that
3465 the caller can tell whether the result is valid.
3467 `n_occurrences' is incremented each time FROM is replaced.
3469 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3471 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3472 by copying if `n_occurrences' is nonzero. */
3475 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3477 enum rtx_code code = GET_CODE (x);
3478 enum machine_mode op0_mode = VOIDmode;
3483 /* Two expressions are equal if they are identical copies of a shared
3484 RTX or if they are both registers with the same register number
3487 #define COMBINE_RTX_EQUAL_P(X,Y) \
3489 || (REG_P (X) && REG_P (Y) \
3490 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3492 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3495 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3498 /* If X and FROM are the same register but different modes, they will
3499 not have been seen as equal above. However, flow.c will make a
3500 LOG_LINKS entry for that case. If we do nothing, we will try to
3501 rerecognize our original insn and, when it succeeds, we will
3502 delete the feeding insn, which is incorrect.
3504 So force this insn not to match in this (rare) case. */
3505 if (! in_dest && code == REG && REG_P (from)
3506 && REGNO (x) == REGNO (from))
3507 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3509 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3510 of which may contain things that can be combined. */
3511 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3514 /* It is possible to have a subexpression appear twice in the insn.
3515 Suppose that FROM is a register that appears within TO.
3516 Then, after that subexpression has been scanned once by `subst',
3517 the second time it is scanned, TO may be found. If we were
3518 to scan TO here, we would find FROM within it and create a
3519 self-referent rtl structure which is completely wrong. */
3520 if (COMBINE_RTX_EQUAL_P (x, to))
3523 /* Parallel asm_operands need special attention because all of the
3524 inputs are shared across the arms. Furthermore, unsharing the
3525 rtl results in recognition failures. Failure to handle this case
3526 specially can result in circular rtl.
3528 Solve this by doing a normal pass across the first entry of the
3529 parallel, and only processing the SET_DESTs of the subsequent
3532 if (code == PARALLEL
3533 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3534 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3536 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3538 /* If this substitution failed, this whole thing fails. */
3539 if (GET_CODE (new) == CLOBBER
3540 && XEXP (new, 0) == const0_rtx)
3543 SUBST (XVECEXP (x, 0, 0), new);
3545 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3547 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3550 && GET_CODE (dest) != CC0
3551 && GET_CODE (dest) != PC)
3553 new = subst (dest, from, to, 0, unique_copy);
3555 /* If this substitution failed, this whole thing fails. */
3556 if (GET_CODE (new) == CLOBBER
3557 && XEXP (new, 0) == const0_rtx)
3560 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3566 len = GET_RTX_LENGTH (code);
3567 fmt = GET_RTX_FORMAT (code);
3569 /* We don't need to process a SET_DEST that is a register, CC0,
3570 or PC, so set up to skip this common case. All other cases
3571 where we want to suppress replacing something inside a
3572 SET_SRC are handled via the IN_DEST operand. */
3574 && (REG_P (SET_DEST (x))
3575 || GET_CODE (SET_DEST (x)) == CC0
3576 || GET_CODE (SET_DEST (x)) == PC))
3579 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3582 op0_mode = GET_MODE (XEXP (x, 0));
3584 for (i = 0; i < len; i++)
3589 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3591 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3593 new = (unique_copy && n_occurrences
3594 ? copy_rtx (to) : to);
3599 new = subst (XVECEXP (x, i, j), from, to, 0,
3602 /* If this substitution failed, this whole thing
3604 if (GET_CODE (new) == CLOBBER
3605 && XEXP (new, 0) == const0_rtx)
3609 SUBST (XVECEXP (x, i, j), new);
3612 else if (fmt[i] == 'e')
3614 /* If this is a register being set, ignore it. */
3618 && (((code == SUBREG || code == ZERO_EXTRACT)
3620 || code == STRICT_LOW_PART))
3623 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3625 /* In general, don't install a subreg involving two
3626 modes not tieable. It can worsen register
3627 allocation, and can even make invalid reload
3628 insns, since the reg inside may need to be copied
3629 from in the outside mode, and that may be invalid
3630 if it is an fp reg copied in integer mode.
3632 We allow two exceptions to this: It is valid if
3633 it is inside another SUBREG and the mode of that
3634 SUBREG and the mode of the inside of TO is
3635 tieable and it is valid if X is a SET that copies
3638 if (GET_CODE (to) == SUBREG
3639 && ! MODES_TIEABLE_P (GET_MODE (to),
3640 GET_MODE (SUBREG_REG (to)))
3641 && ! (code == SUBREG
3642 && MODES_TIEABLE_P (GET_MODE (x),
3643 GET_MODE (SUBREG_REG (to))))
3645 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3648 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3650 #ifdef CANNOT_CHANGE_MODE_CLASS
3653 && REGNO (to) < FIRST_PSEUDO_REGISTER
3654 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3657 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3660 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3664 /* If we are in a SET_DEST, suppress most cases unless we
3665 have gone inside a MEM, in which case we want to
3666 simplify the address. We assume here that things that
3667 are actually part of the destination have their inner
3668 parts in the first expression. This is true for SUBREG,
3669 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3670 things aside from REG and MEM that should appear in a
3672 new = subst (XEXP (x, i), from, to,
3674 && (code == SUBREG || code == STRICT_LOW_PART
3675 || code == ZERO_EXTRACT))
3677 && i == 0), unique_copy);
3679 /* If we found that we will have to reject this combination,
3680 indicate that by returning the CLOBBER ourselves, rather than
3681 an expression containing it. This will speed things up as
3682 well as prevent accidents where two CLOBBERs are considered
3683 to be equal, thus producing an incorrect simplification. */
3685 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3688 if (GET_CODE (x) == SUBREG
3689 && (GET_CODE (new) == CONST_INT
3690 || GET_CODE (new) == CONST_DOUBLE))
3692 enum machine_mode mode = GET_MODE (x);
3694 x = simplify_subreg (GET_MODE (x), new,
3695 GET_MODE (SUBREG_REG (x)),
3698 x = gen_rtx_CLOBBER (mode, const0_rtx);
3700 else if (GET_CODE (new) == CONST_INT
3701 && GET_CODE (x) == ZERO_EXTEND)
3703 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3704 new, GET_MODE (XEXP (x, 0)));
3708 SUBST (XEXP (x, i), new);
3713 /* Try to simplify X. If the simplification changed the code, it is likely
3714 that further simplification will help, so loop, but limit the number
3715 of repetitions that will be performed. */
3717 for (i = 0; i < 4; i++)
3719 /* If X is sufficiently simple, don't bother trying to do anything
3721 if (code != CONST_INT && code != REG && code != CLOBBER)
3722 x = combine_simplify_rtx (x, op0_mode, in_dest);
3724 if (GET_CODE (x) == code)
3727 code = GET_CODE (x);
3729 /* We no longer know the original mode of operand 0 since we
3730 have changed the form of X) */
3731 op0_mode = VOIDmode;
3737 /* Simplify X, a piece of RTL. We just operate on the expression at the
3738 outer level; call `subst' to simplify recursively. Return the new
3741 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3742 if we are inside a SET_DEST. */
3745 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3747 enum rtx_code code = GET_CODE (x);
3748 enum machine_mode mode = GET_MODE (x);
3753 /* If this is a commutative operation, put a constant last and a complex
3754 expression first. We don't need to do this for comparisons here. */
3755 if (COMMUTATIVE_ARITH_P (x)
3756 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3759 SUBST (XEXP (x, 0), XEXP (x, 1));
3760 SUBST (XEXP (x, 1), temp);
3763 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3764 sign extension of a PLUS with a constant, reverse the order of the sign
3765 extension and the addition. Note that this not the same as the original
3766 code, but overflow is undefined for signed values. Also note that the
3767 PLUS will have been partially moved "inside" the sign-extension, so that
3768 the first operand of X will really look like:
3769 (ashiftrt (plus (ashift A C4) C5) C4).
3771 (plus (ashiftrt (ashift A C4) C2) C4)
3772 and replace the first operand of X with that expression. Later parts
3773 of this function may simplify the expression further.
3775 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3776 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3777 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3779 We do this to simplify address expressions. */
3781 if ((code == PLUS || code == MINUS || code == MULT)
3782 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3783 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3784 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3785 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3786 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3787 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3788 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3789 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3790 XEXP (XEXP (XEXP (x, 0), 0), 1),
3791 XEXP (XEXP (x, 0), 1))) != 0)
3794 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3795 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3796 INTVAL (XEXP (XEXP (x, 0), 1)));
3798 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3799 INTVAL (XEXP (XEXP (x, 0), 1)));
3801 SUBST (XEXP (x, 0), simplify_gen_binary (PLUS, mode, new, temp));
3804 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3805 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3806 things. Check for cases where both arms are testing the same
3809 Don't do anything if all operands are very simple. */
3812 && ((!OBJECT_P (XEXP (x, 0))
3813 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3814 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3815 || (!OBJECT_P (XEXP (x, 1))
3816 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3817 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3819 && (!OBJECT_P (XEXP (x, 0))
3820 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3821 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3823 rtx cond, true_rtx, false_rtx;
3825 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3827 /* If everything is a comparison, what we have is highly unlikely
3828 to be simpler, so don't use it. */
3829 && ! (COMPARISON_P (x)
3830 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3832 rtx cop1 = const0_rtx;
3833 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3835 if (cond_code == NE && COMPARISON_P (cond))
3838 /* Simplify the alternative arms; this may collapse the true and
3839 false arms to store-flag values. Be careful to use copy_rtx
3840 here since true_rtx or false_rtx might share RTL with x as a
3841 result of the if_then_else_cond call above. */
3842 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3843 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3845 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3846 is unlikely to be simpler. */
3847 if (general_operand (true_rtx, VOIDmode)
3848 && general_operand (false_rtx, VOIDmode))
3850 enum rtx_code reversed;
3852 /* Restarting if we generate a store-flag expression will cause
3853 us to loop. Just drop through in this case. */
3855 /* If the result values are STORE_FLAG_VALUE and zero, we can
3856 just make the comparison operation. */
3857 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3858 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3860 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3861 && ((reversed = reversed_comparison_code_parts
3862 (cond_code, cond, cop1, NULL))
3864 x = simplify_gen_relational (reversed, mode, VOIDmode,
3867 /* Likewise, we can make the negate of a comparison operation
3868 if the result values are - STORE_FLAG_VALUE and zero. */
3869 else if (GET_CODE (true_rtx) == CONST_INT
3870 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3871 && false_rtx == const0_rtx)
3872 x = simplify_gen_unary (NEG, mode,
3873 simplify_gen_relational (cond_code,
3877 else if (GET_CODE (false_rtx) == CONST_INT
3878 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3879 && true_rtx == const0_rtx
3880 && ((reversed = reversed_comparison_code_parts
3881 (cond_code, cond, cop1, NULL))
3883 x = simplify_gen_unary (NEG, mode,
3884 simplify_gen_relational (reversed,
3889 return gen_rtx_IF_THEN_ELSE (mode,
3890 simplify_gen_relational (cond_code,
3895 true_rtx, false_rtx);
3897 code = GET_CODE (x);
3898 op0_mode = VOIDmode;
3903 /* Try to fold this expression in case we have constants that weren't
3906 switch (GET_RTX_CLASS (code))
3909 if (op0_mode == VOIDmode)
3910 op0_mode = GET_MODE (XEXP (x, 0));
3911 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3914 case RTX_COMM_COMPARE:
3916 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3917 if (cmp_mode == VOIDmode)
3919 cmp_mode = GET_MODE (XEXP (x, 1));
3920 if (cmp_mode == VOIDmode)
3921 cmp_mode = op0_mode;
3923 temp = simplify_relational_operation (code, mode, cmp_mode,
3924 XEXP (x, 0), XEXP (x, 1));
3927 case RTX_COMM_ARITH:
3929 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3931 case RTX_BITFIELD_OPS:
3933 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3934 XEXP (x, 1), XEXP (x, 2));
3943 code = GET_CODE (temp);
3944 op0_mode = VOIDmode;
3945 mode = GET_MODE (temp);
3948 /* First see if we can apply the inverse distributive law. */
3949 if (code == PLUS || code == MINUS
3950 || code == AND || code == IOR || code == XOR)
3952 x = apply_distributive_law (x);
3953 code = GET_CODE (x);
3954 op0_mode = VOIDmode;
3957 /* If CODE is an associative operation not otherwise handled, see if we
3958 can associate some operands. This can win if they are constants or
3959 if they are logically related (i.e. (a & b) & a). */
3960 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3961 || code == AND || code == IOR || code == XOR
3962 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3963 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3964 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3966 if (GET_CODE (XEXP (x, 0)) == code)
3968 rtx other = XEXP (XEXP (x, 0), 0);
3969 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3970 rtx inner_op1 = XEXP (x, 1);
3973 /* Make sure we pass the constant operand if any as the second
3974 one if this is a commutative operation. */
3975 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3977 rtx tem = inner_op0;
3978 inner_op0 = inner_op1;
3981 inner = simplify_binary_operation (code == MINUS ? PLUS
3982 : code == DIV ? MULT
3984 mode, inner_op0, inner_op1);
3986 /* For commutative operations, try the other pair if that one
3988 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3990 other = XEXP (XEXP (x, 0), 1);
3991 inner = simplify_binary_operation (code, mode,
3992 XEXP (XEXP (x, 0), 0),
3997 return simplify_gen_binary (code, mode, other, inner);
4001 /* A little bit of algebraic simplification here. */
4005 /* Ensure that our address has any ASHIFTs converted to MULT in case
4006 address-recognizing predicates are called later. */
4007 temp = make_compound_operation (XEXP (x, 0), MEM);
4008 SUBST (XEXP (x, 0), temp);
4012 if (op0_mode == VOIDmode)
4013 op0_mode = GET_MODE (SUBREG_REG (x));
4015 /* See if this can be moved to simplify_subreg. */
4016 if (CONSTANT_P (SUBREG_REG (x))
4017 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4018 /* Don't call gen_lowpart if the inner mode
4019 is VOIDmode and we cannot simplify it, as SUBREG without
4020 inner mode is invalid. */
4021 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4022 || gen_lowpart_common (mode, SUBREG_REG (x))))
4023 return gen_lowpart (mode, SUBREG_REG (x));
4025 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4029 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4035 /* Don't change the mode of the MEM if that would change the meaning
4037 if (MEM_P (SUBREG_REG (x))
4038 && (MEM_VOLATILE_P (SUBREG_REG (x))
4039 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4040 return gen_rtx_CLOBBER (mode, const0_rtx);
4042 /* Note that we cannot do any narrowing for non-constants since
4043 we might have been counting on using the fact that some bits were
4044 zero. We now do this in the SET. */
4049 if (GET_CODE (XEXP (x, 0)) == SUBREG
4050 && subreg_lowpart_p (XEXP (x, 0))
4051 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4052 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4053 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4054 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4056 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4058 x = gen_rtx_ROTATE (inner_mode,
4059 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4061 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4062 return gen_lowpart (mode, x);
4065 /* Apply De Morgan's laws to reduce number of patterns for machines
4066 with negating logical insns (and-not, nand, etc.). If result has
4067 only one NOT, put it first, since that is how the patterns are
4070 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4072 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4073 enum machine_mode op_mode;
4075 op_mode = GET_MODE (in1);
4076 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4078 op_mode = GET_MODE (in2);
4079 if (op_mode == VOIDmode)
4081 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4083 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4086 in2 = in1; in1 = tem;
4089 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4095 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4096 if (GET_CODE (XEXP (x, 0)) == XOR
4097 && XEXP (XEXP (x, 0), 1) == const1_rtx
4098 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4099 return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4102 temp = expand_compound_operation (XEXP (x, 0));
4104 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4105 replaced by (lshiftrt X C). This will convert
4106 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4108 if (GET_CODE (temp) == ASHIFTRT
4109 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4110 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4111 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4112 INTVAL (XEXP (temp, 1)));
4114 /* If X has only a single bit that might be nonzero, say, bit I, convert
4115 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4116 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4117 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4118 or a SUBREG of one since we'd be making the expression more
4119 complex if it was just a register. */
4122 && ! (GET_CODE (temp) == SUBREG
4123 && REG_P (SUBREG_REG (temp)))
4124 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4126 rtx temp1 = simplify_shift_const
4127 (NULL_RTX, ASHIFTRT, mode,
4128 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4129 GET_MODE_BITSIZE (mode) - 1 - i),
4130 GET_MODE_BITSIZE (mode) - 1 - i);
4132 /* If all we did was surround TEMP with the two shifts, we
4133 haven't improved anything, so don't use it. Otherwise,
4134 we are better off with TEMP1. */
4135 if (GET_CODE (temp1) != ASHIFTRT
4136 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4137 || XEXP (XEXP (temp1, 0), 0) != temp)
4143 /* We can't handle truncation to a partial integer mode here
4144 because we don't know the real bitsize of the partial
4146 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4149 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4150 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4151 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4153 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4154 GET_MODE_MASK (mode), NULL_RTX, 0));
4156 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4157 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4158 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4159 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4160 return XEXP (XEXP (x, 0), 0);
4162 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4163 (OP:SI foo:SI) if OP is NEG or ABS. */
4164 if ((GET_CODE (XEXP (x, 0)) == ABS
4165 || GET_CODE (XEXP (x, 0)) == NEG)
4166 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4167 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4168 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4169 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4170 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4172 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4174 if (GET_CODE (XEXP (x, 0)) == SUBREG
4175 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4176 && subreg_lowpart_p (XEXP (x, 0)))
4177 return SUBREG_REG (XEXP (x, 0));
4179 /* If we know that the value is already truncated, we can
4180 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4181 is nonzero for the corresponding modes. But don't do this
4182 for an (LSHIFTRT (MULT ...)) since this will cause problems
4183 with the umulXi3_highpart patterns. */
4184 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4185 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4186 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4187 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4188 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4189 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4190 return gen_lowpart (mode, XEXP (x, 0));
4192 /* A truncate of a comparison can be replaced with a subreg if
4193 STORE_FLAG_VALUE permits. This is like the previous test,
4194 but it works even if the comparison is done in a mode larger
4195 than HOST_BITS_PER_WIDE_INT. */
4196 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4197 && COMPARISON_P (XEXP (x, 0))
4198 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4199 return gen_lowpart (mode, XEXP (x, 0));
4201 /* Similarly, a truncate of a register whose value is a
4202 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4204 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4205 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4206 && (temp = get_last_value (XEXP (x, 0)))
4207 && COMPARISON_P (temp))
4208 return gen_lowpart (mode, XEXP (x, 0));
4212 case FLOAT_TRUNCATE:
4213 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4214 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4215 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4216 return XEXP (XEXP (x, 0), 0);
4218 /* (float_truncate:SF (float_truncate:DF foo:XF))
4219 = (float_truncate:SF foo:XF).
4220 This may eliminate double rounding, so it is unsafe.
4222 (float_truncate:SF (float_extend:XF foo:DF))
4223 = (float_truncate:SF foo:DF).
4225 (float_truncate:DF (float_extend:XF foo:SF))
4226 = (float_extend:SF foo:DF). */
4227 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4228 && flag_unsafe_math_optimizations)
4229 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4230 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4232 > GET_MODE_SIZE (mode)
4233 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4235 XEXP (XEXP (x, 0), 0), mode);
4237 /* (float_truncate (float x)) is (float x) */
4238 if (GET_CODE (XEXP (x, 0)) == FLOAT
4239 && (flag_unsafe_math_optimizations
4240 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4241 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4242 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4243 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4244 return simplify_gen_unary (FLOAT, mode,
4245 XEXP (XEXP (x, 0), 0),
4246 GET_MODE (XEXP (XEXP (x, 0), 0)));
4248 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4249 (OP:SF foo:SF) if OP is NEG or ABS. */
4250 if ((GET_CODE (XEXP (x, 0)) == ABS
4251 || GET_CODE (XEXP (x, 0)) == NEG)
4252 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4253 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4254 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4255 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4257 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4258 is (float_truncate:SF x). */
4259 if (GET_CODE (XEXP (x, 0)) == SUBREG
4260 && subreg_lowpart_p (XEXP (x, 0))
4261 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4262 return SUBREG_REG (XEXP (x, 0));
4265 /* (float_extend (float_extend x)) is (float_extend x)
4267 (float_extend (float x)) is (float x) assuming that double
4268 rounding can't happen.
4270 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4271 || (GET_CODE (XEXP (x, 0)) == FLOAT
4272 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4273 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4274 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4275 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4276 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4277 XEXP (XEXP (x, 0), 0),
4278 GET_MODE (XEXP (XEXP (x, 0), 0)));
4283 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4284 using cc0, in which case we want to leave it as a COMPARE
4285 so we can distinguish it from a register-register-copy. */
4286 if (XEXP (x, 1) == const0_rtx)
4289 /* x - 0 is the same as x unless x's mode has signed zeros and
4290 allows rounding towards -infinity. Under those conditions,
4292 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4293 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4294 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4300 /* (const (const X)) can become (const X). Do it this way rather than
4301 returning the inner CONST since CONST can be shared with a
4303 if (GET_CODE (XEXP (x, 0)) == CONST)
4304 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4309 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4310 can add in an offset. find_split_point will split this address up
4311 again if it doesn't match. */
4312 if (GET_CODE (XEXP (x, 0)) == HIGH
4313 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4319 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4321 if (GET_CODE (XEXP (x, 0)) == MULT
4322 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4326 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4327 in2 = XEXP (XEXP (x, 0), 1);
4328 return simplify_gen_binary (MINUS, mode, XEXP (x, 1),
4329 simplify_gen_binary (MULT, mode,
4333 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4334 outermost. That's because that's the way indexed addresses are
4335 supposed to appear. This code used to check many more cases, but
4336 they are now checked elsewhere. */
4337 if (GET_CODE (XEXP (x, 0)) == PLUS
4338 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4339 return simplify_gen_binary (PLUS, mode,
4340 simplify_gen_binary (PLUS, mode,
4341 XEXP (XEXP (x, 0), 0),
4343 XEXP (XEXP (x, 0), 1));
4345 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4346 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4347 bit-field and can be replaced by either a sign_extend or a
4348 sign_extract. The `and' may be a zero_extend and the two
4349 <c>, -<c> constants may be reversed. */
4350 if (GET_CODE (XEXP (x, 0)) == XOR
4351 && GET_CODE (XEXP (x, 1)) == CONST_INT
4352 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4353 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4354 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4355 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4356 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4357 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4358 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4359 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4360 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4361 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4362 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4363 == (unsigned int) i + 1))))
4364 return simplify_shift_const
4365 (NULL_RTX, ASHIFTRT, mode,
4366 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4367 XEXP (XEXP (XEXP (x, 0), 0), 0),
4368 GET_MODE_BITSIZE (mode) - (i + 1)),
4369 GET_MODE_BITSIZE (mode) - (i + 1));
4371 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4372 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4373 is 1. This produces better code than the alternative immediately
4375 if (COMPARISON_P (XEXP (x, 0))
4376 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4377 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4378 && (reversed = reversed_comparison (XEXP (x, 0), mode)))
4380 simplify_gen_unary (NEG, mode, reversed, mode);
4382 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4383 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4384 the bitsize of the mode - 1. This allows simplification of
4385 "a = (b & 8) == 0;" */
4386 if (XEXP (x, 1) == constm1_rtx
4387 && !REG_P (XEXP (x, 0))
4388 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4389 && REG_P (SUBREG_REG (XEXP (x, 0))))
4390 && nonzero_bits (XEXP (x, 0), mode) == 1)
4391 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4392 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4393 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4394 GET_MODE_BITSIZE (mode) - 1),
4395 GET_MODE_BITSIZE (mode) - 1);
4397 /* If we are adding two things that have no bits in common, convert
4398 the addition into an IOR. This will often be further simplified,
4399 for example in cases like ((a & 1) + (a & 2)), which can
4402 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4403 && (nonzero_bits (XEXP (x, 0), mode)
4404 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4406 /* Try to simplify the expression further. */
4407 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4408 temp = combine_simplify_rtx (tor, mode, in_dest);
4410 /* If we could, great. If not, do not go ahead with the IOR
4411 replacement, since PLUS appears in many special purpose
4412 address arithmetic instructions. */
4413 if (GET_CODE (temp) != CLOBBER && temp != tor)
4419 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4420 by reversing the comparison code if valid. */
4421 if (STORE_FLAG_VALUE == 1
4422 && XEXP (x, 0) == const1_rtx
4423 && COMPARISON_P (XEXP (x, 1))
4424 && (reversed = reversed_comparison (XEXP (x, 1), mode)))
4427 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4428 (and <foo> (const_int pow2-1)) */
4429 if (GET_CODE (XEXP (x, 1)) == AND
4430 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4431 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4432 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4433 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4434 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4436 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4438 if (GET_CODE (XEXP (x, 1)) == MULT
4439 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4443 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4444 in2 = XEXP (XEXP (x, 1), 1);
4445 return simplify_gen_binary (PLUS, mode,
4446 simplify_gen_binary (MULT, mode,
4451 /* Canonicalize (minus (neg A) (mult B C)) to
4452 (minus (mult (neg B) C) A). */
4453 if (GET_CODE (XEXP (x, 1)) == MULT
4454 && GET_CODE (XEXP (x, 0)) == NEG)
4458 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4459 in2 = XEXP (XEXP (x, 1), 1);
4460 return simplify_gen_binary (MINUS, mode,
4461 simplify_gen_binary (MULT, mode,
4463 XEXP (XEXP (x, 0), 0));
4466 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4468 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4469 return simplify_gen_binary (MINUS, mode,
4470 simplify_gen_binary (MINUS, mode,
4472 XEXP (XEXP (x, 1), 0)),
4473 XEXP (XEXP (x, 1), 1));
4477 /* If we have (mult (plus A B) C), apply the distributive law and then
4478 the inverse distributive law to see if things simplify. This
4479 occurs mostly in addresses, often when unrolling loops. */
4481 if (GET_CODE (XEXP (x, 0)) == PLUS)
4483 rtx result = distribute_and_simplify_rtx (x, 0);
4488 /* Try simplify a*(b/c) as (a*b)/c. */
4489 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4490 && GET_CODE (XEXP (x, 0)) == DIV)
4492 rtx tem = simplify_binary_operation (MULT, mode,
4493 XEXP (XEXP (x, 0), 0),
4496 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4501 /* If this is a divide by a power of two, treat it as a shift if
4502 its first operand is a shift. */
4503 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4504 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4505 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4506 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4507 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4508 || GET_CODE (XEXP (x, 0)) == ROTATE
4509 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4510 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4514 case GT: case GTU: case GE: case GEU:
4515 case LT: case LTU: case LE: case LEU:
4516 case UNEQ: case LTGT:
4517 case UNGT: case UNGE:
4518 case UNLT: case UNLE:
4519 case UNORDERED: case ORDERED:
4520 /* If the first operand is a condition code, we can't do anything
4522 if (GET_CODE (XEXP (x, 0)) == COMPARE
4523 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4524 && ! CC0_P (XEXP (x, 0))))
4526 rtx op0 = XEXP (x, 0);
4527 rtx op1 = XEXP (x, 1);
4528 enum rtx_code new_code;
4530 if (GET_CODE (op0) == COMPARE)
4531 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4533 /* Simplify our comparison, if possible. */
4534 new_code = simplify_comparison (code, &op0, &op1);
4536 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4537 if only the low-order bit is possibly nonzero in X (such as when
4538 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4539 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4540 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4543 Remove any ZERO_EXTRACT we made when thinking this was a
4544 comparison. It may now be simpler to use, e.g., an AND. If a
4545 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4546 the call to make_compound_operation in the SET case. */
4548 if (STORE_FLAG_VALUE == 1
4549 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4550 && op1 == const0_rtx
4551 && mode == GET_MODE (op0)
4552 && nonzero_bits (op0, mode) == 1)
4553 return gen_lowpart (mode,
4554 expand_compound_operation (op0));
4556 else if (STORE_FLAG_VALUE == 1
4557 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4558 && op1 == const0_rtx
4559 && mode == GET_MODE (op0)
4560 && (num_sign_bit_copies (op0, mode)
4561 == GET_MODE_BITSIZE (mode)))
4563 op0 = expand_compound_operation (op0);
4564 return simplify_gen_unary (NEG, mode,
4565 gen_lowpart (mode, op0),
4569 else if (STORE_FLAG_VALUE == 1
4570 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4571 && op1 == const0_rtx
4572 && mode == GET_MODE (op0)
4573 && nonzero_bits (op0, mode) == 1)
4575 op0 = expand_compound_operation (op0);
4576 return simplify_gen_binary (XOR, mode,
4577 gen_lowpart (mode, op0),
4581 else if (STORE_FLAG_VALUE == 1
4582 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4583 && op1 == const0_rtx
4584 && mode == GET_MODE (op0)
4585 && (num_sign_bit_copies (op0, mode)
4586 == GET_MODE_BITSIZE (mode)))
4588 op0 = expand_compound_operation (op0);
4589 return plus_constant (gen_lowpart (mode, op0), 1);
4592 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4594 if (STORE_FLAG_VALUE == -1
4595 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4596 && op1 == const0_rtx
4597 && (num_sign_bit_copies (op0, mode)
4598 == GET_MODE_BITSIZE (mode)))
4599 return gen_lowpart (mode,
4600 expand_compound_operation (op0));
4602 else if (STORE_FLAG_VALUE == -1
4603 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4604 && op1 == const0_rtx
4605 && mode == GET_MODE (op0)
4606 && nonzero_bits (op0, mode) == 1)
4608 op0 = expand_compound_operation (op0);
4609 return simplify_gen_unary (NEG, mode,
4610 gen_lowpart (mode, op0),
4614 else if (STORE_FLAG_VALUE == -1
4615 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4616 && op1 == const0_rtx
4617 && mode == GET_MODE (op0)
4618 && (num_sign_bit_copies (op0, mode)
4619 == GET_MODE_BITSIZE (mode)))
4621 op0 = expand_compound_operation (op0);
4622 return simplify_gen_unary (NOT, mode,
4623 gen_lowpart (mode, op0),
4627 /* If X is 0/1, (eq X 0) is X-1. */
4628 else if (STORE_FLAG_VALUE == -1
4629 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4630 && op1 == const0_rtx
4631 && mode == GET_MODE (op0)
4632 && nonzero_bits (op0, mode) == 1)
4634 op0 = expand_compound_operation (op0);
4635 return plus_constant (gen_lowpart (mode, op0), -1);
4638 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4639 one bit that might be nonzero, we can convert (ne x 0) to
4640 (ashift x c) where C puts the bit in the sign bit. Remove any
4641 AND with STORE_FLAG_VALUE when we are done, since we are only
4642 going to test the sign bit. */
4643 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4644 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4645 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4646 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4647 && op1 == const0_rtx
4648 && mode == GET_MODE (op0)
4649 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4651 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4652 expand_compound_operation (op0),
4653 GET_MODE_BITSIZE (mode) - 1 - i);
4654 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4660 /* If the code changed, return a whole new comparison. */
4661 if (new_code != code)
4662 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4664 /* Otherwise, keep this operation, but maybe change its operands.
4665 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4666 SUBST (XEXP (x, 0), op0);
4667 SUBST (XEXP (x, 1), op1);
4672 return simplify_if_then_else (x);
4678 /* If we are processing SET_DEST, we are done. */
4682 return expand_compound_operation (x);
4685 return simplify_set (x);
4690 return simplify_logical (x);
4693 /* (abs (neg <foo>)) -> (abs <foo>) */
4694 if (GET_CODE (XEXP (x, 0)) == NEG)
4695 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4697 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4699 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4702 /* If operand is something known to be positive, ignore the ABS. */
4703 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4704 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4705 <= HOST_BITS_PER_WIDE_INT)
4706 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4707 & ((HOST_WIDE_INT) 1
4708 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4712 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4713 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4714 return gen_rtx_NEG (mode, XEXP (x, 0));
4719 /* (ffs (*_extend <X>)) = (ffs <X>) */
4720 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4721 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4722 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4727 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4728 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4729 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4733 /* (float (sign_extend <X>)) = (float <X>). */
4734 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4735 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4743 /* If this is a shift by a constant amount, simplify it. */
4744 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4745 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4746 INTVAL (XEXP (x, 1)));
4748 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4750 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4752 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4759 rtx op0 = XEXP (x, 0);
4760 rtx op1 = XEXP (x, 1);
4763 gcc_assert (GET_CODE (op1) == PARALLEL);
4764 len = XVECLEN (op1, 0);
4766 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4767 && GET_CODE (op0) == VEC_CONCAT)
4769 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4771 /* Try to find the element in the VEC_CONCAT. */
4774 if (GET_MODE (op0) == GET_MODE (x))
4776 if (GET_CODE (op0) == VEC_CONCAT)
4778 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4779 if (op0_size < offset)
4780 op0 = XEXP (op0, 0);
4784 op0 = XEXP (op0, 1);
4802 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4805 simplify_if_then_else (rtx x)
4807 enum machine_mode mode = GET_MODE (x);
4808 rtx cond = XEXP (x, 0);
4809 rtx true_rtx = XEXP (x, 1);
4810 rtx false_rtx = XEXP (x, 2);
4811 enum rtx_code true_code = GET_CODE (cond);
4812 int comparison_p = COMPARISON_P (cond);
4815 enum rtx_code false_code;
4818 /* Simplify storing of the truth value. */
4819 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4820 return simplify_gen_relational (true_code, mode, VOIDmode,
4821 XEXP (cond, 0), XEXP (cond, 1));
4823 /* Also when the truth value has to be reversed. */
4825 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4826 && (reversed = reversed_comparison (cond, mode)))
4829 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4830 in it is being compared against certain values. Get the true and false
4831 comparisons and see if that says anything about the value of each arm. */
4834 && ((false_code = reversed_comparison_code (cond, NULL))
4836 && REG_P (XEXP (cond, 0)))
4839 rtx from = XEXP (cond, 0);
4840 rtx true_val = XEXP (cond, 1);
4841 rtx false_val = true_val;
4844 /* If FALSE_CODE is EQ, swap the codes and arms. */
4846 if (false_code == EQ)
4848 swapped = 1, true_code = EQ, false_code = NE;
4849 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4852 /* If we are comparing against zero and the expression being tested has
4853 only a single bit that might be nonzero, that is its value when it is
4854 not equal to zero. Similarly if it is known to be -1 or 0. */
4856 if (true_code == EQ && true_val == const0_rtx
4857 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4858 false_code = EQ, false_val = GEN_INT (nzb);
4859 else if (true_code == EQ && true_val == const0_rtx
4860 && (num_sign_bit_copies (from, GET_MODE (from))
4861 == GET_MODE_BITSIZE (GET_MODE (from))))
4862 false_code = EQ, false_val = constm1_rtx;
4864 /* Now simplify an arm if we know the value of the register in the
4865 branch and it is used in the arm. Be careful due to the potential
4866 of locally-shared RTL. */
4868 if (reg_mentioned_p (from, true_rtx))
4869 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4871 pc_rtx, pc_rtx, 0, 0);
4872 if (reg_mentioned_p (from, false_rtx))
4873 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4875 pc_rtx, pc_rtx, 0, 0);
4877 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4878 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4880 true_rtx = XEXP (x, 1);
4881 false_rtx = XEXP (x, 2);
4882 true_code = GET_CODE (cond);
4885 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4886 reversed, do so to avoid needing two sets of patterns for
4887 subtract-and-branch insns. Similarly if we have a constant in the true
4888 arm, the false arm is the same as the first operand of the comparison, or
4889 the false arm is more complicated than the true arm. */
4892 && reversed_comparison_code (cond, NULL) != UNKNOWN
4893 && (true_rtx == pc_rtx
4894 || (CONSTANT_P (true_rtx)
4895 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4896 || true_rtx == const0_rtx
4897 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4898 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4899 && !OBJECT_P (false_rtx))
4900 || reg_mentioned_p (true_rtx, false_rtx)
4901 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4903 true_code = reversed_comparison_code (cond, NULL);
4904 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4905 SUBST (XEXP (x, 1), false_rtx);
4906 SUBST (XEXP (x, 2), true_rtx);
4908 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4911 /* It is possible that the conditional has been simplified out. */
4912 true_code = GET_CODE (cond);
4913 comparison_p = COMPARISON_P (cond);
4916 /* If the two arms are identical, we don't need the comparison. */
4918 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4921 /* Convert a == b ? b : a to "a". */
4922 if (true_code == EQ && ! side_effects_p (cond)
4923 && !HONOR_NANS (mode)
4924 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4925 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4927 else if (true_code == NE && ! side_effects_p (cond)
4928 && !HONOR_NANS (mode)
4929 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4930 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4933 /* Look for cases where we have (abs x) or (neg (abs X)). */
4935 if (GET_MODE_CLASS (mode) == MODE_INT
4936 && GET_CODE (false_rtx) == NEG
4937 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4939 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4940 && ! side_effects_p (true_rtx))
4945 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4949 simplify_gen_unary (NEG, mode,
4950 simplify_gen_unary (ABS, mode, true_rtx, mode),
4956 /* Look for MIN or MAX. */
4958 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4960 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4961 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4962 && ! side_effects_p (cond))
4967 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4970 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4973 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4976 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4981 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4982 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4983 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4984 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4985 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4986 neither 1 or -1, but it isn't worth checking for. */
4988 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4990 && GET_MODE_CLASS (mode) == MODE_INT
4991 && ! side_effects_p (x))
4993 rtx t = make_compound_operation (true_rtx, SET);
4994 rtx f = make_compound_operation (false_rtx, SET);
4995 rtx cond_op0 = XEXP (cond, 0);
4996 rtx cond_op1 = XEXP (cond, 1);
4997 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4998 enum machine_mode m = mode;
4999 rtx z = 0, c1 = NULL_RTX;
5001 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5002 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5003 || GET_CODE (t) == ASHIFT
5004 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5005 && rtx_equal_p (XEXP (t, 0), f))
5006 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5008 /* If an identity-zero op is commutative, check whether there
5009 would be a match if we swapped the operands. */
5010 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5011 || GET_CODE (t) == XOR)
5012 && rtx_equal_p (XEXP (t, 1), f))
5013 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5014 else if (GET_CODE (t) == SIGN_EXTEND
5015 && (GET_CODE (XEXP (t, 0)) == PLUS
5016 || GET_CODE (XEXP (t, 0)) == MINUS
5017 || GET_CODE (XEXP (t, 0)) == IOR
5018 || GET_CODE (XEXP (t, 0)) == XOR
5019 || GET_CODE (XEXP (t, 0)) == ASHIFT
5020 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5021 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5022 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5023 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5024 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5025 && (num_sign_bit_copies (f, GET_MODE (f))
5027 (GET_MODE_BITSIZE (mode)
5028 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5030 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5031 extend_op = SIGN_EXTEND;
5032 m = GET_MODE (XEXP (t, 0));
5034 else if (GET_CODE (t) == SIGN_EXTEND
5035 && (GET_CODE (XEXP (t, 0)) == PLUS
5036 || GET_CODE (XEXP (t, 0)) == IOR
5037 || GET_CODE (XEXP (t, 0)) == XOR)
5038 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5039 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5040 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5041 && (num_sign_bit_copies (f, GET_MODE (f))
5043 (GET_MODE_BITSIZE (mode)
5044 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5046 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5047 extend_op = SIGN_EXTEND;
5048 m = GET_MODE (XEXP (t, 0));
5050 else if (GET_CODE (t) == ZERO_EXTEND
5051 && (GET_CODE (XEXP (t, 0)) == PLUS
5052 || GET_CODE (XEXP (t, 0)) == MINUS
5053 || GET_CODE (XEXP (t, 0)) == IOR
5054 || GET_CODE (XEXP (t, 0)) == XOR
5055 || GET_CODE (XEXP (t, 0)) == ASHIFT
5056 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5057 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5058 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5059 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5060 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5061 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5062 && ((nonzero_bits (f, GET_MODE (f))
5063 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5066 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5067 extend_op = ZERO_EXTEND;
5068 m = GET_MODE (XEXP (t, 0));
5070 else if (GET_CODE (t) == ZERO_EXTEND
5071 && (GET_CODE (XEXP (t, 0)) == PLUS
5072 || GET_CODE (XEXP (t, 0)) == IOR
5073 || GET_CODE (XEXP (t, 0)) == XOR)
5074 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5075 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5076 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5077 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5078 && ((nonzero_bits (f, GET_MODE (f))
5079 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5082 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5083 extend_op = ZERO_EXTEND;
5084 m = GET_MODE (XEXP (t, 0));
5089 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5090 cond_op0, cond_op1),
5091 pc_rtx, pc_rtx, 0, 0);
5092 temp = simplify_gen_binary (MULT, m, temp,
5093 simplify_gen_binary (MULT, m, c1,
5095 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5096 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5098 if (extend_op != UNKNOWN)
5099 temp = simplify_gen_unary (extend_op, mode, temp, m);
5105 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5106 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5107 negation of a single bit, we can convert this operation to a shift. We
5108 can actually do this more generally, but it doesn't seem worth it. */
5110 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5111 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5112 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5113 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5114 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5115 == GET_MODE_BITSIZE (mode))
5116 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5118 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5119 gen_lowpart (mode, XEXP (cond, 0)), i);
5121 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5122 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5123 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5124 && GET_MODE (XEXP (cond, 0)) == mode
5125 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5126 == nonzero_bits (XEXP (cond, 0), mode)
5127 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5128 return XEXP (cond, 0);
5133 /* Simplify X, a SET expression. Return the new expression. */
5136 simplify_set (rtx x)
5138 rtx src = SET_SRC (x);
5139 rtx dest = SET_DEST (x);
5140 enum machine_mode mode
5141 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5145 /* (set (pc) (return)) gets written as (return). */
5146 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5149 /* Now that we know for sure which bits of SRC we are using, see if we can
5150 simplify the expression for the object knowing that we only need the
5153 if (GET_MODE_CLASS (mode) == MODE_INT
5154 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5156 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5157 SUBST (SET_SRC (x), src);
5160 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5161 the comparison result and try to simplify it unless we already have used
5162 undobuf.other_insn. */
5163 if ((GET_MODE_CLASS (mode) == MODE_CC
5164 || GET_CODE (src) == COMPARE
5166 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5167 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5168 && COMPARISON_P (*cc_use)
5169 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5171 enum rtx_code old_code = GET_CODE (*cc_use);
5172 enum rtx_code new_code;
5174 int other_changed = 0;
5175 enum machine_mode compare_mode = GET_MODE (dest);
5177 if (GET_CODE (src) == COMPARE)
5178 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5180 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5182 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5185 new_code = old_code;
5186 else if (!CONSTANT_P (tmp))
5188 new_code = GET_CODE (tmp);
5189 op0 = XEXP (tmp, 0);
5190 op1 = XEXP (tmp, 1);
5194 rtx pat = PATTERN (other_insn);
5195 undobuf.other_insn = other_insn;
5196 SUBST (*cc_use, tmp);
5198 /* Attempt to simplify CC user. */
5199 if (GET_CODE (pat) == SET)
5201 rtx new = simplify_rtx (SET_SRC (pat));
5202 if (new != NULL_RTX)
5203 SUBST (SET_SRC (pat), new);
5206 /* Convert X into a no-op move. */
5207 SUBST (SET_DEST (x), pc_rtx);
5208 SUBST (SET_SRC (x), pc_rtx);
5212 /* Simplify our comparison, if possible. */
5213 new_code = simplify_comparison (new_code, &op0, &op1);
5215 #ifdef SELECT_CC_MODE
5216 /* If this machine has CC modes other than CCmode, check to see if we
5217 need to use a different CC mode here. */
5218 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5219 compare_mode = GET_MODE (op0);
5221 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5224 /* If the mode changed, we have to change SET_DEST, the mode in the
5225 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5226 a hard register, just build new versions with the proper mode. If it
5227 is a pseudo, we lose unless it is only time we set the pseudo, in
5228 which case we can safely change its mode. */
5229 if (compare_mode != GET_MODE (dest))
5231 unsigned int regno = REGNO (dest);
5232 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5234 if (regno < FIRST_PSEUDO_REGISTER
5235 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5237 if (regno >= FIRST_PSEUDO_REGISTER)
5238 SUBST (regno_reg_rtx[regno], new_dest);
5240 SUBST (SET_DEST (x), new_dest);
5241 SUBST (XEXP (*cc_use, 0), new_dest);
5248 #endif /* SELECT_CC_MODE */
5250 /* If the code changed, we have to build a new comparison in
5251 undobuf.other_insn. */
5252 if (new_code != old_code)
5254 int other_changed_previously = other_changed;
5255 unsigned HOST_WIDE_INT mask;
5257 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5261 /* If the only change we made was to change an EQ into an NE or
5262 vice versa, OP0 has only one bit that might be nonzero, and OP1
5263 is zero, check if changing the user of the condition code will
5264 produce a valid insn. If it won't, we can keep the original code
5265 in that insn by surrounding our operation with an XOR. */
5267 if (((old_code == NE && new_code == EQ)
5268 || (old_code == EQ && new_code == NE))
5269 && ! other_changed_previously && op1 == const0_rtx
5270 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5271 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5273 rtx pat = PATTERN (other_insn), note = 0;
5275 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5276 && ! check_asm_operands (pat)))
5278 PUT_CODE (*cc_use, old_code);
5281 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5282 op0, GEN_INT (mask));
5288 undobuf.other_insn = other_insn;
5291 /* If we are now comparing against zero, change our source if
5292 needed. If we do not use cc0, we always have a COMPARE. */
5293 if (op1 == const0_rtx && dest == cc0_rtx)
5295 SUBST (SET_SRC (x), op0);
5301 /* Otherwise, if we didn't previously have a COMPARE in the
5302 correct mode, we need one. */
5303 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5305 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5310 /* Otherwise, update the COMPARE if needed. */
5311 SUBST (XEXP (src, 0), op0);
5312 SUBST (XEXP (src, 1), op1);
5317 /* Get SET_SRC in a form where we have placed back any
5318 compound expressions. Then do the checks below. */
5319 src = make_compound_operation (src, SET);
5320 SUBST (SET_SRC (x), src);
5323 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5324 and X being a REG or (subreg (reg)), we may be able to convert this to
5325 (set (subreg:m2 x) (op)).
5327 We can always do this if M1 is narrower than M2 because that means that
5328 we only care about the low bits of the result.
5330 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5331 perform a narrower operation than requested since the high-order bits will
5332 be undefined. On machine where it is defined, this transformation is safe
5333 as long as M1 and M2 have the same number of words. */
5335 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5336 && !OBJECT_P (SUBREG_REG (src))
5337 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5339 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5340 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5341 #ifndef WORD_REGISTER_OPERATIONS
5342 && (GET_MODE_SIZE (GET_MODE (src))
5343 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5345 #ifdef CANNOT_CHANGE_MODE_CLASS
5346 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5347 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5348 GET_MODE (SUBREG_REG (src)),
5352 || (GET_CODE (dest) == SUBREG
5353 && REG_P (SUBREG_REG (dest)))))
5355 SUBST (SET_DEST (x),
5356 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5358 SUBST (SET_SRC (x), SUBREG_REG (src));
5360 src = SET_SRC (x), dest = SET_DEST (x);
5364 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5367 && GET_CODE (src) == SUBREG
5368 && subreg_lowpart_p (src)
5369 && (GET_MODE_BITSIZE (GET_MODE (src))
5370 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5372 rtx inner = SUBREG_REG (src);
5373 enum machine_mode inner_mode = GET_MODE (inner);
5375 /* Here we make sure that we don't have a sign bit on. */
5376 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5377 && (nonzero_bits (inner, inner_mode)
5378 < ((unsigned HOST_WIDE_INT) 1
5379 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5381 SUBST (SET_SRC (x), inner);
5387 #ifdef LOAD_EXTEND_OP
5388 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5389 would require a paradoxical subreg. Replace the subreg with a
5390 zero_extend to avoid the reload that would otherwise be required. */
5392 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5393 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5394 && SUBREG_BYTE (src) == 0
5395 && (GET_MODE_SIZE (GET_MODE (src))
5396 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5397 && MEM_P (SUBREG_REG (src)))
5400 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5401 GET_MODE (src), SUBREG_REG (src)));
5407 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5408 are comparing an item known to be 0 or -1 against 0, use a logical
5409 operation instead. Check for one of the arms being an IOR of the other
5410 arm with some value. We compute three terms to be IOR'ed together. In
5411 practice, at most two will be nonzero. Then we do the IOR's. */
5413 if (GET_CODE (dest) != PC
5414 && GET_CODE (src) == IF_THEN_ELSE
5415 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5416 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5417 && XEXP (XEXP (src, 0), 1) == const0_rtx
5418 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5419 #ifdef HAVE_conditional_move
5420 && ! can_conditionally_move_p (GET_MODE (src))
5422 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5423 GET_MODE (XEXP (XEXP (src, 0), 0)))
5424 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5425 && ! side_effects_p (src))
5427 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5428 ? XEXP (src, 1) : XEXP (src, 2));
5429 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5430 ? XEXP (src, 2) : XEXP (src, 1));
5431 rtx term1 = const0_rtx, term2, term3;
5433 if (GET_CODE (true_rtx) == IOR
5434 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5435 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5436 else if (GET_CODE (true_rtx) == IOR
5437 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5438 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5439 else if (GET_CODE (false_rtx) == IOR
5440 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5441 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5442 else if (GET_CODE (false_rtx) == IOR
5443 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5444 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5446 term2 = simplify_gen_binary (AND, GET_MODE (src),
5447 XEXP (XEXP (src, 0), 0), true_rtx);
5448 term3 = simplify_gen_binary (AND, GET_MODE (src),
5449 simplify_gen_unary (NOT, GET_MODE (src),
5450 XEXP (XEXP (src, 0), 0),
5455 simplify_gen_binary (IOR, GET_MODE (src),
5456 simplify_gen_binary (IOR, GET_MODE (src),
5463 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5464 whole thing fail. */
5465 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5467 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5470 /* Convert this into a field assignment operation, if possible. */
5471 return make_field_assignment (x);
5474 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5478 simplify_logical (rtx x)
5480 enum machine_mode mode = GET_MODE (x);
5481 rtx op0 = XEXP (x, 0);
5482 rtx op1 = XEXP (x, 1);
5485 switch (GET_CODE (x))
5488 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5489 insn (and may simplify more). */
5490 if (GET_CODE (op0) == XOR
5491 && rtx_equal_p (XEXP (op0, 0), op1)
5492 && ! side_effects_p (op1))
5493 x = simplify_gen_binary (AND, mode,
5494 simplify_gen_unary (NOT, mode,
5495 XEXP (op0, 1), mode),
5498 if (GET_CODE (op0) == XOR
5499 && rtx_equal_p (XEXP (op0, 1), op1)
5500 && ! side_effects_p (op1))
5501 x = simplify_gen_binary (AND, mode,
5502 simplify_gen_unary (NOT, mode,
5503 XEXP (op0, 0), mode),
5506 /* Similarly for (~(A ^ B)) & A. */
5507 if (GET_CODE (op0) == NOT
5508 && GET_CODE (XEXP (op0, 0)) == XOR
5509 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5510 && ! side_effects_p (op1))
5511 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5513 if (GET_CODE (op0) == NOT
5514 && GET_CODE (XEXP (op0, 0)) == XOR
5515 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5516 && ! side_effects_p (op1))
5517 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5519 /* We can call simplify_and_const_int only if we don't lose
5520 any (sign) bits when converting INTVAL (op1) to
5521 "unsigned HOST_WIDE_INT". */
5522 if (GET_CODE (op1) == CONST_INT
5523 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5524 || INTVAL (op1) > 0))
5526 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5528 /* If we have (ior (and (X C1) C2)) and the next restart would be
5529 the last, simplify this by making C1 as small as possible
5530 and then exit. Only do this if C1 actually changes: for now
5531 this only saves memory but, should this transformation be
5532 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5533 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5534 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5535 && GET_CODE (op1) == CONST_INT
5536 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5537 return simplify_gen_binary (IOR, mode,
5539 (AND, mode, XEXP (op0, 0),
5540 GEN_INT (INTVAL (XEXP (op0, 1))
5541 & ~INTVAL (op1))), op1);
5543 if (GET_CODE (x) != AND)
5550 /* Convert (A | B) & A to A. */
5551 if (GET_CODE (op0) == IOR
5552 && (rtx_equal_p (XEXP (op0, 0), op1)
5553 || rtx_equal_p (XEXP (op0, 1), op1))
5554 && ! side_effects_p (XEXP (op0, 0))
5555 && ! side_effects_p (XEXP (op0, 1)))
5558 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5559 apply the distributive law and then the inverse distributive
5560 law to see if things simplify. */
5561 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5563 rtx result = distribute_and_simplify_rtx (x, 0);
5567 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5569 rtx result = distribute_and_simplify_rtx (x, 1);
5576 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5577 if (GET_CODE (op1) == CONST_INT
5578 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5579 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5582 /* Convert (A & B) | A to A. */
5583 if (GET_CODE (op0) == AND
5584 && (rtx_equal_p (XEXP (op0, 0), op1)
5585 || rtx_equal_p (XEXP (op0, 1), op1))
5586 && ! side_effects_p (XEXP (op0, 0))
5587 && ! side_effects_p (XEXP (op0, 1)))
5590 /* If we have (ior (and A B) C), apply the distributive law and then
5591 the inverse distributive law to see if things simplify. */
5593 if (GET_CODE (op0) == AND)
5595 rtx result = distribute_and_simplify_rtx (x, 0);
5600 if (GET_CODE (op1) == AND)
5602 rtx result = distribute_and_simplify_rtx (x, 1);
5607 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5608 mode size to (rotate A CX). */
5610 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5611 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5612 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5613 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5614 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5615 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5616 == GET_MODE_BITSIZE (mode)))
5617 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5618 (GET_CODE (op0) == ASHIFT
5619 ? XEXP (op0, 1) : XEXP (op1, 1)));
5621 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5622 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5623 does not affect any of the bits in OP1, it can really be done
5624 as a PLUS and we can associate. We do this by seeing if OP1
5625 can be safely shifted left C bits. */
5626 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5627 && GET_CODE (XEXP (op0, 0)) == PLUS
5628 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5629 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5630 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5632 int count = INTVAL (XEXP (op0, 1));
5633 HOST_WIDE_INT mask = INTVAL (op1) << count;
5635 if (mask >> count == INTVAL (op1)
5636 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5638 SUBST (XEXP (XEXP (op0, 0), 1),
5639 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5646 /* If we are XORing two things that have no bits in common,
5647 convert them into an IOR. This helps to detect rotation encoded
5648 using those methods and possibly other simplifications. */
5650 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5651 && (nonzero_bits (op0, mode)
5652 & nonzero_bits (op1, mode)) == 0)
5653 return (simplify_gen_binary (IOR, mode, op0, op1));
5655 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5656 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5659 int num_negated = 0;
5661 if (GET_CODE (op0) == NOT)
5662 num_negated++, op0 = XEXP (op0, 0);
5663 if (GET_CODE (op1) == NOT)
5664 num_negated++, op1 = XEXP (op1, 0);
5666 if (num_negated == 2)
5668 SUBST (XEXP (x, 0), op0);
5669 SUBST (XEXP (x, 1), op1);
5671 else if (num_negated == 1)
5673 simplify_gen_unary (NOT, mode,
5674 simplify_gen_binary (XOR, mode, op0, op1),
5678 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5679 correspond to a machine insn or result in further simplifications
5680 if B is a constant. */
5682 if (GET_CODE (op0) == AND
5683 && rtx_equal_p (XEXP (op0, 1), op1)
5684 && ! side_effects_p (op1))
5685 return simplify_gen_binary (AND, mode,
5686 simplify_gen_unary (NOT, mode,
5687 XEXP (op0, 0), mode),
5690 else if (GET_CODE (op0) == AND
5691 && rtx_equal_p (XEXP (op0, 0), op1)
5692 && ! side_effects_p (op1))
5693 return simplify_gen_binary (AND, mode,
5694 simplify_gen_unary (NOT, mode,
5695 XEXP (op0, 1), mode),
5698 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5699 comparison if STORE_FLAG_VALUE is 1. */
5700 if (STORE_FLAG_VALUE == 1
5701 && op1 == const1_rtx
5702 && COMPARISON_P (op0)
5703 && (reversed = reversed_comparison (op0, mode)))
5706 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5707 is (lt foo (const_int 0)), so we can perform the above
5708 simplification if STORE_FLAG_VALUE is 1. */
5710 if (STORE_FLAG_VALUE == 1
5711 && op1 == const1_rtx
5712 && GET_CODE (op0) == LSHIFTRT
5713 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5714 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5715 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5717 /* (xor (comparison foo bar) (const_int sign-bit))
5718 when STORE_FLAG_VALUE is the sign bit. */
5719 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5720 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5721 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5722 && op1 == const_true_rtx
5723 && COMPARISON_P (op0)
5724 && (reversed = reversed_comparison (op0, mode)))
5736 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5737 operations" because they can be replaced with two more basic operations.
5738 ZERO_EXTEND is also considered "compound" because it can be replaced with
5739 an AND operation, which is simpler, though only one operation.
5741 The function expand_compound_operation is called with an rtx expression
5742 and will convert it to the appropriate shifts and AND operations,
5743 simplifying at each stage.
5745 The function make_compound_operation is called to convert an expression
5746 consisting of shifts and ANDs into the equivalent compound expression.
5747 It is the inverse of this function, loosely speaking. */
5750 expand_compound_operation (rtx x)
5752 unsigned HOST_WIDE_INT pos = 0, len;
5754 unsigned int modewidth;
5757 switch (GET_CODE (x))
5762 /* We can't necessarily use a const_int for a multiword mode;
5763 it depends on implicitly extending the value.
5764 Since we don't know the right way to extend it,
5765 we can't tell whether the implicit way is right.
5767 Even for a mode that is no wider than a const_int,
5768 we can't win, because we need to sign extend one of its bits through
5769 the rest of it, and we don't know which bit. */
5770 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5773 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5774 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5775 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5776 reloaded. If not for that, MEM's would very rarely be safe.
5778 Reject MODEs bigger than a word, because we might not be able
5779 to reference a two-register group starting with an arbitrary register
5780 (and currently gen_lowpart might crash for a SUBREG). */
5782 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5785 /* Reject MODEs that aren't scalar integers because turning vector
5786 or complex modes into shifts causes problems. */
5788 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5791 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5792 /* If the inner object has VOIDmode (the only way this can happen
5793 is if it is an ASM_OPERANDS), we can't do anything since we don't
5794 know how much masking to do. */
5803 /* ... fall through ... */
5806 /* If the operand is a CLOBBER, just return it. */
5807 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5810 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5811 || GET_CODE (XEXP (x, 2)) != CONST_INT
5812 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5815 /* Reject MODEs that aren't scalar integers because turning vector
5816 or complex modes into shifts causes problems. */
5818 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5821 len = INTVAL (XEXP (x, 1));
5822 pos = INTVAL (XEXP (x, 2));
5824 /* If this goes outside the object being extracted, replace the object
5825 with a (use (mem ...)) construct that only combine understands
5826 and is used only for this purpose. */
5827 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5828 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5830 if (BITS_BIG_ENDIAN)
5831 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5838 /* Convert sign extension to zero extension, if we know that the high
5839 bit is not set, as this is easier to optimize. It will be converted
5840 back to cheaper alternative in make_extraction. */
5841 if (GET_CODE (x) == SIGN_EXTEND
5842 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5843 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5844 & ~(((unsigned HOST_WIDE_INT)
5845 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5849 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5850 rtx temp2 = expand_compound_operation (temp);
5852 /* Make sure this is a profitable operation. */
5853 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5855 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5861 /* We can optimize some special cases of ZERO_EXTEND. */
5862 if (GET_CODE (x) == ZERO_EXTEND)
5864 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5865 know that the last value didn't have any inappropriate bits
5867 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5868 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5869 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5870 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5871 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5872 return XEXP (XEXP (x, 0), 0);
5874 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5875 if (GET_CODE (XEXP (x, 0)) == SUBREG
5876 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5877 && subreg_lowpart_p (XEXP (x, 0))
5878 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5879 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5880 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5881 return SUBREG_REG (XEXP (x, 0));
5883 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5884 is a comparison and STORE_FLAG_VALUE permits. This is like
5885 the first case, but it works even when GET_MODE (x) is larger
5886 than HOST_WIDE_INT. */
5887 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5888 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5889 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5890 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5891 <= HOST_BITS_PER_WIDE_INT)
5892 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5893 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5894 return XEXP (XEXP (x, 0), 0);
5896 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5897 if (GET_CODE (XEXP (x, 0)) == SUBREG
5898 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5899 && subreg_lowpart_p (XEXP (x, 0))
5900 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5901 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5902 <= HOST_BITS_PER_WIDE_INT)
5903 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5904 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5905 return SUBREG_REG (XEXP (x, 0));
5909 /* If we reach here, we want to return a pair of shifts. The inner
5910 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5911 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5912 logical depending on the value of UNSIGNEDP.
5914 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5915 converted into an AND of a shift.
5917 We must check for the case where the left shift would have a negative
5918 count. This can happen in a case like (x >> 31) & 255 on machines
5919 that can't shift by a constant. On those machines, we would first
5920 combine the shift with the AND to produce a variable-position
5921 extraction. Then the constant of 31 would be substituted in to produce
5922 a such a position. */
5924 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5925 if (modewidth + len >= pos)
5926 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5928 simplify_shift_const (NULL_RTX, ASHIFT,
5931 modewidth - pos - len),
5934 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5935 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5936 simplify_shift_const (NULL_RTX, LSHIFTRT,
5939 ((HOST_WIDE_INT) 1 << len) - 1);
5941 /* Any other cases we can't handle. */
5944 /* If we couldn't do this for some reason, return the original
5946 if (GET_CODE (tem) == CLOBBER)
5952 /* X is a SET which contains an assignment of one object into
5953 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5954 or certain SUBREGS). If possible, convert it into a series of
5957 We half-heartedly support variable positions, but do not at all
5958 support variable lengths. */
5961 expand_field_assignment (rtx x)
5964 rtx pos; /* Always counts from low bit. */
5966 rtx mask, cleared, masked;
5967 enum machine_mode compute_mode;
5969 /* Loop until we find something we can't simplify. */
5972 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5973 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5975 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5976 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5977 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5979 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5980 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5982 inner = XEXP (SET_DEST (x), 0);
5983 len = INTVAL (XEXP (SET_DEST (x), 1));
5984 pos = XEXP (SET_DEST (x), 2);
5986 /* If the position is constant and spans the width of INNER,
5987 surround INNER with a USE to indicate this. */
5988 if (GET_CODE (pos) == CONST_INT
5989 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5990 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5992 if (BITS_BIG_ENDIAN)
5994 if (GET_CODE (pos) == CONST_INT)
5995 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5997 else if (GET_CODE (pos) == MINUS
5998 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5999 && (INTVAL (XEXP (pos, 1))
6000 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6001 /* If position is ADJUST - X, new position is X. */
6002 pos = XEXP (pos, 0);
6004 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6005 GEN_INT (GET_MODE_BITSIZE (
6012 /* A SUBREG between two modes that occupy the same numbers of words
6013 can be done by moving the SUBREG to the source. */
6014 else if (GET_CODE (SET_DEST (x)) == SUBREG
6015 /* We need SUBREGs to compute nonzero_bits properly. */
6016 && nonzero_sign_valid
6017 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6018 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6019 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6020 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6022 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6024 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6031 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6032 inner = SUBREG_REG (inner);
6034 compute_mode = GET_MODE (inner);
6036 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6037 if (! SCALAR_INT_MODE_P (compute_mode))
6039 enum machine_mode imode;
6041 /* Don't do anything for vector or complex integral types. */
6042 if (! FLOAT_MODE_P (compute_mode))
6045 /* Try to find an integral mode to pun with. */
6046 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6047 if (imode == BLKmode)
6050 compute_mode = imode;
6051 inner = gen_lowpart (imode, inner);
6054 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6055 if (len >= HOST_BITS_PER_WIDE_INT)
6058 /* Now compute the equivalent expression. Make a copy of INNER
6059 for the SET_DEST in case it is a MEM into which we will substitute;
6060 we don't want shared RTL in that case. */
6061 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6062 cleared = simplify_gen_binary (AND, compute_mode,
6063 simplify_gen_unary (NOT, compute_mode,
6064 simplify_gen_binary (ASHIFT,
6069 masked = simplify_gen_binary (ASHIFT, compute_mode,
6070 simplify_gen_binary (
6072 gen_lowpart (compute_mode, SET_SRC (x)),
6076 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6077 simplify_gen_binary (IOR, compute_mode,
6084 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6085 it is an RTX that represents a variable starting position; otherwise,
6086 POS is the (constant) starting bit position (counted from the LSB).
6088 INNER may be a USE. This will occur when we started with a bitfield
6089 that went outside the boundary of the object in memory, which is
6090 allowed on most machines. To isolate this case, we produce a USE
6091 whose mode is wide enough and surround the MEM with it. The only
6092 code that understands the USE is this routine. If it is not removed,
6093 it will cause the resulting insn not to match.
6095 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6098 IN_DEST is nonzero if this is a reference in the destination of a
6099 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6100 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6103 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6104 ZERO_EXTRACT should be built even for bits starting at bit 0.
6106 MODE is the desired mode of the result (if IN_DEST == 0).
6108 The result is an RTX for the extraction or NULL_RTX if the target
6112 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6113 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6114 int in_dest, int in_compare)
6116 /* This mode describes the size of the storage area
6117 to fetch the overall value from. Within that, we
6118 ignore the POS lowest bits, etc. */
6119 enum machine_mode is_mode = GET_MODE (inner);
6120 enum machine_mode inner_mode;
6121 enum machine_mode wanted_inner_mode = byte_mode;
6122 enum machine_mode wanted_inner_reg_mode = word_mode;
6123 enum machine_mode pos_mode = word_mode;
6124 enum machine_mode extraction_mode = word_mode;
6125 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6128 rtx orig_pos_rtx = pos_rtx;
6129 HOST_WIDE_INT orig_pos;
6131 /* Get some information about INNER and get the innermost object. */
6132 if (GET_CODE (inner) == USE)
6133 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6134 /* We don't need to adjust the position because we set up the USE
6135 to pretend that it was a full-word object. */
6136 spans_byte = 1, inner = XEXP (inner, 0);
6137 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6139 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6140 consider just the QI as the memory to extract from.
6141 The subreg adds or removes high bits; its mode is
6142 irrelevant to the meaning of this extraction,
6143 since POS and LEN count from the lsb. */
6144 if (MEM_P (SUBREG_REG (inner)))
6145 is_mode = GET_MODE (SUBREG_REG (inner));
6146 inner = SUBREG_REG (inner);
6148 else if (GET_CODE (inner) == ASHIFT
6149 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6150 && pos_rtx == 0 && pos == 0
6151 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6153 /* We're extracting the least significant bits of an rtx
6154 (ashift X (const_int C)), where LEN > C. Extract the
6155 least significant (LEN - C) bits of X, giving an rtx
6156 whose mode is MODE, then shift it left C times. */
6157 new = make_extraction (mode, XEXP (inner, 0),
6158 0, 0, len - INTVAL (XEXP (inner, 1)),
6159 unsignedp, in_dest, in_compare);
6161 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6164 inner_mode = GET_MODE (inner);
6166 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6167 pos = INTVAL (pos_rtx), pos_rtx = 0;
6169 /* See if this can be done without an extraction. We never can if the
6170 width of the field is not the same as that of some integer mode. For
6171 registers, we can only avoid the extraction if the position is at the
6172 low-order bit and this is either not in the destination or we have the
6173 appropriate STRICT_LOW_PART operation available.
6175 For MEM, we can avoid an extract if the field starts on an appropriate
6176 boundary and we can change the mode of the memory reference. However,
6177 we cannot directly access the MEM if we have a USE and the underlying
6178 MEM is not TMODE. This combination means that MEM was being used in a
6179 context where bits outside its mode were being referenced; that is only
6180 valid in bit-field insns. */
6182 if (tmode != BLKmode
6183 && ! (spans_byte && inner_mode != tmode)
6184 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6188 && have_insn_for (STRICT_LOW_PART, tmode))))
6189 || (MEM_P (inner) && pos_rtx == 0
6191 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6192 : BITS_PER_UNIT)) == 0
6193 /* We can't do this if we are widening INNER_MODE (it
6194 may not be aligned, for one thing). */
6195 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6196 && (inner_mode == tmode
6197 || (! mode_dependent_address_p (XEXP (inner, 0))
6198 && ! MEM_VOLATILE_P (inner))))))
6200 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6201 field. If the original and current mode are the same, we need not
6202 adjust the offset. Otherwise, we do if bytes big endian.
6204 If INNER is not a MEM, get a piece consisting of just the field
6205 of interest (in this case POS % BITS_PER_WORD must be 0). */
6209 HOST_WIDE_INT offset;
6211 /* POS counts from lsb, but make OFFSET count in memory order. */
6212 if (BYTES_BIG_ENDIAN)
6213 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6215 offset = pos / BITS_PER_UNIT;
6217 new = adjust_address_nv (inner, tmode, offset);
6219 else if (REG_P (inner))
6221 if (tmode != inner_mode)
6223 /* We can't call gen_lowpart in a DEST since we
6224 always want a SUBREG (see below) and it would sometimes
6225 return a new hard register. */
6228 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6230 if (WORDS_BIG_ENDIAN
6231 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6232 final_word = ((GET_MODE_SIZE (inner_mode)
6233 - GET_MODE_SIZE (tmode))
6234 / UNITS_PER_WORD) - final_word;
6236 final_word *= UNITS_PER_WORD;
6237 if (BYTES_BIG_ENDIAN &&
6238 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6239 final_word += (GET_MODE_SIZE (inner_mode)
6240 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6242 /* Avoid creating invalid subregs, for example when
6243 simplifying (x>>32)&255. */
6244 if (final_word >= GET_MODE_SIZE (inner_mode))
6247 new = gen_rtx_SUBREG (tmode, inner, final_word);
6250 new = gen_lowpart (tmode, inner);
6256 new = force_to_mode (inner, tmode,
6257 len >= HOST_BITS_PER_WIDE_INT
6258 ? ~(unsigned HOST_WIDE_INT) 0
6259 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6262 /* If this extraction is going into the destination of a SET,
6263 make a STRICT_LOW_PART unless we made a MEM. */
6266 return (MEM_P (new) ? new
6267 : (GET_CODE (new) != SUBREG
6268 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6269 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6274 if (GET_CODE (new) == CONST_INT)
6275 return gen_int_mode (INTVAL (new), mode);
6277 /* If we know that no extraneous bits are set, and that the high
6278 bit is not set, convert the extraction to the cheaper of
6279 sign and zero extension, that are equivalent in these cases. */
6280 if (flag_expensive_optimizations
6281 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6282 && ((nonzero_bits (new, tmode)
6283 & ~(((unsigned HOST_WIDE_INT)
6284 GET_MODE_MASK (tmode))
6288 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6289 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6291 /* Prefer ZERO_EXTENSION, since it gives more information to
6293 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6298 /* Otherwise, sign- or zero-extend unless we already are in the
6301 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6305 /* Unless this is a COMPARE or we have a funny memory reference,
6306 don't do anything with zero-extending field extracts starting at
6307 the low-order bit since they are simple AND operations. */
6308 if (pos_rtx == 0 && pos == 0 && ! in_dest
6309 && ! in_compare && ! spans_byte && unsignedp)
6312 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6313 we would be spanning bytes or if the position is not a constant and the
6314 length is not 1. In all other cases, we would only be going outside
6315 our object in cases when an original shift would have been
6317 if (! spans_byte && MEM_P (inner)
6318 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6319 || (pos_rtx != 0 && len != 1)))
6322 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6323 and the mode for the result. */
6324 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6326 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6327 pos_mode = mode_for_extraction (EP_insv, 2);
6328 extraction_mode = mode_for_extraction (EP_insv, 3);
6331 if (! in_dest && unsignedp
6332 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6334 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6335 pos_mode = mode_for_extraction (EP_extzv, 3);
6336 extraction_mode = mode_for_extraction (EP_extzv, 0);
6339 if (! in_dest && ! unsignedp
6340 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6342 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6343 pos_mode = mode_for_extraction (EP_extv, 3);
6344 extraction_mode = mode_for_extraction (EP_extv, 0);
6347 /* Never narrow an object, since that might not be safe. */
6349 if (mode != VOIDmode
6350 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6351 extraction_mode = mode;
6353 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6354 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6355 pos_mode = GET_MODE (pos_rtx);
6357 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6358 if we have to change the mode of memory and cannot, the desired mode is
6361 wanted_inner_mode = wanted_inner_reg_mode;
6362 else if (inner_mode != wanted_inner_mode
6363 && (mode_dependent_address_p (XEXP (inner, 0))
6364 || MEM_VOLATILE_P (inner)))
6365 wanted_inner_mode = extraction_mode;
6369 if (BITS_BIG_ENDIAN)
6371 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6372 BITS_BIG_ENDIAN style. If position is constant, compute new
6373 position. Otherwise, build subtraction.
6374 Note that POS is relative to the mode of the original argument.
6375 If it's a MEM we need to recompute POS relative to that.
6376 However, if we're extracting from (or inserting into) a register,
6377 we want to recompute POS relative to wanted_inner_mode. */
6378 int width = (MEM_P (inner)
6379 ? GET_MODE_BITSIZE (is_mode)
6380 : GET_MODE_BITSIZE (wanted_inner_mode));
6383 pos = width - len - pos;
6386 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6387 /* POS may be less than 0 now, but we check for that below.
6388 Note that it can only be less than 0 if !MEM_P (inner). */
6391 /* If INNER has a wider mode, make it smaller. If this is a constant
6392 extract, try to adjust the byte to point to the byte containing
6394 if (wanted_inner_mode != VOIDmode
6395 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6397 && (inner_mode == wanted_inner_mode
6398 || (! mode_dependent_address_p (XEXP (inner, 0))
6399 && ! MEM_VOLATILE_P (inner))))))
6403 /* The computations below will be correct if the machine is big
6404 endian in both bits and bytes or little endian in bits and bytes.
6405 If it is mixed, we must adjust. */
6407 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6408 adjust OFFSET to compensate. */
6409 if (BYTES_BIG_ENDIAN
6411 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6412 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6414 /* If this is a constant position, we can move to the desired byte. */
6417 offset += pos / BITS_PER_UNIT;
6418 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6421 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6423 && is_mode != wanted_inner_mode)
6424 offset = (GET_MODE_SIZE (is_mode)
6425 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6427 if (offset != 0 || inner_mode != wanted_inner_mode)
6428 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6431 /* If INNER is not memory, we can always get it into the proper mode. If we
6432 are changing its mode, POS must be a constant and smaller than the size
6434 else if (!MEM_P (inner))
6436 if (GET_MODE (inner) != wanted_inner_mode
6438 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6441 inner = force_to_mode (inner, wanted_inner_mode,
6443 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6444 ? ~(unsigned HOST_WIDE_INT) 0
6445 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6450 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6451 have to zero extend. Otherwise, we can just use a SUBREG. */
6453 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6455 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6457 /* If we know that no extraneous bits are set, and that the high
6458 bit is not set, convert extraction to cheaper one - either
6459 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6461 if (flag_expensive_optimizations
6462 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6463 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6464 & ~(((unsigned HOST_WIDE_INT)
6465 GET_MODE_MASK (GET_MODE (pos_rtx)))
6469 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6471 /* Prefer ZERO_EXTENSION, since it gives more information to
6473 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6478 else if (pos_rtx != 0
6479 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6480 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6482 /* Make POS_RTX unless we already have it and it is correct. If we don't
6483 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6485 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6486 pos_rtx = orig_pos_rtx;
6488 else if (pos_rtx == 0)
6489 pos_rtx = GEN_INT (pos);
6491 /* Make the required operation. See if we can use existing rtx. */
6492 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6493 extraction_mode, inner, GEN_INT (len), pos_rtx);
6495 new = gen_lowpart (mode, new);
6500 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6501 with any other operations in X. Return X without that shift if so. */
6504 extract_left_shift (rtx x, int count)
6506 enum rtx_code code = GET_CODE (x);
6507 enum machine_mode mode = GET_MODE (x);
6513 /* This is the shift itself. If it is wide enough, we will return
6514 either the value being shifted if the shift count is equal to
6515 COUNT or a shift for the difference. */
6516 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6517 && INTVAL (XEXP (x, 1)) >= count)
6518 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6519 INTVAL (XEXP (x, 1)) - count);
6523 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6524 return simplify_gen_unary (code, mode, tem, mode);
6528 case PLUS: case IOR: case XOR: case AND:
6529 /* If we can safely shift this constant and we find the inner shift,
6530 make a new operation. */
6531 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6532 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6533 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6534 return simplify_gen_binary (code, mode, tem,
6535 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6546 /* Look at the expression rooted at X. Look for expressions
6547 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6548 Form these expressions.
6550 Return the new rtx, usually just X.
6552 Also, for machines like the VAX that don't have logical shift insns,
6553 try to convert logical to arithmetic shift operations in cases where
6554 they are equivalent. This undoes the canonicalizations to logical
6555 shifts done elsewhere.
6557 We try, as much as possible, to re-use rtl expressions to save memory.
6559 IN_CODE says what kind of expression we are processing. Normally, it is
6560 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6561 being kludges), it is MEM. When processing the arguments of a comparison
6562 or a COMPARE against zero, it is COMPARE. */
6565 make_compound_operation (rtx x, enum rtx_code in_code)
6567 enum rtx_code code = GET_CODE (x);
6568 enum machine_mode mode = GET_MODE (x);
6569 int mode_width = GET_MODE_BITSIZE (mode);
6571 enum rtx_code next_code;
6577 /* Select the code to be used in recursive calls. Once we are inside an
6578 address, we stay there. If we have a comparison, set to COMPARE,
6579 but once inside, go back to our default of SET. */
6581 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6582 : ((code == COMPARE || COMPARISON_P (x))
6583 && XEXP (x, 1) == const0_rtx) ? COMPARE
6584 : in_code == COMPARE ? SET : in_code);
6586 /* Process depending on the code of this operation. If NEW is set
6587 nonzero, it will be returned. */
6592 /* Convert shifts by constants into multiplications if inside
6594 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6595 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6596 && INTVAL (XEXP (x, 1)) >= 0)
6598 new = make_compound_operation (XEXP (x, 0), next_code);
6599 new = gen_rtx_MULT (mode, new,
6600 GEN_INT ((HOST_WIDE_INT) 1
6601 << INTVAL (XEXP (x, 1))));
6606 /* If the second operand is not a constant, we can't do anything
6608 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6611 /* If the constant is a power of two minus one and the first operand
6612 is a logical right shift, make an extraction. */
6613 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6614 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6616 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6617 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6618 0, in_code == COMPARE);
6621 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6622 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6623 && subreg_lowpart_p (XEXP (x, 0))
6624 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6625 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6627 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6629 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6630 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6631 0, in_code == COMPARE);
6633 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6634 else if ((GET_CODE (XEXP (x, 0)) == XOR
6635 || GET_CODE (XEXP (x, 0)) == IOR)
6636 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6637 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6638 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6640 /* Apply the distributive law, and then try to make extractions. */
6641 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6642 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6644 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6646 new = make_compound_operation (new, in_code);
6649 /* If we are have (and (rotate X C) M) and C is larger than the number
6650 of bits in M, this is an extraction. */
6652 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6653 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6654 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6655 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6657 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6658 new = make_extraction (mode, new,
6659 (GET_MODE_BITSIZE (mode)
6660 - INTVAL (XEXP (XEXP (x, 0), 1))),
6661 NULL_RTX, i, 1, 0, in_code == COMPARE);
6664 /* On machines without logical shifts, if the operand of the AND is
6665 a logical shift and our mask turns off all the propagated sign
6666 bits, we can replace the logical shift with an arithmetic shift. */
6667 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6668 && !have_insn_for (LSHIFTRT, mode)
6669 && have_insn_for (ASHIFTRT, mode)
6670 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6671 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6672 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6673 && mode_width <= HOST_BITS_PER_WIDE_INT)
6675 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6677 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6678 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6680 gen_rtx_ASHIFTRT (mode,
6681 make_compound_operation
6682 (XEXP (XEXP (x, 0), 0), next_code),
6683 XEXP (XEXP (x, 0), 1)));
6686 /* If the constant is one less than a power of two, this might be
6687 representable by an extraction even if no shift is present.
6688 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6689 we are in a COMPARE. */
6690 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6691 new = make_extraction (mode,
6692 make_compound_operation (XEXP (x, 0),
6694 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6696 /* If we are in a comparison and this is an AND with a power of two,
6697 convert this into the appropriate bit extract. */
6698 else if (in_code == COMPARE
6699 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6700 new = make_extraction (mode,
6701 make_compound_operation (XEXP (x, 0),
6703 i, NULL_RTX, 1, 1, 0, 1);
6708 /* If the sign bit is known to be zero, replace this with an
6709 arithmetic shift. */
6710 if (have_insn_for (ASHIFTRT, mode)
6711 && ! have_insn_for (LSHIFTRT, mode)
6712 && mode_width <= HOST_BITS_PER_WIDE_INT
6713 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6715 new = gen_rtx_ASHIFTRT (mode,
6716 make_compound_operation (XEXP (x, 0),
6722 /* ... fall through ... */
6728 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6729 this is a SIGN_EXTRACT. */
6730 if (GET_CODE (rhs) == CONST_INT
6731 && GET_CODE (lhs) == ASHIFT
6732 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6733 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6735 new = make_compound_operation (XEXP (lhs, 0), next_code);
6736 new = make_extraction (mode, new,
6737 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6738 NULL_RTX, mode_width - INTVAL (rhs),
6739 code == LSHIFTRT, 0, in_code == COMPARE);
6743 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6744 If so, try to merge the shifts into a SIGN_EXTEND. We could
6745 also do this for some cases of SIGN_EXTRACT, but it doesn't
6746 seem worth the effort; the case checked for occurs on Alpha. */
6749 && ! (GET_CODE (lhs) == SUBREG
6750 && (OBJECT_P (SUBREG_REG (lhs))))
6751 && GET_CODE (rhs) == CONST_INT
6752 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6753 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6754 new = make_extraction (mode, make_compound_operation (new, next_code),
6755 0, NULL_RTX, mode_width - INTVAL (rhs),
6756 code == LSHIFTRT, 0, in_code == COMPARE);
6761 /* Call ourselves recursively on the inner expression. If we are
6762 narrowing the object and it has a different RTL code from
6763 what it originally did, do this SUBREG as a force_to_mode. */
6765 tem = make_compound_operation (SUBREG_REG (x), in_code);
6766 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6767 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6768 && subreg_lowpart_p (x))
6770 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6773 /* If we have something other than a SUBREG, we might have
6774 done an expansion, so rerun ourselves. */
6775 if (GET_CODE (newer) != SUBREG)
6776 newer = make_compound_operation (newer, in_code);
6781 /* If this is a paradoxical subreg, and the new code is a sign or
6782 zero extension, omit the subreg and widen the extension. If it
6783 is a regular subreg, we can still get rid of the subreg by not
6784 widening so much, or in fact removing the extension entirely. */
6785 if ((GET_CODE (tem) == SIGN_EXTEND
6786 || GET_CODE (tem) == ZERO_EXTEND)
6787 && subreg_lowpart_p (x))
6789 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6790 || (GET_MODE_SIZE (mode) >
6791 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6793 if (! SCALAR_INT_MODE_P (mode))
6795 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6798 tem = gen_lowpart (mode, XEXP (tem, 0));
6809 x = gen_lowpart (mode, new);
6810 code = GET_CODE (x);
6813 /* Now recursively process each operand of this operation. */
6814 fmt = GET_RTX_FORMAT (code);
6815 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6818 new = make_compound_operation (XEXP (x, i), next_code);
6819 SUBST (XEXP (x, i), new);
6825 /* Given M see if it is a value that would select a field of bits
6826 within an item, but not the entire word. Return -1 if not.
6827 Otherwise, return the starting position of the field, where 0 is the
6830 *PLEN is set to the length of the field. */
6833 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6835 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6836 int pos = exact_log2 (m & -m);
6840 /* Now shift off the low-order zero bits and see if we have a
6841 power of two minus 1. */
6842 len = exact_log2 ((m >> pos) + 1);
6851 /* See if X can be simplified knowing that we will only refer to it in
6852 MODE and will only refer to those bits that are nonzero in MASK.
6853 If other bits are being computed or if masking operations are done
6854 that select a superset of the bits in MASK, they can sometimes be
6857 Return a possibly simplified expression, but always convert X to
6858 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6860 Also, if REG is nonzero and X is a register equal in value to REG,
6863 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6864 are all off in X. This is used when X will be complemented, by either
6865 NOT, NEG, or XOR. */
6868 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6869 rtx reg, int just_select)
6871 enum rtx_code code = GET_CODE (x);
6872 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6873 enum machine_mode op_mode;
6874 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6877 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6878 code below will do the wrong thing since the mode of such an
6879 expression is VOIDmode.
6881 Also do nothing if X is a CLOBBER; this can happen if X was
6882 the return value from a call to gen_lowpart. */
6883 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6886 /* We want to perform the operation is its present mode unless we know
6887 that the operation is valid in MODE, in which case we do the operation
6889 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6890 && have_insn_for (code, mode))
6891 ? mode : GET_MODE (x));
6893 /* It is not valid to do a right-shift in a narrower mode
6894 than the one it came in with. */
6895 if ((code == LSHIFTRT || code == ASHIFTRT)
6896 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6897 op_mode = GET_MODE (x);
6899 /* Truncate MASK to fit OP_MODE. */
6901 mask &= GET_MODE_MASK (op_mode);
6903 /* When we have an arithmetic operation, or a shift whose count we
6904 do not know, we need to assume that all bits up to the highest-order
6905 bit in MASK will be needed. This is how we form such a mask. */
6906 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6907 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6909 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6912 /* Determine what bits of X are guaranteed to be (non)zero. */
6913 nonzero = nonzero_bits (x, mode);
6915 /* If none of the bits in X are needed, return a zero. */
6916 if (! just_select && (nonzero & mask) == 0)
6919 /* If X is a CONST_INT, return a new one. Do this here since the
6920 test below will fail. */
6921 if (GET_CODE (x) == CONST_INT)
6923 if (SCALAR_INT_MODE_P (mode))
6924 return gen_int_mode (INTVAL (x) & mask, mode);
6927 x = GEN_INT (INTVAL (x) & mask);
6928 return gen_lowpart_common (mode, x);
6932 /* If X is narrower than MODE and we want all the bits in X's mode, just
6933 get X in the proper mode. */
6934 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6935 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6936 return gen_lowpart (mode, x);
6941 /* If X is a (clobber (const_int)), return it since we know we are
6942 generating something that won't match. */
6946 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6947 spanned the boundary of the MEM. If we are now masking so it is
6948 within that boundary, we don't need the USE any more. */
6949 if (! BITS_BIG_ENDIAN
6950 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6951 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6958 x = expand_compound_operation (x);
6959 if (GET_CODE (x) != code)
6960 return force_to_mode (x, mode, mask, reg, next_select);
6964 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6965 || rtx_equal_p (reg, get_last_value (x))))
6970 if (subreg_lowpart_p (x)
6971 /* We can ignore the effect of this SUBREG if it narrows the mode or
6972 if the constant masks to zero all the bits the mode doesn't
6974 && ((GET_MODE_SIZE (GET_MODE (x))
6975 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6977 & GET_MODE_MASK (GET_MODE (x))
6978 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6979 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6983 /* If this is an AND with a constant, convert it into an AND
6984 whose constant is the AND of that constant with MASK. If it
6985 remains an AND of MASK, delete it since it is redundant. */
6987 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6989 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6990 mask & INTVAL (XEXP (x, 1)));
6992 /* If X is still an AND, see if it is an AND with a mask that
6993 is just some low-order bits. If so, and it is MASK, we don't
6996 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6997 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7001 /* If it remains an AND, try making another AND with the bits
7002 in the mode mask that aren't in MASK turned on. If the
7003 constant in the AND is wide enough, this might make a
7004 cheaper constant. */
7006 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7007 && GET_MODE_MASK (GET_MODE (x)) != mask
7008 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7010 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7011 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7012 int width = GET_MODE_BITSIZE (GET_MODE (x));
7015 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7016 number, sign extend it. */
7017 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7018 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7019 cval |= (HOST_WIDE_INT) -1 << width;
7021 y = simplify_gen_binary (AND, GET_MODE (x),
7022 XEXP (x, 0), GEN_INT (cval));
7023 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7033 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7034 low-order bits (as in an alignment operation) and FOO is already
7035 aligned to that boundary, mask C1 to that boundary as well.
7036 This may eliminate that PLUS and, later, the AND. */
7039 unsigned int width = GET_MODE_BITSIZE (mode);
7040 unsigned HOST_WIDE_INT smask = mask;
7042 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7043 number, sign extend it. */
7045 if (width < HOST_BITS_PER_WIDE_INT
7046 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7047 smask |= (HOST_WIDE_INT) -1 << width;
7049 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7050 && exact_log2 (- smask) >= 0
7051 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7052 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7053 return force_to_mode (plus_constant (XEXP (x, 0),
7054 (INTVAL (XEXP (x, 1)) & smask)),
7055 mode, smask, reg, next_select);
7058 /* ... fall through ... */
7061 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7062 most significant bit in MASK since carries from those bits will
7063 affect the bits we are interested in. */
7068 /* If X is (minus C Y) where C's least set bit is larger than any bit
7069 in the mask, then we may replace with (neg Y). */
7070 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7071 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7072 & -INTVAL (XEXP (x, 0))))
7075 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7077 return force_to_mode (x, mode, mask, reg, next_select);
7080 /* Similarly, if C contains every bit in the fuller_mask, then we may
7081 replace with (not Y). */
7082 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7083 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7084 == INTVAL (XEXP (x, 0))))
7086 x = simplify_gen_unary (NOT, GET_MODE (x),
7087 XEXP (x, 1), GET_MODE (x));
7088 return force_to_mode (x, mode, mask, reg, next_select);
7096 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7097 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7098 operation which may be a bitfield extraction. Ensure that the
7099 constant we form is not wider than the mode of X. */
7101 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7102 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7103 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7104 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7105 && GET_CODE (XEXP (x, 1)) == CONST_INT
7106 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7107 + floor_log2 (INTVAL (XEXP (x, 1))))
7108 < GET_MODE_BITSIZE (GET_MODE (x)))
7109 && (INTVAL (XEXP (x, 1))
7110 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7112 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7113 << INTVAL (XEXP (XEXP (x, 0), 1)));
7114 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7115 XEXP (XEXP (x, 0), 0), temp);
7116 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7117 XEXP (XEXP (x, 0), 1));
7118 return force_to_mode (x, mode, mask, reg, next_select);
7122 /* For most binary operations, just propagate into the operation and
7123 change the mode if we have an operation of that mode. */
7125 op0 = gen_lowpart (op_mode,
7126 force_to_mode (XEXP (x, 0), mode, mask,
7128 op1 = gen_lowpart (op_mode,
7129 force_to_mode (XEXP (x, 1), mode, mask,
7132 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7133 x = simplify_gen_binary (code, op_mode, op0, op1);
7137 /* For left shifts, do the same, but just for the first operand.
7138 However, we cannot do anything with shifts where we cannot
7139 guarantee that the counts are smaller than the size of the mode
7140 because such a count will have a different meaning in a
7143 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7144 && INTVAL (XEXP (x, 1)) >= 0
7145 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7146 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7147 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7148 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7151 /* If the shift count is a constant and we can do arithmetic in
7152 the mode of the shift, refine which bits we need. Otherwise, use the
7153 conservative form of the mask. */
7154 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7155 && INTVAL (XEXP (x, 1)) >= 0
7156 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7157 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7158 mask >>= INTVAL (XEXP (x, 1));
7162 op0 = gen_lowpart (op_mode,
7163 force_to_mode (XEXP (x, 0), op_mode,
7164 mask, reg, next_select));
7166 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7167 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7171 /* Here we can only do something if the shift count is a constant,
7172 this shift constant is valid for the host, and we can do arithmetic
7175 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7176 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7177 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7179 rtx inner = XEXP (x, 0);
7180 unsigned HOST_WIDE_INT inner_mask;
7182 /* Select the mask of the bits we need for the shift operand. */
7183 inner_mask = mask << INTVAL (XEXP (x, 1));
7185 /* We can only change the mode of the shift if we can do arithmetic
7186 in the mode of the shift and INNER_MASK is no wider than the
7187 width of X's mode. */
7188 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7189 op_mode = GET_MODE (x);
7191 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7193 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7194 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7197 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7198 shift and AND produces only copies of the sign bit (C2 is one less
7199 than a power of two), we can do this with just a shift. */
7201 if (GET_CODE (x) == LSHIFTRT
7202 && GET_CODE (XEXP (x, 1)) == CONST_INT
7203 /* The shift puts one of the sign bit copies in the least significant
7205 && ((INTVAL (XEXP (x, 1))
7206 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7207 >= GET_MODE_BITSIZE (GET_MODE (x)))
7208 && exact_log2 (mask + 1) >= 0
7209 /* Number of bits left after the shift must be more than the mask
7211 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7212 <= GET_MODE_BITSIZE (GET_MODE (x)))
7213 /* Must be more sign bit copies than the mask needs. */
7214 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7215 >= exact_log2 (mask + 1)))
7216 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7217 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7218 - exact_log2 (mask + 1)));
7223 /* If we are just looking for the sign bit, we don't need this shift at
7224 all, even if it has a variable count. */
7225 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7226 && (mask == ((unsigned HOST_WIDE_INT) 1
7227 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7228 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7230 /* If this is a shift by a constant, get a mask that contains those bits
7231 that are not copies of the sign bit. We then have two cases: If
7232 MASK only includes those bits, this can be a logical shift, which may
7233 allow simplifications. If MASK is a single-bit field not within
7234 those bits, we are requesting a copy of the sign bit and hence can
7235 shift the sign bit to the appropriate location. */
7237 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7238 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7242 /* If the considered data is wider than HOST_WIDE_INT, we can't
7243 represent a mask for all its bits in a single scalar.
7244 But we only care about the lower bits, so calculate these. */
7246 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7248 nonzero = ~(HOST_WIDE_INT) 0;
7250 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7251 is the number of bits a full-width mask would have set.
7252 We need only shift if these are fewer than nonzero can
7253 hold. If not, we must keep all bits set in nonzero. */
7255 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7256 < HOST_BITS_PER_WIDE_INT)
7257 nonzero >>= INTVAL (XEXP (x, 1))
7258 + HOST_BITS_PER_WIDE_INT
7259 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7263 nonzero = GET_MODE_MASK (GET_MODE (x));
7264 nonzero >>= INTVAL (XEXP (x, 1));
7267 if ((mask & ~nonzero) == 0
7268 || (i = exact_log2 (mask)) >= 0)
7270 x = simplify_shift_const
7271 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7272 i < 0 ? INTVAL (XEXP (x, 1))
7273 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7275 if (GET_CODE (x) != ASHIFTRT)
7276 return force_to_mode (x, mode, mask, reg, next_select);
7280 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7281 even if the shift count isn't a constant. */
7283 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7284 XEXP (x, 0), XEXP (x, 1));
7288 /* If this is a zero- or sign-extension operation that just affects bits
7289 we don't care about, remove it. Be sure the call above returned
7290 something that is still a shift. */
7292 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7293 && GET_CODE (XEXP (x, 1)) == CONST_INT
7294 && INTVAL (XEXP (x, 1)) >= 0
7295 && (INTVAL (XEXP (x, 1))
7296 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7297 && GET_CODE (XEXP (x, 0)) == ASHIFT
7298 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7299 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7306 /* If the shift count is constant and we can do computations
7307 in the mode of X, compute where the bits we care about are.
7308 Otherwise, we can't do anything. Don't change the mode of
7309 the shift or propagate MODE into the shift, though. */
7310 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7311 && INTVAL (XEXP (x, 1)) >= 0)
7313 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7314 GET_MODE (x), GEN_INT (mask),
7316 if (temp && GET_CODE (temp) == CONST_INT)
7318 force_to_mode (XEXP (x, 0), GET_MODE (x),
7319 INTVAL (temp), reg, next_select));
7324 /* If we just want the low-order bit, the NEG isn't needed since it
7325 won't change the low-order bit. */
7327 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7329 /* We need any bits less significant than the most significant bit in
7330 MASK since carries from those bits will affect the bits we are
7336 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7337 same as the XOR case above. Ensure that the constant we form is not
7338 wider than the mode of X. */
7340 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7341 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7342 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7343 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7344 < GET_MODE_BITSIZE (GET_MODE (x)))
7345 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7347 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7349 temp = simplify_gen_binary (XOR, GET_MODE (x),
7350 XEXP (XEXP (x, 0), 0), temp);
7351 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7352 temp, XEXP (XEXP (x, 0), 1));
7354 return force_to_mode (x, mode, mask, reg, next_select);
7357 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7358 use the full mask inside the NOT. */
7362 op0 = gen_lowpart (op_mode,
7363 force_to_mode (XEXP (x, 0), mode, mask,
7365 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7366 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7370 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7371 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7372 which is equal to STORE_FLAG_VALUE. */
7373 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7374 && GET_MODE (XEXP (x, 0)) == mode
7375 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7376 && (nonzero_bits (XEXP (x, 0), mode)
7377 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7378 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7383 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7384 written in a narrower mode. We play it safe and do not do so. */
7387 gen_lowpart (GET_MODE (x),
7388 force_to_mode (XEXP (x, 1), mode,
7389 mask, reg, next_select)));
7391 gen_lowpart (GET_MODE (x),
7392 force_to_mode (XEXP (x, 2), mode,
7393 mask, reg, next_select)));
7400 /* Ensure we return a value of the proper mode. */
7401 return gen_lowpart (mode, x);
7404 /* Return nonzero if X is an expression that has one of two values depending on
7405 whether some other value is zero or nonzero. In that case, we return the
7406 value that is being tested, *PTRUE is set to the value if the rtx being
7407 returned has a nonzero value, and *PFALSE is set to the other alternative.
7409 If we return zero, we set *PTRUE and *PFALSE to X. */
7412 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7414 enum machine_mode mode = GET_MODE (x);
7415 enum rtx_code code = GET_CODE (x);
7416 rtx cond0, cond1, true0, true1, false0, false1;
7417 unsigned HOST_WIDE_INT nz;
7419 /* If we are comparing a value against zero, we are done. */
7420 if ((code == NE || code == EQ)
7421 && XEXP (x, 1) == const0_rtx)
7423 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7424 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7428 /* If this is a unary operation whose operand has one of two values, apply
7429 our opcode to compute those values. */
7430 else if (UNARY_P (x)
7431 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7433 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7434 *pfalse = simplify_gen_unary (code, mode, false0,
7435 GET_MODE (XEXP (x, 0)));
7439 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7440 make can't possibly match and would suppress other optimizations. */
7441 else if (code == COMPARE)
7444 /* If this is a binary operation, see if either side has only one of two
7445 values. If either one does or if both do and they are conditional on
7446 the same value, compute the new true and false values. */
7447 else if (BINARY_P (x))
7449 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7450 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7452 if ((cond0 != 0 || cond1 != 0)
7453 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7455 /* If if_then_else_cond returned zero, then true/false are the
7456 same rtl. We must copy one of them to prevent invalid rtl
7459 true0 = copy_rtx (true0);
7460 else if (cond1 == 0)
7461 true1 = copy_rtx (true1);
7463 if (COMPARISON_P (x))
7465 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7467 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7472 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7473 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7476 return cond0 ? cond0 : cond1;
7479 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7480 operands is zero when the other is nonzero, and vice-versa,
7481 and STORE_FLAG_VALUE is 1 or -1. */
7483 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7484 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7486 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7488 rtx op0 = XEXP (XEXP (x, 0), 1);
7489 rtx op1 = XEXP (XEXP (x, 1), 1);
7491 cond0 = XEXP (XEXP (x, 0), 0);
7492 cond1 = XEXP (XEXP (x, 1), 0);
7494 if (COMPARISON_P (cond0)
7495 && COMPARISON_P (cond1)
7496 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7497 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7498 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7499 || ((swap_condition (GET_CODE (cond0))
7500 == reversed_comparison_code (cond1, NULL))
7501 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7502 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7503 && ! side_effects_p (x))
7505 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7506 *pfalse = simplify_gen_binary (MULT, mode,
7508 ? simplify_gen_unary (NEG, mode,
7516 /* Similarly for MULT, AND and UMIN, except that for these the result
7518 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7519 && (code == MULT || code == AND || code == UMIN)
7520 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7522 cond0 = XEXP (XEXP (x, 0), 0);
7523 cond1 = XEXP (XEXP (x, 1), 0);
7525 if (COMPARISON_P (cond0)
7526 && COMPARISON_P (cond1)
7527 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7528 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7529 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7530 || ((swap_condition (GET_CODE (cond0))
7531 == reversed_comparison_code (cond1, NULL))
7532 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7533 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7534 && ! side_effects_p (x))
7536 *ptrue = *pfalse = const0_rtx;
7542 else if (code == IF_THEN_ELSE)
7544 /* If we have IF_THEN_ELSE already, extract the condition and
7545 canonicalize it if it is NE or EQ. */
7546 cond0 = XEXP (x, 0);
7547 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7548 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7549 return XEXP (cond0, 0);
7550 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7552 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7553 return XEXP (cond0, 0);
7559 /* If X is a SUBREG, we can narrow both the true and false values
7560 if the inner expression, if there is a condition. */
7561 else if (code == SUBREG
7562 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7565 true0 = simplify_gen_subreg (mode, true0,
7566 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7567 false0 = simplify_gen_subreg (mode, false0,
7568 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7569 if (true0 && false0)
7577 /* If X is a constant, this isn't special and will cause confusions
7578 if we treat it as such. Likewise if it is equivalent to a constant. */
7579 else if (CONSTANT_P (x)
7580 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7583 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7584 will be least confusing to the rest of the compiler. */
7585 else if (mode == BImode)
7587 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7591 /* If X is known to be either 0 or -1, those are the true and
7592 false values when testing X. */
7593 else if (x == constm1_rtx || x == const0_rtx
7594 || (mode != VOIDmode
7595 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7597 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7601 /* Likewise for 0 or a single bit. */
7602 else if (SCALAR_INT_MODE_P (mode)
7603 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7604 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7606 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7610 /* Otherwise fail; show no condition with true and false values the same. */
7611 *ptrue = *pfalse = x;
7615 /* Return the value of expression X given the fact that condition COND
7616 is known to be true when applied to REG as its first operand and VAL
7617 as its second. X is known to not be shared and so can be modified in
7620 We only handle the simplest cases, and specifically those cases that
7621 arise with IF_THEN_ELSE expressions. */
7624 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7626 enum rtx_code code = GET_CODE (x);
7631 if (side_effects_p (x))
7634 /* If either operand of the condition is a floating point value,
7635 then we have to avoid collapsing an EQ comparison. */
7637 && rtx_equal_p (x, reg)
7638 && ! FLOAT_MODE_P (GET_MODE (x))
7639 && ! FLOAT_MODE_P (GET_MODE (val)))
7642 if (cond == UNEQ && rtx_equal_p (x, reg))
7645 /* If X is (abs REG) and we know something about REG's relationship
7646 with zero, we may be able to simplify this. */
7648 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7651 case GE: case GT: case EQ:
7654 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7656 GET_MODE (XEXP (x, 0)));
7661 /* The only other cases we handle are MIN, MAX, and comparisons if the
7662 operands are the same as REG and VAL. */
7664 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7666 if (rtx_equal_p (XEXP (x, 0), val))
7667 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7669 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7671 if (COMPARISON_P (x))
7673 if (comparison_dominates_p (cond, code))
7674 return const_true_rtx;
7676 code = reversed_comparison_code (x, NULL);
7678 && comparison_dominates_p (cond, code))
7683 else if (code == SMAX || code == SMIN
7684 || code == UMIN || code == UMAX)
7686 int unsignedp = (code == UMIN || code == UMAX);
7688 /* Do not reverse the condition when it is NE or EQ.
7689 This is because we cannot conclude anything about
7690 the value of 'SMAX (x, y)' when x is not equal to y,
7691 but we can when x equals y. */
7692 if ((code == SMAX || code == UMAX)
7693 && ! (cond == EQ || cond == NE))
7694 cond = reverse_condition (cond);
7699 return unsignedp ? x : XEXP (x, 1);
7701 return unsignedp ? x : XEXP (x, 0);
7703 return unsignedp ? XEXP (x, 1) : x;
7705 return unsignedp ? XEXP (x, 0) : x;
7712 else if (code == SUBREG)
7714 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7715 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7717 if (SUBREG_REG (x) != r)
7719 /* We must simplify subreg here, before we lose track of the
7720 original inner_mode. */
7721 new = simplify_subreg (GET_MODE (x), r,
7722 inner_mode, SUBREG_BYTE (x));
7726 SUBST (SUBREG_REG (x), r);
7731 /* We don't have to handle SIGN_EXTEND here, because even in the
7732 case of replacing something with a modeless CONST_INT, a
7733 CONST_INT is already (supposed to be) a valid sign extension for
7734 its narrower mode, which implies it's already properly
7735 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7736 story is different. */
7737 else if (code == ZERO_EXTEND)
7739 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7740 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7742 if (XEXP (x, 0) != r)
7744 /* We must simplify the zero_extend here, before we lose
7745 track of the original inner_mode. */
7746 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7751 SUBST (XEXP (x, 0), r);
7757 fmt = GET_RTX_FORMAT (code);
7758 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7761 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7762 else if (fmt[i] == 'E')
7763 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7764 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7771 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7772 assignment as a field assignment. */
7775 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7777 if (x == y || rtx_equal_p (x, y))
7780 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7783 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7784 Note that all SUBREGs of MEM are paradoxical; otherwise they
7785 would have been rewritten. */
7786 if (MEM_P (x) && GET_CODE (y) == SUBREG
7787 && MEM_P (SUBREG_REG (y))
7788 && rtx_equal_p (SUBREG_REG (y),
7789 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7792 if (MEM_P (y) && GET_CODE (x) == SUBREG
7793 && MEM_P (SUBREG_REG (x))
7794 && rtx_equal_p (SUBREG_REG (x),
7795 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7798 /* We used to see if get_last_value of X and Y were the same but that's
7799 not correct. In one direction, we'll cause the assignment to have
7800 the wrong destination and in the case, we'll import a register into this
7801 insn that might have already have been dead. So fail if none of the
7802 above cases are true. */
7806 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7807 Return that assignment if so.
7809 We only handle the most common cases. */
7812 make_field_assignment (rtx x)
7814 rtx dest = SET_DEST (x);
7815 rtx src = SET_SRC (x);
7820 unsigned HOST_WIDE_INT len;
7822 enum machine_mode mode;
7824 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7825 a clear of a one-bit field. We will have changed it to
7826 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7829 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7830 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7831 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7832 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7834 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7837 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7841 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7842 && subreg_lowpart_p (XEXP (src, 0))
7843 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7844 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7845 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7846 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7847 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7848 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7850 assign = make_extraction (VOIDmode, dest, 0,
7851 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7854 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7858 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7860 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7861 && XEXP (XEXP (src, 0), 0) == const1_rtx
7862 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7864 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7867 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7871 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7872 SRC is an AND with all bits of that field set, then we can discard
7874 if (GET_CODE (dest) == ZERO_EXTRACT
7875 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7876 && GET_CODE (src) == AND
7877 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7879 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7880 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7881 unsigned HOST_WIDE_INT ze_mask;
7883 if (width >= HOST_BITS_PER_WIDE_INT)
7886 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7888 /* Complete overlap. We can remove the source AND. */
7889 if ((and_mask & ze_mask) == ze_mask)
7890 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7892 /* Partial overlap. We can reduce the source AND. */
7893 if ((and_mask & ze_mask) != and_mask)
7895 mode = GET_MODE (src);
7896 src = gen_rtx_AND (mode, XEXP (src, 0),
7897 gen_int_mode (and_mask & ze_mask, mode));
7898 return gen_rtx_SET (VOIDmode, dest, src);
7902 /* The other case we handle is assignments into a constant-position
7903 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7904 a mask that has all one bits except for a group of zero bits and
7905 OTHER is known to have zeros where C1 has ones, this is such an
7906 assignment. Compute the position and length from C1. Shift OTHER
7907 to the appropriate position, force it to the required mode, and
7908 make the extraction. Check for the AND in both operands. */
7910 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7913 rhs = expand_compound_operation (XEXP (src, 0));
7914 lhs = expand_compound_operation (XEXP (src, 1));
7916 if (GET_CODE (rhs) == AND
7917 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7918 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7919 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7920 else if (GET_CODE (lhs) == AND
7921 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7922 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7923 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7927 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7928 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7929 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7930 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7933 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7937 /* The mode to use for the source is the mode of the assignment, or of
7938 what is inside a possible STRICT_LOW_PART. */
7939 mode = (GET_CODE (assign) == STRICT_LOW_PART
7940 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7942 /* Shift OTHER right POS places and make it the source, restricting it
7943 to the proper length and mode. */
7945 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7946 GET_MODE (src), other, pos),
7948 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7949 ? ~(unsigned HOST_WIDE_INT) 0
7950 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7953 /* If SRC is masked by an AND that does not make a difference in
7954 the value being stored, strip it. */
7955 if (GET_CODE (assign) == ZERO_EXTRACT
7956 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7957 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7958 && GET_CODE (src) == AND
7959 && GET_CODE (XEXP (src, 1)) == CONST_INT
7960 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7961 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7962 src = XEXP (src, 0);
7964 return gen_rtx_SET (VOIDmode, assign, src);
7967 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7971 apply_distributive_law (rtx x)
7973 enum rtx_code code = GET_CODE (x);
7974 enum rtx_code inner_code;
7975 rtx lhs, rhs, other;
7978 /* Distributivity is not true for floating point as it can change the
7979 value. So we don't do it unless -funsafe-math-optimizations. */
7980 if (FLOAT_MODE_P (GET_MODE (x))
7981 && ! flag_unsafe_math_optimizations)
7984 /* The outer operation can only be one of the following: */
7985 if (code != IOR && code != AND && code != XOR
7986 && code != PLUS && code != MINUS)
7992 /* If either operand is a primitive we can't do anything, so get out
7994 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7997 lhs = expand_compound_operation (lhs);
7998 rhs = expand_compound_operation (rhs);
7999 inner_code = GET_CODE (lhs);
8000 if (inner_code != GET_CODE (rhs))
8003 /* See if the inner and outer operations distribute. */
8010 /* These all distribute except over PLUS. */
8011 if (code == PLUS || code == MINUS)
8016 if (code != PLUS && code != MINUS)
8021 /* This is also a multiply, so it distributes over everything. */
8025 /* Non-paradoxical SUBREGs distributes over all operations, provided
8026 the inner modes and byte offsets are the same, this is an extraction
8027 of a low-order part, we don't convert an fp operation to int or
8028 vice versa, and we would not be converting a single-word
8029 operation into a multi-word operation. The latter test is not
8030 required, but it prevents generating unneeded multi-word operations.
8031 Some of the previous tests are redundant given the latter test, but
8032 are retained because they are required for correctness.
8034 We produce the result slightly differently in this case. */
8036 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8037 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8038 || ! subreg_lowpart_p (lhs)
8039 || (GET_MODE_CLASS (GET_MODE (lhs))
8040 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8041 || (GET_MODE_SIZE (GET_MODE (lhs))
8042 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8043 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8046 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8047 SUBREG_REG (lhs), SUBREG_REG (rhs));
8048 return gen_lowpart (GET_MODE (x), tem);
8054 /* Set LHS and RHS to the inner operands (A and B in the example
8055 above) and set OTHER to the common operand (C in the example).
8056 There is only one way to do this unless the inner operation is
8058 if (COMMUTATIVE_ARITH_P (lhs)
8059 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8060 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8061 else if (COMMUTATIVE_ARITH_P (lhs)
8062 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8063 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8064 else if (COMMUTATIVE_ARITH_P (lhs)
8065 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8066 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8067 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8068 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8072 /* Form the new inner operation, seeing if it simplifies first. */
8073 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8075 /* There is one exception to the general way of distributing:
8076 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8077 if (code == XOR && inner_code == IOR)
8080 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8083 /* We may be able to continuing distributing the result, so call
8084 ourselves recursively on the inner operation before forming the
8085 outer operation, which we return. */
8086 return simplify_gen_binary (inner_code, GET_MODE (x),
8087 apply_distributive_law (tem), other);
8090 /* See if X is of the form (* (+ A B) C), and if so convert to
8091 (+ (* A C) (* B C)) and try to simplify.
8093 Most of the time, this results in no change. However, if some of
8094 the operands are the same or inverses of each other, simplifications
8097 For example, (and (ior A B) (not B)) can occur as the result of
8098 expanding a bit field assignment. When we apply the distributive
8099 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8100 which then simplifies to (and (A (not B))).
8102 Note that no checks happen on the validity of applying the inverse
8103 distributive law. This is pointless since we can do it in the
8104 few places where this routine is called.
8106 N is the index of the term that is decomposed (the arithmetic operation,
8107 i.e. (+ A B) in the first example above). !N is the index of the term that
8108 is distributed, i.e. of C in the first example above. */
8110 distribute_and_simplify_rtx (rtx x, int n)
8112 enum machine_mode mode;
8113 enum rtx_code outer_code, inner_code;
8114 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8116 decomposed = XEXP (x, n);
8117 if (!ARITHMETIC_P (decomposed))
8120 mode = GET_MODE (x);
8121 outer_code = GET_CODE (x);
8122 distributed = XEXP (x, !n);
8124 inner_code = GET_CODE (decomposed);
8125 inner_op0 = XEXP (decomposed, 0);
8126 inner_op1 = XEXP (decomposed, 1);
8128 /* Special case (and (xor B C) (not A)), which is equivalent to
8129 (xor (ior A B) (ior A C)) */
8130 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8132 distributed = XEXP (distributed, 0);
8138 /* Distribute the second term. */
8139 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8140 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8144 /* Distribute the first term. */
8145 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8146 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8149 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8151 if (GET_CODE (tmp) != outer_code
8152 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8158 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8161 Return an equivalent form, if different from X. Otherwise, return X. If
8162 X is zero, we are to always construct the equivalent form. */
8165 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8166 unsigned HOST_WIDE_INT constop)
8168 unsigned HOST_WIDE_INT nonzero;
8171 /* Simplify VAROP knowing that we will be only looking at some of the
8174 Note by passing in CONSTOP, we guarantee that the bits not set in
8175 CONSTOP are not significant and will never be examined. We must
8176 ensure that is the case by explicitly masking out those bits
8177 before returning. */
8178 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8180 /* If VAROP is a CLOBBER, we will fail so return it. */
8181 if (GET_CODE (varop) == CLOBBER)
8184 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8185 to VAROP and return the new constant. */
8186 if (GET_CODE (varop) == CONST_INT)
8187 return gen_int_mode (INTVAL (varop) & constop, mode);
8189 /* See what bits may be nonzero in VAROP. Unlike the general case of
8190 a call to nonzero_bits, here we don't care about bits outside
8193 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8195 /* Turn off all bits in the constant that are known to already be zero.
8196 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8197 which is tested below. */
8201 /* If we don't have any bits left, return zero. */
8205 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8206 a power of two, we can replace this with an ASHIFT. */
8207 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8208 && (i = exact_log2 (constop)) >= 0)
8209 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8211 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8212 or XOR, then try to apply the distributive law. This may eliminate
8213 operations if either branch can be simplified because of the AND.
8214 It may also make some cases more complex, but those cases probably
8215 won't match a pattern either with or without this. */
8217 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8221 apply_distributive_law
8222 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8223 simplify_and_const_int (NULL_RTX,
8227 simplify_and_const_int (NULL_RTX,
8232 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8233 the AND and see if one of the operands simplifies to zero. If so, we
8234 may eliminate it. */
8236 if (GET_CODE (varop) == PLUS
8237 && exact_log2 (constop + 1) >= 0)
8241 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8242 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8243 if (o0 == const0_rtx)
8245 if (o1 == const0_rtx)
8249 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8250 if we already had one (just check for the simplest cases). */
8251 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8252 && GET_MODE (XEXP (x, 0)) == mode
8253 && SUBREG_REG (XEXP (x, 0)) == varop)
8254 varop = XEXP (x, 0);
8256 varop = gen_lowpart (mode, varop);
8258 /* If we can't make the SUBREG, try to return what we were given. */
8259 if (GET_CODE (varop) == CLOBBER)
8260 return x ? x : varop;
8262 /* If we are only masking insignificant bits, return VAROP. */
8263 if (constop == nonzero)
8267 /* Otherwise, return an AND. */
8268 constop = trunc_int_for_mode (constop, mode);
8269 /* See how much, if any, of X we can use. */
8270 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8271 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8275 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8276 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8277 SUBST (XEXP (x, 1), GEN_INT (constop));
8279 SUBST (XEXP (x, 0), varop);
8286 /* Given a REG, X, compute which bits in X can be nonzero.
8287 We don't care about bits outside of those defined in MODE.
8289 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8290 a shift, AND, or zero_extract, we can do better. */
8293 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8294 rtx known_x ATTRIBUTE_UNUSED,
8295 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8296 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8297 unsigned HOST_WIDE_INT *nonzero)
8301 /* If X is a register whose nonzero bits value is current, use it.
8302 Otherwise, if X is a register whose value we can find, use that
8303 value. Otherwise, use the previously-computed global nonzero bits
8304 for this register. */
8306 if (reg_stat[REGNO (x)].last_set_value != 0
8307 && (reg_stat[REGNO (x)].last_set_mode == mode
8308 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8309 && GET_MODE_CLASS (mode) == MODE_INT))
8310 && (reg_stat[REGNO (x)].last_set_label == label_tick
8311 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8312 && REG_N_SETS (REGNO (x)) == 1
8313 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8315 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8317 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8321 tem = get_last_value (x);
8325 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8326 /* If X is narrower than MODE and TEM is a non-negative
8327 constant that would appear negative in the mode of X,
8328 sign-extend it for use in reg_nonzero_bits because some
8329 machines (maybe most) will actually do the sign-extension
8330 and this is the conservative approach.
8332 ??? For 2.5, try to tighten up the MD files in this regard
8333 instead of this kludge. */
8335 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8336 && GET_CODE (tem) == CONST_INT
8338 && 0 != (INTVAL (tem)
8339 & ((HOST_WIDE_INT) 1
8340 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8341 tem = GEN_INT (INTVAL (tem)
8342 | ((HOST_WIDE_INT) (-1)
8343 << GET_MODE_BITSIZE (GET_MODE (x))));
8347 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8349 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8351 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8352 /* We don't know anything about the upper bits. */
8353 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8360 /* Return the number of bits at the high-order end of X that are known to
8361 be equal to the sign bit. X will be used in mode MODE; if MODE is
8362 VOIDmode, X will be used in its own mode. The returned value will always
8363 be between 1 and the number of bits in MODE. */
8366 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8367 rtx known_x ATTRIBUTE_UNUSED,
8368 enum machine_mode known_mode
8370 unsigned int known_ret ATTRIBUTE_UNUSED,
8371 unsigned int *result)
8375 if (reg_stat[REGNO (x)].last_set_value != 0
8376 && reg_stat[REGNO (x)].last_set_mode == mode
8377 && (reg_stat[REGNO (x)].last_set_label == label_tick
8378 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8379 && REG_N_SETS (REGNO (x)) == 1
8380 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8382 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8384 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8388 tem = get_last_value (x);
8392 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8393 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8394 *result = reg_stat[REGNO (x)].sign_bit_copies;
8399 /* Return the number of "extended" bits there are in X, when interpreted
8400 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8401 unsigned quantities, this is the number of high-order zero bits.
8402 For signed quantities, this is the number of copies of the sign bit
8403 minus 1. In both case, this function returns the number of "spare"
8404 bits. For example, if two quantities for which this function returns
8405 at least 1 are added, the addition is known not to overflow.
8407 This function will always return 0 unless called during combine, which
8408 implies that it must be called from a define_split. */
8411 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8413 if (nonzero_sign_valid == 0)
8417 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8418 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8419 - floor_log2 (nonzero_bits (x, mode)))
8421 : num_sign_bit_copies (x, mode) - 1);
8424 /* This function is called from `simplify_shift_const' to merge two
8425 outer operations. Specifically, we have already found that we need
8426 to perform operation *POP0 with constant *PCONST0 at the outermost
8427 position. We would now like to also perform OP1 with constant CONST1
8428 (with *POP0 being done last).
8430 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8431 the resulting operation. *PCOMP_P is set to 1 if we would need to
8432 complement the innermost operand, otherwise it is unchanged.
8434 MODE is the mode in which the operation will be done. No bits outside
8435 the width of this mode matter. It is assumed that the width of this mode
8436 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8438 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8439 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8440 result is simply *PCONST0.
8442 If the resulting operation cannot be expressed as one operation, we
8443 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8446 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8448 enum rtx_code op0 = *pop0;
8449 HOST_WIDE_INT const0 = *pconst0;
8451 const0 &= GET_MODE_MASK (mode);
8452 const1 &= GET_MODE_MASK (mode);
8454 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8458 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8461 if (op1 == UNKNOWN || op0 == SET)
8464 else if (op0 == UNKNOWN)
8465 op0 = op1, const0 = const1;
8467 else if (op0 == op1)
8491 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8492 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8495 /* If the two constants aren't the same, we can't do anything. The
8496 remaining six cases can all be done. */
8497 else if (const0 != const1)
8505 /* (a & b) | b == b */
8507 else /* op1 == XOR */
8508 /* (a ^ b) | b == a | b */
8514 /* (a & b) ^ b == (~a) & b */
8515 op0 = AND, *pcomp_p = 1;
8516 else /* op1 == IOR */
8517 /* (a | b) ^ b == a & ~b */
8518 op0 = AND, const0 = ~const0;
8523 /* (a | b) & b == b */
8525 else /* op1 == XOR */
8526 /* (a ^ b) & b) == (~a) & b */
8533 /* Check for NO-OP cases. */
8534 const0 &= GET_MODE_MASK (mode);
8536 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8538 else if (const0 == 0 && op0 == AND)
8540 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8544 /* ??? Slightly redundant with the above mask, but not entirely.
8545 Moving this above means we'd have to sign-extend the mode mask
8546 for the final test. */
8547 const0 = trunc_int_for_mode (const0, mode);
8555 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8556 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8557 that we started with.
8559 The shift is normally computed in the widest mode we find in VAROP, as
8560 long as it isn't a different number of words than RESULT_MODE. Exceptions
8561 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8564 simplify_shift_const (rtx x, enum rtx_code code,
8565 enum machine_mode result_mode, rtx varop,
8568 enum rtx_code orig_code = code;
8571 enum machine_mode mode = result_mode;
8572 enum machine_mode shift_mode, tmode;
8573 unsigned int mode_words
8574 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8575 /* We form (outer_op (code varop count) (outer_const)). */
8576 enum rtx_code outer_op = UNKNOWN;
8577 HOST_WIDE_INT outer_const = 0;
8579 int complement_p = 0;
8582 /* Make sure and truncate the "natural" shift on the way in. We don't
8583 want to do this inside the loop as it makes it more difficult to
8585 if (SHIFT_COUNT_TRUNCATED)
8586 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8588 /* If we were given an invalid count, don't do anything except exactly
8589 what was requested. */
8591 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8596 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8601 /* Unless one of the branches of the `if' in this loop does a `continue',
8602 we will `break' the loop after the `if'. */
8606 /* If we have an operand of (clobber (const_int 0)), just return that
8608 if (GET_CODE (varop) == CLOBBER)
8611 /* If we discovered we had to complement VAROP, leave. Making a NOT
8612 here would cause an infinite loop. */
8616 /* Convert ROTATERT to ROTATE. */
8617 if (code == ROTATERT)
8619 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8621 if (VECTOR_MODE_P (result_mode))
8622 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8624 count = bitsize - count;
8627 /* We need to determine what mode we will do the shift in. If the
8628 shift is a right shift or a ROTATE, we must always do it in the mode
8629 it was originally done in. Otherwise, we can do it in MODE, the
8630 widest mode encountered. */
8632 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8633 ? result_mode : mode);
8635 /* Handle cases where the count is greater than the size of the mode
8636 minus 1. For ASHIFT, use the size minus one as the count (this can
8637 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8638 take the count modulo the size. For other shifts, the result is
8641 Since these shifts are being produced by the compiler by combining
8642 multiple operations, each of which are defined, we know what the
8643 result is supposed to be. */
8645 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8647 if (code == ASHIFTRT)
8648 count = GET_MODE_BITSIZE (shift_mode) - 1;
8649 else if (code == ROTATE || code == ROTATERT)
8650 count %= GET_MODE_BITSIZE (shift_mode);
8653 /* We can't simply return zero because there may be an
8661 /* An arithmetic right shift of a quantity known to be -1 or 0
8663 if (code == ASHIFTRT
8664 && (num_sign_bit_copies (varop, shift_mode)
8665 == GET_MODE_BITSIZE (shift_mode)))
8671 /* If we are doing an arithmetic right shift and discarding all but
8672 the sign bit copies, this is equivalent to doing a shift by the
8673 bitsize minus one. Convert it into that shift because it will often
8674 allow other simplifications. */
8676 if (code == ASHIFTRT
8677 && (count + num_sign_bit_copies (varop, shift_mode)
8678 >= GET_MODE_BITSIZE (shift_mode)))
8679 count = GET_MODE_BITSIZE (shift_mode) - 1;
8681 /* We simplify the tests below and elsewhere by converting
8682 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8683 `make_compound_operation' will convert it to an ASHIFTRT for
8684 those machines (such as VAX) that don't have an LSHIFTRT. */
8685 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8687 && ((nonzero_bits (varop, shift_mode)
8688 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8692 if (code == LSHIFTRT
8693 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8694 && !(nonzero_bits (varop, shift_mode) >> count))
8697 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8698 && !((nonzero_bits (varop, shift_mode) << count)
8699 & GET_MODE_MASK (shift_mode)))
8702 switch (GET_CODE (varop))
8708 new = expand_compound_operation (varop);
8717 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8718 minus the width of a smaller mode, we can do this with a
8719 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8720 if ((code == ASHIFTRT || code == LSHIFTRT)
8721 && ! mode_dependent_address_p (XEXP (varop, 0))
8722 && ! MEM_VOLATILE_P (varop)
8723 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8724 MODE_INT, 1)) != BLKmode)
8726 new = adjust_address_nv (varop, tmode,
8727 BYTES_BIG_ENDIAN ? 0
8728 : count / BITS_PER_UNIT);
8730 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8731 : ZERO_EXTEND, mode, new);
8738 /* Similar to the case above, except that we can only do this if
8739 the resulting mode is the same as that of the underlying
8740 MEM and adjust the address depending on the *bits* endianness
8741 because of the way that bit-field extract insns are defined. */
8742 if ((code == ASHIFTRT || code == LSHIFTRT)
8743 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8744 MODE_INT, 1)) != BLKmode
8745 && tmode == GET_MODE (XEXP (varop, 0)))
8747 if (BITS_BIG_ENDIAN)
8748 new = XEXP (varop, 0);
8751 new = copy_rtx (XEXP (varop, 0));
8752 SUBST (XEXP (new, 0),
8753 plus_constant (XEXP (new, 0),
8754 count / BITS_PER_UNIT));
8757 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8758 : ZERO_EXTEND, mode, new);
8765 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8766 the same number of words as what we've seen so far. Then store
8767 the widest mode in MODE. */
8768 if (subreg_lowpart_p (varop)
8769 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8770 > GET_MODE_SIZE (GET_MODE (varop)))
8771 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8772 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8775 varop = SUBREG_REG (varop);
8776 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8777 mode = GET_MODE (varop);
8783 /* Some machines use MULT instead of ASHIFT because MULT
8784 is cheaper. But it is still better on those machines to
8785 merge two shifts into one. */
8786 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8787 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8790 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8792 GEN_INT (exact_log2 (
8793 INTVAL (XEXP (varop, 1)))));
8799 /* Similar, for when divides are cheaper. */
8800 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8801 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8804 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8806 GEN_INT (exact_log2 (
8807 INTVAL (XEXP (varop, 1)))));
8813 /* If we are extracting just the sign bit of an arithmetic
8814 right shift, that shift is not needed. However, the sign
8815 bit of a wider mode may be different from what would be
8816 interpreted as the sign bit in a narrower mode, so, if
8817 the result is narrower, don't discard the shift. */
8818 if (code == LSHIFTRT
8819 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8820 && (GET_MODE_BITSIZE (result_mode)
8821 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8823 varop = XEXP (varop, 0);
8827 /* ... fall through ... */
8832 /* Here we have two nested shifts. The result is usually the
8833 AND of a new shift with a mask. We compute the result below. */
8834 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8835 && INTVAL (XEXP (varop, 1)) >= 0
8836 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8837 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8838 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8840 enum rtx_code first_code = GET_CODE (varop);
8841 unsigned int first_count = INTVAL (XEXP (varop, 1));
8842 unsigned HOST_WIDE_INT mask;
8845 /* We have one common special case. We can't do any merging if
8846 the inner code is an ASHIFTRT of a smaller mode. However, if
8847 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8848 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8849 we can convert it to
8850 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8851 This simplifies certain SIGN_EXTEND operations. */
8852 if (code == ASHIFT && first_code == ASHIFTRT
8853 && count == (unsigned int)
8854 (GET_MODE_BITSIZE (result_mode)
8855 - GET_MODE_BITSIZE (GET_MODE (varop))))
8857 /* C3 has the low-order C1 bits zero. */
8859 mask = (GET_MODE_MASK (mode)
8860 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8862 varop = simplify_and_const_int (NULL_RTX, result_mode,
8863 XEXP (varop, 0), mask);
8864 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8866 count = first_count;
8871 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8872 than C1 high-order bits equal to the sign bit, we can convert
8873 this to either an ASHIFT or an ASHIFTRT depending on the
8876 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8878 if (code == ASHIFTRT && first_code == ASHIFT
8879 && GET_MODE (varop) == shift_mode
8880 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8883 varop = XEXP (varop, 0);
8885 signed_count = count - first_count;
8886 if (signed_count < 0)
8887 count = -signed_count, code = ASHIFT;
8889 count = signed_count;
8894 /* There are some cases we can't do. If CODE is ASHIFTRT,
8895 we can only do this if FIRST_CODE is also ASHIFTRT.
8897 We can't do the case when CODE is ROTATE and FIRST_CODE is
8900 If the mode of this shift is not the mode of the outer shift,
8901 we can't do this if either shift is a right shift or ROTATE.
8903 Finally, we can't do any of these if the mode is too wide
8904 unless the codes are the same.
8906 Handle the case where the shift codes are the same
8909 if (code == first_code)
8911 if (GET_MODE (varop) != result_mode
8912 && (code == ASHIFTRT || code == LSHIFTRT
8916 count += first_count;
8917 varop = XEXP (varop, 0);
8921 if (code == ASHIFTRT
8922 || (code == ROTATE && first_code == ASHIFTRT)
8923 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8924 || (GET_MODE (varop) != result_mode
8925 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8926 || first_code == ROTATE
8927 || code == ROTATE)))
8930 /* To compute the mask to apply after the shift, shift the
8931 nonzero bits of the inner shift the same way the
8932 outer shift will. */
8934 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8937 = simplify_binary_operation (code, result_mode, mask_rtx,
8940 /* Give up if we can't compute an outer operation to use. */
8942 || GET_CODE (mask_rtx) != CONST_INT
8943 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8945 result_mode, &complement_p))
8948 /* If the shifts are in the same direction, we add the
8949 counts. Otherwise, we subtract them. */
8950 signed_count = count;
8951 if ((code == ASHIFTRT || code == LSHIFTRT)
8952 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8953 signed_count += first_count;
8955 signed_count -= first_count;
8957 /* If COUNT is positive, the new shift is usually CODE,
8958 except for the two exceptions below, in which case it is
8959 FIRST_CODE. If the count is negative, FIRST_CODE should
8961 if (signed_count > 0
8962 && ((first_code == ROTATE && code == ASHIFT)
8963 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8964 code = first_code, count = signed_count;
8965 else if (signed_count < 0)
8966 code = first_code, count = -signed_count;
8968 count = signed_count;
8970 varop = XEXP (varop, 0);
8974 /* If we have (A << B << C) for any shift, we can convert this to
8975 (A << C << B). This wins if A is a constant. Only try this if
8976 B is not a constant. */
8978 else if (GET_CODE (varop) == code
8979 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8981 = simplify_binary_operation (code, mode,
8985 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8992 /* Make this fit the case below. */
8993 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8994 GEN_INT (GET_MODE_MASK (mode)));
9000 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9001 with C the size of VAROP - 1 and the shift is logical if
9002 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9003 we have an (le X 0) operation. If we have an arithmetic shift
9004 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9005 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9007 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9008 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9009 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9010 && (code == LSHIFTRT || code == ASHIFTRT)
9011 && count == (unsigned int)
9012 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9013 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9016 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9019 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9020 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9025 /* If we have (shift (logical)), move the logical to the outside
9026 to allow it to possibly combine with another logical and the
9027 shift to combine with another shift. This also canonicalizes to
9028 what a ZERO_EXTRACT looks like. Also, some machines have
9029 (and (shift)) insns. */
9031 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9032 /* We can't do this if we have (ashiftrt (xor)) and the
9033 constant has its sign bit set in shift_mode. */
9034 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9035 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9037 && (new = simplify_binary_operation (code, result_mode,
9039 GEN_INT (count))) != 0
9040 && GET_CODE (new) == CONST_INT
9041 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9042 INTVAL (new), result_mode, &complement_p))
9044 varop = XEXP (varop, 0);
9048 /* If we can't do that, try to simplify the shift in each arm of the
9049 logical expression, make a new logical expression, and apply
9050 the inverse distributive law. This also can't be done
9051 for some (ashiftrt (xor)). */
9052 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9053 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9054 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9057 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9058 XEXP (varop, 0), count);
9059 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9060 XEXP (varop, 1), count);
9062 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9064 varop = apply_distributive_law (varop);
9072 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9073 says that the sign bit can be tested, FOO has mode MODE, C is
9074 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9075 that may be nonzero. */
9076 if (code == LSHIFTRT
9077 && XEXP (varop, 1) == const0_rtx
9078 && GET_MODE (XEXP (varop, 0)) == result_mode
9079 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9080 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9081 && ((STORE_FLAG_VALUE
9082 & ((HOST_WIDE_INT) 1
9083 < (GET_MODE_BITSIZE (result_mode) - 1))))
9084 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9085 && merge_outer_ops (&outer_op, &outer_const, XOR,
9086 (HOST_WIDE_INT) 1, result_mode,
9089 varop = XEXP (varop, 0);
9096 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9097 than the number of bits in the mode is equivalent to A. */
9098 if (code == LSHIFTRT
9099 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9100 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9102 varop = XEXP (varop, 0);
9107 /* NEG commutes with ASHIFT since it is multiplication. Move the
9108 NEG outside to allow shifts to combine. */
9110 && merge_outer_ops (&outer_op, &outer_const, NEG,
9111 (HOST_WIDE_INT) 0, result_mode,
9114 varop = XEXP (varop, 0);
9120 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9121 is one less than the number of bits in the mode is
9122 equivalent to (xor A 1). */
9123 if (code == LSHIFTRT
9124 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9125 && XEXP (varop, 1) == constm1_rtx
9126 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9127 && merge_outer_ops (&outer_op, &outer_const, XOR,
9128 (HOST_WIDE_INT) 1, result_mode,
9132 varop = XEXP (varop, 0);
9136 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9137 that might be nonzero in BAR are those being shifted out and those
9138 bits are known zero in FOO, we can replace the PLUS with FOO.
9139 Similarly in the other operand order. This code occurs when
9140 we are computing the size of a variable-size array. */
9142 if ((code == ASHIFTRT || code == LSHIFTRT)
9143 && count < HOST_BITS_PER_WIDE_INT
9144 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9145 && (nonzero_bits (XEXP (varop, 1), result_mode)
9146 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9148 varop = XEXP (varop, 0);
9151 else if ((code == ASHIFTRT || code == LSHIFTRT)
9152 && count < HOST_BITS_PER_WIDE_INT
9153 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9154 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9156 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9157 & nonzero_bits (XEXP (varop, 1),
9160 varop = XEXP (varop, 1);
9164 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9166 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9167 && (new = simplify_binary_operation (ASHIFT, result_mode,
9169 GEN_INT (count))) != 0
9170 && GET_CODE (new) == CONST_INT
9171 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9172 INTVAL (new), result_mode, &complement_p))
9174 varop = XEXP (varop, 0);
9178 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9179 signbit', and attempt to change the PLUS to an XOR and move it to
9180 the outer operation as is done above in the AND/IOR/XOR case
9181 leg for shift(logical). See details in logical handling above
9182 for reasoning in doing so. */
9183 if (code == LSHIFTRT
9184 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9185 && mode_signbit_p (result_mode, XEXP (varop, 1))
9186 && (new = simplify_binary_operation (code, result_mode,
9188 GEN_INT (count))) != 0
9189 && GET_CODE (new) == CONST_INT
9190 && merge_outer_ops (&outer_op, &outer_const, XOR,
9191 INTVAL (new), result_mode, &complement_p))
9193 varop = XEXP (varop, 0);
9200 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9201 with C the size of VAROP - 1 and the shift is logical if
9202 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9203 we have a (gt X 0) operation. If the shift is arithmetic with
9204 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9205 we have a (neg (gt X 0)) operation. */
9207 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9208 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9209 && count == (unsigned int)
9210 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9211 && (code == LSHIFTRT || code == ASHIFTRT)
9212 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9213 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9215 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9218 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9221 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9222 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9229 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9230 if the truncate does not affect the value. */
9231 if (code == LSHIFTRT
9232 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9233 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9234 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9235 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9236 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9238 rtx varop_inner = XEXP (varop, 0);
9241 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9242 XEXP (varop_inner, 0),
9244 (count + INTVAL (XEXP (varop_inner, 1))));
9245 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9258 /* We need to determine what mode to do the shift in. If the shift is
9259 a right shift or ROTATE, we must always do it in the mode it was
9260 originally done in. Otherwise, we can do it in MODE, the widest mode
9261 encountered. The code we care about is that of the shift that will
9262 actually be done, not the shift that was originally requested. */
9264 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9265 ? result_mode : mode);
9267 /* We have now finished analyzing the shift. The result should be
9268 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9269 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9270 to the result of the shift. OUTER_CONST is the relevant constant,
9271 but we must turn off all bits turned off in the shift.
9273 If we were passed a value for X, see if we can use any pieces of
9274 it. If not, make new rtx. */
9276 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9277 && GET_CODE (XEXP (x, 1)) == CONST_INT
9278 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9279 const_rtx = XEXP (x, 1);
9281 const_rtx = GEN_INT (count);
9283 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9284 && GET_MODE (XEXP (x, 0)) == shift_mode
9285 && SUBREG_REG (XEXP (x, 0)) == varop)
9286 varop = XEXP (x, 0);
9287 else if (GET_MODE (varop) != shift_mode)
9288 varop = gen_lowpart (shift_mode, varop);
9290 /* If we can't make the SUBREG, try to return what we were given. */
9291 if (GET_CODE (varop) == CLOBBER)
9292 return x ? x : varop;
9294 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9298 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9300 /* If we have an outer operation and we just made a shift, it is
9301 possible that we could have simplified the shift were it not
9302 for the outer operation. So try to do the simplification
9305 if (outer_op != UNKNOWN && GET_CODE (x) == code
9306 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9307 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9308 INTVAL (XEXP (x, 1)));
9310 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9311 turn off all the bits that the shift would have turned off. */
9312 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9313 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9314 GET_MODE_MASK (result_mode) >> orig_count);
9316 /* Do the remainder of the processing in RESULT_MODE. */
9317 x = gen_lowpart (result_mode, x);
9319 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9322 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9324 if (outer_op != UNKNOWN)
9326 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9327 outer_const = trunc_int_for_mode (outer_const, result_mode);
9329 if (outer_op == AND)
9330 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9331 else if (outer_op == SET)
9332 /* This means that we have determined that the result is
9333 equivalent to a constant. This should be rare. */
9334 x = GEN_INT (outer_const);
9335 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9336 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9338 x = simplify_gen_binary (outer_op, result_mode, x,
9339 GEN_INT (outer_const));
9345 /* Like recog, but we receive the address of a pointer to a new pattern.
9346 We try to match the rtx that the pointer points to.
9347 If that fails, we may try to modify or replace the pattern,
9348 storing the replacement into the same pointer object.
9350 Modifications include deletion or addition of CLOBBERs.
9352 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9353 the CLOBBERs are placed.
9355 The value is the final insn code from the pattern ultimately matched,
9359 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9362 int insn_code_number;
9363 int num_clobbers_to_add = 0;
9366 rtx old_notes, old_pat;
9368 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9369 we use to indicate that something didn't match. If we find such a
9370 thing, force rejection. */
9371 if (GET_CODE (pat) == PARALLEL)
9372 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9373 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9374 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9377 old_pat = PATTERN (insn);
9378 old_notes = REG_NOTES (insn);
9379 PATTERN (insn) = pat;
9380 REG_NOTES (insn) = 0;
9382 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9384 /* If it isn't, there is the possibility that we previously had an insn
9385 that clobbered some register as a side effect, but the combined
9386 insn doesn't need to do that. So try once more without the clobbers
9387 unless this represents an ASM insn. */
9389 if (insn_code_number < 0 && ! check_asm_operands (pat)
9390 && GET_CODE (pat) == PARALLEL)
9394 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9395 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9398 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9402 SUBST_INT (XVECLEN (pat, 0), pos);
9405 pat = XVECEXP (pat, 0, 0);
9407 PATTERN (insn) = pat;
9408 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9410 PATTERN (insn) = old_pat;
9411 REG_NOTES (insn) = old_notes;
9413 /* Recognize all noop sets, these will be killed by followup pass. */
9414 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9415 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9417 /* If we had any clobbers to add, make a new pattern than contains
9418 them. Then check to make sure that all of them are dead. */
9419 if (num_clobbers_to_add)
9421 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9422 rtvec_alloc (GET_CODE (pat) == PARALLEL
9424 + num_clobbers_to_add)
9425 : num_clobbers_to_add + 1));
9427 if (GET_CODE (pat) == PARALLEL)
9428 for (i = 0; i < XVECLEN (pat, 0); i++)
9429 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9431 XVECEXP (newpat, 0, 0) = pat;
9433 add_clobbers (newpat, insn_code_number);
9435 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9436 i < XVECLEN (newpat, 0); i++)
9438 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9439 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9441 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9442 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9450 return insn_code_number;
9453 /* Like gen_lowpart_general but for use by combine. In combine it
9454 is not possible to create any new pseudoregs. However, it is
9455 safe to create invalid memory addresses, because combine will
9456 try to recognize them and all they will do is make the combine
9459 If for some reason this cannot do its job, an rtx
9460 (clobber (const_int 0)) is returned.
9461 An insn containing that will not be recognized. */
9464 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9466 enum machine_mode imode = GET_MODE (x);
9467 unsigned int osize = GET_MODE_SIZE (omode);
9468 unsigned int isize = GET_MODE_SIZE (imode);
9474 /* Return identity if this is a CONST or symbolic reference. */
9476 && (GET_CODE (x) == CONST
9477 || GET_CODE (x) == SYMBOL_REF
9478 || GET_CODE (x) == LABEL_REF))
9481 /* We can only support MODE being wider than a word if X is a
9482 constant integer or has a mode the same size. */
9483 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9484 && ! ((imode == VOIDmode
9485 && (GET_CODE (x) == CONST_INT
9486 || GET_CODE (x) == CONST_DOUBLE))
9490 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9491 won't know what to do. So we will strip off the SUBREG here and
9492 process normally. */
9493 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9497 /* For use in case we fall down into the address adjustments
9498 further below, we need to adjust the known mode and size of
9499 x; imode and isize, since we just adjusted x. */
9500 imode = GET_MODE (x);
9505 isize = GET_MODE_SIZE (imode);
9508 result = gen_lowpart_common (omode, x);
9510 #ifdef CANNOT_CHANGE_MODE_CLASS
9511 if (result != 0 && GET_CODE (result) == SUBREG)
9512 record_subregs_of_mode (result);
9522 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9524 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9527 /* If we want to refer to something bigger than the original memref,
9528 generate a paradoxical subreg instead. That will force a reload
9529 of the original memref X. */
9531 return gen_rtx_SUBREG (omode, x, 0);
9533 if (WORDS_BIG_ENDIAN)
9534 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9536 /* Adjust the address so that the address-after-the-data is
9538 if (BYTES_BIG_ENDIAN)
9539 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9541 return adjust_address_nv (x, omode, offset);
9544 /* If X is a comparison operator, rewrite it in a new mode. This
9545 probably won't match, but may allow further simplifications. */
9546 else if (COMPARISON_P (x))
9547 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9549 /* If we couldn't simplify X any other way, just enclose it in a
9550 SUBREG. Normally, this SUBREG won't match, but some patterns may
9551 include an explicit SUBREG or we may simplify it further in combine. */
9557 offset = subreg_lowpart_offset (omode, imode);
9558 if (imode == VOIDmode)
9560 imode = int_mode_for_mode (omode);
9561 x = gen_lowpart_common (imode, x);
9565 res = simplify_gen_subreg (omode, x, imode, offset);
9571 return gen_rtx_CLOBBER (imode, const0_rtx);
9574 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9575 comparison code that will be tested.
9577 The result is a possibly different comparison code to use. *POP0 and
9578 *POP1 may be updated.
9580 It is possible that we might detect that a comparison is either always
9581 true or always false. However, we do not perform general constant
9582 folding in combine, so this knowledge isn't useful. Such tautologies
9583 should have been detected earlier. Hence we ignore all such cases. */
9585 static enum rtx_code
9586 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9592 enum machine_mode mode, tmode;
9594 /* Try a few ways of applying the same transformation to both operands. */
9597 #ifndef WORD_REGISTER_OPERATIONS
9598 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9599 so check specially. */
9600 if (code != GTU && code != GEU && code != LTU && code != LEU
9601 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9602 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9603 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9604 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9605 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9606 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9607 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9608 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9609 && XEXP (op0, 1) == XEXP (op1, 1)
9610 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9611 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9612 && (INTVAL (XEXP (op0, 1))
9613 == (GET_MODE_BITSIZE (GET_MODE (op0))
9615 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9617 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9618 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9622 /* If both operands are the same constant shift, see if we can ignore the
9623 shift. We can if the shift is a rotate or if the bits shifted out of
9624 this shift are known to be zero for both inputs and if the type of
9625 comparison is compatible with the shift. */
9626 if (GET_CODE (op0) == GET_CODE (op1)
9627 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9628 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9629 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9630 && (code != GT && code != LT && code != GE && code != LE))
9631 || (GET_CODE (op0) == ASHIFTRT
9632 && (code != GTU && code != LTU
9633 && code != GEU && code != LEU)))
9634 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9635 && INTVAL (XEXP (op0, 1)) >= 0
9636 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9637 && XEXP (op0, 1) == XEXP (op1, 1))
9639 enum machine_mode mode = GET_MODE (op0);
9640 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9641 int shift_count = INTVAL (XEXP (op0, 1));
9643 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9644 mask &= (mask >> shift_count) << shift_count;
9645 else if (GET_CODE (op0) == ASHIFT)
9646 mask = (mask & (mask << shift_count)) >> shift_count;
9648 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9649 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9650 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9655 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9656 SUBREGs are of the same mode, and, in both cases, the AND would
9657 be redundant if the comparison was done in the narrower mode,
9658 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9659 and the operand's possibly nonzero bits are 0xffffff01; in that case
9660 if we only care about QImode, we don't need the AND). This case
9661 occurs if the output mode of an scc insn is not SImode and
9662 STORE_FLAG_VALUE == 1 (e.g., the 386).
9664 Similarly, check for a case where the AND's are ZERO_EXTEND
9665 operations from some narrower mode even though a SUBREG is not
9668 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9669 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9670 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9672 rtx inner_op0 = XEXP (op0, 0);
9673 rtx inner_op1 = XEXP (op1, 0);
9674 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9675 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9678 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9679 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9680 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9681 && (GET_MODE (SUBREG_REG (inner_op0))
9682 == GET_MODE (SUBREG_REG (inner_op1)))
9683 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9684 <= HOST_BITS_PER_WIDE_INT)
9685 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9686 GET_MODE (SUBREG_REG (inner_op0)))))
9687 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9688 GET_MODE (SUBREG_REG (inner_op1))))))
9690 op0 = SUBREG_REG (inner_op0);
9691 op1 = SUBREG_REG (inner_op1);
9693 /* The resulting comparison is always unsigned since we masked
9694 off the original sign bit. */
9695 code = unsigned_condition (code);
9701 for (tmode = GET_CLASS_NARROWEST_MODE
9702 (GET_MODE_CLASS (GET_MODE (op0)));
9703 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9704 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9706 op0 = gen_lowpart (tmode, inner_op0);
9707 op1 = gen_lowpart (tmode, inner_op1);
9708 code = unsigned_condition (code);
9717 /* If both operands are NOT, we can strip off the outer operation
9718 and adjust the comparison code for swapped operands; similarly for
9719 NEG, except that this must be an equality comparison. */
9720 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9721 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9722 && (code == EQ || code == NE)))
9723 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9729 /* If the first operand is a constant, swap the operands and adjust the
9730 comparison code appropriately, but don't do this if the second operand
9731 is already a constant integer. */
9732 if (swap_commutative_operands_p (op0, op1))
9734 tem = op0, op0 = op1, op1 = tem;
9735 code = swap_condition (code);
9738 /* We now enter a loop during which we will try to simplify the comparison.
9739 For the most part, we only are concerned with comparisons with zero,
9740 but some things may really be comparisons with zero but not start
9741 out looking that way. */
9743 while (GET_CODE (op1) == CONST_INT)
9745 enum machine_mode mode = GET_MODE (op0);
9746 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9747 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9748 int equality_comparison_p;
9749 int sign_bit_comparison_p;
9750 int unsigned_comparison_p;
9751 HOST_WIDE_INT const_op;
9753 /* We only want to handle integral modes. This catches VOIDmode,
9754 CCmode, and the floating-point modes. An exception is that we
9755 can handle VOIDmode if OP0 is a COMPARE or a comparison
9758 if (GET_MODE_CLASS (mode) != MODE_INT
9759 && ! (mode == VOIDmode
9760 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9763 /* Get the constant we are comparing against and turn off all bits
9764 not on in our mode. */
9765 const_op = INTVAL (op1);
9766 if (mode != VOIDmode)
9767 const_op = trunc_int_for_mode (const_op, mode);
9768 op1 = GEN_INT (const_op);
9770 /* If we are comparing against a constant power of two and the value
9771 being compared can only have that single bit nonzero (e.g., it was
9772 `and'ed with that bit), we can replace this with a comparison
9775 && (code == EQ || code == NE || code == GE || code == GEU
9776 || code == LT || code == LTU)
9777 && mode_width <= HOST_BITS_PER_WIDE_INT
9778 && exact_log2 (const_op) >= 0
9779 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9781 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9782 op1 = const0_rtx, const_op = 0;
9785 /* Similarly, if we are comparing a value known to be either -1 or
9786 0 with -1, change it to the opposite comparison against zero. */
9789 && (code == EQ || code == NE || code == GT || code == LE
9790 || code == GEU || code == LTU)
9791 && num_sign_bit_copies (op0, mode) == mode_width)
9793 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9794 op1 = const0_rtx, const_op = 0;
9797 /* Do some canonicalizations based on the comparison code. We prefer
9798 comparisons against zero and then prefer equality comparisons.
9799 If we can reduce the size of a constant, we will do that too. */
9804 /* < C is equivalent to <= (C - 1) */
9808 op1 = GEN_INT (const_op);
9810 /* ... fall through to LE case below. */
9816 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9820 op1 = GEN_INT (const_op);
9824 /* If we are doing a <= 0 comparison on a value known to have
9825 a zero sign bit, we can replace this with == 0. */
9826 else if (const_op == 0
9827 && mode_width <= HOST_BITS_PER_WIDE_INT
9828 && (nonzero_bits (op0, mode)
9829 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9834 /* >= C is equivalent to > (C - 1). */
9838 op1 = GEN_INT (const_op);
9840 /* ... fall through to GT below. */
9846 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9850 op1 = GEN_INT (const_op);
9854 /* If we are doing a > 0 comparison on a value known to have
9855 a zero sign bit, we can replace this with != 0. */
9856 else if (const_op == 0
9857 && mode_width <= HOST_BITS_PER_WIDE_INT
9858 && (nonzero_bits (op0, mode)
9859 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9864 /* < C is equivalent to <= (C - 1). */
9868 op1 = GEN_INT (const_op);
9870 /* ... fall through ... */
9873 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9874 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9875 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9877 const_op = 0, op1 = const0_rtx;
9885 /* unsigned <= 0 is equivalent to == 0 */
9889 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9890 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9891 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9893 const_op = 0, op1 = const0_rtx;
9899 /* >= C is equivalent to > (C - 1). */
9903 op1 = GEN_INT (const_op);
9905 /* ... fall through ... */
9908 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9909 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9910 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9912 const_op = 0, op1 = const0_rtx;
9920 /* unsigned > 0 is equivalent to != 0 */
9924 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9925 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9926 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9928 const_op = 0, op1 = const0_rtx;
9937 /* Compute some predicates to simplify code below. */
9939 equality_comparison_p = (code == EQ || code == NE);
9940 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9941 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9944 /* If this is a sign bit comparison and we can do arithmetic in
9945 MODE, say that we will only be needing the sign bit of OP0. */
9946 if (sign_bit_comparison_p
9947 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9948 op0 = force_to_mode (op0, mode,
9950 << (GET_MODE_BITSIZE (mode) - 1)),
9953 /* Now try cases based on the opcode of OP0. If none of the cases
9954 does a "continue", we exit this loop immediately after the
9957 switch (GET_CODE (op0))
9960 /* If we are extracting a single bit from a variable position in
9961 a constant that has only a single bit set and are comparing it
9962 with zero, we can convert this into an equality comparison
9963 between the position and the location of the single bit. */
9964 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9965 have already reduced the shift count modulo the word size. */
9966 if (!SHIFT_COUNT_TRUNCATED
9967 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9968 && XEXP (op0, 1) == const1_rtx
9969 && equality_comparison_p && const_op == 0
9970 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9972 if (BITS_BIG_ENDIAN)
9974 enum machine_mode new_mode
9975 = mode_for_extraction (EP_extzv, 1);
9976 if (new_mode == MAX_MACHINE_MODE)
9977 i = BITS_PER_WORD - 1 - i;
9981 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9985 op0 = XEXP (op0, 2);
9989 /* Result is nonzero iff shift count is equal to I. */
9990 code = reverse_condition (code);
9994 /* ... fall through ... */
9997 tem = expand_compound_operation (op0);
10006 /* If testing for equality, we can take the NOT of the constant. */
10007 if (equality_comparison_p
10008 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10010 op0 = XEXP (op0, 0);
10015 /* If just looking at the sign bit, reverse the sense of the
10017 if (sign_bit_comparison_p)
10019 op0 = XEXP (op0, 0);
10020 code = (code == GE ? LT : GE);
10026 /* If testing for equality, we can take the NEG of the constant. */
10027 if (equality_comparison_p
10028 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10030 op0 = XEXP (op0, 0);
10035 /* The remaining cases only apply to comparisons with zero. */
10039 /* When X is ABS or is known positive,
10040 (neg X) is < 0 if and only if X != 0. */
10042 if (sign_bit_comparison_p
10043 && (GET_CODE (XEXP (op0, 0)) == ABS
10044 || (mode_width <= HOST_BITS_PER_WIDE_INT
10045 && (nonzero_bits (XEXP (op0, 0), mode)
10046 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10048 op0 = XEXP (op0, 0);
10049 code = (code == LT ? NE : EQ);
10053 /* If we have NEG of something whose two high-order bits are the
10054 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10055 if (num_sign_bit_copies (op0, mode) >= 2)
10057 op0 = XEXP (op0, 0);
10058 code = swap_condition (code);
10064 /* If we are testing equality and our count is a constant, we
10065 can perform the inverse operation on our RHS. */
10066 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10067 && (tem = simplify_binary_operation (ROTATERT, mode,
10068 op1, XEXP (op0, 1))) != 0)
10070 op0 = XEXP (op0, 0);
10075 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10076 a particular bit. Convert it to an AND of a constant of that
10077 bit. This will be converted into a ZERO_EXTRACT. */
10078 if (const_op == 0 && sign_bit_comparison_p
10079 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10080 && mode_width <= HOST_BITS_PER_WIDE_INT)
10082 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10085 - INTVAL (XEXP (op0, 1)))));
10086 code = (code == LT ? NE : EQ);
10090 /* Fall through. */
10093 /* ABS is ignorable inside an equality comparison with zero. */
10094 if (const_op == 0 && equality_comparison_p)
10096 op0 = XEXP (op0, 0);
10102 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10103 (compare FOO CONST) if CONST fits in FOO's mode and we
10104 are either testing inequality or have an unsigned
10105 comparison with ZERO_EXTEND or a signed comparison with
10106 SIGN_EXTEND. But don't do it if we don't have a compare
10107 insn of the given mode, since we'd have to revert it
10108 later on, and then we wouldn't know whether to sign- or
10110 mode = GET_MODE (XEXP (op0, 0));
10111 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10112 && ! unsigned_comparison_p
10113 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10114 && ((unsigned HOST_WIDE_INT) const_op
10115 < (((unsigned HOST_WIDE_INT) 1
10116 << (GET_MODE_BITSIZE (mode) - 1))))
10117 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10119 op0 = XEXP (op0, 0);
10125 /* Check for the case where we are comparing A - C1 with C2, that is
10127 (subreg:MODE (plus (A) (-C1))) op (C2)
10129 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10130 comparison in the wider mode. One of the following two conditions
10131 must be true in order for this to be valid:
10133 1. The mode extension results in the same bit pattern being added
10134 on both sides and the comparison is equality or unsigned. As
10135 C2 has been truncated to fit in MODE, the pattern can only be
10138 2. The mode extension results in the sign bit being copied on
10141 The difficulty here is that we have predicates for A but not for
10142 (A - C1) so we need to check that C1 is within proper bounds so
10143 as to perturbate A as little as possible. */
10145 if (mode_width <= HOST_BITS_PER_WIDE_INT
10146 && subreg_lowpart_p (op0)
10147 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10148 && GET_CODE (SUBREG_REG (op0)) == PLUS
10149 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10151 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10152 rtx a = XEXP (SUBREG_REG (op0), 0);
10153 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10156 && (unsigned HOST_WIDE_INT) c1
10157 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10158 && (equality_comparison_p || unsigned_comparison_p)
10159 /* (A - C1) zero-extends if it is positive and sign-extends
10160 if it is negative, C2 both zero- and sign-extends. */
10161 && ((0 == (nonzero_bits (a, inner_mode)
10162 & ~GET_MODE_MASK (mode))
10164 /* (A - C1) sign-extends if it is positive and 1-extends
10165 if it is negative, C2 both sign- and 1-extends. */
10166 || (num_sign_bit_copies (a, inner_mode)
10167 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10170 || ((unsigned HOST_WIDE_INT) c1
10171 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10172 /* (A - C1) always sign-extends, like C2. */
10173 && num_sign_bit_copies (a, inner_mode)
10174 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10175 - mode_width - 1)))
10177 op0 = SUBREG_REG (op0);
10182 /* If the inner mode is narrower and we are extracting the low part,
10183 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10184 if (subreg_lowpart_p (op0)
10185 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10186 /* Fall through */ ;
10190 /* ... fall through ... */
10193 mode = GET_MODE (XEXP (op0, 0));
10194 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10195 && (unsigned_comparison_p || equality_comparison_p)
10196 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10197 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10198 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10200 op0 = XEXP (op0, 0);
10206 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10207 this for equality comparisons due to pathological cases involving
10209 if (equality_comparison_p
10210 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10211 op1, XEXP (op0, 1))))
10213 op0 = XEXP (op0, 0);
10218 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10219 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10220 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10222 op0 = XEXP (XEXP (op0, 0), 0);
10223 code = (code == LT ? EQ : NE);
10229 /* We used to optimize signed comparisons against zero, but that
10230 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10231 arrive here as equality comparisons, or (GEU, LTU) are
10232 optimized away. No need to special-case them. */
10234 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10235 (eq B (minus A C)), whichever simplifies. We can only do
10236 this for equality comparisons due to pathological cases involving
10238 if (equality_comparison_p
10239 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10240 XEXP (op0, 1), op1)))
10242 op0 = XEXP (op0, 0);
10247 if (equality_comparison_p
10248 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10249 XEXP (op0, 0), op1)))
10251 op0 = XEXP (op0, 1);
10256 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10257 of bits in X minus 1, is one iff X > 0. */
10258 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10259 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10260 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10262 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10264 op0 = XEXP (op0, 1);
10265 code = (code == GE ? LE : GT);
10271 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10272 if C is zero or B is a constant. */
10273 if (equality_comparison_p
10274 && 0 != (tem = simplify_binary_operation (XOR, mode,
10275 XEXP (op0, 1), op1)))
10277 op0 = XEXP (op0, 0);
10284 case UNEQ: case LTGT:
10285 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10286 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10287 case UNORDERED: case ORDERED:
10288 /* We can't do anything if OP0 is a condition code value, rather
10289 than an actual data value. */
10291 || CC0_P (XEXP (op0, 0))
10292 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10295 /* Get the two operands being compared. */
10296 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10297 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10299 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10301 /* Check for the cases where we simply want the result of the
10302 earlier test or the opposite of that result. */
10303 if (code == NE || code == EQ
10304 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10305 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10306 && (STORE_FLAG_VALUE
10307 & (((HOST_WIDE_INT) 1
10308 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10309 && (code == LT || code == GE)))
10311 enum rtx_code new_code;
10312 if (code == LT || code == NE)
10313 new_code = GET_CODE (op0);
10315 new_code = reversed_comparison_code (op0, NULL);
10317 if (new_code != UNKNOWN)
10328 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10330 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10331 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10332 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10334 op0 = XEXP (op0, 1);
10335 code = (code == GE ? GT : LE);
10341 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10342 will be converted to a ZERO_EXTRACT later. */
10343 if (const_op == 0 && equality_comparison_p
10344 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10345 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10347 op0 = simplify_and_const_int
10348 (op0, mode, gen_rtx_LSHIFTRT (mode,
10350 XEXP (XEXP (op0, 0), 1)),
10351 (HOST_WIDE_INT) 1);
10355 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10356 zero and X is a comparison and C1 and C2 describe only bits set
10357 in STORE_FLAG_VALUE, we can compare with X. */
10358 if (const_op == 0 && equality_comparison_p
10359 && mode_width <= HOST_BITS_PER_WIDE_INT
10360 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10361 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10362 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10363 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10364 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10366 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10367 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10368 if ((~STORE_FLAG_VALUE & mask) == 0
10369 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10370 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10371 && COMPARISON_P (tem))))
10373 op0 = XEXP (XEXP (op0, 0), 0);
10378 /* If we are doing an equality comparison of an AND of a bit equal
10379 to the sign bit, replace this with a LT or GE comparison of
10380 the underlying value. */
10381 if (equality_comparison_p
10383 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10384 && mode_width <= HOST_BITS_PER_WIDE_INT
10385 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10386 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10388 op0 = XEXP (op0, 0);
10389 code = (code == EQ ? GE : LT);
10393 /* If this AND operation is really a ZERO_EXTEND from a narrower
10394 mode, the constant fits within that mode, and this is either an
10395 equality or unsigned comparison, try to do this comparison in
10396 the narrower mode. */
10397 if ((equality_comparison_p || unsigned_comparison_p)
10398 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10399 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10400 & GET_MODE_MASK (mode))
10402 && const_op >> i == 0
10403 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10405 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10409 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10410 fits in both M1 and M2 and the SUBREG is either paradoxical
10411 or represents the low part, permute the SUBREG and the AND
10413 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10415 unsigned HOST_WIDE_INT c1;
10416 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10417 /* Require an integral mode, to avoid creating something like
10419 if (SCALAR_INT_MODE_P (tmode)
10420 /* It is unsafe to commute the AND into the SUBREG if the
10421 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10422 not defined. As originally written the upper bits
10423 have a defined value due to the AND operation.
10424 However, if we commute the AND inside the SUBREG then
10425 they no longer have defined values and the meaning of
10426 the code has been changed. */
10428 #ifdef WORD_REGISTER_OPERATIONS
10429 || (mode_width > GET_MODE_BITSIZE (tmode)
10430 && mode_width <= BITS_PER_WORD)
10432 || (mode_width <= GET_MODE_BITSIZE (tmode)
10433 && subreg_lowpart_p (XEXP (op0, 0))))
10434 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10435 && mode_width <= HOST_BITS_PER_WIDE_INT
10436 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10437 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10438 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10440 && c1 != GET_MODE_MASK (tmode))
10442 op0 = simplify_gen_binary (AND, tmode,
10443 SUBREG_REG (XEXP (op0, 0)),
10444 gen_int_mode (c1, tmode));
10445 op0 = gen_lowpart (mode, op0);
10450 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10451 if (const_op == 0 && equality_comparison_p
10452 && XEXP (op0, 1) == const1_rtx
10453 && GET_CODE (XEXP (op0, 0)) == NOT)
10455 op0 = simplify_and_const_int
10456 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10457 code = (code == NE ? EQ : NE);
10461 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10462 (eq (and (lshiftrt X) 1) 0).
10463 Also handle the case where (not X) is expressed using xor. */
10464 if (const_op == 0 && equality_comparison_p
10465 && XEXP (op0, 1) == const1_rtx
10466 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10468 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10469 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10471 if (GET_CODE (shift_op) == NOT
10472 || (GET_CODE (shift_op) == XOR
10473 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10474 && GET_CODE (shift_count) == CONST_INT
10475 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10476 && (INTVAL (XEXP (shift_op, 1))
10477 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10479 op0 = simplify_and_const_int
10481 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10482 (HOST_WIDE_INT) 1);
10483 code = (code == NE ? EQ : NE);
10490 /* If we have (compare (ashift FOO N) (const_int C)) and
10491 the high order N bits of FOO (N+1 if an inequality comparison)
10492 are known to be zero, we can do this by comparing FOO with C
10493 shifted right N bits so long as the low-order N bits of C are
10495 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10496 && INTVAL (XEXP (op0, 1)) >= 0
10497 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10498 < HOST_BITS_PER_WIDE_INT)
10500 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10501 && mode_width <= HOST_BITS_PER_WIDE_INT
10502 && (nonzero_bits (XEXP (op0, 0), mode)
10503 & ~(mask >> (INTVAL (XEXP (op0, 1))
10504 + ! equality_comparison_p))) == 0)
10506 /* We must perform a logical shift, not an arithmetic one,
10507 as we want the top N bits of C to be zero. */
10508 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10510 temp >>= INTVAL (XEXP (op0, 1));
10511 op1 = gen_int_mode (temp, mode);
10512 op0 = XEXP (op0, 0);
10516 /* If we are doing a sign bit comparison, it means we are testing
10517 a particular bit. Convert it to the appropriate AND. */
10518 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10519 && mode_width <= HOST_BITS_PER_WIDE_INT)
10521 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10524 - INTVAL (XEXP (op0, 1)))));
10525 code = (code == LT ? NE : EQ);
10529 /* If this an equality comparison with zero and we are shifting
10530 the low bit to the sign bit, we can convert this to an AND of the
10532 if (const_op == 0 && equality_comparison_p
10533 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10534 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10537 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10538 (HOST_WIDE_INT) 1);
10544 /* If this is an equality comparison with zero, we can do this
10545 as a logical shift, which might be much simpler. */
10546 if (equality_comparison_p && const_op == 0
10547 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10549 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10551 INTVAL (XEXP (op0, 1)));
10555 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10556 do the comparison in a narrower mode. */
10557 if (! unsigned_comparison_p
10558 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10559 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10560 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10561 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10562 MODE_INT, 1)) != BLKmode
10563 && (((unsigned HOST_WIDE_INT) const_op
10564 + (GET_MODE_MASK (tmode) >> 1) + 1)
10565 <= GET_MODE_MASK (tmode)))
10567 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10571 /* Likewise if OP0 is a PLUS of a sign extension with a
10572 constant, which is usually represented with the PLUS
10573 between the shifts. */
10574 if (! unsigned_comparison_p
10575 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10576 && GET_CODE (XEXP (op0, 0)) == PLUS
10577 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10578 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10579 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10580 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10581 MODE_INT, 1)) != BLKmode
10582 && (((unsigned HOST_WIDE_INT) const_op
10583 + (GET_MODE_MASK (tmode) >> 1) + 1)
10584 <= GET_MODE_MASK (tmode)))
10586 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10587 rtx add_const = XEXP (XEXP (op0, 0), 1);
10588 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10589 add_const, XEXP (op0, 1));
10591 op0 = simplify_gen_binary (PLUS, tmode,
10592 gen_lowpart (tmode, inner),
10597 /* ... fall through ... */
10599 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10600 the low order N bits of FOO are known to be zero, we can do this
10601 by comparing FOO with C shifted left N bits so long as no
10602 overflow occurs. */
10603 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10604 && INTVAL (XEXP (op0, 1)) >= 0
10605 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10606 && mode_width <= HOST_BITS_PER_WIDE_INT
10607 && (nonzero_bits (XEXP (op0, 0), mode)
10608 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10609 && (((unsigned HOST_WIDE_INT) const_op
10610 + (GET_CODE (op0) != LSHIFTRT
10611 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10614 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10616 /* If the shift was logical, then we must make the condition
10618 if (GET_CODE (op0) == LSHIFTRT)
10619 code = unsigned_condition (code);
10621 const_op <<= INTVAL (XEXP (op0, 1));
10622 op1 = GEN_INT (const_op);
10623 op0 = XEXP (op0, 0);
10627 /* If we are using this shift to extract just the sign bit, we
10628 can replace this with an LT or GE comparison. */
10630 && (equality_comparison_p || sign_bit_comparison_p)
10631 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10632 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10635 op0 = XEXP (op0, 0);
10636 code = (code == NE || code == GT ? LT : GE);
10648 /* Now make any compound operations involved in this comparison. Then,
10649 check for an outmost SUBREG on OP0 that is not doing anything or is
10650 paradoxical. The latter transformation must only be performed when
10651 it is known that the "extra" bits will be the same in op0 and op1 or
10652 that they don't matter. There are three cases to consider:
10654 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10655 care bits and we can assume they have any convenient value. So
10656 making the transformation is safe.
10658 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10659 In this case the upper bits of op0 are undefined. We should not make
10660 the simplification in that case as we do not know the contents of
10663 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10664 UNKNOWN. In that case we know those bits are zeros or ones. We must
10665 also be sure that they are the same as the upper bits of op1.
10667 We can never remove a SUBREG for a non-equality comparison because
10668 the sign bit is in a different place in the underlying object. */
10670 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10671 op1 = make_compound_operation (op1, SET);
10673 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10674 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10675 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10676 && (code == NE || code == EQ))
10678 if (GET_MODE_SIZE (GET_MODE (op0))
10679 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10681 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10683 if (REG_P (SUBREG_REG (op0)))
10685 op0 = SUBREG_REG (op0);
10686 op1 = gen_lowpart (GET_MODE (op0), op1);
10689 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10690 <= HOST_BITS_PER_WIDE_INT)
10691 && (nonzero_bits (SUBREG_REG (op0),
10692 GET_MODE (SUBREG_REG (op0)))
10693 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10695 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10697 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10698 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10699 op0 = SUBREG_REG (op0), op1 = tem;
10703 /* We now do the opposite procedure: Some machines don't have compare
10704 insns in all modes. If OP0's mode is an integer mode smaller than a
10705 word and we can't do a compare in that mode, see if there is a larger
10706 mode for which we can do the compare. There are a number of cases in
10707 which we can use the wider mode. */
10709 mode = GET_MODE (op0);
10710 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10711 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10712 && ! have_insn_for (COMPARE, mode))
10713 for (tmode = GET_MODE_WIDER_MODE (mode);
10715 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10716 tmode = GET_MODE_WIDER_MODE (tmode))
10717 if (have_insn_for (COMPARE, tmode))
10721 /* If the only nonzero bits in OP0 and OP1 are those in the
10722 narrower mode and this is an equality or unsigned comparison,
10723 we can use the wider mode. Similarly for sign-extended
10724 values, in which case it is true for all comparisons. */
10725 zero_extended = ((code == EQ || code == NE
10726 || code == GEU || code == GTU
10727 || code == LEU || code == LTU)
10728 && (nonzero_bits (op0, tmode)
10729 & ~GET_MODE_MASK (mode)) == 0
10730 && ((GET_CODE (op1) == CONST_INT
10731 || (nonzero_bits (op1, tmode)
10732 & ~GET_MODE_MASK (mode)) == 0)));
10735 || ((num_sign_bit_copies (op0, tmode)
10736 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10737 - GET_MODE_BITSIZE (mode)))
10738 && (num_sign_bit_copies (op1, tmode)
10739 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10740 - GET_MODE_BITSIZE (mode)))))
10742 /* If OP0 is an AND and we don't have an AND in MODE either,
10743 make a new AND in the proper mode. */
10744 if (GET_CODE (op0) == AND
10745 && !have_insn_for (AND, mode))
10746 op0 = simplify_gen_binary (AND, tmode,
10747 gen_lowpart (tmode,
10749 gen_lowpart (tmode,
10752 op0 = gen_lowpart (tmode, op0);
10753 if (zero_extended && GET_CODE (op1) == CONST_INT)
10754 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10755 op1 = gen_lowpart (tmode, op1);
10759 /* If this is a test for negative, we can make an explicit
10760 test of the sign bit. */
10762 if (op1 == const0_rtx && (code == LT || code == GE)
10763 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10765 op0 = simplify_gen_binary (AND, tmode,
10766 gen_lowpart (tmode, op0),
10767 GEN_INT ((HOST_WIDE_INT) 1
10768 << (GET_MODE_BITSIZE (mode)
10770 code = (code == LT) ? NE : EQ;
10775 #ifdef CANONICALIZE_COMPARISON
10776 /* If this machine only supports a subset of valid comparisons, see if we
10777 can convert an unsupported one into a supported one. */
10778 CANONICALIZE_COMPARISON (code, op0, op1);
10787 /* Utility function for record_value_for_reg. Count number of
10792 enum rtx_code code = GET_CODE (x);
10796 if (GET_RTX_CLASS (code) == '2'
10797 || GET_RTX_CLASS (code) == 'c')
10799 rtx x0 = XEXP (x, 0);
10800 rtx x1 = XEXP (x, 1);
10803 return 1 + 2 * count_rtxs (x0);
10805 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10806 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10807 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10808 return 2 + 2 * count_rtxs (x0)
10809 + count_rtxs (x == XEXP (x1, 0)
10810 ? XEXP (x1, 1) : XEXP (x1, 0));
10812 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10813 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10814 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10815 return 2 + 2 * count_rtxs (x1)
10816 + count_rtxs (x == XEXP (x0, 0)
10817 ? XEXP (x0, 1) : XEXP (x0, 0));
10820 fmt = GET_RTX_FORMAT (code);
10821 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10823 ret += count_rtxs (XEXP (x, i));
10828 /* Utility function for following routine. Called when X is part of a value
10829 being stored into last_set_value. Sets last_set_table_tick
10830 for each register mentioned. Similar to mention_regs in cse.c */
10833 update_table_tick (rtx x)
10835 enum rtx_code code = GET_CODE (x);
10836 const char *fmt = GET_RTX_FORMAT (code);
10841 unsigned int regno = REGNO (x);
10842 unsigned int endregno
10843 = regno + (regno < FIRST_PSEUDO_REGISTER
10844 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10847 for (r = regno; r < endregno; r++)
10848 reg_stat[r].last_set_table_tick = label_tick;
10853 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10854 /* Note that we can't have an "E" in values stored; see
10855 get_last_value_validate. */
10858 /* Check for identical subexpressions. If x contains
10859 identical subexpression we only have to traverse one of
10861 if (i == 0 && ARITHMETIC_P (x))
10863 /* Note that at this point x1 has already been
10865 rtx x0 = XEXP (x, 0);
10866 rtx x1 = XEXP (x, 1);
10868 /* If x0 and x1 are identical then there is no need to
10873 /* If x0 is identical to a subexpression of x1 then while
10874 processing x1, x0 has already been processed. Thus we
10875 are done with x. */
10876 if (ARITHMETIC_P (x1)
10877 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10880 /* If x1 is identical to a subexpression of x0 then we
10881 still have to process the rest of x0. */
10882 if (ARITHMETIC_P (x0)
10883 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10885 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10890 update_table_tick (XEXP (x, i));
10894 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10895 are saying that the register is clobbered and we no longer know its
10896 value. If INSN is zero, don't update reg_stat[].last_set; this is
10897 only permitted with VALUE also zero and is used to invalidate the
10901 record_value_for_reg (rtx reg, rtx insn, rtx value)
10903 unsigned int regno = REGNO (reg);
10904 unsigned int endregno
10905 = regno + (regno < FIRST_PSEUDO_REGISTER
10906 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10909 /* If VALUE contains REG and we have a previous value for REG, substitute
10910 the previous value. */
10911 if (value && insn && reg_overlap_mentioned_p (reg, value))
10915 /* Set things up so get_last_value is allowed to see anything set up to
10917 subst_low_cuid = INSN_CUID (insn);
10918 tem = get_last_value (reg);
10920 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10921 it isn't going to be useful and will take a lot of time to process,
10922 so just use the CLOBBER. */
10926 if (ARITHMETIC_P (tem)
10927 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10928 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10929 tem = XEXP (tem, 0);
10930 else if (count_occurrences (value, reg, 1) >= 2)
10932 /* If there are two or more occurrences of REG in VALUE,
10933 prevent the value from growing too much. */
10934 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10935 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10938 value = replace_rtx (copy_rtx (value), reg, tem);
10942 /* For each register modified, show we don't know its value, that
10943 we don't know about its bitwise content, that its value has been
10944 updated, and that we don't know the location of the death of the
10946 for (i = regno; i < endregno; i++)
10949 reg_stat[i].last_set = insn;
10951 reg_stat[i].last_set_value = 0;
10952 reg_stat[i].last_set_mode = 0;
10953 reg_stat[i].last_set_nonzero_bits = 0;
10954 reg_stat[i].last_set_sign_bit_copies = 0;
10955 reg_stat[i].last_death = 0;
10958 /* Mark registers that are being referenced in this value. */
10960 update_table_tick (value);
10962 /* Now update the status of each register being set.
10963 If someone is using this register in this block, set this register
10964 to invalid since we will get confused between the two lives in this
10965 basic block. This makes using this register always invalid. In cse, we
10966 scan the table to invalidate all entries using this register, but this
10967 is too much work for us. */
10969 for (i = regno; i < endregno; i++)
10971 reg_stat[i].last_set_label = label_tick;
10972 if (value && reg_stat[i].last_set_table_tick == label_tick)
10973 reg_stat[i].last_set_invalid = 1;
10975 reg_stat[i].last_set_invalid = 0;
10978 /* The value being assigned might refer to X (like in "x++;"). In that
10979 case, we must replace it with (clobber (const_int 0)) to prevent
10981 if (value && ! get_last_value_validate (&value, insn,
10982 reg_stat[regno].last_set_label, 0))
10984 value = copy_rtx (value);
10985 if (! get_last_value_validate (&value, insn,
10986 reg_stat[regno].last_set_label, 1))
10990 /* For the main register being modified, update the value, the mode, the
10991 nonzero bits, and the number of sign bit copies. */
10993 reg_stat[regno].last_set_value = value;
10997 enum machine_mode mode = GET_MODE (reg);
10998 subst_low_cuid = INSN_CUID (insn);
10999 reg_stat[regno].last_set_mode = mode;
11000 if (GET_MODE_CLASS (mode) == MODE_INT
11001 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11002 mode = nonzero_bits_mode;
11003 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
11004 reg_stat[regno].last_set_sign_bit_copies
11005 = num_sign_bit_copies (value, GET_MODE (reg));
11009 /* Called via note_stores from record_dead_and_set_regs to handle one
11010 SET or CLOBBER in an insn. DATA is the instruction in which the
11011 set is occurring. */
11014 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11016 rtx record_dead_insn = (rtx) data;
11018 if (GET_CODE (dest) == SUBREG)
11019 dest = SUBREG_REG (dest);
11023 /* If we are setting the whole register, we know its value. Otherwise
11024 show that we don't know the value. We can handle SUBREG in
11026 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11027 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11028 else if (GET_CODE (setter) == SET
11029 && GET_CODE (SET_DEST (setter)) == SUBREG
11030 && SUBREG_REG (SET_DEST (setter)) == dest
11031 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11032 && subreg_lowpart_p (SET_DEST (setter)))
11033 record_value_for_reg (dest, record_dead_insn,
11034 gen_lowpart (GET_MODE (dest),
11035 SET_SRC (setter)));
11037 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11039 else if (MEM_P (dest)
11040 /* Ignore pushes, they clobber nothing. */
11041 && ! push_operand (dest, GET_MODE (dest)))
11042 mem_last_set = INSN_CUID (record_dead_insn);
11045 /* Update the records of when each REG was most recently set or killed
11046 for the things done by INSN. This is the last thing done in processing
11047 INSN in the combiner loop.
11049 We update reg_stat[], in particular fields last_set, last_set_value,
11050 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11051 last_death, and also the similar information mem_last_set (which insn
11052 most recently modified memory) and last_call_cuid (which insn was the
11053 most recent subroutine call). */
11056 record_dead_and_set_regs (rtx insn)
11061 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11063 if (REG_NOTE_KIND (link) == REG_DEAD
11064 && REG_P (XEXP (link, 0)))
11066 unsigned int regno = REGNO (XEXP (link, 0));
11067 unsigned int endregno
11068 = regno + (regno < FIRST_PSEUDO_REGISTER
11069 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11072 for (i = regno; i < endregno; i++)
11073 reg_stat[i].last_death = insn;
11075 else if (REG_NOTE_KIND (link) == REG_INC)
11076 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11081 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11082 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11084 reg_stat[i].last_set_value = 0;
11085 reg_stat[i].last_set_mode = 0;
11086 reg_stat[i].last_set_nonzero_bits = 0;
11087 reg_stat[i].last_set_sign_bit_copies = 0;
11088 reg_stat[i].last_death = 0;
11091 last_call_cuid = mem_last_set = INSN_CUID (insn);
11093 /* Don't bother recording what this insn does. It might set the
11094 return value register, but we can't combine into a call
11095 pattern anyway, so there's no point trying (and it may cause
11096 a crash, if e.g. we wind up asking for last_set_value of a
11097 SUBREG of the return value register). */
11101 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11104 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11105 register present in the SUBREG, so for each such SUBREG go back and
11106 adjust nonzero and sign bit information of the registers that are
11107 known to have some zero/sign bits set.
11109 This is needed because when combine blows the SUBREGs away, the
11110 information on zero/sign bits is lost and further combines can be
11111 missed because of that. */
11114 record_promoted_value (rtx insn, rtx subreg)
11117 unsigned int regno = REGNO (SUBREG_REG (subreg));
11118 enum machine_mode mode = GET_MODE (subreg);
11120 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11123 for (links = LOG_LINKS (insn); links;)
11125 insn = XEXP (links, 0);
11126 set = single_set (insn);
11128 if (! set || !REG_P (SET_DEST (set))
11129 || REGNO (SET_DEST (set)) != regno
11130 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11132 links = XEXP (links, 1);
11136 if (reg_stat[regno].last_set == insn)
11138 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11139 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11142 if (REG_P (SET_SRC (set)))
11144 regno = REGNO (SET_SRC (set));
11145 links = LOG_LINKS (insn);
11152 /* Scan X for promoted SUBREGs. For each one found,
11153 note what it implies to the registers used in it. */
11156 check_promoted_subreg (rtx insn, rtx x)
11158 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11159 && REG_P (SUBREG_REG (x)))
11160 record_promoted_value (insn, x);
11163 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11166 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11170 check_promoted_subreg (insn, XEXP (x, i));
11174 if (XVEC (x, i) != 0)
11175 for (j = 0; j < XVECLEN (x, i); j++)
11176 check_promoted_subreg (insn, XVECEXP (x, i, j));
11182 /* Utility routine for the following function. Verify that all the registers
11183 mentioned in *LOC are valid when *LOC was part of a value set when
11184 label_tick == TICK. Return 0 if some are not.
11186 If REPLACE is nonzero, replace the invalid reference with
11187 (clobber (const_int 0)) and return 1. This replacement is useful because
11188 we often can get useful information about the form of a value (e.g., if
11189 it was produced by a shift that always produces -1 or 0) even though
11190 we don't know exactly what registers it was produced from. */
11193 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11196 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11197 int len = GET_RTX_LENGTH (GET_CODE (x));
11202 unsigned int regno = REGNO (x);
11203 unsigned int endregno
11204 = regno + (regno < FIRST_PSEUDO_REGISTER
11205 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11208 for (j = regno; j < endregno; j++)
11209 if (reg_stat[j].last_set_invalid
11210 /* If this is a pseudo-register that was only set once and not
11211 live at the beginning of the function, it is always valid. */
11212 || (! (regno >= FIRST_PSEUDO_REGISTER
11213 && REG_N_SETS (regno) == 1
11214 && (! REGNO_REG_SET_P
11215 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11216 && reg_stat[j].last_set_label > tick))
11219 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11225 /* If this is a memory reference, make sure that there were
11226 no stores after it that might have clobbered the value. We don't
11227 have alias info, so we assume any store invalidates it. */
11228 else if (MEM_P (x) && !MEM_READONLY_P (x)
11229 && INSN_CUID (insn) <= mem_last_set)
11232 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11236 for (i = 0; i < len; i++)
11240 /* Check for identical subexpressions. If x contains
11241 identical subexpression we only have to traverse one of
11243 if (i == 1 && ARITHMETIC_P (x))
11245 /* Note that at this point x0 has already been checked
11246 and found valid. */
11247 rtx x0 = XEXP (x, 0);
11248 rtx x1 = XEXP (x, 1);
11250 /* If x0 and x1 are identical then x is also valid. */
11254 /* If x1 is identical to a subexpression of x0 then
11255 while checking x0, x1 has already been checked. Thus
11256 it is valid and so as x. */
11257 if (ARITHMETIC_P (x0)
11258 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11261 /* If x0 is identical to a subexpression of x1 then x is
11262 valid iff the rest of x1 is valid. */
11263 if (ARITHMETIC_P (x1)
11264 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11266 get_last_value_validate (&XEXP (x1,
11267 x0 == XEXP (x1, 0) ? 1 : 0),
11268 insn, tick, replace);
11271 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11275 /* Don't bother with these. They shouldn't occur anyway. */
11276 else if (fmt[i] == 'E')
11280 /* If we haven't found a reason for it to be invalid, it is valid. */
11284 /* Get the last value assigned to X, if known. Some registers
11285 in the value may be replaced with (clobber (const_int 0)) if their value
11286 is known longer known reliably. */
11289 get_last_value (rtx x)
11291 unsigned int regno;
11294 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11295 then convert it to the desired mode. If this is a paradoxical SUBREG,
11296 we cannot predict what values the "extra" bits might have. */
11297 if (GET_CODE (x) == SUBREG
11298 && subreg_lowpart_p (x)
11299 && (GET_MODE_SIZE (GET_MODE (x))
11300 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11301 && (value = get_last_value (SUBREG_REG (x))) != 0)
11302 return gen_lowpart (GET_MODE (x), value);
11308 value = reg_stat[regno].last_set_value;
11310 /* If we don't have a value, or if it isn't for this basic block and
11311 it's either a hard register, set more than once, or it's a live
11312 at the beginning of the function, return 0.
11314 Because if it's not live at the beginning of the function then the reg
11315 is always set before being used (is never used without being set).
11316 And, if it's set only once, and it's always set before use, then all
11317 uses must have the same last value, even if it's not from this basic
11321 || (reg_stat[regno].last_set_label != label_tick
11322 && (regno < FIRST_PSEUDO_REGISTER
11323 || REG_N_SETS (regno) != 1
11324 || (REGNO_REG_SET_P
11325 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11328 /* If the value was set in a later insn than the ones we are processing,
11329 we can't use it even if the register was only set once. */
11330 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11333 /* If the value has all its registers valid, return it. */
11334 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11335 reg_stat[regno].last_set_label, 0))
11338 /* Otherwise, make a copy and replace any invalid register with
11339 (clobber (const_int 0)). If that fails for some reason, return 0. */
11341 value = copy_rtx (value);
11342 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11343 reg_stat[regno].last_set_label, 1))
11349 /* Return nonzero if expression X refers to a REG or to memory
11350 that is set in an instruction more recent than FROM_CUID. */
11353 use_crosses_set_p (rtx x, int from_cuid)
11357 enum rtx_code code = GET_CODE (x);
11361 unsigned int regno = REGNO (x);
11362 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11363 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11365 #ifdef PUSH_ROUNDING
11366 /* Don't allow uses of the stack pointer to be moved,
11367 because we don't know whether the move crosses a push insn. */
11368 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11371 for (; regno < endreg; regno++)
11372 if (reg_stat[regno].last_set
11373 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11378 if (code == MEM && mem_last_set > from_cuid)
11381 fmt = GET_RTX_FORMAT (code);
11383 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11388 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11389 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11392 else if (fmt[i] == 'e'
11393 && use_crosses_set_p (XEXP (x, i), from_cuid))
11399 /* Define three variables used for communication between the following
11402 static unsigned int reg_dead_regno, reg_dead_endregno;
11403 static int reg_dead_flag;
11405 /* Function called via note_stores from reg_dead_at_p.
11407 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11408 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11411 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11413 unsigned int regno, endregno;
11418 regno = REGNO (dest);
11419 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11420 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11422 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11423 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11426 /* Return nonzero if REG is known to be dead at INSN.
11428 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11429 referencing REG, it is dead. If we hit a SET referencing REG, it is
11430 live. Otherwise, see if it is live or dead at the start of the basic
11431 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11432 must be assumed to be always live. */
11435 reg_dead_at_p (rtx reg, rtx insn)
11440 /* Set variables for reg_dead_at_p_1. */
11441 reg_dead_regno = REGNO (reg);
11442 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11443 ? hard_regno_nregs[reg_dead_regno]
11449 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11450 we allow the machine description to decide whether use-and-clobber
11451 patterns are OK. */
11452 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11454 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11455 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11459 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11460 beginning of function. */
11461 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11462 insn = prev_nonnote_insn (insn))
11464 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11466 return reg_dead_flag == 1 ? 1 : 0;
11468 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11472 /* Get the basic block that we were in. */
11474 block = ENTRY_BLOCK_PTR->next_bb;
11477 FOR_EACH_BB (block)
11478 if (insn == BB_HEAD (block))
11481 if (block == EXIT_BLOCK_PTR)
11485 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11486 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11492 /* Note hard registers in X that are used. This code is similar to
11493 that in flow.c, but much simpler since we don't care about pseudos. */
11496 mark_used_regs_combine (rtx x)
11498 RTX_CODE code = GET_CODE (x);
11499 unsigned int regno;
11512 case ADDR_DIFF_VEC:
11515 /* CC0 must die in the insn after it is set, so we don't need to take
11516 special note of it here. */
11522 /* If we are clobbering a MEM, mark any hard registers inside the
11523 address as used. */
11524 if (MEM_P (XEXP (x, 0)))
11525 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11530 /* A hard reg in a wide mode may really be multiple registers.
11531 If so, mark all of them just like the first. */
11532 if (regno < FIRST_PSEUDO_REGISTER)
11534 unsigned int endregno, r;
11536 /* None of this applies to the stack, frame or arg pointers. */
11537 if (regno == STACK_POINTER_REGNUM
11538 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11539 || regno == HARD_FRAME_POINTER_REGNUM
11541 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11542 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11544 || regno == FRAME_POINTER_REGNUM)
11547 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11548 for (r = regno; r < endregno; r++)
11549 SET_HARD_REG_BIT (newpat_used_regs, r);
11555 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11557 rtx testreg = SET_DEST (x);
11559 while (GET_CODE (testreg) == SUBREG
11560 || GET_CODE (testreg) == ZERO_EXTRACT
11561 || GET_CODE (testreg) == STRICT_LOW_PART)
11562 testreg = XEXP (testreg, 0);
11564 if (MEM_P (testreg))
11565 mark_used_regs_combine (XEXP (testreg, 0));
11567 mark_used_regs_combine (SET_SRC (x));
11575 /* Recursively scan the operands of this expression. */
11578 const char *fmt = GET_RTX_FORMAT (code);
11580 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11583 mark_used_regs_combine (XEXP (x, i));
11584 else if (fmt[i] == 'E')
11588 for (j = 0; j < XVECLEN (x, i); j++)
11589 mark_used_regs_combine (XVECEXP (x, i, j));
11595 /* Remove register number REGNO from the dead registers list of INSN.
11597 Return the note used to record the death, if there was one. */
11600 remove_death (unsigned int regno, rtx insn)
11602 rtx note = find_regno_note (insn, REG_DEAD, regno);
11606 REG_N_DEATHS (regno)--;
11607 remove_note (insn, note);
11613 /* For each register (hardware or pseudo) used within expression X, if its
11614 death is in an instruction with cuid between FROM_CUID (inclusive) and
11615 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11616 list headed by PNOTES.
11618 That said, don't move registers killed by maybe_kill_insn.
11620 This is done when X is being merged by combination into TO_INSN. These
11621 notes will then be distributed as needed. */
11624 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11629 enum rtx_code code = GET_CODE (x);
11633 unsigned int regno = REGNO (x);
11634 rtx where_dead = reg_stat[regno].last_death;
11635 rtx before_dead, after_dead;
11637 /* Don't move the register if it gets killed in between from and to. */
11638 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11639 && ! reg_referenced_p (x, maybe_kill_insn))
11642 /* WHERE_DEAD could be a USE insn made by combine, so first we
11643 make sure that we have insns with valid INSN_CUID values. */
11644 before_dead = where_dead;
11645 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11646 before_dead = PREV_INSN (before_dead);
11648 after_dead = where_dead;
11649 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11650 after_dead = NEXT_INSN (after_dead);
11652 if (before_dead && after_dead
11653 && INSN_CUID (before_dead) >= from_cuid
11654 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11655 || (where_dead != after_dead
11656 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11658 rtx note = remove_death (regno, where_dead);
11660 /* It is possible for the call above to return 0. This can occur
11661 when last_death points to I2 or I1 that we combined with.
11662 In that case make a new note.
11664 We must also check for the case where X is a hard register
11665 and NOTE is a death note for a range of hard registers
11666 including X. In that case, we must put REG_DEAD notes for
11667 the remaining registers in place of NOTE. */
11669 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11670 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11671 > GET_MODE_SIZE (GET_MODE (x))))
11673 unsigned int deadregno = REGNO (XEXP (note, 0));
11674 unsigned int deadend
11675 = (deadregno + hard_regno_nregs[deadregno]
11676 [GET_MODE (XEXP (note, 0))]);
11677 unsigned int ourend
11678 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11681 for (i = deadregno; i < deadend; i++)
11682 if (i < regno || i >= ourend)
11683 REG_NOTES (where_dead)
11684 = gen_rtx_EXPR_LIST (REG_DEAD,
11686 REG_NOTES (where_dead));
11689 /* If we didn't find any note, or if we found a REG_DEAD note that
11690 covers only part of the given reg, and we have a multi-reg hard
11691 register, then to be safe we must check for REG_DEAD notes
11692 for each register other than the first. They could have
11693 their own REG_DEAD notes lying around. */
11694 else if ((note == 0
11696 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11697 < GET_MODE_SIZE (GET_MODE (x)))))
11698 && regno < FIRST_PSEUDO_REGISTER
11699 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11701 unsigned int ourend
11702 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11703 unsigned int i, offset;
11707 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11711 for (i = regno + offset; i < ourend; i++)
11712 move_deaths (regno_reg_rtx[i],
11713 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11716 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11718 XEXP (note, 1) = *pnotes;
11722 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11724 REG_N_DEATHS (regno)++;
11730 else if (GET_CODE (x) == SET)
11732 rtx dest = SET_DEST (x);
11734 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11736 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11737 that accesses one word of a multi-word item, some
11738 piece of everything register in the expression is used by
11739 this insn, so remove any old death. */
11740 /* ??? So why do we test for equality of the sizes? */
11742 if (GET_CODE (dest) == ZERO_EXTRACT
11743 || GET_CODE (dest) == STRICT_LOW_PART
11744 || (GET_CODE (dest) == SUBREG
11745 && (((GET_MODE_SIZE (GET_MODE (dest))
11746 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11747 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11748 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11750 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11754 /* If this is some other SUBREG, we know it replaces the entire
11755 value, so use that as the destination. */
11756 if (GET_CODE (dest) == SUBREG)
11757 dest = SUBREG_REG (dest);
11759 /* If this is a MEM, adjust deaths of anything used in the address.
11760 For a REG (the only other possibility), the entire value is
11761 being replaced so the old value is not used in this insn. */
11764 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11769 else if (GET_CODE (x) == CLOBBER)
11772 len = GET_RTX_LENGTH (code);
11773 fmt = GET_RTX_FORMAT (code);
11775 for (i = 0; i < len; i++)
11780 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11781 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11784 else if (fmt[i] == 'e')
11785 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11789 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11790 pattern of an insn. X must be a REG. */
11793 reg_bitfield_target_p (rtx x, rtx body)
11797 if (GET_CODE (body) == SET)
11799 rtx dest = SET_DEST (body);
11801 unsigned int regno, tregno, endregno, endtregno;
11803 if (GET_CODE (dest) == ZERO_EXTRACT)
11804 target = XEXP (dest, 0);
11805 else if (GET_CODE (dest) == STRICT_LOW_PART)
11806 target = SUBREG_REG (XEXP (dest, 0));
11810 if (GET_CODE (target) == SUBREG)
11811 target = SUBREG_REG (target);
11813 if (!REG_P (target))
11816 tregno = REGNO (target), regno = REGNO (x);
11817 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11818 return target == x;
11820 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11821 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11823 return endregno > tregno && regno < endtregno;
11826 else if (GET_CODE (body) == PARALLEL)
11827 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11828 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11834 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11835 as appropriate. I3 and I2 are the insns resulting from the combination
11836 insns including FROM (I2 may be zero).
11838 Each note in the list is either ignored or placed on some insns, depending
11839 on the type of note. */
11842 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11844 rtx note, next_note;
11847 for (note = notes; note; note = next_note)
11849 rtx place = 0, place2 = 0;
11851 /* If this NOTE references a pseudo register, ensure it references
11852 the latest copy of that register. */
11853 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11854 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11855 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11857 next_note = XEXP (note, 1);
11858 switch (REG_NOTE_KIND (note))
11862 /* Doesn't matter much where we put this, as long as it's somewhere.
11863 It is preferable to keep these notes on branches, which is most
11864 likely to be i3. */
11868 case REG_VALUE_PROFILE:
11869 /* Just get rid of this note, as it is unused later anyway. */
11872 case REG_NON_LOCAL_GOTO:
11877 gcc_assert (i2 && JUMP_P (i2));
11882 case REG_EH_REGION:
11883 /* These notes must remain with the call or trapping instruction. */
11886 else if (i2 && CALL_P (i2))
11890 gcc_assert (flag_non_call_exceptions);
11891 if (may_trap_p (i3))
11893 else if (i2 && may_trap_p (i2))
11895 /* ??? Otherwise assume we've combined things such that we
11896 can now prove that the instructions can't trap. Drop the
11897 note in this case. */
11903 /* These notes must remain with the call. It should not be
11904 possible for both I2 and I3 to be a call. */
11909 gcc_assert (i2 && CALL_P (i2));
11915 /* Any clobbers for i3 may still exist, and so we must process
11916 REG_UNUSED notes from that insn.
11918 Any clobbers from i2 or i1 can only exist if they were added by
11919 recog_for_combine. In that case, recog_for_combine created the
11920 necessary REG_UNUSED notes. Trying to keep any original
11921 REG_UNUSED notes from these insns can cause incorrect output
11922 if it is for the same register as the original i3 dest.
11923 In that case, we will notice that the register is set in i3,
11924 and then add a REG_UNUSED note for the destination of i3, which
11925 is wrong. However, it is possible to have REG_UNUSED notes from
11926 i2 or i1 for register which were both used and clobbered, so
11927 we keep notes from i2 or i1 if they will turn into REG_DEAD
11930 /* If this register is set or clobbered in I3, put the note there
11931 unless there is one already. */
11932 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11934 if (from_insn != i3)
11937 if (! (REG_P (XEXP (note, 0))
11938 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11939 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11942 /* Otherwise, if this register is used by I3, then this register
11943 now dies here, so we must put a REG_DEAD note here unless there
11945 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11946 && ! (REG_P (XEXP (note, 0))
11947 ? find_regno_note (i3, REG_DEAD,
11948 REGNO (XEXP (note, 0)))
11949 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11951 PUT_REG_NOTE_KIND (note, REG_DEAD);
11959 /* These notes say something about results of an insn. We can
11960 only support them if they used to be on I3 in which case they
11961 remain on I3. Otherwise they are ignored.
11963 If the note refers to an expression that is not a constant, we
11964 must also ignore the note since we cannot tell whether the
11965 equivalence is still true. It might be possible to do
11966 slightly better than this (we only have a problem if I2DEST
11967 or I1DEST is present in the expression), but it doesn't
11968 seem worth the trouble. */
11970 if (from_insn == i3
11971 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11976 case REG_NO_CONFLICT:
11977 /* These notes say something about how a register is used. They must
11978 be present on any use of the register in I2 or I3. */
11979 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11982 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11992 /* This can show up in several ways -- either directly in the
11993 pattern, or hidden off in the constant pool with (or without?)
11994 a REG_EQUAL note. */
11995 /* ??? Ignore the without-reg_equal-note problem for now. */
11996 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11997 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11998 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11999 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12003 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12004 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12005 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12006 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12014 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12015 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12016 if (place && JUMP_P (place))
12018 rtx label = JUMP_LABEL (place);
12021 JUMP_LABEL (place) = XEXP (note, 0);
12024 gcc_assert (label == XEXP (note, 0));
12025 if (LABEL_P (label))
12026 LABEL_NUSES (label)--;
12030 if (place2 && JUMP_P (place2))
12032 rtx label = JUMP_LABEL (place2);
12035 JUMP_LABEL (place2) = XEXP (note, 0);
12038 gcc_assert (label == XEXP (note, 0));
12039 if (LABEL_P (label))
12040 LABEL_NUSES (label)--;
12047 /* This note says something about the value of a register prior
12048 to the execution of an insn. It is too much trouble to see
12049 if the note is still correct in all situations. It is better
12050 to simply delete it. */
12054 /* If the insn previously containing this note still exists,
12055 put it back where it was. Otherwise move it to the previous
12056 insn. Adjust the corresponding REG_LIBCALL note. */
12057 if (!NOTE_P (from_insn))
12061 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12062 place = prev_real_insn (from_insn);
12064 XEXP (tem, 0) = place;
12065 /* If we're deleting the last remaining instruction of a
12066 libcall sequence, don't add the notes. */
12067 else if (XEXP (note, 0) == from_insn)
12069 /* Don't add the dangling REG_RETVAL note. */
12076 /* This is handled similarly to REG_RETVAL. */
12077 if (!NOTE_P (from_insn))
12081 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12082 place = next_real_insn (from_insn);
12084 XEXP (tem, 0) = place;
12085 /* If we're deleting the last remaining instruction of a
12086 libcall sequence, don't add the notes. */
12087 else if (XEXP (note, 0) == from_insn)
12089 /* Don't add the dangling REG_LIBCALL note. */
12096 /* If the register is used as an input in I3, it dies there.
12097 Similarly for I2, if it is nonzero and adjacent to I3.
12099 If the register is not used as an input in either I3 or I2
12100 and it is not one of the registers we were supposed to eliminate,
12101 there are two possibilities. We might have a non-adjacent I2
12102 or we might have somehow eliminated an additional register
12103 from a computation. For example, we might have had A & B where
12104 we discover that B will always be zero. In this case we will
12105 eliminate the reference to A.
12107 In both cases, we must search to see if we can find a previous
12108 use of A and put the death note there. */
12111 && CALL_P (from_insn)
12112 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12114 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12116 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12117 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12122 basic_block bb = this_basic_block;
12124 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12126 if (! INSN_P (tem))
12128 if (tem == BB_HEAD (bb))
12133 /* If the register is being set at TEM, see if that is all
12134 TEM is doing. If so, delete TEM. Otherwise, make this
12135 into a REG_UNUSED note instead. Don't delete sets to
12136 global register vars. */
12137 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12138 || !global_regs[REGNO (XEXP (note, 0))])
12139 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12141 rtx set = single_set (tem);
12142 rtx inner_dest = 0;
12144 rtx cc0_setter = NULL_RTX;
12148 for (inner_dest = SET_DEST (set);
12149 (GET_CODE (inner_dest) == STRICT_LOW_PART
12150 || GET_CODE (inner_dest) == SUBREG
12151 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12152 inner_dest = XEXP (inner_dest, 0))
12155 /* Verify that it was the set, and not a clobber that
12156 modified the register.
12158 CC0 targets must be careful to maintain setter/user
12159 pairs. If we cannot delete the setter due to side
12160 effects, mark the user with an UNUSED note instead
12163 if (set != 0 && ! side_effects_p (SET_SRC (set))
12164 && rtx_equal_p (XEXP (note, 0), inner_dest)
12166 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12167 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12168 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12172 /* Move the notes and links of TEM elsewhere.
12173 This might delete other dead insns recursively.
12174 First set the pattern to something that won't use
12176 rtx old_notes = REG_NOTES (tem);
12178 PATTERN (tem) = pc_rtx;
12179 REG_NOTES (tem) = NULL;
12181 distribute_notes (old_notes, tem, tem, NULL_RTX);
12182 distribute_links (LOG_LINKS (tem));
12184 SET_INSN_DELETED (tem);
12187 /* Delete the setter too. */
12190 PATTERN (cc0_setter) = pc_rtx;
12191 old_notes = REG_NOTES (cc0_setter);
12192 REG_NOTES (cc0_setter) = NULL;
12194 distribute_notes (old_notes, cc0_setter,
12195 cc0_setter, NULL_RTX);
12196 distribute_links (LOG_LINKS (cc0_setter));
12198 SET_INSN_DELETED (cc0_setter);
12204 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12206 /* If there isn't already a REG_UNUSED note, put one
12207 here. Do not place a REG_DEAD note, even if
12208 the register is also used here; that would not
12209 match the algorithm used in lifetime analysis
12210 and can cause the consistency check in the
12211 scheduler to fail. */
12212 if (! find_regno_note (tem, REG_UNUSED,
12213 REGNO (XEXP (note, 0))))
12218 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12220 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12224 /* If we are doing a 3->2 combination, and we have a
12225 register which formerly died in i3 and was not used
12226 by i2, which now no longer dies in i3 and is used in
12227 i2 but does not die in i2, and place is between i2
12228 and i3, then we may need to move a link from place to
12230 if (i2 && INSN_UID (place) <= max_uid_cuid
12231 && INSN_CUID (place) > INSN_CUID (i2)
12233 && INSN_CUID (from_insn) > INSN_CUID (i2)
12234 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12236 rtx links = LOG_LINKS (place);
12237 LOG_LINKS (place) = 0;
12238 distribute_links (links);
12243 if (tem == BB_HEAD (bb))
12247 /* We haven't found an insn for the death note and it
12248 is still a REG_DEAD note, but we have hit the beginning
12249 of the block. If the existing life info says the reg
12250 was dead, there's nothing left to do. Otherwise, we'll
12251 need to do a global life update after combine. */
12252 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12253 && REGNO_REG_SET_P (bb->global_live_at_start,
12254 REGNO (XEXP (note, 0))))
12255 SET_BIT (refresh_blocks, this_basic_block->index);
12258 /* If the register is set or already dead at PLACE, we needn't do
12259 anything with this note if it is still a REG_DEAD note.
12260 We check here if it is set at all, not if is it totally replaced,
12261 which is what `dead_or_set_p' checks, so also check for it being
12264 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12266 unsigned int regno = REGNO (XEXP (note, 0));
12268 /* Similarly, if the instruction on which we want to place
12269 the note is a noop, we'll need do a global live update
12270 after we remove them in delete_noop_moves. */
12271 if (noop_move_p (place))
12272 SET_BIT (refresh_blocks, this_basic_block->index);
12274 if (dead_or_set_p (place, XEXP (note, 0))
12275 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12277 /* Unless the register previously died in PLACE, clear
12278 last_death. [I no longer understand why this is
12280 if (reg_stat[regno].last_death != place)
12281 reg_stat[regno].last_death = 0;
12285 reg_stat[regno].last_death = place;
12287 /* If this is a death note for a hard reg that is occupying
12288 multiple registers, ensure that we are still using all
12289 parts of the object. If we find a piece of the object
12290 that is unused, we must arrange for an appropriate REG_DEAD
12291 note to be added for it. However, we can't just emit a USE
12292 and tag the note to it, since the register might actually
12293 be dead; so we recourse, and the recursive call then finds
12294 the previous insn that used this register. */
12296 if (place && regno < FIRST_PSEUDO_REGISTER
12297 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12299 unsigned int endregno
12300 = regno + hard_regno_nregs[regno]
12301 [GET_MODE (XEXP (note, 0))];
12305 for (i = regno; i < endregno; i++)
12306 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12307 && ! find_regno_fusage (place, USE, i))
12308 || dead_or_set_regno_p (place, i))
12313 /* Put only REG_DEAD notes for pieces that are
12314 not already dead or set. */
12316 for (i = regno; i < endregno;
12317 i += hard_regno_nregs[i][reg_raw_mode[i]])
12319 rtx piece = regno_reg_rtx[i];
12320 basic_block bb = this_basic_block;
12322 if (! dead_or_set_p (place, piece)
12323 && ! reg_bitfield_target_p (piece,
12327 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12329 distribute_notes (new_note, place, place,
12332 else if (! refers_to_regno_p (i, i + 1,
12333 PATTERN (place), 0)
12334 && ! find_regno_fusage (place, USE, i))
12335 for (tem = PREV_INSN (place); ;
12336 tem = PREV_INSN (tem))
12338 if (! INSN_P (tem))
12340 if (tem == BB_HEAD (bb))
12342 SET_BIT (refresh_blocks,
12343 this_basic_block->index);
12348 if (dead_or_set_p (tem, piece)
12349 || reg_bitfield_target_p (piece,
12353 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12368 /* Any other notes should not be present at this point in the
12370 gcc_unreachable ();
12375 XEXP (note, 1) = REG_NOTES (place);
12376 REG_NOTES (place) = note;
12378 else if ((REG_NOTE_KIND (note) == REG_DEAD
12379 || REG_NOTE_KIND (note) == REG_UNUSED)
12380 && REG_P (XEXP (note, 0)))
12381 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12385 if ((REG_NOTE_KIND (note) == REG_DEAD
12386 || REG_NOTE_KIND (note) == REG_UNUSED)
12387 && REG_P (XEXP (note, 0)))
12388 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12390 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12391 REG_NOTE_KIND (note),
12393 REG_NOTES (place2));
12398 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12399 I3, I2, and I1 to new locations. This is also called to add a link
12400 pointing at I3 when I3's destination is changed. */
12403 distribute_links (rtx links)
12405 rtx link, next_link;
12407 for (link = links; link; link = next_link)
12413 next_link = XEXP (link, 1);
12415 /* If the insn that this link points to is a NOTE or isn't a single
12416 set, ignore it. In the latter case, it isn't clear what we
12417 can do other than ignore the link, since we can't tell which
12418 register it was for. Such links wouldn't be used by combine
12421 It is not possible for the destination of the target of the link to
12422 have been changed by combine. The only potential of this is if we
12423 replace I3, I2, and I1 by I3 and I2. But in that case the
12424 destination of I2 also remains unchanged. */
12426 if (NOTE_P (XEXP (link, 0))
12427 || (set = single_set (XEXP (link, 0))) == 0)
12430 reg = SET_DEST (set);
12431 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12432 || GET_CODE (reg) == STRICT_LOW_PART)
12433 reg = XEXP (reg, 0);
12435 /* A LOG_LINK is defined as being placed on the first insn that uses
12436 a register and points to the insn that sets the register. Start
12437 searching at the next insn after the target of the link and stop
12438 when we reach a set of the register or the end of the basic block.
12440 Note that this correctly handles the link that used to point from
12441 I3 to I2. Also note that not much searching is typically done here
12442 since most links don't point very far away. */
12444 for (insn = NEXT_INSN (XEXP (link, 0));
12445 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12446 || BB_HEAD (this_basic_block->next_bb) != insn));
12447 insn = NEXT_INSN (insn))
12448 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12450 if (reg_referenced_p (reg, PATTERN (insn)))
12454 else if (CALL_P (insn)
12455 && find_reg_fusage (insn, USE, reg))
12460 else if (INSN_P (insn) && reg_set_p (reg, insn))
12463 /* If we found a place to put the link, place it there unless there
12464 is already a link to the same insn as LINK at that point. */
12470 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12471 if (XEXP (link2, 0) == XEXP (link, 0))
12476 XEXP (link, 1) = LOG_LINKS (place);
12477 LOG_LINKS (place) = link;
12479 /* Set added_links_insn to the earliest insn we added a
12481 if (added_links_insn == 0
12482 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12483 added_links_insn = place;
12489 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12490 Check whether the expression pointer to by LOC is a register or
12491 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12492 Otherwise return zero. */
12495 unmentioned_reg_p_1 (rtx *loc, void *expr)
12500 && (REG_P (x) || MEM_P (x))
12501 && ! reg_mentioned_p (x, (rtx) expr))
12506 /* Check for any register or memory mentioned in EQUIV that is not
12507 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12508 of EXPR where some registers may have been replaced by constants. */
12511 unmentioned_reg_p (rtx equiv, rtx expr)
12513 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12516 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12519 insn_cuid (rtx insn)
12521 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12522 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12523 insn = NEXT_INSN (insn);
12525 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12527 return INSN_CUID (insn);
12531 dump_combine_stats (FILE *file)
12535 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12536 combine_attempts, combine_merges, combine_extras, combine_successes);
12540 dump_combine_total_stats (FILE *file)
12544 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12545 total_attempts, total_merges, total_extras, total_successes);
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