1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-96, 1997 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
84 /* Must precede rtl.h for FFS. */
90 #include "hard-reg-set.h"
92 #include "basic-block.h"
93 #include "insn-config.h"
94 #include "insn-flags.h"
95 #include "insn-codes.h"
96 #include "insn-attr.h"
100 /* It is not safe to use ordinary gen_lowpart in combine.
101 Use gen_lowpart_for_combine instead. See comments there. */
102 #define gen_lowpart dont_use_gen_lowpart_you_dummy
104 /* Number of attempts to combine instructions in this function. */
106 static int combine_attempts;
108 /* Number of attempts that got as far as substitution in this function. */
110 static int combine_merges;
112 /* Number of instructions combined with added SETs in this function. */
114 static int combine_extras;
116 /* Number of instructions combined in this function. */
118 static int combine_successes;
120 /* Totals over entire compilation. */
122 static int total_attempts, total_merges, total_extras, total_successes;
124 /* Define a default value for REVERSIBLE_CC_MODE.
125 We can never assume that a condition code mode is safe to reverse unless
126 the md tells us so. */
127 #ifndef REVERSIBLE_CC_MODE
128 #define REVERSIBLE_CC_MODE(MODE) 0
131 /* Vector mapping INSN_UIDs to cuids.
132 The cuids are like uids but increase monotonically always.
133 Combine always uses cuids so that it can compare them.
134 But actually renumbering the uids, which we used to do,
135 proves to be a bad idea because it makes it hard to compare
136 the dumps produced by earlier passes with those from later passes. */
138 static int *uid_cuid;
139 static int max_uid_cuid;
141 /* Get the cuid of an insn. */
143 #define INSN_CUID(INSN) \
144 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
146 /* Maximum register number, which is the size of the tables below. */
148 static int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is an insn that belongs before subst_insn, but is not currently
177 on the insn chain. */
179 static rtx subst_prev_insn;
181 /* This is the lowest CUID that `subst' is currently dealing with.
182 get_last_value will not return a value if the register was set at or
183 after this CUID. If not for this mechanism, we could get confused if
184 I2 or I1 in try_combine were an insn that used the old value of a register
185 to obtain a new value. In that case, we might erroneously get the
186 new value of the register when we wanted the old one. */
188 static int subst_low_cuid;
190 /* This contains any hard registers that are used in newpat; reg_dead_at_p
191 must consider all these registers to be always live. */
193 static HARD_REG_SET newpat_used_regs;
195 /* This is an insn to which a LOG_LINKS entry has been added. If this
196 insn is the earlier than I2 or I3, combine should rescan starting at
199 static rtx added_links_insn;
201 /* Basic block number of the block in which we are performing combines. */
202 static int this_basic_block;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 storage is nonzero if we must undo the allocation of new storage.
325 The value of storage is what to pass to obfree.
327 other_insn is nonzero if we have modified some other insn in the process
328 of working on subst_insn. It must be verified too.
330 previous_undos is the value of undobuf.undos when we started processing
331 this substitution. This will prevent gen_rtx_combine from re-used a piece
332 from the previous expression. Doing so can produce circular rtl
340 struct undo *previous_undos;
344 static struct undobuf undobuf;
346 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
347 insn. The substitution can be undone by undo_all. If INTO is already
348 set to NEWVAL, do not record this change. Because computing NEWVAL might
349 also call SUBST, we have to compute it before we put anything into
352 #define SUBST(INTO, NEWVAL) \
353 do { rtx _new = (NEWVAL); \
357 _buf = undobuf.frees, undobuf.frees = _buf->next; \
359 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
362 _buf->where.r = &INTO; \
363 _buf->old_contents.r = INTO; \
365 if (_buf->old_contents.r == INTO) \
366 _buf->next = undobuf.frees, undobuf.frees = _buf; \
368 _buf->next = undobuf.undos, undobuf.undos = _buf; \
371 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
372 for the value of a HOST_WIDE_INT value (including CONST_INT) is
375 #define SUBST_INT(INTO, NEWVAL) \
376 do { struct undo *_buf; \
379 _buf = undobuf.frees, undobuf.frees = _buf->next; \
381 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
384 _buf->where.i = (int *) &INTO; \
385 _buf->old_contents.i = INTO; \
387 if (_buf->old_contents.i == INTO) \
388 _buf->next = undobuf.frees, undobuf.frees = _buf; \
390 _buf->next = undobuf.undos, undobuf.undos = _buf; \
393 /* Number of times the pseudo being substituted for
394 was found and replaced. */
396 static int n_occurrences;
398 static void init_reg_last_arrays PROTO((void));
399 static void setup_incoming_promotions PROTO((void));
400 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
401 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
402 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
403 static rtx try_combine PROTO((rtx, rtx, rtx));
404 static void undo_all PROTO((void));
405 static rtx *find_split_point PROTO((rtx *, rtx));
406 static rtx subst PROTO((rtx, rtx, rtx, int, int));
407 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
408 static rtx simplify_if_then_else PROTO((rtx));
409 static rtx simplify_set PROTO((rtx));
410 static rtx simplify_logical PROTO((rtx, int));
411 static rtx expand_compound_operation PROTO((rtx));
412 static rtx expand_field_assignment PROTO((rtx));
413 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
415 static rtx extract_left_shift PROTO((rtx, int));
416 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
417 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
418 static rtx force_to_mode PROTO((rtx, enum machine_mode,
419 unsigned HOST_WIDE_INT, rtx, int));
420 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
421 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
422 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
423 static rtx make_field_assignment PROTO((rtx));
424 static rtx apply_distributive_law PROTO((rtx));
425 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
426 unsigned HOST_WIDE_INT));
427 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
428 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
429 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
430 enum rtx_code, HOST_WIDE_INT,
431 enum machine_mode, int *));
432 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
434 static int recog_for_combine PROTO((rtx *, rtx, rtx *, int *));
435 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
436 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
438 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
440 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
441 enum machine_mode, rtx));
442 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
443 static int reversible_comparison_p PROTO((rtx));
444 static void update_table_tick PROTO((rtx));
445 static void record_value_for_reg PROTO((rtx, rtx, rtx));
446 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
447 static void record_dead_and_set_regs PROTO((rtx));
448 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
449 static rtx get_last_value PROTO((rtx));
450 static int use_crosses_set_p PROTO((rtx, int));
451 static void reg_dead_at_p_1 PROTO((rtx, rtx));
452 static int reg_dead_at_p PROTO((rtx, rtx));
453 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
454 static int reg_bitfield_target_p PROTO((rtx, rtx));
455 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
456 static void distribute_links PROTO((rtx));
457 static void mark_used_regs_combine PROTO((rtx));
458 static int insn_cuid PROTO((rtx));
460 /* Main entry point for combiner. F is the first insn of the function.
461 NREGS is the first unused pseudo-reg number. */
464 combine_instructions (f, nregs)
468 register rtx insn, next, prev;
470 register rtx links, nextlinks;
472 combine_attempts = 0;
475 combine_successes = 0;
476 undobuf.undos = undobuf.previous_undos = 0;
478 combine_max_regno = nregs;
481 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
482 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
484 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
485 bzero (reg_sign_bit_copies, nregs * sizeof (char));
487 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
489 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
490 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
491 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
492 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
494 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
495 reg_last_set_nonzero_bits
496 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
497 reg_last_set_sign_bit_copies
498 = (char *) alloca (nregs * sizeof (char));
500 init_reg_last_arrays ();
502 init_recog_no_volatile ();
504 /* Compute maximum uid value so uid_cuid can be allocated. */
506 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
507 if (INSN_UID (insn) > i)
510 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
513 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
515 /* Don't use reg_nonzero_bits when computing it. This can cause problems
516 when, for example, we have j <<= 1 in a loop. */
518 nonzero_sign_valid = 0;
520 /* Compute the mapping from uids to cuids.
521 Cuids are numbers assigned to insns, like uids,
522 except that cuids increase monotonically through the code.
524 Scan all SETs and see if we can deduce anything about what
525 bits are known to be zero for some registers and how many copies
526 of the sign bit are known to exist for those registers.
528 Also set any known values so that we can use it while searching
529 for what bits are known to be set. */
533 /* We need to initialize it here, because record_dead_and_set_regs may call
535 subst_prev_insn = NULL_RTX;
537 setup_incoming_promotions ();
539 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
541 uid_cuid[INSN_UID (insn)] = ++i;
545 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
547 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
548 record_dead_and_set_regs (insn);
551 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
552 if (REG_NOTE_KIND (links) == REG_INC)
553 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
557 if (GET_CODE (insn) == CODE_LABEL)
561 nonzero_sign_valid = 1;
563 /* Now scan all the insns in forward order. */
565 this_basic_block = -1;
569 init_reg_last_arrays ();
570 setup_incoming_promotions ();
572 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
576 /* If INSN starts a new basic block, update our basic block number. */
577 if (this_basic_block + 1 < n_basic_blocks
578 && basic_block_head[this_basic_block + 1] == insn)
581 if (GET_CODE (insn) == CODE_LABEL)
584 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
586 /* Try this insn with each insn it links back to. */
588 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
589 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
592 /* Try each sequence of three linked insns ending with this one. */
594 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
595 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
596 nextlinks = XEXP (nextlinks, 1))
597 if ((next = try_combine (insn, XEXP (links, 0),
598 XEXP (nextlinks, 0))) != 0)
602 /* Try to combine a jump insn that uses CC0
603 with a preceding insn that sets CC0, and maybe with its
604 logical predecessor as well.
605 This is how we make decrement-and-branch insns.
606 We need this special code because data flow connections
607 via CC0 do not get entered in LOG_LINKS. */
609 if (GET_CODE (insn) == JUMP_INSN
610 && (prev = prev_nonnote_insn (insn)) != 0
611 && GET_CODE (prev) == INSN
612 && sets_cc0_p (PATTERN (prev)))
614 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
617 for (nextlinks = LOG_LINKS (prev); nextlinks;
618 nextlinks = XEXP (nextlinks, 1))
619 if ((next = try_combine (insn, prev,
620 XEXP (nextlinks, 0))) != 0)
624 /* Do the same for an insn that explicitly references CC0. */
625 if (GET_CODE (insn) == INSN
626 && (prev = prev_nonnote_insn (insn)) != 0
627 && GET_CODE (prev) == INSN
628 && sets_cc0_p (PATTERN (prev))
629 && GET_CODE (PATTERN (insn)) == SET
630 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
632 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
635 for (nextlinks = LOG_LINKS (prev); nextlinks;
636 nextlinks = XEXP (nextlinks, 1))
637 if ((next = try_combine (insn, prev,
638 XEXP (nextlinks, 0))) != 0)
642 /* Finally, see if any of the insns that this insn links to
643 explicitly references CC0. If so, try this insn, that insn,
644 and its predecessor if it sets CC0. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 if (GET_CODE (XEXP (links, 0)) == INSN
647 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
648 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
649 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
650 && GET_CODE (prev) == INSN
651 && sets_cc0_p (PATTERN (prev))
652 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
656 /* Try combining an insn with two different insns whose results it
658 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
659 for (nextlinks = XEXP (links, 1); nextlinks;
660 nextlinks = XEXP (nextlinks, 1))
661 if ((next = try_combine (insn, XEXP (links, 0),
662 XEXP (nextlinks, 0))) != 0)
665 if (GET_CODE (insn) != NOTE)
666 record_dead_and_set_regs (insn);
673 total_attempts += combine_attempts;
674 total_merges += combine_merges;
675 total_extras += combine_extras;
676 total_successes += combine_successes;
678 nonzero_sign_valid = 0;
681 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
684 init_reg_last_arrays ()
686 int nregs = combine_max_regno;
688 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
689 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
692 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
693 bzero (reg_last_set_invalid, nregs * sizeof (char));
694 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
695 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
696 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
699 /* Set up any promoted values for incoming argument registers. */
702 setup_incoming_promotions ()
704 #ifdef PROMOTE_FUNCTION_ARGS
707 enum machine_mode mode;
709 rtx first = get_insns ();
711 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
712 if (FUNCTION_ARG_REGNO_P (regno)
713 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
714 record_value_for_reg (reg, first,
715 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
717 gen_rtx (CLOBBER, mode, const0_rtx)));
721 /* Called via note_stores. If X is a pseudo that is narrower than
722 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
724 If we are setting only a portion of X and we can't figure out what
725 portion, assume all bits will be used since we don't know what will
728 Similarly, set how many bits of X are known to be copies of the sign bit
729 at all locations in the function. This is the smallest number implied
733 set_nonzero_bits_and_sign_copies (x, set)
739 if (GET_CODE (x) == REG
740 && REGNO (x) >= FIRST_PSEUDO_REGISTER
741 /* If this register is undefined at the start of the file, we can't
742 say what its contents were. */
743 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], REGNO (x))
744 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
746 if (set == 0 || GET_CODE (set) == CLOBBER)
748 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
749 reg_sign_bit_copies[REGNO (x)] = 1;
753 /* If this is a complex assignment, see if we can convert it into a
754 simple assignment. */
755 set = expand_field_assignment (set);
757 /* If this is a simple assignment, or we have a paradoxical SUBREG,
758 set what we know about X. */
760 if (SET_DEST (set) == x
761 || (GET_CODE (SET_DEST (set)) == SUBREG
762 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
763 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
764 && SUBREG_REG (SET_DEST (set)) == x))
766 rtx src = SET_SRC (set);
768 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
769 /* If X is narrower than a word and SRC is a non-negative
770 constant that would appear negative in the mode of X,
771 sign-extend it for use in reg_nonzero_bits because some
772 machines (maybe most) will actually do the sign-extension
773 and this is the conservative approach.
775 ??? For 2.5, try to tighten up the MD files in this regard
776 instead of this kludge. */
778 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
779 && GET_CODE (src) == CONST_INT
781 && 0 != (INTVAL (src)
783 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
784 src = GEN_INT (INTVAL (src)
785 | ((HOST_WIDE_INT) (-1)
786 << GET_MODE_BITSIZE (GET_MODE (x))));
789 reg_nonzero_bits[REGNO (x)]
790 |= nonzero_bits (src, nonzero_bits_mode);
791 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
792 if (reg_sign_bit_copies[REGNO (x)] == 0
793 || reg_sign_bit_copies[REGNO (x)] > num)
794 reg_sign_bit_copies[REGNO (x)] = num;
798 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
799 reg_sign_bit_copies[REGNO (x)] = 1;
804 /* See if INSN can be combined into I3. PRED and SUCC are optionally
805 insns that were previously combined into I3 or that will be combined
806 into the merger of INSN and I3.
808 Return 0 if the combination is not allowed for any reason.
810 If the combination is allowed, *PDEST will be set to the single
811 destination of INSN and *PSRC to the single source, and this function
815 can_combine_p (insn, i3, pred, succ, pdest, psrc)
822 rtx set = 0, src, dest;
824 int all_adjacent = (succ ? (next_active_insn (insn) == succ
825 && next_active_insn (succ) == i3)
826 : next_active_insn (insn) == i3);
828 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
829 or a PARALLEL consisting of such a SET and CLOBBERs.
831 If INSN has CLOBBER parallel parts, ignore them for our processing.
832 By definition, these happen during the execution of the insn. When it
833 is merged with another insn, all bets are off. If they are, in fact,
834 needed and aren't also supplied in I3, they may be added by
835 recog_for_combine. Otherwise, it won't match.
837 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
840 Get the source and destination of INSN. If more than one, can't
843 if (GET_CODE (PATTERN (insn)) == SET)
844 set = PATTERN (insn);
845 else if (GET_CODE (PATTERN (insn)) == PARALLEL
846 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
848 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
850 rtx elt = XVECEXP (PATTERN (insn), 0, i);
852 switch (GET_CODE (elt))
854 /* We can ignore CLOBBERs. */
859 /* Ignore SETs whose result isn't used but not those that
860 have side-effects. */
861 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
862 && ! side_effects_p (elt))
865 /* If we have already found a SET, this is a second one and
866 so we cannot combine with this insn. */
874 /* Anything else means we can't combine. */
880 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
881 so don't do anything with it. */
882 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
891 set = expand_field_assignment (set);
892 src = SET_SRC (set), dest = SET_DEST (set);
894 /* Don't eliminate a store in the stack pointer. */
895 if (dest == stack_pointer_rtx
896 /* If we couldn't eliminate a field assignment, we can't combine. */
897 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
898 /* Don't combine with an insn that sets a register to itself if it has
899 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
900 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
901 /* Can't merge a function call. */
902 || GET_CODE (src) == CALL
903 /* Don't eliminate a function call argument. */
904 || (GET_CODE (i3) == CALL_INSN
905 && (find_reg_fusage (i3, USE, dest)
906 || (GET_CODE (dest) == REG
907 && REGNO (dest) < FIRST_PSEUDO_REGISTER
908 && global_regs[REGNO (dest)])))
909 /* Don't substitute into an incremented register. */
910 || FIND_REG_INC_NOTE (i3, dest)
911 || (succ && FIND_REG_INC_NOTE (succ, dest))
912 /* Don't combine the end of a libcall into anything. */
913 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
914 /* Make sure that DEST is not used after SUCC but before I3. */
915 || (succ && ! all_adjacent
916 && reg_used_between_p (dest, succ, i3))
917 /* Make sure that the value that is to be substituted for the register
918 does not use any registers whose values alter in between. However,
919 If the insns are adjacent, a use can't cross a set even though we
920 think it might (this can happen for a sequence of insns each setting
921 the same destination; reg_last_set of that register might point to
922 a NOTE). If INSN has a REG_EQUIV note, the register is always
923 equivalent to the memory so the substitution is valid even if there
924 are intervening stores. Also, don't move a volatile asm or
925 UNSPEC_VOLATILE across any other insns. */
927 && (((GET_CODE (src) != MEM
928 || ! find_reg_note (insn, REG_EQUIV, src))
929 && use_crosses_set_p (src, INSN_CUID (insn)))
930 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
931 || GET_CODE (src) == UNSPEC_VOLATILE))
932 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
933 better register allocation by not doing the combine. */
934 || find_reg_note (i3, REG_NO_CONFLICT, dest)
935 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
936 /* Don't combine across a CALL_INSN, because that would possibly
937 change whether the life span of some REGs crosses calls or not,
938 and it is a pain to update that information.
939 Exception: if source is a constant, moving it later can't hurt.
940 Accept that special case, because it helps -fforce-addr a lot. */
941 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
944 /* DEST must either be a REG or CC0. */
945 if (GET_CODE (dest) == REG)
947 /* If register alignment is being enforced for multi-word items in all
948 cases except for parameters, it is possible to have a register copy
949 insn referencing a hard register that is not allowed to contain the
950 mode being copied and which would not be valid as an operand of most
951 insns. Eliminate this problem by not combining with such an insn.
953 Also, on some machines we don't want to extend the life of a hard
956 This is the same test done in can_combine except that we don't test
957 if SRC is a CALL operation to permit a hard register with
958 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
961 if (GET_CODE (src) == REG
962 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
963 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
964 /* Don't extend the life of a hard register unless it is
965 user variable (if we have few registers) or it can't
966 fit into the desired register (meaning something special
968 Also avoid substituting a return register into I3, because
969 reload can't handle a conflict with constraints of other
971 || (REGNO (src) < FIRST_PSEUDO_REGISTER
972 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
973 || (SMALL_REGISTER_CLASSES
974 && ((! all_adjacent && ! REG_USERVAR_P (src))
975 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
976 && ! REG_USERVAR_P (src))))))))
979 else if (GET_CODE (dest) != CC0)
982 /* Don't substitute for a register intended as a clobberable operand.
983 Similarly, don't substitute an expression containing a register that
984 will be clobbered in I3. */
985 if (GET_CODE (PATTERN (i3)) == PARALLEL)
986 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
987 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
988 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
990 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
993 /* If INSN contains anything volatile, or is an `asm' (whether volatile
994 or not), reject, unless nothing volatile comes between it and I3,
995 with the exception of SUCC. */
997 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
998 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
999 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1000 && p != succ && volatile_refs_p (PATTERN (p)))
1003 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1004 to be an explicit register variable, and was chosen for a reason. */
1006 if (GET_CODE (src) == ASM_OPERANDS
1007 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1010 /* If there are any volatile insns between INSN and I3, reject, because
1011 they might affect machine state. */
1013 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1014 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1015 && p != succ && volatile_insn_p (PATTERN (p)))
1018 /* If INSN or I2 contains an autoincrement or autodecrement,
1019 make sure that register is not used between there and I3,
1020 and not already used in I3 either.
1021 Also insist that I3 not be a jump; if it were one
1022 and the incremented register were spilled, we would lose. */
1025 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1026 if (REG_NOTE_KIND (link) == REG_INC
1027 && (GET_CODE (i3) == JUMP_INSN
1028 || reg_used_between_p (XEXP (link, 0), insn, i3)
1029 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1034 /* Don't combine an insn that follows a CC0-setting insn.
1035 An insn that uses CC0 must not be separated from the one that sets it.
1036 We do, however, allow I2 to follow a CC0-setting insn if that insn
1037 is passed as I1; in that case it will be deleted also.
1038 We also allow combining in this case if all the insns are adjacent
1039 because that would leave the two CC0 insns adjacent as well.
1040 It would be more logical to test whether CC0 occurs inside I1 or I2,
1041 but that would be much slower, and this ought to be equivalent. */
1043 p = prev_nonnote_insn (insn);
1044 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1049 /* If we get here, we have passed all the tests and the combination is
1058 /* LOC is the location within I3 that contains its pattern or the component
1059 of a PARALLEL of the pattern. We validate that it is valid for combining.
1061 One problem is if I3 modifies its output, as opposed to replacing it
1062 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1063 so would produce an insn that is not equivalent to the original insns.
1067 (set (reg:DI 101) (reg:DI 100))
1068 (set (subreg:SI (reg:DI 101) 0) <foo>)
1070 This is NOT equivalent to:
1072 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1073 (set (reg:DI 101) (reg:DI 100))])
1075 Not only does this modify 100 (in which case it might still be valid
1076 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1078 We can also run into a problem if I2 sets a register that I1
1079 uses and I1 gets directly substituted into I3 (not via I2). In that
1080 case, we would be getting the wrong value of I2DEST into I3, so we
1081 must reject the combination. This case occurs when I2 and I1 both
1082 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1083 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1084 of a SET must prevent combination from occurring.
1086 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1087 if the destination of a SET is a hard register that isn't a user
1090 Before doing the above check, we first try to expand a field assignment
1091 into a set of logical operations.
1093 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1094 we place a register that is both set and used within I3. If more than one
1095 such register is detected, we fail.
1097 Return 1 if the combination is valid, zero otherwise. */
1100 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1106 rtx *pi3dest_killed;
1110 if (GET_CODE (x) == SET)
1112 rtx set = expand_field_assignment (x);
1113 rtx dest = SET_DEST (set);
1114 rtx src = SET_SRC (set);
1115 rtx inner_dest = dest, inner_src = src;
1119 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1120 || GET_CODE (inner_dest) == SUBREG
1121 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1122 inner_dest = XEXP (inner_dest, 0);
1124 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1127 while (GET_CODE (inner_src) == STRICT_LOW_PART
1128 || GET_CODE (inner_src) == SUBREG
1129 || GET_CODE (inner_src) == ZERO_EXTRACT)
1130 inner_src = XEXP (inner_src, 0);
1132 /* If it is better that two different modes keep two different pseudos,
1133 avoid combining them. This avoids producing the following pattern
1135 (set (subreg:SI (reg/v:QI 21) 0)
1136 (lshiftrt:SI (reg/v:SI 20)
1138 If that were made, reload could not handle the pair of
1139 reg 20/21, since it would try to get any GENERAL_REGS
1140 but some of them don't handle QImode. */
1142 if (rtx_equal_p (inner_src, i2dest)
1143 && GET_CODE (inner_dest) == REG
1144 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1148 /* Check for the case where I3 modifies its output, as
1150 if ((inner_dest != dest
1151 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1152 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1153 /* This is the same test done in can_combine_p except that we
1154 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1156 Moreover, we can't test all_adjacent; we don't have to, since
1157 this instruction will stay in place, thus we are not considering
1158 to increase the lifetime of INNER_DEST. */
1159 || (GET_CODE (inner_dest) == REG
1160 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1161 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1162 GET_MODE (inner_dest))
1163 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1164 && ! REG_USERVAR_P (inner_dest)
1165 && FUNCTION_VALUE_REGNO_P (REGNO (inner_dest)))))
1166 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1169 /* If DEST is used in I3, it is being killed in this insn,
1170 so record that for later.
1171 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1172 STACK_POINTER_REGNUM, since these are always considered to be
1173 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1174 if (pi3dest_killed && GET_CODE (dest) == REG
1175 && reg_referenced_p (dest, PATTERN (i3))
1176 && REGNO (dest) != FRAME_POINTER_REGNUM
1177 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1178 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1180 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1181 && (REGNO (dest) != ARG_POINTER_REGNUM
1182 || ! fixed_regs [REGNO (dest)])
1184 && REGNO (dest) != STACK_POINTER_REGNUM)
1186 if (*pi3dest_killed)
1189 *pi3dest_killed = dest;
1193 else if (GET_CODE (x) == PARALLEL)
1197 for (i = 0; i < XVECLEN (x, 0); i++)
1198 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1199 i1_not_in_src, pi3dest_killed))
1206 /* Try to combine the insns I1 and I2 into I3.
1207 Here I1 and I2 appear earlier than I3.
1208 I1 can be zero; then we combine just I2 into I3.
1210 It we are combining three insns and the resulting insn is not recognized,
1211 try splitting it into two insns. If that happens, I2 and I3 are retained
1212 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1215 Return 0 if the combination does not work. Then nothing is changed.
1216 If we did the combination, return the insn at which combine should
1220 try_combine (i3, i2, i1)
1221 register rtx i3, i2, i1;
1223 /* New patterns for I3 and I3, respectively. */
1224 rtx newpat, newi2pat = 0;
1225 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1226 int added_sets_1, added_sets_2;
1227 /* Total number of SETs to put into I3. */
1229 /* Nonzero is I2's body now appears in I3. */
1231 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1232 int insn_code_number, i2_code_number, other_code_number;
1233 /* Contains I3 if the destination of I3 is used in its source, which means
1234 that the old life of I3 is being killed. If that usage is placed into
1235 I2 and not in I3, a REG_DEAD note must be made. */
1236 rtx i3dest_killed = 0;
1237 /* SET_DEST and SET_SRC of I2 and I1. */
1238 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1239 /* PATTERN (I2), or a copy of it in certain cases. */
1241 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1242 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1243 int i1_feeds_i3 = 0;
1244 /* Notes that must be added to REG_NOTES in I3 and I2. */
1245 rtx new_i3_notes, new_i2_notes;
1246 /* Notes that we substituted I3 into I2 instead of the normal case. */
1247 int i3_subst_into_i2 = 0;
1248 /* Notes that I1, I2 or I3 is a MULT operation. */
1250 /* Number of clobbers of SCRATCH we had to add. */
1251 int i3_scratches = 0, i2_scratches = 0, other_scratches = 0;
1258 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1259 This can occur when flow deletes an insn that it has merged into an
1260 auto-increment address. We also can't do anything if I3 has a
1261 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1264 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1265 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1266 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1267 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1272 undobuf.undos = undobuf.previous_undos = 0;
1273 undobuf.other_insn = 0;
1275 /* Save the current high-water-mark so we can free storage if we didn't
1276 accept this combination. */
1277 undobuf.storage = (char *) oballoc (0);
1279 /* Reset the hard register usage information. */
1280 CLEAR_HARD_REG_SET (newpat_used_regs);
1282 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1283 code below, set I1 to be the earlier of the two insns. */
1284 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1285 temp = i1, i1 = i2, i2 = temp;
1287 added_links_insn = 0;
1289 /* First check for one important special-case that the code below will
1290 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1291 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1292 we may be able to replace that destination with the destination of I3.
1293 This occurs in the common code where we compute both a quotient and
1294 remainder into a structure, in which case we want to do the computation
1295 directly into the structure to avoid register-register copies.
1297 We make very conservative checks below and only try to handle the
1298 most common cases of this. For example, we only handle the case
1299 where I2 and I3 are adjacent to avoid making difficult register
1302 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1303 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1304 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1305 && (! SMALL_REGISTER_CLASSES
1306 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1307 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1308 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1309 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1310 && GET_CODE (PATTERN (i2)) == PARALLEL
1311 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1312 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1313 below would need to check what is inside (and reg_overlap_mentioned_p
1314 doesn't support those codes anyway). Don't allow those destinations;
1315 the resulting insn isn't likely to be recognized anyway. */
1316 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1317 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1318 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1319 SET_DEST (PATTERN (i3)))
1320 && next_real_insn (i2) == i3)
1322 rtx p2 = PATTERN (i2);
1324 /* Make sure that the destination of I3,
1325 which we are going to substitute into one output of I2,
1326 is not used within another output of I2. We must avoid making this:
1327 (parallel [(set (mem (reg 69)) ...)
1328 (set (reg 69) ...)])
1329 which is not well-defined as to order of actions.
1330 (Besides, reload can't handle output reloads for this.)
1332 The problem can also happen if the dest of I3 is a memory ref,
1333 if another dest in I2 is an indirect memory ref. */
1334 for (i = 0; i < XVECLEN (p2, 0); i++)
1335 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1336 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1337 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1338 SET_DEST (XVECEXP (p2, 0, i))))
1341 if (i == XVECLEN (p2, 0))
1342 for (i = 0; i < XVECLEN (p2, 0); i++)
1343 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1348 subst_low_cuid = INSN_CUID (i2);
1350 added_sets_2 = added_sets_1 = 0;
1351 i2dest = SET_SRC (PATTERN (i3));
1353 /* Replace the dest in I2 with our dest and make the resulting
1354 insn the new pattern for I3. Then skip to where we
1355 validate the pattern. Everything was set up above. */
1356 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1357 SET_DEST (PATTERN (i3)));
1360 i3_subst_into_i2 = 1;
1361 goto validate_replacement;
1366 /* If we have no I1 and I2 looks like:
1367 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1369 make up a dummy I1 that is
1372 (set (reg:CC X) (compare:CC Y (const_int 0)))
1374 (We can ignore any trailing CLOBBERs.)
1376 This undoes a previous combination and allows us to match a branch-and-
1379 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1380 && XVECLEN (PATTERN (i2), 0) >= 2
1381 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1382 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1384 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1385 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1386 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1387 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1388 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1389 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1391 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1392 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1397 /* We make I1 with the same INSN_UID as I2. This gives it
1398 the same INSN_CUID for value tracking. Our fake I1 will
1399 never appear in the insn stream so giving it the same INSN_UID
1400 as I2 will not cause a problem. */
1402 subst_prev_insn = i1
1403 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1404 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX, NULL_RTX);
1406 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1407 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1408 SET_DEST (PATTERN (i1)));
1413 /* Verify that I2 and I1 are valid for combining. */
1414 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1415 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1421 /* Record whether I2DEST is used in I2SRC and similarly for the other
1422 cases. Knowing this will help in register status updating below. */
1423 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1424 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1425 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1427 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1429 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1431 /* Ensure that I3's pattern can be the destination of combines. */
1432 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1433 i1 && i2dest_in_i1src && i1_feeds_i3,
1440 /* See if any of the insns is a MULT operation. Unless one is, we will
1441 reject a combination that is, since it must be slower. Be conservative
1443 if (GET_CODE (i2src) == MULT
1444 || (i1 != 0 && GET_CODE (i1src) == MULT)
1445 || (GET_CODE (PATTERN (i3)) == SET
1446 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1449 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1450 We used to do this EXCEPT in one case: I3 has a post-inc in an
1451 output operand. However, that exception can give rise to insns like
1453 which is a famous insn on the PDP-11 where the value of r3 used as the
1454 source was model-dependent. Avoid this sort of thing. */
1457 if (!(GET_CODE (PATTERN (i3)) == SET
1458 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1459 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1460 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1461 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1462 /* It's not the exception. */
1465 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1466 if (REG_NOTE_KIND (link) == REG_INC
1467 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1469 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1476 /* See if the SETs in I1 or I2 need to be kept around in the merged
1477 instruction: whenever the value set there is still needed past I3.
1478 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1480 For the SET in I1, we have two cases: If I1 and I2 independently
1481 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1482 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1483 in I1 needs to be kept around unless I1DEST dies or is set in either
1484 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1485 I1DEST. If so, we know I1 feeds into I2. */
1487 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1490 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1491 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1493 /* If the set in I2 needs to be kept around, we must make a copy of
1494 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1495 PATTERN (I2), we are only substituting for the original I1DEST, not into
1496 an already-substituted copy. This also prevents making self-referential
1497 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1500 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1501 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1505 i2pat = copy_rtx (i2pat);
1509 /* Substitute in the latest insn for the regs set by the earlier ones. */
1511 maxreg = max_reg_num ();
1515 /* It is possible that the source of I2 or I1 may be performing an
1516 unneeded operation, such as a ZERO_EXTEND of something that is known
1517 to have the high part zero. Handle that case by letting subst look at
1518 the innermost one of them.
1520 Another way to do this would be to have a function that tries to
1521 simplify a single insn instead of merging two or more insns. We don't
1522 do this because of the potential of infinite loops and because
1523 of the potential extra memory required. However, doing it the way
1524 we are is a bit of a kludge and doesn't catch all cases.
1526 But only do this if -fexpensive-optimizations since it slows things down
1527 and doesn't usually win. */
1529 if (flag_expensive_optimizations)
1531 /* Pass pc_rtx so no substitutions are done, just simplifications.
1532 The cases that we are interested in here do not involve the few
1533 cases were is_replaced is checked. */
1536 subst_low_cuid = INSN_CUID (i1);
1537 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1541 subst_low_cuid = INSN_CUID (i2);
1542 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1545 undobuf.previous_undos = undobuf.undos;
1549 /* Many machines that don't use CC0 have insns that can both perform an
1550 arithmetic operation and set the condition code. These operations will
1551 be represented as a PARALLEL with the first element of the vector
1552 being a COMPARE of an arithmetic operation with the constant zero.
1553 The second element of the vector will set some pseudo to the result
1554 of the same arithmetic operation. If we simplify the COMPARE, we won't
1555 match such a pattern and so will generate an extra insn. Here we test
1556 for this case, where both the comparison and the operation result are
1557 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1558 I2SRC. Later we will make the PARALLEL that contains I2. */
1560 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1561 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1562 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1563 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1566 enum machine_mode compare_mode;
1568 newpat = PATTERN (i3);
1569 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1573 #ifdef EXTRA_CC_MODES
1574 /* See if a COMPARE with the operand we substituted in should be done
1575 with the mode that is currently being used. If not, do the same
1576 processing we do in `subst' for a SET; namely, if the destination
1577 is used only once, try to replace it with a register of the proper
1578 mode and also replace the COMPARE. */
1579 if (undobuf.other_insn == 0
1580 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1581 &undobuf.other_insn))
1582 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1584 != GET_MODE (SET_DEST (newpat))))
1586 int regno = REGNO (SET_DEST (newpat));
1587 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1589 if (regno < FIRST_PSEUDO_REGISTER
1590 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1591 && ! REG_USERVAR_P (SET_DEST (newpat))))
1593 if (regno >= FIRST_PSEUDO_REGISTER)
1594 SUBST (regno_reg_rtx[regno], new_dest);
1596 SUBST (SET_DEST (newpat), new_dest);
1597 SUBST (XEXP (*cc_use, 0), new_dest);
1598 SUBST (SET_SRC (newpat),
1599 gen_rtx_combine (COMPARE, compare_mode,
1600 i2src, const0_rtx));
1603 undobuf.other_insn = 0;
1610 n_occurrences = 0; /* `subst' counts here */
1612 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1613 need to make a unique copy of I2SRC each time we substitute it
1614 to avoid self-referential rtl. */
1616 subst_low_cuid = INSN_CUID (i2);
1617 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1618 ! i1_feeds_i3 && i1dest_in_i1src);
1619 undobuf.previous_undos = undobuf.undos;
1621 /* Record whether i2's body now appears within i3's body. */
1622 i2_is_used = n_occurrences;
1625 /* If we already got a failure, don't try to do more. Otherwise,
1626 try to substitute in I1 if we have it. */
1628 if (i1 && GET_CODE (newpat) != CLOBBER)
1630 /* Before we can do this substitution, we must redo the test done
1631 above (see detailed comments there) that ensures that I1DEST
1632 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1634 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1642 subst_low_cuid = INSN_CUID (i1);
1643 newpat = subst (newpat, i1dest, i1src, 0, 0);
1644 undobuf.previous_undos = undobuf.undos;
1647 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1648 to count all the ways that I2SRC and I1SRC can be used. */
1649 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1650 && i2_is_used + added_sets_2 > 1)
1651 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1652 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1654 /* Fail if we tried to make a new register (we used to abort, but there's
1655 really no reason to). */
1656 || max_reg_num () != maxreg
1657 /* Fail if we couldn't do something and have a CLOBBER. */
1658 || GET_CODE (newpat) == CLOBBER
1659 /* Fail if this new pattern is a MULT and we didn't have one before
1660 at the outer level. */
1661 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1668 /* If the actions of the earlier insns must be kept
1669 in addition to substituting them into the latest one,
1670 we must make a new PARALLEL for the latest insn
1671 to hold additional the SETs. */
1673 if (added_sets_1 || added_sets_2)
1677 if (GET_CODE (newpat) == PARALLEL)
1679 rtvec old = XVEC (newpat, 0);
1680 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1681 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1682 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1683 sizeof (old->elem[0]) * old->num_elem);
1688 total_sets = 1 + added_sets_1 + added_sets_2;
1689 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1690 XVECEXP (newpat, 0, 0) = old;
1694 XVECEXP (newpat, 0, --total_sets)
1695 = (GET_CODE (PATTERN (i1)) == PARALLEL
1696 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1700 /* If there is no I1, use I2's body as is. We used to also not do
1701 the subst call below if I2 was substituted into I3,
1702 but that could lose a simplification. */
1704 XVECEXP (newpat, 0, --total_sets) = i2pat;
1706 /* See comment where i2pat is assigned. */
1707 XVECEXP (newpat, 0, --total_sets)
1708 = subst (i2pat, i1dest, i1src, 0, 0);
1712 /* We come here when we are replacing a destination in I2 with the
1713 destination of I3. */
1714 validate_replacement:
1716 /* Note which hard regs this insn has as inputs. */
1717 mark_used_regs_combine (newpat);
1719 /* Is the result of combination a valid instruction? */
1721 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1723 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1724 the second SET's destination is a register that is unused. In that case,
1725 we just need the first SET. This can occur when simplifying a divmod
1726 insn. We *must* test for this case here because the code below that
1727 splits two independent SETs doesn't handle this case correctly when it
1728 updates the register status. Also check the case where the first
1729 SET's destination is unused. That would not cause incorrect code, but
1730 does cause an unneeded insn to remain. */
1732 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1733 && XVECLEN (newpat, 0) == 2
1734 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1735 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1736 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1737 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1738 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1739 && asm_noperands (newpat) < 0)
1741 newpat = XVECEXP (newpat, 0, 0);
1743 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1746 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1747 && XVECLEN (newpat, 0) == 2
1748 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1749 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1750 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1751 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1752 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1753 && asm_noperands (newpat) < 0)
1755 newpat = XVECEXP (newpat, 0, 1);
1757 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1760 /* If we were combining three insns and the result is a simple SET
1761 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1762 insns. There are two ways to do this. It can be split using a
1763 machine-specific method (like when you have an addition of a large
1764 constant) or by combine in the function find_split_point. */
1766 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1767 && asm_noperands (newpat) < 0)
1769 rtx m_split, *split;
1770 rtx ni2dest = i2dest;
1772 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1773 use I2DEST as a scratch register will help. In the latter case,
1774 convert I2DEST to the mode of the source of NEWPAT if we can. */
1776 m_split = split_insns (newpat, i3);
1778 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1779 inputs of NEWPAT. */
1781 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1782 possible to try that as a scratch reg. This would require adding
1783 more code to make it work though. */
1785 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1787 /* If I2DEST is a hard register or the only use of a pseudo,
1788 we can change its mode. */
1789 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1790 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1791 && GET_CODE (i2dest) == REG
1792 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1793 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1794 && ! REG_USERVAR_P (i2dest))))
1795 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1798 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1799 gen_rtvec (2, newpat,
1806 if (m_split && GET_CODE (m_split) == SEQUENCE
1807 && XVECLEN (m_split, 0) == 2
1808 && (next_real_insn (i2) == i3
1809 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1813 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1814 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1816 i3set = single_set (XVECEXP (m_split, 0, 1));
1817 i2set = single_set (XVECEXP (m_split, 0, 0));
1819 /* In case we changed the mode of I2DEST, replace it in the
1820 pseudo-register table here. We can't do it above in case this
1821 code doesn't get executed and we do a split the other way. */
1823 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1824 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1826 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes,
1829 /* If I2 or I3 has multiple SETs, we won't know how to track
1830 register status, so don't use these insns. If I2's destination
1831 is used between I2 and I3, we also can't use these insns. */
1833 if (i2_code_number >= 0 && i2set && i3set
1834 && (next_real_insn (i2) == i3
1835 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1836 insn_code_number = recog_for_combine (&newi3pat, i3, &new_i3_notes,
1838 if (insn_code_number >= 0)
1841 /* It is possible that both insns now set the destination of I3.
1842 If so, we must show an extra use of it. */
1844 if (insn_code_number >= 0)
1846 rtx new_i3_dest = SET_DEST (i3set);
1847 rtx new_i2_dest = SET_DEST (i2set);
1849 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1850 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1851 || GET_CODE (new_i3_dest) == SUBREG)
1852 new_i3_dest = XEXP (new_i3_dest, 0);
1854 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1855 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1856 || GET_CODE (new_i2_dest) == SUBREG)
1857 new_i2_dest = XEXP (new_i2_dest, 0);
1859 if (GET_CODE (new_i3_dest) == REG
1860 && GET_CODE (new_i2_dest) == REG
1861 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1862 REG_N_SETS (REGNO (new_i2_dest))++;
1866 /* If we can split it and use I2DEST, go ahead and see if that
1867 helps things be recognized. Verify that none of the registers
1868 are set between I2 and I3. */
1869 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1871 && GET_CODE (i2dest) == REG
1873 /* We need I2DEST in the proper mode. If it is a hard register
1874 or the only use of a pseudo, we can change its mode. */
1875 && (GET_MODE (*split) == GET_MODE (i2dest)
1876 || GET_MODE (*split) == VOIDmode
1877 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1878 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1879 && ! REG_USERVAR_P (i2dest)))
1880 && (next_real_insn (i2) == i3
1881 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1882 /* We can't overwrite I2DEST if its value is still used by
1884 && ! reg_referenced_p (i2dest, newpat))
1886 rtx newdest = i2dest;
1887 enum rtx_code split_code = GET_CODE (*split);
1888 enum machine_mode split_mode = GET_MODE (*split);
1890 /* Get NEWDEST as a register in the proper mode. We have already
1891 validated that we can do this. */
1892 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
1894 newdest = gen_rtx (REG, split_mode, REGNO (i2dest));
1896 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1897 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1900 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1901 an ASHIFT. This can occur if it was inside a PLUS and hence
1902 appeared to be a memory address. This is a kludge. */
1903 if (split_code == MULT
1904 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1905 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1907 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
1908 XEXP (*split, 0), GEN_INT (i)));
1909 /* Update split_code because we may not have a multiply
1911 split_code = GET_CODE (*split);
1914 #ifdef INSN_SCHEDULING
1915 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1916 be written as a ZERO_EXTEND. */
1917 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
1918 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
1922 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1923 SUBST (*split, newdest);
1925 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1927 /* If the split point was a MULT and we didn't have one before,
1928 don't use one now. */
1929 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
1931 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1935 /* Check for a case where we loaded from memory in a narrow mode and
1936 then sign extended it, but we need both registers. In that case,
1937 we have a PARALLEL with both loads from the same memory location.
1938 We can split this into a load from memory followed by a register-register
1939 copy. This saves at least one insn, more if register allocation can
1942 We cannot do this if the destination of the second assignment is
1943 a register that we have already assumed is zero-extended. Similarly
1944 for a SUBREG of such a register. */
1946 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1947 && GET_CODE (newpat) == PARALLEL
1948 && XVECLEN (newpat, 0) == 2
1949 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1950 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1951 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1952 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1953 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1954 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1956 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1957 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1958 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
1959 (GET_CODE (temp) == REG
1960 && reg_nonzero_bits[REGNO (temp)] != 0
1961 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1962 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1963 && (reg_nonzero_bits[REGNO (temp)]
1964 != GET_MODE_MASK (word_mode))))
1965 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
1966 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
1967 (GET_CODE (temp) == REG
1968 && reg_nonzero_bits[REGNO (temp)] != 0
1969 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
1970 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
1971 && (reg_nonzero_bits[REGNO (temp)]
1972 != GET_MODE_MASK (word_mode)))))
1973 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1974 SET_SRC (XVECEXP (newpat, 0, 1)))
1975 && ! find_reg_note (i3, REG_UNUSED,
1976 SET_DEST (XVECEXP (newpat, 0, 0))))
1980 newi2pat = XVECEXP (newpat, 0, 0);
1981 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1982 newpat = XVECEXP (newpat, 0, 1);
1983 SUBST (SET_SRC (newpat),
1984 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1986 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
1988 if (i2_code_number >= 0)
1990 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
1992 if (insn_code_number >= 0)
1997 /* If we will be able to accept this, we have made a change to the
1998 destination of I3. This can invalidate a LOG_LINKS pointing
1999 to I3. No other part of combine.c makes such a transformation.
2001 The new I3 will have a destination that was previously the
2002 destination of I1 or I2 and which was used in i2 or I3. Call
2003 distribute_links to make a LOG_LINK from the next use of
2004 that destination. */
2006 PATTERN (i3) = newpat;
2007 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
2009 /* I3 now uses what used to be its destination and which is
2010 now I2's destination. That means we need a LOG_LINK from
2011 I3 to I2. But we used to have one, so we still will.
2013 However, some later insn might be using I2's dest and have
2014 a LOG_LINK pointing at I3. We must remove this link.
2015 The simplest way to remove the link is to point it at I1,
2016 which we know will be a NOTE. */
2018 for (insn = NEXT_INSN (i3);
2019 insn && (this_basic_block == n_basic_blocks - 1
2020 || insn != basic_block_head[this_basic_block + 1]);
2021 insn = NEXT_INSN (insn))
2023 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2024 && reg_referenced_p (ni2dest, PATTERN (insn)))
2026 for (link = LOG_LINKS (insn); link;
2027 link = XEXP (link, 1))
2028 if (XEXP (link, 0) == i3)
2029 XEXP (link, 0) = i1;
2037 /* Similarly, check for a case where we have a PARALLEL of two independent
2038 SETs but we started with three insns. In this case, we can do the sets
2039 as two separate insns. This case occurs when some SET allows two
2040 other insns to combine, but the destination of that SET is still live. */
2042 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2043 && GET_CODE (newpat) == PARALLEL
2044 && XVECLEN (newpat, 0) == 2
2045 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2046 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2047 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2048 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2049 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2050 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2051 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2053 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2054 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2056 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2057 XVECEXP (newpat, 0, 0))
2058 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2059 XVECEXP (newpat, 0, 1)))
2061 /* Normally, it doesn't matter which of the two is done first,
2062 but it does if one references cc0. In that case, it has to
2065 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2067 newi2pat = XVECEXP (newpat, 0, 0);
2068 newpat = XVECEXP (newpat, 0, 1);
2073 newi2pat = XVECEXP (newpat, 0, 1);
2074 newpat = XVECEXP (newpat, 0, 0);
2078 = recog_for_combine (&newi2pat, i2, &new_i2_notes, &i2_scratches);
2080 if (i2_code_number >= 0)
2082 = recog_for_combine (&newpat, i3, &new_i3_notes, &i3_scratches);
2085 /* If it still isn't recognized, fail and change things back the way they
2087 if ((insn_code_number < 0
2088 /* Is the result a reasonable ASM_OPERANDS? */
2089 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2095 /* If we had to change another insn, make sure it is valid also. */
2096 if (undobuf.other_insn)
2098 rtx other_pat = PATTERN (undobuf.other_insn);
2099 rtx new_other_notes;
2102 CLEAR_HARD_REG_SET (newpat_used_regs);
2105 = recog_for_combine (&other_pat, undobuf.other_insn,
2106 &new_other_notes, &other_scratches);
2108 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2114 PATTERN (undobuf.other_insn) = other_pat;
2116 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2117 are still valid. Then add any non-duplicate notes added by
2118 recog_for_combine. */
2119 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2121 next = XEXP (note, 1);
2123 if (REG_NOTE_KIND (note) == REG_UNUSED
2124 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2126 if (GET_CODE (XEXP (note, 0)) == REG)
2127 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2129 remove_note (undobuf.other_insn, note);
2133 for (note = new_other_notes; note; note = XEXP (note, 1))
2134 if (GET_CODE (XEXP (note, 0)) == REG)
2135 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2137 distribute_notes (new_other_notes, undobuf.other_insn,
2138 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2141 /* We now know that we can do this combination. Merge the insns and
2142 update the status of registers and LOG_LINKS. */
2145 rtx i3notes, i2notes, i1notes = 0;
2146 rtx i3links, i2links, i1links = 0;
2149 /* Compute which registers we expect to eliminate. */
2150 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
2152 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
2154 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2156 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2157 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2159 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2161 /* Ensure that we do not have something that should not be shared but
2162 occurs multiple times in the new insns. Check this by first
2163 resetting all the `used' flags and then copying anything is shared. */
2165 reset_used_flags (i3notes);
2166 reset_used_flags (i2notes);
2167 reset_used_flags (i1notes);
2168 reset_used_flags (newpat);
2169 reset_used_flags (newi2pat);
2170 if (undobuf.other_insn)
2171 reset_used_flags (PATTERN (undobuf.other_insn));
2173 i3notes = copy_rtx_if_shared (i3notes);
2174 i2notes = copy_rtx_if_shared (i2notes);
2175 i1notes = copy_rtx_if_shared (i1notes);
2176 newpat = copy_rtx_if_shared (newpat);
2177 newi2pat = copy_rtx_if_shared (newi2pat);
2178 if (undobuf.other_insn)
2179 reset_used_flags (PATTERN (undobuf.other_insn));
2181 INSN_CODE (i3) = insn_code_number;
2182 PATTERN (i3) = newpat;
2183 if (undobuf.other_insn)
2184 INSN_CODE (undobuf.other_insn) = other_code_number;
2186 /* We had one special case above where I2 had more than one set and
2187 we replaced a destination of one of those sets with the destination
2188 of I3. In that case, we have to update LOG_LINKS of insns later
2189 in this basic block. Note that this (expensive) case is rare.
2191 Also, in this case, we must pretend that all REG_NOTEs for I2
2192 actually came from I3, so that REG_UNUSED notes from I2 will be
2193 properly handled. */
2195 if (i3_subst_into_i2)
2197 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2198 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2199 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2200 && ! find_reg_note (i2, REG_UNUSED,
2201 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2202 for (temp = NEXT_INSN (i2);
2203 temp && (this_basic_block == n_basic_blocks - 1
2204 || basic_block_head[this_basic_block] != temp);
2205 temp = NEXT_INSN (temp))
2206 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2207 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2208 if (XEXP (link, 0) == i2)
2209 XEXP (link, 0) = i3;
2214 while (XEXP (link, 1))
2215 link = XEXP (link, 1);
2216 XEXP (link, 1) = i2notes;
2230 INSN_CODE (i2) = i2_code_number;
2231 PATTERN (i2) = newi2pat;
2235 PUT_CODE (i2, NOTE);
2236 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2237 NOTE_SOURCE_FILE (i2) = 0;
2244 PUT_CODE (i1, NOTE);
2245 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2246 NOTE_SOURCE_FILE (i1) = 0;
2249 /* Get death notes for everything that is now used in either I3 or
2250 I2 and used to die in a previous insn. If we built two new
2251 patterns, move from I1 to I2 then I2 to I3 so that we get the
2252 proper movement on registers that I2 modifies. */
2256 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2257 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2260 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2263 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2265 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2268 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2271 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2274 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2277 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2278 know these are REG_UNUSED and want them to go to the desired insn,
2279 so we always pass it as i3. We have not counted the notes in
2280 reg_n_deaths yet, so we need to do so now. */
2282 if (newi2pat && new_i2_notes)
2284 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2285 if (GET_CODE (XEXP (temp, 0)) == REG)
2286 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2288 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2293 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2294 if (GET_CODE (XEXP (temp, 0)) == REG)
2295 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2297 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2300 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2301 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2302 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2303 in that case, it might delete I2. Similarly for I2 and I1.
2304 Show an additional death due to the REG_DEAD note we make here. If
2305 we discard it in distribute_notes, we will decrement it again. */
2309 if (GET_CODE (i3dest_killed) == REG)
2310 REG_N_DEATHS (REGNO (i3dest_killed))++;
2312 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2313 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2315 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2317 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2319 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2320 NULL_RTX, NULL_RTX);
2323 if (i2dest_in_i2src)
2325 if (GET_CODE (i2dest) == REG)
2326 REG_N_DEATHS (REGNO (i2dest))++;
2328 if (newi2pat && reg_set_p (i2dest, newi2pat))
2329 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2330 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2332 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2333 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2334 NULL_RTX, NULL_RTX);
2337 if (i1dest_in_i1src)
2339 if (GET_CODE (i1dest) == REG)
2340 REG_N_DEATHS (REGNO (i1dest))++;
2342 if (newi2pat && reg_set_p (i1dest, newi2pat))
2343 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2344 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2346 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2347 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2348 NULL_RTX, NULL_RTX);
2351 distribute_links (i3links);
2352 distribute_links (i2links);
2353 distribute_links (i1links);
2355 if (GET_CODE (i2dest) == REG)
2358 rtx i2_insn = 0, i2_val = 0, set;
2360 /* The insn that used to set this register doesn't exist, and
2361 this life of the register may not exist either. See if one of
2362 I3's links points to an insn that sets I2DEST. If it does,
2363 that is now the last known value for I2DEST. If we don't update
2364 this and I2 set the register to a value that depended on its old
2365 contents, we will get confused. If this insn is used, thing
2366 will be set correctly in combine_instructions. */
2368 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2369 if ((set = single_set (XEXP (link, 0))) != 0
2370 && rtx_equal_p (i2dest, SET_DEST (set)))
2371 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2373 record_value_for_reg (i2dest, i2_insn, i2_val);
2375 /* If the reg formerly set in I2 died only once and that was in I3,
2376 zero its use count so it won't make `reload' do any work. */
2378 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2379 && ! i2dest_in_i2src)
2381 regno = REGNO (i2dest);
2382 REG_N_SETS (regno)--;
2383 if (REG_N_SETS (regno) == 0
2384 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2385 REG_N_REFS (regno) = 0;
2389 if (i1 && GET_CODE (i1dest) == REG)
2392 rtx i1_insn = 0, i1_val = 0, set;
2394 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2395 if ((set = single_set (XEXP (link, 0))) != 0
2396 && rtx_equal_p (i1dest, SET_DEST (set)))
2397 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2399 record_value_for_reg (i1dest, i1_insn, i1_val);
2401 regno = REGNO (i1dest);
2402 if (! added_sets_1 && ! i1dest_in_i1src)
2404 REG_N_SETS (regno)--;
2405 if (REG_N_SETS (regno) == 0
2406 && ! REGNO_REG_SET_P (basic_block_live_at_start[0], regno))
2407 REG_N_REFS (regno) = 0;
2411 /* Update reg_nonzero_bits et al for any changes that may have been made
2414 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2416 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2418 /* If we added any (clobber (scratch)), add them to the max for a
2419 block. This is a very pessimistic calculation, since we might
2420 have had them already and this might not be the worst block, but
2421 it's not worth doing any better. */
2422 max_scratch += i3_scratches + i2_scratches + other_scratches;
2424 /* If I3 is now an unconditional jump, ensure that it has a
2425 BARRIER following it since it may have initially been a
2426 conditional jump. It may also be the last nonnote insn. */
2428 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2429 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2430 || GET_CODE (temp) != BARRIER))
2431 emit_barrier_after (i3);
2434 combine_successes++;
2436 /* Clear this here, so that subsequent get_last_value calls are not
2438 subst_prev_insn = NULL_RTX;
2440 if (added_links_insn
2441 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2442 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2443 return added_links_insn;
2445 return newi2pat ? i2 : i3;
2448 /* Undo all the modifications recorded in undobuf. */
2453 struct undo *undo, *next;
2455 for (undo = undobuf.undos; undo; undo = next)
2459 *undo->where.i = undo->old_contents.i;
2461 *undo->where.r = undo->old_contents.r;
2463 undo->next = undobuf.frees;
2464 undobuf.frees = undo;
2467 obfree (undobuf.storage);
2468 undobuf.undos = undobuf.previous_undos = 0;
2470 /* Clear this here, so that subsequent get_last_value calls are not
2472 subst_prev_insn = NULL_RTX;
2475 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2476 where we have an arithmetic expression and return that point. LOC will
2479 try_combine will call this function to see if an insn can be split into
2483 find_split_point (loc, insn)
2488 enum rtx_code code = GET_CODE (x);
2490 int len = 0, pos, unsignedp;
2493 /* First special-case some codes. */
2497 #ifdef INSN_SCHEDULING
2498 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2500 if (GET_CODE (SUBREG_REG (x)) == MEM)
2503 return find_split_point (&SUBREG_REG (x), insn);
2507 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2508 using LO_SUM and HIGH. */
2509 if (GET_CODE (XEXP (x, 0)) == CONST
2510 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2513 gen_rtx_combine (LO_SUM, Pmode,
2514 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2516 return &XEXP (XEXP (x, 0), 0);
2520 /* If we have a PLUS whose second operand is a constant and the
2521 address is not valid, perhaps will can split it up using
2522 the machine-specific way to split large constants. We use
2523 the first pseudo-reg (one of the virtual regs) as a placeholder;
2524 it will not remain in the result. */
2525 if (GET_CODE (XEXP (x, 0)) == PLUS
2526 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2527 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2529 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2530 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2533 /* This should have produced two insns, each of which sets our
2534 placeholder. If the source of the second is a valid address,
2535 we can make put both sources together and make a split point
2538 if (seq && XVECLEN (seq, 0) == 2
2539 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2540 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2541 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2542 && ! reg_mentioned_p (reg,
2543 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2544 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2545 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2546 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2547 && memory_address_p (GET_MODE (x),
2548 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2550 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2551 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2553 /* Replace the placeholder in SRC2 with SRC1. If we can
2554 find where in SRC2 it was placed, that can become our
2555 split point and we can replace this address with SRC2.
2556 Just try two obvious places. */
2558 src2 = replace_rtx (src2, reg, src1);
2560 if (XEXP (src2, 0) == src1)
2561 split = &XEXP (src2, 0);
2562 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2563 && XEXP (XEXP (src2, 0), 0) == src1)
2564 split = &XEXP (XEXP (src2, 0), 0);
2568 SUBST (XEXP (x, 0), src2);
2573 /* If that didn't work, perhaps the first operand is complex and
2574 needs to be computed separately, so make a split point there.
2575 This will occur on machines that just support REG + CONST
2576 and have a constant moved through some previous computation. */
2578 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2579 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2580 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2582 return &XEXP (XEXP (x, 0), 0);
2588 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2589 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2590 we need to put the operand into a register. So split at that
2593 if (SET_DEST (x) == cc0_rtx
2594 && GET_CODE (SET_SRC (x)) != COMPARE
2595 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2596 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2597 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2598 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2599 return &SET_SRC (x);
2602 /* See if we can split SET_SRC as it stands. */
2603 split = find_split_point (&SET_SRC (x), insn);
2604 if (split && split != &SET_SRC (x))
2607 /* See if we can split SET_DEST as it stands. */
2608 split = find_split_point (&SET_DEST (x), insn);
2609 if (split && split != &SET_DEST (x))
2612 /* See if this is a bitfield assignment with everything constant. If
2613 so, this is an IOR of an AND, so split it into that. */
2614 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2615 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2616 <= HOST_BITS_PER_WIDE_INT)
2617 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2618 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2619 && GET_CODE (SET_SRC (x)) == CONST_INT
2620 && ((INTVAL (XEXP (SET_DEST (x), 1))
2621 + INTVAL (XEXP (SET_DEST (x), 2)))
2622 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2623 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2625 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2626 int len = INTVAL (XEXP (SET_DEST (x), 1));
2627 int src = INTVAL (SET_SRC (x));
2628 rtx dest = XEXP (SET_DEST (x), 0);
2629 enum machine_mode mode = GET_MODE (dest);
2630 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2632 if (BITS_BIG_ENDIAN)
2633 pos = GET_MODE_BITSIZE (mode) - len - pos;
2637 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2640 gen_binary (IOR, mode,
2641 gen_binary (AND, mode, dest,
2642 GEN_INT (~ (mask << pos)
2643 & GET_MODE_MASK (mode))),
2644 GEN_INT (src << pos)));
2646 SUBST (SET_DEST (x), dest);
2648 split = find_split_point (&SET_SRC (x), insn);
2649 if (split && split != &SET_SRC (x))
2653 /* Otherwise, see if this is an operation that we can split into two.
2654 If so, try to split that. */
2655 code = GET_CODE (SET_SRC (x));
2660 /* If we are AND'ing with a large constant that is only a single
2661 bit and the result is only being used in a context where we
2662 need to know if it is zero or non-zero, replace it with a bit
2663 extraction. This will avoid the large constant, which might
2664 have taken more than one insn to make. If the constant were
2665 not a valid argument to the AND but took only one insn to make,
2666 this is no worse, but if it took more than one insn, it will
2669 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2670 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2671 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2672 && GET_CODE (SET_DEST (x)) == REG
2673 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2674 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2675 && XEXP (*split, 0) == SET_DEST (x)
2676 && XEXP (*split, 1) == const0_rtx)
2678 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2679 XEXP (SET_SRC (x), 0),
2680 pos, NULL_RTX, 1, 1, 0, 0);
2681 if (extraction != 0)
2683 SUBST (SET_SRC (x), extraction);
2684 return find_split_point (loc, insn);
2690 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2691 is known to be on, this can be converted into a NEG of a shift. */
2692 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2693 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2694 && 1 <= (pos = exact_log2
2695 (nonzero_bits (XEXP (SET_SRC (x), 0),
2696 GET_MODE (XEXP (SET_SRC (x), 0))))))
2698 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2701 gen_rtx_combine (NEG, mode,
2702 gen_rtx_combine (LSHIFTRT, mode,
2703 XEXP (SET_SRC (x), 0),
2706 split = find_split_point (&SET_SRC (x), insn);
2707 if (split && split != &SET_SRC (x))
2713 inner = XEXP (SET_SRC (x), 0);
2715 /* We can't optimize if either mode is a partial integer
2716 mode as we don't know how many bits are significant
2718 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2719 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2723 len = GET_MODE_BITSIZE (GET_MODE (inner));
2729 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2730 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2732 inner = XEXP (SET_SRC (x), 0);
2733 len = INTVAL (XEXP (SET_SRC (x), 1));
2734 pos = INTVAL (XEXP (SET_SRC (x), 2));
2736 if (BITS_BIG_ENDIAN)
2737 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2738 unsignedp = (code == ZERO_EXTRACT);
2746 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2748 enum machine_mode mode = GET_MODE (SET_SRC (x));
2750 /* For unsigned, we have a choice of a shift followed by an
2751 AND or two shifts. Use two shifts for field sizes where the
2752 constant might be too large. We assume here that we can
2753 always at least get 8-bit constants in an AND insn, which is
2754 true for every current RISC. */
2756 if (unsignedp && len <= 8)
2761 gen_rtx_combine (LSHIFTRT, mode,
2762 gen_lowpart_for_combine (mode, inner),
2764 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2766 split = find_split_point (&SET_SRC (x), insn);
2767 if (split && split != &SET_SRC (x))
2774 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2775 gen_rtx_combine (ASHIFT, mode,
2776 gen_lowpart_for_combine (mode, inner),
2777 GEN_INT (GET_MODE_BITSIZE (mode)
2779 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2781 split = find_split_point (&SET_SRC (x), insn);
2782 if (split && split != &SET_SRC (x))
2787 /* See if this is a simple operation with a constant as the second
2788 operand. It might be that this constant is out of range and hence
2789 could be used as a split point. */
2790 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2791 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2792 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2793 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2794 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2795 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2796 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2798 return &XEXP (SET_SRC (x), 1);
2800 /* Finally, see if this is a simple operation with its first operand
2801 not in a register. The operation might require this operand in a
2802 register, so return it as a split point. We can always do this
2803 because if the first operand were another operation, we would have
2804 already found it as a split point. */
2805 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2806 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2807 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2808 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2809 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2810 return &XEXP (SET_SRC (x), 0);
2816 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2817 it is better to write this as (not (ior A B)) so we can split it.
2818 Similarly for IOR. */
2819 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2822 gen_rtx_combine (NOT, GET_MODE (x),
2823 gen_rtx_combine (code == IOR ? AND : IOR,
2825 XEXP (XEXP (x, 0), 0),
2826 XEXP (XEXP (x, 1), 0))));
2827 return find_split_point (loc, insn);
2830 /* Many RISC machines have a large set of logical insns. If the
2831 second operand is a NOT, put it first so we will try to split the
2832 other operand first. */
2833 if (GET_CODE (XEXP (x, 1)) == NOT)
2835 rtx tem = XEXP (x, 0);
2836 SUBST (XEXP (x, 0), XEXP (x, 1));
2837 SUBST (XEXP (x, 1), tem);
2845 /* Otherwise, select our actions depending on our rtx class. */
2846 switch (GET_RTX_CLASS (code))
2848 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2850 split = find_split_point (&XEXP (x, 2), insn);
2853 /* ... fall through ... */
2857 split = find_split_point (&XEXP (x, 1), insn);
2860 /* ... fall through ... */
2862 /* Some machines have (and (shift ...) ...) insns. If X is not
2863 an AND, but XEXP (X, 0) is, use it as our split point. */
2864 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2865 return &XEXP (x, 0);
2867 split = find_split_point (&XEXP (x, 0), insn);
2873 /* Otherwise, we don't have a split point. */
2877 /* Throughout X, replace FROM with TO, and return the result.
2878 The result is TO if X is FROM;
2879 otherwise the result is X, but its contents may have been modified.
2880 If they were modified, a record was made in undobuf so that
2881 undo_all will (among other things) return X to its original state.
2883 If the number of changes necessary is too much to record to undo,
2884 the excess changes are not made, so the result is invalid.
2885 The changes already made can still be undone.
2886 undobuf.num_undo is incremented for such changes, so by testing that
2887 the caller can tell whether the result is valid.
2889 `n_occurrences' is incremented each time FROM is replaced.
2891 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2893 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2894 by copying if `n_occurrences' is non-zero. */
2897 subst (x, from, to, in_dest, unique_copy)
2898 register rtx x, from, to;
2902 register enum rtx_code code = GET_CODE (x);
2903 enum machine_mode op0_mode = VOIDmode;
2905 register int len, i;
2908 /* Two expressions are equal if they are identical copies of a shared
2909 RTX or if they are both registers with the same register number
2912 #define COMBINE_RTX_EQUAL_P(X,Y) \
2914 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2915 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2917 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2920 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2923 /* If X and FROM are the same register but different modes, they will
2924 not have been seen as equal above. However, flow.c will make a
2925 LOG_LINKS entry for that case. If we do nothing, we will try to
2926 rerecognize our original insn and, when it succeeds, we will
2927 delete the feeding insn, which is incorrect.
2929 So force this insn not to match in this (rare) case. */
2930 if (! in_dest && code == REG && GET_CODE (from) == REG
2931 && REGNO (x) == REGNO (from))
2932 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2934 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2935 of which may contain things that can be combined. */
2936 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2939 /* It is possible to have a subexpression appear twice in the insn.
2940 Suppose that FROM is a register that appears within TO.
2941 Then, after that subexpression has been scanned once by `subst',
2942 the second time it is scanned, TO may be found. If we were
2943 to scan TO here, we would find FROM within it and create a
2944 self-referent rtl structure which is completely wrong. */
2945 if (COMBINE_RTX_EQUAL_P (x, to))
2948 len = GET_RTX_LENGTH (code);
2949 fmt = GET_RTX_FORMAT (code);
2951 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2952 set up to skip this common case. All other cases where we want to
2953 suppress replacing something inside a SET_SRC are handled via the
2956 && (GET_CODE (SET_DEST (x)) == REG
2957 || GET_CODE (SET_DEST (x)) == CC0
2958 || GET_CODE (SET_DEST (x)) == PC))
2961 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
2964 op0_mode = GET_MODE (XEXP (x, 0));
2966 for (i = 0; i < len; i++)
2971 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2973 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2975 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2980 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2982 /* If this substitution failed, this whole thing fails. */
2983 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2987 SUBST (XVECEXP (x, i, j), new);
2990 else if (fmt[i] == 'e')
2992 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2994 /* In general, don't install a subreg involving two modes not
2995 tieable. It can worsen register allocation, and can even
2996 make invalid reload insns, since the reg inside may need to
2997 be copied from in the outside mode, and that may be invalid
2998 if it is an fp reg copied in integer mode.
3000 We allow two exceptions to this: It is valid if it is inside
3001 another SUBREG and the mode of that SUBREG and the mode of
3002 the inside of TO is tieable and it is valid if X is a SET
3003 that copies FROM to CC0. */
3004 if (GET_CODE (to) == SUBREG
3005 && ! MODES_TIEABLE_P (GET_MODE (to),
3006 GET_MODE (SUBREG_REG (to)))
3007 && ! (code == SUBREG
3008 && MODES_TIEABLE_P (GET_MODE (x),
3009 GET_MODE (SUBREG_REG (to))))
3011 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3014 return gen_rtx (CLOBBER, VOIDmode, const0_rtx);
3016 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3020 /* If we are in a SET_DEST, suppress most cases unless we
3021 have gone inside a MEM, in which case we want to
3022 simplify the address. We assume here that things that
3023 are actually part of the destination have their inner
3024 parts in the first expression. This is true for SUBREG,
3025 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3026 things aside from REG and MEM that should appear in a
3028 new = subst (XEXP (x, i), from, to,
3030 && (code == SUBREG || code == STRICT_LOW_PART
3031 || code == ZERO_EXTRACT))
3033 && i == 0), unique_copy);
3035 /* If we found that we will have to reject this combination,
3036 indicate that by returning the CLOBBER ourselves, rather than
3037 an expression containing it. This will speed things up as
3038 well as prevent accidents where two CLOBBERs are considered
3039 to be equal, thus producing an incorrect simplification. */
3041 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3044 SUBST (XEXP (x, i), new);
3048 /* Try to simplify X. If the simplification changed the code, it is likely
3049 that further simplification will help, so loop, but limit the number
3050 of repetitions that will be performed. */
3052 for (i = 0; i < 4; i++)
3054 /* If X is sufficiently simple, don't bother trying to do anything
3056 if (code != CONST_INT && code != REG && code != CLOBBER)
3057 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3059 if (GET_CODE (x) == code)
3062 code = GET_CODE (x);
3064 /* We no longer know the original mode of operand 0 since we
3065 have changed the form of X) */
3066 op0_mode = VOIDmode;
3072 /* Simplify X, a piece of RTL. We just operate on the expression at the
3073 outer level; call `subst' to simplify recursively. Return the new
3076 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3077 will be the iteration even if an expression with a code different from
3078 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3081 simplify_rtx (x, op0_mode, last, in_dest)
3083 enum machine_mode op0_mode;
3087 enum rtx_code code = GET_CODE (x);
3088 enum machine_mode mode = GET_MODE (x);
3092 /* If this is a commutative operation, put a constant last and a complex
3093 expression first. We don't need to do this for comparisons here. */
3094 if (GET_RTX_CLASS (code) == 'c'
3095 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3096 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3097 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3098 || (GET_CODE (XEXP (x, 0)) == SUBREG
3099 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3100 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3103 SUBST (XEXP (x, 0), XEXP (x, 1));
3104 SUBST (XEXP (x, 1), temp);
3107 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3108 sign extension of a PLUS with a constant, reverse the order of the sign
3109 extension and the addition. Note that this not the same as the original
3110 code, but overflow is undefined for signed values. Also note that the
3111 PLUS will have been partially moved "inside" the sign-extension, so that
3112 the first operand of X will really look like:
3113 (ashiftrt (plus (ashift A C4) C5) C4).
3115 (plus (ashiftrt (ashift A C4) C2) C4)
3116 and replace the first operand of X with that expression. Later parts
3117 of this function may simplify the expression further.
3119 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3120 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3121 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3123 We do this to simplify address expressions. */
3125 if ((code == PLUS || code == MINUS || code == MULT)
3126 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3127 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3128 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3129 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3130 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3131 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3132 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3133 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3134 XEXP (XEXP (XEXP (x, 0), 0), 1),
3135 XEXP (XEXP (x, 0), 1))) != 0)
3138 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3139 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3140 INTVAL (XEXP (XEXP (x, 0), 1)));
3142 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3143 INTVAL (XEXP (XEXP (x, 0), 1)));
3145 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3148 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3149 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3150 things. Check for cases where both arms are testing the same
3153 Don't do anything if all operands are very simple. */
3155 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3156 || GET_RTX_CLASS (code) == '<')
3157 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3158 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3159 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3161 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3162 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3163 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3165 || (GET_RTX_CLASS (code) == '1'
3166 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3167 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3168 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3171 rtx cond, true, false;
3173 cond = if_then_else_cond (x, &true, &false);
3175 /* If everything is a comparison, what we have is highly unlikely
3176 to be simpler, so don't use it. */
3177 && ! (GET_RTX_CLASS (code) == '<'
3178 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3179 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3181 rtx cop1 = const0_rtx;
3182 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3184 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3187 /* Simplify the alternative arms; this may collapse the true and
3188 false arms to store-flag values. */
3189 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3190 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3192 /* Restarting if we generate a store-flag expression will cause
3193 us to loop. Just drop through in this case. */
3195 /* If the result values are STORE_FLAG_VALUE and zero, we can
3196 just make the comparison operation. */
3197 if (true == const_true_rtx && false == const0_rtx)
3198 x = gen_binary (cond_code, mode, cond, cop1);
3199 else if (true == const0_rtx && false == const_true_rtx)
3200 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3202 /* Likewise, we can make the negate of a comparison operation
3203 if the result values are - STORE_FLAG_VALUE and zero. */
3204 else if (GET_CODE (true) == CONST_INT
3205 && INTVAL (true) == - STORE_FLAG_VALUE
3206 && false == const0_rtx)
3207 x = gen_unary (NEG, mode, mode,
3208 gen_binary (cond_code, mode, cond, cop1));
3209 else if (GET_CODE (false) == CONST_INT
3210 && INTVAL (false) == - STORE_FLAG_VALUE
3211 && true == const0_rtx)
3212 x = gen_unary (NEG, mode, mode,
3213 gen_binary (reverse_condition (cond_code),
3216 return gen_rtx (IF_THEN_ELSE, mode,
3217 gen_binary (cond_code, VOIDmode, cond, cop1),
3220 code = GET_CODE (x);
3221 op0_mode = VOIDmode;
3225 /* Try to fold this expression in case we have constants that weren't
3228 switch (GET_RTX_CLASS (code))
3231 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3234 temp = simplify_relational_operation (code, op0_mode,
3235 XEXP (x, 0), XEXP (x, 1));
3236 #ifdef FLOAT_STORE_FLAG_VALUE
3237 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3238 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3239 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3244 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3248 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3249 XEXP (x, 1), XEXP (x, 2));
3254 x = temp, code = GET_CODE (temp);
3256 /* First see if we can apply the inverse distributive law. */
3257 if (code == PLUS || code == MINUS
3258 || code == AND || code == IOR || code == XOR)
3260 x = apply_distributive_law (x);
3261 code = GET_CODE (x);
3264 /* If CODE is an associative operation not otherwise handled, see if we
3265 can associate some operands. This can win if they are constants or
3266 if they are logically related (i.e. (a & b) & a. */
3267 if ((code == PLUS || code == MINUS
3268 || code == MULT || code == AND || code == IOR || code == XOR
3269 || code == DIV || code == UDIV
3270 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3271 && INTEGRAL_MODE_P (mode))
3273 if (GET_CODE (XEXP (x, 0)) == code)
3275 rtx other = XEXP (XEXP (x, 0), 0);
3276 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3277 rtx inner_op1 = XEXP (x, 1);
3280 /* Make sure we pass the constant operand if any as the second
3281 one if this is a commutative operation. */
3282 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3284 rtx tem = inner_op0;
3285 inner_op0 = inner_op1;
3288 inner = simplify_binary_operation (code == MINUS ? PLUS
3289 : code == DIV ? MULT
3290 : code == UDIV ? MULT
3292 mode, inner_op0, inner_op1);
3294 /* For commutative operations, try the other pair if that one
3296 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3298 other = XEXP (XEXP (x, 0), 1);
3299 inner = simplify_binary_operation (code, mode,
3300 XEXP (XEXP (x, 0), 0),
3305 return gen_binary (code, mode, other, inner);
3309 /* A little bit of algebraic simplification here. */
3313 /* Ensure that our address has any ASHIFTs converted to MULT in case
3314 address-recognizing predicates are called later. */
3315 temp = make_compound_operation (XEXP (x, 0), MEM);
3316 SUBST (XEXP (x, 0), temp);
3320 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3321 is paradoxical. If we can't do that safely, then it becomes
3322 something nonsensical so that this combination won't take place. */
3324 if (GET_CODE (SUBREG_REG (x)) == MEM
3325 && (GET_MODE_SIZE (mode)
3326 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3328 rtx inner = SUBREG_REG (x);
3329 int endian_offset = 0;
3330 /* Don't change the mode of the MEM
3331 if that would change the meaning of the address. */
3332 if (MEM_VOLATILE_P (SUBREG_REG (x))
3333 || mode_dependent_address_p (XEXP (inner, 0)))
3334 return gen_rtx (CLOBBER, mode, const0_rtx);
3336 if (BYTES_BIG_ENDIAN)
3338 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3339 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3340 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3341 endian_offset -= (UNITS_PER_WORD
3342 - GET_MODE_SIZE (GET_MODE (inner)));
3344 /* Note if the plus_constant doesn't make a valid address
3345 then this combination won't be accepted. */
3346 x = gen_rtx (MEM, mode,
3347 plus_constant (XEXP (inner, 0),
3348 (SUBREG_WORD (x) * UNITS_PER_WORD
3350 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
3351 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3352 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
3356 /* If we are in a SET_DEST, these other cases can't apply. */
3360 /* Changing mode twice with SUBREG => just change it once,
3361 or not at all if changing back to starting mode. */
3362 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3364 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3365 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3366 return SUBREG_REG (SUBREG_REG (x));
3368 SUBST_INT (SUBREG_WORD (x),
3369 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3370 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3373 /* SUBREG of a hard register => just change the register number
3374 and/or mode. If the hard register is not valid in that mode,
3375 suppress this combination. If the hard register is the stack,
3376 frame, or argument pointer, leave this as a SUBREG. */
3378 if (GET_CODE (SUBREG_REG (x)) == REG
3379 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3380 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3381 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3382 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3384 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3385 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3387 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3389 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3391 return gen_rtx (REG, mode,
3392 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3394 return gen_rtx (CLOBBER, mode, const0_rtx);
3397 /* For a constant, try to pick up the part we want. Handle a full
3398 word and low-order part. Only do this if we are narrowing
3399 the constant; if it is being widened, we have no idea what
3400 the extra bits will have been set to. */
3402 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3403 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3404 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3405 && GET_MODE_CLASS (mode) == MODE_INT)
3407 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3413 /* If we want a subreg of a constant, at offset 0,
3414 take the low bits. On a little-endian machine, that's
3415 always valid. On a big-endian machine, it's valid
3416 only if the constant's mode fits in one word. Note that we
3417 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3418 if (CONSTANT_P (SUBREG_REG (x))
3419 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3420 || ! WORDS_BIG_ENDIAN)
3421 ? SUBREG_WORD (x) == 0
3423 == ((GET_MODE_SIZE (op0_mode)
3424 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3426 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3427 && (! WORDS_BIG_ENDIAN
3428 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3429 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3431 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3432 since we are saying that the high bits don't matter. */
3433 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3434 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3435 return SUBREG_REG (x);
3437 /* Note that we cannot do any narrowing for non-constants since
3438 we might have been counting on using the fact that some bits were
3439 zero. We now do this in the SET. */
3444 /* (not (plus X -1)) can become (neg X). */
3445 if (GET_CODE (XEXP (x, 0)) == PLUS
3446 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3447 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3449 /* Similarly, (not (neg X)) is (plus X -1). */
3450 if (GET_CODE (XEXP (x, 0)) == NEG)
3451 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3454 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3455 if (GET_CODE (XEXP (x, 0)) == XOR
3456 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3457 && (temp = simplify_unary_operation (NOT, mode,
3458 XEXP (XEXP (x, 0), 1),
3460 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3462 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3463 other than 1, but that is not valid. We could do a similar
3464 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3465 but this doesn't seem common enough to bother with. */
3466 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3467 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3468 return gen_rtx (ROTATE, mode, gen_unary (NOT, mode, mode, const1_rtx),
3469 XEXP (XEXP (x, 0), 1));
3471 if (GET_CODE (XEXP (x, 0)) == SUBREG
3472 && subreg_lowpart_p (XEXP (x, 0))
3473 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3474 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3475 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3476 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3478 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3480 x = gen_rtx (ROTATE, inner_mode,
3481 gen_unary (NOT, inner_mode, inner_mode, const1_rtx),
3482 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3483 return gen_lowpart_for_combine (mode, x);
3486 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3487 reversing the comparison code if valid. */
3488 if (STORE_FLAG_VALUE == -1
3489 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3490 && reversible_comparison_p (XEXP (x, 0)))
3491 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3492 mode, XEXP (XEXP (x, 0), 0),
3493 XEXP (XEXP (x, 0), 1));
3495 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3496 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3497 perform the above simplification. */
3499 if (STORE_FLAG_VALUE == -1
3500 && XEXP (x, 1) == const1_rtx
3501 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3502 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3503 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3504 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3506 /* Apply De Morgan's laws to reduce number of patterns for machines
3507 with negating logical insns (and-not, nand, etc.). If result has
3508 only one NOT, put it first, since that is how the patterns are
3511 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3513 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3515 if (GET_CODE (in1) == NOT)
3516 in1 = XEXP (in1, 0);
3518 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3520 if (GET_CODE (in2) == NOT)
3521 in2 = XEXP (in2, 0);
3522 else if (GET_CODE (in2) == CONST_INT
3523 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3524 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3526 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3528 if (GET_CODE (in2) == NOT)
3531 in2 = in1; in1 = tem;
3534 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3540 /* (neg (plus X 1)) can become (not X). */
3541 if (GET_CODE (XEXP (x, 0)) == PLUS
3542 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3543 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3545 /* Similarly, (neg (not X)) is (plus X 1). */
3546 if (GET_CODE (XEXP (x, 0)) == NOT)
3547 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3549 /* (neg (minus X Y)) can become (minus Y X). */
3550 if (GET_CODE (XEXP (x, 0)) == MINUS
3551 && (! FLOAT_MODE_P (mode)
3552 /* x-y != -(y-x) with IEEE floating point. */
3553 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3555 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3556 XEXP (XEXP (x, 0), 0));
3558 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3559 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3560 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3561 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3563 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3564 if we can then eliminate the NEG (e.g.,
3565 if the operand is a constant). */
3567 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3569 temp = simplify_unary_operation (NEG, mode,
3570 XEXP (XEXP (x, 0), 0), mode);
3573 SUBST (XEXP (XEXP (x, 0), 0), temp);
3578 temp = expand_compound_operation (XEXP (x, 0));
3580 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3581 replaced by (lshiftrt X C). This will convert
3582 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3584 if (GET_CODE (temp) == ASHIFTRT
3585 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3586 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3587 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3588 INTVAL (XEXP (temp, 1)));
3590 /* If X has only a single bit that might be nonzero, say, bit I, convert
3591 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3592 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3593 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3594 or a SUBREG of one since we'd be making the expression more
3595 complex if it was just a register. */
3597 if (GET_CODE (temp) != REG
3598 && ! (GET_CODE (temp) == SUBREG
3599 && GET_CODE (SUBREG_REG (temp)) == REG)
3600 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3602 rtx temp1 = simplify_shift_const
3603 (NULL_RTX, ASHIFTRT, mode,
3604 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3605 GET_MODE_BITSIZE (mode) - 1 - i),
3606 GET_MODE_BITSIZE (mode) - 1 - i);
3608 /* If all we did was surround TEMP with the two shifts, we
3609 haven't improved anything, so don't use it. Otherwise,
3610 we are better off with TEMP1. */
3611 if (GET_CODE (temp1) != ASHIFTRT
3612 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3613 || XEXP (XEXP (temp1, 0), 0) != temp)
3619 /* We can't handle truncation to a partial integer mode here
3620 because we don't know the real bitsize of the partial
3622 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3625 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3627 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3628 GET_MODE_MASK (mode), NULL_RTX, 0));
3630 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3631 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3632 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3633 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3634 return XEXP (XEXP (x, 0), 0);
3636 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3637 (OP:SI foo:SI) if OP is NEG or ABS. */
3638 if ((GET_CODE (XEXP (x, 0)) == ABS
3639 || GET_CODE (XEXP (x, 0)) == NEG)
3640 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3641 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3642 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3643 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3644 XEXP (XEXP (XEXP (x, 0), 0), 0));
3646 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3648 if (GET_CODE (XEXP (x, 0)) == SUBREG
3649 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3650 && subreg_lowpart_p (XEXP (x, 0)))
3651 return SUBREG_REG (XEXP (x, 0));
3653 /* If we know that the value is already truncated, we can
3654 replace the TRUNCATE with a SUBREG. */
3655 if (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_WIDE_INT
3656 && (nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3657 &~ GET_MODE_MASK (mode)) == 0)
3658 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3660 /* A truncate of a comparison can be replaced with a subreg if
3661 STORE_FLAG_VALUE permits. This is like the previous test,
3662 but it works even if the comparison is done in a mode larger
3663 than HOST_BITS_PER_WIDE_INT. */
3664 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3665 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3666 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3667 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3669 /* Similarly, a truncate of a register whose value is a
3670 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3672 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3673 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3674 && (temp = get_last_value (XEXP (x, 0)))
3675 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3676 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3680 case FLOAT_TRUNCATE:
3681 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3682 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3683 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3684 return XEXP (XEXP (x, 0), 0);
3686 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3687 (OP:SF foo:SF) if OP is NEG or ABS. */
3688 if ((GET_CODE (XEXP (x, 0)) == ABS
3689 || GET_CODE (XEXP (x, 0)) == NEG)
3690 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3691 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3692 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3693 XEXP (XEXP (XEXP (x, 0), 0), 0));
3695 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3696 is (float_truncate:SF x). */
3697 if (GET_CODE (XEXP (x, 0)) == SUBREG
3698 && subreg_lowpart_p (XEXP (x, 0))
3699 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3700 return SUBREG_REG (XEXP (x, 0));
3705 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3706 using cc0, in which case we want to leave it as a COMPARE
3707 so we can distinguish it from a register-register-copy. */
3708 if (XEXP (x, 1) == const0_rtx)
3711 /* In IEEE floating point, x-0 is not the same as x. */
3712 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3713 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3715 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3721 /* (const (const X)) can become (const X). Do it this way rather than
3722 returning the inner CONST since CONST can be shared with a
3724 if (GET_CODE (XEXP (x, 0)) == CONST)
3725 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3730 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3731 can add in an offset. find_split_point will split this address up
3732 again if it doesn't match. */
3733 if (GET_CODE (XEXP (x, 0)) == HIGH
3734 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3740 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3741 outermost. That's because that's the way indexed addresses are
3742 supposed to appear. This code used to check many more cases, but
3743 they are now checked elsewhere. */
3744 if (GET_CODE (XEXP (x, 0)) == PLUS
3745 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3746 return gen_binary (PLUS, mode,
3747 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3749 XEXP (XEXP (x, 0), 1));
3751 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3752 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3753 bit-field and can be replaced by either a sign_extend or a
3754 sign_extract. The `and' may be a zero_extend. */
3755 if (GET_CODE (XEXP (x, 0)) == XOR
3756 && GET_CODE (XEXP (x, 1)) == CONST_INT
3757 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3758 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3759 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3760 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3761 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3762 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3763 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3764 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3765 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3766 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3768 return simplify_shift_const
3769 (NULL_RTX, ASHIFTRT, mode,
3770 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3771 XEXP (XEXP (XEXP (x, 0), 0), 0),
3772 GET_MODE_BITSIZE (mode) - (i + 1)),
3773 GET_MODE_BITSIZE (mode) - (i + 1));
3775 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3776 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3777 is 1. This produces better code than the alternative immediately
3779 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3780 && reversible_comparison_p (XEXP (x, 0))
3781 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3782 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3784 gen_unary (NEG, mode, mode,
3785 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3786 mode, XEXP (XEXP (x, 0), 0),
3787 XEXP (XEXP (x, 0), 1)));
3789 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3790 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3791 the bitsize of the mode - 1. This allows simplification of
3792 "a = (b & 8) == 0;" */
3793 if (XEXP (x, 1) == constm1_rtx
3794 && GET_CODE (XEXP (x, 0)) != REG
3795 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3796 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3797 && nonzero_bits (XEXP (x, 0), mode) == 1)
3798 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3799 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3800 gen_rtx_combine (XOR, mode,
3801 XEXP (x, 0), const1_rtx),
3802 GET_MODE_BITSIZE (mode) - 1),
3803 GET_MODE_BITSIZE (mode) - 1);
3805 /* If we are adding two things that have no bits in common, convert
3806 the addition into an IOR. This will often be further simplified,
3807 for example in cases like ((a & 1) + (a & 2)), which can
3810 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3811 && (nonzero_bits (XEXP (x, 0), mode)
3812 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3813 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3817 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3818 by reversing the comparison code if valid. */
3819 if (STORE_FLAG_VALUE == 1
3820 && XEXP (x, 0) == const1_rtx
3821 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3822 && reversible_comparison_p (XEXP (x, 1)))
3823 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3824 mode, XEXP (XEXP (x, 1), 0),
3825 XEXP (XEXP (x, 1), 1));
3827 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3828 (and <foo> (const_int pow2-1)) */
3829 if (GET_CODE (XEXP (x, 1)) == AND
3830 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3831 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3832 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3833 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3834 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3836 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3838 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
3839 return gen_binary (MINUS, mode,
3840 gen_binary (MINUS, mode, XEXP (x, 0),
3841 XEXP (XEXP (x, 1), 0)),
3842 XEXP (XEXP (x, 1), 1));
3846 /* If we have (mult (plus A B) C), apply the distributive law and then
3847 the inverse distributive law to see if things simplify. This
3848 occurs mostly in addresses, often when unrolling loops. */
3850 if (GET_CODE (XEXP (x, 0)) == PLUS)
3852 x = apply_distributive_law
3853 (gen_binary (PLUS, mode,
3854 gen_binary (MULT, mode,
3855 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3856 gen_binary (MULT, mode,
3857 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3859 if (GET_CODE (x) != MULT)
3865 /* If this is a divide by a power of two, treat it as a shift if
3866 its first operand is a shift. */
3867 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3868 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3869 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3870 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3871 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3872 || GET_CODE (XEXP (x, 0)) == ROTATE
3873 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3874 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3878 case GT: case GTU: case GE: case GEU:
3879 case LT: case LTU: case LE: case LEU:
3880 /* If the first operand is a condition code, we can't do anything
3882 if (GET_CODE (XEXP (x, 0)) == COMPARE
3883 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3885 && XEXP (x, 0) != cc0_rtx
3889 rtx op0 = XEXP (x, 0);
3890 rtx op1 = XEXP (x, 1);
3891 enum rtx_code new_code;
3893 if (GET_CODE (op0) == COMPARE)
3894 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3896 /* Simplify our comparison, if possible. */
3897 new_code = simplify_comparison (code, &op0, &op1);
3899 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3900 if only the low-order bit is possibly nonzero in X (such as when
3901 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
3902 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
3903 known to be either 0 or -1, NE becomes a NEG and EQ becomes
3906 Remove any ZERO_EXTRACT we made when thinking this was a
3907 comparison. It may now be simpler to use, e.g., an AND. If a
3908 ZERO_EXTRACT is indeed appropriate, it will be placed back by
3909 the call to make_compound_operation in the SET case. */
3911 if (STORE_FLAG_VALUE == 1
3912 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3913 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
3914 return gen_lowpart_for_combine (mode,
3915 expand_compound_operation (op0));
3917 else if (STORE_FLAG_VALUE == 1
3918 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3919 && op1 == const0_rtx
3920 && (num_sign_bit_copies (op0, mode)
3921 == GET_MODE_BITSIZE (mode)))
3923 op0 = expand_compound_operation (op0);
3924 return gen_unary (NEG, mode, mode,
3925 gen_lowpart_for_combine (mode, op0));
3928 else if (STORE_FLAG_VALUE == 1
3929 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3930 && op1 == const0_rtx
3931 && nonzero_bits (op0, mode) == 1)
3933 op0 = expand_compound_operation (op0);
3934 return gen_binary (XOR, mode,
3935 gen_lowpart_for_combine (mode, op0),
3939 else if (STORE_FLAG_VALUE == 1
3940 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3941 && op1 == const0_rtx
3942 && (num_sign_bit_copies (op0, mode)
3943 == GET_MODE_BITSIZE (mode)))
3945 op0 = expand_compound_operation (op0);
3946 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
3949 /* If STORE_FLAG_VALUE is -1, we have cases similar to
3951 if (STORE_FLAG_VALUE == -1
3952 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3953 && op1 == const0_rtx
3954 && (num_sign_bit_copies (op0, mode)
3955 == GET_MODE_BITSIZE (mode)))
3956 return gen_lowpart_for_combine (mode,
3957 expand_compound_operation (op0));
3959 else if (STORE_FLAG_VALUE == -1
3960 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3961 && op1 == const0_rtx
3962 && nonzero_bits (op0, mode) == 1)
3964 op0 = expand_compound_operation (op0);
3965 return gen_unary (NEG, mode, mode,
3966 gen_lowpart_for_combine (mode, op0));
3969 else if (STORE_FLAG_VALUE == -1
3970 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3971 && op1 == const0_rtx
3972 && (num_sign_bit_copies (op0, mode)
3973 == GET_MODE_BITSIZE (mode)))
3975 op0 = expand_compound_operation (op0);
3976 return gen_unary (NOT, mode, mode,
3977 gen_lowpart_for_combine (mode, op0));
3980 /* If X is 0/1, (eq X 0) is X-1. */
3981 else if (STORE_FLAG_VALUE == -1
3982 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3983 && op1 == const0_rtx
3984 && nonzero_bits (op0, mode) == 1)
3986 op0 = expand_compound_operation (op0);
3987 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
3990 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3991 one bit that might be nonzero, we can convert (ne x 0) to
3992 (ashift x c) where C puts the bit in the sign bit. Remove any
3993 AND with STORE_FLAG_VALUE when we are done, since we are only
3994 going to test the sign bit. */
3995 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3996 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3997 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
3998 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3999 && op1 == const0_rtx
4000 && mode == GET_MODE (op0)
4001 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4003 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4004 expand_compound_operation (op0),
4005 GET_MODE_BITSIZE (mode) - 1 - i);
4006 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4012 /* If the code changed, return a whole new comparison. */
4013 if (new_code != code)
4014 return gen_rtx_combine (new_code, mode, op0, op1);
4016 /* Otherwise, keep this operation, but maybe change its operands.
4017 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4018 SUBST (XEXP (x, 0), op0);
4019 SUBST (XEXP (x, 1), op1);
4024 return simplify_if_then_else (x);
4030 /* If we are processing SET_DEST, we are done. */
4034 return expand_compound_operation (x);
4037 return simplify_set (x);
4042 return simplify_logical (x, last);
4045 /* (abs (neg <foo>)) -> (abs <foo>) */
4046 if (GET_CODE (XEXP (x, 0)) == NEG)
4047 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4049 /* If operand is something known to be positive, ignore the ABS. */
4050 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4051 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4052 <= HOST_BITS_PER_WIDE_INT)
4053 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4054 & ((HOST_WIDE_INT) 1
4055 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4060 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4061 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4062 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4067 /* (ffs (*_extend <X>)) = (ffs <X>) */
4068 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4069 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4070 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4074 /* (float (sign_extend <X>)) = (float <X>). */
4075 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4076 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4084 /* If this is a shift by a constant amount, simplify it. */
4085 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4086 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4087 INTVAL (XEXP (x, 1)));
4089 #ifdef SHIFT_COUNT_TRUNCATED
4090 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4092 force_to_mode (XEXP (x, 1), GET_MODE (x),
4094 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4108 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4111 simplify_if_then_else (x)
4114 enum machine_mode mode = GET_MODE (x);
4115 rtx cond = XEXP (x, 0);
4116 rtx true = XEXP (x, 1);
4117 rtx false = XEXP (x, 2);
4118 enum rtx_code true_code = GET_CODE (cond);
4119 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4123 /* Simplify storing of the truth value. */
4124 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4125 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4127 /* Also when the truth value has to be reversed. */
4128 if (comparison_p && reversible_comparison_p (cond)
4129 && true == const0_rtx && false == const_true_rtx)
4130 return gen_binary (reverse_condition (true_code),
4131 mode, XEXP (cond, 0), XEXP (cond, 1));
4133 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4134 in it is being compared against certain values. Get the true and false
4135 comparisons and see if that says anything about the value of each arm. */
4137 if (comparison_p && reversible_comparison_p (cond)
4138 && GET_CODE (XEXP (cond, 0)) == REG)
4141 rtx from = XEXP (cond, 0);
4142 enum rtx_code false_code = reverse_condition (true_code);
4143 rtx true_val = XEXP (cond, 1);
4144 rtx false_val = true_val;
4147 /* If FALSE_CODE is EQ, swap the codes and arms. */
4149 if (false_code == EQ)
4151 swapped = 1, true_code = EQ, false_code = NE;
4152 temp = true, true = false, false = temp;
4155 /* If we are comparing against zero and the expression being tested has
4156 only a single bit that might be nonzero, that is its value when it is
4157 not equal to zero. Similarly if it is known to be -1 or 0. */
4159 if (true_code == EQ && true_val == const0_rtx
4160 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4161 false_code = EQ, false_val = GEN_INT (nzb);
4162 else if (true_code == EQ && true_val == const0_rtx
4163 && (num_sign_bit_copies (from, GET_MODE (from))
4164 == GET_MODE_BITSIZE (GET_MODE (from))))
4165 false_code = EQ, false_val = constm1_rtx;
4167 /* Now simplify an arm if we know the value of the register in the
4168 branch and it is used in the arm. Be careful due to the potential
4169 of locally-shared RTL. */
4171 if (reg_mentioned_p (from, true))
4172 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4173 pc_rtx, pc_rtx, 0, 0);
4174 if (reg_mentioned_p (from, false))
4175 false = subst (known_cond (copy_rtx (false), false_code,
4177 pc_rtx, pc_rtx, 0, 0);
4179 SUBST (XEXP (x, 1), swapped ? false : true);
4180 SUBST (XEXP (x, 2), swapped ? true : false);
4182 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4185 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4186 reversed, do so to avoid needing two sets of patterns for
4187 subtract-and-branch insns. Similarly if we have a constant in the true
4188 arm, the false arm is the same as the first operand of the comparison, or
4189 the false arm is more complicated than the true arm. */
4191 if (comparison_p && reversible_comparison_p (cond)
4193 || (CONSTANT_P (true)
4194 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4195 || true == const0_rtx
4196 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4197 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4198 || (GET_CODE (true) == SUBREG
4199 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4200 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4201 || reg_mentioned_p (true, false)
4202 || rtx_equal_p (false, XEXP (cond, 0))))
4204 true_code = reverse_condition (true_code);
4206 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4209 SUBST (XEXP (x, 1), false);
4210 SUBST (XEXP (x, 2), true);
4212 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4214 /* It is possible that the conditional has been simplified out. */
4215 true_code = GET_CODE (cond);
4216 comparison_p = GET_RTX_CLASS (true_code) == '<';
4219 /* If the two arms are identical, we don't need the comparison. */
4221 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4224 /* Convert a == b ? b : a to "a". */
4225 if (true_code == EQ && ! side_effects_p (cond)
4226 && rtx_equal_p (XEXP (cond, 0), false)
4227 && rtx_equal_p (XEXP (cond, 1), true))
4229 else if (true_code == NE && ! side_effects_p (cond)
4230 && rtx_equal_p (XEXP (cond, 0), true)
4231 && rtx_equal_p (XEXP (cond, 1), false))
4234 /* Look for cases where we have (abs x) or (neg (abs X)). */
4236 if (GET_MODE_CLASS (mode) == MODE_INT
4237 && GET_CODE (false) == NEG
4238 && rtx_equal_p (true, XEXP (false, 0))
4240 && rtx_equal_p (true, XEXP (cond, 0))
4241 && ! side_effects_p (true))
4246 return gen_unary (ABS, mode, mode, true);
4249 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4254 /* Look for MIN or MAX. */
4256 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4258 && rtx_equal_p (XEXP (cond, 0), true)
4259 && rtx_equal_p (XEXP (cond, 1), false)
4260 && ! side_effects_p (cond))
4265 return gen_binary (SMAX, mode, true, false);
4268 return gen_binary (SMIN, mode, true, false);
4271 return gen_binary (UMAX, mode, true, false);
4274 return gen_binary (UMIN, mode, true, false);
4279 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4280 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4281 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4282 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4283 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4284 neither 1 or -1, but it isn't worth checking for. */
4286 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4287 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4289 rtx t = make_compound_operation (true, SET);
4290 rtx f = make_compound_operation (false, SET);
4291 rtx cond_op0 = XEXP (cond, 0);
4292 rtx cond_op1 = XEXP (cond, 1);
4293 enum rtx_code op, extend_op = NIL;
4294 enum machine_mode m = mode;
4297 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4298 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4299 || GET_CODE (t) == ASHIFT
4300 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4301 && rtx_equal_p (XEXP (t, 0), f))
4302 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4304 /* If an identity-zero op is commutative, check whether there
4305 would be a match if we swapped the operands. */
4306 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4307 || GET_CODE (t) == XOR)
4308 && rtx_equal_p (XEXP (t, 1), f))
4309 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4310 else if (GET_CODE (t) == SIGN_EXTEND
4311 && (GET_CODE (XEXP (t, 0)) == PLUS
4312 || GET_CODE (XEXP (t, 0)) == MINUS
4313 || GET_CODE (XEXP (t, 0)) == IOR
4314 || GET_CODE (XEXP (t, 0)) == XOR
4315 || GET_CODE (XEXP (t, 0)) == ASHIFT
4316 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4317 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4318 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4319 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4320 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4321 && (num_sign_bit_copies (f, GET_MODE (f))
4322 > (GET_MODE_BITSIZE (mode)
4323 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4325 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4326 extend_op = SIGN_EXTEND;
4327 m = GET_MODE (XEXP (t, 0));
4329 else if (GET_CODE (t) == SIGN_EXTEND
4330 && (GET_CODE (XEXP (t, 0)) == PLUS
4331 || GET_CODE (XEXP (t, 0)) == IOR
4332 || GET_CODE (XEXP (t, 0)) == XOR)
4333 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4334 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4335 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4336 && (num_sign_bit_copies (f, GET_MODE (f))
4337 > (GET_MODE_BITSIZE (mode)
4338 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4340 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4341 extend_op = SIGN_EXTEND;
4342 m = GET_MODE (XEXP (t, 0));
4344 else if (GET_CODE (t) == ZERO_EXTEND
4345 && (GET_CODE (XEXP (t, 0)) == PLUS
4346 || GET_CODE (XEXP (t, 0)) == MINUS
4347 || GET_CODE (XEXP (t, 0)) == IOR
4348 || GET_CODE (XEXP (t, 0)) == XOR
4349 || GET_CODE (XEXP (t, 0)) == ASHIFT
4350 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4351 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4352 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4353 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4354 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4355 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4356 && ((nonzero_bits (f, GET_MODE (f))
4357 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4360 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4361 extend_op = ZERO_EXTEND;
4362 m = GET_MODE (XEXP (t, 0));
4364 else if (GET_CODE (t) == ZERO_EXTEND
4365 && (GET_CODE (XEXP (t, 0)) == PLUS
4366 || GET_CODE (XEXP (t, 0)) == IOR
4367 || GET_CODE (XEXP (t, 0)) == XOR)
4368 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4369 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4370 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4371 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4372 && ((nonzero_bits (f, GET_MODE (f))
4373 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4376 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4377 extend_op = ZERO_EXTEND;
4378 m = GET_MODE (XEXP (t, 0));
4383 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4384 pc_rtx, pc_rtx, 0, 0);
4385 temp = gen_binary (MULT, m, temp,
4386 gen_binary (MULT, m, c1, const_true_rtx));
4387 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4388 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4390 if (extend_op != NIL)
4391 temp = gen_unary (extend_op, mode, m, temp);
4397 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4398 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4399 negation of a single bit, we can convert this operation to a shift. We
4400 can actually do this more generally, but it doesn't seem worth it. */
4402 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4403 && false == const0_rtx && GET_CODE (true) == CONST_INT
4404 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4405 && (i = exact_log2 (INTVAL (true))) >= 0)
4406 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4407 == GET_MODE_BITSIZE (mode))
4408 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4410 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4411 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4416 /* Simplify X, a SET expression. Return the new expression. */
4422 rtx src = SET_SRC (x);
4423 rtx dest = SET_DEST (x);
4424 enum machine_mode mode
4425 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4429 /* (set (pc) (return)) gets written as (return). */
4430 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4433 /* Now that we know for sure which bits of SRC we are using, see if we can
4434 simplify the expression for the object knowing that we only need the
4437 if (GET_MODE_CLASS (mode) == MODE_INT)
4438 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4440 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4441 the comparison result and try to simplify it unless we already have used
4442 undobuf.other_insn. */
4443 if ((GET_CODE (src) == COMPARE
4448 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4449 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4450 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4451 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4453 enum rtx_code old_code = GET_CODE (*cc_use);
4454 enum rtx_code new_code;
4456 int other_changed = 0;
4457 enum machine_mode compare_mode = GET_MODE (dest);
4459 if (GET_CODE (src) == COMPARE)
4460 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4462 op0 = src, op1 = const0_rtx;
4464 /* Simplify our comparison, if possible. */
4465 new_code = simplify_comparison (old_code, &op0, &op1);
4467 #ifdef EXTRA_CC_MODES
4468 /* If this machine has CC modes other than CCmode, check to see if we
4469 need to use a different CC mode here. */
4470 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4471 #endif /* EXTRA_CC_MODES */
4473 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4474 /* If the mode changed, we have to change SET_DEST, the mode in the
4475 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4476 a hard register, just build new versions with the proper mode. If it
4477 is a pseudo, we lose unless it is only time we set the pseudo, in
4478 which case we can safely change its mode. */
4479 if (compare_mode != GET_MODE (dest))
4481 int regno = REGNO (dest);
4482 rtx new_dest = gen_rtx (REG, compare_mode, regno);
4484 if (regno < FIRST_PSEUDO_REGISTER
4485 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4487 if (regno >= FIRST_PSEUDO_REGISTER)
4488 SUBST (regno_reg_rtx[regno], new_dest);
4490 SUBST (SET_DEST (x), new_dest);
4491 SUBST (XEXP (*cc_use, 0), new_dest);
4499 /* If the code changed, we have to build a new comparison in
4500 undobuf.other_insn. */
4501 if (new_code != old_code)
4503 unsigned HOST_WIDE_INT mask;
4505 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4508 /* If the only change we made was to change an EQ into an NE or
4509 vice versa, OP0 has only one bit that might be nonzero, and OP1
4510 is zero, check if changing the user of the condition code will
4511 produce a valid insn. If it won't, we can keep the original code
4512 in that insn by surrounding our operation with an XOR. */
4514 if (((old_code == NE && new_code == EQ)
4515 || (old_code == EQ && new_code == NE))
4516 && ! other_changed && op1 == const0_rtx
4517 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4518 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4520 rtx pat = PATTERN (other_insn), note = 0;
4523 if ((recog_for_combine (&pat, other_insn, ¬e, &scratches) < 0
4524 && ! check_asm_operands (pat)))
4526 PUT_CODE (*cc_use, old_code);
4529 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4537 undobuf.other_insn = other_insn;
4540 /* If we are now comparing against zero, change our source if
4541 needed. If we do not use cc0, we always have a COMPARE. */
4542 if (op1 == const0_rtx && dest == cc0_rtx)
4544 SUBST (SET_SRC (x), op0);
4550 /* Otherwise, if we didn't previously have a COMPARE in the
4551 correct mode, we need one. */
4552 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4555 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4560 /* Otherwise, update the COMPARE if needed. */
4561 SUBST (XEXP (src, 0), op0);
4562 SUBST (XEXP (src, 1), op1);
4567 /* Get SET_SRC in a form where we have placed back any
4568 compound expressions. Then do the checks below. */
4569 src = make_compound_operation (src, SET);
4570 SUBST (SET_SRC (x), src);
4573 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4574 and X being a REG or (subreg (reg)), we may be able to convert this to
4575 (set (subreg:m2 x) (op)).
4577 We can always do this if M1 is narrower than M2 because that means that
4578 we only care about the low bits of the result.
4580 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4581 perform a narrower operation that requested since the high-order bits will
4582 be undefined. On machine where it is defined, this transformation is safe
4583 as long as M1 and M2 have the same number of words. */
4585 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4586 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4587 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4589 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4590 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4591 #ifndef WORD_REGISTER_OPERATIONS
4592 && (GET_MODE_SIZE (GET_MODE (src))
4593 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4595 #ifdef CLASS_CANNOT_CHANGE_SIZE
4596 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4597 && (TEST_HARD_REG_BIT
4598 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4600 && (GET_MODE_SIZE (GET_MODE (src))
4601 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4603 && (GET_CODE (dest) == REG
4604 || (GET_CODE (dest) == SUBREG
4605 && GET_CODE (SUBREG_REG (dest)) == REG)))
4607 SUBST (SET_DEST (x),
4608 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4610 SUBST (SET_SRC (x), SUBREG_REG (src));
4612 src = SET_SRC (x), dest = SET_DEST (x);
4615 #ifdef LOAD_EXTEND_OP
4616 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4617 would require a paradoxical subreg. Replace the subreg with a
4618 zero_extend to avoid the reload that would otherwise be required. */
4620 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4621 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4622 && SUBREG_WORD (src) == 0
4623 && (GET_MODE_SIZE (GET_MODE (src))
4624 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4625 && GET_CODE (SUBREG_REG (src)) == MEM)
4628 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4629 GET_MODE (src), XEXP (src, 0)));
4635 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4636 are comparing an item known to be 0 or -1 against 0, use a logical
4637 operation instead. Check for one of the arms being an IOR of the other
4638 arm with some value. We compute three terms to be IOR'ed together. In
4639 practice, at most two will be nonzero. Then we do the IOR's. */
4641 if (GET_CODE (dest) != PC
4642 && GET_CODE (src) == IF_THEN_ELSE
4643 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4644 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4645 && XEXP (XEXP (src, 0), 1) == const0_rtx
4646 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4647 #ifdef HAVE_conditional_move
4648 && ! can_conditionally_move_p (GET_MODE (src))
4650 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4651 GET_MODE (XEXP (XEXP (src, 0), 0)))
4652 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4653 && ! side_effects_p (src))
4655 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4656 ? XEXP (src, 1) : XEXP (src, 2));
4657 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4658 ? XEXP (src, 2) : XEXP (src, 1));
4659 rtx term1 = const0_rtx, term2, term3;
4661 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4662 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4663 else if (GET_CODE (true) == IOR
4664 && rtx_equal_p (XEXP (true, 1), false))
4665 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4666 else if (GET_CODE (false) == IOR
4667 && rtx_equal_p (XEXP (false, 0), true))
4668 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4669 else if (GET_CODE (false) == IOR
4670 && rtx_equal_p (XEXP (false, 1), true))
4671 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4673 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4674 term3 = gen_binary (AND, GET_MODE (src),
4675 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4676 XEXP (XEXP (src, 0), 0)),
4680 gen_binary (IOR, GET_MODE (src),
4681 gen_binary (IOR, GET_MODE (src), term1, term2),
4687 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4688 whole thing fail. */
4689 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4691 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4694 /* Convert this into a field assignment operation, if possible. */
4695 return make_field_assignment (x);
4698 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4699 result. LAST is nonzero if this is the last retry. */
4702 simplify_logical (x, last)
4706 enum machine_mode mode = GET_MODE (x);
4707 rtx op0 = XEXP (x, 0);
4708 rtx op1 = XEXP (x, 1);
4710 switch (GET_CODE (x))
4713 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4714 insn (and may simplify more). */
4715 if (GET_CODE (op0) == XOR
4716 && rtx_equal_p (XEXP (op0, 0), op1)
4717 && ! side_effects_p (op1))
4718 x = gen_binary (AND, mode,
4719 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4721 if (GET_CODE (op0) == XOR
4722 && rtx_equal_p (XEXP (op0, 1), op1)
4723 && ! side_effects_p (op1))
4724 x = gen_binary (AND, mode,
4725 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4727 /* Similarly for (~ (A ^ B)) & A. */
4728 if (GET_CODE (op0) == NOT
4729 && GET_CODE (XEXP (op0, 0)) == XOR
4730 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4731 && ! side_effects_p (op1))
4732 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4734 if (GET_CODE (op0) == NOT
4735 && GET_CODE (XEXP (op0, 0)) == XOR
4736 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4737 && ! side_effects_p (op1))
4738 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4740 if (GET_CODE (op1) == CONST_INT)
4742 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4744 /* If we have (ior (and (X C1) C2)) and the next restart would be
4745 the last, simplify this by making C1 as small as possible
4748 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4749 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4750 && GET_CODE (op1) == CONST_INT)
4751 return gen_binary (IOR, mode,
4752 gen_binary (AND, mode, XEXP (op0, 0),
4753 GEN_INT (INTVAL (XEXP (op0, 1))
4754 & ~ INTVAL (op1))), op1);
4756 if (GET_CODE (x) != AND)
4759 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4760 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4761 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4764 /* Convert (A | B) & A to A. */
4765 if (GET_CODE (op0) == IOR
4766 && (rtx_equal_p (XEXP (op0, 0), op1)
4767 || rtx_equal_p (XEXP (op0, 1), op1))
4768 && ! side_effects_p (XEXP (op0, 0))
4769 && ! side_effects_p (XEXP (op0, 1)))
4772 /* In the following group of tests (and those in case IOR below),
4773 we start with some combination of logical operations and apply
4774 the distributive law followed by the inverse distributive law.
4775 Most of the time, this results in no change. However, if some of
4776 the operands are the same or inverses of each other, simplifications
4779 For example, (and (ior A B) (not B)) can occur as the result of
4780 expanding a bit field assignment. When we apply the distributive
4781 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4782 which then simplifies to (and (A (not B))).
4784 If we have (and (ior A B) C), apply the distributive law and then
4785 the inverse distributive law to see if things simplify. */
4787 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4789 x = apply_distributive_law
4790 (gen_binary (GET_CODE (op0), mode,
4791 gen_binary (AND, mode, XEXP (op0, 0), op1),
4792 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4793 if (GET_CODE (x) != AND)
4797 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4798 return apply_distributive_law
4799 (gen_binary (GET_CODE (op1), mode,
4800 gen_binary (AND, mode, XEXP (op1, 0), op0),
4801 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4803 /* Similarly, taking advantage of the fact that
4804 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4806 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4807 return apply_distributive_law
4808 (gen_binary (XOR, mode,
4809 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4810 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4812 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4813 return apply_distributive_law
4814 (gen_binary (XOR, mode,
4815 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4816 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4820 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4821 if (GET_CODE (op1) == CONST_INT
4822 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4823 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4826 /* Convert (A & B) | A to A. */
4827 if (GET_CODE (op0) == AND
4828 && (rtx_equal_p (XEXP (op0, 0), op1)
4829 || rtx_equal_p (XEXP (op0, 1), op1))
4830 && ! side_effects_p (XEXP (op0, 0))
4831 && ! side_effects_p (XEXP (op0, 1)))
4834 /* If we have (ior (and A B) C), apply the distributive law and then
4835 the inverse distributive law to see if things simplify. */
4837 if (GET_CODE (op0) == AND)
4839 x = apply_distributive_law
4840 (gen_binary (AND, mode,
4841 gen_binary (IOR, mode, XEXP (op0, 0), op1),
4842 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
4844 if (GET_CODE (x) != IOR)
4848 if (GET_CODE (op1) == AND)
4850 x = apply_distributive_law
4851 (gen_binary (AND, mode,
4852 gen_binary (IOR, mode, XEXP (op1, 0), op0),
4853 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
4855 if (GET_CODE (x) != IOR)
4859 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4860 mode size to (rotate A CX). */
4862 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
4863 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
4864 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
4865 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4866 && GET_CODE (XEXP (op1, 1)) == CONST_INT
4867 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
4868 == GET_MODE_BITSIZE (mode)))
4869 return gen_rtx (ROTATE, mode, XEXP (op0, 0),
4870 (GET_CODE (op0) == ASHIFT
4871 ? XEXP (op0, 1) : XEXP (op1, 1)));
4873 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
4874 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
4875 does not affect any of the bits in OP1, it can really be done
4876 as a PLUS and we can associate. We do this by seeing if OP1
4877 can be safely shifted left C bits. */
4878 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
4879 && GET_CODE (XEXP (op0, 0)) == PLUS
4880 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
4881 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4882 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
4884 int count = INTVAL (XEXP (op0, 1));
4885 HOST_WIDE_INT mask = INTVAL (op1) << count;
4887 if (mask >> count == INTVAL (op1)
4888 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
4890 SUBST (XEXP (XEXP (op0, 0), 1),
4891 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
4898 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4899 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4902 int num_negated = 0;
4904 if (GET_CODE (op0) == NOT)
4905 num_negated++, op0 = XEXP (op0, 0);
4906 if (GET_CODE (op1) == NOT)
4907 num_negated++, op1 = XEXP (op1, 0);
4909 if (num_negated == 2)
4911 SUBST (XEXP (x, 0), op0);
4912 SUBST (XEXP (x, 1), op1);
4914 else if (num_negated == 1)
4915 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
4918 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4919 correspond to a machine insn or result in further simplifications
4920 if B is a constant. */
4922 if (GET_CODE (op0) == AND
4923 && rtx_equal_p (XEXP (op0, 1), op1)
4924 && ! side_effects_p (op1))
4925 return gen_binary (AND, mode,
4926 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
4929 else if (GET_CODE (op0) == AND
4930 && rtx_equal_p (XEXP (op0, 0), op1)
4931 && ! side_effects_p (op1))
4932 return gen_binary (AND, mode,
4933 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
4936 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4937 comparison if STORE_FLAG_VALUE is 1. */
4938 if (STORE_FLAG_VALUE == 1
4939 && op1 == const1_rtx
4940 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4941 && reversible_comparison_p (op0))
4942 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4943 mode, XEXP (op0, 0), XEXP (op0, 1));
4945 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4946 is (lt foo (const_int 0)), so we can perform the above
4947 simplification if STORE_FLAG_VALUE is 1. */
4949 if (STORE_FLAG_VALUE == 1
4950 && op1 == const1_rtx
4951 && GET_CODE (op0) == LSHIFTRT
4952 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4953 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
4954 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
4956 /* (xor (comparison foo bar) (const_int sign-bit))
4957 when STORE_FLAG_VALUE is the sign bit. */
4958 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4959 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4960 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4961 && op1 == const_true_rtx
4962 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
4963 && reversible_comparison_p (op0))
4964 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
4965 mode, XEXP (op0, 0), XEXP (op0, 1));
4975 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4976 operations" because they can be replaced with two more basic operations.
4977 ZERO_EXTEND is also considered "compound" because it can be replaced with
4978 an AND operation, which is simpler, though only one operation.
4980 The function expand_compound_operation is called with an rtx expression
4981 and will convert it to the appropriate shifts and AND operations,
4982 simplifying at each stage.
4984 The function make_compound_operation is called to convert an expression
4985 consisting of shifts and ANDs into the equivalent compound expression.
4986 It is the inverse of this function, loosely speaking. */
4989 expand_compound_operation (x)
4997 switch (GET_CODE (x))
5002 /* We can't necessarily use a const_int for a multiword mode;
5003 it depends on implicitly extending the value.
5004 Since we don't know the right way to extend it,
5005 we can't tell whether the implicit way is right.
5007 Even for a mode that is no wider than a const_int,
5008 we can't win, because we need to sign extend one of its bits through
5009 the rest of it, and we don't know which bit. */
5010 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5013 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5014 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5015 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5016 reloaded. If not for that, MEM's would very rarely be safe.
5018 Reject MODEs bigger than a word, because we might not be able
5019 to reference a two-register group starting with an arbitrary register
5020 (and currently gen_lowpart might crash for a SUBREG). */
5022 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5025 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5026 /* If the inner object has VOIDmode (the only way this can happen
5027 is if it is a ASM_OPERANDS), we can't do anything since we don't
5028 know how much masking to do. */
5037 /* If the operand is a CLOBBER, just return it. */
5038 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5041 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5042 || GET_CODE (XEXP (x, 2)) != CONST_INT
5043 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5046 len = INTVAL (XEXP (x, 1));
5047 pos = INTVAL (XEXP (x, 2));
5049 /* If this goes outside the object being extracted, replace the object
5050 with a (use (mem ...)) construct that only combine understands
5051 and is used only for this purpose. */
5052 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5053 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
5055 if (BITS_BIG_ENDIAN)
5056 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5064 /* We can optimize some special cases of ZERO_EXTEND. */
5065 if (GET_CODE (x) == ZERO_EXTEND)
5067 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5068 know that the last value didn't have any inappropriate bits
5070 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5071 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5072 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5073 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5074 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5075 return XEXP (XEXP (x, 0), 0);
5077 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5078 if (GET_CODE (XEXP (x, 0)) == SUBREG
5079 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5080 && subreg_lowpart_p (XEXP (x, 0))
5081 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5082 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5083 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0)
5084 return SUBREG_REG (XEXP (x, 0));
5086 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5087 is a comparison and STORE_FLAG_VALUE permits. This is like
5088 the first case, but it works even when GET_MODE (x) is larger
5089 than HOST_WIDE_INT. */
5090 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5091 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5092 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5093 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5094 <= HOST_BITS_PER_WIDE_INT)
5095 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5096 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5097 return XEXP (XEXP (x, 0), 0);
5099 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5100 if (GET_CODE (XEXP (x, 0)) == SUBREG
5101 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5102 && subreg_lowpart_p (XEXP (x, 0))
5103 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5104 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5105 <= HOST_BITS_PER_WIDE_INT)
5106 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5107 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5108 return SUBREG_REG (XEXP (x, 0));
5110 /* If sign extension is cheaper than zero extension, then use it
5111 if we know that no extraneous bits are set, and that the high
5113 if (flag_expensive_optimizations
5114 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5115 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5116 & ~ (((unsigned HOST_WIDE_INT)
5117 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5120 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5121 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5122 <= HOST_BITS_PER_WIDE_INT)
5123 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5124 & ~ (((unsigned HOST_WIDE_INT)
5125 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5129 rtx temp = gen_rtx (SIGN_EXTEND, GET_MODE (x), XEXP (x, 0));
5131 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5132 return expand_compound_operation (temp);
5136 /* If we reach here, we want to return a pair of shifts. The inner
5137 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5138 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5139 logical depending on the value of UNSIGNEDP.
5141 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5142 converted into an AND of a shift.
5144 We must check for the case where the left shift would have a negative
5145 count. This can happen in a case like (x >> 31) & 255 on machines
5146 that can't shift by a constant. On those machines, we would first
5147 combine the shift with the AND to produce a variable-position
5148 extraction. Then the constant of 31 would be substituted in to produce
5149 a such a position. */
5151 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5152 if (modewidth >= pos - len)
5153 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5155 simplify_shift_const (NULL_RTX, ASHIFT,
5158 modewidth - pos - len),
5161 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5162 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5163 simplify_shift_const (NULL_RTX, LSHIFTRT,
5166 ((HOST_WIDE_INT) 1 << len) - 1);
5168 /* Any other cases we can't handle. */
5172 /* If we couldn't do this for some reason, return the original
5174 if (GET_CODE (tem) == CLOBBER)
5180 /* X is a SET which contains an assignment of one object into
5181 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5182 or certain SUBREGS). If possible, convert it into a series of
5185 We half-heartedly support variable positions, but do not at all
5186 support variable lengths. */
5189 expand_field_assignment (x)
5193 rtx pos; /* Always counts from low bit. */
5196 enum machine_mode compute_mode;
5198 /* Loop until we find something we can't simplify. */
5201 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5202 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5204 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5205 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5206 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5208 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5209 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5211 inner = XEXP (SET_DEST (x), 0);
5212 len = INTVAL (XEXP (SET_DEST (x), 1));
5213 pos = XEXP (SET_DEST (x), 2);
5215 /* If the position is constant and spans the width of INNER,
5216 surround INNER with a USE to indicate this. */
5217 if (GET_CODE (pos) == CONST_INT
5218 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5219 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
5221 if (BITS_BIG_ENDIAN)
5223 if (GET_CODE (pos) == CONST_INT)
5224 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5226 else if (GET_CODE (pos) == MINUS
5227 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5228 && (INTVAL (XEXP (pos, 1))
5229 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5230 /* If position is ADJUST - X, new position is X. */
5231 pos = XEXP (pos, 0);
5233 pos = gen_binary (MINUS, GET_MODE (pos),
5234 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5240 /* A SUBREG between two modes that occupy the same numbers of words
5241 can be done by moving the SUBREG to the source. */
5242 else if (GET_CODE (SET_DEST (x)) == SUBREG
5243 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5244 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5245 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5246 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5248 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
5249 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5256 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5257 inner = SUBREG_REG (inner);
5259 compute_mode = GET_MODE (inner);
5261 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5262 if (len < HOST_BITS_PER_WIDE_INT)
5263 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5267 /* Now compute the equivalent expression. Make a copy of INNER
5268 for the SET_DEST in case it is a MEM into which we will substitute;
5269 we don't want shared RTL in that case. */
5270 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
5271 gen_binary (IOR, compute_mode,
5272 gen_binary (AND, compute_mode,
5273 gen_unary (NOT, compute_mode,
5279 gen_binary (ASHIFT, compute_mode,
5280 gen_binary (AND, compute_mode,
5281 gen_lowpart_for_combine
5291 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5292 it is an RTX that represents a variable starting position; otherwise,
5293 POS is the (constant) starting bit position (counted from the LSB).
5295 INNER may be a USE. This will occur when we started with a bitfield
5296 that went outside the boundary of the object in memory, which is
5297 allowed on most machines. To isolate this case, we produce a USE
5298 whose mode is wide enough and surround the MEM with it. The only
5299 code that understands the USE is this routine. If it is not removed,
5300 it will cause the resulting insn not to match.
5302 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5305 IN_DEST is non-zero if this is a reference in the destination of a
5306 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5307 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5310 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5311 ZERO_EXTRACT should be built even for bits starting at bit 0.
5313 MODE is the desired mode of the result (if IN_DEST == 0).
5315 The result is an RTX for the extraction or NULL_RTX if the target
5319 make_extraction (mode, inner, pos, pos_rtx, len,
5320 unsignedp, in_dest, in_compare)
5321 enum machine_mode mode;
5327 int in_dest, in_compare;
5329 /* This mode describes the size of the storage area
5330 to fetch the overall value from. Within that, we
5331 ignore the POS lowest bits, etc. */
5332 enum machine_mode is_mode = GET_MODE (inner);
5333 enum machine_mode inner_mode;
5334 enum machine_mode wanted_inner_mode = byte_mode;
5335 enum machine_mode wanted_inner_reg_mode = word_mode;
5336 enum machine_mode pos_mode = word_mode;
5337 enum machine_mode extraction_mode = word_mode;
5338 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5341 rtx orig_pos_rtx = pos_rtx;
5344 /* Get some information about INNER and get the innermost object. */
5345 if (GET_CODE (inner) == USE)
5346 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5347 /* We don't need to adjust the position because we set up the USE
5348 to pretend that it was a full-word object. */
5349 spans_byte = 1, inner = XEXP (inner, 0);
5350 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5352 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5353 consider just the QI as the memory to extract from.
5354 The subreg adds or removes high bits; its mode is
5355 irrelevant to the meaning of this extraction,
5356 since POS and LEN count from the lsb. */
5357 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5358 is_mode = GET_MODE (SUBREG_REG (inner));
5359 inner = SUBREG_REG (inner);
5362 inner_mode = GET_MODE (inner);
5364 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5365 pos = INTVAL (pos_rtx), pos_rtx = 0;
5367 /* See if this can be done without an extraction. We never can if the
5368 width of the field is not the same as that of some integer mode. For
5369 registers, we can only avoid the extraction if the position is at the
5370 low-order bit and this is either not in the destination or we have the
5371 appropriate STRICT_LOW_PART operation available.
5373 For MEM, we can avoid an extract if the field starts on an appropriate
5374 boundary and we can change the mode of the memory reference. However,
5375 we cannot directly access the MEM if we have a USE and the underlying
5376 MEM is not TMODE. This combination means that MEM was being used in a
5377 context where bits outside its mode were being referenced; that is only
5378 valid in bit-field insns. */
5380 if (tmode != BLKmode
5381 && ! (spans_byte && inner_mode != tmode)
5382 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5383 && GET_CODE (inner) != MEM
5385 || (GET_CODE (inner) == REG
5386 && (movstrict_optab->handlers[(int) tmode].insn_code
5387 != CODE_FOR_nothing))))
5388 || (GET_CODE (inner) == MEM && pos_rtx == 0
5390 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5391 : BITS_PER_UNIT)) == 0
5392 /* We can't do this if we are widening INNER_MODE (it
5393 may not be aligned, for one thing). */
5394 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5395 && (inner_mode == tmode
5396 || (! mode_dependent_address_p (XEXP (inner, 0))
5397 && ! MEM_VOLATILE_P (inner))))))
5399 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5400 field. If the original and current mode are the same, we need not
5401 adjust the offset. Otherwise, we do if bytes big endian.
5403 If INNER is not a MEM, get a piece consisting of just the field
5404 of interest (in this case POS % BITS_PER_WORD must be 0). */
5406 if (GET_CODE (inner) == MEM)
5409 /* POS counts from lsb, but make OFFSET count in memory order. */
5410 if (BYTES_BIG_ENDIAN)
5411 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5413 offset = pos / BITS_PER_UNIT;
5415 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
5416 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5417 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
5418 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
5420 else if (GET_CODE (inner) == REG)
5422 /* We can't call gen_lowpart_for_combine here since we always want
5423 a SUBREG and it would sometimes return a new hard register. */
5424 if (tmode != inner_mode)
5425 new = gen_rtx (SUBREG, tmode, inner,
5427 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5428 ? (((GET_MODE_SIZE (inner_mode)
5429 - GET_MODE_SIZE (tmode))
5431 - pos / BITS_PER_WORD)
5432 : pos / BITS_PER_WORD));
5437 new = force_to_mode (inner, tmode,
5438 len >= HOST_BITS_PER_WIDE_INT
5439 ? GET_MODE_MASK (tmode)
5440 : ((HOST_WIDE_INT) 1 << len) - 1,
5443 /* If this extraction is going into the destination of a SET,
5444 make a STRICT_LOW_PART unless we made a MEM. */
5447 return (GET_CODE (new) == MEM ? new
5448 : (GET_CODE (new) != SUBREG
5449 ? gen_rtx (CLOBBER, tmode, const0_rtx)
5450 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5452 /* Otherwise, sign- or zero-extend unless we already are in the
5455 return (mode == tmode ? new
5456 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5460 /* Unless this is a COMPARE or we have a funny memory reference,
5461 don't do anything with zero-extending field extracts starting at
5462 the low-order bit since they are simple AND operations. */
5463 if (pos_rtx == 0 && pos == 0 && ! in_dest
5464 && ! in_compare && ! spans_byte && unsignedp)
5467 /* Unless we are allowed to span bytes, reject this if we would be
5468 spanning bytes or if the position is not a constant and the length
5469 is not 1. In all other cases, we would only be going outside
5470 out object in cases when an original shift would have been
5473 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5474 || (pos_rtx != 0 && len != 1)))
5477 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5478 and the mode for the result. */
5482 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
5483 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
5484 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
5489 if (! in_dest && unsignedp)
5491 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
5492 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
5493 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
5498 if (! in_dest && ! unsignedp)
5500 wanted_inner_reg_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
5501 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
5502 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
5506 /* Never narrow an object, since that might not be safe. */
5508 if (mode != VOIDmode
5509 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5510 extraction_mode = mode;
5512 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5513 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5514 pos_mode = GET_MODE (pos_rtx);
5516 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5517 if we have to change the mode of memory and cannot, the desired mode is
5519 if (GET_CODE (inner) != MEM)
5520 wanted_inner_mode = wanted_inner_reg_mode;
5521 else if (inner_mode != wanted_inner_mode
5522 && (mode_dependent_address_p (XEXP (inner, 0))
5523 || MEM_VOLATILE_P (inner)))
5524 wanted_inner_mode = extraction_mode;
5528 if (BITS_BIG_ENDIAN)
5530 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5531 BITS_BIG_ENDIAN style. If position is constant, compute new
5532 position. Otherwise, build subtraction.
5533 Note that POS is relative to the mode of the original argument.
5534 If it's a MEM we need to recompute POS relative to that.
5535 However, if we're extracting from (or inserting into) a register,
5536 we want to recompute POS relative to wanted_inner_mode. */
5537 int width = (GET_CODE (inner) == MEM
5538 ? GET_MODE_BITSIZE (is_mode)
5539 : GET_MODE_BITSIZE (wanted_inner_mode));
5542 pos = width - len - pos;
5545 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5546 GEN_INT (width - len), pos_rtx);
5547 /* POS may be less than 0 now, but we check for that below.
5548 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5551 /* If INNER has a wider mode, make it smaller. If this is a constant
5552 extract, try to adjust the byte to point to the byte containing
5554 if (wanted_inner_mode != VOIDmode
5555 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5556 && ((GET_CODE (inner) == MEM
5557 && (inner_mode == wanted_inner_mode
5558 || (! mode_dependent_address_p (XEXP (inner, 0))
5559 && ! MEM_VOLATILE_P (inner))))))
5563 /* The computations below will be correct if the machine is big
5564 endian in both bits and bytes or little endian in bits and bytes.
5565 If it is mixed, we must adjust. */
5567 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5568 adjust OFFSET to compensate. */
5569 if (BYTES_BIG_ENDIAN
5571 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5572 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5574 /* If this is a constant position, we can move to the desired byte. */
5577 offset += pos / BITS_PER_UNIT;
5578 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5581 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5583 && is_mode != wanted_inner_mode)
5584 offset = (GET_MODE_SIZE (is_mode)
5585 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5587 if (offset != 0 || inner_mode != wanted_inner_mode)
5589 rtx newmem = gen_rtx (MEM, wanted_inner_mode,
5590 plus_constant (XEXP (inner, 0), offset));
5591 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5592 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
5593 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
5598 /* If INNER is not memory, we can always get it into the proper mode. If we
5599 are changing its mode, POS must be a constant and smaller than the size
5601 else if (GET_CODE (inner) != MEM)
5603 if (GET_MODE (inner) != wanted_inner_mode
5605 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5608 inner = force_to_mode (inner, wanted_inner_mode,
5610 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5611 ? GET_MODE_MASK (wanted_inner_mode)
5612 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5616 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5617 have to zero extend. Otherwise, we can just use a SUBREG. */
5619 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5620 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5621 else if (pos_rtx != 0
5622 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5623 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5625 /* Make POS_RTX unless we already have it and it is correct. If we don't
5626 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5628 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5629 pos_rtx = orig_pos_rtx;
5631 else if (pos_rtx == 0)
5632 pos_rtx = GEN_INT (pos);
5634 /* Make the required operation. See if we can use existing rtx. */
5635 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5636 extraction_mode, inner, GEN_INT (len), pos_rtx);
5638 new = gen_lowpart_for_combine (mode, new);
5643 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5644 with any other operations in X. Return X without that shift if so. */
5647 extract_left_shift (x, count)
5651 enum rtx_code code = GET_CODE (x);
5652 enum machine_mode mode = GET_MODE (x);
5658 /* This is the shift itself. If it is wide enough, we will return
5659 either the value being shifted if the shift count is equal to
5660 COUNT or a shift for the difference. */
5661 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5662 && INTVAL (XEXP (x, 1)) >= count)
5663 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5664 INTVAL (XEXP (x, 1)) - count);
5668 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5669 return gen_unary (code, mode, mode, tem);
5673 case PLUS: case IOR: case XOR: case AND:
5674 /* If we can safely shift this constant and we find the inner shift,
5675 make a new operation. */
5676 if (GET_CODE (XEXP (x,1)) == CONST_INT
5677 && (INTVAL (XEXP (x, 1)) & (((HOST_WIDE_INT) 1 << count)) - 1) == 0
5678 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5679 return gen_binary (code, mode, tem,
5680 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5691 /* Look at the expression rooted at X. Look for expressions
5692 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5693 Form these expressions.
5695 Return the new rtx, usually just X.
5697 Also, for machines like the Vax that don't have logical shift insns,
5698 try to convert logical to arithmetic shift operations in cases where
5699 they are equivalent. This undoes the canonicalizations to logical
5700 shifts done elsewhere.
5702 We try, as much as possible, to re-use rtl expressions to save memory.
5704 IN_CODE says what kind of expression we are processing. Normally, it is
5705 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5706 being kludges), it is MEM. When processing the arguments of a comparison
5707 or a COMPARE against zero, it is COMPARE. */
5710 make_compound_operation (x, in_code)
5712 enum rtx_code in_code;
5714 enum rtx_code code = GET_CODE (x);
5715 enum machine_mode mode = GET_MODE (x);
5716 int mode_width = GET_MODE_BITSIZE (mode);
5718 enum rtx_code next_code;
5724 /* Select the code to be used in recursive calls. Once we are inside an
5725 address, we stay there. If we have a comparison, set to COMPARE,
5726 but once inside, go back to our default of SET. */
5728 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5729 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5730 && XEXP (x, 1) == const0_rtx) ? COMPARE
5731 : in_code == COMPARE ? SET : in_code);
5733 /* Process depending on the code of this operation. If NEW is set
5734 non-zero, it will be returned. */
5739 /* Convert shifts by constants into multiplications if inside
5741 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5742 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5743 && INTVAL (XEXP (x, 1)) >= 0)
5745 new = make_compound_operation (XEXP (x, 0), next_code);
5746 new = gen_rtx_combine (MULT, mode, new,
5747 GEN_INT ((HOST_WIDE_INT) 1
5748 << INTVAL (XEXP (x, 1))));
5753 /* If the second operand is not a constant, we can't do anything
5755 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5758 /* If the constant is a power of two minus one and the first operand
5759 is a logical right shift, make an extraction. */
5760 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5761 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5763 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5764 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5765 0, in_code == COMPARE);
5768 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5769 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5770 && subreg_lowpart_p (XEXP (x, 0))
5771 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5772 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5774 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5776 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5777 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5778 0, in_code == COMPARE);
5780 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5781 else if ((GET_CODE (XEXP (x, 0)) == XOR
5782 || GET_CODE (XEXP (x, 0)) == IOR)
5783 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5784 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5785 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5787 /* Apply the distributive law, and then try to make extractions. */
5788 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5789 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 0),
5791 gen_rtx (AND, mode, XEXP (XEXP (x, 0), 1),
5793 new = make_compound_operation (new, in_code);
5796 /* If we are have (and (rotate X C) M) and C is larger than the number
5797 of bits in M, this is an extraction. */
5799 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5800 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5801 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5802 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5804 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5805 new = make_extraction (mode, new,
5806 (GET_MODE_BITSIZE (mode)
5807 - INTVAL (XEXP (XEXP (x, 0), 1))),
5808 NULL_RTX, i, 1, 0, in_code == COMPARE);
5811 /* On machines without logical shifts, if the operand of the AND is
5812 a logical shift and our mask turns off all the propagated sign
5813 bits, we can replace the logical shift with an arithmetic shift. */
5814 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5815 && (lshr_optab->handlers[(int) mode].insn_code
5816 == CODE_FOR_nothing)
5817 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5818 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5819 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5820 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5821 && mode_width <= HOST_BITS_PER_WIDE_INT)
5823 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5825 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5826 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5828 gen_rtx_combine (ASHIFTRT, mode,
5829 make_compound_operation (XEXP (XEXP (x, 0), 0),
5831 XEXP (XEXP (x, 0), 1)));
5834 /* If the constant is one less than a power of two, this might be
5835 representable by an extraction even if no shift is present.
5836 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5837 we are in a COMPARE. */
5838 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5839 new = make_extraction (mode,
5840 make_compound_operation (XEXP (x, 0),
5842 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5844 /* If we are in a comparison and this is an AND with a power of two,
5845 convert this into the appropriate bit extract. */
5846 else if (in_code == COMPARE
5847 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5848 new = make_extraction (mode,
5849 make_compound_operation (XEXP (x, 0),
5851 i, NULL_RTX, 1, 1, 0, 1);
5856 /* If the sign bit is known to be zero, replace this with an
5857 arithmetic shift. */
5858 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5859 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5860 && mode_width <= HOST_BITS_PER_WIDE_INT
5861 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5863 new = gen_rtx_combine (ASHIFTRT, mode,
5864 make_compound_operation (XEXP (x, 0),
5870 /* ... fall through ... */
5876 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5877 this is a SIGN_EXTRACT. */
5878 if (GET_CODE (rhs) == CONST_INT
5879 && GET_CODE (lhs) == ASHIFT
5880 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
5881 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
5883 new = make_compound_operation (XEXP (lhs, 0), next_code);
5884 new = make_extraction (mode, new,
5885 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
5886 NULL_RTX, mode_width - INTVAL (rhs),
5887 code == LSHIFTRT, 0, in_code == COMPARE);
5890 /* See if we have operations between an ASHIFTRT and an ASHIFT.
5891 If so, try to merge the shifts into a SIGN_EXTEND. We could
5892 also do this for some cases of SIGN_EXTRACT, but it doesn't
5893 seem worth the effort; the case checked for occurs on Alpha. */
5895 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
5896 && ! (GET_CODE (lhs) == SUBREG
5897 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
5898 && GET_CODE (rhs) == CONST_INT
5899 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
5900 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
5901 new = make_extraction (mode, make_compound_operation (new, next_code),
5902 0, NULL_RTX, mode_width - INTVAL (rhs),
5903 code == LSHIFTRT, 0, in_code == COMPARE);
5908 /* Call ourselves recursively on the inner expression. If we are
5909 narrowing the object and it has a different RTL code from
5910 what it originally did, do this SUBREG as a force_to_mode. */
5912 tem = make_compound_operation (SUBREG_REG (x), in_code);
5913 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5914 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5915 && subreg_lowpart_p (x))
5917 rtx newer = force_to_mode (tem, mode,
5918 GET_MODE_MASK (mode), NULL_RTX, 0);
5920 /* If we have something other than a SUBREG, we might have
5921 done an expansion, so rerun outselves. */
5922 if (GET_CODE (newer) != SUBREG)
5923 newer = make_compound_operation (newer, in_code);
5935 x = gen_lowpart_for_combine (mode, new);
5936 code = GET_CODE (x);
5939 /* Now recursively process each operand of this operation. */
5940 fmt = GET_RTX_FORMAT (code);
5941 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5944 new = make_compound_operation (XEXP (x, i), next_code);
5945 SUBST (XEXP (x, i), new);
5951 /* Given M see if it is a value that would select a field of bits
5952 within an item, but not the entire word. Return -1 if not.
5953 Otherwise, return the starting position of the field, where 0 is the
5956 *PLEN is set to the length of the field. */
5959 get_pos_from_mask (m, plen)
5960 unsigned HOST_WIDE_INT m;
5963 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5964 int pos = exact_log2 (m & - m);
5969 /* Now shift off the low-order zero bits and see if we have a power of
5971 *plen = exact_log2 ((m >> pos) + 1);
5979 /* See if X can be simplified knowing that we will only refer to it in
5980 MODE and will only refer to those bits that are nonzero in MASK.
5981 If other bits are being computed or if masking operations are done
5982 that select a superset of the bits in MASK, they can sometimes be
5985 Return a possibly simplified expression, but always convert X to
5986 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
5988 Also, if REG is non-zero and X is a register equal in value to REG,
5991 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
5992 are all off in X. This is used when X will be complemented, by either
5993 NOT, NEG, or XOR. */
5996 force_to_mode (x, mode, mask, reg, just_select)
5998 enum machine_mode mode;
5999 unsigned HOST_WIDE_INT mask;
6003 enum rtx_code code = GET_CODE (x);
6004 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6005 enum machine_mode op_mode;
6006 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6009 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6010 code below will do the wrong thing since the mode of such an
6011 expression is VOIDmode. */
6012 if (code == CALL || code == ASM_OPERANDS)
6015 /* We want to perform the operation is its present mode unless we know
6016 that the operation is valid in MODE, in which case we do the operation
6018 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6019 && code_to_optab[(int) code] != 0
6020 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6021 != CODE_FOR_nothing))
6022 ? mode : GET_MODE (x));
6024 /* It is not valid to do a right-shift in a narrower mode
6025 than the one it came in with. */
6026 if ((code == LSHIFTRT || code == ASHIFTRT)
6027 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6028 op_mode = GET_MODE (x);
6030 /* Truncate MASK to fit OP_MODE. */
6032 mask &= GET_MODE_MASK (op_mode);
6034 /* When we have an arithmetic operation, or a shift whose count we
6035 do not know, we need to assume that all bit the up to the highest-order
6036 bit in MASK will be needed. This is how we form such a mask. */
6038 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6039 ? GET_MODE_MASK (op_mode)
6040 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6042 fuller_mask = ~ (HOST_WIDE_INT) 0;
6044 /* Determine what bits of X are guaranteed to be (non)zero. */
6045 nonzero = nonzero_bits (x, mode);
6047 /* If none of the bits in X are needed, return a zero. */
6048 if (! just_select && (nonzero & mask) == 0)
6051 /* If X is a CONST_INT, return a new one. Do this here since the
6052 test below will fail. */
6053 if (GET_CODE (x) == CONST_INT)
6055 HOST_WIDE_INT cval = INTVAL (x) & mask;
6056 int width = GET_MODE_BITSIZE (mode);
6058 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6059 number, sign extend it. */
6060 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6061 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6062 cval |= (HOST_WIDE_INT) -1 << width;
6064 return GEN_INT (cval);
6067 /* If X is narrower than MODE and we want all the bits in X's mode, just
6068 get X in the proper mode. */
6069 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6070 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6071 return gen_lowpart_for_combine (mode, x);
6073 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6074 MASK are already known to be zero in X, we need not do anything. */
6075 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6081 /* If X is a (clobber (const_int)), return it since we know we are
6082 generating something that won't match. */
6086 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6087 spanned the boundary of the MEM. If we are now masking so it is
6088 within that boundary, we don't need the USE any more. */
6089 if (! BITS_BIG_ENDIAN
6090 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6091 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6098 x = expand_compound_operation (x);
6099 if (GET_CODE (x) != code)
6100 return force_to_mode (x, mode, mask, reg, next_select);
6104 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6105 || rtx_equal_p (reg, get_last_value (x))))
6110 if (subreg_lowpart_p (x)
6111 /* We can ignore the effect of this SUBREG if it narrows the mode or
6112 if the constant masks to zero all the bits the mode doesn't
6114 && ((GET_MODE_SIZE (GET_MODE (x))
6115 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6117 & GET_MODE_MASK (GET_MODE (x))
6118 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6119 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6123 /* If this is an AND with a constant, convert it into an AND
6124 whose constant is the AND of that constant with MASK. If it
6125 remains an AND of MASK, delete it since it is redundant. */
6127 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6129 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6130 mask & INTVAL (XEXP (x, 1)));
6132 /* If X is still an AND, see if it is an AND with a mask that
6133 is just some low-order bits. If so, and it is MASK, we don't
6136 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6137 && INTVAL (XEXP (x, 1)) == mask)
6140 /* If it remains an AND, try making another AND with the bits
6141 in the mode mask that aren't in MASK turned on. If the
6142 constant in the AND is wide enough, this might make a
6143 cheaper constant. */
6145 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6146 && GET_MODE_MASK (GET_MODE (x)) != mask
6147 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6149 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6150 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6151 int width = GET_MODE_BITSIZE (GET_MODE (x));
6154 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6155 number, sign extend it. */
6156 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6157 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6158 cval |= (HOST_WIDE_INT) -1 << width;
6160 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6161 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6171 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6172 low-order bits (as in an alignment operation) and FOO is already
6173 aligned to that boundary, mask C1 to that boundary as well.
6174 This may eliminate that PLUS and, later, the AND. */
6177 int width = GET_MODE_BITSIZE (mode);
6178 unsigned HOST_WIDE_INT smask = mask;
6180 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6181 number, sign extend it. */
6183 if (width < HOST_BITS_PER_WIDE_INT
6184 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6185 smask |= (HOST_WIDE_INT) -1 << width;
6187 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6188 && exact_log2 (- smask) >= 0
6189 && (nonzero_bits (XEXP (x, 0), mode) & ~ mask) == 0
6190 && (INTVAL (XEXP (x, 1)) & ~ mask) != 0)
6191 return force_to_mode (plus_constant (XEXP (x, 0),
6192 INTVAL (XEXP (x, 1)) & mask),
6193 mode, mask, reg, next_select);
6196 /* ... fall through ... */
6200 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6201 most significant bit in MASK since carries from those bits will
6202 affect the bits we are interested in. */
6208 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6209 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6210 operation which may be a bitfield extraction. Ensure that the
6211 constant we form is not wider than the mode of X. */
6213 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6214 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6215 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6216 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6217 && GET_CODE (XEXP (x, 1)) == CONST_INT
6218 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6219 + floor_log2 (INTVAL (XEXP (x, 1))))
6220 < GET_MODE_BITSIZE (GET_MODE (x)))
6221 && (INTVAL (XEXP (x, 1))
6222 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6224 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6225 << INTVAL (XEXP (XEXP (x, 0), 1)));
6226 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6227 XEXP (XEXP (x, 0), 0), temp);
6228 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6229 XEXP (XEXP (x, 0), 1));
6230 return force_to_mode (x, mode, mask, reg, next_select);
6234 /* For most binary operations, just propagate into the operation and
6235 change the mode if we have an operation of that mode. */
6237 op0 = gen_lowpart_for_combine (op_mode,
6238 force_to_mode (XEXP (x, 0), mode, mask,
6240 op1 = gen_lowpart_for_combine (op_mode,
6241 force_to_mode (XEXP (x, 1), mode, mask,
6244 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6245 MASK since OP1 might have been sign-extended but we never want
6246 to turn on extra bits, since combine might have previously relied
6247 on them being off. */
6248 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6249 && (INTVAL (op1) & mask) != 0)
6250 op1 = GEN_INT (INTVAL (op1) & mask);
6252 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6253 x = gen_binary (code, op_mode, op0, op1);
6257 /* For left shifts, do the same, but just for the first operand.
6258 However, we cannot do anything with shifts where we cannot
6259 guarantee that the counts are smaller than the size of the mode
6260 because such a count will have a different meaning in a
6263 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6264 && INTVAL (XEXP (x, 1)) >= 0
6265 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6266 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6267 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6268 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6271 /* If the shift count is a constant and we can do arithmetic in
6272 the mode of the shift, refine which bits we need. Otherwise, use the
6273 conservative form of the mask. */
6274 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6275 && INTVAL (XEXP (x, 1)) >= 0
6276 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6277 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6278 mask >>= INTVAL (XEXP (x, 1));
6282 op0 = gen_lowpart_for_combine (op_mode,
6283 force_to_mode (XEXP (x, 0), op_mode,
6284 mask, reg, next_select));
6286 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6287 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6291 /* Here we can only do something if the shift count is a constant,
6292 this shift constant is valid for the host, and we can do arithmetic
6295 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6296 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6297 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6299 rtx inner = XEXP (x, 0);
6301 /* Select the mask of the bits we need for the shift operand. */
6302 mask <<= INTVAL (XEXP (x, 1));
6304 /* We can only change the mode of the shift if we can do arithmetic
6305 in the mode of the shift and MASK is no wider than the width of
6307 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6308 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6309 op_mode = GET_MODE (x);
6311 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6313 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6314 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6317 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6318 shift and AND produces only copies of the sign bit (C2 is one less
6319 than a power of two), we can do this with just a shift. */
6321 if (GET_CODE (x) == LSHIFTRT
6322 && GET_CODE (XEXP (x, 1)) == CONST_INT
6323 && ((INTVAL (XEXP (x, 1))
6324 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6325 >= GET_MODE_BITSIZE (GET_MODE (x)))
6326 && exact_log2 (mask + 1) >= 0
6327 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6328 >= exact_log2 (mask + 1)))
6329 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6330 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6331 - exact_log2 (mask + 1)));
6335 /* If we are just looking for the sign bit, we don't need this shift at
6336 all, even if it has a variable count. */
6337 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6338 && (mask == ((HOST_WIDE_INT) 1
6339 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6340 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6342 /* If this is a shift by a constant, get a mask that contains those bits
6343 that are not copies of the sign bit. We then have two cases: If
6344 MASK only includes those bits, this can be a logical shift, which may
6345 allow simplifications. If MASK is a single-bit field not within
6346 those bits, we are requesting a copy of the sign bit and hence can
6347 shift the sign bit to the appropriate location. */
6349 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6350 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6354 /* If the considered data is wider then HOST_WIDE_INT, we can't
6355 represent a mask for all its bits in a single scalar.
6356 But we only care about the lower bits, so calculate these. */
6358 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6360 nonzero = ~ (HOST_WIDE_INT) 0;
6362 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6363 is the number of bits a full-width mask would have set.
6364 We need only shift if these are fewer than nonzero can
6365 hold. If not, we must keep all bits set in nonzero. */
6367 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6368 < HOST_BITS_PER_WIDE_INT)
6369 nonzero >>= INTVAL (XEXP (x, 1))
6370 + HOST_BITS_PER_WIDE_INT
6371 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6375 nonzero = GET_MODE_MASK (GET_MODE (x));
6376 nonzero >>= INTVAL (XEXP (x, 1));
6379 if ((mask & ~ nonzero) == 0
6380 || (i = exact_log2 (mask)) >= 0)
6382 x = simplify_shift_const
6383 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6384 i < 0 ? INTVAL (XEXP (x, 1))
6385 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6387 if (GET_CODE (x) != ASHIFTRT)
6388 return force_to_mode (x, mode, mask, reg, next_select);
6392 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6393 even if the shift count isn't a constant. */
6395 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6397 /* If this is a sign-extension operation that just affects bits
6398 we don't care about, remove it. Be sure the call above returned
6399 something that is still a shift. */
6401 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6402 && GET_CODE (XEXP (x, 1)) == CONST_INT
6403 && INTVAL (XEXP (x, 1)) >= 0
6404 && (INTVAL (XEXP (x, 1))
6405 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6406 && GET_CODE (XEXP (x, 0)) == ASHIFT
6407 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6408 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6409 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6416 /* If the shift count is constant and we can do computations
6417 in the mode of X, compute where the bits we care about are.
6418 Otherwise, we can't do anything. Don't change the mode of
6419 the shift or propagate MODE into the shift, though. */
6420 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6421 && INTVAL (XEXP (x, 1)) >= 0)
6423 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6424 GET_MODE (x), GEN_INT (mask),
6426 if (temp && GET_CODE(temp) == CONST_INT)
6428 force_to_mode (XEXP (x, 0), GET_MODE (x),
6429 INTVAL (temp), reg, next_select));
6434 /* If we just want the low-order bit, the NEG isn't needed since it
6435 won't change the low-order bit. */
6437 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6439 /* We need any bits less significant than the most significant bit in
6440 MASK since carries from those bits will affect the bits we are
6446 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6447 same as the XOR case above. Ensure that the constant we form is not
6448 wider than the mode of X. */
6450 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6451 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6452 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6453 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6454 < GET_MODE_BITSIZE (GET_MODE (x)))
6455 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6457 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6458 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6459 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6461 return force_to_mode (x, mode, mask, reg, next_select);
6464 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6465 use the full mask inside the NOT. */
6469 op0 = gen_lowpart_for_combine (op_mode,
6470 force_to_mode (XEXP (x, 0), mode, mask,
6472 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6473 x = gen_unary (code, op_mode, op_mode, op0);
6477 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6478 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6479 which is equal to STORE_FLAG_VALUE. */
6480 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6481 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6482 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6483 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6488 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6489 written in a narrower mode. We play it safe and do not do so. */
6492 gen_lowpart_for_combine (GET_MODE (x),
6493 force_to_mode (XEXP (x, 1), mode,
6494 mask, reg, next_select)));
6496 gen_lowpart_for_combine (GET_MODE (x),
6497 force_to_mode (XEXP (x, 2), mode,
6498 mask, reg,next_select)));
6505 /* Ensure we return a value of the proper mode. */
6506 return gen_lowpart_for_combine (mode, x);
6509 /* Return nonzero if X is an expression that has one of two values depending on
6510 whether some other value is zero or nonzero. In that case, we return the
6511 value that is being tested, *PTRUE is set to the value if the rtx being
6512 returned has a nonzero value, and *PFALSE is set to the other alternative.
6514 If we return zero, we set *PTRUE and *PFALSE to X. */
6517 if_then_else_cond (x, ptrue, pfalse)
6519 rtx *ptrue, *pfalse;
6521 enum machine_mode mode = GET_MODE (x);
6522 enum rtx_code code = GET_CODE (x);
6523 int size = GET_MODE_BITSIZE (mode);
6524 rtx cond0, cond1, true0, true1, false0, false1;
6525 unsigned HOST_WIDE_INT nz;
6527 /* If this is a unary operation whose operand has one of two values, apply
6528 our opcode to compute those values. */
6529 if (GET_RTX_CLASS (code) == '1'
6530 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6532 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6533 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6537 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6538 make can't possibly match and would suppress other optimizations. */
6539 else if (code == COMPARE)
6542 /* If this is a binary operation, see if either side has only one of two
6543 values. If either one does or if both do and they are conditional on
6544 the same value, compute the new true and false values. */
6545 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6546 || GET_RTX_CLASS (code) == '<')
6548 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6549 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6551 if ((cond0 != 0 || cond1 != 0)
6552 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6554 /* If if_then_else_cond returned zero, then true/false are the
6555 same rtl. We must copy one of them to prevent invalid rtl
6558 true0 = copy_rtx (true0);
6559 else if (cond1 == 0)
6560 true1 = copy_rtx (true1);
6562 *ptrue = gen_binary (code, mode, true0, true1);
6563 *pfalse = gen_binary (code, mode, false0, false1);
6564 return cond0 ? cond0 : cond1;
6567 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6568 operands is zero when the other is non-zero, and vice-versa,
6569 and STORE_FLAG_VALUE is 1 or -1. */
6571 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6572 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6574 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6576 rtx op0 = XEXP (XEXP (x, 0), 1);
6577 rtx op1 = XEXP (XEXP (x, 1), 1);
6579 cond0 = XEXP (XEXP (x, 0), 0);
6580 cond1 = XEXP (XEXP (x, 1), 0);
6582 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6583 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6584 && reversible_comparison_p (cond1)
6585 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6586 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6587 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6588 || ((swap_condition (GET_CODE (cond0))
6589 == reverse_condition (GET_CODE (cond1)))
6590 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6591 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6592 && ! side_effects_p (x))
6594 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6595 *pfalse = gen_binary (MULT, mode,
6597 ? gen_unary (NEG, mode, mode, op1) : op1),
6603 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6605 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6606 && (code == MULT || code == AND || code == UMIN)
6607 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6609 cond0 = XEXP (XEXP (x, 0), 0);
6610 cond1 = XEXP (XEXP (x, 1), 0);
6612 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6613 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6614 && reversible_comparison_p (cond1)
6615 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6616 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6617 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6618 || ((swap_condition (GET_CODE (cond0))
6619 == reverse_condition (GET_CODE (cond1)))
6620 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6621 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6622 && ! side_effects_p (x))
6624 *ptrue = *pfalse = const0_rtx;
6630 else if (code == IF_THEN_ELSE)
6632 /* If we have IF_THEN_ELSE already, extract the condition and
6633 canonicalize it if it is NE or EQ. */
6634 cond0 = XEXP (x, 0);
6635 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6636 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6637 return XEXP (cond0, 0);
6638 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6640 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6641 return XEXP (cond0, 0);
6647 /* If X is a normal SUBREG with both inner and outer modes integral,
6648 we can narrow both the true and false values of the inner expression,
6649 if there is a condition. */
6650 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6651 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6652 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6653 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6656 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6658 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6663 /* If X is a constant, this isn't special and will cause confusions
6664 if we treat it as such. Likewise if it is equivalent to a constant. */
6665 else if (CONSTANT_P (x)
6666 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6669 /* If X is known to be either 0 or -1, those are the true and
6670 false values when testing X. */
6671 else if (num_sign_bit_copies (x, mode) == size)
6673 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6677 /* Likewise for 0 or a single bit. */
6678 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6680 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6684 /* Otherwise fail; show no condition with true and false values the same. */
6685 *ptrue = *pfalse = x;
6689 /* Return the value of expression X given the fact that condition COND
6690 is known to be true when applied to REG as its first operand and VAL
6691 as its second. X is known to not be shared and so can be modified in
6694 We only handle the simplest cases, and specifically those cases that
6695 arise with IF_THEN_ELSE expressions. */
6698 known_cond (x, cond, reg, val)
6703 enum rtx_code code = GET_CODE (x);
6708 if (side_effects_p (x))
6711 if (cond == EQ && rtx_equal_p (x, reg))
6714 /* If X is (abs REG) and we know something about REG's relationship
6715 with zero, we may be able to simplify this. */
6717 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6720 case GE: case GT: case EQ:
6723 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6729 /* The only other cases we handle are MIN, MAX, and comparisons if the
6730 operands are the same as REG and VAL. */
6732 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6734 if (rtx_equal_p (XEXP (x, 0), val))
6735 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6737 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6739 if (GET_RTX_CLASS (code) == '<')
6740 return (comparison_dominates_p (cond, code) ? const_true_rtx
6741 : (comparison_dominates_p (cond,
6742 reverse_condition (code))
6745 else if (code == SMAX || code == SMIN
6746 || code == UMIN || code == UMAX)
6748 int unsignedp = (code == UMIN || code == UMAX);
6750 if (code == SMAX || code == UMAX)
6751 cond = reverse_condition (cond);
6756 return unsignedp ? x : XEXP (x, 1);
6758 return unsignedp ? x : XEXP (x, 0);
6760 return unsignedp ? XEXP (x, 1) : x;
6762 return unsignedp ? XEXP (x, 0) : x;
6770 fmt = GET_RTX_FORMAT (code);
6771 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6774 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
6775 else if (fmt[i] == 'E')
6776 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6777 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
6784 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
6785 assignment as a field assignment. */
6788 rtx_equal_for_field_assignment_p (x, y)
6794 if (x == y || rtx_equal_p (x, y))
6797 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
6800 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
6801 Note that all SUBREGs of MEM are paradoxical; otherwise they
6802 would have been rewritten. */
6803 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
6804 && GET_CODE (SUBREG_REG (y)) == MEM
6805 && rtx_equal_p (SUBREG_REG (y),
6806 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
6809 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
6810 && GET_CODE (SUBREG_REG (x)) == MEM
6811 && rtx_equal_p (SUBREG_REG (x),
6812 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
6815 last_x = get_last_value (x);
6816 last_y = get_last_value (y);
6818 return ((last_x != 0
6819 && GET_CODE (last_x) != CLOBBER
6820 && rtx_equal_for_field_assignment_p (last_x, y))
6822 && GET_CODE (last_y) != CLOBBER
6823 && rtx_equal_for_field_assignment_p (x, last_y))
6824 || (last_x != 0 && last_y != 0
6825 && GET_CODE (last_x) != CLOBBER
6826 && GET_CODE (last_y) != CLOBBER
6827 && rtx_equal_for_field_assignment_p (last_x, last_y)));
6830 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
6831 Return that assignment if so.
6833 We only handle the most common cases. */
6836 make_field_assignment (x)
6839 rtx dest = SET_DEST (x);
6840 rtx src = SET_SRC (x);
6846 enum machine_mode mode;
6848 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
6849 a clear of a one-bit field. We will have changed it to
6850 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
6853 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
6854 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
6855 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
6856 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6858 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6861 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6865 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
6866 && subreg_lowpart_p (XEXP (src, 0))
6867 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
6868 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
6869 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
6870 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
6871 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6873 assign = make_extraction (VOIDmode, dest, 0,
6874 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
6877 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
6881 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
6883 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
6884 && XEXP (XEXP (src, 0), 0) == const1_rtx
6885 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
6887 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
6890 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
6894 /* The other case we handle is assignments into a constant-position
6895 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
6896 a mask that has all one bits except for a group of zero bits and
6897 OTHER is known to have zeros where C1 has ones, this is such an
6898 assignment. Compute the position and length from C1. Shift OTHER
6899 to the appropriate position, force it to the required mode, and
6900 make the extraction. Check for the AND in both operands. */
6902 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
6905 rhs = expand_compound_operation (XEXP (src, 0));
6906 lhs = expand_compound_operation (XEXP (src, 1));
6908 if (GET_CODE (rhs) == AND
6909 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
6910 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
6911 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
6912 else if (GET_CODE (lhs) == AND
6913 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6914 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
6915 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
6919 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
6920 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
6921 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
6922 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
6925 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
6929 /* The mode to use for the source is the mode of the assignment, or of
6930 what is inside a possible STRICT_LOW_PART. */
6931 mode = (GET_CODE (assign) == STRICT_LOW_PART
6932 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
6934 /* Shift OTHER right POS places and make it the source, restricting it
6935 to the proper length and mode. */
6937 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
6938 GET_MODE (src), other, pos),
6940 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
6941 ? GET_MODE_MASK (mode)
6942 : ((HOST_WIDE_INT) 1 << len) - 1,
6945 return gen_rtx_combine (SET, VOIDmode, assign, src);
6948 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
6952 apply_distributive_law (x)
6955 enum rtx_code code = GET_CODE (x);
6956 rtx lhs, rhs, other;
6958 enum rtx_code inner_code;
6960 /* Distributivity is not true for floating point.
6961 It can change the value. So don't do it.
6962 -- rms and moshier@world.std.com. */
6963 if (FLOAT_MODE_P (GET_MODE (x)))
6966 /* The outer operation can only be one of the following: */
6967 if (code != IOR && code != AND && code != XOR
6968 && code != PLUS && code != MINUS)
6971 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
6973 /* If either operand is a primitive we can't do anything, so get out
6975 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
6976 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
6979 lhs = expand_compound_operation (lhs);
6980 rhs = expand_compound_operation (rhs);
6981 inner_code = GET_CODE (lhs);
6982 if (inner_code != GET_CODE (rhs))
6985 /* See if the inner and outer operations distribute. */
6992 /* These all distribute except over PLUS. */
6993 if (code == PLUS || code == MINUS)
6998 if (code != PLUS && code != MINUS)
7003 /* This is also a multiply, so it distributes over everything. */
7007 /* Non-paradoxical SUBREGs distributes over all operations, provided
7008 the inner modes and word numbers are the same, this is an extraction
7009 of a low-order part, we don't convert an fp operation to int or
7010 vice versa, and we would not be converting a single-word
7011 operation into a multi-word operation. The latter test is not
7012 required, but it prevents generating unneeded multi-word operations.
7013 Some of the previous tests are redundant given the latter test, but
7014 are retained because they are required for correctness.
7016 We produce the result slightly differently in this case. */
7018 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7019 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7020 || ! subreg_lowpart_p (lhs)
7021 || (GET_MODE_CLASS (GET_MODE (lhs))
7022 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7023 || (GET_MODE_SIZE (GET_MODE (lhs))
7024 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7025 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7028 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7029 SUBREG_REG (lhs), SUBREG_REG (rhs));
7030 return gen_lowpart_for_combine (GET_MODE (x), tem);
7036 /* Set LHS and RHS to the inner operands (A and B in the example
7037 above) and set OTHER to the common operand (C in the example).
7038 These is only one way to do this unless the inner operation is
7040 if (GET_RTX_CLASS (inner_code) == 'c'
7041 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7042 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7043 else if (GET_RTX_CLASS (inner_code) == 'c'
7044 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7045 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7046 else if (GET_RTX_CLASS (inner_code) == 'c'
7047 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7048 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7049 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7050 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7054 /* Form the new inner operation, seeing if it simplifies first. */
7055 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7057 /* There is one exception to the general way of distributing:
7058 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7059 if (code == XOR && inner_code == IOR)
7062 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7065 /* We may be able to continuing distributing the result, so call
7066 ourselves recursively on the inner operation before forming the
7067 outer operation, which we return. */
7068 return gen_binary (inner_code, GET_MODE (x),
7069 apply_distributive_law (tem), other);
7072 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7075 Return an equivalent form, if different from X. Otherwise, return X. If
7076 X is zero, we are to always construct the equivalent form. */
7079 simplify_and_const_int (x, mode, varop, constop)
7081 enum machine_mode mode;
7083 unsigned HOST_WIDE_INT constop;
7085 unsigned HOST_WIDE_INT nonzero;
7086 int width = GET_MODE_BITSIZE (mode);
7089 /* Simplify VAROP knowing that we will be only looking at some of the
7091 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7093 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7094 CONST_INT, we are done. */
7095 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7098 /* See what bits may be nonzero in VAROP. Unlike the general case of
7099 a call to nonzero_bits, here we don't care about bits outside
7102 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7104 /* If this would be an entire word for the target, but is not for
7105 the host, then sign-extend on the host so that the number will look
7106 the same way on the host that it would on the target.
7108 For example, when building a 64 bit alpha hosted 32 bit sparc
7109 targeted compiler, then we want the 32 bit unsigned value -1 to be
7110 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
7111 The later confuses the sparc backend. */
7113 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
7114 && (nonzero & ((HOST_WIDE_INT) 1 << (width - 1))))
7115 nonzero |= ((HOST_WIDE_INT) (-1) << width);
7117 /* Turn off all bits in the constant that are known to already be zero.
7118 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7119 which is tested below. */
7123 /* If we don't have any bits left, return zero. */
7127 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7128 a power of two, we can replace this with a ASHIFT. */
7129 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7130 && (i = exact_log2 (constop)) >= 0)
7131 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7133 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7134 or XOR, then try to apply the distributive law. This may eliminate
7135 operations if either branch can be simplified because of the AND.
7136 It may also make some cases more complex, but those cases probably
7137 won't match a pattern either with or without this. */
7139 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7141 gen_lowpart_for_combine
7143 apply_distributive_law
7144 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7145 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7146 XEXP (varop, 0), constop),
7147 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7148 XEXP (varop, 1), constop))));
7150 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7151 if we already had one (just check for the simplest cases). */
7152 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7153 && GET_MODE (XEXP (x, 0)) == mode
7154 && SUBREG_REG (XEXP (x, 0)) == varop)
7155 varop = XEXP (x, 0);
7157 varop = gen_lowpart_for_combine (mode, varop);
7159 /* If we can't make the SUBREG, try to return what we were given. */
7160 if (GET_CODE (varop) == CLOBBER)
7161 return x ? x : varop;
7163 /* If we are only masking insignificant bits, return VAROP. */
7164 if (constop == nonzero)
7167 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7168 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7169 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7173 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7174 || INTVAL (XEXP (x, 1)) != constop)
7175 SUBST (XEXP (x, 1), GEN_INT (constop));
7177 SUBST (XEXP (x, 0), varop);
7183 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7184 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7185 is less useful. We can't allow both, because that results in exponential
7186 run time recusion. There is a nullstone testcase that triggered
7187 this. This macro avoids accidental uses of num_sign_bit_copies. */
7188 #define num_sign_bit_copies()
7190 /* Given an expression, X, compute which bits in X can be non-zero.
7191 We don't care about bits outside of those defined in MODE.
7193 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7194 a shift, AND, or zero_extract, we can do better. */
7196 static unsigned HOST_WIDE_INT
7197 nonzero_bits (x, mode)
7199 enum machine_mode mode;
7201 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7202 unsigned HOST_WIDE_INT inner_nz;
7204 int mode_width = GET_MODE_BITSIZE (mode);
7207 /* For floating-point values, assume all bits are needed. */
7208 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7211 /* If X is wider than MODE, use its mode instead. */
7212 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7214 mode = GET_MODE (x);
7215 nonzero = GET_MODE_MASK (mode);
7216 mode_width = GET_MODE_BITSIZE (mode);
7219 if (mode_width > HOST_BITS_PER_WIDE_INT)
7220 /* Our only callers in this case look for single bit values. So
7221 just return the mode mask. Those tests will then be false. */
7224 #ifndef WORD_REGISTER_OPERATIONS
7225 /* If MODE is wider than X, but both are a single word for both the host
7226 and target machines, we can compute this from which bits of the
7227 object might be nonzero in its own mode, taking into account the fact
7228 that on many CISC machines, accessing an object in a wider mode
7229 causes the high-order bits to become undefined. So they are
7230 not known to be zero. */
7232 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7233 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7234 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7235 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7237 nonzero &= nonzero_bits (x, GET_MODE (x));
7238 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7243 code = GET_CODE (x);
7247 #ifdef POINTERS_EXTEND_UNSIGNED
7248 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7249 all the bits above ptr_mode are known to be zero. */
7250 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7251 && REGNO_POINTER_FLAG (REGNO (x)))
7252 nonzero &= GET_MODE_MASK (ptr_mode);
7255 #ifdef STACK_BOUNDARY
7256 /* If this is the stack pointer, we may know something about its
7257 alignment. If PUSH_ROUNDING is defined, it is possible for the
7258 stack to be momentarily aligned only to that amount, so we pick
7259 the least alignment. */
7261 /* We can't check for arg_pointer_rtx here, because it is not
7262 guaranteed to have as much alignment as the stack pointer.
7263 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7264 alignment but the argument pointer has only 64 bit alignment. */
7266 if (x == stack_pointer_rtx || x == frame_pointer_rtx
7267 || x == hard_frame_pointer_rtx
7268 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7269 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7271 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7273 #ifdef PUSH_ROUNDING
7274 if (REGNO (x) == STACK_POINTER_REGNUM)
7275 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7278 /* We must return here, otherwise we may get a worse result from
7279 one of the choices below. There is nothing useful below as
7280 far as the stack pointer is concerned. */
7281 return nonzero &= ~ (sp_alignment - 1);
7285 /* If X is a register whose nonzero bits value is current, use it.
7286 Otherwise, if X is a register whose value we can find, use that
7287 value. Otherwise, use the previously-computed global nonzero bits
7288 for this register. */
7290 if (reg_last_set_value[REGNO (x)] != 0
7291 && reg_last_set_mode[REGNO (x)] == mode
7292 && (REG_N_SETS (REGNO (x)) == 1
7293 || reg_last_set_label[REGNO (x)] == label_tick)
7294 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7295 return reg_last_set_nonzero_bits[REGNO (x)];
7297 tem = get_last_value (x);
7301 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7302 /* If X is narrower than MODE and TEM is a non-negative
7303 constant that would appear negative in the mode of X,
7304 sign-extend it for use in reg_nonzero_bits because some
7305 machines (maybe most) will actually do the sign-extension
7306 and this is the conservative approach.
7308 ??? For 2.5, try to tighten up the MD files in this regard
7309 instead of this kludge. */
7311 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7312 && GET_CODE (tem) == CONST_INT
7314 && 0 != (INTVAL (tem)
7315 & ((HOST_WIDE_INT) 1
7316 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7317 tem = GEN_INT (INTVAL (tem)
7318 | ((HOST_WIDE_INT) (-1)
7319 << GET_MODE_BITSIZE (GET_MODE (x))));
7321 return nonzero_bits (tem, mode);
7323 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7324 return reg_nonzero_bits[REGNO (x)] & nonzero;
7329 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7330 /* If X is negative in MODE, sign-extend the value. */
7331 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7332 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7333 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7339 #ifdef LOAD_EXTEND_OP
7340 /* In many, if not most, RISC machines, reading a byte from memory
7341 zeros the rest of the register. Noticing that fact saves a lot
7342 of extra zero-extends. */
7343 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7344 nonzero &= GET_MODE_MASK (GET_MODE (x));
7354 /* If this produces an integer result, we know which bits are set.
7355 Code here used to clear bits outside the mode of X, but that is
7358 if (GET_MODE_CLASS (mode) == MODE_INT
7359 && mode_width <= HOST_BITS_PER_WIDE_INT)
7360 nonzero = STORE_FLAG_VALUE;
7365 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7366 and num_sign_bit_copies. */
7367 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7368 == GET_MODE_BITSIZE (GET_MODE (x)))
7372 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7373 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7378 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7379 and num_sign_bit_copies. */
7380 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7381 == GET_MODE_BITSIZE (GET_MODE (x)))
7387 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7391 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7392 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7393 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7397 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7398 Otherwise, show all the bits in the outer mode but not the inner
7400 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7401 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7403 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7405 & (((HOST_WIDE_INT) 1
7406 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7407 inner_nz |= (GET_MODE_MASK (mode)
7408 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7411 nonzero &= inner_nz;
7415 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7416 & nonzero_bits (XEXP (x, 1), mode));
7420 case UMIN: case UMAX: case SMIN: case SMAX:
7421 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7422 | nonzero_bits (XEXP (x, 1), mode));
7425 case PLUS: case MINUS:
7427 case DIV: case UDIV:
7428 case MOD: case UMOD:
7429 /* We can apply the rules of arithmetic to compute the number of
7430 high- and low-order zero bits of these operations. We start by
7431 computing the width (position of the highest-order non-zero bit)
7432 and the number of low-order zero bits for each value. */
7434 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7435 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7436 int width0 = floor_log2 (nz0) + 1;
7437 int width1 = floor_log2 (nz1) + 1;
7438 int low0 = floor_log2 (nz0 & -nz0);
7439 int low1 = floor_log2 (nz1 & -nz1);
7440 HOST_WIDE_INT op0_maybe_minusp
7441 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7442 HOST_WIDE_INT op1_maybe_minusp
7443 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7444 int result_width = mode_width;
7450 result_width = MAX (width0, width1) + 1;
7451 result_low = MIN (low0, low1);
7454 result_low = MIN (low0, low1);
7457 result_width = width0 + width1;
7458 result_low = low0 + low1;
7461 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7462 result_width = width0;
7465 result_width = width0;
7468 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7469 result_width = MIN (width0, width1);
7470 result_low = MIN (low0, low1);
7473 result_width = MIN (width0, width1);
7474 result_low = MIN (low0, low1);
7480 if (result_width < mode_width)
7481 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7484 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7489 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7490 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7491 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7495 /* If this is a SUBREG formed for a promoted variable that has
7496 been zero-extended, we know that at least the high-order bits
7497 are zero, though others might be too. */
7499 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7500 nonzero = (GET_MODE_MASK (GET_MODE (x))
7501 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7503 /* If the inner mode is a single word for both the host and target
7504 machines, we can compute this from which bits of the inner
7505 object might be nonzero. */
7506 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7507 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7508 <= HOST_BITS_PER_WIDE_INT))
7510 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7512 #ifndef WORD_REGISTER_OPERATIONS
7513 /* On many CISC machines, accessing an object in a wider mode
7514 causes the high-order bits to become undefined. So they are
7515 not known to be zero. */
7516 if (GET_MODE_SIZE (GET_MODE (x))
7517 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7518 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7519 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7528 /* The nonzero bits are in two classes: any bits within MODE
7529 that aren't in GET_MODE (x) are always significant. The rest of the
7530 nonzero bits are those that are significant in the operand of
7531 the shift when shifted the appropriate number of bits. This
7532 shows that high-order bits are cleared by the right shift and
7533 low-order bits by left shifts. */
7534 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7535 && INTVAL (XEXP (x, 1)) >= 0
7536 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7538 enum machine_mode inner_mode = GET_MODE (x);
7539 int width = GET_MODE_BITSIZE (inner_mode);
7540 int count = INTVAL (XEXP (x, 1));
7541 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7542 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7543 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7544 unsigned HOST_WIDE_INT outer = 0;
7546 if (mode_width > width)
7547 outer = (op_nonzero & nonzero & ~ mode_mask);
7549 if (code == LSHIFTRT)
7551 else if (code == ASHIFTRT)
7555 /* If the sign bit may have been nonzero before the shift, we
7556 need to mark all the places it could have been copied to
7557 by the shift as possibly nonzero. */
7558 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7559 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7561 else if (code == ASHIFT)
7564 inner = ((inner << (count % width)
7565 | (inner >> (width - (count % width)))) & mode_mask);
7567 nonzero &= (outer | inner);
7572 /* This is at most the number of bits in the mode. */
7573 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7577 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7578 | nonzero_bits (XEXP (x, 2), mode));
7588 /* See the macro definition above. */
7589 #undef num_sign_bit_copies
7591 /* Return the number of bits at the high-order end of X that are known to
7592 be equal to the sign bit. X will be used in mode MODE; if MODE is
7593 VOIDmode, X will be used in its own mode. The returned value will always
7594 be between 1 and the number of bits in MODE. */
7597 num_sign_bit_copies (x, mode)
7599 enum machine_mode mode;
7601 enum rtx_code code = GET_CODE (x);
7603 int num0, num1, result;
7604 unsigned HOST_WIDE_INT nonzero;
7607 /* If we weren't given a mode, use the mode of X. If the mode is still
7608 VOIDmode, we don't know anything. Likewise if one of the modes is
7611 if (mode == VOIDmode)
7612 mode = GET_MODE (x);
7614 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7617 bitwidth = GET_MODE_BITSIZE (mode);
7619 /* For a smaller object, just ignore the high bits. */
7620 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7621 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7622 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7624 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7626 #ifndef WORD_REGISTER_OPERATIONS
7627 /* If this machine does not do all register operations on the entire
7628 register and MODE is wider than the mode of X, we can say nothing
7629 at all about the high-order bits. */
7632 /* Likewise on machines that do, if the mode of the object is smaller
7633 than a word and loads of that size don't sign extend, we can say
7634 nothing about the high order bits. */
7635 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7636 #ifdef LOAD_EXTEND_OP
7637 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7648 #ifdef POINTERS_EXTEND_UNSIGNED
7649 /* If pointers extend signed and this is a pointer in Pmode, say that
7650 all the bits above ptr_mode are known to be sign bit copies. */
7651 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7652 && REGNO_POINTER_FLAG (REGNO (x)))
7653 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7656 if (reg_last_set_value[REGNO (x)] != 0
7657 && reg_last_set_mode[REGNO (x)] == mode
7658 && (REG_N_SETS (REGNO (x)) == 1
7659 || reg_last_set_label[REGNO (x)] == label_tick)
7660 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7661 return reg_last_set_sign_bit_copies[REGNO (x)];
7663 tem = get_last_value (x);
7665 return num_sign_bit_copies (tem, mode);
7667 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7668 return reg_sign_bit_copies[REGNO (x)];
7672 #ifdef LOAD_EXTEND_OP
7673 /* Some RISC machines sign-extend all loads of smaller than a word. */
7674 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7675 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7680 /* If the constant is negative, take its 1's complement and remask.
7681 Then see how many zero bits we have. */
7682 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7683 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7684 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7685 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7687 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7690 /* If this is a SUBREG for a promoted object that is sign-extended
7691 and we are looking at it in a wider mode, we know that at least the
7692 high-order bits are known to be sign bit copies. */
7694 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7695 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7696 num_sign_bit_copies (SUBREG_REG (x), mode));
7698 /* For a smaller object, just ignore the high bits. */
7699 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7701 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7702 return MAX (1, (num0
7703 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7707 #ifdef WORD_REGISTER_OPERATIONS
7708 #ifdef LOAD_EXTEND_OP
7709 /* For paradoxical SUBREGs on machines where all register operations
7710 affect the entire register, just look inside. Note that we are
7711 passing MODE to the recursive call, so the number of sign bit copies
7712 will remain relative to that mode, not the inner mode. */
7714 /* This works only if loads sign extend. Otherwise, if we get a
7715 reload for the inner part, it may be loaded from the stack, and
7716 then we lose all sign bit copies that existed before the store
7719 if ((GET_MODE_SIZE (GET_MODE (x))
7720 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7721 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7722 return num_sign_bit_copies (SUBREG_REG (x), mode);
7728 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7729 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7733 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7734 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7737 /* For a smaller object, just ignore the high bits. */
7738 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7739 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7743 return num_sign_bit_copies (XEXP (x, 0), mode);
7745 case ROTATE: case ROTATERT:
7746 /* If we are rotating left by a number of bits less than the number
7747 of sign bit copies, we can just subtract that amount from the
7749 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7750 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
7752 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7753 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
7754 : bitwidth - INTVAL (XEXP (x, 1))));
7759 /* In general, this subtracts one sign bit copy. But if the value
7760 is known to be positive, the number of sign bit copies is the
7761 same as that of the input. Finally, if the input has just one bit
7762 that might be nonzero, all the bits are copies of the sign bit. */
7763 nonzero = nonzero_bits (XEXP (x, 0), mode);
7767 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7769 && bitwidth <= HOST_BITS_PER_WIDE_INT
7770 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
7775 case IOR: case AND: case XOR:
7776 case SMIN: case SMAX: case UMIN: case UMAX:
7777 /* Logical operations will preserve the number of sign-bit copies.
7778 MIN and MAX operations always return one of the operands. */
7779 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7780 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7781 return MIN (num0, num1);
7783 case PLUS: case MINUS:
7784 /* For addition and subtraction, we can have a 1-bit carry. However,
7785 if we are subtracting 1 from a positive number, there will not
7786 be such a carry. Furthermore, if the positive number is known to
7787 be 0 or 1, we know the result is either -1 or 0. */
7789 if (code == PLUS && XEXP (x, 1) == constm1_rtx
7790 && bitwidth <= HOST_BITS_PER_WIDE_INT)
7792 nonzero = nonzero_bits (XEXP (x, 0), mode);
7793 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
7794 return (nonzero == 1 || nonzero == 0 ? bitwidth
7795 : bitwidth - floor_log2 (nonzero) - 1);
7798 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7799 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7800 return MAX (1, MIN (num0, num1) - 1);
7803 /* The number of bits of the product is the sum of the number of
7804 bits of both terms. However, unless one of the terms if known
7805 to be positive, we must allow for an additional bit since negating
7806 a negative number can remove one sign bit copy. */
7808 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7809 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
7811 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
7813 && bitwidth <= HOST_BITS_PER_WIDE_INT
7814 && ((nonzero_bits (XEXP (x, 0), mode)
7815 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7816 && ((nonzero_bits (XEXP (x, 1), mode)
7817 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
7820 return MAX (1, result);
7823 /* The result must be <= the first operand. */
7824 return num_sign_bit_copies (XEXP (x, 0), mode);
7827 /* The result must be <= the scond operand. */
7828 return num_sign_bit_copies (XEXP (x, 1), mode);
7831 /* Similar to unsigned division, except that we have to worry about
7832 the case where the divisor is negative, in which case we have
7834 result = num_sign_bit_copies (XEXP (x, 0), mode);
7836 && bitwidth <= HOST_BITS_PER_WIDE_INT
7837 && (nonzero_bits (XEXP (x, 1), mode)
7838 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7844 result = num_sign_bit_copies (XEXP (x, 1), mode);
7846 && bitwidth <= HOST_BITS_PER_WIDE_INT
7847 && (nonzero_bits (XEXP (x, 1), mode)
7848 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7854 /* Shifts by a constant add to the number of bits equal to the
7856 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7857 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7858 && INTVAL (XEXP (x, 1)) > 0)
7859 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
7864 /* Left shifts destroy copies. */
7865 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7866 || INTVAL (XEXP (x, 1)) < 0
7867 || INTVAL (XEXP (x, 1)) >= bitwidth)
7870 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
7871 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
7874 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
7875 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
7876 return MIN (num0, num1);
7878 case EQ: case NE: case GE: case GT: case LE: case LT:
7879 case GEU: case GTU: case LEU: case LTU:
7880 if (STORE_FLAG_VALUE == -1)
7888 /* If we haven't been able to figure it out by one of the above rules,
7889 see if some of the high-order bits are known to be zero. If so,
7890 count those bits and return one less than that amount. If we can't
7891 safely compute the mask for this mode, always return BITWIDTH. */
7893 if (bitwidth > HOST_BITS_PER_WIDE_INT)
7896 nonzero = nonzero_bits (x, mode);
7897 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
7898 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
7901 /* Return the number of "extended" bits there are in X, when interpreted
7902 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
7903 unsigned quantities, this is the number of high-order zero bits.
7904 For signed quantities, this is the number of copies of the sign bit
7905 minus 1. In both case, this function returns the number of "spare"
7906 bits. For example, if two quantities for which this function returns
7907 at least 1 are added, the addition is known not to overflow.
7909 This function will always return 0 unless called during combine, which
7910 implies that it must be called from a define_split. */
7913 extended_count (x, mode, unsignedp)
7915 enum machine_mode mode;
7918 if (nonzero_sign_valid == 0)
7922 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7923 && (GET_MODE_BITSIZE (mode) - 1
7924 - floor_log2 (nonzero_bits (x, mode))))
7925 : num_sign_bit_copies (x, mode) - 1);
7928 /* This function is called from `simplify_shift_const' to merge two
7929 outer operations. Specifically, we have already found that we need
7930 to perform operation *POP0 with constant *PCONST0 at the outermost
7931 position. We would now like to also perform OP1 with constant CONST1
7932 (with *POP0 being done last).
7934 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
7935 the resulting operation. *PCOMP_P is set to 1 if we would need to
7936 complement the innermost operand, otherwise it is unchanged.
7938 MODE is the mode in which the operation will be done. No bits outside
7939 the width of this mode matter. It is assumed that the width of this mode
7940 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
7942 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
7943 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
7944 result is simply *PCONST0.
7946 If the resulting operation cannot be expressed as one operation, we
7947 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
7950 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
7951 enum rtx_code *pop0;
7952 HOST_WIDE_INT *pconst0;
7954 HOST_WIDE_INT const1;
7955 enum machine_mode mode;
7958 enum rtx_code op0 = *pop0;
7959 HOST_WIDE_INT const0 = *pconst0;
7960 int width = GET_MODE_BITSIZE (mode);
7962 const0 &= GET_MODE_MASK (mode);
7963 const1 &= GET_MODE_MASK (mode);
7965 /* If OP0 is an AND, clear unimportant bits in CONST1. */
7969 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
7972 if (op1 == NIL || op0 == SET)
7975 else if (op0 == NIL)
7976 op0 = op1, const0 = const1;
7978 else if (op0 == op1)
8002 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8003 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8006 /* If the two constants aren't the same, we can't do anything. The
8007 remaining six cases can all be done. */
8008 else if (const0 != const1)
8016 /* (a & b) | b == b */
8018 else /* op1 == XOR */
8019 /* (a ^ b) | b == a | b */
8025 /* (a & b) ^ b == (~a) & b */
8026 op0 = AND, *pcomp_p = 1;
8027 else /* op1 == IOR */
8028 /* (a | b) ^ b == a & ~b */
8029 op0 = AND, *pconst0 = ~ const0;
8034 /* (a | b) & b == b */
8036 else /* op1 == XOR */
8037 /* (a ^ b) & b) == (~a) & b */
8044 /* Check for NO-OP cases. */
8045 const0 &= GET_MODE_MASK (mode);
8047 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8049 else if (const0 == 0 && op0 == AND)
8051 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
8054 /* If this would be an entire word for the target, but is not for
8055 the host, then sign-extend on the host so that the number will look
8056 the same way on the host that it would on the target.
8058 For example, when building a 64 bit alpha hosted 32 bit sparc
8059 targeted compiler, then we want the 32 bit unsigned value -1 to be
8060 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8061 The later confuses the sparc backend. */
8063 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8064 && (const0 & ((HOST_WIDE_INT) 1 << (width - 1))))
8065 const0 |= ((HOST_WIDE_INT) (-1) << width);
8073 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8074 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8075 that we started with.
8077 The shift is normally computed in the widest mode we find in VAROP, as
8078 long as it isn't a different number of words than RESULT_MODE. Exceptions
8079 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8082 simplify_shift_const (x, code, result_mode, varop, count)
8085 enum machine_mode result_mode;
8089 enum rtx_code orig_code = code;
8090 int orig_count = count;
8091 enum machine_mode mode = result_mode;
8092 enum machine_mode shift_mode, tmode;
8094 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8095 /* We form (outer_op (code varop count) (outer_const)). */
8096 enum rtx_code outer_op = NIL;
8097 HOST_WIDE_INT outer_const = 0;
8099 int complement_p = 0;
8102 /* If we were given an invalid count, don't do anything except exactly
8103 what was requested. */
8105 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8110 return gen_rtx (code, mode, varop, GEN_INT (count));
8113 /* Unless one of the branches of the `if' in this loop does a `continue',
8114 we will `break' the loop after the `if'. */
8118 /* If we have an operand of (clobber (const_int 0)), just return that
8120 if (GET_CODE (varop) == CLOBBER)
8123 /* If we discovered we had to complement VAROP, leave. Making a NOT
8124 here would cause an infinite loop. */
8128 /* Convert ROTATERT to ROTATE. */
8129 if (code == ROTATERT)
8130 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8132 /* We need to determine what mode we will do the shift in. If the
8133 shift is a right shift or a ROTATE, we must always do it in the mode
8134 it was originally done in. Otherwise, we can do it in MODE, the
8135 widest mode encountered. */
8137 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8138 ? result_mode : mode);
8140 /* Handle cases where the count is greater than the size of the mode
8141 minus 1. For ASHIFT, use the size minus one as the count (this can
8142 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8143 take the count modulo the size. For other shifts, the result is
8146 Since these shifts are being produced by the compiler by combining
8147 multiple operations, each of which are defined, we know what the
8148 result is supposed to be. */
8150 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8152 if (code == ASHIFTRT)
8153 count = GET_MODE_BITSIZE (shift_mode) - 1;
8154 else if (code == ROTATE || code == ROTATERT)
8155 count %= GET_MODE_BITSIZE (shift_mode);
8158 /* We can't simply return zero because there may be an
8166 /* Negative counts are invalid and should not have been made (a
8167 programmer-specified negative count should have been handled
8172 /* An arithmetic right shift of a quantity known to be -1 or 0
8174 if (code == ASHIFTRT
8175 && (num_sign_bit_copies (varop, shift_mode)
8176 == GET_MODE_BITSIZE (shift_mode)))
8182 /* If we are doing an arithmetic right shift and discarding all but
8183 the sign bit copies, this is equivalent to doing a shift by the
8184 bitsize minus one. Convert it into that shift because it will often
8185 allow other simplifications. */
8187 if (code == ASHIFTRT
8188 && (count + num_sign_bit_copies (varop, shift_mode)
8189 >= GET_MODE_BITSIZE (shift_mode)))
8190 count = GET_MODE_BITSIZE (shift_mode) - 1;
8192 /* We simplify the tests below and elsewhere by converting
8193 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8194 `make_compound_operation' will convert it to a ASHIFTRT for
8195 those machines (such as Vax) that don't have a LSHIFTRT. */
8196 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8198 && ((nonzero_bits (varop, shift_mode)
8199 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8203 switch (GET_CODE (varop))
8209 new = expand_compound_operation (varop);
8218 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8219 minus the width of a smaller mode, we can do this with a
8220 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8221 if ((code == ASHIFTRT || code == LSHIFTRT)
8222 && ! mode_dependent_address_p (XEXP (varop, 0))
8223 && ! MEM_VOLATILE_P (varop)
8224 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8225 MODE_INT, 1)) != BLKmode)
8227 if (BYTES_BIG_ENDIAN)
8228 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
8230 new = gen_rtx (MEM, tmode,
8231 plus_constant (XEXP (varop, 0),
8232 count / BITS_PER_UNIT));
8233 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8234 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
8235 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
8236 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8237 : ZERO_EXTEND, mode, new);
8244 /* Similar to the case above, except that we can only do this if
8245 the resulting mode is the same as that of the underlying
8246 MEM and adjust the address depending on the *bits* endianness
8247 because of the way that bit-field extract insns are defined. */
8248 if ((code == ASHIFTRT || code == LSHIFTRT)
8249 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8250 MODE_INT, 1)) != BLKmode
8251 && tmode == GET_MODE (XEXP (varop, 0)))
8253 if (BITS_BIG_ENDIAN)
8254 new = XEXP (varop, 0);
8257 new = copy_rtx (XEXP (varop, 0));
8258 SUBST (XEXP (new, 0),
8259 plus_constant (XEXP (new, 0),
8260 count / BITS_PER_UNIT));
8263 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8264 : ZERO_EXTEND, mode, new);
8271 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8272 the same number of words as what we've seen so far. Then store
8273 the widest mode in MODE. */
8274 if (subreg_lowpart_p (varop)
8275 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8276 > GET_MODE_SIZE (GET_MODE (varop)))
8277 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8278 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8281 varop = SUBREG_REG (varop);
8282 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8283 mode = GET_MODE (varop);
8289 /* Some machines use MULT instead of ASHIFT because MULT
8290 is cheaper. But it is still better on those machines to
8291 merge two shifts into one. */
8292 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8293 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8295 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8296 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8302 /* Similar, for when divides are cheaper. */
8303 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8304 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8306 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8307 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8313 /* If we are extracting just the sign bit of an arithmetic right
8314 shift, that shift is not needed. */
8315 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8317 varop = XEXP (varop, 0);
8321 /* ... fall through ... */
8326 /* Here we have two nested shifts. The result is usually the
8327 AND of a new shift with a mask. We compute the result below. */
8328 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8329 && INTVAL (XEXP (varop, 1)) >= 0
8330 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8331 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8332 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8334 enum rtx_code first_code = GET_CODE (varop);
8335 int first_count = INTVAL (XEXP (varop, 1));
8336 unsigned HOST_WIDE_INT mask;
8339 /* We have one common special case. We can't do any merging if
8340 the inner code is an ASHIFTRT of a smaller mode. However, if
8341 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8342 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8343 we can convert it to
8344 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8345 This simplifies certain SIGN_EXTEND operations. */
8346 if (code == ASHIFT && first_code == ASHIFTRT
8347 && (GET_MODE_BITSIZE (result_mode)
8348 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8350 /* C3 has the low-order C1 bits zero. */
8352 mask = (GET_MODE_MASK (mode)
8353 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8355 varop = simplify_and_const_int (NULL_RTX, result_mode,
8356 XEXP (varop, 0), mask);
8357 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8359 count = first_count;
8364 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8365 than C1 high-order bits equal to the sign bit, we can convert
8366 this to either an ASHIFT or a ASHIFTRT depending on the
8369 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8371 if (code == ASHIFTRT && first_code == ASHIFT
8372 && GET_MODE (varop) == shift_mode
8373 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8376 count -= first_count;
8378 count = - count, code = ASHIFT;
8379 varop = XEXP (varop, 0);
8383 /* There are some cases we can't do. If CODE is ASHIFTRT,
8384 we can only do this if FIRST_CODE is also ASHIFTRT.
8386 We can't do the case when CODE is ROTATE and FIRST_CODE is
8389 If the mode of this shift is not the mode of the outer shift,
8390 we can't do this if either shift is a right shift or ROTATE.
8392 Finally, we can't do any of these if the mode is too wide
8393 unless the codes are the same.
8395 Handle the case where the shift codes are the same
8398 if (code == first_code)
8400 if (GET_MODE (varop) != result_mode
8401 && (code == ASHIFTRT || code == LSHIFTRT
8405 count += first_count;
8406 varop = XEXP (varop, 0);
8410 if (code == ASHIFTRT
8411 || (code == ROTATE && first_code == ASHIFTRT)
8412 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8413 || (GET_MODE (varop) != result_mode
8414 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8415 || first_code == ROTATE
8416 || code == ROTATE)))
8419 /* To compute the mask to apply after the shift, shift the
8420 nonzero bits of the inner shift the same way the
8421 outer shift will. */
8423 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8426 = simplify_binary_operation (code, result_mode, mask_rtx,
8429 /* Give up if we can't compute an outer operation to use. */
8431 || GET_CODE (mask_rtx) != CONST_INT
8432 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8434 result_mode, &complement_p))
8437 /* If the shifts are in the same direction, we add the
8438 counts. Otherwise, we subtract them. */
8439 if ((code == ASHIFTRT || code == LSHIFTRT)
8440 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8441 count += first_count;
8443 count -= first_count;
8445 /* If COUNT is positive, the new shift is usually CODE,
8446 except for the two exceptions below, in which case it is
8447 FIRST_CODE. If the count is negative, FIRST_CODE should
8450 && ((first_code == ROTATE && code == ASHIFT)
8451 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8454 code = first_code, count = - count;
8456 varop = XEXP (varop, 0);
8460 /* If we have (A << B << C) for any shift, we can convert this to
8461 (A << C << B). This wins if A is a constant. Only try this if
8462 B is not a constant. */
8464 else if (GET_CODE (varop) == code
8465 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8467 = simplify_binary_operation (code, mode,
8471 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8478 /* Make this fit the case below. */
8479 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8480 GEN_INT (GET_MODE_MASK (mode)));
8486 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8487 with C the size of VAROP - 1 and the shift is logical if
8488 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8489 we have an (le X 0) operation. If we have an arithmetic shift
8490 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8491 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8493 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8494 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8495 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8496 && (code == LSHIFTRT || code == ASHIFTRT)
8497 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8498 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8501 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8504 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8505 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8510 /* If we have (shift (logical)), move the logical to the outside
8511 to allow it to possibly combine with another logical and the
8512 shift to combine with another shift. This also canonicalizes to
8513 what a ZERO_EXTRACT looks like. Also, some machines have
8514 (and (shift)) insns. */
8516 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8517 && (new = simplify_binary_operation (code, result_mode,
8519 GEN_INT (count))) != 0
8520 && GET_CODE(new) == CONST_INT
8521 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8522 INTVAL (new), result_mode, &complement_p))
8524 varop = XEXP (varop, 0);
8528 /* If we can't do that, try to simplify the shift in each arm of the
8529 logical expression, make a new logical expression, and apply
8530 the inverse distributive law. */
8532 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8533 XEXP (varop, 0), count);
8534 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8535 XEXP (varop, 1), count);
8537 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8538 varop = apply_distributive_law (varop);
8545 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8546 says that the sign bit can be tested, FOO has mode MODE, C is
8547 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8548 that may be nonzero. */
8549 if (code == LSHIFTRT
8550 && XEXP (varop, 1) == const0_rtx
8551 && GET_MODE (XEXP (varop, 0)) == result_mode
8552 && count == GET_MODE_BITSIZE (result_mode) - 1
8553 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8554 && ((STORE_FLAG_VALUE
8555 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8556 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8557 && merge_outer_ops (&outer_op, &outer_const, XOR,
8558 (HOST_WIDE_INT) 1, result_mode,
8561 varop = XEXP (varop, 0);
8568 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8569 than the number of bits in the mode is equivalent to A. */
8570 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8571 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8573 varop = XEXP (varop, 0);
8578 /* NEG commutes with ASHIFT since it is multiplication. Move the
8579 NEG outside to allow shifts to combine. */
8581 && merge_outer_ops (&outer_op, &outer_const, NEG,
8582 (HOST_WIDE_INT) 0, result_mode,
8585 varop = XEXP (varop, 0);
8591 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8592 is one less than the number of bits in the mode is
8593 equivalent to (xor A 1). */
8594 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8595 && XEXP (varop, 1) == constm1_rtx
8596 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8597 && merge_outer_ops (&outer_op, &outer_const, XOR,
8598 (HOST_WIDE_INT) 1, result_mode,
8602 varop = XEXP (varop, 0);
8606 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8607 that might be nonzero in BAR are those being shifted out and those
8608 bits are known zero in FOO, we can replace the PLUS with FOO.
8609 Similarly in the other operand order. This code occurs when
8610 we are computing the size of a variable-size array. */
8612 if ((code == ASHIFTRT || code == LSHIFTRT)
8613 && count < HOST_BITS_PER_WIDE_INT
8614 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8615 && (nonzero_bits (XEXP (varop, 1), result_mode)
8616 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8618 varop = XEXP (varop, 0);
8621 else if ((code == ASHIFTRT || code == LSHIFTRT)
8622 && count < HOST_BITS_PER_WIDE_INT
8623 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8624 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8626 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8627 & nonzero_bits (XEXP (varop, 1),
8630 varop = XEXP (varop, 1);
8634 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8636 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8637 && (new = simplify_binary_operation (ASHIFT, result_mode,
8639 GEN_INT (count))) != 0
8640 && GET_CODE(new) == CONST_INT
8641 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8642 INTVAL (new), result_mode, &complement_p))
8644 varop = XEXP (varop, 0);
8650 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8651 with C the size of VAROP - 1 and the shift is logical if
8652 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8653 we have a (gt X 0) operation. If the shift is arithmetic with
8654 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8655 we have a (neg (gt X 0)) operation. */
8657 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8658 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8659 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8660 && (code == LSHIFTRT || code == ASHIFTRT)
8661 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8662 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8663 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8666 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8669 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8670 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8683 /* We need to determine what mode to do the shift in. If the shift is
8684 a right shift or ROTATE, we must always do it in the mode it was
8685 originally done in. Otherwise, we can do it in MODE, the widest mode
8686 encountered. The code we care about is that of the shift that will
8687 actually be done, not the shift that was originally requested. */
8689 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8690 ? result_mode : mode);
8692 /* We have now finished analyzing the shift. The result should be
8693 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8694 OUTER_OP is non-NIL, it is an operation that needs to be applied
8695 to the result of the shift. OUTER_CONST is the relevant constant,
8696 but we must turn off all bits turned off in the shift.
8698 If we were passed a value for X, see if we can use any pieces of
8699 it. If not, make new rtx. */
8701 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8702 && GET_CODE (XEXP (x, 1)) == CONST_INT
8703 && INTVAL (XEXP (x, 1)) == count)
8704 const_rtx = XEXP (x, 1);
8706 const_rtx = GEN_INT (count);
8708 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8709 && GET_MODE (XEXP (x, 0)) == shift_mode
8710 && SUBREG_REG (XEXP (x, 0)) == varop)
8711 varop = XEXP (x, 0);
8712 else if (GET_MODE (varop) != shift_mode)
8713 varop = gen_lowpart_for_combine (shift_mode, varop);
8715 /* If we can't make the SUBREG, try to return what we were given. */
8716 if (GET_CODE (varop) == CLOBBER)
8717 return x ? x : varop;
8719 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8724 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
8725 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
8727 SUBST (XEXP (x, 0), varop);
8728 SUBST (XEXP (x, 1), const_rtx);
8731 /* If we have an outer operation and we just made a shift, it is
8732 possible that we could have simplified the shift were it not
8733 for the outer operation. So try to do the simplification
8736 if (outer_op != NIL && GET_CODE (x) == code
8737 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8738 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8739 INTVAL (XEXP (x, 1)));
8741 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
8742 turn off all the bits that the shift would have turned off. */
8743 if (orig_code == LSHIFTRT && result_mode != shift_mode)
8744 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
8745 GET_MODE_MASK (result_mode) >> orig_count);
8747 /* Do the remainder of the processing in RESULT_MODE. */
8748 x = gen_lowpart_for_combine (result_mode, x);
8750 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
8753 x = gen_unary (NOT, result_mode, result_mode, x);
8755 if (outer_op != NIL)
8757 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
8759 int width = GET_MODE_BITSIZE (result_mode);
8761 outer_const &= GET_MODE_MASK (result_mode);
8763 /* If this would be an entire word for the target, but is not for
8764 the host, then sign-extend on the host so that the number will
8765 look the same way on the host that it would on the target.
8767 For example, when building a 64 bit alpha hosted 32 bit sparc
8768 targeted compiler, then we want the 32 bit unsigned value -1 to be
8769 represented as a 64 bit value -1, and not as 0x00000000ffffffff.
8770 The later confuses the sparc backend. */
8772 if (BITS_PER_WORD < HOST_BITS_PER_WIDE_INT && BITS_PER_WORD == width
8773 && (outer_const & ((HOST_WIDE_INT) 1 << (width - 1))))
8774 outer_const |= ((HOST_WIDE_INT) (-1) << width);
8777 if (outer_op == AND)
8778 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
8779 else if (outer_op == SET)
8780 /* This means that we have determined that the result is
8781 equivalent to a constant. This should be rare. */
8782 x = GEN_INT (outer_const);
8783 else if (GET_RTX_CLASS (outer_op) == '1')
8784 x = gen_unary (outer_op, result_mode, result_mode, x);
8786 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
8792 /* Like recog, but we receive the address of a pointer to a new pattern.
8793 We try to match the rtx that the pointer points to.
8794 If that fails, we may try to modify or replace the pattern,
8795 storing the replacement into the same pointer object.
8797 Modifications include deletion or addition of CLOBBERs.
8799 PNOTES is a pointer to a location where any REG_UNUSED notes added for
8800 the CLOBBERs are placed.
8802 PADDED_SCRATCHES is set to the number of (clobber (scratch)) patterns
8805 The value is the final insn code from the pattern ultimately matched,
8809 recog_for_combine (pnewpat, insn, pnotes, padded_scratches)
8813 int *padded_scratches;
8815 register rtx pat = *pnewpat;
8816 int insn_code_number;
8817 int num_clobbers_to_add = 0;
8821 *padded_scratches = 0;
8823 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
8824 we use to indicate that something didn't match. If we find such a
8825 thing, force rejection. */
8826 if (GET_CODE (pat) == PARALLEL)
8827 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
8828 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
8829 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
8832 /* Is the result of combination a valid instruction? */
8833 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8835 /* If it isn't, there is the possibility that we previously had an insn
8836 that clobbered some register as a side effect, but the combined
8837 insn doesn't need to do that. So try once more without the clobbers
8838 unless this represents an ASM insn. */
8840 if (insn_code_number < 0 && ! check_asm_operands (pat)
8841 && GET_CODE (pat) == PARALLEL)
8845 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
8846 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
8849 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
8853 SUBST_INT (XVECLEN (pat, 0), pos);
8856 pat = XVECEXP (pat, 0, 0);
8858 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
8861 /* If we had any clobbers to add, make a new pattern than contains
8862 them. Then check to make sure that all of them are dead. */
8863 if (num_clobbers_to_add)
8865 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
8866 gen_rtvec (GET_CODE (pat) == PARALLEL
8867 ? XVECLEN (pat, 0) + num_clobbers_to_add
8868 : num_clobbers_to_add + 1));
8870 if (GET_CODE (pat) == PARALLEL)
8871 for (i = 0; i < XVECLEN (pat, 0); i++)
8872 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
8874 XVECEXP (newpat, 0, 0) = pat;
8876 add_clobbers (newpat, insn_code_number);
8878 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
8879 i < XVECLEN (newpat, 0); i++)
8881 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
8882 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
8884 else if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == SCRATCH)
8885 (*padded_scratches)++;
8886 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
8887 XEXP (XVECEXP (newpat, 0, i), 0), notes);
8895 return insn_code_number;
8898 /* Like gen_lowpart but for use by combine. In combine it is not possible
8899 to create any new pseudoregs. However, it is safe to create
8900 invalid memory addresses, because combine will try to recognize
8901 them and all they will do is make the combine attempt fail.
8903 If for some reason this cannot do its job, an rtx
8904 (clobber (const_int 0)) is returned.
8905 An insn containing that will not be recognized. */
8910 gen_lowpart_for_combine (mode, x)
8911 enum machine_mode mode;
8916 if (GET_MODE (x) == mode)
8919 /* We can only support MODE being wider than a word if X is a
8920 constant integer or has a mode the same size. */
8922 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
8923 && ! ((GET_MODE (x) == VOIDmode
8924 && (GET_CODE (x) == CONST_INT
8925 || GET_CODE (x) == CONST_DOUBLE))
8926 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
8927 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8929 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
8930 won't know what to do. So we will strip off the SUBREG here and
8931 process normally. */
8932 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
8935 if (GET_MODE (x) == mode)
8939 result = gen_lowpart_common (mode, x);
8941 && GET_CODE (result) == SUBREG
8942 && GET_CODE (SUBREG_REG (result)) == REG
8943 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
8944 && (GET_MODE_SIZE (GET_MODE (result))
8945 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
8946 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
8951 if (GET_CODE (x) == MEM)
8953 register int offset = 0;
8956 /* Refuse to work on a volatile memory ref or one with a mode-dependent
8958 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
8959 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
8961 /* If we want to refer to something bigger than the original memref,
8962 generate a perverse subreg instead. That will force a reload
8963 of the original memref X. */
8964 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
8965 return gen_rtx (SUBREG, mode, x, 0);
8967 if (WORDS_BIG_ENDIAN)
8968 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
8969 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
8970 if (BYTES_BIG_ENDIAN)
8972 /* Adjust the address so that the address-after-the-data is
8974 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
8975 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
8977 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
8978 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
8979 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
8980 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
8984 /* If X is a comparison operator, rewrite it in a new mode. This
8985 probably won't match, but may allow further simplifications. */
8986 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
8987 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
8989 /* If we couldn't simplify X any other way, just enclose it in a
8990 SUBREG. Normally, this SUBREG won't match, but some patterns may
8991 include an explicit SUBREG or we may simplify it further in combine. */
8996 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
8997 word = ((GET_MODE_SIZE (GET_MODE (x))
8998 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9000 return gen_rtx (SUBREG, mode, x, word);
9004 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9005 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9007 If the identical expression was previously in the insn (in the undobuf),
9008 it will be returned. Only if it is not found will a new expression
9013 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9017 enum machine_mode mode;
9030 code = va_arg (p, enum rtx_code);
9031 mode = va_arg (p, enum machine_mode);
9034 n_args = GET_RTX_LENGTH (code);
9035 fmt = GET_RTX_FORMAT (code);
9037 if (n_args == 0 || n_args > 3)
9040 /* Get each arg and verify that it is supposed to be an expression. */
9041 for (j = 0; j < n_args; j++)
9046 args[j] = va_arg (p, rtx);
9049 /* See if this is in undobuf. Be sure we don't use objects that came
9050 from another insn; this could produce circular rtl structures. */
9052 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9054 && GET_CODE (undo->old_contents.r) == code
9055 && GET_MODE (undo->old_contents.r) == mode)
9057 for (j = 0; j < n_args; j++)
9058 if (XEXP (undo->old_contents.r, j) != args[j])
9062 return undo->old_contents.r;
9065 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9066 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9067 rt = rtx_alloc (code);
9068 PUT_MODE (rt, mode);
9069 XEXP (rt, 0) = args[0];
9072 XEXP (rt, 1) = args[1];
9074 XEXP (rt, 2) = args[2];
9079 /* These routines make binary and unary operations by first seeing if they
9080 fold; if not, a new expression is allocated. */
9083 gen_binary (code, mode, op0, op1)
9085 enum machine_mode mode;
9091 if (GET_RTX_CLASS (code) == 'c'
9092 && (GET_CODE (op0) == CONST_INT
9093 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9094 tem = op0, op0 = op1, op1 = tem;
9096 if (GET_RTX_CLASS (code) == '<')
9098 enum machine_mode op_mode = GET_MODE (op0);
9100 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9101 just (REL_OP X Y). */
9102 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9104 op1 = XEXP (op0, 1);
9105 op0 = XEXP (op0, 0);
9106 op_mode = GET_MODE (op0);
9109 if (op_mode == VOIDmode)
9110 op_mode = GET_MODE (op1);
9111 result = simplify_relational_operation (code, op_mode, op0, op1);
9114 result = simplify_binary_operation (code, mode, op0, op1);
9119 /* Put complex operands first and constants second. */
9120 if (GET_RTX_CLASS (code) == 'c'
9121 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9122 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9123 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9124 || (GET_CODE (op0) == SUBREG
9125 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9126 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9127 return gen_rtx_combine (code, mode, op1, op0);
9129 return gen_rtx_combine (code, mode, op0, op1);
9133 gen_unary (code, mode, op0_mode, op0)
9135 enum machine_mode mode, op0_mode;
9138 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9143 return gen_rtx_combine (code, mode, op0);
9146 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9147 comparison code that will be tested.
9149 The result is a possibly different comparison code to use. *POP0 and
9150 *POP1 may be updated.
9152 It is possible that we might detect that a comparison is either always
9153 true or always false. However, we do not perform general constant
9154 folding in combine, so this knowledge isn't useful. Such tautologies
9155 should have been detected earlier. Hence we ignore all such cases. */
9157 static enum rtx_code
9158 simplify_comparison (code, pop0, pop1)
9167 enum machine_mode mode, tmode;
9169 /* Try a few ways of applying the same transformation to both operands. */
9172 #ifndef WORD_REGISTER_OPERATIONS
9173 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9174 so check specially. */
9175 if (code != GTU && code != GEU && code != LTU && code != LEU
9176 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9177 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9178 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9179 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9180 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9181 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9182 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9183 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9184 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9185 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9186 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9187 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9188 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9189 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9190 && (INTVAL (XEXP (op0, 1))
9191 == (GET_MODE_BITSIZE (GET_MODE (op0))
9193 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9195 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9196 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9200 /* If both operands are the same constant shift, see if we can ignore the
9201 shift. We can if the shift is a rotate or if the bits shifted out of
9202 this shift are known to be zero for both inputs and if the type of
9203 comparison is compatible with the shift. */
9204 if (GET_CODE (op0) == GET_CODE (op1)
9205 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9206 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9207 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9208 && (code != GT && code != LT && code != GE && code != LE))
9209 || (GET_CODE (op0) == ASHIFTRT
9210 && (code != GTU && code != LTU
9211 && code != GEU && code != GEU)))
9212 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9213 && INTVAL (XEXP (op0, 1)) >= 0
9214 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9215 && XEXP (op0, 1) == XEXP (op1, 1))
9217 enum machine_mode mode = GET_MODE (op0);
9218 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9219 int shift_count = INTVAL (XEXP (op0, 1));
9221 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9222 mask &= (mask >> shift_count) << shift_count;
9223 else if (GET_CODE (op0) == ASHIFT)
9224 mask = (mask & (mask << shift_count)) >> shift_count;
9226 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9227 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9228 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9233 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9234 SUBREGs are of the same mode, and, in both cases, the AND would
9235 be redundant if the comparison was done in the narrower mode,
9236 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9237 and the operand's possibly nonzero bits are 0xffffff01; in that case
9238 if we only care about QImode, we don't need the AND). This case
9239 occurs if the output mode of an scc insn is not SImode and
9240 STORE_FLAG_VALUE == 1 (e.g., the 386).
9242 Similarly, check for a case where the AND's are ZERO_EXTEND
9243 operations from some narrower mode even though a SUBREG is not
9246 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9247 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9248 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9250 rtx inner_op0 = XEXP (op0, 0);
9251 rtx inner_op1 = XEXP (op1, 0);
9252 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9253 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9256 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9257 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9258 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9259 && (GET_MODE (SUBREG_REG (inner_op0))
9260 == GET_MODE (SUBREG_REG (inner_op1)))
9261 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9262 <= HOST_BITS_PER_WIDE_INT)
9263 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9264 GET_MODE (SUBREG_REG (op0)))))
9265 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9266 GET_MODE (SUBREG_REG (inner_op1))))))
9268 op0 = SUBREG_REG (inner_op0);
9269 op1 = SUBREG_REG (inner_op1);
9271 /* The resulting comparison is always unsigned since we masked
9272 off the original sign bit. */
9273 code = unsigned_condition (code);
9279 for (tmode = GET_CLASS_NARROWEST_MODE
9280 (GET_MODE_CLASS (GET_MODE (op0)));
9281 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9282 if (c0 == GET_MODE_MASK (tmode))
9284 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9285 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9286 code = unsigned_condition (code);
9295 /* If both operands are NOT, we can strip off the outer operation
9296 and adjust the comparison code for swapped operands; similarly for
9297 NEG, except that this must be an equality comparison. */
9298 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9299 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9300 && (code == EQ || code == NE)))
9301 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9307 /* If the first operand is a constant, swap the operands and adjust the
9308 comparison code appropriately, but don't do this if the second operand
9309 is already a constant integer. */
9310 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9312 tem = op0, op0 = op1, op1 = tem;
9313 code = swap_condition (code);
9316 /* We now enter a loop during which we will try to simplify the comparison.
9317 For the most part, we only are concerned with comparisons with zero,
9318 but some things may really be comparisons with zero but not start
9319 out looking that way. */
9321 while (GET_CODE (op1) == CONST_INT)
9323 enum machine_mode mode = GET_MODE (op0);
9324 int mode_width = GET_MODE_BITSIZE (mode);
9325 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9326 int equality_comparison_p;
9327 int sign_bit_comparison_p;
9328 int unsigned_comparison_p;
9329 HOST_WIDE_INT const_op;
9331 /* We only want to handle integral modes. This catches VOIDmode,
9332 CCmode, and the floating-point modes. An exception is that we
9333 can handle VOIDmode if OP0 is a COMPARE or a comparison
9336 if (GET_MODE_CLASS (mode) != MODE_INT
9337 && ! (mode == VOIDmode
9338 && (GET_CODE (op0) == COMPARE
9339 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9342 /* Get the constant we are comparing against and turn off all bits
9343 not on in our mode. */
9344 const_op = INTVAL (op1);
9345 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9348 /* If we are comparing against a constant power of two and the value
9349 being compared can only have that single bit nonzero (e.g., it was
9350 `and'ed with that bit), we can replace this with a comparison
9353 && (code == EQ || code == NE || code == GE || code == GEU
9354 || code == LT || code == LTU)
9355 && mode_width <= HOST_BITS_PER_WIDE_INT
9356 && exact_log2 (const_op) >= 0
9357 && nonzero_bits (op0, mode) == const_op)
9359 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9360 op1 = const0_rtx, const_op = 0;
9363 /* Similarly, if we are comparing a value known to be either -1 or
9364 0 with -1, change it to the opposite comparison against zero. */
9367 && (code == EQ || code == NE || code == GT || code == LE
9368 || code == GEU || code == LTU)
9369 && num_sign_bit_copies (op0, mode) == mode_width)
9371 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9372 op1 = const0_rtx, const_op = 0;
9375 /* Do some canonicalizations based on the comparison code. We prefer
9376 comparisons against zero and then prefer equality comparisons.
9377 If we can reduce the size of a constant, we will do that too. */
9382 /* < C is equivalent to <= (C - 1) */
9386 op1 = GEN_INT (const_op);
9388 /* ... fall through to LE case below. */
9394 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9398 op1 = GEN_INT (const_op);
9402 /* If we are doing a <= 0 comparison on a value known to have
9403 a zero sign bit, we can replace this with == 0. */
9404 else if (const_op == 0
9405 && mode_width <= HOST_BITS_PER_WIDE_INT
9406 && (nonzero_bits (op0, mode)
9407 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9412 /* >= C is equivalent to > (C - 1). */
9416 op1 = GEN_INT (const_op);
9418 /* ... fall through to GT below. */
9424 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9428 op1 = GEN_INT (const_op);
9432 /* If we are doing a > 0 comparison on a value known to have
9433 a zero sign bit, we can replace this with != 0. */
9434 else if (const_op == 0
9435 && mode_width <= HOST_BITS_PER_WIDE_INT
9436 && (nonzero_bits (op0, mode)
9437 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9442 /* < C is equivalent to <= (C - 1). */
9446 op1 = GEN_INT (const_op);
9448 /* ... fall through ... */
9451 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9452 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9453 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9455 const_op = 0, op1 = const0_rtx;
9463 /* unsigned <= 0 is equivalent to == 0 */
9467 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9468 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9469 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9471 const_op = 0, op1 = const0_rtx;
9477 /* >= C is equivalent to < (C - 1). */
9481 op1 = GEN_INT (const_op);
9483 /* ... fall through ... */
9486 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9487 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9488 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9490 const_op = 0, op1 = const0_rtx;
9498 /* unsigned > 0 is equivalent to != 0 */
9502 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9503 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9504 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9506 const_op = 0, op1 = const0_rtx;
9515 /* Compute some predicates to simplify code below. */
9517 equality_comparison_p = (code == EQ || code == NE);
9518 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9519 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9522 /* If this is a sign bit comparison and we can do arithmetic in
9523 MODE, say that we will only be needing the sign bit of OP0. */
9524 if (sign_bit_comparison_p
9525 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9526 op0 = force_to_mode (op0, mode,
9528 << (GET_MODE_BITSIZE (mode) - 1)),
9531 /* Now try cases based on the opcode of OP0. If none of the cases
9532 does a "continue", we exit this loop immediately after the
9535 switch (GET_CODE (op0))
9538 /* If we are extracting a single bit from a variable position in
9539 a constant that has only a single bit set and are comparing it
9540 with zero, we can convert this into an equality comparison
9541 between the position and the location of the single bit. */
9543 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9544 && XEXP (op0, 1) == const1_rtx
9545 && equality_comparison_p && const_op == 0
9546 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9548 if (BITS_BIG_ENDIAN)
9550 i = (GET_MODE_BITSIZE
9551 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
9553 i = BITS_PER_WORD - 1 - i;
9556 op0 = XEXP (op0, 2);
9560 /* Result is nonzero iff shift count is equal to I. */
9561 code = reverse_condition (code);
9565 /* ... fall through ... */
9568 tem = expand_compound_operation (op0);
9577 /* If testing for equality, we can take the NOT of the constant. */
9578 if (equality_comparison_p
9579 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9581 op0 = XEXP (op0, 0);
9586 /* If just looking at the sign bit, reverse the sense of the
9588 if (sign_bit_comparison_p)
9590 op0 = XEXP (op0, 0);
9591 code = (code == GE ? LT : GE);
9597 /* If testing for equality, we can take the NEG of the constant. */
9598 if (equality_comparison_p
9599 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9601 op0 = XEXP (op0, 0);
9606 /* The remaining cases only apply to comparisons with zero. */
9610 /* When X is ABS or is known positive,
9611 (neg X) is < 0 if and only if X != 0. */
9613 if (sign_bit_comparison_p
9614 && (GET_CODE (XEXP (op0, 0)) == ABS
9615 || (mode_width <= HOST_BITS_PER_WIDE_INT
9616 && (nonzero_bits (XEXP (op0, 0), mode)
9617 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9619 op0 = XEXP (op0, 0);
9620 code = (code == LT ? NE : EQ);
9624 /* If we have NEG of something whose two high-order bits are the
9625 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9626 if (num_sign_bit_copies (op0, mode) >= 2)
9628 op0 = XEXP (op0, 0);
9629 code = swap_condition (code);
9635 /* If we are testing equality and our count is a constant, we
9636 can perform the inverse operation on our RHS. */
9637 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9638 && (tem = simplify_binary_operation (ROTATERT, mode,
9639 op1, XEXP (op0, 1))) != 0)
9641 op0 = XEXP (op0, 0);
9646 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9647 a particular bit. Convert it to an AND of a constant of that
9648 bit. This will be converted into a ZERO_EXTRACT. */
9649 if (const_op == 0 && sign_bit_comparison_p
9650 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9651 && mode_width <= HOST_BITS_PER_WIDE_INT)
9653 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9656 - INTVAL (XEXP (op0, 1)))));
9657 code = (code == LT ? NE : EQ);
9661 /* ... fall through ... */
9664 /* ABS is ignorable inside an equality comparison with zero. */
9665 if (const_op == 0 && equality_comparison_p)
9667 op0 = XEXP (op0, 0);
9674 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9675 to (compare FOO CONST) if CONST fits in FOO's mode and we
9676 are either testing inequality or have an unsigned comparison
9677 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9678 if (! unsigned_comparison_p
9679 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9680 <= HOST_BITS_PER_WIDE_INT)
9681 && ((unsigned HOST_WIDE_INT) const_op
9682 < (((HOST_WIDE_INT) 1
9683 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9685 op0 = XEXP (op0, 0);
9691 /* Check for the case where we are comparing A - C1 with C2,
9692 both constants are smaller than 1/2 the maximum positive
9693 value in MODE, and the comparison is equality or unsigned.
9694 In that case, if A is either zero-extended to MODE or has
9695 sufficient sign bits so that the high-order bit in MODE
9696 is a copy of the sign in the inner mode, we can prove that it is
9697 safe to do the operation in the wider mode. This simplifies
9698 many range checks. */
9700 if (mode_width <= HOST_BITS_PER_WIDE_INT
9701 && subreg_lowpart_p (op0)
9702 && GET_CODE (SUBREG_REG (op0)) == PLUS
9703 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9704 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9705 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9706 < GET_MODE_MASK (mode) / 2)
9707 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9708 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9709 GET_MODE (SUBREG_REG (op0)))
9710 & ~ GET_MODE_MASK (mode))
9711 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9712 GET_MODE (SUBREG_REG (op0)))
9713 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9714 - GET_MODE_BITSIZE (mode)))))
9716 op0 = SUBREG_REG (op0);
9720 /* If the inner mode is narrower and we are extracting the low part,
9721 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9722 if (subreg_lowpart_p (op0)
9723 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9724 /* Fall through */ ;
9728 /* ... fall through ... */
9731 if ((unsigned_comparison_p || equality_comparison_p)
9732 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9733 <= HOST_BITS_PER_WIDE_INT)
9734 && ((unsigned HOST_WIDE_INT) const_op
9735 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
9737 op0 = XEXP (op0, 0);
9743 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9744 this for equality comparisons due to pathological cases involving
9746 if (equality_comparison_p
9747 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9748 op1, XEXP (op0, 1))))
9750 op0 = XEXP (op0, 0);
9755 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9756 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9757 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9759 op0 = XEXP (XEXP (op0, 0), 0);
9760 code = (code == LT ? EQ : NE);
9766 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9767 (eq B (minus A C)), whichever simplifies. We can only do
9768 this for equality comparisons due to pathological cases involving
9770 if (equality_comparison_p
9771 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9772 XEXP (op0, 1), op1)))
9774 op0 = XEXP (op0, 0);
9779 if (equality_comparison_p
9780 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9781 XEXP (op0, 0), op1)))
9783 op0 = XEXP (op0, 1);
9788 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9789 of bits in X minus 1, is one iff X > 0. */
9790 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9791 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9792 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
9793 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9795 op0 = XEXP (op0, 1);
9796 code = (code == GE ? LE : GT);
9802 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9803 if C is zero or B is a constant. */
9804 if (equality_comparison_p
9805 && 0 != (tem = simplify_binary_operation (XOR, mode,
9806 XEXP (op0, 1), op1)))
9808 op0 = XEXP (op0, 0);
9815 case LT: case LTU: case LE: case LEU:
9816 case GT: case GTU: case GE: case GEU:
9817 /* We can't do anything if OP0 is a condition code value, rather
9818 than an actual data value. */
9821 || XEXP (op0, 0) == cc0_rtx
9823 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9826 /* Get the two operands being compared. */
9827 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9828 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9830 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9832 /* Check for the cases where we simply want the result of the
9833 earlier test or the opposite of that result. */
9835 || (code == EQ && reversible_comparison_p (op0))
9836 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9837 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9838 && (STORE_FLAG_VALUE
9839 & (((HOST_WIDE_INT) 1
9840 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9842 || (code == GE && reversible_comparison_p (op0)))))
9844 code = (code == LT || code == NE
9845 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
9846 op0 = tem, op1 = tem1;
9852 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
9854 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
9855 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
9856 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9858 op0 = XEXP (op0, 1);
9859 code = (code == GE ? GT : LE);
9865 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
9866 will be converted to a ZERO_EXTRACT later. */
9867 if (const_op == 0 && equality_comparison_p
9868 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9869 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
9871 op0 = simplify_and_const_int
9872 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
9874 XEXP (XEXP (op0, 0), 1)),
9879 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
9880 zero and X is a comparison and C1 and C2 describe only bits set
9881 in STORE_FLAG_VALUE, we can compare with X. */
9882 if (const_op == 0 && equality_comparison_p
9883 && mode_width <= HOST_BITS_PER_WIDE_INT
9884 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9885 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
9886 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9887 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
9888 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9890 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9891 << INTVAL (XEXP (XEXP (op0, 0), 1)));
9892 if ((~ STORE_FLAG_VALUE & mask) == 0
9893 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
9894 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
9895 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
9897 op0 = XEXP (XEXP (op0, 0), 0);
9902 /* If we are doing an equality comparison of an AND of a bit equal
9903 to the sign bit, replace this with a LT or GE comparison of
9904 the underlying value. */
9905 if (equality_comparison_p
9907 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9908 && mode_width <= HOST_BITS_PER_WIDE_INT
9909 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
9910 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9912 op0 = XEXP (op0, 0);
9913 code = (code == EQ ? GE : LT);
9917 /* If this AND operation is really a ZERO_EXTEND from a narrower
9918 mode, the constant fits within that mode, and this is either an
9919 equality or unsigned comparison, try to do this comparison in
9920 the narrower mode. */
9921 if ((equality_comparison_p || unsigned_comparison_p)
9922 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9923 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
9924 & GET_MODE_MASK (mode))
9926 && const_op >> i == 0
9927 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
9929 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
9935 /* If we have (compare (ashift FOO N) (const_int C)) and
9936 the high order N bits of FOO (N+1 if an inequality comparison)
9937 are known to be zero, we can do this by comparing FOO with C
9938 shifted right N bits so long as the low-order N bits of C are
9940 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
9941 && INTVAL (XEXP (op0, 1)) >= 0
9942 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
9943 < HOST_BITS_PER_WIDE_INT)
9945 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
9946 && mode_width <= HOST_BITS_PER_WIDE_INT
9947 && (nonzero_bits (XEXP (op0, 0), mode)
9948 & ~ (mask >> (INTVAL (XEXP (op0, 1))
9949 + ! equality_comparison_p))) == 0)
9951 const_op >>= INTVAL (XEXP (op0, 1));
9952 op1 = GEN_INT (const_op);
9953 op0 = XEXP (op0, 0);
9957 /* If we are doing a sign bit comparison, it means we are testing
9958 a particular bit. Convert it to the appropriate AND. */
9959 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9960 && mode_width <= HOST_BITS_PER_WIDE_INT)
9962 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9965 - INTVAL (XEXP (op0, 1)))));
9966 code = (code == LT ? NE : EQ);
9970 /* If this an equality comparison with zero and we are shifting
9971 the low bit to the sign bit, we can convert this to an AND of the
9973 if (const_op == 0 && equality_comparison_p
9974 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9975 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
9977 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9984 /* If this is an equality comparison with zero, we can do this
9985 as a logical shift, which might be much simpler. */
9986 if (equality_comparison_p && const_op == 0
9987 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
9989 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
9991 INTVAL (XEXP (op0, 1)));
9995 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
9996 do the comparison in a narrower mode. */
9997 if (! unsigned_comparison_p
9998 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9999 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10000 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10001 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10002 MODE_INT, 1)) != BLKmode
10003 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10004 || ((unsigned HOST_WIDE_INT) - const_op
10005 <= GET_MODE_MASK (tmode))))
10007 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10011 /* ... fall through ... */
10013 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10014 the low order N bits of FOO are known to be zero, we can do this
10015 by comparing FOO with C shifted left N bits so long as no
10016 overflow occurs. */
10017 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10018 && INTVAL (XEXP (op0, 1)) >= 0
10019 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10020 && mode_width <= HOST_BITS_PER_WIDE_INT
10021 && (nonzero_bits (XEXP (op0, 0), mode)
10022 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10024 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10027 const_op <<= INTVAL (XEXP (op0, 1));
10028 op1 = GEN_INT (const_op);
10029 op0 = XEXP (op0, 0);
10033 /* If we are using this shift to extract just the sign bit, we
10034 can replace this with an LT or GE comparison. */
10036 && (equality_comparison_p || sign_bit_comparison_p)
10037 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10038 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10040 op0 = XEXP (op0, 0);
10041 code = (code == NE || code == GT ? LT : GE);
10053 /* Now make any compound operations involved in this comparison. Then,
10054 check for an outmost SUBREG on OP0 that isn't doing anything or is
10055 paradoxical. The latter case can only occur when it is known that the
10056 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10057 We can never remove a SUBREG for a non-equality comparison because the
10058 sign bit is in a different place in the underlying object. */
10060 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10061 op1 = make_compound_operation (op1, SET);
10063 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10064 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10065 && (code == NE || code == EQ)
10066 && ((GET_MODE_SIZE (GET_MODE (op0))
10067 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10069 op0 = SUBREG_REG (op0);
10070 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10073 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10074 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10075 && (code == NE || code == EQ)
10076 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10077 <= HOST_BITS_PER_WIDE_INT)
10078 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10079 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10080 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10082 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10083 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10084 op0 = SUBREG_REG (op0), op1 = tem;
10086 /* We now do the opposite procedure: Some machines don't have compare
10087 insns in all modes. If OP0's mode is an integer mode smaller than a
10088 word and we can't do a compare in that mode, see if there is a larger
10089 mode for which we can do the compare. There are a number of cases in
10090 which we can use the wider mode. */
10092 mode = GET_MODE (op0);
10093 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10094 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10095 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10096 for (tmode = GET_MODE_WIDER_MODE (mode);
10098 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10099 tmode = GET_MODE_WIDER_MODE (tmode))
10100 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10102 /* If the only nonzero bits in OP0 and OP1 are those in the
10103 narrower mode and this is an equality or unsigned comparison,
10104 we can use the wider mode. Similarly for sign-extended
10105 values, in which case it is true for all comparisons. */
10106 if (((code == EQ || code == NE
10107 || code == GEU || code == GTU || code == LEU || code == LTU)
10108 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10109 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10110 || ((num_sign_bit_copies (op0, tmode)
10111 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10112 && (num_sign_bit_copies (op1, tmode)
10113 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10115 op0 = gen_lowpart_for_combine (tmode, op0);
10116 op1 = gen_lowpart_for_combine (tmode, op1);
10120 /* If this is a test for negative, we can make an explicit
10121 test of the sign bit. */
10123 if (op1 == const0_rtx && (code == LT || code == GE)
10124 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10126 op0 = gen_binary (AND, tmode,
10127 gen_lowpart_for_combine (tmode, op0),
10128 GEN_INT ((HOST_WIDE_INT) 1
10129 << (GET_MODE_BITSIZE (mode) - 1)));
10130 code = (code == LT) ? NE : EQ;
10135 #ifdef CANONICALIZE_COMPARISON
10136 /* If this machine only supports a subset of valid comparisons, see if we
10137 can convert an unsupported one into a supported one. */
10138 CANONICALIZE_COMPARISON (code, op0, op1);
10147 /* Return 1 if we know that X, a comparison operation, is not operating
10148 on a floating-point value or is EQ or NE, meaning that we can safely
10152 reversible_comparison_p (x)
10155 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10157 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10160 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10163 case MODE_PARTIAL_INT:
10164 case MODE_COMPLEX_INT:
10168 /* If the mode of the condition codes tells us that this is safe,
10169 we need look no further. */
10170 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10173 /* Otherwise try and find where the condition codes were last set and
10175 x = get_last_value (XEXP (x, 0));
10176 return (x && GET_CODE (x) == COMPARE
10177 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10184 /* Utility function for following routine. Called when X is part of a value
10185 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10186 for each register mentioned. Similar to mention_regs in cse.c */
10189 update_table_tick (x)
10192 register enum rtx_code code = GET_CODE (x);
10193 register char *fmt = GET_RTX_FORMAT (code);
10198 int regno = REGNO (x);
10199 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10200 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10202 for (i = regno; i < endregno; i++)
10203 reg_last_set_table_tick[i] = label_tick;
10208 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10209 /* Note that we can't have an "E" in values stored; see
10210 get_last_value_validate. */
10212 update_table_tick (XEXP (x, i));
10215 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10216 are saying that the register is clobbered and we no longer know its
10217 value. If INSN is zero, don't update reg_last_set; this is only permitted
10218 with VALUE also zero and is used to invalidate the register. */
10221 record_value_for_reg (reg, insn, value)
10226 int regno = REGNO (reg);
10227 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10228 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10231 /* If VALUE contains REG and we have a previous value for REG, substitute
10232 the previous value. */
10233 if (value && insn && reg_overlap_mentioned_p (reg, value))
10237 /* Set things up so get_last_value is allowed to see anything set up to
10239 subst_low_cuid = INSN_CUID (insn);
10240 tem = get_last_value (reg);
10243 value = replace_rtx (copy_rtx (value), reg, tem);
10246 /* For each register modified, show we don't know its value, that
10247 we don't know about its bitwise content, that its value has been
10248 updated, and that we don't know the location of the death of the
10250 for (i = regno; i < endregno; i ++)
10253 reg_last_set[i] = insn;
10254 reg_last_set_value[i] = 0;
10255 reg_last_set_mode[i] = 0;
10256 reg_last_set_nonzero_bits[i] = 0;
10257 reg_last_set_sign_bit_copies[i] = 0;
10258 reg_last_death[i] = 0;
10261 /* Mark registers that are being referenced in this value. */
10263 update_table_tick (value);
10265 /* Now update the status of each register being set.
10266 If someone is using this register in this block, set this register
10267 to invalid since we will get confused between the two lives in this
10268 basic block. This makes using this register always invalid. In cse, we
10269 scan the table to invalidate all entries using this register, but this
10270 is too much work for us. */
10272 for (i = regno; i < endregno; i++)
10274 reg_last_set_label[i] = label_tick;
10275 if (value && reg_last_set_table_tick[i] == label_tick)
10276 reg_last_set_invalid[i] = 1;
10278 reg_last_set_invalid[i] = 0;
10281 /* The value being assigned might refer to X (like in "x++;"). In that
10282 case, we must replace it with (clobber (const_int 0)) to prevent
10284 if (value && ! get_last_value_validate (&value, insn,
10285 reg_last_set_label[regno], 0))
10287 value = copy_rtx (value);
10288 if (! get_last_value_validate (&value, insn,
10289 reg_last_set_label[regno], 1))
10293 /* For the main register being modified, update the value, the mode, the
10294 nonzero bits, and the number of sign bit copies. */
10296 reg_last_set_value[regno] = value;
10300 subst_low_cuid = INSN_CUID (insn);
10301 reg_last_set_mode[regno] = GET_MODE (reg);
10302 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10303 reg_last_set_sign_bit_copies[regno]
10304 = num_sign_bit_copies (value, GET_MODE (reg));
10308 /* Used for communication between the following two routines. */
10309 static rtx record_dead_insn;
10311 /* Called via note_stores from record_dead_and_set_regs to handle one
10312 SET or CLOBBER in an insn. */
10315 record_dead_and_set_regs_1 (dest, setter)
10318 if (GET_CODE (dest) == SUBREG)
10319 dest = SUBREG_REG (dest);
10321 if (GET_CODE (dest) == REG)
10323 /* If we are setting the whole register, we know its value. Otherwise
10324 show that we don't know the value. We can handle SUBREG in
10326 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10327 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10328 else if (GET_CODE (setter) == SET
10329 && GET_CODE (SET_DEST (setter)) == SUBREG
10330 && SUBREG_REG (SET_DEST (setter)) == dest
10331 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10332 && subreg_lowpart_p (SET_DEST (setter)))
10333 record_value_for_reg (dest, record_dead_insn,
10334 gen_lowpart_for_combine (GET_MODE (dest),
10335 SET_SRC (setter)));
10337 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10339 else if (GET_CODE (dest) == MEM
10340 /* Ignore pushes, they clobber nothing. */
10341 && ! push_operand (dest, GET_MODE (dest)))
10342 mem_last_set = INSN_CUID (record_dead_insn);
10345 /* Update the records of when each REG was most recently set or killed
10346 for the things done by INSN. This is the last thing done in processing
10347 INSN in the combiner loop.
10349 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10350 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10351 and also the similar information mem_last_set (which insn most recently
10352 modified memory) and last_call_cuid (which insn was the most recent
10353 subroutine call). */
10356 record_dead_and_set_regs (insn)
10362 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10364 if (REG_NOTE_KIND (link) == REG_DEAD
10365 && GET_CODE (XEXP (link, 0)) == REG)
10367 int regno = REGNO (XEXP (link, 0));
10369 = regno + (regno < FIRST_PSEUDO_REGISTER
10370 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10373 for (i = regno; i < endregno; i++)
10374 reg_last_death[i] = insn;
10376 else if (REG_NOTE_KIND (link) == REG_INC)
10377 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10380 if (GET_CODE (insn) == CALL_INSN)
10382 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10383 if (call_used_regs[i])
10385 reg_last_set_value[i] = 0;
10386 reg_last_set_mode[i] = 0;
10387 reg_last_set_nonzero_bits[i] = 0;
10388 reg_last_set_sign_bit_copies[i] = 0;
10389 reg_last_death[i] = 0;
10392 last_call_cuid = mem_last_set = INSN_CUID (insn);
10395 record_dead_insn = insn;
10396 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10399 /* Utility routine for the following function. Verify that all the registers
10400 mentioned in *LOC are valid when *LOC was part of a value set when
10401 label_tick == TICK. Return 0 if some are not.
10403 If REPLACE is non-zero, replace the invalid reference with
10404 (clobber (const_int 0)) and return 1. This replacement is useful because
10405 we often can get useful information about the form of a value (e.g., if
10406 it was produced by a shift that always produces -1 or 0) even though
10407 we don't know exactly what registers it was produced from. */
10410 get_last_value_validate (loc, insn, tick, replace)
10417 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10418 int len = GET_RTX_LENGTH (GET_CODE (x));
10421 if (GET_CODE (x) == REG)
10423 int regno = REGNO (x);
10424 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10425 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10428 for (j = regno; j < endregno; j++)
10429 if (reg_last_set_invalid[j]
10430 /* If this is a pseudo-register that was only set once, it is
10432 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10433 && reg_last_set_label[j] > tick))
10436 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10442 /* If this is a memory reference, make sure that there were
10443 no stores after it that might have clobbered the value. We don't
10444 have alias info, so we assume any store invalidates it. */
10445 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10446 && INSN_CUID (insn) <= mem_last_set)
10449 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
10453 for (i = 0; i < len; i++)
10455 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10456 /* Don't bother with these. They shouldn't occur anyway. */
10460 /* If we haven't found a reason for it to be invalid, it is valid. */
10464 /* Get the last value assigned to X, if known. Some registers
10465 in the value may be replaced with (clobber (const_int 0)) if their value
10466 is known longer known reliably. */
10475 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10476 then convert it to the desired mode. If this is a paradoxical SUBREG,
10477 we cannot predict what values the "extra" bits might have. */
10478 if (GET_CODE (x) == SUBREG
10479 && subreg_lowpart_p (x)
10480 && (GET_MODE_SIZE (GET_MODE (x))
10481 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10482 && (value = get_last_value (SUBREG_REG (x))) != 0)
10483 return gen_lowpart_for_combine (GET_MODE (x), value);
10485 if (GET_CODE (x) != REG)
10489 value = reg_last_set_value[regno];
10491 /* If we don't have a value or if it isn't for this basic block,
10495 || (REG_N_SETS (regno) != 1
10496 && reg_last_set_label[regno] != label_tick))
10499 /* If the value was set in a later insn than the ones we are processing,
10500 we can't use it even if the register was only set once, but make a quick
10501 check to see if the previous insn set it to something. This is commonly
10502 the case when the same pseudo is used by repeated insns.
10504 This does not work if there exists an instruction which is temporarily
10505 not on the insn chain. */
10507 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10511 /* We can not do anything useful in this case, because there is
10512 an instruction which is not on the insn chain. */
10513 if (subst_prev_insn)
10516 /* Skip over USE insns. They are not useful here, and they may have
10517 been made by combine, in which case they do not have a INSN_CUID
10518 value. We can't use prev_real_insn, because that would incorrectly
10519 take us backwards across labels. Skip over BARRIERs also, since
10520 they could have been made by combine. If we see one, we must be
10521 optimizing dead code, so it doesn't matter what we do. */
10522 for (insn = prev_nonnote_insn (subst_insn);
10523 insn && ((GET_CODE (insn) == INSN
10524 && GET_CODE (PATTERN (insn)) == USE)
10525 || GET_CODE (insn) == BARRIER
10526 || INSN_CUID (insn) >= subst_low_cuid);
10527 insn = prev_nonnote_insn (insn))
10531 && (set = single_set (insn)) != 0
10532 && rtx_equal_p (SET_DEST (set), x))
10534 value = SET_SRC (set);
10536 /* Make sure that VALUE doesn't reference X. Replace any
10537 explicit references with a CLOBBER. If there are any remaining
10538 references (rare), don't use the value. */
10540 if (reg_mentioned_p (x, value))
10541 value = replace_rtx (copy_rtx (value), x,
10542 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
10544 if (reg_overlap_mentioned_p (x, value))
10551 /* If the value has all its registers valid, return it. */
10552 if (get_last_value_validate (&value, reg_last_set[regno],
10553 reg_last_set_label[regno], 0))
10556 /* Otherwise, make a copy and replace any invalid register with
10557 (clobber (const_int 0)). If that fails for some reason, return 0. */
10559 value = copy_rtx (value);
10560 if (get_last_value_validate (&value, reg_last_set[regno],
10561 reg_last_set_label[regno], 1))
10567 /* Return nonzero if expression X refers to a REG or to memory
10568 that is set in an instruction more recent than FROM_CUID. */
10571 use_crosses_set_p (x, from_cuid)
10575 register char *fmt;
10577 register enum rtx_code code = GET_CODE (x);
10581 register int regno = REGNO (x);
10582 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10583 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10585 #ifdef PUSH_ROUNDING
10586 /* Don't allow uses of the stack pointer to be moved,
10587 because we don't know whether the move crosses a push insn. */
10588 if (regno == STACK_POINTER_REGNUM)
10591 for (;regno < endreg; regno++)
10592 if (reg_last_set[regno]
10593 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10598 if (code == MEM && mem_last_set > from_cuid)
10601 fmt = GET_RTX_FORMAT (code);
10603 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10608 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10609 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10612 else if (fmt[i] == 'e'
10613 && use_crosses_set_p (XEXP (x, i), from_cuid))
10619 /* Define three variables used for communication between the following
10622 static int reg_dead_regno, reg_dead_endregno;
10623 static int reg_dead_flag;
10625 /* Function called via note_stores from reg_dead_at_p.
10627 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10628 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10631 reg_dead_at_p_1 (dest, x)
10635 int regno, endregno;
10637 if (GET_CODE (dest) != REG)
10640 regno = REGNO (dest);
10641 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10642 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10644 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10645 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10648 /* Return non-zero if REG is known to be dead at INSN.
10650 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10651 referencing REG, it is dead. If we hit a SET referencing REG, it is
10652 live. Otherwise, see if it is live or dead at the start of the basic
10653 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10654 must be assumed to be always live. */
10657 reg_dead_at_p (reg, insn)
10663 /* Set variables for reg_dead_at_p_1. */
10664 reg_dead_regno = REGNO (reg);
10665 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10666 ? HARD_REGNO_NREGS (reg_dead_regno,
10672 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10673 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10675 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10676 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10680 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10681 beginning of function. */
10682 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10683 insn = prev_nonnote_insn (insn))
10685 note_stores (PATTERN (insn), reg_dead_at_p_1);
10687 return reg_dead_flag == 1 ? 1 : 0;
10689 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
10693 /* Get the basic block number that we were in. */
10698 for (block = 0; block < n_basic_blocks; block++)
10699 if (insn == basic_block_head[block])
10702 if (block == n_basic_blocks)
10706 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10707 if (REGNO_REG_SET_P (basic_block_live_at_start[block], i))
10713 /* Note hard registers in X that are used. This code is similar to
10714 that in flow.c, but much simpler since we don't care about pseudos. */
10717 mark_used_regs_combine (x)
10720 register RTX_CODE code = GET_CODE (x);
10721 register int regno;
10733 case ADDR_DIFF_VEC:
10736 /* CC0 must die in the insn after it is set, so we don't need to take
10737 special note of it here. */
10743 /* If we are clobbering a MEM, mark any hard registers inside the
10744 address as used. */
10745 if (GET_CODE (XEXP (x, 0)) == MEM)
10746 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
10751 /* A hard reg in a wide mode may really be multiple registers.
10752 If so, mark all of them just like the first. */
10753 if (regno < FIRST_PSEUDO_REGISTER)
10755 /* None of this applies to the stack, frame or arg pointers */
10756 if (regno == STACK_POINTER_REGNUM
10757 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
10758 || regno == HARD_FRAME_POINTER_REGNUM
10760 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
10761 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
10763 || regno == FRAME_POINTER_REGNUM)
10766 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
10768 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
10774 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
10776 register rtx testreg = SET_DEST (x);
10778 while (GET_CODE (testreg) == SUBREG
10779 || GET_CODE (testreg) == ZERO_EXTRACT
10780 || GET_CODE (testreg) == SIGN_EXTRACT
10781 || GET_CODE (testreg) == STRICT_LOW_PART)
10782 testreg = XEXP (testreg, 0);
10784 if (GET_CODE (testreg) == MEM)
10785 mark_used_regs_combine (XEXP (testreg, 0));
10787 mark_used_regs_combine (SET_SRC (x));
10795 /* Recursively scan the operands of this expression. */
10798 register char *fmt = GET_RTX_FORMAT (code);
10800 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10803 mark_used_regs_combine (XEXP (x, i));
10804 else if (fmt[i] == 'E')
10808 for (j = 0; j < XVECLEN (x, i); j++)
10809 mark_used_regs_combine (XVECEXP (x, i, j));
10816 /* Remove register number REGNO from the dead registers list of INSN.
10818 Return the note used to record the death, if there was one. */
10821 remove_death (regno, insn)
10825 register rtx note = find_regno_note (insn, REG_DEAD, regno);
10829 REG_N_DEATHS (regno)--;
10830 remove_note (insn, note);
10836 /* For each register (hardware or pseudo) used within expression X, if its
10837 death is in an instruction with cuid between FROM_CUID (inclusive) and
10838 TO_INSN (exclusive), put a REG_DEAD note for that register in the
10839 list headed by PNOTES.
10841 That said, don't move registers killed by maybe_kill_insn.
10843 This is done when X is being merged by combination into TO_INSN. These
10844 notes will then be distributed as needed. */
10847 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
10849 rtx maybe_kill_insn;
10854 register char *fmt;
10855 register int len, i;
10856 register enum rtx_code code = GET_CODE (x);
10860 register int regno = REGNO (x);
10861 register rtx where_dead = reg_last_death[regno];
10862 register rtx before_dead, after_dead;
10864 /* Don't move the register if it gets killed in between from and to */
10865 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
10866 && !reg_referenced_p (x, maybe_kill_insn))
10869 /* WHERE_DEAD could be a USE insn made by combine, so first we
10870 make sure that we have insns with valid INSN_CUID values. */
10871 before_dead = where_dead;
10872 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
10873 before_dead = PREV_INSN (before_dead);
10874 after_dead = where_dead;
10875 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
10876 after_dead = NEXT_INSN (after_dead);
10878 if (before_dead && after_dead
10879 && INSN_CUID (before_dead) >= from_cuid
10880 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
10881 || (where_dead != after_dead
10882 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
10884 rtx note = remove_death (regno, where_dead);
10886 /* It is possible for the call above to return 0. This can occur
10887 when reg_last_death points to I2 or I1 that we combined with.
10888 In that case make a new note.
10890 We must also check for the case where X is a hard register
10891 and NOTE is a death note for a range of hard registers
10892 including X. In that case, we must put REG_DEAD notes for
10893 the remaining registers in place of NOTE. */
10895 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
10896 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10897 > GET_MODE_SIZE (GET_MODE (x))))
10899 int deadregno = REGNO (XEXP (note, 0));
10901 = (deadregno + HARD_REGNO_NREGS (deadregno,
10902 GET_MODE (XEXP (note, 0))));
10903 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10906 for (i = deadregno; i < deadend; i++)
10907 if (i < regno || i >= ourend)
10908 REG_NOTES (where_dead)
10909 = gen_rtx (EXPR_LIST, REG_DEAD,
10910 gen_rtx (REG, reg_raw_mode[i], i),
10911 REG_NOTES (where_dead));
10913 /* If we didn't find any note, or if we found a REG_DEAD note that
10914 covers only part of the given reg, and we have a multi-reg hard
10915 register, then to be safe we must check for REG_DEAD notes
10916 for each register other than the first. They could have
10917 their own REG_DEAD notes lying around. */
10918 else if ((note == 0
10920 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
10921 < GET_MODE_SIZE (GET_MODE (x)))))
10922 && regno < FIRST_PSEUDO_REGISTER
10923 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
10925 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
10930 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
10934 for (i = regno + offset; i < ourend; i++)
10935 move_deaths (gen_rtx (REG, reg_raw_mode[i], i),
10936 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
10939 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
10941 XEXP (note, 1) = *pnotes;
10945 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
10947 REG_N_DEATHS (regno)++;
10953 else if (GET_CODE (x) == SET)
10955 rtx dest = SET_DEST (x);
10957 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
10959 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
10960 that accesses one word of a multi-word item, some
10961 piece of everything register in the expression is used by
10962 this insn, so remove any old death. */
10964 if (GET_CODE (dest) == ZERO_EXTRACT
10965 || GET_CODE (dest) == STRICT_LOW_PART
10966 || (GET_CODE (dest) == SUBREG
10967 && (((GET_MODE_SIZE (GET_MODE (dest))
10968 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
10969 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
10970 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
10972 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
10976 /* If this is some other SUBREG, we know it replaces the entire
10977 value, so use that as the destination. */
10978 if (GET_CODE (dest) == SUBREG)
10979 dest = SUBREG_REG (dest);
10981 /* If this is a MEM, adjust deaths of anything used in the address.
10982 For a REG (the only other possibility), the entire value is
10983 being replaced so the old value is not used in this insn. */
10985 if (GET_CODE (dest) == MEM)
10986 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
10991 else if (GET_CODE (x) == CLOBBER)
10994 len = GET_RTX_LENGTH (code);
10995 fmt = GET_RTX_FORMAT (code);
10997 for (i = 0; i < len; i++)
11002 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11003 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11006 else if (fmt[i] == 'e')
11007 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11011 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11012 pattern of an insn. X must be a REG. */
11015 reg_bitfield_target_p (x, body)
11021 if (GET_CODE (body) == SET)
11023 rtx dest = SET_DEST (body);
11025 int regno, tregno, endregno, endtregno;
11027 if (GET_CODE (dest) == ZERO_EXTRACT)
11028 target = XEXP (dest, 0);
11029 else if (GET_CODE (dest) == STRICT_LOW_PART)
11030 target = SUBREG_REG (XEXP (dest, 0));
11034 if (GET_CODE (target) == SUBREG)
11035 target = SUBREG_REG (target);
11037 if (GET_CODE (target) != REG)
11040 tregno = REGNO (target), regno = REGNO (x);
11041 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11042 return target == x;
11044 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11045 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11047 return endregno > tregno && regno < endtregno;
11050 else if (GET_CODE (body) == PARALLEL)
11051 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11052 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11058 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11059 as appropriate. I3 and I2 are the insns resulting from the combination
11060 insns including FROM (I2 may be zero).
11062 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11063 not need REG_DEAD notes because they are being substituted for. This
11064 saves searching in the most common cases.
11066 Each note in the list is either ignored or placed on some insns, depending
11067 on the type of note. */
11070 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11074 rtx elim_i2, elim_i1;
11076 rtx note, next_note;
11079 for (note = notes; note; note = next_note)
11081 rtx place = 0, place2 = 0;
11083 /* If this NOTE references a pseudo register, ensure it references
11084 the latest copy of that register. */
11085 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11086 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11087 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11089 next_note = XEXP (note, 1);
11090 switch (REG_NOTE_KIND (note))
11093 case REG_EXEC_COUNT:
11094 /* Doesn't matter much where we put this, as long as it's somewhere.
11095 It is preferable to keep these notes on branches, which is most
11096 likely to be i3. */
11101 /* Any clobbers for i3 may still exist, and so we must process
11102 REG_UNUSED notes from that insn.
11104 Any clobbers from i2 or i1 can only exist if they were added by
11105 recog_for_combine. In that case, recog_for_combine created the
11106 necessary REG_UNUSED notes. Trying to keep any original
11107 REG_UNUSED notes from these insns can cause incorrect output
11108 if it is for the same register as the original i3 dest.
11109 In that case, we will notice that the register is set in i3,
11110 and then add a REG_UNUSED note for the destination of i3, which
11111 is wrong. However, it is possible to have REG_UNUSED notes from
11112 i2 or i1 for register which were both used and clobbered, so
11113 we keep notes from i2 or i1 if they will turn into REG_DEAD
11116 /* If this register is set or clobbered in I3, put the note there
11117 unless there is one already. */
11118 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11120 if (from_insn != i3)
11123 if (! (GET_CODE (XEXP (note, 0)) == REG
11124 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11125 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11128 /* Otherwise, if this register is used by I3, then this register
11129 now dies here, so we must put a REG_DEAD note here unless there
11131 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11132 && ! (GET_CODE (XEXP (note, 0)) == REG
11133 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11134 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11136 PUT_REG_NOTE_KIND (note, REG_DEAD);
11145 /* These notes say something about results of an insn. We can
11146 only support them if they used to be on I3 in which case they
11147 remain on I3. Otherwise they are ignored.
11149 If the note refers to an expression that is not a constant, we
11150 must also ignore the note since we cannot tell whether the
11151 equivalence is still true. It might be possible to do
11152 slightly better than this (we only have a problem if I2DEST
11153 or I1DEST is present in the expression), but it doesn't
11154 seem worth the trouble. */
11156 if (from_insn == i3
11157 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11162 case REG_NO_CONFLICT:
11164 /* These notes say something about how a register is used. They must
11165 be present on any use of the register in I2 or I3. */
11166 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11169 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11179 /* It is too much trouble to try to see if this note is still
11180 correct in all situations. It is better to simply delete it. */
11184 /* If the insn previously containing this note still exists,
11185 put it back where it was. Otherwise move it to the previous
11186 insn. Adjust the corresponding REG_LIBCALL note. */
11187 if (GET_CODE (from_insn) != NOTE)
11191 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11192 place = prev_real_insn (from_insn);
11194 XEXP (tem, 0) = place;
11199 /* This is handled similarly to REG_RETVAL. */
11200 if (GET_CODE (from_insn) != NOTE)
11204 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11205 place = next_real_insn (from_insn);
11207 XEXP (tem, 0) = place;
11212 /* If the register is used as an input in I3, it dies there.
11213 Similarly for I2, if it is non-zero and adjacent to I3.
11215 If the register is not used as an input in either I3 or I2
11216 and it is not one of the registers we were supposed to eliminate,
11217 there are two possibilities. We might have a non-adjacent I2
11218 or we might have somehow eliminated an additional register
11219 from a computation. For example, we might have had A & B where
11220 we discover that B will always be zero. In this case we will
11221 eliminate the reference to A.
11223 In both cases, we must search to see if we can find a previous
11224 use of A and put the death note there. */
11227 && GET_CODE (from_insn) == CALL_INSN
11228 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11230 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11232 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11233 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11236 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11239 /* If the register is used in both I2 and I3 and it dies in I3,
11240 we might have added another reference to it. If reg_n_refs
11241 was 2, bump it to 3. This has to be correct since the
11242 register must have been set somewhere. The reason this is
11243 done is because local-alloc.c treats 2 references as a
11246 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11247 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11248 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11249 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11253 for (tem = prev_nonnote_insn (i3);
11255 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11256 tem = prev_nonnote_insn (tem))
11258 /* If the register is being set at TEM, see if that is all
11259 TEM is doing. If so, delete TEM. Otherwise, make this
11260 into a REG_UNUSED note instead. */
11261 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11263 rtx set = single_set (tem);
11265 /* Verify that it was the set, and not a clobber that
11266 modified the register. */
11268 if (set != 0 && ! side_effects_p (SET_SRC (set))
11269 && (rtx_equal_p (XEXP (note, 0), SET_DEST (set))
11270 || (GET_CODE (SET_DEST (set)) == SUBREG
11271 && rtx_equal_p (XEXP (note, 0),
11272 XEXP (SET_DEST (set), 0)))))
11274 /* Move the notes and links of TEM elsewhere.
11275 This might delete other dead insns recursively.
11276 First set the pattern to something that won't use
11279 PATTERN (tem) = pc_rtx;
11281 distribute_notes (REG_NOTES (tem), tem, tem,
11282 NULL_RTX, NULL_RTX, NULL_RTX);
11283 distribute_links (LOG_LINKS (tem));
11285 PUT_CODE (tem, NOTE);
11286 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11287 NOTE_SOURCE_FILE (tem) = 0;
11291 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11293 /* If there isn't already a REG_UNUSED note, put one
11295 if (! find_regno_note (tem, REG_UNUSED,
11296 REGNO (XEXP (note, 0))))
11301 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11302 || (GET_CODE (tem) == CALL_INSN
11303 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11307 /* If we are doing a 3->2 combination, and we have a
11308 register which formerly died in i3 and was not used
11309 by i2, which now no longer dies in i3 and is used in
11310 i2 but does not die in i2, and place is between i2
11311 and i3, then we may need to move a link from place to
11313 if (i2 && INSN_UID (place) <= max_uid_cuid
11314 && INSN_CUID (place) > INSN_CUID (i2)
11315 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11316 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11318 rtx links = LOG_LINKS (place);
11319 LOG_LINKS (place) = 0;
11320 distribute_links (links);
11326 /* If we haven't found an insn for the death note and it
11327 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11328 insert a USE insn for the register at that label and
11329 put the death node there. This prevents problems with
11330 call-state tracking in caller-save.c. */
11331 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11334 = emit_insn_after (gen_rtx (USE, VOIDmode, XEXP (note, 0)),
11337 /* If this insn was emitted between blocks, then update
11338 basic_block_head of the current block to include it. */
11339 if (basic_block_end[this_basic_block - 1] == tem)
11340 basic_block_head[this_basic_block] = place;
11344 /* If the register is set or already dead at PLACE, we needn't do
11345 anything with this note if it is still a REG_DEAD note.
11347 Note that we cannot use just `dead_or_set_p' here since we can
11348 convert an assignment to a register into a bit-field assignment.
11349 Therefore, we must also omit the note if the register is the
11350 target of a bitfield assignment. */
11352 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11354 int regno = REGNO (XEXP (note, 0));
11356 if (dead_or_set_p (place, XEXP (note, 0))
11357 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11359 /* Unless the register previously died in PLACE, clear
11360 reg_last_death. [I no longer understand why this is
11362 if (reg_last_death[regno] != place)
11363 reg_last_death[regno] = 0;
11367 reg_last_death[regno] = place;
11369 /* If this is a death note for a hard reg that is occupying
11370 multiple registers, ensure that we are still using all
11371 parts of the object. If we find a piece of the object
11372 that is unused, we must add a USE for that piece before
11373 PLACE and put the appropriate REG_DEAD note on it.
11375 An alternative would be to put a REG_UNUSED for the pieces
11376 on the insn that set the register, but that can't be done if
11377 it is not in the same block. It is simpler, though less
11378 efficient, to add the USE insns. */
11380 if (place && regno < FIRST_PSEUDO_REGISTER
11381 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11384 = regno + HARD_REGNO_NREGS (regno,
11385 GET_MODE (XEXP (note, 0)));
11389 for (i = regno; i < endregno; i++)
11390 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11391 && ! find_regno_fusage (place, USE, i))
11393 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11396 /* See if we already placed a USE note for this
11397 register in front of PLACE. */
11399 GET_CODE (PREV_INSN (p)) == INSN
11400 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11402 if (rtx_equal_p (piece,
11403 XEXP (PATTERN (PREV_INSN (p)), 0)))
11412 = emit_insn_before (gen_rtx (USE, VOIDmode,
11415 REG_NOTES (use_insn)
11416 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
11417 REG_NOTES (use_insn));
11423 /* Check for the case where the register dying partially
11424 overlaps the register set by this insn. */
11426 for (i = regno; i < endregno; i++)
11427 if (dead_or_set_regno_p (place, i))
11435 /* Put only REG_DEAD notes for pieces that are
11436 still used and that are not already dead or set. */
11438 for (i = regno; i < endregno; i++)
11440 rtx piece = gen_rtx (REG, reg_raw_mode[i], i);
11442 if ((reg_referenced_p (piece, PATTERN (place))
11443 || (GET_CODE (place) == CALL_INSN
11444 && find_reg_fusage (place, USE, piece)))
11445 && ! dead_or_set_p (place, piece)
11446 && ! reg_bitfield_target_p (piece,
11448 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
11450 REG_NOTES (place));
11460 /* Any other notes should not be present at this point in the
11467 XEXP (note, 1) = REG_NOTES (place);
11468 REG_NOTES (place) = note;
11470 else if ((REG_NOTE_KIND (note) == REG_DEAD
11471 || REG_NOTE_KIND (note) == REG_UNUSED)
11472 && GET_CODE (XEXP (note, 0)) == REG)
11473 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11477 if ((REG_NOTE_KIND (note) == REG_DEAD
11478 || REG_NOTE_KIND (note) == REG_UNUSED)
11479 && GET_CODE (XEXP (note, 0)) == REG)
11480 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11482 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
11483 XEXP (note, 0), REG_NOTES (place2));
11488 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11489 I3, I2, and I1 to new locations. This is also called in one case to
11490 add a link pointing at I3 when I3's destination is changed. */
11493 distribute_links (links)
11496 rtx link, next_link;
11498 for (link = links; link; link = next_link)
11504 next_link = XEXP (link, 1);
11506 /* If the insn that this link points to is a NOTE or isn't a single
11507 set, ignore it. In the latter case, it isn't clear what we
11508 can do other than ignore the link, since we can't tell which
11509 register it was for. Such links wouldn't be used by combine
11512 It is not possible for the destination of the target of the link to
11513 have been changed by combine. The only potential of this is if we
11514 replace I3, I2, and I1 by I3 and I2. But in that case the
11515 destination of I2 also remains unchanged. */
11517 if (GET_CODE (XEXP (link, 0)) == NOTE
11518 || (set = single_set (XEXP (link, 0))) == 0)
11521 reg = SET_DEST (set);
11522 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11523 || GET_CODE (reg) == SIGN_EXTRACT
11524 || GET_CODE (reg) == STRICT_LOW_PART)
11525 reg = XEXP (reg, 0);
11527 /* A LOG_LINK is defined as being placed on the first insn that uses
11528 a register and points to the insn that sets the register. Start
11529 searching at the next insn after the target of the link and stop
11530 when we reach a set of the register or the end of the basic block.
11532 Note that this correctly handles the link that used to point from
11533 I3 to I2. Also note that not much searching is typically done here
11534 since most links don't point very far away. */
11536 for (insn = NEXT_INSN (XEXP (link, 0));
11537 (insn && (this_basic_block == n_basic_blocks - 1
11538 || basic_block_head[this_basic_block + 1] != insn));
11539 insn = NEXT_INSN (insn))
11540 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11541 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11543 if (reg_referenced_p (reg, PATTERN (insn)))
11547 else if (GET_CODE (insn) == CALL_INSN
11548 && find_reg_fusage (insn, USE, reg))
11554 /* If we found a place to put the link, place it there unless there
11555 is already a link to the same insn as LINK at that point. */
11561 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11562 if (XEXP (link2, 0) == XEXP (link, 0))
11567 XEXP (link, 1) = LOG_LINKS (place);
11568 LOG_LINKS (place) = link;
11570 /* Set added_links_insn to the earliest insn we added a
11572 if (added_links_insn == 0
11573 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11574 added_links_insn = place;
11580 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11586 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11587 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11588 insn = NEXT_INSN (insn);
11590 if (INSN_UID (insn) > max_uid_cuid)
11593 return INSN_CUID (insn);
11597 dump_combine_stats (file)
11602 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11603 combine_attempts, combine_merges, combine_extras, combine_successes);
11607 dump_combine_total_stats (file)
11612 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
11613 total_attempts, total_merges, total_extras, total_successes);