1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
120 /* Define a default value for REVERSIBLE_CC_MODE.
121 We can never assume that a condition code mode is safe to reverse unless
122 the md tells us so. */
123 #ifndef REVERSIBLE_CC_MODE
124 #define REVERSIBLE_CC_MODE(MODE) 0
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static int combine_max_regno;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx *reg_last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx *reg_last_set;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn;
172 /* This is an insn that belongs before subst_insn, but is not currently
173 on the insn chain. */
175 static rtx subst_prev_insn;
177 /* This is the lowest CUID that `subst' is currently dealing with.
178 get_last_value will not return a value if the register was set at or
179 after this CUID. If not for this mechanism, we could get confused if
180 I2 or I1 in try_combine were an insn that used the old value of a register
181 to obtain a new value. In that case, we might erroneously get the
182 new value of the register when we wanted the old one. */
184 static int subst_low_cuid;
186 /* This contains any hard registers that are used in newpat; reg_dead_at_p
187 must consider all these registers to be always live. */
189 static HARD_REG_SET newpat_used_regs;
191 /* This is an insn to which a LOG_LINKS entry has been added. If this
192 insn is the earlier than I2 or I3, combine should rescan starting at
195 static rtx added_links_insn;
197 /* Basic block number of the block in which we are performing combines. */
198 static int this_basic_block;
200 /* A bitmap indicating which blocks had registers go dead at entry.
201 After combine, we'll need to re-do global life analysis with
202 those blocks as starting points. */
203 static sbitmap refresh_blocks;
204 static int need_refresh;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx *reg_last_set_value;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick;
264 /* Set non-zero if references to register n in expressions should not be
267 static char *reg_last_set_invalid;
269 /* Incremented for each label. */
271 static int label_tick;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static char *reg_sign_bit_copies;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode *reg_last_set_mode;
308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309 static char *reg_last_set_sign_bit_copies;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too.
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
342 struct undo *previous_undos;
346 static struct undobuf undobuf;
348 /* Number of times the pseudo being substituted for
349 was found and replaced. */
351 static int n_occurrences;
353 static void do_SUBST PROTO((rtx *, rtx));
354 static void do_SUBST_INT PROTO((int *, int));
355 static void init_reg_last_arrays PROTO((void));
356 static void setup_incoming_promotions PROTO((void));
357 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
358 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
359 static int sets_function_arg_p PROTO((rtx));
360 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
361 static rtx try_combine PROTO((rtx, rtx, rtx));
362 static void undo_all PROTO((void));
363 static rtx *find_split_point PROTO((rtx *, rtx));
364 static rtx subst PROTO((rtx, rtx, rtx, int, int));
365 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
366 static rtx simplify_if_then_else PROTO((rtx));
367 static rtx simplify_set PROTO((rtx));
368 static rtx simplify_logical PROTO((rtx, int));
369 static rtx expand_compound_operation PROTO((rtx));
370 static rtx expand_field_assignment PROTO((rtx));
371 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
373 static rtx extract_left_shift PROTO((rtx, int));
374 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
375 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
376 static rtx force_to_mode PROTO((rtx, enum machine_mode,
377 unsigned HOST_WIDE_INT, rtx, int));
378 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
379 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
380 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
381 static rtx make_field_assignment PROTO((rtx));
382 static rtx apply_distributive_law PROTO((rtx));
383 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
384 unsigned HOST_WIDE_INT));
385 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
386 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
387 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
388 enum rtx_code, HOST_WIDE_INT,
389 enum machine_mode, int *));
390 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
392 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
393 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
394 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
396 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
398 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
399 enum machine_mode, rtx));
400 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
401 static int reversible_comparison_p PROTO((rtx));
402 static void update_table_tick PROTO((rtx));
403 static void record_value_for_reg PROTO((rtx, rtx, rtx));
404 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
405 static void record_dead_and_set_regs PROTO((rtx));
406 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
407 static rtx get_last_value PROTO((rtx));
408 static int use_crosses_set_p PROTO((rtx, int));
409 static void reg_dead_at_p_1 PROTO((rtx, rtx));
410 static int reg_dead_at_p PROTO((rtx, rtx));
411 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
412 static int reg_bitfield_target_p PROTO((rtx, rtx));
413 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
414 static void distribute_links PROTO((rtx));
415 static void mark_used_regs_combine PROTO((rtx));
416 static int insn_cuid PROTO((rtx));
418 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
419 insn. The substitution can be undone by undo_all. If INTO is already
420 set to NEWVAL, do not record this change. Because computing NEWVAL might
421 also call SUBST, we have to compute it before we put anything into
425 do_SUBST(into, newval)
431 if (oldval == newval)
435 buf = undobuf.frees, undobuf.frees = buf->next;
437 buf = (struct undo *) xmalloc (sizeof (struct undo));
441 buf->old_contents.r = oldval;
444 buf->next = undobuf.undos, undobuf.undos = buf;
447 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
449 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
450 for the value of a HOST_WIDE_INT value (including CONST_INT) is
454 do_SUBST_INT(into, newval)
460 if (oldval == newval)
464 buf = undobuf.frees, undobuf.frees = buf->next;
466 buf = (struct undo *) xmalloc (sizeof (struct undo));
470 buf->old_contents.i = oldval;
473 buf->next = undobuf.undos, undobuf.undos = buf;
476 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
478 /* Main entry point for combiner. F is the first insn of the function.
479 NREGS is the first unused pseudo-reg number. */
482 combine_instructions (f, nregs)
486 register rtx insn, next;
491 register rtx links, nextlinks;
493 combine_attempts = 0;
496 combine_successes = 0;
497 undobuf.undos = undobuf.previous_undos = 0;
499 combine_max_regno = nregs;
502 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
503 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
505 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
506 bzero (reg_sign_bit_copies, nregs * sizeof (char));
508 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
509 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
510 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
511 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
512 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
513 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
515 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
516 reg_last_set_nonzero_bits
517 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
518 reg_last_set_sign_bit_copies
519 = (char *) alloca (nregs * sizeof (char));
521 init_reg_last_arrays ();
523 init_recog_no_volatile ();
525 /* Compute maximum uid value so uid_cuid can be allocated. */
527 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
528 if (INSN_UID (insn) > i)
531 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
534 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
536 /* Don't use reg_nonzero_bits when computing it. This can cause problems
537 when, for example, we have j <<= 1 in a loop. */
539 nonzero_sign_valid = 0;
541 /* Compute the mapping from uids to cuids.
542 Cuids are numbers assigned to insns, like uids,
543 except that cuids increase monotonically through the code.
545 Scan all SETs and see if we can deduce anything about what
546 bits are known to be zero for some registers and how many copies
547 of the sign bit are known to exist for those registers.
549 Also set any known values so that we can use it while searching
550 for what bits are known to be set. */
554 /* We need to initialize it here, because record_dead_and_set_regs may call
556 subst_prev_insn = NULL_RTX;
558 setup_incoming_promotions ();
560 refresh_blocks = sbitmap_alloc (n_basic_blocks);
561 sbitmap_zero (refresh_blocks);
564 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
566 uid_cuid[INSN_UID (insn)] = ++i;
570 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
572 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
573 record_dead_and_set_regs (insn);
576 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
577 if (REG_NOTE_KIND (links) == REG_INC)
578 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
582 if (GET_CODE (insn) == CODE_LABEL)
586 nonzero_sign_valid = 1;
588 /* Now scan all the insns in forward order. */
590 this_basic_block = -1;
594 init_reg_last_arrays ();
595 setup_incoming_promotions ();
597 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
601 /* If INSN starts a new basic block, update our basic block number. */
602 if (this_basic_block + 1 < n_basic_blocks
603 && BLOCK_HEAD (this_basic_block + 1) == insn)
606 if (GET_CODE (insn) == CODE_LABEL)
609 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
611 /* Try this insn with each insn it links back to. */
613 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
614 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
617 /* Try each sequence of three linked insns ending with this one. */
619 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
620 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
621 nextlinks = XEXP (nextlinks, 1))
622 if ((next = try_combine (insn, XEXP (links, 0),
623 XEXP (nextlinks, 0))) != 0)
627 /* Try to combine a jump insn that uses CC0
628 with a preceding insn that sets CC0, and maybe with its
629 logical predecessor as well.
630 This is how we make decrement-and-branch insns.
631 We need this special code because data flow connections
632 via CC0 do not get entered in LOG_LINKS. */
634 if (GET_CODE (insn) == JUMP_INSN
635 && (prev = prev_nonnote_insn (insn)) != 0
636 && GET_CODE (prev) == INSN
637 && sets_cc0_p (PATTERN (prev)))
639 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
642 for (nextlinks = LOG_LINKS (prev); nextlinks;
643 nextlinks = XEXP (nextlinks, 1))
644 if ((next = try_combine (insn, prev,
645 XEXP (nextlinks, 0))) != 0)
649 /* Do the same for an insn that explicitly references CC0. */
650 if (GET_CODE (insn) == INSN
651 && (prev = prev_nonnote_insn (insn)) != 0
652 && GET_CODE (prev) == INSN
653 && sets_cc0_p (PATTERN (prev))
654 && GET_CODE (PATTERN (insn)) == SET
655 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
657 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
660 for (nextlinks = LOG_LINKS (prev); nextlinks;
661 nextlinks = XEXP (nextlinks, 1))
662 if ((next = try_combine (insn, prev,
663 XEXP (nextlinks, 0))) != 0)
667 /* Finally, see if any of the insns that this insn links to
668 explicitly references CC0. If so, try this insn, that insn,
669 and its predecessor if it sets CC0. */
670 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
671 if (GET_CODE (XEXP (links, 0)) == INSN
672 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
673 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
674 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
675 && GET_CODE (prev) == INSN
676 && sets_cc0_p (PATTERN (prev))
677 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
681 /* Try combining an insn with two different insns whose results it
683 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
684 for (nextlinks = XEXP (links, 1); nextlinks;
685 nextlinks = XEXP (nextlinks, 1))
686 if ((next = try_combine (insn, XEXP (links, 0),
687 XEXP (nextlinks, 0))) != 0)
690 if (GET_CODE (insn) != NOTE)
691 record_dead_and_set_regs (insn);
699 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES);
700 sbitmap_free (refresh_blocks);
702 total_attempts += combine_attempts;
703 total_merges += combine_merges;
704 total_extras += combine_extras;
705 total_successes += combine_successes;
707 nonzero_sign_valid = 0;
709 /* Make recognizer allow volatile MEMs again. */
713 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
716 init_reg_last_arrays ()
718 int nregs = combine_max_regno;
720 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
721 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
722 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
723 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
724 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
725 bzero (reg_last_set_invalid, nregs * sizeof (char));
726 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
727 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
728 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
731 /* Set up any promoted values for incoming argument registers. */
734 setup_incoming_promotions ()
736 #ifdef PROMOTE_FUNCTION_ARGS
739 enum machine_mode mode;
741 rtx first = get_insns ();
743 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
744 if (FUNCTION_ARG_REGNO_P (regno)
745 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
748 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
751 gen_rtx_CLOBBER (mode, const0_rtx)));
756 /* Called via note_stores. If X is a pseudo that is narrower than
757 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
759 If we are setting only a portion of X and we can't figure out what
760 portion, assume all bits will be used since we don't know what will
763 Similarly, set how many bits of X are known to be copies of the sign bit
764 at all locations in the function. This is the smallest number implied
768 set_nonzero_bits_and_sign_copies (x, set)
774 if (GET_CODE (x) == REG
775 && REGNO (x) >= FIRST_PSEUDO_REGISTER
776 /* If this register is undefined at the start of the file, we can't
777 say what its contents were. */
778 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
779 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
781 if (set == 0 || GET_CODE (set) == CLOBBER)
783 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
784 reg_sign_bit_copies[REGNO (x)] = 1;
788 /* If this is a complex assignment, see if we can convert it into a
789 simple assignment. */
790 set = expand_field_assignment (set);
792 /* If this is a simple assignment, or we have a paradoxical SUBREG,
793 set what we know about X. */
795 if (SET_DEST (set) == x
796 || (GET_CODE (SET_DEST (set)) == SUBREG
797 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
798 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
799 && SUBREG_REG (SET_DEST (set)) == x))
801 rtx src = SET_SRC (set);
803 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
804 /* If X is narrower than a word and SRC is a non-negative
805 constant that would appear negative in the mode of X,
806 sign-extend it for use in reg_nonzero_bits because some
807 machines (maybe most) will actually do the sign-extension
808 and this is the conservative approach.
810 ??? For 2.5, try to tighten up the MD files in this regard
811 instead of this kludge. */
813 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
814 && GET_CODE (src) == CONST_INT
816 && 0 != (INTVAL (src)
818 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
819 src = GEN_INT (INTVAL (src)
820 | ((HOST_WIDE_INT) (-1)
821 << GET_MODE_BITSIZE (GET_MODE (x))));
824 reg_nonzero_bits[REGNO (x)]
825 |= nonzero_bits (src, nonzero_bits_mode);
826 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
827 if (reg_sign_bit_copies[REGNO (x)] == 0
828 || reg_sign_bit_copies[REGNO (x)] > num)
829 reg_sign_bit_copies[REGNO (x)] = num;
833 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
834 reg_sign_bit_copies[REGNO (x)] = 1;
839 /* See if INSN can be combined into I3. PRED and SUCC are optionally
840 insns that were previously combined into I3 or that will be combined
841 into the merger of INSN and I3.
843 Return 0 if the combination is not allowed for any reason.
845 If the combination is allowed, *PDEST will be set to the single
846 destination of INSN and *PSRC to the single source, and this function
850 can_combine_p (insn, i3, pred, succ, pdest, psrc)
853 rtx pred ATTRIBUTE_UNUSED;
858 rtx set = 0, src, dest;
863 int all_adjacent = (succ ? (next_active_insn (insn) == succ
864 && next_active_insn (succ) == i3)
865 : next_active_insn (insn) == i3);
867 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
868 or a PARALLEL consisting of such a SET and CLOBBERs.
870 If INSN has CLOBBER parallel parts, ignore them for our processing.
871 By definition, these happen during the execution of the insn. When it
872 is merged with another insn, all bets are off. If they are, in fact,
873 needed and aren't also supplied in I3, they may be added by
874 recog_for_combine. Otherwise, it won't match.
876 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
879 Get the source and destination of INSN. If more than one, can't
882 if (GET_CODE (PATTERN (insn)) == SET)
883 set = PATTERN (insn);
884 else if (GET_CODE (PATTERN (insn)) == PARALLEL
885 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
887 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
889 rtx elt = XVECEXP (PATTERN (insn), 0, i);
891 switch (GET_CODE (elt))
893 /* This is important to combine floating point insns
896 /* Combining an isolated USE doesn't make sense.
897 We depend here on combinable_i3_pat to reject them. */
898 /* The code below this loop only verifies that the inputs of
899 the SET in INSN do not change. We call reg_set_between_p
900 to verify that the REG in the USE does not change betweeen
902 If the USE in INSN was for a pseudo register, the matching
903 insn pattern will likely match any register; combining this
904 with any other USE would only be safe if we knew that the
905 used registers have identical values, or if there was
906 something to tell them apart, e.g. different modes. For
907 now, we forgo such compilcated tests and simply disallow
908 combining of USES of pseudo registers with any other USE. */
909 if (GET_CODE (XEXP (elt, 0)) == REG
910 && GET_CODE (PATTERN (i3)) == PARALLEL)
912 rtx i3pat = PATTERN (i3);
913 int i = XVECLEN (i3pat, 0) - 1;
914 int regno = REGNO (XEXP (elt, 0));
917 rtx i3elt = XVECEXP (i3pat, 0, i);
918 if (GET_CODE (i3elt) == USE
919 && GET_CODE (XEXP (i3elt, 0)) == REG
920 && (REGNO (XEXP (i3elt, 0)) == regno
921 ? reg_set_between_p (XEXP (elt, 0),
922 PREV_INSN (insn), i3)
923 : regno >= FIRST_PSEUDO_REGISTER))
930 /* We can ignore CLOBBERs. */
935 /* Ignore SETs whose result isn't used but not those that
936 have side-effects. */
937 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
938 && ! side_effects_p (elt))
941 /* If we have already found a SET, this is a second one and
942 so we cannot combine with this insn. */
950 /* Anything else means we can't combine. */
956 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
957 so don't do anything with it. */
958 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
967 set = expand_field_assignment (set);
968 src = SET_SRC (set), dest = SET_DEST (set);
970 /* Don't eliminate a store in the stack pointer. */
971 if (dest == stack_pointer_rtx
972 /* If we couldn't eliminate a field assignment, we can't combine. */
973 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
974 /* Don't combine with an insn that sets a register to itself if it has
975 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
976 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
977 /* Can't merge a function call. */
978 || GET_CODE (src) == CALL
979 /* Don't eliminate a function call argument. */
980 || (GET_CODE (i3) == CALL_INSN
981 && (find_reg_fusage (i3, USE, dest)
982 || (GET_CODE (dest) == REG
983 && REGNO (dest) < FIRST_PSEUDO_REGISTER
984 && global_regs[REGNO (dest)])))
985 /* Don't substitute into an incremented register. */
986 || FIND_REG_INC_NOTE (i3, dest)
987 || (succ && FIND_REG_INC_NOTE (succ, dest))
989 /* Don't combine the end of a libcall into anything. */
990 /* ??? This gives worse code, and appears to be unnecessary, since no
991 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
992 use REG_RETVAL notes for noconflict blocks, but other code here
993 makes sure that those insns don't disappear. */
994 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
996 /* Make sure that DEST is not used after SUCC but before I3. */
997 || (succ && ! all_adjacent
998 && reg_used_between_p (dest, succ, i3))
999 /* Make sure that the value that is to be substituted for the register
1000 does not use any registers whose values alter in between. However,
1001 If the insns are adjacent, a use can't cross a set even though we
1002 think it might (this can happen for a sequence of insns each setting
1003 the same destination; reg_last_set of that register might point to
1004 a NOTE). If INSN has a REG_EQUIV note, the register is always
1005 equivalent to the memory so the substitution is valid even if there
1006 are intervening stores. Also, don't move a volatile asm or
1007 UNSPEC_VOLATILE across any other insns. */
1009 && (((GET_CODE (src) != MEM
1010 || ! find_reg_note (insn, REG_EQUIV, src))
1011 && use_crosses_set_p (src, INSN_CUID (insn)))
1012 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1013 || GET_CODE (src) == UNSPEC_VOLATILE))
1014 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1015 better register allocation by not doing the combine. */
1016 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1017 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1018 /* Don't combine across a CALL_INSN, because that would possibly
1019 change whether the life span of some REGs crosses calls or not,
1020 and it is a pain to update that information.
1021 Exception: if source is a constant, moving it later can't hurt.
1022 Accept that special case, because it helps -fforce-addr a lot. */
1023 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1026 /* DEST must either be a REG or CC0. */
1027 if (GET_CODE (dest) == REG)
1029 /* If register alignment is being enforced for multi-word items in all
1030 cases except for parameters, it is possible to have a register copy
1031 insn referencing a hard register that is not allowed to contain the
1032 mode being copied and which would not be valid as an operand of most
1033 insns. Eliminate this problem by not combining with such an insn.
1035 Also, on some machines we don't want to extend the life of a hard
1038 This is the same test done in can_combine except that we don't test
1039 if SRC is a CALL operation to permit a hard register with
1040 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1043 if (GET_CODE (src) == REG
1044 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1045 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1046 /* Don't extend the life of a hard register unless it is
1047 user variable (if we have few registers) or it can't
1048 fit into the desired register (meaning something special
1050 Also avoid substituting a return register into I3, because
1051 reload can't handle a conflict with constraints of other
1053 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1054 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1055 || (SMALL_REGISTER_CLASSES
1056 && ((! all_adjacent && ! REG_USERVAR_P (src))
1057 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1058 && ! REG_USERVAR_P (src))))))))
1061 else if (GET_CODE (dest) != CC0)
1064 /* Don't substitute for a register intended as a clobberable operand.
1065 Similarly, don't substitute an expression containing a register that
1066 will be clobbered in I3. */
1067 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1068 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1069 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1070 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1072 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1075 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1076 or not), reject, unless nothing volatile comes between it and I3 */
1078 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1080 /* Make sure succ doesn't contain a volatile reference. */
1081 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1084 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1085 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1086 && p != succ && volatile_refs_p (PATTERN (p)))
1090 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1091 to be an explicit register variable, and was chosen for a reason. */
1093 if (GET_CODE (src) == ASM_OPERANDS
1094 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1097 /* If there are any volatile insns between INSN and I3, reject, because
1098 they might affect machine state. */
1100 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1101 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1102 && p != succ && volatile_insn_p (PATTERN (p)))
1105 /* If INSN or I2 contains an autoincrement or autodecrement,
1106 make sure that register is not used between there and I3,
1107 and not already used in I3 either.
1108 Also insist that I3 not be a jump; if it were one
1109 and the incremented register were spilled, we would lose. */
1112 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1113 if (REG_NOTE_KIND (link) == REG_INC
1114 && (GET_CODE (i3) == JUMP_INSN
1115 || reg_used_between_p (XEXP (link, 0), insn, i3)
1116 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1121 /* Don't combine an insn that follows a CC0-setting insn.
1122 An insn that uses CC0 must not be separated from the one that sets it.
1123 We do, however, allow I2 to follow a CC0-setting insn if that insn
1124 is passed as I1; in that case it will be deleted also.
1125 We also allow combining in this case if all the insns are adjacent
1126 because that would leave the two CC0 insns adjacent as well.
1127 It would be more logical to test whether CC0 occurs inside I1 or I2,
1128 but that would be much slower, and this ought to be equivalent. */
1130 p = prev_nonnote_insn (insn);
1131 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1136 /* If we get here, we have passed all the tests and the combination is
1145 /* Check if PAT is an insn - or a part of it - used to set up an
1146 argument for a function in a hard register. */
1149 sets_function_arg_p (pat)
1155 switch (GET_CODE (pat))
1158 return sets_function_arg_p (PATTERN (pat));
1161 for (i = XVECLEN (pat, 0); --i >= 0;)
1162 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1168 inner_dest = SET_DEST (pat);
1169 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1170 || GET_CODE (inner_dest) == SUBREG
1171 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1172 inner_dest = XEXP (inner_dest, 0);
1174 return (GET_CODE (inner_dest) == REG
1175 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1176 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1185 /* LOC is the location within I3 that contains its pattern or the component
1186 of a PARALLEL of the pattern. We validate that it is valid for combining.
1188 One problem is if I3 modifies its output, as opposed to replacing it
1189 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1190 so would produce an insn that is not equivalent to the original insns.
1194 (set (reg:DI 101) (reg:DI 100))
1195 (set (subreg:SI (reg:DI 101) 0) <foo>)
1197 This is NOT equivalent to:
1199 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1200 (set (reg:DI 101) (reg:DI 100))])
1202 Not only does this modify 100 (in which case it might still be valid
1203 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1205 We can also run into a problem if I2 sets a register that I1
1206 uses and I1 gets directly substituted into I3 (not via I2). In that
1207 case, we would be getting the wrong value of I2DEST into I3, so we
1208 must reject the combination. This case occurs when I2 and I1 both
1209 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1210 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1211 of a SET must prevent combination from occurring.
1213 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1214 if the destination of a SET is a hard register that isn't a user
1217 Before doing the above check, we first try to expand a field assignment
1218 into a set of logical operations.
1220 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1221 we place a register that is both set and used within I3. If more than one
1222 such register is detected, we fail.
1224 Return 1 if the combination is valid, zero otherwise. */
1227 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1233 rtx *pi3dest_killed;
1237 if (GET_CODE (x) == SET)
1239 rtx set = expand_field_assignment (x);
1240 rtx dest = SET_DEST (set);
1241 rtx src = SET_SRC (set);
1242 rtx inner_dest = dest;
1245 rtx inner_src = src;
1250 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1251 || GET_CODE (inner_dest) == SUBREG
1252 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1253 inner_dest = XEXP (inner_dest, 0);
1255 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1258 while (GET_CODE (inner_src) == STRICT_LOW_PART
1259 || GET_CODE (inner_src) == SUBREG
1260 || GET_CODE (inner_src) == ZERO_EXTRACT)
1261 inner_src = XEXP (inner_src, 0);
1263 /* If it is better that two different modes keep two different pseudos,
1264 avoid combining them. This avoids producing the following pattern
1266 (set (subreg:SI (reg/v:QI 21) 0)
1267 (lshiftrt:SI (reg/v:SI 20)
1269 If that were made, reload could not handle the pair of
1270 reg 20/21, since it would try to get any GENERAL_REGS
1271 but some of them don't handle QImode. */
1273 if (rtx_equal_p (inner_src, i2dest)
1274 && GET_CODE (inner_dest) == REG
1275 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1279 /* Check for the case where I3 modifies its output, as
1281 if ((inner_dest != dest
1282 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1283 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1285 /* This is the same test done in can_combine_p except that we
1286 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1287 CALL operation. Moreover, we can't test all_adjacent; we don't
1288 have to, since this instruction will stay in place, thus we are
1289 not considering increasing the lifetime of INNER_DEST.
1291 Also, if this insn sets a function argument, combining it with
1292 something that might need a spill could clobber a previous
1293 function argument; the all_adjacent test in can_combine_p also
1294 checks this; here, we do a more specific test for this case. */
1296 || (GET_CODE (inner_dest) == REG
1297 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1298 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1299 GET_MODE (inner_dest))
1300 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1301 && ! REG_USERVAR_P (inner_dest)
1302 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1303 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1305 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1306 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1309 /* If DEST is used in I3, it is being killed in this insn,
1310 so record that for later.
1311 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1312 STACK_POINTER_REGNUM, since these are always considered to be
1313 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1314 if (pi3dest_killed && GET_CODE (dest) == REG
1315 && reg_referenced_p (dest, PATTERN (i3))
1316 && REGNO (dest) != FRAME_POINTER_REGNUM
1317 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1318 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1320 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1321 && (REGNO (dest) != ARG_POINTER_REGNUM
1322 || ! fixed_regs [REGNO (dest)])
1324 && REGNO (dest) != STACK_POINTER_REGNUM)
1326 if (*pi3dest_killed)
1329 *pi3dest_killed = dest;
1333 else if (GET_CODE (x) == PARALLEL)
1337 for (i = 0; i < XVECLEN (x, 0); i++)
1338 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1339 i1_not_in_src, pi3dest_killed))
1346 /* Try to combine the insns I1 and I2 into I3.
1347 Here I1 and I2 appear earlier than I3.
1348 I1 can be zero; then we combine just I2 into I3.
1350 It we are combining three insns and the resulting insn is not recognized,
1351 try splitting it into two insns. If that happens, I2 and I3 are retained
1352 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1355 Return 0 if the combination does not work. Then nothing is changed.
1356 If we did the combination, return the insn at which combine should
1360 try_combine (i3, i2, i1)
1361 register rtx i3, i2, i1;
1363 /* New patterns for I3 and I3, respectively. */
1364 rtx newpat, newi2pat = 0;
1365 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1366 int added_sets_1, added_sets_2;
1367 /* Total number of SETs to put into I3. */
1369 /* Nonzero is I2's body now appears in I3. */
1371 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1372 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1373 /* Contains I3 if the destination of I3 is used in its source, which means
1374 that the old life of I3 is being killed. If that usage is placed into
1375 I2 and not in I3, a REG_DEAD note must be made. */
1376 rtx i3dest_killed = 0;
1377 /* SET_DEST and SET_SRC of I2 and I1. */
1378 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1379 /* PATTERN (I2), or a copy of it in certain cases. */
1381 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1382 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1383 int i1_feeds_i3 = 0;
1384 /* Notes that must be added to REG_NOTES in I3 and I2. */
1385 rtx new_i3_notes, new_i2_notes;
1386 /* Notes that we substituted I3 into I2 instead of the normal case. */
1387 int i3_subst_into_i2 = 0;
1388 /* Notes that I1, I2 or I3 is a MULT operation. */
1396 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1397 This can occur when flow deletes an insn that it has merged into an
1398 auto-increment address. We also can't do anything if I3 has a
1399 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1402 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1403 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1404 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1406 /* ??? This gives worse code, and appears to be unnecessary, since no
1407 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1408 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1415 undobuf.undos = undobuf.previous_undos = 0;
1416 undobuf.other_insn = 0;
1418 /* Save the current high-water-mark so we can free storage if we didn't
1419 accept this combination. */
1420 undobuf.storage = (char *) oballoc (0);
1422 /* Reset the hard register usage information. */
1423 CLEAR_HARD_REG_SET (newpat_used_regs);
1425 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1426 code below, set I1 to be the earlier of the two insns. */
1427 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1428 temp = i1, i1 = i2, i2 = temp;
1430 added_links_insn = 0;
1432 /* First check for one important special-case that the code below will
1433 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1434 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1435 we may be able to replace that destination with the destination of I3.
1436 This occurs in the common code where we compute both a quotient and
1437 remainder into a structure, in which case we want to do the computation
1438 directly into the structure to avoid register-register copies.
1440 We make very conservative checks below and only try to handle the
1441 most common cases of this. For example, we only handle the case
1442 where I2 and I3 are adjacent to avoid making difficult register
1445 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1446 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1447 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1448 && (! SMALL_REGISTER_CLASSES
1449 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1450 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1451 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1452 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1453 && GET_CODE (PATTERN (i2)) == PARALLEL
1454 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1455 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1456 below would need to check what is inside (and reg_overlap_mentioned_p
1457 doesn't support those codes anyway). Don't allow those destinations;
1458 the resulting insn isn't likely to be recognized anyway. */
1459 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1460 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1461 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1462 SET_DEST (PATTERN (i3)))
1463 && next_real_insn (i2) == i3)
1465 rtx p2 = PATTERN (i2);
1467 /* Make sure that the destination of I3,
1468 which we are going to substitute into one output of I2,
1469 is not used within another output of I2. We must avoid making this:
1470 (parallel [(set (mem (reg 69)) ...)
1471 (set (reg 69) ...)])
1472 which is not well-defined as to order of actions.
1473 (Besides, reload can't handle output reloads for this.)
1475 The problem can also happen if the dest of I3 is a memory ref,
1476 if another dest in I2 is an indirect memory ref. */
1477 for (i = 0; i < XVECLEN (p2, 0); i++)
1478 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1479 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1480 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1481 SET_DEST (XVECEXP (p2, 0, i))))
1484 if (i == XVECLEN (p2, 0))
1485 for (i = 0; i < XVECLEN (p2, 0); i++)
1486 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1491 subst_low_cuid = INSN_CUID (i2);
1493 added_sets_2 = added_sets_1 = 0;
1494 i2dest = SET_SRC (PATTERN (i3));
1496 /* Replace the dest in I2 with our dest and make the resulting
1497 insn the new pattern for I3. Then skip to where we
1498 validate the pattern. Everything was set up above. */
1499 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1500 SET_DEST (PATTERN (i3)));
1503 i3_subst_into_i2 = 1;
1504 goto validate_replacement;
1509 /* If we have no I1 and I2 looks like:
1510 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1512 make up a dummy I1 that is
1515 (set (reg:CC X) (compare:CC Y (const_int 0)))
1517 (We can ignore any trailing CLOBBERs.)
1519 This undoes a previous combination and allows us to match a branch-and-
1522 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1523 && XVECLEN (PATTERN (i2), 0) >= 2
1524 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1525 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1527 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1528 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1529 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1530 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1531 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1532 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1534 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1535 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1540 /* We make I1 with the same INSN_UID as I2. This gives it
1541 the same INSN_CUID for value tracking. Our fake I1 will
1542 never appear in the insn stream so giving it the same INSN_UID
1543 as I2 will not cause a problem. */
1545 subst_prev_insn = i1
1546 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1547 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1550 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1551 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1552 SET_DEST (PATTERN (i1)));
1557 /* Verify that I2 and I1 are valid for combining. */
1558 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1559 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1565 /* Record whether I2DEST is used in I2SRC and similarly for the other
1566 cases. Knowing this will help in register status updating below. */
1567 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1568 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1569 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1571 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1573 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1575 /* Ensure that I3's pattern can be the destination of combines. */
1576 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1577 i1 && i2dest_in_i1src && i1_feeds_i3,
1584 /* See if any of the insns is a MULT operation. Unless one is, we will
1585 reject a combination that is, since it must be slower. Be conservative
1587 if (GET_CODE (i2src) == MULT
1588 || (i1 != 0 && GET_CODE (i1src) == MULT)
1589 || (GET_CODE (PATTERN (i3)) == SET
1590 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1593 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1594 We used to do this EXCEPT in one case: I3 has a post-inc in an
1595 output operand. However, that exception can give rise to insns like
1597 which is a famous insn on the PDP-11 where the value of r3 used as the
1598 source was model-dependent. Avoid this sort of thing. */
1601 if (!(GET_CODE (PATTERN (i3)) == SET
1602 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1603 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1604 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1605 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1606 /* It's not the exception. */
1609 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1610 if (REG_NOTE_KIND (link) == REG_INC
1611 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1613 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1620 /* See if the SETs in I1 or I2 need to be kept around in the merged
1621 instruction: whenever the value set there is still needed past I3.
1622 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1624 For the SET in I1, we have two cases: If I1 and I2 independently
1625 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1626 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1627 in I1 needs to be kept around unless I1DEST dies or is set in either
1628 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1629 I1DEST. If so, we know I1 feeds into I2. */
1631 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1634 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1635 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1637 /* If the set in I2 needs to be kept around, we must make a copy of
1638 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1639 PATTERN (I2), we are only substituting for the original I1DEST, not into
1640 an already-substituted copy. This also prevents making self-referential
1641 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1644 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1645 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1649 i2pat = copy_rtx (i2pat);
1653 /* Substitute in the latest insn for the regs set by the earlier ones. */
1655 maxreg = max_reg_num ();
1659 /* It is possible that the source of I2 or I1 may be performing an
1660 unneeded operation, such as a ZERO_EXTEND of something that is known
1661 to have the high part zero. Handle that case by letting subst look at
1662 the innermost one of them.
1664 Another way to do this would be to have a function that tries to
1665 simplify a single insn instead of merging two or more insns. We don't
1666 do this because of the potential of infinite loops and because
1667 of the potential extra memory required. However, doing it the way
1668 we are is a bit of a kludge and doesn't catch all cases.
1670 But only do this if -fexpensive-optimizations since it slows things down
1671 and doesn't usually win. */
1673 if (flag_expensive_optimizations)
1675 /* Pass pc_rtx so no substitutions are done, just simplifications.
1676 The cases that we are interested in here do not involve the few
1677 cases were is_replaced is checked. */
1680 subst_low_cuid = INSN_CUID (i1);
1681 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1685 subst_low_cuid = INSN_CUID (i2);
1686 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1689 undobuf.previous_undos = undobuf.undos;
1693 /* Many machines that don't use CC0 have insns that can both perform an
1694 arithmetic operation and set the condition code. These operations will
1695 be represented as a PARALLEL with the first element of the vector
1696 being a COMPARE of an arithmetic operation with the constant zero.
1697 The second element of the vector will set some pseudo to the result
1698 of the same arithmetic operation. If we simplify the COMPARE, we won't
1699 match such a pattern and so will generate an extra insn. Here we test
1700 for this case, where both the comparison and the operation result are
1701 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1702 I2SRC. Later we will make the PARALLEL that contains I2. */
1704 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1705 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1706 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1707 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1709 #ifdef EXTRA_CC_MODES
1711 enum machine_mode compare_mode;
1714 newpat = PATTERN (i3);
1715 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1719 #ifdef EXTRA_CC_MODES
1720 /* See if a COMPARE with the operand we substituted in should be done
1721 with the mode that is currently being used. If not, do the same
1722 processing we do in `subst' for a SET; namely, if the destination
1723 is used only once, try to replace it with a register of the proper
1724 mode and also replace the COMPARE. */
1725 if (undobuf.other_insn == 0
1726 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1727 &undobuf.other_insn))
1728 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1730 != GET_MODE (SET_DEST (newpat))))
1732 int regno = REGNO (SET_DEST (newpat));
1733 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1735 if (regno < FIRST_PSEUDO_REGISTER
1736 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1737 && ! REG_USERVAR_P (SET_DEST (newpat))))
1739 if (regno >= FIRST_PSEUDO_REGISTER)
1740 SUBST (regno_reg_rtx[regno], new_dest);
1742 SUBST (SET_DEST (newpat), new_dest);
1743 SUBST (XEXP (*cc_use, 0), new_dest);
1744 SUBST (SET_SRC (newpat),
1745 gen_rtx_combine (COMPARE, compare_mode,
1746 i2src, const0_rtx));
1749 undobuf.other_insn = 0;
1756 n_occurrences = 0; /* `subst' counts here */
1758 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1759 need to make a unique copy of I2SRC each time we substitute it
1760 to avoid self-referential rtl. */
1762 subst_low_cuid = INSN_CUID (i2);
1763 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1764 ! i1_feeds_i3 && i1dest_in_i1src);
1765 undobuf.previous_undos = undobuf.undos;
1767 /* Record whether i2's body now appears within i3's body. */
1768 i2_is_used = n_occurrences;
1771 /* If we already got a failure, don't try to do more. Otherwise,
1772 try to substitute in I1 if we have it. */
1774 if (i1 && GET_CODE (newpat) != CLOBBER)
1776 /* Before we can do this substitution, we must redo the test done
1777 above (see detailed comments there) that ensures that I1DEST
1778 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1780 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1788 subst_low_cuid = INSN_CUID (i1);
1789 newpat = subst (newpat, i1dest, i1src, 0, 0);
1790 undobuf.previous_undos = undobuf.undos;
1793 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1794 to count all the ways that I2SRC and I1SRC can be used. */
1795 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1796 && i2_is_used + added_sets_2 > 1)
1797 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1798 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1800 /* Fail if we tried to make a new register (we used to abort, but there's
1801 really no reason to). */
1802 || max_reg_num () != maxreg
1803 /* Fail if we couldn't do something and have a CLOBBER. */
1804 || GET_CODE (newpat) == CLOBBER
1805 /* Fail if this new pattern is a MULT and we didn't have one before
1806 at the outer level. */
1807 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1814 /* If the actions of the earlier insns must be kept
1815 in addition to substituting them into the latest one,
1816 we must make a new PARALLEL for the latest insn
1817 to hold additional the SETs. */
1819 if (added_sets_1 || added_sets_2)
1823 if (GET_CODE (newpat) == PARALLEL)
1825 rtvec old = XVEC (newpat, 0);
1826 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1827 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1828 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1829 sizeof (old->elem[0]) * old->num_elem);
1834 total_sets = 1 + added_sets_1 + added_sets_2;
1835 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1836 XVECEXP (newpat, 0, 0) = old;
1840 XVECEXP (newpat, 0, --total_sets)
1841 = (GET_CODE (PATTERN (i1)) == PARALLEL
1842 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1846 /* If there is no I1, use I2's body as is. We used to also not do
1847 the subst call below if I2 was substituted into I3,
1848 but that could lose a simplification. */
1850 XVECEXP (newpat, 0, --total_sets) = i2pat;
1852 /* See comment where i2pat is assigned. */
1853 XVECEXP (newpat, 0, --total_sets)
1854 = subst (i2pat, i1dest, i1src, 0, 0);
1858 /* We come here when we are replacing a destination in I2 with the
1859 destination of I3. */
1860 validate_replacement:
1862 /* Note which hard regs this insn has as inputs. */
1863 mark_used_regs_combine (newpat);
1865 /* Is the result of combination a valid instruction? */
1866 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1868 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1869 the second SET's destination is a register that is unused. In that case,
1870 we just need the first SET. This can occur when simplifying a divmod
1871 insn. We *must* test for this case here because the code below that
1872 splits two independent SETs doesn't handle this case correctly when it
1873 updates the register status. Also check the case where the first
1874 SET's destination is unused. That would not cause incorrect code, but
1875 does cause an unneeded insn to remain. */
1877 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1878 && XVECLEN (newpat, 0) == 2
1879 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1880 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1881 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1882 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1883 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1884 && asm_noperands (newpat) < 0)
1886 newpat = XVECEXP (newpat, 0, 0);
1887 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1890 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1891 && XVECLEN (newpat, 0) == 2
1892 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1893 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1894 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1895 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1896 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1897 && asm_noperands (newpat) < 0)
1899 newpat = XVECEXP (newpat, 0, 1);
1900 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1903 /* If we were combining three insns and the result is a simple SET
1904 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1905 insns. There are two ways to do this. It can be split using a
1906 machine-specific method (like when you have an addition of a large
1907 constant) or by combine in the function find_split_point. */
1909 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1910 && asm_noperands (newpat) < 0)
1912 rtx m_split, *split;
1913 rtx ni2dest = i2dest;
1915 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1916 use I2DEST as a scratch register will help. In the latter case,
1917 convert I2DEST to the mode of the source of NEWPAT if we can. */
1919 m_split = split_insns (newpat, i3);
1921 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1922 inputs of NEWPAT. */
1924 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1925 possible to try that as a scratch reg. This would require adding
1926 more code to make it work though. */
1928 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1930 /* If I2DEST is a hard register or the only use of a pseudo,
1931 we can change its mode. */
1932 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1933 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1934 && GET_CODE (i2dest) == REG
1935 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1936 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1937 && ! REG_USERVAR_P (i2dest))))
1938 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1941 m_split = split_insns (gen_rtx_PARALLEL
1943 gen_rtvec (2, newpat,
1944 gen_rtx_CLOBBER (VOIDmode,
1949 if (m_split && GET_CODE (m_split) == SEQUENCE
1950 && XVECLEN (m_split, 0) == 2
1951 && (next_real_insn (i2) == i3
1952 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1956 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1957 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1959 i3set = single_set (XVECEXP (m_split, 0, 1));
1960 i2set = single_set (XVECEXP (m_split, 0, 0));
1962 /* In case we changed the mode of I2DEST, replace it in the
1963 pseudo-register table here. We can't do it above in case this
1964 code doesn't get executed and we do a split the other way. */
1966 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1967 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1969 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1971 /* If I2 or I3 has multiple SETs, we won't know how to track
1972 register status, so don't use these insns. If I2's destination
1973 is used between I2 and I3, we also can't use these insns. */
1975 if (i2_code_number >= 0 && i2set && i3set
1976 && (next_real_insn (i2) == i3
1977 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1978 insn_code_number = recog_for_combine (&newi3pat, i3,
1980 if (insn_code_number >= 0)
1983 /* It is possible that both insns now set the destination of I3.
1984 If so, we must show an extra use of it. */
1986 if (insn_code_number >= 0)
1988 rtx new_i3_dest = SET_DEST (i3set);
1989 rtx new_i2_dest = SET_DEST (i2set);
1991 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1992 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1993 || GET_CODE (new_i3_dest) == SUBREG)
1994 new_i3_dest = XEXP (new_i3_dest, 0);
1996 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1997 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1998 || GET_CODE (new_i2_dest) == SUBREG)
1999 new_i2_dest = XEXP (new_i2_dest, 0);
2001 if (GET_CODE (new_i3_dest) == REG
2002 && GET_CODE (new_i2_dest) == REG
2003 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2004 REG_N_SETS (REGNO (new_i2_dest))++;
2008 /* If we can split it and use I2DEST, go ahead and see if that
2009 helps things be recognized. Verify that none of the registers
2010 are set between I2 and I3. */
2011 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2013 && GET_CODE (i2dest) == REG
2015 /* We need I2DEST in the proper mode. If it is a hard register
2016 or the only use of a pseudo, we can change its mode. */
2017 && (GET_MODE (*split) == GET_MODE (i2dest)
2018 || GET_MODE (*split) == VOIDmode
2019 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2020 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2021 && ! REG_USERVAR_P (i2dest)))
2022 && (next_real_insn (i2) == i3
2023 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2024 /* We can't overwrite I2DEST if its value is still used by
2026 && ! reg_referenced_p (i2dest, newpat))
2028 rtx newdest = i2dest;
2029 enum rtx_code split_code = GET_CODE (*split);
2030 enum machine_mode split_mode = GET_MODE (*split);
2032 /* Get NEWDEST as a register in the proper mode. We have already
2033 validated that we can do this. */
2034 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2036 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2038 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2039 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2042 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2043 an ASHIFT. This can occur if it was inside a PLUS and hence
2044 appeared to be a memory address. This is a kludge. */
2045 if (split_code == MULT
2046 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2047 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2049 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2050 XEXP (*split, 0), GEN_INT (i)));
2051 /* Update split_code because we may not have a multiply
2053 split_code = GET_CODE (*split);
2056 #ifdef INSN_SCHEDULING
2057 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2058 be written as a ZERO_EXTEND. */
2059 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2060 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2064 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2065 SUBST (*split, newdest);
2066 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2068 /* If the split point was a MULT and we didn't have one before,
2069 don't use one now. */
2070 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2071 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2075 /* Check for a case where we loaded from memory in a narrow mode and
2076 then sign extended it, but we need both registers. In that case,
2077 we have a PARALLEL with both loads from the same memory location.
2078 We can split this into a load from memory followed by a register-register
2079 copy. This saves at least one insn, more if register allocation can
2082 We cannot do this if the destination of the second assignment is
2083 a register that we have already assumed is zero-extended. Similarly
2084 for a SUBREG of such a register. */
2086 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2087 && GET_CODE (newpat) == PARALLEL
2088 && XVECLEN (newpat, 0) == 2
2089 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2090 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2091 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2092 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2093 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2094 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2096 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2097 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2098 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2099 (GET_CODE (temp) == REG
2100 && reg_nonzero_bits[REGNO (temp)] != 0
2101 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2102 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2103 && (reg_nonzero_bits[REGNO (temp)]
2104 != GET_MODE_MASK (word_mode))))
2105 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2106 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2107 (GET_CODE (temp) == REG
2108 && reg_nonzero_bits[REGNO (temp)] != 0
2109 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2110 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2111 && (reg_nonzero_bits[REGNO (temp)]
2112 != GET_MODE_MASK (word_mode)))))
2113 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2114 SET_SRC (XVECEXP (newpat, 0, 1)))
2115 && ! find_reg_note (i3, REG_UNUSED,
2116 SET_DEST (XVECEXP (newpat, 0, 0))))
2120 newi2pat = XVECEXP (newpat, 0, 0);
2121 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2122 newpat = XVECEXP (newpat, 0, 1);
2123 SUBST (SET_SRC (newpat),
2124 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2125 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2127 if (i2_code_number >= 0)
2128 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2130 if (insn_code_number >= 0)
2135 /* If we will be able to accept this, we have made a change to the
2136 destination of I3. This can invalidate a LOG_LINKS pointing
2137 to I3. No other part of combine.c makes such a transformation.
2139 The new I3 will have a destination that was previously the
2140 destination of I1 or I2 and which was used in i2 or I3. Call
2141 distribute_links to make a LOG_LINK from the next use of
2142 that destination. */
2144 PATTERN (i3) = newpat;
2145 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2147 /* I3 now uses what used to be its destination and which is
2148 now I2's destination. That means we need a LOG_LINK from
2149 I3 to I2. But we used to have one, so we still will.
2151 However, some later insn might be using I2's dest and have
2152 a LOG_LINK pointing at I3. We must remove this link.
2153 The simplest way to remove the link is to point it at I1,
2154 which we know will be a NOTE. */
2156 for (insn = NEXT_INSN (i3);
2157 insn && (this_basic_block == n_basic_blocks - 1
2158 || insn != BLOCK_HEAD (this_basic_block + 1));
2159 insn = NEXT_INSN (insn))
2161 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2162 && reg_referenced_p (ni2dest, PATTERN (insn)))
2164 for (link = LOG_LINKS (insn); link;
2165 link = XEXP (link, 1))
2166 if (XEXP (link, 0) == i3)
2167 XEXP (link, 0) = i1;
2175 /* Similarly, check for a case where we have a PARALLEL of two independent
2176 SETs but we started with three insns. In this case, we can do the sets
2177 as two separate insns. This case occurs when some SET allows two
2178 other insns to combine, but the destination of that SET is still live. */
2180 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2181 && GET_CODE (newpat) == PARALLEL
2182 && XVECLEN (newpat, 0) == 2
2183 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2184 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2185 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2186 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2187 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2188 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2189 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2191 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2192 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2193 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2194 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2195 XVECEXP (newpat, 0, 0))
2196 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2197 XVECEXP (newpat, 0, 1)))
2199 /* Normally, it doesn't matter which of the two is done first,
2200 but it does if one references cc0. In that case, it has to
2203 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2205 newi2pat = XVECEXP (newpat, 0, 0);
2206 newpat = XVECEXP (newpat, 0, 1);
2211 newi2pat = XVECEXP (newpat, 0, 1);
2212 newpat = XVECEXP (newpat, 0, 0);
2215 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2217 if (i2_code_number >= 0)
2218 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2221 /* If it still isn't recognized, fail and change things back the way they
2223 if ((insn_code_number < 0
2224 /* Is the result a reasonable ASM_OPERANDS? */
2225 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2231 /* If we had to change another insn, make sure it is valid also. */
2232 if (undobuf.other_insn)
2234 rtx other_pat = PATTERN (undobuf.other_insn);
2235 rtx new_other_notes;
2238 CLEAR_HARD_REG_SET (newpat_used_regs);
2240 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2243 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2249 PATTERN (undobuf.other_insn) = other_pat;
2251 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2252 are still valid. Then add any non-duplicate notes added by
2253 recog_for_combine. */
2254 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2256 next = XEXP (note, 1);
2258 if (REG_NOTE_KIND (note) == REG_UNUSED
2259 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2261 if (GET_CODE (XEXP (note, 0)) == REG)
2262 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2264 remove_note (undobuf.other_insn, note);
2268 for (note = new_other_notes; note; note = XEXP (note, 1))
2269 if (GET_CODE (XEXP (note, 0)) == REG)
2270 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2272 distribute_notes (new_other_notes, undobuf.other_insn,
2273 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2276 /* We now know that we can do this combination. Merge the insns and
2277 update the status of registers and LOG_LINKS. */
2280 rtx i3notes, i2notes, i1notes = 0;
2281 rtx i3links, i2links, i1links = 0;
2284 /* Compute which registers we expect to eliminate. newi2pat may be setting
2285 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2286 same as i3dest, in which case newi2pat may be setting i1dest. */
2287 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2288 || i2dest_in_i2src || i2dest_in_i1src
2290 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2291 || (newi2pat && reg_set_p (i1dest, newi2pat))
2294 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2296 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2297 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2299 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2301 /* Ensure that we do not have something that should not be shared but
2302 occurs multiple times in the new insns. Check this by first
2303 resetting all the `used' flags and then copying anything is shared. */
2305 reset_used_flags (i3notes);
2306 reset_used_flags (i2notes);
2307 reset_used_flags (i1notes);
2308 reset_used_flags (newpat);
2309 reset_used_flags (newi2pat);
2310 if (undobuf.other_insn)
2311 reset_used_flags (PATTERN (undobuf.other_insn));
2313 i3notes = copy_rtx_if_shared (i3notes);
2314 i2notes = copy_rtx_if_shared (i2notes);
2315 i1notes = copy_rtx_if_shared (i1notes);
2316 newpat = copy_rtx_if_shared (newpat);
2317 newi2pat = copy_rtx_if_shared (newi2pat);
2318 if (undobuf.other_insn)
2319 reset_used_flags (PATTERN (undobuf.other_insn));
2321 INSN_CODE (i3) = insn_code_number;
2322 PATTERN (i3) = newpat;
2323 if (undobuf.other_insn)
2324 INSN_CODE (undobuf.other_insn) = other_code_number;
2326 /* We had one special case above where I2 had more than one set and
2327 we replaced a destination of one of those sets with the destination
2328 of I3. In that case, we have to update LOG_LINKS of insns later
2329 in this basic block. Note that this (expensive) case is rare.
2331 Also, in this case, we must pretend that all REG_NOTEs for I2
2332 actually came from I3, so that REG_UNUSED notes from I2 will be
2333 properly handled. */
2335 if (i3_subst_into_i2)
2337 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2338 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2339 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2340 && ! find_reg_note (i2, REG_UNUSED,
2341 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2342 for (temp = NEXT_INSN (i2);
2343 temp && (this_basic_block == n_basic_blocks - 1
2344 || BLOCK_HEAD (this_basic_block) != temp);
2345 temp = NEXT_INSN (temp))
2346 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2347 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2348 if (XEXP (link, 0) == i2)
2349 XEXP (link, 0) = i3;
2354 while (XEXP (link, 1))
2355 link = XEXP (link, 1);
2356 XEXP (link, 1) = i2notes;
2370 INSN_CODE (i2) = i2_code_number;
2371 PATTERN (i2) = newi2pat;
2375 PUT_CODE (i2, NOTE);
2376 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2377 NOTE_SOURCE_FILE (i2) = 0;
2384 PUT_CODE (i1, NOTE);
2385 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2386 NOTE_SOURCE_FILE (i1) = 0;
2389 /* Get death notes for everything that is now used in either I3 or
2390 I2 and used to die in a previous insn. If we built two new
2391 patterns, move from I1 to I2 then I2 to I3 so that we get the
2392 proper movement on registers that I2 modifies. */
2396 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2397 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2400 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2403 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2405 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2408 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2411 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2414 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2417 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2418 know these are REG_UNUSED and want them to go to the desired insn,
2419 so we always pass it as i3. We have not counted the notes in
2420 reg_n_deaths yet, so we need to do so now. */
2422 if (newi2pat && new_i2_notes)
2424 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2425 if (GET_CODE (XEXP (temp, 0)) == REG)
2426 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2428 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2433 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2434 if (GET_CODE (XEXP (temp, 0)) == REG)
2435 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2437 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2440 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2441 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2442 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2443 in that case, it might delete I2. Similarly for I2 and I1.
2444 Show an additional death due to the REG_DEAD note we make here. If
2445 we discard it in distribute_notes, we will decrement it again. */
2449 if (GET_CODE (i3dest_killed) == REG)
2450 REG_N_DEATHS (REGNO (i3dest_killed))++;
2452 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2453 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2455 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2457 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2459 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2463 if (i2dest_in_i2src)
2465 if (GET_CODE (i2dest) == REG)
2466 REG_N_DEATHS (REGNO (i2dest))++;
2468 if (newi2pat && reg_set_p (i2dest, newi2pat))
2469 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2470 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2472 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2473 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2474 NULL_RTX, NULL_RTX);
2477 if (i1dest_in_i1src)
2479 if (GET_CODE (i1dest) == REG)
2480 REG_N_DEATHS (REGNO (i1dest))++;
2482 if (newi2pat && reg_set_p (i1dest, newi2pat))
2483 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2484 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2486 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2487 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2488 NULL_RTX, NULL_RTX);
2491 distribute_links (i3links);
2492 distribute_links (i2links);
2493 distribute_links (i1links);
2495 if (GET_CODE (i2dest) == REG)
2498 rtx i2_insn = 0, i2_val = 0, set;
2500 /* The insn that used to set this register doesn't exist, and
2501 this life of the register may not exist either. See if one of
2502 I3's links points to an insn that sets I2DEST. If it does,
2503 that is now the last known value for I2DEST. If we don't update
2504 this and I2 set the register to a value that depended on its old
2505 contents, we will get confused. If this insn is used, thing
2506 will be set correctly in combine_instructions. */
2508 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2509 if ((set = single_set (XEXP (link, 0))) != 0
2510 && rtx_equal_p (i2dest, SET_DEST (set)))
2511 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2513 record_value_for_reg (i2dest, i2_insn, i2_val);
2515 /* If the reg formerly set in I2 died only once and that was in I3,
2516 zero its use count so it won't make `reload' do any work. */
2518 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2519 && ! i2dest_in_i2src)
2521 regno = REGNO (i2dest);
2522 REG_N_SETS (regno)--;
2523 if (REG_N_SETS (regno) == 0
2524 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2526 REG_N_REFS (regno) = 0;
2530 if (i1 && GET_CODE (i1dest) == REG)
2533 rtx i1_insn = 0, i1_val = 0, set;
2535 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2536 if ((set = single_set (XEXP (link, 0))) != 0
2537 && rtx_equal_p (i1dest, SET_DEST (set)))
2538 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2540 record_value_for_reg (i1dest, i1_insn, i1_val);
2542 regno = REGNO (i1dest);
2543 if (! added_sets_1 && ! i1dest_in_i1src)
2545 REG_N_SETS (regno)--;
2546 if (REG_N_SETS (regno) == 0
2547 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2549 REG_N_REFS (regno) = 0;
2553 /* Update reg_nonzero_bits et al for any changes that may have been made
2556 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2558 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2560 /* If I3 is now an unconditional jump, ensure that it has a
2561 BARRIER following it since it may have initially been a
2562 conditional jump. It may also be the last nonnote insn. */
2564 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2565 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2566 || GET_CODE (temp) != BARRIER))
2567 emit_barrier_after (i3);
2570 combine_successes++;
2572 /* Clear this here, so that subsequent get_last_value calls are not
2574 subst_prev_insn = NULL_RTX;
2576 if (added_links_insn
2577 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2578 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2579 return added_links_insn;
2581 return newi2pat ? i2 : i3;
2584 /* Undo all the modifications recorded in undobuf. */
2589 struct undo *undo, *next;
2591 for (undo = undobuf.undos; undo; undo = next)
2595 *undo->where.i = undo->old_contents.i;
2597 *undo->where.r = undo->old_contents.r;
2599 undo->next = undobuf.frees;
2600 undobuf.frees = undo;
2603 obfree (undobuf.storage);
2604 undobuf.undos = undobuf.previous_undos = 0;
2606 /* Clear this here, so that subsequent get_last_value calls are not
2608 subst_prev_insn = NULL_RTX;
2611 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2612 where we have an arithmetic expression and return that point. LOC will
2615 try_combine will call this function to see if an insn can be split into
2619 find_split_point (loc, insn)
2624 enum rtx_code code = GET_CODE (x);
2626 int len = 0, pos = 0, unsignedp = 0;
2627 rtx inner = NULL_RTX;
2629 /* First special-case some codes. */
2633 #ifdef INSN_SCHEDULING
2634 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2636 if (GET_CODE (SUBREG_REG (x)) == MEM)
2639 return find_split_point (&SUBREG_REG (x), insn);
2643 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2644 using LO_SUM and HIGH. */
2645 if (GET_CODE (XEXP (x, 0)) == CONST
2646 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2649 gen_rtx_combine (LO_SUM, Pmode,
2650 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2652 return &XEXP (XEXP (x, 0), 0);
2656 /* If we have a PLUS whose second operand is a constant and the
2657 address is not valid, perhaps will can split it up using
2658 the machine-specific way to split large constants. We use
2659 the first pseudo-reg (one of the virtual regs) as a placeholder;
2660 it will not remain in the result. */
2661 if (GET_CODE (XEXP (x, 0)) == PLUS
2662 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2663 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2665 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2666 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2669 /* This should have produced two insns, each of which sets our
2670 placeholder. If the source of the second is a valid address,
2671 we can make put both sources together and make a split point
2674 if (seq && XVECLEN (seq, 0) == 2
2675 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2676 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2677 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2678 && ! reg_mentioned_p (reg,
2679 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2680 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2681 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2682 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2683 && memory_address_p (GET_MODE (x),
2684 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2686 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2687 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2689 /* Replace the placeholder in SRC2 with SRC1. If we can
2690 find where in SRC2 it was placed, that can become our
2691 split point and we can replace this address with SRC2.
2692 Just try two obvious places. */
2694 src2 = replace_rtx (src2, reg, src1);
2696 if (XEXP (src2, 0) == src1)
2697 split = &XEXP (src2, 0);
2698 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2699 && XEXP (XEXP (src2, 0), 0) == src1)
2700 split = &XEXP (XEXP (src2, 0), 0);
2704 SUBST (XEXP (x, 0), src2);
2709 /* If that didn't work, perhaps the first operand is complex and
2710 needs to be computed separately, so make a split point there.
2711 This will occur on machines that just support REG + CONST
2712 and have a constant moved through some previous computation. */
2714 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2715 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2716 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2718 return &XEXP (XEXP (x, 0), 0);
2724 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2725 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2726 we need to put the operand into a register. So split at that
2729 if (SET_DEST (x) == cc0_rtx
2730 && GET_CODE (SET_SRC (x)) != COMPARE
2731 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2732 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2733 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2734 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2735 return &SET_SRC (x);
2738 /* See if we can split SET_SRC as it stands. */
2739 split = find_split_point (&SET_SRC (x), insn);
2740 if (split && split != &SET_SRC (x))
2743 /* See if we can split SET_DEST as it stands. */
2744 split = find_split_point (&SET_DEST (x), insn);
2745 if (split && split != &SET_DEST (x))
2748 /* See if this is a bitfield assignment with everything constant. If
2749 so, this is an IOR of an AND, so split it into that. */
2750 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2751 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2752 <= HOST_BITS_PER_WIDE_INT)
2753 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2754 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2755 && GET_CODE (SET_SRC (x)) == CONST_INT
2756 && ((INTVAL (XEXP (SET_DEST (x), 1))
2757 + INTVAL (XEXP (SET_DEST (x), 2)))
2758 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2759 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2761 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2762 int len = INTVAL (XEXP (SET_DEST (x), 1));
2763 int src = INTVAL (SET_SRC (x));
2764 rtx dest = XEXP (SET_DEST (x), 0);
2765 enum machine_mode mode = GET_MODE (dest);
2766 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2768 if (BITS_BIG_ENDIAN)
2769 pos = GET_MODE_BITSIZE (mode) - len - pos;
2771 if ((unsigned HOST_WIDE_INT) src == mask)
2773 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2776 gen_binary (IOR, mode,
2777 gen_binary (AND, mode, dest,
2778 GEN_INT (~ (mask << pos)
2779 & GET_MODE_MASK (mode))),
2780 GEN_INT (src << pos)));
2782 SUBST (SET_DEST (x), dest);
2784 split = find_split_point (&SET_SRC (x), insn);
2785 if (split && split != &SET_SRC (x))
2789 /* Otherwise, see if this is an operation that we can split into two.
2790 If so, try to split that. */
2791 code = GET_CODE (SET_SRC (x));
2796 /* If we are AND'ing with a large constant that is only a single
2797 bit and the result is only being used in a context where we
2798 need to know if it is zero or non-zero, replace it with a bit
2799 extraction. This will avoid the large constant, which might
2800 have taken more than one insn to make. If the constant were
2801 not a valid argument to the AND but took only one insn to make,
2802 this is no worse, but if it took more than one insn, it will
2805 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2806 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2807 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2808 && GET_CODE (SET_DEST (x)) == REG
2809 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2810 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2811 && XEXP (*split, 0) == SET_DEST (x)
2812 && XEXP (*split, 1) == const0_rtx)
2814 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2815 XEXP (SET_SRC (x), 0),
2816 pos, NULL_RTX, 1, 1, 0, 0);
2817 if (extraction != 0)
2819 SUBST (SET_SRC (x), extraction);
2820 return find_split_point (loc, insn);
2826 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2827 is known to be on, this can be converted into a NEG of a shift. */
2828 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2829 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2830 && 1 <= (pos = exact_log2
2831 (nonzero_bits (XEXP (SET_SRC (x), 0),
2832 GET_MODE (XEXP (SET_SRC (x), 0))))))
2834 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2837 gen_rtx_combine (NEG, mode,
2838 gen_rtx_combine (LSHIFTRT, mode,
2839 XEXP (SET_SRC (x), 0),
2842 split = find_split_point (&SET_SRC (x), insn);
2843 if (split && split != &SET_SRC (x))
2849 inner = XEXP (SET_SRC (x), 0);
2851 /* We can't optimize if either mode is a partial integer
2852 mode as we don't know how many bits are significant
2854 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2855 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2859 len = GET_MODE_BITSIZE (GET_MODE (inner));
2865 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2866 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2868 inner = XEXP (SET_SRC (x), 0);
2869 len = INTVAL (XEXP (SET_SRC (x), 1));
2870 pos = INTVAL (XEXP (SET_SRC (x), 2));
2872 if (BITS_BIG_ENDIAN)
2873 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2874 unsignedp = (code == ZERO_EXTRACT);
2882 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2884 enum machine_mode mode = GET_MODE (SET_SRC (x));
2886 /* For unsigned, we have a choice of a shift followed by an
2887 AND or two shifts. Use two shifts for field sizes where the
2888 constant might be too large. We assume here that we can
2889 always at least get 8-bit constants in an AND insn, which is
2890 true for every current RISC. */
2892 if (unsignedp && len <= 8)
2897 gen_rtx_combine (LSHIFTRT, mode,
2898 gen_lowpart_for_combine (mode, inner),
2900 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2902 split = find_split_point (&SET_SRC (x), insn);
2903 if (split && split != &SET_SRC (x))
2910 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2911 gen_rtx_combine (ASHIFT, mode,
2912 gen_lowpart_for_combine (mode, inner),
2913 GEN_INT (GET_MODE_BITSIZE (mode)
2915 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2917 split = find_split_point (&SET_SRC (x), insn);
2918 if (split && split != &SET_SRC (x))
2923 /* See if this is a simple operation with a constant as the second
2924 operand. It might be that this constant is out of range and hence
2925 could be used as a split point. */
2926 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2927 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2928 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2929 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2930 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2931 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2932 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2934 return &XEXP (SET_SRC (x), 1);
2936 /* Finally, see if this is a simple operation with its first operand
2937 not in a register. The operation might require this operand in a
2938 register, so return it as a split point. We can always do this
2939 because if the first operand were another operation, we would have
2940 already found it as a split point. */
2941 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2942 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2943 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2944 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2945 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2946 return &XEXP (SET_SRC (x), 0);
2952 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2953 it is better to write this as (not (ior A B)) so we can split it.
2954 Similarly for IOR. */
2955 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2958 gen_rtx_combine (NOT, GET_MODE (x),
2959 gen_rtx_combine (code == IOR ? AND : IOR,
2961 XEXP (XEXP (x, 0), 0),
2962 XEXP (XEXP (x, 1), 0))));
2963 return find_split_point (loc, insn);
2966 /* Many RISC machines have a large set of logical insns. If the
2967 second operand is a NOT, put it first so we will try to split the
2968 other operand first. */
2969 if (GET_CODE (XEXP (x, 1)) == NOT)
2971 rtx tem = XEXP (x, 0);
2972 SUBST (XEXP (x, 0), XEXP (x, 1));
2973 SUBST (XEXP (x, 1), tem);
2981 /* Otherwise, select our actions depending on our rtx class. */
2982 switch (GET_RTX_CLASS (code))
2984 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2986 split = find_split_point (&XEXP (x, 2), insn);
2989 /* ... fall through ... */
2993 split = find_split_point (&XEXP (x, 1), insn);
2996 /* ... fall through ... */
2998 /* Some machines have (and (shift ...) ...) insns. If X is not
2999 an AND, but XEXP (X, 0) is, use it as our split point. */
3000 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3001 return &XEXP (x, 0);
3003 split = find_split_point (&XEXP (x, 0), insn);
3009 /* Otherwise, we don't have a split point. */
3013 /* Throughout X, replace FROM with TO, and return the result.
3014 The result is TO if X is FROM;
3015 otherwise the result is X, but its contents may have been modified.
3016 If they were modified, a record was made in undobuf so that
3017 undo_all will (among other things) return X to its original state.
3019 If the number of changes necessary is too much to record to undo,
3020 the excess changes are not made, so the result is invalid.
3021 The changes already made can still be undone.
3022 undobuf.num_undo is incremented for such changes, so by testing that
3023 the caller can tell whether the result is valid.
3025 `n_occurrences' is incremented each time FROM is replaced.
3027 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3029 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3030 by copying if `n_occurrences' is non-zero. */
3033 subst (x, from, to, in_dest, unique_copy)
3034 register rtx x, from, to;
3038 register enum rtx_code code = GET_CODE (x);
3039 enum machine_mode op0_mode = VOIDmode;
3040 register const char *fmt;
3041 register int len, i;
3044 /* Two expressions are equal if they are identical copies of a shared
3045 RTX or if they are both registers with the same register number
3048 #define COMBINE_RTX_EQUAL_P(X,Y) \
3050 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3051 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3053 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3056 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3059 /* If X and FROM are the same register but different modes, they will
3060 not have been seen as equal above. However, flow.c will make a
3061 LOG_LINKS entry for that case. If we do nothing, we will try to
3062 rerecognize our original insn and, when it succeeds, we will
3063 delete the feeding insn, which is incorrect.
3065 So force this insn not to match in this (rare) case. */
3066 if (! in_dest && code == REG && GET_CODE (from) == REG
3067 && REGNO (x) == REGNO (from))
3068 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3070 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3071 of which may contain things that can be combined. */
3072 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3075 /* It is possible to have a subexpression appear twice in the insn.
3076 Suppose that FROM is a register that appears within TO.
3077 Then, after that subexpression has been scanned once by `subst',
3078 the second time it is scanned, TO may be found. If we were
3079 to scan TO here, we would find FROM within it and create a
3080 self-referent rtl structure which is completely wrong. */
3081 if (COMBINE_RTX_EQUAL_P (x, to))
3084 /* Parallel asm_operands need special attention because all of the
3085 inputs are shared across the arms. Furthermore, unsharing the
3086 rtl results in recognition failures. Failure to handle this case
3087 specially can result in circular rtl.
3089 Solve this by doing a normal pass across the first entry of the
3090 parallel, and only processing the SET_DESTs of the subsequent
3093 if (code == PARALLEL
3094 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3095 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3097 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3099 /* If this substitution failed, this whole thing fails. */
3100 if (GET_CODE (new) == CLOBBER
3101 && XEXP (new, 0) == const0_rtx)
3104 SUBST (XVECEXP (x, 0, 0), new);
3106 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3108 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3110 if (GET_CODE (dest) != REG
3111 && GET_CODE (dest) != CC0
3112 && GET_CODE (dest) != PC)
3114 new = subst (dest, from, to, 0, unique_copy);
3116 /* If this substitution failed, this whole thing fails. */
3117 if (GET_CODE (new) == CLOBBER
3118 && XEXP (new, 0) == const0_rtx)
3121 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3127 len = GET_RTX_LENGTH (code);
3128 fmt = GET_RTX_FORMAT (code);
3130 /* We don't need to process a SET_DEST that is a register, CC0,
3131 or PC, so set up to skip this common case. All other cases
3132 where we want to suppress replacing something inside a
3133 SET_SRC are handled via the IN_DEST operand. */
3135 && (GET_CODE (SET_DEST (x)) == REG
3136 || GET_CODE (SET_DEST (x)) == CC0
3137 || GET_CODE (SET_DEST (x)) == PC))
3140 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3143 op0_mode = GET_MODE (XEXP (x, 0));
3145 for (i = 0; i < len; i++)
3150 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3152 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3154 new = (unique_copy && n_occurrences
3155 ? copy_rtx (to) : to);
3160 new = subst (XVECEXP (x, i, j), from, to, 0,
3163 /* If this substitution failed, this whole thing
3165 if (GET_CODE (new) == CLOBBER
3166 && XEXP (new, 0) == const0_rtx)
3170 SUBST (XVECEXP (x, i, j), new);
3173 else if (fmt[i] == 'e')
3175 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3177 /* In general, don't install a subreg involving two
3178 modes not tieable. It can worsen register
3179 allocation, and can even make invalid reload
3180 insns, since the reg inside may need to be copied
3181 from in the outside mode, and that may be invalid
3182 if it is an fp reg copied in integer mode.
3184 We allow two exceptions to this: It is valid if
3185 it is inside another SUBREG and the mode of that
3186 SUBREG and the mode of the inside of TO is
3187 tieable and it is valid if X is a SET that copies
3190 if (GET_CODE (to) == SUBREG
3191 && ! MODES_TIEABLE_P (GET_MODE (to),
3192 GET_MODE (SUBREG_REG (to)))
3193 && ! (code == SUBREG
3194 && MODES_TIEABLE_P (GET_MODE (x),
3195 GET_MODE (SUBREG_REG (to))))
3197 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3200 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3202 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3206 /* If we are in a SET_DEST, suppress most cases unless we
3207 have gone inside a MEM, in which case we want to
3208 simplify the address. We assume here that things that
3209 are actually part of the destination have their inner
3210 parts in the first expression. This is true for SUBREG,
3211 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3212 things aside from REG and MEM that should appear in a
3214 new = subst (XEXP (x, i), from, to,
3216 && (code == SUBREG || code == STRICT_LOW_PART
3217 || code == ZERO_EXTRACT))
3219 && i == 0), unique_copy);
3221 /* If we found that we will have to reject this combination,
3222 indicate that by returning the CLOBBER ourselves, rather than
3223 an expression containing it. This will speed things up as
3224 well as prevent accidents where two CLOBBERs are considered
3225 to be equal, thus producing an incorrect simplification. */
3227 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3230 SUBST (XEXP (x, i), new);
3235 /* Try to simplify X. If the simplification changed the code, it is likely
3236 that further simplification will help, so loop, but limit the number
3237 of repetitions that will be performed. */
3239 for (i = 0; i < 4; i++)
3241 /* If X is sufficiently simple, don't bother trying to do anything
3243 if (code != CONST_INT && code != REG && code != CLOBBER)
3244 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3246 if (GET_CODE (x) == code)
3249 code = GET_CODE (x);
3251 /* We no longer know the original mode of operand 0 since we
3252 have changed the form of X) */
3253 op0_mode = VOIDmode;
3259 /* Simplify X, a piece of RTL. We just operate on the expression at the
3260 outer level; call `subst' to simplify recursively. Return the new
3263 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3264 will be the iteration even if an expression with a code different from
3265 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3268 simplify_rtx (x, op0_mode, last, in_dest)
3270 enum machine_mode op0_mode;
3274 enum rtx_code code = GET_CODE (x);
3275 enum machine_mode mode = GET_MODE (x);
3279 /* If this is a commutative operation, put a constant last and a complex
3280 expression first. We don't need to do this for comparisons here. */
3281 if (GET_RTX_CLASS (code) == 'c'
3282 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3283 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3284 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3285 || (GET_CODE (XEXP (x, 0)) == SUBREG
3286 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3287 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3290 SUBST (XEXP (x, 0), XEXP (x, 1));
3291 SUBST (XEXP (x, 1), temp);
3294 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3295 sign extension of a PLUS with a constant, reverse the order of the sign
3296 extension and the addition. Note that this not the same as the original
3297 code, but overflow is undefined for signed values. Also note that the
3298 PLUS will have been partially moved "inside" the sign-extension, so that
3299 the first operand of X will really look like:
3300 (ashiftrt (plus (ashift A C4) C5) C4).
3302 (plus (ashiftrt (ashift A C4) C2) C4)
3303 and replace the first operand of X with that expression. Later parts
3304 of this function may simplify the expression further.
3306 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3307 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3308 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3310 We do this to simplify address expressions. */
3312 if ((code == PLUS || code == MINUS || code == MULT)
3313 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3314 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3315 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3316 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3317 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3318 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3319 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3320 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3321 XEXP (XEXP (XEXP (x, 0), 0), 1),
3322 XEXP (XEXP (x, 0), 1))) != 0)
3325 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3326 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3327 INTVAL (XEXP (XEXP (x, 0), 1)));
3329 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3330 INTVAL (XEXP (XEXP (x, 0), 1)));
3332 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3335 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3336 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3337 things. Check for cases where both arms are testing the same
3340 Don't do anything if all operands are very simple. */
3342 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3343 || GET_RTX_CLASS (code) == '<')
3344 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3345 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3346 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3348 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3349 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3350 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3352 || (GET_RTX_CLASS (code) == '1'
3353 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3354 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3355 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3358 rtx cond, true, false;
3360 cond = if_then_else_cond (x, &true, &false);
3362 /* If everything is a comparison, what we have is highly unlikely
3363 to be simpler, so don't use it. */
3364 && ! (GET_RTX_CLASS (code) == '<'
3365 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3366 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3368 rtx cop1 = const0_rtx;
3369 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3371 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3374 /* Simplify the alternative arms; this may collapse the true and
3375 false arms to store-flag values. */
3376 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3377 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3379 /* Restarting if we generate a store-flag expression will cause
3380 us to loop. Just drop through in this case. */
3382 /* If the result values are STORE_FLAG_VALUE and zero, we can
3383 just make the comparison operation. */
3384 if (true == const_true_rtx && false == const0_rtx)
3385 x = gen_binary (cond_code, mode, cond, cop1);
3386 else if (true == const0_rtx && false == const_true_rtx)
3387 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3389 /* Likewise, we can make the negate of a comparison operation
3390 if the result values are - STORE_FLAG_VALUE and zero. */
3391 else if (GET_CODE (true) == CONST_INT
3392 && INTVAL (true) == - STORE_FLAG_VALUE
3393 && false == const0_rtx)
3394 x = gen_unary (NEG, mode, mode,
3395 gen_binary (cond_code, mode, cond, cop1));
3396 else if (GET_CODE (false) == CONST_INT
3397 && INTVAL (false) == - STORE_FLAG_VALUE
3398 && true == const0_rtx)
3399 x = gen_unary (NEG, mode, mode,
3400 gen_binary (reverse_condition (cond_code),
3403 return gen_rtx_IF_THEN_ELSE (mode,
3404 gen_binary (cond_code, VOIDmode,
3408 code = GET_CODE (x);
3409 op0_mode = VOIDmode;
3413 /* Try to fold this expression in case we have constants that weren't
3416 switch (GET_RTX_CLASS (code))
3419 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3422 temp = simplify_relational_operation (code, op0_mode,
3423 XEXP (x, 0), XEXP (x, 1));
3424 #ifdef FLOAT_STORE_FLAG_VALUE
3425 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3426 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3427 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3432 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3436 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3437 XEXP (x, 1), XEXP (x, 2));
3442 x = temp, code = GET_CODE (temp);
3444 /* First see if we can apply the inverse distributive law. */
3445 if (code == PLUS || code == MINUS
3446 || code == AND || code == IOR || code == XOR)
3448 x = apply_distributive_law (x);
3449 code = GET_CODE (x);
3452 /* If CODE is an associative operation not otherwise handled, see if we
3453 can associate some operands. This can win if they are constants or
3454 if they are logically related (i.e. (a & b) & a. */
3455 if ((code == PLUS || code == MINUS
3456 || code == MULT || code == AND || code == IOR || code == XOR
3457 || code == DIV || code == UDIV
3458 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3459 && INTEGRAL_MODE_P (mode))
3461 if (GET_CODE (XEXP (x, 0)) == code)
3463 rtx other = XEXP (XEXP (x, 0), 0);
3464 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3465 rtx inner_op1 = XEXP (x, 1);
3468 /* Make sure we pass the constant operand if any as the second
3469 one if this is a commutative operation. */
3470 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3472 rtx tem = inner_op0;
3473 inner_op0 = inner_op1;
3476 inner = simplify_binary_operation (code == MINUS ? PLUS
3477 : code == DIV ? MULT
3478 : code == UDIV ? MULT
3480 mode, inner_op0, inner_op1);
3482 /* For commutative operations, try the other pair if that one
3484 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3486 other = XEXP (XEXP (x, 0), 1);
3487 inner = simplify_binary_operation (code, mode,
3488 XEXP (XEXP (x, 0), 0),
3493 return gen_binary (code, mode, other, inner);
3497 /* A little bit of algebraic simplification here. */
3501 /* Ensure that our address has any ASHIFTs converted to MULT in case
3502 address-recognizing predicates are called later. */
3503 temp = make_compound_operation (XEXP (x, 0), MEM);
3504 SUBST (XEXP (x, 0), temp);
3508 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3509 is paradoxical. If we can't do that safely, then it becomes
3510 something nonsensical so that this combination won't take place. */
3512 if (GET_CODE (SUBREG_REG (x)) == MEM
3513 && (GET_MODE_SIZE (mode)
3514 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3516 rtx inner = SUBREG_REG (x);
3517 int endian_offset = 0;
3518 /* Don't change the mode of the MEM
3519 if that would change the meaning of the address. */
3520 if (MEM_VOLATILE_P (SUBREG_REG (x))
3521 || mode_dependent_address_p (XEXP (inner, 0)))
3522 return gen_rtx_CLOBBER (mode, const0_rtx);
3524 if (BYTES_BIG_ENDIAN)
3526 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3527 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3528 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3529 endian_offset -= (UNITS_PER_WORD
3530 - GET_MODE_SIZE (GET_MODE (inner)));
3532 /* Note if the plus_constant doesn't make a valid address
3533 then this combination won't be accepted. */
3534 x = gen_rtx_MEM (mode,
3535 plus_constant (XEXP (inner, 0),
3536 (SUBREG_WORD (x) * UNITS_PER_WORD
3538 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3539 MEM_COPY_ATTRIBUTES (x, inner);
3543 /* If we are in a SET_DEST, these other cases can't apply. */
3547 /* Changing mode twice with SUBREG => just change it once,
3548 or not at all if changing back to starting mode. */
3549 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3551 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3552 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3553 return SUBREG_REG (SUBREG_REG (x));
3555 SUBST_INT (SUBREG_WORD (x),
3556 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3557 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3560 /* SUBREG of a hard register => just change the register number
3561 and/or mode. If the hard register is not valid in that mode,
3562 suppress this combination. If the hard register is the stack,
3563 frame, or argument pointer, leave this as a SUBREG. */
3565 if (GET_CODE (SUBREG_REG (x)) == REG
3566 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3567 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3568 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3569 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3571 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3572 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3574 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3576 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3578 return gen_rtx_REG (mode,
3579 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3581 return gen_rtx_CLOBBER (mode, const0_rtx);
3584 /* For a constant, try to pick up the part we want. Handle a full
3585 word and low-order part. Only do this if we are narrowing
3586 the constant; if it is being widened, we have no idea what
3587 the extra bits will have been set to. */
3589 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3590 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3591 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3592 && GET_MODE_CLASS (mode) == MODE_INT)
3594 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3600 /* If we want a subreg of a constant, at offset 0,
3601 take the low bits. On a little-endian machine, that's
3602 always valid. On a big-endian machine, it's valid
3603 only if the constant's mode fits in one word. Note that we
3604 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3605 if (CONSTANT_P (SUBREG_REG (x))
3606 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3607 || ! WORDS_BIG_ENDIAN)
3608 ? SUBREG_WORD (x) == 0
3610 == ((GET_MODE_SIZE (op0_mode)
3611 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3613 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3614 && (! WORDS_BIG_ENDIAN
3615 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3616 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3618 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3619 since we are saying that the high bits don't matter. */
3620 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3621 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3622 return SUBREG_REG (x);
3624 /* Note that we cannot do any narrowing for non-constants since
3625 we might have been counting on using the fact that some bits were
3626 zero. We now do this in the SET. */
3631 /* (not (plus X -1)) can become (neg X). */
3632 if (GET_CODE (XEXP (x, 0)) == PLUS
3633 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3634 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3636 /* Similarly, (not (neg X)) is (plus X -1). */
3637 if (GET_CODE (XEXP (x, 0)) == NEG)
3638 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3641 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3642 if (GET_CODE (XEXP (x, 0)) == XOR
3643 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3644 && (temp = simplify_unary_operation (NOT, mode,
3645 XEXP (XEXP (x, 0), 1),
3647 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3649 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3650 other than 1, but that is not valid. We could do a similar
3651 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3652 but this doesn't seem common enough to bother with. */
3653 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3654 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3655 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3656 XEXP (XEXP (x, 0), 1));
3658 if (GET_CODE (XEXP (x, 0)) == SUBREG
3659 && subreg_lowpart_p (XEXP (x, 0))
3660 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3661 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3662 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3663 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3665 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3667 x = gen_rtx_ROTATE (inner_mode,
3668 gen_unary (NOT, inner_mode, inner_mode,
3670 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3671 return gen_lowpart_for_combine (mode, x);
3674 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3675 reversing the comparison code if valid. */
3676 if (STORE_FLAG_VALUE == -1
3677 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3678 && reversible_comparison_p (XEXP (x, 0)))
3679 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3680 mode, XEXP (XEXP (x, 0), 0),
3681 XEXP (XEXP (x, 0), 1));
3683 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3684 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3685 perform the above simplification. */
3687 if (STORE_FLAG_VALUE == -1
3688 && XEXP (x, 1) == const1_rtx
3689 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3690 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3691 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3692 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3694 /* Apply De Morgan's laws to reduce number of patterns for machines
3695 with negating logical insns (and-not, nand, etc.). If result has
3696 only one NOT, put it first, since that is how the patterns are
3699 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3701 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3703 if (GET_CODE (in1) == NOT)
3704 in1 = XEXP (in1, 0);
3706 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3708 if (GET_CODE (in2) == NOT)
3709 in2 = XEXP (in2, 0);
3710 else if (GET_CODE (in2) == CONST_INT
3711 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3712 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3714 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3716 if (GET_CODE (in2) == NOT)
3719 in2 = in1; in1 = tem;
3722 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3728 /* (neg (plus X 1)) can become (not X). */
3729 if (GET_CODE (XEXP (x, 0)) == PLUS
3730 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3731 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3733 /* Similarly, (neg (not X)) is (plus X 1). */
3734 if (GET_CODE (XEXP (x, 0)) == NOT)
3735 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3737 /* (neg (minus X Y)) can become (minus Y X). */
3738 if (GET_CODE (XEXP (x, 0)) == MINUS
3739 && (! FLOAT_MODE_P (mode)
3740 /* x-y != -(y-x) with IEEE floating point. */
3741 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3743 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3744 XEXP (XEXP (x, 0), 0));
3746 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3747 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3748 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3749 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3751 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3752 if we can then eliminate the NEG (e.g.,
3753 if the operand is a constant). */
3755 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3757 temp = simplify_unary_operation (NEG, mode,
3758 XEXP (XEXP (x, 0), 0), mode);
3761 SUBST (XEXP (XEXP (x, 0), 0), temp);
3766 temp = expand_compound_operation (XEXP (x, 0));
3768 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3769 replaced by (lshiftrt X C). This will convert
3770 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3772 if (GET_CODE (temp) == ASHIFTRT
3773 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3774 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3775 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3776 INTVAL (XEXP (temp, 1)));
3778 /* If X has only a single bit that might be nonzero, say, bit I, convert
3779 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3780 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3781 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3782 or a SUBREG of one since we'd be making the expression more
3783 complex if it was just a register. */
3785 if (GET_CODE (temp) != REG
3786 && ! (GET_CODE (temp) == SUBREG
3787 && GET_CODE (SUBREG_REG (temp)) == REG)
3788 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3790 rtx temp1 = simplify_shift_const
3791 (NULL_RTX, ASHIFTRT, mode,
3792 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3793 GET_MODE_BITSIZE (mode) - 1 - i),
3794 GET_MODE_BITSIZE (mode) - 1 - i);
3796 /* If all we did was surround TEMP with the two shifts, we
3797 haven't improved anything, so don't use it. Otherwise,
3798 we are better off with TEMP1. */
3799 if (GET_CODE (temp1) != ASHIFTRT
3800 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3801 || XEXP (XEXP (temp1, 0), 0) != temp)
3807 /* We can't handle truncation to a partial integer mode here
3808 because we don't know the real bitsize of the partial
3810 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3813 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3814 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3815 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3817 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3818 GET_MODE_MASK (mode), NULL_RTX, 0));
3820 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3821 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3822 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3823 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3824 return XEXP (XEXP (x, 0), 0);
3826 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3827 (OP:SI foo:SI) if OP is NEG or ABS. */
3828 if ((GET_CODE (XEXP (x, 0)) == ABS
3829 || GET_CODE (XEXP (x, 0)) == NEG)
3830 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3831 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3832 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3833 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3834 XEXP (XEXP (XEXP (x, 0), 0), 0));
3836 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3838 if (GET_CODE (XEXP (x, 0)) == SUBREG
3839 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3840 && subreg_lowpart_p (XEXP (x, 0)))
3841 return SUBREG_REG (XEXP (x, 0));
3843 /* If we know that the value is already truncated, we can
3844 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3845 nonzero for the corresponding modes. */
3846 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3847 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3848 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3849 >= GET_MODE_BITSIZE (mode) + 1)
3850 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3852 /* A truncate of a comparison can be replaced with a subreg if
3853 STORE_FLAG_VALUE permits. This is like the previous test,
3854 but it works even if the comparison is done in a mode larger
3855 than HOST_BITS_PER_WIDE_INT. */
3856 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3857 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3858 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3859 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3861 /* Similarly, a truncate of a register whose value is a
3862 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3864 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3865 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3866 && (temp = get_last_value (XEXP (x, 0)))
3867 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3868 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3872 case FLOAT_TRUNCATE:
3873 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3874 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3875 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3876 return XEXP (XEXP (x, 0), 0);
3878 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3879 (OP:SF foo:SF) if OP is NEG or ABS. */
3880 if ((GET_CODE (XEXP (x, 0)) == ABS
3881 || GET_CODE (XEXP (x, 0)) == NEG)
3882 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3883 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3884 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3885 XEXP (XEXP (XEXP (x, 0), 0), 0));
3887 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3888 is (float_truncate:SF x). */
3889 if (GET_CODE (XEXP (x, 0)) == SUBREG
3890 && subreg_lowpart_p (XEXP (x, 0))
3891 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3892 return SUBREG_REG (XEXP (x, 0));
3897 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3898 using cc0, in which case we want to leave it as a COMPARE
3899 so we can distinguish it from a register-register-copy. */
3900 if (XEXP (x, 1) == const0_rtx)
3903 /* In IEEE floating point, x-0 is not the same as x. */
3904 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3905 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3907 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3913 /* (const (const X)) can become (const X). Do it this way rather than
3914 returning the inner CONST since CONST can be shared with a
3916 if (GET_CODE (XEXP (x, 0)) == CONST)
3917 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3922 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3923 can add in an offset. find_split_point will split this address up
3924 again if it doesn't match. */
3925 if (GET_CODE (XEXP (x, 0)) == HIGH
3926 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3932 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3933 outermost. That's because that's the way indexed addresses are
3934 supposed to appear. This code used to check many more cases, but
3935 they are now checked elsewhere. */
3936 if (GET_CODE (XEXP (x, 0)) == PLUS
3937 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3938 return gen_binary (PLUS, mode,
3939 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3941 XEXP (XEXP (x, 0), 1));
3943 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3944 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3945 bit-field and can be replaced by either a sign_extend or a
3946 sign_extract. The `and' may be a zero_extend and the two
3947 <c>, -<c> constants may be reversed. */
3948 if (GET_CODE (XEXP (x, 0)) == XOR
3949 && GET_CODE (XEXP (x, 1)) == CONST_INT
3950 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3951 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3952 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3953 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
3954 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3955 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3956 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3957 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3958 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3959 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3960 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3962 return simplify_shift_const
3963 (NULL_RTX, ASHIFTRT, mode,
3964 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3965 XEXP (XEXP (XEXP (x, 0), 0), 0),
3966 GET_MODE_BITSIZE (mode) - (i + 1)),
3967 GET_MODE_BITSIZE (mode) - (i + 1));
3969 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3970 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3971 is 1. This produces better code than the alternative immediately
3973 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3974 && reversible_comparison_p (XEXP (x, 0))
3975 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3976 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3978 gen_unary (NEG, mode, mode,
3979 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3980 mode, XEXP (XEXP (x, 0), 0),
3981 XEXP (XEXP (x, 0), 1)));
3983 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3984 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3985 the bitsize of the mode - 1. This allows simplification of
3986 "a = (b & 8) == 0;" */
3987 if (XEXP (x, 1) == constm1_rtx
3988 && GET_CODE (XEXP (x, 0)) != REG
3989 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3990 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3991 && nonzero_bits (XEXP (x, 0), mode) == 1)
3992 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3993 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3994 gen_rtx_combine (XOR, mode,
3995 XEXP (x, 0), const1_rtx),
3996 GET_MODE_BITSIZE (mode) - 1),
3997 GET_MODE_BITSIZE (mode) - 1);
3999 /* If we are adding two things that have no bits in common, convert
4000 the addition into an IOR. This will often be further simplified,
4001 for example in cases like ((a & 1) + (a & 2)), which can
4004 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4005 && (nonzero_bits (XEXP (x, 0), mode)
4006 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4007 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4011 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4012 by reversing the comparison code if valid. */
4013 if (STORE_FLAG_VALUE == 1
4014 && XEXP (x, 0) == const1_rtx
4015 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4016 && reversible_comparison_p (XEXP (x, 1)))
4017 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4018 mode, XEXP (XEXP (x, 1), 0),
4019 XEXP (XEXP (x, 1), 1));
4021 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4022 (and <foo> (const_int pow2-1)) */
4023 if (GET_CODE (XEXP (x, 1)) == AND
4024 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4025 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4026 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4027 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4028 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4030 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4032 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4033 return gen_binary (MINUS, mode,
4034 gen_binary (MINUS, mode, XEXP (x, 0),
4035 XEXP (XEXP (x, 1), 0)),
4036 XEXP (XEXP (x, 1), 1));
4040 /* If we have (mult (plus A B) C), apply the distributive law and then
4041 the inverse distributive law to see if things simplify. This
4042 occurs mostly in addresses, often when unrolling loops. */
4044 if (GET_CODE (XEXP (x, 0)) == PLUS)
4046 x = apply_distributive_law
4047 (gen_binary (PLUS, mode,
4048 gen_binary (MULT, mode,
4049 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4050 gen_binary (MULT, mode,
4051 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4053 if (GET_CODE (x) != MULT)
4059 /* If this is a divide by a power of two, treat it as a shift if
4060 its first operand is a shift. */
4061 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4062 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4063 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4064 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4065 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4066 || GET_CODE (XEXP (x, 0)) == ROTATE
4067 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4068 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4072 case GT: case GTU: case GE: case GEU:
4073 case LT: case LTU: case LE: case LEU:
4074 /* If the first operand is a condition code, we can't do anything
4076 if (GET_CODE (XEXP (x, 0)) == COMPARE
4077 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4079 && XEXP (x, 0) != cc0_rtx
4083 rtx op0 = XEXP (x, 0);
4084 rtx op1 = XEXP (x, 1);
4085 enum rtx_code new_code;
4087 if (GET_CODE (op0) == COMPARE)
4088 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4090 /* Simplify our comparison, if possible. */
4091 new_code = simplify_comparison (code, &op0, &op1);
4093 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4094 if only the low-order bit is possibly nonzero in X (such as when
4095 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4096 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4097 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4100 Remove any ZERO_EXTRACT we made when thinking this was a
4101 comparison. It may now be simpler to use, e.g., an AND. If a
4102 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4103 the call to make_compound_operation in the SET case. */
4105 if (STORE_FLAG_VALUE == 1
4106 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4107 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4108 return gen_lowpart_for_combine (mode,
4109 expand_compound_operation (op0));
4111 else if (STORE_FLAG_VALUE == 1
4112 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4113 && op1 == const0_rtx
4114 && (num_sign_bit_copies (op0, mode)
4115 == GET_MODE_BITSIZE (mode)))
4117 op0 = expand_compound_operation (op0);
4118 return gen_unary (NEG, mode, mode,
4119 gen_lowpart_for_combine (mode, op0));
4122 else if (STORE_FLAG_VALUE == 1
4123 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4124 && op1 == const0_rtx
4125 && nonzero_bits (op0, mode) == 1)
4127 op0 = expand_compound_operation (op0);
4128 return gen_binary (XOR, mode,
4129 gen_lowpart_for_combine (mode, op0),
4133 else if (STORE_FLAG_VALUE == 1
4134 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4135 && op1 == const0_rtx
4136 && (num_sign_bit_copies (op0, mode)
4137 == GET_MODE_BITSIZE (mode)))
4139 op0 = expand_compound_operation (op0);
4140 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4143 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4145 if (STORE_FLAG_VALUE == -1
4146 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4147 && op1 == const0_rtx
4148 && (num_sign_bit_copies (op0, mode)
4149 == GET_MODE_BITSIZE (mode)))
4150 return gen_lowpart_for_combine (mode,
4151 expand_compound_operation (op0));
4153 else if (STORE_FLAG_VALUE == -1
4154 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4155 && op1 == const0_rtx
4156 && nonzero_bits (op0, mode) == 1)
4158 op0 = expand_compound_operation (op0);
4159 return gen_unary (NEG, mode, mode,
4160 gen_lowpart_for_combine (mode, op0));
4163 else if (STORE_FLAG_VALUE == -1
4164 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4165 && op1 == const0_rtx
4166 && (num_sign_bit_copies (op0, mode)
4167 == GET_MODE_BITSIZE (mode)))
4169 op0 = expand_compound_operation (op0);
4170 return gen_unary (NOT, mode, mode,
4171 gen_lowpart_for_combine (mode, op0));
4174 /* If X is 0/1, (eq X 0) is X-1. */
4175 else if (STORE_FLAG_VALUE == -1
4176 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4177 && op1 == const0_rtx
4178 && nonzero_bits (op0, mode) == 1)
4180 op0 = expand_compound_operation (op0);
4181 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4184 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4185 one bit that might be nonzero, we can convert (ne x 0) to
4186 (ashift x c) where C puts the bit in the sign bit. Remove any
4187 AND with STORE_FLAG_VALUE when we are done, since we are only
4188 going to test the sign bit. */
4189 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4190 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4191 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4192 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4193 && op1 == const0_rtx
4194 && mode == GET_MODE (op0)
4195 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4197 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4198 expand_compound_operation (op0),
4199 GET_MODE_BITSIZE (mode) - 1 - i);
4200 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4206 /* If the code changed, return a whole new comparison. */
4207 if (new_code != code)
4208 return gen_rtx_combine (new_code, mode, op0, op1);
4210 /* Otherwise, keep this operation, but maybe change its operands.
4211 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4212 SUBST (XEXP (x, 0), op0);
4213 SUBST (XEXP (x, 1), op1);
4218 return simplify_if_then_else (x);
4224 /* If we are processing SET_DEST, we are done. */
4228 return expand_compound_operation (x);
4231 return simplify_set (x);
4236 return simplify_logical (x, last);
4239 /* (abs (neg <foo>)) -> (abs <foo>) */
4240 if (GET_CODE (XEXP (x, 0)) == NEG)
4241 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4243 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4245 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4248 /* If operand is something known to be positive, ignore the ABS. */
4249 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4250 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4251 <= HOST_BITS_PER_WIDE_INT)
4252 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4253 & ((HOST_WIDE_INT) 1
4254 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4259 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4260 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4261 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4266 /* (ffs (*_extend <X>)) = (ffs <X>) */
4267 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4268 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4269 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4273 /* (float (sign_extend <X>)) = (float <X>). */
4274 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4275 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4283 /* If this is a shift by a constant amount, simplify it. */
4284 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4285 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4286 INTVAL (XEXP (x, 1)));
4288 #ifdef SHIFT_COUNT_TRUNCATED
4289 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4291 force_to_mode (XEXP (x, 1), GET_MODE (x),
4293 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4307 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4310 simplify_if_then_else (x)
4313 enum machine_mode mode = GET_MODE (x);
4314 rtx cond = XEXP (x, 0);
4315 rtx true = XEXP (x, 1);
4316 rtx false = XEXP (x, 2);
4317 enum rtx_code true_code = GET_CODE (cond);
4318 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4322 /* Simplify storing of the truth value. */
4323 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4324 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4326 /* Also when the truth value has to be reversed. */
4327 if (comparison_p && reversible_comparison_p (cond)
4328 && true == const0_rtx && false == const_true_rtx)
4329 return gen_binary (reverse_condition (true_code),
4330 mode, XEXP (cond, 0), XEXP (cond, 1));
4332 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4333 in it is being compared against certain values. Get the true and false
4334 comparisons and see if that says anything about the value of each arm. */
4336 if (comparison_p && reversible_comparison_p (cond)
4337 && GET_CODE (XEXP (cond, 0)) == REG)
4340 rtx from = XEXP (cond, 0);
4341 enum rtx_code false_code = reverse_condition (true_code);
4342 rtx true_val = XEXP (cond, 1);
4343 rtx false_val = true_val;
4346 /* If FALSE_CODE is EQ, swap the codes and arms. */
4348 if (false_code == EQ)
4350 swapped = 1, true_code = EQ, false_code = NE;
4351 temp = true, true = false, false = temp;
4354 /* If we are comparing against zero and the expression being tested has
4355 only a single bit that might be nonzero, that is its value when it is
4356 not equal to zero. Similarly if it is known to be -1 or 0. */
4358 if (true_code == EQ && true_val == const0_rtx
4359 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4360 false_code = EQ, false_val = GEN_INT (nzb);
4361 else if (true_code == EQ && true_val == const0_rtx
4362 && (num_sign_bit_copies (from, GET_MODE (from))
4363 == GET_MODE_BITSIZE (GET_MODE (from))))
4364 false_code = EQ, false_val = constm1_rtx;
4366 /* Now simplify an arm if we know the value of the register in the
4367 branch and it is used in the arm. Be careful due to the potential
4368 of locally-shared RTL. */
4370 if (reg_mentioned_p (from, true))
4371 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4372 pc_rtx, pc_rtx, 0, 0);
4373 if (reg_mentioned_p (from, false))
4374 false = subst (known_cond (copy_rtx (false), false_code,
4376 pc_rtx, pc_rtx, 0, 0);
4378 SUBST (XEXP (x, 1), swapped ? false : true);
4379 SUBST (XEXP (x, 2), swapped ? true : false);
4381 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4384 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4385 reversed, do so to avoid needing two sets of patterns for
4386 subtract-and-branch insns. Similarly if we have a constant in the true
4387 arm, the false arm is the same as the first operand of the comparison, or
4388 the false arm is more complicated than the true arm. */
4390 if (comparison_p && reversible_comparison_p (cond)
4392 || (CONSTANT_P (true)
4393 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4394 || true == const0_rtx
4395 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4396 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4397 || (GET_CODE (true) == SUBREG
4398 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4399 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4400 || reg_mentioned_p (true, false)
4401 || rtx_equal_p (false, XEXP (cond, 0))))
4403 true_code = reverse_condition (true_code);
4405 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4408 SUBST (XEXP (x, 1), false);
4409 SUBST (XEXP (x, 2), true);
4411 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4413 /* It is possible that the conditional has been simplified out. */
4414 true_code = GET_CODE (cond);
4415 comparison_p = GET_RTX_CLASS (true_code) == '<';
4418 /* If the two arms are identical, we don't need the comparison. */
4420 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4423 /* Convert a == b ? b : a to "a". */
4424 if (true_code == EQ && ! side_effects_p (cond)
4425 && rtx_equal_p (XEXP (cond, 0), false)
4426 && rtx_equal_p (XEXP (cond, 1), true))
4428 else if (true_code == NE && ! side_effects_p (cond)
4429 && rtx_equal_p (XEXP (cond, 0), true)
4430 && rtx_equal_p (XEXP (cond, 1), false))
4433 /* Look for cases where we have (abs x) or (neg (abs X)). */
4435 if (GET_MODE_CLASS (mode) == MODE_INT
4436 && GET_CODE (false) == NEG
4437 && rtx_equal_p (true, XEXP (false, 0))
4439 && rtx_equal_p (true, XEXP (cond, 0))
4440 && ! side_effects_p (true))
4445 return gen_unary (ABS, mode, mode, true);
4448 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4453 /* Look for MIN or MAX. */
4455 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4457 && rtx_equal_p (XEXP (cond, 0), true)
4458 && rtx_equal_p (XEXP (cond, 1), false)
4459 && ! side_effects_p (cond))
4464 return gen_binary (SMAX, mode, true, false);
4467 return gen_binary (SMIN, mode, true, false);
4470 return gen_binary (UMAX, mode, true, false);
4473 return gen_binary (UMIN, mode, true, false);
4478 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4479 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4480 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4481 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4482 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4483 neither 1 or -1, but it isn't worth checking for. */
4485 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4486 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4488 rtx t = make_compound_operation (true, SET);
4489 rtx f = make_compound_operation (false, SET);
4490 rtx cond_op0 = XEXP (cond, 0);
4491 rtx cond_op1 = XEXP (cond, 1);
4492 enum rtx_code op = NIL, extend_op = NIL;
4493 enum machine_mode m = mode;
4494 rtx z = 0, c1 = NULL_RTX;
4496 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4497 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4498 || GET_CODE (t) == ASHIFT
4499 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4500 && rtx_equal_p (XEXP (t, 0), f))
4501 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4503 /* If an identity-zero op is commutative, check whether there
4504 would be a match if we swapped the operands. */
4505 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4506 || GET_CODE (t) == XOR)
4507 && rtx_equal_p (XEXP (t, 1), f))
4508 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4509 else if (GET_CODE (t) == SIGN_EXTEND
4510 && (GET_CODE (XEXP (t, 0)) == PLUS
4511 || GET_CODE (XEXP (t, 0)) == MINUS
4512 || GET_CODE (XEXP (t, 0)) == IOR
4513 || GET_CODE (XEXP (t, 0)) == XOR
4514 || GET_CODE (XEXP (t, 0)) == ASHIFT
4515 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4516 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4517 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4518 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4519 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4520 && (num_sign_bit_copies (f, GET_MODE (f))
4521 > (GET_MODE_BITSIZE (mode)
4522 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4524 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4525 extend_op = SIGN_EXTEND;
4526 m = GET_MODE (XEXP (t, 0));
4528 else if (GET_CODE (t) == SIGN_EXTEND
4529 && (GET_CODE (XEXP (t, 0)) == PLUS
4530 || GET_CODE (XEXP (t, 0)) == IOR
4531 || GET_CODE (XEXP (t, 0)) == XOR)
4532 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4533 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4534 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4535 && (num_sign_bit_copies (f, GET_MODE (f))
4536 > (GET_MODE_BITSIZE (mode)
4537 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4539 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4540 extend_op = SIGN_EXTEND;
4541 m = GET_MODE (XEXP (t, 0));
4543 else if (GET_CODE (t) == ZERO_EXTEND
4544 && (GET_CODE (XEXP (t, 0)) == PLUS
4545 || GET_CODE (XEXP (t, 0)) == MINUS
4546 || GET_CODE (XEXP (t, 0)) == IOR
4547 || GET_CODE (XEXP (t, 0)) == XOR
4548 || GET_CODE (XEXP (t, 0)) == ASHIFT
4549 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4550 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4551 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4552 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4553 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4554 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4555 && ((nonzero_bits (f, GET_MODE (f))
4556 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4559 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4560 extend_op = ZERO_EXTEND;
4561 m = GET_MODE (XEXP (t, 0));
4563 else if (GET_CODE (t) == ZERO_EXTEND
4564 && (GET_CODE (XEXP (t, 0)) == PLUS
4565 || GET_CODE (XEXP (t, 0)) == IOR
4566 || GET_CODE (XEXP (t, 0)) == XOR)
4567 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4568 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4569 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4570 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4571 && ((nonzero_bits (f, GET_MODE (f))
4572 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4575 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4576 extend_op = ZERO_EXTEND;
4577 m = GET_MODE (XEXP (t, 0));
4582 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4583 pc_rtx, pc_rtx, 0, 0);
4584 temp = gen_binary (MULT, m, temp,
4585 gen_binary (MULT, m, c1, const_true_rtx));
4586 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4587 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4589 if (extend_op != NIL)
4590 temp = gen_unary (extend_op, mode, m, temp);
4596 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4597 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4598 negation of a single bit, we can convert this operation to a shift. We
4599 can actually do this more generally, but it doesn't seem worth it. */
4601 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4602 && false == const0_rtx && GET_CODE (true) == CONST_INT
4603 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4604 && (i = exact_log2 (INTVAL (true))) >= 0)
4605 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4606 == GET_MODE_BITSIZE (mode))
4607 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4609 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4610 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4615 /* Simplify X, a SET expression. Return the new expression. */
4621 rtx src = SET_SRC (x);
4622 rtx dest = SET_DEST (x);
4623 enum machine_mode mode
4624 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4628 /* (set (pc) (return)) gets written as (return). */
4629 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4632 /* Now that we know for sure which bits of SRC we are using, see if we can
4633 simplify the expression for the object knowing that we only need the
4636 if (GET_MODE_CLASS (mode) == MODE_INT)
4638 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4639 SUBST (SET_SRC (x), src);
4642 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4643 the comparison result and try to simplify it unless we already have used
4644 undobuf.other_insn. */
4645 if ((GET_CODE (src) == COMPARE
4650 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4651 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4652 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4653 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4655 enum rtx_code old_code = GET_CODE (*cc_use);
4656 enum rtx_code new_code;
4658 int other_changed = 0;
4659 enum machine_mode compare_mode = GET_MODE (dest);
4661 if (GET_CODE (src) == COMPARE)
4662 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4664 op0 = src, op1 = const0_rtx;
4666 /* Simplify our comparison, if possible. */
4667 new_code = simplify_comparison (old_code, &op0, &op1);
4669 #ifdef EXTRA_CC_MODES
4670 /* If this machine has CC modes other than CCmode, check to see if we
4671 need to use a different CC mode here. */
4672 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4673 #endif /* EXTRA_CC_MODES */
4675 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4676 /* If the mode changed, we have to change SET_DEST, the mode in the
4677 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4678 a hard register, just build new versions with the proper mode. If it
4679 is a pseudo, we lose unless it is only time we set the pseudo, in
4680 which case we can safely change its mode. */
4681 if (compare_mode != GET_MODE (dest))
4683 int regno = REGNO (dest);
4684 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4686 if (regno < FIRST_PSEUDO_REGISTER
4687 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4689 if (regno >= FIRST_PSEUDO_REGISTER)
4690 SUBST (regno_reg_rtx[regno], new_dest);
4692 SUBST (SET_DEST (x), new_dest);
4693 SUBST (XEXP (*cc_use, 0), new_dest);
4701 /* If the code changed, we have to build a new comparison in
4702 undobuf.other_insn. */
4703 if (new_code != old_code)
4705 unsigned HOST_WIDE_INT mask;
4707 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4710 /* If the only change we made was to change an EQ into an NE or
4711 vice versa, OP0 has only one bit that might be nonzero, and OP1
4712 is zero, check if changing the user of the condition code will
4713 produce a valid insn. If it won't, we can keep the original code
4714 in that insn by surrounding our operation with an XOR. */
4716 if (((old_code == NE && new_code == EQ)
4717 || (old_code == EQ && new_code == NE))
4718 && ! other_changed && op1 == const0_rtx
4719 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4720 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4722 rtx pat = PATTERN (other_insn), note = 0;
4724 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4725 && ! check_asm_operands (pat)))
4727 PUT_CODE (*cc_use, old_code);
4730 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4738 undobuf.other_insn = other_insn;
4741 /* If we are now comparing against zero, change our source if
4742 needed. If we do not use cc0, we always have a COMPARE. */
4743 if (op1 == const0_rtx && dest == cc0_rtx)
4745 SUBST (SET_SRC (x), op0);
4751 /* Otherwise, if we didn't previously have a COMPARE in the
4752 correct mode, we need one. */
4753 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4756 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4761 /* Otherwise, update the COMPARE if needed. */
4762 SUBST (XEXP (src, 0), op0);
4763 SUBST (XEXP (src, 1), op1);
4768 /* Get SET_SRC in a form where we have placed back any
4769 compound expressions. Then do the checks below. */
4770 src = make_compound_operation (src, SET);
4771 SUBST (SET_SRC (x), src);
4774 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4775 and X being a REG or (subreg (reg)), we may be able to convert this to
4776 (set (subreg:m2 x) (op)).
4778 We can always do this if M1 is narrower than M2 because that means that
4779 we only care about the low bits of the result.
4781 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4782 perform a narrower operation than requested since the high-order bits will
4783 be undefined. On machine where it is defined, this transformation is safe
4784 as long as M1 and M2 have the same number of words. */
4786 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4787 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4788 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4790 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4791 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4792 #ifndef WORD_REGISTER_OPERATIONS
4793 && (GET_MODE_SIZE (GET_MODE (src))
4794 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4796 #ifdef CLASS_CANNOT_CHANGE_SIZE
4797 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4798 && (TEST_HARD_REG_BIT
4799 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4801 && (GET_MODE_SIZE (GET_MODE (src))
4802 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4804 && (GET_CODE (dest) == REG
4805 || (GET_CODE (dest) == SUBREG
4806 && GET_CODE (SUBREG_REG (dest)) == REG)))
4808 SUBST (SET_DEST (x),
4809 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4811 SUBST (SET_SRC (x), SUBREG_REG (src));
4813 src = SET_SRC (x), dest = SET_DEST (x);
4816 #ifdef LOAD_EXTEND_OP
4817 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4818 would require a paradoxical subreg. Replace the subreg with a
4819 zero_extend to avoid the reload that would otherwise be required. */
4821 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4822 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4823 && SUBREG_WORD (src) == 0
4824 && (GET_MODE_SIZE (GET_MODE (src))
4825 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4826 && GET_CODE (SUBREG_REG (src)) == MEM)
4829 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4830 GET_MODE (src), XEXP (src, 0)));
4836 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4837 are comparing an item known to be 0 or -1 against 0, use a logical
4838 operation instead. Check for one of the arms being an IOR of the other
4839 arm with some value. We compute three terms to be IOR'ed together. In
4840 practice, at most two will be nonzero. Then we do the IOR's. */
4842 if (GET_CODE (dest) != PC
4843 && GET_CODE (src) == IF_THEN_ELSE
4844 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4845 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4846 && XEXP (XEXP (src, 0), 1) == const0_rtx
4847 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4848 #ifdef HAVE_conditional_move
4849 && ! can_conditionally_move_p (GET_MODE (src))
4851 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4852 GET_MODE (XEXP (XEXP (src, 0), 0)))
4853 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4854 && ! side_effects_p (src))
4856 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4857 ? XEXP (src, 1) : XEXP (src, 2));
4858 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4859 ? XEXP (src, 2) : XEXP (src, 1));
4860 rtx term1 = const0_rtx, term2, term3;
4862 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4863 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4864 else if (GET_CODE (true) == IOR
4865 && rtx_equal_p (XEXP (true, 1), false))
4866 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4867 else if (GET_CODE (false) == IOR
4868 && rtx_equal_p (XEXP (false, 0), true))
4869 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4870 else if (GET_CODE (false) == IOR
4871 && rtx_equal_p (XEXP (false, 1), true))
4872 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4874 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4875 term3 = gen_binary (AND, GET_MODE (src),
4876 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4877 XEXP (XEXP (src, 0), 0)),
4881 gen_binary (IOR, GET_MODE (src),
4882 gen_binary (IOR, GET_MODE (src), term1, term2),
4888 #ifdef HAVE_conditional_arithmetic
4889 /* If we have conditional arithmetic and the operand of a SET is
4890 a conditional expression, replace this with an IF_THEN_ELSE.
4891 We can either have a conditional expression or a MULT of that expression
4893 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
4894 || GET_RTX_CLASS (GET_CODE (src)) == '2'
4895 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
4896 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
4897 || (GET_CODE (XEXP (src, 0)) == MULT
4898 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
4899 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
4901 rtx cond = XEXP (src, 0);
4902 rtx true_val = const1_rtx;
4903 rtx false_arm, true_arm;
4905 if (GET_CODE (cond) == MULT)
4907 true_val = XEXP (cond, 1);
4908 cond = XEXP (cond, 0);
4911 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
4913 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
4914 GET_MODE (XEXP (src, 0)), true_val);
4915 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
4916 GET_MODE (XEXP (src, 0)), const0_rtx);
4920 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
4921 true_val, XEXP (src, 1));
4922 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
4923 const0_rtx, XEXP (src, 1));
4926 /* Canonicalize if true_arm is the simpler one. */
4927 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
4928 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
4929 && reversible_comparison_p (cond))
4931 rtx temp = true_arm;
4933 true_arm = false_arm;
4936 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
4937 GET_MODE (cond), XEXP (cond, 0),
4941 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
4942 gen_rtx_combine (GET_CODE (cond), VOIDmode,
4945 true_arm, false_arm);
4946 SUBST (SET_SRC (x), src);
4950 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4951 whole thing fail. */
4952 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4954 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4957 /* Convert this into a field assignment operation, if possible. */
4958 return make_field_assignment (x);
4961 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4962 result. LAST is nonzero if this is the last retry. */
4965 simplify_logical (x, last)
4969 enum machine_mode mode = GET_MODE (x);
4970 rtx op0 = XEXP (x, 0);
4971 rtx op1 = XEXP (x, 1);
4973 switch (GET_CODE (x))
4976 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4977 insn (and may simplify more). */
4978 if (GET_CODE (op0) == XOR
4979 && rtx_equal_p (XEXP (op0, 0), op1)
4980 && ! side_effects_p (op1))
4981 x = gen_binary (AND, mode,
4982 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4984 if (GET_CODE (op0) == XOR
4985 && rtx_equal_p (XEXP (op0, 1), op1)
4986 && ! side_effects_p (op1))
4987 x = gen_binary (AND, mode,
4988 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4990 /* Similarly for (~ (A ^ B)) & A. */
4991 if (GET_CODE (op0) == NOT
4992 && GET_CODE (XEXP (op0, 0)) == XOR
4993 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4994 && ! side_effects_p (op1))
4995 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4997 if (GET_CODE (op0) == NOT
4998 && GET_CODE (XEXP (op0, 0)) == XOR
4999 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5000 && ! side_effects_p (op1))
5001 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5003 /* We can call simplify_and_const_int only if we don't lose
5004 any (sign) bits when converting INTVAL (op1) to
5005 "unsigned HOST_WIDE_INT". */
5006 if (GET_CODE (op1) == CONST_INT
5007 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5008 || INTVAL (op1) > 0))
5010 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5012 /* If we have (ior (and (X C1) C2)) and the next restart would be
5013 the last, simplify this by making C1 as small as possible
5016 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5017 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5018 && GET_CODE (op1) == CONST_INT)
5019 return gen_binary (IOR, mode,
5020 gen_binary (AND, mode, XEXP (op0, 0),
5021 GEN_INT (INTVAL (XEXP (op0, 1))
5022 & ~ INTVAL (op1))), op1);
5024 if (GET_CODE (x) != AND)
5027 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5028 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5029 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5032 /* Convert (A | B) & A to A. */
5033 if (GET_CODE (op0) == IOR
5034 && (rtx_equal_p (XEXP (op0, 0), op1)
5035 || rtx_equal_p (XEXP (op0, 1), op1))
5036 && ! side_effects_p (XEXP (op0, 0))
5037 && ! side_effects_p (XEXP (op0, 1)))
5040 /* In the following group of tests (and those in case IOR below),
5041 we start with some combination of logical operations and apply
5042 the distributive law followed by the inverse distributive law.
5043 Most of the time, this results in no change. However, if some of
5044 the operands are the same or inverses of each other, simplifications
5047 For example, (and (ior A B) (not B)) can occur as the result of
5048 expanding a bit field assignment. When we apply the distributive
5049 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5050 which then simplifies to (and (A (not B))).
5052 If we have (and (ior A B) C), apply the distributive law and then
5053 the inverse distributive law to see if things simplify. */
5055 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5057 x = apply_distributive_law
5058 (gen_binary (GET_CODE (op0), mode,
5059 gen_binary (AND, mode, XEXP (op0, 0), op1),
5060 gen_binary (AND, mode, XEXP (op0, 1), op1)));
5061 if (GET_CODE (x) != AND)
5065 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5066 return apply_distributive_law
5067 (gen_binary (GET_CODE (op1), mode,
5068 gen_binary (AND, mode, XEXP (op1, 0), op0),
5069 gen_binary (AND, mode, XEXP (op1, 1), op0)));
5071 /* Similarly, taking advantage of the fact that
5072 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5074 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5075 return apply_distributive_law
5076 (gen_binary (XOR, mode,
5077 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5078 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
5080 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5081 return apply_distributive_law
5082 (gen_binary (XOR, mode,
5083 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5084 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
5088 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5089 if (GET_CODE (op1) == CONST_INT
5090 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5091 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5094 /* Convert (A & B) | A to A. */
5095 if (GET_CODE (op0) == AND
5096 && (rtx_equal_p (XEXP (op0, 0), op1)
5097 || rtx_equal_p (XEXP (op0, 1), op1))
5098 && ! side_effects_p (XEXP (op0, 0))
5099 && ! side_effects_p (XEXP (op0, 1)))
5102 /* If we have (ior (and A B) C), apply the distributive law and then
5103 the inverse distributive law to see if things simplify. */
5105 if (GET_CODE (op0) == AND)
5107 x = apply_distributive_law
5108 (gen_binary (AND, mode,
5109 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5110 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
5112 if (GET_CODE (x) != IOR)
5116 if (GET_CODE (op1) == AND)
5118 x = apply_distributive_law
5119 (gen_binary (AND, mode,
5120 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5121 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
5123 if (GET_CODE (x) != IOR)
5127 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5128 mode size to (rotate A CX). */
5130 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5131 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5132 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5133 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5134 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5135 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5136 == GET_MODE_BITSIZE (mode)))
5137 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5138 (GET_CODE (op0) == ASHIFT
5139 ? XEXP (op0, 1) : XEXP (op1, 1)));
5141 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5142 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5143 does not affect any of the bits in OP1, it can really be done
5144 as a PLUS and we can associate. We do this by seeing if OP1
5145 can be safely shifted left C bits. */
5146 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5147 && GET_CODE (XEXP (op0, 0)) == PLUS
5148 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5149 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5150 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5152 int count = INTVAL (XEXP (op0, 1));
5153 HOST_WIDE_INT mask = INTVAL (op1) << count;
5155 if (mask >> count == INTVAL (op1)
5156 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5158 SUBST (XEXP (XEXP (op0, 0), 1),
5159 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5166 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5167 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5170 int num_negated = 0;
5172 if (GET_CODE (op0) == NOT)
5173 num_negated++, op0 = XEXP (op0, 0);
5174 if (GET_CODE (op1) == NOT)
5175 num_negated++, op1 = XEXP (op1, 0);
5177 if (num_negated == 2)
5179 SUBST (XEXP (x, 0), op0);
5180 SUBST (XEXP (x, 1), op1);
5182 else if (num_negated == 1)
5183 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5186 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5187 correspond to a machine insn or result in further simplifications
5188 if B is a constant. */
5190 if (GET_CODE (op0) == AND
5191 && rtx_equal_p (XEXP (op0, 1), op1)
5192 && ! side_effects_p (op1))
5193 return gen_binary (AND, mode,
5194 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5197 else if (GET_CODE (op0) == AND
5198 && rtx_equal_p (XEXP (op0, 0), op1)
5199 && ! side_effects_p (op1))
5200 return gen_binary (AND, mode,
5201 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5204 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5205 comparison if STORE_FLAG_VALUE is 1. */
5206 if (STORE_FLAG_VALUE == 1
5207 && op1 == const1_rtx
5208 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5209 && reversible_comparison_p (op0))
5210 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5211 mode, XEXP (op0, 0), XEXP (op0, 1));
5213 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5214 is (lt foo (const_int 0)), so we can perform the above
5215 simplification if STORE_FLAG_VALUE is 1. */
5217 if (STORE_FLAG_VALUE == 1
5218 && op1 == const1_rtx
5219 && GET_CODE (op0) == LSHIFTRT
5220 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5221 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5222 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5224 /* (xor (comparison foo bar) (const_int sign-bit))
5225 when STORE_FLAG_VALUE is the sign bit. */
5226 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5227 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5228 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5229 && op1 == const_true_rtx
5230 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5231 && reversible_comparison_p (op0))
5232 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5233 mode, XEXP (op0, 0), XEXP (op0, 1));
5243 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5244 operations" because they can be replaced with two more basic operations.
5245 ZERO_EXTEND is also considered "compound" because it can be replaced with
5246 an AND operation, which is simpler, though only one operation.
5248 The function expand_compound_operation is called with an rtx expression
5249 and will convert it to the appropriate shifts and AND operations,
5250 simplifying at each stage.
5252 The function make_compound_operation is called to convert an expression
5253 consisting of shifts and ANDs into the equivalent compound expression.
5254 It is the inverse of this function, loosely speaking. */
5257 expand_compound_operation (x)
5265 switch (GET_CODE (x))
5270 /* We can't necessarily use a const_int for a multiword mode;
5271 it depends on implicitly extending the value.
5272 Since we don't know the right way to extend it,
5273 we can't tell whether the implicit way is right.
5275 Even for a mode that is no wider than a const_int,
5276 we can't win, because we need to sign extend one of its bits through
5277 the rest of it, and we don't know which bit. */
5278 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5281 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5282 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5283 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5284 reloaded. If not for that, MEM's would very rarely be safe.
5286 Reject MODEs bigger than a word, because we might not be able
5287 to reference a two-register group starting with an arbitrary register
5288 (and currently gen_lowpart might crash for a SUBREG). */
5290 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5293 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5294 /* If the inner object has VOIDmode (the only way this can happen
5295 is if it is a ASM_OPERANDS), we can't do anything since we don't
5296 know how much masking to do. */
5305 /* If the operand is a CLOBBER, just return it. */
5306 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5309 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5310 || GET_CODE (XEXP (x, 2)) != CONST_INT
5311 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5314 len = INTVAL (XEXP (x, 1));
5315 pos = INTVAL (XEXP (x, 2));
5317 /* If this goes outside the object being extracted, replace the object
5318 with a (use (mem ...)) construct that only combine understands
5319 and is used only for this purpose. */
5320 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5321 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5323 if (BITS_BIG_ENDIAN)
5324 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5332 /* We can optimize some special cases of ZERO_EXTEND. */
5333 if (GET_CODE (x) == ZERO_EXTEND)
5335 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5336 know that the last value didn't have any inappropriate bits
5338 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5339 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5340 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5341 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5342 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5343 return XEXP (XEXP (x, 0), 0);
5345 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5346 if (GET_CODE (XEXP (x, 0)) == SUBREG
5347 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5348 && subreg_lowpart_p (XEXP (x, 0))
5349 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5350 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5351 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5352 return SUBREG_REG (XEXP (x, 0));
5354 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5355 is a comparison and STORE_FLAG_VALUE permits. This is like
5356 the first case, but it works even when GET_MODE (x) is larger
5357 than HOST_WIDE_INT. */
5358 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5359 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5360 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5361 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5362 <= HOST_BITS_PER_WIDE_INT)
5363 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5364 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5365 return XEXP (XEXP (x, 0), 0);
5367 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5368 if (GET_CODE (XEXP (x, 0)) == SUBREG
5369 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5370 && subreg_lowpart_p (XEXP (x, 0))
5371 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5372 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5373 <= HOST_BITS_PER_WIDE_INT)
5374 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5375 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5376 return SUBREG_REG (XEXP (x, 0));
5378 /* If sign extension is cheaper than zero extension, then use it
5379 if we know that no extraneous bits are set, and that the high
5381 if (flag_expensive_optimizations
5382 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5383 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5384 & ~ (((unsigned HOST_WIDE_INT)
5385 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5388 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5389 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5390 <= HOST_BITS_PER_WIDE_INT)
5391 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5392 & ~ (((unsigned HOST_WIDE_INT)
5393 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5397 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5399 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5400 return expand_compound_operation (temp);
5404 /* If we reach here, we want to return a pair of shifts. The inner
5405 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5406 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5407 logical depending on the value of UNSIGNEDP.
5409 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5410 converted into an AND of a shift.
5412 We must check for the case where the left shift would have a negative
5413 count. This can happen in a case like (x >> 31) & 255 on machines
5414 that can't shift by a constant. On those machines, we would first
5415 combine the shift with the AND to produce a variable-position
5416 extraction. Then the constant of 31 would be substituted in to produce
5417 a such a position. */
5419 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5420 if (modewidth >= pos - len)
5421 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5423 simplify_shift_const (NULL_RTX, ASHIFT,
5426 modewidth - pos - len),
5429 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5430 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5431 simplify_shift_const (NULL_RTX, LSHIFTRT,
5434 ((HOST_WIDE_INT) 1 << len) - 1);
5436 /* Any other cases we can't handle. */
5440 /* If we couldn't do this for some reason, return the original
5442 if (GET_CODE (tem) == CLOBBER)
5448 /* X is a SET which contains an assignment of one object into
5449 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5450 or certain SUBREGS). If possible, convert it into a series of
5453 We half-heartedly support variable positions, but do not at all
5454 support variable lengths. */
5457 expand_field_assignment (x)
5461 rtx pos; /* Always counts from low bit. */
5464 enum machine_mode compute_mode;
5466 /* Loop until we find something we can't simplify. */
5469 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5470 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5472 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5473 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5474 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5476 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5477 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5479 inner = XEXP (SET_DEST (x), 0);
5480 len = INTVAL (XEXP (SET_DEST (x), 1));
5481 pos = XEXP (SET_DEST (x), 2);
5483 /* If the position is constant and spans the width of INNER,
5484 surround INNER with a USE to indicate this. */
5485 if (GET_CODE (pos) == CONST_INT
5486 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5487 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5489 if (BITS_BIG_ENDIAN)
5491 if (GET_CODE (pos) == CONST_INT)
5492 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5494 else if (GET_CODE (pos) == MINUS
5495 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5496 && (INTVAL (XEXP (pos, 1))
5497 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5498 /* If position is ADJUST - X, new position is X. */
5499 pos = XEXP (pos, 0);
5501 pos = gen_binary (MINUS, GET_MODE (pos),
5502 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5508 /* A SUBREG between two modes that occupy the same numbers of words
5509 can be done by moving the SUBREG to the source. */
5510 else if (GET_CODE (SET_DEST (x)) == SUBREG
5511 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5512 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5513 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5514 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5516 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5517 gen_lowpart_for_combine
5518 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5525 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5526 inner = SUBREG_REG (inner);
5528 compute_mode = GET_MODE (inner);
5530 /* Don't attempt bitwise arithmetic on non-integral modes. */
5531 if (! INTEGRAL_MODE_P (compute_mode))
5533 enum machine_mode imode;
5535 /* Something is probably seriously wrong if this matches. */
5536 if (! FLOAT_MODE_P (compute_mode))
5539 /* Try to find an integral mode to pun with. */
5540 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5541 if (imode == BLKmode)
5544 compute_mode = imode;
5545 inner = gen_lowpart_for_combine (imode, inner);
5548 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5549 if (len < HOST_BITS_PER_WIDE_INT)
5550 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5554 /* Now compute the equivalent expression. Make a copy of INNER
5555 for the SET_DEST in case it is a MEM into which we will substitute;
5556 we don't want shared RTL in that case. */
5558 (VOIDmode, copy_rtx (inner),
5559 gen_binary (IOR, compute_mode,
5560 gen_binary (AND, compute_mode,
5561 gen_unary (NOT, compute_mode,
5567 gen_binary (ASHIFT, compute_mode,
5568 gen_binary (AND, compute_mode,
5569 gen_lowpart_for_combine
5570 (compute_mode, SET_SRC (x)),
5578 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5579 it is an RTX that represents a variable starting position; otherwise,
5580 POS is the (constant) starting bit position (counted from the LSB).
5582 INNER may be a USE. This will occur when we started with a bitfield
5583 that went outside the boundary of the object in memory, which is
5584 allowed on most machines. To isolate this case, we produce a USE
5585 whose mode is wide enough and surround the MEM with it. The only
5586 code that understands the USE is this routine. If it is not removed,
5587 it will cause the resulting insn not to match.
5589 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5592 IN_DEST is non-zero if this is a reference in the destination of a
5593 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5594 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5597 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5598 ZERO_EXTRACT should be built even for bits starting at bit 0.
5600 MODE is the desired mode of the result (if IN_DEST == 0).
5602 The result is an RTX for the extraction or NULL_RTX if the target
5606 make_extraction (mode, inner, pos, pos_rtx, len,
5607 unsignedp, in_dest, in_compare)
5608 enum machine_mode mode;
5614 int in_dest, in_compare;
5616 /* This mode describes the size of the storage area
5617 to fetch the overall value from. Within that, we
5618 ignore the POS lowest bits, etc. */
5619 enum machine_mode is_mode = GET_MODE (inner);
5620 enum machine_mode inner_mode;
5621 enum machine_mode wanted_inner_mode = byte_mode;
5622 enum machine_mode wanted_inner_reg_mode = word_mode;
5623 enum machine_mode pos_mode = word_mode;
5624 enum machine_mode extraction_mode = word_mode;
5625 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5628 rtx orig_pos_rtx = pos_rtx;
5631 /* Get some information about INNER and get the innermost object. */
5632 if (GET_CODE (inner) == USE)
5633 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5634 /* We don't need to adjust the position because we set up the USE
5635 to pretend that it was a full-word object. */
5636 spans_byte = 1, inner = XEXP (inner, 0);
5637 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5639 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5640 consider just the QI as the memory to extract from.
5641 The subreg adds or removes high bits; its mode is
5642 irrelevant to the meaning of this extraction,
5643 since POS and LEN count from the lsb. */
5644 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5645 is_mode = GET_MODE (SUBREG_REG (inner));
5646 inner = SUBREG_REG (inner);
5649 inner_mode = GET_MODE (inner);
5651 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5652 pos = INTVAL (pos_rtx), pos_rtx = 0;
5654 /* See if this can be done without an extraction. We never can if the
5655 width of the field is not the same as that of some integer mode. For
5656 registers, we can only avoid the extraction if the position is at the
5657 low-order bit and this is either not in the destination or we have the
5658 appropriate STRICT_LOW_PART operation available.
5660 For MEM, we can avoid an extract if the field starts on an appropriate
5661 boundary and we can change the mode of the memory reference. However,
5662 we cannot directly access the MEM if we have a USE and the underlying
5663 MEM is not TMODE. This combination means that MEM was being used in a
5664 context where bits outside its mode were being referenced; that is only
5665 valid in bit-field insns. */
5667 if (tmode != BLKmode
5668 && ! (spans_byte && inner_mode != tmode)
5669 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5670 && GET_CODE (inner) != MEM
5672 || (GET_CODE (inner) == REG
5673 && (movstrict_optab->handlers[(int) tmode].insn_code
5674 != CODE_FOR_nothing))))
5675 || (GET_CODE (inner) == MEM && pos_rtx == 0
5677 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5678 : BITS_PER_UNIT)) == 0
5679 /* We can't do this if we are widening INNER_MODE (it
5680 may not be aligned, for one thing). */
5681 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5682 && (inner_mode == tmode
5683 || (! mode_dependent_address_p (XEXP (inner, 0))
5684 && ! MEM_VOLATILE_P (inner))))))
5686 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5687 field. If the original and current mode are the same, we need not
5688 adjust the offset. Otherwise, we do if bytes big endian.
5690 If INNER is not a MEM, get a piece consisting of just the field
5691 of interest (in this case POS % BITS_PER_WORD must be 0). */
5693 if (GET_CODE (inner) == MEM)
5696 /* POS counts from lsb, but make OFFSET count in memory order. */
5697 if (BYTES_BIG_ENDIAN)
5698 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5700 offset = pos / BITS_PER_UNIT;
5702 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5703 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5704 MEM_COPY_ATTRIBUTES (new, inner);
5706 else if (GET_CODE (inner) == REG)
5708 /* We can't call gen_lowpart_for_combine here since we always want
5709 a SUBREG and it would sometimes return a new hard register. */
5710 if (tmode != inner_mode)
5711 new = gen_rtx_SUBREG (tmode, inner,
5713 && (GET_MODE_SIZE (inner_mode)
5715 ? (((GET_MODE_SIZE (inner_mode)
5716 - GET_MODE_SIZE (tmode))
5718 - pos / BITS_PER_WORD)
5719 : pos / BITS_PER_WORD));
5724 new = force_to_mode (inner, tmode,
5725 len >= HOST_BITS_PER_WIDE_INT
5726 ? GET_MODE_MASK (tmode)
5727 : ((HOST_WIDE_INT) 1 << len) - 1,
5730 /* If this extraction is going into the destination of a SET,
5731 make a STRICT_LOW_PART unless we made a MEM. */
5734 return (GET_CODE (new) == MEM ? new
5735 : (GET_CODE (new) != SUBREG
5736 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5737 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5739 /* Otherwise, sign- or zero-extend unless we already are in the
5742 return (mode == tmode ? new
5743 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5747 /* Unless this is a COMPARE or we have a funny memory reference,
5748 don't do anything with zero-extending field extracts starting at
5749 the low-order bit since they are simple AND operations. */
5750 if (pos_rtx == 0 && pos == 0 && ! in_dest
5751 && ! in_compare && ! spans_byte && unsignedp)
5754 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5755 we would be spanning bytes or if the position is not a constant and the
5756 length is not 1. In all other cases, we would only be going outside
5757 our object in cases when an original shift would have been
5759 if (! spans_byte && GET_CODE (inner) == MEM
5760 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5761 || (pos_rtx != 0 && len != 1)))
5764 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5765 and the mode for the result. */
5769 wanted_inner_reg_mode
5770 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
5771 if (wanted_inner_reg_mode == VOIDmode)
5772 wanted_inner_reg_mode = word_mode;
5774 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
5775 if (pos_mode == VOIDmode)
5776 pos_mode = word_mode;
5778 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
5779 if (extraction_mode == VOIDmode)
5780 extraction_mode = word_mode;
5785 if (! in_dest && unsignedp)
5787 wanted_inner_reg_mode
5788 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
5789 if (wanted_inner_reg_mode == VOIDmode)
5790 wanted_inner_reg_mode = word_mode;
5792 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
5793 if (pos_mode == VOIDmode)
5794 pos_mode = word_mode;
5796 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
5797 if (extraction_mode == VOIDmode)
5798 extraction_mode = word_mode;
5803 if (! in_dest && ! unsignedp)
5805 wanted_inner_reg_mode
5806 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
5807 if (wanted_inner_reg_mode == VOIDmode)
5808 wanted_inner_reg_mode = word_mode;
5810 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
5811 if (pos_mode == VOIDmode)
5812 pos_mode = word_mode;
5814 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
5815 if (extraction_mode == VOIDmode)
5816 extraction_mode = word_mode;
5820 /* Never narrow an object, since that might not be safe. */
5822 if (mode != VOIDmode
5823 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5824 extraction_mode = mode;
5826 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5827 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5828 pos_mode = GET_MODE (pos_rtx);
5830 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5831 if we have to change the mode of memory and cannot, the desired mode is
5833 if (GET_CODE (inner) != MEM)
5834 wanted_inner_mode = wanted_inner_reg_mode;
5835 else if (inner_mode != wanted_inner_mode
5836 && (mode_dependent_address_p (XEXP (inner, 0))
5837 || MEM_VOLATILE_P (inner)))
5838 wanted_inner_mode = extraction_mode;
5842 if (BITS_BIG_ENDIAN)
5844 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5845 BITS_BIG_ENDIAN style. If position is constant, compute new
5846 position. Otherwise, build subtraction.
5847 Note that POS is relative to the mode of the original argument.
5848 If it's a MEM we need to recompute POS relative to that.
5849 However, if we're extracting from (or inserting into) a register,
5850 we want to recompute POS relative to wanted_inner_mode. */
5851 int width = (GET_CODE (inner) == MEM
5852 ? GET_MODE_BITSIZE (is_mode)
5853 : GET_MODE_BITSIZE (wanted_inner_mode));
5856 pos = width - len - pos;
5859 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5860 GEN_INT (width - len), pos_rtx);
5861 /* POS may be less than 0 now, but we check for that below.
5862 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5865 /* If INNER has a wider mode, make it smaller. If this is a constant
5866 extract, try to adjust the byte to point to the byte containing
5868 if (wanted_inner_mode != VOIDmode
5869 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5870 && ((GET_CODE (inner) == MEM
5871 && (inner_mode == wanted_inner_mode
5872 || (! mode_dependent_address_p (XEXP (inner, 0))
5873 && ! MEM_VOLATILE_P (inner))))))
5877 /* The computations below will be correct if the machine is big
5878 endian in both bits and bytes or little endian in bits and bytes.
5879 If it is mixed, we must adjust. */
5881 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5882 adjust OFFSET to compensate. */
5883 if (BYTES_BIG_ENDIAN
5885 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5886 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5888 /* If this is a constant position, we can move to the desired byte. */
5891 offset += pos / BITS_PER_UNIT;
5892 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5895 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5897 && is_mode != wanted_inner_mode)
5898 offset = (GET_MODE_SIZE (is_mode)
5899 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5901 if (offset != 0 || inner_mode != wanted_inner_mode)
5903 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5904 plus_constant (XEXP (inner, 0), offset));
5905 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5906 MEM_COPY_ATTRIBUTES (newmem, inner);
5911 /* If INNER is not memory, we can always get it into the proper mode. If we
5912 are changing its mode, POS must be a constant and smaller than the size
5914 else if (GET_CODE (inner) != MEM)
5916 if (GET_MODE (inner) != wanted_inner_mode
5918 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5921 inner = force_to_mode (inner, wanted_inner_mode,
5923 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5924 ? GET_MODE_MASK (wanted_inner_mode)
5925 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5929 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5930 have to zero extend. Otherwise, we can just use a SUBREG. */
5932 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5933 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5934 else if (pos_rtx != 0
5935 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5936 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5938 /* Make POS_RTX unless we already have it and it is correct. If we don't
5939 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5941 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5942 pos_rtx = orig_pos_rtx;
5944 else if (pos_rtx == 0)
5945 pos_rtx = GEN_INT (pos);
5947 /* Make the required operation. See if we can use existing rtx. */
5948 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5949 extraction_mode, inner, GEN_INT (len), pos_rtx);
5951 new = gen_lowpart_for_combine (mode, new);
5956 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5957 with any other operations in X. Return X without that shift if so. */
5960 extract_left_shift (x, count)
5964 enum rtx_code code = GET_CODE (x);
5965 enum machine_mode mode = GET_MODE (x);
5971 /* This is the shift itself. If it is wide enough, we will return
5972 either the value being shifted if the shift count is equal to
5973 COUNT or a shift for the difference. */
5974 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5975 && INTVAL (XEXP (x, 1)) >= count)
5976 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5977 INTVAL (XEXP (x, 1)) - count);
5981 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5982 return gen_unary (code, mode, mode, tem);
5986 case PLUS: case IOR: case XOR: case AND:
5987 /* If we can safely shift this constant and we find the inner shift,
5988 make a new operation. */
5989 if (GET_CODE (XEXP (x,1)) == CONST_INT
5990 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
5991 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5992 return gen_binary (code, mode, tem,
5993 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6004 /* Look at the expression rooted at X. Look for expressions
6005 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6006 Form these expressions.
6008 Return the new rtx, usually just X.
6010 Also, for machines like the Vax that don't have logical shift insns,
6011 try to convert logical to arithmetic shift operations in cases where
6012 they are equivalent. This undoes the canonicalizations to logical
6013 shifts done elsewhere.
6015 We try, as much as possible, to re-use rtl expressions to save memory.
6017 IN_CODE says what kind of expression we are processing. Normally, it is
6018 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6019 being kludges), it is MEM. When processing the arguments of a comparison
6020 or a COMPARE against zero, it is COMPARE. */
6023 make_compound_operation (x, in_code)
6025 enum rtx_code in_code;
6027 enum rtx_code code = GET_CODE (x);
6028 enum machine_mode mode = GET_MODE (x);
6029 int mode_width = GET_MODE_BITSIZE (mode);
6031 enum rtx_code next_code;
6037 /* Select the code to be used in recursive calls. Once we are inside an
6038 address, we stay there. If we have a comparison, set to COMPARE,
6039 but once inside, go back to our default of SET. */
6041 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6042 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6043 && XEXP (x, 1) == const0_rtx) ? COMPARE
6044 : in_code == COMPARE ? SET : in_code);
6046 /* Process depending on the code of this operation. If NEW is set
6047 non-zero, it will be returned. */
6052 /* Convert shifts by constants into multiplications if inside
6054 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6055 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6056 && INTVAL (XEXP (x, 1)) >= 0)
6058 new = make_compound_operation (XEXP (x, 0), next_code);
6059 new = gen_rtx_combine (MULT, mode, new,
6060 GEN_INT ((HOST_WIDE_INT) 1
6061 << INTVAL (XEXP (x, 1))));
6066 /* If the second operand is not a constant, we can't do anything
6068 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6071 /* If the constant is a power of two minus one and the first operand
6072 is a logical right shift, make an extraction. */
6073 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6074 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6076 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6077 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6078 0, in_code == COMPARE);
6081 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6082 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6083 && subreg_lowpart_p (XEXP (x, 0))
6084 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6085 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6087 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6089 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6090 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6091 0, in_code == COMPARE);
6093 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6094 else if ((GET_CODE (XEXP (x, 0)) == XOR
6095 || GET_CODE (XEXP (x, 0)) == IOR)
6096 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6097 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6098 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6100 /* Apply the distributive law, and then try to make extractions. */
6101 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6102 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6104 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6106 new = make_compound_operation (new, in_code);
6109 /* If we are have (and (rotate X C) M) and C is larger than the number
6110 of bits in M, this is an extraction. */
6112 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6113 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6114 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6115 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6117 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6118 new = make_extraction (mode, new,
6119 (GET_MODE_BITSIZE (mode)
6120 - INTVAL (XEXP (XEXP (x, 0), 1))),
6121 NULL_RTX, i, 1, 0, in_code == COMPARE);
6124 /* On machines without logical shifts, if the operand of the AND is
6125 a logical shift and our mask turns off all the propagated sign
6126 bits, we can replace the logical shift with an arithmetic shift. */
6127 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6128 && (lshr_optab->handlers[(int) mode].insn_code
6129 == CODE_FOR_nothing)
6130 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6131 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6132 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6133 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6134 && mode_width <= HOST_BITS_PER_WIDE_INT)
6136 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6138 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6139 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6141 gen_rtx_combine (ASHIFTRT, mode,
6142 make_compound_operation (XEXP (XEXP (x, 0), 0),
6144 XEXP (XEXP (x, 0), 1)));
6147 /* If the constant is one less than a power of two, this might be
6148 representable by an extraction even if no shift is present.
6149 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6150 we are in a COMPARE. */
6151 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6152 new = make_extraction (mode,
6153 make_compound_operation (XEXP (x, 0),
6155 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6157 /* If we are in a comparison and this is an AND with a power of two,
6158 convert this into the appropriate bit extract. */
6159 else if (in_code == COMPARE
6160 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6161 new = make_extraction (mode,
6162 make_compound_operation (XEXP (x, 0),
6164 i, NULL_RTX, 1, 1, 0, 1);
6169 /* If the sign bit is known to be zero, replace this with an
6170 arithmetic shift. */
6171 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6172 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6173 && mode_width <= HOST_BITS_PER_WIDE_INT
6174 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6176 new = gen_rtx_combine (ASHIFTRT, mode,
6177 make_compound_operation (XEXP (x, 0),
6183 /* ... fall through ... */
6189 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6190 this is a SIGN_EXTRACT. */
6191 if (GET_CODE (rhs) == CONST_INT
6192 && GET_CODE (lhs) == ASHIFT
6193 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6194 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6196 new = make_compound_operation (XEXP (lhs, 0), next_code);
6197 new = make_extraction (mode, new,
6198 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6199 NULL_RTX, mode_width - INTVAL (rhs),
6200 code == LSHIFTRT, 0, in_code == COMPARE);
6203 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6204 If so, try to merge the shifts into a SIGN_EXTEND. We could
6205 also do this for some cases of SIGN_EXTRACT, but it doesn't
6206 seem worth the effort; the case checked for occurs on Alpha. */
6208 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6209 && ! (GET_CODE (lhs) == SUBREG
6210 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6211 && GET_CODE (rhs) == CONST_INT
6212 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6213 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6214 new = make_extraction (mode, make_compound_operation (new, next_code),
6215 0, NULL_RTX, mode_width - INTVAL (rhs),
6216 code == LSHIFTRT, 0, in_code == COMPARE);
6221 /* Call ourselves recursively on the inner expression. If we are
6222 narrowing the object and it has a different RTL code from
6223 what it originally did, do this SUBREG as a force_to_mode. */
6225 tem = make_compound_operation (SUBREG_REG (x), in_code);
6226 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6227 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6228 && subreg_lowpart_p (x))
6230 rtx newer = force_to_mode (tem, mode,
6231 GET_MODE_MASK (mode), NULL_RTX, 0);
6233 /* If we have something other than a SUBREG, we might have
6234 done an expansion, so rerun outselves. */
6235 if (GET_CODE (newer) != SUBREG)
6236 newer = make_compound_operation (newer, in_code);
6241 /* If this is a paradoxical subreg, and the new code is a sign or
6242 zero extension, omit the subreg and widen the extension. If it
6243 is a regular subreg, we can still get rid of the subreg by not
6244 widening so much, or in fact removing the extension entirely. */
6245 if ((GET_CODE (tem) == SIGN_EXTEND
6246 || GET_CODE (tem) == ZERO_EXTEND)
6247 && subreg_lowpart_p (x))
6249 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6250 || (GET_MODE_SIZE (mode) >
6251 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6252 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6254 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6265 x = gen_lowpart_for_combine (mode, new);
6266 code = GET_CODE (x);
6269 /* Now recursively process each operand of this operation. */
6270 fmt = GET_RTX_FORMAT (code);
6271 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6274 new = make_compound_operation (XEXP (x, i), next_code);
6275 SUBST (XEXP (x, i), new);
6281 /* Given M see if it is a value that would select a field of bits
6282 within an item, but not the entire word. Return -1 if not.
6283 Otherwise, return the starting position of the field, where 0 is the
6286 *PLEN is set to the length of the field. */
6289 get_pos_from_mask (m, plen)
6290 unsigned HOST_WIDE_INT m;
6293 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6294 int pos = exact_log2 (m & - m);
6299 /* Now shift off the low-order zero bits and see if we have a power of
6301 *plen = exact_log2 ((m >> pos) + 1);
6309 /* See if X can be simplified knowing that we will only refer to it in
6310 MODE and will only refer to those bits that are nonzero in MASK.
6311 If other bits are being computed or if masking operations are done
6312 that select a superset of the bits in MASK, they can sometimes be
6315 Return a possibly simplified expression, but always convert X to
6316 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6318 Also, if REG is non-zero and X is a register equal in value to REG,
6321 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6322 are all off in X. This is used when X will be complemented, by either
6323 NOT, NEG, or XOR. */
6326 force_to_mode (x, mode, mask, reg, just_select)
6328 enum machine_mode mode;
6329 unsigned HOST_WIDE_INT mask;
6333 enum rtx_code code = GET_CODE (x);
6334 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6335 enum machine_mode op_mode;
6336 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6339 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6340 code below will do the wrong thing since the mode of such an
6341 expression is VOIDmode.
6343 Also do nothing if X is a CLOBBER; this can happen if X was
6344 the return value from a call to gen_lowpart_for_combine. */
6345 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6348 /* We want to perform the operation is its present mode unless we know
6349 that the operation is valid in MODE, in which case we do the operation
6351 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6352 && code_to_optab[(int) code] != 0
6353 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6354 != CODE_FOR_nothing))
6355 ? mode : GET_MODE (x));
6357 /* It is not valid to do a right-shift in a narrower mode
6358 than the one it came in with. */
6359 if ((code == LSHIFTRT || code == ASHIFTRT)
6360 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6361 op_mode = GET_MODE (x);
6363 /* Truncate MASK to fit OP_MODE. */
6365 mask &= GET_MODE_MASK (op_mode);
6367 /* When we have an arithmetic operation, or a shift whose count we
6368 do not know, we need to assume that all bit the up to the highest-order
6369 bit in MASK will be needed. This is how we form such a mask. */
6371 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6372 ? GET_MODE_MASK (op_mode)
6373 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6375 fuller_mask = ~ (HOST_WIDE_INT) 0;
6377 /* Determine what bits of X are guaranteed to be (non)zero. */
6378 nonzero = nonzero_bits (x, mode);
6380 /* If none of the bits in X are needed, return a zero. */
6381 if (! just_select && (nonzero & mask) == 0)
6384 /* If X is a CONST_INT, return a new one. Do this here since the
6385 test below will fail. */
6386 if (GET_CODE (x) == CONST_INT)
6388 HOST_WIDE_INT cval = INTVAL (x) & mask;
6389 int width = GET_MODE_BITSIZE (mode);
6391 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6392 number, sign extend it. */
6393 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6394 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6395 cval |= (HOST_WIDE_INT) -1 << width;
6397 return GEN_INT (cval);
6400 /* If X is narrower than MODE and we want all the bits in X's mode, just
6401 get X in the proper mode. */
6402 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6403 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6404 return gen_lowpart_for_combine (mode, x);
6406 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6407 MASK are already known to be zero in X, we need not do anything. */
6408 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6414 /* If X is a (clobber (const_int)), return it since we know we are
6415 generating something that won't match. */
6419 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6420 spanned the boundary of the MEM. If we are now masking so it is
6421 within that boundary, we don't need the USE any more. */
6422 if (! BITS_BIG_ENDIAN
6423 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6424 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6431 x = expand_compound_operation (x);
6432 if (GET_CODE (x) != code)
6433 return force_to_mode (x, mode, mask, reg, next_select);
6437 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6438 || rtx_equal_p (reg, get_last_value (x))))
6443 if (subreg_lowpart_p (x)
6444 /* We can ignore the effect of this SUBREG if it narrows the mode or
6445 if the constant masks to zero all the bits the mode doesn't
6447 && ((GET_MODE_SIZE (GET_MODE (x))
6448 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6450 & GET_MODE_MASK (GET_MODE (x))
6451 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6452 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6456 /* If this is an AND with a constant, convert it into an AND
6457 whose constant is the AND of that constant with MASK. If it
6458 remains an AND of MASK, delete it since it is redundant. */
6460 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6462 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6463 mask & INTVAL (XEXP (x, 1)));
6465 /* If X is still an AND, see if it is an AND with a mask that
6466 is just some low-order bits. If so, and it is MASK, we don't
6469 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6470 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6473 /* If it remains an AND, try making another AND with the bits
6474 in the mode mask that aren't in MASK turned on. If the
6475 constant in the AND is wide enough, this might make a
6476 cheaper constant. */
6478 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6479 && GET_MODE_MASK (GET_MODE (x)) != mask
6480 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6482 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6483 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6484 int width = GET_MODE_BITSIZE (GET_MODE (x));
6487 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6488 number, sign extend it. */
6489 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6490 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6491 cval |= (HOST_WIDE_INT) -1 << width;
6493 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6494 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6504 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6505 low-order bits (as in an alignment operation) and FOO is already
6506 aligned to that boundary, mask C1 to that boundary as well.
6507 This may eliminate that PLUS and, later, the AND. */
6510 int width = GET_MODE_BITSIZE (mode);
6511 unsigned HOST_WIDE_INT smask = mask;
6513 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6514 number, sign extend it. */
6516 if (width < HOST_BITS_PER_WIDE_INT
6517 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6518 smask |= (HOST_WIDE_INT) -1 << width;
6520 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6521 && exact_log2 (- smask) >= 0)
6525 && (XEXP (x, 0) == stack_pointer_rtx
6526 || XEXP (x, 0) == frame_pointer_rtx))
6528 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6529 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6531 sp_mask &= ~ (sp_alignment - 1);
6532 if ((sp_mask & ~ smask) == 0
6533 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6534 return force_to_mode (plus_constant (XEXP (x, 0),
6535 ((INTVAL (XEXP (x, 1)) -
6536 STACK_BIAS) & smask)
6538 mode, smask, reg, next_select);
6541 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6542 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6543 return force_to_mode (plus_constant (XEXP (x, 0),
6544 (INTVAL (XEXP (x, 1))
6546 mode, smask, reg, next_select);
6550 /* ... fall through ... */
6554 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6555 most significant bit in MASK since carries from those bits will
6556 affect the bits we are interested in. */
6562 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6563 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6564 operation which may be a bitfield extraction. Ensure that the
6565 constant we form is not wider than the mode of X. */
6567 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6568 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6569 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6570 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6571 && GET_CODE (XEXP (x, 1)) == CONST_INT
6572 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6573 + floor_log2 (INTVAL (XEXP (x, 1))))
6574 < GET_MODE_BITSIZE (GET_MODE (x)))
6575 && (INTVAL (XEXP (x, 1))
6576 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6578 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6579 << INTVAL (XEXP (XEXP (x, 0), 1)));
6580 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6581 XEXP (XEXP (x, 0), 0), temp);
6582 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6583 XEXP (XEXP (x, 0), 1));
6584 return force_to_mode (x, mode, mask, reg, next_select);
6588 /* For most binary operations, just propagate into the operation and
6589 change the mode if we have an operation of that mode. */
6591 op0 = gen_lowpart_for_combine (op_mode,
6592 force_to_mode (XEXP (x, 0), mode, mask,
6594 op1 = gen_lowpart_for_combine (op_mode,
6595 force_to_mode (XEXP (x, 1), mode, mask,
6598 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6599 MASK since OP1 might have been sign-extended but we never want
6600 to turn on extra bits, since combine might have previously relied
6601 on them being off. */
6602 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6603 && (INTVAL (op1) & mask) != 0)
6604 op1 = GEN_INT (INTVAL (op1) & mask);
6606 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6607 x = gen_binary (code, op_mode, op0, op1);
6611 /* For left shifts, do the same, but just for the first operand.
6612 However, we cannot do anything with shifts where we cannot
6613 guarantee that the counts are smaller than the size of the mode
6614 because such a count will have a different meaning in a
6617 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6618 && INTVAL (XEXP (x, 1)) >= 0
6619 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6620 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6621 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6622 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6625 /* If the shift count is a constant and we can do arithmetic in
6626 the mode of the shift, refine which bits we need. Otherwise, use the
6627 conservative form of the mask. */
6628 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6629 && INTVAL (XEXP (x, 1)) >= 0
6630 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6631 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6632 mask >>= INTVAL (XEXP (x, 1));
6636 op0 = gen_lowpart_for_combine (op_mode,
6637 force_to_mode (XEXP (x, 0), op_mode,
6638 mask, reg, next_select));
6640 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6641 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6645 /* Here we can only do something if the shift count is a constant,
6646 this shift constant is valid for the host, and we can do arithmetic
6649 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6650 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6651 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6653 rtx inner = XEXP (x, 0);
6655 /* Select the mask of the bits we need for the shift operand. */
6656 mask <<= INTVAL (XEXP (x, 1));
6658 /* We can only change the mode of the shift if we can do arithmetic
6659 in the mode of the shift and MASK is no wider than the width of
6661 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6662 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6663 op_mode = GET_MODE (x);
6665 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6667 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6668 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6671 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6672 shift and AND produces only copies of the sign bit (C2 is one less
6673 than a power of two), we can do this with just a shift. */
6675 if (GET_CODE (x) == LSHIFTRT
6676 && GET_CODE (XEXP (x, 1)) == CONST_INT
6677 && ((INTVAL (XEXP (x, 1))
6678 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6679 >= GET_MODE_BITSIZE (GET_MODE (x)))
6680 && exact_log2 (mask + 1) >= 0
6681 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6682 >= exact_log2 (mask + 1)))
6683 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6684 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6685 - exact_log2 (mask + 1)));
6690 /* If we are just looking for the sign bit, we don't need this shift at
6691 all, even if it has a variable count. */
6692 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6693 && (mask == ((unsigned HOST_WIDE_INT) 1
6694 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6695 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6697 /* If this is a shift by a constant, get a mask that contains those bits
6698 that are not copies of the sign bit. We then have two cases: If
6699 MASK only includes those bits, this can be a logical shift, which may
6700 allow simplifications. If MASK is a single-bit field not within
6701 those bits, we are requesting a copy of the sign bit and hence can
6702 shift the sign bit to the appropriate location. */
6704 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6705 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6709 /* If the considered data is wider then HOST_WIDE_INT, we can't
6710 represent a mask for all its bits in a single scalar.
6711 But we only care about the lower bits, so calculate these. */
6713 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6715 nonzero = ~ (HOST_WIDE_INT) 0;
6717 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6718 is the number of bits a full-width mask would have set.
6719 We need only shift if these are fewer than nonzero can
6720 hold. If not, we must keep all bits set in nonzero. */
6722 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6723 < HOST_BITS_PER_WIDE_INT)
6724 nonzero >>= INTVAL (XEXP (x, 1))
6725 + HOST_BITS_PER_WIDE_INT
6726 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6730 nonzero = GET_MODE_MASK (GET_MODE (x));
6731 nonzero >>= INTVAL (XEXP (x, 1));
6734 if ((mask & ~ nonzero) == 0
6735 || (i = exact_log2 (mask)) >= 0)
6737 x = simplify_shift_const
6738 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6739 i < 0 ? INTVAL (XEXP (x, 1))
6740 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6742 if (GET_CODE (x) != ASHIFTRT)
6743 return force_to_mode (x, mode, mask, reg, next_select);
6747 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6748 even if the shift count isn't a constant. */
6750 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6754 /* If this is a zero- or sign-extension operation that just affects bits
6755 we don't care about, remove it. Be sure the call above returned
6756 something that is still a shift. */
6758 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6759 && GET_CODE (XEXP (x, 1)) == CONST_INT
6760 && INTVAL (XEXP (x, 1)) >= 0
6761 && (INTVAL (XEXP (x, 1))
6762 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6763 && GET_CODE (XEXP (x, 0)) == ASHIFT
6764 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6765 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6766 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6773 /* If the shift count is constant and we can do computations
6774 in the mode of X, compute where the bits we care about are.
6775 Otherwise, we can't do anything. Don't change the mode of
6776 the shift or propagate MODE into the shift, though. */
6777 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6778 && INTVAL (XEXP (x, 1)) >= 0)
6780 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6781 GET_MODE (x), GEN_INT (mask),
6783 if (temp && GET_CODE(temp) == CONST_INT)
6785 force_to_mode (XEXP (x, 0), GET_MODE (x),
6786 INTVAL (temp), reg, next_select));
6791 /* If we just want the low-order bit, the NEG isn't needed since it
6792 won't change the low-order bit. */
6794 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6796 /* We need any bits less significant than the most significant bit in
6797 MASK since carries from those bits will affect the bits we are
6803 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6804 same as the XOR case above. Ensure that the constant we form is not
6805 wider than the mode of X. */
6807 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6808 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6809 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6810 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6811 < GET_MODE_BITSIZE (GET_MODE (x)))
6812 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6814 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6815 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6816 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6818 return force_to_mode (x, mode, mask, reg, next_select);
6821 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6822 use the full mask inside the NOT. */
6826 op0 = gen_lowpart_for_combine (op_mode,
6827 force_to_mode (XEXP (x, 0), mode, mask,
6829 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6830 x = gen_unary (code, op_mode, op_mode, op0);
6834 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6835 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6836 which is equal to STORE_FLAG_VALUE. */
6837 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6838 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6839 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6840 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6845 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6846 written in a narrower mode. We play it safe and do not do so. */
6849 gen_lowpart_for_combine (GET_MODE (x),
6850 force_to_mode (XEXP (x, 1), mode,
6851 mask, reg, next_select)));
6853 gen_lowpart_for_combine (GET_MODE (x),
6854 force_to_mode (XEXP (x, 2), mode,
6855 mask, reg,next_select)));
6862 /* Ensure we return a value of the proper mode. */
6863 return gen_lowpart_for_combine (mode, x);
6866 /* Return nonzero if X is an expression that has one of two values depending on
6867 whether some other value is zero or nonzero. In that case, we return the
6868 value that is being tested, *PTRUE is set to the value if the rtx being
6869 returned has a nonzero value, and *PFALSE is set to the other alternative.
6871 If we return zero, we set *PTRUE and *PFALSE to X. */
6874 if_then_else_cond (x, ptrue, pfalse)
6876 rtx *ptrue, *pfalse;
6878 enum machine_mode mode = GET_MODE (x);
6879 enum rtx_code code = GET_CODE (x);
6880 int size = GET_MODE_BITSIZE (mode);
6881 rtx cond0, cond1, true0, true1, false0, false1;
6882 unsigned HOST_WIDE_INT nz;
6884 /* If this is a unary operation whose operand has one of two values, apply
6885 our opcode to compute those values. */
6886 if (GET_RTX_CLASS (code) == '1'
6887 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6889 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6890 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6894 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6895 make can't possibly match and would suppress other optimizations. */
6896 else if (code == COMPARE)
6899 /* If this is a binary operation, see if either side has only one of two
6900 values. If either one does or if both do and they are conditional on
6901 the same value, compute the new true and false values. */
6902 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6903 || GET_RTX_CLASS (code) == '<')
6905 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6906 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6908 if ((cond0 != 0 || cond1 != 0)
6909 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6911 /* If if_then_else_cond returned zero, then true/false are the
6912 same rtl. We must copy one of them to prevent invalid rtl
6915 true0 = copy_rtx (true0);
6916 else if (cond1 == 0)
6917 true1 = copy_rtx (true1);
6919 *ptrue = gen_binary (code, mode, true0, true1);
6920 *pfalse = gen_binary (code, mode, false0, false1);
6921 return cond0 ? cond0 : cond1;
6924 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6925 operands is zero when the other is non-zero, and vice-versa,
6926 and STORE_FLAG_VALUE is 1 or -1. */
6928 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6929 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6931 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6933 rtx op0 = XEXP (XEXP (x, 0), 1);
6934 rtx op1 = XEXP (XEXP (x, 1), 1);
6936 cond0 = XEXP (XEXP (x, 0), 0);
6937 cond1 = XEXP (XEXP (x, 1), 0);
6939 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6940 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6941 && reversible_comparison_p (cond1)
6942 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6943 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6944 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6945 || ((swap_condition (GET_CODE (cond0))
6946 == reverse_condition (GET_CODE (cond1)))
6947 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6948 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6949 && ! side_effects_p (x))
6951 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6952 *pfalse = gen_binary (MULT, mode,
6954 ? gen_unary (NEG, mode, mode, op1) : op1),
6960 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6962 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6963 && (code == MULT || code == AND || code == UMIN)
6964 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6966 cond0 = XEXP (XEXP (x, 0), 0);
6967 cond1 = XEXP (XEXP (x, 1), 0);
6969 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6970 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6971 && reversible_comparison_p (cond1)
6972 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6973 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6974 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6975 || ((swap_condition (GET_CODE (cond0))
6976 == reverse_condition (GET_CODE (cond1)))
6977 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6978 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6979 && ! side_effects_p (x))
6981 *ptrue = *pfalse = const0_rtx;
6987 else if (code == IF_THEN_ELSE)
6989 /* If we have IF_THEN_ELSE already, extract the condition and
6990 canonicalize it if it is NE or EQ. */
6991 cond0 = XEXP (x, 0);
6992 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6993 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6994 return XEXP (cond0, 0);
6995 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6997 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6998 return XEXP (cond0, 0);
7004 /* If X is a normal SUBREG with both inner and outer modes integral,
7005 we can narrow both the true and false values of the inner expression,
7006 if there is a condition. */
7007 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7008 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7009 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7010 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7013 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7015 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7020 /* If X is a constant, this isn't special and will cause confusions
7021 if we treat it as such. Likewise if it is equivalent to a constant. */
7022 else if (CONSTANT_P (x)
7023 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7026 /* If X is known to be either 0 or -1, those are the true and
7027 false values when testing X. */
7028 else if (num_sign_bit_copies (x, mode) == size)
7030 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7034 /* Likewise for 0 or a single bit. */
7035 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7037 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7041 /* Otherwise fail; show no condition with true and false values the same. */
7042 *ptrue = *pfalse = x;
7046 /* Return the value of expression X given the fact that condition COND
7047 is known to be true when applied to REG as its first operand and VAL
7048 as its second. X is known to not be shared and so can be modified in
7051 We only handle the simplest cases, and specifically those cases that
7052 arise with IF_THEN_ELSE expressions. */
7055 known_cond (x, cond, reg, val)
7060 enum rtx_code code = GET_CODE (x);
7065 if (side_effects_p (x))
7068 if (cond == EQ && rtx_equal_p (x, reg))
7071 /* If X is (abs REG) and we know something about REG's relationship
7072 with zero, we may be able to simplify this. */
7074 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7077 case GE: case GT: case EQ:
7080 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7086 /* The only other cases we handle are MIN, MAX, and comparisons if the
7087 operands are the same as REG and VAL. */
7089 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7091 if (rtx_equal_p (XEXP (x, 0), val))
7092 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7094 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7096 if (GET_RTX_CLASS (code) == '<')
7097 return (comparison_dominates_p (cond, code) ? const_true_rtx
7098 : (comparison_dominates_p (cond,
7099 reverse_condition (code))
7102 else if (code == SMAX || code == SMIN
7103 || code == UMIN || code == UMAX)
7105 int unsignedp = (code == UMIN || code == UMAX);
7107 if (code == SMAX || code == UMAX)
7108 cond = reverse_condition (cond);
7113 return unsignedp ? x : XEXP (x, 1);
7115 return unsignedp ? x : XEXP (x, 0);
7117 return unsignedp ? XEXP (x, 1) : x;
7119 return unsignedp ? XEXP (x, 0) : x;
7127 fmt = GET_RTX_FORMAT (code);
7128 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7131 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7132 else if (fmt[i] == 'E')
7133 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7134 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7141 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7142 assignment as a field assignment. */
7145 rtx_equal_for_field_assignment_p (x, y)
7149 if (x == y || rtx_equal_p (x, y))
7152 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7155 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7156 Note that all SUBREGs of MEM are paradoxical; otherwise they
7157 would have been rewritten. */
7158 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7159 && GET_CODE (SUBREG_REG (y)) == MEM
7160 && rtx_equal_p (SUBREG_REG (y),
7161 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7164 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7165 && GET_CODE (SUBREG_REG (x)) == MEM
7166 && rtx_equal_p (SUBREG_REG (x),
7167 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7170 /* We used to see if get_last_value of X and Y were the same but that's
7171 not correct. In one direction, we'll cause the assignment to have
7172 the wrong destination and in the case, we'll import a register into this
7173 insn that might have already have been dead. So fail if none of the
7174 above cases are true. */
7178 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7179 Return that assignment if so.
7181 We only handle the most common cases. */
7184 make_field_assignment (x)
7187 rtx dest = SET_DEST (x);
7188 rtx src = SET_SRC (x);
7194 enum machine_mode mode;
7196 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7197 a clear of a one-bit field. We will have changed it to
7198 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7201 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7202 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7203 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7204 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7206 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7209 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7213 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7214 && subreg_lowpart_p (XEXP (src, 0))
7215 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7216 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7217 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7218 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7219 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7221 assign = make_extraction (VOIDmode, dest, 0,
7222 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7225 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7229 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7231 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7232 && XEXP (XEXP (src, 0), 0) == const1_rtx
7233 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7235 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7238 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7242 /* The other case we handle is assignments into a constant-position
7243 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7244 a mask that has all one bits except for a group of zero bits and
7245 OTHER is known to have zeros where C1 has ones, this is such an
7246 assignment. Compute the position and length from C1. Shift OTHER
7247 to the appropriate position, force it to the required mode, and
7248 make the extraction. Check for the AND in both operands. */
7250 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7253 rhs = expand_compound_operation (XEXP (src, 0));
7254 lhs = expand_compound_operation (XEXP (src, 1));
7256 if (GET_CODE (rhs) == AND
7257 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7258 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7259 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7260 else if (GET_CODE (lhs) == AND
7261 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7262 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7263 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7267 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7268 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7269 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7270 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7273 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7277 /* The mode to use for the source is the mode of the assignment, or of
7278 what is inside a possible STRICT_LOW_PART. */
7279 mode = (GET_CODE (assign) == STRICT_LOW_PART
7280 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7282 /* Shift OTHER right POS places and make it the source, restricting it
7283 to the proper length and mode. */
7285 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7286 GET_MODE (src), other, pos),
7288 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7289 ? GET_MODE_MASK (mode)
7290 : ((HOST_WIDE_INT) 1 << len) - 1,
7293 return gen_rtx_combine (SET, VOIDmode, assign, src);
7296 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7300 apply_distributive_law (x)
7303 enum rtx_code code = GET_CODE (x);
7304 rtx lhs, rhs, other;
7306 enum rtx_code inner_code;
7308 /* Distributivity is not true for floating point.
7309 It can change the value. So don't do it.
7310 -- rms and moshier@world.std.com. */
7311 if (FLOAT_MODE_P (GET_MODE (x)))
7314 /* The outer operation can only be one of the following: */
7315 if (code != IOR && code != AND && code != XOR
7316 && code != PLUS && code != MINUS)
7319 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7321 /* If either operand is a primitive we can't do anything, so get out
7323 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7324 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7327 lhs = expand_compound_operation (lhs);
7328 rhs = expand_compound_operation (rhs);
7329 inner_code = GET_CODE (lhs);
7330 if (inner_code != GET_CODE (rhs))
7333 /* See if the inner and outer operations distribute. */
7340 /* These all distribute except over PLUS. */
7341 if (code == PLUS || code == MINUS)
7346 if (code != PLUS && code != MINUS)
7351 /* This is also a multiply, so it distributes over everything. */
7355 /* Non-paradoxical SUBREGs distributes over all operations, provided
7356 the inner modes and word numbers are the same, this is an extraction
7357 of a low-order part, we don't convert an fp operation to int or
7358 vice versa, and we would not be converting a single-word
7359 operation into a multi-word operation. The latter test is not
7360 required, but it prevents generating unneeded multi-word operations.
7361 Some of the previous tests are redundant given the latter test, but
7362 are retained because they are required for correctness.
7364 We produce the result slightly differently in this case. */
7366 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7367 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7368 || ! subreg_lowpart_p (lhs)
7369 || (GET_MODE_CLASS (GET_MODE (lhs))
7370 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7371 || (GET_MODE_SIZE (GET_MODE (lhs))
7372 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7373 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7376 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7377 SUBREG_REG (lhs), SUBREG_REG (rhs));
7378 return gen_lowpart_for_combine (GET_MODE (x), tem);
7384 /* Set LHS and RHS to the inner operands (A and B in the example
7385 above) and set OTHER to the common operand (C in the example).
7386 These is only one way to do this unless the inner operation is
7388 if (GET_RTX_CLASS (inner_code) == 'c'
7389 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7390 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7391 else if (GET_RTX_CLASS (inner_code) == 'c'
7392 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7393 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7394 else if (GET_RTX_CLASS (inner_code) == 'c'
7395 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7396 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7397 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7398 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7402 /* Form the new inner operation, seeing if it simplifies first. */
7403 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7405 /* There is one exception to the general way of distributing:
7406 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7407 if (code == XOR && inner_code == IOR)
7410 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7413 /* We may be able to continuing distributing the result, so call
7414 ourselves recursively on the inner operation before forming the
7415 outer operation, which we return. */
7416 return gen_binary (inner_code, GET_MODE (x),
7417 apply_distributive_law (tem), other);
7420 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7423 Return an equivalent form, if different from X. Otherwise, return X. If
7424 X is zero, we are to always construct the equivalent form. */
7427 simplify_and_const_int (x, mode, varop, constop)
7429 enum machine_mode mode;
7431 unsigned HOST_WIDE_INT constop;
7433 unsigned HOST_WIDE_INT nonzero;
7436 /* Simplify VAROP knowing that we will be only looking at some of the
7438 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7440 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7441 CONST_INT, we are done. */
7442 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7445 /* See what bits may be nonzero in VAROP. Unlike the general case of
7446 a call to nonzero_bits, here we don't care about bits outside
7449 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7450 nonzero = trunc_int_for_mode (nonzero, mode);
7452 /* Turn off all bits in the constant that are known to already be zero.
7453 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7454 which is tested below. */
7458 /* If we don't have any bits left, return zero. */
7462 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7463 a power of two, we can replace this with a ASHIFT. */
7464 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7465 && (i = exact_log2 (constop)) >= 0)
7466 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7468 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7469 or XOR, then try to apply the distributive law. This may eliminate
7470 operations if either branch can be simplified because of the AND.
7471 It may also make some cases more complex, but those cases probably
7472 won't match a pattern either with or without this. */
7474 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7476 gen_lowpart_for_combine
7478 apply_distributive_law
7479 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7480 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7481 XEXP (varop, 0), constop),
7482 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7483 XEXP (varop, 1), constop))));
7485 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7486 if we already had one (just check for the simplest cases). */
7487 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7488 && GET_MODE (XEXP (x, 0)) == mode
7489 && SUBREG_REG (XEXP (x, 0)) == varop)
7490 varop = XEXP (x, 0);
7492 varop = gen_lowpart_for_combine (mode, varop);
7494 /* If we can't make the SUBREG, try to return what we were given. */
7495 if (GET_CODE (varop) == CLOBBER)
7496 return x ? x : varop;
7498 /* If we are only masking insignificant bits, return VAROP. */
7499 if (constop == nonzero)
7502 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7503 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7504 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7508 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7509 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7510 SUBST (XEXP (x, 1), GEN_INT (constop));
7512 SUBST (XEXP (x, 0), varop);
7518 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7519 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7520 is less useful. We can't allow both, because that results in exponential
7521 run time recursion. There is a nullstone testcase that triggered
7522 this. This macro avoids accidental uses of num_sign_bit_copies. */
7523 #define num_sign_bit_copies()
7525 /* Given an expression, X, compute which bits in X can be non-zero.
7526 We don't care about bits outside of those defined in MODE.
7528 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7529 a shift, AND, or zero_extract, we can do better. */
7531 static unsigned HOST_WIDE_INT
7532 nonzero_bits (x, mode)
7534 enum machine_mode mode;
7536 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7537 unsigned HOST_WIDE_INT inner_nz;
7539 int mode_width = GET_MODE_BITSIZE (mode);
7542 /* For floating-point values, assume all bits are needed. */
7543 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7546 /* If X is wider than MODE, use its mode instead. */
7547 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7549 mode = GET_MODE (x);
7550 nonzero = GET_MODE_MASK (mode);
7551 mode_width = GET_MODE_BITSIZE (mode);
7554 if (mode_width > HOST_BITS_PER_WIDE_INT)
7555 /* Our only callers in this case look for single bit values. So
7556 just return the mode mask. Those tests will then be false. */
7559 #ifndef WORD_REGISTER_OPERATIONS
7560 /* If MODE is wider than X, but both are a single word for both the host
7561 and target machines, we can compute this from which bits of the
7562 object might be nonzero in its own mode, taking into account the fact
7563 that on many CISC machines, accessing an object in a wider mode
7564 causes the high-order bits to become undefined. So they are
7565 not known to be zero. */
7567 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7568 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7569 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7570 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7572 nonzero &= nonzero_bits (x, GET_MODE (x));
7573 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7578 code = GET_CODE (x);
7582 #ifdef POINTERS_EXTEND_UNSIGNED
7583 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7584 all the bits above ptr_mode are known to be zero. */
7585 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7586 && REGNO_POINTER_FLAG (REGNO (x)))
7587 nonzero &= GET_MODE_MASK (ptr_mode);
7590 #ifdef STACK_BOUNDARY
7591 /* If this is the stack pointer, we may know something about its
7592 alignment. If PUSH_ROUNDING is defined, it is possible for the
7593 stack to be momentarily aligned only to that amount, so we pick
7594 the least alignment. */
7596 /* We can't check for arg_pointer_rtx here, because it is not
7597 guaranteed to have as much alignment as the stack pointer.
7598 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7599 alignment but the argument pointer has only 64 bit alignment. */
7601 if ((x == frame_pointer_rtx
7602 || x == stack_pointer_rtx
7603 || x == hard_frame_pointer_rtx
7604 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7605 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7611 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7613 #ifdef PUSH_ROUNDING
7614 if (REGNO (x) == STACK_POINTER_REGNUM)
7615 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7618 /* We must return here, otherwise we may get a worse result from
7619 one of the choices below. There is nothing useful below as
7620 far as the stack pointer is concerned. */
7621 return nonzero &= ~ (sp_alignment - 1);
7625 /* If X is a register whose nonzero bits value is current, use it.
7626 Otherwise, if X is a register whose value we can find, use that
7627 value. Otherwise, use the previously-computed global nonzero bits
7628 for this register. */
7630 if (reg_last_set_value[REGNO (x)] != 0
7631 && reg_last_set_mode[REGNO (x)] == mode
7632 && (reg_last_set_label[REGNO (x)] == label_tick
7633 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7634 && REG_N_SETS (REGNO (x)) == 1
7635 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7637 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7638 return reg_last_set_nonzero_bits[REGNO (x)];
7640 tem = get_last_value (x);
7644 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7645 /* If X is narrower than MODE and TEM is a non-negative
7646 constant that would appear negative in the mode of X,
7647 sign-extend it for use in reg_nonzero_bits because some
7648 machines (maybe most) will actually do the sign-extension
7649 and this is the conservative approach.
7651 ??? For 2.5, try to tighten up the MD files in this regard
7652 instead of this kludge. */
7654 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7655 && GET_CODE (tem) == CONST_INT
7657 && 0 != (INTVAL (tem)
7658 & ((HOST_WIDE_INT) 1
7659 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7660 tem = GEN_INT (INTVAL (tem)
7661 | ((HOST_WIDE_INT) (-1)
7662 << GET_MODE_BITSIZE (GET_MODE (x))));
7664 return nonzero_bits (tem, mode);
7666 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7667 return reg_nonzero_bits[REGNO (x)] & nonzero;
7672 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7673 /* If X is negative in MODE, sign-extend the value. */
7674 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7675 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7676 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7682 #ifdef LOAD_EXTEND_OP
7683 /* In many, if not most, RISC machines, reading a byte from memory
7684 zeros the rest of the register. Noticing that fact saves a lot
7685 of extra zero-extends. */
7686 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7687 nonzero &= GET_MODE_MASK (GET_MODE (x));
7697 /* If this produces an integer result, we know which bits are set.
7698 Code here used to clear bits outside the mode of X, but that is
7701 if (GET_MODE_CLASS (mode) == MODE_INT
7702 && mode_width <= HOST_BITS_PER_WIDE_INT)
7703 nonzero = STORE_FLAG_VALUE;
7708 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7709 and num_sign_bit_copies. */
7710 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7711 == GET_MODE_BITSIZE (GET_MODE (x)))
7715 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7716 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7721 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7722 and num_sign_bit_copies. */
7723 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7724 == GET_MODE_BITSIZE (GET_MODE (x)))
7730 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7734 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7735 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7736 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7740 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7741 Otherwise, show all the bits in the outer mode but not the inner
7743 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7744 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7746 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7748 & (((HOST_WIDE_INT) 1
7749 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7750 inner_nz |= (GET_MODE_MASK (mode)
7751 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7754 nonzero &= inner_nz;
7758 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7759 & nonzero_bits (XEXP (x, 1), mode));
7763 case UMIN: case UMAX: case SMIN: case SMAX:
7764 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7765 | nonzero_bits (XEXP (x, 1), mode));
7768 case PLUS: case MINUS:
7770 case DIV: case UDIV:
7771 case MOD: case UMOD:
7772 /* We can apply the rules of arithmetic to compute the number of
7773 high- and low-order zero bits of these operations. We start by
7774 computing the width (position of the highest-order non-zero bit)
7775 and the number of low-order zero bits for each value. */
7777 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7778 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7779 int width0 = floor_log2 (nz0) + 1;
7780 int width1 = floor_log2 (nz1) + 1;
7781 int low0 = floor_log2 (nz0 & -nz0);
7782 int low1 = floor_log2 (nz1 & -nz1);
7783 HOST_WIDE_INT op0_maybe_minusp
7784 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7785 HOST_WIDE_INT op1_maybe_minusp
7786 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7787 int result_width = mode_width;
7795 && (XEXP (x, 0) == stack_pointer_rtx
7796 || XEXP (x, 0) == frame_pointer_rtx)
7797 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7799 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7801 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7802 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7803 width0 = floor_log2 (nz0) + 1;
7804 width1 = floor_log2 (nz1) + 1;
7805 low0 = floor_log2 (nz0 & -nz0);
7806 low1 = floor_log2 (nz1 & -nz1);
7809 result_width = MAX (width0, width1) + 1;
7810 result_low = MIN (low0, low1);
7813 result_low = MIN (low0, low1);
7816 result_width = width0 + width1;
7817 result_low = low0 + low1;
7820 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7821 result_width = width0;
7824 result_width = width0;
7827 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7828 result_width = MIN (width0, width1);
7829 result_low = MIN (low0, low1);
7832 result_width = MIN (width0, width1);
7833 result_low = MIN (low0, low1);
7839 if (result_width < mode_width)
7840 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7843 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7848 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7849 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7850 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7854 /* If this is a SUBREG formed for a promoted variable that has
7855 been zero-extended, we know that at least the high-order bits
7856 are zero, though others might be too. */
7858 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7859 nonzero = (GET_MODE_MASK (GET_MODE (x))
7860 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7862 /* If the inner mode is a single word for both the host and target
7863 machines, we can compute this from which bits of the inner
7864 object might be nonzero. */
7865 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7866 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7867 <= HOST_BITS_PER_WIDE_INT))
7869 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7871 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7872 /* If this is a typical RISC machine, we only have to worry
7873 about the way loads are extended. */
7874 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7876 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7877 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7880 /* On many CISC machines, accessing an object in a wider mode
7881 causes the high-order bits to become undefined. So they are
7882 not known to be zero. */
7883 if (GET_MODE_SIZE (GET_MODE (x))
7884 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7885 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7886 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7895 /* The nonzero bits are in two classes: any bits within MODE
7896 that aren't in GET_MODE (x) are always significant. The rest of the
7897 nonzero bits are those that are significant in the operand of
7898 the shift when shifted the appropriate number of bits. This
7899 shows that high-order bits are cleared by the right shift and
7900 low-order bits by left shifts. */
7901 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7902 && INTVAL (XEXP (x, 1)) >= 0
7903 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7905 enum machine_mode inner_mode = GET_MODE (x);
7906 int width = GET_MODE_BITSIZE (inner_mode);
7907 int count = INTVAL (XEXP (x, 1));
7908 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7909 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7910 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7911 unsigned HOST_WIDE_INT outer = 0;
7913 if (mode_width > width)
7914 outer = (op_nonzero & nonzero & ~ mode_mask);
7916 if (code == LSHIFTRT)
7918 else if (code == ASHIFTRT)
7922 /* If the sign bit may have been nonzero before the shift, we
7923 need to mark all the places it could have been copied to
7924 by the shift as possibly nonzero. */
7925 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7926 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7928 else if (code == ASHIFT)
7931 inner = ((inner << (count % width)
7932 | (inner >> (width - (count % width)))) & mode_mask);
7934 nonzero &= (outer | inner);
7939 /* This is at most the number of bits in the mode. */
7940 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7944 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7945 | nonzero_bits (XEXP (x, 2), mode));
7955 /* See the macro definition above. */
7956 #undef num_sign_bit_copies
7958 /* Return the number of bits at the high-order end of X that are known to
7959 be equal to the sign bit. X will be used in mode MODE; if MODE is
7960 VOIDmode, X will be used in its own mode. The returned value will always
7961 be between 1 and the number of bits in MODE. */
7964 num_sign_bit_copies (x, mode)
7966 enum machine_mode mode;
7968 enum rtx_code code = GET_CODE (x);
7970 int num0, num1, result;
7971 unsigned HOST_WIDE_INT nonzero;
7974 /* If we weren't given a mode, use the mode of X. If the mode is still
7975 VOIDmode, we don't know anything. Likewise if one of the modes is
7978 if (mode == VOIDmode)
7979 mode = GET_MODE (x);
7981 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7984 bitwidth = GET_MODE_BITSIZE (mode);
7986 /* For a smaller object, just ignore the high bits. */
7987 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7988 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7989 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7991 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7993 #ifndef WORD_REGISTER_OPERATIONS
7994 /* If this machine does not do all register operations on the entire
7995 register and MODE is wider than the mode of X, we can say nothing
7996 at all about the high-order bits. */
7999 /* Likewise on machines that do, if the mode of the object is smaller
8000 than a word and loads of that size don't sign extend, we can say
8001 nothing about the high order bits. */
8002 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8003 #ifdef LOAD_EXTEND_OP
8004 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8015 #ifdef POINTERS_EXTEND_UNSIGNED
8016 /* If pointers extend signed and this is a pointer in Pmode, say that
8017 all the bits above ptr_mode are known to be sign bit copies. */
8018 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8019 && REGNO_POINTER_FLAG (REGNO (x)))
8020 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8023 if (reg_last_set_value[REGNO (x)] != 0
8024 && reg_last_set_mode[REGNO (x)] == mode
8025 && (reg_last_set_label[REGNO (x)] == label_tick
8026 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8027 && REG_N_SETS (REGNO (x)) == 1
8028 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8030 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8031 return reg_last_set_sign_bit_copies[REGNO (x)];
8033 tem = get_last_value (x);
8035 return num_sign_bit_copies (tem, mode);
8037 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8038 return reg_sign_bit_copies[REGNO (x)];
8042 #ifdef LOAD_EXTEND_OP
8043 /* Some RISC machines sign-extend all loads of smaller than a word. */
8044 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8045 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
8050 /* If the constant is negative, take its 1's complement and remask.
8051 Then see how many zero bits we have. */
8052 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8053 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8054 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8055 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8057 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8060 /* If this is a SUBREG for a promoted object that is sign-extended
8061 and we are looking at it in a wider mode, we know that at least the
8062 high-order bits are known to be sign bit copies. */
8064 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8065 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8066 num_sign_bit_copies (SUBREG_REG (x), mode));
8068 /* For a smaller object, just ignore the high bits. */
8069 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8071 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8072 return MAX (1, (num0
8073 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8077 #ifdef WORD_REGISTER_OPERATIONS
8078 #ifdef LOAD_EXTEND_OP
8079 /* For paradoxical SUBREGs on machines where all register operations
8080 affect the entire register, just look inside. Note that we are
8081 passing MODE to the recursive call, so the number of sign bit copies
8082 will remain relative to that mode, not the inner mode. */
8084 /* This works only if loads sign extend. Otherwise, if we get a
8085 reload for the inner part, it may be loaded from the stack, and
8086 then we lose all sign bit copies that existed before the store
8089 if ((GET_MODE_SIZE (GET_MODE (x))
8090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8091 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8092 return num_sign_bit_copies (SUBREG_REG (x), mode);
8098 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8099 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
8103 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8104 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8107 /* For a smaller object, just ignore the high bits. */
8108 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8109 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8113 return num_sign_bit_copies (XEXP (x, 0), mode);
8115 case ROTATE: case ROTATERT:
8116 /* If we are rotating left by a number of bits less than the number
8117 of sign bit copies, we can just subtract that amount from the
8119 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8120 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8122 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8123 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8124 : bitwidth - INTVAL (XEXP (x, 1))));
8129 /* In general, this subtracts one sign bit copy. But if the value
8130 is known to be positive, the number of sign bit copies is the
8131 same as that of the input. Finally, if the input has just one bit
8132 that might be nonzero, all the bits are copies of the sign bit. */
8133 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8134 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8135 return num0 > 1 ? num0 - 1 : 1;
8137 nonzero = nonzero_bits (XEXP (x, 0), mode);
8142 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8147 case IOR: case AND: case XOR:
8148 case SMIN: case SMAX: case UMIN: case UMAX:
8149 /* Logical operations will preserve the number of sign-bit copies.
8150 MIN and MAX operations always return one of the operands. */
8151 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8152 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8153 return MIN (num0, num1);
8155 case PLUS: case MINUS:
8156 /* For addition and subtraction, we can have a 1-bit carry. However,
8157 if we are subtracting 1 from a positive number, there will not
8158 be such a carry. Furthermore, if the positive number is known to
8159 be 0 or 1, we know the result is either -1 or 0. */
8161 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8162 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8164 nonzero = nonzero_bits (XEXP (x, 0), mode);
8165 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8166 return (nonzero == 1 || nonzero == 0 ? bitwidth
8167 : bitwidth - floor_log2 (nonzero) - 1);
8170 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8171 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8172 return MAX (1, MIN (num0, num1) - 1);
8175 /* The number of bits of the product is the sum of the number of
8176 bits of both terms. However, unless one of the terms if known
8177 to be positive, we must allow for an additional bit since negating
8178 a negative number can remove one sign bit copy. */
8180 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8181 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8183 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8185 && (bitwidth > HOST_BITS_PER_WIDE_INT
8186 || (((nonzero_bits (XEXP (x, 0), mode)
8187 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8188 && ((nonzero_bits (XEXP (x, 1), mode)
8189 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8192 return MAX (1, result);
8195 /* The result must be <= the first operand. If the first operand
8196 has the high bit set, we know nothing about the number of sign
8198 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8200 else if ((nonzero_bits (XEXP (x, 0), mode)
8201 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8204 return num_sign_bit_copies (XEXP (x, 0), mode);
8207 /* The result must be <= the scond operand. */
8208 return num_sign_bit_copies (XEXP (x, 1), mode);
8211 /* Similar to unsigned division, except that we have to worry about
8212 the case where the divisor is negative, in which case we have
8214 result = num_sign_bit_copies (XEXP (x, 0), mode);
8216 && (bitwidth > HOST_BITS_PER_WIDE_INT
8217 || (nonzero_bits (XEXP (x, 1), mode)
8218 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8224 result = num_sign_bit_copies (XEXP (x, 1), mode);
8226 && (bitwidth > HOST_BITS_PER_WIDE_INT
8227 || (nonzero_bits (XEXP (x, 1), mode)
8228 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8234 /* Shifts by a constant add to the number of bits equal to the
8236 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8237 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8238 && INTVAL (XEXP (x, 1)) > 0)
8239 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8244 /* Left shifts destroy copies. */
8245 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8246 || INTVAL (XEXP (x, 1)) < 0
8247 || INTVAL (XEXP (x, 1)) >= bitwidth)
8250 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8251 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8254 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8255 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8256 return MIN (num0, num1);
8258 case EQ: case NE: case GE: case GT: case LE: case LT:
8259 case GEU: case GTU: case LEU: case LTU:
8260 if (STORE_FLAG_VALUE == -1)
8268 /* If we haven't been able to figure it out by one of the above rules,
8269 see if some of the high-order bits are known to be zero. If so,
8270 count those bits and return one less than that amount. If we can't
8271 safely compute the mask for this mode, always return BITWIDTH. */
8273 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8276 nonzero = nonzero_bits (x, mode);
8277 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8278 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8281 /* Return the number of "extended" bits there are in X, when interpreted
8282 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8283 unsigned quantities, this is the number of high-order zero bits.
8284 For signed quantities, this is the number of copies of the sign bit
8285 minus 1. In both case, this function returns the number of "spare"
8286 bits. For example, if two quantities for which this function returns
8287 at least 1 are added, the addition is known not to overflow.
8289 This function will always return 0 unless called during combine, which
8290 implies that it must be called from a define_split. */
8293 extended_count (x, mode, unsignedp)
8295 enum machine_mode mode;
8298 if (nonzero_sign_valid == 0)
8302 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8303 && (GET_MODE_BITSIZE (mode) - 1
8304 - floor_log2 (nonzero_bits (x, mode))))
8305 : num_sign_bit_copies (x, mode) - 1);
8308 /* This function is called from `simplify_shift_const' to merge two
8309 outer operations. Specifically, we have already found that we need
8310 to perform operation *POP0 with constant *PCONST0 at the outermost
8311 position. We would now like to also perform OP1 with constant CONST1
8312 (with *POP0 being done last).
8314 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8315 the resulting operation. *PCOMP_P is set to 1 if we would need to
8316 complement the innermost operand, otherwise it is unchanged.
8318 MODE is the mode in which the operation will be done. No bits outside
8319 the width of this mode matter. It is assumed that the width of this mode
8320 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8322 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8323 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8324 result is simply *PCONST0.
8326 If the resulting operation cannot be expressed as one operation, we
8327 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8330 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8331 enum rtx_code *pop0;
8332 HOST_WIDE_INT *pconst0;
8334 HOST_WIDE_INT const1;
8335 enum machine_mode mode;
8338 enum rtx_code op0 = *pop0;
8339 HOST_WIDE_INT const0 = *pconst0;
8341 const0 &= GET_MODE_MASK (mode);
8342 const1 &= GET_MODE_MASK (mode);
8344 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8348 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8351 if (op1 == NIL || op0 == SET)
8354 else if (op0 == NIL)
8355 op0 = op1, const0 = const1;
8357 else if (op0 == op1)
8381 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8382 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8385 /* If the two constants aren't the same, we can't do anything. The
8386 remaining six cases can all be done. */
8387 else if (const0 != const1)
8395 /* (a & b) | b == b */
8397 else /* op1 == XOR */
8398 /* (a ^ b) | b == a | b */
8404 /* (a & b) ^ b == (~a) & b */
8405 op0 = AND, *pcomp_p = 1;
8406 else /* op1 == IOR */
8407 /* (a | b) ^ b == a & ~b */
8408 op0 = AND, *pconst0 = ~ const0;
8413 /* (a | b) & b == b */
8415 else /* op1 == XOR */
8416 /* (a ^ b) & b) == (~a) & b */
8423 /* Check for NO-OP cases. */
8424 const0 &= GET_MODE_MASK (mode);
8426 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8428 else if (const0 == 0 && op0 == AND)
8430 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8434 /* ??? Slightly redundant with the above mask, but not entirely.
8435 Moving this above means we'd have to sign-extend the mode mask
8436 for the final test. */
8437 const0 = trunc_int_for_mode (const0, mode);
8445 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8446 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8447 that we started with.
8449 The shift is normally computed in the widest mode we find in VAROP, as
8450 long as it isn't a different number of words than RESULT_MODE. Exceptions
8451 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8454 simplify_shift_const (x, code, result_mode, varop, count)
8457 enum machine_mode result_mode;
8461 enum rtx_code orig_code = code;
8462 int orig_count = count;
8463 enum machine_mode mode = result_mode;
8464 enum machine_mode shift_mode, tmode;
8466 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8467 /* We form (outer_op (code varop count) (outer_const)). */
8468 enum rtx_code outer_op = NIL;
8469 HOST_WIDE_INT outer_const = 0;
8471 int complement_p = 0;
8474 /* If we were given an invalid count, don't do anything except exactly
8475 what was requested. */
8477 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8482 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8485 /* Unless one of the branches of the `if' in this loop does a `continue',
8486 we will `break' the loop after the `if'. */
8490 /* If we have an operand of (clobber (const_int 0)), just return that
8492 if (GET_CODE (varop) == CLOBBER)
8495 /* If we discovered we had to complement VAROP, leave. Making a NOT
8496 here would cause an infinite loop. */
8500 /* Convert ROTATERT to ROTATE. */
8501 if (code == ROTATERT)
8502 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8504 /* We need to determine what mode we will do the shift in. If the
8505 shift is a right shift or a ROTATE, we must always do it in the mode
8506 it was originally done in. Otherwise, we can do it in MODE, the
8507 widest mode encountered. */
8509 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8510 ? result_mode : mode);
8512 /* Handle cases where the count is greater than the size of the mode
8513 minus 1. For ASHIFT, use the size minus one as the count (this can
8514 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8515 take the count modulo the size. For other shifts, the result is
8518 Since these shifts are being produced by the compiler by combining
8519 multiple operations, each of which are defined, we know what the
8520 result is supposed to be. */
8522 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8524 if (code == ASHIFTRT)
8525 count = GET_MODE_BITSIZE (shift_mode) - 1;
8526 else if (code == ROTATE || code == ROTATERT)
8527 count %= GET_MODE_BITSIZE (shift_mode);
8530 /* We can't simply return zero because there may be an
8538 /* Negative counts are invalid and should not have been made (a
8539 programmer-specified negative count should have been handled
8544 /* An arithmetic right shift of a quantity known to be -1 or 0
8546 if (code == ASHIFTRT
8547 && (num_sign_bit_copies (varop, shift_mode)
8548 == GET_MODE_BITSIZE (shift_mode)))
8554 /* If we are doing an arithmetic right shift and discarding all but
8555 the sign bit copies, this is equivalent to doing a shift by the
8556 bitsize minus one. Convert it into that shift because it will often
8557 allow other simplifications. */
8559 if (code == ASHIFTRT
8560 && (count + num_sign_bit_copies (varop, shift_mode)
8561 >= GET_MODE_BITSIZE (shift_mode)))
8562 count = GET_MODE_BITSIZE (shift_mode) - 1;
8564 /* We simplify the tests below and elsewhere by converting
8565 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8566 `make_compound_operation' will convert it to a ASHIFTRT for
8567 those machines (such as Vax) that don't have a LSHIFTRT. */
8568 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8570 && ((nonzero_bits (varop, shift_mode)
8571 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8575 switch (GET_CODE (varop))
8581 new = expand_compound_operation (varop);
8590 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8591 minus the width of a smaller mode, we can do this with a
8592 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8593 if ((code == ASHIFTRT || code == LSHIFTRT)
8594 && ! mode_dependent_address_p (XEXP (varop, 0))
8595 && ! MEM_VOLATILE_P (varop)
8596 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8597 MODE_INT, 1)) != BLKmode)
8599 if (BYTES_BIG_ENDIAN)
8600 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8602 new = gen_rtx_MEM (tmode,
8603 plus_constant (XEXP (varop, 0),
8604 count / BITS_PER_UNIT));
8605 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8606 MEM_COPY_ATTRIBUTES (new, varop);
8607 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8608 : ZERO_EXTEND, mode, new);
8615 /* Similar to the case above, except that we can only do this if
8616 the resulting mode is the same as that of the underlying
8617 MEM and adjust the address depending on the *bits* endianness
8618 because of the way that bit-field extract insns are defined. */
8619 if ((code == ASHIFTRT || code == LSHIFTRT)
8620 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8621 MODE_INT, 1)) != BLKmode
8622 && tmode == GET_MODE (XEXP (varop, 0)))
8624 if (BITS_BIG_ENDIAN)
8625 new = XEXP (varop, 0);
8628 new = copy_rtx (XEXP (varop, 0));
8629 SUBST (XEXP (new, 0),
8630 plus_constant (XEXP (new, 0),
8631 count / BITS_PER_UNIT));
8634 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8635 : ZERO_EXTEND, mode, new);
8642 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8643 the same number of words as what we've seen so far. Then store
8644 the widest mode in MODE. */
8645 if (subreg_lowpart_p (varop)
8646 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8647 > GET_MODE_SIZE (GET_MODE (varop)))
8648 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8649 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8652 varop = SUBREG_REG (varop);
8653 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8654 mode = GET_MODE (varop);
8660 /* Some machines use MULT instead of ASHIFT because MULT
8661 is cheaper. But it is still better on those machines to
8662 merge two shifts into one. */
8663 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8664 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8666 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8667 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8673 /* Similar, for when divides are cheaper. */
8674 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8675 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8677 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8678 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8684 /* If we are extracting just the sign bit of an arithmetic right
8685 shift, that shift is not needed. */
8686 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8688 varop = XEXP (varop, 0);
8692 /* ... fall through ... */
8697 /* Here we have two nested shifts. The result is usually the
8698 AND of a new shift with a mask. We compute the result below. */
8699 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8700 && INTVAL (XEXP (varop, 1)) >= 0
8701 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8702 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8703 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8705 enum rtx_code first_code = GET_CODE (varop);
8706 int first_count = INTVAL (XEXP (varop, 1));
8707 unsigned HOST_WIDE_INT mask;
8710 /* We have one common special case. We can't do any merging if
8711 the inner code is an ASHIFTRT of a smaller mode. However, if
8712 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8713 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8714 we can convert it to
8715 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8716 This simplifies certain SIGN_EXTEND operations. */
8717 if (code == ASHIFT && first_code == ASHIFTRT
8718 && (GET_MODE_BITSIZE (result_mode)
8719 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8721 /* C3 has the low-order C1 bits zero. */
8723 mask = (GET_MODE_MASK (mode)
8724 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8726 varop = simplify_and_const_int (NULL_RTX, result_mode,
8727 XEXP (varop, 0), mask);
8728 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8730 count = first_count;
8735 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8736 than C1 high-order bits equal to the sign bit, we can convert
8737 this to either an ASHIFT or a ASHIFTRT depending on the
8740 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8742 if (code == ASHIFTRT && first_code == ASHIFT
8743 && GET_MODE (varop) == shift_mode
8744 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8747 count -= first_count;
8749 count = - count, code = ASHIFT;
8750 varop = XEXP (varop, 0);
8754 /* There are some cases we can't do. If CODE is ASHIFTRT,
8755 we can only do this if FIRST_CODE is also ASHIFTRT.
8757 We can't do the case when CODE is ROTATE and FIRST_CODE is
8760 If the mode of this shift is not the mode of the outer shift,
8761 we can't do this if either shift is a right shift or ROTATE.
8763 Finally, we can't do any of these if the mode is too wide
8764 unless the codes are the same.
8766 Handle the case where the shift codes are the same
8769 if (code == first_code)
8771 if (GET_MODE (varop) != result_mode
8772 && (code == ASHIFTRT || code == LSHIFTRT
8776 count += first_count;
8777 varop = XEXP (varop, 0);
8781 if (code == ASHIFTRT
8782 || (code == ROTATE && first_code == ASHIFTRT)
8783 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8784 || (GET_MODE (varop) != result_mode
8785 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8786 || first_code == ROTATE
8787 || code == ROTATE)))
8790 /* To compute the mask to apply after the shift, shift the
8791 nonzero bits of the inner shift the same way the
8792 outer shift will. */
8794 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8797 = simplify_binary_operation (code, result_mode, mask_rtx,
8800 /* Give up if we can't compute an outer operation to use. */
8802 || GET_CODE (mask_rtx) != CONST_INT
8803 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8805 result_mode, &complement_p))
8808 /* If the shifts are in the same direction, we add the
8809 counts. Otherwise, we subtract them. */
8810 if ((code == ASHIFTRT || code == LSHIFTRT)
8811 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8812 count += first_count;
8814 count -= first_count;
8816 /* If COUNT is positive, the new shift is usually CODE,
8817 except for the two exceptions below, in which case it is
8818 FIRST_CODE. If the count is negative, FIRST_CODE should
8821 && ((first_code == ROTATE && code == ASHIFT)
8822 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8825 code = first_code, count = - count;
8827 varop = XEXP (varop, 0);
8831 /* If we have (A << B << C) for any shift, we can convert this to
8832 (A << C << B). This wins if A is a constant. Only try this if
8833 B is not a constant. */
8835 else if (GET_CODE (varop) == code
8836 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8838 = simplify_binary_operation (code, mode,
8842 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8849 /* Make this fit the case below. */
8850 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8851 GEN_INT (GET_MODE_MASK (mode)));
8857 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8858 with C the size of VAROP - 1 and the shift is logical if
8859 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8860 we have an (le X 0) operation. If we have an arithmetic shift
8861 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8862 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8864 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8865 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8866 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8867 && (code == LSHIFTRT || code == ASHIFTRT)
8868 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8869 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8872 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8875 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8876 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8881 /* If we have (shift (logical)), move the logical to the outside
8882 to allow it to possibly combine with another logical and the
8883 shift to combine with another shift. This also canonicalizes to
8884 what a ZERO_EXTRACT looks like. Also, some machines have
8885 (and (shift)) insns. */
8887 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8888 && (new = simplify_binary_operation (code, result_mode,
8890 GEN_INT (count))) != 0
8891 && GET_CODE(new) == CONST_INT
8892 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8893 INTVAL (new), result_mode, &complement_p))
8895 varop = XEXP (varop, 0);
8899 /* If we can't do that, try to simplify the shift in each arm of the
8900 logical expression, make a new logical expression, and apply
8901 the inverse distributive law. */
8903 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8904 XEXP (varop, 0), count);
8905 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8906 XEXP (varop, 1), count);
8908 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8909 varop = apply_distributive_law (varop);
8916 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8917 says that the sign bit can be tested, FOO has mode MODE, C is
8918 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8919 that may be nonzero. */
8920 if (code == LSHIFTRT
8921 && XEXP (varop, 1) == const0_rtx
8922 && GET_MODE (XEXP (varop, 0)) == result_mode
8923 && count == GET_MODE_BITSIZE (result_mode) - 1
8924 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8925 && ((STORE_FLAG_VALUE
8926 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8927 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8928 && merge_outer_ops (&outer_op, &outer_const, XOR,
8929 (HOST_WIDE_INT) 1, result_mode,
8932 varop = XEXP (varop, 0);
8939 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8940 than the number of bits in the mode is equivalent to A. */
8941 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8942 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8944 varop = XEXP (varop, 0);
8949 /* NEG commutes with ASHIFT since it is multiplication. Move the
8950 NEG outside to allow shifts to combine. */
8952 && merge_outer_ops (&outer_op, &outer_const, NEG,
8953 (HOST_WIDE_INT) 0, result_mode,
8956 varop = XEXP (varop, 0);
8962 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8963 is one less than the number of bits in the mode is
8964 equivalent to (xor A 1). */
8965 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8966 && XEXP (varop, 1) == constm1_rtx
8967 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8968 && merge_outer_ops (&outer_op, &outer_const, XOR,
8969 (HOST_WIDE_INT) 1, result_mode,
8973 varop = XEXP (varop, 0);
8977 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8978 that might be nonzero in BAR are those being shifted out and those
8979 bits are known zero in FOO, we can replace the PLUS with FOO.
8980 Similarly in the other operand order. This code occurs when
8981 we are computing the size of a variable-size array. */
8983 if ((code == ASHIFTRT || code == LSHIFTRT)
8984 && count < HOST_BITS_PER_WIDE_INT
8985 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8986 && (nonzero_bits (XEXP (varop, 1), result_mode)
8987 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8989 varop = XEXP (varop, 0);
8992 else if ((code == ASHIFTRT || code == LSHIFTRT)
8993 && count < HOST_BITS_PER_WIDE_INT
8994 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8995 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8997 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8998 & nonzero_bits (XEXP (varop, 1),
9001 varop = XEXP (varop, 1);
9005 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9007 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9008 && (new = simplify_binary_operation (ASHIFT, result_mode,
9010 GEN_INT (count))) != 0
9011 && GET_CODE(new) == CONST_INT
9012 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9013 INTVAL (new), result_mode, &complement_p))
9015 varop = XEXP (varop, 0);
9021 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9022 with C the size of VAROP - 1 and the shift is logical if
9023 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9024 we have a (gt X 0) operation. If the shift is arithmetic with
9025 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9026 we have a (neg (gt X 0)) operation. */
9028 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9029 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9030 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9031 && (code == LSHIFTRT || code == ASHIFTRT)
9032 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9033 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9034 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9037 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9040 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9041 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9048 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9049 if the truncate does not affect the value. */
9050 if (code == LSHIFTRT
9051 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9052 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9053 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9054 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9055 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9057 rtx varop_inner = XEXP (varop, 0);
9059 varop_inner = gen_rtx_combine (LSHIFTRT,
9060 GET_MODE (varop_inner),
9061 XEXP (varop_inner, 0),
9062 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
9063 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9077 /* We need to determine what mode to do the shift in. If the shift is
9078 a right shift or ROTATE, we must always do it in the mode it was
9079 originally done in. Otherwise, we can do it in MODE, the widest mode
9080 encountered. The code we care about is that of the shift that will
9081 actually be done, not the shift that was originally requested. */
9083 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9084 ? result_mode : mode);
9086 /* We have now finished analyzing the shift. The result should be
9087 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9088 OUTER_OP is non-NIL, it is an operation that needs to be applied
9089 to the result of the shift. OUTER_CONST is the relevant constant,
9090 but we must turn off all bits turned off in the shift.
9092 If we were passed a value for X, see if we can use any pieces of
9093 it. If not, make new rtx. */
9095 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9096 && GET_CODE (XEXP (x, 1)) == CONST_INT
9097 && INTVAL (XEXP (x, 1)) == count)
9098 const_rtx = XEXP (x, 1);
9100 const_rtx = GEN_INT (count);
9102 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9103 && GET_MODE (XEXP (x, 0)) == shift_mode
9104 && SUBREG_REG (XEXP (x, 0)) == varop)
9105 varop = XEXP (x, 0);
9106 else if (GET_MODE (varop) != shift_mode)
9107 varop = gen_lowpart_for_combine (shift_mode, varop);
9109 /* If we can't make the SUBREG, try to return what we were given. */
9110 if (GET_CODE (varop) == CLOBBER)
9111 return x ? x : varop;
9113 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9118 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9119 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9121 SUBST (XEXP (x, 0), varop);
9122 SUBST (XEXP (x, 1), const_rtx);
9125 /* If we have an outer operation and we just made a shift, it is
9126 possible that we could have simplified the shift were it not
9127 for the outer operation. So try to do the simplification
9130 if (outer_op != NIL && GET_CODE (x) == code
9131 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9132 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9133 INTVAL (XEXP (x, 1)));
9135 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9136 turn off all the bits that the shift would have turned off. */
9137 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9138 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9139 GET_MODE_MASK (result_mode) >> orig_count);
9141 /* Do the remainder of the processing in RESULT_MODE. */
9142 x = gen_lowpart_for_combine (result_mode, x);
9144 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9147 x = gen_unary (NOT, result_mode, result_mode, x);
9149 if (outer_op != NIL)
9151 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9152 outer_const = trunc_int_for_mode (outer_const, result_mode);
9154 if (outer_op == AND)
9155 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9156 else if (outer_op == SET)
9157 /* This means that we have determined that the result is
9158 equivalent to a constant. This should be rare. */
9159 x = GEN_INT (outer_const);
9160 else if (GET_RTX_CLASS (outer_op) == '1')
9161 x = gen_unary (outer_op, result_mode, result_mode, x);
9163 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9169 /* Like recog, but we receive the address of a pointer to a new pattern.
9170 We try to match the rtx that the pointer points to.
9171 If that fails, we may try to modify or replace the pattern,
9172 storing the replacement into the same pointer object.
9174 Modifications include deletion or addition of CLOBBERs.
9176 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9177 the CLOBBERs are placed.
9179 The value is the final insn code from the pattern ultimately matched,
9183 recog_for_combine (pnewpat, insn, pnotes)
9188 register rtx pat = *pnewpat;
9189 int insn_code_number;
9190 int num_clobbers_to_add = 0;
9194 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9195 we use to indicate that something didn't match. If we find such a
9196 thing, force rejection. */
9197 if (GET_CODE (pat) == PARALLEL)
9198 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9199 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9200 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9203 /* Is the result of combination a valid instruction? */
9204 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9206 /* If it isn't, there is the possibility that we previously had an insn
9207 that clobbered some register as a side effect, but the combined
9208 insn doesn't need to do that. So try once more without the clobbers
9209 unless this represents an ASM insn. */
9211 if (insn_code_number < 0 && ! check_asm_operands (pat)
9212 && GET_CODE (pat) == PARALLEL)
9216 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9217 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9220 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9224 SUBST_INT (XVECLEN (pat, 0), pos);
9227 pat = XVECEXP (pat, 0, 0);
9229 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9232 /* If we had any clobbers to add, make a new pattern than contains
9233 them. Then check to make sure that all of them are dead. */
9234 if (num_clobbers_to_add)
9236 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9237 gen_rtvec (GET_CODE (pat) == PARALLEL
9239 + num_clobbers_to_add)
9240 : num_clobbers_to_add + 1));
9242 if (GET_CODE (pat) == PARALLEL)
9243 for (i = 0; i < XVECLEN (pat, 0); i++)
9244 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9246 XVECEXP (newpat, 0, 0) = pat;
9248 add_clobbers (newpat, insn_code_number);
9250 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9251 i < XVECLEN (newpat, 0); i++)
9253 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9254 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9256 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9257 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9265 return insn_code_number;
9268 /* Like gen_lowpart but for use by combine. In combine it is not possible
9269 to create any new pseudoregs. However, it is safe to create
9270 invalid memory addresses, because combine will try to recognize
9271 them and all they will do is make the combine attempt fail.
9273 If for some reason this cannot do its job, an rtx
9274 (clobber (const_int 0)) is returned.
9275 An insn containing that will not be recognized. */
9280 gen_lowpart_for_combine (mode, x)
9281 enum machine_mode mode;
9286 if (GET_MODE (x) == mode)
9289 /* We can only support MODE being wider than a word if X is a
9290 constant integer or has a mode the same size. */
9292 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9293 && ! ((GET_MODE (x) == VOIDmode
9294 && (GET_CODE (x) == CONST_INT
9295 || GET_CODE (x) == CONST_DOUBLE))
9296 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9297 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9299 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9300 won't know what to do. So we will strip off the SUBREG here and
9301 process normally. */
9302 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9305 if (GET_MODE (x) == mode)
9309 result = gen_lowpart_common (mode, x);
9311 && GET_CODE (result) == SUBREG
9312 && GET_CODE (SUBREG_REG (result)) == REG
9313 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9314 && (GET_MODE_SIZE (GET_MODE (result))
9315 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9316 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9321 if (GET_CODE (x) == MEM)
9323 register int offset = 0;
9326 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9328 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9329 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9331 /* If we want to refer to something bigger than the original memref,
9332 generate a perverse subreg instead. That will force a reload
9333 of the original memref X. */
9334 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9335 return gen_rtx_SUBREG (mode, x, 0);
9337 if (WORDS_BIG_ENDIAN)
9338 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9339 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9341 if (BYTES_BIG_ENDIAN)
9343 /* Adjust the address so that the address-after-the-data is
9345 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9346 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9348 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9349 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9350 MEM_COPY_ATTRIBUTES (new, x);
9354 /* If X is a comparison operator, rewrite it in a new mode. This
9355 probably won't match, but may allow further simplifications. */
9356 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9357 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9359 /* If we couldn't simplify X any other way, just enclose it in a
9360 SUBREG. Normally, this SUBREG won't match, but some patterns may
9361 include an explicit SUBREG or we may simplify it further in combine. */
9366 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9367 word = ((GET_MODE_SIZE (GET_MODE (x))
9368 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9370 return gen_rtx_SUBREG (mode, x, word);
9374 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9375 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9377 If the identical expression was previously in the insn (in the undobuf),
9378 it will be returned. Only if it is not found will a new expression
9383 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9385 #ifndef ANSI_PROTOTYPES
9387 enum machine_mode mode;
9399 #ifndef ANSI_PROTOTYPES
9400 code = va_arg (p, enum rtx_code);
9401 mode = va_arg (p, enum machine_mode);
9404 n_args = GET_RTX_LENGTH (code);
9405 fmt = GET_RTX_FORMAT (code);
9407 if (n_args == 0 || n_args > 3)
9410 /* Get each arg and verify that it is supposed to be an expression. */
9411 for (j = 0; j < n_args; j++)
9416 args[j] = va_arg (p, rtx);
9421 /* See if this is in undobuf. Be sure we don't use objects that came
9422 from another insn; this could produce circular rtl structures. */
9424 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9426 && GET_CODE (undo->old_contents.r) == code
9427 && GET_MODE (undo->old_contents.r) == mode)
9429 for (j = 0; j < n_args; j++)
9430 if (XEXP (undo->old_contents.r, j) != args[j])
9434 return undo->old_contents.r;
9437 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9438 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9439 rt = rtx_alloc (code);
9440 PUT_MODE (rt, mode);
9441 XEXP (rt, 0) = args[0];
9444 XEXP (rt, 1) = args[1];
9446 XEXP (rt, 2) = args[2];
9451 /* These routines make binary and unary operations by first seeing if they
9452 fold; if not, a new expression is allocated. */
9455 gen_binary (code, mode, op0, op1)
9457 enum machine_mode mode;
9463 if (GET_RTX_CLASS (code) == 'c'
9464 && (GET_CODE (op0) == CONST_INT
9465 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9466 tem = op0, op0 = op1, op1 = tem;
9468 if (GET_RTX_CLASS (code) == '<')
9470 enum machine_mode op_mode = GET_MODE (op0);
9472 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9473 just (REL_OP X Y). */
9474 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9476 op1 = XEXP (op0, 1);
9477 op0 = XEXP (op0, 0);
9478 op_mode = GET_MODE (op0);
9481 if (op_mode == VOIDmode)
9482 op_mode = GET_MODE (op1);
9483 result = simplify_relational_operation (code, op_mode, op0, op1);
9486 result = simplify_binary_operation (code, mode, op0, op1);
9491 /* Put complex operands first and constants second. */
9492 if (GET_RTX_CLASS (code) == 'c'
9493 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9494 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9495 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9496 || (GET_CODE (op0) == SUBREG
9497 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9498 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9499 return gen_rtx_combine (code, mode, op1, op0);
9501 /* If we are turning off bits already known off in OP0, we need not do
9503 else if (code == AND && GET_CODE (op1) == CONST_INT
9504 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9505 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9508 return gen_rtx_combine (code, mode, op0, op1);
9512 gen_unary (code, mode, op0_mode, op0)
9514 enum machine_mode mode, op0_mode;
9517 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9522 return gen_rtx_combine (code, mode, op0);
9525 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9526 comparison code that will be tested.
9528 The result is a possibly different comparison code to use. *POP0 and
9529 *POP1 may be updated.
9531 It is possible that we might detect that a comparison is either always
9532 true or always false. However, we do not perform general constant
9533 folding in combine, so this knowledge isn't useful. Such tautologies
9534 should have been detected earlier. Hence we ignore all such cases. */
9536 static enum rtx_code
9537 simplify_comparison (code, pop0, pop1)
9546 enum machine_mode mode, tmode;
9548 /* Try a few ways of applying the same transformation to both operands. */
9551 #ifndef WORD_REGISTER_OPERATIONS
9552 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9553 so check specially. */
9554 if (code != GTU && code != GEU && code != LTU && code != LEU
9555 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9556 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9557 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9558 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9559 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9560 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9561 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9562 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9563 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9564 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9565 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9566 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9567 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9568 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9569 && (INTVAL (XEXP (op0, 1))
9570 == (GET_MODE_BITSIZE (GET_MODE (op0))
9572 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9574 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9575 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9579 /* If both operands are the same constant shift, see if we can ignore the
9580 shift. We can if the shift is a rotate or if the bits shifted out of
9581 this shift are known to be zero for both inputs and if the type of
9582 comparison is compatible with the shift. */
9583 if (GET_CODE (op0) == GET_CODE (op1)
9584 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9585 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9586 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9587 && (code != GT && code != LT && code != GE && code != LE))
9588 || (GET_CODE (op0) == ASHIFTRT
9589 && (code != GTU && code != LTU
9590 && code != GEU && code != GEU)))
9591 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9592 && INTVAL (XEXP (op0, 1)) >= 0
9593 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9594 && XEXP (op0, 1) == XEXP (op1, 1))
9596 enum machine_mode mode = GET_MODE (op0);
9597 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9598 int shift_count = INTVAL (XEXP (op0, 1));
9600 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9601 mask &= (mask >> shift_count) << shift_count;
9602 else if (GET_CODE (op0) == ASHIFT)
9603 mask = (mask & (mask << shift_count)) >> shift_count;
9605 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9606 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9607 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9612 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9613 SUBREGs are of the same mode, and, in both cases, the AND would
9614 be redundant if the comparison was done in the narrower mode,
9615 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9616 and the operand's possibly nonzero bits are 0xffffff01; in that case
9617 if we only care about QImode, we don't need the AND). This case
9618 occurs if the output mode of an scc insn is not SImode and
9619 STORE_FLAG_VALUE == 1 (e.g., the 386).
9621 Similarly, check for a case where the AND's are ZERO_EXTEND
9622 operations from some narrower mode even though a SUBREG is not
9625 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9626 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9627 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9629 rtx inner_op0 = XEXP (op0, 0);
9630 rtx inner_op1 = XEXP (op1, 0);
9631 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9632 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9635 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9636 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9637 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9638 && (GET_MODE (SUBREG_REG (inner_op0))
9639 == GET_MODE (SUBREG_REG (inner_op1)))
9640 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9641 <= HOST_BITS_PER_WIDE_INT)
9642 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9643 GET_MODE (SUBREG_REG (inner_op0)))))
9644 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9645 GET_MODE (SUBREG_REG (inner_op1))))))
9647 op0 = SUBREG_REG (inner_op0);
9648 op1 = SUBREG_REG (inner_op1);
9650 /* The resulting comparison is always unsigned since we masked
9651 off the original sign bit. */
9652 code = unsigned_condition (code);
9658 for (tmode = GET_CLASS_NARROWEST_MODE
9659 (GET_MODE_CLASS (GET_MODE (op0)));
9660 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9661 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9663 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9664 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9665 code = unsigned_condition (code);
9674 /* If both operands are NOT, we can strip off the outer operation
9675 and adjust the comparison code for swapped operands; similarly for
9676 NEG, except that this must be an equality comparison. */
9677 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9678 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9679 && (code == EQ || code == NE)))
9680 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9686 /* If the first operand is a constant, swap the operands and adjust the
9687 comparison code appropriately, but don't do this if the second operand
9688 is already a constant integer. */
9689 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9691 tem = op0, op0 = op1, op1 = tem;
9692 code = swap_condition (code);
9695 /* We now enter a loop during which we will try to simplify the comparison.
9696 For the most part, we only are concerned with comparisons with zero,
9697 but some things may really be comparisons with zero but not start
9698 out looking that way. */
9700 while (GET_CODE (op1) == CONST_INT)
9702 enum machine_mode mode = GET_MODE (op0);
9703 int mode_width = GET_MODE_BITSIZE (mode);
9704 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9705 int equality_comparison_p;
9706 int sign_bit_comparison_p;
9707 int unsigned_comparison_p;
9708 HOST_WIDE_INT const_op;
9710 /* We only want to handle integral modes. This catches VOIDmode,
9711 CCmode, and the floating-point modes. An exception is that we
9712 can handle VOIDmode if OP0 is a COMPARE or a comparison
9715 if (GET_MODE_CLASS (mode) != MODE_INT
9716 && ! (mode == VOIDmode
9717 && (GET_CODE (op0) == COMPARE
9718 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9721 /* Get the constant we are comparing against and turn off all bits
9722 not on in our mode. */
9723 const_op = INTVAL (op1);
9724 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9727 /* If we are comparing against a constant power of two and the value
9728 being compared can only have that single bit nonzero (e.g., it was
9729 `and'ed with that bit), we can replace this with a comparison
9732 && (code == EQ || code == NE || code == GE || code == GEU
9733 || code == LT || code == LTU)
9734 && mode_width <= HOST_BITS_PER_WIDE_INT
9735 && exact_log2 (const_op) >= 0
9736 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9738 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9739 op1 = const0_rtx, const_op = 0;
9742 /* Similarly, if we are comparing a value known to be either -1 or
9743 0 with -1, change it to the opposite comparison against zero. */
9746 && (code == EQ || code == NE || code == GT || code == LE
9747 || code == GEU || code == LTU)
9748 && num_sign_bit_copies (op0, mode) == mode_width)
9750 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9751 op1 = const0_rtx, const_op = 0;
9754 /* Do some canonicalizations based on the comparison code. We prefer
9755 comparisons against zero and then prefer equality comparisons.
9756 If we can reduce the size of a constant, we will do that too. */
9761 /* < C is equivalent to <= (C - 1) */
9765 op1 = GEN_INT (const_op);
9767 /* ... fall through to LE case below. */
9773 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9777 op1 = GEN_INT (const_op);
9781 /* If we are doing a <= 0 comparison on a value known to have
9782 a zero sign bit, we can replace this with == 0. */
9783 else if (const_op == 0
9784 && mode_width <= HOST_BITS_PER_WIDE_INT
9785 && (nonzero_bits (op0, mode)
9786 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9791 /* >= C is equivalent to > (C - 1). */
9795 op1 = GEN_INT (const_op);
9797 /* ... fall through to GT below. */
9803 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9807 op1 = GEN_INT (const_op);
9811 /* If we are doing a > 0 comparison on a value known to have
9812 a zero sign bit, we can replace this with != 0. */
9813 else if (const_op == 0
9814 && mode_width <= HOST_BITS_PER_WIDE_INT
9815 && (nonzero_bits (op0, mode)
9816 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9821 /* < C is equivalent to <= (C - 1). */
9825 op1 = GEN_INT (const_op);
9827 /* ... fall through ... */
9830 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9831 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9832 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9834 const_op = 0, op1 = const0_rtx;
9842 /* unsigned <= 0 is equivalent to == 0 */
9846 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9847 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9848 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9850 const_op = 0, op1 = const0_rtx;
9856 /* >= C is equivalent to < (C - 1). */
9860 op1 = GEN_INT (const_op);
9862 /* ... fall through ... */
9865 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9866 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9867 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9869 const_op = 0, op1 = const0_rtx;
9877 /* unsigned > 0 is equivalent to != 0 */
9881 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9882 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9883 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9885 const_op = 0, op1 = const0_rtx;
9894 /* Compute some predicates to simplify code below. */
9896 equality_comparison_p = (code == EQ || code == NE);
9897 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9898 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9901 /* If this is a sign bit comparison and we can do arithmetic in
9902 MODE, say that we will only be needing the sign bit of OP0. */
9903 if (sign_bit_comparison_p
9904 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9905 op0 = force_to_mode (op0, mode,
9907 << (GET_MODE_BITSIZE (mode) - 1)),
9910 /* Now try cases based on the opcode of OP0. If none of the cases
9911 does a "continue", we exit this loop immediately after the
9914 switch (GET_CODE (op0))
9917 /* If we are extracting a single bit from a variable position in
9918 a constant that has only a single bit set and are comparing it
9919 with zero, we can convert this into an equality comparison
9920 between the position and the location of the single bit. */
9922 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9923 && XEXP (op0, 1) == const1_rtx
9924 && equality_comparison_p && const_op == 0
9925 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9927 if (BITS_BIG_ENDIAN)
9930 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
9931 if (mode == VOIDmode)
9933 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9935 i = BITS_PER_WORD - 1 - i;
9939 op0 = XEXP (op0, 2);
9943 /* Result is nonzero iff shift count is equal to I. */
9944 code = reverse_condition (code);
9948 /* ... fall through ... */
9951 tem = expand_compound_operation (op0);
9960 /* If testing for equality, we can take the NOT of the constant. */
9961 if (equality_comparison_p
9962 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9964 op0 = XEXP (op0, 0);
9969 /* If just looking at the sign bit, reverse the sense of the
9971 if (sign_bit_comparison_p)
9973 op0 = XEXP (op0, 0);
9974 code = (code == GE ? LT : GE);
9980 /* If testing for equality, we can take the NEG of the constant. */
9981 if (equality_comparison_p
9982 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9984 op0 = XEXP (op0, 0);
9989 /* The remaining cases only apply to comparisons with zero. */
9993 /* When X is ABS or is known positive,
9994 (neg X) is < 0 if and only if X != 0. */
9996 if (sign_bit_comparison_p
9997 && (GET_CODE (XEXP (op0, 0)) == ABS
9998 || (mode_width <= HOST_BITS_PER_WIDE_INT
9999 && (nonzero_bits (XEXP (op0, 0), mode)
10000 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10002 op0 = XEXP (op0, 0);
10003 code = (code == LT ? NE : EQ);
10007 /* If we have NEG of something whose two high-order bits are the
10008 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10009 if (num_sign_bit_copies (op0, mode) >= 2)
10011 op0 = XEXP (op0, 0);
10012 code = swap_condition (code);
10018 /* If we are testing equality and our count is a constant, we
10019 can perform the inverse operation on our RHS. */
10020 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10021 && (tem = simplify_binary_operation (ROTATERT, mode,
10022 op1, XEXP (op0, 1))) != 0)
10024 op0 = XEXP (op0, 0);
10029 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10030 a particular bit. Convert it to an AND of a constant of that
10031 bit. This will be converted into a ZERO_EXTRACT. */
10032 if (const_op == 0 && sign_bit_comparison_p
10033 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10034 && mode_width <= HOST_BITS_PER_WIDE_INT)
10036 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10039 - INTVAL (XEXP (op0, 1)))));
10040 code = (code == LT ? NE : EQ);
10044 /* ... fall through ... */
10047 /* ABS is ignorable inside an equality comparison with zero. */
10048 if (const_op == 0 && equality_comparison_p)
10050 op0 = XEXP (op0, 0);
10057 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10058 to (compare FOO CONST) if CONST fits in FOO's mode and we
10059 are either testing inequality or have an unsigned comparison
10060 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10061 if (! unsigned_comparison_p
10062 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10063 <= HOST_BITS_PER_WIDE_INT)
10064 && ((unsigned HOST_WIDE_INT) const_op
10065 < (((unsigned HOST_WIDE_INT) 1
10066 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10068 op0 = XEXP (op0, 0);
10074 /* Check for the case where we are comparing A - C1 with C2,
10075 both constants are smaller than 1/2 the maximum positive
10076 value in MODE, and the comparison is equality or unsigned.
10077 In that case, if A is either zero-extended to MODE or has
10078 sufficient sign bits so that the high-order bit in MODE
10079 is a copy of the sign in the inner mode, we can prove that it is
10080 safe to do the operation in the wider mode. This simplifies
10081 many range checks. */
10083 if (mode_width <= HOST_BITS_PER_WIDE_INT
10084 && subreg_lowpart_p (op0)
10085 && GET_CODE (SUBREG_REG (op0)) == PLUS
10086 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10087 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10088 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10089 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10090 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10091 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10092 GET_MODE (SUBREG_REG (op0)))
10093 & ~ GET_MODE_MASK (mode))
10094 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10095 GET_MODE (SUBREG_REG (op0)))
10096 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10097 - GET_MODE_BITSIZE (mode)))))
10099 op0 = SUBREG_REG (op0);
10103 /* If the inner mode is narrower and we are extracting the low part,
10104 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10105 if (subreg_lowpart_p (op0)
10106 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10107 /* Fall through */ ;
10111 /* ... fall through ... */
10114 if ((unsigned_comparison_p || equality_comparison_p)
10115 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10116 <= HOST_BITS_PER_WIDE_INT)
10117 && ((unsigned HOST_WIDE_INT) const_op
10118 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10120 op0 = XEXP (op0, 0);
10126 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10127 this for equality comparisons due to pathological cases involving
10129 if (equality_comparison_p
10130 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10131 op1, XEXP (op0, 1))))
10133 op0 = XEXP (op0, 0);
10138 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10139 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10140 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10142 op0 = XEXP (XEXP (op0, 0), 0);
10143 code = (code == LT ? EQ : NE);
10149 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10150 (eq B (minus A C)), whichever simplifies. We can only do
10151 this for equality comparisons due to pathological cases involving
10153 if (equality_comparison_p
10154 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10155 XEXP (op0, 1), op1)))
10157 op0 = XEXP (op0, 0);
10162 if (equality_comparison_p
10163 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10164 XEXP (op0, 0), op1)))
10166 op0 = XEXP (op0, 1);
10171 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10172 of bits in X minus 1, is one iff X > 0. */
10173 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10174 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10175 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10176 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10178 op0 = XEXP (op0, 1);
10179 code = (code == GE ? LE : GT);
10185 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10186 if C is zero or B is a constant. */
10187 if (equality_comparison_p
10188 && 0 != (tem = simplify_binary_operation (XOR, mode,
10189 XEXP (op0, 1), op1)))
10191 op0 = XEXP (op0, 0);
10198 case LT: case LTU: case LE: case LEU:
10199 case GT: case GTU: case GE: case GEU:
10200 /* We can't do anything if OP0 is a condition code value, rather
10201 than an actual data value. */
10204 || XEXP (op0, 0) == cc0_rtx
10206 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10209 /* Get the two operands being compared. */
10210 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10211 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10213 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10215 /* Check for the cases where we simply want the result of the
10216 earlier test or the opposite of that result. */
10218 || (code == EQ && reversible_comparison_p (op0))
10219 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10220 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10221 && (STORE_FLAG_VALUE
10222 & (((HOST_WIDE_INT) 1
10223 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10225 || (code == GE && reversible_comparison_p (op0)))))
10227 code = (code == LT || code == NE
10228 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10229 op0 = tem, op1 = tem1;
10235 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10237 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10238 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10239 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10241 op0 = XEXP (op0, 1);
10242 code = (code == GE ? GT : LE);
10248 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10249 will be converted to a ZERO_EXTRACT later. */
10250 if (const_op == 0 && equality_comparison_p
10251 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10252 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10254 op0 = simplify_and_const_int
10255 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10257 XEXP (XEXP (op0, 0), 1)),
10258 (HOST_WIDE_INT) 1);
10262 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10263 zero and X is a comparison and C1 and C2 describe only bits set
10264 in STORE_FLAG_VALUE, we can compare with X. */
10265 if (const_op == 0 && equality_comparison_p
10266 && mode_width <= HOST_BITS_PER_WIDE_INT
10267 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10268 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10269 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10270 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10271 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10273 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10274 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10275 if ((~ STORE_FLAG_VALUE & mask) == 0
10276 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10277 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10278 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10280 op0 = XEXP (XEXP (op0, 0), 0);
10285 /* If we are doing an equality comparison of an AND of a bit equal
10286 to the sign bit, replace this with a LT or GE comparison of
10287 the underlying value. */
10288 if (equality_comparison_p
10290 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10291 && mode_width <= HOST_BITS_PER_WIDE_INT
10292 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10293 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10295 op0 = XEXP (op0, 0);
10296 code = (code == EQ ? GE : LT);
10300 /* If this AND operation is really a ZERO_EXTEND from a narrower
10301 mode, the constant fits within that mode, and this is either an
10302 equality or unsigned comparison, try to do this comparison in
10303 the narrower mode. */
10304 if ((equality_comparison_p || unsigned_comparison_p)
10305 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10306 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10307 & GET_MODE_MASK (mode))
10309 && const_op >> i == 0
10310 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10312 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10316 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10317 in both M1 and M2 and the SUBREG is either paradoxical or
10318 represents the low part, permute the SUBREG and the AND and
10320 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10322 #ifdef WORD_REGISTER_OPERATIONS
10324 > (GET_MODE_BITSIZE
10325 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10326 && mode_width <= BITS_PER_WORD)
10329 <= (GET_MODE_BITSIZE
10330 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10331 && subreg_lowpart_p (XEXP (op0, 0))))
10332 #ifndef WORD_REGISTER_OPERATIONS
10333 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10334 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10335 As originally written the upper bits have a defined value
10336 due to the AND operation. However, if we commute the AND
10337 inside the SUBREG then they no longer have defined values
10338 and the meaning of the code has been changed. */
10339 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10340 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10342 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10343 && mode_width <= HOST_BITS_PER_WIDE_INT
10344 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10345 <= HOST_BITS_PER_WIDE_INT)
10346 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10347 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10348 & INTVAL (XEXP (op0, 1)))
10349 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10350 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10351 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10355 = gen_lowpart_for_combine
10357 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10358 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10365 /* If we have (compare (ashift FOO N) (const_int C)) and
10366 the high order N bits of FOO (N+1 if an inequality comparison)
10367 are known to be zero, we can do this by comparing FOO with C
10368 shifted right N bits so long as the low-order N bits of C are
10370 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10371 && INTVAL (XEXP (op0, 1)) >= 0
10372 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10373 < HOST_BITS_PER_WIDE_INT)
10375 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10376 && mode_width <= HOST_BITS_PER_WIDE_INT
10377 && (nonzero_bits (XEXP (op0, 0), mode)
10378 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10379 + ! equality_comparison_p))) == 0)
10381 /* We must perform a logical shift, not an arithmetic one,
10382 as we want the top N bits of C to be zero. */
10383 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10385 temp >>= INTVAL (XEXP (op0, 1));
10386 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10387 op0 = XEXP (op0, 0);
10391 /* If we are doing a sign bit comparison, it means we are testing
10392 a particular bit. Convert it to the appropriate AND. */
10393 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10394 && mode_width <= HOST_BITS_PER_WIDE_INT)
10396 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10399 - INTVAL (XEXP (op0, 1)))));
10400 code = (code == LT ? NE : EQ);
10404 /* If this an equality comparison with zero and we are shifting
10405 the low bit to the sign bit, we can convert this to an AND of the
10407 if (const_op == 0 && equality_comparison_p
10408 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10409 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10411 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10412 (HOST_WIDE_INT) 1);
10418 /* If this is an equality comparison with zero, we can do this
10419 as a logical shift, which might be much simpler. */
10420 if (equality_comparison_p && const_op == 0
10421 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10423 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10425 INTVAL (XEXP (op0, 1)));
10429 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10430 do the comparison in a narrower mode. */
10431 if (! unsigned_comparison_p
10432 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10433 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10434 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10435 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10436 MODE_INT, 1)) != BLKmode
10437 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10438 || ((unsigned HOST_WIDE_INT) - const_op
10439 <= GET_MODE_MASK (tmode))))
10441 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10445 /* ... fall through ... */
10447 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10448 the low order N bits of FOO are known to be zero, we can do this
10449 by comparing FOO with C shifted left N bits so long as no
10450 overflow occurs. */
10451 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10452 && INTVAL (XEXP (op0, 1)) >= 0
10453 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10454 && mode_width <= HOST_BITS_PER_WIDE_INT
10455 && (nonzero_bits (XEXP (op0, 0), mode)
10456 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10458 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10461 const_op <<= INTVAL (XEXP (op0, 1));
10462 op1 = GEN_INT (const_op);
10463 op0 = XEXP (op0, 0);
10467 /* If we are using this shift to extract just the sign bit, we
10468 can replace this with an LT or GE comparison. */
10470 && (equality_comparison_p || sign_bit_comparison_p)
10471 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10472 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10474 op0 = XEXP (op0, 0);
10475 code = (code == NE || code == GT ? LT : GE);
10487 /* Now make any compound operations involved in this comparison. Then,
10488 check for an outmost SUBREG on OP0 that is not doing anything or is
10489 paradoxical. The latter case can only occur when it is known that the
10490 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10491 We can never remove a SUBREG for a non-equality comparison because the
10492 sign bit is in a different place in the underlying object. */
10494 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10495 op1 = make_compound_operation (op1, SET);
10497 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10498 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10499 && (code == NE || code == EQ)
10500 && ((GET_MODE_SIZE (GET_MODE (op0))
10501 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10503 op0 = SUBREG_REG (op0);
10504 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10507 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10508 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10509 && (code == NE || code == EQ)
10510 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10511 <= HOST_BITS_PER_WIDE_INT)
10512 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10513 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10514 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10516 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10517 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10518 op0 = SUBREG_REG (op0), op1 = tem;
10520 /* We now do the opposite procedure: Some machines don't have compare
10521 insns in all modes. If OP0's mode is an integer mode smaller than a
10522 word and we can't do a compare in that mode, see if there is a larger
10523 mode for which we can do the compare. There are a number of cases in
10524 which we can use the wider mode. */
10526 mode = GET_MODE (op0);
10527 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10528 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10529 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10530 for (tmode = GET_MODE_WIDER_MODE (mode);
10532 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10533 tmode = GET_MODE_WIDER_MODE (tmode))
10534 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10536 /* If the only nonzero bits in OP0 and OP1 are those in the
10537 narrower mode and this is an equality or unsigned comparison,
10538 we can use the wider mode. Similarly for sign-extended
10539 values, in which case it is true for all comparisons. */
10540 if (((code == EQ || code == NE
10541 || code == GEU || code == GTU || code == LEU || code == LTU)
10542 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10543 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10544 || ((num_sign_bit_copies (op0, tmode)
10545 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10546 && (num_sign_bit_copies (op1, tmode)
10547 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10549 op0 = gen_lowpart_for_combine (tmode, op0);
10550 op1 = gen_lowpart_for_combine (tmode, op1);
10554 /* If this is a test for negative, we can make an explicit
10555 test of the sign bit. */
10557 if (op1 == const0_rtx && (code == LT || code == GE)
10558 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10560 op0 = gen_binary (AND, tmode,
10561 gen_lowpart_for_combine (tmode, op0),
10562 GEN_INT ((HOST_WIDE_INT) 1
10563 << (GET_MODE_BITSIZE (mode) - 1)));
10564 code = (code == LT) ? NE : EQ;
10569 #ifdef CANONICALIZE_COMPARISON
10570 /* If this machine only supports a subset of valid comparisons, see if we
10571 can convert an unsupported one into a supported one. */
10572 CANONICALIZE_COMPARISON (code, op0, op1);
10581 /* Return 1 if we know that X, a comparison operation, is not operating
10582 on a floating-point value or is EQ or NE, meaning that we can safely
10586 reversible_comparison_p (x)
10589 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10591 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10594 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10597 case MODE_PARTIAL_INT:
10598 case MODE_COMPLEX_INT:
10602 /* If the mode of the condition codes tells us that this is safe,
10603 we need look no further. */
10604 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10607 /* Otherwise try and find where the condition codes were last set and
10609 x = get_last_value (XEXP (x, 0));
10610 return (x && GET_CODE (x) == COMPARE
10611 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10618 /* Utility function for following routine. Called when X is part of a value
10619 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10620 for each register mentioned. Similar to mention_regs in cse.c */
10623 update_table_tick (x)
10626 register enum rtx_code code = GET_CODE (x);
10627 register const char *fmt = GET_RTX_FORMAT (code);
10632 int regno = REGNO (x);
10633 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10634 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10636 for (i = regno; i < endregno; i++)
10637 reg_last_set_table_tick[i] = label_tick;
10642 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10643 /* Note that we can't have an "E" in values stored; see
10644 get_last_value_validate. */
10646 update_table_tick (XEXP (x, i));
10649 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10650 are saying that the register is clobbered and we no longer know its
10651 value. If INSN is zero, don't update reg_last_set; this is only permitted
10652 with VALUE also zero and is used to invalidate the register. */
10655 record_value_for_reg (reg, insn, value)
10660 int regno = REGNO (reg);
10661 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10662 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10665 /* If VALUE contains REG and we have a previous value for REG, substitute
10666 the previous value. */
10667 if (value && insn && reg_overlap_mentioned_p (reg, value))
10671 /* Set things up so get_last_value is allowed to see anything set up to
10673 subst_low_cuid = INSN_CUID (insn);
10674 tem = get_last_value (reg);
10677 value = replace_rtx (copy_rtx (value), reg, tem);
10680 /* For each register modified, show we don't know its value, that
10681 we don't know about its bitwise content, that its value has been
10682 updated, and that we don't know the location of the death of the
10684 for (i = regno; i < endregno; i ++)
10687 reg_last_set[i] = insn;
10688 reg_last_set_value[i] = 0;
10689 reg_last_set_mode[i] = 0;
10690 reg_last_set_nonzero_bits[i] = 0;
10691 reg_last_set_sign_bit_copies[i] = 0;
10692 reg_last_death[i] = 0;
10695 /* Mark registers that are being referenced in this value. */
10697 update_table_tick (value);
10699 /* Now update the status of each register being set.
10700 If someone is using this register in this block, set this register
10701 to invalid since we will get confused between the two lives in this
10702 basic block. This makes using this register always invalid. In cse, we
10703 scan the table to invalidate all entries using this register, but this
10704 is too much work for us. */
10706 for (i = regno; i < endregno; i++)
10708 reg_last_set_label[i] = label_tick;
10709 if (value && reg_last_set_table_tick[i] == label_tick)
10710 reg_last_set_invalid[i] = 1;
10712 reg_last_set_invalid[i] = 0;
10715 /* The value being assigned might refer to X (like in "x++;"). In that
10716 case, we must replace it with (clobber (const_int 0)) to prevent
10718 if (value && ! get_last_value_validate (&value, insn,
10719 reg_last_set_label[regno], 0))
10721 value = copy_rtx (value);
10722 if (! get_last_value_validate (&value, insn,
10723 reg_last_set_label[regno], 1))
10727 /* For the main register being modified, update the value, the mode, the
10728 nonzero bits, and the number of sign bit copies. */
10730 reg_last_set_value[regno] = value;
10734 subst_low_cuid = INSN_CUID (insn);
10735 reg_last_set_mode[regno] = GET_MODE (reg);
10736 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10737 reg_last_set_sign_bit_copies[regno]
10738 = num_sign_bit_copies (value, GET_MODE (reg));
10742 /* Used for communication between the following two routines. */
10743 static rtx record_dead_insn;
10745 /* Called via note_stores from record_dead_and_set_regs to handle one
10746 SET or CLOBBER in an insn. */
10749 record_dead_and_set_regs_1 (dest, setter)
10752 if (GET_CODE (dest) == SUBREG)
10753 dest = SUBREG_REG (dest);
10755 if (GET_CODE (dest) == REG)
10757 /* If we are setting the whole register, we know its value. Otherwise
10758 show that we don't know the value. We can handle SUBREG in
10760 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10761 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10762 else if (GET_CODE (setter) == SET
10763 && GET_CODE (SET_DEST (setter)) == SUBREG
10764 && SUBREG_REG (SET_DEST (setter)) == dest
10765 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10766 && subreg_lowpart_p (SET_DEST (setter)))
10767 record_value_for_reg (dest, record_dead_insn,
10768 gen_lowpart_for_combine (GET_MODE (dest),
10769 SET_SRC (setter)));
10771 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10773 else if (GET_CODE (dest) == MEM
10774 /* Ignore pushes, they clobber nothing. */
10775 && ! push_operand (dest, GET_MODE (dest)))
10776 mem_last_set = INSN_CUID (record_dead_insn);
10779 /* Update the records of when each REG was most recently set or killed
10780 for the things done by INSN. This is the last thing done in processing
10781 INSN in the combiner loop.
10783 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10784 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10785 and also the similar information mem_last_set (which insn most recently
10786 modified memory) and last_call_cuid (which insn was the most recent
10787 subroutine call). */
10790 record_dead_and_set_regs (insn)
10796 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10798 if (REG_NOTE_KIND (link) == REG_DEAD
10799 && GET_CODE (XEXP (link, 0)) == REG)
10801 int regno = REGNO (XEXP (link, 0));
10803 = regno + (regno < FIRST_PSEUDO_REGISTER
10804 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10807 for (i = regno; i < endregno; i++)
10808 reg_last_death[i] = insn;
10810 else if (REG_NOTE_KIND (link) == REG_INC)
10811 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10814 if (GET_CODE (insn) == CALL_INSN)
10816 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10817 if (call_used_regs[i])
10819 reg_last_set_value[i] = 0;
10820 reg_last_set_mode[i] = 0;
10821 reg_last_set_nonzero_bits[i] = 0;
10822 reg_last_set_sign_bit_copies[i] = 0;
10823 reg_last_death[i] = 0;
10826 last_call_cuid = mem_last_set = INSN_CUID (insn);
10829 record_dead_insn = insn;
10830 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10833 /* Utility routine for the following function. Verify that all the registers
10834 mentioned in *LOC are valid when *LOC was part of a value set when
10835 label_tick == TICK. Return 0 if some are not.
10837 If REPLACE is non-zero, replace the invalid reference with
10838 (clobber (const_int 0)) and return 1. This replacement is useful because
10839 we often can get useful information about the form of a value (e.g., if
10840 it was produced by a shift that always produces -1 or 0) even though
10841 we don't know exactly what registers it was produced from. */
10844 get_last_value_validate (loc, insn, tick, replace)
10851 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10852 int len = GET_RTX_LENGTH (GET_CODE (x));
10855 if (GET_CODE (x) == REG)
10857 int regno = REGNO (x);
10858 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10859 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10862 for (j = regno; j < endregno; j++)
10863 if (reg_last_set_invalid[j]
10864 /* If this is a pseudo-register that was only set once and not
10865 live at the beginning of the function, it is always valid. */
10866 || (! (regno >= FIRST_PSEUDO_REGISTER
10867 && REG_N_SETS (regno) == 1
10868 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))
10869 && reg_last_set_label[j] > tick))
10872 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10878 /* If this is a memory reference, make sure that there were
10879 no stores after it that might have clobbered the value. We don't
10880 have alias info, so we assume any store invalidates it. */
10881 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10882 && INSN_CUID (insn) <= mem_last_set)
10885 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10889 for (i = 0; i < len; i++)
10891 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10892 /* Don't bother with these. They shouldn't occur anyway. */
10896 /* If we haven't found a reason for it to be invalid, it is valid. */
10900 /* Get the last value assigned to X, if known. Some registers
10901 in the value may be replaced with (clobber (const_int 0)) if their value
10902 is known longer known reliably. */
10911 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10912 then convert it to the desired mode. If this is a paradoxical SUBREG,
10913 we cannot predict what values the "extra" bits might have. */
10914 if (GET_CODE (x) == SUBREG
10915 && subreg_lowpart_p (x)
10916 && (GET_MODE_SIZE (GET_MODE (x))
10917 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10918 && (value = get_last_value (SUBREG_REG (x))) != 0)
10919 return gen_lowpart_for_combine (GET_MODE (x), value);
10921 if (GET_CODE (x) != REG)
10925 value = reg_last_set_value[regno];
10927 /* If we don't have a value, or if it isn't for this basic block and
10928 it's either a hard register, set more than once, or it's a live
10929 at the beginning of the function, return 0.
10931 Because if it's not live at the beginnning of the function then the reg
10932 is always set before being used (is never used without being set).
10933 And, if it's set only once, and it's always set before use, then all
10934 uses must have the same last value, even if it's not from this basic
10938 || (reg_last_set_label[regno] != label_tick
10939 && (regno < FIRST_PSEUDO_REGISTER
10940 || REG_N_SETS (regno) != 1
10941 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))))
10944 /* If the value was set in a later insn than the ones we are processing,
10945 we can't use it even if the register was only set once, but make a quick
10946 check to see if the previous insn set it to something. This is commonly
10947 the case when the same pseudo is used by repeated insns.
10949 This does not work if there exists an instruction which is temporarily
10950 not on the insn chain. */
10952 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10956 /* We can't do anything if the value is set in between the insns we are
10958 if (INSN_CUID (reg_last_set[regno]) <= INSN_CUID (subst_insn))
10961 /* We can not do anything useful in this case, because there is
10962 an instruction which is not on the insn chain. */
10963 if (subst_prev_insn)
10966 /* Skip over USE insns. They are not useful here, and they may have
10967 been made by combine, in which case they do not have a INSN_CUID
10968 value. We can't use prev_real_insn, because that would incorrectly
10969 take us backwards across labels. Skip over BARRIERs also, since
10970 they could have been made by combine. If we see one, we must be
10971 optimizing dead code, so it doesn't matter what we do. */
10972 for (insn = prev_nonnote_insn (subst_insn);
10973 insn && ((GET_CODE (insn) == INSN
10974 && GET_CODE (PATTERN (insn)) == USE)
10975 || GET_CODE (insn) == BARRIER
10976 || INSN_CUID (insn) >= subst_low_cuid);
10977 insn = prev_nonnote_insn (insn))
10981 && (set = single_set (insn)) != 0
10982 && rtx_equal_p (SET_DEST (set), x))
10984 value = SET_SRC (set);
10986 /* Make sure that VALUE doesn't reference X. Replace any
10987 explicit references with a CLOBBER. If there are any remaining
10988 references (rare), don't use the value. */
10990 if (reg_mentioned_p (x, value))
10991 value = replace_rtx (copy_rtx (value), x,
10992 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
10994 if (reg_overlap_mentioned_p (x, value))
11001 /* If the value has all its registers valid, return it. */
11002 if (get_last_value_validate (&value, reg_last_set[regno],
11003 reg_last_set_label[regno], 0))
11006 /* Otherwise, make a copy and replace any invalid register with
11007 (clobber (const_int 0)). If that fails for some reason, return 0. */
11009 value = copy_rtx (value);
11010 if (get_last_value_validate (&value, reg_last_set[regno],
11011 reg_last_set_label[regno], 1))
11017 /* Return nonzero if expression X refers to a REG or to memory
11018 that is set in an instruction more recent than FROM_CUID. */
11021 use_crosses_set_p (x, from_cuid)
11025 register const char *fmt;
11027 register enum rtx_code code = GET_CODE (x);
11031 register int regno = REGNO (x);
11032 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11033 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11035 #ifdef PUSH_ROUNDING
11036 /* Don't allow uses of the stack pointer to be moved,
11037 because we don't know whether the move crosses a push insn. */
11038 if (regno == STACK_POINTER_REGNUM)
11041 for (;regno < endreg; regno++)
11042 if (reg_last_set[regno]
11043 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11048 if (code == MEM && mem_last_set > from_cuid)
11051 fmt = GET_RTX_FORMAT (code);
11053 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11058 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11059 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11062 else if (fmt[i] == 'e'
11063 && use_crosses_set_p (XEXP (x, i), from_cuid))
11069 /* Define three variables used for communication between the following
11072 static int reg_dead_regno, reg_dead_endregno;
11073 static int reg_dead_flag;
11075 /* Function called via note_stores from reg_dead_at_p.
11077 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11078 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11081 reg_dead_at_p_1 (dest, x)
11085 int regno, endregno;
11087 if (GET_CODE (dest) != REG)
11090 regno = REGNO (dest);
11091 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11092 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11094 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11095 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11098 /* Return non-zero if REG is known to be dead at INSN.
11100 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11101 referencing REG, it is dead. If we hit a SET referencing REG, it is
11102 live. Otherwise, see if it is live or dead at the start of the basic
11103 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11104 must be assumed to be always live. */
11107 reg_dead_at_p (reg, insn)
11113 /* Set variables for reg_dead_at_p_1. */
11114 reg_dead_regno = REGNO (reg);
11115 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11116 ? HARD_REGNO_NREGS (reg_dead_regno,
11122 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11123 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11125 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11126 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11130 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11131 beginning of function. */
11132 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11133 insn = prev_nonnote_insn (insn))
11135 note_stores (PATTERN (insn), reg_dead_at_p_1);
11137 return reg_dead_flag == 1 ? 1 : 0;
11139 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11143 /* Get the basic block number that we were in. */
11148 for (block = 0; block < n_basic_blocks; block++)
11149 if (insn == BLOCK_HEAD (block))
11152 if (block == n_basic_blocks)
11156 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11157 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11163 /* Note hard registers in X that are used. This code is similar to
11164 that in flow.c, but much simpler since we don't care about pseudos. */
11167 mark_used_regs_combine (x)
11170 register RTX_CODE code = GET_CODE (x);
11171 register int regno;
11183 case ADDR_DIFF_VEC:
11186 /* CC0 must die in the insn after it is set, so we don't need to take
11187 special note of it here. */
11193 /* If we are clobbering a MEM, mark any hard registers inside the
11194 address as used. */
11195 if (GET_CODE (XEXP (x, 0)) == MEM)
11196 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11201 /* A hard reg in a wide mode may really be multiple registers.
11202 If so, mark all of them just like the first. */
11203 if (regno < FIRST_PSEUDO_REGISTER)
11205 /* None of this applies to the stack, frame or arg pointers */
11206 if (regno == STACK_POINTER_REGNUM
11207 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11208 || regno == HARD_FRAME_POINTER_REGNUM
11210 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11211 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11213 || regno == FRAME_POINTER_REGNUM)
11216 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11218 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11224 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11226 register rtx testreg = SET_DEST (x);
11228 while (GET_CODE (testreg) == SUBREG
11229 || GET_CODE (testreg) == ZERO_EXTRACT
11230 || GET_CODE (testreg) == SIGN_EXTRACT
11231 || GET_CODE (testreg) == STRICT_LOW_PART)
11232 testreg = XEXP (testreg, 0);
11234 if (GET_CODE (testreg) == MEM)
11235 mark_used_regs_combine (XEXP (testreg, 0));
11237 mark_used_regs_combine (SET_SRC (x));
11245 /* Recursively scan the operands of this expression. */
11248 register const char *fmt = GET_RTX_FORMAT (code);
11250 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11253 mark_used_regs_combine (XEXP (x, i));
11254 else if (fmt[i] == 'E')
11258 for (j = 0; j < XVECLEN (x, i); j++)
11259 mark_used_regs_combine (XVECEXP (x, i, j));
11266 /* Remove register number REGNO from the dead registers list of INSN.
11268 Return the note used to record the death, if there was one. */
11271 remove_death (regno, insn)
11275 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11279 REG_N_DEATHS (regno)--;
11280 remove_note (insn, note);
11286 /* For each register (hardware or pseudo) used within expression X, if its
11287 death is in an instruction with cuid between FROM_CUID (inclusive) and
11288 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11289 list headed by PNOTES.
11291 That said, don't move registers killed by maybe_kill_insn.
11293 This is done when X is being merged by combination into TO_INSN. These
11294 notes will then be distributed as needed. */
11297 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11299 rtx maybe_kill_insn;
11304 register const char *fmt;
11305 register int len, i;
11306 register enum rtx_code code = GET_CODE (x);
11310 register int regno = REGNO (x);
11311 register rtx where_dead = reg_last_death[regno];
11312 register rtx before_dead, after_dead;
11314 /* Don't move the register if it gets killed in between from and to */
11315 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11316 && !reg_referenced_p (x, maybe_kill_insn))
11319 /* WHERE_DEAD could be a USE insn made by combine, so first we
11320 make sure that we have insns with valid INSN_CUID values. */
11321 before_dead = where_dead;
11322 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11323 before_dead = PREV_INSN (before_dead);
11324 after_dead = where_dead;
11325 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11326 after_dead = NEXT_INSN (after_dead);
11328 if (before_dead && after_dead
11329 && INSN_CUID (before_dead) >= from_cuid
11330 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11331 || (where_dead != after_dead
11332 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11334 rtx note = remove_death (regno, where_dead);
11336 /* It is possible for the call above to return 0. This can occur
11337 when reg_last_death points to I2 or I1 that we combined with.
11338 In that case make a new note.
11340 We must also check for the case where X is a hard register
11341 and NOTE is a death note for a range of hard registers
11342 including X. In that case, we must put REG_DEAD notes for
11343 the remaining registers in place of NOTE. */
11345 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11346 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11347 > GET_MODE_SIZE (GET_MODE (x))))
11349 int deadregno = REGNO (XEXP (note, 0));
11351 = (deadregno + HARD_REGNO_NREGS (deadregno,
11352 GET_MODE (XEXP (note, 0))));
11353 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11356 for (i = deadregno; i < deadend; i++)
11357 if (i < regno || i >= ourend)
11358 REG_NOTES (where_dead)
11359 = gen_rtx_EXPR_LIST (REG_DEAD,
11360 gen_rtx_REG (reg_raw_mode[i], i),
11361 REG_NOTES (where_dead));
11363 /* If we didn't find any note, or if we found a REG_DEAD note that
11364 covers only part of the given reg, and we have a multi-reg hard
11365 register, then to be safe we must check for REG_DEAD notes
11366 for each register other than the first. They could have
11367 their own REG_DEAD notes lying around. */
11368 else if ((note == 0
11370 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11371 < GET_MODE_SIZE (GET_MODE (x)))))
11372 && regno < FIRST_PSEUDO_REGISTER
11373 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11375 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11380 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11384 for (i = regno + offset; i < ourend; i++)
11385 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11386 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11389 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11391 XEXP (note, 1) = *pnotes;
11395 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11397 REG_N_DEATHS (regno)++;
11403 else if (GET_CODE (x) == SET)
11405 rtx dest = SET_DEST (x);
11407 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11409 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11410 that accesses one word of a multi-word item, some
11411 piece of everything register in the expression is used by
11412 this insn, so remove any old death. */
11414 if (GET_CODE (dest) == ZERO_EXTRACT
11415 || GET_CODE (dest) == STRICT_LOW_PART
11416 || (GET_CODE (dest) == SUBREG
11417 && (((GET_MODE_SIZE (GET_MODE (dest))
11418 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11419 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11420 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11422 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11426 /* If this is some other SUBREG, we know it replaces the entire
11427 value, so use that as the destination. */
11428 if (GET_CODE (dest) == SUBREG)
11429 dest = SUBREG_REG (dest);
11431 /* If this is a MEM, adjust deaths of anything used in the address.
11432 For a REG (the only other possibility), the entire value is
11433 being replaced so the old value is not used in this insn. */
11435 if (GET_CODE (dest) == MEM)
11436 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11441 else if (GET_CODE (x) == CLOBBER)
11444 len = GET_RTX_LENGTH (code);
11445 fmt = GET_RTX_FORMAT (code);
11447 for (i = 0; i < len; i++)
11452 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11453 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11456 else if (fmt[i] == 'e')
11457 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11461 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11462 pattern of an insn. X must be a REG. */
11465 reg_bitfield_target_p (x, body)
11471 if (GET_CODE (body) == SET)
11473 rtx dest = SET_DEST (body);
11475 int regno, tregno, endregno, endtregno;
11477 if (GET_CODE (dest) == ZERO_EXTRACT)
11478 target = XEXP (dest, 0);
11479 else if (GET_CODE (dest) == STRICT_LOW_PART)
11480 target = SUBREG_REG (XEXP (dest, 0));
11484 if (GET_CODE (target) == SUBREG)
11485 target = SUBREG_REG (target);
11487 if (GET_CODE (target) != REG)
11490 tregno = REGNO (target), regno = REGNO (x);
11491 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11492 return target == x;
11494 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11495 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11497 return endregno > tregno && regno < endtregno;
11500 else if (GET_CODE (body) == PARALLEL)
11501 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11502 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11508 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11509 as appropriate. I3 and I2 are the insns resulting from the combination
11510 insns including FROM (I2 may be zero).
11512 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11513 not need REG_DEAD notes because they are being substituted for. This
11514 saves searching in the most common cases.
11516 Each note in the list is either ignored or placed on some insns, depending
11517 on the type of note. */
11520 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11524 rtx elim_i2, elim_i1;
11526 rtx note, next_note;
11529 for (note = notes; note; note = next_note)
11531 rtx place = 0, place2 = 0;
11533 /* If this NOTE references a pseudo register, ensure it references
11534 the latest copy of that register. */
11535 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11536 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11537 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11539 next_note = XEXP (note, 1);
11540 switch (REG_NOTE_KIND (note))
11543 case REG_EXEC_COUNT:
11544 /* Doesn't matter much where we put this, as long as it's somewhere.
11545 It is preferable to keep these notes on branches, which is most
11546 likely to be i3. */
11550 case REG_EH_REGION:
11551 case REG_EH_RETHROW:
11552 /* These notes must remain with the call. It should not be
11553 possible for both I2 and I3 to be a call. */
11554 if (GET_CODE (i3) == CALL_INSN)
11556 else if (i2 && GET_CODE (i2) == CALL_INSN)
11563 /* Any clobbers for i3 may still exist, and so we must process
11564 REG_UNUSED notes from that insn.
11566 Any clobbers from i2 or i1 can only exist if they were added by
11567 recog_for_combine. In that case, recog_for_combine created the
11568 necessary REG_UNUSED notes. Trying to keep any original
11569 REG_UNUSED notes from these insns can cause incorrect output
11570 if it is for the same register as the original i3 dest.
11571 In that case, we will notice that the register is set in i3,
11572 and then add a REG_UNUSED note for the destination of i3, which
11573 is wrong. However, it is possible to have REG_UNUSED notes from
11574 i2 or i1 for register which were both used and clobbered, so
11575 we keep notes from i2 or i1 if they will turn into REG_DEAD
11578 /* If this register is set or clobbered in I3, put the note there
11579 unless there is one already. */
11580 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11582 if (from_insn != i3)
11585 if (! (GET_CODE (XEXP (note, 0)) == REG
11586 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11587 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11590 /* Otherwise, if this register is used by I3, then this register
11591 now dies here, so we must put a REG_DEAD note here unless there
11593 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11594 && ! (GET_CODE (XEXP (note, 0)) == REG
11595 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11596 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11598 PUT_REG_NOTE_KIND (note, REG_DEAD);
11607 /* These notes say something about results of an insn. We can
11608 only support them if they used to be on I3 in which case they
11609 remain on I3. Otherwise they are ignored.
11611 If the note refers to an expression that is not a constant, we
11612 must also ignore the note since we cannot tell whether the
11613 equivalence is still true. It might be possible to do
11614 slightly better than this (we only have a problem if I2DEST
11615 or I1DEST is present in the expression), but it doesn't
11616 seem worth the trouble. */
11618 if (from_insn == i3
11619 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11624 case REG_NO_CONFLICT:
11625 /* These notes say something about how a register is used. They must
11626 be present on any use of the register in I2 or I3. */
11627 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11630 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11640 /* This can show up in several ways -- either directly in the
11641 pattern, or hidden off in the constant pool with (or without?)
11642 a REG_EQUAL note. */
11643 /* ??? Ignore the without-reg_equal-note problem for now. */
11644 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11645 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11646 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11647 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11651 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11652 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11653 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11654 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11664 /* It is too much trouble to try to see if this note is still
11665 correct in all situations. It is better to simply delete it. */
11669 /* If the insn previously containing this note still exists,
11670 put it back where it was. Otherwise move it to the previous
11671 insn. Adjust the corresponding REG_LIBCALL note. */
11672 if (GET_CODE (from_insn) != NOTE)
11676 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11677 place = prev_real_insn (from_insn);
11679 XEXP (tem, 0) = place;
11684 /* This is handled similarly to REG_RETVAL. */
11685 if (GET_CODE (from_insn) != NOTE)
11689 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11690 place = next_real_insn (from_insn);
11692 XEXP (tem, 0) = place;
11697 /* If the register is used as an input in I3, it dies there.
11698 Similarly for I2, if it is non-zero and adjacent to I3.
11700 If the register is not used as an input in either I3 or I2
11701 and it is not one of the registers we were supposed to eliminate,
11702 there are two possibilities. We might have a non-adjacent I2
11703 or we might have somehow eliminated an additional register
11704 from a computation. For example, we might have had A & B where
11705 we discover that B will always be zero. In this case we will
11706 eliminate the reference to A.
11708 In both cases, we must search to see if we can find a previous
11709 use of A and put the death note there. */
11712 && GET_CODE (from_insn) == CALL_INSN
11713 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11715 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11717 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11718 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11721 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11724 /* If the register is used in both I2 and I3 and it dies in I3,
11725 we might have added another reference to it. If reg_n_refs
11726 was 2, bump it to 3. This has to be correct since the
11727 register must have been set somewhere. The reason this is
11728 done is because local-alloc.c treats 2 references as a
11731 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11732 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11733 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11734 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11738 basic_block bb = BASIC_BLOCK (this_basic_block);
11740 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11742 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
11744 if (tem == bb->head)
11749 /* If the register is being set at TEM, see if that is all
11750 TEM is doing. If so, delete TEM. Otherwise, make this
11751 into a REG_UNUSED note instead. */
11752 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11754 rtx set = single_set (tem);
11755 rtx inner_dest = 0;
11757 rtx cc0_setter = NULL_RTX;
11761 for (inner_dest = SET_DEST (set);
11762 GET_CODE (inner_dest) == STRICT_LOW_PART
11763 || GET_CODE (inner_dest) == SUBREG
11764 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11765 inner_dest = XEXP (inner_dest, 0))
11768 /* Verify that it was the set, and not a clobber that
11769 modified the register.
11771 CC0 targets must be careful to maintain setter/user
11772 pairs. If we cannot delete the setter due to side
11773 effects, mark the user with an UNUSED note instead
11776 if (set != 0 && ! side_effects_p (SET_SRC (set))
11777 && rtx_equal_p (XEXP (note, 0), inner_dest)
11779 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11780 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11781 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11785 /* Move the notes and links of TEM elsewhere.
11786 This might delete other dead insns recursively.
11787 First set the pattern to something that won't use
11790 PATTERN (tem) = pc_rtx;
11792 distribute_notes (REG_NOTES (tem), tem, tem,
11793 NULL_RTX, NULL_RTX, NULL_RTX);
11794 distribute_links (LOG_LINKS (tem));
11796 PUT_CODE (tem, NOTE);
11797 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11798 NOTE_SOURCE_FILE (tem) = 0;
11801 /* Delete the setter too. */
11804 PATTERN (cc0_setter) = pc_rtx;
11806 distribute_notes (REG_NOTES (cc0_setter),
11807 cc0_setter, cc0_setter,
11808 NULL_RTX, NULL_RTX, NULL_RTX);
11809 distribute_links (LOG_LINKS (cc0_setter));
11811 PUT_CODE (cc0_setter, NOTE);
11812 NOTE_LINE_NUMBER (cc0_setter)
11813 = NOTE_INSN_DELETED;
11814 NOTE_SOURCE_FILE (cc0_setter) = 0;
11818 /* If the register is both set and used here, put the
11819 REG_DEAD note here, but place a REG_UNUSED note
11820 here too unless there already is one. */
11821 else if (reg_referenced_p (XEXP (note, 0),
11826 if (! find_regno_note (tem, REG_UNUSED,
11827 REGNO (XEXP (note, 0))))
11829 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
11834 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11836 /* If there isn't already a REG_UNUSED note, put one
11838 if (! find_regno_note (tem, REG_UNUSED,
11839 REGNO (XEXP (note, 0))))
11844 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11845 || (GET_CODE (tem) == CALL_INSN
11846 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11850 /* If we are doing a 3->2 combination, and we have a
11851 register which formerly died in i3 and was not used
11852 by i2, which now no longer dies in i3 and is used in
11853 i2 but does not die in i2, and place is between i2
11854 and i3, then we may need to move a link from place to
11856 if (i2 && INSN_UID (place) <= max_uid_cuid
11857 && INSN_CUID (place) > INSN_CUID (i2)
11858 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11859 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11861 rtx links = LOG_LINKS (place);
11862 LOG_LINKS (place) = 0;
11863 distribute_links (links);
11868 if (tem == bb->head)
11872 /* We haven't found an insn for the death note and it
11873 is still a REG_DEAD note, but we have hit the beginning
11874 of the block. If the existing life info says the reg
11875 was dead, there's nothing left to do. Otherwise, we'll
11876 need to do a global life update after combine. */
11877 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0)
11879 int regno = REGNO (XEXP (note, 0));
11880 if (REGNO_REG_SET_P (bb->global_live_at_start, regno))
11882 SET_BIT (refresh_blocks, this_basic_block);
11888 /* If the register is set or already dead at PLACE, we needn't do
11889 anything with this note if it is still a REG_DEAD note.
11890 We can here if it is set at all, not if is it totally replace,
11891 which is what `dead_or_set_p' checks, so also check for it being
11894 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11896 int regno = REGNO (XEXP (note, 0));
11898 if (dead_or_set_p (place, XEXP (note, 0))
11899 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11901 /* Unless the register previously died in PLACE, clear
11902 reg_last_death. [I no longer understand why this is
11904 if (reg_last_death[regno] != place)
11905 reg_last_death[regno] = 0;
11909 reg_last_death[regno] = place;
11911 /* If this is a death note for a hard reg that is occupying
11912 multiple registers, ensure that we are still using all
11913 parts of the object. If we find a piece of the object
11914 that is unused, we must add a USE for that piece before
11915 PLACE and put the appropriate REG_DEAD note on it.
11917 An alternative would be to put a REG_UNUSED for the pieces
11918 on the insn that set the register, but that can't be done if
11919 it is not in the same block. It is simpler, though less
11920 efficient, to add the USE insns. */
11922 if (place && regno < FIRST_PSEUDO_REGISTER
11923 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11926 = regno + HARD_REGNO_NREGS (regno,
11927 GET_MODE (XEXP (note, 0)));
11931 for (i = regno; i < endregno; i++)
11932 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11933 && ! find_regno_fusage (place, USE, i))
11935 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11938 /* See if we already placed a USE note for this
11939 register in front of PLACE. */
11941 GET_CODE (PREV_INSN (p)) == INSN
11942 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11944 if (rtx_equal_p (piece,
11945 XEXP (PATTERN (PREV_INSN (p)), 0)))
11954 = emit_insn_before (gen_rtx_USE (VOIDmode,
11957 REG_NOTES (use_insn)
11958 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11959 REG_NOTES (use_insn));
11965 /* Check for the case where the register dying partially
11966 overlaps the register set by this insn. */
11968 for (i = regno; i < endregno; i++)
11969 if (dead_or_set_regno_p (place, i))
11977 /* Put only REG_DEAD notes for pieces that are
11978 still used and that are not already dead or set. */
11980 for (i = regno; i < endregno; i++)
11982 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11984 if ((reg_referenced_p (piece, PATTERN (place))
11985 || (GET_CODE (place) == CALL_INSN
11986 && find_reg_fusage (place, USE, piece)))
11987 && ! dead_or_set_p (place, piece)
11988 && ! reg_bitfield_target_p (piece,
11991 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11992 REG_NOTES (place));
12002 /* Any other notes should not be present at this point in the
12009 XEXP (note, 1) = REG_NOTES (place);
12010 REG_NOTES (place) = note;
12012 else if ((REG_NOTE_KIND (note) == REG_DEAD
12013 || REG_NOTE_KIND (note) == REG_UNUSED)
12014 && GET_CODE (XEXP (note, 0)) == REG)
12015 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12019 if ((REG_NOTE_KIND (note) == REG_DEAD
12020 || REG_NOTE_KIND (note) == REG_UNUSED)
12021 && GET_CODE (XEXP (note, 0)) == REG)
12022 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12024 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12025 REG_NOTE_KIND (note),
12027 REG_NOTES (place2));
12032 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12033 I3, I2, and I1 to new locations. This is also called in one case to
12034 add a link pointing at I3 when I3's destination is changed. */
12037 distribute_links (links)
12040 rtx link, next_link;
12042 for (link = links; link; link = next_link)
12048 next_link = XEXP (link, 1);
12050 /* If the insn that this link points to is a NOTE or isn't a single
12051 set, ignore it. In the latter case, it isn't clear what we
12052 can do other than ignore the link, since we can't tell which
12053 register it was for. Such links wouldn't be used by combine
12056 It is not possible for the destination of the target of the link to
12057 have been changed by combine. The only potential of this is if we
12058 replace I3, I2, and I1 by I3 and I2. But in that case the
12059 destination of I2 also remains unchanged. */
12061 if (GET_CODE (XEXP (link, 0)) == NOTE
12062 || (set = single_set (XEXP (link, 0))) == 0)
12065 reg = SET_DEST (set);
12066 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12067 || GET_CODE (reg) == SIGN_EXTRACT
12068 || GET_CODE (reg) == STRICT_LOW_PART)
12069 reg = XEXP (reg, 0);
12071 /* A LOG_LINK is defined as being placed on the first insn that uses
12072 a register and points to the insn that sets the register. Start
12073 searching at the next insn after the target of the link and stop
12074 when we reach a set of the register or the end of the basic block.
12076 Note that this correctly handles the link that used to point from
12077 I3 to I2. Also note that not much searching is typically done here
12078 since most links don't point very far away. */
12080 for (insn = NEXT_INSN (XEXP (link, 0));
12081 (insn && (this_basic_block == n_basic_blocks - 1
12082 || BLOCK_HEAD (this_basic_block + 1) != insn));
12083 insn = NEXT_INSN (insn))
12084 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12085 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12087 if (reg_referenced_p (reg, PATTERN (insn)))
12091 else if (GET_CODE (insn) == CALL_INSN
12092 && find_reg_fusage (insn, USE, reg))
12098 /* If we found a place to put the link, place it there unless there
12099 is already a link to the same insn as LINK at that point. */
12105 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12106 if (XEXP (link2, 0) == XEXP (link, 0))
12111 XEXP (link, 1) = LOG_LINKS (place);
12112 LOG_LINKS (place) = link;
12114 /* Set added_links_insn to the earliest insn we added a
12116 if (added_links_insn == 0
12117 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12118 added_links_insn = place;
12124 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12130 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12131 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12132 insn = NEXT_INSN (insn);
12134 if (INSN_UID (insn) > max_uid_cuid)
12137 return INSN_CUID (insn);
12141 dump_combine_stats (file)
12146 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12147 combine_attempts, combine_merges, combine_extras, combine_successes);
12151 dump_combine_total_stats (file)
12156 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12157 total_attempts, total_merges, total_extras, total_successes);