1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
428 buf = undobuf.frees, undobuf.frees = buf->next;
430 buf = (struct undo *) xmalloc (sizeof (struct undo));
434 buf->old_contents.r = oldval;
437 buf->next = undobuf.undos, undobuf.undos = buf;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into, newval)
448 unsigned int *into, newval;
451 unsigned int oldval = *into;
453 if (oldval == newval)
457 buf = undobuf.frees, undobuf.frees = buf->next;
459 buf = (struct undo *) xmalloc (sizeof (struct undo));
463 buf->old_contents.i = oldval;
466 buf->next = undobuf.undos, undobuf.undos = buf;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f, nregs)
486 rtx links, nextlinks;
488 int new_direct_jump_p = 0;
490 combine_attempts = 0;
493 combine_successes = 0;
495 combine_max_regno = nregs;
497 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
498 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
500 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
502 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
503 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
504 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
505 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
506 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
507 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
509 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs * sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
522 if (INSN_UID (insn) > i)
525 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
528 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid = 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn = NULL_RTX;
552 setup_incoming_promotions ();
554 refresh_blocks = sbitmap_alloc (n_basic_blocks);
555 sbitmap_zero (refresh_blocks);
558 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
560 uid_cuid[INSN_UID (insn)] = ++i;
566 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
568 record_dead_and_set_regs (insn);
571 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
572 if (REG_NOTE_KIND (links) == REG_INC)
573 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
578 if (GET_CODE (insn) == CODE_LABEL)
582 nonzero_sign_valid = 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block = -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block + 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block + 1) == insn)
602 if (GET_CODE (insn) == CODE_LABEL)
605 else if (INSN_P (insn))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn, PATTERN (insn));
611 /* Try this insn with each insn it links back to. */
613 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
614 if ((next = try_combine (insn, XEXP (links, 0),
615 NULL_RTX, &new_direct_jump_p)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
622 rtx link = XEXP (links, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in pursuing this chain any further. */
626 if (GET_CODE (link) == NOTE)
629 for (nextlinks = LOG_LINKS (link);
631 nextlinks = XEXP (nextlinks, 1))
632 if ((next = try_combine (insn, link,
634 &new_direct_jump_p)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn) == JUMP_INSN
647 && (prev = prev_nonnote_insn (insn)) != 0
648 && GET_CODE (prev) == INSN
649 && sets_cc0_p (PATTERN (prev)))
651 if ((next = try_combine (insn, prev,
652 NULL_RTX, &new_direct_jump_p)) != 0)
655 for (nextlinks = LOG_LINKS (prev); nextlinks;
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, prev,
659 &new_direct_jump_p)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn) == INSN
665 && (prev = prev_nonnote_insn (insn)) != 0
666 && GET_CODE (prev) == INSN
667 && sets_cc0_p (PATTERN (prev))
668 && GET_CODE (PATTERN (insn)) == SET
669 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
671 if ((next = try_combine (insn, prev,
672 NULL_RTX, &new_direct_jump_p)) != 0)
675 for (nextlinks = LOG_LINKS (prev); nextlinks;
676 nextlinks = XEXP (nextlinks, 1))
677 if ((next = try_combine (insn, prev,
679 &new_direct_jump_p)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
687 if (GET_CODE (XEXP (links, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
689 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
690 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && (next = try_combine (insn, XEXP (links, 0),
694 prev, &new_direct_jump_p)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
701 for (nextlinks = XEXP (links, 1); nextlinks;
702 nextlinks = XEXP (nextlinks, 1))
703 if ((next = try_combine (insn, XEXP (links, 0),
705 &new_direct_jump_p)) != 0)
708 if (GET_CODE (insn) != NOTE)
709 record_dead_and_set_regs (insn);
716 delete_noop_moves (f);
720 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
725 sbitmap_free (refresh_blocks);
726 free (reg_nonzero_bits);
727 free (reg_sign_bit_copies);
728 free (reg_last_death);
730 free (reg_last_set_value);
731 free (reg_last_set_table_tick);
732 free (reg_last_set_label);
733 free (reg_last_set_invalid);
734 free (reg_last_set_mode);
735 free (reg_last_set_nonzero_bits);
736 free (reg_last_set_sign_bit_copies);
740 struct undo *undo, *next;
741 for (undo = undobuf.frees; undo; undo = next)
749 total_attempts += combine_attempts;
750 total_merges += combine_merges;
751 total_extras += combine_extras;
752 total_successes += combine_successes;
754 nonzero_sign_valid = 0;
756 /* Make recognizer allow volatile MEMs again. */
759 return new_direct_jump_p;
762 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
765 init_reg_last_arrays ()
767 unsigned int nregs = combine_max_regno;
769 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
770 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
771 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
772 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
773 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
774 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
775 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
776 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
777 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
780 /* Set up any promoted values for incoming argument registers. */
783 setup_incoming_promotions ()
785 #ifdef PROMOTE_FUNCTION_ARGS
788 enum machine_mode mode;
790 rtx first = get_insns ();
792 #ifndef OUTGOING_REGNO
793 #define OUTGOING_REGNO(N) N
795 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
796 /* Check whether this register can hold an incoming pointer
797 argument. FUNCTION_ARG_REGNO_P tests outgoing register
798 numbers, so translate if necessary due to register windows. */
799 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
800 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
803 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
806 gen_rtx_CLOBBER (mode, const0_rtx)));
811 /* Called via note_stores. If X is a pseudo that is narrower than
812 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
814 If we are setting only a portion of X and we can't figure out what
815 portion, assume all bits will be used since we don't know what will
818 Similarly, set how many bits of X are known to be copies of the sign bit
819 at all locations in the function. This is the smallest number implied
823 set_nonzero_bits_and_sign_copies (x, set, data)
826 void *data ATTRIBUTE_UNUSED;
830 if (GET_CODE (x) == REG
831 && REGNO (x) >= FIRST_PSEUDO_REGISTER
832 /* If this register is undefined at the start of the file, we can't
833 say what its contents were. */
834 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
835 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
837 if (set == 0 || GET_CODE (set) == CLOBBER)
839 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
840 reg_sign_bit_copies[REGNO (x)] = 1;
844 /* If this is a complex assignment, see if we can convert it into a
845 simple assignment. */
846 set = expand_field_assignment (set);
848 /* If this is a simple assignment, or we have a paradoxical SUBREG,
849 set what we know about X. */
851 if (SET_DEST (set) == x
852 || (GET_CODE (SET_DEST (set)) == SUBREG
853 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
855 && SUBREG_REG (SET_DEST (set)) == x))
857 rtx src = SET_SRC (set);
859 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
860 /* If X is narrower than a word and SRC is a non-negative
861 constant that would appear negative in the mode of X,
862 sign-extend it for use in reg_nonzero_bits because some
863 machines (maybe most) will actually do the sign-extension
864 and this is the conservative approach.
866 ??? For 2.5, try to tighten up the MD files in this regard
867 instead of this kludge. */
869 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
870 && GET_CODE (src) == CONST_INT
872 && 0 != (INTVAL (src)
874 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
875 src = GEN_INT (INTVAL (src)
876 | ((HOST_WIDE_INT) (-1)
877 << GET_MODE_BITSIZE (GET_MODE (x))));
880 reg_nonzero_bits[REGNO (x)]
881 |= nonzero_bits (src, nonzero_bits_mode);
882 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
883 if (reg_sign_bit_copies[REGNO (x)] == 0
884 || reg_sign_bit_copies[REGNO (x)] > num)
885 reg_sign_bit_copies[REGNO (x)] = num;
889 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
890 reg_sign_bit_copies[REGNO (x)] = 1;
895 /* See if INSN can be combined into I3. PRED and SUCC are optionally
896 insns that were previously combined into I3 or that will be combined
897 into the merger of INSN and I3.
899 Return 0 if the combination is not allowed for any reason.
901 If the combination is allowed, *PDEST will be set to the single
902 destination of INSN and *PSRC to the single source, and this function
906 can_combine_p (insn, i3, pred, succ, pdest, psrc)
909 rtx pred ATTRIBUTE_UNUSED;
914 rtx set = 0, src, dest;
919 int all_adjacent = (succ ? (next_active_insn (insn) == succ
920 && next_active_insn (succ) == i3)
921 : next_active_insn (insn) == i3);
923 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
924 or a PARALLEL consisting of such a SET and CLOBBERs.
926 If INSN has CLOBBER parallel parts, ignore them for our processing.
927 By definition, these happen during the execution of the insn. When it
928 is merged with another insn, all bets are off. If they are, in fact,
929 needed and aren't also supplied in I3, they may be added by
930 recog_for_combine. Otherwise, it won't match.
932 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
935 Get the source and destination of INSN. If more than one, can't
938 if (GET_CODE (PATTERN (insn)) == SET)
939 set = PATTERN (insn);
940 else if (GET_CODE (PATTERN (insn)) == PARALLEL
941 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
943 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
945 rtx elt = XVECEXP (PATTERN (insn), 0, i);
947 switch (GET_CODE (elt))
949 /* This is important to combine floating point insns
952 /* Combining an isolated USE doesn't make sense.
953 We depend here on combinable_i3pat to reject them. */
954 /* The code below this loop only verifies that the inputs of
955 the SET in INSN do not change. We call reg_set_between_p
956 to verify that the REG in the USE does not change between
958 If the USE in INSN was for a pseudo register, the matching
959 insn pattern will likely match any register; combining this
960 with any other USE would only be safe if we knew that the
961 used registers have identical values, or if there was
962 something to tell them apart, e.g. different modes. For
963 now, we forgo such complicated tests and simply disallow
964 combining of USES of pseudo registers with any other USE. */
965 if (GET_CODE (XEXP (elt, 0)) == REG
966 && GET_CODE (PATTERN (i3)) == PARALLEL)
968 rtx i3pat = PATTERN (i3);
969 int i = XVECLEN (i3pat, 0) - 1;
970 unsigned int regno = REGNO (XEXP (elt, 0));
974 rtx i3elt = XVECEXP (i3pat, 0, i);
976 if (GET_CODE (i3elt) == USE
977 && GET_CODE (XEXP (i3elt, 0)) == REG
978 && (REGNO (XEXP (i3elt, 0)) == regno
979 ? reg_set_between_p (XEXP (elt, 0),
980 PREV_INSN (insn), i3)
981 : regno >= FIRST_PSEUDO_REGISTER))
988 /* We can ignore CLOBBERs. */
993 /* Ignore SETs whose result isn't used but not those that
994 have side-effects. */
995 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
996 && ! side_effects_p (elt))
999 /* If we have already found a SET, this is a second one and
1000 so we cannot combine with this insn. */
1008 /* Anything else means we can't combine. */
1014 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1015 so don't do anything with it. */
1016 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1025 set = expand_field_assignment (set);
1026 src = SET_SRC (set), dest = SET_DEST (set);
1028 /* Don't eliminate a store in the stack pointer. */
1029 if (dest == stack_pointer_rtx
1030 /* If we couldn't eliminate a field assignment, we can't combine. */
1031 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1032 /* Don't combine with an insn that sets a register to itself if it has
1033 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1034 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1035 /* Can't merge an ASM_OPERANDS. */
1036 || GET_CODE (src) == ASM_OPERANDS
1037 /* Can't merge a function call. */
1038 || GET_CODE (src) == CALL
1039 /* Don't eliminate a function call argument. */
1040 || (GET_CODE (i3) == CALL_INSN
1041 && (find_reg_fusage (i3, USE, dest)
1042 || (GET_CODE (dest) == REG
1043 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1044 && global_regs[REGNO (dest)])))
1045 /* Don't substitute into an incremented register. */
1046 || FIND_REG_INC_NOTE (i3, dest)
1047 || (succ && FIND_REG_INC_NOTE (succ, dest))
1049 /* Don't combine the end of a libcall into anything. */
1050 /* ??? This gives worse code, and appears to be unnecessary, since no
1051 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1052 use REG_RETVAL notes for noconflict blocks, but other code here
1053 makes sure that those insns don't disappear. */
1054 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1056 /* Make sure that DEST is not used after SUCC but before I3. */
1057 || (succ && ! all_adjacent
1058 && reg_used_between_p (dest, succ, i3))
1059 /* Make sure that the value that is to be substituted for the register
1060 does not use any registers whose values alter in between. However,
1061 If the insns are adjacent, a use can't cross a set even though we
1062 think it might (this can happen for a sequence of insns each setting
1063 the same destination; reg_last_set of that register might point to
1064 a NOTE). If INSN has a REG_EQUIV note, the register is always
1065 equivalent to the memory so the substitution is valid even if there
1066 are intervening stores. Also, don't move a volatile asm or
1067 UNSPEC_VOLATILE across any other insns. */
1069 && (((GET_CODE (src) != MEM
1070 || ! find_reg_note (insn, REG_EQUIV, src))
1071 && use_crosses_set_p (src, INSN_CUID (insn)))
1072 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1073 || GET_CODE (src) == UNSPEC_VOLATILE))
1074 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1075 better register allocation by not doing the combine. */
1076 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1077 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1078 /* Don't combine across a CALL_INSN, because that would possibly
1079 change whether the life span of some REGs crosses calls or not,
1080 and it is a pain to update that information.
1081 Exception: if source is a constant, moving it later can't hurt.
1082 Accept that special case, because it helps -fforce-addr a lot. */
1083 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1086 /* DEST must either be a REG or CC0. */
1087 if (GET_CODE (dest) == REG)
1089 /* If register alignment is being enforced for multi-word items in all
1090 cases except for parameters, it is possible to have a register copy
1091 insn referencing a hard register that is not allowed to contain the
1092 mode being copied and which would not be valid as an operand of most
1093 insns. Eliminate this problem by not combining with such an insn.
1095 Also, on some machines we don't want to extend the life of a hard
1098 if (GET_CODE (src) == REG
1099 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1100 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1101 /* Don't extend the life of a hard register unless it is
1102 user variable (if we have few registers) or it can't
1103 fit into the desired register (meaning something special
1105 Also avoid substituting a return register into I3, because
1106 reload can't handle a conflict with constraints of other
1108 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1109 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1112 else if (GET_CODE (dest) != CC0)
1115 /* Don't substitute for a register intended as a clobberable operand.
1116 Similarly, don't substitute an expression containing a register that
1117 will be clobbered in I3. */
1118 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1119 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1120 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1121 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1123 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1126 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1127 or not), reject, unless nothing volatile comes between it and I3 */
1129 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1131 /* Make sure succ doesn't contain a volatile reference. */
1132 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1135 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1136 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1140 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1141 to be an explicit register variable, and was chosen for a reason. */
1143 if (GET_CODE (src) == ASM_OPERANDS
1144 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1147 /* If there are any volatile insns between INSN and I3, reject, because
1148 they might affect machine state. */
1150 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1151 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1154 /* If INSN or I2 contains an autoincrement or autodecrement,
1155 make sure that register is not used between there and I3,
1156 and not already used in I3 either.
1157 Also insist that I3 not be a jump; if it were one
1158 and the incremented register were spilled, we would lose. */
1161 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1162 if (REG_NOTE_KIND (link) == REG_INC
1163 && (GET_CODE (i3) == JUMP_INSN
1164 || reg_used_between_p (XEXP (link, 0), insn, i3)
1165 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1170 /* Don't combine an insn that follows a CC0-setting insn.
1171 An insn that uses CC0 must not be separated from the one that sets it.
1172 We do, however, allow I2 to follow a CC0-setting insn if that insn
1173 is passed as I1; in that case it will be deleted also.
1174 We also allow combining in this case if all the insns are adjacent
1175 because that would leave the two CC0 insns adjacent as well.
1176 It would be more logical to test whether CC0 occurs inside I1 or I2,
1177 but that would be much slower, and this ought to be equivalent. */
1179 p = prev_nonnote_insn (insn);
1180 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1185 /* If we get here, we have passed all the tests and the combination is
1194 /* Check if PAT is an insn - or a part of it - used to set up an
1195 argument for a function in a hard register. */
1198 sets_function_arg_p (pat)
1204 switch (GET_CODE (pat))
1207 return sets_function_arg_p (PATTERN (pat));
1210 for (i = XVECLEN (pat, 0); --i >= 0;)
1211 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1217 inner_dest = SET_DEST (pat);
1218 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1219 || GET_CODE (inner_dest) == SUBREG
1220 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1221 inner_dest = XEXP (inner_dest, 0);
1223 return (GET_CODE (inner_dest) == REG
1224 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1225 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1234 /* LOC is the location within I3 that contains its pattern or the component
1235 of a PARALLEL of the pattern. We validate that it is valid for combining.
1237 One problem is if I3 modifies its output, as opposed to replacing it
1238 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1239 so would produce an insn that is not equivalent to the original insns.
1243 (set (reg:DI 101) (reg:DI 100))
1244 (set (subreg:SI (reg:DI 101) 0) <foo>)
1246 This is NOT equivalent to:
1248 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1249 (set (reg:DI 101) (reg:DI 100))])
1251 Not only does this modify 100 (in which case it might still be valid
1252 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1254 We can also run into a problem if I2 sets a register that I1
1255 uses and I1 gets directly substituted into I3 (not via I2). In that
1256 case, we would be getting the wrong value of I2DEST into I3, so we
1257 must reject the combination. This case occurs when I2 and I1 both
1258 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1259 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1260 of a SET must prevent combination from occurring.
1262 Before doing the above check, we first try to expand a field assignment
1263 into a set of logical operations.
1265 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1266 we place a register that is both set and used within I3. If more than one
1267 such register is detected, we fail.
1269 Return 1 if the combination is valid, zero otherwise. */
1272 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1278 rtx *pi3dest_killed;
1282 if (GET_CODE (x) == SET)
1284 rtx set = expand_field_assignment (x);
1285 rtx dest = SET_DEST (set);
1286 rtx src = SET_SRC (set);
1287 rtx inner_dest = dest;
1290 rtx inner_src = src;
1295 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1296 || GET_CODE (inner_dest) == SUBREG
1297 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1298 inner_dest = XEXP (inner_dest, 0);
1300 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1303 while (GET_CODE (inner_src) == STRICT_LOW_PART
1304 || GET_CODE (inner_src) == SUBREG
1305 || GET_CODE (inner_src) == ZERO_EXTRACT)
1306 inner_src = XEXP (inner_src, 0);
1308 /* If it is better that two different modes keep two different pseudos,
1309 avoid combining them. This avoids producing the following pattern
1311 (set (subreg:SI (reg/v:QI 21) 0)
1312 (lshiftrt:SI (reg/v:SI 20)
1314 If that were made, reload could not handle the pair of
1315 reg 20/21, since it would try to get any GENERAL_REGS
1316 but some of them don't handle QImode. */
1318 if (rtx_equal_p (inner_src, i2dest)
1319 && GET_CODE (inner_dest) == REG
1320 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1324 /* Check for the case where I3 modifies its output, as
1326 if ((inner_dest != dest
1327 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1328 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1330 /* This is the same test done in can_combine_p except we can't test
1331 all_adjacent; we don't have to, since this instruction will stay
1332 in place, thus we are not considering increasing the lifetime of
1335 Also, if this insn sets a function argument, combining it with
1336 something that might need a spill could clobber a previous
1337 function argument; the all_adjacent test in can_combine_p also
1338 checks this; here, we do a more specific test for this case. */
1340 || (GET_CODE (inner_dest) == REG
1341 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1342 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1343 GET_MODE (inner_dest))))
1344 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1347 /* If DEST is used in I3, it is being killed in this insn,
1348 so record that for later.
1349 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1350 STACK_POINTER_REGNUM, since these are always considered to be
1351 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1352 if (pi3dest_killed && GET_CODE (dest) == REG
1353 && reg_referenced_p (dest, PATTERN (i3))
1354 && REGNO (dest) != FRAME_POINTER_REGNUM
1355 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1356 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1358 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1359 && (REGNO (dest) != ARG_POINTER_REGNUM
1360 || ! fixed_regs [REGNO (dest)])
1362 && REGNO (dest) != STACK_POINTER_REGNUM)
1364 if (*pi3dest_killed)
1367 *pi3dest_killed = dest;
1371 else if (GET_CODE (x) == PARALLEL)
1375 for (i = 0; i < XVECLEN (x, 0); i++)
1376 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1377 i1_not_in_src, pi3dest_killed))
1384 /* Return 1 if X is an arithmetic expression that contains a multiplication
1385 and division. We don't count multiplications by powers of two here. */
1391 switch (GET_CODE (x))
1393 case MOD: case DIV: case UMOD: case UDIV:
1397 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1398 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1400 switch (GET_RTX_CLASS (GET_CODE (x)))
1402 case 'c': case '<': case '2':
1403 return contains_muldiv (XEXP (x, 0))
1404 || contains_muldiv (XEXP (x, 1));
1407 return contains_muldiv (XEXP (x, 0));
1415 /* Determine whether INSN can be used in a combination. Return nonzero if
1416 not. This is used in try_combine to detect early some cases where we
1417 can't perform combinations. */
1420 cant_combine_insn_p (insn)
1426 /* If this isn't really an insn, we can't do anything.
1427 This can occur when flow deletes an insn that it has merged into an
1428 auto-increment address. */
1429 if (! INSN_P (insn))
1432 /* Never combine loads and stores involving hard regs. The register
1433 allocator can usually handle such reg-reg moves by tying. If we allow
1434 the combiner to make substitutions of hard regs, we risk aborting in
1435 reload on machines that have SMALL_REGISTER_CLASSES.
1436 As an exception, we allow combinations involving fixed regs; these are
1437 not available to the register allocator so there's no risk involved. */
1439 set = single_set (insn);
1442 src = SET_SRC (set);
1443 dest = SET_DEST (set);
1444 if (GET_CODE (src) == SUBREG)
1445 src = SUBREG_REG (src);
1446 if (GET_CODE (dest) == SUBREG)
1447 dest = SUBREG_REG (dest);
1448 if (REG_P (src) && REG_P (dest)
1449 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1450 && ! fixed_regs[REGNO (src)])
1451 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1452 && ! fixed_regs[REGNO (dest)])))
1458 /* Try to combine the insns I1 and I2 into I3.
1459 Here I1 and I2 appear earlier than I3.
1460 I1 can be zero; then we combine just I2 into I3.
1462 If we are combining three insns and the resulting insn is not recognized,
1463 try splitting it into two insns. If that happens, I2 and I3 are retained
1464 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1467 Return 0 if the combination does not work. Then nothing is changed.
1468 If we did the combination, return the insn at which combine should
1471 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1472 new direct jump instruction. */
1475 try_combine (i3, i2, i1, new_direct_jump_p)
1477 int *new_direct_jump_p;
1479 /* New patterns for I3 and I2, respectively. */
1480 rtx newpat, newi2pat = 0;
1481 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1482 int added_sets_1, added_sets_2;
1483 /* Total number of SETs to put into I3. */
1485 /* Nonzero is I2's body now appears in I3. */
1487 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1488 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1489 /* Contains I3 if the destination of I3 is used in its source, which means
1490 that the old life of I3 is being killed. If that usage is placed into
1491 I2 and not in I3, a REG_DEAD note must be made. */
1492 rtx i3dest_killed = 0;
1493 /* SET_DEST and SET_SRC of I2 and I1. */
1494 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1495 /* PATTERN (I2), or a copy of it in certain cases. */
1497 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1498 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1499 int i1_feeds_i3 = 0;
1500 /* Notes that must be added to REG_NOTES in I3 and I2. */
1501 rtx new_i3_notes, new_i2_notes;
1502 /* Notes that we substituted I3 into I2 instead of the normal case. */
1503 int i3_subst_into_i2 = 0;
1504 /* Notes that I1, I2 or I3 is a MULT operation. */
1512 /* Exit early if one of the insns involved can't be used for
1514 if (cant_combine_insn_p (i3)
1515 || cant_combine_insn_p (i2)
1516 || (i1 && cant_combine_insn_p (i1))
1517 /* We also can't do anything if I3 has a
1518 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1521 /* ??? This gives worse code, and appears to be unnecessary, since no
1522 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1523 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1529 undobuf.other_insn = 0;
1531 /* Reset the hard register usage information. */
1532 CLEAR_HARD_REG_SET (newpat_used_regs);
1534 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1535 code below, set I1 to be the earlier of the two insns. */
1536 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1537 temp = i1, i1 = i2, i2 = temp;
1539 added_links_insn = 0;
1541 /* First check for one important special-case that the code below will
1542 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1543 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1544 we may be able to replace that destination with the destination of I3.
1545 This occurs in the common code where we compute both a quotient and
1546 remainder into a structure, in which case we want to do the computation
1547 directly into the structure to avoid register-register copies.
1549 Note that this case handles both multiple sets in I2 and also
1550 cases where I2 has a number of CLOBBER or PARALLELs.
1552 We make very conservative checks below and only try to handle the
1553 most common cases of this. For example, we only handle the case
1554 where I2 and I3 are adjacent to avoid making difficult register
1557 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1558 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1559 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1560 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1561 && GET_CODE (PATTERN (i2)) == PARALLEL
1562 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1563 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1564 below would need to check what is inside (and reg_overlap_mentioned_p
1565 doesn't support those codes anyway). Don't allow those destinations;
1566 the resulting insn isn't likely to be recognized anyway. */
1567 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1568 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1569 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1570 SET_DEST (PATTERN (i3)))
1571 && next_real_insn (i2) == i3)
1573 rtx p2 = PATTERN (i2);
1575 /* Make sure that the destination of I3,
1576 which we are going to substitute into one output of I2,
1577 is not used within another output of I2. We must avoid making this:
1578 (parallel [(set (mem (reg 69)) ...)
1579 (set (reg 69) ...)])
1580 which is not well-defined as to order of actions.
1581 (Besides, reload can't handle output reloads for this.)
1583 The problem can also happen if the dest of I3 is a memory ref,
1584 if another dest in I2 is an indirect memory ref. */
1585 for (i = 0; i < XVECLEN (p2, 0); i++)
1586 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1587 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1588 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1589 SET_DEST (XVECEXP (p2, 0, i))))
1592 if (i == XVECLEN (p2, 0))
1593 for (i = 0; i < XVECLEN (p2, 0); i++)
1594 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1595 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1596 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1601 subst_low_cuid = INSN_CUID (i2);
1603 added_sets_2 = added_sets_1 = 0;
1604 i2dest = SET_SRC (PATTERN (i3));
1606 /* Replace the dest in I2 with our dest and make the resulting
1607 insn the new pattern for I3. Then skip to where we
1608 validate the pattern. Everything was set up above. */
1609 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1610 SET_DEST (PATTERN (i3)));
1613 i3_subst_into_i2 = 1;
1614 goto validate_replacement;
1618 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1619 one of those words to another constant, merge them by making a new
1622 && (temp = single_set (i2)) != 0
1623 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1624 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1625 && GET_CODE (SET_DEST (temp)) == REG
1626 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1627 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1628 && GET_CODE (PATTERN (i3)) == SET
1629 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1630 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1633 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1635 HOST_WIDE_INT lo, hi;
1637 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1638 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1641 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1642 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1645 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1647 /* We don't handle the case of the target word being wider
1648 than a host wide int. */
1649 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1652 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1653 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1654 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1656 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1657 hi = INTVAL (SET_SRC (PATTERN (i3)));
1658 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1660 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1661 >> (HOST_BITS_PER_WIDE_INT - 1));
1663 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1664 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1665 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1666 (INTVAL (SET_SRC (PATTERN (i3)))));
1668 hi = lo < 0 ? -1 : 0;
1671 /* We don't handle the case of the higher word not fitting
1672 entirely in either hi or lo. */
1677 subst_low_cuid = INSN_CUID (i2);
1678 added_sets_2 = added_sets_1 = 0;
1679 i2dest = SET_DEST (temp);
1681 SUBST (SET_SRC (temp),
1682 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1684 newpat = PATTERN (i2);
1685 goto validate_replacement;
1689 /* If we have no I1 and I2 looks like:
1690 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1692 make up a dummy I1 that is
1695 (set (reg:CC X) (compare:CC Y (const_int 0)))
1697 (We can ignore any trailing CLOBBERs.)
1699 This undoes a previous combination and allows us to match a branch-and-
1702 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1703 && XVECLEN (PATTERN (i2), 0) >= 2
1704 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1705 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1707 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1708 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1709 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1710 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1711 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1712 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1714 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1715 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1720 /* We make I1 with the same INSN_UID as I2. This gives it
1721 the same INSN_CUID for value tracking. Our fake I1 will
1722 never appear in the insn stream so giving it the same INSN_UID
1723 as I2 will not cause a problem. */
1725 subst_prev_insn = i1
1726 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1727 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1730 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1731 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1732 SET_DEST (PATTERN (i1)));
1737 /* Verify that I2 and I1 are valid for combining. */
1738 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1739 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1745 /* Record whether I2DEST is used in I2SRC and similarly for the other
1746 cases. Knowing this will help in register status updating below. */
1747 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1748 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1749 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1751 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1753 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1755 /* Ensure that I3's pattern can be the destination of combines. */
1756 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1757 i1 && i2dest_in_i1src && i1_feeds_i3,
1764 /* See if any of the insns is a MULT operation. Unless one is, we will
1765 reject a combination that is, since it must be slower. Be conservative
1767 if (GET_CODE (i2src) == MULT
1768 || (i1 != 0 && GET_CODE (i1src) == MULT)
1769 || (GET_CODE (PATTERN (i3)) == SET
1770 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1773 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1774 We used to do this EXCEPT in one case: I3 has a post-inc in an
1775 output operand. However, that exception can give rise to insns like
1777 which is a famous insn on the PDP-11 where the value of r3 used as the
1778 source was model-dependent. Avoid this sort of thing. */
1781 if (!(GET_CODE (PATTERN (i3)) == SET
1782 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1783 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1784 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1785 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1786 /* It's not the exception. */
1789 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1790 if (REG_NOTE_KIND (link) == REG_INC
1791 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1793 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1800 /* See if the SETs in I1 or I2 need to be kept around in the merged
1801 instruction: whenever the value set there is still needed past I3.
1802 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1804 For the SET in I1, we have two cases: If I1 and I2 independently
1805 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1806 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1807 in I1 needs to be kept around unless I1DEST dies or is set in either
1808 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1809 I1DEST. If so, we know I1 feeds into I2. */
1811 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1814 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1815 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1817 /* If the set in I2 needs to be kept around, we must make a copy of
1818 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1819 PATTERN (I2), we are only substituting for the original I1DEST, not into
1820 an already-substituted copy. This also prevents making self-referential
1821 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1824 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1825 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1829 i2pat = copy_rtx (i2pat);
1833 /* Substitute in the latest insn for the regs set by the earlier ones. */
1835 maxreg = max_reg_num ();
1839 /* It is possible that the source of I2 or I1 may be performing an
1840 unneeded operation, such as a ZERO_EXTEND of something that is known
1841 to have the high part zero. Handle that case by letting subst look at
1842 the innermost one of them.
1844 Another way to do this would be to have a function that tries to
1845 simplify a single insn instead of merging two or more insns. We don't
1846 do this because of the potential of infinite loops and because
1847 of the potential extra memory required. However, doing it the way
1848 we are is a bit of a kludge and doesn't catch all cases.
1850 But only do this if -fexpensive-optimizations since it slows things down
1851 and doesn't usually win. */
1853 if (flag_expensive_optimizations)
1855 /* Pass pc_rtx so no substitutions are done, just simplifications.
1856 The cases that we are interested in here do not involve the few
1857 cases were is_replaced is checked. */
1860 subst_low_cuid = INSN_CUID (i1);
1861 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1865 subst_low_cuid = INSN_CUID (i2);
1866 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1871 /* Many machines that don't use CC0 have insns that can both perform an
1872 arithmetic operation and set the condition code. These operations will
1873 be represented as a PARALLEL with the first element of the vector
1874 being a COMPARE of an arithmetic operation with the constant zero.
1875 The second element of the vector will set some pseudo to the result
1876 of the same arithmetic operation. If we simplify the COMPARE, we won't
1877 match such a pattern and so will generate an extra insn. Here we test
1878 for this case, where both the comparison and the operation result are
1879 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1880 I2SRC. Later we will make the PARALLEL that contains I2. */
1882 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1883 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1884 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1885 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1887 #ifdef EXTRA_CC_MODES
1889 enum machine_mode compare_mode;
1892 newpat = PATTERN (i3);
1893 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1897 #ifdef EXTRA_CC_MODES
1898 /* See if a COMPARE with the operand we substituted in should be done
1899 with the mode that is currently being used. If not, do the same
1900 processing we do in `subst' for a SET; namely, if the destination
1901 is used only once, try to replace it with a register of the proper
1902 mode and also replace the COMPARE. */
1903 if (undobuf.other_insn == 0
1904 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1905 &undobuf.other_insn))
1906 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1908 != GET_MODE (SET_DEST (newpat))))
1910 unsigned int regno = REGNO (SET_DEST (newpat));
1911 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1913 if (regno < FIRST_PSEUDO_REGISTER
1914 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1915 && ! REG_USERVAR_P (SET_DEST (newpat))))
1917 if (regno >= FIRST_PSEUDO_REGISTER)
1918 SUBST (regno_reg_rtx[regno], new_dest);
1920 SUBST (SET_DEST (newpat), new_dest);
1921 SUBST (XEXP (*cc_use, 0), new_dest);
1922 SUBST (SET_SRC (newpat),
1923 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1926 undobuf.other_insn = 0;
1933 n_occurrences = 0; /* `subst' counts here */
1935 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1936 need to make a unique copy of I2SRC each time we substitute it
1937 to avoid self-referential rtl. */
1939 subst_low_cuid = INSN_CUID (i2);
1940 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1941 ! i1_feeds_i3 && i1dest_in_i1src);
1943 /* Record whether i2's body now appears within i3's body. */
1944 i2_is_used = n_occurrences;
1947 /* If we already got a failure, don't try to do more. Otherwise,
1948 try to substitute in I1 if we have it. */
1950 if (i1 && GET_CODE (newpat) != CLOBBER)
1952 /* Before we can do this substitution, we must redo the test done
1953 above (see detailed comments there) that ensures that I1DEST
1954 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1956 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1964 subst_low_cuid = INSN_CUID (i1);
1965 newpat = subst (newpat, i1dest, i1src, 0, 0);
1968 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1969 to count all the ways that I2SRC and I1SRC can be used. */
1970 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1971 && i2_is_used + added_sets_2 > 1)
1972 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1973 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1975 /* Fail if we tried to make a new register (we used to abort, but there's
1976 really no reason to). */
1977 || max_reg_num () != maxreg
1978 /* Fail if we couldn't do something and have a CLOBBER. */
1979 || GET_CODE (newpat) == CLOBBER
1980 /* Fail if this new pattern is a MULT and we didn't have one before
1981 at the outer level. */
1982 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1989 /* If the actions of the earlier insns must be kept
1990 in addition to substituting them into the latest one,
1991 we must make a new PARALLEL for the latest insn
1992 to hold additional the SETs. */
1994 if (added_sets_1 || added_sets_2)
1998 if (GET_CODE (newpat) == PARALLEL)
2000 rtvec old = XVEC (newpat, 0);
2001 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2002 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2003 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2004 sizeof (old->elem[0]) * old->num_elem);
2009 total_sets = 1 + added_sets_1 + added_sets_2;
2010 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2011 XVECEXP (newpat, 0, 0) = old;
2015 XVECEXP (newpat, 0, --total_sets)
2016 = (GET_CODE (PATTERN (i1)) == PARALLEL
2017 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2021 /* If there is no I1, use I2's body as is. We used to also not do
2022 the subst call below if I2 was substituted into I3,
2023 but that could lose a simplification. */
2025 XVECEXP (newpat, 0, --total_sets) = i2pat;
2027 /* See comment where i2pat is assigned. */
2028 XVECEXP (newpat, 0, --total_sets)
2029 = subst (i2pat, i1dest, i1src, 0, 0);
2033 /* We come here when we are replacing a destination in I2 with the
2034 destination of I3. */
2035 validate_replacement:
2037 /* Note which hard regs this insn has as inputs. */
2038 mark_used_regs_combine (newpat);
2040 /* Is the result of combination a valid instruction? */
2041 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2043 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2044 the second SET's destination is a register that is unused. In that case,
2045 we just need the first SET. This can occur when simplifying a divmod
2046 insn. We *must* test for this case here because the code below that
2047 splits two independent SETs doesn't handle this case correctly when it
2048 updates the register status. Also check the case where the first
2049 SET's destination is unused. That would not cause incorrect code, but
2050 does cause an unneeded insn to remain. */
2052 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2053 && XVECLEN (newpat, 0) == 2
2054 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2055 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2056 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2057 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2058 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2059 && asm_noperands (newpat) < 0)
2061 newpat = XVECEXP (newpat, 0, 0);
2062 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2065 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2066 && XVECLEN (newpat, 0) == 2
2067 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2068 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2069 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2070 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2071 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2072 && asm_noperands (newpat) < 0)
2074 newpat = XVECEXP (newpat, 0, 1);
2075 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2078 /* If we were combining three insns and the result is a simple SET
2079 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2080 insns. There are two ways to do this. It can be split using a
2081 machine-specific method (like when you have an addition of a large
2082 constant) or by combine in the function find_split_point. */
2084 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2085 && asm_noperands (newpat) < 0)
2087 rtx m_split, *split;
2088 rtx ni2dest = i2dest;
2090 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2091 use I2DEST as a scratch register will help. In the latter case,
2092 convert I2DEST to the mode of the source of NEWPAT if we can. */
2094 m_split = split_insns (newpat, i3);
2096 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2097 inputs of NEWPAT. */
2099 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2100 possible to try that as a scratch reg. This would require adding
2101 more code to make it work though. */
2103 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2105 /* If I2DEST is a hard register or the only use of a pseudo,
2106 we can change its mode. */
2107 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2108 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2109 && GET_CODE (i2dest) == REG
2110 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2111 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2112 && ! REG_USERVAR_P (i2dest))))
2113 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2116 m_split = split_insns (gen_rtx_PARALLEL
2118 gen_rtvec (2, newpat,
2119 gen_rtx_CLOBBER (VOIDmode,
2122 /* If the split with the mode-changed register didn't work, try
2123 the original register. */
2124 if (! m_split && ni2dest != i2dest)
2127 m_split = split_insns (gen_rtx_PARALLEL
2129 gen_rtvec (2, newpat,
2130 gen_rtx_CLOBBER (VOIDmode,
2136 /* If we've split a jump pattern, we'll wind up with a sequence even
2137 with one instruction. We can handle that below, so extract it. */
2138 if (m_split && GET_CODE (m_split) == SEQUENCE
2139 && XVECLEN (m_split, 0) == 1)
2140 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2142 if (m_split && GET_CODE (m_split) != SEQUENCE)
2144 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2145 if (insn_code_number >= 0)
2148 else if (m_split && GET_CODE (m_split) == SEQUENCE
2149 && XVECLEN (m_split, 0) == 2
2150 && (next_real_insn (i2) == i3
2151 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2155 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2156 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2158 i3set = single_set (XVECEXP (m_split, 0, 1));
2159 i2set = single_set (XVECEXP (m_split, 0, 0));
2161 /* In case we changed the mode of I2DEST, replace it in the
2162 pseudo-register table here. We can't do it above in case this
2163 code doesn't get executed and we do a split the other way. */
2165 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2166 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2168 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2170 /* If I2 or I3 has multiple SETs, we won't know how to track
2171 register status, so don't use these insns. If I2's destination
2172 is used between I2 and I3, we also can't use these insns. */
2174 if (i2_code_number >= 0 && i2set && i3set
2175 && (next_real_insn (i2) == i3
2176 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2177 insn_code_number = recog_for_combine (&newi3pat, i3,
2179 if (insn_code_number >= 0)
2182 /* It is possible that both insns now set the destination of I3.
2183 If so, we must show an extra use of it. */
2185 if (insn_code_number >= 0)
2187 rtx new_i3_dest = SET_DEST (i3set);
2188 rtx new_i2_dest = SET_DEST (i2set);
2190 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2191 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2192 || GET_CODE (new_i3_dest) == SUBREG)
2193 new_i3_dest = XEXP (new_i3_dest, 0);
2195 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2196 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2197 || GET_CODE (new_i2_dest) == SUBREG)
2198 new_i2_dest = XEXP (new_i2_dest, 0);
2200 if (GET_CODE (new_i3_dest) == REG
2201 && GET_CODE (new_i2_dest) == REG
2202 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2203 REG_N_SETS (REGNO (new_i2_dest))++;
2207 /* If we can split it and use I2DEST, go ahead and see if that
2208 helps things be recognized. Verify that none of the registers
2209 are set between I2 and I3. */
2210 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2212 && GET_CODE (i2dest) == REG
2214 /* We need I2DEST in the proper mode. If it is a hard register
2215 or the only use of a pseudo, we can change its mode. */
2216 && (GET_MODE (*split) == GET_MODE (i2dest)
2217 || GET_MODE (*split) == VOIDmode
2218 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2219 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2220 && ! REG_USERVAR_P (i2dest)))
2221 && (next_real_insn (i2) == i3
2222 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2223 /* We can't overwrite I2DEST if its value is still used by
2225 && ! reg_referenced_p (i2dest, newpat))
2227 rtx newdest = i2dest;
2228 enum rtx_code split_code = GET_CODE (*split);
2229 enum machine_mode split_mode = GET_MODE (*split);
2231 /* Get NEWDEST as a register in the proper mode. We have already
2232 validated that we can do this. */
2233 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2235 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2237 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2238 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2241 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2242 an ASHIFT. This can occur if it was inside a PLUS and hence
2243 appeared to be a memory address. This is a kludge. */
2244 if (split_code == MULT
2245 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2246 && INTVAL (XEXP (*split, 1)) > 0
2247 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2249 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2250 XEXP (*split, 0), GEN_INT (i)));
2251 /* Update split_code because we may not have a multiply
2253 split_code = GET_CODE (*split);
2256 #ifdef INSN_SCHEDULING
2257 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2258 be written as a ZERO_EXTEND. */
2259 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2260 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2261 SUBREG_REG (*split)));
2264 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2265 SUBST (*split, newdest);
2266 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2268 /* If the split point was a MULT and we didn't have one before,
2269 don't use one now. */
2270 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2271 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2275 /* Check for a case where we loaded from memory in a narrow mode and
2276 then sign extended it, but we need both registers. In that case,
2277 we have a PARALLEL with both loads from the same memory location.
2278 We can split this into a load from memory followed by a register-register
2279 copy. This saves at least one insn, more if register allocation can
2282 We cannot do this if the destination of the second assignment is
2283 a register that we have already assumed is zero-extended. Similarly
2284 for a SUBREG of such a register. */
2286 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2287 && GET_CODE (newpat) == PARALLEL
2288 && XVECLEN (newpat, 0) == 2
2289 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2290 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2291 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2292 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2293 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2294 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2296 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2297 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2298 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2299 (GET_CODE (temp) == REG
2300 && reg_nonzero_bits[REGNO (temp)] != 0
2301 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2302 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2303 && (reg_nonzero_bits[REGNO (temp)]
2304 != GET_MODE_MASK (word_mode))))
2305 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2306 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2307 (GET_CODE (temp) == REG
2308 && reg_nonzero_bits[REGNO (temp)] != 0
2309 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2310 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2311 && (reg_nonzero_bits[REGNO (temp)]
2312 != GET_MODE_MASK (word_mode)))))
2313 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2314 SET_SRC (XVECEXP (newpat, 0, 1)))
2315 && ! find_reg_note (i3, REG_UNUSED,
2316 SET_DEST (XVECEXP (newpat, 0, 0))))
2320 newi2pat = XVECEXP (newpat, 0, 0);
2321 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2322 newpat = XVECEXP (newpat, 0, 1);
2323 SUBST (SET_SRC (newpat),
2324 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2325 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2327 if (i2_code_number >= 0)
2328 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2330 if (insn_code_number >= 0)
2335 /* If we will be able to accept this, we have made a change to the
2336 destination of I3. This can invalidate a LOG_LINKS pointing
2337 to I3. No other part of combine.c makes such a transformation.
2339 The new I3 will have a destination that was previously the
2340 destination of I1 or I2 and which was used in i2 or I3. Call
2341 distribute_links to make a LOG_LINK from the next use of
2342 that destination. */
2344 PATTERN (i3) = newpat;
2345 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2347 /* I3 now uses what used to be its destination and which is
2348 now I2's destination. That means we need a LOG_LINK from
2349 I3 to I2. But we used to have one, so we still will.
2351 However, some later insn might be using I2's dest and have
2352 a LOG_LINK pointing at I3. We must remove this link.
2353 The simplest way to remove the link is to point it at I1,
2354 which we know will be a NOTE. */
2356 for (insn = NEXT_INSN (i3);
2357 insn && (this_basic_block == n_basic_blocks - 1
2358 || insn != BLOCK_HEAD (this_basic_block + 1));
2359 insn = NEXT_INSN (insn))
2361 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2363 for (link = LOG_LINKS (insn); link;
2364 link = XEXP (link, 1))
2365 if (XEXP (link, 0) == i3)
2366 XEXP (link, 0) = i1;
2374 /* Similarly, check for a case where we have a PARALLEL of two independent
2375 SETs but we started with three insns. In this case, we can do the sets
2376 as two separate insns. This case occurs when some SET allows two
2377 other insns to combine, but the destination of that SET is still live. */
2379 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2380 && GET_CODE (newpat) == PARALLEL
2381 && XVECLEN (newpat, 0) == 2
2382 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2384 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2385 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2386 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2387 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2388 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2390 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2391 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2392 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2393 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2394 XVECEXP (newpat, 0, 0))
2395 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2396 XVECEXP (newpat, 0, 1))
2397 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2398 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2400 /* Normally, it doesn't matter which of the two is done first,
2401 but it does if one references cc0. In that case, it has to
2404 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2406 newi2pat = XVECEXP (newpat, 0, 0);
2407 newpat = XVECEXP (newpat, 0, 1);
2412 newi2pat = XVECEXP (newpat, 0, 1);
2413 newpat = XVECEXP (newpat, 0, 0);
2416 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2418 if (i2_code_number >= 0)
2419 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2422 /* If it still isn't recognized, fail and change things back the way they
2424 if ((insn_code_number < 0
2425 /* Is the result a reasonable ASM_OPERANDS? */
2426 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2432 /* If we had to change another insn, make sure it is valid also. */
2433 if (undobuf.other_insn)
2435 rtx other_pat = PATTERN (undobuf.other_insn);
2436 rtx new_other_notes;
2439 CLEAR_HARD_REG_SET (newpat_used_regs);
2441 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2444 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2450 PATTERN (undobuf.other_insn) = other_pat;
2452 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2453 are still valid. Then add any non-duplicate notes added by
2454 recog_for_combine. */
2455 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2457 next = XEXP (note, 1);
2459 if (REG_NOTE_KIND (note) == REG_UNUSED
2460 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2462 if (GET_CODE (XEXP (note, 0)) == REG)
2463 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2465 remove_note (undobuf.other_insn, note);
2469 for (note = new_other_notes; note; note = XEXP (note, 1))
2470 if (GET_CODE (XEXP (note, 0)) == REG)
2471 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2473 distribute_notes (new_other_notes, undobuf.other_insn,
2474 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2477 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2478 they are adjacent to each other or not. */
2480 rtx p = prev_nonnote_insn (i3);
2481 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2482 && sets_cc0_p (newi2pat))
2490 /* We now know that we can do this combination. Merge the insns and
2491 update the status of registers and LOG_LINKS. */
2494 rtx i3notes, i2notes, i1notes = 0;
2495 rtx i3links, i2links, i1links = 0;
2498 /* Compute which registers we expect to eliminate. newi2pat may be setting
2499 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2500 same as i3dest, in which case newi2pat may be setting i1dest. */
2501 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2502 || i2dest_in_i2src || i2dest_in_i1src
2504 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2505 || (newi2pat && reg_set_p (i1dest, newi2pat))
2508 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2510 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2511 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2513 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2515 /* Ensure that we do not have something that should not be shared but
2516 occurs multiple times in the new insns. Check this by first
2517 resetting all the `used' flags and then copying anything is shared. */
2519 reset_used_flags (i3notes);
2520 reset_used_flags (i2notes);
2521 reset_used_flags (i1notes);
2522 reset_used_flags (newpat);
2523 reset_used_flags (newi2pat);
2524 if (undobuf.other_insn)
2525 reset_used_flags (PATTERN (undobuf.other_insn));
2527 i3notes = copy_rtx_if_shared (i3notes);
2528 i2notes = copy_rtx_if_shared (i2notes);
2529 i1notes = copy_rtx_if_shared (i1notes);
2530 newpat = copy_rtx_if_shared (newpat);
2531 newi2pat = copy_rtx_if_shared (newi2pat);
2532 if (undobuf.other_insn)
2533 reset_used_flags (PATTERN (undobuf.other_insn));
2535 INSN_CODE (i3) = insn_code_number;
2536 PATTERN (i3) = newpat;
2537 if (undobuf.other_insn)
2538 INSN_CODE (undobuf.other_insn) = other_code_number;
2540 /* We had one special case above where I2 had more than one set and
2541 we replaced a destination of one of those sets with the destination
2542 of I3. In that case, we have to update LOG_LINKS of insns later
2543 in this basic block. Note that this (expensive) case is rare.
2545 Also, in this case, we must pretend that all REG_NOTEs for I2
2546 actually came from I3, so that REG_UNUSED notes from I2 will be
2547 properly handled. */
2549 if (i3_subst_into_i2)
2551 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2552 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2553 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2554 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2555 && ! find_reg_note (i2, REG_UNUSED,
2556 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2557 for (temp = NEXT_INSN (i2);
2558 temp && (this_basic_block == n_basic_blocks - 1
2559 || BLOCK_HEAD (this_basic_block) != temp);
2560 temp = NEXT_INSN (temp))
2561 if (temp != i3 && INSN_P (temp))
2562 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2563 if (XEXP (link, 0) == i2)
2564 XEXP (link, 0) = i3;
2569 while (XEXP (link, 1))
2570 link = XEXP (link, 1);
2571 XEXP (link, 1) = i2notes;
2585 INSN_CODE (i2) = i2_code_number;
2586 PATTERN (i2) = newi2pat;
2590 PUT_CODE (i2, NOTE);
2591 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2592 NOTE_SOURCE_FILE (i2) = 0;
2599 PUT_CODE (i1, NOTE);
2600 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2601 NOTE_SOURCE_FILE (i1) = 0;
2604 /* Get death notes for everything that is now used in either I3 or
2605 I2 and used to die in a previous insn. If we built two new
2606 patterns, move from I1 to I2 then I2 to I3 so that we get the
2607 proper movement on registers that I2 modifies. */
2611 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2612 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2615 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2618 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2620 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2623 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2626 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2629 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2632 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2633 know these are REG_UNUSED and want them to go to the desired insn,
2634 so we always pass it as i3. We have not counted the notes in
2635 reg_n_deaths yet, so we need to do so now. */
2637 if (newi2pat && new_i2_notes)
2639 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2640 if (GET_CODE (XEXP (temp, 0)) == REG)
2641 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2643 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2648 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2649 if (GET_CODE (XEXP (temp, 0)) == REG)
2650 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2652 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2655 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2656 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2657 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2658 in that case, it might delete I2. Similarly for I2 and I1.
2659 Show an additional death due to the REG_DEAD note we make here. If
2660 we discard it in distribute_notes, we will decrement it again. */
2664 if (GET_CODE (i3dest_killed) == REG)
2665 REG_N_DEATHS (REGNO (i3dest_killed))++;
2667 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2668 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2670 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2674 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2678 if (i2dest_in_i2src)
2680 if (GET_CODE (i2dest) == REG)
2681 REG_N_DEATHS (REGNO (i2dest))++;
2683 if (newi2pat && reg_set_p (i2dest, newi2pat))
2684 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2685 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2687 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2688 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2689 NULL_RTX, NULL_RTX);
2692 if (i1dest_in_i1src)
2694 if (GET_CODE (i1dest) == REG)
2695 REG_N_DEATHS (REGNO (i1dest))++;
2697 if (newi2pat && reg_set_p (i1dest, newi2pat))
2698 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2699 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2701 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2702 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2703 NULL_RTX, NULL_RTX);
2706 distribute_links (i3links);
2707 distribute_links (i2links);
2708 distribute_links (i1links);
2710 if (GET_CODE (i2dest) == REG)
2713 rtx i2_insn = 0, i2_val = 0, set;
2715 /* The insn that used to set this register doesn't exist, and
2716 this life of the register may not exist either. See if one of
2717 I3's links points to an insn that sets I2DEST. If it does,
2718 that is now the last known value for I2DEST. If we don't update
2719 this and I2 set the register to a value that depended on its old
2720 contents, we will get confused. If this insn is used, thing
2721 will be set correctly in combine_instructions. */
2723 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2724 if ((set = single_set (XEXP (link, 0))) != 0
2725 && rtx_equal_p (i2dest, SET_DEST (set)))
2726 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2728 record_value_for_reg (i2dest, i2_insn, i2_val);
2730 /* If the reg formerly set in I2 died only once and that was in I3,
2731 zero its use count so it won't make `reload' do any work. */
2733 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2734 && ! i2dest_in_i2src)
2736 regno = REGNO (i2dest);
2737 REG_N_SETS (regno)--;
2741 if (i1 && GET_CODE (i1dest) == REG)
2744 rtx i1_insn = 0, i1_val = 0, set;
2746 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2747 if ((set = single_set (XEXP (link, 0))) != 0
2748 && rtx_equal_p (i1dest, SET_DEST (set)))
2749 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2751 record_value_for_reg (i1dest, i1_insn, i1_val);
2753 regno = REGNO (i1dest);
2754 if (! added_sets_1 && ! i1dest_in_i1src)
2755 REG_N_SETS (regno)--;
2758 /* Update reg_nonzero_bits et al for any changes that may have been made
2759 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2760 important. Because newi2pat can affect nonzero_bits of newpat */
2762 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2763 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2765 /* Set new_direct_jump_p if a new return or simple jump instruction
2768 If I3 is now an unconditional jump, ensure that it has a
2769 BARRIER following it since it may have initially been a
2770 conditional jump. It may also be the last nonnote insn. */
2772 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2774 *new_direct_jump_p = 1;
2776 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2777 || GET_CODE (temp) != BARRIER)
2778 emit_barrier_after (i3);
2780 /* An NOOP jump does not need barrier, but it does need cleaning up
2782 if (GET_CODE (newpat) == SET
2783 && SET_SRC (newpat) == pc_rtx
2784 && SET_DEST (newpat) == pc_rtx)
2785 *new_direct_jump_p = 1;
2788 combine_successes++;
2791 /* Clear this here, so that subsequent get_last_value calls are not
2793 subst_prev_insn = NULL_RTX;
2795 if (added_links_insn
2796 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2797 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2798 return added_links_insn;
2800 return newi2pat ? i2 : i3;
2803 /* Undo all the modifications recorded in undobuf. */
2808 struct undo *undo, *next;
2810 for (undo = undobuf.undos; undo; undo = next)
2814 *undo->where.i = undo->old_contents.i;
2816 *undo->where.r = undo->old_contents.r;
2818 undo->next = undobuf.frees;
2819 undobuf.frees = undo;
2824 /* Clear this here, so that subsequent get_last_value calls are not
2826 subst_prev_insn = NULL_RTX;
2829 /* We've committed to accepting the changes we made. Move all
2830 of the undos to the free list. */
2835 struct undo *undo, *next;
2837 for (undo = undobuf.undos; undo; undo = next)
2840 undo->next = undobuf.frees;
2841 undobuf.frees = undo;
2847 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2848 where we have an arithmetic expression and return that point. LOC will
2851 try_combine will call this function to see if an insn can be split into
2855 find_split_point (loc, insn)
2860 enum rtx_code code = GET_CODE (x);
2862 unsigned HOST_WIDE_INT len = 0;
2863 HOST_WIDE_INT pos = 0;
2865 rtx inner = NULL_RTX;
2867 /* First special-case some codes. */
2871 #ifdef INSN_SCHEDULING
2872 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2874 if (GET_CODE (SUBREG_REG (x)) == MEM)
2877 return find_split_point (&SUBREG_REG (x), insn);
2881 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2882 using LO_SUM and HIGH. */
2883 if (GET_CODE (XEXP (x, 0)) == CONST
2884 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2887 gen_rtx_LO_SUM (Pmode,
2888 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2890 return &XEXP (XEXP (x, 0), 0);
2894 /* If we have a PLUS whose second operand is a constant and the
2895 address is not valid, perhaps will can split it up using
2896 the machine-specific way to split large constants. We use
2897 the first pseudo-reg (one of the virtual regs) as a placeholder;
2898 it will not remain in the result. */
2899 if (GET_CODE (XEXP (x, 0)) == PLUS
2900 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2901 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2903 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2904 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2907 /* This should have produced two insns, each of which sets our
2908 placeholder. If the source of the second is a valid address,
2909 we can make put both sources together and make a split point
2912 if (seq && XVECLEN (seq, 0) == 2
2913 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2914 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2915 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2916 && ! reg_mentioned_p (reg,
2917 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2918 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2919 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2920 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2921 && memory_address_p (GET_MODE (x),
2922 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2924 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2925 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2927 /* Replace the placeholder in SRC2 with SRC1. If we can
2928 find where in SRC2 it was placed, that can become our
2929 split point and we can replace this address with SRC2.
2930 Just try two obvious places. */
2932 src2 = replace_rtx (src2, reg, src1);
2934 if (XEXP (src2, 0) == src1)
2935 split = &XEXP (src2, 0);
2936 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2937 && XEXP (XEXP (src2, 0), 0) == src1)
2938 split = &XEXP (XEXP (src2, 0), 0);
2942 SUBST (XEXP (x, 0), src2);
2947 /* If that didn't work, perhaps the first operand is complex and
2948 needs to be computed separately, so make a split point there.
2949 This will occur on machines that just support REG + CONST
2950 and have a constant moved through some previous computation. */
2952 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2953 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2954 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2956 return &XEXP (XEXP (x, 0), 0);
2962 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2963 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2964 we need to put the operand into a register. So split at that
2967 if (SET_DEST (x) == cc0_rtx
2968 && GET_CODE (SET_SRC (x)) != COMPARE
2969 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2970 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2971 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2972 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2973 return &SET_SRC (x);
2976 /* See if we can split SET_SRC as it stands. */
2977 split = find_split_point (&SET_SRC (x), insn);
2978 if (split && split != &SET_SRC (x))
2981 /* See if we can split SET_DEST as it stands. */
2982 split = find_split_point (&SET_DEST (x), insn);
2983 if (split && split != &SET_DEST (x))
2986 /* See if this is a bitfield assignment with everything constant. If
2987 so, this is an IOR of an AND, so split it into that. */
2988 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2989 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2990 <= HOST_BITS_PER_WIDE_INT)
2991 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2992 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2993 && GET_CODE (SET_SRC (x)) == CONST_INT
2994 && ((INTVAL (XEXP (SET_DEST (x), 1))
2995 + INTVAL (XEXP (SET_DEST (x), 2)))
2996 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2997 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2999 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3000 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3001 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3002 rtx dest = XEXP (SET_DEST (x), 0);
3003 enum machine_mode mode = GET_MODE (dest);
3004 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3006 if (BITS_BIG_ENDIAN)
3007 pos = GET_MODE_BITSIZE (mode) - len - pos;
3011 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3014 gen_binary (IOR, mode,
3015 gen_binary (AND, mode, dest,
3016 GEN_INT (~(mask << pos)
3017 & GET_MODE_MASK (mode))),
3018 GEN_INT (src << pos)));
3020 SUBST (SET_DEST (x), dest);
3022 split = find_split_point (&SET_SRC (x), insn);
3023 if (split && split != &SET_SRC (x))
3027 /* Otherwise, see if this is an operation that we can split into two.
3028 If so, try to split that. */
3029 code = GET_CODE (SET_SRC (x));
3034 /* If we are AND'ing with a large constant that is only a single
3035 bit and the result is only being used in a context where we
3036 need to know if it is zero or non-zero, replace it with a bit
3037 extraction. This will avoid the large constant, which might
3038 have taken more than one insn to make. If the constant were
3039 not a valid argument to the AND but took only one insn to make,
3040 this is no worse, but if it took more than one insn, it will
3043 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3044 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3045 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3046 && GET_CODE (SET_DEST (x)) == REG
3047 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3048 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3049 && XEXP (*split, 0) == SET_DEST (x)
3050 && XEXP (*split, 1) == const0_rtx)
3052 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3053 XEXP (SET_SRC (x), 0),
3054 pos, NULL_RTX, 1, 1, 0, 0);
3055 if (extraction != 0)
3057 SUBST (SET_SRC (x), extraction);
3058 return find_split_point (loc, insn);
3064 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3065 is known to be on, this can be converted into a NEG of a shift. */
3066 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3067 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3068 && 1 <= (pos = exact_log2
3069 (nonzero_bits (XEXP (SET_SRC (x), 0),
3070 GET_MODE (XEXP (SET_SRC (x), 0))))))
3072 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3076 gen_rtx_LSHIFTRT (mode,
3077 XEXP (SET_SRC (x), 0),
3080 split = find_split_point (&SET_SRC (x), insn);
3081 if (split && split != &SET_SRC (x))
3087 inner = XEXP (SET_SRC (x), 0);
3089 /* We can't optimize if either mode is a partial integer
3090 mode as we don't know how many bits are significant
3092 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3093 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3097 len = GET_MODE_BITSIZE (GET_MODE (inner));
3103 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3104 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3106 inner = XEXP (SET_SRC (x), 0);
3107 len = INTVAL (XEXP (SET_SRC (x), 1));
3108 pos = INTVAL (XEXP (SET_SRC (x), 2));
3110 if (BITS_BIG_ENDIAN)
3111 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3112 unsignedp = (code == ZERO_EXTRACT);
3120 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3122 enum machine_mode mode = GET_MODE (SET_SRC (x));
3124 /* For unsigned, we have a choice of a shift followed by an
3125 AND or two shifts. Use two shifts for field sizes where the
3126 constant might be too large. We assume here that we can
3127 always at least get 8-bit constants in an AND insn, which is
3128 true for every current RISC. */
3130 if (unsignedp && len <= 8)
3135 (mode, gen_lowpart_for_combine (mode, inner),
3137 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3139 split = find_split_point (&SET_SRC (x), insn);
3140 if (split && split != &SET_SRC (x))
3147 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3148 gen_rtx_ASHIFT (mode,
3149 gen_lowpart_for_combine (mode, inner),
3150 GEN_INT (GET_MODE_BITSIZE (mode)
3152 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3154 split = find_split_point (&SET_SRC (x), insn);
3155 if (split && split != &SET_SRC (x))
3160 /* See if this is a simple operation with a constant as the second
3161 operand. It might be that this constant is out of range and hence
3162 could be used as a split point. */
3163 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3165 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3166 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3167 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3168 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3169 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3171 return &XEXP (SET_SRC (x), 1);
3173 /* Finally, see if this is a simple operation with its first operand
3174 not in a register. The operation might require this operand in a
3175 register, so return it as a split point. We can always do this
3176 because if the first operand were another operation, we would have
3177 already found it as a split point. */
3178 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3179 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3181 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3182 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3183 return &XEXP (SET_SRC (x), 0);
3189 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3190 it is better to write this as (not (ior A B)) so we can split it.
3191 Similarly for IOR. */
3192 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3195 gen_rtx_NOT (GET_MODE (x),
3196 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3198 XEXP (XEXP (x, 0), 0),
3199 XEXP (XEXP (x, 1), 0))));
3200 return find_split_point (loc, insn);
3203 /* Many RISC machines have a large set of logical insns. If the
3204 second operand is a NOT, put it first so we will try to split the
3205 other operand first. */
3206 if (GET_CODE (XEXP (x, 1)) == NOT)
3208 rtx tem = XEXP (x, 0);
3209 SUBST (XEXP (x, 0), XEXP (x, 1));
3210 SUBST (XEXP (x, 1), tem);
3218 /* Otherwise, select our actions depending on our rtx class. */
3219 switch (GET_RTX_CLASS (code))
3221 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3223 split = find_split_point (&XEXP (x, 2), insn);
3226 /* ... fall through ... */
3230 split = find_split_point (&XEXP (x, 1), insn);
3233 /* ... fall through ... */
3235 /* Some machines have (and (shift ...) ...) insns. If X is not
3236 an AND, but XEXP (X, 0) is, use it as our split point. */
3237 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3238 return &XEXP (x, 0);
3240 split = find_split_point (&XEXP (x, 0), insn);
3246 /* Otherwise, we don't have a split point. */
3250 /* Throughout X, replace FROM with TO, and return the result.
3251 The result is TO if X is FROM;
3252 otherwise the result is X, but its contents may have been modified.
3253 If they were modified, a record was made in undobuf so that
3254 undo_all will (among other things) return X to its original state.
3256 If the number of changes necessary is too much to record to undo,
3257 the excess changes are not made, so the result is invalid.
3258 The changes already made can still be undone.
3259 undobuf.num_undo is incremented for such changes, so by testing that
3260 the caller can tell whether the result is valid.
3262 `n_occurrences' is incremented each time FROM is replaced.
3264 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3266 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3267 by copying if `n_occurrences' is non-zero. */
3270 subst (x, from, to, in_dest, unique_copy)
3275 enum rtx_code code = GET_CODE (x);
3276 enum machine_mode op0_mode = VOIDmode;
3281 /* Two expressions are equal if they are identical copies of a shared
3282 RTX or if they are both registers with the same register number
3285 #define COMBINE_RTX_EQUAL_P(X,Y) \
3287 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3288 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3290 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3293 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3296 /* If X and FROM are the same register but different modes, they will
3297 not have been seen as equal above. However, flow.c will make a
3298 LOG_LINKS entry for that case. If we do nothing, we will try to
3299 rerecognize our original insn and, when it succeeds, we will
3300 delete the feeding insn, which is incorrect.
3302 So force this insn not to match in this (rare) case. */
3303 if (! in_dest && code == REG && GET_CODE (from) == REG
3304 && REGNO (x) == REGNO (from))
3305 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3307 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3308 of which may contain things that can be combined. */
3309 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3312 /* It is possible to have a subexpression appear twice in the insn.
3313 Suppose that FROM is a register that appears within TO.
3314 Then, after that subexpression has been scanned once by `subst',
3315 the second time it is scanned, TO may be found. If we were
3316 to scan TO here, we would find FROM within it and create a
3317 self-referent rtl structure which is completely wrong. */
3318 if (COMBINE_RTX_EQUAL_P (x, to))
3321 /* Parallel asm_operands need special attention because all of the
3322 inputs are shared across the arms. Furthermore, unsharing the
3323 rtl results in recognition failures. Failure to handle this case
3324 specially can result in circular rtl.
3326 Solve this by doing a normal pass across the first entry of the
3327 parallel, and only processing the SET_DESTs of the subsequent
3330 if (code == PARALLEL
3331 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3332 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3334 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3336 /* If this substitution failed, this whole thing fails. */
3337 if (GET_CODE (new) == CLOBBER
3338 && XEXP (new, 0) == const0_rtx)
3341 SUBST (XVECEXP (x, 0, 0), new);
3343 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3345 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3347 if (GET_CODE (dest) != REG
3348 && GET_CODE (dest) != CC0
3349 && GET_CODE (dest) != PC)
3351 new = subst (dest, from, to, 0, unique_copy);
3353 /* If this substitution failed, this whole thing fails. */
3354 if (GET_CODE (new) == CLOBBER
3355 && XEXP (new, 0) == const0_rtx)
3358 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3364 len = GET_RTX_LENGTH (code);
3365 fmt = GET_RTX_FORMAT (code);
3367 /* We don't need to process a SET_DEST that is a register, CC0,
3368 or PC, so set up to skip this common case. All other cases
3369 where we want to suppress replacing something inside a
3370 SET_SRC are handled via the IN_DEST operand. */
3372 && (GET_CODE (SET_DEST (x)) == REG
3373 || GET_CODE (SET_DEST (x)) == CC0
3374 || GET_CODE (SET_DEST (x)) == PC))
3377 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3380 op0_mode = GET_MODE (XEXP (x, 0));
3382 for (i = 0; i < len; i++)
3387 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3389 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3391 new = (unique_copy && n_occurrences
3392 ? copy_rtx (to) : to);
3397 new = subst (XVECEXP (x, i, j), from, to, 0,
3400 /* If this substitution failed, this whole thing
3402 if (GET_CODE (new) == CLOBBER
3403 && XEXP (new, 0) == const0_rtx)
3407 SUBST (XVECEXP (x, i, j), new);
3410 else if (fmt[i] == 'e')
3412 /* If this is a register being set, ignore it. */
3415 && (code == SUBREG || code == STRICT_LOW_PART
3416 || code == ZERO_EXTRACT)
3418 && GET_CODE (new) == REG)
3421 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3423 /* In general, don't install a subreg involving two
3424 modes not tieable. It can worsen register
3425 allocation, and can even make invalid reload
3426 insns, since the reg inside may need to be copied
3427 from in the outside mode, and that may be invalid
3428 if it is an fp reg copied in integer mode.
3430 We allow two exceptions to this: It is valid if
3431 it is inside another SUBREG and the mode of that
3432 SUBREG and the mode of the inside of TO is
3433 tieable and it is valid if X is a SET that copies
3436 if (GET_CODE (to) == SUBREG
3437 && ! MODES_TIEABLE_P (GET_MODE (to),
3438 GET_MODE (SUBREG_REG (to)))
3439 && ! (code == SUBREG
3440 && MODES_TIEABLE_P (GET_MODE (x),
3441 GET_MODE (SUBREG_REG (to))))
3443 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3446 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3448 #ifdef CLASS_CANNOT_CHANGE_MODE
3450 && GET_CODE (to) == REG
3451 && REGNO (to) < FIRST_PSEUDO_REGISTER
3452 && (TEST_HARD_REG_BIT
3453 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3455 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3457 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3460 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3464 /* If we are in a SET_DEST, suppress most cases unless we
3465 have gone inside a MEM, in which case we want to
3466 simplify the address. We assume here that things that
3467 are actually part of the destination have their inner
3468 parts in the first expression. This is true for SUBREG,
3469 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3470 things aside from REG and MEM that should appear in a
3472 new = subst (XEXP (x, i), from, to,
3474 && (code == SUBREG || code == STRICT_LOW_PART
3475 || code == ZERO_EXTRACT))
3477 && i == 0), unique_copy);
3479 /* If we found that we will have to reject this combination,
3480 indicate that by returning the CLOBBER ourselves, rather than
3481 an expression containing it. This will speed things up as
3482 well as prevent accidents where two CLOBBERs are considered
3483 to be equal, thus producing an incorrect simplification. */
3485 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3488 SUBST (XEXP (x, i), new);
3493 /* Try to simplify X. If the simplification changed the code, it is likely
3494 that further simplification will help, so loop, but limit the number
3495 of repetitions that will be performed. */
3497 for (i = 0; i < 4; i++)
3499 /* If X is sufficiently simple, don't bother trying to do anything
3501 if (code != CONST_INT && code != REG && code != CLOBBER)
3502 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3504 if (GET_CODE (x) == code)
3507 code = GET_CODE (x);
3509 /* We no longer know the original mode of operand 0 since we
3510 have changed the form of X) */
3511 op0_mode = VOIDmode;
3517 /* Simplify X, a piece of RTL. We just operate on the expression at the
3518 outer level; call `subst' to simplify recursively. Return the new
3521 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3522 will be the iteration even if an expression with a code different from
3523 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3526 combine_simplify_rtx (x, op0_mode, last, in_dest)
3528 enum machine_mode op0_mode;
3532 enum rtx_code code = GET_CODE (x);
3533 enum machine_mode mode = GET_MODE (x);
3538 /* If this is a commutative operation, put a constant last and a complex
3539 expression first. We don't need to do this for comparisons here. */
3540 if (GET_RTX_CLASS (code) == 'c'
3541 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3544 SUBST (XEXP (x, 0), XEXP (x, 1));
3545 SUBST (XEXP (x, 1), temp);
3548 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3549 sign extension of a PLUS with a constant, reverse the order of the sign
3550 extension and the addition. Note that this not the same as the original
3551 code, but overflow is undefined for signed values. Also note that the
3552 PLUS will have been partially moved "inside" the sign-extension, so that
3553 the first operand of X will really look like:
3554 (ashiftrt (plus (ashift A C4) C5) C4).
3556 (plus (ashiftrt (ashift A C4) C2) C4)
3557 and replace the first operand of X with that expression. Later parts
3558 of this function may simplify the expression further.
3560 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3561 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3562 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3564 We do this to simplify address expressions. */
3566 if ((code == PLUS || code == MINUS || code == MULT)
3567 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3568 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3569 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3570 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3571 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3572 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3573 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3574 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3575 XEXP (XEXP (XEXP (x, 0), 0), 1),
3576 XEXP (XEXP (x, 0), 1))) != 0)
3579 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3580 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3581 INTVAL (XEXP (XEXP (x, 0), 1)));
3583 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3584 INTVAL (XEXP (XEXP (x, 0), 1)));
3586 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3589 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3590 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3591 things. Check for cases where both arms are testing the same
3594 Don't do anything if all operands are very simple. */
3596 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3597 || GET_RTX_CLASS (code) == '<')
3598 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3599 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3600 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3602 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3603 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3604 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3606 || (GET_RTX_CLASS (code) == '1'
3607 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3608 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3609 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3612 rtx cond, true_rtx, false_rtx;
3614 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3616 /* If everything is a comparison, what we have is highly unlikely
3617 to be simpler, so don't use it. */
3618 && ! (GET_RTX_CLASS (code) == '<'
3619 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3620 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3622 rtx cop1 = const0_rtx;
3623 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3625 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3628 /* Simplify the alternative arms; this may collapse the true and
3629 false arms to store-flag values. */
3630 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3631 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3633 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3634 is unlikely to be simpler. */
3635 if (general_operand (true_rtx, VOIDmode)
3636 && general_operand (false_rtx, VOIDmode))
3638 /* Restarting if we generate a store-flag expression will cause
3639 us to loop. Just drop through in this case. */
3641 /* If the result values are STORE_FLAG_VALUE and zero, we can
3642 just make the comparison operation. */
3643 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3644 x = gen_binary (cond_code, mode, cond, cop1);
3645 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3646 && reverse_condition (cond_code) != UNKNOWN)
3647 x = gen_binary (reverse_condition (cond_code),
3650 /* Likewise, we can make the negate of a comparison operation
3651 if the result values are - STORE_FLAG_VALUE and zero. */
3652 else if (GET_CODE (true_rtx) == CONST_INT
3653 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3654 && false_rtx == const0_rtx)
3655 x = simplify_gen_unary (NEG, mode,
3656 gen_binary (cond_code, mode, cond,
3659 else if (GET_CODE (false_rtx) == CONST_INT
3660 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3661 && true_rtx == const0_rtx)
3662 x = simplify_gen_unary (NEG, mode,
3663 gen_binary (reverse_condition
3668 return gen_rtx_IF_THEN_ELSE (mode,
3669 gen_binary (cond_code, VOIDmode,
3671 true_rtx, false_rtx);
3673 code = GET_CODE (x);
3674 op0_mode = VOIDmode;
3679 /* Try to fold this expression in case we have constants that weren't
3682 switch (GET_RTX_CLASS (code))
3685 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3689 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3690 if (cmp_mode == VOIDmode)
3692 cmp_mode = GET_MODE (XEXP (x, 1));
3693 if (cmp_mode == VOIDmode)
3694 cmp_mode = op0_mode;
3696 temp = simplify_relational_operation (code, cmp_mode,
3697 XEXP (x, 0), XEXP (x, 1));
3699 #ifdef FLOAT_STORE_FLAG_VALUE
3700 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3702 if (temp == const0_rtx)
3703 temp = CONST0_RTX (mode);
3705 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3711 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3715 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3716 XEXP (x, 1), XEXP (x, 2));
3723 code = GET_CODE (temp);
3724 op0_mode = VOIDmode;
3725 mode = GET_MODE (temp);
3728 /* First see if we can apply the inverse distributive law. */
3729 if (code == PLUS || code == MINUS
3730 || code == AND || code == IOR || code == XOR)
3732 x = apply_distributive_law (x);
3733 code = GET_CODE (x);
3734 op0_mode = VOIDmode;
3737 /* If CODE is an associative operation not otherwise handled, see if we
3738 can associate some operands. This can win if they are constants or
3739 if they are logically related (i.e. (a & b) & a). */
3740 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3741 || code == AND || code == IOR || code == XOR
3742 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3743 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3744 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3746 if (GET_CODE (XEXP (x, 0)) == code)
3748 rtx other = XEXP (XEXP (x, 0), 0);
3749 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3750 rtx inner_op1 = XEXP (x, 1);
3753 /* Make sure we pass the constant operand if any as the second
3754 one if this is a commutative operation. */
3755 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3757 rtx tem = inner_op0;
3758 inner_op0 = inner_op1;
3761 inner = simplify_binary_operation (code == MINUS ? PLUS
3762 : code == DIV ? MULT
3764 mode, inner_op0, inner_op1);
3766 /* For commutative operations, try the other pair if that one
3768 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3770 other = XEXP (XEXP (x, 0), 1);
3771 inner = simplify_binary_operation (code, mode,
3772 XEXP (XEXP (x, 0), 0),
3777 return gen_binary (code, mode, other, inner);
3781 /* A little bit of algebraic simplification here. */
3785 /* Ensure that our address has any ASHIFTs converted to MULT in case
3786 address-recognizing predicates are called later. */
3787 temp = make_compound_operation (XEXP (x, 0), MEM);
3788 SUBST (XEXP (x, 0), temp);
3792 if (op0_mode == VOIDmode)
3793 op0_mode = GET_MODE (SUBREG_REG (x));
3795 /* simplify_subreg can't use gen_lowpart_for_combine. */
3796 if (CONSTANT_P (SUBREG_REG (x))
3797 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3798 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3800 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3804 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3810 /* Note that we cannot do any narrowing for non-constants since
3811 we might have been counting on using the fact that some bits were
3812 zero. We now do this in the SET. */
3817 /* (not (plus X -1)) can become (neg X). */
3818 if (GET_CODE (XEXP (x, 0)) == PLUS
3819 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3820 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3822 /* Similarly, (not (neg X)) is (plus X -1). */
3823 if (GET_CODE (XEXP (x, 0)) == NEG)
3824 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3826 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3827 if (GET_CODE (XEXP (x, 0)) == XOR
3828 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3829 && (temp = simplify_unary_operation (NOT, mode,
3830 XEXP (XEXP (x, 0), 1),
3832 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3834 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3835 other than 1, but that is not valid. We could do a similar
3836 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3837 but this doesn't seem common enough to bother with. */
3838 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3839 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3840 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3842 XEXP (XEXP (x, 0), 1));
3844 if (GET_CODE (XEXP (x, 0)) == SUBREG
3845 && subreg_lowpart_p (XEXP (x, 0))
3846 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3847 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3848 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3849 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3851 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3853 x = gen_rtx_ROTATE (inner_mode,
3854 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3856 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3857 return gen_lowpart_for_combine (mode, x);
3860 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3861 reversing the comparison code if valid. */
3862 if (STORE_FLAG_VALUE == -1
3863 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3864 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3865 XEXP (XEXP (x, 0), 1))))
3868 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3869 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3870 perform the above simplification. */
3872 if (STORE_FLAG_VALUE == -1
3873 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3874 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3875 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3876 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3878 /* Apply De Morgan's laws to reduce number of patterns for machines
3879 with negating logical insns (and-not, nand, etc.). If result has
3880 only one NOT, put it first, since that is how the patterns are
3883 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3885 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3886 enum machine_mode op_mode;
3888 op_mode = GET_MODE (in1);
3889 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3891 op_mode = GET_MODE (in2);
3892 if (op_mode == VOIDmode)
3894 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3896 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3899 in2 = in1; in1 = tem;
3902 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3908 /* (neg (plus X 1)) can become (not X). */
3909 if (GET_CODE (XEXP (x, 0)) == PLUS
3910 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3911 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3913 /* Similarly, (neg (not X)) is (plus X 1). */
3914 if (GET_CODE (XEXP (x, 0)) == NOT)
3915 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3917 /* (neg (minus X Y)) can become (minus Y X). */
3918 if (GET_CODE (XEXP (x, 0)) == MINUS
3919 && (! FLOAT_MODE_P (mode)
3920 /* x-y != -(y-x) with IEEE floating point. */
3921 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3922 || flag_unsafe_math_optimizations))
3923 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3924 XEXP (XEXP (x, 0), 0));
3926 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3927 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3928 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3929 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3931 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3932 if we can then eliminate the NEG (e.g.,
3933 if the operand is a constant). */
3935 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3937 temp = simplify_unary_operation (NEG, mode,
3938 XEXP (XEXP (x, 0), 0), mode);
3940 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
3943 temp = expand_compound_operation (XEXP (x, 0));
3945 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3946 replaced by (lshiftrt X C). This will convert
3947 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3949 if (GET_CODE (temp) == ASHIFTRT
3950 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3951 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3952 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3953 INTVAL (XEXP (temp, 1)));
3955 /* If X has only a single bit that might be nonzero, say, bit I, convert
3956 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3957 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3958 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3959 or a SUBREG of one since we'd be making the expression more
3960 complex if it was just a register. */
3962 if (GET_CODE (temp) != REG
3963 && ! (GET_CODE (temp) == SUBREG
3964 && GET_CODE (SUBREG_REG (temp)) == REG)
3965 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3967 rtx temp1 = simplify_shift_const
3968 (NULL_RTX, ASHIFTRT, mode,
3969 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3970 GET_MODE_BITSIZE (mode) - 1 - i),
3971 GET_MODE_BITSIZE (mode) - 1 - i);
3973 /* If all we did was surround TEMP with the two shifts, we
3974 haven't improved anything, so don't use it. Otherwise,
3975 we are better off with TEMP1. */
3976 if (GET_CODE (temp1) != ASHIFTRT
3977 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3978 || XEXP (XEXP (temp1, 0), 0) != temp)
3984 /* We can't handle truncation to a partial integer mode here
3985 because we don't know the real bitsize of the partial
3987 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3990 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3991 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3992 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3994 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3995 GET_MODE_MASK (mode), NULL_RTX, 0));
3997 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3998 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3999 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4000 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4001 return XEXP (XEXP (x, 0), 0);
4003 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4004 (OP:SI foo:SI) if OP is NEG or ABS. */
4005 if ((GET_CODE (XEXP (x, 0)) == ABS
4006 || GET_CODE (XEXP (x, 0)) == NEG)
4007 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4008 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4009 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4010 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4011 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4013 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4015 if (GET_CODE (XEXP (x, 0)) == SUBREG
4016 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4017 && subreg_lowpart_p (XEXP (x, 0)))
4018 return SUBREG_REG (XEXP (x, 0));
4020 /* If we know that the value is already truncated, we can
4021 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4022 is nonzero for the corresponding modes. But don't do this
4023 for an (LSHIFTRT (MULT ...)) since this will cause problems
4024 with the umulXi3_highpart patterns. */
4025 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4026 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4027 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4028 >= GET_MODE_BITSIZE (mode) + 1
4029 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4030 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4031 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4033 /* A truncate of a comparison can be replaced with a subreg if
4034 STORE_FLAG_VALUE permits. This is like the previous test,
4035 but it works even if the comparison is done in a mode larger
4036 than HOST_BITS_PER_WIDE_INT. */
4037 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4038 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4039 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4040 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4042 /* Similarly, a truncate of a register whose value is a
4043 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4045 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4046 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4047 && (temp = get_last_value (XEXP (x, 0)))
4048 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4049 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4053 case FLOAT_TRUNCATE:
4054 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4055 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4056 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4057 return XEXP (XEXP (x, 0), 0);
4059 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4060 (OP:SF foo:SF) if OP is NEG or ABS. */
4061 if ((GET_CODE (XEXP (x, 0)) == ABS
4062 || GET_CODE (XEXP (x, 0)) == NEG)
4063 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4064 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4065 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4066 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4068 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4069 is (float_truncate:SF x). */
4070 if (GET_CODE (XEXP (x, 0)) == SUBREG
4071 && subreg_lowpart_p (XEXP (x, 0))
4072 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4073 return SUBREG_REG (XEXP (x, 0));
4078 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4079 using cc0, in which case we want to leave it as a COMPARE
4080 so we can distinguish it from a register-register-copy. */
4081 if (XEXP (x, 1) == const0_rtx)
4084 /* In IEEE floating point, x-0 is not the same as x. */
4085 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4086 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4087 || flag_unsafe_math_optimizations)
4088 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4094 /* (const (const X)) can become (const X). Do it this way rather than
4095 returning the inner CONST since CONST can be shared with a
4097 if (GET_CODE (XEXP (x, 0)) == CONST)
4098 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4103 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4104 can add in an offset. find_split_point will split this address up
4105 again if it doesn't match. */
4106 if (GET_CODE (XEXP (x, 0)) == HIGH
4107 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4113 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4114 outermost. That's because that's the way indexed addresses are
4115 supposed to appear. This code used to check many more cases, but
4116 they are now checked elsewhere. */
4117 if (GET_CODE (XEXP (x, 0)) == PLUS
4118 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4119 return gen_binary (PLUS, mode,
4120 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4122 XEXP (XEXP (x, 0), 1));
4124 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4125 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4126 bit-field and can be replaced by either a sign_extend or a
4127 sign_extract. The `and' may be a zero_extend and the two
4128 <c>, -<c> constants may be reversed. */
4129 if (GET_CODE (XEXP (x, 0)) == XOR
4130 && GET_CODE (XEXP (x, 1)) == CONST_INT
4131 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4132 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4133 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4134 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4135 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4136 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4137 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4138 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4139 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4140 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4141 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4142 == (unsigned int) i + 1))))
4143 return simplify_shift_const
4144 (NULL_RTX, ASHIFTRT, mode,
4145 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4146 XEXP (XEXP (XEXP (x, 0), 0), 0),
4147 GET_MODE_BITSIZE (mode) - (i + 1)),
4148 GET_MODE_BITSIZE (mode) - (i + 1));
4150 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4151 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4152 is 1. This produces better code than the alternative immediately
4154 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4155 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4156 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4157 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4158 XEXP (XEXP (x, 0), 0),
4159 XEXP (XEXP (x, 0), 1))))
4161 simplify_gen_unary (NEG, mode, reversed, mode);
4163 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4164 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4165 the bitsize of the mode - 1. This allows simplification of
4166 "a = (b & 8) == 0;" */
4167 if (XEXP (x, 1) == constm1_rtx
4168 && GET_CODE (XEXP (x, 0)) != REG
4169 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4170 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4171 && nonzero_bits (XEXP (x, 0), mode) == 1)
4172 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4173 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4174 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4175 GET_MODE_BITSIZE (mode) - 1),
4176 GET_MODE_BITSIZE (mode) - 1);
4178 /* If we are adding two things that have no bits in common, convert
4179 the addition into an IOR. This will often be further simplified,
4180 for example in cases like ((a & 1) + (a & 2)), which can
4183 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4184 && (nonzero_bits (XEXP (x, 0), mode)
4185 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4187 /* Try to simplify the expression further. */
4188 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4189 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4191 /* If we could, great. If not, do not go ahead with the IOR
4192 replacement, since PLUS appears in many special purpose
4193 address arithmetic instructions. */
4194 if (GET_CODE (temp) != CLOBBER && temp != tor)
4200 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4201 by reversing the comparison code if valid. */
4202 if (STORE_FLAG_VALUE == 1
4203 && XEXP (x, 0) == const1_rtx
4204 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4205 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4206 XEXP (XEXP (x, 1), 0),
4207 XEXP (XEXP (x, 1), 1))))
4210 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4211 (and <foo> (const_int pow2-1)) */
4212 if (GET_CODE (XEXP (x, 1)) == AND
4213 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4214 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4215 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4216 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4217 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4219 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4221 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4222 return gen_binary (MINUS, mode,
4223 gen_binary (MINUS, mode, XEXP (x, 0),
4224 XEXP (XEXP (x, 1), 0)),
4225 XEXP (XEXP (x, 1), 1));
4229 /* If we have (mult (plus A B) C), apply the distributive law and then
4230 the inverse distributive law to see if things simplify. This
4231 occurs mostly in addresses, often when unrolling loops. */
4233 if (GET_CODE (XEXP (x, 0)) == PLUS)
4235 x = apply_distributive_law
4236 (gen_binary (PLUS, mode,
4237 gen_binary (MULT, mode,
4238 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4239 gen_binary (MULT, mode,
4240 XEXP (XEXP (x, 0), 1),
4241 copy_rtx (XEXP (x, 1)))));
4243 if (GET_CODE (x) != MULT)
4246 /* Try simplify a*(b/c) as (a*b)/c. */
4247 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4248 && GET_CODE (XEXP (x, 0)) == DIV)
4250 rtx tem = simplify_binary_operation (MULT, mode,
4251 XEXP (XEXP (x, 0), 0),
4254 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4259 /* If this is a divide by a power of two, treat it as a shift if
4260 its first operand is a shift. */
4261 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4262 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4263 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4264 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4265 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4266 || GET_CODE (XEXP (x, 0)) == ROTATE
4267 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4268 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4272 case GT: case GTU: case GE: case GEU:
4273 case LT: case LTU: case LE: case LEU:
4274 case UNEQ: case LTGT:
4275 case UNGT: case UNGE:
4276 case UNLT: case UNLE:
4277 case UNORDERED: case ORDERED:
4278 /* If the first operand is a condition code, we can't do anything
4280 if (GET_CODE (XEXP (x, 0)) == COMPARE
4281 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4283 && XEXP (x, 0) != cc0_rtx
4287 rtx op0 = XEXP (x, 0);
4288 rtx op1 = XEXP (x, 1);
4289 enum rtx_code new_code;
4291 if (GET_CODE (op0) == COMPARE)
4292 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4294 /* Simplify our comparison, if possible. */
4295 new_code = simplify_comparison (code, &op0, &op1);
4297 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4298 if only the low-order bit is possibly nonzero in X (such as when
4299 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4300 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4301 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4304 Remove any ZERO_EXTRACT we made when thinking this was a
4305 comparison. It may now be simpler to use, e.g., an AND. If a
4306 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4307 the call to make_compound_operation in the SET case. */
4309 if (STORE_FLAG_VALUE == 1
4310 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4311 && op1 == const0_rtx
4312 && mode == GET_MODE (op0)
4313 && nonzero_bits (op0, mode) == 1)
4314 return gen_lowpart_for_combine (mode,
4315 expand_compound_operation (op0));
4317 else if (STORE_FLAG_VALUE == 1
4318 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4319 && op1 == const0_rtx
4320 && mode == GET_MODE (op0)
4321 && (num_sign_bit_copies (op0, mode)
4322 == GET_MODE_BITSIZE (mode)))
4324 op0 = expand_compound_operation (op0);
4325 return simplify_gen_unary (NEG, mode,
4326 gen_lowpart_for_combine (mode, op0),
4330 else if (STORE_FLAG_VALUE == 1
4331 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4332 && op1 == const0_rtx
4333 && mode == GET_MODE (op0)
4334 && nonzero_bits (op0, mode) == 1)
4336 op0 = expand_compound_operation (op0);
4337 return gen_binary (XOR, mode,
4338 gen_lowpart_for_combine (mode, op0),
4342 else if (STORE_FLAG_VALUE == 1
4343 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4344 && op1 == const0_rtx
4345 && mode == GET_MODE (op0)
4346 && (num_sign_bit_copies (op0, mode)
4347 == GET_MODE_BITSIZE (mode)))
4349 op0 = expand_compound_operation (op0);
4350 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4353 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4355 if (STORE_FLAG_VALUE == -1
4356 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4357 && op1 == const0_rtx
4358 && (num_sign_bit_copies (op0, mode)
4359 == GET_MODE_BITSIZE (mode)))
4360 return gen_lowpart_for_combine (mode,
4361 expand_compound_operation (op0));
4363 else if (STORE_FLAG_VALUE == -1
4364 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4365 && op1 == const0_rtx
4366 && mode == GET_MODE (op0)
4367 && nonzero_bits (op0, mode) == 1)
4369 op0 = expand_compound_operation (op0);
4370 return simplify_gen_unary (NEG, mode,
4371 gen_lowpart_for_combine (mode, op0),
4375 else if (STORE_FLAG_VALUE == -1
4376 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4377 && op1 == const0_rtx
4378 && mode == GET_MODE (op0)
4379 && (num_sign_bit_copies (op0, mode)
4380 == GET_MODE_BITSIZE (mode)))
4382 op0 = expand_compound_operation (op0);
4383 return simplify_gen_unary (NOT, mode,
4384 gen_lowpart_for_combine (mode, op0),
4388 /* If X is 0/1, (eq X 0) is X-1. */
4389 else if (STORE_FLAG_VALUE == -1
4390 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4391 && op1 == const0_rtx
4392 && mode == GET_MODE (op0)
4393 && nonzero_bits (op0, mode) == 1)
4395 op0 = expand_compound_operation (op0);
4396 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4399 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4400 one bit that might be nonzero, we can convert (ne x 0) to
4401 (ashift x c) where C puts the bit in the sign bit. Remove any
4402 AND with STORE_FLAG_VALUE when we are done, since we are only
4403 going to test the sign bit. */
4404 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4405 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4406 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4407 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4408 && op1 == const0_rtx
4409 && mode == GET_MODE (op0)
4410 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4412 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4413 expand_compound_operation (op0),
4414 GET_MODE_BITSIZE (mode) - 1 - i);
4415 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4421 /* If the code changed, return a whole new comparison. */
4422 if (new_code != code)
4423 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4425 /* Otherwise, keep this operation, but maybe change its operands.
4426 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4427 SUBST (XEXP (x, 0), op0);
4428 SUBST (XEXP (x, 1), op1);
4433 return simplify_if_then_else (x);
4439 /* If we are processing SET_DEST, we are done. */
4443 return expand_compound_operation (x);
4446 return simplify_set (x);
4451 return simplify_logical (x, last);
4454 /* (abs (neg <foo>)) -> (abs <foo>) */
4455 if (GET_CODE (XEXP (x, 0)) == NEG)
4456 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4458 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4460 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4463 /* If operand is something known to be positive, ignore the ABS. */
4464 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4465 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4466 <= HOST_BITS_PER_WIDE_INT)
4467 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4468 & ((HOST_WIDE_INT) 1
4469 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4473 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4474 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4475 return gen_rtx_NEG (mode, XEXP (x, 0));
4480 /* (ffs (*_extend <X>)) = (ffs <X>) */
4481 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4482 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4483 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4487 /* (float (sign_extend <X>)) = (float <X>). */
4488 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4489 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4497 /* If this is a shift by a constant amount, simplify it. */
4498 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4499 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4500 INTVAL (XEXP (x, 1)));
4502 #ifdef SHIFT_COUNT_TRUNCATED
4503 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4505 force_to_mode (XEXP (x, 1), GET_MODE (x),
4507 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4516 rtx op0 = XEXP (x, 0);
4517 rtx op1 = XEXP (x, 1);
4520 if (GET_CODE (op1) != PARALLEL)
4522 len = XVECLEN (op1, 0);
4524 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4525 && GET_CODE (op0) == VEC_CONCAT)
4527 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4529 /* Try to find the element in the VEC_CONCAT. */
4532 if (GET_MODE (op0) == GET_MODE (x))
4534 if (GET_CODE (op0) == VEC_CONCAT)
4536 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4537 if (op0_size < offset)
4538 op0 = XEXP (op0, 0);
4542 op0 = XEXP (op0, 1);
4560 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4563 simplify_if_then_else (x)
4566 enum machine_mode mode = GET_MODE (x);
4567 rtx cond = XEXP (x, 0);
4568 rtx true_rtx = XEXP (x, 1);
4569 rtx false_rtx = XEXP (x, 2);
4570 enum rtx_code true_code = GET_CODE (cond);
4571 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4574 enum rtx_code false_code;
4577 /* Simplify storing of the truth value. */
4578 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4579 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4581 /* Also when the truth value has to be reversed. */
4583 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4584 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4588 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4589 in it is being compared against certain values. Get the true and false
4590 comparisons and see if that says anything about the value of each arm. */
4593 && ((false_code = combine_reversed_comparison_code (cond))
4595 && GET_CODE (XEXP (cond, 0)) == REG)
4598 rtx from = XEXP (cond, 0);
4599 rtx true_val = XEXP (cond, 1);
4600 rtx false_val = true_val;
4603 /* If FALSE_CODE is EQ, swap the codes and arms. */
4605 if (false_code == EQ)
4607 swapped = 1, true_code = EQ, false_code = NE;
4608 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4611 /* If we are comparing against zero and the expression being tested has
4612 only a single bit that might be nonzero, that is its value when it is
4613 not equal to zero. Similarly if it is known to be -1 or 0. */
4615 if (true_code == EQ && true_val == const0_rtx
4616 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4617 false_code = EQ, false_val = GEN_INT (nzb);
4618 else if (true_code == EQ && true_val == const0_rtx
4619 && (num_sign_bit_copies (from, GET_MODE (from))
4620 == GET_MODE_BITSIZE (GET_MODE (from))))
4621 false_code = EQ, false_val = constm1_rtx;
4623 /* Now simplify an arm if we know the value of the register in the
4624 branch and it is used in the arm. Be careful due to the potential
4625 of locally-shared RTL. */
4627 if (reg_mentioned_p (from, true_rtx))
4628 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4630 pc_rtx, pc_rtx, 0, 0);
4631 if (reg_mentioned_p (from, false_rtx))
4632 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4634 pc_rtx, pc_rtx, 0, 0);
4636 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4637 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4639 true_rtx = XEXP (x, 1);
4640 false_rtx = XEXP (x, 2);
4641 true_code = GET_CODE (cond);
4644 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4645 reversed, do so to avoid needing two sets of patterns for
4646 subtract-and-branch insns. Similarly if we have a constant in the true
4647 arm, the false arm is the same as the first operand of the comparison, or
4648 the false arm is more complicated than the true arm. */
4651 && combine_reversed_comparison_code (cond) != UNKNOWN
4652 && (true_rtx == pc_rtx
4653 || (CONSTANT_P (true_rtx)
4654 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4655 || true_rtx == const0_rtx
4656 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4657 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4658 || (GET_CODE (true_rtx) == SUBREG
4659 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4660 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4661 || reg_mentioned_p (true_rtx, false_rtx)
4662 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4664 true_code = reversed_comparison_code (cond, NULL);
4666 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4669 SUBST (XEXP (x, 1), false_rtx);
4670 SUBST (XEXP (x, 2), true_rtx);
4672 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4675 /* It is possible that the conditional has been simplified out. */
4676 true_code = GET_CODE (cond);
4677 comparison_p = GET_RTX_CLASS (true_code) == '<';
4680 /* If the two arms are identical, we don't need the comparison. */
4682 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4685 /* Convert a == b ? b : a to "a". */
4686 if (true_code == EQ && ! side_effects_p (cond)
4687 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4688 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4689 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4691 else if (true_code == NE && ! side_effects_p (cond)
4692 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4693 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4694 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4697 /* Look for cases where we have (abs x) or (neg (abs X)). */
4699 if (GET_MODE_CLASS (mode) == MODE_INT
4700 && GET_CODE (false_rtx) == NEG
4701 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4703 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4704 && ! side_effects_p (true_rtx))
4709 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4713 simplify_gen_unary (NEG, mode,
4714 simplify_gen_unary (ABS, mode, true_rtx, mode),
4720 /* Look for MIN or MAX. */
4722 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4724 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4725 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4726 && ! side_effects_p (cond))
4731 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4734 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4737 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4740 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4745 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4746 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4747 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4748 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4749 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4750 neither 1 or -1, but it isn't worth checking for. */
4752 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4753 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4755 rtx t = make_compound_operation (true_rtx, SET);
4756 rtx f = make_compound_operation (false_rtx, SET);
4757 rtx cond_op0 = XEXP (cond, 0);
4758 rtx cond_op1 = XEXP (cond, 1);
4759 enum rtx_code op = NIL, extend_op = NIL;
4760 enum machine_mode m = mode;
4761 rtx z = 0, c1 = NULL_RTX;
4763 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4764 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4765 || GET_CODE (t) == ASHIFT
4766 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4767 && rtx_equal_p (XEXP (t, 0), f))
4768 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4770 /* If an identity-zero op is commutative, check whether there
4771 would be a match if we swapped the operands. */
4772 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4773 || GET_CODE (t) == XOR)
4774 && rtx_equal_p (XEXP (t, 1), f))
4775 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4776 else if (GET_CODE (t) == SIGN_EXTEND
4777 && (GET_CODE (XEXP (t, 0)) == PLUS
4778 || GET_CODE (XEXP (t, 0)) == MINUS
4779 || GET_CODE (XEXP (t, 0)) == IOR
4780 || GET_CODE (XEXP (t, 0)) == XOR
4781 || GET_CODE (XEXP (t, 0)) == ASHIFT
4782 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4783 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4784 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4785 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4786 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4787 && (num_sign_bit_copies (f, GET_MODE (f))
4788 > (GET_MODE_BITSIZE (mode)
4789 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4791 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4792 extend_op = SIGN_EXTEND;
4793 m = GET_MODE (XEXP (t, 0));
4795 else if (GET_CODE (t) == SIGN_EXTEND
4796 && (GET_CODE (XEXP (t, 0)) == PLUS
4797 || GET_CODE (XEXP (t, 0)) == IOR
4798 || GET_CODE (XEXP (t, 0)) == XOR)
4799 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4800 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4801 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4802 && (num_sign_bit_copies (f, GET_MODE (f))
4803 > (GET_MODE_BITSIZE (mode)
4804 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4806 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4807 extend_op = SIGN_EXTEND;
4808 m = GET_MODE (XEXP (t, 0));
4810 else if (GET_CODE (t) == ZERO_EXTEND
4811 && (GET_CODE (XEXP (t, 0)) == PLUS
4812 || GET_CODE (XEXP (t, 0)) == MINUS
4813 || GET_CODE (XEXP (t, 0)) == IOR
4814 || GET_CODE (XEXP (t, 0)) == XOR
4815 || GET_CODE (XEXP (t, 0)) == ASHIFT
4816 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4817 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4818 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4819 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4820 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4821 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4822 && ((nonzero_bits (f, GET_MODE (f))
4823 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4826 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4827 extend_op = ZERO_EXTEND;
4828 m = GET_MODE (XEXP (t, 0));
4830 else if (GET_CODE (t) == ZERO_EXTEND
4831 && (GET_CODE (XEXP (t, 0)) == PLUS
4832 || GET_CODE (XEXP (t, 0)) == IOR
4833 || GET_CODE (XEXP (t, 0)) == XOR)
4834 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4835 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4836 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4837 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4838 && ((nonzero_bits (f, GET_MODE (f))
4839 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4842 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4843 extend_op = ZERO_EXTEND;
4844 m = GET_MODE (XEXP (t, 0));
4849 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4850 pc_rtx, pc_rtx, 0, 0);
4851 temp = gen_binary (MULT, m, temp,
4852 gen_binary (MULT, m, c1, const_true_rtx));
4853 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4854 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4856 if (extend_op != NIL)
4857 temp = simplify_gen_unary (extend_op, mode, temp, m);
4863 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4864 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4865 negation of a single bit, we can convert this operation to a shift. We
4866 can actually do this more generally, but it doesn't seem worth it. */
4868 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4869 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4870 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4871 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4872 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4873 == GET_MODE_BITSIZE (mode))
4874 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4876 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4877 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4882 /* Simplify X, a SET expression. Return the new expression. */
4888 rtx src = SET_SRC (x);
4889 rtx dest = SET_DEST (x);
4890 enum machine_mode mode
4891 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4895 /* (set (pc) (return)) gets written as (return). */
4896 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4899 /* Now that we know for sure which bits of SRC we are using, see if we can
4900 simplify the expression for the object knowing that we only need the
4903 if (GET_MODE_CLASS (mode) == MODE_INT)
4905 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4906 SUBST (SET_SRC (x), src);
4909 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4910 the comparison result and try to simplify it unless we already have used
4911 undobuf.other_insn. */
4912 if ((GET_CODE (src) == COMPARE
4917 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4918 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4919 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4920 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4922 enum rtx_code old_code = GET_CODE (*cc_use);
4923 enum rtx_code new_code;
4925 int other_changed = 0;
4926 enum machine_mode compare_mode = GET_MODE (dest);
4928 if (GET_CODE (src) == COMPARE)
4929 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4931 op0 = src, op1 = const0_rtx;
4933 /* Simplify our comparison, if possible. */
4934 new_code = simplify_comparison (old_code, &op0, &op1);
4936 #ifdef EXTRA_CC_MODES
4937 /* If this machine has CC modes other than CCmode, check to see if we
4938 need to use a different CC mode here. */
4939 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4940 #endif /* EXTRA_CC_MODES */
4942 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4943 /* If the mode changed, we have to change SET_DEST, the mode in the
4944 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4945 a hard register, just build new versions with the proper mode. If it
4946 is a pseudo, we lose unless it is only time we set the pseudo, in
4947 which case we can safely change its mode. */
4948 if (compare_mode != GET_MODE (dest))
4950 unsigned int regno = REGNO (dest);
4951 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4953 if (regno < FIRST_PSEUDO_REGISTER
4954 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4956 if (regno >= FIRST_PSEUDO_REGISTER)
4957 SUBST (regno_reg_rtx[regno], new_dest);
4959 SUBST (SET_DEST (x), new_dest);
4960 SUBST (XEXP (*cc_use, 0), new_dest);
4968 /* If the code changed, we have to build a new comparison in
4969 undobuf.other_insn. */
4970 if (new_code != old_code)
4972 unsigned HOST_WIDE_INT mask;
4974 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
4977 /* If the only change we made was to change an EQ into an NE or
4978 vice versa, OP0 has only one bit that might be nonzero, and OP1
4979 is zero, check if changing the user of the condition code will
4980 produce a valid insn. If it won't, we can keep the original code
4981 in that insn by surrounding our operation with an XOR. */
4983 if (((old_code == NE && new_code == EQ)
4984 || (old_code == EQ && new_code == NE))
4985 && ! other_changed && op1 == const0_rtx
4986 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4987 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4989 rtx pat = PATTERN (other_insn), note = 0;
4991 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4992 && ! check_asm_operands (pat)))
4994 PUT_CODE (*cc_use, old_code);
4997 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5005 undobuf.other_insn = other_insn;
5008 /* If we are now comparing against zero, change our source if
5009 needed. If we do not use cc0, we always have a COMPARE. */
5010 if (op1 == const0_rtx && dest == cc0_rtx)
5012 SUBST (SET_SRC (x), op0);
5018 /* Otherwise, if we didn't previously have a COMPARE in the
5019 correct mode, we need one. */
5020 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5022 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5027 /* Otherwise, update the COMPARE if needed. */
5028 SUBST (XEXP (src, 0), op0);
5029 SUBST (XEXP (src, 1), op1);
5034 /* Get SET_SRC in a form where we have placed back any
5035 compound expressions. Then do the checks below. */
5036 src = make_compound_operation (src, SET);
5037 SUBST (SET_SRC (x), src);
5040 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5041 and X being a REG or (subreg (reg)), we may be able to convert this to
5042 (set (subreg:m2 x) (op)).
5044 We can always do this if M1 is narrower than M2 because that means that
5045 we only care about the low bits of the result.
5047 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5048 perform a narrower operation than requested since the high-order bits will
5049 be undefined. On machine where it is defined, this transformation is safe
5050 as long as M1 and M2 have the same number of words. */
5052 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5053 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5054 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5056 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5057 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5058 #ifndef WORD_REGISTER_OPERATIONS
5059 && (GET_MODE_SIZE (GET_MODE (src))
5060 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5062 #ifdef CLASS_CANNOT_CHANGE_MODE
5063 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5064 && (TEST_HARD_REG_BIT
5065 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5067 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5068 GET_MODE (SUBREG_REG (src))))
5070 && (GET_CODE (dest) == REG
5071 || (GET_CODE (dest) == SUBREG
5072 && GET_CODE (SUBREG_REG (dest)) == REG)))
5074 SUBST (SET_DEST (x),
5075 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5077 SUBST (SET_SRC (x), SUBREG_REG (src));
5079 src = SET_SRC (x), dest = SET_DEST (x);
5082 #ifdef LOAD_EXTEND_OP
5083 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5084 would require a paradoxical subreg. Replace the subreg with a
5085 zero_extend to avoid the reload that would otherwise be required. */
5087 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5088 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5089 && SUBREG_BYTE (src) == 0
5090 && (GET_MODE_SIZE (GET_MODE (src))
5091 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5092 && GET_CODE (SUBREG_REG (src)) == MEM)
5095 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5096 GET_MODE (src), SUBREG_REG (src)));
5102 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5103 are comparing an item known to be 0 or -1 against 0, use a logical
5104 operation instead. Check for one of the arms being an IOR of the other
5105 arm with some value. We compute three terms to be IOR'ed together. In
5106 practice, at most two will be nonzero. Then we do the IOR's. */
5108 if (GET_CODE (dest) != PC
5109 && GET_CODE (src) == IF_THEN_ELSE
5110 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5111 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5112 && XEXP (XEXP (src, 0), 1) == const0_rtx
5113 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5114 #ifdef HAVE_conditional_move
5115 && ! can_conditionally_move_p (GET_MODE (src))
5117 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5118 GET_MODE (XEXP (XEXP (src, 0), 0)))
5119 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5120 && ! side_effects_p (src))
5122 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5123 ? XEXP (src, 1) : XEXP (src, 2));
5124 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5125 ? XEXP (src, 2) : XEXP (src, 1));
5126 rtx term1 = const0_rtx, term2, term3;
5128 if (GET_CODE (true_rtx) == IOR
5129 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5130 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5131 else if (GET_CODE (true_rtx) == IOR
5132 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5133 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5134 else if (GET_CODE (false_rtx) == IOR
5135 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5136 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5137 else if (GET_CODE (false_rtx) == IOR
5138 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5139 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5141 term2 = gen_binary (AND, GET_MODE (src),
5142 XEXP (XEXP (src, 0), 0), true_rtx);
5143 term3 = gen_binary (AND, GET_MODE (src),
5144 simplify_gen_unary (NOT, GET_MODE (src),
5145 XEXP (XEXP (src, 0), 0),
5150 gen_binary (IOR, GET_MODE (src),
5151 gen_binary (IOR, GET_MODE (src), term1, term2),
5157 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5158 whole thing fail. */
5159 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5161 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5164 /* Convert this into a field assignment operation, if possible. */
5165 return make_field_assignment (x);
5168 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5169 result. LAST is nonzero if this is the last retry. */
5172 simplify_logical (x, last)
5176 enum machine_mode mode = GET_MODE (x);
5177 rtx op0 = XEXP (x, 0);
5178 rtx op1 = XEXP (x, 1);
5181 switch (GET_CODE (x))
5184 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5185 insn (and may simplify more). */
5186 if (GET_CODE (op0) == XOR
5187 && rtx_equal_p (XEXP (op0, 0), op1)
5188 && ! side_effects_p (op1))
5189 x = gen_binary (AND, mode,
5190 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5193 if (GET_CODE (op0) == XOR
5194 && rtx_equal_p (XEXP (op0, 1), op1)
5195 && ! side_effects_p (op1))
5196 x = gen_binary (AND, mode,
5197 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5200 /* Similarly for (~(A ^ B)) & A. */
5201 if (GET_CODE (op0) == NOT
5202 && GET_CODE (XEXP (op0, 0)) == XOR
5203 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5204 && ! side_effects_p (op1))
5205 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5207 if (GET_CODE (op0) == NOT
5208 && GET_CODE (XEXP (op0, 0)) == XOR
5209 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5210 && ! side_effects_p (op1))
5211 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5213 /* We can call simplify_and_const_int only if we don't lose
5214 any (sign) bits when converting INTVAL (op1) to
5215 "unsigned HOST_WIDE_INT". */
5216 if (GET_CODE (op1) == CONST_INT
5217 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5218 || INTVAL (op1) > 0))
5220 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5222 /* If we have (ior (and (X C1) C2)) and the next restart would be
5223 the last, simplify this by making C1 as small as possible
5226 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5227 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5228 && GET_CODE (op1) == CONST_INT)
5229 return gen_binary (IOR, mode,
5230 gen_binary (AND, mode, XEXP (op0, 0),
5231 GEN_INT (INTVAL (XEXP (op0, 1))
5232 & ~INTVAL (op1))), op1);
5234 if (GET_CODE (x) != AND)
5237 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5238 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5239 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5242 /* Convert (A | B) & A to A. */
5243 if (GET_CODE (op0) == IOR
5244 && (rtx_equal_p (XEXP (op0, 0), op1)
5245 || rtx_equal_p (XEXP (op0, 1), op1))
5246 && ! side_effects_p (XEXP (op0, 0))
5247 && ! side_effects_p (XEXP (op0, 1)))
5250 /* In the following group of tests (and those in case IOR below),
5251 we start with some combination of logical operations and apply
5252 the distributive law followed by the inverse distributive law.
5253 Most of the time, this results in no change. However, if some of
5254 the operands are the same or inverses of each other, simplifications
5257 For example, (and (ior A B) (not B)) can occur as the result of
5258 expanding a bit field assignment. When we apply the distributive
5259 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5260 which then simplifies to (and (A (not B))).
5262 If we have (and (ior A B) C), apply the distributive law and then
5263 the inverse distributive law to see if things simplify. */
5265 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5267 x = apply_distributive_law
5268 (gen_binary (GET_CODE (op0), mode,
5269 gen_binary (AND, mode, XEXP (op0, 0), op1),
5270 gen_binary (AND, mode, XEXP (op0, 1),
5272 if (GET_CODE (x) != AND)
5276 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5277 return apply_distributive_law
5278 (gen_binary (GET_CODE (op1), mode,
5279 gen_binary (AND, mode, XEXP (op1, 0), op0),
5280 gen_binary (AND, mode, XEXP (op1, 1),
5283 /* Similarly, taking advantage of the fact that
5284 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5286 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5287 return apply_distributive_law
5288 (gen_binary (XOR, mode,
5289 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5290 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5293 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5294 return apply_distributive_law
5295 (gen_binary (XOR, mode,
5296 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5297 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5301 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5302 if (GET_CODE (op1) == CONST_INT
5303 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5304 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5307 /* Convert (A & B) | A to A. */
5308 if (GET_CODE (op0) == AND
5309 && (rtx_equal_p (XEXP (op0, 0), op1)
5310 || rtx_equal_p (XEXP (op0, 1), op1))
5311 && ! side_effects_p (XEXP (op0, 0))
5312 && ! side_effects_p (XEXP (op0, 1)))
5315 /* If we have (ior (and A B) C), apply the distributive law and then
5316 the inverse distributive law to see if things simplify. */
5318 if (GET_CODE (op0) == AND)
5320 x = apply_distributive_law
5321 (gen_binary (AND, mode,
5322 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5323 gen_binary (IOR, mode, XEXP (op0, 1),
5326 if (GET_CODE (x) != IOR)
5330 if (GET_CODE (op1) == AND)
5332 x = apply_distributive_law
5333 (gen_binary (AND, mode,
5334 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5335 gen_binary (IOR, mode, XEXP (op1, 1),
5338 if (GET_CODE (x) != IOR)
5342 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5343 mode size to (rotate A CX). */
5345 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5346 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5347 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5348 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5349 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5350 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5351 == GET_MODE_BITSIZE (mode)))
5352 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5353 (GET_CODE (op0) == ASHIFT
5354 ? XEXP (op0, 1) : XEXP (op1, 1)));
5356 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5357 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5358 does not affect any of the bits in OP1, it can really be done
5359 as a PLUS and we can associate. We do this by seeing if OP1
5360 can be safely shifted left C bits. */
5361 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5362 && GET_CODE (XEXP (op0, 0)) == PLUS
5363 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5364 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5365 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5367 int count = INTVAL (XEXP (op0, 1));
5368 HOST_WIDE_INT mask = INTVAL (op1) << count;
5370 if (mask >> count == INTVAL (op1)
5371 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5373 SUBST (XEXP (XEXP (op0, 0), 1),
5374 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5381 /* If we are XORing two things that have no bits in common,
5382 convert them into an IOR. This helps to detect rotation encoded
5383 using those methods and possibly other simplifications. */
5385 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5386 && (nonzero_bits (op0, mode)
5387 & nonzero_bits (op1, mode)) == 0)
5388 return (gen_binary (IOR, mode, op0, op1));
5390 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5391 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5394 int num_negated = 0;
5396 if (GET_CODE (op0) == NOT)
5397 num_negated++, op0 = XEXP (op0, 0);
5398 if (GET_CODE (op1) == NOT)
5399 num_negated++, op1 = XEXP (op1, 0);
5401 if (num_negated == 2)
5403 SUBST (XEXP (x, 0), op0);
5404 SUBST (XEXP (x, 1), op1);
5406 else if (num_negated == 1)
5408 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5412 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5413 correspond to a machine insn or result in further simplifications
5414 if B is a constant. */
5416 if (GET_CODE (op0) == AND
5417 && rtx_equal_p (XEXP (op0, 1), op1)
5418 && ! side_effects_p (op1))
5419 return gen_binary (AND, mode,
5420 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5423 else if (GET_CODE (op0) == AND
5424 && rtx_equal_p (XEXP (op0, 0), op1)
5425 && ! side_effects_p (op1))
5426 return gen_binary (AND, mode,
5427 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5430 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5431 comparison if STORE_FLAG_VALUE is 1. */
5432 if (STORE_FLAG_VALUE == 1
5433 && op1 == const1_rtx
5434 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5435 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5439 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5440 is (lt foo (const_int 0)), so we can perform the above
5441 simplification if STORE_FLAG_VALUE is 1. */
5443 if (STORE_FLAG_VALUE == 1
5444 && op1 == const1_rtx
5445 && GET_CODE (op0) == LSHIFTRT
5446 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5447 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5448 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5450 /* (xor (comparison foo bar) (const_int sign-bit))
5451 when STORE_FLAG_VALUE is the sign bit. */
5452 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5453 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5454 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5455 && op1 == const_true_rtx
5456 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5457 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5470 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5471 operations" because they can be replaced with two more basic operations.
5472 ZERO_EXTEND is also considered "compound" because it can be replaced with
5473 an AND operation, which is simpler, though only one operation.
5475 The function expand_compound_operation is called with an rtx expression
5476 and will convert it to the appropriate shifts and AND operations,
5477 simplifying at each stage.
5479 The function make_compound_operation is called to convert an expression
5480 consisting of shifts and ANDs into the equivalent compound expression.
5481 It is the inverse of this function, loosely speaking. */
5484 expand_compound_operation (x)
5487 unsigned HOST_WIDE_INT pos = 0, len;
5489 unsigned int modewidth;
5492 switch (GET_CODE (x))
5497 /* We can't necessarily use a const_int for a multiword mode;
5498 it depends on implicitly extending the value.
5499 Since we don't know the right way to extend it,
5500 we can't tell whether the implicit way is right.
5502 Even for a mode that is no wider than a const_int,
5503 we can't win, because we need to sign extend one of its bits through
5504 the rest of it, and we don't know which bit. */
5505 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5508 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5509 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5510 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5511 reloaded. If not for that, MEM's would very rarely be safe.
5513 Reject MODEs bigger than a word, because we might not be able
5514 to reference a two-register group starting with an arbitrary register
5515 (and currently gen_lowpart might crash for a SUBREG). */
5517 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5520 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5521 /* If the inner object has VOIDmode (the only way this can happen
5522 is if it is a ASM_OPERANDS), we can't do anything since we don't
5523 know how much masking to do. */
5532 /* If the operand is a CLOBBER, just return it. */
5533 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5536 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5537 || GET_CODE (XEXP (x, 2)) != CONST_INT
5538 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5541 len = INTVAL (XEXP (x, 1));
5542 pos = INTVAL (XEXP (x, 2));
5544 /* If this goes outside the object being extracted, replace the object
5545 with a (use (mem ...)) construct that only combine understands
5546 and is used only for this purpose. */
5547 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5548 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5550 if (BITS_BIG_ENDIAN)
5551 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5558 /* Convert sign extension to zero extension, if we know that the high
5559 bit is not set, as this is easier to optimize. It will be converted
5560 back to cheaper alternative in make_extraction. */
5561 if (GET_CODE (x) == SIGN_EXTEND
5562 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5563 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5564 & ~(((unsigned HOST_WIDE_INT)
5565 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5569 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5570 return expand_compound_operation (temp);
5573 /* We can optimize some special cases of ZERO_EXTEND. */
5574 if (GET_CODE (x) == ZERO_EXTEND)
5576 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5577 know that the last value didn't have any inappropriate bits
5579 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5580 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5581 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5582 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5583 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5584 return XEXP (XEXP (x, 0), 0);
5586 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5587 if (GET_CODE (XEXP (x, 0)) == SUBREG
5588 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5589 && subreg_lowpart_p (XEXP (x, 0))
5590 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5591 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5592 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5593 return SUBREG_REG (XEXP (x, 0));
5595 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5596 is a comparison and STORE_FLAG_VALUE permits. This is like
5597 the first case, but it works even when GET_MODE (x) is larger
5598 than HOST_WIDE_INT. */
5599 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5600 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5601 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5602 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5603 <= HOST_BITS_PER_WIDE_INT)
5604 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5605 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5606 return XEXP (XEXP (x, 0), 0);
5608 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5609 if (GET_CODE (XEXP (x, 0)) == SUBREG
5610 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5611 && subreg_lowpart_p (XEXP (x, 0))
5612 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5613 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5614 <= HOST_BITS_PER_WIDE_INT)
5615 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5616 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5617 return SUBREG_REG (XEXP (x, 0));
5621 /* If we reach here, we want to return a pair of shifts. The inner
5622 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5623 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5624 logical depending on the value of UNSIGNEDP.
5626 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5627 converted into an AND of a shift.
5629 We must check for the case where the left shift would have a negative
5630 count. This can happen in a case like (x >> 31) & 255 on machines
5631 that can't shift by a constant. On those machines, we would first
5632 combine the shift with the AND to produce a variable-position
5633 extraction. Then the constant of 31 would be substituted in to produce
5634 a such a position. */
5636 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5637 if (modewidth + len >= pos)
5638 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5640 simplify_shift_const (NULL_RTX, ASHIFT,
5643 modewidth - pos - len),
5646 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5647 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5648 simplify_shift_const (NULL_RTX, LSHIFTRT,
5651 ((HOST_WIDE_INT) 1 << len) - 1);
5653 /* Any other cases we can't handle. */
5656 /* If we couldn't do this for some reason, return the original
5658 if (GET_CODE (tem) == CLOBBER)
5664 /* X is a SET which contains an assignment of one object into
5665 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5666 or certain SUBREGS). If possible, convert it into a series of
5669 We half-heartedly support variable positions, but do not at all
5670 support variable lengths. */
5673 expand_field_assignment (x)
5677 rtx pos; /* Always counts from low bit. */
5680 enum machine_mode compute_mode;
5682 /* Loop until we find something we can't simplify. */
5685 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5686 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5688 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5689 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5690 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5692 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5693 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5695 inner = XEXP (SET_DEST (x), 0);
5696 len = INTVAL (XEXP (SET_DEST (x), 1));
5697 pos = XEXP (SET_DEST (x), 2);
5699 /* If the position is constant and spans the width of INNER,
5700 surround INNER with a USE to indicate this. */
5701 if (GET_CODE (pos) == CONST_INT
5702 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5703 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5705 if (BITS_BIG_ENDIAN)
5707 if (GET_CODE (pos) == CONST_INT)
5708 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5710 else if (GET_CODE (pos) == MINUS
5711 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5712 && (INTVAL (XEXP (pos, 1))
5713 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5714 /* If position is ADJUST - X, new position is X. */
5715 pos = XEXP (pos, 0);
5717 pos = gen_binary (MINUS, GET_MODE (pos),
5718 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5724 /* A SUBREG between two modes that occupy the same numbers of words
5725 can be done by moving the SUBREG to the source. */
5726 else if (GET_CODE (SET_DEST (x)) == SUBREG
5727 /* We need SUBREGs to compute nonzero_bits properly. */
5728 && nonzero_sign_valid
5729 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5730 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5731 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5732 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5734 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5735 gen_lowpart_for_combine
5736 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5743 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5744 inner = SUBREG_REG (inner);
5746 compute_mode = GET_MODE (inner);
5748 /* Don't attempt bitwise arithmetic on non-integral modes. */
5749 if (! INTEGRAL_MODE_P (compute_mode))
5751 enum machine_mode imode;
5753 /* Something is probably seriously wrong if this matches. */
5754 if (! FLOAT_MODE_P (compute_mode))
5757 /* Try to find an integral mode to pun with. */
5758 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5759 if (imode == BLKmode)
5762 compute_mode = imode;
5763 inner = gen_lowpart_for_combine (imode, inner);
5766 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5767 if (len < HOST_BITS_PER_WIDE_INT)
5768 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5772 /* Now compute the equivalent expression. Make a copy of INNER
5773 for the SET_DEST in case it is a MEM into which we will substitute;
5774 we don't want shared RTL in that case. */
5776 (VOIDmode, copy_rtx (inner),
5777 gen_binary (IOR, compute_mode,
5778 gen_binary (AND, compute_mode,
5779 simplify_gen_unary (NOT, compute_mode,
5785 gen_binary (ASHIFT, compute_mode,
5786 gen_binary (AND, compute_mode,
5787 gen_lowpart_for_combine
5788 (compute_mode, SET_SRC (x)),
5796 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5797 it is an RTX that represents a variable starting position; otherwise,
5798 POS is the (constant) starting bit position (counted from the LSB).
5800 INNER may be a USE. This will occur when we started with a bitfield
5801 that went outside the boundary of the object in memory, which is
5802 allowed on most machines. To isolate this case, we produce a USE
5803 whose mode is wide enough and surround the MEM with it. The only
5804 code that understands the USE is this routine. If it is not removed,
5805 it will cause the resulting insn not to match.
5807 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5810 IN_DEST is non-zero if this is a reference in the destination of a
5811 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5812 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5815 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5816 ZERO_EXTRACT should be built even for bits starting at bit 0.
5818 MODE is the desired mode of the result (if IN_DEST == 0).
5820 The result is an RTX for the extraction or NULL_RTX if the target
5824 make_extraction (mode, inner, pos, pos_rtx, len,
5825 unsignedp, in_dest, in_compare)
5826 enum machine_mode mode;
5830 unsigned HOST_WIDE_INT len;
5832 int in_dest, in_compare;
5834 /* This mode describes the size of the storage area
5835 to fetch the overall value from. Within that, we
5836 ignore the POS lowest bits, etc. */
5837 enum machine_mode is_mode = GET_MODE (inner);
5838 enum machine_mode inner_mode;
5839 enum machine_mode wanted_inner_mode = byte_mode;
5840 enum machine_mode wanted_inner_reg_mode = word_mode;
5841 enum machine_mode pos_mode = word_mode;
5842 enum machine_mode extraction_mode = word_mode;
5843 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5846 rtx orig_pos_rtx = pos_rtx;
5847 HOST_WIDE_INT orig_pos;
5849 /* Get some information about INNER and get the innermost object. */
5850 if (GET_CODE (inner) == USE)
5851 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5852 /* We don't need to adjust the position because we set up the USE
5853 to pretend that it was a full-word object. */
5854 spans_byte = 1, inner = XEXP (inner, 0);
5855 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5857 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5858 consider just the QI as the memory to extract from.
5859 The subreg adds or removes high bits; its mode is
5860 irrelevant to the meaning of this extraction,
5861 since POS and LEN count from the lsb. */
5862 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5863 is_mode = GET_MODE (SUBREG_REG (inner));
5864 inner = SUBREG_REG (inner);
5867 inner_mode = GET_MODE (inner);
5869 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5870 pos = INTVAL (pos_rtx), pos_rtx = 0;
5872 /* See if this can be done without an extraction. We never can if the
5873 width of the field is not the same as that of some integer mode. For
5874 registers, we can only avoid the extraction if the position is at the
5875 low-order bit and this is either not in the destination or we have the
5876 appropriate STRICT_LOW_PART operation available.
5878 For MEM, we can avoid an extract if the field starts on an appropriate
5879 boundary and we can change the mode of the memory reference. However,
5880 we cannot directly access the MEM if we have a USE and the underlying
5881 MEM is not TMODE. This combination means that MEM was being used in a
5882 context where bits outside its mode were being referenced; that is only
5883 valid in bit-field insns. */
5885 if (tmode != BLKmode
5886 && ! (spans_byte && inner_mode != tmode)
5887 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5888 && GET_CODE (inner) != MEM
5890 || (GET_CODE (inner) == REG
5891 && have_insn_for (STRICT_LOW_PART, tmode))))
5892 || (GET_CODE (inner) == MEM && pos_rtx == 0
5894 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5895 : BITS_PER_UNIT)) == 0
5896 /* We can't do this if we are widening INNER_MODE (it
5897 may not be aligned, for one thing). */
5898 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5899 && (inner_mode == tmode
5900 || (! mode_dependent_address_p (XEXP (inner, 0))
5901 && ! MEM_VOLATILE_P (inner))))))
5903 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5904 field. If the original and current mode are the same, we need not
5905 adjust the offset. Otherwise, we do if bytes big endian.
5907 If INNER is not a MEM, get a piece consisting of just the field
5908 of interest (in this case POS % BITS_PER_WORD must be 0). */
5910 if (GET_CODE (inner) == MEM)
5912 HOST_WIDE_INT offset;
5914 /* POS counts from lsb, but make OFFSET count in memory order. */
5915 if (BYTES_BIG_ENDIAN)
5916 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5918 offset = pos / BITS_PER_UNIT;
5920 new = adjust_address_nv (inner, tmode, offset);
5922 else if (GET_CODE (inner) == REG)
5924 /* We can't call gen_lowpart_for_combine here since we always want
5925 a SUBREG and it would sometimes return a new hard register. */
5926 if (tmode != inner_mode)
5928 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5930 if (WORDS_BIG_ENDIAN
5931 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5932 final_word = ((GET_MODE_SIZE (inner_mode)
5933 - GET_MODE_SIZE (tmode))
5934 / UNITS_PER_WORD) - final_word;
5936 final_word *= UNITS_PER_WORD;
5937 if (BYTES_BIG_ENDIAN &&
5938 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5939 final_word += (GET_MODE_SIZE (inner_mode)
5940 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5942 new = gen_rtx_SUBREG (tmode, inner, final_word);
5948 new = force_to_mode (inner, tmode,
5949 len >= HOST_BITS_PER_WIDE_INT
5950 ? ~(unsigned HOST_WIDE_INT) 0
5951 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5954 /* If this extraction is going into the destination of a SET,
5955 make a STRICT_LOW_PART unless we made a MEM. */
5958 return (GET_CODE (new) == MEM ? new
5959 : (GET_CODE (new) != SUBREG
5960 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5961 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
5966 /* If we know that no extraneous bits are set, and that the high
5967 bit is not set, convert the extraction to the cheaper of
5968 sign and zero extension, that are equivalent in these cases. */
5969 if (flag_expensive_optimizations
5970 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5971 && ((nonzero_bits (new, tmode)
5972 & ~(((unsigned HOST_WIDE_INT)
5973 GET_MODE_MASK (tmode))
5977 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5978 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5980 /* Prefer ZERO_EXTENSION, since it gives more information to
5982 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
5987 /* Otherwise, sign- or zero-extend unless we already are in the
5990 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5994 /* Unless this is a COMPARE or we have a funny memory reference,
5995 don't do anything with zero-extending field extracts starting at
5996 the low-order bit since they are simple AND operations. */
5997 if (pos_rtx == 0 && pos == 0 && ! in_dest
5998 && ! in_compare && ! spans_byte && unsignedp)
6001 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6002 we would be spanning bytes or if the position is not a constant and the
6003 length is not 1. In all other cases, we would only be going outside
6004 our object in cases when an original shift would have been
6006 if (! spans_byte && GET_CODE (inner) == MEM
6007 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6008 || (pos_rtx != 0 && len != 1)))
6011 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6012 and the mode for the result. */
6013 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6015 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6016 pos_mode = mode_for_extraction (EP_insv, 2);
6017 extraction_mode = mode_for_extraction (EP_insv, 3);
6020 if (! in_dest && unsignedp
6021 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6023 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6024 pos_mode = mode_for_extraction (EP_extzv, 3);
6025 extraction_mode = mode_for_extraction (EP_extzv, 0);
6028 if (! in_dest && ! unsignedp
6029 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6031 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6032 pos_mode = mode_for_extraction (EP_extv, 3);
6033 extraction_mode = mode_for_extraction (EP_extv, 0);
6036 /* Never narrow an object, since that might not be safe. */
6038 if (mode != VOIDmode
6039 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6040 extraction_mode = mode;
6042 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6043 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6044 pos_mode = GET_MODE (pos_rtx);
6046 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6047 if we have to change the mode of memory and cannot, the desired mode is
6049 if (GET_CODE (inner) != MEM)
6050 wanted_inner_mode = wanted_inner_reg_mode;
6051 else if (inner_mode != wanted_inner_mode
6052 && (mode_dependent_address_p (XEXP (inner, 0))
6053 || MEM_VOLATILE_P (inner)))
6054 wanted_inner_mode = extraction_mode;
6058 if (BITS_BIG_ENDIAN)
6060 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6061 BITS_BIG_ENDIAN style. If position is constant, compute new
6062 position. Otherwise, build subtraction.
6063 Note that POS is relative to the mode of the original argument.
6064 If it's a MEM we need to recompute POS relative to that.
6065 However, if we're extracting from (or inserting into) a register,
6066 we want to recompute POS relative to wanted_inner_mode. */
6067 int width = (GET_CODE (inner) == MEM
6068 ? GET_MODE_BITSIZE (is_mode)
6069 : GET_MODE_BITSIZE (wanted_inner_mode));
6072 pos = width - len - pos;
6075 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6076 /* POS may be less than 0 now, but we check for that below.
6077 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6080 /* If INNER has a wider mode, make it smaller. If this is a constant
6081 extract, try to adjust the byte to point to the byte containing
6083 if (wanted_inner_mode != VOIDmode
6084 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6085 && ((GET_CODE (inner) == MEM
6086 && (inner_mode == wanted_inner_mode
6087 || (! mode_dependent_address_p (XEXP (inner, 0))
6088 && ! MEM_VOLATILE_P (inner))))))
6092 /* The computations below will be correct if the machine is big
6093 endian in both bits and bytes or little endian in bits and bytes.
6094 If it is mixed, we must adjust. */
6096 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6097 adjust OFFSET to compensate. */
6098 if (BYTES_BIG_ENDIAN
6100 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6101 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6103 /* If this is a constant position, we can move to the desired byte. */
6106 offset += pos / BITS_PER_UNIT;
6107 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6110 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6112 && is_mode != wanted_inner_mode)
6113 offset = (GET_MODE_SIZE (is_mode)
6114 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6116 if (offset != 0 || inner_mode != wanted_inner_mode)
6117 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6120 /* If INNER is not memory, we can always get it into the proper mode. If we
6121 are changing its mode, POS must be a constant and smaller than the size
6123 else if (GET_CODE (inner) != MEM)
6125 if (GET_MODE (inner) != wanted_inner_mode
6127 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6130 inner = force_to_mode (inner, wanted_inner_mode,
6132 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6133 ? ~(unsigned HOST_WIDE_INT) 0
6134 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6139 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6140 have to zero extend. Otherwise, we can just use a SUBREG. */
6142 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6144 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6146 /* If we know that no extraneous bits are set, and that the high
6147 bit is not set, convert extraction to cheaper one - either
6148 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6150 if (flag_expensive_optimizations
6151 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6152 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6153 & ~(((unsigned HOST_WIDE_INT)
6154 GET_MODE_MASK (GET_MODE (pos_rtx)))
6158 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6160 /* Prefer ZERO_EXTENSION, since it gives more information to
6162 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6167 else if (pos_rtx != 0
6168 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6169 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6171 /* Make POS_RTX unless we already have it and it is correct. If we don't
6172 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6174 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6175 pos_rtx = orig_pos_rtx;
6177 else if (pos_rtx == 0)
6178 pos_rtx = GEN_INT (pos);
6180 /* Make the required operation. See if we can use existing rtx. */
6181 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6182 extraction_mode, inner, GEN_INT (len), pos_rtx);
6184 new = gen_lowpart_for_combine (mode, new);
6189 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6190 with any other operations in X. Return X without that shift if so. */
6193 extract_left_shift (x, count)
6197 enum rtx_code code = GET_CODE (x);
6198 enum machine_mode mode = GET_MODE (x);
6204 /* This is the shift itself. If it is wide enough, we will return
6205 either the value being shifted if the shift count is equal to
6206 COUNT or a shift for the difference. */
6207 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6208 && INTVAL (XEXP (x, 1)) >= count)
6209 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6210 INTVAL (XEXP (x, 1)) - count);
6214 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6215 return simplify_gen_unary (code, mode, tem, mode);
6219 case PLUS: case IOR: case XOR: case AND:
6220 /* If we can safely shift this constant and we find the inner shift,
6221 make a new operation. */
6222 if (GET_CODE (XEXP (x,1)) == CONST_INT
6223 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6224 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6225 return gen_binary (code, mode, tem,
6226 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6237 /* Look at the expression rooted at X. Look for expressions
6238 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6239 Form these expressions.
6241 Return the new rtx, usually just X.
6243 Also, for machines like the VAX that don't have logical shift insns,
6244 try to convert logical to arithmetic shift operations in cases where
6245 they are equivalent. This undoes the canonicalizations to logical
6246 shifts done elsewhere.
6248 We try, as much as possible, to re-use rtl expressions to save memory.
6250 IN_CODE says what kind of expression we are processing. Normally, it is
6251 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6252 being kludges), it is MEM. When processing the arguments of a comparison
6253 or a COMPARE against zero, it is COMPARE. */
6256 make_compound_operation (x, in_code)
6258 enum rtx_code in_code;
6260 enum rtx_code code = GET_CODE (x);
6261 enum machine_mode mode = GET_MODE (x);
6262 int mode_width = GET_MODE_BITSIZE (mode);
6264 enum rtx_code next_code;
6270 /* Select the code to be used in recursive calls. Once we are inside an
6271 address, we stay there. If we have a comparison, set to COMPARE,
6272 but once inside, go back to our default of SET. */
6274 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6275 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6276 && XEXP (x, 1) == const0_rtx) ? COMPARE
6277 : in_code == COMPARE ? SET : in_code);
6279 /* Process depending on the code of this operation. If NEW is set
6280 non-zero, it will be returned. */
6285 /* Convert shifts by constants into multiplications if inside
6287 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6288 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6289 && INTVAL (XEXP (x, 1)) >= 0)
6291 new = make_compound_operation (XEXP (x, 0), next_code);
6292 new = gen_rtx_MULT (mode, new,
6293 GEN_INT ((HOST_WIDE_INT) 1
6294 << INTVAL (XEXP (x, 1))));
6299 /* If the second operand is not a constant, we can't do anything
6301 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6304 /* If the constant is a power of two minus one and the first operand
6305 is a logical right shift, make an extraction. */
6306 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6307 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6309 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6310 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6311 0, in_code == COMPARE);
6314 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6315 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6316 && subreg_lowpart_p (XEXP (x, 0))
6317 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6318 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6320 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6322 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6323 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6324 0, in_code == COMPARE);
6326 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6327 else if ((GET_CODE (XEXP (x, 0)) == XOR
6328 || GET_CODE (XEXP (x, 0)) == IOR)
6329 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6330 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6331 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6333 /* Apply the distributive law, and then try to make extractions. */
6334 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6335 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6337 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6339 new = make_compound_operation (new, in_code);
6342 /* If we are have (and (rotate X C) M) and C is larger than the number
6343 of bits in M, this is an extraction. */
6345 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6346 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6347 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6348 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6350 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6351 new = make_extraction (mode, new,
6352 (GET_MODE_BITSIZE (mode)
6353 - INTVAL (XEXP (XEXP (x, 0), 1))),
6354 NULL_RTX, i, 1, 0, in_code == COMPARE);
6357 /* On machines without logical shifts, if the operand of the AND is
6358 a logical shift and our mask turns off all the propagated sign
6359 bits, we can replace the logical shift with an arithmetic shift. */
6360 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6361 && !have_insn_for (LSHIFTRT, mode)
6362 && have_insn_for (ASHIFTRT, mode)
6363 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6364 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6365 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6366 && mode_width <= HOST_BITS_PER_WIDE_INT)
6368 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6370 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6371 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6373 gen_rtx_ASHIFTRT (mode,
6374 make_compound_operation
6375 (XEXP (XEXP (x, 0), 0), next_code),
6376 XEXP (XEXP (x, 0), 1)));
6379 /* If the constant is one less than a power of two, this might be
6380 representable by an extraction even if no shift is present.
6381 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6382 we are in a COMPARE. */
6383 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6384 new = make_extraction (mode,
6385 make_compound_operation (XEXP (x, 0),
6387 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6389 /* If we are in a comparison and this is an AND with a power of two,
6390 convert this into the appropriate bit extract. */
6391 else if (in_code == COMPARE
6392 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6393 new = make_extraction (mode,
6394 make_compound_operation (XEXP (x, 0),
6396 i, NULL_RTX, 1, 1, 0, 1);
6401 /* If the sign bit is known to be zero, replace this with an
6402 arithmetic shift. */
6403 if (have_insn_for (ASHIFTRT, mode)
6404 && ! have_insn_for (LSHIFTRT, mode)
6405 && mode_width <= HOST_BITS_PER_WIDE_INT
6406 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6408 new = gen_rtx_ASHIFTRT (mode,
6409 make_compound_operation (XEXP (x, 0),
6415 /* ... fall through ... */
6421 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6422 this is a SIGN_EXTRACT. */
6423 if (GET_CODE (rhs) == CONST_INT
6424 && GET_CODE (lhs) == ASHIFT
6425 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6426 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6428 new = make_compound_operation (XEXP (lhs, 0), next_code);
6429 new = make_extraction (mode, new,
6430 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6431 NULL_RTX, mode_width - INTVAL (rhs),
6432 code == LSHIFTRT, 0, in_code == COMPARE);
6436 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6437 If so, try to merge the shifts into a SIGN_EXTEND. We could
6438 also do this for some cases of SIGN_EXTRACT, but it doesn't
6439 seem worth the effort; the case checked for occurs on Alpha. */
6441 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6442 && ! (GET_CODE (lhs) == SUBREG
6443 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6444 && GET_CODE (rhs) == CONST_INT
6445 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6446 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6447 new = make_extraction (mode, make_compound_operation (new, next_code),
6448 0, NULL_RTX, mode_width - INTVAL (rhs),
6449 code == LSHIFTRT, 0, in_code == COMPARE);
6454 /* Call ourselves recursively on the inner expression. If we are
6455 narrowing the object and it has a different RTL code from
6456 what it originally did, do this SUBREG as a force_to_mode. */
6458 tem = make_compound_operation (SUBREG_REG (x), in_code);
6459 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6460 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6461 && subreg_lowpart_p (x))
6463 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6466 /* If we have something other than a SUBREG, we might have
6467 done an expansion, so rerun ourselves. */
6468 if (GET_CODE (newer) != SUBREG)
6469 newer = make_compound_operation (newer, in_code);
6474 /* If this is a paradoxical subreg, and the new code is a sign or
6475 zero extension, omit the subreg and widen the extension. If it
6476 is a regular subreg, we can still get rid of the subreg by not
6477 widening so much, or in fact removing the extension entirely. */
6478 if ((GET_CODE (tem) == SIGN_EXTEND
6479 || GET_CODE (tem) == ZERO_EXTEND)
6480 && subreg_lowpart_p (x))
6482 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6483 || (GET_MODE_SIZE (mode) >
6484 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6485 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6487 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6498 x = gen_lowpart_for_combine (mode, new);
6499 code = GET_CODE (x);
6502 /* Now recursively process each operand of this operation. */
6503 fmt = GET_RTX_FORMAT (code);
6504 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6507 new = make_compound_operation (XEXP (x, i), next_code);
6508 SUBST (XEXP (x, i), new);
6514 /* Given M see if it is a value that would select a field of bits
6515 within an item, but not the entire word. Return -1 if not.
6516 Otherwise, return the starting position of the field, where 0 is the
6519 *PLEN is set to the length of the field. */
6522 get_pos_from_mask (m, plen)
6523 unsigned HOST_WIDE_INT m;
6524 unsigned HOST_WIDE_INT *plen;
6526 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6527 int pos = exact_log2 (m & -m);
6533 /* Now shift off the low-order zero bits and see if we have a power of
6535 len = exact_log2 ((m >> pos) + 1);
6544 /* See if X can be simplified knowing that we will only refer to it in
6545 MODE and will only refer to those bits that are nonzero in MASK.
6546 If other bits are being computed or if masking operations are done
6547 that select a superset of the bits in MASK, they can sometimes be
6550 Return a possibly simplified expression, but always convert X to
6551 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6553 Also, if REG is non-zero and X is a register equal in value to REG,
6556 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6557 are all off in X. This is used when X will be complemented, by either
6558 NOT, NEG, or XOR. */
6561 force_to_mode (x, mode, mask, reg, just_select)
6563 enum machine_mode mode;
6564 unsigned HOST_WIDE_INT mask;
6568 enum rtx_code code = GET_CODE (x);
6569 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6570 enum machine_mode op_mode;
6571 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6574 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6575 code below will do the wrong thing since the mode of such an
6576 expression is VOIDmode.
6578 Also do nothing if X is a CLOBBER; this can happen if X was
6579 the return value from a call to gen_lowpart_for_combine. */
6580 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6583 /* We want to perform the operation is its present mode unless we know
6584 that the operation is valid in MODE, in which case we do the operation
6586 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6587 && have_insn_for (code, mode))
6588 ? mode : GET_MODE (x));
6590 /* It is not valid to do a right-shift in a narrower mode
6591 than the one it came in with. */
6592 if ((code == LSHIFTRT || code == ASHIFTRT)
6593 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6594 op_mode = GET_MODE (x);
6596 /* Truncate MASK to fit OP_MODE. */
6598 mask &= GET_MODE_MASK (op_mode);
6600 /* When we have an arithmetic operation, or a shift whose count we
6601 do not know, we need to assume that all bit the up to the highest-order
6602 bit in MASK will be needed. This is how we form such a mask. */
6604 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6605 ? GET_MODE_MASK (op_mode)
6606 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6609 fuller_mask = ~(HOST_WIDE_INT) 0;
6611 /* Determine what bits of X are guaranteed to be (non)zero. */
6612 nonzero = nonzero_bits (x, mode);
6614 /* If none of the bits in X are needed, return a zero. */
6615 if (! just_select && (nonzero & mask) == 0)
6618 /* If X is a CONST_INT, return a new one. Do this here since the
6619 test below will fail. */
6620 if (GET_CODE (x) == CONST_INT)
6622 HOST_WIDE_INT cval = INTVAL (x) & mask;
6623 int width = GET_MODE_BITSIZE (mode);
6625 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6626 number, sign extend it. */
6627 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6628 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6629 cval |= (HOST_WIDE_INT) -1 << width;
6631 return GEN_INT (cval);
6634 /* If X is narrower than MODE and we want all the bits in X's mode, just
6635 get X in the proper mode. */
6636 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6637 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6638 return gen_lowpart_for_combine (mode, x);
6640 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6641 MASK are already known to be zero in X, we need not do anything. */
6642 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6648 /* If X is a (clobber (const_int)), return it since we know we are
6649 generating something that won't match. */
6653 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6654 spanned the boundary of the MEM. If we are now masking so it is
6655 within that boundary, we don't need the USE any more. */
6656 if (! BITS_BIG_ENDIAN
6657 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6658 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6665 x = expand_compound_operation (x);
6666 if (GET_CODE (x) != code)
6667 return force_to_mode (x, mode, mask, reg, next_select);
6671 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6672 || rtx_equal_p (reg, get_last_value (x))))
6677 if (subreg_lowpart_p (x)
6678 /* We can ignore the effect of this SUBREG if it narrows the mode or
6679 if the constant masks to zero all the bits the mode doesn't
6681 && ((GET_MODE_SIZE (GET_MODE (x))
6682 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6684 & GET_MODE_MASK (GET_MODE (x))
6685 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6686 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6690 /* If this is an AND with a constant, convert it into an AND
6691 whose constant is the AND of that constant with MASK. If it
6692 remains an AND of MASK, delete it since it is redundant. */
6694 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6696 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6697 mask & INTVAL (XEXP (x, 1)));
6699 /* If X is still an AND, see if it is an AND with a mask that
6700 is just some low-order bits. If so, and it is MASK, we don't
6703 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6704 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6705 == (HOST_WIDE_INT) mask))
6708 /* If it remains an AND, try making another AND with the bits
6709 in the mode mask that aren't in MASK turned on. If the
6710 constant in the AND is wide enough, this might make a
6711 cheaper constant. */
6713 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6714 && GET_MODE_MASK (GET_MODE (x)) != mask
6715 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6717 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6718 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6719 int width = GET_MODE_BITSIZE (GET_MODE (x));
6722 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6723 number, sign extend it. */
6724 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6725 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6726 cval |= (HOST_WIDE_INT) -1 << width;
6728 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6729 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6739 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6740 low-order bits (as in an alignment operation) and FOO is already
6741 aligned to that boundary, mask C1 to that boundary as well.
6742 This may eliminate that PLUS and, later, the AND. */
6745 unsigned int width = GET_MODE_BITSIZE (mode);
6746 unsigned HOST_WIDE_INT smask = mask;
6748 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6749 number, sign extend it. */
6751 if (width < HOST_BITS_PER_WIDE_INT
6752 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6753 smask |= (HOST_WIDE_INT) -1 << width;
6755 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6756 && exact_log2 (- smask) >= 0
6757 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6758 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6759 return force_to_mode (plus_constant (XEXP (x, 0),
6760 (INTVAL (XEXP (x, 1)) & smask)),
6761 mode, smask, reg, next_select);
6764 /* ... fall through ... */
6767 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6768 most significant bit in MASK since carries from those bits will
6769 affect the bits we are interested in. */
6774 /* If X is (minus C Y) where C's least set bit is larger than any bit
6775 in the mask, then we may replace with (neg Y). */
6776 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6777 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6778 & -INTVAL (XEXP (x, 0))))
6781 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6783 return force_to_mode (x, mode, mask, reg, next_select);
6786 /* Similarly, if C contains every bit in the mask, then we may
6787 replace with (not Y). */
6788 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6789 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6790 == INTVAL (XEXP (x, 0))))
6792 x = simplify_gen_unary (NOT, GET_MODE (x),
6793 XEXP (x, 1), GET_MODE (x));
6794 return force_to_mode (x, mode, mask, reg, next_select);
6802 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6803 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6804 operation which may be a bitfield extraction. Ensure that the
6805 constant we form is not wider than the mode of X. */
6807 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6808 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6809 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6810 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6811 && GET_CODE (XEXP (x, 1)) == CONST_INT
6812 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6813 + floor_log2 (INTVAL (XEXP (x, 1))))
6814 < GET_MODE_BITSIZE (GET_MODE (x)))
6815 && (INTVAL (XEXP (x, 1))
6816 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6818 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6819 << INTVAL (XEXP (XEXP (x, 0), 1)));
6820 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6821 XEXP (XEXP (x, 0), 0), temp);
6822 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6823 XEXP (XEXP (x, 0), 1));
6824 return force_to_mode (x, mode, mask, reg, next_select);
6828 /* For most binary operations, just propagate into the operation and
6829 change the mode if we have an operation of that mode. */
6831 op0 = gen_lowpart_for_combine (op_mode,
6832 force_to_mode (XEXP (x, 0), mode, mask,
6834 op1 = gen_lowpart_for_combine (op_mode,
6835 force_to_mode (XEXP (x, 1), mode, mask,
6838 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6839 MASK since OP1 might have been sign-extended but we never want
6840 to turn on extra bits, since combine might have previously relied
6841 on them being off. */
6842 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6843 && (INTVAL (op1) & mask) != 0)
6844 op1 = GEN_INT (INTVAL (op1) & mask);
6846 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6847 x = gen_binary (code, op_mode, op0, op1);
6851 /* For left shifts, do the same, but just for the first operand.
6852 However, we cannot do anything with shifts where we cannot
6853 guarantee that the counts are smaller than the size of the mode
6854 because such a count will have a different meaning in a
6857 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6858 && INTVAL (XEXP (x, 1)) >= 0
6859 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6860 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6861 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6862 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6865 /* If the shift count is a constant and we can do arithmetic in
6866 the mode of the shift, refine which bits we need. Otherwise, use the
6867 conservative form of the mask. */
6868 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6869 && INTVAL (XEXP (x, 1)) >= 0
6870 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6871 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6872 mask >>= INTVAL (XEXP (x, 1));
6876 op0 = gen_lowpart_for_combine (op_mode,
6877 force_to_mode (XEXP (x, 0), op_mode,
6878 mask, reg, next_select));
6880 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6881 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6885 /* Here we can only do something if the shift count is a constant,
6886 this shift constant is valid for the host, and we can do arithmetic
6889 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6890 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6891 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6893 rtx inner = XEXP (x, 0);
6894 unsigned HOST_WIDE_INT inner_mask;
6896 /* Select the mask of the bits we need for the shift operand. */
6897 inner_mask = mask << INTVAL (XEXP (x, 1));
6899 /* We can only change the mode of the shift if we can do arithmetic
6900 in the mode of the shift and INNER_MASK is no wider than the
6901 width of OP_MODE. */
6902 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6903 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6904 op_mode = GET_MODE (x);
6906 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6908 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6909 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6912 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6913 shift and AND produces only copies of the sign bit (C2 is one less
6914 than a power of two), we can do this with just a shift. */
6916 if (GET_CODE (x) == LSHIFTRT
6917 && GET_CODE (XEXP (x, 1)) == CONST_INT
6918 /* The shift puts one of the sign bit copies in the least significant
6920 && ((INTVAL (XEXP (x, 1))
6921 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6922 >= GET_MODE_BITSIZE (GET_MODE (x)))
6923 && exact_log2 (mask + 1) >= 0
6924 /* Number of bits left after the shift must be more than the mask
6926 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6927 <= GET_MODE_BITSIZE (GET_MODE (x)))
6928 /* Must be more sign bit copies than the mask needs. */
6929 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6930 >= exact_log2 (mask + 1)))
6931 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6932 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6933 - exact_log2 (mask + 1)));
6938 /* If we are just looking for the sign bit, we don't need this shift at
6939 all, even if it has a variable count. */
6940 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6941 && (mask == ((unsigned HOST_WIDE_INT) 1
6942 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6943 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6945 /* If this is a shift by a constant, get a mask that contains those bits
6946 that are not copies of the sign bit. We then have two cases: If
6947 MASK only includes those bits, this can be a logical shift, which may
6948 allow simplifications. If MASK is a single-bit field not within
6949 those bits, we are requesting a copy of the sign bit and hence can
6950 shift the sign bit to the appropriate location. */
6952 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6953 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6957 /* If the considered data is wider than HOST_WIDE_INT, we can't
6958 represent a mask for all its bits in a single scalar.
6959 But we only care about the lower bits, so calculate these. */
6961 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6963 nonzero = ~(HOST_WIDE_INT) 0;
6965 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6966 is the number of bits a full-width mask would have set.
6967 We need only shift if these are fewer than nonzero can
6968 hold. If not, we must keep all bits set in nonzero. */
6970 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6971 < HOST_BITS_PER_WIDE_INT)
6972 nonzero >>= INTVAL (XEXP (x, 1))
6973 + HOST_BITS_PER_WIDE_INT
6974 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6978 nonzero = GET_MODE_MASK (GET_MODE (x));
6979 nonzero >>= INTVAL (XEXP (x, 1));
6982 if ((mask & ~nonzero) == 0
6983 || (i = exact_log2 (mask)) >= 0)
6985 x = simplify_shift_const
6986 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6987 i < 0 ? INTVAL (XEXP (x, 1))
6988 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6990 if (GET_CODE (x) != ASHIFTRT)
6991 return force_to_mode (x, mode, mask, reg, next_select);
6995 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6996 even if the shift count isn't a constant. */
6998 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7002 /* If this is a zero- or sign-extension operation that just affects bits
7003 we don't care about, remove it. Be sure the call above returned
7004 something that is still a shift. */
7006 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7007 && GET_CODE (XEXP (x, 1)) == CONST_INT
7008 && INTVAL (XEXP (x, 1)) >= 0
7009 && (INTVAL (XEXP (x, 1))
7010 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7011 && GET_CODE (XEXP (x, 0)) == ASHIFT
7012 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7013 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7014 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7021 /* If the shift count is constant and we can do computations
7022 in the mode of X, compute where the bits we care about are.
7023 Otherwise, we can't do anything. Don't change the mode of
7024 the shift or propagate MODE into the shift, though. */
7025 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7026 && INTVAL (XEXP (x, 1)) >= 0)
7028 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7029 GET_MODE (x), GEN_INT (mask),
7031 if (temp && GET_CODE(temp) == CONST_INT)
7033 force_to_mode (XEXP (x, 0), GET_MODE (x),
7034 INTVAL (temp), reg, next_select));
7039 /* If we just want the low-order bit, the NEG isn't needed since it
7040 won't change the low-order bit. */
7042 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7044 /* We need any bits less significant than the most significant bit in
7045 MASK since carries from those bits will affect the bits we are
7051 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7052 same as the XOR case above. Ensure that the constant we form is not
7053 wider than the mode of X. */
7055 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7056 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7057 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7058 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7059 < GET_MODE_BITSIZE (GET_MODE (x)))
7060 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7062 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7063 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7064 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7066 return force_to_mode (x, mode, mask, reg, next_select);
7069 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7070 use the full mask inside the NOT. */
7074 op0 = gen_lowpart_for_combine (op_mode,
7075 force_to_mode (XEXP (x, 0), mode, mask,
7077 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7078 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7082 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7083 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7084 which is equal to STORE_FLAG_VALUE. */
7085 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7086 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7087 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7088 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7093 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7094 written in a narrower mode. We play it safe and do not do so. */
7097 gen_lowpart_for_combine (GET_MODE (x),
7098 force_to_mode (XEXP (x, 1), mode,
7099 mask, reg, next_select)));
7101 gen_lowpart_for_combine (GET_MODE (x),
7102 force_to_mode (XEXP (x, 2), mode,
7103 mask, reg,next_select)));
7110 /* Ensure we return a value of the proper mode. */
7111 return gen_lowpart_for_combine (mode, x);
7114 /* Return nonzero if X is an expression that has one of two values depending on
7115 whether some other value is zero or nonzero. In that case, we return the
7116 value that is being tested, *PTRUE is set to the value if the rtx being
7117 returned has a nonzero value, and *PFALSE is set to the other alternative.
7119 If we return zero, we set *PTRUE and *PFALSE to X. */
7122 if_then_else_cond (x, ptrue, pfalse)
7124 rtx *ptrue, *pfalse;
7126 enum machine_mode mode = GET_MODE (x);
7127 enum rtx_code code = GET_CODE (x);
7128 rtx cond0, cond1, true0, true1, false0, false1;
7129 unsigned HOST_WIDE_INT nz;
7131 /* If we are comparing a value against zero, we are done. */
7132 if ((code == NE || code == EQ)
7133 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7135 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7136 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7140 /* If this is a unary operation whose operand has one of two values, apply
7141 our opcode to compute those values. */
7142 else if (GET_RTX_CLASS (code) == '1'
7143 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7145 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7146 *pfalse = simplify_gen_unary (code, mode, false0,
7147 GET_MODE (XEXP (x, 0)));
7151 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7152 make can't possibly match and would suppress other optimizations. */
7153 else if (code == COMPARE)
7156 /* If this is a binary operation, see if either side has only one of two
7157 values. If either one does or if both do and they are conditional on
7158 the same value, compute the new true and false values. */
7159 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7160 || GET_RTX_CLASS (code) == '<')
7162 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7163 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7165 if ((cond0 != 0 || cond1 != 0)
7166 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7168 /* If if_then_else_cond returned zero, then true/false are the
7169 same rtl. We must copy one of them to prevent invalid rtl
7172 true0 = copy_rtx (true0);
7173 else if (cond1 == 0)
7174 true1 = copy_rtx (true1);
7176 *ptrue = gen_binary (code, mode, true0, true1);
7177 *pfalse = gen_binary (code, mode, false0, false1);
7178 return cond0 ? cond0 : cond1;
7181 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7182 operands is zero when the other is non-zero, and vice-versa,
7183 and STORE_FLAG_VALUE is 1 or -1. */
7185 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7186 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7188 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7190 rtx op0 = XEXP (XEXP (x, 0), 1);
7191 rtx op1 = XEXP (XEXP (x, 1), 1);
7193 cond0 = XEXP (XEXP (x, 0), 0);
7194 cond1 = XEXP (XEXP (x, 1), 0);
7196 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7197 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7198 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7199 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7200 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7201 || ((swap_condition (GET_CODE (cond0))
7202 == combine_reversed_comparison_code (cond1))
7203 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7204 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7205 && ! side_effects_p (x))
7207 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7208 *pfalse = gen_binary (MULT, mode,
7210 ? simplify_gen_unary (NEG, mode, op1,
7218 /* Similarly for MULT, AND and UMIN, except that for these the result
7220 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7221 && (code == MULT || code == AND || code == UMIN)
7222 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7224 cond0 = XEXP (XEXP (x, 0), 0);
7225 cond1 = XEXP (XEXP (x, 1), 0);
7227 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7228 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7229 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7230 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7231 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7232 || ((swap_condition (GET_CODE (cond0))
7233 == combine_reversed_comparison_code (cond1))
7234 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7235 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7236 && ! side_effects_p (x))
7238 *ptrue = *pfalse = const0_rtx;
7244 else if (code == IF_THEN_ELSE)
7246 /* If we have IF_THEN_ELSE already, extract the condition and
7247 canonicalize it if it is NE or EQ. */
7248 cond0 = XEXP (x, 0);
7249 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7250 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7251 return XEXP (cond0, 0);
7252 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7254 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7255 return XEXP (cond0, 0);
7261 /* If X is a SUBREG, we can narrow both the true and false values
7262 if the inner expression, if there is a condition. */
7263 else if (code == SUBREG
7264 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7267 *ptrue = simplify_gen_subreg (mode, true0,
7268 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7269 *pfalse = simplify_gen_subreg (mode, false0,
7270 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7275 /* If X is a constant, this isn't special and will cause confusions
7276 if we treat it as such. Likewise if it is equivalent to a constant. */
7277 else if (CONSTANT_P (x)
7278 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7281 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7282 will be least confusing to the rest of the compiler. */
7283 else if (mode == BImode)
7285 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7289 /* If X is known to be either 0 or -1, those are the true and
7290 false values when testing X. */
7291 else if (x == constm1_rtx || x == const0_rtx
7292 || (mode != VOIDmode
7293 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7295 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7299 /* Likewise for 0 or a single bit. */
7300 else if (mode != VOIDmode
7301 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7302 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7304 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7308 /* Otherwise fail; show no condition with true and false values the same. */
7309 *ptrue = *pfalse = x;
7313 /* Return the value of expression X given the fact that condition COND
7314 is known to be true when applied to REG as its first operand and VAL
7315 as its second. X is known to not be shared and so can be modified in
7318 We only handle the simplest cases, and specifically those cases that
7319 arise with IF_THEN_ELSE expressions. */
7322 known_cond (x, cond, reg, val)
7327 enum rtx_code code = GET_CODE (x);
7332 if (side_effects_p (x))
7335 /* If either operand of the condition is a floating point value,
7336 then we have to avoid collapsing an EQ comparison. */
7338 && rtx_equal_p (x, reg)
7339 && ! FLOAT_MODE_P (GET_MODE (x))
7340 && ! FLOAT_MODE_P (GET_MODE (val)))
7343 if (cond == UNEQ && rtx_equal_p (x, reg))
7346 /* If X is (abs REG) and we know something about REG's relationship
7347 with zero, we may be able to simplify this. */
7349 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7352 case GE: case GT: case EQ:
7355 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7357 GET_MODE (XEXP (x, 0)));
7362 /* The only other cases we handle are MIN, MAX, and comparisons if the
7363 operands are the same as REG and VAL. */
7365 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7367 if (rtx_equal_p (XEXP (x, 0), val))
7368 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7370 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7372 if (GET_RTX_CLASS (code) == '<')
7374 if (comparison_dominates_p (cond, code))
7375 return const_true_rtx;
7377 code = combine_reversed_comparison_code (x);
7379 && comparison_dominates_p (cond, code))
7384 else if (code == SMAX || code == SMIN
7385 || code == UMIN || code == UMAX)
7387 int unsignedp = (code == UMIN || code == UMAX);
7389 /* Do not reverse the condition when it is NE or EQ.
7390 This is because we cannot conclude anything about
7391 the value of 'SMAX (x, y)' when x is not equal to y,
7392 but we can when x equals y. */
7393 if ((code == SMAX || code == UMAX)
7394 && ! (cond == EQ || cond == NE))
7395 cond = reverse_condition (cond);
7400 return unsignedp ? x : XEXP (x, 1);
7402 return unsignedp ? x : XEXP (x, 0);
7404 return unsignedp ? XEXP (x, 1) : x;
7406 return unsignedp ? XEXP (x, 0) : x;
7414 fmt = GET_RTX_FORMAT (code);
7415 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7418 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7419 else if (fmt[i] == 'E')
7420 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7421 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7428 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7429 assignment as a field assignment. */
7432 rtx_equal_for_field_assignment_p (x, y)
7436 if (x == y || rtx_equal_p (x, y))
7439 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7442 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7443 Note that all SUBREGs of MEM are paradoxical; otherwise they
7444 would have been rewritten. */
7445 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7446 && GET_CODE (SUBREG_REG (y)) == MEM
7447 && rtx_equal_p (SUBREG_REG (y),
7448 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7451 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7452 && GET_CODE (SUBREG_REG (x)) == MEM
7453 && rtx_equal_p (SUBREG_REG (x),
7454 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7457 /* We used to see if get_last_value of X and Y were the same but that's
7458 not correct. In one direction, we'll cause the assignment to have
7459 the wrong destination and in the case, we'll import a register into this
7460 insn that might have already have been dead. So fail if none of the
7461 above cases are true. */
7465 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7466 Return that assignment if so.
7468 We only handle the most common cases. */
7471 make_field_assignment (x)
7474 rtx dest = SET_DEST (x);
7475 rtx src = SET_SRC (x);
7480 unsigned HOST_WIDE_INT len;
7482 enum machine_mode mode;
7484 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7485 a clear of a one-bit field. We will have changed it to
7486 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7489 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7490 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7491 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7492 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7494 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7497 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7501 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7502 && subreg_lowpart_p (XEXP (src, 0))
7503 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7504 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7505 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7506 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7507 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7509 assign = make_extraction (VOIDmode, dest, 0,
7510 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7513 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7517 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7519 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7520 && XEXP (XEXP (src, 0), 0) == const1_rtx
7521 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7523 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7526 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7530 /* The other case we handle is assignments into a constant-position
7531 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7532 a mask that has all one bits except for a group of zero bits and
7533 OTHER is known to have zeros where C1 has ones, this is such an
7534 assignment. Compute the position and length from C1. Shift OTHER
7535 to the appropriate position, force it to the required mode, and
7536 make the extraction. Check for the AND in both operands. */
7538 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7541 rhs = expand_compound_operation (XEXP (src, 0));
7542 lhs = expand_compound_operation (XEXP (src, 1));
7544 if (GET_CODE (rhs) == AND
7545 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7546 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7547 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7548 else if (GET_CODE (lhs) == AND
7549 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7550 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7551 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7555 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7556 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7557 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7558 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7561 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7565 /* The mode to use for the source is the mode of the assignment, or of
7566 what is inside a possible STRICT_LOW_PART. */
7567 mode = (GET_CODE (assign) == STRICT_LOW_PART
7568 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7570 /* Shift OTHER right POS places and make it the source, restricting it
7571 to the proper length and mode. */
7573 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7574 GET_MODE (src), other, pos),
7576 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7577 ? ~(unsigned HOST_WIDE_INT) 0
7578 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7581 return gen_rtx_SET (VOIDmode, assign, src);
7584 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7588 apply_distributive_law (x)
7591 enum rtx_code code = GET_CODE (x);
7592 rtx lhs, rhs, other;
7594 enum rtx_code inner_code;
7596 /* Distributivity is not true for floating point.
7597 It can change the value. So don't do it.
7598 -- rms and moshier@world.std.com. */
7599 if (FLOAT_MODE_P (GET_MODE (x)))
7602 /* The outer operation can only be one of the following: */
7603 if (code != IOR && code != AND && code != XOR
7604 && code != PLUS && code != MINUS)
7607 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7609 /* If either operand is a primitive we can't do anything, so get out
7611 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7612 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7615 lhs = expand_compound_operation (lhs);
7616 rhs = expand_compound_operation (rhs);
7617 inner_code = GET_CODE (lhs);
7618 if (inner_code != GET_CODE (rhs))
7621 /* See if the inner and outer operations distribute. */
7628 /* These all distribute except over PLUS. */
7629 if (code == PLUS || code == MINUS)
7634 if (code != PLUS && code != MINUS)
7639 /* This is also a multiply, so it distributes over everything. */
7643 /* Non-paradoxical SUBREGs distributes over all operations, provided
7644 the inner modes and byte offsets are the same, this is an extraction
7645 of a low-order part, we don't convert an fp operation to int or
7646 vice versa, and we would not be converting a single-word
7647 operation into a multi-word operation. The latter test is not
7648 required, but it prevents generating unneeded multi-word operations.
7649 Some of the previous tests are redundant given the latter test, but
7650 are retained because they are required for correctness.
7652 We produce the result slightly differently in this case. */
7654 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7655 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7656 || ! subreg_lowpart_p (lhs)
7657 || (GET_MODE_CLASS (GET_MODE (lhs))
7658 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7659 || (GET_MODE_SIZE (GET_MODE (lhs))
7660 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7661 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7664 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7665 SUBREG_REG (lhs), SUBREG_REG (rhs));
7666 return gen_lowpart_for_combine (GET_MODE (x), tem);
7672 /* Set LHS and RHS to the inner operands (A and B in the example
7673 above) and set OTHER to the common operand (C in the example).
7674 These is only one way to do this unless the inner operation is
7676 if (GET_RTX_CLASS (inner_code) == 'c'
7677 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7678 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7679 else if (GET_RTX_CLASS (inner_code) == 'c'
7680 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7681 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7682 else if (GET_RTX_CLASS (inner_code) == 'c'
7683 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7684 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7685 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7686 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7690 /* Form the new inner operation, seeing if it simplifies first. */
7691 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7693 /* There is one exception to the general way of distributing:
7694 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7695 if (code == XOR && inner_code == IOR)
7698 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7701 /* We may be able to continuing distributing the result, so call
7702 ourselves recursively on the inner operation before forming the
7703 outer operation, which we return. */
7704 return gen_binary (inner_code, GET_MODE (x),
7705 apply_distributive_law (tem), other);
7708 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7711 Return an equivalent form, if different from X. Otherwise, return X. If
7712 X is zero, we are to always construct the equivalent form. */
7715 simplify_and_const_int (x, mode, varop, constop)
7717 enum machine_mode mode;
7719 unsigned HOST_WIDE_INT constop;
7721 unsigned HOST_WIDE_INT nonzero;
7724 /* Simplify VAROP knowing that we will be only looking at some of the
7726 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7728 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7729 CONST_INT, we are done. */
7730 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7733 /* See what bits may be nonzero in VAROP. Unlike the general case of
7734 a call to nonzero_bits, here we don't care about bits outside
7737 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7739 /* Turn off all bits in the constant that are known to already be zero.
7740 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7741 which is tested below. */
7745 /* If we don't have any bits left, return zero. */
7749 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7750 a power of two, we can replace this with a ASHIFT. */
7751 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7752 && (i = exact_log2 (constop)) >= 0)
7753 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7755 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7756 or XOR, then try to apply the distributive law. This may eliminate
7757 operations if either branch can be simplified because of the AND.
7758 It may also make some cases more complex, but those cases probably
7759 won't match a pattern either with or without this. */
7761 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7763 gen_lowpart_for_combine
7765 apply_distributive_law
7766 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7767 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7768 XEXP (varop, 0), constop),
7769 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7770 XEXP (varop, 1), constop))));
7772 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7773 the AND and see if one of the operands simplifies to zero. If so, we
7774 may eliminate it. */
7776 if (GET_CODE (varop) == PLUS
7777 && exact_log2 (constop + 1) >= 0)
7781 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7782 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7783 if (o0 == const0_rtx)
7785 if (o1 == const0_rtx)
7789 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7790 if we already had one (just check for the simplest cases). */
7791 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7792 && GET_MODE (XEXP (x, 0)) == mode
7793 && SUBREG_REG (XEXP (x, 0)) == varop)
7794 varop = XEXP (x, 0);
7796 varop = gen_lowpart_for_combine (mode, varop);
7798 /* If we can't make the SUBREG, try to return what we were given. */
7799 if (GET_CODE (varop) == CLOBBER)
7800 return x ? x : varop;
7802 /* If we are only masking insignificant bits, return VAROP. */
7803 if (constop == nonzero)
7807 /* Otherwise, return an AND. */
7808 constop = trunc_int_for_mode (constop, mode);
7809 /* See how much, if any, of X we can use. */
7810 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7811 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7815 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7816 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7817 SUBST (XEXP (x, 1), GEN_INT (constop));
7819 SUBST (XEXP (x, 0), varop);
7826 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7827 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7828 is less useful. We can't allow both, because that results in exponential
7829 run time recursion. There is a nullstone testcase that triggered
7830 this. This macro avoids accidental uses of num_sign_bit_copies. */
7831 #define num_sign_bit_copies()
7833 /* Given an expression, X, compute which bits in X can be non-zero.
7834 We don't care about bits outside of those defined in MODE.
7836 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7837 a shift, AND, or zero_extract, we can do better. */
7839 static unsigned HOST_WIDE_INT
7840 nonzero_bits (x, mode)
7842 enum machine_mode mode;
7844 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7845 unsigned HOST_WIDE_INT inner_nz;
7847 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7850 /* For floating-point values, assume all bits are needed. */
7851 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7854 /* If X is wider than MODE, use its mode instead. */
7855 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7857 mode = GET_MODE (x);
7858 nonzero = GET_MODE_MASK (mode);
7859 mode_width = GET_MODE_BITSIZE (mode);
7862 if (mode_width > HOST_BITS_PER_WIDE_INT)
7863 /* Our only callers in this case look for single bit values. So
7864 just return the mode mask. Those tests will then be false. */
7867 #ifndef WORD_REGISTER_OPERATIONS
7868 /* If MODE is wider than X, but both are a single word for both the host
7869 and target machines, we can compute this from which bits of the
7870 object might be nonzero in its own mode, taking into account the fact
7871 that on many CISC machines, accessing an object in a wider mode
7872 causes the high-order bits to become undefined. So they are
7873 not known to be zero. */
7875 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7876 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7877 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7878 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7880 nonzero &= nonzero_bits (x, GET_MODE (x));
7881 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
7886 code = GET_CODE (x);
7890 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7891 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7892 all the bits above ptr_mode are known to be zero. */
7893 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7895 nonzero &= GET_MODE_MASK (ptr_mode);
7898 /* Include declared information about alignment of pointers. */
7900 if (REG_POINTER (x) && REGNO_POINTER_ALIGN (REGNO (x)))
7902 unsigned HOST_WIDE_INT alignment
7903 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
7905 #ifdef PUSH_ROUNDING
7906 /* If PUSH_ROUNDING is defined, it is possible for the
7907 stack to be momentarily aligned only to that amount,
7908 so we pick the least alignment. */
7909 if (x == stack_pointer_rtx && PUSH_ARGS)
7910 alignment = MIN (PUSH_ROUNDING (1), alignment);
7913 nonzero &= ~(alignment - 1);
7916 /* If X is a register whose nonzero bits value is current, use it.
7917 Otherwise, if X is a register whose value we can find, use that
7918 value. Otherwise, use the previously-computed global nonzero bits
7919 for this register. */
7921 if (reg_last_set_value[REGNO (x)] != 0
7922 && reg_last_set_mode[REGNO (x)] == mode
7923 && (reg_last_set_label[REGNO (x)] == label_tick
7924 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7925 && REG_N_SETS (REGNO (x)) == 1
7926 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7928 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7929 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
7931 tem = get_last_value (x);
7935 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7936 /* If X is narrower than MODE and TEM is a non-negative
7937 constant that would appear negative in the mode of X,
7938 sign-extend it for use in reg_nonzero_bits because some
7939 machines (maybe most) will actually do the sign-extension
7940 and this is the conservative approach.
7942 ??? For 2.5, try to tighten up the MD files in this regard
7943 instead of this kludge. */
7945 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7946 && GET_CODE (tem) == CONST_INT
7948 && 0 != (INTVAL (tem)
7949 & ((HOST_WIDE_INT) 1
7950 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7951 tem = GEN_INT (INTVAL (tem)
7952 | ((HOST_WIDE_INT) (-1)
7953 << GET_MODE_BITSIZE (GET_MODE (x))));
7955 return nonzero_bits (tem, mode) & nonzero;
7957 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7959 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
7961 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
7962 /* We don't know anything about the upper bits. */
7963 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
7964 return nonzero & mask;
7970 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7971 /* If X is negative in MODE, sign-extend the value. */
7972 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7973 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7974 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7980 #ifdef LOAD_EXTEND_OP
7981 /* In many, if not most, RISC machines, reading a byte from memory
7982 zeros the rest of the register. Noticing that fact saves a lot
7983 of extra zero-extends. */
7984 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7985 nonzero &= GET_MODE_MASK (GET_MODE (x));
7990 case UNEQ: case LTGT:
7991 case GT: case GTU: case UNGT:
7992 case LT: case LTU: case UNLT:
7993 case GE: case GEU: case UNGE:
7994 case LE: case LEU: case UNLE:
7995 case UNORDERED: case ORDERED:
7997 /* If this produces an integer result, we know which bits are set.
7998 Code here used to clear bits outside the mode of X, but that is
8001 if (GET_MODE_CLASS (mode) == MODE_INT
8002 && mode_width <= HOST_BITS_PER_WIDE_INT)
8003 nonzero = STORE_FLAG_VALUE;
8008 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8009 and num_sign_bit_copies. */
8010 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8011 == GET_MODE_BITSIZE (GET_MODE (x)))
8015 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8016 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8021 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8022 and num_sign_bit_copies. */
8023 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8024 == GET_MODE_BITSIZE (GET_MODE (x)))
8030 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8034 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8035 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8036 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8040 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8041 Otherwise, show all the bits in the outer mode but not the inner
8043 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8044 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8046 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8048 & (((HOST_WIDE_INT) 1
8049 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8050 inner_nz |= (GET_MODE_MASK (mode)
8051 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8054 nonzero &= inner_nz;
8058 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8059 & nonzero_bits (XEXP (x, 1), mode));
8063 case UMIN: case UMAX: case SMIN: case SMAX:
8064 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8065 | nonzero_bits (XEXP (x, 1), mode));
8068 case PLUS: case MINUS:
8070 case DIV: case UDIV:
8071 case MOD: case UMOD:
8072 /* We can apply the rules of arithmetic to compute the number of
8073 high- and low-order zero bits of these operations. We start by
8074 computing the width (position of the highest-order non-zero bit)
8075 and the number of low-order zero bits for each value. */
8077 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8078 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8079 int width0 = floor_log2 (nz0) + 1;
8080 int width1 = floor_log2 (nz1) + 1;
8081 int low0 = floor_log2 (nz0 & -nz0);
8082 int low1 = floor_log2 (nz1 & -nz1);
8083 HOST_WIDE_INT op0_maybe_minusp
8084 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8085 HOST_WIDE_INT op1_maybe_minusp
8086 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8087 unsigned int result_width = mode_width;
8093 result_width = MAX (width0, width1) + 1;
8094 result_low = MIN (low0, low1);
8097 result_low = MIN (low0, low1);
8100 result_width = width0 + width1;
8101 result_low = low0 + low1;
8106 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8107 result_width = width0;
8112 result_width = width0;
8117 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8118 result_width = MIN (width0, width1);
8119 result_low = MIN (low0, low1);
8124 result_width = MIN (width0, width1);
8125 result_low = MIN (low0, low1);
8131 if (result_width < mode_width)
8132 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8135 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8137 #ifdef POINTERS_EXTEND_UNSIGNED
8138 /* If pointers extend unsigned and this is an addition or subtraction
8139 to a pointer in Pmode, all the bits above ptr_mode are known to be
8141 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8142 && (code == PLUS || code == MINUS)
8143 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8144 nonzero &= GET_MODE_MASK (ptr_mode);
8150 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8151 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8152 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8156 /* If this is a SUBREG formed for a promoted variable that has
8157 been zero-extended, we know that at least the high-order bits
8158 are zero, though others might be too. */
8160 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8161 nonzero = (GET_MODE_MASK (GET_MODE (x))
8162 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8164 /* If the inner mode is a single word for both the host and target
8165 machines, we can compute this from which bits of the inner
8166 object might be nonzero. */
8167 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8168 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8169 <= HOST_BITS_PER_WIDE_INT))
8171 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8173 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8174 /* If this is a typical RISC machine, we only have to worry
8175 about the way loads are extended. */
8176 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8178 & (((unsigned HOST_WIDE_INT) 1
8179 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8181 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8184 /* On many CISC machines, accessing an object in a wider mode
8185 causes the high-order bits to become undefined. So they are
8186 not known to be zero. */
8187 if (GET_MODE_SIZE (GET_MODE (x))
8188 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8189 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8190 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8199 /* The nonzero bits are in two classes: any bits within MODE
8200 that aren't in GET_MODE (x) are always significant. The rest of the
8201 nonzero bits are those that are significant in the operand of
8202 the shift when shifted the appropriate number of bits. This
8203 shows that high-order bits are cleared by the right shift and
8204 low-order bits by left shifts. */
8205 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8206 && INTVAL (XEXP (x, 1)) >= 0
8207 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8209 enum machine_mode inner_mode = GET_MODE (x);
8210 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8211 int count = INTVAL (XEXP (x, 1));
8212 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8213 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8214 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8215 unsigned HOST_WIDE_INT outer = 0;
8217 if (mode_width > width)
8218 outer = (op_nonzero & nonzero & ~mode_mask);
8220 if (code == LSHIFTRT)
8222 else if (code == ASHIFTRT)
8226 /* If the sign bit may have been nonzero before the shift, we
8227 need to mark all the places it could have been copied to
8228 by the shift as possibly nonzero. */
8229 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8230 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8232 else if (code == ASHIFT)
8235 inner = ((inner << (count % width)
8236 | (inner >> (width - (count % width)))) & mode_mask);
8238 nonzero &= (outer | inner);
8243 /* This is at most the number of bits in the mode. */
8244 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8248 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8249 | nonzero_bits (XEXP (x, 2), mode));
8259 /* See the macro definition above. */
8260 #undef num_sign_bit_copies
8262 /* Return the number of bits at the high-order end of X that are known to
8263 be equal to the sign bit. X will be used in mode MODE; if MODE is
8264 VOIDmode, X will be used in its own mode. The returned value will always
8265 be between 1 and the number of bits in MODE. */
8268 num_sign_bit_copies (x, mode)
8270 enum machine_mode mode;
8272 enum rtx_code code = GET_CODE (x);
8273 unsigned int bitwidth;
8274 int num0, num1, result;
8275 unsigned HOST_WIDE_INT nonzero;
8278 /* If we weren't given a mode, use the mode of X. If the mode is still
8279 VOIDmode, we don't know anything. Likewise if one of the modes is
8282 if (mode == VOIDmode)
8283 mode = GET_MODE (x);
8285 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8288 bitwidth = GET_MODE_BITSIZE (mode);
8290 /* For a smaller object, just ignore the high bits. */
8291 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8293 num0 = num_sign_bit_copies (x, GET_MODE (x));
8295 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8298 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8300 #ifndef WORD_REGISTER_OPERATIONS
8301 /* If this machine does not do all register operations on the entire
8302 register and MODE is wider than the mode of X, we can say nothing
8303 at all about the high-order bits. */
8306 /* Likewise on machines that do, if the mode of the object is smaller
8307 than a word and loads of that size don't sign extend, we can say
8308 nothing about the high order bits. */
8309 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8310 #ifdef LOAD_EXTEND_OP
8311 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8322 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8323 /* If pointers extend signed and this is a pointer in Pmode, say that
8324 all the bits above ptr_mode are known to be sign bit copies. */
8325 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8327 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8330 if (reg_last_set_value[REGNO (x)] != 0
8331 && reg_last_set_mode[REGNO (x)] == mode
8332 && (reg_last_set_label[REGNO (x)] == label_tick
8333 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8334 && REG_N_SETS (REGNO (x)) == 1
8335 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8337 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8338 return reg_last_set_sign_bit_copies[REGNO (x)];
8340 tem = get_last_value (x);
8342 return num_sign_bit_copies (tem, mode);
8344 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8345 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8346 return reg_sign_bit_copies[REGNO (x)];
8350 #ifdef LOAD_EXTEND_OP
8351 /* Some RISC machines sign-extend all loads of smaller than a word. */
8352 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8353 return MAX (1, ((int) bitwidth
8354 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8359 /* If the constant is negative, take its 1's complement and remask.
8360 Then see how many zero bits we have. */
8361 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8362 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8363 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8364 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8366 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8369 /* If this is a SUBREG for a promoted object that is sign-extended
8370 and we are looking at it in a wider mode, we know that at least the
8371 high-order bits are known to be sign bit copies. */
8373 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8375 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8376 return MAX ((int) bitwidth
8377 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8381 /* For a smaller object, just ignore the high bits. */
8382 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8384 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8385 return MAX (1, (num0
8386 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8390 #ifdef WORD_REGISTER_OPERATIONS
8391 #ifdef LOAD_EXTEND_OP
8392 /* For paradoxical SUBREGs on machines where all register operations
8393 affect the entire register, just look inside. Note that we are
8394 passing MODE to the recursive call, so the number of sign bit copies
8395 will remain relative to that mode, not the inner mode. */
8397 /* This works only if loads sign extend. Otherwise, if we get a
8398 reload for the inner part, it may be loaded from the stack, and
8399 then we lose all sign bit copies that existed before the store
8402 if ((GET_MODE_SIZE (GET_MODE (x))
8403 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8404 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8405 return num_sign_bit_copies (SUBREG_REG (x), mode);
8411 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8412 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8416 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8417 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8420 /* For a smaller object, just ignore the high bits. */
8421 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8422 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8426 return num_sign_bit_copies (XEXP (x, 0), mode);
8428 case ROTATE: case ROTATERT:
8429 /* If we are rotating left by a number of bits less than the number
8430 of sign bit copies, we can just subtract that amount from the
8432 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8433 && INTVAL (XEXP (x, 1)) >= 0
8434 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8436 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8437 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8438 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8443 /* In general, this subtracts one sign bit copy. But if the value
8444 is known to be positive, the number of sign bit copies is the
8445 same as that of the input. Finally, if the input has just one bit
8446 that might be nonzero, all the bits are copies of the sign bit. */
8447 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8448 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8449 return num0 > 1 ? num0 - 1 : 1;
8451 nonzero = nonzero_bits (XEXP (x, 0), mode);
8456 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8461 case IOR: case AND: case XOR:
8462 case SMIN: case SMAX: case UMIN: case UMAX:
8463 /* Logical operations will preserve the number of sign-bit copies.
8464 MIN and MAX operations always return one of the operands. */
8465 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8466 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8467 return MIN (num0, num1);
8469 case PLUS: case MINUS:
8470 /* For addition and subtraction, we can have a 1-bit carry. However,
8471 if we are subtracting 1 from a positive number, there will not
8472 be such a carry. Furthermore, if the positive number is known to
8473 be 0 or 1, we know the result is either -1 or 0. */
8475 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8476 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8478 nonzero = nonzero_bits (XEXP (x, 0), mode);
8479 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8480 return (nonzero == 1 || nonzero == 0 ? bitwidth
8481 : bitwidth - floor_log2 (nonzero) - 1);
8484 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8485 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8486 result = MAX (1, MIN (num0, num1) - 1);
8488 #ifdef POINTERS_EXTEND_UNSIGNED
8489 /* If pointers extend signed and this is an addition or subtraction
8490 to a pointer in Pmode, all the bits above ptr_mode are known to be
8492 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8493 && (code == PLUS || code == MINUS)
8494 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8495 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8496 - GET_MODE_BITSIZE (ptr_mode) + 1),
8502 /* The number of bits of the product is the sum of the number of
8503 bits of both terms. However, unless one of the terms if known
8504 to be positive, we must allow for an additional bit since negating
8505 a negative number can remove one sign bit copy. */
8507 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8508 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8510 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8512 && (bitwidth > HOST_BITS_PER_WIDE_INT
8513 || (((nonzero_bits (XEXP (x, 0), mode)
8514 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8515 && ((nonzero_bits (XEXP (x, 1), mode)
8516 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8519 return MAX (1, result);
8522 /* The result must be <= the first operand. If the first operand
8523 has the high bit set, we know nothing about the number of sign
8525 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8527 else if ((nonzero_bits (XEXP (x, 0), mode)
8528 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8531 return num_sign_bit_copies (XEXP (x, 0), mode);
8534 /* The result must be <= the second operand. */
8535 return num_sign_bit_copies (XEXP (x, 1), mode);
8538 /* Similar to unsigned division, except that we have to worry about
8539 the case where the divisor is negative, in which case we have
8541 result = num_sign_bit_copies (XEXP (x, 0), mode);
8543 && (bitwidth > HOST_BITS_PER_WIDE_INT
8544 || (nonzero_bits (XEXP (x, 1), mode)
8545 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8551 result = num_sign_bit_copies (XEXP (x, 1), mode);
8553 && (bitwidth > HOST_BITS_PER_WIDE_INT
8554 || (nonzero_bits (XEXP (x, 1), mode)
8555 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8561 /* Shifts by a constant add to the number of bits equal to the
8563 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8564 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8565 && INTVAL (XEXP (x, 1)) > 0)
8566 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8571 /* Left shifts destroy copies. */
8572 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8573 || INTVAL (XEXP (x, 1)) < 0
8574 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8577 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8578 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8581 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8582 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8583 return MIN (num0, num1);
8585 case EQ: case NE: case GE: case GT: case LE: case LT:
8586 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8587 case GEU: case GTU: case LEU: case LTU:
8588 case UNORDERED: case ORDERED:
8589 /* If the constant is negative, take its 1's complement and remask.
8590 Then see how many zero bits we have. */
8591 nonzero = STORE_FLAG_VALUE;
8592 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8593 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8594 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8596 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8603 /* If we haven't been able to figure it out by one of the above rules,
8604 see if some of the high-order bits are known to be zero. If so,
8605 count those bits and return one less than that amount. If we can't
8606 safely compute the mask for this mode, always return BITWIDTH. */
8608 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8611 nonzero = nonzero_bits (x, mode);
8612 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8613 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8616 /* Return the number of "extended" bits there are in X, when interpreted
8617 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8618 unsigned quantities, this is the number of high-order zero bits.
8619 For signed quantities, this is the number of copies of the sign bit
8620 minus 1. In both case, this function returns the number of "spare"
8621 bits. For example, if two quantities for which this function returns
8622 at least 1 are added, the addition is known not to overflow.
8624 This function will always return 0 unless called during combine, which
8625 implies that it must be called from a define_split. */
8628 extended_count (x, mode, unsignedp)
8630 enum machine_mode mode;
8633 if (nonzero_sign_valid == 0)
8637 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8638 ? (GET_MODE_BITSIZE (mode) - 1
8639 - floor_log2 (nonzero_bits (x, mode)))
8641 : num_sign_bit_copies (x, mode) - 1);
8644 /* This function is called from `simplify_shift_const' to merge two
8645 outer operations. Specifically, we have already found that we need
8646 to perform operation *POP0 with constant *PCONST0 at the outermost
8647 position. We would now like to also perform OP1 with constant CONST1
8648 (with *POP0 being done last).
8650 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8651 the resulting operation. *PCOMP_P is set to 1 if we would need to
8652 complement the innermost operand, otherwise it is unchanged.
8654 MODE is the mode in which the operation will be done. No bits outside
8655 the width of this mode matter. It is assumed that the width of this mode
8656 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8658 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8659 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8660 result is simply *PCONST0.
8662 If the resulting operation cannot be expressed as one operation, we
8663 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8666 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8667 enum rtx_code *pop0;
8668 HOST_WIDE_INT *pconst0;
8670 HOST_WIDE_INT const1;
8671 enum machine_mode mode;
8674 enum rtx_code op0 = *pop0;
8675 HOST_WIDE_INT const0 = *pconst0;
8677 const0 &= GET_MODE_MASK (mode);
8678 const1 &= GET_MODE_MASK (mode);
8680 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8684 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8687 if (op1 == NIL || op0 == SET)
8690 else if (op0 == NIL)
8691 op0 = op1, const0 = const1;
8693 else if (op0 == op1)
8717 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8718 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8721 /* If the two constants aren't the same, we can't do anything. The
8722 remaining six cases can all be done. */
8723 else if (const0 != const1)
8731 /* (a & b) | b == b */
8733 else /* op1 == XOR */
8734 /* (a ^ b) | b == a | b */
8740 /* (a & b) ^ b == (~a) & b */
8741 op0 = AND, *pcomp_p = 1;
8742 else /* op1 == IOR */
8743 /* (a | b) ^ b == a & ~b */
8744 op0 = AND, *pconst0 = ~const0;
8749 /* (a | b) & b == b */
8751 else /* op1 == XOR */
8752 /* (a ^ b) & b) == (~a) & b */
8759 /* Check for NO-OP cases. */
8760 const0 &= GET_MODE_MASK (mode);
8762 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8764 else if (const0 == 0 && op0 == AND)
8766 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8770 /* ??? Slightly redundant with the above mask, but not entirely.
8771 Moving this above means we'd have to sign-extend the mode mask
8772 for the final test. */
8773 const0 = trunc_int_for_mode (const0, mode);
8781 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8782 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8783 that we started with.
8785 The shift is normally computed in the widest mode we find in VAROP, as
8786 long as it isn't a different number of words than RESULT_MODE. Exceptions
8787 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8790 simplify_shift_const (x, code, result_mode, varop, orig_count)
8793 enum machine_mode result_mode;
8797 enum rtx_code orig_code = code;
8800 enum machine_mode mode = result_mode;
8801 enum machine_mode shift_mode, tmode;
8802 unsigned int mode_words
8803 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8804 /* We form (outer_op (code varop count) (outer_const)). */
8805 enum rtx_code outer_op = NIL;
8806 HOST_WIDE_INT outer_const = 0;
8808 int complement_p = 0;
8811 /* Make sure and truncate the "natural" shift on the way in. We don't
8812 want to do this inside the loop as it makes it more difficult to
8814 #ifdef SHIFT_COUNT_TRUNCATED
8815 if (SHIFT_COUNT_TRUNCATED)
8816 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8819 /* If we were given an invalid count, don't do anything except exactly
8820 what was requested. */
8822 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8827 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8832 /* Unless one of the branches of the `if' in this loop does a `continue',
8833 we will `break' the loop after the `if'. */
8837 /* If we have an operand of (clobber (const_int 0)), just return that
8839 if (GET_CODE (varop) == CLOBBER)
8842 /* If we discovered we had to complement VAROP, leave. Making a NOT
8843 here would cause an infinite loop. */
8847 /* Convert ROTATERT to ROTATE. */
8848 if (code == ROTATERT)
8849 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8851 /* We need to determine what mode we will do the shift in. If the
8852 shift is a right shift or a ROTATE, we must always do it in the mode
8853 it was originally done in. Otherwise, we can do it in MODE, the
8854 widest mode encountered. */
8856 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8857 ? result_mode : mode);
8859 /* Handle cases where the count is greater than the size of the mode
8860 minus 1. For ASHIFT, use the size minus one as the count (this can
8861 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8862 take the count modulo the size. For other shifts, the result is
8865 Since these shifts are being produced by the compiler by combining
8866 multiple operations, each of which are defined, we know what the
8867 result is supposed to be. */
8869 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8871 if (code == ASHIFTRT)
8872 count = GET_MODE_BITSIZE (shift_mode) - 1;
8873 else if (code == ROTATE || code == ROTATERT)
8874 count %= GET_MODE_BITSIZE (shift_mode);
8877 /* We can't simply return zero because there may be an
8885 /* An arithmetic right shift of a quantity known to be -1 or 0
8887 if (code == ASHIFTRT
8888 && (num_sign_bit_copies (varop, shift_mode)
8889 == GET_MODE_BITSIZE (shift_mode)))
8895 /* If we are doing an arithmetic right shift and discarding all but
8896 the sign bit copies, this is equivalent to doing a shift by the
8897 bitsize minus one. Convert it into that shift because it will often
8898 allow other simplifications. */
8900 if (code == ASHIFTRT
8901 && (count + num_sign_bit_copies (varop, shift_mode)
8902 >= GET_MODE_BITSIZE (shift_mode)))
8903 count = GET_MODE_BITSIZE (shift_mode) - 1;
8905 /* We simplify the tests below and elsewhere by converting
8906 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8907 `make_compound_operation' will convert it to a ASHIFTRT for
8908 those machines (such as VAX) that don't have a LSHIFTRT. */
8909 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8911 && ((nonzero_bits (varop, shift_mode)
8912 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8916 switch (GET_CODE (varop))
8922 new = expand_compound_operation (varop);
8931 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8932 minus the width of a smaller mode, we can do this with a
8933 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8934 if ((code == ASHIFTRT || code == LSHIFTRT)
8935 && ! mode_dependent_address_p (XEXP (varop, 0))
8936 && ! MEM_VOLATILE_P (varop)
8937 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8938 MODE_INT, 1)) != BLKmode)
8940 new = adjust_address_nv (varop, tmode,
8941 BYTES_BIG_ENDIAN ? 0
8942 : count / BITS_PER_UNIT);
8944 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8945 : ZERO_EXTEND, mode, new);
8952 /* Similar to the case above, except that we can only do this if
8953 the resulting mode is the same as that of the underlying
8954 MEM and adjust the address depending on the *bits* endianness
8955 because of the way that bit-field extract insns are defined. */
8956 if ((code == ASHIFTRT || code == LSHIFTRT)
8957 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8958 MODE_INT, 1)) != BLKmode
8959 && tmode == GET_MODE (XEXP (varop, 0)))
8961 if (BITS_BIG_ENDIAN)
8962 new = XEXP (varop, 0);
8965 new = copy_rtx (XEXP (varop, 0));
8966 SUBST (XEXP (new, 0),
8967 plus_constant (XEXP (new, 0),
8968 count / BITS_PER_UNIT));
8971 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8972 : ZERO_EXTEND, mode, new);
8979 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8980 the same number of words as what we've seen so far. Then store
8981 the widest mode in MODE. */
8982 if (subreg_lowpart_p (varop)
8983 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8984 > GET_MODE_SIZE (GET_MODE (varop)))
8985 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8986 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8989 varop = SUBREG_REG (varop);
8990 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8991 mode = GET_MODE (varop);
8997 /* Some machines use MULT instead of ASHIFT because MULT
8998 is cheaper. But it is still better on those machines to
8999 merge two shifts into one. */
9000 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9001 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9004 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9005 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9011 /* Similar, for when divides are cheaper. */
9012 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9013 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9016 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9017 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9023 /* If we are extracting just the sign bit of an arithmetic
9024 right shift, that shift is not needed. However, the sign
9025 bit of a wider mode may be different from what would be
9026 interpreted as the sign bit in a narrower mode, so, if
9027 the result is narrower, don't discard the shift. */
9028 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9029 && (GET_MODE_BITSIZE (result_mode)
9030 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9032 varop = XEXP (varop, 0);
9036 /* ... fall through ... */
9041 /* Here we have two nested shifts. The result is usually the
9042 AND of a new shift with a mask. We compute the result below. */
9043 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9044 && INTVAL (XEXP (varop, 1)) >= 0
9045 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9046 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9047 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9049 enum rtx_code first_code = GET_CODE (varop);
9050 unsigned int first_count = INTVAL (XEXP (varop, 1));
9051 unsigned HOST_WIDE_INT mask;
9054 /* We have one common special case. We can't do any merging if
9055 the inner code is an ASHIFTRT of a smaller mode. However, if
9056 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9057 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9058 we can convert it to
9059 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9060 This simplifies certain SIGN_EXTEND operations. */
9061 if (code == ASHIFT && first_code == ASHIFTRT
9062 && (GET_MODE_BITSIZE (result_mode)
9063 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9065 /* C3 has the low-order C1 bits zero. */
9067 mask = (GET_MODE_MASK (mode)
9068 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9070 varop = simplify_and_const_int (NULL_RTX, result_mode,
9071 XEXP (varop, 0), mask);
9072 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9074 count = first_count;
9079 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9080 than C1 high-order bits equal to the sign bit, we can convert
9081 this to either an ASHIFT or a ASHIFTRT depending on the
9084 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9086 if (code == ASHIFTRT && first_code == ASHIFT
9087 && GET_MODE (varop) == shift_mode
9088 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9091 varop = XEXP (varop, 0);
9093 signed_count = count - first_count;
9094 if (signed_count < 0)
9095 count = -signed_count, code = ASHIFT;
9097 count = signed_count;
9102 /* There are some cases we can't do. If CODE is ASHIFTRT,
9103 we can only do this if FIRST_CODE is also ASHIFTRT.
9105 We can't do the case when CODE is ROTATE and FIRST_CODE is
9108 If the mode of this shift is not the mode of the outer shift,
9109 we can't do this if either shift is a right shift or ROTATE.
9111 Finally, we can't do any of these if the mode is too wide
9112 unless the codes are the same.
9114 Handle the case where the shift codes are the same
9117 if (code == first_code)
9119 if (GET_MODE (varop) != result_mode
9120 && (code == ASHIFTRT || code == LSHIFTRT
9124 count += first_count;
9125 varop = XEXP (varop, 0);
9129 if (code == ASHIFTRT
9130 || (code == ROTATE && first_code == ASHIFTRT)
9131 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9132 || (GET_MODE (varop) != result_mode
9133 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9134 || first_code == ROTATE
9135 || code == ROTATE)))
9138 /* To compute the mask to apply after the shift, shift the
9139 nonzero bits of the inner shift the same way the
9140 outer shift will. */
9142 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9145 = simplify_binary_operation (code, result_mode, mask_rtx,
9148 /* Give up if we can't compute an outer operation to use. */
9150 || GET_CODE (mask_rtx) != CONST_INT
9151 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9153 result_mode, &complement_p))
9156 /* If the shifts are in the same direction, we add the
9157 counts. Otherwise, we subtract them. */
9158 signed_count = count;
9159 if ((code == ASHIFTRT || code == LSHIFTRT)
9160 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9161 signed_count += first_count;
9163 signed_count -= first_count;
9165 /* If COUNT is positive, the new shift is usually CODE,
9166 except for the two exceptions below, in which case it is
9167 FIRST_CODE. If the count is negative, FIRST_CODE should
9169 if (signed_count > 0
9170 && ((first_code == ROTATE && code == ASHIFT)
9171 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9172 code = first_code, count = signed_count;
9173 else if (signed_count < 0)
9174 code = first_code, count = -signed_count;
9176 count = signed_count;
9178 varop = XEXP (varop, 0);
9182 /* If we have (A << B << C) for any shift, we can convert this to
9183 (A << C << B). This wins if A is a constant. Only try this if
9184 B is not a constant. */
9186 else if (GET_CODE (varop) == code
9187 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9189 = simplify_binary_operation (code, mode,
9193 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9200 /* Make this fit the case below. */
9201 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9202 GEN_INT (GET_MODE_MASK (mode)));
9208 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9209 with C the size of VAROP - 1 and the shift is logical if
9210 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9211 we have an (le X 0) operation. If we have an arithmetic shift
9212 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9213 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9215 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9216 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9217 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9218 && (code == LSHIFTRT || code == ASHIFTRT)
9219 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9220 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9223 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9226 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9227 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9232 /* If we have (shift (logical)), move the logical to the outside
9233 to allow it to possibly combine with another logical and the
9234 shift to combine with another shift. This also canonicalizes to
9235 what a ZERO_EXTRACT looks like. Also, some machines have
9236 (and (shift)) insns. */
9238 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9239 && (new = simplify_binary_operation (code, result_mode,
9241 GEN_INT (count))) != 0
9242 && GET_CODE (new) == CONST_INT
9243 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9244 INTVAL (new), result_mode, &complement_p))
9246 varop = XEXP (varop, 0);
9250 /* If we can't do that, try to simplify the shift in each arm of the
9251 logical expression, make a new logical expression, and apply
9252 the inverse distributive law. */
9254 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9255 XEXP (varop, 0), count);
9256 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9257 XEXP (varop, 1), count);
9259 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9260 varop = apply_distributive_law (varop);
9267 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9268 says that the sign bit can be tested, FOO has mode MODE, C is
9269 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9270 that may be nonzero. */
9271 if (code == LSHIFTRT
9272 && XEXP (varop, 1) == const0_rtx
9273 && GET_MODE (XEXP (varop, 0)) == result_mode
9274 && count == GET_MODE_BITSIZE (result_mode) - 1
9275 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9276 && ((STORE_FLAG_VALUE
9277 & ((HOST_WIDE_INT) 1
9278 < (GET_MODE_BITSIZE (result_mode) - 1))))
9279 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9280 && merge_outer_ops (&outer_op, &outer_const, XOR,
9281 (HOST_WIDE_INT) 1, result_mode,
9284 varop = XEXP (varop, 0);
9291 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9292 than the number of bits in the mode is equivalent to A. */
9293 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9294 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9296 varop = XEXP (varop, 0);
9301 /* NEG commutes with ASHIFT since it is multiplication. Move the
9302 NEG outside to allow shifts to combine. */
9304 && merge_outer_ops (&outer_op, &outer_const, NEG,
9305 (HOST_WIDE_INT) 0, result_mode,
9308 varop = XEXP (varop, 0);
9314 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9315 is one less than the number of bits in the mode is
9316 equivalent to (xor A 1). */
9317 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9318 && XEXP (varop, 1) == constm1_rtx
9319 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9320 && merge_outer_ops (&outer_op, &outer_const, XOR,
9321 (HOST_WIDE_INT) 1, result_mode,
9325 varop = XEXP (varop, 0);
9329 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9330 that might be nonzero in BAR are those being shifted out and those
9331 bits are known zero in FOO, we can replace the PLUS with FOO.
9332 Similarly in the other operand order. This code occurs when
9333 we are computing the size of a variable-size array. */
9335 if ((code == ASHIFTRT || code == LSHIFTRT)
9336 && count < HOST_BITS_PER_WIDE_INT
9337 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9338 && (nonzero_bits (XEXP (varop, 1), result_mode)
9339 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9341 varop = XEXP (varop, 0);
9344 else if ((code == ASHIFTRT || code == LSHIFTRT)
9345 && count < HOST_BITS_PER_WIDE_INT
9346 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9347 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9349 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9350 & nonzero_bits (XEXP (varop, 1),
9353 varop = XEXP (varop, 1);
9357 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9359 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9360 && (new = simplify_binary_operation (ASHIFT, result_mode,
9362 GEN_INT (count))) != 0
9363 && GET_CODE (new) == CONST_INT
9364 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9365 INTVAL (new), result_mode, &complement_p))
9367 varop = XEXP (varop, 0);
9373 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9374 with C the size of VAROP - 1 and the shift is logical if
9375 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9376 we have a (gt X 0) operation. If the shift is arithmetic with
9377 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9378 we have a (neg (gt X 0)) operation. */
9380 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9381 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9382 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9383 && (code == LSHIFTRT || code == ASHIFTRT)
9384 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9385 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9386 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9389 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9392 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9393 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9400 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9401 if the truncate does not affect the value. */
9402 if (code == LSHIFTRT
9403 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9404 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9405 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9406 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9407 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9409 rtx varop_inner = XEXP (varop, 0);
9412 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9413 XEXP (varop_inner, 0),
9415 (count + INTVAL (XEXP (varop_inner, 1))));
9416 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9429 /* We need to determine what mode to do the shift in. If the shift is
9430 a right shift or ROTATE, we must always do it in the mode it was
9431 originally done in. Otherwise, we can do it in MODE, the widest mode
9432 encountered. The code we care about is that of the shift that will
9433 actually be done, not the shift that was originally requested. */
9435 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9436 ? result_mode : mode);
9438 /* We have now finished analyzing the shift. The result should be
9439 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9440 OUTER_OP is non-NIL, it is an operation that needs to be applied
9441 to the result of the shift. OUTER_CONST is the relevant constant,
9442 but we must turn off all bits turned off in the shift.
9444 If we were passed a value for X, see if we can use any pieces of
9445 it. If not, make new rtx. */
9447 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9448 && GET_CODE (XEXP (x, 1)) == CONST_INT
9449 && INTVAL (XEXP (x, 1)) == count)
9450 const_rtx = XEXP (x, 1);
9452 const_rtx = GEN_INT (count);
9454 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9455 && GET_MODE (XEXP (x, 0)) == shift_mode
9456 && SUBREG_REG (XEXP (x, 0)) == varop)
9457 varop = XEXP (x, 0);
9458 else if (GET_MODE (varop) != shift_mode)
9459 varop = gen_lowpart_for_combine (shift_mode, varop);
9461 /* If we can't make the SUBREG, try to return what we were given. */
9462 if (GET_CODE (varop) == CLOBBER)
9463 return x ? x : varop;
9465 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9469 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9471 /* If we have an outer operation and we just made a shift, it is
9472 possible that we could have simplified the shift were it not
9473 for the outer operation. So try to do the simplification
9476 if (outer_op != NIL && GET_CODE (x) == code
9477 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9478 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9479 INTVAL (XEXP (x, 1)));
9481 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9482 turn off all the bits that the shift would have turned off. */
9483 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9484 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9485 GET_MODE_MASK (result_mode) >> orig_count);
9487 /* Do the remainder of the processing in RESULT_MODE. */
9488 x = gen_lowpart_for_combine (result_mode, x);
9490 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9493 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9495 if (outer_op != NIL)
9497 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9498 outer_const = trunc_int_for_mode (outer_const, result_mode);
9500 if (outer_op == AND)
9501 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9502 else if (outer_op == SET)
9503 /* This means that we have determined that the result is
9504 equivalent to a constant. This should be rare. */
9505 x = GEN_INT (outer_const);
9506 else if (GET_RTX_CLASS (outer_op) == '1')
9507 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9509 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9515 /* Like recog, but we receive the address of a pointer to a new pattern.
9516 We try to match the rtx that the pointer points to.
9517 If that fails, we may try to modify or replace the pattern,
9518 storing the replacement into the same pointer object.
9520 Modifications include deletion or addition of CLOBBERs.
9522 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9523 the CLOBBERs are placed.
9525 The value is the final insn code from the pattern ultimately matched,
9529 recog_for_combine (pnewpat, insn, pnotes)
9535 int insn_code_number;
9536 int num_clobbers_to_add = 0;
9541 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9542 we use to indicate that something didn't match. If we find such a
9543 thing, force rejection. */
9544 if (GET_CODE (pat) == PARALLEL)
9545 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9546 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9547 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9550 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9551 instruction for pattern recognition. */
9552 dummy_insn = shallow_copy_rtx (insn);
9553 PATTERN (dummy_insn) = pat;
9554 REG_NOTES (dummy_insn) = 0;
9556 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9558 /* If it isn't, there is the possibility that we previously had an insn
9559 that clobbered some register as a side effect, but the combined
9560 insn doesn't need to do that. So try once more without the clobbers
9561 unless this represents an ASM insn. */
9563 if (insn_code_number < 0 && ! check_asm_operands (pat)
9564 && GET_CODE (pat) == PARALLEL)
9568 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9569 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9572 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9576 SUBST_INT (XVECLEN (pat, 0), pos);
9579 pat = XVECEXP (pat, 0, 0);
9581 PATTERN (dummy_insn) = pat;
9582 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9585 /* Recognize all noop sets, these will be killed by followup pass. */
9586 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9587 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9589 /* If we had any clobbers to add, make a new pattern than contains
9590 them. Then check to make sure that all of them are dead. */
9591 if (num_clobbers_to_add)
9593 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9594 rtvec_alloc (GET_CODE (pat) == PARALLEL
9596 + num_clobbers_to_add)
9597 : num_clobbers_to_add + 1));
9599 if (GET_CODE (pat) == PARALLEL)
9600 for (i = 0; i < XVECLEN (pat, 0); i++)
9601 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9603 XVECEXP (newpat, 0, 0) = pat;
9605 add_clobbers (newpat, insn_code_number);
9607 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9608 i < XVECLEN (newpat, 0); i++)
9610 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9611 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9613 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9614 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9622 return insn_code_number;
9625 /* Like gen_lowpart but for use by combine. In combine it is not possible
9626 to create any new pseudoregs. However, it is safe to create
9627 invalid memory addresses, because combine will try to recognize
9628 them and all they will do is make the combine attempt fail.
9630 If for some reason this cannot do its job, an rtx
9631 (clobber (const_int 0)) is returned.
9632 An insn containing that will not be recognized. */
9637 gen_lowpart_for_combine (mode, x)
9638 enum machine_mode mode;
9643 if (GET_MODE (x) == mode)
9646 /* We can only support MODE being wider than a word if X is a
9647 constant integer or has a mode the same size. */
9649 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9650 && ! ((GET_MODE (x) == VOIDmode
9651 && (GET_CODE (x) == CONST_INT
9652 || GET_CODE (x) == CONST_DOUBLE))
9653 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9654 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9656 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9657 won't know what to do. So we will strip off the SUBREG here and
9658 process normally. */
9659 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9662 if (GET_MODE (x) == mode)
9666 result = gen_lowpart_common (mode, x);
9667 #ifdef CLASS_CANNOT_CHANGE_MODE
9669 && GET_CODE (result) == SUBREG
9670 && GET_CODE (SUBREG_REG (result)) == REG
9671 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9672 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9673 GET_MODE (SUBREG_REG (result))))
9674 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9680 if (GET_CODE (x) == MEM)
9684 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9686 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9687 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9689 /* If we want to refer to something bigger than the original memref,
9690 generate a perverse subreg instead. That will force a reload
9691 of the original memref X. */
9692 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9693 return gen_rtx_SUBREG (mode, x, 0);
9695 if (WORDS_BIG_ENDIAN)
9696 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9697 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9699 if (BYTES_BIG_ENDIAN)
9701 /* Adjust the address so that the address-after-the-data is
9703 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9704 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9707 return adjust_address_nv (x, mode, offset);
9710 /* If X is a comparison operator, rewrite it in a new mode. This
9711 probably won't match, but may allow further simplifications. */
9712 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9713 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9715 /* If we couldn't simplify X any other way, just enclose it in a
9716 SUBREG. Normally, this SUBREG won't match, but some patterns may
9717 include an explicit SUBREG or we may simplify it further in combine. */
9723 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9724 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9727 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9731 /* These routines make binary and unary operations by first seeing if they
9732 fold; if not, a new expression is allocated. */
9735 gen_binary (code, mode, op0, op1)
9737 enum machine_mode mode;
9743 if (GET_RTX_CLASS (code) == 'c'
9744 && swap_commutative_operands_p (op0, op1))
9745 tem = op0, op0 = op1, op1 = tem;
9747 if (GET_RTX_CLASS (code) == '<')
9749 enum machine_mode op_mode = GET_MODE (op0);
9751 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9752 just (REL_OP X Y). */
9753 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9755 op1 = XEXP (op0, 1);
9756 op0 = XEXP (op0, 0);
9757 op_mode = GET_MODE (op0);
9760 if (op_mode == VOIDmode)
9761 op_mode = GET_MODE (op1);
9762 result = simplify_relational_operation (code, op_mode, op0, op1);
9765 result = simplify_binary_operation (code, mode, op0, op1);
9770 /* Put complex operands first and constants second. */
9771 if (GET_RTX_CLASS (code) == 'c'
9772 && swap_commutative_operands_p (op0, op1))
9773 return gen_rtx_fmt_ee (code, mode, op1, op0);
9775 /* If we are turning off bits already known off in OP0, we need not do
9777 else if (code == AND && GET_CODE (op1) == CONST_INT
9778 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9779 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9782 return gen_rtx_fmt_ee (code, mode, op0, op1);
9785 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9786 comparison code that will be tested.
9788 The result is a possibly different comparison code to use. *POP0 and
9789 *POP1 may be updated.
9791 It is possible that we might detect that a comparison is either always
9792 true or always false. However, we do not perform general constant
9793 folding in combine, so this knowledge isn't useful. Such tautologies
9794 should have been detected earlier. Hence we ignore all such cases. */
9796 static enum rtx_code
9797 simplify_comparison (code, pop0, pop1)
9806 enum machine_mode mode, tmode;
9808 /* Try a few ways of applying the same transformation to both operands. */
9811 #ifndef WORD_REGISTER_OPERATIONS
9812 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9813 so check specially. */
9814 if (code != GTU && code != GEU && code != LTU && code != LEU
9815 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9816 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9817 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9818 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9819 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9820 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9821 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9822 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9823 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9824 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9825 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9826 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9827 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9828 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9829 && (INTVAL (XEXP (op0, 1))
9830 == (GET_MODE_BITSIZE (GET_MODE (op0))
9832 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9834 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9835 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9839 /* If both operands are the same constant shift, see if we can ignore the
9840 shift. We can if the shift is a rotate or if the bits shifted out of
9841 this shift are known to be zero for both inputs and if the type of
9842 comparison is compatible with the shift. */
9843 if (GET_CODE (op0) == GET_CODE (op1)
9844 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9845 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9846 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9847 && (code != GT && code != LT && code != GE && code != LE))
9848 || (GET_CODE (op0) == ASHIFTRT
9849 && (code != GTU && code != LTU
9850 && code != GEU && code != LEU)))
9851 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9852 && INTVAL (XEXP (op0, 1)) >= 0
9853 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9854 && XEXP (op0, 1) == XEXP (op1, 1))
9856 enum machine_mode mode = GET_MODE (op0);
9857 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9858 int shift_count = INTVAL (XEXP (op0, 1));
9860 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9861 mask &= (mask >> shift_count) << shift_count;
9862 else if (GET_CODE (op0) == ASHIFT)
9863 mask = (mask & (mask << shift_count)) >> shift_count;
9865 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9866 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9867 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9872 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9873 SUBREGs are of the same mode, and, in both cases, the AND would
9874 be redundant if the comparison was done in the narrower mode,
9875 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9876 and the operand's possibly nonzero bits are 0xffffff01; in that case
9877 if we only care about QImode, we don't need the AND). This case
9878 occurs if the output mode of an scc insn is not SImode and
9879 STORE_FLAG_VALUE == 1 (e.g., the 386).
9881 Similarly, check for a case where the AND's are ZERO_EXTEND
9882 operations from some narrower mode even though a SUBREG is not
9885 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9886 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9887 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9889 rtx inner_op0 = XEXP (op0, 0);
9890 rtx inner_op1 = XEXP (op1, 0);
9891 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9892 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9895 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9896 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9897 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9898 && (GET_MODE (SUBREG_REG (inner_op0))
9899 == GET_MODE (SUBREG_REG (inner_op1)))
9900 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9901 <= HOST_BITS_PER_WIDE_INT)
9902 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9903 GET_MODE (SUBREG_REG (inner_op0)))))
9904 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9905 GET_MODE (SUBREG_REG (inner_op1))))))
9907 op0 = SUBREG_REG (inner_op0);
9908 op1 = SUBREG_REG (inner_op1);
9910 /* The resulting comparison is always unsigned since we masked
9911 off the original sign bit. */
9912 code = unsigned_condition (code);
9918 for (tmode = GET_CLASS_NARROWEST_MODE
9919 (GET_MODE_CLASS (GET_MODE (op0)));
9920 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9921 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9923 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9924 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9925 code = unsigned_condition (code);
9934 /* If both operands are NOT, we can strip off the outer operation
9935 and adjust the comparison code for swapped operands; similarly for
9936 NEG, except that this must be an equality comparison. */
9937 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9938 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9939 && (code == EQ || code == NE)))
9940 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9946 /* If the first operand is a constant, swap the operands and adjust the
9947 comparison code appropriately, but don't do this if the second operand
9948 is already a constant integer. */
9949 if (swap_commutative_operands_p (op0, op1))
9951 tem = op0, op0 = op1, op1 = tem;
9952 code = swap_condition (code);
9955 /* We now enter a loop during which we will try to simplify the comparison.
9956 For the most part, we only are concerned with comparisons with zero,
9957 but some things may really be comparisons with zero but not start
9958 out looking that way. */
9960 while (GET_CODE (op1) == CONST_INT)
9962 enum machine_mode mode = GET_MODE (op0);
9963 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9964 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9965 int equality_comparison_p;
9966 int sign_bit_comparison_p;
9967 int unsigned_comparison_p;
9968 HOST_WIDE_INT const_op;
9970 /* We only want to handle integral modes. This catches VOIDmode,
9971 CCmode, and the floating-point modes. An exception is that we
9972 can handle VOIDmode if OP0 is a COMPARE or a comparison
9975 if (GET_MODE_CLASS (mode) != MODE_INT
9976 && ! (mode == VOIDmode
9977 && (GET_CODE (op0) == COMPARE
9978 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9981 /* Get the constant we are comparing against and turn off all bits
9982 not on in our mode. */
9983 const_op = trunc_int_for_mode (INTVAL (op1), mode);
9984 op1 = GEN_INT (const_op);
9986 /* If we are comparing against a constant power of two and the value
9987 being compared can only have that single bit nonzero (e.g., it was
9988 `and'ed with that bit), we can replace this with a comparison
9991 && (code == EQ || code == NE || code == GE || code == GEU
9992 || code == LT || code == LTU)
9993 && mode_width <= HOST_BITS_PER_WIDE_INT
9994 && exact_log2 (const_op) >= 0
9995 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9997 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9998 op1 = const0_rtx, const_op = 0;
10001 /* Similarly, if we are comparing a value known to be either -1 or
10002 0 with -1, change it to the opposite comparison against zero. */
10005 && (code == EQ || code == NE || code == GT || code == LE
10006 || code == GEU || code == LTU)
10007 && num_sign_bit_copies (op0, mode) == mode_width)
10009 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10010 op1 = const0_rtx, const_op = 0;
10013 /* Do some canonicalizations based on the comparison code. We prefer
10014 comparisons against zero and then prefer equality comparisons.
10015 If we can reduce the size of a constant, we will do that too. */
10020 /* < C is equivalent to <= (C - 1) */
10024 op1 = GEN_INT (const_op);
10026 /* ... fall through to LE case below. */
10032 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10036 op1 = GEN_INT (const_op);
10040 /* If we are doing a <= 0 comparison on a value known to have
10041 a zero sign bit, we can replace this with == 0. */
10042 else if (const_op == 0
10043 && mode_width <= HOST_BITS_PER_WIDE_INT
10044 && (nonzero_bits (op0, mode)
10045 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10050 /* >= C is equivalent to > (C - 1). */
10054 op1 = GEN_INT (const_op);
10056 /* ... fall through to GT below. */
10062 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10066 op1 = GEN_INT (const_op);
10070 /* If we are doing a > 0 comparison on a value known to have
10071 a zero sign bit, we can replace this with != 0. */
10072 else if (const_op == 0
10073 && mode_width <= HOST_BITS_PER_WIDE_INT
10074 && (nonzero_bits (op0, mode)
10075 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10080 /* < C is equivalent to <= (C - 1). */
10084 op1 = GEN_INT (const_op);
10086 /* ... fall through ... */
10089 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10090 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10091 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10093 const_op = 0, op1 = const0_rtx;
10101 /* unsigned <= 0 is equivalent to == 0 */
10105 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10106 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10107 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10109 const_op = 0, op1 = const0_rtx;
10115 /* >= C is equivalent to < (C - 1). */
10119 op1 = GEN_INT (const_op);
10121 /* ... fall through ... */
10124 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10125 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10126 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10128 const_op = 0, op1 = const0_rtx;
10136 /* unsigned > 0 is equivalent to != 0 */
10140 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10141 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10142 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10144 const_op = 0, op1 = const0_rtx;
10153 /* Compute some predicates to simplify code below. */
10155 equality_comparison_p = (code == EQ || code == NE);
10156 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10157 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10160 /* If this is a sign bit comparison and we can do arithmetic in
10161 MODE, say that we will only be needing the sign bit of OP0. */
10162 if (sign_bit_comparison_p
10163 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10164 op0 = force_to_mode (op0, mode,
10166 << (GET_MODE_BITSIZE (mode) - 1)),
10169 /* Now try cases based on the opcode of OP0. If none of the cases
10170 does a "continue", we exit this loop immediately after the
10173 switch (GET_CODE (op0))
10176 /* If we are extracting a single bit from a variable position in
10177 a constant that has only a single bit set and are comparing it
10178 with zero, we can convert this into an equality comparison
10179 between the position and the location of the single bit. */
10181 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10182 && XEXP (op0, 1) == const1_rtx
10183 && equality_comparison_p && const_op == 0
10184 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10186 if (BITS_BIG_ENDIAN)
10188 enum machine_mode new_mode
10189 = mode_for_extraction (EP_extzv, 1);
10190 if (new_mode == MAX_MACHINE_MODE)
10191 i = BITS_PER_WORD - 1 - i;
10195 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10199 op0 = XEXP (op0, 2);
10203 /* Result is nonzero iff shift count is equal to I. */
10204 code = reverse_condition (code);
10208 /* ... fall through ... */
10211 tem = expand_compound_operation (op0);
10220 /* If testing for equality, we can take the NOT of the constant. */
10221 if (equality_comparison_p
10222 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10224 op0 = XEXP (op0, 0);
10229 /* If just looking at the sign bit, reverse the sense of the
10231 if (sign_bit_comparison_p)
10233 op0 = XEXP (op0, 0);
10234 code = (code == GE ? LT : GE);
10240 /* If testing for equality, we can take the NEG of the constant. */
10241 if (equality_comparison_p
10242 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10244 op0 = XEXP (op0, 0);
10249 /* The remaining cases only apply to comparisons with zero. */
10253 /* When X is ABS or is known positive,
10254 (neg X) is < 0 if and only if X != 0. */
10256 if (sign_bit_comparison_p
10257 && (GET_CODE (XEXP (op0, 0)) == ABS
10258 || (mode_width <= HOST_BITS_PER_WIDE_INT
10259 && (nonzero_bits (XEXP (op0, 0), mode)
10260 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10262 op0 = XEXP (op0, 0);
10263 code = (code == LT ? NE : EQ);
10267 /* If we have NEG of something whose two high-order bits are the
10268 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10269 if (num_sign_bit_copies (op0, mode) >= 2)
10271 op0 = XEXP (op0, 0);
10272 code = swap_condition (code);
10278 /* If we are testing equality and our count is a constant, we
10279 can perform the inverse operation on our RHS. */
10280 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10281 && (tem = simplify_binary_operation (ROTATERT, mode,
10282 op1, XEXP (op0, 1))) != 0)
10284 op0 = XEXP (op0, 0);
10289 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10290 a particular bit. Convert it to an AND of a constant of that
10291 bit. This will be converted into a ZERO_EXTRACT. */
10292 if (const_op == 0 && sign_bit_comparison_p
10293 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10294 && mode_width <= HOST_BITS_PER_WIDE_INT)
10296 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10299 - INTVAL (XEXP (op0, 1)))));
10300 code = (code == LT ? NE : EQ);
10304 /* Fall through. */
10307 /* ABS is ignorable inside an equality comparison with zero. */
10308 if (const_op == 0 && equality_comparison_p)
10310 op0 = XEXP (op0, 0);
10316 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10317 to (compare FOO CONST) if CONST fits in FOO's mode and we
10318 are either testing inequality or have an unsigned comparison
10319 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10320 if (! unsigned_comparison_p
10321 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10322 <= HOST_BITS_PER_WIDE_INT)
10323 && ((unsigned HOST_WIDE_INT) const_op
10324 < (((unsigned HOST_WIDE_INT) 1
10325 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10327 op0 = XEXP (op0, 0);
10333 /* Check for the case where we are comparing A - C1 with C2,
10334 both constants are smaller than 1/2 the maximum positive
10335 value in MODE, and the comparison is equality or unsigned.
10336 In that case, if A is either zero-extended to MODE or has
10337 sufficient sign bits so that the high-order bit in MODE
10338 is a copy of the sign in the inner mode, we can prove that it is
10339 safe to do the operation in the wider mode. This simplifies
10340 many range checks. */
10342 if (mode_width <= HOST_BITS_PER_WIDE_INT
10343 && subreg_lowpart_p (op0)
10344 && GET_CODE (SUBREG_REG (op0)) == PLUS
10345 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10346 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10347 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10348 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10349 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10350 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10351 GET_MODE (SUBREG_REG (op0)))
10352 & ~GET_MODE_MASK (mode))
10353 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10354 GET_MODE (SUBREG_REG (op0)))
10355 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10356 - GET_MODE_BITSIZE (mode)))))
10358 op0 = SUBREG_REG (op0);
10362 /* If the inner mode is narrower and we are extracting the low part,
10363 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10364 if (subreg_lowpart_p (op0)
10365 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10366 /* Fall through */ ;
10370 /* ... fall through ... */
10373 if ((unsigned_comparison_p || equality_comparison_p)
10374 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10375 <= HOST_BITS_PER_WIDE_INT)
10376 && ((unsigned HOST_WIDE_INT) const_op
10377 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10379 op0 = XEXP (op0, 0);
10385 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10386 this for equality comparisons due to pathological cases involving
10388 if (equality_comparison_p
10389 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10390 op1, XEXP (op0, 1))))
10392 op0 = XEXP (op0, 0);
10397 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10398 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10399 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10401 op0 = XEXP (XEXP (op0, 0), 0);
10402 code = (code == LT ? EQ : NE);
10408 /* We used to optimize signed comparisons against zero, but that
10409 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10410 arrive here as equality comparisons, or (GEU, LTU) are
10411 optimized away. No need to special-case them. */
10413 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10414 (eq B (minus A C)), whichever simplifies. We can only do
10415 this for equality comparisons due to pathological cases involving
10417 if (equality_comparison_p
10418 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10419 XEXP (op0, 1), op1)))
10421 op0 = XEXP (op0, 0);
10426 if (equality_comparison_p
10427 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10428 XEXP (op0, 0), op1)))
10430 op0 = XEXP (op0, 1);
10435 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10436 of bits in X minus 1, is one iff X > 0. */
10437 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10438 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10439 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10440 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10442 op0 = XEXP (op0, 1);
10443 code = (code == GE ? LE : GT);
10449 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10450 if C is zero or B is a constant. */
10451 if (equality_comparison_p
10452 && 0 != (tem = simplify_binary_operation (XOR, mode,
10453 XEXP (op0, 1), op1)))
10455 op0 = XEXP (op0, 0);
10462 case UNEQ: case LTGT:
10463 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10464 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10465 case UNORDERED: case ORDERED:
10466 /* We can't do anything if OP0 is a condition code value, rather
10467 than an actual data value. */
10470 || XEXP (op0, 0) == cc0_rtx
10472 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10475 /* Get the two operands being compared. */
10476 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10477 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10479 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10481 /* Check for the cases where we simply want the result of the
10482 earlier test or the opposite of that result. */
10483 if (code == NE || code == EQ
10484 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10485 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10486 && (STORE_FLAG_VALUE
10487 & (((HOST_WIDE_INT) 1
10488 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10489 && (code == LT || code == GE)))
10491 enum rtx_code new_code;
10492 if (code == LT || code == NE)
10493 new_code = GET_CODE (op0);
10495 new_code = combine_reversed_comparison_code (op0);
10497 if (new_code != UNKNOWN)
10508 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10510 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10511 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10512 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10514 op0 = XEXP (op0, 1);
10515 code = (code == GE ? GT : LE);
10521 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10522 will be converted to a ZERO_EXTRACT later. */
10523 if (const_op == 0 && equality_comparison_p
10524 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10525 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10527 op0 = simplify_and_const_int
10528 (op0, mode, gen_rtx_LSHIFTRT (mode,
10530 XEXP (XEXP (op0, 0), 1)),
10531 (HOST_WIDE_INT) 1);
10535 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10536 zero and X is a comparison and C1 and C2 describe only bits set
10537 in STORE_FLAG_VALUE, we can compare with X. */
10538 if (const_op == 0 && equality_comparison_p
10539 && mode_width <= HOST_BITS_PER_WIDE_INT
10540 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10541 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10542 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10543 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10544 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10546 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10547 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10548 if ((~STORE_FLAG_VALUE & mask) == 0
10549 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10550 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10551 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10553 op0 = XEXP (XEXP (op0, 0), 0);
10558 /* If we are doing an equality comparison of an AND of a bit equal
10559 to the sign bit, replace this with a LT or GE comparison of
10560 the underlying value. */
10561 if (equality_comparison_p
10563 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10564 && mode_width <= HOST_BITS_PER_WIDE_INT
10565 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10566 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10568 op0 = XEXP (op0, 0);
10569 code = (code == EQ ? GE : LT);
10573 /* If this AND operation is really a ZERO_EXTEND from a narrower
10574 mode, the constant fits within that mode, and this is either an
10575 equality or unsigned comparison, try to do this comparison in
10576 the narrower mode. */
10577 if ((equality_comparison_p || unsigned_comparison_p)
10578 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10579 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10580 & GET_MODE_MASK (mode))
10582 && const_op >> i == 0
10583 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10585 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10589 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10590 in both M1 and M2 and the SUBREG is either paradoxical or
10591 represents the low part, permute the SUBREG and the AND and
10593 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10595 #ifdef WORD_REGISTER_OPERATIONS
10597 > (GET_MODE_BITSIZE
10598 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10599 && mode_width <= BITS_PER_WORD)
10602 <= (GET_MODE_BITSIZE
10603 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10604 && subreg_lowpart_p (XEXP (op0, 0))))
10605 #ifndef WORD_REGISTER_OPERATIONS
10606 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10607 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10608 As originally written the upper bits have a defined value
10609 due to the AND operation. However, if we commute the AND
10610 inside the SUBREG then they no longer have defined values
10611 and the meaning of the code has been changed. */
10612 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10613 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10615 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10616 && mode_width <= HOST_BITS_PER_WIDE_INT
10617 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10618 <= HOST_BITS_PER_WIDE_INT)
10619 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10620 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10621 & INTVAL (XEXP (op0, 1)))
10622 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10623 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10624 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10628 = gen_lowpart_for_combine
10630 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10631 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10635 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10636 (eq (and (lshiftrt X) 1) 0). */
10637 if (const_op == 0 && equality_comparison_p
10638 && XEXP (op0, 1) == const1_rtx
10639 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10640 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10642 op0 = simplify_and_const_int
10644 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10645 XEXP (XEXP (op0, 0), 1)),
10646 (HOST_WIDE_INT) 1);
10647 code = (code == NE ? EQ : NE);
10653 /* If we have (compare (ashift FOO N) (const_int C)) and
10654 the high order N bits of FOO (N+1 if an inequality comparison)
10655 are known to be zero, we can do this by comparing FOO with C
10656 shifted right N bits so long as the low-order N bits of C are
10658 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10659 && INTVAL (XEXP (op0, 1)) >= 0
10660 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10661 < HOST_BITS_PER_WIDE_INT)
10663 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10664 && mode_width <= HOST_BITS_PER_WIDE_INT
10665 && (nonzero_bits (XEXP (op0, 0), mode)
10666 & ~(mask >> (INTVAL (XEXP (op0, 1))
10667 + ! equality_comparison_p))) == 0)
10669 /* We must perform a logical shift, not an arithmetic one,
10670 as we want the top N bits of C to be zero. */
10671 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10673 temp >>= INTVAL (XEXP (op0, 1));
10674 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10675 op0 = XEXP (op0, 0);
10679 /* If we are doing a sign bit comparison, it means we are testing
10680 a particular bit. Convert it to the appropriate AND. */
10681 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10682 && mode_width <= HOST_BITS_PER_WIDE_INT)
10684 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10687 - INTVAL (XEXP (op0, 1)))));
10688 code = (code == LT ? NE : EQ);
10692 /* If this an equality comparison with zero and we are shifting
10693 the low bit to the sign bit, we can convert this to an AND of the
10695 if (const_op == 0 && equality_comparison_p
10696 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10697 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10699 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10700 (HOST_WIDE_INT) 1);
10706 /* If this is an equality comparison with zero, we can do this
10707 as a logical shift, which might be much simpler. */
10708 if (equality_comparison_p && const_op == 0
10709 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10711 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10713 INTVAL (XEXP (op0, 1)));
10717 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10718 do the comparison in a narrower mode. */
10719 if (! unsigned_comparison_p
10720 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10721 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10722 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10723 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10724 MODE_INT, 1)) != BLKmode
10725 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10726 || ((unsigned HOST_WIDE_INT) -const_op
10727 <= GET_MODE_MASK (tmode))))
10729 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10733 /* Likewise if OP0 is a PLUS of a sign extension with a
10734 constant, which is usually represented with the PLUS
10735 between the shifts. */
10736 if (! unsigned_comparison_p
10737 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10738 && GET_CODE (XEXP (op0, 0)) == PLUS
10739 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10740 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10741 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10742 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10743 MODE_INT, 1)) != BLKmode
10744 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10745 || ((unsigned HOST_WIDE_INT) -const_op
10746 <= GET_MODE_MASK (tmode))))
10748 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10749 rtx add_const = XEXP (XEXP (op0, 0), 1);
10750 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10753 op0 = gen_binary (PLUS, tmode,
10754 gen_lowpart_for_combine (tmode, inner),
10759 /* ... fall through ... */
10761 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10762 the low order N bits of FOO are known to be zero, we can do this
10763 by comparing FOO with C shifted left N bits so long as no
10764 overflow occurs. */
10765 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10766 && INTVAL (XEXP (op0, 1)) >= 0
10767 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10768 && mode_width <= HOST_BITS_PER_WIDE_INT
10769 && (nonzero_bits (XEXP (op0, 0), mode)
10770 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10772 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10775 const_op <<= INTVAL (XEXP (op0, 1));
10776 op1 = GEN_INT (const_op);
10777 op0 = XEXP (op0, 0);
10781 /* If we are using this shift to extract just the sign bit, we
10782 can replace this with an LT or GE comparison. */
10784 && (equality_comparison_p || sign_bit_comparison_p)
10785 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10786 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10788 op0 = XEXP (op0, 0);
10789 code = (code == NE || code == GT ? LT : GE);
10801 /* Now make any compound operations involved in this comparison. Then,
10802 check for an outmost SUBREG on OP0 that is not doing anything or is
10803 paradoxical. The latter case can only occur when it is known that the
10804 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10805 We can never remove a SUBREG for a non-equality comparison because the
10806 sign bit is in a different place in the underlying object. */
10808 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10809 op1 = make_compound_operation (op1, SET);
10811 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10812 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10813 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10814 && (code == NE || code == EQ)
10815 && ((GET_MODE_SIZE (GET_MODE (op0))
10816 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10818 op0 = SUBREG_REG (op0);
10819 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10822 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10823 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10824 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10825 && (code == NE || code == EQ)
10826 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10827 <= HOST_BITS_PER_WIDE_INT)
10828 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10829 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10830 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10832 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10833 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10834 op0 = SUBREG_REG (op0), op1 = tem;
10836 /* We now do the opposite procedure: Some machines don't have compare
10837 insns in all modes. If OP0's mode is an integer mode smaller than a
10838 word and we can't do a compare in that mode, see if there is a larger
10839 mode for which we can do the compare. There are a number of cases in
10840 which we can use the wider mode. */
10842 mode = GET_MODE (op0);
10843 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10844 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10845 && ! have_insn_for (COMPARE, mode))
10846 for (tmode = GET_MODE_WIDER_MODE (mode);
10848 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10849 tmode = GET_MODE_WIDER_MODE (tmode))
10850 if (have_insn_for (COMPARE, tmode))
10852 /* If the only nonzero bits in OP0 and OP1 are those in the
10853 narrower mode and this is an equality or unsigned comparison,
10854 we can use the wider mode. Similarly for sign-extended
10855 values, in which case it is true for all comparisons. */
10856 if (((code == EQ || code == NE
10857 || code == GEU || code == GTU || code == LEU || code == LTU)
10858 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
10859 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
10860 || ((num_sign_bit_copies (op0, tmode)
10861 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10862 && (num_sign_bit_copies (op1, tmode)
10863 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10865 /* If OP0 is an AND and we don't have an AND in MODE either,
10866 make a new AND in the proper mode. */
10867 if (GET_CODE (op0) == AND
10868 && !have_insn_for (AND, mode))
10869 op0 = gen_binary (AND, tmode,
10870 gen_lowpart_for_combine (tmode,
10872 gen_lowpart_for_combine (tmode,
10875 op0 = gen_lowpart_for_combine (tmode, op0);
10876 op1 = gen_lowpart_for_combine (tmode, op1);
10880 /* If this is a test for negative, we can make an explicit
10881 test of the sign bit. */
10883 if (op1 == const0_rtx && (code == LT || code == GE)
10884 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10886 op0 = gen_binary (AND, tmode,
10887 gen_lowpart_for_combine (tmode, op0),
10888 GEN_INT ((HOST_WIDE_INT) 1
10889 << (GET_MODE_BITSIZE (mode) - 1)));
10890 code = (code == LT) ? NE : EQ;
10895 #ifdef CANONICALIZE_COMPARISON
10896 /* If this machine only supports a subset of valid comparisons, see if we
10897 can convert an unsupported one into a supported one. */
10898 CANONICALIZE_COMPARISON (code, op0, op1);
10907 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10908 searching backward. */
10909 static enum rtx_code
10910 combine_reversed_comparison_code (exp)
10913 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10916 if (code1 != UNKNOWN
10917 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10919 /* Otherwise try and find where the condition codes were last set and
10921 x = get_last_value (XEXP (exp, 0));
10922 if (!x || GET_CODE (x) != COMPARE)
10924 return reversed_comparison_code_parts (GET_CODE (exp),
10925 XEXP (x, 0), XEXP (x, 1), NULL);
10927 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10928 Return NULL_RTX in case we fail to do the reversal. */
10930 reversed_comparison (exp, mode, op0, op1)
10932 enum machine_mode mode;
10934 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10935 if (reversed_code == UNKNOWN)
10938 return gen_binary (reversed_code, mode, op0, op1);
10941 /* Utility function for following routine. Called when X is part of a value
10942 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10943 for each register mentioned. Similar to mention_regs in cse.c */
10946 update_table_tick (x)
10949 enum rtx_code code = GET_CODE (x);
10950 const char *fmt = GET_RTX_FORMAT (code);
10955 unsigned int regno = REGNO (x);
10956 unsigned int endregno
10957 = regno + (regno < FIRST_PSEUDO_REGISTER
10958 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10961 for (r = regno; r < endregno; r++)
10962 reg_last_set_table_tick[r] = label_tick;
10967 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10968 /* Note that we can't have an "E" in values stored; see
10969 get_last_value_validate. */
10971 update_table_tick (XEXP (x, i));
10974 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10975 are saying that the register is clobbered and we no longer know its
10976 value. If INSN is zero, don't update reg_last_set; this is only permitted
10977 with VALUE also zero and is used to invalidate the register. */
10980 record_value_for_reg (reg, insn, value)
10985 unsigned int regno = REGNO (reg);
10986 unsigned int endregno
10987 = regno + (regno < FIRST_PSEUDO_REGISTER
10988 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10991 /* If VALUE contains REG and we have a previous value for REG, substitute
10992 the previous value. */
10993 if (value && insn && reg_overlap_mentioned_p (reg, value))
10997 /* Set things up so get_last_value is allowed to see anything set up to
10999 subst_low_cuid = INSN_CUID (insn);
11000 tem = get_last_value (reg);
11002 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11003 it isn't going to be useful and will take a lot of time to process,
11004 so just use the CLOBBER. */
11008 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11009 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11010 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11011 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11012 tem = XEXP (tem, 0);
11014 value = replace_rtx (copy_rtx (value), reg, tem);
11018 /* For each register modified, show we don't know its value, that
11019 we don't know about its bitwise content, that its value has been
11020 updated, and that we don't know the location of the death of the
11022 for (i = regno; i < endregno; i++)
11025 reg_last_set[i] = insn;
11027 reg_last_set_value[i] = 0;
11028 reg_last_set_mode[i] = 0;
11029 reg_last_set_nonzero_bits[i] = 0;
11030 reg_last_set_sign_bit_copies[i] = 0;
11031 reg_last_death[i] = 0;
11034 /* Mark registers that are being referenced in this value. */
11036 update_table_tick (value);
11038 /* Now update the status of each register being set.
11039 If someone is using this register in this block, set this register
11040 to invalid since we will get confused between the two lives in this
11041 basic block. This makes using this register always invalid. In cse, we
11042 scan the table to invalidate all entries using this register, but this
11043 is too much work for us. */
11045 for (i = regno; i < endregno; i++)
11047 reg_last_set_label[i] = label_tick;
11048 if (value && reg_last_set_table_tick[i] == label_tick)
11049 reg_last_set_invalid[i] = 1;
11051 reg_last_set_invalid[i] = 0;
11054 /* The value being assigned might refer to X (like in "x++;"). In that
11055 case, we must replace it with (clobber (const_int 0)) to prevent
11057 if (value && ! get_last_value_validate (&value, insn,
11058 reg_last_set_label[regno], 0))
11060 value = copy_rtx (value);
11061 if (! get_last_value_validate (&value, insn,
11062 reg_last_set_label[regno], 1))
11066 /* For the main register being modified, update the value, the mode, the
11067 nonzero bits, and the number of sign bit copies. */
11069 reg_last_set_value[regno] = value;
11073 subst_low_cuid = INSN_CUID (insn);
11074 reg_last_set_mode[regno] = GET_MODE (reg);
11075 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11076 reg_last_set_sign_bit_copies[regno]
11077 = num_sign_bit_copies (value, GET_MODE (reg));
11081 /* Called via note_stores from record_dead_and_set_regs to handle one
11082 SET or CLOBBER in an insn. DATA is the instruction in which the
11083 set is occurring. */
11086 record_dead_and_set_regs_1 (dest, setter, data)
11090 rtx record_dead_insn = (rtx) data;
11092 if (GET_CODE (dest) == SUBREG)
11093 dest = SUBREG_REG (dest);
11095 if (GET_CODE (dest) == REG)
11097 /* If we are setting the whole register, we know its value. Otherwise
11098 show that we don't know the value. We can handle SUBREG in
11100 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11101 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11102 else if (GET_CODE (setter) == SET
11103 && GET_CODE (SET_DEST (setter)) == SUBREG
11104 && SUBREG_REG (SET_DEST (setter)) == dest
11105 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11106 && subreg_lowpart_p (SET_DEST (setter)))
11107 record_value_for_reg (dest, record_dead_insn,
11108 gen_lowpart_for_combine (GET_MODE (dest),
11109 SET_SRC (setter)));
11111 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11113 else if (GET_CODE (dest) == MEM
11114 /* Ignore pushes, they clobber nothing. */
11115 && ! push_operand (dest, GET_MODE (dest)))
11116 mem_last_set = INSN_CUID (record_dead_insn);
11119 /* Update the records of when each REG was most recently set or killed
11120 for the things done by INSN. This is the last thing done in processing
11121 INSN in the combiner loop.
11123 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11124 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11125 and also the similar information mem_last_set (which insn most recently
11126 modified memory) and last_call_cuid (which insn was the most recent
11127 subroutine call). */
11130 record_dead_and_set_regs (insn)
11136 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11138 if (REG_NOTE_KIND (link) == REG_DEAD
11139 && GET_CODE (XEXP (link, 0)) == REG)
11141 unsigned int regno = REGNO (XEXP (link, 0));
11142 unsigned int endregno
11143 = regno + (regno < FIRST_PSEUDO_REGISTER
11144 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11147 for (i = regno; i < endregno; i++)
11148 reg_last_death[i] = insn;
11150 else if (REG_NOTE_KIND (link) == REG_INC)
11151 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11154 if (GET_CODE (insn) == CALL_INSN)
11156 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11157 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11159 reg_last_set_value[i] = 0;
11160 reg_last_set_mode[i] = 0;
11161 reg_last_set_nonzero_bits[i] = 0;
11162 reg_last_set_sign_bit_copies[i] = 0;
11163 reg_last_death[i] = 0;
11166 last_call_cuid = mem_last_set = INSN_CUID (insn);
11168 /* Don't bother recording what this insn does. It might set the
11169 return value register, but we can't combine into a call
11170 pattern anyway, so there's no point trying (and it may cause
11171 a crash, if e.g. we wind up asking for last_set_value of a
11172 SUBREG of the return value register). */
11176 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11179 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11180 register present in the SUBREG, so for each such SUBREG go back and
11181 adjust nonzero and sign bit information of the registers that are
11182 known to have some zero/sign bits set.
11184 This is needed because when combine blows the SUBREGs away, the
11185 information on zero/sign bits is lost and further combines can be
11186 missed because of that. */
11189 record_promoted_value (insn, subreg)
11194 unsigned int regno = REGNO (SUBREG_REG (subreg));
11195 enum machine_mode mode = GET_MODE (subreg);
11197 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11200 for (links = LOG_LINKS (insn); links;)
11202 insn = XEXP (links, 0);
11203 set = single_set (insn);
11205 if (! set || GET_CODE (SET_DEST (set)) != REG
11206 || REGNO (SET_DEST (set)) != regno
11207 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11209 links = XEXP (links, 1);
11213 if (reg_last_set[regno] == insn)
11215 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11216 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11219 if (GET_CODE (SET_SRC (set)) == REG)
11221 regno = REGNO (SET_SRC (set));
11222 links = LOG_LINKS (insn);
11229 /* Scan X for promoted SUBREGs. For each one found,
11230 note what it implies to the registers used in it. */
11233 check_promoted_subreg (insn, x)
11237 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11238 && GET_CODE (SUBREG_REG (x)) == REG)
11239 record_promoted_value (insn, x);
11242 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11245 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11249 check_promoted_subreg (insn, XEXP (x, i));
11253 if (XVEC (x, i) != 0)
11254 for (j = 0; j < XVECLEN (x, i); j++)
11255 check_promoted_subreg (insn, XVECEXP (x, i, j));
11261 /* Utility routine for the following function. Verify that all the registers
11262 mentioned in *LOC are valid when *LOC was part of a value set when
11263 label_tick == TICK. Return 0 if some are not.
11265 If REPLACE is non-zero, replace the invalid reference with
11266 (clobber (const_int 0)) and return 1. This replacement is useful because
11267 we often can get useful information about the form of a value (e.g., if
11268 it was produced by a shift that always produces -1 or 0) even though
11269 we don't know exactly what registers it was produced from. */
11272 get_last_value_validate (loc, insn, tick, replace)
11279 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11280 int len = GET_RTX_LENGTH (GET_CODE (x));
11283 if (GET_CODE (x) == REG)
11285 unsigned int regno = REGNO (x);
11286 unsigned int endregno
11287 = regno + (regno < FIRST_PSEUDO_REGISTER
11288 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11291 for (j = regno; j < endregno; j++)
11292 if (reg_last_set_invalid[j]
11293 /* If this is a pseudo-register that was only set once and not
11294 live at the beginning of the function, it is always valid. */
11295 || (! (regno >= FIRST_PSEUDO_REGISTER
11296 && REG_N_SETS (regno) == 1
11297 && (! REGNO_REG_SET_P
11298 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11299 && reg_last_set_label[j] > tick))
11302 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11308 /* If this is a memory reference, make sure that there were
11309 no stores after it that might have clobbered the value. We don't
11310 have alias info, so we assume any store invalidates it. */
11311 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11312 && INSN_CUID (insn) <= mem_last_set)
11315 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11319 for (i = 0; i < len; i++)
11321 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11322 /* Don't bother with these. They shouldn't occur anyway. */
11326 /* If we haven't found a reason for it to be invalid, it is valid. */
11330 /* Get the last value assigned to X, if known. Some registers
11331 in the value may be replaced with (clobber (const_int 0)) if their value
11332 is known longer known reliably. */
11338 unsigned int regno;
11341 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11342 then convert it to the desired mode. If this is a paradoxical SUBREG,
11343 we cannot predict what values the "extra" bits might have. */
11344 if (GET_CODE (x) == SUBREG
11345 && subreg_lowpart_p (x)
11346 && (GET_MODE_SIZE (GET_MODE (x))
11347 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11348 && (value = get_last_value (SUBREG_REG (x))) != 0)
11349 return gen_lowpart_for_combine (GET_MODE (x), value);
11351 if (GET_CODE (x) != REG)
11355 value = reg_last_set_value[regno];
11357 /* If we don't have a value, or if it isn't for this basic block and
11358 it's either a hard register, set more than once, or it's a live
11359 at the beginning of the function, return 0.
11361 Because if it's not live at the beginning of the function then the reg
11362 is always set before being used (is never used without being set).
11363 And, if it's set only once, and it's always set before use, then all
11364 uses must have the same last value, even if it's not from this basic
11368 || (reg_last_set_label[regno] != label_tick
11369 && (regno < FIRST_PSEUDO_REGISTER
11370 || REG_N_SETS (regno) != 1
11371 || (REGNO_REG_SET_P
11372 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11375 /* If the value was set in a later insn than the ones we are processing,
11376 we can't use it even if the register was only set once. */
11377 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11380 /* If the value has all its registers valid, return it. */
11381 if (get_last_value_validate (&value, reg_last_set[regno],
11382 reg_last_set_label[regno], 0))
11385 /* Otherwise, make a copy and replace any invalid register with
11386 (clobber (const_int 0)). If that fails for some reason, return 0. */
11388 value = copy_rtx (value);
11389 if (get_last_value_validate (&value, reg_last_set[regno],
11390 reg_last_set_label[regno], 1))
11396 /* Return nonzero if expression X refers to a REG or to memory
11397 that is set in an instruction more recent than FROM_CUID. */
11400 use_crosses_set_p (x, from_cuid)
11406 enum rtx_code code = GET_CODE (x);
11410 unsigned int regno = REGNO (x);
11411 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11412 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11414 #ifdef PUSH_ROUNDING
11415 /* Don't allow uses of the stack pointer to be moved,
11416 because we don't know whether the move crosses a push insn. */
11417 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11420 for (; regno < endreg; regno++)
11421 if (reg_last_set[regno]
11422 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11427 if (code == MEM && mem_last_set > from_cuid)
11430 fmt = GET_RTX_FORMAT (code);
11432 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11437 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11438 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11441 else if (fmt[i] == 'e'
11442 && use_crosses_set_p (XEXP (x, i), from_cuid))
11448 /* Define three variables used for communication between the following
11451 static unsigned int reg_dead_regno, reg_dead_endregno;
11452 static int reg_dead_flag;
11454 /* Function called via note_stores from reg_dead_at_p.
11456 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11457 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11460 reg_dead_at_p_1 (dest, x, data)
11463 void *data ATTRIBUTE_UNUSED;
11465 unsigned int regno, endregno;
11467 if (GET_CODE (dest) != REG)
11470 regno = REGNO (dest);
11471 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11472 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11474 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11475 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11478 /* Return non-zero if REG is known to be dead at INSN.
11480 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11481 referencing REG, it is dead. If we hit a SET referencing REG, it is
11482 live. Otherwise, see if it is live or dead at the start of the basic
11483 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11484 must be assumed to be always live. */
11487 reg_dead_at_p (reg, insn)
11494 /* Set variables for reg_dead_at_p_1. */
11495 reg_dead_regno = REGNO (reg);
11496 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11497 ? HARD_REGNO_NREGS (reg_dead_regno,
11503 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11504 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11506 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11507 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11511 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11512 beginning of function. */
11513 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11514 insn = prev_nonnote_insn (insn))
11516 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11518 return reg_dead_flag == 1 ? 1 : 0;
11520 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11524 /* Get the basic block number that we were in. */
11529 for (block = 0; block < n_basic_blocks; block++)
11530 if (insn == BLOCK_HEAD (block))
11533 if (block == n_basic_blocks)
11537 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11538 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11544 /* Note hard registers in X that are used. This code is similar to
11545 that in flow.c, but much simpler since we don't care about pseudos. */
11548 mark_used_regs_combine (x)
11551 RTX_CODE code = GET_CODE (x);
11552 unsigned int regno;
11564 case ADDR_DIFF_VEC:
11567 /* CC0 must die in the insn after it is set, so we don't need to take
11568 special note of it here. */
11574 /* If we are clobbering a MEM, mark any hard registers inside the
11575 address as used. */
11576 if (GET_CODE (XEXP (x, 0)) == MEM)
11577 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11582 /* A hard reg in a wide mode may really be multiple registers.
11583 If so, mark all of them just like the first. */
11584 if (regno < FIRST_PSEUDO_REGISTER)
11586 unsigned int endregno, r;
11588 /* None of this applies to the stack, frame or arg pointers */
11589 if (regno == STACK_POINTER_REGNUM
11590 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11591 || regno == HARD_FRAME_POINTER_REGNUM
11593 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11594 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11596 || regno == FRAME_POINTER_REGNUM)
11599 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11600 for (r = regno; r < endregno; r++)
11601 SET_HARD_REG_BIT (newpat_used_regs, r);
11607 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11609 rtx testreg = SET_DEST (x);
11611 while (GET_CODE (testreg) == SUBREG
11612 || GET_CODE (testreg) == ZERO_EXTRACT
11613 || GET_CODE (testreg) == SIGN_EXTRACT
11614 || GET_CODE (testreg) == STRICT_LOW_PART)
11615 testreg = XEXP (testreg, 0);
11617 if (GET_CODE (testreg) == MEM)
11618 mark_used_regs_combine (XEXP (testreg, 0));
11620 mark_used_regs_combine (SET_SRC (x));
11628 /* Recursively scan the operands of this expression. */
11631 const char *fmt = GET_RTX_FORMAT (code);
11633 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11636 mark_used_regs_combine (XEXP (x, i));
11637 else if (fmt[i] == 'E')
11641 for (j = 0; j < XVECLEN (x, i); j++)
11642 mark_used_regs_combine (XVECEXP (x, i, j));
11648 /* Remove register number REGNO from the dead registers list of INSN.
11650 Return the note used to record the death, if there was one. */
11653 remove_death (regno, insn)
11654 unsigned int regno;
11657 rtx note = find_regno_note (insn, REG_DEAD, regno);
11661 REG_N_DEATHS (regno)--;
11662 remove_note (insn, note);
11668 /* For each register (hardware or pseudo) used within expression X, if its
11669 death is in an instruction with cuid between FROM_CUID (inclusive) and
11670 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11671 list headed by PNOTES.
11673 That said, don't move registers killed by maybe_kill_insn.
11675 This is done when X is being merged by combination into TO_INSN. These
11676 notes will then be distributed as needed. */
11679 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11681 rtx maybe_kill_insn;
11688 enum rtx_code code = GET_CODE (x);
11692 unsigned int regno = REGNO (x);
11693 rtx where_dead = reg_last_death[regno];
11694 rtx before_dead, after_dead;
11696 /* Don't move the register if it gets killed in between from and to */
11697 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11698 && ! reg_referenced_p (x, maybe_kill_insn))
11701 /* WHERE_DEAD could be a USE insn made by combine, so first we
11702 make sure that we have insns with valid INSN_CUID values. */
11703 before_dead = where_dead;
11704 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11705 before_dead = PREV_INSN (before_dead);
11707 after_dead = where_dead;
11708 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11709 after_dead = NEXT_INSN (after_dead);
11711 if (before_dead && after_dead
11712 && INSN_CUID (before_dead) >= from_cuid
11713 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11714 || (where_dead != after_dead
11715 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11717 rtx note = remove_death (regno, where_dead);
11719 /* It is possible for the call above to return 0. This can occur
11720 when reg_last_death points to I2 or I1 that we combined with.
11721 In that case make a new note.
11723 We must also check for the case where X is a hard register
11724 and NOTE is a death note for a range of hard registers
11725 including X. In that case, we must put REG_DEAD notes for
11726 the remaining registers in place of NOTE. */
11728 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11729 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11730 > GET_MODE_SIZE (GET_MODE (x))))
11732 unsigned int deadregno = REGNO (XEXP (note, 0));
11733 unsigned int deadend
11734 = (deadregno + HARD_REGNO_NREGS (deadregno,
11735 GET_MODE (XEXP (note, 0))));
11736 unsigned int ourend
11737 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11740 for (i = deadregno; i < deadend; i++)
11741 if (i < regno || i >= ourend)
11742 REG_NOTES (where_dead)
11743 = gen_rtx_EXPR_LIST (REG_DEAD,
11744 gen_rtx_REG (reg_raw_mode[i], i),
11745 REG_NOTES (where_dead));
11748 /* If we didn't find any note, or if we found a REG_DEAD note that
11749 covers only part of the given reg, and we have a multi-reg hard
11750 register, then to be safe we must check for REG_DEAD notes
11751 for each register other than the first. They could have
11752 their own REG_DEAD notes lying around. */
11753 else if ((note == 0
11755 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11756 < GET_MODE_SIZE (GET_MODE (x)))))
11757 && regno < FIRST_PSEUDO_REGISTER
11758 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11760 unsigned int ourend
11761 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11762 unsigned int i, offset;
11766 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11770 for (i = regno + offset; i < ourend; i++)
11771 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11772 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11775 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11777 XEXP (note, 1) = *pnotes;
11781 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11783 REG_N_DEATHS (regno)++;
11789 else if (GET_CODE (x) == SET)
11791 rtx dest = SET_DEST (x);
11793 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11795 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11796 that accesses one word of a multi-word item, some
11797 piece of everything register in the expression is used by
11798 this insn, so remove any old death. */
11799 /* ??? So why do we test for equality of the sizes? */
11801 if (GET_CODE (dest) == ZERO_EXTRACT
11802 || GET_CODE (dest) == STRICT_LOW_PART
11803 || (GET_CODE (dest) == SUBREG
11804 && (((GET_MODE_SIZE (GET_MODE (dest))
11805 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11806 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11807 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11809 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11813 /* If this is some other SUBREG, we know it replaces the entire
11814 value, so use that as the destination. */
11815 if (GET_CODE (dest) == SUBREG)
11816 dest = SUBREG_REG (dest);
11818 /* If this is a MEM, adjust deaths of anything used in the address.
11819 For a REG (the only other possibility), the entire value is
11820 being replaced so the old value is not used in this insn. */
11822 if (GET_CODE (dest) == MEM)
11823 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11828 else if (GET_CODE (x) == CLOBBER)
11831 len = GET_RTX_LENGTH (code);
11832 fmt = GET_RTX_FORMAT (code);
11834 for (i = 0; i < len; i++)
11839 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11840 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11843 else if (fmt[i] == 'e')
11844 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11848 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11849 pattern of an insn. X must be a REG. */
11852 reg_bitfield_target_p (x, body)
11858 if (GET_CODE (body) == SET)
11860 rtx dest = SET_DEST (body);
11862 unsigned int regno, tregno, endregno, endtregno;
11864 if (GET_CODE (dest) == ZERO_EXTRACT)
11865 target = XEXP (dest, 0);
11866 else if (GET_CODE (dest) == STRICT_LOW_PART)
11867 target = SUBREG_REG (XEXP (dest, 0));
11871 if (GET_CODE (target) == SUBREG)
11872 target = SUBREG_REG (target);
11874 if (GET_CODE (target) != REG)
11877 tregno = REGNO (target), regno = REGNO (x);
11878 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11879 return target == x;
11881 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11882 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11884 return endregno > tregno && regno < endtregno;
11887 else if (GET_CODE (body) == PARALLEL)
11888 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11889 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11895 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11896 as appropriate. I3 and I2 are the insns resulting from the combination
11897 insns including FROM (I2 may be zero).
11899 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11900 not need REG_DEAD notes because they are being substituted for. This
11901 saves searching in the most common cases.
11903 Each note in the list is either ignored or placed on some insns, depending
11904 on the type of note. */
11907 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11911 rtx elim_i2, elim_i1;
11913 rtx note, next_note;
11916 for (note = notes; note; note = next_note)
11918 rtx place = 0, place2 = 0;
11920 /* If this NOTE references a pseudo register, ensure it references
11921 the latest copy of that register. */
11922 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11923 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11924 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11926 next_note = XEXP (note, 1);
11927 switch (REG_NOTE_KIND (note))
11931 case REG_EXEC_COUNT:
11932 /* Doesn't matter much where we put this, as long as it's somewhere.
11933 It is preferable to keep these notes on branches, which is most
11934 likely to be i3. */
11938 case REG_VTABLE_REF:
11939 /* ??? Should remain with *a particular* memory load. Given the
11940 nature of vtable data, the last insn seems relatively safe. */
11944 case REG_NON_LOCAL_GOTO:
11945 if (GET_CODE (i3) == JUMP_INSN)
11947 else if (i2 && GET_CODE (i2) == JUMP_INSN)
11953 case REG_EH_REGION:
11954 /* These notes must remain with the call or trapping instruction. */
11955 if (GET_CODE (i3) == CALL_INSN)
11957 else if (i2 && GET_CODE (i2) == CALL_INSN)
11959 else if (flag_non_call_exceptions)
11961 if (may_trap_p (i3))
11963 else if (i2 && may_trap_p (i2))
11965 /* ??? Otherwise assume we've combined things such that we
11966 can now prove that the instructions can't trap. Drop the
11967 note in this case. */
11975 /* These notes must remain with the call. It should not be
11976 possible for both I2 and I3 to be a call. */
11977 if (GET_CODE (i3) == CALL_INSN)
11979 else if (i2 && GET_CODE (i2) == CALL_INSN)
11986 /* Any clobbers for i3 may still exist, and so we must process
11987 REG_UNUSED notes from that insn.
11989 Any clobbers from i2 or i1 can only exist if they were added by
11990 recog_for_combine. In that case, recog_for_combine created the
11991 necessary REG_UNUSED notes. Trying to keep any original
11992 REG_UNUSED notes from these insns can cause incorrect output
11993 if it is for the same register as the original i3 dest.
11994 In that case, we will notice that the register is set in i3,
11995 and then add a REG_UNUSED note for the destination of i3, which
11996 is wrong. However, it is possible to have REG_UNUSED notes from
11997 i2 or i1 for register which were both used and clobbered, so
11998 we keep notes from i2 or i1 if they will turn into REG_DEAD
12001 /* If this register is set or clobbered in I3, put the note there
12002 unless there is one already. */
12003 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12005 if (from_insn != i3)
12008 if (! (GET_CODE (XEXP (note, 0)) == REG
12009 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12010 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12013 /* Otherwise, if this register is used by I3, then this register
12014 now dies here, so we must put a REG_DEAD note here unless there
12016 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12017 && ! (GET_CODE (XEXP (note, 0)) == REG
12018 ? find_regno_note (i3, REG_DEAD,
12019 REGNO (XEXP (note, 0)))
12020 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12022 PUT_REG_NOTE_KIND (note, REG_DEAD);
12030 /* These notes say something about results of an insn. We can
12031 only support them if they used to be on I3 in which case they
12032 remain on I3. Otherwise they are ignored.
12034 If the note refers to an expression that is not a constant, we
12035 must also ignore the note since we cannot tell whether the
12036 equivalence is still true. It might be possible to do
12037 slightly better than this (we only have a problem if I2DEST
12038 or I1DEST is present in the expression), but it doesn't
12039 seem worth the trouble. */
12041 if (from_insn == i3
12042 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12047 case REG_NO_CONFLICT:
12048 /* These notes say something about how a register is used. They must
12049 be present on any use of the register in I2 or I3. */
12050 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12053 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12063 /* This can show up in several ways -- either directly in the
12064 pattern, or hidden off in the constant pool with (or without?)
12065 a REG_EQUAL note. */
12066 /* ??? Ignore the without-reg_equal-note problem for now. */
12067 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12068 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12069 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12070 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12074 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12075 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12076 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12077 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12085 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12086 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12087 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12089 if (JUMP_LABEL (place) != XEXP (note, 0))
12091 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12092 LABEL_NUSES (JUMP_LABEL (place))--;
12095 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12097 if (JUMP_LABEL (place2) != XEXP (note, 0))
12099 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12100 LABEL_NUSES (JUMP_LABEL (place2))--;
12107 /* These notes say something about the value of a register prior
12108 to the execution of an insn. It is too much trouble to see
12109 if the note is still correct in all situations. It is better
12110 to simply delete it. */
12114 /* If the insn previously containing this note still exists,
12115 put it back where it was. Otherwise move it to the previous
12116 insn. Adjust the corresponding REG_LIBCALL note. */
12117 if (GET_CODE (from_insn) != NOTE)
12121 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12122 place = prev_real_insn (from_insn);
12124 XEXP (tem, 0) = place;
12125 /* If we're deleting the last remaining instruction of a
12126 libcall sequence, don't add the notes. */
12127 else if (XEXP (note, 0) == from_insn)
12133 /* This is handled similarly to REG_RETVAL. */
12134 if (GET_CODE (from_insn) != NOTE)
12138 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12139 place = next_real_insn (from_insn);
12141 XEXP (tem, 0) = place;
12142 /* If we're deleting the last remaining instruction of a
12143 libcall sequence, don't add the notes. */
12144 else if (XEXP (note, 0) == from_insn)
12150 /* If the register is used as an input in I3, it dies there.
12151 Similarly for I2, if it is non-zero and adjacent to I3.
12153 If the register is not used as an input in either I3 or I2
12154 and it is not one of the registers we were supposed to eliminate,
12155 there are two possibilities. We might have a non-adjacent I2
12156 or we might have somehow eliminated an additional register
12157 from a computation. For example, we might have had A & B where
12158 we discover that B will always be zero. In this case we will
12159 eliminate the reference to A.
12161 In both cases, we must search to see if we can find a previous
12162 use of A and put the death note there. */
12165 && GET_CODE (from_insn) == CALL_INSN
12166 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12168 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12170 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12171 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12174 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12175 || rtx_equal_p (XEXP (note, 0), elim_i1))
12180 basic_block bb = BASIC_BLOCK (this_basic_block);
12182 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12184 if (! INSN_P (tem))
12186 if (tem == bb->head)
12191 /* If the register is being set at TEM, see if that is all
12192 TEM is doing. If so, delete TEM. Otherwise, make this
12193 into a REG_UNUSED note instead. */
12194 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12196 rtx set = single_set (tem);
12197 rtx inner_dest = 0;
12199 rtx cc0_setter = NULL_RTX;
12203 for (inner_dest = SET_DEST (set);
12204 (GET_CODE (inner_dest) == STRICT_LOW_PART
12205 || GET_CODE (inner_dest) == SUBREG
12206 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12207 inner_dest = XEXP (inner_dest, 0))
12210 /* Verify that it was the set, and not a clobber that
12211 modified the register.
12213 CC0 targets must be careful to maintain setter/user
12214 pairs. If we cannot delete the setter due to side
12215 effects, mark the user with an UNUSED note instead
12218 if (set != 0 && ! side_effects_p (SET_SRC (set))
12219 && rtx_equal_p (XEXP (note, 0), inner_dest)
12221 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12222 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12223 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12227 /* Move the notes and links of TEM elsewhere.
12228 This might delete other dead insns recursively.
12229 First set the pattern to something that won't use
12232 PATTERN (tem) = pc_rtx;
12234 distribute_notes (REG_NOTES (tem), tem, tem,
12235 NULL_RTX, NULL_RTX, NULL_RTX);
12236 distribute_links (LOG_LINKS (tem));
12238 PUT_CODE (tem, NOTE);
12239 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12240 NOTE_SOURCE_FILE (tem) = 0;
12243 /* Delete the setter too. */
12246 PATTERN (cc0_setter) = pc_rtx;
12248 distribute_notes (REG_NOTES (cc0_setter),
12249 cc0_setter, cc0_setter,
12250 NULL_RTX, NULL_RTX, NULL_RTX);
12251 distribute_links (LOG_LINKS (cc0_setter));
12253 PUT_CODE (cc0_setter, NOTE);
12254 NOTE_LINE_NUMBER (cc0_setter)
12255 = NOTE_INSN_DELETED;
12256 NOTE_SOURCE_FILE (cc0_setter) = 0;
12260 /* If the register is both set and used here, put the
12261 REG_DEAD note here, but place a REG_UNUSED note
12262 here too unless there already is one. */
12263 else if (reg_referenced_p (XEXP (note, 0),
12268 if (! find_regno_note (tem, REG_UNUSED,
12269 REGNO (XEXP (note, 0))))
12271 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12276 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12278 /* If there isn't already a REG_UNUSED note, put one
12280 if (! find_regno_note (tem, REG_UNUSED,
12281 REGNO (XEXP (note, 0))))
12286 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12287 || (GET_CODE (tem) == CALL_INSN
12288 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12292 /* If we are doing a 3->2 combination, and we have a
12293 register which formerly died in i3 and was not used
12294 by i2, which now no longer dies in i3 and is used in
12295 i2 but does not die in i2, and place is between i2
12296 and i3, then we may need to move a link from place to
12298 if (i2 && INSN_UID (place) <= max_uid_cuid
12299 && INSN_CUID (place) > INSN_CUID (i2)
12301 && INSN_CUID (from_insn) > INSN_CUID (i2)
12302 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12304 rtx links = LOG_LINKS (place);
12305 LOG_LINKS (place) = 0;
12306 distribute_links (links);
12311 if (tem == bb->head)
12315 /* We haven't found an insn for the death note and it
12316 is still a REG_DEAD note, but we have hit the beginning
12317 of the block. If the existing life info says the reg
12318 was dead, there's nothing left to do. Otherwise, we'll
12319 need to do a global life update after combine. */
12320 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12321 && REGNO_REG_SET_P (bb->global_live_at_start,
12322 REGNO (XEXP (note, 0))))
12324 SET_BIT (refresh_blocks, this_basic_block);
12329 /* If the register is set or already dead at PLACE, we needn't do
12330 anything with this note if it is still a REG_DEAD note.
12331 We can here if it is set at all, not if is it totally replace,
12332 which is what `dead_or_set_p' checks, so also check for it being
12335 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12337 unsigned int regno = REGNO (XEXP (note, 0));
12339 /* Similarly, if the instruction on which we want to place
12340 the note is a noop, we'll need do a global live update
12341 after we remove them in delete_noop_moves. */
12342 if (noop_move_p (place))
12344 SET_BIT (refresh_blocks, this_basic_block);
12348 if (dead_or_set_p (place, XEXP (note, 0))
12349 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12351 /* Unless the register previously died in PLACE, clear
12352 reg_last_death. [I no longer understand why this is
12354 if (reg_last_death[regno] != place)
12355 reg_last_death[regno] = 0;
12359 reg_last_death[regno] = place;
12361 /* If this is a death note for a hard reg that is occupying
12362 multiple registers, ensure that we are still using all
12363 parts of the object. If we find a piece of the object
12364 that is unused, we must arrange for an appropriate REG_DEAD
12365 note to be added for it. However, we can't just emit a USE
12366 and tag the note to it, since the register might actually
12367 be dead; so we recourse, and the recursive call then finds
12368 the previous insn that used this register. */
12370 if (place && regno < FIRST_PSEUDO_REGISTER
12371 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12373 unsigned int endregno
12374 = regno + HARD_REGNO_NREGS (regno,
12375 GET_MODE (XEXP (note, 0)));
12379 for (i = regno; i < endregno; i++)
12380 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12381 && ! find_regno_fusage (place, USE, i))
12382 || dead_or_set_regno_p (place, i))
12387 /* Put only REG_DEAD notes for pieces that are
12388 not already dead or set. */
12390 for (i = regno; i < endregno;
12391 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12393 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12394 basic_block bb = BASIC_BLOCK (this_basic_block);
12396 if (! dead_or_set_p (place, piece)
12397 && ! reg_bitfield_target_p (piece,
12401 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12403 distribute_notes (new_note, place, place,
12404 NULL_RTX, NULL_RTX, NULL_RTX);
12406 else if (! refers_to_regno_p (i, i + 1,
12407 PATTERN (place), 0)
12408 && ! find_regno_fusage (place, USE, i))
12409 for (tem = PREV_INSN (place); ;
12410 tem = PREV_INSN (tem))
12412 if (! INSN_P (tem))
12414 if (tem == bb->head)
12416 SET_BIT (refresh_blocks,
12423 if (dead_or_set_p (tem, piece)
12424 || reg_bitfield_target_p (piece,
12428 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12443 /* Any other notes should not be present at this point in the
12450 XEXP (note, 1) = REG_NOTES (place);
12451 REG_NOTES (place) = note;
12453 else if ((REG_NOTE_KIND (note) == REG_DEAD
12454 || REG_NOTE_KIND (note) == REG_UNUSED)
12455 && GET_CODE (XEXP (note, 0)) == REG)
12456 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12460 if ((REG_NOTE_KIND (note) == REG_DEAD
12461 || REG_NOTE_KIND (note) == REG_UNUSED)
12462 && GET_CODE (XEXP (note, 0)) == REG)
12463 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12465 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12466 REG_NOTE_KIND (note),
12468 REG_NOTES (place2));
12473 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12474 I3, I2, and I1 to new locations. This is also called in one case to
12475 add a link pointing at I3 when I3's destination is changed. */
12478 distribute_links (links)
12481 rtx link, next_link;
12483 for (link = links; link; link = next_link)
12489 next_link = XEXP (link, 1);
12491 /* If the insn that this link points to is a NOTE or isn't a single
12492 set, ignore it. In the latter case, it isn't clear what we
12493 can do other than ignore the link, since we can't tell which
12494 register it was for. Such links wouldn't be used by combine
12497 It is not possible for the destination of the target of the link to
12498 have been changed by combine. The only potential of this is if we
12499 replace I3, I2, and I1 by I3 and I2. But in that case the
12500 destination of I2 also remains unchanged. */
12502 if (GET_CODE (XEXP (link, 0)) == NOTE
12503 || (set = single_set (XEXP (link, 0))) == 0)
12506 reg = SET_DEST (set);
12507 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12508 || GET_CODE (reg) == SIGN_EXTRACT
12509 || GET_CODE (reg) == STRICT_LOW_PART)
12510 reg = XEXP (reg, 0);
12512 /* A LOG_LINK is defined as being placed on the first insn that uses
12513 a register and points to the insn that sets the register. Start
12514 searching at the next insn after the target of the link and stop
12515 when we reach a set of the register or the end of the basic block.
12517 Note that this correctly handles the link that used to point from
12518 I3 to I2. Also note that not much searching is typically done here
12519 since most links don't point very far away. */
12521 for (insn = NEXT_INSN (XEXP (link, 0));
12522 (insn && (this_basic_block == n_basic_blocks - 1
12523 || BLOCK_HEAD (this_basic_block + 1) != insn));
12524 insn = NEXT_INSN (insn))
12525 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12527 if (reg_referenced_p (reg, PATTERN (insn)))
12531 else if (GET_CODE (insn) == CALL_INSN
12532 && find_reg_fusage (insn, USE, reg))
12538 /* If we found a place to put the link, place it there unless there
12539 is already a link to the same insn as LINK at that point. */
12545 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12546 if (XEXP (link2, 0) == XEXP (link, 0))
12551 XEXP (link, 1) = LOG_LINKS (place);
12552 LOG_LINKS (place) = link;
12554 /* Set added_links_insn to the earliest insn we added a
12556 if (added_links_insn == 0
12557 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12558 added_links_insn = place;
12564 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12570 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12571 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12572 insn = NEXT_INSN (insn);
12574 if (INSN_UID (insn) > max_uid_cuid)
12577 return INSN_CUID (insn);
12581 dump_combine_stats (file)
12586 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12587 combine_attempts, combine_merges, combine_extras, combine_successes);
12591 dump_combine_total_stats (file)
12596 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12597 total_attempts, total_merges, total_extras, total_successes);