1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block in which we are performing combines. */
196 static basic_block this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((int *, int));
343 static void init_reg_last_arrays PARAMS ((void));
344 static void setup_incoming_promotions PARAMS ((void));
345 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
346 static int cant_combine_insn_p PARAMS ((rtx));
347 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
348 static int sets_function_arg_p PARAMS ((rtx));
349 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
350 static int contains_muldiv PARAMS ((rtx));
351 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
352 static void undo_all PARAMS ((void));
353 static void undo_commit PARAMS ((void));
354 static rtx *find_split_point PARAMS ((rtx *, rtx));
355 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
356 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
357 static rtx simplify_if_then_else PARAMS ((rtx));
358 static rtx simplify_set PARAMS ((rtx));
359 static rtx simplify_logical PARAMS ((rtx, int));
360 static rtx expand_compound_operation PARAMS ((rtx));
361 static rtx expand_field_assignment PARAMS ((rtx));
362 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
363 rtx, unsigned HOST_WIDE_INT, int,
365 static rtx extract_left_shift PARAMS ((rtx, int));
366 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
367 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
368 unsigned HOST_WIDE_INT *));
369 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
370 unsigned HOST_WIDE_INT, rtx, int));
371 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
372 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
373 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
374 static rtx make_field_assignment PARAMS ((rtx));
375 static rtx apply_distributive_law PARAMS ((rtx));
376 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
377 unsigned HOST_WIDE_INT));
378 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
379 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
380 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
381 enum rtx_code, HOST_WIDE_INT,
382 enum machine_mode, int *));
383 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
385 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
386 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
387 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
389 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
390 static void update_table_tick PARAMS ((rtx));
391 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
392 static void check_promoted_subreg PARAMS ((rtx, rtx));
393 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
394 static void record_dead_and_set_regs PARAMS ((rtx));
395 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
396 static rtx get_last_value PARAMS ((rtx));
397 static int use_crosses_set_p PARAMS ((rtx, int));
398 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
399 static int reg_dead_at_p PARAMS ((rtx, rtx));
400 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
401 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
402 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
403 static void distribute_links PARAMS ((rtx));
404 static void mark_used_regs_combine PARAMS ((rtx));
405 static int insn_cuid PARAMS ((rtx));
406 static void record_promoted_value PARAMS ((rtx, rtx));
407 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
408 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
410 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
411 insn. The substitution can be undone by undo_all. If INTO is already
412 set to NEWVAL, do not record this change. Because computing NEWVAL might
413 also call SUBST, we have to compute it before we put anything into
417 do_SUBST (into, newval)
423 if (oldval == newval)
426 /* We'd like to catch as many invalid transformations here as
427 possible. Unfortunately, there are way too many mode changes
428 that are perfectly valid, so we'd waste too much effort for
429 little gain doing the checks here. Focus on catching invalid
430 transformations involving integer constants. */
431 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
432 && GET_CODE (newval) == CONST_INT)
434 /* Sanity check that we're replacing oldval with a CONST_INT
435 that is a valid sign-extension for the original mode. */
436 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
440 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
441 CONST_INT is not valid, because after the replacement, the
442 original mode would be gone. Unfortunately, we can't tell
443 when do_SUBST is called to replace the operand thereof, so we
444 perform this test on oldval instead, checking whether an
445 invalid replacement took place before we got here. */
446 if ((GET_CODE (oldval) == SUBREG
447 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
448 || (GET_CODE (oldval) == ZERO_EXTEND
449 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
454 buf = undobuf.frees, undobuf.frees = buf->next;
456 buf = (struct undo *) xmalloc (sizeof (struct undo));
460 buf->old_contents.r = oldval;
463 buf->next = undobuf.undos, undobuf.undos = buf;
466 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
468 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
469 for the value of a HOST_WIDE_INT value (including CONST_INT) is
473 do_SUBST_INT (into, newval)
479 if (oldval == newval)
483 buf = undobuf.frees, undobuf.frees = buf->next;
485 buf = (struct undo *) xmalloc (sizeof (struct undo));
489 buf->old_contents.i = oldval;
492 buf->next = undobuf.undos, undobuf.undos = buf;
495 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
497 /* Main entry point for combiner. F is the first insn of the function.
498 NREGS is the first unused pseudo-reg number.
500 Return non-zero if the combiner has turned an indirect jump
501 instruction into a direct jump. */
503 combine_instructions (f, nregs)
512 rtx links, nextlinks;
514 int new_direct_jump_p = 0;
516 combine_attempts = 0;
519 combine_successes = 0;
521 combine_max_regno = nregs;
523 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
524 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
526 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
528 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
531 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
533 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
535 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
536 reg_last_set_nonzero_bits
537 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
538 reg_last_set_sign_bit_copies
539 = (char *) xmalloc (nregs * sizeof (char));
541 init_reg_last_arrays ();
543 init_recog_no_volatile ();
545 /* Compute maximum uid value so uid_cuid can be allocated. */
547 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
548 if (INSN_UID (insn) > i)
551 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
554 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
556 /* Don't use reg_nonzero_bits when computing it. This can cause problems
557 when, for example, we have j <<= 1 in a loop. */
559 nonzero_sign_valid = 0;
561 /* Compute the mapping from uids to cuids.
562 Cuids are numbers assigned to insns, like uids,
563 except that cuids increase monotonically through the code.
565 Scan all SETs and see if we can deduce anything about what
566 bits are known to be zero for some registers and how many copies
567 of the sign bit are known to exist for those registers.
569 Also set any known values so that we can use it while searching
570 for what bits are known to be set. */
574 /* We need to initialize it here, because record_dead_and_set_regs may call
576 subst_prev_insn = NULL_RTX;
578 setup_incoming_promotions ();
580 refresh_blocks = sbitmap_alloc (last_basic_block);
581 sbitmap_zero (refresh_blocks);
584 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
586 uid_cuid[INSN_UID (insn)] = ++i;
592 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
594 record_dead_and_set_regs (insn);
597 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
598 if (REG_NOTE_KIND (links) == REG_INC)
599 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
604 if (GET_CODE (insn) == CODE_LABEL)
608 nonzero_sign_valid = 1;
610 /* Now scan all the insns in forward order. */
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 FOR_EACH_BB (this_basic_block)
620 for (insn = this_basic_block->head;
621 insn != NEXT_INSN (this_basic_block->end);
622 insn = next ? next : NEXT_INSN (insn))
626 if (GET_CODE (insn) == CODE_LABEL)
629 else if (INSN_P (insn))
631 /* See if we know about function return values before this
632 insn based upon SUBREG flags. */
633 check_promoted_subreg (insn, PATTERN (insn));
635 /* Try this insn with each insn it links back to. */
637 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
638 if ((next = try_combine (insn, XEXP (links, 0),
639 NULL_RTX, &new_direct_jump_p)) != 0)
642 /* Try each sequence of three linked insns ending with this one. */
644 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
646 rtx link = XEXP (links, 0);
648 /* If the linked insn has been replaced by a note, then there
649 is no point in pursuing this chain any further. */
650 if (GET_CODE (link) == NOTE)
653 for (nextlinks = LOG_LINKS (link);
655 nextlinks = XEXP (nextlinks, 1))
656 if ((next = try_combine (insn, link,
658 &new_direct_jump_p)) != 0)
663 /* Try to combine a jump insn that uses CC0
664 with a preceding insn that sets CC0, and maybe with its
665 logical predecessor as well.
666 This is how we make decrement-and-branch insns.
667 We need this special code because data flow connections
668 via CC0 do not get entered in LOG_LINKS. */
670 if (GET_CODE (insn) == JUMP_INSN
671 && (prev = prev_nonnote_insn (insn)) != 0
672 && GET_CODE (prev) == INSN
673 && sets_cc0_p (PATTERN (prev)))
675 if ((next = try_combine (insn, prev,
676 NULL_RTX, &new_direct_jump_p)) != 0)
679 for (nextlinks = LOG_LINKS (prev); nextlinks;
680 nextlinks = XEXP (nextlinks, 1))
681 if ((next = try_combine (insn, prev,
683 &new_direct_jump_p)) != 0)
687 /* Do the same for an insn that explicitly references CC0. */
688 if (GET_CODE (insn) == INSN
689 && (prev = prev_nonnote_insn (insn)) != 0
690 && GET_CODE (prev) == INSN
691 && sets_cc0_p (PATTERN (prev))
692 && GET_CODE (PATTERN (insn)) == SET
693 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
695 if ((next = try_combine (insn, prev,
696 NULL_RTX, &new_direct_jump_p)) != 0)
699 for (nextlinks = LOG_LINKS (prev); nextlinks;
700 nextlinks = XEXP (nextlinks, 1))
701 if ((next = try_combine (insn, prev,
703 &new_direct_jump_p)) != 0)
707 /* Finally, see if any of the insns that this insn links to
708 explicitly references CC0. If so, try this insn, that insn,
709 and its predecessor if it sets CC0. */
710 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
711 if (GET_CODE (XEXP (links, 0)) == INSN
712 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
713 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
714 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
715 && GET_CODE (prev) == INSN
716 && sets_cc0_p (PATTERN (prev))
717 && (next = try_combine (insn, XEXP (links, 0),
718 prev, &new_direct_jump_p)) != 0)
722 /* Try combining an insn with two different insns whose results it
724 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
725 for (nextlinks = XEXP (links, 1); nextlinks;
726 nextlinks = XEXP (nextlinks, 1))
727 if ((next = try_combine (insn, XEXP (links, 0),
729 &new_direct_jump_p)) != 0)
732 if (GET_CODE (insn) != NOTE)
733 record_dead_and_set_regs (insn);
742 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
743 BASIC_BLOCK (i)->flags |= BB_DIRTY);
744 new_direct_jump_p |= purge_all_dead_edges (0);
745 delete_noop_moves (f);
747 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
748 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
749 | PROP_KILL_DEAD_CODE);
752 sbitmap_free (refresh_blocks);
753 free (reg_nonzero_bits);
754 free (reg_sign_bit_copies);
755 free (reg_last_death);
757 free (reg_last_set_value);
758 free (reg_last_set_table_tick);
759 free (reg_last_set_label);
760 free (reg_last_set_invalid);
761 free (reg_last_set_mode);
762 free (reg_last_set_nonzero_bits);
763 free (reg_last_set_sign_bit_copies);
767 struct undo *undo, *next;
768 for (undo = undobuf.frees; undo; undo = next)
776 total_attempts += combine_attempts;
777 total_merges += combine_merges;
778 total_extras += combine_extras;
779 total_successes += combine_successes;
781 nonzero_sign_valid = 0;
783 /* Make recognizer allow volatile MEMs again. */
786 return new_direct_jump_p;
789 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
792 init_reg_last_arrays ()
794 unsigned int nregs = combine_max_regno;
796 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
797 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
798 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
799 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
800 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
801 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
802 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
803 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
804 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
807 /* Set up any promoted values for incoming argument registers. */
810 setup_incoming_promotions ()
812 #ifdef PROMOTE_FUNCTION_ARGS
815 enum machine_mode mode;
817 rtx first = get_insns ();
819 #ifndef OUTGOING_REGNO
820 #define OUTGOING_REGNO(N) N
822 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
823 /* Check whether this register can hold an incoming pointer
824 argument. FUNCTION_ARG_REGNO_P tests outgoing register
825 numbers, so translate if necessary due to register windows. */
826 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
827 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
830 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
833 gen_rtx_CLOBBER (mode, const0_rtx)));
838 /* Called via note_stores. If X is a pseudo that is narrower than
839 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
841 If we are setting only a portion of X and we can't figure out what
842 portion, assume all bits will be used since we don't know what will
845 Similarly, set how many bits of X are known to be copies of the sign bit
846 at all locations in the function. This is the smallest number implied
850 set_nonzero_bits_and_sign_copies (x, set, data)
853 void *data ATTRIBUTE_UNUSED;
857 if (GET_CODE (x) == REG
858 && REGNO (x) >= FIRST_PSEUDO_REGISTER
859 /* If this register is undefined at the start of the file, we can't
860 say what its contents were. */
861 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
862 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
864 if (set == 0 || GET_CODE (set) == CLOBBER)
866 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
867 reg_sign_bit_copies[REGNO (x)] = 1;
871 /* If this is a complex assignment, see if we can convert it into a
872 simple assignment. */
873 set = expand_field_assignment (set);
875 /* If this is a simple assignment, or we have a paradoxical SUBREG,
876 set what we know about X. */
878 if (SET_DEST (set) == x
879 || (GET_CODE (SET_DEST (set)) == SUBREG
880 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
881 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
882 && SUBREG_REG (SET_DEST (set)) == x))
884 rtx src = SET_SRC (set);
886 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
887 /* If X is narrower than a word and SRC is a non-negative
888 constant that would appear negative in the mode of X,
889 sign-extend it for use in reg_nonzero_bits because some
890 machines (maybe most) will actually do the sign-extension
891 and this is the conservative approach.
893 ??? For 2.5, try to tighten up the MD files in this regard
894 instead of this kludge. */
896 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
897 && GET_CODE (src) == CONST_INT
899 && 0 != (INTVAL (src)
901 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
902 src = GEN_INT (INTVAL (src)
903 | ((HOST_WIDE_INT) (-1)
904 << GET_MODE_BITSIZE (GET_MODE (x))));
907 /* Don't call nonzero_bits if it cannot change anything. */
908 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
909 reg_nonzero_bits[REGNO (x)]
910 |= nonzero_bits (src, nonzero_bits_mode);
911 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
912 if (reg_sign_bit_copies[REGNO (x)] == 0
913 || reg_sign_bit_copies[REGNO (x)] > num)
914 reg_sign_bit_copies[REGNO (x)] = num;
918 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
919 reg_sign_bit_copies[REGNO (x)] = 1;
924 /* See if INSN can be combined into I3. PRED and SUCC are optionally
925 insns that were previously combined into I3 or that will be combined
926 into the merger of INSN and I3.
928 Return 0 if the combination is not allowed for any reason.
930 If the combination is allowed, *PDEST will be set to the single
931 destination of INSN and *PSRC to the single source, and this function
935 can_combine_p (insn, i3, pred, succ, pdest, psrc)
938 rtx pred ATTRIBUTE_UNUSED;
943 rtx set = 0, src, dest;
948 int all_adjacent = (succ ? (next_active_insn (insn) == succ
949 && next_active_insn (succ) == i3)
950 : next_active_insn (insn) == i3);
952 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
953 or a PARALLEL consisting of such a SET and CLOBBERs.
955 If INSN has CLOBBER parallel parts, ignore them for our processing.
956 By definition, these happen during the execution of the insn. When it
957 is merged with another insn, all bets are off. If they are, in fact,
958 needed and aren't also supplied in I3, they may be added by
959 recog_for_combine. Otherwise, it won't match.
961 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
964 Get the source and destination of INSN. If more than one, can't
967 if (GET_CODE (PATTERN (insn)) == SET)
968 set = PATTERN (insn);
969 else if (GET_CODE (PATTERN (insn)) == PARALLEL
970 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
972 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
974 rtx elt = XVECEXP (PATTERN (insn), 0, i);
976 switch (GET_CODE (elt))
978 /* This is important to combine floating point insns
981 /* Combining an isolated USE doesn't make sense.
982 We depend here on combinable_i3pat to reject them. */
983 /* The code below this loop only verifies that the inputs of
984 the SET in INSN do not change. We call reg_set_between_p
985 to verify that the REG in the USE does not change between
987 If the USE in INSN was for a pseudo register, the matching
988 insn pattern will likely match any register; combining this
989 with any other USE would only be safe if we knew that the
990 used registers have identical values, or if there was
991 something to tell them apart, e.g. different modes. For
992 now, we forgo such complicated tests and simply disallow
993 combining of USES of pseudo registers with any other USE. */
994 if (GET_CODE (XEXP (elt, 0)) == REG
995 && GET_CODE (PATTERN (i3)) == PARALLEL)
997 rtx i3pat = PATTERN (i3);
998 int i = XVECLEN (i3pat, 0) - 1;
999 unsigned int regno = REGNO (XEXP (elt, 0));
1003 rtx i3elt = XVECEXP (i3pat, 0, i);
1005 if (GET_CODE (i3elt) == USE
1006 && GET_CODE (XEXP (i3elt, 0)) == REG
1007 && (REGNO (XEXP (i3elt, 0)) == regno
1008 ? reg_set_between_p (XEXP (elt, 0),
1009 PREV_INSN (insn), i3)
1010 : regno >= FIRST_PSEUDO_REGISTER))
1017 /* We can ignore CLOBBERs. */
1022 /* Ignore SETs whose result isn't used but not those that
1023 have side-effects. */
1024 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1025 && ! side_effects_p (elt))
1028 /* If we have already found a SET, this is a second one and
1029 so we cannot combine with this insn. */
1037 /* Anything else means we can't combine. */
1043 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1044 so don't do anything with it. */
1045 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1054 set = expand_field_assignment (set);
1055 src = SET_SRC (set), dest = SET_DEST (set);
1057 /* Don't eliminate a store in the stack pointer. */
1058 if (dest == stack_pointer_rtx
1059 /* If we couldn't eliminate a field assignment, we can't combine. */
1060 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1061 /* Don't combine with an insn that sets a register to itself if it has
1062 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1063 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1064 /* Can't merge an ASM_OPERANDS. */
1065 || GET_CODE (src) == ASM_OPERANDS
1066 /* Can't merge a function call. */
1067 || GET_CODE (src) == CALL
1068 /* Don't eliminate a function call argument. */
1069 || (GET_CODE (i3) == CALL_INSN
1070 && (find_reg_fusage (i3, USE, dest)
1071 || (GET_CODE (dest) == REG
1072 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1073 && global_regs[REGNO (dest)])))
1074 /* Don't substitute into an incremented register. */
1075 || FIND_REG_INC_NOTE (i3, dest)
1076 || (succ && FIND_REG_INC_NOTE (succ, dest))
1078 /* Don't combine the end of a libcall into anything. */
1079 /* ??? This gives worse code, and appears to be unnecessary, since no
1080 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1081 use REG_RETVAL notes for noconflict blocks, but other code here
1082 makes sure that those insns don't disappear. */
1083 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1085 /* Make sure that DEST is not used after SUCC but before I3. */
1086 || (succ && ! all_adjacent
1087 && reg_used_between_p (dest, succ, i3))
1088 /* Make sure that the value that is to be substituted for the register
1089 does not use any registers whose values alter in between. However,
1090 If the insns are adjacent, a use can't cross a set even though we
1091 think it might (this can happen for a sequence of insns each setting
1092 the same destination; reg_last_set of that register might point to
1093 a NOTE). If INSN has a REG_EQUIV note, the register is always
1094 equivalent to the memory so the substitution is valid even if there
1095 are intervening stores. Also, don't move a volatile asm or
1096 UNSPEC_VOLATILE across any other insns. */
1098 && (((GET_CODE (src) != MEM
1099 || ! find_reg_note (insn, REG_EQUIV, src))
1100 && use_crosses_set_p (src, INSN_CUID (insn)))
1101 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1102 || GET_CODE (src) == UNSPEC_VOLATILE))
1103 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1104 better register allocation by not doing the combine. */
1105 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1106 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1107 /* Don't combine across a CALL_INSN, because that would possibly
1108 change whether the life span of some REGs crosses calls or not,
1109 and it is a pain to update that information.
1110 Exception: if source is a constant, moving it later can't hurt.
1111 Accept that special case, because it helps -fforce-addr a lot. */
1112 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1115 /* DEST must either be a REG or CC0. */
1116 if (GET_CODE (dest) == REG)
1118 /* If register alignment is being enforced for multi-word items in all
1119 cases except for parameters, it is possible to have a register copy
1120 insn referencing a hard register that is not allowed to contain the
1121 mode being copied and which would not be valid as an operand of most
1122 insns. Eliminate this problem by not combining with such an insn.
1124 Also, on some machines we don't want to extend the life of a hard
1127 if (GET_CODE (src) == REG
1128 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1129 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1130 /* Don't extend the life of a hard register unless it is
1131 user variable (if we have few registers) or it can't
1132 fit into the desired register (meaning something special
1134 Also avoid substituting a return register into I3, because
1135 reload can't handle a conflict with constraints of other
1137 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1138 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1141 else if (GET_CODE (dest) != CC0)
1144 /* Don't substitute for a register intended as a clobberable operand.
1145 Similarly, don't substitute an expression containing a register that
1146 will be clobbered in I3. */
1147 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1148 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1149 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1150 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1152 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1155 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1156 or not), reject, unless nothing volatile comes between it and I3 */
1158 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1160 /* Make sure succ doesn't contain a volatile reference. */
1161 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1164 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1165 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1169 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1170 to be an explicit register variable, and was chosen for a reason. */
1172 if (GET_CODE (src) == ASM_OPERANDS
1173 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1176 /* If there are any volatile insns between INSN and I3, reject, because
1177 they might affect machine state. */
1179 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1180 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1183 /* If INSN or I2 contains an autoincrement or autodecrement,
1184 make sure that register is not used between there and I3,
1185 and not already used in I3 either.
1186 Also insist that I3 not be a jump; if it were one
1187 and the incremented register were spilled, we would lose. */
1190 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1191 if (REG_NOTE_KIND (link) == REG_INC
1192 && (GET_CODE (i3) == JUMP_INSN
1193 || reg_used_between_p (XEXP (link, 0), insn, i3)
1194 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1199 /* Don't combine an insn that follows a CC0-setting insn.
1200 An insn that uses CC0 must not be separated from the one that sets it.
1201 We do, however, allow I2 to follow a CC0-setting insn if that insn
1202 is passed as I1; in that case it will be deleted also.
1203 We also allow combining in this case if all the insns are adjacent
1204 because that would leave the two CC0 insns adjacent as well.
1205 It would be more logical to test whether CC0 occurs inside I1 or I2,
1206 but that would be much slower, and this ought to be equivalent. */
1208 p = prev_nonnote_insn (insn);
1209 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1214 /* If we get here, we have passed all the tests and the combination is
1223 /* Check if PAT is an insn - or a part of it - used to set up an
1224 argument for a function in a hard register. */
1227 sets_function_arg_p (pat)
1233 switch (GET_CODE (pat))
1236 return sets_function_arg_p (PATTERN (pat));
1239 for (i = XVECLEN (pat, 0); --i >= 0;)
1240 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1246 inner_dest = SET_DEST (pat);
1247 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1248 || GET_CODE (inner_dest) == SUBREG
1249 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1250 inner_dest = XEXP (inner_dest, 0);
1252 return (GET_CODE (inner_dest) == REG
1253 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1254 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1263 /* LOC is the location within I3 that contains its pattern or the component
1264 of a PARALLEL of the pattern. We validate that it is valid for combining.
1266 One problem is if I3 modifies its output, as opposed to replacing it
1267 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1268 so would produce an insn that is not equivalent to the original insns.
1272 (set (reg:DI 101) (reg:DI 100))
1273 (set (subreg:SI (reg:DI 101) 0) <foo>)
1275 This is NOT equivalent to:
1277 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1278 (set (reg:DI 101) (reg:DI 100))])
1280 Not only does this modify 100 (in which case it might still be valid
1281 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1283 We can also run into a problem if I2 sets a register that I1
1284 uses and I1 gets directly substituted into I3 (not via I2). In that
1285 case, we would be getting the wrong value of I2DEST into I3, so we
1286 must reject the combination. This case occurs when I2 and I1 both
1287 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1288 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1289 of a SET must prevent combination from occurring.
1291 Before doing the above check, we first try to expand a field assignment
1292 into a set of logical operations.
1294 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1295 we place a register that is both set and used within I3. If more than one
1296 such register is detected, we fail.
1298 Return 1 if the combination is valid, zero otherwise. */
1301 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1307 rtx *pi3dest_killed;
1311 if (GET_CODE (x) == SET)
1313 rtx set = expand_field_assignment (x);
1314 rtx dest = SET_DEST (set);
1315 rtx src = SET_SRC (set);
1316 rtx inner_dest = dest;
1319 rtx inner_src = src;
1324 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1325 || GET_CODE (inner_dest) == SUBREG
1326 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1327 inner_dest = XEXP (inner_dest, 0);
1329 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1332 while (GET_CODE (inner_src) == STRICT_LOW_PART
1333 || GET_CODE (inner_src) == SUBREG
1334 || GET_CODE (inner_src) == ZERO_EXTRACT)
1335 inner_src = XEXP (inner_src, 0);
1337 /* If it is better that two different modes keep two different pseudos,
1338 avoid combining them. This avoids producing the following pattern
1340 (set (subreg:SI (reg/v:QI 21) 0)
1341 (lshiftrt:SI (reg/v:SI 20)
1343 If that were made, reload could not handle the pair of
1344 reg 20/21, since it would try to get any GENERAL_REGS
1345 but some of them don't handle QImode. */
1347 if (rtx_equal_p (inner_src, i2dest)
1348 && GET_CODE (inner_dest) == REG
1349 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1353 /* Check for the case where I3 modifies its output, as
1355 if ((inner_dest != dest
1356 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1357 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1359 /* This is the same test done in can_combine_p except we can't test
1360 all_adjacent; we don't have to, since this instruction will stay
1361 in place, thus we are not considering increasing the lifetime of
1364 Also, if this insn sets a function argument, combining it with
1365 something that might need a spill could clobber a previous
1366 function argument; the all_adjacent test in can_combine_p also
1367 checks this; here, we do a more specific test for this case. */
1369 || (GET_CODE (inner_dest) == REG
1370 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1371 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1372 GET_MODE (inner_dest))))
1373 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1376 /* If DEST is used in I3, it is being killed in this insn,
1377 so record that for later.
1378 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1379 STACK_POINTER_REGNUM, since these are always considered to be
1380 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1381 if (pi3dest_killed && GET_CODE (dest) == REG
1382 && reg_referenced_p (dest, PATTERN (i3))
1383 && REGNO (dest) != FRAME_POINTER_REGNUM
1384 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1385 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1387 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1388 && (REGNO (dest) != ARG_POINTER_REGNUM
1389 || ! fixed_regs [REGNO (dest)])
1391 && REGNO (dest) != STACK_POINTER_REGNUM)
1393 if (*pi3dest_killed)
1396 *pi3dest_killed = dest;
1400 else if (GET_CODE (x) == PARALLEL)
1404 for (i = 0; i < XVECLEN (x, 0); i++)
1405 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1406 i1_not_in_src, pi3dest_killed))
1413 /* Return 1 if X is an arithmetic expression that contains a multiplication
1414 and division. We don't count multiplications by powers of two here. */
1420 switch (GET_CODE (x))
1422 case MOD: case DIV: case UMOD: case UDIV:
1426 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1427 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1429 switch (GET_RTX_CLASS (GET_CODE (x)))
1431 case 'c': case '<': case '2':
1432 return contains_muldiv (XEXP (x, 0))
1433 || contains_muldiv (XEXP (x, 1));
1436 return contains_muldiv (XEXP (x, 0));
1444 /* Determine whether INSN can be used in a combination. Return nonzero if
1445 not. This is used in try_combine to detect early some cases where we
1446 can't perform combinations. */
1449 cant_combine_insn_p (insn)
1455 /* If this isn't really an insn, we can't do anything.
1456 This can occur when flow deletes an insn that it has merged into an
1457 auto-increment address. */
1458 if (! INSN_P (insn))
1461 /* Never combine loads and stores involving hard regs. The register
1462 allocator can usually handle such reg-reg moves by tying. If we allow
1463 the combiner to make substitutions of hard regs, we risk aborting in
1464 reload on machines that have SMALL_REGISTER_CLASSES.
1465 As an exception, we allow combinations involving fixed regs; these are
1466 not available to the register allocator so there's no risk involved. */
1468 set = single_set (insn);
1471 src = SET_SRC (set);
1472 dest = SET_DEST (set);
1473 if (GET_CODE (src) == SUBREG)
1474 src = SUBREG_REG (src);
1475 if (GET_CODE (dest) == SUBREG)
1476 dest = SUBREG_REG (dest);
1477 if (REG_P (src) && REG_P (dest)
1478 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1479 && ! fixed_regs[REGNO (src)])
1480 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1481 && ! fixed_regs[REGNO (dest)])))
1487 /* Try to combine the insns I1 and I2 into I3.
1488 Here I1 and I2 appear earlier than I3.
1489 I1 can be zero; then we combine just I2 into I3.
1491 If we are combining three insns and the resulting insn is not recognized,
1492 try splitting it into two insns. If that happens, I2 and I3 are retained
1493 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1496 Return 0 if the combination does not work. Then nothing is changed.
1497 If we did the combination, return the insn at which combine should
1500 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1501 new direct jump instruction. */
1504 try_combine (i3, i2, i1, new_direct_jump_p)
1506 int *new_direct_jump_p;
1508 /* New patterns for I3 and I2, respectively. */
1509 rtx newpat, newi2pat = 0;
1510 int substed_i2 = 0, substed_i1 = 0;
1511 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1512 int added_sets_1, added_sets_2;
1513 /* Total number of SETs to put into I3. */
1515 /* Nonzero is I2's body now appears in I3. */
1517 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1518 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1519 /* Contains I3 if the destination of I3 is used in its source, which means
1520 that the old life of I3 is being killed. If that usage is placed into
1521 I2 and not in I3, a REG_DEAD note must be made. */
1522 rtx i3dest_killed = 0;
1523 /* SET_DEST and SET_SRC of I2 and I1. */
1524 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1525 /* PATTERN (I2), or a copy of it in certain cases. */
1527 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1528 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1529 int i1_feeds_i3 = 0;
1530 /* Notes that must be added to REG_NOTES in I3 and I2. */
1531 rtx new_i3_notes, new_i2_notes;
1532 /* Notes that we substituted I3 into I2 instead of the normal case. */
1533 int i3_subst_into_i2 = 0;
1534 /* Notes that I1, I2 or I3 is a MULT operation. */
1542 /* Exit early if one of the insns involved can't be used for
1544 if (cant_combine_insn_p (i3)
1545 || cant_combine_insn_p (i2)
1546 || (i1 && cant_combine_insn_p (i1))
1547 /* We also can't do anything if I3 has a
1548 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1551 /* ??? This gives worse code, and appears to be unnecessary, since no
1552 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1553 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1559 undobuf.other_insn = 0;
1561 /* Reset the hard register usage information. */
1562 CLEAR_HARD_REG_SET (newpat_used_regs);
1564 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1565 code below, set I1 to be the earlier of the two insns. */
1566 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1567 temp = i1, i1 = i2, i2 = temp;
1569 added_links_insn = 0;
1571 /* First check for one important special-case that the code below will
1572 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1573 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1574 we may be able to replace that destination with the destination of I3.
1575 This occurs in the common code where we compute both a quotient and
1576 remainder into a structure, in which case we want to do the computation
1577 directly into the structure to avoid register-register copies.
1579 Note that this case handles both multiple sets in I2 and also
1580 cases where I2 has a number of CLOBBER or PARALLELs.
1582 We make very conservative checks below and only try to handle the
1583 most common cases of this. For example, we only handle the case
1584 where I2 and I3 are adjacent to avoid making difficult register
1587 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1588 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1589 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1590 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1591 && GET_CODE (PATTERN (i2)) == PARALLEL
1592 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1593 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1594 below would need to check what is inside (and reg_overlap_mentioned_p
1595 doesn't support those codes anyway). Don't allow those destinations;
1596 the resulting insn isn't likely to be recognized anyway. */
1597 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1598 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1599 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1600 SET_DEST (PATTERN (i3)))
1601 && next_real_insn (i2) == i3)
1603 rtx p2 = PATTERN (i2);
1605 /* Make sure that the destination of I3,
1606 which we are going to substitute into one output of I2,
1607 is not used within another output of I2. We must avoid making this:
1608 (parallel [(set (mem (reg 69)) ...)
1609 (set (reg 69) ...)])
1610 which is not well-defined as to order of actions.
1611 (Besides, reload can't handle output reloads for this.)
1613 The problem can also happen if the dest of I3 is a memory ref,
1614 if another dest in I2 is an indirect memory ref. */
1615 for (i = 0; i < XVECLEN (p2, 0); i++)
1616 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1617 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1618 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1619 SET_DEST (XVECEXP (p2, 0, i))))
1622 if (i == XVECLEN (p2, 0))
1623 for (i = 0; i < XVECLEN (p2, 0); i++)
1624 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1625 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1626 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1631 subst_low_cuid = INSN_CUID (i2);
1633 added_sets_2 = added_sets_1 = 0;
1634 i2dest = SET_SRC (PATTERN (i3));
1636 /* Replace the dest in I2 with our dest and make the resulting
1637 insn the new pattern for I3. Then skip to where we
1638 validate the pattern. Everything was set up above. */
1639 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1640 SET_DEST (PATTERN (i3)));
1643 i3_subst_into_i2 = 1;
1644 goto validate_replacement;
1648 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1649 one of those words to another constant, merge them by making a new
1652 && (temp = single_set (i2)) != 0
1653 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1654 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1655 && GET_CODE (SET_DEST (temp)) == REG
1656 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1657 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1658 && GET_CODE (PATTERN (i3)) == SET
1659 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1660 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1661 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1662 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1663 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1665 HOST_WIDE_INT lo, hi;
1667 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1668 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1671 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1672 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1675 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1677 /* We don't handle the case of the target word being wider
1678 than a host wide int. */
1679 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1682 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1683 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1684 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1686 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1687 hi = INTVAL (SET_SRC (PATTERN (i3)));
1688 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1690 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1691 >> (HOST_BITS_PER_WIDE_INT - 1));
1693 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1694 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1695 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1696 (INTVAL (SET_SRC (PATTERN (i3)))));
1698 hi = lo < 0 ? -1 : 0;
1701 /* We don't handle the case of the higher word not fitting
1702 entirely in either hi or lo. */
1707 subst_low_cuid = INSN_CUID (i2);
1708 added_sets_2 = added_sets_1 = 0;
1709 i2dest = SET_DEST (temp);
1711 SUBST (SET_SRC (temp),
1712 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1714 newpat = PATTERN (i2);
1715 goto validate_replacement;
1719 /* If we have no I1 and I2 looks like:
1720 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1722 make up a dummy I1 that is
1725 (set (reg:CC X) (compare:CC Y (const_int 0)))
1727 (We can ignore any trailing CLOBBERs.)
1729 This undoes a previous combination and allows us to match a branch-and-
1732 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1733 && XVECLEN (PATTERN (i2), 0) >= 2
1734 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1735 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1737 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1738 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1739 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1740 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1741 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1742 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1744 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1745 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1750 /* We make I1 with the same INSN_UID as I2. This gives it
1751 the same INSN_CUID for value tracking. Our fake I1 will
1752 never appear in the insn stream so giving it the same INSN_UID
1753 as I2 will not cause a problem. */
1755 subst_prev_insn = i1
1756 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1757 BLOCK_FOR_INSN (i2), INSN_SCOPE (i2),
1758 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1761 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1762 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1763 SET_DEST (PATTERN (i1)));
1768 /* Verify that I2 and I1 are valid for combining. */
1769 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1770 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1776 /* Record whether I2DEST is used in I2SRC and similarly for the other
1777 cases. Knowing this will help in register status updating below. */
1778 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1779 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1780 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1782 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1784 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1786 /* Ensure that I3's pattern can be the destination of combines. */
1787 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1788 i1 && i2dest_in_i1src && i1_feeds_i3,
1795 /* See if any of the insns is a MULT operation. Unless one is, we will
1796 reject a combination that is, since it must be slower. Be conservative
1798 if (GET_CODE (i2src) == MULT
1799 || (i1 != 0 && GET_CODE (i1src) == MULT)
1800 || (GET_CODE (PATTERN (i3)) == SET
1801 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1804 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1805 We used to do this EXCEPT in one case: I3 has a post-inc in an
1806 output operand. However, that exception can give rise to insns like
1808 which is a famous insn on the PDP-11 where the value of r3 used as the
1809 source was model-dependent. Avoid this sort of thing. */
1812 if (!(GET_CODE (PATTERN (i3)) == SET
1813 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1814 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1815 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1816 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1817 /* It's not the exception. */
1820 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1821 if (REG_NOTE_KIND (link) == REG_INC
1822 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1824 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1831 /* See if the SETs in I1 or I2 need to be kept around in the merged
1832 instruction: whenever the value set there is still needed past I3.
1833 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1835 For the SET in I1, we have two cases: If I1 and I2 independently
1836 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1837 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1838 in I1 needs to be kept around unless I1DEST dies or is set in either
1839 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1840 I1DEST. If so, we know I1 feeds into I2. */
1842 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1845 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1846 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1848 /* If the set in I2 needs to be kept around, we must make a copy of
1849 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1850 PATTERN (I2), we are only substituting for the original I1DEST, not into
1851 an already-substituted copy. This also prevents making self-referential
1852 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1855 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1856 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1860 i2pat = copy_rtx (i2pat);
1864 /* Substitute in the latest insn for the regs set by the earlier ones. */
1866 maxreg = max_reg_num ();
1870 /* It is possible that the source of I2 or I1 may be performing an
1871 unneeded operation, such as a ZERO_EXTEND of something that is known
1872 to have the high part zero. Handle that case by letting subst look at
1873 the innermost one of them.
1875 Another way to do this would be to have a function that tries to
1876 simplify a single insn instead of merging two or more insns. We don't
1877 do this because of the potential of infinite loops and because
1878 of the potential extra memory required. However, doing it the way
1879 we are is a bit of a kludge and doesn't catch all cases.
1881 But only do this if -fexpensive-optimizations since it slows things down
1882 and doesn't usually win. */
1884 if (flag_expensive_optimizations)
1886 /* Pass pc_rtx so no substitutions are done, just simplifications.
1887 The cases that we are interested in here do not involve the few
1888 cases were is_replaced is checked. */
1891 subst_low_cuid = INSN_CUID (i1);
1892 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1896 subst_low_cuid = INSN_CUID (i2);
1897 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1902 /* Many machines that don't use CC0 have insns that can both perform an
1903 arithmetic operation and set the condition code. These operations will
1904 be represented as a PARALLEL with the first element of the vector
1905 being a COMPARE of an arithmetic operation with the constant zero.
1906 The second element of the vector will set some pseudo to the result
1907 of the same arithmetic operation. If we simplify the COMPARE, we won't
1908 match such a pattern and so will generate an extra insn. Here we test
1909 for this case, where both the comparison and the operation result are
1910 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1911 I2SRC. Later we will make the PARALLEL that contains I2. */
1913 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1914 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1915 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1916 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1918 #ifdef EXTRA_CC_MODES
1920 enum machine_mode compare_mode;
1923 newpat = PATTERN (i3);
1924 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1928 #ifdef EXTRA_CC_MODES
1929 /* See if a COMPARE with the operand we substituted in should be done
1930 with the mode that is currently being used. If not, do the same
1931 processing we do in `subst' for a SET; namely, if the destination
1932 is used only once, try to replace it with a register of the proper
1933 mode and also replace the COMPARE. */
1934 if (undobuf.other_insn == 0
1935 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1936 &undobuf.other_insn))
1937 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1939 != GET_MODE (SET_DEST (newpat))))
1941 unsigned int regno = REGNO (SET_DEST (newpat));
1942 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1944 if (regno < FIRST_PSEUDO_REGISTER
1945 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1946 && ! REG_USERVAR_P (SET_DEST (newpat))))
1948 if (regno >= FIRST_PSEUDO_REGISTER)
1949 SUBST (regno_reg_rtx[regno], new_dest);
1951 SUBST (SET_DEST (newpat), new_dest);
1952 SUBST (XEXP (*cc_use, 0), new_dest);
1953 SUBST (SET_SRC (newpat),
1954 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1957 undobuf.other_insn = 0;
1964 n_occurrences = 0; /* `subst' counts here */
1966 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1967 need to make a unique copy of I2SRC each time we substitute it
1968 to avoid self-referential rtl. */
1970 subst_low_cuid = INSN_CUID (i2);
1971 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1972 ! i1_feeds_i3 && i1dest_in_i1src);
1975 /* Record whether i2's body now appears within i3's body. */
1976 i2_is_used = n_occurrences;
1979 /* If we already got a failure, don't try to do more. Otherwise,
1980 try to substitute in I1 if we have it. */
1982 if (i1 && GET_CODE (newpat) != CLOBBER)
1984 /* Before we can do this substitution, we must redo the test done
1985 above (see detailed comments there) that ensures that I1DEST
1986 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1988 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1996 subst_low_cuid = INSN_CUID (i1);
1997 newpat = subst (newpat, i1dest, i1src, 0, 0);
2001 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2002 to count all the ways that I2SRC and I1SRC can be used. */
2003 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2004 && i2_is_used + added_sets_2 > 1)
2005 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2006 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2008 /* Fail if we tried to make a new register (we used to abort, but there's
2009 really no reason to). */
2010 || max_reg_num () != maxreg
2011 /* Fail if we couldn't do something and have a CLOBBER. */
2012 || GET_CODE (newpat) == CLOBBER
2013 /* Fail if this new pattern is a MULT and we didn't have one before
2014 at the outer level. */
2015 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2022 /* If the actions of the earlier insns must be kept
2023 in addition to substituting them into the latest one,
2024 we must make a new PARALLEL for the latest insn
2025 to hold additional the SETs. */
2027 if (added_sets_1 || added_sets_2)
2031 if (GET_CODE (newpat) == PARALLEL)
2033 rtvec old = XVEC (newpat, 0);
2034 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2035 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2036 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2037 sizeof (old->elem[0]) * old->num_elem);
2042 total_sets = 1 + added_sets_1 + added_sets_2;
2043 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2044 XVECEXP (newpat, 0, 0) = old;
2048 XVECEXP (newpat, 0, --total_sets)
2049 = (GET_CODE (PATTERN (i1)) == PARALLEL
2050 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2054 /* If there is no I1, use I2's body as is. We used to also not do
2055 the subst call below if I2 was substituted into I3,
2056 but that could lose a simplification. */
2058 XVECEXP (newpat, 0, --total_sets) = i2pat;
2060 /* See comment where i2pat is assigned. */
2061 XVECEXP (newpat, 0, --total_sets)
2062 = subst (i2pat, i1dest, i1src, 0, 0);
2066 /* We come here when we are replacing a destination in I2 with the
2067 destination of I3. */
2068 validate_replacement:
2070 /* Note which hard regs this insn has as inputs. */
2071 mark_used_regs_combine (newpat);
2073 /* Is the result of combination a valid instruction? */
2074 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2076 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2077 the second SET's destination is a register that is unused. In that case,
2078 we just need the first SET. This can occur when simplifying a divmod
2079 insn. We *must* test for this case here because the code below that
2080 splits two independent SETs doesn't handle this case correctly when it
2081 updates the register status. Also check the case where the first
2082 SET's destination is unused. That would not cause incorrect code, but
2083 does cause an unneeded insn to remain. */
2085 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2086 && XVECLEN (newpat, 0) == 2
2087 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2088 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2089 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2090 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2091 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2092 && asm_noperands (newpat) < 0)
2094 newpat = XVECEXP (newpat, 0, 0);
2095 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2098 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2099 && XVECLEN (newpat, 0) == 2
2100 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2101 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2102 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2103 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2104 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2105 && asm_noperands (newpat) < 0)
2107 newpat = XVECEXP (newpat, 0, 1);
2108 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2111 /* If we were combining three insns and the result is a simple SET
2112 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2113 insns. There are two ways to do this. It can be split using a
2114 machine-specific method (like when you have an addition of a large
2115 constant) or by combine in the function find_split_point. */
2117 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2118 && asm_noperands (newpat) < 0)
2120 rtx m_split, *split;
2121 rtx ni2dest = i2dest;
2123 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2124 use I2DEST as a scratch register will help. In the latter case,
2125 convert I2DEST to the mode of the source of NEWPAT if we can. */
2127 m_split = split_insns (newpat, i3);
2129 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2130 inputs of NEWPAT. */
2132 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2133 possible to try that as a scratch reg. This would require adding
2134 more code to make it work though. */
2136 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2138 /* If I2DEST is a hard register or the only use of a pseudo,
2139 we can change its mode. */
2140 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2141 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2142 && GET_CODE (i2dest) == REG
2143 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2144 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2145 && ! REG_USERVAR_P (i2dest))))
2146 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2149 m_split = split_insns (gen_rtx_PARALLEL
2151 gen_rtvec (2, newpat,
2152 gen_rtx_CLOBBER (VOIDmode,
2155 /* If the split with the mode-changed register didn't work, try
2156 the original register. */
2157 if (! m_split && ni2dest != i2dest)
2160 m_split = split_insns (gen_rtx_PARALLEL
2162 gen_rtvec (2, newpat,
2163 gen_rtx_CLOBBER (VOIDmode,
2169 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2171 m_split = PATTERN (m_split);
2172 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2173 if (insn_code_number >= 0)
2176 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2177 && (next_real_insn (i2) == i3
2178 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2181 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2182 newi2pat = PATTERN (m_split);
2184 i3set = single_set (NEXT_INSN (m_split));
2185 i2set = single_set (m_split);
2187 /* In case we changed the mode of I2DEST, replace it in the
2188 pseudo-register table here. We can't do it above in case this
2189 code doesn't get executed and we do a split the other way. */
2191 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2192 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2194 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2196 /* If I2 or I3 has multiple SETs, we won't know how to track
2197 register status, so don't use these insns. If I2's destination
2198 is used between I2 and I3, we also can't use these insns. */
2200 if (i2_code_number >= 0 && i2set && i3set
2201 && (next_real_insn (i2) == i3
2202 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2203 insn_code_number = recog_for_combine (&newi3pat, i3,
2205 if (insn_code_number >= 0)
2208 /* It is possible that both insns now set the destination of I3.
2209 If so, we must show an extra use of it. */
2211 if (insn_code_number >= 0)
2213 rtx new_i3_dest = SET_DEST (i3set);
2214 rtx new_i2_dest = SET_DEST (i2set);
2216 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2217 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2218 || GET_CODE (new_i3_dest) == SUBREG)
2219 new_i3_dest = XEXP (new_i3_dest, 0);
2221 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2222 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2223 || GET_CODE (new_i2_dest) == SUBREG)
2224 new_i2_dest = XEXP (new_i2_dest, 0);
2226 if (GET_CODE (new_i3_dest) == REG
2227 && GET_CODE (new_i2_dest) == REG
2228 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2229 REG_N_SETS (REGNO (new_i2_dest))++;
2233 /* If we can split it and use I2DEST, go ahead and see if that
2234 helps things be recognized. Verify that none of the registers
2235 are set between I2 and I3. */
2236 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2238 && GET_CODE (i2dest) == REG
2240 /* We need I2DEST in the proper mode. If it is a hard register
2241 or the only use of a pseudo, we can change its mode. */
2242 && (GET_MODE (*split) == GET_MODE (i2dest)
2243 || GET_MODE (*split) == VOIDmode
2244 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2245 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2246 && ! REG_USERVAR_P (i2dest)))
2247 && (next_real_insn (i2) == i3
2248 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2249 /* We can't overwrite I2DEST if its value is still used by
2251 && ! reg_referenced_p (i2dest, newpat))
2253 rtx newdest = i2dest;
2254 enum rtx_code split_code = GET_CODE (*split);
2255 enum machine_mode split_mode = GET_MODE (*split);
2257 /* Get NEWDEST as a register in the proper mode. We have already
2258 validated that we can do this. */
2259 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2261 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2263 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2264 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2267 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2268 an ASHIFT. This can occur if it was inside a PLUS and hence
2269 appeared to be a memory address. This is a kludge. */
2270 if (split_code == MULT
2271 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2272 && INTVAL (XEXP (*split, 1)) > 0
2273 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2275 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2276 XEXP (*split, 0), GEN_INT (i)));
2277 /* Update split_code because we may not have a multiply
2279 split_code = GET_CODE (*split);
2282 #ifdef INSN_SCHEDULING
2283 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2284 be written as a ZERO_EXTEND. */
2285 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2286 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2287 SUBREG_REG (*split)));
2290 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2291 SUBST (*split, newdest);
2292 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2294 /* If the split point was a MULT and we didn't have one before,
2295 don't use one now. */
2296 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2297 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2301 /* Check for a case where we loaded from memory in a narrow mode and
2302 then sign extended it, but we need both registers. In that case,
2303 we have a PARALLEL with both loads from the same memory location.
2304 We can split this into a load from memory followed by a register-register
2305 copy. This saves at least one insn, more if register allocation can
2308 We cannot do this if the destination of the second assignment is
2309 a register that we have already assumed is zero-extended. Similarly
2310 for a SUBREG of such a register. */
2312 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2313 && GET_CODE (newpat) == PARALLEL
2314 && XVECLEN (newpat, 0) == 2
2315 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2316 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2317 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2318 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2319 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2320 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2322 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2323 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2324 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2325 (GET_CODE (temp) == REG
2326 && reg_nonzero_bits[REGNO (temp)] != 0
2327 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2328 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2329 && (reg_nonzero_bits[REGNO (temp)]
2330 != GET_MODE_MASK (word_mode))))
2331 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2332 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2333 (GET_CODE (temp) == REG
2334 && reg_nonzero_bits[REGNO (temp)] != 0
2335 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2336 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2337 && (reg_nonzero_bits[REGNO (temp)]
2338 != GET_MODE_MASK (word_mode)))))
2339 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2340 SET_SRC (XVECEXP (newpat, 0, 1)))
2341 && ! find_reg_note (i3, REG_UNUSED,
2342 SET_DEST (XVECEXP (newpat, 0, 0))))
2346 newi2pat = XVECEXP (newpat, 0, 0);
2347 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2348 newpat = XVECEXP (newpat, 0, 1);
2349 SUBST (SET_SRC (newpat),
2350 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2351 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2353 if (i2_code_number >= 0)
2354 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2356 if (insn_code_number >= 0)
2361 /* If we will be able to accept this, we have made a change to the
2362 destination of I3. This can invalidate a LOG_LINKS pointing
2363 to I3. No other part of combine.c makes such a transformation.
2365 The new I3 will have a destination that was previously the
2366 destination of I1 or I2 and which was used in i2 or I3. Call
2367 distribute_links to make a LOG_LINK from the next use of
2368 that destination. */
2370 PATTERN (i3) = newpat;
2371 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2373 /* I3 now uses what used to be its destination and which is
2374 now I2's destination. That means we need a LOG_LINK from
2375 I3 to I2. But we used to have one, so we still will.
2377 However, some later insn might be using I2's dest and have
2378 a LOG_LINK pointing at I3. We must remove this link.
2379 The simplest way to remove the link is to point it at I1,
2380 which we know will be a NOTE. */
2382 for (insn = NEXT_INSN (i3);
2383 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2384 || insn != this_basic_block->next_bb->head);
2385 insn = NEXT_INSN (insn))
2387 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2389 for (link = LOG_LINKS (insn); link;
2390 link = XEXP (link, 1))
2391 if (XEXP (link, 0) == i3)
2392 XEXP (link, 0) = i1;
2400 /* Similarly, check for a case where we have a PARALLEL of two independent
2401 SETs but we started with three insns. In this case, we can do the sets
2402 as two separate insns. This case occurs when some SET allows two
2403 other insns to combine, but the destination of that SET is still live. */
2405 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2406 && GET_CODE (newpat) == PARALLEL
2407 && XVECLEN (newpat, 0) == 2
2408 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2409 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2410 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2411 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2412 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2413 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2414 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2416 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2417 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2418 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2419 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2420 XVECEXP (newpat, 0, 0))
2421 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2422 XVECEXP (newpat, 0, 1))
2423 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2424 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2426 /* Normally, it doesn't matter which of the two is done first,
2427 but it does if one references cc0. In that case, it has to
2430 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2432 newi2pat = XVECEXP (newpat, 0, 0);
2433 newpat = XVECEXP (newpat, 0, 1);
2438 newi2pat = XVECEXP (newpat, 0, 1);
2439 newpat = XVECEXP (newpat, 0, 0);
2442 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2444 if (i2_code_number >= 0)
2445 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2448 /* If it still isn't recognized, fail and change things back the way they
2450 if ((insn_code_number < 0
2451 /* Is the result a reasonable ASM_OPERANDS? */
2452 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2458 /* If we had to change another insn, make sure it is valid also. */
2459 if (undobuf.other_insn)
2461 rtx other_pat = PATTERN (undobuf.other_insn);
2462 rtx new_other_notes;
2465 CLEAR_HARD_REG_SET (newpat_used_regs);
2467 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2470 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2476 PATTERN (undobuf.other_insn) = other_pat;
2478 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2479 are still valid. Then add any non-duplicate notes added by
2480 recog_for_combine. */
2481 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2483 next = XEXP (note, 1);
2485 if (REG_NOTE_KIND (note) == REG_UNUSED
2486 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2488 if (GET_CODE (XEXP (note, 0)) == REG)
2489 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2491 remove_note (undobuf.other_insn, note);
2495 for (note = new_other_notes; note; note = XEXP (note, 1))
2496 if (GET_CODE (XEXP (note, 0)) == REG)
2497 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2499 distribute_notes (new_other_notes, undobuf.other_insn,
2500 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2503 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2504 they are adjacent to each other or not. */
2506 rtx p = prev_nonnote_insn (i3);
2507 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2508 && sets_cc0_p (newi2pat))
2516 /* We now know that we can do this combination. Merge the insns and
2517 update the status of registers and LOG_LINKS. */
2520 rtx i3notes, i2notes, i1notes = 0;
2521 rtx i3links, i2links, i1links = 0;
2524 /* Compute which registers we expect to eliminate. newi2pat may be setting
2525 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2526 same as i3dest, in which case newi2pat may be setting i1dest. */
2527 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2528 || i2dest_in_i2src || i2dest_in_i1src
2530 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2531 || (newi2pat && reg_set_p (i1dest, newi2pat))
2534 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2536 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2537 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2539 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2541 /* Ensure that we do not have something that should not be shared but
2542 occurs multiple times in the new insns. Check this by first
2543 resetting all the `used' flags and then copying anything is shared. */
2545 reset_used_flags (i3notes);
2546 reset_used_flags (i2notes);
2547 reset_used_flags (i1notes);
2548 reset_used_flags (newpat);
2549 reset_used_flags (newi2pat);
2550 if (undobuf.other_insn)
2551 reset_used_flags (PATTERN (undobuf.other_insn));
2553 i3notes = copy_rtx_if_shared (i3notes);
2554 i2notes = copy_rtx_if_shared (i2notes);
2555 i1notes = copy_rtx_if_shared (i1notes);
2556 newpat = copy_rtx_if_shared (newpat);
2557 newi2pat = copy_rtx_if_shared (newi2pat);
2558 if (undobuf.other_insn)
2559 reset_used_flags (PATTERN (undobuf.other_insn));
2561 INSN_CODE (i3) = insn_code_number;
2562 PATTERN (i3) = newpat;
2564 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2566 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2568 reset_used_flags (call_usage);
2569 call_usage = copy_rtx (call_usage);
2572 replace_rtx (call_usage, i2dest, i2src);
2575 replace_rtx (call_usage, i1dest, i1src);
2577 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2580 if (undobuf.other_insn)
2581 INSN_CODE (undobuf.other_insn) = other_code_number;
2583 /* We had one special case above where I2 had more than one set and
2584 we replaced a destination of one of those sets with the destination
2585 of I3. In that case, we have to update LOG_LINKS of insns later
2586 in this basic block. Note that this (expensive) case is rare.
2588 Also, in this case, we must pretend that all REG_NOTEs for I2
2589 actually came from I3, so that REG_UNUSED notes from I2 will be
2590 properly handled. */
2592 if (i3_subst_into_i2)
2594 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2595 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2596 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2597 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2598 && ! find_reg_note (i2, REG_UNUSED,
2599 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2600 for (temp = NEXT_INSN (i2);
2601 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2602 || this_basic_block->head != temp);
2603 temp = NEXT_INSN (temp))
2604 if (temp != i3 && INSN_P (temp))
2605 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2606 if (XEXP (link, 0) == i2)
2607 XEXP (link, 0) = i3;
2612 while (XEXP (link, 1))
2613 link = XEXP (link, 1);
2614 XEXP (link, 1) = i2notes;
2628 INSN_CODE (i2) = i2_code_number;
2629 PATTERN (i2) = newi2pat;
2633 PUT_CODE (i2, NOTE);
2634 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2635 NOTE_SOURCE_FILE (i2) = 0;
2642 PUT_CODE (i1, NOTE);
2643 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2644 NOTE_SOURCE_FILE (i1) = 0;
2647 /* Get death notes for everything that is now used in either I3 or
2648 I2 and used to die in a previous insn. If we built two new
2649 patterns, move from I1 to I2 then I2 to I3 so that we get the
2650 proper movement on registers that I2 modifies. */
2654 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2655 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2658 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2661 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2663 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2666 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2669 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2672 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2675 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2676 know these are REG_UNUSED and want them to go to the desired insn,
2677 so we always pass it as i3. We have not counted the notes in
2678 reg_n_deaths yet, so we need to do so now. */
2680 if (newi2pat && new_i2_notes)
2682 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2683 if (GET_CODE (XEXP (temp, 0)) == REG)
2684 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2686 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2691 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2692 if (GET_CODE (XEXP (temp, 0)) == REG)
2693 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2695 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2698 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2699 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2700 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2701 in that case, it might delete I2. Similarly for I2 and I1.
2702 Show an additional death due to the REG_DEAD note we make here. If
2703 we discard it in distribute_notes, we will decrement it again. */
2707 if (GET_CODE (i3dest_killed) == REG)
2708 REG_N_DEATHS (REGNO (i3dest_killed))++;
2710 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2711 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2713 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2715 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2717 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2721 if (i2dest_in_i2src)
2723 if (GET_CODE (i2dest) == REG)
2724 REG_N_DEATHS (REGNO (i2dest))++;
2726 if (newi2pat && reg_set_p (i2dest, newi2pat))
2727 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2728 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2730 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2731 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2732 NULL_RTX, NULL_RTX);
2735 if (i1dest_in_i1src)
2737 if (GET_CODE (i1dest) == REG)
2738 REG_N_DEATHS (REGNO (i1dest))++;
2740 if (newi2pat && reg_set_p (i1dest, newi2pat))
2741 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2742 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2744 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2745 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2746 NULL_RTX, NULL_RTX);
2749 distribute_links (i3links);
2750 distribute_links (i2links);
2751 distribute_links (i1links);
2753 if (GET_CODE (i2dest) == REG)
2756 rtx i2_insn = 0, i2_val = 0, set;
2758 /* The insn that used to set this register doesn't exist, and
2759 this life of the register may not exist either. See if one of
2760 I3's links points to an insn that sets I2DEST. If it does,
2761 that is now the last known value for I2DEST. If we don't update
2762 this and I2 set the register to a value that depended on its old
2763 contents, we will get confused. If this insn is used, thing
2764 will be set correctly in combine_instructions. */
2766 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2767 if ((set = single_set (XEXP (link, 0))) != 0
2768 && rtx_equal_p (i2dest, SET_DEST (set)))
2769 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2771 record_value_for_reg (i2dest, i2_insn, i2_val);
2773 /* If the reg formerly set in I2 died only once and that was in I3,
2774 zero its use count so it won't make `reload' do any work. */
2776 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2777 && ! i2dest_in_i2src)
2779 regno = REGNO (i2dest);
2780 REG_N_SETS (regno)--;
2784 if (i1 && GET_CODE (i1dest) == REG)
2787 rtx i1_insn = 0, i1_val = 0, set;
2789 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2790 if ((set = single_set (XEXP (link, 0))) != 0
2791 && rtx_equal_p (i1dest, SET_DEST (set)))
2792 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2794 record_value_for_reg (i1dest, i1_insn, i1_val);
2796 regno = REGNO (i1dest);
2797 if (! added_sets_1 && ! i1dest_in_i1src)
2798 REG_N_SETS (regno)--;
2801 /* Update reg_nonzero_bits et al for any changes that may have been made
2802 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2803 important. Because newi2pat can affect nonzero_bits of newpat */
2805 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2806 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2808 /* Set new_direct_jump_p if a new return or simple jump instruction
2811 If I3 is now an unconditional jump, ensure that it has a
2812 BARRIER following it since it may have initially been a
2813 conditional jump. It may also be the last nonnote insn. */
2815 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2817 *new_direct_jump_p = 1;
2819 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2820 || GET_CODE (temp) != BARRIER)
2821 emit_barrier_after (i3);
2823 /* An NOOP jump does not need barrier, but it does need cleaning up
2825 if (GET_CODE (newpat) == SET
2826 && SET_SRC (newpat) == pc_rtx
2827 && SET_DEST (newpat) == pc_rtx)
2828 *new_direct_jump_p = 1;
2831 combine_successes++;
2834 /* Clear this here, so that subsequent get_last_value calls are not
2836 subst_prev_insn = NULL_RTX;
2838 if (added_links_insn
2839 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2840 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2841 return added_links_insn;
2843 return newi2pat ? i2 : i3;
2846 /* Undo all the modifications recorded in undobuf. */
2851 struct undo *undo, *next;
2853 for (undo = undobuf.undos; undo; undo = next)
2857 *undo->where.i = undo->old_contents.i;
2859 *undo->where.r = undo->old_contents.r;
2861 undo->next = undobuf.frees;
2862 undobuf.frees = undo;
2867 /* Clear this here, so that subsequent get_last_value calls are not
2869 subst_prev_insn = NULL_RTX;
2872 /* We've committed to accepting the changes we made. Move all
2873 of the undos to the free list. */
2878 struct undo *undo, *next;
2880 for (undo = undobuf.undos; undo; undo = next)
2883 undo->next = undobuf.frees;
2884 undobuf.frees = undo;
2890 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2891 where we have an arithmetic expression and return that point. LOC will
2894 try_combine will call this function to see if an insn can be split into
2898 find_split_point (loc, insn)
2903 enum rtx_code code = GET_CODE (x);
2905 unsigned HOST_WIDE_INT len = 0;
2906 HOST_WIDE_INT pos = 0;
2908 rtx inner = NULL_RTX;
2910 /* First special-case some codes. */
2914 #ifdef INSN_SCHEDULING
2915 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2917 if (GET_CODE (SUBREG_REG (x)) == MEM)
2920 return find_split_point (&SUBREG_REG (x), insn);
2924 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2925 using LO_SUM and HIGH. */
2926 if (GET_CODE (XEXP (x, 0)) == CONST
2927 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2930 gen_rtx_LO_SUM (Pmode,
2931 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2933 return &XEXP (XEXP (x, 0), 0);
2937 /* If we have a PLUS whose second operand is a constant and the
2938 address is not valid, perhaps will can split it up using
2939 the machine-specific way to split large constants. We use
2940 the first pseudo-reg (one of the virtual regs) as a placeholder;
2941 it will not remain in the result. */
2942 if (GET_CODE (XEXP (x, 0)) == PLUS
2943 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2944 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2946 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2947 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2950 /* This should have produced two insns, each of which sets our
2951 placeholder. If the source of the second is a valid address,
2952 we can make put both sources together and make a split point
2956 && NEXT_INSN (seq) != NULL_RTX
2957 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2958 && GET_CODE (seq) == INSN
2959 && GET_CODE (PATTERN (seq)) == SET
2960 && SET_DEST (PATTERN (seq)) == reg
2961 && ! reg_mentioned_p (reg,
2962 SET_SRC (PATTERN (seq)))
2963 && GET_CODE (NEXT_INSN (seq)) == INSN
2964 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2965 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2966 && memory_address_p (GET_MODE (x),
2967 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2969 rtx src1 = SET_SRC (PATTERN (seq));
2970 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2972 /* Replace the placeholder in SRC2 with SRC1. If we can
2973 find where in SRC2 it was placed, that can become our
2974 split point and we can replace this address with SRC2.
2975 Just try two obvious places. */
2977 src2 = replace_rtx (src2, reg, src1);
2979 if (XEXP (src2, 0) == src1)
2980 split = &XEXP (src2, 0);
2981 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2982 && XEXP (XEXP (src2, 0), 0) == src1)
2983 split = &XEXP (XEXP (src2, 0), 0);
2987 SUBST (XEXP (x, 0), src2);
2992 /* If that didn't work, perhaps the first operand is complex and
2993 needs to be computed separately, so make a split point there.
2994 This will occur on machines that just support REG + CONST
2995 and have a constant moved through some previous computation. */
2997 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2998 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2999 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
3001 return &XEXP (XEXP (x, 0), 0);
3007 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3008 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3009 we need to put the operand into a register. So split at that
3012 if (SET_DEST (x) == cc0_rtx
3013 && GET_CODE (SET_SRC (x)) != COMPARE
3014 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3015 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
3016 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3017 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
3018 return &SET_SRC (x);
3021 /* See if we can split SET_SRC as it stands. */
3022 split = find_split_point (&SET_SRC (x), insn);
3023 if (split && split != &SET_SRC (x))
3026 /* See if we can split SET_DEST as it stands. */
3027 split = find_split_point (&SET_DEST (x), insn);
3028 if (split && split != &SET_DEST (x))
3031 /* See if this is a bitfield assignment with everything constant. If
3032 so, this is an IOR of an AND, so split it into that. */
3033 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3034 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3035 <= HOST_BITS_PER_WIDE_INT)
3036 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3037 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3038 && GET_CODE (SET_SRC (x)) == CONST_INT
3039 && ((INTVAL (XEXP (SET_DEST (x), 1))
3040 + INTVAL (XEXP (SET_DEST (x), 2)))
3041 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3042 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3044 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3045 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3046 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3047 rtx dest = XEXP (SET_DEST (x), 0);
3048 enum machine_mode mode = GET_MODE (dest);
3049 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3051 if (BITS_BIG_ENDIAN)
3052 pos = GET_MODE_BITSIZE (mode) - len - pos;
3056 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3059 gen_binary (IOR, mode,
3060 gen_binary (AND, mode, dest,
3061 gen_int_mode (~(mask << pos),
3063 GEN_INT (src << pos)));
3065 SUBST (SET_DEST (x), dest);
3067 split = find_split_point (&SET_SRC (x), insn);
3068 if (split && split != &SET_SRC (x))
3072 /* Otherwise, see if this is an operation that we can split into two.
3073 If so, try to split that. */
3074 code = GET_CODE (SET_SRC (x));
3079 /* If we are AND'ing with a large constant that is only a single
3080 bit and the result is only being used in a context where we
3081 need to know if it is zero or non-zero, replace it with a bit
3082 extraction. This will avoid the large constant, which might
3083 have taken more than one insn to make. If the constant were
3084 not a valid argument to the AND but took only one insn to make,
3085 this is no worse, but if it took more than one insn, it will
3088 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3089 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3090 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3091 && GET_CODE (SET_DEST (x)) == REG
3092 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3093 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3094 && XEXP (*split, 0) == SET_DEST (x)
3095 && XEXP (*split, 1) == const0_rtx)
3097 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3098 XEXP (SET_SRC (x), 0),
3099 pos, NULL_RTX, 1, 1, 0, 0);
3100 if (extraction != 0)
3102 SUBST (SET_SRC (x), extraction);
3103 return find_split_point (loc, insn);
3109 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3110 is known to be on, this can be converted into a NEG of a shift. */
3111 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3112 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3113 && 1 <= (pos = exact_log2
3114 (nonzero_bits (XEXP (SET_SRC (x), 0),
3115 GET_MODE (XEXP (SET_SRC (x), 0))))))
3117 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3121 gen_rtx_LSHIFTRT (mode,
3122 XEXP (SET_SRC (x), 0),
3125 split = find_split_point (&SET_SRC (x), insn);
3126 if (split && split != &SET_SRC (x))
3132 inner = XEXP (SET_SRC (x), 0);
3134 /* We can't optimize if either mode is a partial integer
3135 mode as we don't know how many bits are significant
3137 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3138 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3142 len = GET_MODE_BITSIZE (GET_MODE (inner));
3148 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3149 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3151 inner = XEXP (SET_SRC (x), 0);
3152 len = INTVAL (XEXP (SET_SRC (x), 1));
3153 pos = INTVAL (XEXP (SET_SRC (x), 2));
3155 if (BITS_BIG_ENDIAN)
3156 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3157 unsignedp = (code == ZERO_EXTRACT);
3165 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3167 enum machine_mode mode = GET_MODE (SET_SRC (x));
3169 /* For unsigned, we have a choice of a shift followed by an
3170 AND or two shifts. Use two shifts for field sizes where the
3171 constant might be too large. We assume here that we can
3172 always at least get 8-bit constants in an AND insn, which is
3173 true for every current RISC. */
3175 if (unsignedp && len <= 8)
3180 (mode, gen_lowpart_for_combine (mode, inner),
3182 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3184 split = find_split_point (&SET_SRC (x), insn);
3185 if (split && split != &SET_SRC (x))
3192 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3193 gen_rtx_ASHIFT (mode,
3194 gen_lowpart_for_combine (mode, inner),
3195 GEN_INT (GET_MODE_BITSIZE (mode)
3197 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3199 split = find_split_point (&SET_SRC (x), insn);
3200 if (split && split != &SET_SRC (x))
3205 /* See if this is a simple operation with a constant as the second
3206 operand. It might be that this constant is out of range and hence
3207 could be used as a split point. */
3208 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3209 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3210 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3211 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3212 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3213 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3214 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3216 return &XEXP (SET_SRC (x), 1);
3218 /* Finally, see if this is a simple operation with its first operand
3219 not in a register. The operation might require this operand in a
3220 register, so return it as a split point. We can always do this
3221 because if the first operand were another operation, we would have
3222 already found it as a split point. */
3223 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3224 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3225 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3226 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3227 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3228 return &XEXP (SET_SRC (x), 0);
3234 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3235 it is better to write this as (not (ior A B)) so we can split it.
3236 Similarly for IOR. */
3237 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3240 gen_rtx_NOT (GET_MODE (x),
3241 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3243 XEXP (XEXP (x, 0), 0),
3244 XEXP (XEXP (x, 1), 0))));
3245 return find_split_point (loc, insn);
3248 /* Many RISC machines have a large set of logical insns. If the
3249 second operand is a NOT, put it first so we will try to split the
3250 other operand first. */
3251 if (GET_CODE (XEXP (x, 1)) == NOT)
3253 rtx tem = XEXP (x, 0);
3254 SUBST (XEXP (x, 0), XEXP (x, 1));
3255 SUBST (XEXP (x, 1), tem);
3263 /* Otherwise, select our actions depending on our rtx class. */
3264 switch (GET_RTX_CLASS (code))
3266 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3268 split = find_split_point (&XEXP (x, 2), insn);
3271 /* ... fall through ... */
3275 split = find_split_point (&XEXP (x, 1), insn);
3278 /* ... fall through ... */
3280 /* Some machines have (and (shift ...) ...) insns. If X is not
3281 an AND, but XEXP (X, 0) is, use it as our split point. */
3282 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3283 return &XEXP (x, 0);
3285 split = find_split_point (&XEXP (x, 0), insn);
3291 /* Otherwise, we don't have a split point. */
3295 /* Throughout X, replace FROM with TO, and return the result.
3296 The result is TO if X is FROM;
3297 otherwise the result is X, but its contents may have been modified.
3298 If they were modified, a record was made in undobuf so that
3299 undo_all will (among other things) return X to its original state.
3301 If the number of changes necessary is too much to record to undo,
3302 the excess changes are not made, so the result is invalid.
3303 The changes already made can still be undone.
3304 undobuf.num_undo is incremented for such changes, so by testing that
3305 the caller can tell whether the result is valid.
3307 `n_occurrences' is incremented each time FROM is replaced.
3309 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3311 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3312 by copying if `n_occurrences' is non-zero. */
3315 subst (x, from, to, in_dest, unique_copy)
3320 enum rtx_code code = GET_CODE (x);
3321 enum machine_mode op0_mode = VOIDmode;
3326 /* Two expressions are equal if they are identical copies of a shared
3327 RTX or if they are both registers with the same register number
3330 #define COMBINE_RTX_EQUAL_P(X,Y) \
3332 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3333 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3335 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3338 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3341 /* If X and FROM are the same register but different modes, they will
3342 not have been seen as equal above. However, flow.c will make a
3343 LOG_LINKS entry for that case. If we do nothing, we will try to
3344 rerecognize our original insn and, when it succeeds, we will
3345 delete the feeding insn, which is incorrect.
3347 So force this insn not to match in this (rare) case. */
3348 if (! in_dest && code == REG && GET_CODE (from) == REG
3349 && REGNO (x) == REGNO (from))
3350 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3352 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3353 of which may contain things that can be combined. */
3354 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3357 /* It is possible to have a subexpression appear twice in the insn.
3358 Suppose that FROM is a register that appears within TO.
3359 Then, after that subexpression has been scanned once by `subst',
3360 the second time it is scanned, TO may be found. If we were
3361 to scan TO here, we would find FROM within it and create a
3362 self-referent rtl structure which is completely wrong. */
3363 if (COMBINE_RTX_EQUAL_P (x, to))
3366 /* Parallel asm_operands need special attention because all of the
3367 inputs are shared across the arms. Furthermore, unsharing the
3368 rtl results in recognition failures. Failure to handle this case
3369 specially can result in circular rtl.
3371 Solve this by doing a normal pass across the first entry of the
3372 parallel, and only processing the SET_DESTs of the subsequent
3375 if (code == PARALLEL
3376 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3377 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3379 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3381 /* If this substitution failed, this whole thing fails. */
3382 if (GET_CODE (new) == CLOBBER
3383 && XEXP (new, 0) == const0_rtx)
3386 SUBST (XVECEXP (x, 0, 0), new);
3388 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3390 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3392 if (GET_CODE (dest) != REG
3393 && GET_CODE (dest) != CC0
3394 && GET_CODE (dest) != PC)
3396 new = subst (dest, from, to, 0, unique_copy);
3398 /* If this substitution failed, this whole thing fails. */
3399 if (GET_CODE (new) == CLOBBER
3400 && XEXP (new, 0) == const0_rtx)
3403 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3409 len = GET_RTX_LENGTH (code);
3410 fmt = GET_RTX_FORMAT (code);
3412 /* We don't need to process a SET_DEST that is a register, CC0,
3413 or PC, so set up to skip this common case. All other cases
3414 where we want to suppress replacing something inside a
3415 SET_SRC are handled via the IN_DEST operand. */
3417 && (GET_CODE (SET_DEST (x)) == REG
3418 || GET_CODE (SET_DEST (x)) == CC0
3419 || GET_CODE (SET_DEST (x)) == PC))
3422 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3425 op0_mode = GET_MODE (XEXP (x, 0));
3427 for (i = 0; i < len; i++)
3432 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3434 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3436 new = (unique_copy && n_occurrences
3437 ? copy_rtx (to) : to);
3442 new = subst (XVECEXP (x, i, j), from, to, 0,
3445 /* If this substitution failed, this whole thing
3447 if (GET_CODE (new) == CLOBBER
3448 && XEXP (new, 0) == const0_rtx)
3452 SUBST (XVECEXP (x, i, j), new);
3455 else if (fmt[i] == 'e')
3457 /* If this is a register being set, ignore it. */
3460 && (code == SUBREG || code == STRICT_LOW_PART
3461 || code == ZERO_EXTRACT)
3463 && GET_CODE (new) == REG)
3466 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3468 /* In general, don't install a subreg involving two
3469 modes not tieable. It can worsen register
3470 allocation, and can even make invalid reload
3471 insns, since the reg inside may need to be copied
3472 from in the outside mode, and that may be invalid
3473 if it is an fp reg copied in integer mode.
3475 We allow two exceptions to this: It is valid if
3476 it is inside another SUBREG and the mode of that
3477 SUBREG and the mode of the inside of TO is
3478 tieable and it is valid if X is a SET that copies
3481 if (GET_CODE (to) == SUBREG
3482 && ! MODES_TIEABLE_P (GET_MODE (to),
3483 GET_MODE (SUBREG_REG (to)))
3484 && ! (code == SUBREG
3485 && MODES_TIEABLE_P (GET_MODE (x),
3486 GET_MODE (SUBREG_REG (to))))
3488 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3491 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3493 #ifdef CLASS_CANNOT_CHANGE_MODE
3495 && GET_CODE (to) == REG
3496 && REGNO (to) < FIRST_PSEUDO_REGISTER
3497 && (TEST_HARD_REG_BIT
3498 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3500 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3502 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3505 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3509 /* If we are in a SET_DEST, suppress most cases unless we
3510 have gone inside a MEM, in which case we want to
3511 simplify the address. We assume here that things that
3512 are actually part of the destination have their inner
3513 parts in the first expression. This is true for SUBREG,
3514 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3515 things aside from REG and MEM that should appear in a
3517 new = subst (XEXP (x, i), from, to,
3519 && (code == SUBREG || code == STRICT_LOW_PART
3520 || code == ZERO_EXTRACT))
3522 && i == 0), unique_copy);
3524 /* If we found that we will have to reject this combination,
3525 indicate that by returning the CLOBBER ourselves, rather than
3526 an expression containing it. This will speed things up as
3527 well as prevent accidents where two CLOBBERs are considered
3528 to be equal, thus producing an incorrect simplification. */
3530 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3533 if (GET_CODE (new) == CONST_INT && GET_CODE (x) == SUBREG)
3535 enum machine_mode mode = GET_MODE (x);
3537 x = simplify_subreg (GET_MODE (x), new,
3538 GET_MODE (SUBREG_REG (x)),
3541 x = gen_rtx_CLOBBER (mode, const0_rtx);
3543 else if (GET_CODE (new) == CONST_INT
3544 && GET_CODE (x) == ZERO_EXTEND)
3546 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3547 new, GET_MODE (XEXP (x, 0)));
3552 SUBST (XEXP (x, i), new);
3557 /* Try to simplify X. If the simplification changed the code, it is likely
3558 that further simplification will help, so loop, but limit the number
3559 of repetitions that will be performed. */
3561 for (i = 0; i < 4; i++)
3563 /* If X is sufficiently simple, don't bother trying to do anything
3565 if (code != CONST_INT && code != REG && code != CLOBBER)
3566 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3568 if (GET_CODE (x) == code)
3571 code = GET_CODE (x);
3573 /* We no longer know the original mode of operand 0 since we
3574 have changed the form of X) */
3575 op0_mode = VOIDmode;
3581 /* Simplify X, a piece of RTL. We just operate on the expression at the
3582 outer level; call `subst' to simplify recursively. Return the new
3585 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3586 will be the iteration even if an expression with a code different from
3587 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3590 combine_simplify_rtx (x, op0_mode, last, in_dest)
3592 enum machine_mode op0_mode;
3596 enum rtx_code code = GET_CODE (x);
3597 enum machine_mode mode = GET_MODE (x);
3602 /* If this is a commutative operation, put a constant last and a complex
3603 expression first. We don't need to do this for comparisons here. */
3604 if (GET_RTX_CLASS (code) == 'c'
3605 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3608 SUBST (XEXP (x, 0), XEXP (x, 1));
3609 SUBST (XEXP (x, 1), temp);
3612 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3613 sign extension of a PLUS with a constant, reverse the order of the sign
3614 extension and the addition. Note that this not the same as the original
3615 code, but overflow is undefined for signed values. Also note that the
3616 PLUS will have been partially moved "inside" the sign-extension, so that
3617 the first operand of X will really look like:
3618 (ashiftrt (plus (ashift A C4) C5) C4).
3620 (plus (ashiftrt (ashift A C4) C2) C4)
3621 and replace the first operand of X with that expression. Later parts
3622 of this function may simplify the expression further.
3624 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3625 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3626 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3628 We do this to simplify address expressions. */
3630 if ((code == PLUS || code == MINUS || code == MULT)
3631 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3632 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3633 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3634 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3635 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3636 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3637 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3638 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3639 XEXP (XEXP (XEXP (x, 0), 0), 1),
3640 XEXP (XEXP (x, 0), 1))) != 0)
3643 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3644 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3645 INTVAL (XEXP (XEXP (x, 0), 1)));
3647 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3648 INTVAL (XEXP (XEXP (x, 0), 1)));
3650 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3653 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3654 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3655 things. Check for cases where both arms are testing the same
3658 Don't do anything if all operands are very simple. */
3660 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3661 || GET_RTX_CLASS (code) == '<')
3662 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3663 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3664 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3666 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3667 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3668 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3670 || (GET_RTX_CLASS (code) == '1'
3671 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3672 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3673 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3676 rtx cond, true_rtx, false_rtx;
3678 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3680 /* If everything is a comparison, what we have is highly unlikely
3681 to be simpler, so don't use it. */
3682 && ! (GET_RTX_CLASS (code) == '<'
3683 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3684 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3686 rtx cop1 = const0_rtx;
3687 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3689 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3692 /* Simplify the alternative arms; this may collapse the true and
3693 false arms to store-flag values. */
3694 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3695 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3697 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3698 is unlikely to be simpler. */
3699 if (general_operand (true_rtx, VOIDmode)
3700 && general_operand (false_rtx, VOIDmode))
3702 /* Restarting if we generate a store-flag expression will cause
3703 us to loop. Just drop through in this case. */
3705 /* If the result values are STORE_FLAG_VALUE and zero, we can
3706 just make the comparison operation. */
3707 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3708 x = gen_binary (cond_code, mode, cond, cop1);
3709 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3710 && reverse_condition (cond_code) != UNKNOWN)
3711 x = gen_binary (reverse_condition (cond_code),
3714 /* Likewise, we can make the negate of a comparison operation
3715 if the result values are - STORE_FLAG_VALUE and zero. */
3716 else if (GET_CODE (true_rtx) == CONST_INT
3717 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3718 && false_rtx == const0_rtx)
3719 x = simplify_gen_unary (NEG, mode,
3720 gen_binary (cond_code, mode, cond,
3723 else if (GET_CODE (false_rtx) == CONST_INT
3724 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3725 && true_rtx == const0_rtx)
3726 x = simplify_gen_unary (NEG, mode,
3727 gen_binary (reverse_condition
3732 return gen_rtx_IF_THEN_ELSE (mode,
3733 gen_binary (cond_code, VOIDmode,
3735 true_rtx, false_rtx);
3737 code = GET_CODE (x);
3738 op0_mode = VOIDmode;
3743 /* Try to fold this expression in case we have constants that weren't
3746 switch (GET_RTX_CLASS (code))
3749 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3753 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3754 if (cmp_mode == VOIDmode)
3756 cmp_mode = GET_MODE (XEXP (x, 1));
3757 if (cmp_mode == VOIDmode)
3758 cmp_mode = op0_mode;
3760 temp = simplify_relational_operation (code, cmp_mode,
3761 XEXP (x, 0), XEXP (x, 1));
3763 #ifdef FLOAT_STORE_FLAG_VALUE
3764 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3766 if (temp == const0_rtx)
3767 temp = CONST0_RTX (mode);
3769 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3776 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3780 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3781 XEXP (x, 1), XEXP (x, 2));
3788 code = GET_CODE (temp);
3789 op0_mode = VOIDmode;
3790 mode = GET_MODE (temp);
3793 /* First see if we can apply the inverse distributive law. */
3794 if (code == PLUS || code == MINUS
3795 || code == AND || code == IOR || code == XOR)
3797 x = apply_distributive_law (x);
3798 code = GET_CODE (x);
3799 op0_mode = VOIDmode;
3802 /* If CODE is an associative operation not otherwise handled, see if we
3803 can associate some operands. This can win if they are constants or
3804 if they are logically related (i.e. (a & b) & a). */
3805 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3806 || code == AND || code == IOR || code == XOR
3807 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3808 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3809 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3811 if (GET_CODE (XEXP (x, 0)) == code)
3813 rtx other = XEXP (XEXP (x, 0), 0);
3814 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3815 rtx inner_op1 = XEXP (x, 1);
3818 /* Make sure we pass the constant operand if any as the second
3819 one if this is a commutative operation. */
3820 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3822 rtx tem = inner_op0;
3823 inner_op0 = inner_op1;
3826 inner = simplify_binary_operation (code == MINUS ? PLUS
3827 : code == DIV ? MULT
3829 mode, inner_op0, inner_op1);
3831 /* For commutative operations, try the other pair if that one
3833 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3835 other = XEXP (XEXP (x, 0), 1);
3836 inner = simplify_binary_operation (code, mode,
3837 XEXP (XEXP (x, 0), 0),
3842 return gen_binary (code, mode, other, inner);
3846 /* A little bit of algebraic simplification here. */
3850 /* Ensure that our address has any ASHIFTs converted to MULT in case
3851 address-recognizing predicates are called later. */
3852 temp = make_compound_operation (XEXP (x, 0), MEM);
3853 SUBST (XEXP (x, 0), temp);
3857 if (op0_mode == VOIDmode)
3858 op0_mode = GET_MODE (SUBREG_REG (x));
3860 /* simplify_subreg can't use gen_lowpart_for_combine. */
3861 if (CONSTANT_P (SUBREG_REG (x))
3862 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3863 /* Don't call gen_lowpart_for_combine if the inner mode
3864 is VOIDmode and we cannot simplify it, as SUBREG without
3865 inner mode is invalid. */
3866 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3867 || gen_lowpart_common (mode, SUBREG_REG (x))))
3868 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3870 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3874 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3880 /* Don't change the mode of the MEM if that would change the meaning
3882 if (GET_CODE (SUBREG_REG (x)) == MEM
3883 && (MEM_VOLATILE_P (SUBREG_REG (x))
3884 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3885 return gen_rtx_CLOBBER (mode, const0_rtx);
3887 /* Note that we cannot do any narrowing for non-constants since
3888 we might have been counting on using the fact that some bits were
3889 zero. We now do this in the SET. */
3894 /* (not (plus X -1)) can become (neg X). */
3895 if (GET_CODE (XEXP (x, 0)) == PLUS
3896 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3897 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3899 /* Similarly, (not (neg X)) is (plus X -1). */
3900 if (GET_CODE (XEXP (x, 0)) == NEG)
3901 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3903 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3904 if (GET_CODE (XEXP (x, 0)) == XOR
3905 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3906 && (temp = simplify_unary_operation (NOT, mode,
3907 XEXP (XEXP (x, 0), 1),
3909 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3911 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3912 other than 1, but that is not valid. We could do a similar
3913 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3914 but this doesn't seem common enough to bother with. */
3915 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3916 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3917 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3919 XEXP (XEXP (x, 0), 1));
3921 if (GET_CODE (XEXP (x, 0)) == SUBREG
3922 && subreg_lowpart_p (XEXP (x, 0))
3923 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3924 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3925 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3926 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3928 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3930 x = gen_rtx_ROTATE (inner_mode,
3931 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3933 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3934 return gen_lowpart_for_combine (mode, x);
3937 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3938 reversing the comparison code if valid. */
3939 if (STORE_FLAG_VALUE == -1
3940 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3941 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3942 XEXP (XEXP (x, 0), 1))))
3945 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3946 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3947 perform the above simplification. */
3949 if (STORE_FLAG_VALUE == -1
3950 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3952 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3953 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3955 /* Apply De Morgan's laws to reduce number of patterns for machines
3956 with negating logical insns (and-not, nand, etc.). If result has
3957 only one NOT, put it first, since that is how the patterns are
3960 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3962 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3963 enum machine_mode op_mode;
3965 op_mode = GET_MODE (in1);
3966 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3968 op_mode = GET_MODE (in2);
3969 if (op_mode == VOIDmode)
3971 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3973 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3976 in2 = in1; in1 = tem;
3979 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3985 /* (neg (plus X 1)) can become (not X). */
3986 if (GET_CODE (XEXP (x, 0)) == PLUS
3987 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3988 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3990 /* Similarly, (neg (not X)) is (plus X 1). */
3991 if (GET_CODE (XEXP (x, 0)) == NOT)
3992 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3994 /* (neg (minus X Y)) can become (minus Y X). This transformation
3995 isn't safe for modes with signed zeros, since if X and Y are
3996 both +0, (minus Y X) is the same as (minus X Y). If the rounding
3997 mode is towards +infinity (or -infinity) then the two expressions
3998 will be rounded differently. */
3999 if (GET_CODE (XEXP (x, 0)) == MINUS
4000 && !HONOR_SIGNED_ZEROS (mode)
4001 && !HONOR_SIGN_DEPENDENT_ROUNDING (mode))
4002 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4003 XEXP (XEXP (x, 0), 0));
4005 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4006 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4007 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4008 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4010 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4011 if we can then eliminate the NEG (e.g.,
4012 if the operand is a constant). */
4014 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4016 temp = simplify_unary_operation (NEG, mode,
4017 XEXP (XEXP (x, 0), 0), mode);
4019 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
4022 temp = expand_compound_operation (XEXP (x, 0));
4024 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4025 replaced by (lshiftrt X C). This will convert
4026 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4028 if (GET_CODE (temp) == ASHIFTRT
4029 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4030 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4031 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4032 INTVAL (XEXP (temp, 1)));
4034 /* If X has only a single bit that might be nonzero, say, bit I, convert
4035 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4036 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4037 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4038 or a SUBREG of one since we'd be making the expression more
4039 complex if it was just a register. */
4041 if (GET_CODE (temp) != REG
4042 && ! (GET_CODE (temp) == SUBREG
4043 && GET_CODE (SUBREG_REG (temp)) == REG)
4044 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4046 rtx temp1 = simplify_shift_const
4047 (NULL_RTX, ASHIFTRT, mode,
4048 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4049 GET_MODE_BITSIZE (mode) - 1 - i),
4050 GET_MODE_BITSIZE (mode) - 1 - i);
4052 /* If all we did was surround TEMP with the two shifts, we
4053 haven't improved anything, so don't use it. Otherwise,
4054 we are better off with TEMP1. */
4055 if (GET_CODE (temp1) != ASHIFTRT
4056 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4057 || XEXP (XEXP (temp1, 0), 0) != temp)
4063 /* We can't handle truncation to a partial integer mode here
4064 because we don't know the real bitsize of the partial
4066 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4069 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4070 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4071 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4073 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4074 GET_MODE_MASK (mode), NULL_RTX, 0));
4076 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4077 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4078 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4079 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4080 return XEXP (XEXP (x, 0), 0);
4082 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4083 (OP:SI foo:SI) if OP is NEG or ABS. */
4084 if ((GET_CODE (XEXP (x, 0)) == ABS
4085 || GET_CODE (XEXP (x, 0)) == NEG)
4086 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4087 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4088 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4089 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4090 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4092 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4094 if (GET_CODE (XEXP (x, 0)) == SUBREG
4095 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4096 && subreg_lowpart_p (XEXP (x, 0)))
4097 return SUBREG_REG (XEXP (x, 0));
4099 /* If we know that the value is already truncated, we can
4100 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4101 is nonzero for the corresponding modes. But don't do this
4102 for an (LSHIFTRT (MULT ...)) since this will cause problems
4103 with the umulXi3_highpart patterns. */
4104 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4105 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4106 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4107 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4108 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4109 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4110 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4112 /* A truncate of a comparison can be replaced with a subreg if
4113 STORE_FLAG_VALUE permits. This is like the previous test,
4114 but it works even if the comparison is done in a mode larger
4115 than HOST_BITS_PER_WIDE_INT. */
4116 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4117 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4118 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4119 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4121 /* Similarly, a truncate of a register whose value is a
4122 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4124 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4125 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4126 && (temp = get_last_value (XEXP (x, 0)))
4127 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4128 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4132 case FLOAT_TRUNCATE:
4133 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4134 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4135 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4136 return XEXP (XEXP (x, 0), 0);
4138 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4139 (OP:SF foo:SF) if OP is NEG or ABS. */
4140 if ((GET_CODE (XEXP (x, 0)) == ABS
4141 || GET_CODE (XEXP (x, 0)) == NEG)
4142 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4143 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4144 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4145 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4147 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4148 is (float_truncate:SF x). */
4149 if (GET_CODE (XEXP (x, 0)) == SUBREG
4150 && subreg_lowpart_p (XEXP (x, 0))
4151 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4152 return SUBREG_REG (XEXP (x, 0));
4157 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4158 using cc0, in which case we want to leave it as a COMPARE
4159 so we can distinguish it from a register-register-copy. */
4160 if (XEXP (x, 1) == const0_rtx)
4163 /* x - 0 is the same as x unless x's mode has signed zeros and
4164 allows rounding towards -infinity. Under those conditions,
4166 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4167 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4168 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4174 /* (const (const X)) can become (const X). Do it this way rather than
4175 returning the inner CONST since CONST can be shared with a
4177 if (GET_CODE (XEXP (x, 0)) == CONST)
4178 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4183 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4184 can add in an offset. find_split_point will split this address up
4185 again if it doesn't match. */
4186 if (GET_CODE (XEXP (x, 0)) == HIGH
4187 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4193 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4194 outermost. That's because that's the way indexed addresses are
4195 supposed to appear. This code used to check many more cases, but
4196 they are now checked elsewhere. */
4197 if (GET_CODE (XEXP (x, 0)) == PLUS
4198 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4199 return gen_binary (PLUS, mode,
4200 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4202 XEXP (XEXP (x, 0), 1));
4204 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4205 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4206 bit-field and can be replaced by either a sign_extend or a
4207 sign_extract. The `and' may be a zero_extend and the two
4208 <c>, -<c> constants may be reversed. */
4209 if (GET_CODE (XEXP (x, 0)) == XOR
4210 && GET_CODE (XEXP (x, 1)) == CONST_INT
4211 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4212 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4213 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4214 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4215 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4216 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4217 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4218 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4219 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4220 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4221 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4222 == (unsigned int) i + 1))))
4223 return simplify_shift_const
4224 (NULL_RTX, ASHIFTRT, mode,
4225 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4226 XEXP (XEXP (XEXP (x, 0), 0), 0),
4227 GET_MODE_BITSIZE (mode) - (i + 1)),
4228 GET_MODE_BITSIZE (mode) - (i + 1));
4230 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4231 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4232 is 1. This produces better code than the alternative immediately
4234 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4235 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4236 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4237 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4238 XEXP (XEXP (x, 0), 0),
4239 XEXP (XEXP (x, 0), 1))))
4241 simplify_gen_unary (NEG, mode, reversed, mode);
4243 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4244 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4245 the bitsize of the mode - 1. This allows simplification of
4246 "a = (b & 8) == 0;" */
4247 if (XEXP (x, 1) == constm1_rtx
4248 && GET_CODE (XEXP (x, 0)) != REG
4249 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4250 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4251 && nonzero_bits (XEXP (x, 0), mode) == 1)
4252 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4253 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4254 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4255 GET_MODE_BITSIZE (mode) - 1),
4256 GET_MODE_BITSIZE (mode) - 1);
4258 /* If we are adding two things that have no bits in common, convert
4259 the addition into an IOR. This will often be further simplified,
4260 for example in cases like ((a & 1) + (a & 2)), which can
4263 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4264 && (nonzero_bits (XEXP (x, 0), mode)
4265 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4267 /* Try to simplify the expression further. */
4268 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4269 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4271 /* If we could, great. If not, do not go ahead with the IOR
4272 replacement, since PLUS appears in many special purpose
4273 address arithmetic instructions. */
4274 if (GET_CODE (temp) != CLOBBER && temp != tor)
4280 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4281 by reversing the comparison code if valid. */
4282 if (STORE_FLAG_VALUE == 1
4283 && XEXP (x, 0) == const1_rtx
4284 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4285 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4286 XEXP (XEXP (x, 1), 0),
4287 XEXP (XEXP (x, 1), 1))))
4290 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4291 (and <foo> (const_int pow2-1)) */
4292 if (GET_CODE (XEXP (x, 1)) == AND
4293 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4294 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4295 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4296 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4297 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4299 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4301 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4302 return gen_binary (MINUS, mode,
4303 gen_binary (MINUS, mode, XEXP (x, 0),
4304 XEXP (XEXP (x, 1), 0)),
4305 XEXP (XEXP (x, 1), 1));
4309 /* If we have (mult (plus A B) C), apply the distributive law and then
4310 the inverse distributive law to see if things simplify. This
4311 occurs mostly in addresses, often when unrolling loops. */
4313 if (GET_CODE (XEXP (x, 0)) == PLUS)
4315 x = apply_distributive_law
4316 (gen_binary (PLUS, mode,
4317 gen_binary (MULT, mode,
4318 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4319 gen_binary (MULT, mode,
4320 XEXP (XEXP (x, 0), 1),
4321 copy_rtx (XEXP (x, 1)))));
4323 if (GET_CODE (x) != MULT)
4326 /* Try simplify a*(b/c) as (a*b)/c. */
4327 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4328 && GET_CODE (XEXP (x, 0)) == DIV)
4330 rtx tem = simplify_binary_operation (MULT, mode,
4331 XEXP (XEXP (x, 0), 0),
4334 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4339 /* If this is a divide by a power of two, treat it as a shift if
4340 its first operand is a shift. */
4341 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4342 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4343 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4344 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4345 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4346 || GET_CODE (XEXP (x, 0)) == ROTATE
4347 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4348 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4352 case GT: case GTU: case GE: case GEU:
4353 case LT: case LTU: case LE: case LEU:
4354 case UNEQ: case LTGT:
4355 case UNGT: case UNGE:
4356 case UNLT: case UNLE:
4357 case UNORDERED: case ORDERED:
4358 /* If the first operand is a condition code, we can't do anything
4360 if (GET_CODE (XEXP (x, 0)) == COMPARE
4361 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4363 && XEXP (x, 0) != cc0_rtx
4367 rtx op0 = XEXP (x, 0);
4368 rtx op1 = XEXP (x, 1);
4369 enum rtx_code new_code;
4371 if (GET_CODE (op0) == COMPARE)
4372 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4374 /* Simplify our comparison, if possible. */
4375 new_code = simplify_comparison (code, &op0, &op1);
4377 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4378 if only the low-order bit is possibly nonzero in X (such as when
4379 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4380 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4381 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4384 Remove any ZERO_EXTRACT we made when thinking this was a
4385 comparison. It may now be simpler to use, e.g., an AND. If a
4386 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4387 the call to make_compound_operation in the SET case. */
4389 if (STORE_FLAG_VALUE == 1
4390 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4391 && op1 == const0_rtx
4392 && mode == GET_MODE (op0)
4393 && nonzero_bits (op0, mode) == 1)
4394 return gen_lowpart_for_combine (mode,
4395 expand_compound_operation (op0));
4397 else if (STORE_FLAG_VALUE == 1
4398 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4399 && op1 == const0_rtx
4400 && mode == GET_MODE (op0)
4401 && (num_sign_bit_copies (op0, mode)
4402 == GET_MODE_BITSIZE (mode)))
4404 op0 = expand_compound_operation (op0);
4405 return simplify_gen_unary (NEG, mode,
4406 gen_lowpart_for_combine (mode, op0),
4410 else if (STORE_FLAG_VALUE == 1
4411 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4412 && op1 == const0_rtx
4413 && mode == GET_MODE (op0)
4414 && nonzero_bits (op0, mode) == 1)
4416 op0 = expand_compound_operation (op0);
4417 return gen_binary (XOR, mode,
4418 gen_lowpart_for_combine (mode, op0),
4422 else if (STORE_FLAG_VALUE == 1
4423 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4424 && op1 == const0_rtx
4425 && mode == GET_MODE (op0)
4426 && (num_sign_bit_copies (op0, mode)
4427 == GET_MODE_BITSIZE (mode)))
4429 op0 = expand_compound_operation (op0);
4430 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4433 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4435 if (STORE_FLAG_VALUE == -1
4436 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4437 && op1 == const0_rtx
4438 && (num_sign_bit_copies (op0, mode)
4439 == GET_MODE_BITSIZE (mode)))
4440 return gen_lowpart_for_combine (mode,
4441 expand_compound_operation (op0));
4443 else if (STORE_FLAG_VALUE == -1
4444 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4445 && op1 == const0_rtx
4446 && mode == GET_MODE (op0)
4447 && nonzero_bits (op0, mode) == 1)
4449 op0 = expand_compound_operation (op0);
4450 return simplify_gen_unary (NEG, mode,
4451 gen_lowpart_for_combine (mode, op0),
4455 else if (STORE_FLAG_VALUE == -1
4456 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4457 && op1 == const0_rtx
4458 && mode == GET_MODE (op0)
4459 && (num_sign_bit_copies (op0, mode)
4460 == GET_MODE_BITSIZE (mode)))
4462 op0 = expand_compound_operation (op0);
4463 return simplify_gen_unary (NOT, mode,
4464 gen_lowpart_for_combine (mode, op0),
4468 /* If X is 0/1, (eq X 0) is X-1. */
4469 else if (STORE_FLAG_VALUE == -1
4470 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4471 && op1 == const0_rtx
4472 && mode == GET_MODE (op0)
4473 && nonzero_bits (op0, mode) == 1)
4475 op0 = expand_compound_operation (op0);
4476 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4479 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4480 one bit that might be nonzero, we can convert (ne x 0) to
4481 (ashift x c) where C puts the bit in the sign bit. Remove any
4482 AND with STORE_FLAG_VALUE when we are done, since we are only
4483 going to test the sign bit. */
4484 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4485 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4486 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4487 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4488 && op1 == const0_rtx
4489 && mode == GET_MODE (op0)
4490 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4492 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4493 expand_compound_operation (op0),
4494 GET_MODE_BITSIZE (mode) - 1 - i);
4495 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4501 /* If the code changed, return a whole new comparison. */
4502 if (new_code != code)
4503 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4505 /* Otherwise, keep this operation, but maybe change its operands.
4506 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4507 SUBST (XEXP (x, 0), op0);
4508 SUBST (XEXP (x, 1), op1);
4513 return simplify_if_then_else (x);
4519 /* If we are processing SET_DEST, we are done. */
4523 return expand_compound_operation (x);
4526 return simplify_set (x);
4531 return simplify_logical (x, last);
4534 /* (abs (neg <foo>)) -> (abs <foo>) */
4535 if (GET_CODE (XEXP (x, 0)) == NEG)
4536 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4538 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4540 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4543 /* If operand is something known to be positive, ignore the ABS. */
4544 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4545 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4546 <= HOST_BITS_PER_WIDE_INT)
4547 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4548 & ((HOST_WIDE_INT) 1
4549 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4553 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4554 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4555 return gen_rtx_NEG (mode, XEXP (x, 0));
4560 /* (ffs (*_extend <X>)) = (ffs <X>) */
4561 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4562 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4563 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4567 /* (float (sign_extend <X>)) = (float <X>). */
4568 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4569 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4577 /* If this is a shift by a constant amount, simplify it. */
4578 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4579 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4580 INTVAL (XEXP (x, 1)));
4582 #ifdef SHIFT_COUNT_TRUNCATED
4583 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4585 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4587 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4596 rtx op0 = XEXP (x, 0);
4597 rtx op1 = XEXP (x, 1);
4600 if (GET_CODE (op1) != PARALLEL)
4602 len = XVECLEN (op1, 0);
4604 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4605 && GET_CODE (op0) == VEC_CONCAT)
4607 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4609 /* Try to find the element in the VEC_CONCAT. */
4612 if (GET_MODE (op0) == GET_MODE (x))
4614 if (GET_CODE (op0) == VEC_CONCAT)
4616 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4617 if (op0_size < offset)
4618 op0 = XEXP (op0, 0);
4622 op0 = XEXP (op0, 1);
4640 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4643 simplify_if_then_else (x)
4646 enum machine_mode mode = GET_MODE (x);
4647 rtx cond = XEXP (x, 0);
4648 rtx true_rtx = XEXP (x, 1);
4649 rtx false_rtx = XEXP (x, 2);
4650 enum rtx_code true_code = GET_CODE (cond);
4651 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4654 enum rtx_code false_code;
4657 /* Simplify storing of the truth value. */
4658 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4659 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4661 /* Also when the truth value has to be reversed. */
4663 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4664 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4668 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4669 in it is being compared against certain values. Get the true and false
4670 comparisons and see if that says anything about the value of each arm. */
4673 && ((false_code = combine_reversed_comparison_code (cond))
4675 && GET_CODE (XEXP (cond, 0)) == REG)
4678 rtx from = XEXP (cond, 0);
4679 rtx true_val = XEXP (cond, 1);
4680 rtx false_val = true_val;
4683 /* If FALSE_CODE is EQ, swap the codes and arms. */
4685 if (false_code == EQ)
4687 swapped = 1, true_code = EQ, false_code = NE;
4688 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4691 /* If we are comparing against zero and the expression being tested has
4692 only a single bit that might be nonzero, that is its value when it is
4693 not equal to zero. Similarly if it is known to be -1 or 0. */
4695 if (true_code == EQ && true_val == const0_rtx
4696 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4697 false_code = EQ, false_val = GEN_INT (nzb);
4698 else if (true_code == EQ && true_val == const0_rtx
4699 && (num_sign_bit_copies (from, GET_MODE (from))
4700 == GET_MODE_BITSIZE (GET_MODE (from))))
4701 false_code = EQ, false_val = constm1_rtx;
4703 /* Now simplify an arm if we know the value of the register in the
4704 branch and it is used in the arm. Be careful due to the potential
4705 of locally-shared RTL. */
4707 if (reg_mentioned_p (from, true_rtx))
4708 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4710 pc_rtx, pc_rtx, 0, 0);
4711 if (reg_mentioned_p (from, false_rtx))
4712 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4714 pc_rtx, pc_rtx, 0, 0);
4716 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4717 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4719 true_rtx = XEXP (x, 1);
4720 false_rtx = XEXP (x, 2);
4721 true_code = GET_CODE (cond);
4724 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4725 reversed, do so to avoid needing two sets of patterns for
4726 subtract-and-branch insns. Similarly if we have a constant in the true
4727 arm, the false arm is the same as the first operand of the comparison, or
4728 the false arm is more complicated than the true arm. */
4731 && combine_reversed_comparison_code (cond) != UNKNOWN
4732 && (true_rtx == pc_rtx
4733 || (CONSTANT_P (true_rtx)
4734 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4735 || true_rtx == const0_rtx
4736 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4737 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4738 || (GET_CODE (true_rtx) == SUBREG
4739 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4740 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4741 || reg_mentioned_p (true_rtx, false_rtx)
4742 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4744 true_code = reversed_comparison_code (cond, NULL);
4746 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4749 SUBST (XEXP (x, 1), false_rtx);
4750 SUBST (XEXP (x, 2), true_rtx);
4752 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4755 /* It is possible that the conditional has been simplified out. */
4756 true_code = GET_CODE (cond);
4757 comparison_p = GET_RTX_CLASS (true_code) == '<';
4760 /* If the two arms are identical, we don't need the comparison. */
4762 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4765 /* Convert a == b ? b : a to "a". */
4766 if (true_code == EQ && ! side_effects_p (cond)
4767 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4768 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4769 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4771 else if (true_code == NE && ! side_effects_p (cond)
4772 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4773 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4774 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4777 /* Look for cases where we have (abs x) or (neg (abs X)). */
4779 if (GET_MODE_CLASS (mode) == MODE_INT
4780 && GET_CODE (false_rtx) == NEG
4781 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4783 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4784 && ! side_effects_p (true_rtx))
4789 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4793 simplify_gen_unary (NEG, mode,
4794 simplify_gen_unary (ABS, mode, true_rtx, mode),
4800 /* Look for MIN or MAX. */
4802 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4804 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4805 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4806 && ! side_effects_p (cond))
4811 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4814 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4817 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4820 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4825 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4826 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4827 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4828 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4829 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4830 neither 1 or -1, but it isn't worth checking for. */
4832 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4833 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4835 rtx t = make_compound_operation (true_rtx, SET);
4836 rtx f = make_compound_operation (false_rtx, SET);
4837 rtx cond_op0 = XEXP (cond, 0);
4838 rtx cond_op1 = XEXP (cond, 1);
4839 enum rtx_code op = NIL, extend_op = NIL;
4840 enum machine_mode m = mode;
4841 rtx z = 0, c1 = NULL_RTX;
4843 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4844 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4845 || GET_CODE (t) == ASHIFT
4846 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4847 && rtx_equal_p (XEXP (t, 0), f))
4848 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4850 /* If an identity-zero op is commutative, check whether there
4851 would be a match if we swapped the operands. */
4852 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4853 || GET_CODE (t) == XOR)
4854 && rtx_equal_p (XEXP (t, 1), f))
4855 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4856 else if (GET_CODE (t) == SIGN_EXTEND
4857 && (GET_CODE (XEXP (t, 0)) == PLUS
4858 || GET_CODE (XEXP (t, 0)) == MINUS
4859 || GET_CODE (XEXP (t, 0)) == IOR
4860 || GET_CODE (XEXP (t, 0)) == XOR
4861 || GET_CODE (XEXP (t, 0)) == ASHIFT
4862 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4863 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4864 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4865 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4866 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4867 && (num_sign_bit_copies (f, GET_MODE (f))
4869 (GET_MODE_BITSIZE (mode)
4870 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4872 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4873 extend_op = SIGN_EXTEND;
4874 m = GET_MODE (XEXP (t, 0));
4876 else if (GET_CODE (t) == SIGN_EXTEND
4877 && (GET_CODE (XEXP (t, 0)) == PLUS
4878 || GET_CODE (XEXP (t, 0)) == IOR
4879 || GET_CODE (XEXP (t, 0)) == XOR)
4880 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4881 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4882 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4883 && (num_sign_bit_copies (f, GET_MODE (f))
4885 (GET_MODE_BITSIZE (mode)
4886 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4888 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4889 extend_op = SIGN_EXTEND;
4890 m = GET_MODE (XEXP (t, 0));
4892 else if (GET_CODE (t) == ZERO_EXTEND
4893 && (GET_CODE (XEXP (t, 0)) == PLUS
4894 || GET_CODE (XEXP (t, 0)) == MINUS
4895 || GET_CODE (XEXP (t, 0)) == IOR
4896 || GET_CODE (XEXP (t, 0)) == XOR
4897 || GET_CODE (XEXP (t, 0)) == ASHIFT
4898 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4899 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4900 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4901 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4902 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4903 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4904 && ((nonzero_bits (f, GET_MODE (f))
4905 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4908 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4909 extend_op = ZERO_EXTEND;
4910 m = GET_MODE (XEXP (t, 0));
4912 else if (GET_CODE (t) == ZERO_EXTEND
4913 && (GET_CODE (XEXP (t, 0)) == PLUS
4914 || GET_CODE (XEXP (t, 0)) == IOR
4915 || GET_CODE (XEXP (t, 0)) == XOR)
4916 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4917 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4918 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4919 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4920 && ((nonzero_bits (f, GET_MODE (f))
4921 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4924 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4925 extend_op = ZERO_EXTEND;
4926 m = GET_MODE (XEXP (t, 0));
4931 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4932 pc_rtx, pc_rtx, 0, 0);
4933 temp = gen_binary (MULT, m, temp,
4934 gen_binary (MULT, m, c1, const_true_rtx));
4935 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4936 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4938 if (extend_op != NIL)
4939 temp = simplify_gen_unary (extend_op, mode, temp, m);
4945 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4946 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4947 negation of a single bit, we can convert this operation to a shift. We
4948 can actually do this more generally, but it doesn't seem worth it. */
4950 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4951 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4952 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4953 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4954 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4955 == GET_MODE_BITSIZE (mode))
4956 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4958 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4959 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4964 /* Simplify X, a SET expression. Return the new expression. */
4970 rtx src = SET_SRC (x);
4971 rtx dest = SET_DEST (x);
4972 enum machine_mode mode
4973 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4977 /* (set (pc) (return)) gets written as (return). */
4978 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4981 /* Now that we know for sure which bits of SRC we are using, see if we can
4982 simplify the expression for the object knowing that we only need the
4985 if (GET_MODE_CLASS (mode) == MODE_INT)
4987 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4988 SUBST (SET_SRC (x), src);
4991 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4992 the comparison result and try to simplify it unless we already have used
4993 undobuf.other_insn. */
4994 if ((GET_CODE (src) == COMPARE
4999 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5000 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5001 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5002 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5004 enum rtx_code old_code = GET_CODE (*cc_use);
5005 enum rtx_code new_code;
5007 int other_changed = 0;
5008 enum machine_mode compare_mode = GET_MODE (dest);
5010 if (GET_CODE (src) == COMPARE)
5011 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5013 op0 = src, op1 = const0_rtx;
5015 /* Simplify our comparison, if possible. */
5016 new_code = simplify_comparison (old_code, &op0, &op1);
5018 #ifdef EXTRA_CC_MODES
5019 /* If this machine has CC modes other than CCmode, check to see if we
5020 need to use a different CC mode here. */
5021 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5022 #endif /* EXTRA_CC_MODES */
5024 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5025 /* If the mode changed, we have to change SET_DEST, the mode in the
5026 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5027 a hard register, just build new versions with the proper mode. If it
5028 is a pseudo, we lose unless it is only time we set the pseudo, in
5029 which case we can safely change its mode. */
5030 if (compare_mode != GET_MODE (dest))
5032 unsigned int regno = REGNO (dest);
5033 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5035 if (regno < FIRST_PSEUDO_REGISTER
5036 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5038 if (regno >= FIRST_PSEUDO_REGISTER)
5039 SUBST (regno_reg_rtx[regno], new_dest);
5041 SUBST (SET_DEST (x), new_dest);
5042 SUBST (XEXP (*cc_use, 0), new_dest);
5050 /* If the code changed, we have to build a new comparison in
5051 undobuf.other_insn. */
5052 if (new_code != old_code)
5054 unsigned HOST_WIDE_INT mask;
5056 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5059 /* If the only change we made was to change an EQ into an NE or
5060 vice versa, OP0 has only one bit that might be nonzero, and OP1
5061 is zero, check if changing the user of the condition code will
5062 produce a valid insn. If it won't, we can keep the original code
5063 in that insn by surrounding our operation with an XOR. */
5065 if (((old_code == NE && new_code == EQ)
5066 || (old_code == EQ && new_code == NE))
5067 && ! other_changed && op1 == const0_rtx
5068 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5069 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5071 rtx pat = PATTERN (other_insn), note = 0;
5073 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5074 && ! check_asm_operands (pat)))
5076 PUT_CODE (*cc_use, old_code);
5079 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5087 undobuf.other_insn = other_insn;
5090 /* If we are now comparing against zero, change our source if
5091 needed. If we do not use cc0, we always have a COMPARE. */
5092 if (op1 == const0_rtx && dest == cc0_rtx)
5094 SUBST (SET_SRC (x), op0);
5100 /* Otherwise, if we didn't previously have a COMPARE in the
5101 correct mode, we need one. */
5102 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5104 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5109 /* Otherwise, update the COMPARE if needed. */
5110 SUBST (XEXP (src, 0), op0);
5111 SUBST (XEXP (src, 1), op1);
5116 /* Get SET_SRC in a form where we have placed back any
5117 compound expressions. Then do the checks below. */
5118 src = make_compound_operation (src, SET);
5119 SUBST (SET_SRC (x), src);
5122 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5123 and X being a REG or (subreg (reg)), we may be able to convert this to
5124 (set (subreg:m2 x) (op)).
5126 We can always do this if M1 is narrower than M2 because that means that
5127 we only care about the low bits of the result.
5129 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5130 perform a narrower operation than requested since the high-order bits will
5131 be undefined. On machine where it is defined, this transformation is safe
5132 as long as M1 and M2 have the same number of words. */
5134 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5135 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5136 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5138 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5139 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5140 #ifndef WORD_REGISTER_OPERATIONS
5141 && (GET_MODE_SIZE (GET_MODE (src))
5142 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5144 #ifdef CLASS_CANNOT_CHANGE_MODE
5145 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5146 && (TEST_HARD_REG_BIT
5147 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5149 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5150 GET_MODE (SUBREG_REG (src))))
5152 && (GET_CODE (dest) == REG
5153 || (GET_CODE (dest) == SUBREG
5154 && GET_CODE (SUBREG_REG (dest)) == REG)))
5156 SUBST (SET_DEST (x),
5157 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5159 SUBST (SET_SRC (x), SUBREG_REG (src));
5161 src = SET_SRC (x), dest = SET_DEST (x);
5165 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5168 && GET_CODE (src) == SUBREG
5169 && subreg_lowpart_p (src)
5170 && (GET_MODE_BITSIZE (GET_MODE (src))
5171 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5173 rtx inner = SUBREG_REG (src);
5174 enum machine_mode inner_mode = GET_MODE (inner);
5176 /* Here we make sure that we don't have a sign bit on. */
5177 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5178 && (nonzero_bits (inner, inner_mode)
5179 < ((unsigned HOST_WIDE_INT) 1
5180 << (GET_MODE_BITSIZE (inner_mode) - 1))))
5182 SUBST (SET_SRC (x), inner);
5188 #ifdef LOAD_EXTEND_OP
5189 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5190 would require a paradoxical subreg. Replace the subreg with a
5191 zero_extend to avoid the reload that would otherwise be required. */
5193 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5194 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5195 && SUBREG_BYTE (src) == 0
5196 && (GET_MODE_SIZE (GET_MODE (src))
5197 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5198 && GET_CODE (SUBREG_REG (src)) == MEM)
5201 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5202 GET_MODE (src), SUBREG_REG (src)));
5208 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5209 are comparing an item known to be 0 or -1 against 0, use a logical
5210 operation instead. Check for one of the arms being an IOR of the other
5211 arm with some value. We compute three terms to be IOR'ed together. In
5212 practice, at most two will be nonzero. Then we do the IOR's. */
5214 if (GET_CODE (dest) != PC
5215 && GET_CODE (src) == IF_THEN_ELSE
5216 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5217 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5218 && XEXP (XEXP (src, 0), 1) == const0_rtx
5219 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5220 #ifdef HAVE_conditional_move
5221 && ! can_conditionally_move_p (GET_MODE (src))
5223 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5224 GET_MODE (XEXP (XEXP (src, 0), 0)))
5225 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5226 && ! side_effects_p (src))
5228 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5229 ? XEXP (src, 1) : XEXP (src, 2));
5230 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5231 ? XEXP (src, 2) : XEXP (src, 1));
5232 rtx term1 = const0_rtx, term2, term3;
5234 if (GET_CODE (true_rtx) == IOR
5235 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5236 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5237 else if (GET_CODE (true_rtx) == IOR
5238 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5239 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5240 else if (GET_CODE (false_rtx) == IOR
5241 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5242 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5243 else if (GET_CODE (false_rtx) == IOR
5244 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5245 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5247 term2 = gen_binary (AND, GET_MODE (src),
5248 XEXP (XEXP (src, 0), 0), true_rtx);
5249 term3 = gen_binary (AND, GET_MODE (src),
5250 simplify_gen_unary (NOT, GET_MODE (src),
5251 XEXP (XEXP (src, 0), 0),
5256 gen_binary (IOR, GET_MODE (src),
5257 gen_binary (IOR, GET_MODE (src), term1, term2),
5263 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5264 whole thing fail. */
5265 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5267 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5270 /* Convert this into a field assignment operation, if possible. */
5271 return make_field_assignment (x);
5274 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5275 result. LAST is nonzero if this is the last retry. */
5278 simplify_logical (x, last)
5282 enum machine_mode mode = GET_MODE (x);
5283 rtx op0 = XEXP (x, 0);
5284 rtx op1 = XEXP (x, 1);
5287 switch (GET_CODE (x))
5290 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5291 insn (and may simplify more). */
5292 if (GET_CODE (op0) == XOR
5293 && rtx_equal_p (XEXP (op0, 0), op1)
5294 && ! side_effects_p (op1))
5295 x = gen_binary (AND, mode,
5296 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5299 if (GET_CODE (op0) == XOR
5300 && rtx_equal_p (XEXP (op0, 1), op1)
5301 && ! side_effects_p (op1))
5302 x = gen_binary (AND, mode,
5303 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5306 /* Similarly for (~(A ^ B)) & A. */
5307 if (GET_CODE (op0) == NOT
5308 && GET_CODE (XEXP (op0, 0)) == XOR
5309 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5310 && ! side_effects_p (op1))
5311 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5313 if (GET_CODE (op0) == NOT
5314 && GET_CODE (XEXP (op0, 0)) == XOR
5315 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5316 && ! side_effects_p (op1))
5317 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5319 /* We can call simplify_and_const_int only if we don't lose
5320 any (sign) bits when converting INTVAL (op1) to
5321 "unsigned HOST_WIDE_INT". */
5322 if (GET_CODE (op1) == CONST_INT
5323 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5324 || INTVAL (op1) > 0))
5326 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5328 /* If we have (ior (and (X C1) C2)) and the next restart would be
5329 the last, simplify this by making C1 as small as possible
5332 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5333 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5334 && GET_CODE (op1) == CONST_INT)
5335 return gen_binary (IOR, mode,
5336 gen_binary (AND, mode, XEXP (op0, 0),
5337 GEN_INT (INTVAL (XEXP (op0, 1))
5338 & ~INTVAL (op1))), op1);
5340 if (GET_CODE (x) != AND)
5343 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5344 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5345 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5348 /* Convert (A | B) & A to A. */
5349 if (GET_CODE (op0) == IOR
5350 && (rtx_equal_p (XEXP (op0, 0), op1)
5351 || rtx_equal_p (XEXP (op0, 1), op1))
5352 && ! side_effects_p (XEXP (op0, 0))
5353 && ! side_effects_p (XEXP (op0, 1)))
5356 /* In the following group of tests (and those in case IOR below),
5357 we start with some combination of logical operations and apply
5358 the distributive law followed by the inverse distributive law.
5359 Most of the time, this results in no change. However, if some of
5360 the operands are the same or inverses of each other, simplifications
5363 For example, (and (ior A B) (not B)) can occur as the result of
5364 expanding a bit field assignment. When we apply the distributive
5365 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5366 which then simplifies to (and (A (not B))).
5368 If we have (and (ior A B) C), apply the distributive law and then
5369 the inverse distributive law to see if things simplify. */
5371 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5373 x = apply_distributive_law
5374 (gen_binary (GET_CODE (op0), mode,
5375 gen_binary (AND, mode, XEXP (op0, 0), op1),
5376 gen_binary (AND, mode, XEXP (op0, 1),
5378 if (GET_CODE (x) != AND)
5382 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5383 return apply_distributive_law
5384 (gen_binary (GET_CODE (op1), mode,
5385 gen_binary (AND, mode, XEXP (op1, 0), op0),
5386 gen_binary (AND, mode, XEXP (op1, 1),
5389 /* Similarly, taking advantage of the fact that
5390 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5392 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5393 return apply_distributive_law
5394 (gen_binary (XOR, mode,
5395 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5396 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5399 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5400 return apply_distributive_law
5401 (gen_binary (XOR, mode,
5402 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5403 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5407 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5408 if (GET_CODE (op1) == CONST_INT
5409 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5410 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5413 /* Convert (A & B) | A to A. */
5414 if (GET_CODE (op0) == AND
5415 && (rtx_equal_p (XEXP (op0, 0), op1)
5416 || rtx_equal_p (XEXP (op0, 1), op1))
5417 && ! side_effects_p (XEXP (op0, 0))
5418 && ! side_effects_p (XEXP (op0, 1)))
5421 /* If we have (ior (and A B) C), apply the distributive law and then
5422 the inverse distributive law to see if things simplify. */
5424 if (GET_CODE (op0) == AND)
5426 x = apply_distributive_law
5427 (gen_binary (AND, mode,
5428 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5429 gen_binary (IOR, mode, XEXP (op0, 1),
5432 if (GET_CODE (x) != IOR)
5436 if (GET_CODE (op1) == AND)
5438 x = apply_distributive_law
5439 (gen_binary (AND, mode,
5440 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5441 gen_binary (IOR, mode, XEXP (op1, 1),
5444 if (GET_CODE (x) != IOR)
5448 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5449 mode size to (rotate A CX). */
5451 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5452 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5453 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5454 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5455 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5456 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5457 == GET_MODE_BITSIZE (mode)))
5458 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5459 (GET_CODE (op0) == ASHIFT
5460 ? XEXP (op0, 1) : XEXP (op1, 1)));
5462 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5463 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5464 does not affect any of the bits in OP1, it can really be done
5465 as a PLUS and we can associate. We do this by seeing if OP1
5466 can be safely shifted left C bits. */
5467 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5468 && GET_CODE (XEXP (op0, 0)) == PLUS
5469 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5470 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5471 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5473 int count = INTVAL (XEXP (op0, 1));
5474 HOST_WIDE_INT mask = INTVAL (op1) << count;
5476 if (mask >> count == INTVAL (op1)
5477 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5479 SUBST (XEXP (XEXP (op0, 0), 1),
5480 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5487 /* If we are XORing two things that have no bits in common,
5488 convert them into an IOR. This helps to detect rotation encoded
5489 using those methods and possibly other simplifications. */
5491 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5492 && (nonzero_bits (op0, mode)
5493 & nonzero_bits (op1, mode)) == 0)
5494 return (gen_binary (IOR, mode, op0, op1));
5496 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5497 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5500 int num_negated = 0;
5502 if (GET_CODE (op0) == NOT)
5503 num_negated++, op0 = XEXP (op0, 0);
5504 if (GET_CODE (op1) == NOT)
5505 num_negated++, op1 = XEXP (op1, 0);
5507 if (num_negated == 2)
5509 SUBST (XEXP (x, 0), op0);
5510 SUBST (XEXP (x, 1), op1);
5512 else if (num_negated == 1)
5514 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5518 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5519 correspond to a machine insn or result in further simplifications
5520 if B is a constant. */
5522 if (GET_CODE (op0) == AND
5523 && rtx_equal_p (XEXP (op0, 1), op1)
5524 && ! side_effects_p (op1))
5525 return gen_binary (AND, mode,
5526 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5529 else if (GET_CODE (op0) == AND
5530 && rtx_equal_p (XEXP (op0, 0), op1)
5531 && ! side_effects_p (op1))
5532 return gen_binary (AND, mode,
5533 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5536 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5537 comparison if STORE_FLAG_VALUE is 1. */
5538 if (STORE_FLAG_VALUE == 1
5539 && op1 == const1_rtx
5540 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5541 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5545 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5546 is (lt foo (const_int 0)), so we can perform the above
5547 simplification if STORE_FLAG_VALUE is 1. */
5549 if (STORE_FLAG_VALUE == 1
5550 && op1 == const1_rtx
5551 && GET_CODE (op0) == LSHIFTRT
5552 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5553 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5554 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5556 /* (xor (comparison foo bar) (const_int sign-bit))
5557 when STORE_FLAG_VALUE is the sign bit. */
5558 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5559 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5560 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5561 && op1 == const_true_rtx
5562 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5563 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5576 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5577 operations" because they can be replaced with two more basic operations.
5578 ZERO_EXTEND is also considered "compound" because it can be replaced with
5579 an AND operation, which is simpler, though only one operation.
5581 The function expand_compound_operation is called with an rtx expression
5582 and will convert it to the appropriate shifts and AND operations,
5583 simplifying at each stage.
5585 The function make_compound_operation is called to convert an expression
5586 consisting of shifts and ANDs into the equivalent compound expression.
5587 It is the inverse of this function, loosely speaking. */
5590 expand_compound_operation (x)
5593 unsigned HOST_WIDE_INT pos = 0, len;
5595 unsigned int modewidth;
5598 switch (GET_CODE (x))
5603 /* We can't necessarily use a const_int for a multiword mode;
5604 it depends on implicitly extending the value.
5605 Since we don't know the right way to extend it,
5606 we can't tell whether the implicit way is right.
5608 Even for a mode that is no wider than a const_int,
5609 we can't win, because we need to sign extend one of its bits through
5610 the rest of it, and we don't know which bit. */
5611 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5614 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5615 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5616 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5617 reloaded. If not for that, MEM's would very rarely be safe.
5619 Reject MODEs bigger than a word, because we might not be able
5620 to reference a two-register group starting with an arbitrary register
5621 (and currently gen_lowpart might crash for a SUBREG). */
5623 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5626 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5627 /* If the inner object has VOIDmode (the only way this can happen
5628 is if it is an ASM_OPERANDS), we can't do anything since we don't
5629 know how much masking to do. */
5638 /* If the operand is a CLOBBER, just return it. */
5639 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5642 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5643 || GET_CODE (XEXP (x, 2)) != CONST_INT
5644 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5647 len = INTVAL (XEXP (x, 1));
5648 pos = INTVAL (XEXP (x, 2));
5650 /* If this goes outside the object being extracted, replace the object
5651 with a (use (mem ...)) construct that only combine understands
5652 and is used only for this purpose. */
5653 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5654 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5656 if (BITS_BIG_ENDIAN)
5657 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5664 /* Convert sign extension to zero extension, if we know that the high
5665 bit is not set, as this is easier to optimize. It will be converted
5666 back to cheaper alternative in make_extraction. */
5667 if (GET_CODE (x) == SIGN_EXTEND
5668 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5669 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5670 & ~(((unsigned HOST_WIDE_INT)
5671 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5675 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5676 return expand_compound_operation (temp);
5679 /* We can optimize some special cases of ZERO_EXTEND. */
5680 if (GET_CODE (x) == ZERO_EXTEND)
5682 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5683 know that the last value didn't have any inappropriate bits
5685 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5686 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5687 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5688 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5689 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5690 return XEXP (XEXP (x, 0), 0);
5692 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5693 if (GET_CODE (XEXP (x, 0)) == SUBREG
5694 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5695 && subreg_lowpart_p (XEXP (x, 0))
5696 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5697 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5698 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5699 return SUBREG_REG (XEXP (x, 0));
5701 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5702 is a comparison and STORE_FLAG_VALUE permits. This is like
5703 the first case, but it works even when GET_MODE (x) is larger
5704 than HOST_WIDE_INT. */
5705 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5706 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5707 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5708 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5709 <= HOST_BITS_PER_WIDE_INT)
5710 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5711 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5712 return XEXP (XEXP (x, 0), 0);
5714 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5715 if (GET_CODE (XEXP (x, 0)) == SUBREG
5716 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5717 && subreg_lowpart_p (XEXP (x, 0))
5718 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5719 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5720 <= HOST_BITS_PER_WIDE_INT)
5721 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5722 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5723 return SUBREG_REG (XEXP (x, 0));
5727 /* If we reach here, we want to return a pair of shifts. The inner
5728 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5729 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5730 logical depending on the value of UNSIGNEDP.
5732 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5733 converted into an AND of a shift.
5735 We must check for the case where the left shift would have a negative
5736 count. This can happen in a case like (x >> 31) & 255 on machines
5737 that can't shift by a constant. On those machines, we would first
5738 combine the shift with the AND to produce a variable-position
5739 extraction. Then the constant of 31 would be substituted in to produce
5740 a such a position. */
5742 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5743 if (modewidth + len >= pos)
5744 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5746 simplify_shift_const (NULL_RTX, ASHIFT,
5749 modewidth - pos - len),
5752 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5753 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5754 simplify_shift_const (NULL_RTX, LSHIFTRT,
5757 ((HOST_WIDE_INT) 1 << len) - 1);
5759 /* Any other cases we can't handle. */
5762 /* If we couldn't do this for some reason, return the original
5764 if (GET_CODE (tem) == CLOBBER)
5770 /* X is a SET which contains an assignment of one object into
5771 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5772 or certain SUBREGS). If possible, convert it into a series of
5775 We half-heartedly support variable positions, but do not at all
5776 support variable lengths. */
5779 expand_field_assignment (x)
5783 rtx pos; /* Always counts from low bit. */
5786 enum machine_mode compute_mode;
5788 /* Loop until we find something we can't simplify. */
5791 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5792 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5794 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5795 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5796 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5798 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5799 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5801 inner = XEXP (SET_DEST (x), 0);
5802 len = INTVAL (XEXP (SET_DEST (x), 1));
5803 pos = XEXP (SET_DEST (x), 2);
5805 /* If the position is constant and spans the width of INNER,
5806 surround INNER with a USE to indicate this. */
5807 if (GET_CODE (pos) == CONST_INT
5808 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5809 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5811 if (BITS_BIG_ENDIAN)
5813 if (GET_CODE (pos) == CONST_INT)
5814 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5816 else if (GET_CODE (pos) == MINUS
5817 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5818 && (INTVAL (XEXP (pos, 1))
5819 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5820 /* If position is ADJUST - X, new position is X. */
5821 pos = XEXP (pos, 0);
5823 pos = gen_binary (MINUS, GET_MODE (pos),
5824 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5830 /* A SUBREG between two modes that occupy the same numbers of words
5831 can be done by moving the SUBREG to the source. */
5832 else if (GET_CODE (SET_DEST (x)) == SUBREG
5833 /* We need SUBREGs to compute nonzero_bits properly. */
5834 && nonzero_sign_valid
5835 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5836 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5837 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5838 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5840 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5841 gen_lowpart_for_combine
5842 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5849 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5850 inner = SUBREG_REG (inner);
5852 compute_mode = GET_MODE (inner);
5854 /* Don't attempt bitwise arithmetic on non-integral modes. */
5855 if (! INTEGRAL_MODE_P (compute_mode))
5857 enum machine_mode imode;
5859 /* Something is probably seriously wrong if this matches. */
5860 if (! FLOAT_MODE_P (compute_mode))
5863 /* Try to find an integral mode to pun with. */
5864 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5865 if (imode == BLKmode)
5868 compute_mode = imode;
5869 inner = gen_lowpart_for_combine (imode, inner);
5872 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5873 if (len < HOST_BITS_PER_WIDE_INT)
5874 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5878 /* Now compute the equivalent expression. Make a copy of INNER
5879 for the SET_DEST in case it is a MEM into which we will substitute;
5880 we don't want shared RTL in that case. */
5882 (VOIDmode, copy_rtx (inner),
5883 gen_binary (IOR, compute_mode,
5884 gen_binary (AND, compute_mode,
5885 simplify_gen_unary (NOT, compute_mode,
5891 gen_binary (ASHIFT, compute_mode,
5892 gen_binary (AND, compute_mode,
5893 gen_lowpart_for_combine
5894 (compute_mode, SET_SRC (x)),
5902 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5903 it is an RTX that represents a variable starting position; otherwise,
5904 POS is the (constant) starting bit position (counted from the LSB).
5906 INNER may be a USE. This will occur when we started with a bitfield
5907 that went outside the boundary of the object in memory, which is
5908 allowed on most machines. To isolate this case, we produce a USE
5909 whose mode is wide enough and surround the MEM with it. The only
5910 code that understands the USE is this routine. If it is not removed,
5911 it will cause the resulting insn not to match.
5913 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5916 IN_DEST is non-zero if this is a reference in the destination of a
5917 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5918 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5921 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5922 ZERO_EXTRACT should be built even for bits starting at bit 0.
5924 MODE is the desired mode of the result (if IN_DEST == 0).
5926 The result is an RTX for the extraction or NULL_RTX if the target
5930 make_extraction (mode, inner, pos, pos_rtx, len,
5931 unsignedp, in_dest, in_compare)
5932 enum machine_mode mode;
5936 unsigned HOST_WIDE_INT len;
5938 int in_dest, in_compare;
5940 /* This mode describes the size of the storage area
5941 to fetch the overall value from. Within that, we
5942 ignore the POS lowest bits, etc. */
5943 enum machine_mode is_mode = GET_MODE (inner);
5944 enum machine_mode inner_mode;
5945 enum machine_mode wanted_inner_mode = byte_mode;
5946 enum machine_mode wanted_inner_reg_mode = word_mode;
5947 enum machine_mode pos_mode = word_mode;
5948 enum machine_mode extraction_mode = word_mode;
5949 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5952 rtx orig_pos_rtx = pos_rtx;
5953 HOST_WIDE_INT orig_pos;
5955 /* Get some information about INNER and get the innermost object. */
5956 if (GET_CODE (inner) == USE)
5957 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5958 /* We don't need to adjust the position because we set up the USE
5959 to pretend that it was a full-word object. */
5960 spans_byte = 1, inner = XEXP (inner, 0);
5961 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5963 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5964 consider just the QI as the memory to extract from.
5965 The subreg adds or removes high bits; its mode is
5966 irrelevant to the meaning of this extraction,
5967 since POS and LEN count from the lsb. */
5968 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5969 is_mode = GET_MODE (SUBREG_REG (inner));
5970 inner = SUBREG_REG (inner);
5972 else if (GET_CODE (inner) == ASHIFT
5973 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5974 && pos_rtx == 0 && pos == 0
5975 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5977 /* We're extracting the least significant bits of an rtx
5978 (ashift X (const_int C)), where LEN > C. Extract the
5979 least significant (LEN - C) bits of X, giving an rtx
5980 whose mode is MODE, then shift it left C times. */
5981 new = make_extraction (mode, XEXP (inner, 0),
5982 0, 0, len - INTVAL (XEXP (inner, 1)),
5983 unsignedp, in_dest, in_compare);
5985 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5988 inner_mode = GET_MODE (inner);
5990 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5991 pos = INTVAL (pos_rtx), pos_rtx = 0;
5993 /* See if this can be done without an extraction. We never can if the
5994 width of the field is not the same as that of some integer mode. For
5995 registers, we can only avoid the extraction if the position is at the
5996 low-order bit and this is either not in the destination or we have the
5997 appropriate STRICT_LOW_PART operation available.
5999 For MEM, we can avoid an extract if the field starts on an appropriate
6000 boundary and we can change the mode of the memory reference. However,
6001 we cannot directly access the MEM if we have a USE and the underlying
6002 MEM is not TMODE. This combination means that MEM was being used in a
6003 context where bits outside its mode were being referenced; that is only
6004 valid in bit-field insns. */
6006 if (tmode != BLKmode
6007 && ! (spans_byte && inner_mode != tmode)
6008 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6009 && GET_CODE (inner) != MEM
6011 || (GET_CODE (inner) == REG
6012 && have_insn_for (STRICT_LOW_PART, tmode))))
6013 || (GET_CODE (inner) == MEM && pos_rtx == 0
6015 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6016 : BITS_PER_UNIT)) == 0
6017 /* We can't do this if we are widening INNER_MODE (it
6018 may not be aligned, for one thing). */
6019 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6020 && (inner_mode == tmode
6021 || (! mode_dependent_address_p (XEXP (inner, 0))
6022 && ! MEM_VOLATILE_P (inner))))))
6024 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6025 field. If the original and current mode are the same, we need not
6026 adjust the offset. Otherwise, we do if bytes big endian.
6028 If INNER is not a MEM, get a piece consisting of just the field
6029 of interest (in this case POS % BITS_PER_WORD must be 0). */
6031 if (GET_CODE (inner) == MEM)
6033 HOST_WIDE_INT offset;
6035 /* POS counts from lsb, but make OFFSET count in memory order. */
6036 if (BYTES_BIG_ENDIAN)
6037 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6039 offset = pos / BITS_PER_UNIT;
6041 new = adjust_address_nv (inner, tmode, offset);
6043 else if (GET_CODE (inner) == REG)
6045 /* We can't call gen_lowpart_for_combine here since we always want
6046 a SUBREG and it would sometimes return a new hard register. */
6047 if (tmode != inner_mode)
6049 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6051 if (WORDS_BIG_ENDIAN
6052 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6053 final_word = ((GET_MODE_SIZE (inner_mode)
6054 - GET_MODE_SIZE (tmode))
6055 / UNITS_PER_WORD) - final_word;
6057 final_word *= UNITS_PER_WORD;
6058 if (BYTES_BIG_ENDIAN &&
6059 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6060 final_word += (GET_MODE_SIZE (inner_mode)
6061 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6063 new = gen_rtx_SUBREG (tmode, inner, final_word);
6069 new = force_to_mode (inner, tmode,
6070 len >= HOST_BITS_PER_WIDE_INT
6071 ? ~(unsigned HOST_WIDE_INT) 0
6072 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6075 /* If this extraction is going into the destination of a SET,
6076 make a STRICT_LOW_PART unless we made a MEM. */
6079 return (GET_CODE (new) == MEM ? new
6080 : (GET_CODE (new) != SUBREG
6081 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6082 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6087 if (GET_CODE (new) == CONST_INT)
6088 return gen_int_mode (INTVAL (new), mode);
6090 /* If we know that no extraneous bits are set, and that the high
6091 bit is not set, convert the extraction to the cheaper of
6092 sign and zero extension, that are equivalent in these cases. */
6093 if (flag_expensive_optimizations
6094 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6095 && ((nonzero_bits (new, tmode)
6096 & ~(((unsigned HOST_WIDE_INT)
6097 GET_MODE_MASK (tmode))
6101 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6102 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6104 /* Prefer ZERO_EXTENSION, since it gives more information to
6106 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6111 /* Otherwise, sign- or zero-extend unless we already are in the
6114 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6118 /* Unless this is a COMPARE or we have a funny memory reference,
6119 don't do anything with zero-extending field extracts starting at
6120 the low-order bit since they are simple AND operations. */
6121 if (pos_rtx == 0 && pos == 0 && ! in_dest
6122 && ! in_compare && ! spans_byte && unsignedp)
6125 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6126 we would be spanning bytes or if the position is not a constant and the
6127 length is not 1. In all other cases, we would only be going outside
6128 our object in cases when an original shift would have been
6130 if (! spans_byte && GET_CODE (inner) == MEM
6131 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6132 || (pos_rtx != 0 && len != 1)))
6135 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6136 and the mode for the result. */
6137 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6139 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6140 pos_mode = mode_for_extraction (EP_insv, 2);
6141 extraction_mode = mode_for_extraction (EP_insv, 3);
6144 if (! in_dest && unsignedp
6145 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6147 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6148 pos_mode = mode_for_extraction (EP_extzv, 3);
6149 extraction_mode = mode_for_extraction (EP_extzv, 0);
6152 if (! in_dest && ! unsignedp
6153 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6155 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6156 pos_mode = mode_for_extraction (EP_extv, 3);
6157 extraction_mode = mode_for_extraction (EP_extv, 0);
6160 /* Never narrow an object, since that might not be safe. */
6162 if (mode != VOIDmode
6163 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6164 extraction_mode = mode;
6166 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6167 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6168 pos_mode = GET_MODE (pos_rtx);
6170 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6171 if we have to change the mode of memory and cannot, the desired mode is
6173 if (GET_CODE (inner) != MEM)
6174 wanted_inner_mode = wanted_inner_reg_mode;
6175 else if (inner_mode != wanted_inner_mode
6176 && (mode_dependent_address_p (XEXP (inner, 0))
6177 || MEM_VOLATILE_P (inner)))
6178 wanted_inner_mode = extraction_mode;
6182 if (BITS_BIG_ENDIAN)
6184 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6185 BITS_BIG_ENDIAN style. If position is constant, compute new
6186 position. Otherwise, build subtraction.
6187 Note that POS is relative to the mode of the original argument.
6188 If it's a MEM we need to recompute POS relative to that.
6189 However, if we're extracting from (or inserting into) a register,
6190 we want to recompute POS relative to wanted_inner_mode. */
6191 int width = (GET_CODE (inner) == MEM
6192 ? GET_MODE_BITSIZE (is_mode)
6193 : GET_MODE_BITSIZE (wanted_inner_mode));
6196 pos = width - len - pos;
6199 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6200 /* POS may be less than 0 now, but we check for that below.
6201 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6204 /* If INNER has a wider mode, make it smaller. If this is a constant
6205 extract, try to adjust the byte to point to the byte containing
6207 if (wanted_inner_mode != VOIDmode
6208 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6209 && ((GET_CODE (inner) == MEM
6210 && (inner_mode == wanted_inner_mode
6211 || (! mode_dependent_address_p (XEXP (inner, 0))
6212 && ! MEM_VOLATILE_P (inner))))))
6216 /* The computations below will be correct if the machine is big
6217 endian in both bits and bytes or little endian in bits and bytes.
6218 If it is mixed, we must adjust. */
6220 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6221 adjust OFFSET to compensate. */
6222 if (BYTES_BIG_ENDIAN
6224 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6225 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6227 /* If this is a constant position, we can move to the desired byte. */
6230 offset += pos / BITS_PER_UNIT;
6231 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6234 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6236 && is_mode != wanted_inner_mode)
6237 offset = (GET_MODE_SIZE (is_mode)
6238 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6240 if (offset != 0 || inner_mode != wanted_inner_mode)
6241 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6244 /* If INNER is not memory, we can always get it into the proper mode. If we
6245 are changing its mode, POS must be a constant and smaller than the size
6247 else if (GET_CODE (inner) != MEM)
6249 if (GET_MODE (inner) != wanted_inner_mode
6251 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6254 inner = force_to_mode (inner, wanted_inner_mode,
6256 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6257 ? ~(unsigned HOST_WIDE_INT) 0
6258 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6263 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6264 have to zero extend. Otherwise, we can just use a SUBREG. */
6266 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6268 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6270 /* If we know that no extraneous bits are set, and that the high
6271 bit is not set, convert extraction to cheaper one - either
6272 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6274 if (flag_expensive_optimizations
6275 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6276 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6277 & ~(((unsigned HOST_WIDE_INT)
6278 GET_MODE_MASK (GET_MODE (pos_rtx)))
6282 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6284 /* Prefer ZERO_EXTENSION, since it gives more information to
6286 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6291 else if (pos_rtx != 0
6292 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6293 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6295 /* Make POS_RTX unless we already have it and it is correct. If we don't
6296 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6298 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6299 pos_rtx = orig_pos_rtx;
6301 else if (pos_rtx == 0)
6302 pos_rtx = GEN_INT (pos);
6304 /* Make the required operation. See if we can use existing rtx. */
6305 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6306 extraction_mode, inner, GEN_INT (len), pos_rtx);
6308 new = gen_lowpart_for_combine (mode, new);
6313 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6314 with any other operations in X. Return X without that shift if so. */
6317 extract_left_shift (x, count)
6321 enum rtx_code code = GET_CODE (x);
6322 enum machine_mode mode = GET_MODE (x);
6328 /* This is the shift itself. If it is wide enough, we will return
6329 either the value being shifted if the shift count is equal to
6330 COUNT or a shift for the difference. */
6331 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6332 && INTVAL (XEXP (x, 1)) >= count)
6333 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6334 INTVAL (XEXP (x, 1)) - count);
6338 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6339 return simplify_gen_unary (code, mode, tem, mode);
6343 case PLUS: case IOR: case XOR: case AND:
6344 /* If we can safely shift this constant and we find the inner shift,
6345 make a new operation. */
6346 if (GET_CODE (XEXP (x,1)) == CONST_INT
6347 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6348 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6349 return gen_binary (code, mode, tem,
6350 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6361 /* Look at the expression rooted at X. Look for expressions
6362 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6363 Form these expressions.
6365 Return the new rtx, usually just X.
6367 Also, for machines like the VAX that don't have logical shift insns,
6368 try to convert logical to arithmetic shift operations in cases where
6369 they are equivalent. This undoes the canonicalizations to logical
6370 shifts done elsewhere.
6372 We try, as much as possible, to re-use rtl expressions to save memory.
6374 IN_CODE says what kind of expression we are processing. Normally, it is
6375 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6376 being kludges), it is MEM. When processing the arguments of a comparison
6377 or a COMPARE against zero, it is COMPARE. */
6380 make_compound_operation (x, in_code)
6382 enum rtx_code in_code;
6384 enum rtx_code code = GET_CODE (x);
6385 enum machine_mode mode = GET_MODE (x);
6386 int mode_width = GET_MODE_BITSIZE (mode);
6388 enum rtx_code next_code;
6394 /* Select the code to be used in recursive calls. Once we are inside an
6395 address, we stay there. If we have a comparison, set to COMPARE,
6396 but once inside, go back to our default of SET. */
6398 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6399 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6400 && XEXP (x, 1) == const0_rtx) ? COMPARE
6401 : in_code == COMPARE ? SET : in_code);
6403 /* Process depending on the code of this operation. If NEW is set
6404 non-zero, it will be returned. */
6409 /* Convert shifts by constants into multiplications if inside
6411 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6412 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6413 && INTVAL (XEXP (x, 1)) >= 0)
6415 new = make_compound_operation (XEXP (x, 0), next_code);
6416 new = gen_rtx_MULT (mode, new,
6417 GEN_INT ((HOST_WIDE_INT) 1
6418 << INTVAL (XEXP (x, 1))));
6423 /* If the second operand is not a constant, we can't do anything
6425 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6428 /* If the constant is a power of two minus one and the first operand
6429 is a logical right shift, make an extraction. */
6430 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6431 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6433 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6434 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6435 0, in_code == COMPARE);
6438 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6439 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6440 && subreg_lowpart_p (XEXP (x, 0))
6441 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6442 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6444 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6446 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6447 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6448 0, in_code == COMPARE);
6450 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6451 else if ((GET_CODE (XEXP (x, 0)) == XOR
6452 || GET_CODE (XEXP (x, 0)) == IOR)
6453 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6454 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6455 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6457 /* Apply the distributive law, and then try to make extractions. */
6458 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6459 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6461 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6463 new = make_compound_operation (new, in_code);
6466 /* If we are have (and (rotate X C) M) and C is larger than the number
6467 of bits in M, this is an extraction. */
6469 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6470 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6471 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6472 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6474 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6475 new = make_extraction (mode, new,
6476 (GET_MODE_BITSIZE (mode)
6477 - INTVAL (XEXP (XEXP (x, 0), 1))),
6478 NULL_RTX, i, 1, 0, in_code == COMPARE);
6481 /* On machines without logical shifts, if the operand of the AND is
6482 a logical shift and our mask turns off all the propagated sign
6483 bits, we can replace the logical shift with an arithmetic shift. */
6484 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6485 && !have_insn_for (LSHIFTRT, mode)
6486 && have_insn_for (ASHIFTRT, mode)
6487 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6488 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6489 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6490 && mode_width <= HOST_BITS_PER_WIDE_INT)
6492 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6494 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6495 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6497 gen_rtx_ASHIFTRT (mode,
6498 make_compound_operation
6499 (XEXP (XEXP (x, 0), 0), next_code),
6500 XEXP (XEXP (x, 0), 1)));
6503 /* If the constant is one less than a power of two, this might be
6504 representable by an extraction even if no shift is present.
6505 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6506 we are in a COMPARE. */
6507 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6508 new = make_extraction (mode,
6509 make_compound_operation (XEXP (x, 0),
6511 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6513 /* If we are in a comparison and this is an AND with a power of two,
6514 convert this into the appropriate bit extract. */
6515 else if (in_code == COMPARE
6516 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6517 new = make_extraction (mode,
6518 make_compound_operation (XEXP (x, 0),
6520 i, NULL_RTX, 1, 1, 0, 1);
6525 /* If the sign bit is known to be zero, replace this with an
6526 arithmetic shift. */
6527 if (have_insn_for (ASHIFTRT, mode)
6528 && ! have_insn_for (LSHIFTRT, mode)
6529 && mode_width <= HOST_BITS_PER_WIDE_INT
6530 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6532 new = gen_rtx_ASHIFTRT (mode,
6533 make_compound_operation (XEXP (x, 0),
6539 /* ... fall through ... */
6545 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6546 this is a SIGN_EXTRACT. */
6547 if (GET_CODE (rhs) == CONST_INT
6548 && GET_CODE (lhs) == ASHIFT
6549 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6550 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6552 new = make_compound_operation (XEXP (lhs, 0), next_code);
6553 new = make_extraction (mode, new,
6554 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6555 NULL_RTX, mode_width - INTVAL (rhs),
6556 code == LSHIFTRT, 0, in_code == COMPARE);
6560 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6561 If so, try to merge the shifts into a SIGN_EXTEND. We could
6562 also do this for some cases of SIGN_EXTRACT, but it doesn't
6563 seem worth the effort; the case checked for occurs on Alpha. */
6565 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6566 && ! (GET_CODE (lhs) == SUBREG
6567 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6568 && GET_CODE (rhs) == CONST_INT
6569 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6570 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6571 new = make_extraction (mode, make_compound_operation (new, next_code),
6572 0, NULL_RTX, mode_width - INTVAL (rhs),
6573 code == LSHIFTRT, 0, in_code == COMPARE);
6578 /* Call ourselves recursively on the inner expression. If we are
6579 narrowing the object and it has a different RTL code from
6580 what it originally did, do this SUBREG as a force_to_mode. */
6582 tem = make_compound_operation (SUBREG_REG (x), in_code);
6583 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6584 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6585 && subreg_lowpart_p (x))
6587 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6590 /* If we have something other than a SUBREG, we might have
6591 done an expansion, so rerun ourselves. */
6592 if (GET_CODE (newer) != SUBREG)
6593 newer = make_compound_operation (newer, in_code);
6598 /* If this is a paradoxical subreg, and the new code is a sign or
6599 zero extension, omit the subreg and widen the extension. If it
6600 is a regular subreg, we can still get rid of the subreg by not
6601 widening so much, or in fact removing the extension entirely. */
6602 if ((GET_CODE (tem) == SIGN_EXTEND
6603 || GET_CODE (tem) == ZERO_EXTEND)
6604 && subreg_lowpart_p (x))
6606 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6607 || (GET_MODE_SIZE (mode) >
6608 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6609 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6611 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6622 x = gen_lowpart_for_combine (mode, new);
6623 code = GET_CODE (x);
6626 /* Now recursively process each operand of this operation. */
6627 fmt = GET_RTX_FORMAT (code);
6628 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6631 new = make_compound_operation (XEXP (x, i), next_code);
6632 SUBST (XEXP (x, i), new);
6638 /* Given M see if it is a value that would select a field of bits
6639 within an item, but not the entire word. Return -1 if not.
6640 Otherwise, return the starting position of the field, where 0 is the
6643 *PLEN is set to the length of the field. */
6646 get_pos_from_mask (m, plen)
6647 unsigned HOST_WIDE_INT m;
6648 unsigned HOST_WIDE_INT *plen;
6650 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6651 int pos = exact_log2 (m & -m);
6657 /* Now shift off the low-order zero bits and see if we have a power of
6659 len = exact_log2 ((m >> pos) + 1);
6668 /* See if X can be simplified knowing that we will only refer to it in
6669 MODE and will only refer to those bits that are nonzero in MASK.
6670 If other bits are being computed or if masking operations are done
6671 that select a superset of the bits in MASK, they can sometimes be
6674 Return a possibly simplified expression, but always convert X to
6675 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6677 Also, if REG is non-zero and X is a register equal in value to REG,
6680 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6681 are all off in X. This is used when X will be complemented, by either
6682 NOT, NEG, or XOR. */
6685 force_to_mode (x, mode, mask, reg, just_select)
6687 enum machine_mode mode;
6688 unsigned HOST_WIDE_INT mask;
6692 enum rtx_code code = GET_CODE (x);
6693 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6694 enum machine_mode op_mode;
6695 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6698 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6699 code below will do the wrong thing since the mode of such an
6700 expression is VOIDmode.
6702 Also do nothing if X is a CLOBBER; this can happen if X was
6703 the return value from a call to gen_lowpart_for_combine. */
6704 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6707 /* We want to perform the operation is its present mode unless we know
6708 that the operation is valid in MODE, in which case we do the operation
6710 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6711 && have_insn_for (code, mode))
6712 ? mode : GET_MODE (x));
6714 /* It is not valid to do a right-shift in a narrower mode
6715 than the one it came in with. */
6716 if ((code == LSHIFTRT || code == ASHIFTRT)
6717 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6718 op_mode = GET_MODE (x);
6720 /* Truncate MASK to fit OP_MODE. */
6722 mask &= GET_MODE_MASK (op_mode);
6724 /* When we have an arithmetic operation, or a shift whose count we
6725 do not know, we need to assume that all bit the up to the highest-order
6726 bit in MASK will be needed. This is how we form such a mask. */
6728 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6729 ? GET_MODE_MASK (op_mode)
6730 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6733 fuller_mask = ~(HOST_WIDE_INT) 0;
6735 /* Determine what bits of X are guaranteed to be (non)zero. */
6736 nonzero = nonzero_bits (x, mode);
6738 /* If none of the bits in X are needed, return a zero. */
6739 if (! just_select && (nonzero & mask) == 0)
6742 /* If X is a CONST_INT, return a new one. Do this here since the
6743 test below will fail. */
6744 if (GET_CODE (x) == CONST_INT)
6745 return gen_int_mode (INTVAL (x) & mask, mode);
6747 /* If X is narrower than MODE and we want all the bits in X's mode, just
6748 get X in the proper mode. */
6749 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6750 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6751 return gen_lowpart_for_combine (mode, x);
6753 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6754 MASK are already known to be zero in X, we need not do anything. */
6755 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6761 /* If X is a (clobber (const_int)), return it since we know we are
6762 generating something that won't match. */
6766 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6767 spanned the boundary of the MEM. If we are now masking so it is
6768 within that boundary, we don't need the USE any more. */
6769 if (! BITS_BIG_ENDIAN
6770 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6771 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6778 x = expand_compound_operation (x);
6779 if (GET_CODE (x) != code)
6780 return force_to_mode (x, mode, mask, reg, next_select);
6784 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6785 || rtx_equal_p (reg, get_last_value (x))))
6790 if (subreg_lowpart_p (x)
6791 /* We can ignore the effect of this SUBREG if it narrows the mode or
6792 if the constant masks to zero all the bits the mode doesn't
6794 && ((GET_MODE_SIZE (GET_MODE (x))
6795 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6797 & GET_MODE_MASK (GET_MODE (x))
6798 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6799 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6803 /* If this is an AND with a constant, convert it into an AND
6804 whose constant is the AND of that constant with MASK. If it
6805 remains an AND of MASK, delete it since it is redundant. */
6807 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6809 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6810 mask & INTVAL (XEXP (x, 1)));
6812 /* If X is still an AND, see if it is an AND with a mask that
6813 is just some low-order bits. If so, and it is MASK, we don't
6816 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6817 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6821 /* If it remains an AND, try making another AND with the bits
6822 in the mode mask that aren't in MASK turned on. If the
6823 constant in the AND is wide enough, this might make a
6824 cheaper constant. */
6826 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6827 && GET_MODE_MASK (GET_MODE (x)) != mask
6828 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6830 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6831 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6832 int width = GET_MODE_BITSIZE (GET_MODE (x));
6835 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6836 number, sign extend it. */
6837 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6838 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6839 cval |= (HOST_WIDE_INT) -1 << width;
6841 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6842 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6852 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6853 low-order bits (as in an alignment operation) and FOO is already
6854 aligned to that boundary, mask C1 to that boundary as well.
6855 This may eliminate that PLUS and, later, the AND. */
6858 unsigned int width = GET_MODE_BITSIZE (mode);
6859 unsigned HOST_WIDE_INT smask = mask;
6861 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6862 number, sign extend it. */
6864 if (width < HOST_BITS_PER_WIDE_INT
6865 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6866 smask |= (HOST_WIDE_INT) -1 << width;
6868 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6869 && exact_log2 (- smask) >= 0
6870 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6871 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6872 return force_to_mode (plus_constant (XEXP (x, 0),
6873 (INTVAL (XEXP (x, 1)) & smask)),
6874 mode, smask, reg, next_select);
6877 /* ... fall through ... */
6880 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6881 most significant bit in MASK since carries from those bits will
6882 affect the bits we are interested in. */
6887 /* If X is (minus C Y) where C's least set bit is larger than any bit
6888 in the mask, then we may replace with (neg Y). */
6889 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6890 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6891 & -INTVAL (XEXP (x, 0))))
6894 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6896 return force_to_mode (x, mode, mask, reg, next_select);
6899 /* Similarly, if C contains every bit in the mask, then we may
6900 replace with (not Y). */
6901 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6902 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6903 == INTVAL (XEXP (x, 0))))
6905 x = simplify_gen_unary (NOT, GET_MODE (x),
6906 XEXP (x, 1), GET_MODE (x));
6907 return force_to_mode (x, mode, mask, reg, next_select);
6915 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6916 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6917 operation which may be a bitfield extraction. Ensure that the
6918 constant we form is not wider than the mode of X. */
6920 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6921 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6922 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6923 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6924 && GET_CODE (XEXP (x, 1)) == CONST_INT
6925 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6926 + floor_log2 (INTVAL (XEXP (x, 1))))
6927 < GET_MODE_BITSIZE (GET_MODE (x)))
6928 && (INTVAL (XEXP (x, 1))
6929 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6931 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6932 << INTVAL (XEXP (XEXP (x, 0), 1)));
6933 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6934 XEXP (XEXP (x, 0), 0), temp);
6935 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6936 XEXP (XEXP (x, 0), 1));
6937 return force_to_mode (x, mode, mask, reg, next_select);
6941 /* For most binary operations, just propagate into the operation and
6942 change the mode if we have an operation of that mode. */
6944 op0 = gen_lowpart_for_combine (op_mode,
6945 force_to_mode (XEXP (x, 0), mode, mask,
6947 op1 = gen_lowpart_for_combine (op_mode,
6948 force_to_mode (XEXP (x, 1), mode, mask,
6951 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6952 x = gen_binary (code, op_mode, op0, op1);
6956 /* For left shifts, do the same, but just for the first operand.
6957 However, we cannot do anything with shifts where we cannot
6958 guarantee that the counts are smaller than the size of the mode
6959 because such a count will have a different meaning in a
6962 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6963 && INTVAL (XEXP (x, 1)) >= 0
6964 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6965 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6966 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6967 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6970 /* If the shift count is a constant and we can do arithmetic in
6971 the mode of the shift, refine which bits we need. Otherwise, use the
6972 conservative form of the mask. */
6973 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6974 && INTVAL (XEXP (x, 1)) >= 0
6975 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6976 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6977 mask >>= INTVAL (XEXP (x, 1));
6981 op0 = gen_lowpart_for_combine (op_mode,
6982 force_to_mode (XEXP (x, 0), op_mode,
6983 mask, reg, next_select));
6985 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6986 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6990 /* Here we can only do something if the shift count is a constant,
6991 this shift constant is valid for the host, and we can do arithmetic
6994 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6995 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6996 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6998 rtx inner = XEXP (x, 0);
6999 unsigned HOST_WIDE_INT inner_mask;
7001 /* Select the mask of the bits we need for the shift operand. */
7002 inner_mask = mask << INTVAL (XEXP (x, 1));
7004 /* We can only change the mode of the shift if we can do arithmetic
7005 in the mode of the shift and INNER_MASK is no wider than the
7006 width of OP_MODE. */
7007 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7008 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7009 op_mode = GET_MODE (x);
7011 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7013 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7014 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7017 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7018 shift and AND produces only copies of the sign bit (C2 is one less
7019 than a power of two), we can do this with just a shift. */
7021 if (GET_CODE (x) == LSHIFTRT
7022 && GET_CODE (XEXP (x, 1)) == CONST_INT
7023 /* The shift puts one of the sign bit copies in the least significant
7025 && ((INTVAL (XEXP (x, 1))
7026 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7027 >= GET_MODE_BITSIZE (GET_MODE (x)))
7028 && exact_log2 (mask + 1) >= 0
7029 /* Number of bits left after the shift must be more than the mask
7031 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7032 <= GET_MODE_BITSIZE (GET_MODE (x)))
7033 /* Must be more sign bit copies than the mask needs. */
7034 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7035 >= exact_log2 (mask + 1)))
7036 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7037 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7038 - exact_log2 (mask + 1)));
7043 /* If we are just looking for the sign bit, we don't need this shift at
7044 all, even if it has a variable count. */
7045 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7046 && (mask == ((unsigned HOST_WIDE_INT) 1
7047 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7048 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7050 /* If this is a shift by a constant, get a mask that contains those bits
7051 that are not copies of the sign bit. We then have two cases: If
7052 MASK only includes those bits, this can be a logical shift, which may
7053 allow simplifications. If MASK is a single-bit field not within
7054 those bits, we are requesting a copy of the sign bit and hence can
7055 shift the sign bit to the appropriate location. */
7057 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7058 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7062 /* If the considered data is wider than HOST_WIDE_INT, we can't
7063 represent a mask for all its bits in a single scalar.
7064 But we only care about the lower bits, so calculate these. */
7066 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7068 nonzero = ~(HOST_WIDE_INT) 0;
7070 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7071 is the number of bits a full-width mask would have set.
7072 We need only shift if these are fewer than nonzero can
7073 hold. If not, we must keep all bits set in nonzero. */
7075 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7076 < HOST_BITS_PER_WIDE_INT)
7077 nonzero >>= INTVAL (XEXP (x, 1))
7078 + HOST_BITS_PER_WIDE_INT
7079 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7083 nonzero = GET_MODE_MASK (GET_MODE (x));
7084 nonzero >>= INTVAL (XEXP (x, 1));
7087 if ((mask & ~nonzero) == 0
7088 || (i = exact_log2 (mask)) >= 0)
7090 x = simplify_shift_const
7091 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7092 i < 0 ? INTVAL (XEXP (x, 1))
7093 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7095 if (GET_CODE (x) != ASHIFTRT)
7096 return force_to_mode (x, mode, mask, reg, next_select);
7100 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7101 even if the shift count isn't a constant. */
7103 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7107 /* If this is a zero- or sign-extension operation that just affects bits
7108 we don't care about, remove it. Be sure the call above returned
7109 something that is still a shift. */
7111 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7112 && GET_CODE (XEXP (x, 1)) == CONST_INT
7113 && INTVAL (XEXP (x, 1)) >= 0
7114 && (INTVAL (XEXP (x, 1))
7115 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7116 && GET_CODE (XEXP (x, 0)) == ASHIFT
7117 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7118 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7119 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7126 /* If the shift count is constant and we can do computations
7127 in the mode of X, compute where the bits we care about are.
7128 Otherwise, we can't do anything. Don't change the mode of
7129 the shift or propagate MODE into the shift, though. */
7130 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7131 && INTVAL (XEXP (x, 1)) >= 0)
7133 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7134 GET_MODE (x), GEN_INT (mask),
7136 if (temp && GET_CODE(temp) == CONST_INT)
7138 force_to_mode (XEXP (x, 0), GET_MODE (x),
7139 INTVAL (temp), reg, next_select));
7144 /* If we just want the low-order bit, the NEG isn't needed since it
7145 won't change the low-order bit. */
7147 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7149 /* We need any bits less significant than the most significant bit in
7150 MASK since carries from those bits will affect the bits we are
7156 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7157 same as the XOR case above. Ensure that the constant we form is not
7158 wider than the mode of X. */
7160 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7161 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7162 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7163 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7164 < GET_MODE_BITSIZE (GET_MODE (x)))
7165 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7167 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7168 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7169 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7171 return force_to_mode (x, mode, mask, reg, next_select);
7174 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7175 use the full mask inside the NOT. */
7179 op0 = gen_lowpart_for_combine (op_mode,
7180 force_to_mode (XEXP (x, 0), mode, mask,
7182 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7183 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7187 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7188 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7189 which is equal to STORE_FLAG_VALUE. */
7190 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7191 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7192 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7193 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7198 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7199 written in a narrower mode. We play it safe and do not do so. */
7202 gen_lowpart_for_combine (GET_MODE (x),
7203 force_to_mode (XEXP (x, 1), mode,
7204 mask, reg, next_select)));
7206 gen_lowpart_for_combine (GET_MODE (x),
7207 force_to_mode (XEXP (x, 2), mode,
7208 mask, reg,next_select)));
7215 /* Ensure we return a value of the proper mode. */
7216 return gen_lowpart_for_combine (mode, x);
7219 /* Return nonzero if X is an expression that has one of two values depending on
7220 whether some other value is zero or nonzero. In that case, we return the
7221 value that is being tested, *PTRUE is set to the value if the rtx being
7222 returned has a nonzero value, and *PFALSE is set to the other alternative.
7224 If we return zero, we set *PTRUE and *PFALSE to X. */
7227 if_then_else_cond (x, ptrue, pfalse)
7229 rtx *ptrue, *pfalse;
7231 enum machine_mode mode = GET_MODE (x);
7232 enum rtx_code code = GET_CODE (x);
7233 rtx cond0, cond1, true0, true1, false0, false1;
7234 unsigned HOST_WIDE_INT nz;
7236 /* If we are comparing a value against zero, we are done. */
7237 if ((code == NE || code == EQ)
7238 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7240 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7241 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7245 /* If this is a unary operation whose operand has one of two values, apply
7246 our opcode to compute those values. */
7247 else if (GET_RTX_CLASS (code) == '1'
7248 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7250 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7251 *pfalse = simplify_gen_unary (code, mode, false0,
7252 GET_MODE (XEXP (x, 0)));
7256 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7257 make can't possibly match and would suppress other optimizations. */
7258 else if (code == COMPARE)
7261 /* If this is a binary operation, see if either side has only one of two
7262 values. If either one does or if both do and they are conditional on
7263 the same value, compute the new true and false values. */
7264 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7265 || GET_RTX_CLASS (code) == '<')
7267 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7268 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7270 if ((cond0 != 0 || cond1 != 0)
7271 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7273 /* If if_then_else_cond returned zero, then true/false are the
7274 same rtl. We must copy one of them to prevent invalid rtl
7277 true0 = copy_rtx (true0);
7278 else if (cond1 == 0)
7279 true1 = copy_rtx (true1);
7281 *ptrue = gen_binary (code, mode, true0, true1);
7282 *pfalse = gen_binary (code, mode, false0, false1);
7283 return cond0 ? cond0 : cond1;
7286 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7287 operands is zero when the other is non-zero, and vice-versa,
7288 and STORE_FLAG_VALUE is 1 or -1. */
7290 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7291 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7293 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7295 rtx op0 = XEXP (XEXP (x, 0), 1);
7296 rtx op1 = XEXP (XEXP (x, 1), 1);
7298 cond0 = XEXP (XEXP (x, 0), 0);
7299 cond1 = XEXP (XEXP (x, 1), 0);
7301 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7302 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7303 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7304 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7305 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7306 || ((swap_condition (GET_CODE (cond0))
7307 == combine_reversed_comparison_code (cond1))
7308 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7309 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7310 && ! side_effects_p (x))
7312 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7313 *pfalse = gen_binary (MULT, mode,
7315 ? simplify_gen_unary (NEG, mode, op1,
7323 /* Similarly for MULT, AND and UMIN, except that for these the result
7325 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7326 && (code == MULT || code == AND || code == UMIN)
7327 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7329 cond0 = XEXP (XEXP (x, 0), 0);
7330 cond1 = XEXP (XEXP (x, 1), 0);
7332 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7333 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7334 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7335 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7336 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7337 || ((swap_condition (GET_CODE (cond0))
7338 == combine_reversed_comparison_code (cond1))
7339 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7340 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7341 && ! side_effects_p (x))
7343 *ptrue = *pfalse = const0_rtx;
7349 else if (code == IF_THEN_ELSE)
7351 /* If we have IF_THEN_ELSE already, extract the condition and
7352 canonicalize it if it is NE or EQ. */
7353 cond0 = XEXP (x, 0);
7354 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7355 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7356 return XEXP (cond0, 0);
7357 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7359 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7360 return XEXP (cond0, 0);
7366 /* If X is a SUBREG, we can narrow both the true and false values
7367 if the inner expression, if there is a condition. */
7368 else if (code == SUBREG
7369 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7372 *ptrue = simplify_gen_subreg (mode, true0,
7373 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7374 *pfalse = simplify_gen_subreg (mode, false0,
7375 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7380 /* If X is a constant, this isn't special and will cause confusions
7381 if we treat it as such. Likewise if it is equivalent to a constant. */
7382 else if (CONSTANT_P (x)
7383 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7386 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7387 will be least confusing to the rest of the compiler. */
7388 else if (mode == BImode)
7390 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7394 /* If X is known to be either 0 or -1, those are the true and
7395 false values when testing X. */
7396 else if (x == constm1_rtx || x == const0_rtx
7397 || (mode != VOIDmode
7398 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7400 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7404 /* Likewise for 0 or a single bit. */
7405 else if (mode != VOIDmode
7406 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7407 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7409 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7413 /* Otherwise fail; show no condition with true and false values the same. */
7414 *ptrue = *pfalse = x;
7418 /* Return the value of expression X given the fact that condition COND
7419 is known to be true when applied to REG as its first operand and VAL
7420 as its second. X is known to not be shared and so can be modified in
7423 We only handle the simplest cases, and specifically those cases that
7424 arise with IF_THEN_ELSE expressions. */
7427 known_cond (x, cond, reg, val)
7432 enum rtx_code code = GET_CODE (x);
7437 if (side_effects_p (x))
7440 /* If either operand of the condition is a floating point value,
7441 then we have to avoid collapsing an EQ comparison. */
7443 && rtx_equal_p (x, reg)
7444 && ! FLOAT_MODE_P (GET_MODE (x))
7445 && ! FLOAT_MODE_P (GET_MODE (val)))
7448 if (cond == UNEQ && rtx_equal_p (x, reg))
7451 /* If X is (abs REG) and we know something about REG's relationship
7452 with zero, we may be able to simplify this. */
7454 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7457 case GE: case GT: case EQ:
7460 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7462 GET_MODE (XEXP (x, 0)));
7467 /* The only other cases we handle are MIN, MAX, and comparisons if the
7468 operands are the same as REG and VAL. */
7470 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7472 if (rtx_equal_p (XEXP (x, 0), val))
7473 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7475 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7477 if (GET_RTX_CLASS (code) == '<')
7479 if (comparison_dominates_p (cond, code))
7480 return const_true_rtx;
7482 code = combine_reversed_comparison_code (x);
7484 && comparison_dominates_p (cond, code))
7489 else if (code == SMAX || code == SMIN
7490 || code == UMIN || code == UMAX)
7492 int unsignedp = (code == UMIN || code == UMAX);
7494 /* Do not reverse the condition when it is NE or EQ.
7495 This is because we cannot conclude anything about
7496 the value of 'SMAX (x, y)' when x is not equal to y,
7497 but we can when x equals y. */
7498 if ((code == SMAX || code == UMAX)
7499 && ! (cond == EQ || cond == NE))
7500 cond = reverse_condition (cond);
7505 return unsignedp ? x : XEXP (x, 1);
7507 return unsignedp ? x : XEXP (x, 0);
7509 return unsignedp ? XEXP (x, 1) : x;
7511 return unsignedp ? XEXP (x, 0) : x;
7518 else if (code == SUBREG)
7520 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7521 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7523 if (SUBREG_REG (x) != r)
7525 /* We must simplify subreg here, before we lose track of the
7526 original inner_mode. */
7527 new = simplify_subreg (GET_MODE (x), r,
7528 inner_mode, SUBREG_BYTE (x));
7532 SUBST (SUBREG_REG (x), r);
7537 /* We don't have to handle SIGN_EXTEND here, because even in the
7538 case of replacing something with a modeless CONST_INT, a
7539 CONST_INT is already (supposed to be) a valid sign extension for
7540 its narrower mode, which implies it's already properly
7541 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7542 story is different. */
7543 else if (code == ZERO_EXTEND)
7545 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7546 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7548 if (XEXP (x, 0) != r)
7550 /* We must simplify the zero_extend here, before we lose
7551 track of the original inner_mode. */
7552 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7557 SUBST (XEXP (x, 0), r);
7563 fmt = GET_RTX_FORMAT (code);
7564 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7567 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7568 else if (fmt[i] == 'E')
7569 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7570 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7577 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7578 assignment as a field assignment. */
7581 rtx_equal_for_field_assignment_p (x, y)
7585 if (x == y || rtx_equal_p (x, y))
7588 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7591 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7592 Note that all SUBREGs of MEM are paradoxical; otherwise they
7593 would have been rewritten. */
7594 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7595 && GET_CODE (SUBREG_REG (y)) == MEM
7596 && rtx_equal_p (SUBREG_REG (y),
7597 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7600 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7601 && GET_CODE (SUBREG_REG (x)) == MEM
7602 && rtx_equal_p (SUBREG_REG (x),
7603 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7606 /* We used to see if get_last_value of X and Y were the same but that's
7607 not correct. In one direction, we'll cause the assignment to have
7608 the wrong destination and in the case, we'll import a register into this
7609 insn that might have already have been dead. So fail if none of the
7610 above cases are true. */
7614 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7615 Return that assignment if so.
7617 We only handle the most common cases. */
7620 make_field_assignment (x)
7623 rtx dest = SET_DEST (x);
7624 rtx src = SET_SRC (x);
7629 unsigned HOST_WIDE_INT len;
7631 enum machine_mode mode;
7633 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7634 a clear of a one-bit field. We will have changed it to
7635 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7638 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7639 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7640 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7641 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7643 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7646 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7650 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7651 && subreg_lowpart_p (XEXP (src, 0))
7652 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7653 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7654 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7655 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7656 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7658 assign = make_extraction (VOIDmode, dest, 0,
7659 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7662 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7666 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7668 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7669 && XEXP (XEXP (src, 0), 0) == const1_rtx
7670 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7672 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7675 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7679 /* The other case we handle is assignments into a constant-position
7680 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7681 a mask that has all one bits except for a group of zero bits and
7682 OTHER is known to have zeros where C1 has ones, this is such an
7683 assignment. Compute the position and length from C1. Shift OTHER
7684 to the appropriate position, force it to the required mode, and
7685 make the extraction. Check for the AND in both operands. */
7687 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7690 rhs = expand_compound_operation (XEXP (src, 0));
7691 lhs = expand_compound_operation (XEXP (src, 1));
7693 if (GET_CODE (rhs) == AND
7694 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7695 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7696 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7697 else if (GET_CODE (lhs) == AND
7698 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7699 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7700 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7704 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7705 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7706 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7707 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7710 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7714 /* The mode to use for the source is the mode of the assignment, or of
7715 what is inside a possible STRICT_LOW_PART. */
7716 mode = (GET_CODE (assign) == STRICT_LOW_PART
7717 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7719 /* Shift OTHER right POS places and make it the source, restricting it
7720 to the proper length and mode. */
7722 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7723 GET_MODE (src), other, pos),
7725 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7726 ? ~(unsigned HOST_WIDE_INT) 0
7727 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7730 return gen_rtx_SET (VOIDmode, assign, src);
7733 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7737 apply_distributive_law (x)
7740 enum rtx_code code = GET_CODE (x);
7741 rtx lhs, rhs, other;
7743 enum rtx_code inner_code;
7745 /* Distributivity is not true for floating point.
7746 It can change the value. So don't do it.
7747 -- rms and moshier@world.std.com. */
7748 if (FLOAT_MODE_P (GET_MODE (x)))
7751 /* The outer operation can only be one of the following: */
7752 if (code != IOR && code != AND && code != XOR
7753 && code != PLUS && code != MINUS)
7756 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7758 /* If either operand is a primitive we can't do anything, so get out
7760 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7761 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7764 lhs = expand_compound_operation (lhs);
7765 rhs = expand_compound_operation (rhs);
7766 inner_code = GET_CODE (lhs);
7767 if (inner_code != GET_CODE (rhs))
7770 /* See if the inner and outer operations distribute. */
7777 /* These all distribute except over PLUS. */
7778 if (code == PLUS || code == MINUS)
7783 if (code != PLUS && code != MINUS)
7788 /* This is also a multiply, so it distributes over everything. */
7792 /* Non-paradoxical SUBREGs distributes over all operations, provided
7793 the inner modes and byte offsets are the same, this is an extraction
7794 of a low-order part, we don't convert an fp operation to int or
7795 vice versa, and we would not be converting a single-word
7796 operation into a multi-word operation. The latter test is not
7797 required, but it prevents generating unneeded multi-word operations.
7798 Some of the previous tests are redundant given the latter test, but
7799 are retained because they are required for correctness.
7801 We produce the result slightly differently in this case. */
7803 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7804 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7805 || ! subreg_lowpart_p (lhs)
7806 || (GET_MODE_CLASS (GET_MODE (lhs))
7807 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7808 || (GET_MODE_SIZE (GET_MODE (lhs))
7809 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7810 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7813 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7814 SUBREG_REG (lhs), SUBREG_REG (rhs));
7815 return gen_lowpart_for_combine (GET_MODE (x), tem);
7821 /* Set LHS and RHS to the inner operands (A and B in the example
7822 above) and set OTHER to the common operand (C in the example).
7823 These is only one way to do this unless the inner operation is
7825 if (GET_RTX_CLASS (inner_code) == 'c'
7826 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7827 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7828 else if (GET_RTX_CLASS (inner_code) == 'c'
7829 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7830 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7831 else if (GET_RTX_CLASS (inner_code) == 'c'
7832 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7833 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7834 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7835 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7839 /* Form the new inner operation, seeing if it simplifies first. */
7840 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7842 /* There is one exception to the general way of distributing:
7843 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7844 if (code == XOR && inner_code == IOR)
7847 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7850 /* We may be able to continuing distributing the result, so call
7851 ourselves recursively on the inner operation before forming the
7852 outer operation, which we return. */
7853 return gen_binary (inner_code, GET_MODE (x),
7854 apply_distributive_law (tem), other);
7857 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7860 Return an equivalent form, if different from X. Otherwise, return X. If
7861 X is zero, we are to always construct the equivalent form. */
7864 simplify_and_const_int (x, mode, varop, constop)
7866 enum machine_mode mode;
7868 unsigned HOST_WIDE_INT constop;
7870 unsigned HOST_WIDE_INT nonzero;
7873 /* Simplify VAROP knowing that we will be only looking at some of the
7876 Note by passing in CONSTOP, we guarantee that the bits not set in
7877 CONSTOP are not significant and will never be examined. We must
7878 ensure that is the case by explicitly masking out those bits
7879 before returning. */
7880 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7882 /* If VAROP is a CLOBBER, we will fail so return it. */
7883 if (GET_CODE (varop) == CLOBBER)
7886 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7887 to VAROP and return the new constant. */
7888 if (GET_CODE (varop) == CONST_INT)
7889 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7891 /* See what bits may be nonzero in VAROP. Unlike the general case of
7892 a call to nonzero_bits, here we don't care about bits outside
7895 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7897 /* Turn off all bits in the constant that are known to already be zero.
7898 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7899 which is tested below. */
7903 /* If we don't have any bits left, return zero. */
7907 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7908 a power of two, we can replace this with an ASHIFT. */
7909 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7910 && (i = exact_log2 (constop)) >= 0)
7911 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7913 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7914 or XOR, then try to apply the distributive law. This may eliminate
7915 operations if either branch can be simplified because of the AND.
7916 It may also make some cases more complex, but those cases probably
7917 won't match a pattern either with or without this. */
7919 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7921 gen_lowpart_for_combine
7923 apply_distributive_law
7924 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7925 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7926 XEXP (varop, 0), constop),
7927 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7928 XEXP (varop, 1), constop))));
7930 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7931 the AND and see if one of the operands simplifies to zero. If so, we
7932 may eliminate it. */
7934 if (GET_CODE (varop) == PLUS
7935 && exact_log2 (constop + 1) >= 0)
7939 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7940 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7941 if (o0 == const0_rtx)
7943 if (o1 == const0_rtx)
7947 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7948 if we already had one (just check for the simplest cases). */
7949 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7950 && GET_MODE (XEXP (x, 0)) == mode
7951 && SUBREG_REG (XEXP (x, 0)) == varop)
7952 varop = XEXP (x, 0);
7954 varop = gen_lowpart_for_combine (mode, varop);
7956 /* If we can't make the SUBREG, try to return what we were given. */
7957 if (GET_CODE (varop) == CLOBBER)
7958 return x ? x : varop;
7960 /* If we are only masking insignificant bits, return VAROP. */
7961 if (constop == nonzero)
7965 /* Otherwise, return an AND. */
7966 constop = trunc_int_for_mode (constop, mode);
7967 /* See how much, if any, of X we can use. */
7968 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7969 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7973 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7974 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7975 SUBST (XEXP (x, 1), GEN_INT (constop));
7977 SUBST (XEXP (x, 0), varop);
7984 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7985 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7986 is less useful. We can't allow both, because that results in exponential
7987 run time recursion. There is a nullstone testcase that triggered
7988 this. This macro avoids accidental uses of num_sign_bit_copies. */
7989 #define num_sign_bit_copies()
7991 /* Given an expression, X, compute which bits in X can be non-zero.
7992 We don't care about bits outside of those defined in MODE.
7994 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7995 a shift, AND, or zero_extract, we can do better. */
7997 static unsigned HOST_WIDE_INT
7998 nonzero_bits (x, mode)
8000 enum machine_mode mode;
8002 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8003 unsigned HOST_WIDE_INT inner_nz;
8005 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8008 /* For floating-point values, assume all bits are needed. */
8009 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8012 /* If X is wider than MODE, use its mode instead. */
8013 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8015 mode = GET_MODE (x);
8016 nonzero = GET_MODE_MASK (mode);
8017 mode_width = GET_MODE_BITSIZE (mode);
8020 if (mode_width > HOST_BITS_PER_WIDE_INT)
8021 /* Our only callers in this case look for single bit values. So
8022 just return the mode mask. Those tests will then be false. */
8025 #ifndef WORD_REGISTER_OPERATIONS
8026 /* If MODE is wider than X, but both are a single word for both the host
8027 and target machines, we can compute this from which bits of the
8028 object might be nonzero in its own mode, taking into account the fact
8029 that on many CISC machines, accessing an object in a wider mode
8030 causes the high-order bits to become undefined. So they are
8031 not known to be zero. */
8033 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8034 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8035 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8036 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8038 nonzero &= nonzero_bits (x, GET_MODE (x));
8039 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8044 code = GET_CODE (x);
8048 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8049 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8050 all the bits above ptr_mode are known to be zero. */
8051 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8053 nonzero &= GET_MODE_MASK (ptr_mode);
8056 /* Include declared information about alignment of pointers. */
8057 /* ??? We don't properly preserve REG_POINTER changes across
8058 pointer-to-integer casts, so we can't trust it except for
8059 things that we know must be pointers. See execute/960116-1.c. */
8060 if ((x == stack_pointer_rtx
8061 || x == frame_pointer_rtx
8062 || x == arg_pointer_rtx)
8063 && REGNO_POINTER_ALIGN (REGNO (x)))
8065 unsigned HOST_WIDE_INT alignment
8066 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8068 #ifdef PUSH_ROUNDING
8069 /* If PUSH_ROUNDING is defined, it is possible for the
8070 stack to be momentarily aligned only to that amount,
8071 so we pick the least alignment. */
8072 if (x == stack_pointer_rtx && PUSH_ARGS)
8073 alignment = MIN (PUSH_ROUNDING (1), alignment);
8076 nonzero &= ~(alignment - 1);
8079 /* If X is a register whose nonzero bits value is current, use it.
8080 Otherwise, if X is a register whose value we can find, use that
8081 value. Otherwise, use the previously-computed global nonzero bits
8082 for this register. */
8084 if (reg_last_set_value[REGNO (x)] != 0
8085 && (reg_last_set_mode[REGNO (x)] == mode
8086 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8087 && GET_MODE_CLASS (mode) == MODE_INT))
8088 && (reg_last_set_label[REGNO (x)] == label_tick
8089 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8090 && REG_N_SETS (REGNO (x)) == 1
8091 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8093 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8094 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8096 tem = get_last_value (x);
8100 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8101 /* If X is narrower than MODE and TEM is a non-negative
8102 constant that would appear negative in the mode of X,
8103 sign-extend it for use in reg_nonzero_bits because some
8104 machines (maybe most) will actually do the sign-extension
8105 and this is the conservative approach.
8107 ??? For 2.5, try to tighten up the MD files in this regard
8108 instead of this kludge. */
8110 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8111 && GET_CODE (tem) == CONST_INT
8113 && 0 != (INTVAL (tem)
8114 & ((HOST_WIDE_INT) 1
8115 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8116 tem = GEN_INT (INTVAL (tem)
8117 | ((HOST_WIDE_INT) (-1)
8118 << GET_MODE_BITSIZE (GET_MODE (x))));
8120 return nonzero_bits (tem, mode) & nonzero;
8122 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8124 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8126 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8127 /* We don't know anything about the upper bits. */
8128 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8129 return nonzero & mask;
8135 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8136 /* If X is negative in MODE, sign-extend the value. */
8137 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8138 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8139 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8145 #ifdef LOAD_EXTEND_OP
8146 /* In many, if not most, RISC machines, reading a byte from memory
8147 zeros the rest of the register. Noticing that fact saves a lot
8148 of extra zero-extends. */
8149 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8150 nonzero &= GET_MODE_MASK (GET_MODE (x));
8155 case UNEQ: case LTGT:
8156 case GT: case GTU: case UNGT:
8157 case LT: case LTU: case UNLT:
8158 case GE: case GEU: case UNGE:
8159 case LE: case LEU: case UNLE:
8160 case UNORDERED: case ORDERED:
8162 /* If this produces an integer result, we know which bits are set.
8163 Code here used to clear bits outside the mode of X, but that is
8166 if (GET_MODE_CLASS (mode) == MODE_INT
8167 && mode_width <= HOST_BITS_PER_WIDE_INT)
8168 nonzero = STORE_FLAG_VALUE;
8173 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8174 and num_sign_bit_copies. */
8175 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8176 == GET_MODE_BITSIZE (GET_MODE (x)))
8180 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8181 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8186 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8187 and num_sign_bit_copies. */
8188 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8189 == GET_MODE_BITSIZE (GET_MODE (x)))
8195 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8199 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8200 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8201 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8205 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8206 Otherwise, show all the bits in the outer mode but not the inner
8208 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8209 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8211 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8213 & (((HOST_WIDE_INT) 1
8214 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8215 inner_nz |= (GET_MODE_MASK (mode)
8216 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8219 nonzero &= inner_nz;
8223 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8224 & nonzero_bits (XEXP (x, 1), mode));
8228 case UMIN: case UMAX: case SMIN: case SMAX:
8230 unsigned HOST_WIDE_INT nonzero0 = nonzero_bits (XEXP (x, 0), mode);
8232 /* Don't call nonzero_bits for the second time if it cannot change
8234 if ((nonzero & nonzero0) != nonzero)
8235 nonzero &= (nonzero0 | nonzero_bits (XEXP (x, 1), mode));
8239 case PLUS: case MINUS:
8241 case DIV: case UDIV:
8242 case MOD: case UMOD:
8243 /* We can apply the rules of arithmetic to compute the number of
8244 high- and low-order zero bits of these operations. We start by
8245 computing the width (position of the highest-order non-zero bit)
8246 and the number of low-order zero bits for each value. */
8248 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8249 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8250 int width0 = floor_log2 (nz0) + 1;
8251 int width1 = floor_log2 (nz1) + 1;
8252 int low0 = floor_log2 (nz0 & -nz0);
8253 int low1 = floor_log2 (nz1 & -nz1);
8254 HOST_WIDE_INT op0_maybe_minusp
8255 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8256 HOST_WIDE_INT op1_maybe_minusp
8257 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8258 unsigned int result_width = mode_width;
8264 result_width = MAX (width0, width1) + 1;
8265 result_low = MIN (low0, low1);
8268 result_low = MIN (low0, low1);
8271 result_width = width0 + width1;
8272 result_low = low0 + low1;
8277 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8278 result_width = width0;
8283 result_width = width0;
8288 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8289 result_width = MIN (width0, width1);
8290 result_low = MIN (low0, low1);
8295 result_width = MIN (width0, width1);
8296 result_low = MIN (low0, low1);
8302 if (result_width < mode_width)
8303 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8306 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8308 #ifdef POINTERS_EXTEND_UNSIGNED
8309 /* If pointers extend unsigned and this is an addition or subtraction
8310 to a pointer in Pmode, all the bits above ptr_mode are known to be
8312 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8313 && (code == PLUS || code == MINUS)
8314 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8315 nonzero &= GET_MODE_MASK (ptr_mode);
8321 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8322 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8323 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8327 /* If this is a SUBREG formed for a promoted variable that has
8328 been zero-extended, we know that at least the high-order bits
8329 are zero, though others might be too. */
8331 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8332 nonzero = (GET_MODE_MASK (GET_MODE (x))
8333 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8335 /* If the inner mode is a single word for both the host and target
8336 machines, we can compute this from which bits of the inner
8337 object might be nonzero. */
8338 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8339 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8340 <= HOST_BITS_PER_WIDE_INT))
8342 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8344 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8345 /* If this is a typical RISC machine, we only have to worry
8346 about the way loads are extended. */
8347 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8349 & (((unsigned HOST_WIDE_INT) 1
8350 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8352 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8355 /* On many CISC machines, accessing an object in a wider mode
8356 causes the high-order bits to become undefined. So they are
8357 not known to be zero. */
8358 if (GET_MODE_SIZE (GET_MODE (x))
8359 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8360 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8361 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8370 /* The nonzero bits are in two classes: any bits within MODE
8371 that aren't in GET_MODE (x) are always significant. The rest of the
8372 nonzero bits are those that are significant in the operand of
8373 the shift when shifted the appropriate number of bits. This
8374 shows that high-order bits are cleared by the right shift and
8375 low-order bits by left shifts. */
8376 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8377 && INTVAL (XEXP (x, 1)) >= 0
8378 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8380 enum machine_mode inner_mode = GET_MODE (x);
8381 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8382 int count = INTVAL (XEXP (x, 1));
8383 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8384 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8385 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8386 unsigned HOST_WIDE_INT outer = 0;
8388 if (mode_width > width)
8389 outer = (op_nonzero & nonzero & ~mode_mask);
8391 if (code == LSHIFTRT)
8393 else if (code == ASHIFTRT)
8397 /* If the sign bit may have been nonzero before the shift, we
8398 need to mark all the places it could have been copied to
8399 by the shift as possibly nonzero. */
8400 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8401 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8403 else if (code == ASHIFT)
8406 inner = ((inner << (count % width)
8407 | (inner >> (width - (count % width)))) & mode_mask);
8409 nonzero &= (outer | inner);
8414 /* This is at most the number of bits in the mode. */
8415 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8419 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8420 | nonzero_bits (XEXP (x, 2), mode));
8430 /* See the macro definition above. */
8431 #undef num_sign_bit_copies
8433 /* Return the number of bits at the high-order end of X that are known to
8434 be equal to the sign bit. X will be used in mode MODE; if MODE is
8435 VOIDmode, X will be used in its own mode. The returned value will always
8436 be between 1 and the number of bits in MODE. */
8439 num_sign_bit_copies (x, mode)
8441 enum machine_mode mode;
8443 enum rtx_code code = GET_CODE (x);
8444 unsigned int bitwidth;
8445 int num0, num1, result;
8446 unsigned HOST_WIDE_INT nonzero;
8449 /* If we weren't given a mode, use the mode of X. If the mode is still
8450 VOIDmode, we don't know anything. Likewise if one of the modes is
8453 if (mode == VOIDmode)
8454 mode = GET_MODE (x);
8456 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8459 bitwidth = GET_MODE_BITSIZE (mode);
8461 /* For a smaller object, just ignore the high bits. */
8462 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8464 num0 = num_sign_bit_copies (x, GET_MODE (x));
8466 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8469 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8471 #ifndef WORD_REGISTER_OPERATIONS
8472 /* If this machine does not do all register operations on the entire
8473 register and MODE is wider than the mode of X, we can say nothing
8474 at all about the high-order bits. */
8477 /* Likewise on machines that do, if the mode of the object is smaller
8478 than a word and loads of that size don't sign extend, we can say
8479 nothing about the high order bits. */
8480 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8481 #ifdef LOAD_EXTEND_OP
8482 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8493 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8494 /* If pointers extend signed and this is a pointer in Pmode, say that
8495 all the bits above ptr_mode are known to be sign bit copies. */
8496 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8498 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8501 if (reg_last_set_value[REGNO (x)] != 0
8502 && reg_last_set_mode[REGNO (x)] == mode
8503 && (reg_last_set_label[REGNO (x)] == label_tick
8504 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8505 && REG_N_SETS (REGNO (x)) == 1
8506 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8508 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8509 return reg_last_set_sign_bit_copies[REGNO (x)];
8511 tem = get_last_value (x);
8513 return num_sign_bit_copies (tem, mode);
8515 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8516 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8517 return reg_sign_bit_copies[REGNO (x)];
8521 #ifdef LOAD_EXTEND_OP
8522 /* Some RISC machines sign-extend all loads of smaller than a word. */
8523 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8524 return MAX (1, ((int) bitwidth
8525 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8530 /* If the constant is negative, take its 1's complement and remask.
8531 Then see how many zero bits we have. */
8532 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8533 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8534 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8535 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8537 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8540 /* If this is a SUBREG for a promoted object that is sign-extended
8541 and we are looking at it in a wider mode, we know that at least the
8542 high-order bits are known to be sign bit copies. */
8544 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8546 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8547 return MAX ((int) bitwidth
8548 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8552 /* For a smaller object, just ignore the high bits. */
8553 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8555 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8556 return MAX (1, (num0
8557 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8561 #ifdef WORD_REGISTER_OPERATIONS
8562 #ifdef LOAD_EXTEND_OP
8563 /* For paradoxical SUBREGs on machines where all register operations
8564 affect the entire register, just look inside. Note that we are
8565 passing MODE to the recursive call, so the number of sign bit copies
8566 will remain relative to that mode, not the inner mode. */
8568 /* This works only if loads sign extend. Otherwise, if we get a
8569 reload for the inner part, it may be loaded from the stack, and
8570 then we lose all sign bit copies that existed before the store
8573 if ((GET_MODE_SIZE (GET_MODE (x))
8574 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8575 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8576 return num_sign_bit_copies (SUBREG_REG (x), mode);
8582 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8583 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8587 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8588 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8591 /* For a smaller object, just ignore the high bits. */
8592 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8593 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8597 return num_sign_bit_copies (XEXP (x, 0), mode);
8599 case ROTATE: case ROTATERT:
8600 /* If we are rotating left by a number of bits less than the number
8601 of sign bit copies, we can just subtract that amount from the
8603 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8604 && INTVAL (XEXP (x, 1)) >= 0
8605 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8607 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8608 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8609 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8614 /* In general, this subtracts one sign bit copy. But if the value
8615 is known to be positive, the number of sign bit copies is the
8616 same as that of the input. Finally, if the input has just one bit
8617 that might be nonzero, all the bits are copies of the sign bit. */
8618 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8619 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8620 return num0 > 1 ? num0 - 1 : 1;
8622 nonzero = nonzero_bits (XEXP (x, 0), mode);
8627 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8632 case IOR: case AND: case XOR:
8633 case SMIN: case SMAX: case UMIN: case UMAX:
8634 /* Logical operations will preserve the number of sign-bit copies.
8635 MIN and MAX operations always return one of the operands. */
8636 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8637 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8638 return MIN (num0, num1);
8640 case PLUS: case MINUS:
8641 /* For addition and subtraction, we can have a 1-bit carry. However,
8642 if we are subtracting 1 from a positive number, there will not
8643 be such a carry. Furthermore, if the positive number is known to
8644 be 0 or 1, we know the result is either -1 or 0. */
8646 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8647 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8649 nonzero = nonzero_bits (XEXP (x, 0), mode);
8650 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8651 return (nonzero == 1 || nonzero == 0 ? bitwidth
8652 : bitwidth - floor_log2 (nonzero) - 1);
8655 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8656 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8657 result = MAX (1, MIN (num0, num1) - 1);
8659 #ifdef POINTERS_EXTEND_UNSIGNED
8660 /* If pointers extend signed and this is an addition or subtraction
8661 to a pointer in Pmode, all the bits above ptr_mode are known to be
8663 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8664 && (code == PLUS || code == MINUS)
8665 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8666 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8667 - GET_MODE_BITSIZE (ptr_mode) + 1),
8673 /* The number of bits of the product is the sum of the number of
8674 bits of both terms. However, unless one of the terms if known
8675 to be positive, we must allow for an additional bit since negating
8676 a negative number can remove one sign bit copy. */
8678 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8679 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8681 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8683 && (bitwidth > HOST_BITS_PER_WIDE_INT
8684 || (((nonzero_bits (XEXP (x, 0), mode)
8685 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8686 && ((nonzero_bits (XEXP (x, 1), mode)
8687 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8690 return MAX (1, result);
8693 /* The result must be <= the first operand. If the first operand
8694 has the high bit set, we know nothing about the number of sign
8696 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8698 else if ((nonzero_bits (XEXP (x, 0), mode)
8699 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8702 return num_sign_bit_copies (XEXP (x, 0), mode);
8705 /* The result must be <= the second operand. */
8706 return num_sign_bit_copies (XEXP (x, 1), mode);
8709 /* Similar to unsigned division, except that we have to worry about
8710 the case where the divisor is negative, in which case we have
8712 result = num_sign_bit_copies (XEXP (x, 0), mode);
8714 && (bitwidth > HOST_BITS_PER_WIDE_INT
8715 || (nonzero_bits (XEXP (x, 1), mode)
8716 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8722 result = num_sign_bit_copies (XEXP (x, 1), mode);
8724 && (bitwidth > HOST_BITS_PER_WIDE_INT
8725 || (nonzero_bits (XEXP (x, 1), mode)
8726 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8732 /* Shifts by a constant add to the number of bits equal to the
8734 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8735 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8736 && INTVAL (XEXP (x, 1)) > 0)
8737 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8742 /* Left shifts destroy copies. */
8743 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8744 || INTVAL (XEXP (x, 1)) < 0
8745 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8748 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8749 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8752 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8753 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8754 return MIN (num0, num1);
8756 case EQ: case NE: case GE: case GT: case LE: case LT:
8757 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8758 case GEU: case GTU: case LEU: case LTU:
8759 case UNORDERED: case ORDERED:
8760 /* If the constant is negative, take its 1's complement and remask.
8761 Then see how many zero bits we have. */
8762 nonzero = STORE_FLAG_VALUE;
8763 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8764 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8765 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8767 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8774 /* If we haven't been able to figure it out by one of the above rules,
8775 see if some of the high-order bits are known to be zero. If so,
8776 count those bits and return one less than that amount. If we can't
8777 safely compute the mask for this mode, always return BITWIDTH. */
8779 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8782 nonzero = nonzero_bits (x, mode);
8783 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8784 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8787 /* Return the number of "extended" bits there are in X, when interpreted
8788 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8789 unsigned quantities, this is the number of high-order zero bits.
8790 For signed quantities, this is the number of copies of the sign bit
8791 minus 1. In both case, this function returns the number of "spare"
8792 bits. For example, if two quantities for which this function returns
8793 at least 1 are added, the addition is known not to overflow.
8795 This function will always return 0 unless called during combine, which
8796 implies that it must be called from a define_split. */
8799 extended_count (x, mode, unsignedp)
8801 enum machine_mode mode;
8804 if (nonzero_sign_valid == 0)
8808 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8809 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8810 - floor_log2 (nonzero_bits (x, mode)))
8812 : num_sign_bit_copies (x, mode) - 1);
8815 /* This function is called from `simplify_shift_const' to merge two
8816 outer operations. Specifically, we have already found that we need
8817 to perform operation *POP0 with constant *PCONST0 at the outermost
8818 position. We would now like to also perform OP1 with constant CONST1
8819 (with *POP0 being done last).
8821 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8822 the resulting operation. *PCOMP_P is set to 1 if we would need to
8823 complement the innermost operand, otherwise it is unchanged.
8825 MODE is the mode in which the operation will be done. No bits outside
8826 the width of this mode matter. It is assumed that the width of this mode
8827 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8829 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8830 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8831 result is simply *PCONST0.
8833 If the resulting operation cannot be expressed as one operation, we
8834 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8837 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8838 enum rtx_code *pop0;
8839 HOST_WIDE_INT *pconst0;
8841 HOST_WIDE_INT const1;
8842 enum machine_mode mode;
8845 enum rtx_code op0 = *pop0;
8846 HOST_WIDE_INT const0 = *pconst0;
8848 const0 &= GET_MODE_MASK (mode);
8849 const1 &= GET_MODE_MASK (mode);
8851 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8855 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8858 if (op1 == NIL || op0 == SET)
8861 else if (op0 == NIL)
8862 op0 = op1, const0 = const1;
8864 else if (op0 == op1)
8888 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8889 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8892 /* If the two constants aren't the same, we can't do anything. The
8893 remaining six cases can all be done. */
8894 else if (const0 != const1)
8902 /* (a & b) | b == b */
8904 else /* op1 == XOR */
8905 /* (a ^ b) | b == a | b */
8911 /* (a & b) ^ b == (~a) & b */
8912 op0 = AND, *pcomp_p = 1;
8913 else /* op1 == IOR */
8914 /* (a | b) ^ b == a & ~b */
8915 op0 = AND, *pconst0 = ~const0;
8920 /* (a | b) & b == b */
8922 else /* op1 == XOR */
8923 /* (a ^ b) & b) == (~a) & b */
8930 /* Check for NO-OP cases. */
8931 const0 &= GET_MODE_MASK (mode);
8933 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8935 else if (const0 == 0 && op0 == AND)
8937 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8941 /* ??? Slightly redundant with the above mask, but not entirely.
8942 Moving this above means we'd have to sign-extend the mode mask
8943 for the final test. */
8944 const0 = trunc_int_for_mode (const0, mode);
8952 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8953 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8954 that we started with.
8956 The shift is normally computed in the widest mode we find in VAROP, as
8957 long as it isn't a different number of words than RESULT_MODE. Exceptions
8958 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8961 simplify_shift_const (x, code, result_mode, varop, orig_count)
8964 enum machine_mode result_mode;
8968 enum rtx_code orig_code = code;
8971 enum machine_mode mode = result_mode;
8972 enum machine_mode shift_mode, tmode;
8973 unsigned int mode_words
8974 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8975 /* We form (outer_op (code varop count) (outer_const)). */
8976 enum rtx_code outer_op = NIL;
8977 HOST_WIDE_INT outer_const = 0;
8979 int complement_p = 0;
8982 /* Make sure and truncate the "natural" shift on the way in. We don't
8983 want to do this inside the loop as it makes it more difficult to
8985 #ifdef SHIFT_COUNT_TRUNCATED
8986 if (SHIFT_COUNT_TRUNCATED)
8987 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8990 /* If we were given an invalid count, don't do anything except exactly
8991 what was requested. */
8993 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8998 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9003 /* Unless one of the branches of the `if' in this loop does a `continue',
9004 we will `break' the loop after the `if'. */
9008 /* If we have an operand of (clobber (const_int 0)), just return that
9010 if (GET_CODE (varop) == CLOBBER)
9013 /* If we discovered we had to complement VAROP, leave. Making a NOT
9014 here would cause an infinite loop. */
9018 /* Convert ROTATERT to ROTATE. */
9019 if (code == ROTATERT)
9020 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
9022 /* We need to determine what mode we will do the shift in. If the
9023 shift is a right shift or a ROTATE, we must always do it in the mode
9024 it was originally done in. Otherwise, we can do it in MODE, the
9025 widest mode encountered. */
9027 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9028 ? result_mode : mode);
9030 /* Handle cases where the count is greater than the size of the mode
9031 minus 1. For ASHIFT, use the size minus one as the count (this can
9032 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9033 take the count modulo the size. For other shifts, the result is
9036 Since these shifts are being produced by the compiler by combining
9037 multiple operations, each of which are defined, we know what the
9038 result is supposed to be. */
9040 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9042 if (code == ASHIFTRT)
9043 count = GET_MODE_BITSIZE (shift_mode) - 1;
9044 else if (code == ROTATE || code == ROTATERT)
9045 count %= GET_MODE_BITSIZE (shift_mode);
9048 /* We can't simply return zero because there may be an
9056 /* An arithmetic right shift of a quantity known to be -1 or 0
9058 if (code == ASHIFTRT
9059 && (num_sign_bit_copies (varop, shift_mode)
9060 == GET_MODE_BITSIZE (shift_mode)))
9066 /* If we are doing an arithmetic right shift and discarding all but
9067 the sign bit copies, this is equivalent to doing a shift by the
9068 bitsize minus one. Convert it into that shift because it will often
9069 allow other simplifications. */
9071 if (code == ASHIFTRT
9072 && (count + num_sign_bit_copies (varop, shift_mode)
9073 >= GET_MODE_BITSIZE (shift_mode)))
9074 count = GET_MODE_BITSIZE (shift_mode) - 1;
9076 /* We simplify the tests below and elsewhere by converting
9077 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9078 `make_compound_operation' will convert it to an ASHIFTRT for
9079 those machines (such as VAX) that don't have an LSHIFTRT. */
9080 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9082 && ((nonzero_bits (varop, shift_mode)
9083 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9087 switch (GET_CODE (varop))
9093 new = expand_compound_operation (varop);
9102 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9103 minus the width of a smaller mode, we can do this with a
9104 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9105 if ((code == ASHIFTRT || code == LSHIFTRT)
9106 && ! mode_dependent_address_p (XEXP (varop, 0))
9107 && ! MEM_VOLATILE_P (varop)
9108 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9109 MODE_INT, 1)) != BLKmode)
9111 new = adjust_address_nv (varop, tmode,
9112 BYTES_BIG_ENDIAN ? 0
9113 : count / BITS_PER_UNIT);
9115 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9116 : ZERO_EXTEND, mode, new);
9123 /* Similar to the case above, except that we can only do this if
9124 the resulting mode is the same as that of the underlying
9125 MEM and adjust the address depending on the *bits* endianness
9126 because of the way that bit-field extract insns are defined. */
9127 if ((code == ASHIFTRT || code == LSHIFTRT)
9128 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9129 MODE_INT, 1)) != BLKmode
9130 && tmode == GET_MODE (XEXP (varop, 0)))
9132 if (BITS_BIG_ENDIAN)
9133 new = XEXP (varop, 0);
9136 new = copy_rtx (XEXP (varop, 0));
9137 SUBST (XEXP (new, 0),
9138 plus_constant (XEXP (new, 0),
9139 count / BITS_PER_UNIT));
9142 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9143 : ZERO_EXTEND, mode, new);
9150 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9151 the same number of words as what we've seen so far. Then store
9152 the widest mode in MODE. */
9153 if (subreg_lowpart_p (varop)
9154 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9155 > GET_MODE_SIZE (GET_MODE (varop)))
9156 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9157 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9160 varop = SUBREG_REG (varop);
9161 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9162 mode = GET_MODE (varop);
9168 /* Some machines use MULT instead of ASHIFT because MULT
9169 is cheaper. But it is still better on those machines to
9170 merge two shifts into one. */
9171 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9172 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9175 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9176 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9182 /* Similar, for when divides are cheaper. */
9183 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9184 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9187 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9188 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9194 /* If we are extracting just the sign bit of an arithmetic
9195 right shift, that shift is not needed. However, the sign
9196 bit of a wider mode may be different from what would be
9197 interpreted as the sign bit in a narrower mode, so, if
9198 the result is narrower, don't discard the shift. */
9199 if (code == LSHIFTRT
9200 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9201 && (GET_MODE_BITSIZE (result_mode)
9202 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9204 varop = XEXP (varop, 0);
9208 /* ... fall through ... */
9213 /* Here we have two nested shifts. The result is usually the
9214 AND of a new shift with a mask. We compute the result below. */
9215 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9216 && INTVAL (XEXP (varop, 1)) >= 0
9217 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9218 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9219 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9221 enum rtx_code first_code = GET_CODE (varop);
9222 unsigned int first_count = INTVAL (XEXP (varop, 1));
9223 unsigned HOST_WIDE_INT mask;
9226 /* We have one common special case. We can't do any merging if
9227 the inner code is an ASHIFTRT of a smaller mode. However, if
9228 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9229 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9230 we can convert it to
9231 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9232 This simplifies certain SIGN_EXTEND operations. */
9233 if (code == ASHIFT && first_code == ASHIFTRT
9234 && count == (unsigned int)
9235 (GET_MODE_BITSIZE (result_mode)
9236 - GET_MODE_BITSIZE (GET_MODE (varop))))
9238 /* C3 has the low-order C1 bits zero. */
9240 mask = (GET_MODE_MASK (mode)
9241 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9243 varop = simplify_and_const_int (NULL_RTX, result_mode,
9244 XEXP (varop, 0), mask);
9245 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9247 count = first_count;
9252 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9253 than C1 high-order bits equal to the sign bit, we can convert
9254 this to either an ASHIFT or an ASHIFTRT depending on the
9257 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9259 if (code == ASHIFTRT && first_code == ASHIFT
9260 && GET_MODE (varop) == shift_mode
9261 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9264 varop = XEXP (varop, 0);
9266 signed_count = count - first_count;
9267 if (signed_count < 0)
9268 count = -signed_count, code = ASHIFT;
9270 count = signed_count;
9275 /* There are some cases we can't do. If CODE is ASHIFTRT,
9276 we can only do this if FIRST_CODE is also ASHIFTRT.
9278 We can't do the case when CODE is ROTATE and FIRST_CODE is
9281 If the mode of this shift is not the mode of the outer shift,
9282 we can't do this if either shift is a right shift or ROTATE.
9284 Finally, we can't do any of these if the mode is too wide
9285 unless the codes are the same.
9287 Handle the case where the shift codes are the same
9290 if (code == first_code)
9292 if (GET_MODE (varop) != result_mode
9293 && (code == ASHIFTRT || code == LSHIFTRT
9297 count += first_count;
9298 varop = XEXP (varop, 0);
9302 if (code == ASHIFTRT
9303 || (code == ROTATE && first_code == ASHIFTRT)
9304 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9305 || (GET_MODE (varop) != result_mode
9306 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9307 || first_code == ROTATE
9308 || code == ROTATE)))
9311 /* To compute the mask to apply after the shift, shift the
9312 nonzero bits of the inner shift the same way the
9313 outer shift will. */
9315 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9318 = simplify_binary_operation (code, result_mode, mask_rtx,
9321 /* Give up if we can't compute an outer operation to use. */
9323 || GET_CODE (mask_rtx) != CONST_INT
9324 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9326 result_mode, &complement_p))
9329 /* If the shifts are in the same direction, we add the
9330 counts. Otherwise, we subtract them. */
9331 signed_count = count;
9332 if ((code == ASHIFTRT || code == LSHIFTRT)
9333 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9334 signed_count += first_count;
9336 signed_count -= first_count;
9338 /* If COUNT is positive, the new shift is usually CODE,
9339 except for the two exceptions below, in which case it is
9340 FIRST_CODE. If the count is negative, FIRST_CODE should
9342 if (signed_count > 0
9343 && ((first_code == ROTATE && code == ASHIFT)
9344 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9345 code = first_code, count = signed_count;
9346 else if (signed_count < 0)
9347 code = first_code, count = -signed_count;
9349 count = signed_count;
9351 varop = XEXP (varop, 0);
9355 /* If we have (A << B << C) for any shift, we can convert this to
9356 (A << C << B). This wins if A is a constant. Only try this if
9357 B is not a constant. */
9359 else if (GET_CODE (varop) == code
9360 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9362 = simplify_binary_operation (code, mode,
9366 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9373 /* Make this fit the case below. */
9374 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9375 GEN_INT (GET_MODE_MASK (mode)));
9381 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9382 with C the size of VAROP - 1 and the shift is logical if
9383 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9384 we have an (le X 0) operation. If we have an arithmetic shift
9385 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9386 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9388 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9389 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9390 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9391 && (code == LSHIFTRT || code == ASHIFTRT)
9392 && count == (unsigned int)
9393 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9394 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9397 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9400 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9401 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9406 /* If we have (shift (logical)), move the logical to the outside
9407 to allow it to possibly combine with another logical and the
9408 shift to combine with another shift. This also canonicalizes to
9409 what a ZERO_EXTRACT looks like. Also, some machines have
9410 (and (shift)) insns. */
9412 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9413 && (new = simplify_binary_operation (code, result_mode,
9415 GEN_INT (count))) != 0
9416 && GET_CODE (new) == CONST_INT
9417 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9418 INTVAL (new), result_mode, &complement_p))
9420 varop = XEXP (varop, 0);
9424 /* If we can't do that, try to simplify the shift in each arm of the
9425 logical expression, make a new logical expression, and apply
9426 the inverse distributive law. */
9428 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9429 XEXP (varop, 0), count);
9430 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9431 XEXP (varop, 1), count);
9433 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9434 varop = apply_distributive_law (varop);
9441 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9442 says that the sign bit can be tested, FOO has mode MODE, C is
9443 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9444 that may be nonzero. */
9445 if (code == LSHIFTRT
9446 && XEXP (varop, 1) == const0_rtx
9447 && GET_MODE (XEXP (varop, 0)) == result_mode
9448 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9449 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9450 && ((STORE_FLAG_VALUE
9451 & ((HOST_WIDE_INT) 1
9452 < (GET_MODE_BITSIZE (result_mode) - 1))))
9453 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9454 && merge_outer_ops (&outer_op, &outer_const, XOR,
9455 (HOST_WIDE_INT) 1, result_mode,
9458 varop = XEXP (varop, 0);
9465 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9466 than the number of bits in the mode is equivalent to A. */
9467 if (code == LSHIFTRT
9468 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9469 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9471 varop = XEXP (varop, 0);
9476 /* NEG commutes with ASHIFT since it is multiplication. Move the
9477 NEG outside to allow shifts to combine. */
9479 && merge_outer_ops (&outer_op, &outer_const, NEG,
9480 (HOST_WIDE_INT) 0, result_mode,
9483 varop = XEXP (varop, 0);
9489 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9490 is one less than the number of bits in the mode is
9491 equivalent to (xor A 1). */
9492 if (code == LSHIFTRT
9493 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9494 && XEXP (varop, 1) == constm1_rtx
9495 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9496 && merge_outer_ops (&outer_op, &outer_const, XOR,
9497 (HOST_WIDE_INT) 1, result_mode,
9501 varop = XEXP (varop, 0);
9505 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9506 that might be nonzero in BAR are those being shifted out and those
9507 bits are known zero in FOO, we can replace the PLUS with FOO.
9508 Similarly in the other operand order. This code occurs when
9509 we are computing the size of a variable-size array. */
9511 if ((code == ASHIFTRT || code == LSHIFTRT)
9512 && count < HOST_BITS_PER_WIDE_INT
9513 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9514 && (nonzero_bits (XEXP (varop, 1), result_mode)
9515 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9517 varop = XEXP (varop, 0);
9520 else if ((code == ASHIFTRT || code == LSHIFTRT)
9521 && count < HOST_BITS_PER_WIDE_INT
9522 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9523 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9525 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9526 & nonzero_bits (XEXP (varop, 1),
9529 varop = XEXP (varop, 1);
9533 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9535 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9536 && (new = simplify_binary_operation (ASHIFT, result_mode,
9538 GEN_INT (count))) != 0
9539 && GET_CODE (new) == CONST_INT
9540 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9541 INTVAL (new), result_mode, &complement_p))
9543 varop = XEXP (varop, 0);
9549 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9550 with C the size of VAROP - 1 and the shift is logical if
9551 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9552 we have a (gt X 0) operation. If the shift is arithmetic with
9553 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9554 we have a (neg (gt X 0)) operation. */
9556 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9557 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9558 && count == (unsigned int)
9559 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9560 && (code == LSHIFTRT || code == ASHIFTRT)
9561 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9562 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9564 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9567 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9570 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9571 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9578 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9579 if the truncate does not affect the value. */
9580 if (code == LSHIFTRT
9581 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9582 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9583 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9584 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9585 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9587 rtx varop_inner = XEXP (varop, 0);
9590 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9591 XEXP (varop_inner, 0),
9593 (count + INTVAL (XEXP (varop_inner, 1))));
9594 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9607 /* We need to determine what mode to do the shift in. If the shift is
9608 a right shift or ROTATE, we must always do it in the mode it was
9609 originally done in. Otherwise, we can do it in MODE, the widest mode
9610 encountered. The code we care about is that of the shift that will
9611 actually be done, not the shift that was originally requested. */
9613 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9614 ? result_mode : mode);
9616 /* We have now finished analyzing the shift. The result should be
9617 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9618 OUTER_OP is non-NIL, it is an operation that needs to be applied
9619 to the result of the shift. OUTER_CONST is the relevant constant,
9620 but we must turn off all bits turned off in the shift.
9622 If we were passed a value for X, see if we can use any pieces of
9623 it. If not, make new rtx. */
9625 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9626 && GET_CODE (XEXP (x, 1)) == CONST_INT
9627 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9628 const_rtx = XEXP (x, 1);
9630 const_rtx = GEN_INT (count);
9632 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9633 && GET_MODE (XEXP (x, 0)) == shift_mode
9634 && SUBREG_REG (XEXP (x, 0)) == varop)
9635 varop = XEXP (x, 0);
9636 else if (GET_MODE (varop) != shift_mode)
9637 varop = gen_lowpart_for_combine (shift_mode, varop);
9639 /* If we can't make the SUBREG, try to return what we were given. */
9640 if (GET_CODE (varop) == CLOBBER)
9641 return x ? x : varop;
9643 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9647 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9649 /* If we have an outer operation and we just made a shift, it is
9650 possible that we could have simplified the shift were it not
9651 for the outer operation. So try to do the simplification
9654 if (outer_op != NIL && GET_CODE (x) == code
9655 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9656 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9657 INTVAL (XEXP (x, 1)));
9659 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9660 turn off all the bits that the shift would have turned off. */
9661 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9662 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9663 GET_MODE_MASK (result_mode) >> orig_count);
9665 /* Do the remainder of the processing in RESULT_MODE. */
9666 x = gen_lowpart_for_combine (result_mode, x);
9668 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9671 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9673 if (outer_op != NIL)
9675 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9676 outer_const = trunc_int_for_mode (outer_const, result_mode);
9678 if (outer_op == AND)
9679 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9680 else if (outer_op == SET)
9681 /* This means that we have determined that the result is
9682 equivalent to a constant. This should be rare. */
9683 x = GEN_INT (outer_const);
9684 else if (GET_RTX_CLASS (outer_op) == '1')
9685 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9687 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9693 /* Like recog, but we receive the address of a pointer to a new pattern.
9694 We try to match the rtx that the pointer points to.
9695 If that fails, we may try to modify or replace the pattern,
9696 storing the replacement into the same pointer object.
9698 Modifications include deletion or addition of CLOBBERs.
9700 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9701 the CLOBBERs are placed.
9703 The value is the final insn code from the pattern ultimately matched,
9707 recog_for_combine (pnewpat, insn, pnotes)
9713 int insn_code_number;
9714 int num_clobbers_to_add = 0;
9719 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9720 we use to indicate that something didn't match. If we find such a
9721 thing, force rejection. */
9722 if (GET_CODE (pat) == PARALLEL)
9723 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9724 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9725 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9728 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9729 instruction for pattern recognition. */
9730 dummy_insn = shallow_copy_rtx (insn);
9731 PATTERN (dummy_insn) = pat;
9732 REG_NOTES (dummy_insn) = 0;
9734 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9736 /* If it isn't, there is the possibility that we previously had an insn
9737 that clobbered some register as a side effect, but the combined
9738 insn doesn't need to do that. So try once more without the clobbers
9739 unless this represents an ASM insn. */
9741 if (insn_code_number < 0 && ! check_asm_operands (pat)
9742 && GET_CODE (pat) == PARALLEL)
9746 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9747 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9750 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9754 SUBST_INT (XVECLEN (pat, 0), pos);
9757 pat = XVECEXP (pat, 0, 0);
9759 PATTERN (dummy_insn) = pat;
9760 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9763 /* Recognize all noop sets, these will be killed by followup pass. */
9764 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9765 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9767 /* If we had any clobbers to add, make a new pattern than contains
9768 them. Then check to make sure that all of them are dead. */
9769 if (num_clobbers_to_add)
9771 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9772 rtvec_alloc (GET_CODE (pat) == PARALLEL
9774 + num_clobbers_to_add)
9775 : num_clobbers_to_add + 1));
9777 if (GET_CODE (pat) == PARALLEL)
9778 for (i = 0; i < XVECLEN (pat, 0); i++)
9779 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9781 XVECEXP (newpat, 0, 0) = pat;
9783 add_clobbers (newpat, insn_code_number);
9785 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9786 i < XVECLEN (newpat, 0); i++)
9788 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9789 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9791 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9792 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9800 return insn_code_number;
9803 /* Like gen_lowpart but for use by combine. In combine it is not possible
9804 to create any new pseudoregs. However, it is safe to create
9805 invalid memory addresses, because combine will try to recognize
9806 them and all they will do is make the combine attempt fail.
9808 If for some reason this cannot do its job, an rtx
9809 (clobber (const_int 0)) is returned.
9810 An insn containing that will not be recognized. */
9815 gen_lowpart_for_combine (mode, x)
9816 enum machine_mode mode;
9821 if (GET_MODE (x) == mode)
9824 /* We can only support MODE being wider than a word if X is a
9825 constant integer or has a mode the same size. */
9827 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9828 && ! ((GET_MODE (x) == VOIDmode
9829 && (GET_CODE (x) == CONST_INT
9830 || GET_CODE (x) == CONST_DOUBLE))
9831 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9832 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9834 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9835 won't know what to do. So we will strip off the SUBREG here and
9836 process normally. */
9837 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9840 if (GET_MODE (x) == mode)
9844 result = gen_lowpart_common (mode, x);
9845 #ifdef CLASS_CANNOT_CHANGE_MODE
9847 && GET_CODE (result) == SUBREG
9848 && GET_CODE (SUBREG_REG (result)) == REG
9849 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9850 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9851 GET_MODE (SUBREG_REG (result))))
9852 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9858 if (GET_CODE (x) == MEM)
9862 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9864 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9865 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9867 /* If we want to refer to something bigger than the original memref,
9868 generate a perverse subreg instead. That will force a reload
9869 of the original memref X. */
9870 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9871 return gen_rtx_SUBREG (mode, x, 0);
9873 if (WORDS_BIG_ENDIAN)
9874 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9875 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9877 if (BYTES_BIG_ENDIAN)
9879 /* Adjust the address so that the address-after-the-data is
9881 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9882 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9885 return adjust_address_nv (x, mode, offset);
9888 /* If X is a comparison operator, rewrite it in a new mode. This
9889 probably won't match, but may allow further simplifications. */
9890 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9891 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9893 /* If we couldn't simplify X any other way, just enclose it in a
9894 SUBREG. Normally, this SUBREG won't match, but some patterns may
9895 include an explicit SUBREG or we may simplify it further in combine. */
9900 enum machine_mode sub_mode = GET_MODE (x);
9902 offset = subreg_lowpart_offset (mode, sub_mode);
9903 if (sub_mode == VOIDmode)
9905 sub_mode = int_mode_for_mode (mode);
9906 x = gen_lowpart_common (sub_mode, x);
9908 res = simplify_gen_subreg (mode, x, sub_mode, offset);
9911 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9915 /* These routines make binary and unary operations by first seeing if they
9916 fold; if not, a new expression is allocated. */
9919 gen_binary (code, mode, op0, op1)
9921 enum machine_mode mode;
9927 if (GET_RTX_CLASS (code) == 'c'
9928 && swap_commutative_operands_p (op0, op1))
9929 tem = op0, op0 = op1, op1 = tem;
9931 if (GET_RTX_CLASS (code) == '<')
9933 enum machine_mode op_mode = GET_MODE (op0);
9935 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9936 just (REL_OP X Y). */
9937 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9939 op1 = XEXP (op0, 1);
9940 op0 = XEXP (op0, 0);
9941 op_mode = GET_MODE (op0);
9944 if (op_mode == VOIDmode)
9945 op_mode = GET_MODE (op1);
9946 result = simplify_relational_operation (code, op_mode, op0, op1);
9949 result = simplify_binary_operation (code, mode, op0, op1);
9954 /* Put complex operands first and constants second. */
9955 if (GET_RTX_CLASS (code) == 'c'
9956 && swap_commutative_operands_p (op0, op1))
9957 return gen_rtx_fmt_ee (code, mode, op1, op0);
9959 /* If we are turning off bits already known off in OP0, we need not do
9961 else if (code == AND && GET_CODE (op1) == CONST_INT
9962 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9963 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9966 return gen_rtx_fmt_ee (code, mode, op0, op1);
9969 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9970 comparison code that will be tested.
9972 The result is a possibly different comparison code to use. *POP0 and
9973 *POP1 may be updated.
9975 It is possible that we might detect that a comparison is either always
9976 true or always false. However, we do not perform general constant
9977 folding in combine, so this knowledge isn't useful. Such tautologies
9978 should have been detected earlier. Hence we ignore all such cases. */
9980 static enum rtx_code
9981 simplify_comparison (code, pop0, pop1)
9990 enum machine_mode mode, tmode;
9992 /* Try a few ways of applying the same transformation to both operands. */
9995 #ifndef WORD_REGISTER_OPERATIONS
9996 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9997 so check specially. */
9998 if (code != GTU && code != GEU && code != LTU && code != LEU
9999 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10000 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10001 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10002 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10003 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10004 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10005 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10006 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10007 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10008 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10009 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10010 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10011 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10012 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10013 && (INTVAL (XEXP (op0, 1))
10014 == (GET_MODE_BITSIZE (GET_MODE (op0))
10015 - (GET_MODE_BITSIZE
10016 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10018 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10019 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10023 /* If both operands are the same constant shift, see if we can ignore the
10024 shift. We can if the shift is a rotate or if the bits shifted out of
10025 this shift are known to be zero for both inputs and if the type of
10026 comparison is compatible with the shift. */
10027 if (GET_CODE (op0) == GET_CODE (op1)
10028 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10029 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10030 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10031 && (code != GT && code != LT && code != GE && code != LE))
10032 || (GET_CODE (op0) == ASHIFTRT
10033 && (code != GTU && code != LTU
10034 && code != GEU && code != LEU)))
10035 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10036 && INTVAL (XEXP (op0, 1)) >= 0
10037 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10038 && XEXP (op0, 1) == XEXP (op1, 1))
10040 enum machine_mode mode = GET_MODE (op0);
10041 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10042 int shift_count = INTVAL (XEXP (op0, 1));
10044 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10045 mask &= (mask >> shift_count) << shift_count;
10046 else if (GET_CODE (op0) == ASHIFT)
10047 mask = (mask & (mask << shift_count)) >> shift_count;
10049 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10050 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10051 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10056 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10057 SUBREGs are of the same mode, and, in both cases, the AND would
10058 be redundant if the comparison was done in the narrower mode,
10059 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10060 and the operand's possibly nonzero bits are 0xffffff01; in that case
10061 if we only care about QImode, we don't need the AND). This case
10062 occurs if the output mode of an scc insn is not SImode and
10063 STORE_FLAG_VALUE == 1 (e.g., the 386).
10065 Similarly, check for a case where the AND's are ZERO_EXTEND
10066 operations from some narrower mode even though a SUBREG is not
10069 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10070 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10071 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10073 rtx inner_op0 = XEXP (op0, 0);
10074 rtx inner_op1 = XEXP (op1, 0);
10075 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10076 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10079 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10080 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10081 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10082 && (GET_MODE (SUBREG_REG (inner_op0))
10083 == GET_MODE (SUBREG_REG (inner_op1)))
10084 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10085 <= HOST_BITS_PER_WIDE_INT)
10086 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10087 GET_MODE (SUBREG_REG (inner_op0)))))
10088 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10089 GET_MODE (SUBREG_REG (inner_op1))))))
10091 op0 = SUBREG_REG (inner_op0);
10092 op1 = SUBREG_REG (inner_op1);
10094 /* The resulting comparison is always unsigned since we masked
10095 off the original sign bit. */
10096 code = unsigned_condition (code);
10102 for (tmode = GET_CLASS_NARROWEST_MODE
10103 (GET_MODE_CLASS (GET_MODE (op0)));
10104 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10105 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10107 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10108 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10109 code = unsigned_condition (code);
10118 /* If both operands are NOT, we can strip off the outer operation
10119 and adjust the comparison code for swapped operands; similarly for
10120 NEG, except that this must be an equality comparison. */
10121 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10122 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10123 && (code == EQ || code == NE)))
10124 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10130 /* If the first operand is a constant, swap the operands and adjust the
10131 comparison code appropriately, but don't do this if the second operand
10132 is already a constant integer. */
10133 if (swap_commutative_operands_p (op0, op1))
10135 tem = op0, op0 = op1, op1 = tem;
10136 code = swap_condition (code);
10139 /* We now enter a loop during which we will try to simplify the comparison.
10140 For the most part, we only are concerned with comparisons with zero,
10141 but some things may really be comparisons with zero but not start
10142 out looking that way. */
10144 while (GET_CODE (op1) == CONST_INT)
10146 enum machine_mode mode = GET_MODE (op0);
10147 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10148 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10149 int equality_comparison_p;
10150 int sign_bit_comparison_p;
10151 int unsigned_comparison_p;
10152 HOST_WIDE_INT const_op;
10154 /* We only want to handle integral modes. This catches VOIDmode,
10155 CCmode, and the floating-point modes. An exception is that we
10156 can handle VOIDmode if OP0 is a COMPARE or a comparison
10159 if (GET_MODE_CLASS (mode) != MODE_INT
10160 && ! (mode == VOIDmode
10161 && (GET_CODE (op0) == COMPARE
10162 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10165 /* Get the constant we are comparing against and turn off all bits
10166 not on in our mode. */
10167 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10168 op1 = GEN_INT (const_op);
10170 /* If we are comparing against a constant power of two and the value
10171 being compared can only have that single bit nonzero (e.g., it was
10172 `and'ed with that bit), we can replace this with a comparison
10175 && (code == EQ || code == NE || code == GE || code == GEU
10176 || code == LT || code == LTU)
10177 && mode_width <= HOST_BITS_PER_WIDE_INT
10178 && exact_log2 (const_op) >= 0
10179 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10181 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10182 op1 = const0_rtx, const_op = 0;
10185 /* Similarly, if we are comparing a value known to be either -1 or
10186 0 with -1, change it to the opposite comparison against zero. */
10189 && (code == EQ || code == NE || code == GT || code == LE
10190 || code == GEU || code == LTU)
10191 && num_sign_bit_copies (op0, mode) == mode_width)
10193 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10194 op1 = const0_rtx, const_op = 0;
10197 /* Do some canonicalizations based on the comparison code. We prefer
10198 comparisons against zero and then prefer equality comparisons.
10199 If we can reduce the size of a constant, we will do that too. */
10204 /* < C is equivalent to <= (C - 1) */
10208 op1 = GEN_INT (const_op);
10210 /* ... fall through to LE case below. */
10216 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10220 op1 = GEN_INT (const_op);
10224 /* If we are doing a <= 0 comparison on a value known to have
10225 a zero sign bit, we can replace this with == 0. */
10226 else if (const_op == 0
10227 && mode_width <= HOST_BITS_PER_WIDE_INT
10228 && (nonzero_bits (op0, mode)
10229 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10234 /* >= C is equivalent to > (C - 1). */
10238 op1 = GEN_INT (const_op);
10240 /* ... fall through to GT below. */
10246 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10250 op1 = GEN_INT (const_op);
10254 /* If we are doing a > 0 comparison on a value known to have
10255 a zero sign bit, we can replace this with != 0. */
10256 else if (const_op == 0
10257 && mode_width <= HOST_BITS_PER_WIDE_INT
10258 && (nonzero_bits (op0, mode)
10259 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10264 /* < C is equivalent to <= (C - 1). */
10268 op1 = GEN_INT (const_op);
10270 /* ... fall through ... */
10273 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10274 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10275 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10277 const_op = 0, op1 = const0_rtx;
10285 /* unsigned <= 0 is equivalent to == 0 */
10289 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10290 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10291 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10293 const_op = 0, op1 = const0_rtx;
10299 /* >= C is equivalent to < (C - 1). */
10303 op1 = GEN_INT (const_op);
10305 /* ... fall through ... */
10308 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10309 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10310 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10312 const_op = 0, op1 = const0_rtx;
10320 /* unsigned > 0 is equivalent to != 0 */
10324 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10325 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10326 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10328 const_op = 0, op1 = const0_rtx;
10337 /* Compute some predicates to simplify code below. */
10339 equality_comparison_p = (code == EQ || code == NE);
10340 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10341 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10344 /* If this is a sign bit comparison and we can do arithmetic in
10345 MODE, say that we will only be needing the sign bit of OP0. */
10346 if (sign_bit_comparison_p
10347 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10348 op0 = force_to_mode (op0, mode,
10350 << (GET_MODE_BITSIZE (mode) - 1)),
10353 /* Now try cases based on the opcode of OP0. If none of the cases
10354 does a "continue", we exit this loop immediately after the
10357 switch (GET_CODE (op0))
10360 /* If we are extracting a single bit from a variable position in
10361 a constant that has only a single bit set and are comparing it
10362 with zero, we can convert this into an equality comparison
10363 between the position and the location of the single bit. */
10365 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10366 && XEXP (op0, 1) == const1_rtx
10367 && equality_comparison_p && const_op == 0
10368 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10370 if (BITS_BIG_ENDIAN)
10372 enum machine_mode new_mode
10373 = mode_for_extraction (EP_extzv, 1);
10374 if (new_mode == MAX_MACHINE_MODE)
10375 i = BITS_PER_WORD - 1 - i;
10379 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10383 op0 = XEXP (op0, 2);
10387 /* Result is nonzero iff shift count is equal to I. */
10388 code = reverse_condition (code);
10392 /* ... fall through ... */
10395 tem = expand_compound_operation (op0);
10404 /* If testing for equality, we can take the NOT of the constant. */
10405 if (equality_comparison_p
10406 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10408 op0 = XEXP (op0, 0);
10413 /* If just looking at the sign bit, reverse the sense of the
10415 if (sign_bit_comparison_p)
10417 op0 = XEXP (op0, 0);
10418 code = (code == GE ? LT : GE);
10424 /* If testing for equality, we can take the NEG of the constant. */
10425 if (equality_comparison_p
10426 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10428 op0 = XEXP (op0, 0);
10433 /* The remaining cases only apply to comparisons with zero. */
10437 /* When X is ABS or is known positive,
10438 (neg X) is < 0 if and only if X != 0. */
10440 if (sign_bit_comparison_p
10441 && (GET_CODE (XEXP (op0, 0)) == ABS
10442 || (mode_width <= HOST_BITS_PER_WIDE_INT
10443 && (nonzero_bits (XEXP (op0, 0), mode)
10444 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10446 op0 = XEXP (op0, 0);
10447 code = (code == LT ? NE : EQ);
10451 /* If we have NEG of something whose two high-order bits are the
10452 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10453 if (num_sign_bit_copies (op0, mode) >= 2)
10455 op0 = XEXP (op0, 0);
10456 code = swap_condition (code);
10462 /* If we are testing equality and our count is a constant, we
10463 can perform the inverse operation on our RHS. */
10464 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10465 && (tem = simplify_binary_operation (ROTATERT, mode,
10466 op1, XEXP (op0, 1))) != 0)
10468 op0 = XEXP (op0, 0);
10473 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10474 a particular bit. Convert it to an AND of a constant of that
10475 bit. This will be converted into a ZERO_EXTRACT. */
10476 if (const_op == 0 && sign_bit_comparison_p
10477 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10478 && mode_width <= HOST_BITS_PER_WIDE_INT)
10480 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10483 - INTVAL (XEXP (op0, 1)))));
10484 code = (code == LT ? NE : EQ);
10488 /* Fall through. */
10491 /* ABS is ignorable inside an equality comparison with zero. */
10492 if (const_op == 0 && equality_comparison_p)
10494 op0 = XEXP (op0, 0);
10500 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10501 to (compare FOO CONST) if CONST fits in FOO's mode and we
10502 are either testing inequality or have an unsigned comparison
10503 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10504 if (! unsigned_comparison_p
10505 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10506 <= HOST_BITS_PER_WIDE_INT)
10507 && ((unsigned HOST_WIDE_INT) const_op
10508 < (((unsigned HOST_WIDE_INT) 1
10509 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10511 op0 = XEXP (op0, 0);
10517 /* Check for the case where we are comparing A - C1 with C2,
10518 both constants are smaller than 1/2 the maximum positive
10519 value in MODE, and the comparison is equality or unsigned.
10520 In that case, if A is either zero-extended to MODE or has
10521 sufficient sign bits so that the high-order bit in MODE
10522 is a copy of the sign in the inner mode, we can prove that it is
10523 safe to do the operation in the wider mode. This simplifies
10524 many range checks. */
10526 if (mode_width <= HOST_BITS_PER_WIDE_INT
10527 && subreg_lowpart_p (op0)
10528 && GET_CODE (SUBREG_REG (op0)) == PLUS
10529 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10530 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10531 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10532 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10533 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10534 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10535 GET_MODE (SUBREG_REG (op0)))
10536 & ~GET_MODE_MASK (mode))
10537 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10538 GET_MODE (SUBREG_REG (op0)))
10540 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10541 - GET_MODE_BITSIZE (mode)))))
10543 op0 = SUBREG_REG (op0);
10547 /* If the inner mode is narrower and we are extracting the low part,
10548 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10549 if (subreg_lowpart_p (op0)
10550 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10551 /* Fall through */ ;
10555 /* ... fall through ... */
10558 if ((unsigned_comparison_p || equality_comparison_p)
10559 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10560 <= HOST_BITS_PER_WIDE_INT)
10561 && ((unsigned HOST_WIDE_INT) const_op
10562 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10564 op0 = XEXP (op0, 0);
10570 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10571 this for equality comparisons due to pathological cases involving
10573 if (equality_comparison_p
10574 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10575 op1, XEXP (op0, 1))))
10577 op0 = XEXP (op0, 0);
10582 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10583 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10584 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10586 op0 = XEXP (XEXP (op0, 0), 0);
10587 code = (code == LT ? EQ : NE);
10593 /* We used to optimize signed comparisons against zero, but that
10594 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10595 arrive here as equality comparisons, or (GEU, LTU) are
10596 optimized away. No need to special-case them. */
10598 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10599 (eq B (minus A C)), whichever simplifies. We can only do
10600 this for equality comparisons due to pathological cases involving
10602 if (equality_comparison_p
10603 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10604 XEXP (op0, 1), op1)))
10606 op0 = XEXP (op0, 0);
10611 if (equality_comparison_p
10612 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10613 XEXP (op0, 0), op1)))
10615 op0 = XEXP (op0, 1);
10620 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10621 of bits in X minus 1, is one iff X > 0. */
10622 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10623 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10624 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10626 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10628 op0 = XEXP (op0, 1);
10629 code = (code == GE ? LE : GT);
10635 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10636 if C is zero or B is a constant. */
10637 if (equality_comparison_p
10638 && 0 != (tem = simplify_binary_operation (XOR, mode,
10639 XEXP (op0, 1), op1)))
10641 op0 = XEXP (op0, 0);
10648 case UNEQ: case LTGT:
10649 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10650 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10651 case UNORDERED: case ORDERED:
10652 /* We can't do anything if OP0 is a condition code value, rather
10653 than an actual data value. */
10656 || XEXP (op0, 0) == cc0_rtx
10658 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10661 /* Get the two operands being compared. */
10662 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10663 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10665 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10667 /* Check for the cases where we simply want the result of the
10668 earlier test or the opposite of that result. */
10669 if (code == NE || code == EQ
10670 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10671 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10672 && (STORE_FLAG_VALUE
10673 & (((HOST_WIDE_INT) 1
10674 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10675 && (code == LT || code == GE)))
10677 enum rtx_code new_code;
10678 if (code == LT || code == NE)
10679 new_code = GET_CODE (op0);
10681 new_code = combine_reversed_comparison_code (op0);
10683 if (new_code != UNKNOWN)
10694 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10696 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10697 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10698 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10700 op0 = XEXP (op0, 1);
10701 code = (code == GE ? GT : LE);
10707 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10708 will be converted to a ZERO_EXTRACT later. */
10709 if (const_op == 0 && equality_comparison_p
10710 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10711 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10713 op0 = simplify_and_const_int
10714 (op0, mode, gen_rtx_LSHIFTRT (mode,
10716 XEXP (XEXP (op0, 0), 1)),
10717 (HOST_WIDE_INT) 1);
10721 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10722 zero and X is a comparison and C1 and C2 describe only bits set
10723 in STORE_FLAG_VALUE, we can compare with X. */
10724 if (const_op == 0 && equality_comparison_p
10725 && mode_width <= HOST_BITS_PER_WIDE_INT
10726 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10727 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10728 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10729 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10730 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10732 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10733 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10734 if ((~STORE_FLAG_VALUE & mask) == 0
10735 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10736 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10737 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10739 op0 = XEXP (XEXP (op0, 0), 0);
10744 /* If we are doing an equality comparison of an AND of a bit equal
10745 to the sign bit, replace this with a LT or GE comparison of
10746 the underlying value. */
10747 if (equality_comparison_p
10749 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10750 && mode_width <= HOST_BITS_PER_WIDE_INT
10751 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10752 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10754 op0 = XEXP (op0, 0);
10755 code = (code == EQ ? GE : LT);
10759 /* If this AND operation is really a ZERO_EXTEND from a narrower
10760 mode, the constant fits within that mode, and this is either an
10761 equality or unsigned comparison, try to do this comparison in
10762 the narrower mode. */
10763 if ((equality_comparison_p || unsigned_comparison_p)
10764 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10765 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10766 & GET_MODE_MASK (mode))
10768 && const_op >> i == 0
10769 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10771 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10775 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10776 in both M1 and M2 and the SUBREG is either paradoxical or
10777 represents the low part, permute the SUBREG and the AND and
10779 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10781 #ifdef WORD_REGISTER_OPERATIONS
10783 > (GET_MODE_BITSIZE
10784 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10785 && mode_width <= BITS_PER_WORD)
10788 <= (GET_MODE_BITSIZE
10789 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10790 && subreg_lowpart_p (XEXP (op0, 0))))
10791 #ifndef WORD_REGISTER_OPERATIONS
10792 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10793 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10794 As originally written the upper bits have a defined value
10795 due to the AND operation. However, if we commute the AND
10796 inside the SUBREG then they no longer have defined values
10797 and the meaning of the code has been changed. */
10798 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10799 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10801 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10802 && mode_width <= HOST_BITS_PER_WIDE_INT
10803 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10804 <= HOST_BITS_PER_WIDE_INT)
10805 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10806 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10807 & INTVAL (XEXP (op0, 1)))
10808 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10809 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10810 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10814 = gen_lowpart_for_combine
10816 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10817 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10821 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10822 (eq (and (lshiftrt X) 1) 0). */
10823 if (const_op == 0 && equality_comparison_p
10824 && XEXP (op0, 1) == const1_rtx
10825 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10826 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10828 op0 = simplify_and_const_int
10830 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10831 XEXP (XEXP (op0, 0), 1)),
10832 (HOST_WIDE_INT) 1);
10833 code = (code == NE ? EQ : NE);
10839 /* If we have (compare (ashift FOO N) (const_int C)) and
10840 the high order N bits of FOO (N+1 if an inequality comparison)
10841 are known to be zero, we can do this by comparing FOO with C
10842 shifted right N bits so long as the low-order N bits of C are
10844 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10845 && INTVAL (XEXP (op0, 1)) >= 0
10846 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10847 < HOST_BITS_PER_WIDE_INT)
10849 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10850 && mode_width <= HOST_BITS_PER_WIDE_INT
10851 && (nonzero_bits (XEXP (op0, 0), mode)
10852 & ~(mask >> (INTVAL (XEXP (op0, 1))
10853 + ! equality_comparison_p))) == 0)
10855 /* We must perform a logical shift, not an arithmetic one,
10856 as we want the top N bits of C to be zero. */
10857 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10859 temp >>= INTVAL (XEXP (op0, 1));
10860 op1 = gen_int_mode (temp, mode);
10861 op0 = XEXP (op0, 0);
10865 /* If we are doing a sign bit comparison, it means we are testing
10866 a particular bit. Convert it to the appropriate AND. */
10867 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10868 && mode_width <= HOST_BITS_PER_WIDE_INT)
10870 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10873 - INTVAL (XEXP (op0, 1)))));
10874 code = (code == LT ? NE : EQ);
10878 /* If this an equality comparison with zero and we are shifting
10879 the low bit to the sign bit, we can convert this to an AND of the
10881 if (const_op == 0 && equality_comparison_p
10882 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10883 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10886 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10887 (HOST_WIDE_INT) 1);
10893 /* If this is an equality comparison with zero, we can do this
10894 as a logical shift, which might be much simpler. */
10895 if (equality_comparison_p && const_op == 0
10896 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10898 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10900 INTVAL (XEXP (op0, 1)));
10904 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10905 do the comparison in a narrower mode. */
10906 if (! unsigned_comparison_p
10907 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10908 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10909 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10910 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10911 MODE_INT, 1)) != BLKmode
10912 && (((unsigned HOST_WIDE_INT) const_op
10913 + (GET_MODE_MASK (tmode) >> 1) + 1)
10914 <= GET_MODE_MASK (tmode)))
10916 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10920 /* Likewise if OP0 is a PLUS of a sign extension with a
10921 constant, which is usually represented with the PLUS
10922 between the shifts. */
10923 if (! unsigned_comparison_p
10924 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10925 && GET_CODE (XEXP (op0, 0)) == PLUS
10926 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10927 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10928 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10929 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10930 MODE_INT, 1)) != BLKmode
10931 && (((unsigned HOST_WIDE_INT) const_op
10932 + (GET_MODE_MASK (tmode) >> 1) + 1)
10933 <= GET_MODE_MASK (tmode)))
10935 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10936 rtx add_const = XEXP (XEXP (op0, 0), 1);
10937 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10940 op0 = gen_binary (PLUS, tmode,
10941 gen_lowpart_for_combine (tmode, inner),
10946 /* ... fall through ... */
10948 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10949 the low order N bits of FOO are known to be zero, we can do this
10950 by comparing FOO with C shifted left N bits so long as no
10951 overflow occurs. */
10952 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10953 && INTVAL (XEXP (op0, 1)) >= 0
10954 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10955 && mode_width <= HOST_BITS_PER_WIDE_INT
10956 && (nonzero_bits (XEXP (op0, 0), mode)
10957 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10958 && (((unsigned HOST_WIDE_INT) const_op
10959 + (GET_CODE (op0) != LSHIFTRT
10960 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10963 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10965 /* If the shift was logical, then we must make the condition
10967 if (GET_CODE (op0) == LSHIFTRT)
10968 code = unsigned_condition (code);
10970 const_op <<= INTVAL (XEXP (op0, 1));
10971 op1 = GEN_INT (const_op);
10972 op0 = XEXP (op0, 0);
10976 /* If we are using this shift to extract just the sign bit, we
10977 can replace this with an LT or GE comparison. */
10979 && (equality_comparison_p || sign_bit_comparison_p)
10980 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10981 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10984 op0 = XEXP (op0, 0);
10985 code = (code == NE || code == GT ? LT : GE);
10997 /* Now make any compound operations involved in this comparison. Then,
10998 check for an outmost SUBREG on OP0 that is not doing anything or is
10999 paradoxical. The latter transformation must only be performed when
11000 it is known that the "extra" bits will be the same in op0 and op1 or
11001 that they don't matter. There are three cases to consider:
11003 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11004 care bits and we can assume they have any convenient value. So
11005 making the transformation is safe.
11007 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11008 In this case the upper bits of op0 are undefined. We should not make
11009 the simplification in that case as we do not know the contents of
11012 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11013 NIL. In that case we know those bits are zeros or ones. We must
11014 also be sure that they are the same as the upper bits of op1.
11016 We can never remove a SUBREG for a non-equality comparison because
11017 the sign bit is in a different place in the underlying object. */
11019 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11020 op1 = make_compound_operation (op1, SET);
11022 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11023 /* Case 3 above, to sometimes allow (subreg (mem x)), isn't
11025 && GET_CODE (SUBREG_REG (op0)) == REG
11026 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11027 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11028 && (code == NE || code == EQ))
11030 if (GET_MODE_SIZE (GET_MODE (op0))
11031 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11033 op0 = SUBREG_REG (op0);
11034 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11036 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11037 <= HOST_BITS_PER_WIDE_INT)
11038 && (nonzero_bits (SUBREG_REG (op0),
11039 GET_MODE (SUBREG_REG (op0)))
11040 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11042 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11044 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11045 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11046 op0 = SUBREG_REG (op0), op1 = tem;
11050 /* We now do the opposite procedure: Some machines don't have compare
11051 insns in all modes. If OP0's mode is an integer mode smaller than a
11052 word and we can't do a compare in that mode, see if there is a larger
11053 mode for which we can do the compare. There are a number of cases in
11054 which we can use the wider mode. */
11056 mode = GET_MODE (op0);
11057 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11058 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11059 && ! have_insn_for (COMPARE, mode))
11060 for (tmode = GET_MODE_WIDER_MODE (mode);
11062 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11063 tmode = GET_MODE_WIDER_MODE (tmode))
11064 if (have_insn_for (COMPARE, tmode))
11068 /* If the only nonzero bits in OP0 and OP1 are those in the
11069 narrower mode and this is an equality or unsigned comparison,
11070 we can use the wider mode. Similarly for sign-extended
11071 values, in which case it is true for all comparisons. */
11072 zero_extended = ((code == EQ || code == NE
11073 || code == GEU || code == GTU
11074 || code == LEU || code == LTU)
11075 && (nonzero_bits (op0, tmode)
11076 & ~GET_MODE_MASK (mode)) == 0
11077 && ((GET_CODE (op1) == CONST_INT
11078 || (nonzero_bits (op1, tmode)
11079 & ~GET_MODE_MASK (mode)) == 0)));
11082 || ((num_sign_bit_copies (op0, tmode)
11083 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11084 - GET_MODE_BITSIZE (mode)))
11085 && (num_sign_bit_copies (op1, tmode)
11086 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11087 - GET_MODE_BITSIZE (mode)))))
11089 /* If OP0 is an AND and we don't have an AND in MODE either,
11090 make a new AND in the proper mode. */
11091 if (GET_CODE (op0) == AND
11092 && !have_insn_for (AND, mode))
11093 op0 = gen_binary (AND, tmode,
11094 gen_lowpart_for_combine (tmode,
11096 gen_lowpart_for_combine (tmode,
11099 op0 = gen_lowpart_for_combine (tmode, op0);
11100 if (zero_extended && GET_CODE (op1) == CONST_INT)
11101 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11102 op1 = gen_lowpart_for_combine (tmode, op1);
11106 /* If this is a test for negative, we can make an explicit
11107 test of the sign bit. */
11109 if (op1 == const0_rtx && (code == LT || code == GE)
11110 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11112 op0 = gen_binary (AND, tmode,
11113 gen_lowpart_for_combine (tmode, op0),
11114 GEN_INT ((HOST_WIDE_INT) 1
11115 << (GET_MODE_BITSIZE (mode) - 1)));
11116 code = (code == LT) ? NE : EQ;
11121 #ifdef CANONICALIZE_COMPARISON
11122 /* If this machine only supports a subset of valid comparisons, see if we
11123 can convert an unsupported one into a supported one. */
11124 CANONICALIZE_COMPARISON (code, op0, op1);
11133 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11134 searching backward. */
11135 static enum rtx_code
11136 combine_reversed_comparison_code (exp)
11139 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11142 if (code1 != UNKNOWN
11143 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11145 /* Otherwise try and find where the condition codes were last set and
11147 x = get_last_value (XEXP (exp, 0));
11148 if (!x || GET_CODE (x) != COMPARE)
11150 return reversed_comparison_code_parts (GET_CODE (exp),
11151 XEXP (x, 0), XEXP (x, 1), NULL);
11153 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11154 Return NULL_RTX in case we fail to do the reversal. */
11156 reversed_comparison (exp, mode, op0, op1)
11158 enum machine_mode mode;
11160 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11161 if (reversed_code == UNKNOWN)
11164 return gen_binary (reversed_code, mode, op0, op1);
11167 /* Utility function for following routine. Called when X is part of a value
11168 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11169 for each register mentioned. Similar to mention_regs in cse.c */
11172 update_table_tick (x)
11175 enum rtx_code code = GET_CODE (x);
11176 const char *fmt = GET_RTX_FORMAT (code);
11181 unsigned int regno = REGNO (x);
11182 unsigned int endregno
11183 = regno + (regno < FIRST_PSEUDO_REGISTER
11184 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11187 for (r = regno; r < endregno; r++)
11188 reg_last_set_table_tick[r] = label_tick;
11193 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11194 /* Note that we can't have an "E" in values stored; see
11195 get_last_value_validate. */
11197 update_table_tick (XEXP (x, i));
11200 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11201 are saying that the register is clobbered and we no longer know its
11202 value. If INSN is zero, don't update reg_last_set; this is only permitted
11203 with VALUE also zero and is used to invalidate the register. */
11206 record_value_for_reg (reg, insn, value)
11211 unsigned int regno = REGNO (reg);
11212 unsigned int endregno
11213 = regno + (regno < FIRST_PSEUDO_REGISTER
11214 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11217 /* If VALUE contains REG and we have a previous value for REG, substitute
11218 the previous value. */
11219 if (value && insn && reg_overlap_mentioned_p (reg, value))
11223 /* Set things up so get_last_value is allowed to see anything set up to
11225 subst_low_cuid = INSN_CUID (insn);
11226 tem = get_last_value (reg);
11228 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11229 it isn't going to be useful and will take a lot of time to process,
11230 so just use the CLOBBER. */
11234 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11235 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11236 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11237 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11238 tem = XEXP (tem, 0);
11240 value = replace_rtx (copy_rtx (value), reg, tem);
11244 /* For each register modified, show we don't know its value, that
11245 we don't know about its bitwise content, that its value has been
11246 updated, and that we don't know the location of the death of the
11248 for (i = regno; i < endregno; i++)
11251 reg_last_set[i] = insn;
11253 reg_last_set_value[i] = 0;
11254 reg_last_set_mode[i] = 0;
11255 reg_last_set_nonzero_bits[i] = 0;
11256 reg_last_set_sign_bit_copies[i] = 0;
11257 reg_last_death[i] = 0;
11260 /* Mark registers that are being referenced in this value. */
11262 update_table_tick (value);
11264 /* Now update the status of each register being set.
11265 If someone is using this register in this block, set this register
11266 to invalid since we will get confused between the two lives in this
11267 basic block. This makes using this register always invalid. In cse, we
11268 scan the table to invalidate all entries using this register, but this
11269 is too much work for us. */
11271 for (i = regno; i < endregno; i++)
11273 reg_last_set_label[i] = label_tick;
11274 if (value && reg_last_set_table_tick[i] == label_tick)
11275 reg_last_set_invalid[i] = 1;
11277 reg_last_set_invalid[i] = 0;
11280 /* The value being assigned might refer to X (like in "x++;"). In that
11281 case, we must replace it with (clobber (const_int 0)) to prevent
11283 if (value && ! get_last_value_validate (&value, insn,
11284 reg_last_set_label[regno], 0))
11286 value = copy_rtx (value);
11287 if (! get_last_value_validate (&value, insn,
11288 reg_last_set_label[regno], 1))
11292 /* For the main register being modified, update the value, the mode, the
11293 nonzero bits, and the number of sign bit copies. */
11295 reg_last_set_value[regno] = value;
11299 enum machine_mode mode = GET_MODE (reg);
11300 subst_low_cuid = INSN_CUID (insn);
11301 reg_last_set_mode[regno] = mode;
11302 if (GET_MODE_CLASS (mode) == MODE_INT
11303 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11304 mode = nonzero_bits_mode;
11305 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11306 reg_last_set_sign_bit_copies[regno]
11307 = num_sign_bit_copies (value, GET_MODE (reg));
11311 /* Called via note_stores from record_dead_and_set_regs to handle one
11312 SET or CLOBBER in an insn. DATA is the instruction in which the
11313 set is occurring. */
11316 record_dead_and_set_regs_1 (dest, setter, data)
11320 rtx record_dead_insn = (rtx) data;
11322 if (GET_CODE (dest) == SUBREG)
11323 dest = SUBREG_REG (dest);
11325 if (GET_CODE (dest) == REG)
11327 /* If we are setting the whole register, we know its value. Otherwise
11328 show that we don't know the value. We can handle SUBREG in
11330 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11331 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11332 else if (GET_CODE (setter) == SET
11333 && GET_CODE (SET_DEST (setter)) == SUBREG
11334 && SUBREG_REG (SET_DEST (setter)) == dest
11335 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11336 && subreg_lowpart_p (SET_DEST (setter)))
11337 record_value_for_reg (dest, record_dead_insn,
11338 gen_lowpart_for_combine (GET_MODE (dest),
11339 SET_SRC (setter)));
11341 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11343 else if (GET_CODE (dest) == MEM
11344 /* Ignore pushes, they clobber nothing. */
11345 && ! push_operand (dest, GET_MODE (dest)))
11346 mem_last_set = INSN_CUID (record_dead_insn);
11349 /* Update the records of when each REG was most recently set or killed
11350 for the things done by INSN. This is the last thing done in processing
11351 INSN in the combiner loop.
11353 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11354 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11355 and also the similar information mem_last_set (which insn most recently
11356 modified memory) and last_call_cuid (which insn was the most recent
11357 subroutine call). */
11360 record_dead_and_set_regs (insn)
11366 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11368 if (REG_NOTE_KIND (link) == REG_DEAD
11369 && GET_CODE (XEXP (link, 0)) == REG)
11371 unsigned int regno = REGNO (XEXP (link, 0));
11372 unsigned int endregno
11373 = regno + (regno < FIRST_PSEUDO_REGISTER
11374 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11377 for (i = regno; i < endregno; i++)
11378 reg_last_death[i] = insn;
11380 else if (REG_NOTE_KIND (link) == REG_INC)
11381 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11384 if (GET_CODE (insn) == CALL_INSN)
11386 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11387 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11389 reg_last_set_value[i] = 0;
11390 reg_last_set_mode[i] = 0;
11391 reg_last_set_nonzero_bits[i] = 0;
11392 reg_last_set_sign_bit_copies[i] = 0;
11393 reg_last_death[i] = 0;
11396 last_call_cuid = mem_last_set = INSN_CUID (insn);
11398 /* Don't bother recording what this insn does. It might set the
11399 return value register, but we can't combine into a call
11400 pattern anyway, so there's no point trying (and it may cause
11401 a crash, if e.g. we wind up asking for last_set_value of a
11402 SUBREG of the return value register). */
11406 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11409 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11410 register present in the SUBREG, so for each such SUBREG go back and
11411 adjust nonzero and sign bit information of the registers that are
11412 known to have some zero/sign bits set.
11414 This is needed because when combine blows the SUBREGs away, the
11415 information on zero/sign bits is lost and further combines can be
11416 missed because of that. */
11419 record_promoted_value (insn, subreg)
11424 unsigned int regno = REGNO (SUBREG_REG (subreg));
11425 enum machine_mode mode = GET_MODE (subreg);
11427 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11430 for (links = LOG_LINKS (insn); links;)
11432 insn = XEXP (links, 0);
11433 set = single_set (insn);
11435 if (! set || GET_CODE (SET_DEST (set)) != REG
11436 || REGNO (SET_DEST (set)) != regno
11437 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11439 links = XEXP (links, 1);
11443 if (reg_last_set[regno] == insn)
11445 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11446 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11449 if (GET_CODE (SET_SRC (set)) == REG)
11451 regno = REGNO (SET_SRC (set));
11452 links = LOG_LINKS (insn);
11459 /* Scan X for promoted SUBREGs. For each one found,
11460 note what it implies to the registers used in it. */
11463 check_promoted_subreg (insn, x)
11467 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11468 && GET_CODE (SUBREG_REG (x)) == REG)
11469 record_promoted_value (insn, x);
11472 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11475 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11479 check_promoted_subreg (insn, XEXP (x, i));
11483 if (XVEC (x, i) != 0)
11484 for (j = 0; j < XVECLEN (x, i); j++)
11485 check_promoted_subreg (insn, XVECEXP (x, i, j));
11491 /* Utility routine for the following function. Verify that all the registers
11492 mentioned in *LOC are valid when *LOC was part of a value set when
11493 label_tick == TICK. Return 0 if some are not.
11495 If REPLACE is non-zero, replace the invalid reference with
11496 (clobber (const_int 0)) and return 1. This replacement is useful because
11497 we often can get useful information about the form of a value (e.g., if
11498 it was produced by a shift that always produces -1 or 0) even though
11499 we don't know exactly what registers it was produced from. */
11502 get_last_value_validate (loc, insn, tick, replace)
11509 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11510 int len = GET_RTX_LENGTH (GET_CODE (x));
11513 if (GET_CODE (x) == REG)
11515 unsigned int regno = REGNO (x);
11516 unsigned int endregno
11517 = regno + (regno < FIRST_PSEUDO_REGISTER
11518 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11521 for (j = regno; j < endregno; j++)
11522 if (reg_last_set_invalid[j]
11523 /* If this is a pseudo-register that was only set once and not
11524 live at the beginning of the function, it is always valid. */
11525 || (! (regno >= FIRST_PSEUDO_REGISTER
11526 && REG_N_SETS (regno) == 1
11527 && (! REGNO_REG_SET_P
11528 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11529 && reg_last_set_label[j] > tick))
11532 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11538 /* If this is a memory reference, make sure that there were
11539 no stores after it that might have clobbered the value. We don't
11540 have alias info, so we assume any store invalidates it. */
11541 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11542 && INSN_CUID (insn) <= mem_last_set)
11545 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11549 for (i = 0; i < len; i++)
11551 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11552 /* Don't bother with these. They shouldn't occur anyway. */
11556 /* If we haven't found a reason for it to be invalid, it is valid. */
11560 /* Get the last value assigned to X, if known. Some registers
11561 in the value may be replaced with (clobber (const_int 0)) if their value
11562 is known longer known reliably. */
11568 unsigned int regno;
11571 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11572 then convert it to the desired mode. If this is a paradoxical SUBREG,
11573 we cannot predict what values the "extra" bits might have. */
11574 if (GET_CODE (x) == SUBREG
11575 && subreg_lowpart_p (x)
11576 && (GET_MODE_SIZE (GET_MODE (x))
11577 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11578 && (value = get_last_value (SUBREG_REG (x))) != 0)
11579 return gen_lowpart_for_combine (GET_MODE (x), value);
11581 if (GET_CODE (x) != REG)
11585 value = reg_last_set_value[regno];
11587 /* If we don't have a value, or if it isn't for this basic block and
11588 it's either a hard register, set more than once, or it's a live
11589 at the beginning of the function, return 0.
11591 Because if it's not live at the beginning of the function then the reg
11592 is always set before being used (is never used without being set).
11593 And, if it's set only once, and it's always set before use, then all
11594 uses must have the same last value, even if it's not from this basic
11598 || (reg_last_set_label[regno] != label_tick
11599 && (regno < FIRST_PSEUDO_REGISTER
11600 || REG_N_SETS (regno) != 1
11601 || (REGNO_REG_SET_P
11602 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11605 /* If the value was set in a later insn than the ones we are processing,
11606 we can't use it even if the register was only set once. */
11607 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11610 /* If the value has all its registers valid, return it. */
11611 if (get_last_value_validate (&value, reg_last_set[regno],
11612 reg_last_set_label[regno], 0))
11615 /* Otherwise, make a copy and replace any invalid register with
11616 (clobber (const_int 0)). If that fails for some reason, return 0. */
11618 value = copy_rtx (value);
11619 if (get_last_value_validate (&value, reg_last_set[regno],
11620 reg_last_set_label[regno], 1))
11626 /* Return nonzero if expression X refers to a REG or to memory
11627 that is set in an instruction more recent than FROM_CUID. */
11630 use_crosses_set_p (x, from_cuid)
11636 enum rtx_code code = GET_CODE (x);
11640 unsigned int regno = REGNO (x);
11641 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11642 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11644 #ifdef PUSH_ROUNDING
11645 /* Don't allow uses of the stack pointer to be moved,
11646 because we don't know whether the move crosses a push insn. */
11647 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11650 for (; regno < endreg; regno++)
11651 if (reg_last_set[regno]
11652 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11657 if (code == MEM && mem_last_set > from_cuid)
11660 fmt = GET_RTX_FORMAT (code);
11662 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11667 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11668 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11671 else if (fmt[i] == 'e'
11672 && use_crosses_set_p (XEXP (x, i), from_cuid))
11678 /* Define three variables used for communication between the following
11681 static unsigned int reg_dead_regno, reg_dead_endregno;
11682 static int reg_dead_flag;
11684 /* Function called via note_stores from reg_dead_at_p.
11686 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11687 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11690 reg_dead_at_p_1 (dest, x, data)
11693 void *data ATTRIBUTE_UNUSED;
11695 unsigned int regno, endregno;
11697 if (GET_CODE (dest) != REG)
11700 regno = REGNO (dest);
11701 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11702 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11704 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11705 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11708 /* Return non-zero if REG is known to be dead at INSN.
11710 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11711 referencing REG, it is dead. If we hit a SET referencing REG, it is
11712 live. Otherwise, see if it is live or dead at the start of the basic
11713 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11714 must be assumed to be always live. */
11717 reg_dead_at_p (reg, insn)
11724 /* Set variables for reg_dead_at_p_1. */
11725 reg_dead_regno = REGNO (reg);
11726 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11727 ? HARD_REGNO_NREGS (reg_dead_regno,
11733 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11734 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11736 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11737 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11741 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11742 beginning of function. */
11743 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11744 insn = prev_nonnote_insn (insn))
11746 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11748 return reg_dead_flag == 1 ? 1 : 0;
11750 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11754 /* Get the basic block that we were in. */
11756 block = ENTRY_BLOCK_PTR->next_bb;
11759 FOR_EACH_BB (block)
11760 if (insn == block->head)
11763 if (block == EXIT_BLOCK_PTR)
11767 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11768 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11774 /* Note hard registers in X that are used. This code is similar to
11775 that in flow.c, but much simpler since we don't care about pseudos. */
11778 mark_used_regs_combine (x)
11781 RTX_CODE code = GET_CODE (x);
11782 unsigned int regno;
11795 case ADDR_DIFF_VEC:
11798 /* CC0 must die in the insn after it is set, so we don't need to take
11799 special note of it here. */
11805 /* If we are clobbering a MEM, mark any hard registers inside the
11806 address as used. */
11807 if (GET_CODE (XEXP (x, 0)) == MEM)
11808 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11813 /* A hard reg in a wide mode may really be multiple registers.
11814 If so, mark all of them just like the first. */
11815 if (regno < FIRST_PSEUDO_REGISTER)
11817 unsigned int endregno, r;
11819 /* None of this applies to the stack, frame or arg pointers */
11820 if (regno == STACK_POINTER_REGNUM
11821 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11822 || regno == HARD_FRAME_POINTER_REGNUM
11824 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11825 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11827 || regno == FRAME_POINTER_REGNUM)
11830 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11831 for (r = regno; r < endregno; r++)
11832 SET_HARD_REG_BIT (newpat_used_regs, r);
11838 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11840 rtx testreg = SET_DEST (x);
11842 while (GET_CODE (testreg) == SUBREG
11843 || GET_CODE (testreg) == ZERO_EXTRACT
11844 || GET_CODE (testreg) == SIGN_EXTRACT
11845 || GET_CODE (testreg) == STRICT_LOW_PART)
11846 testreg = XEXP (testreg, 0);
11848 if (GET_CODE (testreg) == MEM)
11849 mark_used_regs_combine (XEXP (testreg, 0));
11851 mark_used_regs_combine (SET_SRC (x));
11859 /* Recursively scan the operands of this expression. */
11862 const char *fmt = GET_RTX_FORMAT (code);
11864 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11867 mark_used_regs_combine (XEXP (x, i));
11868 else if (fmt[i] == 'E')
11872 for (j = 0; j < XVECLEN (x, i); j++)
11873 mark_used_regs_combine (XVECEXP (x, i, j));
11879 /* Remove register number REGNO from the dead registers list of INSN.
11881 Return the note used to record the death, if there was one. */
11884 remove_death (regno, insn)
11885 unsigned int regno;
11888 rtx note = find_regno_note (insn, REG_DEAD, regno);
11892 REG_N_DEATHS (regno)--;
11893 remove_note (insn, note);
11899 /* For each register (hardware or pseudo) used within expression X, if its
11900 death is in an instruction with cuid between FROM_CUID (inclusive) and
11901 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11902 list headed by PNOTES.
11904 That said, don't move registers killed by maybe_kill_insn.
11906 This is done when X is being merged by combination into TO_INSN. These
11907 notes will then be distributed as needed. */
11910 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11912 rtx maybe_kill_insn;
11919 enum rtx_code code = GET_CODE (x);
11923 unsigned int regno = REGNO (x);
11924 rtx where_dead = reg_last_death[regno];
11925 rtx before_dead, after_dead;
11927 /* Don't move the register if it gets killed in between from and to */
11928 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11929 && ! reg_referenced_p (x, maybe_kill_insn))
11932 /* WHERE_DEAD could be a USE insn made by combine, so first we
11933 make sure that we have insns with valid INSN_CUID values. */
11934 before_dead = where_dead;
11935 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11936 before_dead = PREV_INSN (before_dead);
11938 after_dead = where_dead;
11939 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11940 after_dead = NEXT_INSN (after_dead);
11942 if (before_dead && after_dead
11943 && INSN_CUID (before_dead) >= from_cuid
11944 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11945 || (where_dead != after_dead
11946 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11948 rtx note = remove_death (regno, where_dead);
11950 /* It is possible for the call above to return 0. This can occur
11951 when reg_last_death points to I2 or I1 that we combined with.
11952 In that case make a new note.
11954 We must also check for the case where X is a hard register
11955 and NOTE is a death note for a range of hard registers
11956 including X. In that case, we must put REG_DEAD notes for
11957 the remaining registers in place of NOTE. */
11959 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11960 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11961 > GET_MODE_SIZE (GET_MODE (x))))
11963 unsigned int deadregno = REGNO (XEXP (note, 0));
11964 unsigned int deadend
11965 = (deadregno + HARD_REGNO_NREGS (deadregno,
11966 GET_MODE (XEXP (note, 0))));
11967 unsigned int ourend
11968 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11971 for (i = deadregno; i < deadend; i++)
11972 if (i < regno || i >= ourend)
11973 REG_NOTES (where_dead)
11974 = gen_rtx_EXPR_LIST (REG_DEAD,
11976 REG_NOTES (where_dead));
11979 /* If we didn't find any note, or if we found a REG_DEAD note that
11980 covers only part of the given reg, and we have a multi-reg hard
11981 register, then to be safe we must check for REG_DEAD notes
11982 for each register other than the first. They could have
11983 their own REG_DEAD notes lying around. */
11984 else if ((note == 0
11986 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11987 < GET_MODE_SIZE (GET_MODE (x)))))
11988 && regno < FIRST_PSEUDO_REGISTER
11989 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11991 unsigned int ourend
11992 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11993 unsigned int i, offset;
11997 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12001 for (i = regno + offset; i < ourend; i++)
12002 move_deaths (regno_reg_rtx[i],
12003 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12006 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12008 XEXP (note, 1) = *pnotes;
12012 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12014 REG_N_DEATHS (regno)++;
12020 else if (GET_CODE (x) == SET)
12022 rtx dest = SET_DEST (x);
12024 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12026 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12027 that accesses one word of a multi-word item, some
12028 piece of everything register in the expression is used by
12029 this insn, so remove any old death. */
12030 /* ??? So why do we test for equality of the sizes? */
12032 if (GET_CODE (dest) == ZERO_EXTRACT
12033 || GET_CODE (dest) == STRICT_LOW_PART
12034 || (GET_CODE (dest) == SUBREG
12035 && (((GET_MODE_SIZE (GET_MODE (dest))
12036 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12037 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12038 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12040 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12044 /* If this is some other SUBREG, we know it replaces the entire
12045 value, so use that as the destination. */
12046 if (GET_CODE (dest) == SUBREG)
12047 dest = SUBREG_REG (dest);
12049 /* If this is a MEM, adjust deaths of anything used in the address.
12050 For a REG (the only other possibility), the entire value is
12051 being replaced so the old value is not used in this insn. */
12053 if (GET_CODE (dest) == MEM)
12054 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12059 else if (GET_CODE (x) == CLOBBER)
12062 len = GET_RTX_LENGTH (code);
12063 fmt = GET_RTX_FORMAT (code);
12065 for (i = 0; i < len; i++)
12070 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12071 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12074 else if (fmt[i] == 'e')
12075 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12079 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12080 pattern of an insn. X must be a REG. */
12083 reg_bitfield_target_p (x, body)
12089 if (GET_CODE (body) == SET)
12091 rtx dest = SET_DEST (body);
12093 unsigned int regno, tregno, endregno, endtregno;
12095 if (GET_CODE (dest) == ZERO_EXTRACT)
12096 target = XEXP (dest, 0);
12097 else if (GET_CODE (dest) == STRICT_LOW_PART)
12098 target = SUBREG_REG (XEXP (dest, 0));
12102 if (GET_CODE (target) == SUBREG)
12103 target = SUBREG_REG (target);
12105 if (GET_CODE (target) != REG)
12108 tregno = REGNO (target), regno = REGNO (x);
12109 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12110 return target == x;
12112 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12113 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12115 return endregno > tregno && regno < endtregno;
12118 else if (GET_CODE (body) == PARALLEL)
12119 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12120 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12126 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12127 as appropriate. I3 and I2 are the insns resulting from the combination
12128 insns including FROM (I2 may be zero).
12130 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12131 not need REG_DEAD notes because they are being substituted for. This
12132 saves searching in the most common cases.
12134 Each note in the list is either ignored or placed on some insns, depending
12135 on the type of note. */
12138 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12142 rtx elim_i2, elim_i1;
12144 rtx note, next_note;
12147 for (note = notes; note; note = next_note)
12149 rtx place = 0, place2 = 0;
12151 /* If this NOTE references a pseudo register, ensure it references
12152 the latest copy of that register. */
12153 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12154 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12155 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12157 next_note = XEXP (note, 1);
12158 switch (REG_NOTE_KIND (note))
12162 case REG_EXEC_COUNT:
12163 /* Doesn't matter much where we put this, as long as it's somewhere.
12164 It is preferable to keep these notes on branches, which is most
12165 likely to be i3. */
12169 case REG_VTABLE_REF:
12170 /* ??? Should remain with *a particular* memory load. Given the
12171 nature of vtable data, the last insn seems relatively safe. */
12175 case REG_NON_LOCAL_GOTO:
12176 if (GET_CODE (i3) == JUMP_INSN)
12178 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12184 case REG_EH_REGION:
12185 /* These notes must remain with the call or trapping instruction. */
12186 if (GET_CODE (i3) == CALL_INSN)
12188 else if (i2 && GET_CODE (i2) == CALL_INSN)
12190 else if (flag_non_call_exceptions)
12192 if (may_trap_p (i3))
12194 else if (i2 && may_trap_p (i2))
12196 /* ??? Otherwise assume we've combined things such that we
12197 can now prove that the instructions can't trap. Drop the
12198 note in this case. */
12206 /* These notes must remain with the call. It should not be
12207 possible for both I2 and I3 to be a call. */
12208 if (GET_CODE (i3) == CALL_INSN)
12210 else if (i2 && GET_CODE (i2) == CALL_INSN)
12217 /* Any clobbers for i3 may still exist, and so we must process
12218 REG_UNUSED notes from that insn.
12220 Any clobbers from i2 or i1 can only exist if they were added by
12221 recog_for_combine. In that case, recog_for_combine created the
12222 necessary REG_UNUSED notes. Trying to keep any original
12223 REG_UNUSED notes from these insns can cause incorrect output
12224 if it is for the same register as the original i3 dest.
12225 In that case, we will notice that the register is set in i3,
12226 and then add a REG_UNUSED note for the destination of i3, which
12227 is wrong. However, it is possible to have REG_UNUSED notes from
12228 i2 or i1 for register which were both used and clobbered, so
12229 we keep notes from i2 or i1 if they will turn into REG_DEAD
12232 /* If this register is set or clobbered in I3, put the note there
12233 unless there is one already. */
12234 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12236 if (from_insn != i3)
12239 if (! (GET_CODE (XEXP (note, 0)) == REG
12240 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12241 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12244 /* Otherwise, if this register is used by I3, then this register
12245 now dies here, so we must put a REG_DEAD note here unless there
12247 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12248 && ! (GET_CODE (XEXP (note, 0)) == REG
12249 ? find_regno_note (i3, REG_DEAD,
12250 REGNO (XEXP (note, 0)))
12251 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12253 PUT_REG_NOTE_KIND (note, REG_DEAD);
12261 /* These notes say something about results of an insn. We can
12262 only support them if they used to be on I3 in which case they
12263 remain on I3. Otherwise they are ignored.
12265 If the note refers to an expression that is not a constant, we
12266 must also ignore the note since we cannot tell whether the
12267 equivalence is still true. It might be possible to do
12268 slightly better than this (we only have a problem if I2DEST
12269 or I1DEST is present in the expression), but it doesn't
12270 seem worth the trouble. */
12272 if (from_insn == i3
12273 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12278 case REG_NO_CONFLICT:
12279 /* These notes say something about how a register is used. They must
12280 be present on any use of the register in I2 or I3. */
12281 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12284 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12294 /* This can show up in several ways -- either directly in the
12295 pattern, or hidden off in the constant pool with (or without?)
12296 a REG_EQUAL note. */
12297 /* ??? Ignore the without-reg_equal-note problem for now. */
12298 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12299 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12300 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12301 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12305 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12306 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12307 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12308 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12316 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12317 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12318 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12320 if (JUMP_LABEL (place) != XEXP (note, 0))
12322 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12323 LABEL_NUSES (JUMP_LABEL (place))--;
12326 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12328 if (JUMP_LABEL (place2) != XEXP (note, 0))
12330 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12331 LABEL_NUSES (JUMP_LABEL (place2))--;
12338 /* These notes say something about the value of a register prior
12339 to the execution of an insn. It is too much trouble to see
12340 if the note is still correct in all situations. It is better
12341 to simply delete it. */
12345 /* If the insn previously containing this note still exists,
12346 put it back where it was. Otherwise move it to the previous
12347 insn. Adjust the corresponding REG_LIBCALL note. */
12348 if (GET_CODE (from_insn) != NOTE)
12352 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12353 place = prev_real_insn (from_insn);
12355 XEXP (tem, 0) = place;
12356 /* If we're deleting the last remaining instruction of a
12357 libcall sequence, don't add the notes. */
12358 else if (XEXP (note, 0) == from_insn)
12364 /* This is handled similarly to REG_RETVAL. */
12365 if (GET_CODE (from_insn) != NOTE)
12369 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12370 place = next_real_insn (from_insn);
12372 XEXP (tem, 0) = place;
12373 /* If we're deleting the last remaining instruction of a
12374 libcall sequence, don't add the notes. */
12375 else if (XEXP (note, 0) == from_insn)
12381 /* If the register is used as an input in I3, it dies there.
12382 Similarly for I2, if it is non-zero and adjacent to I3.
12384 If the register is not used as an input in either I3 or I2
12385 and it is not one of the registers we were supposed to eliminate,
12386 there are two possibilities. We might have a non-adjacent I2
12387 or we might have somehow eliminated an additional register
12388 from a computation. For example, we might have had A & B where
12389 we discover that B will always be zero. In this case we will
12390 eliminate the reference to A.
12392 In both cases, we must search to see if we can find a previous
12393 use of A and put the death note there. */
12396 && GET_CODE (from_insn) == CALL_INSN
12397 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12399 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12401 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12402 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12405 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12406 || rtx_equal_p (XEXP (note, 0), elim_i1))
12411 basic_block bb = this_basic_block;
12413 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12415 if (! INSN_P (tem))
12417 if (tem == bb->head)
12422 /* If the register is being set at TEM, see if that is all
12423 TEM is doing. If so, delete TEM. Otherwise, make this
12424 into a REG_UNUSED note instead. */
12425 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12427 rtx set = single_set (tem);
12428 rtx inner_dest = 0;
12430 rtx cc0_setter = NULL_RTX;
12434 for (inner_dest = SET_DEST (set);
12435 (GET_CODE (inner_dest) == STRICT_LOW_PART
12436 || GET_CODE (inner_dest) == SUBREG
12437 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12438 inner_dest = XEXP (inner_dest, 0))
12441 /* Verify that it was the set, and not a clobber that
12442 modified the register.
12444 CC0 targets must be careful to maintain setter/user
12445 pairs. If we cannot delete the setter due to side
12446 effects, mark the user with an UNUSED note instead
12449 if (set != 0 && ! side_effects_p (SET_SRC (set))
12450 && rtx_equal_p (XEXP (note, 0), inner_dest)
12452 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12453 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12454 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12458 /* Move the notes and links of TEM elsewhere.
12459 This might delete other dead insns recursively.
12460 First set the pattern to something that won't use
12463 PATTERN (tem) = pc_rtx;
12465 distribute_notes (REG_NOTES (tem), tem, tem,
12466 NULL_RTX, NULL_RTX, NULL_RTX);
12467 distribute_links (LOG_LINKS (tem));
12469 PUT_CODE (tem, NOTE);
12470 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12471 NOTE_SOURCE_FILE (tem) = 0;
12474 /* Delete the setter too. */
12477 PATTERN (cc0_setter) = pc_rtx;
12479 distribute_notes (REG_NOTES (cc0_setter),
12480 cc0_setter, cc0_setter,
12481 NULL_RTX, NULL_RTX, NULL_RTX);
12482 distribute_links (LOG_LINKS (cc0_setter));
12484 PUT_CODE (cc0_setter, NOTE);
12485 NOTE_LINE_NUMBER (cc0_setter)
12486 = NOTE_INSN_DELETED;
12487 NOTE_SOURCE_FILE (cc0_setter) = 0;
12491 /* If the register is both set and used here, put the
12492 REG_DEAD note here, but place a REG_UNUSED note
12493 here too unless there already is one. */
12494 else if (reg_referenced_p (XEXP (note, 0),
12499 if (! find_regno_note (tem, REG_UNUSED,
12500 REGNO (XEXP (note, 0))))
12502 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12507 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12509 /* If there isn't already a REG_UNUSED note, put one
12511 if (! find_regno_note (tem, REG_UNUSED,
12512 REGNO (XEXP (note, 0))))
12517 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12518 || (GET_CODE (tem) == CALL_INSN
12519 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12523 /* If we are doing a 3->2 combination, and we have a
12524 register which formerly died in i3 and was not used
12525 by i2, which now no longer dies in i3 and is used in
12526 i2 but does not die in i2, and place is between i2
12527 and i3, then we may need to move a link from place to
12529 if (i2 && INSN_UID (place) <= max_uid_cuid
12530 && INSN_CUID (place) > INSN_CUID (i2)
12532 && INSN_CUID (from_insn) > INSN_CUID (i2)
12533 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12535 rtx links = LOG_LINKS (place);
12536 LOG_LINKS (place) = 0;
12537 distribute_links (links);
12542 if (tem == bb->head)
12546 /* We haven't found an insn for the death note and it
12547 is still a REG_DEAD note, but we have hit the beginning
12548 of the block. If the existing life info says the reg
12549 was dead, there's nothing left to do. Otherwise, we'll
12550 need to do a global life update after combine. */
12551 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12552 && REGNO_REG_SET_P (bb->global_live_at_start,
12553 REGNO (XEXP (note, 0))))
12555 SET_BIT (refresh_blocks, this_basic_block->index);
12560 /* If the register is set or already dead at PLACE, we needn't do
12561 anything with this note if it is still a REG_DEAD note.
12562 We can here if it is set at all, not if is it totally replace,
12563 which is what `dead_or_set_p' checks, so also check for it being
12566 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12568 unsigned int regno = REGNO (XEXP (note, 0));
12570 /* Similarly, if the instruction on which we want to place
12571 the note is a noop, we'll need do a global live update
12572 after we remove them in delete_noop_moves. */
12573 if (noop_move_p (place))
12575 SET_BIT (refresh_blocks, this_basic_block->index);
12579 if (dead_or_set_p (place, XEXP (note, 0))
12580 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12582 /* Unless the register previously died in PLACE, clear
12583 reg_last_death. [I no longer understand why this is
12585 if (reg_last_death[regno] != place)
12586 reg_last_death[regno] = 0;
12590 reg_last_death[regno] = place;
12592 /* If this is a death note for a hard reg that is occupying
12593 multiple registers, ensure that we are still using all
12594 parts of the object. If we find a piece of the object
12595 that is unused, we must arrange for an appropriate REG_DEAD
12596 note to be added for it. However, we can't just emit a USE
12597 and tag the note to it, since the register might actually
12598 be dead; so we recourse, and the recursive call then finds
12599 the previous insn that used this register. */
12601 if (place && regno < FIRST_PSEUDO_REGISTER
12602 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12604 unsigned int endregno
12605 = regno + HARD_REGNO_NREGS (regno,
12606 GET_MODE (XEXP (note, 0)));
12610 for (i = regno; i < endregno; i++)
12611 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12612 && ! find_regno_fusage (place, USE, i))
12613 || dead_or_set_regno_p (place, i))
12618 /* Put only REG_DEAD notes for pieces that are
12619 not already dead or set. */
12621 for (i = regno; i < endregno;
12622 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12624 rtx piece = regno_reg_rtx[i];
12625 basic_block bb = this_basic_block;
12627 if (! dead_or_set_p (place, piece)
12628 && ! reg_bitfield_target_p (piece,
12632 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12634 distribute_notes (new_note, place, place,
12635 NULL_RTX, NULL_RTX, NULL_RTX);
12637 else if (! refers_to_regno_p (i, i + 1,
12638 PATTERN (place), 0)
12639 && ! find_regno_fusage (place, USE, i))
12640 for (tem = PREV_INSN (place); ;
12641 tem = PREV_INSN (tem))
12643 if (! INSN_P (tem))
12645 if (tem == bb->head)
12647 SET_BIT (refresh_blocks,
12648 this_basic_block->index);
12654 if (dead_or_set_p (tem, piece)
12655 || reg_bitfield_target_p (piece,
12659 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12674 /* Any other notes should not be present at this point in the
12681 XEXP (note, 1) = REG_NOTES (place);
12682 REG_NOTES (place) = note;
12684 else if ((REG_NOTE_KIND (note) == REG_DEAD
12685 || REG_NOTE_KIND (note) == REG_UNUSED)
12686 && GET_CODE (XEXP (note, 0)) == REG)
12687 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12691 if ((REG_NOTE_KIND (note) == REG_DEAD
12692 || REG_NOTE_KIND (note) == REG_UNUSED)
12693 && GET_CODE (XEXP (note, 0)) == REG)
12694 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12696 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12697 REG_NOTE_KIND (note),
12699 REG_NOTES (place2));
12704 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12705 I3, I2, and I1 to new locations. This is also called in one case to
12706 add a link pointing at I3 when I3's destination is changed. */
12709 distribute_links (links)
12712 rtx link, next_link;
12714 for (link = links; link; link = next_link)
12720 next_link = XEXP (link, 1);
12722 /* If the insn that this link points to is a NOTE or isn't a single
12723 set, ignore it. In the latter case, it isn't clear what we
12724 can do other than ignore the link, since we can't tell which
12725 register it was for. Such links wouldn't be used by combine
12728 It is not possible for the destination of the target of the link to
12729 have been changed by combine. The only potential of this is if we
12730 replace I3, I2, and I1 by I3 and I2. But in that case the
12731 destination of I2 also remains unchanged. */
12733 if (GET_CODE (XEXP (link, 0)) == NOTE
12734 || (set = single_set (XEXP (link, 0))) == 0)
12737 reg = SET_DEST (set);
12738 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12739 || GET_CODE (reg) == SIGN_EXTRACT
12740 || GET_CODE (reg) == STRICT_LOW_PART)
12741 reg = XEXP (reg, 0);
12743 /* A LOG_LINK is defined as being placed on the first insn that uses
12744 a register and points to the insn that sets the register. Start
12745 searching at the next insn after the target of the link and stop
12746 when we reach a set of the register or the end of the basic block.
12748 Note that this correctly handles the link that used to point from
12749 I3 to I2. Also note that not much searching is typically done here
12750 since most links don't point very far away. */
12752 for (insn = NEXT_INSN (XEXP (link, 0));
12753 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12754 || this_basic_block->next_bb->head != insn));
12755 insn = NEXT_INSN (insn))
12756 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12758 if (reg_referenced_p (reg, PATTERN (insn)))
12762 else if (GET_CODE (insn) == CALL_INSN
12763 && find_reg_fusage (insn, USE, reg))
12769 /* If we found a place to put the link, place it there unless there
12770 is already a link to the same insn as LINK at that point. */
12776 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12777 if (XEXP (link2, 0) == XEXP (link, 0))
12782 XEXP (link, 1) = LOG_LINKS (place);
12783 LOG_LINKS (place) = link;
12785 /* Set added_links_insn to the earliest insn we added a
12787 if (added_links_insn == 0
12788 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12789 added_links_insn = place;
12795 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12801 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12802 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12803 insn = NEXT_INSN (insn);
12805 if (INSN_UID (insn) > max_uid_cuid)
12808 return INSN_CUID (insn);
12812 dump_combine_stats (file)
12817 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12818 combine_attempts, combine_merges, combine_extras, combine_successes);
12822 dump_combine_total_stats (file)
12827 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12828 total_attempts, total_merges, total_extras, total_successes);