1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 /* It is not safe to use ordinary gen_lowpart in combine.
97 Use gen_lowpart_for_combine instead. See comments there. */
98 #define gen_lowpart dont_use_gen_lowpart_you_dummy
100 /* Number of attempts to combine instructions in this function. */
102 static int combine_attempts;
104 /* Number of attempts that got as far as substitution in this function. */
106 static int combine_merges;
108 /* Number of instructions combined with added SETs in this function. */
110 static int combine_extras;
112 /* Number of instructions combined in this function. */
114 static int combine_successes;
116 /* Totals over entire compilation. */
118 static int total_attempts, total_merges, total_extras, total_successes;
120 /* Define a default value for REVERSIBLE_CC_MODE.
121 We can never assume that a condition code mode is safe to reverse unless
122 the md tells us so. */
123 #ifndef REVERSIBLE_CC_MODE
124 #define REVERSIBLE_CC_MODE(MODE) 0
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* Maximum register number, which is the size of the tables below. */
144 static int combine_max_regno;
146 /* Record last point of death of (hard or pseudo) register n. */
148 static rtx *reg_last_death;
150 /* Record last point of modification of (hard or pseudo) register n. */
152 static rtx *reg_last_set;
154 /* Record the cuid of the last insn that invalidated memory
155 (anything that writes memory, and subroutine calls, but not pushes). */
157 static int mem_last_set;
159 /* Record the cuid of the last CALL_INSN
160 so we can tell whether a potential combination crosses any calls. */
162 static int last_call_cuid;
164 /* When `subst' is called, this is the insn that is being modified
165 (by combining in a previous insn). The PATTERN of this insn
166 is still the old pattern partially modified and it should not be
167 looked at, but this may be used to examine the successors of the insn
168 to judge whether a simplification is valid. */
170 static rtx subst_insn;
172 /* This is an insn that belongs before subst_insn, but is not currently
173 on the insn chain. */
175 static rtx subst_prev_insn;
177 /* This is the lowest CUID that `subst' is currently dealing with.
178 get_last_value will not return a value if the register was set at or
179 after this CUID. If not for this mechanism, we could get confused if
180 I2 or I1 in try_combine were an insn that used the old value of a register
181 to obtain a new value. In that case, we might erroneously get the
182 new value of the register when we wanted the old one. */
184 static int subst_low_cuid;
186 /* This contains any hard registers that are used in newpat; reg_dead_at_p
187 must consider all these registers to be always live. */
189 static HARD_REG_SET newpat_used_regs;
191 /* This is an insn to which a LOG_LINKS entry has been added. If this
192 insn is the earlier than I2 or I3, combine should rescan starting at
195 static rtx added_links_insn;
197 /* Basic block number of the block in which we are performing combines. */
198 static int this_basic_block;
200 /* A bitmap indicating which blocks had registers go dead at entry.
201 After combine, we'll need to re-do global life analysis with
202 those blocks as starting points. */
203 static sbitmap refresh_blocks;
204 static int need_refresh;
206 /* The next group of arrays allows the recording of the last value assigned
207 to (hard or pseudo) register n. We use this information to see if a
208 operation being processed is redundant given a prior operation performed
209 on the register. For example, an `and' with a constant is redundant if
210 all the zero bits are already known to be turned off.
212 We use an approach similar to that used by cse, but change it in the
215 (1) We do not want to reinitialize at each label.
216 (2) It is useful, but not critical, to know the actual value assigned
217 to a register. Often just its form is helpful.
219 Therefore, we maintain the following arrays:
221 reg_last_set_value the last value assigned
222 reg_last_set_label records the value of label_tick when the
223 register was assigned
224 reg_last_set_table_tick records the value of label_tick when a
225 value using the register is assigned
226 reg_last_set_invalid set to non-zero when it is not valid
227 to use the value of this register in some
230 To understand the usage of these tables, it is important to understand
231 the distinction between the value in reg_last_set_value being valid
232 and the register being validly contained in some other expression in the
235 Entry I in reg_last_set_value is valid if it is non-zero, and either
236 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
238 Register I may validly appear in any expression returned for the value
239 of another register if reg_n_sets[i] is 1. It may also appear in the
240 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
241 reg_last_set_invalid[j] is zero.
243 If an expression is found in the table containing a register which may
244 not validly appear in an expression, the register is replaced by
245 something that won't match, (clobber (const_int 0)).
247 reg_last_set_invalid[i] is set non-zero when register I is being assigned
248 to and reg_last_set_table_tick[i] == label_tick. */
250 /* Record last value assigned to (hard or pseudo) register n. */
252 static rtx *reg_last_set_value;
254 /* Record the value of label_tick when the value for register n is placed in
255 reg_last_set_value[n]. */
257 static int *reg_last_set_label;
259 /* Record the value of label_tick when an expression involving register n
260 is placed in reg_last_set_value. */
262 static int *reg_last_set_table_tick;
264 /* Set non-zero if references to register n in expressions should not be
267 static char *reg_last_set_invalid;
269 /* Incremented for each label. */
271 static int label_tick;
273 /* Some registers that are set more than once and used in more than one
274 basic block are nevertheless always set in similar ways. For example,
275 a QImode register may be loaded from memory in two places on a machine
276 where byte loads zero extend.
278 We record in the following array what we know about the nonzero
279 bits of a register, specifically which bits are known to be zero.
281 If an entry is zero, it means that we don't know anything special. */
283 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
285 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
286 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
288 static enum machine_mode nonzero_bits_mode;
290 /* Nonzero if we know that a register has some leading bits that are always
291 equal to the sign bit. */
293 static char *reg_sign_bit_copies;
295 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
296 It is zero while computing them and after combine has completed. This
297 former test prevents propagating values based on previously set values,
298 which can be incorrect if a variable is modified in a loop. */
300 static int nonzero_sign_valid;
302 /* These arrays are maintained in parallel with reg_last_set_value
303 and are used to store the mode in which the register was last set,
304 the bits that were known to be zero when it was last set, and the
305 number of sign bits copies it was known to have when it was last set. */
307 static enum machine_mode *reg_last_set_mode;
308 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
309 static char *reg_last_set_sign_bit_copies;
311 /* Record one modification to rtl structure
312 to be undone by storing old_contents into *where.
313 is_int is 1 if the contents are an int. */
319 union {rtx r; int i;} old_contents;
320 union {rtx *r; int *i;} where;
323 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
324 num_undo says how many are currently recorded.
326 storage is nonzero if we must undo the allocation of new storage.
327 The value of storage is what to pass to obfree.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too.
332 previous_undos is the value of undobuf.undos when we started processing
333 this substitution. This will prevent gen_rtx_combine from re-used a piece
334 from the previous expression. Doing so can produce circular rtl
342 struct undo *previous_undos;
346 static struct undobuf undobuf;
348 /* Number of times the pseudo being substituted for
349 was found and replaced. */
351 static int n_occurrences;
353 static void do_SUBST PROTO((rtx *, rtx));
354 static void do_SUBST_INT PROTO((int *, int));
355 static void init_reg_last_arrays PROTO((void));
356 static void setup_incoming_promotions PROTO((void));
357 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx, void *));
358 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
359 static int sets_function_arg_p PROTO((rtx));
360 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
361 static rtx try_combine PROTO((rtx, rtx, rtx));
362 static void undo_all PROTO((void));
363 static rtx *find_split_point PROTO((rtx *, rtx));
364 static rtx subst PROTO((rtx, rtx, rtx, int, int));
365 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
366 static rtx simplify_if_then_else PROTO((rtx));
367 static rtx simplify_set PROTO((rtx));
368 static rtx simplify_logical PROTO((rtx, int));
369 static rtx expand_compound_operation PROTO((rtx));
370 static rtx expand_field_assignment PROTO((rtx));
371 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
373 static rtx extract_left_shift PROTO((rtx, int));
374 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
375 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
376 static rtx force_to_mode PROTO((rtx, enum machine_mode,
377 unsigned HOST_WIDE_INT, rtx, int));
378 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
379 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
380 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
381 static rtx make_field_assignment PROTO((rtx));
382 static rtx apply_distributive_law PROTO((rtx));
383 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
384 unsigned HOST_WIDE_INT));
385 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
386 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
387 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
388 enum rtx_code, HOST_WIDE_INT,
389 enum machine_mode, int *));
390 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
392 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
393 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
394 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
396 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
398 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
399 enum machine_mode, rtx));
400 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
401 static int reversible_comparison_p PROTO((rtx));
402 static void update_table_tick PROTO((rtx));
403 static void record_value_for_reg PROTO((rtx, rtx, rtx));
404 static void record_dead_and_set_regs_1 PROTO((rtx, rtx, void *));
405 static void record_dead_and_set_regs PROTO((rtx));
406 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
407 static rtx get_last_value PROTO((rtx));
408 static int use_crosses_set_p PROTO((rtx, int));
409 static void reg_dead_at_p_1 PROTO((rtx, rtx, void *));
410 static int reg_dead_at_p PROTO((rtx, rtx));
411 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
412 static int reg_bitfield_target_p PROTO((rtx, rtx));
413 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
414 static void distribute_links PROTO((rtx));
415 static void mark_used_regs_combine PROTO((rtx));
416 static int insn_cuid PROTO((rtx));
418 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
419 insn. The substitution can be undone by undo_all. If INTO is already
420 set to NEWVAL, do not record this change. Because computing NEWVAL might
421 also call SUBST, we have to compute it before we put anything into
425 do_SUBST(into, newval)
431 if (oldval == newval)
435 buf = undobuf.frees, undobuf.frees = buf->next;
437 buf = (struct undo *) xmalloc (sizeof (struct undo));
441 buf->old_contents.r = oldval;
444 buf->next = undobuf.undos, undobuf.undos = buf;
447 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
449 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
450 for the value of a HOST_WIDE_INT value (including CONST_INT) is
454 do_SUBST_INT(into, newval)
460 if (oldval == newval)
464 buf = undobuf.frees, undobuf.frees = buf->next;
466 buf = (struct undo *) xmalloc (sizeof (struct undo));
470 buf->old_contents.i = oldval;
473 buf->next = undobuf.undos, undobuf.undos = buf;
476 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
478 /* Main entry point for combiner. F is the first insn of the function.
479 NREGS is the first unused pseudo-reg number. */
482 combine_instructions (f, nregs)
486 register rtx insn, next;
491 register rtx links, nextlinks;
493 combine_attempts = 0;
496 combine_successes = 0;
497 undobuf.undos = undobuf.previous_undos = 0;
499 combine_max_regno = nregs;
502 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
503 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
505 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
506 bzero (reg_sign_bit_copies, nregs * sizeof (char));
508 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
509 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
510 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
511 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
512 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
513 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
515 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
516 reg_last_set_nonzero_bits
517 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
518 reg_last_set_sign_bit_copies
519 = (char *) alloca (nregs * sizeof (char));
521 init_reg_last_arrays ();
523 init_recog_no_volatile ();
525 /* Compute maximum uid value so uid_cuid can be allocated. */
527 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
528 if (INSN_UID (insn) > i)
531 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
534 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
536 /* Don't use reg_nonzero_bits when computing it. This can cause problems
537 when, for example, we have j <<= 1 in a loop. */
539 nonzero_sign_valid = 0;
541 /* Compute the mapping from uids to cuids.
542 Cuids are numbers assigned to insns, like uids,
543 except that cuids increase monotonically through the code.
545 Scan all SETs and see if we can deduce anything about what
546 bits are known to be zero for some registers and how many copies
547 of the sign bit are known to exist for those registers.
549 Also set any known values so that we can use it while searching
550 for what bits are known to be set. */
554 /* We need to initialize it here, because record_dead_and_set_regs may call
556 subst_prev_insn = NULL_RTX;
558 setup_incoming_promotions ();
560 refresh_blocks = sbitmap_alloc (n_basic_blocks);
561 sbitmap_zero (refresh_blocks);
564 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
566 uid_cuid[INSN_UID (insn)] = ++i;
570 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
572 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
574 record_dead_and_set_regs (insn);
577 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
578 if (REG_NOTE_KIND (links) == REG_INC)
579 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
584 if (GET_CODE (insn) == CODE_LABEL)
588 nonzero_sign_valid = 1;
590 /* Now scan all the insns in forward order. */
592 this_basic_block = -1;
596 init_reg_last_arrays ();
597 setup_incoming_promotions ();
599 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
603 /* If INSN starts a new basic block, update our basic block number. */
604 if (this_basic_block + 1 < n_basic_blocks
605 && BLOCK_HEAD (this_basic_block + 1) == insn)
608 if (GET_CODE (insn) == CODE_LABEL)
611 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
613 /* Try this insn with each insn it links back to. */
615 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
616 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
619 /* Try each sequence of three linked insns ending with this one. */
621 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
622 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
623 nextlinks = XEXP (nextlinks, 1))
624 if ((next = try_combine (insn, XEXP (links, 0),
625 XEXP (nextlinks, 0))) != 0)
629 /* Try to combine a jump insn that uses CC0
630 with a preceding insn that sets CC0, and maybe with its
631 logical predecessor as well.
632 This is how we make decrement-and-branch insns.
633 We need this special code because data flow connections
634 via CC0 do not get entered in LOG_LINKS. */
636 if (GET_CODE (insn) == JUMP_INSN
637 && (prev = prev_nonnote_insn (insn)) != 0
638 && GET_CODE (prev) == INSN
639 && sets_cc0_p (PATTERN (prev)))
641 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
644 for (nextlinks = LOG_LINKS (prev); nextlinks;
645 nextlinks = XEXP (nextlinks, 1))
646 if ((next = try_combine (insn, prev,
647 XEXP (nextlinks, 0))) != 0)
651 /* Do the same for an insn that explicitly references CC0. */
652 if (GET_CODE (insn) == INSN
653 && (prev = prev_nonnote_insn (insn)) != 0
654 && GET_CODE (prev) == INSN
655 && sets_cc0_p (PATTERN (prev))
656 && GET_CODE (PATTERN (insn)) == SET
657 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
659 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
662 for (nextlinks = LOG_LINKS (prev); nextlinks;
663 nextlinks = XEXP (nextlinks, 1))
664 if ((next = try_combine (insn, prev,
665 XEXP (nextlinks, 0))) != 0)
669 /* Finally, see if any of the insns that this insn links to
670 explicitly references CC0. If so, try this insn, that insn,
671 and its predecessor if it sets CC0. */
672 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
673 if (GET_CODE (XEXP (links, 0)) == INSN
674 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
675 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
676 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
677 && GET_CODE (prev) == INSN
678 && sets_cc0_p (PATTERN (prev))
679 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
683 /* Try combining an insn with two different insns whose results it
685 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
686 for (nextlinks = XEXP (links, 1); nextlinks;
687 nextlinks = XEXP (nextlinks, 1))
688 if ((next = try_combine (insn, XEXP (links, 0),
689 XEXP (nextlinks, 0))) != 0)
692 if (GET_CODE (insn) != NOTE)
693 record_dead_and_set_regs (insn);
702 compute_bb_for_insn (get_max_uid ());
703 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
706 sbitmap_free (refresh_blocks);
708 total_attempts += combine_attempts;
709 total_merges += combine_merges;
710 total_extras += combine_extras;
711 total_successes += combine_successes;
713 nonzero_sign_valid = 0;
715 /* Make recognizer allow volatile MEMs again. */
719 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
722 init_reg_last_arrays ()
724 int nregs = combine_max_regno;
726 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
727 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
728 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
729 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
730 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
731 bzero (reg_last_set_invalid, nregs * sizeof (char));
732 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
733 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
734 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
737 /* Set up any promoted values for incoming argument registers. */
740 setup_incoming_promotions ()
742 #ifdef PROMOTE_FUNCTION_ARGS
745 enum machine_mode mode;
747 rtx first = get_insns ();
749 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
750 if (FUNCTION_ARG_REGNO_P (regno)
751 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
754 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
757 gen_rtx_CLOBBER (mode, const0_rtx)));
762 /* Called via note_stores. If X is a pseudo that is narrower than
763 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
765 If we are setting only a portion of X and we can't figure out what
766 portion, assume all bits will be used since we don't know what will
769 Similarly, set how many bits of X are known to be copies of the sign bit
770 at all locations in the function. This is the smallest number implied
774 set_nonzero_bits_and_sign_copies (x, set, data)
777 void *data ATTRIBUTE_UNUSED;
781 if (GET_CODE (x) == REG
782 && REGNO (x) >= FIRST_PSEUDO_REGISTER
783 /* If this register is undefined at the start of the file, we can't
784 say what its contents were. */
785 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
786 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
788 if (set == 0 || GET_CODE (set) == CLOBBER)
790 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
791 reg_sign_bit_copies[REGNO (x)] = 1;
795 /* If this is a complex assignment, see if we can convert it into a
796 simple assignment. */
797 set = expand_field_assignment (set);
799 /* If this is a simple assignment, or we have a paradoxical SUBREG,
800 set what we know about X. */
802 if (SET_DEST (set) == x
803 || (GET_CODE (SET_DEST (set)) == SUBREG
804 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
805 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
806 && SUBREG_REG (SET_DEST (set)) == x))
808 rtx src = SET_SRC (set);
810 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
811 /* If X is narrower than a word and SRC is a non-negative
812 constant that would appear negative in the mode of X,
813 sign-extend it for use in reg_nonzero_bits because some
814 machines (maybe most) will actually do the sign-extension
815 and this is the conservative approach.
817 ??? For 2.5, try to tighten up the MD files in this regard
818 instead of this kludge. */
820 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
821 && GET_CODE (src) == CONST_INT
823 && 0 != (INTVAL (src)
825 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
826 src = GEN_INT (INTVAL (src)
827 | ((HOST_WIDE_INT) (-1)
828 << GET_MODE_BITSIZE (GET_MODE (x))));
831 reg_nonzero_bits[REGNO (x)]
832 |= nonzero_bits (src, nonzero_bits_mode);
833 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
834 if (reg_sign_bit_copies[REGNO (x)] == 0
835 || reg_sign_bit_copies[REGNO (x)] > num)
836 reg_sign_bit_copies[REGNO (x)] = num;
840 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
841 reg_sign_bit_copies[REGNO (x)] = 1;
846 /* See if INSN can be combined into I3. PRED and SUCC are optionally
847 insns that were previously combined into I3 or that will be combined
848 into the merger of INSN and I3.
850 Return 0 if the combination is not allowed for any reason.
852 If the combination is allowed, *PDEST will be set to the single
853 destination of INSN and *PSRC to the single source, and this function
857 can_combine_p (insn, i3, pred, succ, pdest, psrc)
860 rtx pred ATTRIBUTE_UNUSED;
865 rtx set = 0, src, dest;
870 int all_adjacent = (succ ? (next_active_insn (insn) == succ
871 && next_active_insn (succ) == i3)
872 : next_active_insn (insn) == i3);
874 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
875 or a PARALLEL consisting of such a SET and CLOBBERs.
877 If INSN has CLOBBER parallel parts, ignore them for our processing.
878 By definition, these happen during the execution of the insn. When it
879 is merged with another insn, all bets are off. If they are, in fact,
880 needed and aren't also supplied in I3, they may be added by
881 recog_for_combine. Otherwise, it won't match.
883 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
886 Get the source and destination of INSN. If more than one, can't
889 if (GET_CODE (PATTERN (insn)) == SET)
890 set = PATTERN (insn);
891 else if (GET_CODE (PATTERN (insn)) == PARALLEL
892 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
894 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
896 rtx elt = XVECEXP (PATTERN (insn), 0, i);
898 switch (GET_CODE (elt))
900 /* This is important to combine floating point insns
903 /* Combining an isolated USE doesn't make sense.
904 We depend here on combinable_i3_pat to reject them. */
905 /* The code below this loop only verifies that the inputs of
906 the SET in INSN do not change. We call reg_set_between_p
907 to verify that the REG in the USE does not change betweeen
909 If the USE in INSN was for a pseudo register, the matching
910 insn pattern will likely match any register; combining this
911 with any other USE would only be safe if we knew that the
912 used registers have identical values, or if there was
913 something to tell them apart, e.g. different modes. For
914 now, we forgo such compilcated tests and simply disallow
915 combining of USES of pseudo registers with any other USE. */
916 if (GET_CODE (XEXP (elt, 0)) == REG
917 && GET_CODE (PATTERN (i3)) == PARALLEL)
919 rtx i3pat = PATTERN (i3);
920 int i = XVECLEN (i3pat, 0) - 1;
921 int regno = REGNO (XEXP (elt, 0));
924 rtx i3elt = XVECEXP (i3pat, 0, i);
925 if (GET_CODE (i3elt) == USE
926 && GET_CODE (XEXP (i3elt, 0)) == REG
927 && (REGNO (XEXP (i3elt, 0)) == regno
928 ? reg_set_between_p (XEXP (elt, 0),
929 PREV_INSN (insn), i3)
930 : regno >= FIRST_PSEUDO_REGISTER))
937 /* We can ignore CLOBBERs. */
942 /* Ignore SETs whose result isn't used but not those that
943 have side-effects. */
944 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
945 && ! side_effects_p (elt))
948 /* If we have already found a SET, this is a second one and
949 so we cannot combine with this insn. */
957 /* Anything else means we can't combine. */
963 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
964 so don't do anything with it. */
965 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
974 set = expand_field_assignment (set);
975 src = SET_SRC (set), dest = SET_DEST (set);
977 /* Don't eliminate a store in the stack pointer. */
978 if (dest == stack_pointer_rtx
979 /* If we couldn't eliminate a field assignment, we can't combine. */
980 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
981 /* Don't combine with an insn that sets a register to itself if it has
982 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
983 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
984 /* Can't merge a function call. */
985 || GET_CODE (src) == CALL
986 /* Don't eliminate a function call argument. */
987 || (GET_CODE (i3) == CALL_INSN
988 && (find_reg_fusage (i3, USE, dest)
989 || (GET_CODE (dest) == REG
990 && REGNO (dest) < FIRST_PSEUDO_REGISTER
991 && global_regs[REGNO (dest)])))
992 /* Don't substitute into an incremented register. */
993 || FIND_REG_INC_NOTE (i3, dest)
994 || (succ && FIND_REG_INC_NOTE (succ, dest))
996 /* Don't combine the end of a libcall into anything. */
997 /* ??? This gives worse code, and appears to be unnecessary, since no
998 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
999 use REG_RETVAL notes for noconflict blocks, but other code here
1000 makes sure that those insns don't disappear. */
1001 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1003 /* Make sure that DEST is not used after SUCC but before I3. */
1004 || (succ && ! all_adjacent
1005 && reg_used_between_p (dest, succ, i3))
1006 /* Make sure that the value that is to be substituted for the register
1007 does not use any registers whose values alter in between. However,
1008 If the insns are adjacent, a use can't cross a set even though we
1009 think it might (this can happen for a sequence of insns each setting
1010 the same destination; reg_last_set of that register might point to
1011 a NOTE). If INSN has a REG_EQUIV note, the register is always
1012 equivalent to the memory so the substitution is valid even if there
1013 are intervening stores. Also, don't move a volatile asm or
1014 UNSPEC_VOLATILE across any other insns. */
1016 && (((GET_CODE (src) != MEM
1017 || ! find_reg_note (insn, REG_EQUIV, src))
1018 && use_crosses_set_p (src, INSN_CUID (insn)))
1019 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1020 || GET_CODE (src) == UNSPEC_VOLATILE))
1021 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1022 better register allocation by not doing the combine. */
1023 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1024 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1025 /* Don't combine across a CALL_INSN, because that would possibly
1026 change whether the life span of some REGs crosses calls or not,
1027 and it is a pain to update that information.
1028 Exception: if source is a constant, moving it later can't hurt.
1029 Accept that special case, because it helps -fforce-addr a lot. */
1030 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1033 /* DEST must either be a REG or CC0. */
1034 if (GET_CODE (dest) == REG)
1036 /* If register alignment is being enforced for multi-word items in all
1037 cases except for parameters, it is possible to have a register copy
1038 insn referencing a hard register that is not allowed to contain the
1039 mode being copied and which would not be valid as an operand of most
1040 insns. Eliminate this problem by not combining with such an insn.
1042 Also, on some machines we don't want to extend the life of a hard
1045 This is the same test done in can_combine except that we don't test
1046 if SRC is a CALL operation to permit a hard register with
1047 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1050 if (GET_CODE (src) == REG
1051 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1052 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1053 /* Don't extend the life of a hard register unless it is
1054 user variable (if we have few registers) or it can't
1055 fit into the desired register (meaning something special
1057 Also avoid substituting a return register into I3, because
1058 reload can't handle a conflict with constraints of other
1060 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1061 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1062 || (SMALL_REGISTER_CLASSES
1063 && ((! all_adjacent && ! REG_USERVAR_P (src))
1064 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1065 && ! REG_USERVAR_P (src))))))))
1068 else if (GET_CODE (dest) != CC0)
1071 /* Don't substitute for a register intended as a clobberable operand.
1072 Similarly, don't substitute an expression containing a register that
1073 will be clobbered in I3. */
1074 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1075 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1076 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1077 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1079 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1082 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1083 or not), reject, unless nothing volatile comes between it and I3 */
1085 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1087 /* Make sure succ doesn't contain a volatile reference. */
1088 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1091 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1092 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1093 && p != succ && volatile_refs_p (PATTERN (p)))
1097 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1098 to be an explicit register variable, and was chosen for a reason. */
1100 if (GET_CODE (src) == ASM_OPERANDS
1101 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1104 /* If there are any volatile insns between INSN and I3, reject, because
1105 they might affect machine state. */
1107 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1108 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1109 && p != succ && volatile_insn_p (PATTERN (p)))
1112 /* If INSN or I2 contains an autoincrement or autodecrement,
1113 make sure that register is not used between there and I3,
1114 and not already used in I3 either.
1115 Also insist that I3 not be a jump; if it were one
1116 and the incremented register were spilled, we would lose. */
1119 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1120 if (REG_NOTE_KIND (link) == REG_INC
1121 && (GET_CODE (i3) == JUMP_INSN
1122 || reg_used_between_p (XEXP (link, 0), insn, i3)
1123 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1128 /* Don't combine an insn that follows a CC0-setting insn.
1129 An insn that uses CC0 must not be separated from the one that sets it.
1130 We do, however, allow I2 to follow a CC0-setting insn if that insn
1131 is passed as I1; in that case it will be deleted also.
1132 We also allow combining in this case if all the insns are adjacent
1133 because that would leave the two CC0 insns adjacent as well.
1134 It would be more logical to test whether CC0 occurs inside I1 or I2,
1135 but that would be much slower, and this ought to be equivalent. */
1137 p = prev_nonnote_insn (insn);
1138 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1143 /* If we get here, we have passed all the tests and the combination is
1152 /* Check if PAT is an insn - or a part of it - used to set up an
1153 argument for a function in a hard register. */
1156 sets_function_arg_p (pat)
1162 switch (GET_CODE (pat))
1165 return sets_function_arg_p (PATTERN (pat));
1168 for (i = XVECLEN (pat, 0); --i >= 0;)
1169 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1175 inner_dest = SET_DEST (pat);
1176 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1177 || GET_CODE (inner_dest) == SUBREG
1178 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1179 inner_dest = XEXP (inner_dest, 0);
1181 return (GET_CODE (inner_dest) == REG
1182 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1183 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1192 /* LOC is the location within I3 that contains its pattern or the component
1193 of a PARALLEL of the pattern. We validate that it is valid for combining.
1195 One problem is if I3 modifies its output, as opposed to replacing it
1196 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1197 so would produce an insn that is not equivalent to the original insns.
1201 (set (reg:DI 101) (reg:DI 100))
1202 (set (subreg:SI (reg:DI 101) 0) <foo>)
1204 This is NOT equivalent to:
1206 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1207 (set (reg:DI 101) (reg:DI 100))])
1209 Not only does this modify 100 (in which case it might still be valid
1210 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1212 We can also run into a problem if I2 sets a register that I1
1213 uses and I1 gets directly substituted into I3 (not via I2). In that
1214 case, we would be getting the wrong value of I2DEST into I3, so we
1215 must reject the combination. This case occurs when I2 and I1 both
1216 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1217 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1218 of a SET must prevent combination from occurring.
1220 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1221 if the destination of a SET is a hard register that isn't a user
1224 Before doing the above check, we first try to expand a field assignment
1225 into a set of logical operations.
1227 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1228 we place a register that is both set and used within I3. If more than one
1229 such register is detected, we fail.
1231 Return 1 if the combination is valid, zero otherwise. */
1234 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1240 rtx *pi3dest_killed;
1244 if (GET_CODE (x) == SET)
1246 rtx set = expand_field_assignment (x);
1247 rtx dest = SET_DEST (set);
1248 rtx src = SET_SRC (set);
1249 rtx inner_dest = dest;
1252 rtx inner_src = src;
1257 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1258 || GET_CODE (inner_dest) == SUBREG
1259 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1260 inner_dest = XEXP (inner_dest, 0);
1262 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1265 while (GET_CODE (inner_src) == STRICT_LOW_PART
1266 || GET_CODE (inner_src) == SUBREG
1267 || GET_CODE (inner_src) == ZERO_EXTRACT)
1268 inner_src = XEXP (inner_src, 0);
1270 /* If it is better that two different modes keep two different pseudos,
1271 avoid combining them. This avoids producing the following pattern
1273 (set (subreg:SI (reg/v:QI 21) 0)
1274 (lshiftrt:SI (reg/v:SI 20)
1276 If that were made, reload could not handle the pair of
1277 reg 20/21, since it would try to get any GENERAL_REGS
1278 but some of them don't handle QImode. */
1280 if (rtx_equal_p (inner_src, i2dest)
1281 && GET_CODE (inner_dest) == REG
1282 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1286 /* Check for the case where I3 modifies its output, as
1288 if ((inner_dest != dest
1289 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1290 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1292 /* This is the same test done in can_combine_p except that we
1293 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1294 CALL operation. Moreover, we can't test all_adjacent; we don't
1295 have to, since this instruction will stay in place, thus we are
1296 not considering increasing the lifetime of INNER_DEST.
1298 Also, if this insn sets a function argument, combining it with
1299 something that might need a spill could clobber a previous
1300 function argument; the all_adjacent test in can_combine_p also
1301 checks this; here, we do a more specific test for this case. */
1303 || (GET_CODE (inner_dest) == REG
1304 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1305 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1306 GET_MODE (inner_dest))
1307 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1308 && ! REG_USERVAR_P (inner_dest)
1309 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1310 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1312 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1313 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1316 /* If DEST is used in I3, it is being killed in this insn,
1317 so record that for later.
1318 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1319 STACK_POINTER_REGNUM, since these are always considered to be
1320 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1321 if (pi3dest_killed && GET_CODE (dest) == REG
1322 && reg_referenced_p (dest, PATTERN (i3))
1323 && REGNO (dest) != FRAME_POINTER_REGNUM
1324 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1325 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1327 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1328 && (REGNO (dest) != ARG_POINTER_REGNUM
1329 || ! fixed_regs [REGNO (dest)])
1331 && REGNO (dest) != STACK_POINTER_REGNUM)
1333 if (*pi3dest_killed)
1336 *pi3dest_killed = dest;
1340 else if (GET_CODE (x) == PARALLEL)
1344 for (i = 0; i < XVECLEN (x, 0); i++)
1345 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1346 i1_not_in_src, pi3dest_killed))
1353 /* Try to combine the insns I1 and I2 into I3.
1354 Here I1 and I2 appear earlier than I3.
1355 I1 can be zero; then we combine just I2 into I3.
1357 It we are combining three insns and the resulting insn is not recognized,
1358 try splitting it into two insns. If that happens, I2 and I3 are retained
1359 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1362 Return 0 if the combination does not work. Then nothing is changed.
1363 If we did the combination, return the insn at which combine should
1367 try_combine (i3, i2, i1)
1368 register rtx i3, i2, i1;
1370 /* New patterns for I3 and I3, respectively. */
1371 rtx newpat, newi2pat = 0;
1372 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1373 int added_sets_1, added_sets_2;
1374 /* Total number of SETs to put into I3. */
1376 /* Nonzero is I2's body now appears in I3. */
1378 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1379 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1380 /* Contains I3 if the destination of I3 is used in its source, which means
1381 that the old life of I3 is being killed. If that usage is placed into
1382 I2 and not in I3, a REG_DEAD note must be made. */
1383 rtx i3dest_killed = 0;
1384 /* SET_DEST and SET_SRC of I2 and I1. */
1385 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1386 /* PATTERN (I2), or a copy of it in certain cases. */
1388 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1389 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1390 int i1_feeds_i3 = 0;
1391 /* Notes that must be added to REG_NOTES in I3 and I2. */
1392 rtx new_i3_notes, new_i2_notes;
1393 /* Notes that we substituted I3 into I2 instead of the normal case. */
1394 int i3_subst_into_i2 = 0;
1395 /* Notes that I1, I2 or I3 is a MULT operation. */
1403 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1404 This can occur when flow deletes an insn that it has merged into an
1405 auto-increment address. We also can't do anything if I3 has a
1406 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1409 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1410 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1411 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1413 /* ??? This gives worse code, and appears to be unnecessary, since no
1414 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1415 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1422 undobuf.undos = undobuf.previous_undos = 0;
1423 undobuf.other_insn = 0;
1425 /* Save the current high-water-mark so we can free storage if we didn't
1426 accept this combination. */
1427 undobuf.storage = (char *) oballoc (0);
1429 /* Reset the hard register usage information. */
1430 CLEAR_HARD_REG_SET (newpat_used_regs);
1432 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1433 code below, set I1 to be the earlier of the two insns. */
1434 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1435 temp = i1, i1 = i2, i2 = temp;
1437 added_links_insn = 0;
1439 /* First check for one important special-case that the code below will
1440 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1441 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1442 we may be able to replace that destination with the destination of I3.
1443 This occurs in the common code where we compute both a quotient and
1444 remainder into a structure, in which case we want to do the computation
1445 directly into the structure to avoid register-register copies.
1447 We make very conservative checks below and only try to handle the
1448 most common cases of this. For example, we only handle the case
1449 where I2 and I3 are adjacent to avoid making difficult register
1452 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1453 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1454 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1455 && (! SMALL_REGISTER_CLASSES
1456 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1457 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1458 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1459 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1460 && GET_CODE (PATTERN (i2)) == PARALLEL
1461 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1462 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1463 below would need to check what is inside (and reg_overlap_mentioned_p
1464 doesn't support those codes anyway). Don't allow those destinations;
1465 the resulting insn isn't likely to be recognized anyway. */
1466 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1467 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1468 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1469 SET_DEST (PATTERN (i3)))
1470 && next_real_insn (i2) == i3)
1472 rtx p2 = PATTERN (i2);
1474 /* Make sure that the destination of I3,
1475 which we are going to substitute into one output of I2,
1476 is not used within another output of I2. We must avoid making this:
1477 (parallel [(set (mem (reg 69)) ...)
1478 (set (reg 69) ...)])
1479 which is not well-defined as to order of actions.
1480 (Besides, reload can't handle output reloads for this.)
1482 The problem can also happen if the dest of I3 is a memory ref,
1483 if another dest in I2 is an indirect memory ref. */
1484 for (i = 0; i < XVECLEN (p2, 0); i++)
1485 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1486 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1487 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1488 SET_DEST (XVECEXP (p2, 0, i))))
1491 if (i == XVECLEN (p2, 0))
1492 for (i = 0; i < XVECLEN (p2, 0); i++)
1493 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1498 subst_low_cuid = INSN_CUID (i2);
1500 added_sets_2 = added_sets_1 = 0;
1501 i2dest = SET_SRC (PATTERN (i3));
1503 /* Replace the dest in I2 with our dest and make the resulting
1504 insn the new pattern for I3. Then skip to where we
1505 validate the pattern. Everything was set up above. */
1506 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1507 SET_DEST (PATTERN (i3)));
1510 i3_subst_into_i2 = 1;
1511 goto validate_replacement;
1516 /* If we have no I1 and I2 looks like:
1517 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1519 make up a dummy I1 that is
1522 (set (reg:CC X) (compare:CC Y (const_int 0)))
1524 (We can ignore any trailing CLOBBERs.)
1526 This undoes a previous combination and allows us to match a branch-and-
1529 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1530 && XVECLEN (PATTERN (i2), 0) >= 2
1531 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1532 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1534 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1535 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1536 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1537 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1538 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1539 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1541 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1542 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1547 /* We make I1 with the same INSN_UID as I2. This gives it
1548 the same INSN_CUID for value tracking. Our fake I1 will
1549 never appear in the insn stream so giving it the same INSN_UID
1550 as I2 will not cause a problem. */
1552 subst_prev_insn = i1
1553 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1554 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1557 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1558 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1559 SET_DEST (PATTERN (i1)));
1564 /* Verify that I2 and I1 are valid for combining. */
1565 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1566 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1572 /* Record whether I2DEST is used in I2SRC and similarly for the other
1573 cases. Knowing this will help in register status updating below. */
1574 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1575 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1576 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1578 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1580 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1582 /* Ensure that I3's pattern can be the destination of combines. */
1583 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1584 i1 && i2dest_in_i1src && i1_feeds_i3,
1591 /* See if any of the insns is a MULT operation. Unless one is, we will
1592 reject a combination that is, since it must be slower. Be conservative
1594 if (GET_CODE (i2src) == MULT
1595 || (i1 != 0 && GET_CODE (i1src) == MULT)
1596 || (GET_CODE (PATTERN (i3)) == SET
1597 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1600 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1601 We used to do this EXCEPT in one case: I3 has a post-inc in an
1602 output operand. However, that exception can give rise to insns like
1604 which is a famous insn on the PDP-11 where the value of r3 used as the
1605 source was model-dependent. Avoid this sort of thing. */
1608 if (!(GET_CODE (PATTERN (i3)) == SET
1609 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1610 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1611 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1612 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1613 /* It's not the exception. */
1616 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1617 if (REG_NOTE_KIND (link) == REG_INC
1618 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1620 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1627 /* See if the SETs in I1 or I2 need to be kept around in the merged
1628 instruction: whenever the value set there is still needed past I3.
1629 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1631 For the SET in I1, we have two cases: If I1 and I2 independently
1632 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1633 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1634 in I1 needs to be kept around unless I1DEST dies or is set in either
1635 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1636 I1DEST. If so, we know I1 feeds into I2. */
1638 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1641 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1642 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1644 /* If the set in I2 needs to be kept around, we must make a copy of
1645 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1646 PATTERN (I2), we are only substituting for the original I1DEST, not into
1647 an already-substituted copy. This also prevents making self-referential
1648 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1651 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1652 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1656 i2pat = copy_rtx (i2pat);
1660 /* Substitute in the latest insn for the regs set by the earlier ones. */
1662 maxreg = max_reg_num ();
1666 /* It is possible that the source of I2 or I1 may be performing an
1667 unneeded operation, such as a ZERO_EXTEND of something that is known
1668 to have the high part zero. Handle that case by letting subst look at
1669 the innermost one of them.
1671 Another way to do this would be to have a function that tries to
1672 simplify a single insn instead of merging two or more insns. We don't
1673 do this because of the potential of infinite loops and because
1674 of the potential extra memory required. However, doing it the way
1675 we are is a bit of a kludge and doesn't catch all cases.
1677 But only do this if -fexpensive-optimizations since it slows things down
1678 and doesn't usually win. */
1680 if (flag_expensive_optimizations)
1682 /* Pass pc_rtx so no substitutions are done, just simplifications.
1683 The cases that we are interested in here do not involve the few
1684 cases were is_replaced is checked. */
1687 subst_low_cuid = INSN_CUID (i1);
1688 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1692 subst_low_cuid = INSN_CUID (i2);
1693 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1696 undobuf.previous_undos = undobuf.undos;
1700 /* Many machines that don't use CC0 have insns that can both perform an
1701 arithmetic operation and set the condition code. These operations will
1702 be represented as a PARALLEL with the first element of the vector
1703 being a COMPARE of an arithmetic operation with the constant zero.
1704 The second element of the vector will set some pseudo to the result
1705 of the same arithmetic operation. If we simplify the COMPARE, we won't
1706 match such a pattern and so will generate an extra insn. Here we test
1707 for this case, where both the comparison and the operation result are
1708 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1709 I2SRC. Later we will make the PARALLEL that contains I2. */
1711 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1712 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1713 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1714 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1716 #ifdef EXTRA_CC_MODES
1718 enum machine_mode compare_mode;
1721 newpat = PATTERN (i3);
1722 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1726 #ifdef EXTRA_CC_MODES
1727 /* See if a COMPARE with the operand we substituted in should be done
1728 with the mode that is currently being used. If not, do the same
1729 processing we do in `subst' for a SET; namely, if the destination
1730 is used only once, try to replace it with a register of the proper
1731 mode and also replace the COMPARE. */
1732 if (undobuf.other_insn == 0
1733 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1734 &undobuf.other_insn))
1735 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1737 != GET_MODE (SET_DEST (newpat))))
1739 int regno = REGNO (SET_DEST (newpat));
1740 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1742 if (regno < FIRST_PSEUDO_REGISTER
1743 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1744 && ! REG_USERVAR_P (SET_DEST (newpat))))
1746 if (regno >= FIRST_PSEUDO_REGISTER)
1747 SUBST (regno_reg_rtx[regno], new_dest);
1749 SUBST (SET_DEST (newpat), new_dest);
1750 SUBST (XEXP (*cc_use, 0), new_dest);
1751 SUBST (SET_SRC (newpat),
1752 gen_rtx_combine (COMPARE, compare_mode,
1753 i2src, const0_rtx));
1756 undobuf.other_insn = 0;
1763 n_occurrences = 0; /* `subst' counts here */
1765 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1766 need to make a unique copy of I2SRC each time we substitute it
1767 to avoid self-referential rtl. */
1769 subst_low_cuid = INSN_CUID (i2);
1770 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1771 ! i1_feeds_i3 && i1dest_in_i1src);
1772 undobuf.previous_undos = undobuf.undos;
1774 /* Record whether i2's body now appears within i3's body. */
1775 i2_is_used = n_occurrences;
1778 /* If we already got a failure, don't try to do more. Otherwise,
1779 try to substitute in I1 if we have it. */
1781 if (i1 && GET_CODE (newpat) != CLOBBER)
1783 /* Before we can do this substitution, we must redo the test done
1784 above (see detailed comments there) that ensures that I1DEST
1785 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1787 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1795 subst_low_cuid = INSN_CUID (i1);
1796 newpat = subst (newpat, i1dest, i1src, 0, 0);
1797 undobuf.previous_undos = undobuf.undos;
1800 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1801 to count all the ways that I2SRC and I1SRC can be used. */
1802 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1803 && i2_is_used + added_sets_2 > 1)
1804 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1805 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1807 /* Fail if we tried to make a new register (we used to abort, but there's
1808 really no reason to). */
1809 || max_reg_num () != maxreg
1810 /* Fail if we couldn't do something and have a CLOBBER. */
1811 || GET_CODE (newpat) == CLOBBER
1812 /* Fail if this new pattern is a MULT and we didn't have one before
1813 at the outer level. */
1814 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1821 /* If the actions of the earlier insns must be kept
1822 in addition to substituting them into the latest one,
1823 we must make a new PARALLEL for the latest insn
1824 to hold additional the SETs. */
1826 if (added_sets_1 || added_sets_2)
1830 if (GET_CODE (newpat) == PARALLEL)
1832 rtvec old = XVEC (newpat, 0);
1833 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1834 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1835 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1836 sizeof (old->elem[0]) * old->num_elem);
1841 total_sets = 1 + added_sets_1 + added_sets_2;
1842 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1843 XVECEXP (newpat, 0, 0) = old;
1847 XVECEXP (newpat, 0, --total_sets)
1848 = (GET_CODE (PATTERN (i1)) == PARALLEL
1849 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1853 /* If there is no I1, use I2's body as is. We used to also not do
1854 the subst call below if I2 was substituted into I3,
1855 but that could lose a simplification. */
1857 XVECEXP (newpat, 0, --total_sets) = i2pat;
1859 /* See comment where i2pat is assigned. */
1860 XVECEXP (newpat, 0, --total_sets)
1861 = subst (i2pat, i1dest, i1src, 0, 0);
1865 /* We come here when we are replacing a destination in I2 with the
1866 destination of I3. */
1867 validate_replacement:
1869 /* Note which hard regs this insn has as inputs. */
1870 mark_used_regs_combine (newpat);
1872 /* Is the result of combination a valid instruction? */
1873 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1875 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1876 the second SET's destination is a register that is unused. In that case,
1877 we just need the first SET. This can occur when simplifying a divmod
1878 insn. We *must* test for this case here because the code below that
1879 splits two independent SETs doesn't handle this case correctly when it
1880 updates the register status. Also check the case where the first
1881 SET's destination is unused. That would not cause incorrect code, but
1882 does cause an unneeded insn to remain. */
1884 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1885 && XVECLEN (newpat, 0) == 2
1886 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1887 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1888 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1889 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1890 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1891 && asm_noperands (newpat) < 0)
1893 newpat = XVECEXP (newpat, 0, 0);
1894 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1897 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1898 && XVECLEN (newpat, 0) == 2
1899 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1900 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1901 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1902 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1903 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1904 && asm_noperands (newpat) < 0)
1906 newpat = XVECEXP (newpat, 0, 1);
1907 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1910 /* If we were combining three insns and the result is a simple SET
1911 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1912 insns. There are two ways to do this. It can be split using a
1913 machine-specific method (like when you have an addition of a large
1914 constant) or by combine in the function find_split_point. */
1916 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1917 && asm_noperands (newpat) < 0)
1919 rtx m_split, *split;
1920 rtx ni2dest = i2dest;
1922 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1923 use I2DEST as a scratch register will help. In the latter case,
1924 convert I2DEST to the mode of the source of NEWPAT if we can. */
1926 m_split = split_insns (newpat, i3);
1928 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1929 inputs of NEWPAT. */
1931 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1932 possible to try that as a scratch reg. This would require adding
1933 more code to make it work though. */
1935 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1937 /* If I2DEST is a hard register or the only use of a pseudo,
1938 we can change its mode. */
1939 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1940 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1941 && GET_CODE (i2dest) == REG
1942 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1943 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1944 && ! REG_USERVAR_P (i2dest))))
1945 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1948 m_split = split_insns (gen_rtx_PARALLEL
1950 gen_rtvec (2, newpat,
1951 gen_rtx_CLOBBER (VOIDmode,
1956 if (m_split && GET_CODE (m_split) == SEQUENCE
1957 && XVECLEN (m_split, 0) == 2
1958 && (next_real_insn (i2) == i3
1959 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1963 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1964 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1966 i3set = single_set (XVECEXP (m_split, 0, 1));
1967 i2set = single_set (XVECEXP (m_split, 0, 0));
1969 /* In case we changed the mode of I2DEST, replace it in the
1970 pseudo-register table here. We can't do it above in case this
1971 code doesn't get executed and we do a split the other way. */
1973 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1974 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1976 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1978 /* If I2 or I3 has multiple SETs, we won't know how to track
1979 register status, so don't use these insns. If I2's destination
1980 is used between I2 and I3, we also can't use these insns. */
1982 if (i2_code_number >= 0 && i2set && i3set
1983 && (next_real_insn (i2) == i3
1984 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1985 insn_code_number = recog_for_combine (&newi3pat, i3,
1987 if (insn_code_number >= 0)
1990 /* It is possible that both insns now set the destination of I3.
1991 If so, we must show an extra use of it. */
1993 if (insn_code_number >= 0)
1995 rtx new_i3_dest = SET_DEST (i3set);
1996 rtx new_i2_dest = SET_DEST (i2set);
1998 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1999 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2000 || GET_CODE (new_i3_dest) == SUBREG)
2001 new_i3_dest = XEXP (new_i3_dest, 0);
2003 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2004 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2005 || GET_CODE (new_i2_dest) == SUBREG)
2006 new_i2_dest = XEXP (new_i2_dest, 0);
2008 if (GET_CODE (new_i3_dest) == REG
2009 && GET_CODE (new_i2_dest) == REG
2010 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2011 REG_N_SETS (REGNO (new_i2_dest))++;
2015 /* If we can split it and use I2DEST, go ahead and see if that
2016 helps things be recognized. Verify that none of the registers
2017 are set between I2 and I3. */
2018 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2020 && GET_CODE (i2dest) == REG
2022 /* We need I2DEST in the proper mode. If it is a hard register
2023 or the only use of a pseudo, we can change its mode. */
2024 && (GET_MODE (*split) == GET_MODE (i2dest)
2025 || GET_MODE (*split) == VOIDmode
2026 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2027 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2028 && ! REG_USERVAR_P (i2dest)))
2029 && (next_real_insn (i2) == i3
2030 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2031 /* We can't overwrite I2DEST if its value is still used by
2033 && ! reg_referenced_p (i2dest, newpat))
2035 rtx newdest = i2dest;
2036 enum rtx_code split_code = GET_CODE (*split);
2037 enum machine_mode split_mode = GET_MODE (*split);
2039 /* Get NEWDEST as a register in the proper mode. We have already
2040 validated that we can do this. */
2041 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2043 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2045 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2046 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2049 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2050 an ASHIFT. This can occur if it was inside a PLUS and hence
2051 appeared to be a memory address. This is a kludge. */
2052 if (split_code == MULT
2053 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2054 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2056 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2057 XEXP (*split, 0), GEN_INT (i)));
2058 /* Update split_code because we may not have a multiply
2060 split_code = GET_CODE (*split);
2063 #ifdef INSN_SCHEDULING
2064 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2065 be written as a ZERO_EXTEND. */
2066 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2067 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2071 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2072 SUBST (*split, newdest);
2073 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2075 /* If the split point was a MULT and we didn't have one before,
2076 don't use one now. */
2077 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2078 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2082 /* Check for a case where we loaded from memory in a narrow mode and
2083 then sign extended it, but we need both registers. In that case,
2084 we have a PARALLEL with both loads from the same memory location.
2085 We can split this into a load from memory followed by a register-register
2086 copy. This saves at least one insn, more if register allocation can
2089 We cannot do this if the destination of the second assignment is
2090 a register that we have already assumed is zero-extended. Similarly
2091 for a SUBREG of such a register. */
2093 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2094 && GET_CODE (newpat) == PARALLEL
2095 && XVECLEN (newpat, 0) == 2
2096 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2097 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2098 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2099 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2100 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2101 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2103 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2104 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2105 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2106 (GET_CODE (temp) == REG
2107 && reg_nonzero_bits[REGNO (temp)] != 0
2108 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2109 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2110 && (reg_nonzero_bits[REGNO (temp)]
2111 != GET_MODE_MASK (word_mode))))
2112 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2113 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2114 (GET_CODE (temp) == REG
2115 && reg_nonzero_bits[REGNO (temp)] != 0
2116 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2117 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2118 && (reg_nonzero_bits[REGNO (temp)]
2119 != GET_MODE_MASK (word_mode)))))
2120 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2121 SET_SRC (XVECEXP (newpat, 0, 1)))
2122 && ! find_reg_note (i3, REG_UNUSED,
2123 SET_DEST (XVECEXP (newpat, 0, 0))))
2127 newi2pat = XVECEXP (newpat, 0, 0);
2128 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2129 newpat = XVECEXP (newpat, 0, 1);
2130 SUBST (SET_SRC (newpat),
2131 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2132 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2134 if (i2_code_number >= 0)
2135 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2137 if (insn_code_number >= 0)
2142 /* If we will be able to accept this, we have made a change to the
2143 destination of I3. This can invalidate a LOG_LINKS pointing
2144 to I3. No other part of combine.c makes such a transformation.
2146 The new I3 will have a destination that was previously the
2147 destination of I1 or I2 and which was used in i2 or I3. Call
2148 distribute_links to make a LOG_LINK from the next use of
2149 that destination. */
2151 PATTERN (i3) = newpat;
2152 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2154 /* I3 now uses what used to be its destination and which is
2155 now I2's destination. That means we need a LOG_LINK from
2156 I3 to I2. But we used to have one, so we still will.
2158 However, some later insn might be using I2's dest and have
2159 a LOG_LINK pointing at I3. We must remove this link.
2160 The simplest way to remove the link is to point it at I1,
2161 which we know will be a NOTE. */
2163 for (insn = NEXT_INSN (i3);
2164 insn && (this_basic_block == n_basic_blocks - 1
2165 || insn != BLOCK_HEAD (this_basic_block + 1));
2166 insn = NEXT_INSN (insn))
2168 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2169 && reg_referenced_p (ni2dest, PATTERN (insn)))
2171 for (link = LOG_LINKS (insn); link;
2172 link = XEXP (link, 1))
2173 if (XEXP (link, 0) == i3)
2174 XEXP (link, 0) = i1;
2182 /* Similarly, check for a case where we have a PARALLEL of two independent
2183 SETs but we started with three insns. In this case, we can do the sets
2184 as two separate insns. This case occurs when some SET allows two
2185 other insns to combine, but the destination of that SET is still live. */
2187 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2188 && GET_CODE (newpat) == PARALLEL
2189 && XVECLEN (newpat, 0) == 2
2190 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2191 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2192 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2193 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2194 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2195 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2196 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2198 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2199 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2200 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2201 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2202 XVECEXP (newpat, 0, 0))
2203 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2204 XVECEXP (newpat, 0, 1)))
2206 /* Normally, it doesn't matter which of the two is done first,
2207 but it does if one references cc0. In that case, it has to
2210 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2212 newi2pat = XVECEXP (newpat, 0, 0);
2213 newpat = XVECEXP (newpat, 0, 1);
2218 newi2pat = XVECEXP (newpat, 0, 1);
2219 newpat = XVECEXP (newpat, 0, 0);
2222 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2224 if (i2_code_number >= 0)
2225 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2228 /* If it still isn't recognized, fail and change things back the way they
2230 if ((insn_code_number < 0
2231 /* Is the result a reasonable ASM_OPERANDS? */
2232 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2238 /* If we had to change another insn, make sure it is valid also. */
2239 if (undobuf.other_insn)
2241 rtx other_pat = PATTERN (undobuf.other_insn);
2242 rtx new_other_notes;
2245 CLEAR_HARD_REG_SET (newpat_used_regs);
2247 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2250 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2256 PATTERN (undobuf.other_insn) = other_pat;
2258 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2259 are still valid. Then add any non-duplicate notes added by
2260 recog_for_combine. */
2261 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2263 next = XEXP (note, 1);
2265 if (REG_NOTE_KIND (note) == REG_UNUSED
2266 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2268 if (GET_CODE (XEXP (note, 0)) == REG)
2269 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2271 remove_note (undobuf.other_insn, note);
2275 for (note = new_other_notes; note; note = XEXP (note, 1))
2276 if (GET_CODE (XEXP (note, 0)) == REG)
2277 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2279 distribute_notes (new_other_notes, undobuf.other_insn,
2280 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2283 /* We now know that we can do this combination. Merge the insns and
2284 update the status of registers and LOG_LINKS. */
2287 rtx i3notes, i2notes, i1notes = 0;
2288 rtx i3links, i2links, i1links = 0;
2291 /* Compute which registers we expect to eliminate. newi2pat may be setting
2292 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2293 same as i3dest, in which case newi2pat may be setting i1dest. */
2294 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2295 || i2dest_in_i2src || i2dest_in_i1src
2297 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2298 || (newi2pat && reg_set_p (i1dest, newi2pat))
2301 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2303 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2304 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2306 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2308 /* Ensure that we do not have something that should not be shared but
2309 occurs multiple times in the new insns. Check this by first
2310 resetting all the `used' flags and then copying anything is shared. */
2312 reset_used_flags (i3notes);
2313 reset_used_flags (i2notes);
2314 reset_used_flags (i1notes);
2315 reset_used_flags (newpat);
2316 reset_used_flags (newi2pat);
2317 if (undobuf.other_insn)
2318 reset_used_flags (PATTERN (undobuf.other_insn));
2320 i3notes = copy_rtx_if_shared (i3notes);
2321 i2notes = copy_rtx_if_shared (i2notes);
2322 i1notes = copy_rtx_if_shared (i1notes);
2323 newpat = copy_rtx_if_shared (newpat);
2324 newi2pat = copy_rtx_if_shared (newi2pat);
2325 if (undobuf.other_insn)
2326 reset_used_flags (PATTERN (undobuf.other_insn));
2328 INSN_CODE (i3) = insn_code_number;
2329 PATTERN (i3) = newpat;
2330 if (undobuf.other_insn)
2331 INSN_CODE (undobuf.other_insn) = other_code_number;
2333 /* We had one special case above where I2 had more than one set and
2334 we replaced a destination of one of those sets with the destination
2335 of I3. In that case, we have to update LOG_LINKS of insns later
2336 in this basic block. Note that this (expensive) case is rare.
2338 Also, in this case, we must pretend that all REG_NOTEs for I2
2339 actually came from I3, so that REG_UNUSED notes from I2 will be
2340 properly handled. */
2342 if (i3_subst_into_i2)
2344 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2345 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2346 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2347 && ! find_reg_note (i2, REG_UNUSED,
2348 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2349 for (temp = NEXT_INSN (i2);
2350 temp && (this_basic_block == n_basic_blocks - 1
2351 || BLOCK_HEAD (this_basic_block) != temp);
2352 temp = NEXT_INSN (temp))
2353 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2354 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2355 if (XEXP (link, 0) == i2)
2356 XEXP (link, 0) = i3;
2361 while (XEXP (link, 1))
2362 link = XEXP (link, 1);
2363 XEXP (link, 1) = i2notes;
2377 INSN_CODE (i2) = i2_code_number;
2378 PATTERN (i2) = newi2pat;
2382 PUT_CODE (i2, NOTE);
2383 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2384 NOTE_SOURCE_FILE (i2) = 0;
2391 PUT_CODE (i1, NOTE);
2392 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2393 NOTE_SOURCE_FILE (i1) = 0;
2396 /* Get death notes for everything that is now used in either I3 or
2397 I2 and used to die in a previous insn. If we built two new
2398 patterns, move from I1 to I2 then I2 to I3 so that we get the
2399 proper movement on registers that I2 modifies. */
2403 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2404 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2407 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2410 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2412 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2415 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2418 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2421 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2424 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2425 know these are REG_UNUSED and want them to go to the desired insn,
2426 so we always pass it as i3. We have not counted the notes in
2427 reg_n_deaths yet, so we need to do so now. */
2429 if (newi2pat && new_i2_notes)
2431 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2432 if (GET_CODE (XEXP (temp, 0)) == REG)
2433 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2435 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2440 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2441 if (GET_CODE (XEXP (temp, 0)) == REG)
2442 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2444 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2447 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2448 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2449 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2450 in that case, it might delete I2. Similarly for I2 and I1.
2451 Show an additional death due to the REG_DEAD note we make here. If
2452 we discard it in distribute_notes, we will decrement it again. */
2456 if (GET_CODE (i3dest_killed) == REG)
2457 REG_N_DEATHS (REGNO (i3dest_killed))++;
2459 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2460 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2462 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2464 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2466 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2470 if (i2dest_in_i2src)
2472 if (GET_CODE (i2dest) == REG)
2473 REG_N_DEATHS (REGNO (i2dest))++;
2475 if (newi2pat && reg_set_p (i2dest, newi2pat))
2476 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2477 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2479 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2480 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2481 NULL_RTX, NULL_RTX);
2484 if (i1dest_in_i1src)
2486 if (GET_CODE (i1dest) == REG)
2487 REG_N_DEATHS (REGNO (i1dest))++;
2489 if (newi2pat && reg_set_p (i1dest, newi2pat))
2490 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2491 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2493 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2494 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2495 NULL_RTX, NULL_RTX);
2498 distribute_links (i3links);
2499 distribute_links (i2links);
2500 distribute_links (i1links);
2502 if (GET_CODE (i2dest) == REG)
2505 rtx i2_insn = 0, i2_val = 0, set;
2507 /* The insn that used to set this register doesn't exist, and
2508 this life of the register may not exist either. See if one of
2509 I3's links points to an insn that sets I2DEST. If it does,
2510 that is now the last known value for I2DEST. If we don't update
2511 this and I2 set the register to a value that depended on its old
2512 contents, we will get confused. If this insn is used, thing
2513 will be set correctly in combine_instructions. */
2515 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2516 if ((set = single_set (XEXP (link, 0))) != 0
2517 && rtx_equal_p (i2dest, SET_DEST (set)))
2518 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2520 record_value_for_reg (i2dest, i2_insn, i2_val);
2522 /* If the reg formerly set in I2 died only once and that was in I3,
2523 zero its use count so it won't make `reload' do any work. */
2525 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2526 && ! i2dest_in_i2src)
2528 regno = REGNO (i2dest);
2529 REG_N_SETS (regno)--;
2530 if (REG_N_SETS (regno) == 0
2531 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2533 REG_N_REFS (regno) = 0;
2537 if (i1 && GET_CODE (i1dest) == REG)
2540 rtx i1_insn = 0, i1_val = 0, set;
2542 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2543 if ((set = single_set (XEXP (link, 0))) != 0
2544 && rtx_equal_p (i1dest, SET_DEST (set)))
2545 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2547 record_value_for_reg (i1dest, i1_insn, i1_val);
2549 regno = REGNO (i1dest);
2550 if (! added_sets_1 && ! i1dest_in_i1src)
2552 REG_N_SETS (regno)--;
2553 if (REG_N_SETS (regno) == 0
2554 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2556 REG_N_REFS (regno) = 0;
2560 /* Update reg_nonzero_bits et al for any changes that may have been made
2563 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2565 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2567 /* If I3 is now an unconditional jump, ensure that it has a
2568 BARRIER following it since it may have initially been a
2569 conditional jump. It may also be the last nonnote insn. */
2571 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2572 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2573 || GET_CODE (temp) != BARRIER))
2574 emit_barrier_after (i3);
2577 combine_successes++;
2579 /* Clear this here, so that subsequent get_last_value calls are not
2581 subst_prev_insn = NULL_RTX;
2583 if (added_links_insn
2584 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2585 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2586 return added_links_insn;
2588 return newi2pat ? i2 : i3;
2591 /* Undo all the modifications recorded in undobuf. */
2596 struct undo *undo, *next;
2598 for (undo = undobuf.undos; undo; undo = next)
2602 *undo->where.i = undo->old_contents.i;
2604 *undo->where.r = undo->old_contents.r;
2606 undo->next = undobuf.frees;
2607 undobuf.frees = undo;
2610 obfree (undobuf.storage);
2611 undobuf.undos = undobuf.previous_undos = 0;
2613 /* Clear this here, so that subsequent get_last_value calls are not
2615 subst_prev_insn = NULL_RTX;
2618 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2619 where we have an arithmetic expression and return that point. LOC will
2622 try_combine will call this function to see if an insn can be split into
2626 find_split_point (loc, insn)
2631 enum rtx_code code = GET_CODE (x);
2633 int len = 0, pos = 0, unsignedp = 0;
2634 rtx inner = NULL_RTX;
2636 /* First special-case some codes. */
2640 #ifdef INSN_SCHEDULING
2641 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2643 if (GET_CODE (SUBREG_REG (x)) == MEM)
2646 return find_split_point (&SUBREG_REG (x), insn);
2650 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2651 using LO_SUM and HIGH. */
2652 if (GET_CODE (XEXP (x, 0)) == CONST
2653 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2656 gen_rtx_combine (LO_SUM, Pmode,
2657 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2659 return &XEXP (XEXP (x, 0), 0);
2663 /* If we have a PLUS whose second operand is a constant and the
2664 address is not valid, perhaps will can split it up using
2665 the machine-specific way to split large constants. We use
2666 the first pseudo-reg (one of the virtual regs) as a placeholder;
2667 it will not remain in the result. */
2668 if (GET_CODE (XEXP (x, 0)) == PLUS
2669 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2670 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2672 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2673 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2676 /* This should have produced two insns, each of which sets our
2677 placeholder. If the source of the second is a valid address,
2678 we can make put both sources together and make a split point
2681 if (seq && XVECLEN (seq, 0) == 2
2682 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2683 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2684 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2685 && ! reg_mentioned_p (reg,
2686 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2687 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2688 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2689 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2690 && memory_address_p (GET_MODE (x),
2691 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2693 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2694 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2696 /* Replace the placeholder in SRC2 with SRC1. If we can
2697 find where in SRC2 it was placed, that can become our
2698 split point and we can replace this address with SRC2.
2699 Just try two obvious places. */
2701 src2 = replace_rtx (src2, reg, src1);
2703 if (XEXP (src2, 0) == src1)
2704 split = &XEXP (src2, 0);
2705 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2706 && XEXP (XEXP (src2, 0), 0) == src1)
2707 split = &XEXP (XEXP (src2, 0), 0);
2711 SUBST (XEXP (x, 0), src2);
2716 /* If that didn't work, perhaps the first operand is complex and
2717 needs to be computed separately, so make a split point there.
2718 This will occur on machines that just support REG + CONST
2719 and have a constant moved through some previous computation. */
2721 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2722 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2723 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2725 return &XEXP (XEXP (x, 0), 0);
2731 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2732 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2733 we need to put the operand into a register. So split at that
2736 if (SET_DEST (x) == cc0_rtx
2737 && GET_CODE (SET_SRC (x)) != COMPARE
2738 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2739 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2740 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2741 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2742 return &SET_SRC (x);
2745 /* See if we can split SET_SRC as it stands. */
2746 split = find_split_point (&SET_SRC (x), insn);
2747 if (split && split != &SET_SRC (x))
2750 /* See if we can split SET_DEST as it stands. */
2751 split = find_split_point (&SET_DEST (x), insn);
2752 if (split && split != &SET_DEST (x))
2755 /* See if this is a bitfield assignment with everything constant. If
2756 so, this is an IOR of an AND, so split it into that. */
2757 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2758 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2759 <= HOST_BITS_PER_WIDE_INT)
2760 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2761 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2762 && GET_CODE (SET_SRC (x)) == CONST_INT
2763 && ((INTVAL (XEXP (SET_DEST (x), 1))
2764 + INTVAL (XEXP (SET_DEST (x), 2)))
2765 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2766 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2768 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2769 int len = INTVAL (XEXP (SET_DEST (x), 1));
2770 int src = INTVAL (SET_SRC (x));
2771 rtx dest = XEXP (SET_DEST (x), 0);
2772 enum machine_mode mode = GET_MODE (dest);
2773 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2775 if (BITS_BIG_ENDIAN)
2776 pos = GET_MODE_BITSIZE (mode) - len - pos;
2778 if ((unsigned HOST_WIDE_INT) src == mask)
2780 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2783 gen_binary (IOR, mode,
2784 gen_binary (AND, mode, dest,
2785 GEN_INT (~ (mask << pos)
2786 & GET_MODE_MASK (mode))),
2787 GEN_INT (src << pos)));
2789 SUBST (SET_DEST (x), dest);
2791 split = find_split_point (&SET_SRC (x), insn);
2792 if (split && split != &SET_SRC (x))
2796 /* Otherwise, see if this is an operation that we can split into two.
2797 If so, try to split that. */
2798 code = GET_CODE (SET_SRC (x));
2803 /* If we are AND'ing with a large constant that is only a single
2804 bit and the result is only being used in a context where we
2805 need to know if it is zero or non-zero, replace it with a bit
2806 extraction. This will avoid the large constant, which might
2807 have taken more than one insn to make. If the constant were
2808 not a valid argument to the AND but took only one insn to make,
2809 this is no worse, but if it took more than one insn, it will
2812 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2813 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2814 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2815 && GET_CODE (SET_DEST (x)) == REG
2816 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2817 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2818 && XEXP (*split, 0) == SET_DEST (x)
2819 && XEXP (*split, 1) == const0_rtx)
2821 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2822 XEXP (SET_SRC (x), 0),
2823 pos, NULL_RTX, 1, 1, 0, 0);
2824 if (extraction != 0)
2826 SUBST (SET_SRC (x), extraction);
2827 return find_split_point (loc, insn);
2833 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2834 is known to be on, this can be converted into a NEG of a shift. */
2835 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2836 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2837 && 1 <= (pos = exact_log2
2838 (nonzero_bits (XEXP (SET_SRC (x), 0),
2839 GET_MODE (XEXP (SET_SRC (x), 0))))))
2841 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2844 gen_rtx_combine (NEG, mode,
2845 gen_rtx_combine (LSHIFTRT, mode,
2846 XEXP (SET_SRC (x), 0),
2849 split = find_split_point (&SET_SRC (x), insn);
2850 if (split && split != &SET_SRC (x))
2856 inner = XEXP (SET_SRC (x), 0);
2858 /* We can't optimize if either mode is a partial integer
2859 mode as we don't know how many bits are significant
2861 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2862 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2866 len = GET_MODE_BITSIZE (GET_MODE (inner));
2872 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2873 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2875 inner = XEXP (SET_SRC (x), 0);
2876 len = INTVAL (XEXP (SET_SRC (x), 1));
2877 pos = INTVAL (XEXP (SET_SRC (x), 2));
2879 if (BITS_BIG_ENDIAN)
2880 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2881 unsignedp = (code == ZERO_EXTRACT);
2889 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2891 enum machine_mode mode = GET_MODE (SET_SRC (x));
2893 /* For unsigned, we have a choice of a shift followed by an
2894 AND or two shifts. Use two shifts for field sizes where the
2895 constant might be too large. We assume here that we can
2896 always at least get 8-bit constants in an AND insn, which is
2897 true for every current RISC. */
2899 if (unsignedp && len <= 8)
2904 gen_rtx_combine (LSHIFTRT, mode,
2905 gen_lowpart_for_combine (mode, inner),
2907 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2909 split = find_split_point (&SET_SRC (x), insn);
2910 if (split && split != &SET_SRC (x))
2917 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2918 gen_rtx_combine (ASHIFT, mode,
2919 gen_lowpart_for_combine (mode, inner),
2920 GEN_INT (GET_MODE_BITSIZE (mode)
2922 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2924 split = find_split_point (&SET_SRC (x), insn);
2925 if (split && split != &SET_SRC (x))
2930 /* See if this is a simple operation with a constant as the second
2931 operand. It might be that this constant is out of range and hence
2932 could be used as a split point. */
2933 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2934 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2935 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2936 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2937 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2938 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2939 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2941 return &XEXP (SET_SRC (x), 1);
2943 /* Finally, see if this is a simple operation with its first operand
2944 not in a register. The operation might require this operand in a
2945 register, so return it as a split point. We can always do this
2946 because if the first operand were another operation, we would have
2947 already found it as a split point. */
2948 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2949 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2950 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2951 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2952 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2953 return &XEXP (SET_SRC (x), 0);
2959 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2960 it is better to write this as (not (ior A B)) so we can split it.
2961 Similarly for IOR. */
2962 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2965 gen_rtx_combine (NOT, GET_MODE (x),
2966 gen_rtx_combine (code == IOR ? AND : IOR,
2968 XEXP (XEXP (x, 0), 0),
2969 XEXP (XEXP (x, 1), 0))));
2970 return find_split_point (loc, insn);
2973 /* Many RISC machines have a large set of logical insns. If the
2974 second operand is a NOT, put it first so we will try to split the
2975 other operand first. */
2976 if (GET_CODE (XEXP (x, 1)) == NOT)
2978 rtx tem = XEXP (x, 0);
2979 SUBST (XEXP (x, 0), XEXP (x, 1));
2980 SUBST (XEXP (x, 1), tem);
2988 /* Otherwise, select our actions depending on our rtx class. */
2989 switch (GET_RTX_CLASS (code))
2991 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2993 split = find_split_point (&XEXP (x, 2), insn);
2996 /* ... fall through ... */
3000 split = find_split_point (&XEXP (x, 1), insn);
3003 /* ... fall through ... */
3005 /* Some machines have (and (shift ...) ...) insns. If X is not
3006 an AND, but XEXP (X, 0) is, use it as our split point. */
3007 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3008 return &XEXP (x, 0);
3010 split = find_split_point (&XEXP (x, 0), insn);
3016 /* Otherwise, we don't have a split point. */
3020 /* Throughout X, replace FROM with TO, and return the result.
3021 The result is TO if X is FROM;
3022 otherwise the result is X, but its contents may have been modified.
3023 If they were modified, a record was made in undobuf so that
3024 undo_all will (among other things) return X to its original state.
3026 If the number of changes necessary is too much to record to undo,
3027 the excess changes are not made, so the result is invalid.
3028 The changes already made can still be undone.
3029 undobuf.num_undo is incremented for such changes, so by testing that
3030 the caller can tell whether the result is valid.
3032 `n_occurrences' is incremented each time FROM is replaced.
3034 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3036 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3037 by copying if `n_occurrences' is non-zero. */
3040 subst (x, from, to, in_dest, unique_copy)
3041 register rtx x, from, to;
3045 register enum rtx_code code = GET_CODE (x);
3046 enum machine_mode op0_mode = VOIDmode;
3047 register const char *fmt;
3048 register int len, i;
3051 /* Two expressions are equal if they are identical copies of a shared
3052 RTX or if they are both registers with the same register number
3055 #define COMBINE_RTX_EQUAL_P(X,Y) \
3057 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3058 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3060 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3063 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3066 /* If X and FROM are the same register but different modes, they will
3067 not have been seen as equal above. However, flow.c will make a
3068 LOG_LINKS entry for that case. If we do nothing, we will try to
3069 rerecognize our original insn and, when it succeeds, we will
3070 delete the feeding insn, which is incorrect.
3072 So force this insn not to match in this (rare) case. */
3073 if (! in_dest && code == REG && GET_CODE (from) == REG
3074 && REGNO (x) == REGNO (from))
3075 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3077 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3078 of which may contain things that can be combined. */
3079 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3082 /* It is possible to have a subexpression appear twice in the insn.
3083 Suppose that FROM is a register that appears within TO.
3084 Then, after that subexpression has been scanned once by `subst',
3085 the second time it is scanned, TO may be found. If we were
3086 to scan TO here, we would find FROM within it and create a
3087 self-referent rtl structure which is completely wrong. */
3088 if (COMBINE_RTX_EQUAL_P (x, to))
3091 /* Parallel asm_operands need special attention because all of the
3092 inputs are shared across the arms. Furthermore, unsharing the
3093 rtl results in recognition failures. Failure to handle this case
3094 specially can result in circular rtl.
3096 Solve this by doing a normal pass across the first entry of the
3097 parallel, and only processing the SET_DESTs of the subsequent
3100 if (code == PARALLEL
3101 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3102 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3104 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3106 /* If this substitution failed, this whole thing fails. */
3107 if (GET_CODE (new) == CLOBBER
3108 && XEXP (new, 0) == const0_rtx)
3111 SUBST (XVECEXP (x, 0, 0), new);
3113 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3115 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3117 if (GET_CODE (dest) != REG
3118 && GET_CODE (dest) != CC0
3119 && GET_CODE (dest) != PC)
3121 new = subst (dest, from, to, 0, unique_copy);
3123 /* If this substitution failed, this whole thing fails. */
3124 if (GET_CODE (new) == CLOBBER
3125 && XEXP (new, 0) == const0_rtx)
3128 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3134 len = GET_RTX_LENGTH (code);
3135 fmt = GET_RTX_FORMAT (code);
3137 /* We don't need to process a SET_DEST that is a register, CC0,
3138 or PC, so set up to skip this common case. All other cases
3139 where we want to suppress replacing something inside a
3140 SET_SRC are handled via the IN_DEST operand. */
3142 && (GET_CODE (SET_DEST (x)) == REG
3143 || GET_CODE (SET_DEST (x)) == CC0
3144 || GET_CODE (SET_DEST (x)) == PC))
3147 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3150 op0_mode = GET_MODE (XEXP (x, 0));
3152 for (i = 0; i < len; i++)
3157 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3159 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3161 new = (unique_copy && n_occurrences
3162 ? copy_rtx (to) : to);
3167 new = subst (XVECEXP (x, i, j), from, to, 0,
3170 /* If this substitution failed, this whole thing
3172 if (GET_CODE (new) == CLOBBER
3173 && XEXP (new, 0) == const0_rtx)
3177 SUBST (XVECEXP (x, i, j), new);
3180 else if (fmt[i] == 'e')
3182 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3184 /* In general, don't install a subreg involving two
3185 modes not tieable. It can worsen register
3186 allocation, and can even make invalid reload
3187 insns, since the reg inside may need to be copied
3188 from in the outside mode, and that may be invalid
3189 if it is an fp reg copied in integer mode.
3191 We allow two exceptions to this: It is valid if
3192 it is inside another SUBREG and the mode of that
3193 SUBREG and the mode of the inside of TO is
3194 tieable and it is valid if X is a SET that copies
3197 if (GET_CODE (to) == SUBREG
3198 && ! MODES_TIEABLE_P (GET_MODE (to),
3199 GET_MODE (SUBREG_REG (to)))
3200 && ! (code == SUBREG
3201 && MODES_TIEABLE_P (GET_MODE (x),
3202 GET_MODE (SUBREG_REG (to))))
3204 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3207 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3209 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3213 /* If we are in a SET_DEST, suppress most cases unless we
3214 have gone inside a MEM, in which case we want to
3215 simplify the address. We assume here that things that
3216 are actually part of the destination have their inner
3217 parts in the first expression. This is true for SUBREG,
3218 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3219 things aside from REG and MEM that should appear in a
3221 new = subst (XEXP (x, i), from, to,
3223 && (code == SUBREG || code == STRICT_LOW_PART
3224 || code == ZERO_EXTRACT))
3226 && i == 0), unique_copy);
3228 /* If we found that we will have to reject this combination,
3229 indicate that by returning the CLOBBER ourselves, rather than
3230 an expression containing it. This will speed things up as
3231 well as prevent accidents where two CLOBBERs are considered
3232 to be equal, thus producing an incorrect simplification. */
3234 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3237 SUBST (XEXP (x, i), new);
3242 /* Try to simplify X. If the simplification changed the code, it is likely
3243 that further simplification will help, so loop, but limit the number
3244 of repetitions that will be performed. */
3246 for (i = 0; i < 4; i++)
3248 /* If X is sufficiently simple, don't bother trying to do anything
3250 if (code != CONST_INT && code != REG && code != CLOBBER)
3251 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3253 if (GET_CODE (x) == code)
3256 code = GET_CODE (x);
3258 /* We no longer know the original mode of operand 0 since we
3259 have changed the form of X) */
3260 op0_mode = VOIDmode;
3266 /* Simplify X, a piece of RTL. We just operate on the expression at the
3267 outer level; call `subst' to simplify recursively. Return the new
3270 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3271 will be the iteration even if an expression with a code different from
3272 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3275 simplify_rtx (x, op0_mode, last, in_dest)
3277 enum machine_mode op0_mode;
3281 enum rtx_code code = GET_CODE (x);
3282 enum machine_mode mode = GET_MODE (x);
3286 /* If this is a commutative operation, put a constant last and a complex
3287 expression first. We don't need to do this for comparisons here. */
3288 if (GET_RTX_CLASS (code) == 'c'
3289 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3290 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3291 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3292 || (GET_CODE (XEXP (x, 0)) == SUBREG
3293 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3294 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3297 SUBST (XEXP (x, 0), XEXP (x, 1));
3298 SUBST (XEXP (x, 1), temp);
3301 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3302 sign extension of a PLUS with a constant, reverse the order of the sign
3303 extension and the addition. Note that this not the same as the original
3304 code, but overflow is undefined for signed values. Also note that the
3305 PLUS will have been partially moved "inside" the sign-extension, so that
3306 the first operand of X will really look like:
3307 (ashiftrt (plus (ashift A C4) C5) C4).
3309 (plus (ashiftrt (ashift A C4) C2) C4)
3310 and replace the first operand of X with that expression. Later parts
3311 of this function may simplify the expression further.
3313 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3314 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3315 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3317 We do this to simplify address expressions. */
3319 if ((code == PLUS || code == MINUS || code == MULT)
3320 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3321 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3322 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3323 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3324 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3325 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3326 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3327 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3328 XEXP (XEXP (XEXP (x, 0), 0), 1),
3329 XEXP (XEXP (x, 0), 1))) != 0)
3332 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3333 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3334 INTVAL (XEXP (XEXP (x, 0), 1)));
3336 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3337 INTVAL (XEXP (XEXP (x, 0), 1)));
3339 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3342 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3343 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3344 things. Check for cases where both arms are testing the same
3347 Don't do anything if all operands are very simple. */
3349 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3350 || GET_RTX_CLASS (code) == '<')
3351 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3352 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3353 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3355 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3356 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3357 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3359 || (GET_RTX_CLASS (code) == '1'
3360 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3361 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3362 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3365 rtx cond, true, false;
3367 cond = if_then_else_cond (x, &true, &false);
3369 /* If everything is a comparison, what we have is highly unlikely
3370 to be simpler, so don't use it. */
3371 && ! (GET_RTX_CLASS (code) == '<'
3372 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3373 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3375 rtx cop1 = const0_rtx;
3376 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3378 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3381 /* Simplify the alternative arms; this may collapse the true and
3382 false arms to store-flag values. */
3383 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3384 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3386 /* Restarting if we generate a store-flag expression will cause
3387 us to loop. Just drop through in this case. */
3389 /* If the result values are STORE_FLAG_VALUE and zero, we can
3390 just make the comparison operation. */
3391 if (true == const_true_rtx && false == const0_rtx)
3392 x = gen_binary (cond_code, mode, cond, cop1);
3393 else if (true == const0_rtx && false == const_true_rtx)
3394 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3396 /* Likewise, we can make the negate of a comparison operation
3397 if the result values are - STORE_FLAG_VALUE and zero. */
3398 else if (GET_CODE (true) == CONST_INT
3399 && INTVAL (true) == - STORE_FLAG_VALUE
3400 && false == const0_rtx)
3401 x = gen_unary (NEG, mode, mode,
3402 gen_binary (cond_code, mode, cond, cop1));
3403 else if (GET_CODE (false) == CONST_INT
3404 && INTVAL (false) == - STORE_FLAG_VALUE
3405 && true == const0_rtx)
3406 x = gen_unary (NEG, mode, mode,
3407 gen_binary (reverse_condition (cond_code),
3410 return gen_rtx_IF_THEN_ELSE (mode,
3411 gen_binary (cond_code, VOIDmode,
3415 code = GET_CODE (x);
3416 op0_mode = VOIDmode;
3420 /* Try to fold this expression in case we have constants that weren't
3423 switch (GET_RTX_CLASS (code))
3426 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3429 temp = simplify_relational_operation (code, op0_mode,
3430 XEXP (x, 0), XEXP (x, 1));
3431 #ifdef FLOAT_STORE_FLAG_VALUE
3432 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3433 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3434 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3439 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3443 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3444 XEXP (x, 1), XEXP (x, 2));
3449 x = temp, code = GET_CODE (temp);
3451 /* First see if we can apply the inverse distributive law. */
3452 if (code == PLUS || code == MINUS
3453 || code == AND || code == IOR || code == XOR)
3455 x = apply_distributive_law (x);
3456 code = GET_CODE (x);
3459 /* If CODE is an associative operation not otherwise handled, see if we
3460 can associate some operands. This can win if they are constants or
3461 if they are logically related (i.e. (a & b) & a. */
3462 if ((code == PLUS || code == MINUS
3463 || code == MULT || code == AND || code == IOR || code == XOR
3464 || code == DIV || code == UDIV
3465 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3466 && INTEGRAL_MODE_P (mode))
3468 if (GET_CODE (XEXP (x, 0)) == code)
3470 rtx other = XEXP (XEXP (x, 0), 0);
3471 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3472 rtx inner_op1 = XEXP (x, 1);
3475 /* Make sure we pass the constant operand if any as the second
3476 one if this is a commutative operation. */
3477 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3479 rtx tem = inner_op0;
3480 inner_op0 = inner_op1;
3483 inner = simplify_binary_operation (code == MINUS ? PLUS
3484 : code == DIV ? MULT
3485 : code == UDIV ? MULT
3487 mode, inner_op0, inner_op1);
3489 /* For commutative operations, try the other pair if that one
3491 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3493 other = XEXP (XEXP (x, 0), 1);
3494 inner = simplify_binary_operation (code, mode,
3495 XEXP (XEXP (x, 0), 0),
3500 return gen_binary (code, mode, other, inner);
3504 /* A little bit of algebraic simplification here. */
3508 /* Ensure that our address has any ASHIFTs converted to MULT in case
3509 address-recognizing predicates are called later. */
3510 temp = make_compound_operation (XEXP (x, 0), MEM);
3511 SUBST (XEXP (x, 0), temp);
3515 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3516 is paradoxical. If we can't do that safely, then it becomes
3517 something nonsensical so that this combination won't take place. */
3519 if (GET_CODE (SUBREG_REG (x)) == MEM
3520 && (GET_MODE_SIZE (mode)
3521 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3523 rtx inner = SUBREG_REG (x);
3524 int endian_offset = 0;
3525 /* Don't change the mode of the MEM
3526 if that would change the meaning of the address. */
3527 if (MEM_VOLATILE_P (SUBREG_REG (x))
3528 || mode_dependent_address_p (XEXP (inner, 0)))
3529 return gen_rtx_CLOBBER (mode, const0_rtx);
3531 if (BYTES_BIG_ENDIAN)
3533 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3534 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3535 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3536 endian_offset -= (UNITS_PER_WORD
3537 - GET_MODE_SIZE (GET_MODE (inner)));
3539 /* Note if the plus_constant doesn't make a valid address
3540 then this combination won't be accepted. */
3541 x = gen_rtx_MEM (mode,
3542 plus_constant (XEXP (inner, 0),
3543 (SUBREG_WORD (x) * UNITS_PER_WORD
3545 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3546 MEM_COPY_ATTRIBUTES (x, inner);
3550 /* If we are in a SET_DEST, these other cases can't apply. */
3554 /* Changing mode twice with SUBREG => just change it once,
3555 or not at all if changing back to starting mode. */
3556 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3558 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3559 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3560 return SUBREG_REG (SUBREG_REG (x));
3562 SUBST_INT (SUBREG_WORD (x),
3563 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3564 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3567 /* SUBREG of a hard register => just change the register number
3568 and/or mode. If the hard register is not valid in that mode,
3569 suppress this combination. If the hard register is the stack,
3570 frame, or argument pointer, leave this as a SUBREG. */
3572 if (GET_CODE (SUBREG_REG (x)) == REG
3573 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3574 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3575 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3576 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3578 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3579 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3581 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3583 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3585 return gen_rtx_REG (mode,
3586 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3588 return gen_rtx_CLOBBER (mode, const0_rtx);
3591 /* For a constant, try to pick up the part we want. Handle a full
3592 word and low-order part. Only do this if we are narrowing
3593 the constant; if it is being widened, we have no idea what
3594 the extra bits will have been set to. */
3596 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3597 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3598 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3599 && GET_MODE_CLASS (mode) == MODE_INT)
3601 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3607 /* If we want a subreg of a constant, at offset 0,
3608 take the low bits. On a little-endian machine, that's
3609 always valid. On a big-endian machine, it's valid
3610 only if the constant's mode fits in one word. Note that we
3611 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3612 if (CONSTANT_P (SUBREG_REG (x))
3613 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3614 || ! WORDS_BIG_ENDIAN)
3615 ? SUBREG_WORD (x) == 0
3617 == ((GET_MODE_SIZE (op0_mode)
3618 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3620 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3621 && (! WORDS_BIG_ENDIAN
3622 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3623 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3625 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3626 since we are saying that the high bits don't matter. */
3627 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3628 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3629 return SUBREG_REG (x);
3631 /* Note that we cannot do any narrowing for non-constants since
3632 we might have been counting on using the fact that some bits were
3633 zero. We now do this in the SET. */
3638 /* (not (plus X -1)) can become (neg X). */
3639 if (GET_CODE (XEXP (x, 0)) == PLUS
3640 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3641 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3643 /* Similarly, (not (neg X)) is (plus X -1). */
3644 if (GET_CODE (XEXP (x, 0)) == NEG)
3645 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3648 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3649 if (GET_CODE (XEXP (x, 0)) == XOR
3650 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3651 && (temp = simplify_unary_operation (NOT, mode,
3652 XEXP (XEXP (x, 0), 1),
3654 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3656 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3657 other than 1, but that is not valid. We could do a similar
3658 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3659 but this doesn't seem common enough to bother with. */
3660 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3661 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3662 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3663 XEXP (XEXP (x, 0), 1));
3665 if (GET_CODE (XEXP (x, 0)) == SUBREG
3666 && subreg_lowpart_p (XEXP (x, 0))
3667 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3668 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3669 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3670 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3672 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3674 x = gen_rtx_ROTATE (inner_mode,
3675 gen_unary (NOT, inner_mode, inner_mode,
3677 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3678 return gen_lowpart_for_combine (mode, x);
3681 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3682 reversing the comparison code if valid. */
3683 if (STORE_FLAG_VALUE == -1
3684 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3685 && reversible_comparison_p (XEXP (x, 0)))
3686 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3687 mode, XEXP (XEXP (x, 0), 0),
3688 XEXP (XEXP (x, 0), 1));
3690 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3691 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3692 perform the above simplification. */
3694 if (STORE_FLAG_VALUE == -1
3695 && XEXP (x, 1) == const1_rtx
3696 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3697 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3698 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3699 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3701 /* Apply De Morgan's laws to reduce number of patterns for machines
3702 with negating logical insns (and-not, nand, etc.). If result has
3703 only one NOT, put it first, since that is how the patterns are
3706 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3708 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3710 if (GET_CODE (in1) == NOT)
3711 in1 = XEXP (in1, 0);
3713 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3715 if (GET_CODE (in2) == NOT)
3716 in2 = XEXP (in2, 0);
3717 else if (GET_CODE (in2) == CONST_INT
3718 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3719 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3721 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3723 if (GET_CODE (in2) == NOT)
3726 in2 = in1; in1 = tem;
3729 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3735 /* (neg (plus X 1)) can become (not X). */
3736 if (GET_CODE (XEXP (x, 0)) == PLUS
3737 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3738 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3740 /* Similarly, (neg (not X)) is (plus X 1). */
3741 if (GET_CODE (XEXP (x, 0)) == NOT)
3742 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3744 /* (neg (minus X Y)) can become (minus Y X). */
3745 if (GET_CODE (XEXP (x, 0)) == MINUS
3746 && (! FLOAT_MODE_P (mode)
3747 /* x-y != -(y-x) with IEEE floating point. */
3748 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3750 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3751 XEXP (XEXP (x, 0), 0));
3753 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3754 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3755 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3756 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3758 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3759 if we can then eliminate the NEG (e.g.,
3760 if the operand is a constant). */
3762 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3764 temp = simplify_unary_operation (NEG, mode,
3765 XEXP (XEXP (x, 0), 0), mode);
3768 SUBST (XEXP (XEXP (x, 0), 0), temp);
3773 temp = expand_compound_operation (XEXP (x, 0));
3775 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3776 replaced by (lshiftrt X C). This will convert
3777 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3779 if (GET_CODE (temp) == ASHIFTRT
3780 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3781 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3782 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3783 INTVAL (XEXP (temp, 1)));
3785 /* If X has only a single bit that might be nonzero, say, bit I, convert
3786 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3787 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3788 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3789 or a SUBREG of one since we'd be making the expression more
3790 complex if it was just a register. */
3792 if (GET_CODE (temp) != REG
3793 && ! (GET_CODE (temp) == SUBREG
3794 && GET_CODE (SUBREG_REG (temp)) == REG)
3795 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3797 rtx temp1 = simplify_shift_const
3798 (NULL_RTX, ASHIFTRT, mode,
3799 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3800 GET_MODE_BITSIZE (mode) - 1 - i),
3801 GET_MODE_BITSIZE (mode) - 1 - i);
3803 /* If all we did was surround TEMP with the two shifts, we
3804 haven't improved anything, so don't use it. Otherwise,
3805 we are better off with TEMP1. */
3806 if (GET_CODE (temp1) != ASHIFTRT
3807 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3808 || XEXP (XEXP (temp1, 0), 0) != temp)
3814 /* We can't handle truncation to a partial integer mode here
3815 because we don't know the real bitsize of the partial
3817 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3820 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3821 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3822 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3824 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3825 GET_MODE_MASK (mode), NULL_RTX, 0));
3827 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3828 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3829 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3830 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3831 return XEXP (XEXP (x, 0), 0);
3833 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3834 (OP:SI foo:SI) if OP is NEG or ABS. */
3835 if ((GET_CODE (XEXP (x, 0)) == ABS
3836 || GET_CODE (XEXP (x, 0)) == NEG)
3837 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3838 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3839 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3840 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3841 XEXP (XEXP (XEXP (x, 0), 0), 0));
3843 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3845 if (GET_CODE (XEXP (x, 0)) == SUBREG
3846 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3847 && subreg_lowpart_p (XEXP (x, 0)))
3848 return SUBREG_REG (XEXP (x, 0));
3850 /* If we know that the value is already truncated, we can
3851 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3852 nonzero for the corresponding modes. */
3853 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3854 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3855 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3856 >= GET_MODE_BITSIZE (mode) + 1)
3857 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3859 /* A truncate of a comparison can be replaced with a subreg if
3860 STORE_FLAG_VALUE permits. This is like the previous test,
3861 but it works even if the comparison is done in a mode larger
3862 than HOST_BITS_PER_WIDE_INT. */
3863 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3864 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3865 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3866 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3868 /* Similarly, a truncate of a register whose value is a
3869 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3871 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3872 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3873 && (temp = get_last_value (XEXP (x, 0)))
3874 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3875 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3879 case FLOAT_TRUNCATE:
3880 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3881 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3882 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3883 return XEXP (XEXP (x, 0), 0);
3885 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3886 (OP:SF foo:SF) if OP is NEG or ABS. */
3887 if ((GET_CODE (XEXP (x, 0)) == ABS
3888 || GET_CODE (XEXP (x, 0)) == NEG)
3889 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3890 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3891 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3892 XEXP (XEXP (XEXP (x, 0), 0), 0));
3894 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3895 is (float_truncate:SF x). */
3896 if (GET_CODE (XEXP (x, 0)) == SUBREG
3897 && subreg_lowpart_p (XEXP (x, 0))
3898 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3899 return SUBREG_REG (XEXP (x, 0));
3904 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3905 using cc0, in which case we want to leave it as a COMPARE
3906 so we can distinguish it from a register-register-copy. */
3907 if (XEXP (x, 1) == const0_rtx)
3910 /* In IEEE floating point, x-0 is not the same as x. */
3911 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3912 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3914 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3920 /* (const (const X)) can become (const X). Do it this way rather than
3921 returning the inner CONST since CONST can be shared with a
3923 if (GET_CODE (XEXP (x, 0)) == CONST)
3924 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3929 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3930 can add in an offset. find_split_point will split this address up
3931 again if it doesn't match. */
3932 if (GET_CODE (XEXP (x, 0)) == HIGH
3933 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3939 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3940 outermost. That's because that's the way indexed addresses are
3941 supposed to appear. This code used to check many more cases, but
3942 they are now checked elsewhere. */
3943 if (GET_CODE (XEXP (x, 0)) == PLUS
3944 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3945 return gen_binary (PLUS, mode,
3946 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3948 XEXP (XEXP (x, 0), 1));
3950 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3951 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3952 bit-field and can be replaced by either a sign_extend or a
3953 sign_extract. The `and' may be a zero_extend and the two
3954 <c>, -<c> constants may be reversed. */
3955 if (GET_CODE (XEXP (x, 0)) == XOR
3956 && GET_CODE (XEXP (x, 1)) == CONST_INT
3957 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3958 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3959 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3960 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
3961 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3962 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3963 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3964 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3965 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3966 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3967 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3969 return simplify_shift_const
3970 (NULL_RTX, ASHIFTRT, mode,
3971 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3972 XEXP (XEXP (XEXP (x, 0), 0), 0),
3973 GET_MODE_BITSIZE (mode) - (i + 1)),
3974 GET_MODE_BITSIZE (mode) - (i + 1));
3976 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3977 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3978 is 1. This produces better code than the alternative immediately
3980 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3981 && reversible_comparison_p (XEXP (x, 0))
3982 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3983 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3985 gen_unary (NEG, mode, mode,
3986 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3987 mode, XEXP (XEXP (x, 0), 0),
3988 XEXP (XEXP (x, 0), 1)));
3990 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3991 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3992 the bitsize of the mode - 1. This allows simplification of
3993 "a = (b & 8) == 0;" */
3994 if (XEXP (x, 1) == constm1_rtx
3995 && GET_CODE (XEXP (x, 0)) != REG
3996 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3997 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3998 && nonzero_bits (XEXP (x, 0), mode) == 1)
3999 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4000 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4001 gen_rtx_combine (XOR, mode,
4002 XEXP (x, 0), const1_rtx),
4003 GET_MODE_BITSIZE (mode) - 1),
4004 GET_MODE_BITSIZE (mode) - 1);
4006 /* If we are adding two things that have no bits in common, convert
4007 the addition into an IOR. This will often be further simplified,
4008 for example in cases like ((a & 1) + (a & 2)), which can
4011 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4012 && (nonzero_bits (XEXP (x, 0), mode)
4013 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4014 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4018 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4019 by reversing the comparison code if valid. */
4020 if (STORE_FLAG_VALUE == 1
4021 && XEXP (x, 0) == const1_rtx
4022 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4023 && reversible_comparison_p (XEXP (x, 1)))
4024 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
4025 mode, XEXP (XEXP (x, 1), 0),
4026 XEXP (XEXP (x, 1), 1));
4028 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4029 (and <foo> (const_int pow2-1)) */
4030 if (GET_CODE (XEXP (x, 1)) == AND
4031 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4032 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4033 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4034 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4035 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4037 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4039 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4040 return gen_binary (MINUS, mode,
4041 gen_binary (MINUS, mode, XEXP (x, 0),
4042 XEXP (XEXP (x, 1), 0)),
4043 XEXP (XEXP (x, 1), 1));
4047 /* If we have (mult (plus A B) C), apply the distributive law and then
4048 the inverse distributive law to see if things simplify. This
4049 occurs mostly in addresses, often when unrolling loops. */
4051 if (GET_CODE (XEXP (x, 0)) == PLUS)
4053 x = apply_distributive_law
4054 (gen_binary (PLUS, mode,
4055 gen_binary (MULT, mode,
4056 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4057 gen_binary (MULT, mode,
4058 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4060 if (GET_CODE (x) != MULT)
4066 /* If this is a divide by a power of two, treat it as a shift if
4067 its first operand is a shift. */
4068 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4069 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4070 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4071 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4072 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4073 || GET_CODE (XEXP (x, 0)) == ROTATE
4074 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4075 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4079 case GT: case GTU: case GE: case GEU:
4080 case LT: case LTU: case LE: case LEU:
4081 /* If the first operand is a condition code, we can't do anything
4083 if (GET_CODE (XEXP (x, 0)) == COMPARE
4084 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4086 && XEXP (x, 0) != cc0_rtx
4090 rtx op0 = XEXP (x, 0);
4091 rtx op1 = XEXP (x, 1);
4092 enum rtx_code new_code;
4094 if (GET_CODE (op0) == COMPARE)
4095 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4097 /* Simplify our comparison, if possible. */
4098 new_code = simplify_comparison (code, &op0, &op1);
4100 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4101 if only the low-order bit is possibly nonzero in X (such as when
4102 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4103 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4104 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4107 Remove any ZERO_EXTRACT we made when thinking this was a
4108 comparison. It may now be simpler to use, e.g., an AND. If a
4109 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4110 the call to make_compound_operation in the SET case. */
4112 if (STORE_FLAG_VALUE == 1
4113 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4114 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4115 return gen_lowpart_for_combine (mode,
4116 expand_compound_operation (op0));
4118 else if (STORE_FLAG_VALUE == 1
4119 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4120 && op1 == const0_rtx
4121 && (num_sign_bit_copies (op0, mode)
4122 == GET_MODE_BITSIZE (mode)))
4124 op0 = expand_compound_operation (op0);
4125 return gen_unary (NEG, mode, mode,
4126 gen_lowpart_for_combine (mode, op0));
4129 else if (STORE_FLAG_VALUE == 1
4130 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4131 && op1 == const0_rtx
4132 && nonzero_bits (op0, mode) == 1)
4134 op0 = expand_compound_operation (op0);
4135 return gen_binary (XOR, mode,
4136 gen_lowpart_for_combine (mode, op0),
4140 else if (STORE_FLAG_VALUE == 1
4141 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4142 && op1 == const0_rtx
4143 && (num_sign_bit_copies (op0, mode)
4144 == GET_MODE_BITSIZE (mode)))
4146 op0 = expand_compound_operation (op0);
4147 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4150 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4152 if (STORE_FLAG_VALUE == -1
4153 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4154 && op1 == const0_rtx
4155 && (num_sign_bit_copies (op0, mode)
4156 == GET_MODE_BITSIZE (mode)))
4157 return gen_lowpart_for_combine (mode,
4158 expand_compound_operation (op0));
4160 else if (STORE_FLAG_VALUE == -1
4161 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4162 && op1 == const0_rtx
4163 && nonzero_bits (op0, mode) == 1)
4165 op0 = expand_compound_operation (op0);
4166 return gen_unary (NEG, mode, mode,
4167 gen_lowpart_for_combine (mode, op0));
4170 else if (STORE_FLAG_VALUE == -1
4171 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4172 && op1 == const0_rtx
4173 && (num_sign_bit_copies (op0, mode)
4174 == GET_MODE_BITSIZE (mode)))
4176 op0 = expand_compound_operation (op0);
4177 return gen_unary (NOT, mode, mode,
4178 gen_lowpart_for_combine (mode, op0));
4181 /* If X is 0/1, (eq X 0) is X-1. */
4182 else if (STORE_FLAG_VALUE == -1
4183 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4184 && op1 == const0_rtx
4185 && nonzero_bits (op0, mode) == 1)
4187 op0 = expand_compound_operation (op0);
4188 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4191 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4192 one bit that might be nonzero, we can convert (ne x 0) to
4193 (ashift x c) where C puts the bit in the sign bit. Remove any
4194 AND with STORE_FLAG_VALUE when we are done, since we are only
4195 going to test the sign bit. */
4196 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4197 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4198 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4199 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4200 && op1 == const0_rtx
4201 && mode == GET_MODE (op0)
4202 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4204 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4205 expand_compound_operation (op0),
4206 GET_MODE_BITSIZE (mode) - 1 - i);
4207 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4213 /* If the code changed, return a whole new comparison. */
4214 if (new_code != code)
4215 return gen_rtx_combine (new_code, mode, op0, op1);
4217 /* Otherwise, keep this operation, but maybe change its operands.
4218 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4219 SUBST (XEXP (x, 0), op0);
4220 SUBST (XEXP (x, 1), op1);
4225 return simplify_if_then_else (x);
4231 /* If we are processing SET_DEST, we are done. */
4235 return expand_compound_operation (x);
4238 return simplify_set (x);
4243 return simplify_logical (x, last);
4246 /* (abs (neg <foo>)) -> (abs <foo>) */
4247 if (GET_CODE (XEXP (x, 0)) == NEG)
4248 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4250 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4252 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4255 /* If operand is something known to be positive, ignore the ABS. */
4256 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4257 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4258 <= HOST_BITS_PER_WIDE_INT)
4259 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4260 & ((HOST_WIDE_INT) 1
4261 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4266 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4267 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4268 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4273 /* (ffs (*_extend <X>)) = (ffs <X>) */
4274 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4275 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4276 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4280 /* (float (sign_extend <X>)) = (float <X>). */
4281 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4282 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4290 /* If this is a shift by a constant amount, simplify it. */
4291 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4292 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4293 INTVAL (XEXP (x, 1)));
4295 #ifdef SHIFT_COUNT_TRUNCATED
4296 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4298 force_to_mode (XEXP (x, 1), GET_MODE (x),
4300 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4314 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4317 simplify_if_then_else (x)
4320 enum machine_mode mode = GET_MODE (x);
4321 rtx cond = XEXP (x, 0);
4322 rtx true = XEXP (x, 1);
4323 rtx false = XEXP (x, 2);
4324 enum rtx_code true_code = GET_CODE (cond);
4325 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4329 /* Simplify storing of the truth value. */
4330 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4331 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4333 /* Also when the truth value has to be reversed. */
4334 if (comparison_p && reversible_comparison_p (cond)
4335 && true == const0_rtx && false == const_true_rtx)
4336 return gen_binary (reverse_condition (true_code),
4337 mode, XEXP (cond, 0), XEXP (cond, 1));
4339 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4340 in it is being compared against certain values. Get the true and false
4341 comparisons and see if that says anything about the value of each arm. */
4343 if (comparison_p && reversible_comparison_p (cond)
4344 && GET_CODE (XEXP (cond, 0)) == REG)
4347 rtx from = XEXP (cond, 0);
4348 enum rtx_code false_code = reverse_condition (true_code);
4349 rtx true_val = XEXP (cond, 1);
4350 rtx false_val = true_val;
4353 /* If FALSE_CODE is EQ, swap the codes and arms. */
4355 if (false_code == EQ)
4357 swapped = 1, true_code = EQ, false_code = NE;
4358 temp = true, true = false, false = temp;
4361 /* If we are comparing against zero and the expression being tested has
4362 only a single bit that might be nonzero, that is its value when it is
4363 not equal to zero. Similarly if it is known to be -1 or 0. */
4365 if (true_code == EQ && true_val == const0_rtx
4366 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4367 false_code = EQ, false_val = GEN_INT (nzb);
4368 else if (true_code == EQ && true_val == const0_rtx
4369 && (num_sign_bit_copies (from, GET_MODE (from))
4370 == GET_MODE_BITSIZE (GET_MODE (from))))
4371 false_code = EQ, false_val = constm1_rtx;
4373 /* Now simplify an arm if we know the value of the register in the
4374 branch and it is used in the arm. Be careful due to the potential
4375 of locally-shared RTL. */
4377 if (reg_mentioned_p (from, true))
4378 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4379 pc_rtx, pc_rtx, 0, 0);
4380 if (reg_mentioned_p (from, false))
4381 false = subst (known_cond (copy_rtx (false), false_code,
4383 pc_rtx, pc_rtx, 0, 0);
4385 SUBST (XEXP (x, 1), swapped ? false : true);
4386 SUBST (XEXP (x, 2), swapped ? true : false);
4388 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4391 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4392 reversed, do so to avoid needing two sets of patterns for
4393 subtract-and-branch insns. Similarly if we have a constant in the true
4394 arm, the false arm is the same as the first operand of the comparison, or
4395 the false arm is more complicated than the true arm. */
4397 if (comparison_p && reversible_comparison_p (cond)
4399 || (CONSTANT_P (true)
4400 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4401 || true == const0_rtx
4402 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4403 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4404 || (GET_CODE (true) == SUBREG
4405 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4406 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4407 || reg_mentioned_p (true, false)
4408 || rtx_equal_p (false, XEXP (cond, 0))))
4410 true_code = reverse_condition (true_code);
4412 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4415 SUBST (XEXP (x, 1), false);
4416 SUBST (XEXP (x, 2), true);
4418 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4420 /* It is possible that the conditional has been simplified out. */
4421 true_code = GET_CODE (cond);
4422 comparison_p = GET_RTX_CLASS (true_code) == '<';
4425 /* If the two arms are identical, we don't need the comparison. */
4427 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4430 /* Convert a == b ? b : a to "a". */
4431 if (true_code == EQ && ! side_effects_p (cond)
4432 && rtx_equal_p (XEXP (cond, 0), false)
4433 && rtx_equal_p (XEXP (cond, 1), true))
4435 else if (true_code == NE && ! side_effects_p (cond)
4436 && rtx_equal_p (XEXP (cond, 0), true)
4437 && rtx_equal_p (XEXP (cond, 1), false))
4440 /* Look for cases where we have (abs x) or (neg (abs X)). */
4442 if (GET_MODE_CLASS (mode) == MODE_INT
4443 && GET_CODE (false) == NEG
4444 && rtx_equal_p (true, XEXP (false, 0))
4446 && rtx_equal_p (true, XEXP (cond, 0))
4447 && ! side_effects_p (true))
4452 return gen_unary (ABS, mode, mode, true);
4455 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4460 /* Look for MIN or MAX. */
4462 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4464 && rtx_equal_p (XEXP (cond, 0), true)
4465 && rtx_equal_p (XEXP (cond, 1), false)
4466 && ! side_effects_p (cond))
4471 return gen_binary (SMAX, mode, true, false);
4474 return gen_binary (SMIN, mode, true, false);
4477 return gen_binary (UMAX, mode, true, false);
4480 return gen_binary (UMIN, mode, true, false);
4485 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4486 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4487 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4488 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4489 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4490 neither 1 or -1, but it isn't worth checking for. */
4492 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4493 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4495 rtx t = make_compound_operation (true, SET);
4496 rtx f = make_compound_operation (false, SET);
4497 rtx cond_op0 = XEXP (cond, 0);
4498 rtx cond_op1 = XEXP (cond, 1);
4499 enum rtx_code op = NIL, extend_op = NIL;
4500 enum machine_mode m = mode;
4501 rtx z = 0, c1 = NULL_RTX;
4503 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4504 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4505 || GET_CODE (t) == ASHIFT
4506 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4507 && rtx_equal_p (XEXP (t, 0), f))
4508 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4510 /* If an identity-zero op is commutative, check whether there
4511 would be a match if we swapped the operands. */
4512 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4513 || GET_CODE (t) == XOR)
4514 && rtx_equal_p (XEXP (t, 1), f))
4515 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4516 else if (GET_CODE (t) == SIGN_EXTEND
4517 && (GET_CODE (XEXP (t, 0)) == PLUS
4518 || GET_CODE (XEXP (t, 0)) == MINUS
4519 || GET_CODE (XEXP (t, 0)) == IOR
4520 || GET_CODE (XEXP (t, 0)) == XOR
4521 || GET_CODE (XEXP (t, 0)) == ASHIFT
4522 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4523 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4524 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4525 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4526 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4527 && (num_sign_bit_copies (f, GET_MODE (f))
4528 > (GET_MODE_BITSIZE (mode)
4529 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4531 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4532 extend_op = SIGN_EXTEND;
4533 m = GET_MODE (XEXP (t, 0));
4535 else if (GET_CODE (t) == SIGN_EXTEND
4536 && (GET_CODE (XEXP (t, 0)) == PLUS
4537 || GET_CODE (XEXP (t, 0)) == IOR
4538 || GET_CODE (XEXP (t, 0)) == XOR)
4539 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4540 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4541 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4542 && (num_sign_bit_copies (f, GET_MODE (f))
4543 > (GET_MODE_BITSIZE (mode)
4544 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4546 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4547 extend_op = SIGN_EXTEND;
4548 m = GET_MODE (XEXP (t, 0));
4550 else if (GET_CODE (t) == ZERO_EXTEND
4551 && (GET_CODE (XEXP (t, 0)) == PLUS
4552 || GET_CODE (XEXP (t, 0)) == MINUS
4553 || GET_CODE (XEXP (t, 0)) == IOR
4554 || GET_CODE (XEXP (t, 0)) == XOR
4555 || GET_CODE (XEXP (t, 0)) == ASHIFT
4556 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4557 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4558 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4559 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4560 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4561 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4562 && ((nonzero_bits (f, GET_MODE (f))
4563 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4566 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4567 extend_op = ZERO_EXTEND;
4568 m = GET_MODE (XEXP (t, 0));
4570 else if (GET_CODE (t) == ZERO_EXTEND
4571 && (GET_CODE (XEXP (t, 0)) == PLUS
4572 || GET_CODE (XEXP (t, 0)) == IOR
4573 || GET_CODE (XEXP (t, 0)) == XOR)
4574 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4575 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4576 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4577 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4578 && ((nonzero_bits (f, GET_MODE (f))
4579 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4582 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4583 extend_op = ZERO_EXTEND;
4584 m = GET_MODE (XEXP (t, 0));
4589 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4590 pc_rtx, pc_rtx, 0, 0);
4591 temp = gen_binary (MULT, m, temp,
4592 gen_binary (MULT, m, c1, const_true_rtx));
4593 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4594 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4596 if (extend_op != NIL)
4597 temp = gen_unary (extend_op, mode, m, temp);
4603 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4604 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4605 negation of a single bit, we can convert this operation to a shift. We
4606 can actually do this more generally, but it doesn't seem worth it. */
4608 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4609 && false == const0_rtx && GET_CODE (true) == CONST_INT
4610 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4611 && (i = exact_log2 (INTVAL (true))) >= 0)
4612 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4613 == GET_MODE_BITSIZE (mode))
4614 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4616 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4617 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4622 /* Simplify X, a SET expression. Return the new expression. */
4628 rtx src = SET_SRC (x);
4629 rtx dest = SET_DEST (x);
4630 enum machine_mode mode
4631 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4635 /* (set (pc) (return)) gets written as (return). */
4636 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4639 /* Now that we know for sure which bits of SRC we are using, see if we can
4640 simplify the expression for the object knowing that we only need the
4643 if (GET_MODE_CLASS (mode) == MODE_INT)
4645 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4646 SUBST (SET_SRC (x), src);
4649 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4650 the comparison result and try to simplify it unless we already have used
4651 undobuf.other_insn. */
4652 if ((GET_CODE (src) == COMPARE
4657 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4658 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4659 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4660 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4662 enum rtx_code old_code = GET_CODE (*cc_use);
4663 enum rtx_code new_code;
4665 int other_changed = 0;
4666 enum machine_mode compare_mode = GET_MODE (dest);
4668 if (GET_CODE (src) == COMPARE)
4669 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4671 op0 = src, op1 = const0_rtx;
4673 /* Simplify our comparison, if possible. */
4674 new_code = simplify_comparison (old_code, &op0, &op1);
4676 #ifdef EXTRA_CC_MODES
4677 /* If this machine has CC modes other than CCmode, check to see if we
4678 need to use a different CC mode here. */
4679 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4680 #endif /* EXTRA_CC_MODES */
4682 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4683 /* If the mode changed, we have to change SET_DEST, the mode in the
4684 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4685 a hard register, just build new versions with the proper mode. If it
4686 is a pseudo, we lose unless it is only time we set the pseudo, in
4687 which case we can safely change its mode. */
4688 if (compare_mode != GET_MODE (dest))
4690 int regno = REGNO (dest);
4691 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4693 if (regno < FIRST_PSEUDO_REGISTER
4694 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4696 if (regno >= FIRST_PSEUDO_REGISTER)
4697 SUBST (regno_reg_rtx[regno], new_dest);
4699 SUBST (SET_DEST (x), new_dest);
4700 SUBST (XEXP (*cc_use, 0), new_dest);
4708 /* If the code changed, we have to build a new comparison in
4709 undobuf.other_insn. */
4710 if (new_code != old_code)
4712 unsigned HOST_WIDE_INT mask;
4714 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4717 /* If the only change we made was to change an EQ into an NE or
4718 vice versa, OP0 has only one bit that might be nonzero, and OP1
4719 is zero, check if changing the user of the condition code will
4720 produce a valid insn. If it won't, we can keep the original code
4721 in that insn by surrounding our operation with an XOR. */
4723 if (((old_code == NE && new_code == EQ)
4724 || (old_code == EQ && new_code == NE))
4725 && ! other_changed && op1 == const0_rtx
4726 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4727 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4729 rtx pat = PATTERN (other_insn), note = 0;
4731 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4732 && ! check_asm_operands (pat)))
4734 PUT_CODE (*cc_use, old_code);
4737 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4745 undobuf.other_insn = other_insn;
4748 /* If we are now comparing against zero, change our source if
4749 needed. If we do not use cc0, we always have a COMPARE. */
4750 if (op1 == const0_rtx && dest == cc0_rtx)
4752 SUBST (SET_SRC (x), op0);
4758 /* Otherwise, if we didn't previously have a COMPARE in the
4759 correct mode, we need one. */
4760 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4763 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4768 /* Otherwise, update the COMPARE if needed. */
4769 SUBST (XEXP (src, 0), op0);
4770 SUBST (XEXP (src, 1), op1);
4775 /* Get SET_SRC in a form where we have placed back any
4776 compound expressions. Then do the checks below. */
4777 src = make_compound_operation (src, SET);
4778 SUBST (SET_SRC (x), src);
4781 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4782 and X being a REG or (subreg (reg)), we may be able to convert this to
4783 (set (subreg:m2 x) (op)).
4785 We can always do this if M1 is narrower than M2 because that means that
4786 we only care about the low bits of the result.
4788 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4789 perform a narrower operation than requested since the high-order bits will
4790 be undefined. On machine where it is defined, this transformation is safe
4791 as long as M1 and M2 have the same number of words. */
4793 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4794 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4795 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4797 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4798 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4799 #ifndef WORD_REGISTER_OPERATIONS
4800 && (GET_MODE_SIZE (GET_MODE (src))
4801 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4803 #ifdef CLASS_CANNOT_CHANGE_SIZE
4804 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4805 && (TEST_HARD_REG_BIT
4806 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4808 && (GET_MODE_SIZE (GET_MODE (src))
4809 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4811 && (GET_CODE (dest) == REG
4812 || (GET_CODE (dest) == SUBREG
4813 && GET_CODE (SUBREG_REG (dest)) == REG)))
4815 SUBST (SET_DEST (x),
4816 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4818 SUBST (SET_SRC (x), SUBREG_REG (src));
4820 src = SET_SRC (x), dest = SET_DEST (x);
4823 #ifdef LOAD_EXTEND_OP
4824 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4825 would require a paradoxical subreg. Replace the subreg with a
4826 zero_extend to avoid the reload that would otherwise be required. */
4828 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4829 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4830 && SUBREG_WORD (src) == 0
4831 && (GET_MODE_SIZE (GET_MODE (src))
4832 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4833 && GET_CODE (SUBREG_REG (src)) == MEM)
4836 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4837 GET_MODE (src), XEXP (src, 0)));
4843 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4844 are comparing an item known to be 0 or -1 against 0, use a logical
4845 operation instead. Check for one of the arms being an IOR of the other
4846 arm with some value. We compute three terms to be IOR'ed together. In
4847 practice, at most two will be nonzero. Then we do the IOR's. */
4849 if (GET_CODE (dest) != PC
4850 && GET_CODE (src) == IF_THEN_ELSE
4851 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4852 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4853 && XEXP (XEXP (src, 0), 1) == const0_rtx
4854 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4855 #ifdef HAVE_conditional_move
4856 && ! can_conditionally_move_p (GET_MODE (src))
4858 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4859 GET_MODE (XEXP (XEXP (src, 0), 0)))
4860 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4861 && ! side_effects_p (src))
4863 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4864 ? XEXP (src, 1) : XEXP (src, 2));
4865 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4866 ? XEXP (src, 2) : XEXP (src, 1));
4867 rtx term1 = const0_rtx, term2, term3;
4869 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4870 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4871 else if (GET_CODE (true) == IOR
4872 && rtx_equal_p (XEXP (true, 1), false))
4873 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4874 else if (GET_CODE (false) == IOR
4875 && rtx_equal_p (XEXP (false, 0), true))
4876 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4877 else if (GET_CODE (false) == IOR
4878 && rtx_equal_p (XEXP (false, 1), true))
4879 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4881 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4882 term3 = gen_binary (AND, GET_MODE (src),
4883 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4884 XEXP (XEXP (src, 0), 0)),
4888 gen_binary (IOR, GET_MODE (src),
4889 gen_binary (IOR, GET_MODE (src), term1, term2),
4895 #ifdef HAVE_conditional_arithmetic
4896 /* If we have conditional arithmetic and the operand of a SET is
4897 a conditional expression, replace this with an IF_THEN_ELSE.
4898 We can either have a conditional expression or a MULT of that expression
4900 if ((GET_RTX_CLASS (GET_CODE (src)) == '1'
4901 || GET_RTX_CLASS (GET_CODE (src)) == '2'
4902 || GET_RTX_CLASS (GET_CODE (src)) == 'c')
4903 && (GET_RTX_CLASS (GET_CODE (XEXP (src, 0))) == '<'
4904 || (GET_CODE (XEXP (src, 0)) == MULT
4905 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src, 0), 0))) == '<'
4906 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT)))
4908 rtx cond = XEXP (src, 0);
4909 rtx true_val = const1_rtx;
4910 rtx false_arm, true_arm;
4912 if (GET_CODE (cond) == MULT)
4914 true_val = XEXP (cond, 1);
4915 cond = XEXP (cond, 0);
4918 if (GET_RTX_CLASS (GET_CODE (src)) == '1')
4920 true_arm = gen_unary (GET_CODE (src), GET_MODE (src),
4921 GET_MODE (XEXP (src, 0)), true_val);
4922 false_arm = gen_unary (GET_CODE (src), GET_MODE (src),
4923 GET_MODE (XEXP (src, 0)), const0_rtx);
4927 true_arm = gen_binary (GET_CODE (src), GET_MODE (src),
4928 true_val, XEXP (src, 1));
4929 false_arm = gen_binary (GET_CODE (src), GET_MODE (src),
4930 const0_rtx, XEXP (src, 1));
4933 /* Canonicalize if true_arm is the simpler one. */
4934 if (GET_RTX_CLASS (GET_CODE (true_arm)) == 'o'
4935 && GET_RTX_CLASS (GET_CODE (false_arm)) != 'o'
4936 && reversible_comparison_p (cond))
4938 rtx temp = true_arm;
4940 true_arm = false_arm;
4943 cond = gen_rtx_combine (reverse_condition (GET_CODE (cond)),
4944 GET_MODE (cond), XEXP (cond, 0),
4948 src = gen_rtx_combine (IF_THEN_ELSE, GET_MODE (src),
4949 gen_rtx_combine (GET_CODE (cond), VOIDmode,
4952 true_arm, false_arm);
4953 SUBST (SET_SRC (x), src);
4957 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4958 whole thing fail. */
4959 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4961 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4964 /* Convert this into a field assignment operation, if possible. */
4965 return make_field_assignment (x);
4968 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4969 result. LAST is nonzero if this is the last retry. */
4972 simplify_logical (x, last)
4976 enum machine_mode mode = GET_MODE (x);
4977 rtx op0 = XEXP (x, 0);
4978 rtx op1 = XEXP (x, 1);
4980 switch (GET_CODE (x))
4983 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4984 insn (and may simplify more). */
4985 if (GET_CODE (op0) == XOR
4986 && rtx_equal_p (XEXP (op0, 0), op1)
4987 && ! side_effects_p (op1))
4988 x = gen_binary (AND, mode,
4989 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4991 if (GET_CODE (op0) == XOR
4992 && rtx_equal_p (XEXP (op0, 1), op1)
4993 && ! side_effects_p (op1))
4994 x = gen_binary (AND, mode,
4995 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4997 /* Similarly for (~ (A ^ B)) & A. */
4998 if (GET_CODE (op0) == NOT
4999 && GET_CODE (XEXP (op0, 0)) == XOR
5000 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5001 && ! side_effects_p (op1))
5002 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5004 if (GET_CODE (op0) == NOT
5005 && GET_CODE (XEXP (op0, 0)) == XOR
5006 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5007 && ! side_effects_p (op1))
5008 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5010 /* We can call simplify_and_const_int only if we don't lose
5011 any (sign) bits when converting INTVAL (op1) to
5012 "unsigned HOST_WIDE_INT". */
5013 if (GET_CODE (op1) == CONST_INT
5014 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5015 || INTVAL (op1) > 0))
5017 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5019 /* If we have (ior (and (X C1) C2)) and the next restart would be
5020 the last, simplify this by making C1 as small as possible
5023 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5024 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5025 && GET_CODE (op1) == CONST_INT)
5026 return gen_binary (IOR, mode,
5027 gen_binary (AND, mode, XEXP (op0, 0),
5028 GEN_INT (INTVAL (XEXP (op0, 1))
5029 & ~ INTVAL (op1))), op1);
5031 if (GET_CODE (x) != AND)
5034 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5035 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5036 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5039 /* Convert (A | B) & A to A. */
5040 if (GET_CODE (op0) == IOR
5041 && (rtx_equal_p (XEXP (op0, 0), op1)
5042 || rtx_equal_p (XEXP (op0, 1), op1))
5043 && ! side_effects_p (XEXP (op0, 0))
5044 && ! side_effects_p (XEXP (op0, 1)))
5047 /* In the following group of tests (and those in case IOR below),
5048 we start with some combination of logical operations and apply
5049 the distributive law followed by the inverse distributive law.
5050 Most of the time, this results in no change. However, if some of
5051 the operands are the same or inverses of each other, simplifications
5054 For example, (and (ior A B) (not B)) can occur as the result of
5055 expanding a bit field assignment. When we apply the distributive
5056 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5057 which then simplifies to (and (A (not B))).
5059 If we have (and (ior A B) C), apply the distributive law and then
5060 the inverse distributive law to see if things simplify. */
5062 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5064 x = apply_distributive_law
5065 (gen_binary (GET_CODE (op0), mode,
5066 gen_binary (AND, mode, XEXP (op0, 0), op1),
5067 gen_binary (AND, mode, XEXP (op0, 1), op1)));
5068 if (GET_CODE (x) != AND)
5072 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5073 return apply_distributive_law
5074 (gen_binary (GET_CODE (op1), mode,
5075 gen_binary (AND, mode, XEXP (op1, 0), op0),
5076 gen_binary (AND, mode, XEXP (op1, 1), op0)));
5078 /* Similarly, taking advantage of the fact that
5079 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5081 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5082 return apply_distributive_law
5083 (gen_binary (XOR, mode,
5084 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5085 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
5087 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5088 return apply_distributive_law
5089 (gen_binary (XOR, mode,
5090 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5091 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
5095 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5096 if (GET_CODE (op1) == CONST_INT
5097 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5098 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
5101 /* Convert (A & B) | A to A. */
5102 if (GET_CODE (op0) == AND
5103 && (rtx_equal_p (XEXP (op0, 0), op1)
5104 || rtx_equal_p (XEXP (op0, 1), op1))
5105 && ! side_effects_p (XEXP (op0, 0))
5106 && ! side_effects_p (XEXP (op0, 1)))
5109 /* If we have (ior (and A B) C), apply the distributive law and then
5110 the inverse distributive law to see if things simplify. */
5112 if (GET_CODE (op0) == AND)
5114 x = apply_distributive_law
5115 (gen_binary (AND, mode,
5116 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5117 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
5119 if (GET_CODE (x) != IOR)
5123 if (GET_CODE (op1) == AND)
5125 x = apply_distributive_law
5126 (gen_binary (AND, mode,
5127 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5128 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
5130 if (GET_CODE (x) != IOR)
5134 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5135 mode size to (rotate A CX). */
5137 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5138 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5139 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5140 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5141 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5142 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5143 == GET_MODE_BITSIZE (mode)))
5144 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5145 (GET_CODE (op0) == ASHIFT
5146 ? XEXP (op0, 1) : XEXP (op1, 1)));
5148 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5149 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5150 does not affect any of the bits in OP1, it can really be done
5151 as a PLUS and we can associate. We do this by seeing if OP1
5152 can be safely shifted left C bits. */
5153 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5154 && GET_CODE (XEXP (op0, 0)) == PLUS
5155 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5156 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5157 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5159 int count = INTVAL (XEXP (op0, 1));
5160 HOST_WIDE_INT mask = INTVAL (op1) << count;
5162 if (mask >> count == INTVAL (op1)
5163 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5165 SUBST (XEXP (XEXP (op0, 0), 1),
5166 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5173 /* If we are XORing two things that have no bits in common,
5174 convert them into an IOR. This helps to detect rotation encoded
5175 using those methods and possibly other simplifications. */
5177 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5178 && (nonzero_bits (op0, mode)
5179 & nonzero_bits (op1, mode)) == 0)
5180 return (gen_binary (IOR, mode, op0, op1));
5182 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5183 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5186 int num_negated = 0;
5188 if (GET_CODE (op0) == NOT)
5189 num_negated++, op0 = XEXP (op0, 0);
5190 if (GET_CODE (op1) == NOT)
5191 num_negated++, op1 = XEXP (op1, 0);
5193 if (num_negated == 2)
5195 SUBST (XEXP (x, 0), op0);
5196 SUBST (XEXP (x, 1), op1);
5198 else if (num_negated == 1)
5199 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5202 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5203 correspond to a machine insn or result in further simplifications
5204 if B is a constant. */
5206 if (GET_CODE (op0) == AND
5207 && rtx_equal_p (XEXP (op0, 1), op1)
5208 && ! side_effects_p (op1))
5209 return gen_binary (AND, mode,
5210 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5213 else if (GET_CODE (op0) == AND
5214 && rtx_equal_p (XEXP (op0, 0), op1)
5215 && ! side_effects_p (op1))
5216 return gen_binary (AND, mode,
5217 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5220 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5221 comparison if STORE_FLAG_VALUE is 1. */
5222 if (STORE_FLAG_VALUE == 1
5223 && op1 == const1_rtx
5224 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5225 && reversible_comparison_p (op0))
5226 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5227 mode, XEXP (op0, 0), XEXP (op0, 1));
5229 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5230 is (lt foo (const_int 0)), so we can perform the above
5231 simplification if STORE_FLAG_VALUE is 1. */
5233 if (STORE_FLAG_VALUE == 1
5234 && op1 == const1_rtx
5235 && GET_CODE (op0) == LSHIFTRT
5236 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5237 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5238 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5240 /* (xor (comparison foo bar) (const_int sign-bit))
5241 when STORE_FLAG_VALUE is the sign bit. */
5242 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5243 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5244 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5245 && op1 == const_true_rtx
5246 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5247 && reversible_comparison_p (op0))
5248 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5249 mode, XEXP (op0, 0), XEXP (op0, 1));
5260 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5261 operations" because they can be replaced with two more basic operations.
5262 ZERO_EXTEND is also considered "compound" because it can be replaced with
5263 an AND operation, which is simpler, though only one operation.
5265 The function expand_compound_operation is called with an rtx expression
5266 and will convert it to the appropriate shifts and AND operations,
5267 simplifying at each stage.
5269 The function make_compound_operation is called to convert an expression
5270 consisting of shifts and ANDs into the equivalent compound expression.
5271 It is the inverse of this function, loosely speaking. */
5274 expand_compound_operation (x)
5282 switch (GET_CODE (x))
5287 /* We can't necessarily use a const_int for a multiword mode;
5288 it depends on implicitly extending the value.
5289 Since we don't know the right way to extend it,
5290 we can't tell whether the implicit way is right.
5292 Even for a mode that is no wider than a const_int,
5293 we can't win, because we need to sign extend one of its bits through
5294 the rest of it, and we don't know which bit. */
5295 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5298 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5299 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5300 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5301 reloaded. If not for that, MEM's would very rarely be safe.
5303 Reject MODEs bigger than a word, because we might not be able
5304 to reference a two-register group starting with an arbitrary register
5305 (and currently gen_lowpart might crash for a SUBREG). */
5307 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5310 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5311 /* If the inner object has VOIDmode (the only way this can happen
5312 is if it is a ASM_OPERANDS), we can't do anything since we don't
5313 know how much masking to do. */
5322 /* If the operand is a CLOBBER, just return it. */
5323 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5326 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5327 || GET_CODE (XEXP (x, 2)) != CONST_INT
5328 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5331 len = INTVAL (XEXP (x, 1));
5332 pos = INTVAL (XEXP (x, 2));
5334 /* If this goes outside the object being extracted, replace the object
5335 with a (use (mem ...)) construct that only combine understands
5336 and is used only for this purpose. */
5337 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5338 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5340 if (BITS_BIG_ENDIAN)
5341 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5349 /* We can optimize some special cases of ZERO_EXTEND. */
5350 if (GET_CODE (x) == ZERO_EXTEND)
5352 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5353 know that the last value didn't have any inappropriate bits
5355 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5356 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5357 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5358 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5359 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5360 return XEXP (XEXP (x, 0), 0);
5362 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5363 if (GET_CODE (XEXP (x, 0)) == SUBREG
5364 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5365 && subreg_lowpart_p (XEXP (x, 0))
5366 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5367 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5368 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5369 return SUBREG_REG (XEXP (x, 0));
5371 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5372 is a comparison and STORE_FLAG_VALUE permits. This is like
5373 the first case, but it works even when GET_MODE (x) is larger
5374 than HOST_WIDE_INT. */
5375 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5376 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5377 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5378 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5379 <= HOST_BITS_PER_WIDE_INT)
5380 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5381 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5382 return XEXP (XEXP (x, 0), 0);
5384 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5385 if (GET_CODE (XEXP (x, 0)) == SUBREG
5386 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5387 && subreg_lowpart_p (XEXP (x, 0))
5388 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5389 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5390 <= HOST_BITS_PER_WIDE_INT)
5391 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5392 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5393 return SUBREG_REG (XEXP (x, 0));
5395 /* If sign extension is cheaper than zero extension, then use it
5396 if we know that no extraneous bits are set, and that the high
5398 if (flag_expensive_optimizations
5399 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5400 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5401 & ~ (((unsigned HOST_WIDE_INT)
5402 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5405 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5406 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5407 <= HOST_BITS_PER_WIDE_INT)
5408 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5409 & ~ (((unsigned HOST_WIDE_INT)
5410 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5414 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5416 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5417 return expand_compound_operation (temp);
5421 /* If we reach here, we want to return a pair of shifts. The inner
5422 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5423 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5424 logical depending on the value of UNSIGNEDP.
5426 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5427 converted into an AND of a shift.
5429 We must check for the case where the left shift would have a negative
5430 count. This can happen in a case like (x >> 31) & 255 on machines
5431 that can't shift by a constant. On those machines, we would first
5432 combine the shift with the AND to produce a variable-position
5433 extraction. Then the constant of 31 would be substituted in to produce
5434 a such a position. */
5436 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5437 if (modewidth >= pos - len)
5438 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5440 simplify_shift_const (NULL_RTX, ASHIFT,
5443 modewidth - pos - len),
5446 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5447 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5448 simplify_shift_const (NULL_RTX, LSHIFTRT,
5451 ((HOST_WIDE_INT) 1 << len) - 1);
5453 /* Any other cases we can't handle. */
5457 /* If we couldn't do this for some reason, return the original
5459 if (GET_CODE (tem) == CLOBBER)
5465 /* X is a SET which contains an assignment of one object into
5466 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5467 or certain SUBREGS). If possible, convert it into a series of
5470 We half-heartedly support variable positions, but do not at all
5471 support variable lengths. */
5474 expand_field_assignment (x)
5478 rtx pos; /* Always counts from low bit. */
5481 enum machine_mode compute_mode;
5483 /* Loop until we find something we can't simplify. */
5486 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5487 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5489 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5490 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5491 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5493 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5494 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5496 inner = XEXP (SET_DEST (x), 0);
5497 len = INTVAL (XEXP (SET_DEST (x), 1));
5498 pos = XEXP (SET_DEST (x), 2);
5500 /* If the position is constant and spans the width of INNER,
5501 surround INNER with a USE to indicate this. */
5502 if (GET_CODE (pos) == CONST_INT
5503 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5504 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5506 if (BITS_BIG_ENDIAN)
5508 if (GET_CODE (pos) == CONST_INT)
5509 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5511 else if (GET_CODE (pos) == MINUS
5512 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5513 && (INTVAL (XEXP (pos, 1))
5514 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5515 /* If position is ADJUST - X, new position is X. */
5516 pos = XEXP (pos, 0);
5518 pos = gen_binary (MINUS, GET_MODE (pos),
5519 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5525 /* A SUBREG between two modes that occupy the same numbers of words
5526 can be done by moving the SUBREG to the source. */
5527 else if (GET_CODE (SET_DEST (x)) == SUBREG
5528 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5529 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5530 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5533 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5534 gen_lowpart_for_combine
5535 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5542 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5543 inner = SUBREG_REG (inner);
5545 compute_mode = GET_MODE (inner);
5547 /* Don't attempt bitwise arithmetic on non-integral modes. */
5548 if (! INTEGRAL_MODE_P (compute_mode))
5550 enum machine_mode imode;
5552 /* Something is probably seriously wrong if this matches. */
5553 if (! FLOAT_MODE_P (compute_mode))
5556 /* Try to find an integral mode to pun with. */
5557 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5558 if (imode == BLKmode)
5561 compute_mode = imode;
5562 inner = gen_lowpart_for_combine (imode, inner);
5565 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5566 if (len < HOST_BITS_PER_WIDE_INT)
5567 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5571 /* Now compute the equivalent expression. Make a copy of INNER
5572 for the SET_DEST in case it is a MEM into which we will substitute;
5573 we don't want shared RTL in that case. */
5575 (VOIDmode, copy_rtx (inner),
5576 gen_binary (IOR, compute_mode,
5577 gen_binary (AND, compute_mode,
5578 gen_unary (NOT, compute_mode,
5584 gen_binary (ASHIFT, compute_mode,
5585 gen_binary (AND, compute_mode,
5586 gen_lowpart_for_combine
5587 (compute_mode, SET_SRC (x)),
5595 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5596 it is an RTX that represents a variable starting position; otherwise,
5597 POS is the (constant) starting bit position (counted from the LSB).
5599 INNER may be a USE. This will occur when we started with a bitfield
5600 that went outside the boundary of the object in memory, which is
5601 allowed on most machines. To isolate this case, we produce a USE
5602 whose mode is wide enough and surround the MEM with it. The only
5603 code that understands the USE is this routine. If it is not removed,
5604 it will cause the resulting insn not to match.
5606 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5609 IN_DEST is non-zero if this is a reference in the destination of a
5610 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5611 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5614 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5615 ZERO_EXTRACT should be built even for bits starting at bit 0.
5617 MODE is the desired mode of the result (if IN_DEST == 0).
5619 The result is an RTX for the extraction or NULL_RTX if the target
5623 make_extraction (mode, inner, pos, pos_rtx, len,
5624 unsignedp, in_dest, in_compare)
5625 enum machine_mode mode;
5631 int in_dest, in_compare;
5633 /* This mode describes the size of the storage area
5634 to fetch the overall value from. Within that, we
5635 ignore the POS lowest bits, etc. */
5636 enum machine_mode is_mode = GET_MODE (inner);
5637 enum machine_mode inner_mode;
5638 enum machine_mode wanted_inner_mode = byte_mode;
5639 enum machine_mode wanted_inner_reg_mode = word_mode;
5640 enum machine_mode pos_mode = word_mode;
5641 enum machine_mode extraction_mode = word_mode;
5642 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5645 rtx orig_pos_rtx = pos_rtx;
5648 /* Get some information about INNER and get the innermost object. */
5649 if (GET_CODE (inner) == USE)
5650 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5651 /* We don't need to adjust the position because we set up the USE
5652 to pretend that it was a full-word object. */
5653 spans_byte = 1, inner = XEXP (inner, 0);
5654 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5656 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5657 consider just the QI as the memory to extract from.
5658 The subreg adds or removes high bits; its mode is
5659 irrelevant to the meaning of this extraction,
5660 since POS and LEN count from the lsb. */
5661 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5662 is_mode = GET_MODE (SUBREG_REG (inner));
5663 inner = SUBREG_REG (inner);
5666 inner_mode = GET_MODE (inner);
5668 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5669 pos = INTVAL (pos_rtx), pos_rtx = 0;
5671 /* See if this can be done without an extraction. We never can if the
5672 width of the field is not the same as that of some integer mode. For
5673 registers, we can only avoid the extraction if the position is at the
5674 low-order bit and this is either not in the destination or we have the
5675 appropriate STRICT_LOW_PART operation available.
5677 For MEM, we can avoid an extract if the field starts on an appropriate
5678 boundary and we can change the mode of the memory reference. However,
5679 we cannot directly access the MEM if we have a USE and the underlying
5680 MEM is not TMODE. This combination means that MEM was being used in a
5681 context where bits outside its mode were being referenced; that is only
5682 valid in bit-field insns. */
5684 if (tmode != BLKmode
5685 && ! (spans_byte && inner_mode != tmode)
5686 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5687 && GET_CODE (inner) != MEM
5689 || (GET_CODE (inner) == REG
5690 && (movstrict_optab->handlers[(int) tmode].insn_code
5691 != CODE_FOR_nothing))))
5692 || (GET_CODE (inner) == MEM && pos_rtx == 0
5694 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5695 : BITS_PER_UNIT)) == 0
5696 /* We can't do this if we are widening INNER_MODE (it
5697 may not be aligned, for one thing). */
5698 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5699 && (inner_mode == tmode
5700 || (! mode_dependent_address_p (XEXP (inner, 0))
5701 && ! MEM_VOLATILE_P (inner))))))
5703 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5704 field. If the original and current mode are the same, we need not
5705 adjust the offset. Otherwise, we do if bytes big endian.
5707 If INNER is not a MEM, get a piece consisting of just the field
5708 of interest (in this case POS % BITS_PER_WORD must be 0). */
5710 if (GET_CODE (inner) == MEM)
5713 /* POS counts from lsb, but make OFFSET count in memory order. */
5714 if (BYTES_BIG_ENDIAN)
5715 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5717 offset = pos / BITS_PER_UNIT;
5719 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5720 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5721 MEM_COPY_ATTRIBUTES (new, inner);
5723 else if (GET_CODE (inner) == REG)
5725 /* We can't call gen_lowpart_for_combine here since we always want
5726 a SUBREG and it would sometimes return a new hard register. */
5727 if (tmode != inner_mode)
5728 new = gen_rtx_SUBREG (tmode, inner,
5730 && (GET_MODE_SIZE (inner_mode)
5732 ? (((GET_MODE_SIZE (inner_mode)
5733 - GET_MODE_SIZE (tmode))
5735 - pos / BITS_PER_WORD)
5736 : pos / BITS_PER_WORD));
5741 new = force_to_mode (inner, tmode,
5742 len >= HOST_BITS_PER_WIDE_INT
5743 ? GET_MODE_MASK (tmode)
5744 : ((HOST_WIDE_INT) 1 << len) - 1,
5747 /* If this extraction is going into the destination of a SET,
5748 make a STRICT_LOW_PART unless we made a MEM. */
5751 return (GET_CODE (new) == MEM ? new
5752 : (GET_CODE (new) != SUBREG
5753 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5754 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5756 /* Otherwise, sign- or zero-extend unless we already are in the
5759 return (mode == tmode ? new
5760 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5764 /* Unless this is a COMPARE or we have a funny memory reference,
5765 don't do anything with zero-extending field extracts starting at
5766 the low-order bit since they are simple AND operations. */
5767 if (pos_rtx == 0 && pos == 0 && ! in_dest
5768 && ! in_compare && ! spans_byte && unsignedp)
5771 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5772 we would be spanning bytes or if the position is not a constant and the
5773 length is not 1. In all other cases, we would only be going outside
5774 our object in cases when an original shift would have been
5776 if (! spans_byte && GET_CODE (inner) == MEM
5777 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5778 || (pos_rtx != 0 && len != 1)))
5781 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5782 and the mode for the result. */
5786 wanted_inner_reg_mode
5787 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
5788 if (wanted_inner_reg_mode == VOIDmode)
5789 wanted_inner_reg_mode = word_mode;
5791 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
5792 if (pos_mode == VOIDmode)
5793 pos_mode = word_mode;
5795 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
5796 if (extraction_mode == VOIDmode)
5797 extraction_mode = word_mode;
5802 if (! in_dest && unsignedp)
5804 wanted_inner_reg_mode
5805 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
5806 if (wanted_inner_reg_mode == VOIDmode)
5807 wanted_inner_reg_mode = word_mode;
5809 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
5810 if (pos_mode == VOIDmode)
5811 pos_mode = word_mode;
5813 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
5814 if (extraction_mode == VOIDmode)
5815 extraction_mode = word_mode;
5820 if (! in_dest && ! unsignedp)
5822 wanted_inner_reg_mode
5823 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
5824 if (wanted_inner_reg_mode == VOIDmode)
5825 wanted_inner_reg_mode = word_mode;
5827 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
5828 if (pos_mode == VOIDmode)
5829 pos_mode = word_mode;
5831 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
5832 if (extraction_mode == VOIDmode)
5833 extraction_mode = word_mode;
5837 /* Never narrow an object, since that might not be safe. */
5839 if (mode != VOIDmode
5840 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5841 extraction_mode = mode;
5843 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5844 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5845 pos_mode = GET_MODE (pos_rtx);
5847 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5848 if we have to change the mode of memory and cannot, the desired mode is
5850 if (GET_CODE (inner) != MEM)
5851 wanted_inner_mode = wanted_inner_reg_mode;
5852 else if (inner_mode != wanted_inner_mode
5853 && (mode_dependent_address_p (XEXP (inner, 0))
5854 || MEM_VOLATILE_P (inner)))
5855 wanted_inner_mode = extraction_mode;
5859 if (BITS_BIG_ENDIAN)
5861 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5862 BITS_BIG_ENDIAN style. If position is constant, compute new
5863 position. Otherwise, build subtraction.
5864 Note that POS is relative to the mode of the original argument.
5865 If it's a MEM we need to recompute POS relative to that.
5866 However, if we're extracting from (or inserting into) a register,
5867 we want to recompute POS relative to wanted_inner_mode. */
5868 int width = (GET_CODE (inner) == MEM
5869 ? GET_MODE_BITSIZE (is_mode)
5870 : GET_MODE_BITSIZE (wanted_inner_mode));
5873 pos = width - len - pos;
5876 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5877 GEN_INT (width - len), pos_rtx);
5878 /* POS may be less than 0 now, but we check for that below.
5879 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5882 /* If INNER has a wider mode, make it smaller. If this is a constant
5883 extract, try to adjust the byte to point to the byte containing
5885 if (wanted_inner_mode != VOIDmode
5886 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5887 && ((GET_CODE (inner) == MEM
5888 && (inner_mode == wanted_inner_mode
5889 || (! mode_dependent_address_p (XEXP (inner, 0))
5890 && ! MEM_VOLATILE_P (inner))))))
5894 /* The computations below will be correct if the machine is big
5895 endian in both bits and bytes or little endian in bits and bytes.
5896 If it is mixed, we must adjust. */
5898 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5899 adjust OFFSET to compensate. */
5900 if (BYTES_BIG_ENDIAN
5902 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5903 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5905 /* If this is a constant position, we can move to the desired byte. */
5908 offset += pos / BITS_PER_UNIT;
5909 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5912 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5914 && is_mode != wanted_inner_mode)
5915 offset = (GET_MODE_SIZE (is_mode)
5916 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5918 if (offset != 0 || inner_mode != wanted_inner_mode)
5920 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5921 plus_constant (XEXP (inner, 0), offset));
5922 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5923 MEM_COPY_ATTRIBUTES (newmem, inner);
5928 /* If INNER is not memory, we can always get it into the proper mode. If we
5929 are changing its mode, POS must be a constant and smaller than the size
5931 else if (GET_CODE (inner) != MEM)
5933 if (GET_MODE (inner) != wanted_inner_mode
5935 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5938 inner = force_to_mode (inner, wanted_inner_mode,
5940 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5941 ? GET_MODE_MASK (wanted_inner_mode)
5942 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5946 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5947 have to zero extend. Otherwise, we can just use a SUBREG. */
5949 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5950 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5951 else if (pos_rtx != 0
5952 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5953 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5955 /* Make POS_RTX unless we already have it and it is correct. If we don't
5956 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5958 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5959 pos_rtx = orig_pos_rtx;
5961 else if (pos_rtx == 0)
5962 pos_rtx = GEN_INT (pos);
5964 /* Make the required operation. See if we can use existing rtx. */
5965 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5966 extraction_mode, inner, GEN_INT (len), pos_rtx);
5968 new = gen_lowpart_for_combine (mode, new);
5973 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5974 with any other operations in X. Return X without that shift if so. */
5977 extract_left_shift (x, count)
5981 enum rtx_code code = GET_CODE (x);
5982 enum machine_mode mode = GET_MODE (x);
5988 /* This is the shift itself. If it is wide enough, we will return
5989 either the value being shifted if the shift count is equal to
5990 COUNT or a shift for the difference. */
5991 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5992 && INTVAL (XEXP (x, 1)) >= count)
5993 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5994 INTVAL (XEXP (x, 1)) - count);
5998 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5999 return gen_unary (code, mode, mode, tem);
6003 case PLUS: case IOR: case XOR: case AND:
6004 /* If we can safely shift this constant and we find the inner shift,
6005 make a new operation. */
6006 if (GET_CODE (XEXP (x,1)) == CONST_INT
6007 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6008 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6009 return gen_binary (code, mode, tem,
6010 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6021 /* Look at the expression rooted at X. Look for expressions
6022 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6023 Form these expressions.
6025 Return the new rtx, usually just X.
6027 Also, for machines like the Vax that don't have logical shift insns,
6028 try to convert logical to arithmetic shift operations in cases where
6029 they are equivalent. This undoes the canonicalizations to logical
6030 shifts done elsewhere.
6032 We try, as much as possible, to re-use rtl expressions to save memory.
6034 IN_CODE says what kind of expression we are processing. Normally, it is
6035 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6036 being kludges), it is MEM. When processing the arguments of a comparison
6037 or a COMPARE against zero, it is COMPARE. */
6040 make_compound_operation (x, in_code)
6042 enum rtx_code in_code;
6044 enum rtx_code code = GET_CODE (x);
6045 enum machine_mode mode = GET_MODE (x);
6046 int mode_width = GET_MODE_BITSIZE (mode);
6048 enum rtx_code next_code;
6054 /* Select the code to be used in recursive calls. Once we are inside an
6055 address, we stay there. If we have a comparison, set to COMPARE,
6056 but once inside, go back to our default of SET. */
6058 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6059 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6060 && XEXP (x, 1) == const0_rtx) ? COMPARE
6061 : in_code == COMPARE ? SET : in_code);
6063 /* Process depending on the code of this operation. If NEW is set
6064 non-zero, it will be returned. */
6069 /* Convert shifts by constants into multiplications if inside
6071 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6072 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6073 && INTVAL (XEXP (x, 1)) >= 0)
6075 new = make_compound_operation (XEXP (x, 0), next_code);
6076 new = gen_rtx_combine (MULT, mode, new,
6077 GEN_INT ((HOST_WIDE_INT) 1
6078 << INTVAL (XEXP (x, 1))));
6083 /* If the second operand is not a constant, we can't do anything
6085 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6088 /* If the constant is a power of two minus one and the first operand
6089 is a logical right shift, make an extraction. */
6090 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6091 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6093 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6094 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6095 0, in_code == COMPARE);
6098 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6099 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6100 && subreg_lowpart_p (XEXP (x, 0))
6101 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6102 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6104 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6106 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6107 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6108 0, in_code == COMPARE);
6110 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6111 else if ((GET_CODE (XEXP (x, 0)) == XOR
6112 || GET_CODE (XEXP (x, 0)) == IOR)
6113 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6114 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6115 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6117 /* Apply the distributive law, and then try to make extractions. */
6118 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6119 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6121 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6123 new = make_compound_operation (new, in_code);
6126 /* If we are have (and (rotate X C) M) and C is larger than the number
6127 of bits in M, this is an extraction. */
6129 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6130 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6131 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6132 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6134 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6135 new = make_extraction (mode, new,
6136 (GET_MODE_BITSIZE (mode)
6137 - INTVAL (XEXP (XEXP (x, 0), 1))),
6138 NULL_RTX, i, 1, 0, in_code == COMPARE);
6141 /* On machines without logical shifts, if the operand of the AND is
6142 a logical shift and our mask turns off all the propagated sign
6143 bits, we can replace the logical shift with an arithmetic shift. */
6144 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6145 && (lshr_optab->handlers[(int) mode].insn_code
6146 == CODE_FOR_nothing)
6147 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6148 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6149 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6150 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6151 && mode_width <= HOST_BITS_PER_WIDE_INT)
6153 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6155 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6156 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6158 gen_rtx_combine (ASHIFTRT, mode,
6159 make_compound_operation (XEXP (XEXP (x, 0), 0),
6161 XEXP (XEXP (x, 0), 1)));
6164 /* If the constant is one less than a power of two, this might be
6165 representable by an extraction even if no shift is present.
6166 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6167 we are in a COMPARE. */
6168 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6169 new = make_extraction (mode,
6170 make_compound_operation (XEXP (x, 0),
6172 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6174 /* If we are in a comparison and this is an AND with a power of two,
6175 convert this into the appropriate bit extract. */
6176 else if (in_code == COMPARE
6177 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6178 new = make_extraction (mode,
6179 make_compound_operation (XEXP (x, 0),
6181 i, NULL_RTX, 1, 1, 0, 1);
6186 /* If the sign bit is known to be zero, replace this with an
6187 arithmetic shift. */
6188 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6189 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6190 && mode_width <= HOST_BITS_PER_WIDE_INT
6191 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6193 new = gen_rtx_combine (ASHIFTRT, mode,
6194 make_compound_operation (XEXP (x, 0),
6200 /* ... fall through ... */
6206 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6207 this is a SIGN_EXTRACT. */
6208 if (GET_CODE (rhs) == CONST_INT
6209 && GET_CODE (lhs) == ASHIFT
6210 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6211 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6213 new = make_compound_operation (XEXP (lhs, 0), next_code);
6214 new = make_extraction (mode, new,
6215 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6216 NULL_RTX, mode_width - INTVAL (rhs),
6217 code == LSHIFTRT, 0, in_code == COMPARE);
6220 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6221 If so, try to merge the shifts into a SIGN_EXTEND. We could
6222 also do this for some cases of SIGN_EXTRACT, but it doesn't
6223 seem worth the effort; the case checked for occurs on Alpha. */
6225 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6226 && ! (GET_CODE (lhs) == SUBREG
6227 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6228 && GET_CODE (rhs) == CONST_INT
6229 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6230 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6231 new = make_extraction (mode, make_compound_operation (new, next_code),
6232 0, NULL_RTX, mode_width - INTVAL (rhs),
6233 code == LSHIFTRT, 0, in_code == COMPARE);
6238 /* Call ourselves recursively on the inner expression. If we are
6239 narrowing the object and it has a different RTL code from
6240 what it originally did, do this SUBREG as a force_to_mode. */
6242 tem = make_compound_operation (SUBREG_REG (x), in_code);
6243 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6244 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6245 && subreg_lowpart_p (x))
6247 rtx newer = force_to_mode (tem, mode,
6248 GET_MODE_MASK (mode), NULL_RTX, 0);
6250 /* If we have something other than a SUBREG, we might have
6251 done an expansion, so rerun outselves. */
6252 if (GET_CODE (newer) != SUBREG)
6253 newer = make_compound_operation (newer, in_code);
6258 /* If this is a paradoxical subreg, and the new code is a sign or
6259 zero extension, omit the subreg and widen the extension. If it
6260 is a regular subreg, we can still get rid of the subreg by not
6261 widening so much, or in fact removing the extension entirely. */
6262 if ((GET_CODE (tem) == SIGN_EXTEND
6263 || GET_CODE (tem) == ZERO_EXTEND)
6264 && subreg_lowpart_p (x))
6266 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6267 || (GET_MODE_SIZE (mode) >
6268 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6269 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6271 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6282 x = gen_lowpart_for_combine (mode, new);
6283 code = GET_CODE (x);
6286 /* Now recursively process each operand of this operation. */
6287 fmt = GET_RTX_FORMAT (code);
6288 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6291 new = make_compound_operation (XEXP (x, i), next_code);
6292 SUBST (XEXP (x, i), new);
6298 /* Given M see if it is a value that would select a field of bits
6299 within an item, but not the entire word. Return -1 if not.
6300 Otherwise, return the starting position of the field, where 0 is the
6303 *PLEN is set to the length of the field. */
6306 get_pos_from_mask (m, plen)
6307 unsigned HOST_WIDE_INT m;
6310 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6311 int pos = exact_log2 (m & - m);
6316 /* Now shift off the low-order zero bits and see if we have a power of
6318 *plen = exact_log2 ((m >> pos) + 1);
6326 /* See if X can be simplified knowing that we will only refer to it in
6327 MODE and will only refer to those bits that are nonzero in MASK.
6328 If other bits are being computed or if masking operations are done
6329 that select a superset of the bits in MASK, they can sometimes be
6332 Return a possibly simplified expression, but always convert X to
6333 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6335 Also, if REG is non-zero and X is a register equal in value to REG,
6338 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6339 are all off in X. This is used when X will be complemented, by either
6340 NOT, NEG, or XOR. */
6343 force_to_mode (x, mode, mask, reg, just_select)
6345 enum machine_mode mode;
6346 unsigned HOST_WIDE_INT mask;
6350 enum rtx_code code = GET_CODE (x);
6351 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6352 enum machine_mode op_mode;
6353 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6356 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6357 code below will do the wrong thing since the mode of such an
6358 expression is VOIDmode.
6360 Also do nothing if X is a CLOBBER; this can happen if X was
6361 the return value from a call to gen_lowpart_for_combine. */
6362 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6365 /* We want to perform the operation is its present mode unless we know
6366 that the operation is valid in MODE, in which case we do the operation
6368 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6369 && code_to_optab[(int) code] != 0
6370 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6371 != CODE_FOR_nothing))
6372 ? mode : GET_MODE (x));
6374 /* It is not valid to do a right-shift in a narrower mode
6375 than the one it came in with. */
6376 if ((code == LSHIFTRT || code == ASHIFTRT)
6377 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6378 op_mode = GET_MODE (x);
6380 /* Truncate MASK to fit OP_MODE. */
6382 mask &= GET_MODE_MASK (op_mode);
6384 /* When we have an arithmetic operation, or a shift whose count we
6385 do not know, we need to assume that all bit the up to the highest-order
6386 bit in MASK will be needed. This is how we form such a mask. */
6388 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6389 ? GET_MODE_MASK (op_mode)
6390 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6392 fuller_mask = ~ (HOST_WIDE_INT) 0;
6394 /* Determine what bits of X are guaranteed to be (non)zero. */
6395 nonzero = nonzero_bits (x, mode);
6397 /* If none of the bits in X are needed, return a zero. */
6398 if (! just_select && (nonzero & mask) == 0)
6401 /* If X is a CONST_INT, return a new one. Do this here since the
6402 test below will fail. */
6403 if (GET_CODE (x) == CONST_INT)
6405 HOST_WIDE_INT cval = INTVAL (x) & mask;
6406 int width = GET_MODE_BITSIZE (mode);
6408 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6409 number, sign extend it. */
6410 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6411 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6412 cval |= (HOST_WIDE_INT) -1 << width;
6414 return GEN_INT (cval);
6417 /* If X is narrower than MODE and we want all the bits in X's mode, just
6418 get X in the proper mode. */
6419 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6420 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6421 return gen_lowpart_for_combine (mode, x);
6423 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6424 MASK are already known to be zero in X, we need not do anything. */
6425 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6431 /* If X is a (clobber (const_int)), return it since we know we are
6432 generating something that won't match. */
6436 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6437 spanned the boundary of the MEM. If we are now masking so it is
6438 within that boundary, we don't need the USE any more. */
6439 if (! BITS_BIG_ENDIAN
6440 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6441 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6448 x = expand_compound_operation (x);
6449 if (GET_CODE (x) != code)
6450 return force_to_mode (x, mode, mask, reg, next_select);
6454 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6455 || rtx_equal_p (reg, get_last_value (x))))
6460 if (subreg_lowpart_p (x)
6461 /* We can ignore the effect of this SUBREG if it narrows the mode or
6462 if the constant masks to zero all the bits the mode doesn't
6464 && ((GET_MODE_SIZE (GET_MODE (x))
6465 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6467 & GET_MODE_MASK (GET_MODE (x))
6468 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6469 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6473 /* If this is an AND with a constant, convert it into an AND
6474 whose constant is the AND of that constant with MASK. If it
6475 remains an AND of MASK, delete it since it is redundant. */
6477 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6479 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6480 mask & INTVAL (XEXP (x, 1)));
6482 /* If X is still an AND, see if it is an AND with a mask that
6483 is just some low-order bits. If so, and it is MASK, we don't
6486 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6487 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6490 /* If it remains an AND, try making another AND with the bits
6491 in the mode mask that aren't in MASK turned on. If the
6492 constant in the AND is wide enough, this might make a
6493 cheaper constant. */
6495 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6496 && GET_MODE_MASK (GET_MODE (x)) != mask
6497 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6499 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6500 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6501 int width = GET_MODE_BITSIZE (GET_MODE (x));
6504 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6505 number, sign extend it. */
6506 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6507 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6508 cval |= (HOST_WIDE_INT) -1 << width;
6510 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6511 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6521 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6522 low-order bits (as in an alignment operation) and FOO is already
6523 aligned to that boundary, mask C1 to that boundary as well.
6524 This may eliminate that PLUS and, later, the AND. */
6527 int width = GET_MODE_BITSIZE (mode);
6528 unsigned HOST_WIDE_INT smask = mask;
6530 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6531 number, sign extend it. */
6533 if (width < HOST_BITS_PER_WIDE_INT
6534 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6535 smask |= (HOST_WIDE_INT) -1 << width;
6537 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6538 && exact_log2 (- smask) >= 0)
6542 && (XEXP (x, 0) == stack_pointer_rtx
6543 || XEXP (x, 0) == frame_pointer_rtx))
6545 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6546 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6548 sp_mask &= ~ (sp_alignment - 1);
6549 if ((sp_mask & ~ smask) == 0
6550 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6551 return force_to_mode (plus_constant (XEXP (x, 0),
6552 ((INTVAL (XEXP (x, 1)) -
6553 STACK_BIAS) & smask)
6555 mode, smask, reg, next_select);
6558 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6559 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6560 return force_to_mode (plus_constant (XEXP (x, 0),
6561 (INTVAL (XEXP (x, 1))
6563 mode, smask, reg, next_select);
6567 /* ... fall through ... */
6571 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6572 most significant bit in MASK since carries from those bits will
6573 affect the bits we are interested in. */
6579 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6580 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6581 operation which may be a bitfield extraction. Ensure that the
6582 constant we form is not wider than the mode of X. */
6584 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6585 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6586 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6587 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6588 && GET_CODE (XEXP (x, 1)) == CONST_INT
6589 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6590 + floor_log2 (INTVAL (XEXP (x, 1))))
6591 < GET_MODE_BITSIZE (GET_MODE (x)))
6592 && (INTVAL (XEXP (x, 1))
6593 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6595 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6596 << INTVAL (XEXP (XEXP (x, 0), 1)));
6597 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6598 XEXP (XEXP (x, 0), 0), temp);
6599 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6600 XEXP (XEXP (x, 0), 1));
6601 return force_to_mode (x, mode, mask, reg, next_select);
6605 /* For most binary operations, just propagate into the operation and
6606 change the mode if we have an operation of that mode. */
6608 op0 = gen_lowpart_for_combine (op_mode,
6609 force_to_mode (XEXP (x, 0), mode, mask,
6611 op1 = gen_lowpart_for_combine (op_mode,
6612 force_to_mode (XEXP (x, 1), mode, mask,
6615 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6616 MASK since OP1 might have been sign-extended but we never want
6617 to turn on extra bits, since combine might have previously relied
6618 on them being off. */
6619 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6620 && (INTVAL (op1) & mask) != 0)
6621 op1 = GEN_INT (INTVAL (op1) & mask);
6623 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6624 x = gen_binary (code, op_mode, op0, op1);
6628 /* For left shifts, do the same, but just for the first operand.
6629 However, we cannot do anything with shifts where we cannot
6630 guarantee that the counts are smaller than the size of the mode
6631 because such a count will have a different meaning in a
6634 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6635 && INTVAL (XEXP (x, 1)) >= 0
6636 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6637 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6638 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6639 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6642 /* If the shift count is a constant and we can do arithmetic in
6643 the mode of the shift, refine which bits we need. Otherwise, use the
6644 conservative form of the mask. */
6645 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6646 && INTVAL (XEXP (x, 1)) >= 0
6647 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6648 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6649 mask >>= INTVAL (XEXP (x, 1));
6653 op0 = gen_lowpart_for_combine (op_mode,
6654 force_to_mode (XEXP (x, 0), op_mode,
6655 mask, reg, next_select));
6657 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6658 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6662 /* Here we can only do something if the shift count is a constant,
6663 this shift constant is valid for the host, and we can do arithmetic
6666 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6667 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6668 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6670 rtx inner = XEXP (x, 0);
6672 /* Select the mask of the bits we need for the shift operand. */
6673 mask <<= INTVAL (XEXP (x, 1));
6675 /* We can only change the mode of the shift if we can do arithmetic
6676 in the mode of the shift and MASK is no wider than the width of
6678 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6679 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6680 op_mode = GET_MODE (x);
6682 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6684 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6685 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6688 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6689 shift and AND produces only copies of the sign bit (C2 is one less
6690 than a power of two), we can do this with just a shift. */
6692 if (GET_CODE (x) == LSHIFTRT
6693 && GET_CODE (XEXP (x, 1)) == CONST_INT
6694 && ((INTVAL (XEXP (x, 1))
6695 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6696 >= GET_MODE_BITSIZE (GET_MODE (x)))
6697 && exact_log2 (mask + 1) >= 0
6698 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6699 >= exact_log2 (mask + 1)))
6700 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6701 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6702 - exact_log2 (mask + 1)));
6707 /* If we are just looking for the sign bit, we don't need this shift at
6708 all, even if it has a variable count. */
6709 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6710 && (mask == ((unsigned HOST_WIDE_INT) 1
6711 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6712 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6714 /* If this is a shift by a constant, get a mask that contains those bits
6715 that are not copies of the sign bit. We then have two cases: If
6716 MASK only includes those bits, this can be a logical shift, which may
6717 allow simplifications. If MASK is a single-bit field not within
6718 those bits, we are requesting a copy of the sign bit and hence can
6719 shift the sign bit to the appropriate location. */
6721 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6722 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6726 /* If the considered data is wider then HOST_WIDE_INT, we can't
6727 represent a mask for all its bits in a single scalar.
6728 But we only care about the lower bits, so calculate these. */
6730 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6732 nonzero = ~ (HOST_WIDE_INT) 0;
6734 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6735 is the number of bits a full-width mask would have set.
6736 We need only shift if these are fewer than nonzero can
6737 hold. If not, we must keep all bits set in nonzero. */
6739 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6740 < HOST_BITS_PER_WIDE_INT)
6741 nonzero >>= INTVAL (XEXP (x, 1))
6742 + HOST_BITS_PER_WIDE_INT
6743 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6747 nonzero = GET_MODE_MASK (GET_MODE (x));
6748 nonzero >>= INTVAL (XEXP (x, 1));
6751 if ((mask & ~ nonzero) == 0
6752 || (i = exact_log2 (mask)) >= 0)
6754 x = simplify_shift_const
6755 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6756 i < 0 ? INTVAL (XEXP (x, 1))
6757 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6759 if (GET_CODE (x) != ASHIFTRT)
6760 return force_to_mode (x, mode, mask, reg, next_select);
6764 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6765 even if the shift count isn't a constant. */
6767 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6771 /* If this is a zero- or sign-extension operation that just affects bits
6772 we don't care about, remove it. Be sure the call above returned
6773 something that is still a shift. */
6775 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6776 && GET_CODE (XEXP (x, 1)) == CONST_INT
6777 && INTVAL (XEXP (x, 1)) >= 0
6778 && (INTVAL (XEXP (x, 1))
6779 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6780 && GET_CODE (XEXP (x, 0)) == ASHIFT
6781 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6782 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6783 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6790 /* If the shift count is constant and we can do computations
6791 in the mode of X, compute where the bits we care about are.
6792 Otherwise, we can't do anything. Don't change the mode of
6793 the shift or propagate MODE into the shift, though. */
6794 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6795 && INTVAL (XEXP (x, 1)) >= 0)
6797 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6798 GET_MODE (x), GEN_INT (mask),
6800 if (temp && GET_CODE(temp) == CONST_INT)
6802 force_to_mode (XEXP (x, 0), GET_MODE (x),
6803 INTVAL (temp), reg, next_select));
6808 /* If we just want the low-order bit, the NEG isn't needed since it
6809 won't change the low-order bit. */
6811 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6813 /* We need any bits less significant than the most significant bit in
6814 MASK since carries from those bits will affect the bits we are
6820 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6821 same as the XOR case above. Ensure that the constant we form is not
6822 wider than the mode of X. */
6824 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6825 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6826 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6827 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6828 < GET_MODE_BITSIZE (GET_MODE (x)))
6829 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6831 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6832 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6833 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6835 return force_to_mode (x, mode, mask, reg, next_select);
6838 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6839 use the full mask inside the NOT. */
6843 op0 = gen_lowpart_for_combine (op_mode,
6844 force_to_mode (XEXP (x, 0), mode, mask,
6846 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6847 x = gen_unary (code, op_mode, op_mode, op0);
6851 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6852 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6853 which is equal to STORE_FLAG_VALUE. */
6854 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6855 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6856 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6857 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6862 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6863 written in a narrower mode. We play it safe and do not do so. */
6866 gen_lowpart_for_combine (GET_MODE (x),
6867 force_to_mode (XEXP (x, 1), mode,
6868 mask, reg, next_select)));
6870 gen_lowpart_for_combine (GET_MODE (x),
6871 force_to_mode (XEXP (x, 2), mode,
6872 mask, reg,next_select)));
6879 /* Ensure we return a value of the proper mode. */
6880 return gen_lowpart_for_combine (mode, x);
6883 /* Return nonzero if X is an expression that has one of two values depending on
6884 whether some other value is zero or nonzero. In that case, we return the
6885 value that is being tested, *PTRUE is set to the value if the rtx being
6886 returned has a nonzero value, and *PFALSE is set to the other alternative.
6888 If we return zero, we set *PTRUE and *PFALSE to X. */
6891 if_then_else_cond (x, ptrue, pfalse)
6893 rtx *ptrue, *pfalse;
6895 enum machine_mode mode = GET_MODE (x);
6896 enum rtx_code code = GET_CODE (x);
6897 int size = GET_MODE_BITSIZE (mode);
6898 rtx cond0, cond1, true0, true1, false0, false1;
6899 unsigned HOST_WIDE_INT nz;
6901 /* If this is a unary operation whose operand has one of two values, apply
6902 our opcode to compute those values. */
6903 if (GET_RTX_CLASS (code) == '1'
6904 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6906 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6907 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6911 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6912 make can't possibly match and would suppress other optimizations. */
6913 else if (code == COMPARE)
6916 /* If this is a binary operation, see if either side has only one of two
6917 values. If either one does or if both do and they are conditional on
6918 the same value, compute the new true and false values. */
6919 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6920 || GET_RTX_CLASS (code) == '<')
6922 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6923 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6925 if ((cond0 != 0 || cond1 != 0)
6926 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6928 /* If if_then_else_cond returned zero, then true/false are the
6929 same rtl. We must copy one of them to prevent invalid rtl
6932 true0 = copy_rtx (true0);
6933 else if (cond1 == 0)
6934 true1 = copy_rtx (true1);
6936 *ptrue = gen_binary (code, mode, true0, true1);
6937 *pfalse = gen_binary (code, mode, false0, false1);
6938 return cond0 ? cond0 : cond1;
6941 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6942 operands is zero when the other is non-zero, and vice-versa,
6943 and STORE_FLAG_VALUE is 1 or -1. */
6945 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6946 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6948 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6950 rtx op0 = XEXP (XEXP (x, 0), 1);
6951 rtx op1 = XEXP (XEXP (x, 1), 1);
6953 cond0 = XEXP (XEXP (x, 0), 0);
6954 cond1 = XEXP (XEXP (x, 1), 0);
6956 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6957 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6958 && reversible_comparison_p (cond1)
6959 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6960 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6961 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6962 || ((swap_condition (GET_CODE (cond0))
6963 == reverse_condition (GET_CODE (cond1)))
6964 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6965 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6966 && ! side_effects_p (x))
6968 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6969 *pfalse = gen_binary (MULT, mode,
6971 ? gen_unary (NEG, mode, mode, op1) : op1),
6977 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6979 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6980 && (code == MULT || code == AND || code == UMIN)
6981 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6983 cond0 = XEXP (XEXP (x, 0), 0);
6984 cond1 = XEXP (XEXP (x, 1), 0);
6986 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6987 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6988 && reversible_comparison_p (cond1)
6989 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6990 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6991 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6992 || ((swap_condition (GET_CODE (cond0))
6993 == reverse_condition (GET_CODE (cond1)))
6994 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6995 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6996 && ! side_effects_p (x))
6998 *ptrue = *pfalse = const0_rtx;
7004 else if (code == IF_THEN_ELSE)
7006 /* If we have IF_THEN_ELSE already, extract the condition and
7007 canonicalize it if it is NE or EQ. */
7008 cond0 = XEXP (x, 0);
7009 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7010 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7011 return XEXP (cond0, 0);
7012 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7014 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7015 return XEXP (cond0, 0);
7021 /* If X is a normal SUBREG with both inner and outer modes integral,
7022 we can narrow both the true and false values of the inner expression,
7023 if there is a condition. */
7024 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7025 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7026 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7027 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7030 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7032 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
7037 /* If X is a constant, this isn't special and will cause confusions
7038 if we treat it as such. Likewise if it is equivalent to a constant. */
7039 else if (CONSTANT_P (x)
7040 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7043 /* If X is known to be either 0 or -1, those are the true and
7044 false values when testing X. */
7045 else if (num_sign_bit_copies (x, mode) == size)
7047 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7051 /* Likewise for 0 or a single bit. */
7052 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7054 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7058 /* Otherwise fail; show no condition with true and false values the same. */
7059 *ptrue = *pfalse = x;
7063 /* Return the value of expression X given the fact that condition COND
7064 is known to be true when applied to REG as its first operand and VAL
7065 as its second. X is known to not be shared and so can be modified in
7068 We only handle the simplest cases, and specifically those cases that
7069 arise with IF_THEN_ELSE expressions. */
7072 known_cond (x, cond, reg, val)
7077 enum rtx_code code = GET_CODE (x);
7082 if (side_effects_p (x))
7085 if (cond == EQ && rtx_equal_p (x, reg))
7088 /* If X is (abs REG) and we know something about REG's relationship
7089 with zero, we may be able to simplify this. */
7091 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7094 case GE: case GT: case EQ:
7097 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7103 /* The only other cases we handle are MIN, MAX, and comparisons if the
7104 operands are the same as REG and VAL. */
7106 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7108 if (rtx_equal_p (XEXP (x, 0), val))
7109 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7111 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7113 if (GET_RTX_CLASS (code) == '<')
7114 return (comparison_dominates_p (cond, code) ? const_true_rtx
7115 : (comparison_dominates_p (cond,
7116 reverse_condition (code))
7119 else if (code == SMAX || code == SMIN
7120 || code == UMIN || code == UMAX)
7122 int unsignedp = (code == UMIN || code == UMAX);
7124 if (code == SMAX || code == UMAX)
7125 cond = reverse_condition (cond);
7130 return unsignedp ? x : XEXP (x, 1);
7132 return unsignedp ? x : XEXP (x, 0);
7134 return unsignedp ? XEXP (x, 1) : x;
7136 return unsignedp ? XEXP (x, 0) : x;
7144 fmt = GET_RTX_FORMAT (code);
7145 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7148 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7149 else if (fmt[i] == 'E')
7150 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7151 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7158 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7159 assignment as a field assignment. */
7162 rtx_equal_for_field_assignment_p (x, y)
7166 if (x == y || rtx_equal_p (x, y))
7169 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7172 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7173 Note that all SUBREGs of MEM are paradoxical; otherwise they
7174 would have been rewritten. */
7175 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7176 && GET_CODE (SUBREG_REG (y)) == MEM
7177 && rtx_equal_p (SUBREG_REG (y),
7178 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7181 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7182 && GET_CODE (SUBREG_REG (x)) == MEM
7183 && rtx_equal_p (SUBREG_REG (x),
7184 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7187 /* We used to see if get_last_value of X and Y were the same but that's
7188 not correct. In one direction, we'll cause the assignment to have
7189 the wrong destination and in the case, we'll import a register into this
7190 insn that might have already have been dead. So fail if none of the
7191 above cases are true. */
7195 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7196 Return that assignment if so.
7198 We only handle the most common cases. */
7201 make_field_assignment (x)
7204 rtx dest = SET_DEST (x);
7205 rtx src = SET_SRC (x);
7211 enum machine_mode mode;
7213 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7214 a clear of a one-bit field. We will have changed it to
7215 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7218 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7219 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7220 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7221 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7223 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7226 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7230 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7231 && subreg_lowpart_p (XEXP (src, 0))
7232 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7233 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7234 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7235 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7236 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7238 assign = make_extraction (VOIDmode, dest, 0,
7239 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7242 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7246 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7248 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7249 && XEXP (XEXP (src, 0), 0) == const1_rtx
7250 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7252 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7255 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7259 /* The other case we handle is assignments into a constant-position
7260 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7261 a mask that has all one bits except for a group of zero bits and
7262 OTHER is known to have zeros where C1 has ones, this is such an
7263 assignment. Compute the position and length from C1. Shift OTHER
7264 to the appropriate position, force it to the required mode, and
7265 make the extraction. Check for the AND in both operands. */
7267 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7270 rhs = expand_compound_operation (XEXP (src, 0));
7271 lhs = expand_compound_operation (XEXP (src, 1));
7273 if (GET_CODE (rhs) == AND
7274 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7275 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7276 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7277 else if (GET_CODE (lhs) == AND
7278 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7279 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7280 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7284 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7285 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7286 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7287 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7290 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7294 /* The mode to use for the source is the mode of the assignment, or of
7295 what is inside a possible STRICT_LOW_PART. */
7296 mode = (GET_CODE (assign) == STRICT_LOW_PART
7297 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7299 /* Shift OTHER right POS places and make it the source, restricting it
7300 to the proper length and mode. */
7302 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7303 GET_MODE (src), other, pos),
7305 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7306 ? GET_MODE_MASK (mode)
7307 : ((HOST_WIDE_INT) 1 << len) - 1,
7310 return gen_rtx_combine (SET, VOIDmode, assign, src);
7313 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7317 apply_distributive_law (x)
7320 enum rtx_code code = GET_CODE (x);
7321 rtx lhs, rhs, other;
7323 enum rtx_code inner_code;
7325 /* Distributivity is not true for floating point.
7326 It can change the value. So don't do it.
7327 -- rms and moshier@world.std.com. */
7328 if (FLOAT_MODE_P (GET_MODE (x)))
7331 /* The outer operation can only be one of the following: */
7332 if (code != IOR && code != AND && code != XOR
7333 && code != PLUS && code != MINUS)
7336 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7338 /* If either operand is a primitive we can't do anything, so get out
7340 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7341 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7344 lhs = expand_compound_operation (lhs);
7345 rhs = expand_compound_operation (rhs);
7346 inner_code = GET_CODE (lhs);
7347 if (inner_code != GET_CODE (rhs))
7350 /* See if the inner and outer operations distribute. */
7357 /* These all distribute except over PLUS. */
7358 if (code == PLUS || code == MINUS)
7363 if (code != PLUS && code != MINUS)
7368 /* This is also a multiply, so it distributes over everything. */
7372 /* Non-paradoxical SUBREGs distributes over all operations, provided
7373 the inner modes and word numbers are the same, this is an extraction
7374 of a low-order part, we don't convert an fp operation to int or
7375 vice versa, and we would not be converting a single-word
7376 operation into a multi-word operation. The latter test is not
7377 required, but it prevents generating unneeded multi-word operations.
7378 Some of the previous tests are redundant given the latter test, but
7379 are retained because they are required for correctness.
7381 We produce the result slightly differently in this case. */
7383 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7384 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7385 || ! subreg_lowpart_p (lhs)
7386 || (GET_MODE_CLASS (GET_MODE (lhs))
7387 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7388 || (GET_MODE_SIZE (GET_MODE (lhs))
7389 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7390 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7393 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7394 SUBREG_REG (lhs), SUBREG_REG (rhs));
7395 return gen_lowpart_for_combine (GET_MODE (x), tem);
7401 /* Set LHS and RHS to the inner operands (A and B in the example
7402 above) and set OTHER to the common operand (C in the example).
7403 These is only one way to do this unless the inner operation is
7405 if (GET_RTX_CLASS (inner_code) == 'c'
7406 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7407 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7408 else if (GET_RTX_CLASS (inner_code) == 'c'
7409 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7410 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7411 else if (GET_RTX_CLASS (inner_code) == 'c'
7412 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7413 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7414 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7415 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7419 /* Form the new inner operation, seeing if it simplifies first. */
7420 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7422 /* There is one exception to the general way of distributing:
7423 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7424 if (code == XOR && inner_code == IOR)
7427 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7430 /* We may be able to continuing distributing the result, so call
7431 ourselves recursively on the inner operation before forming the
7432 outer operation, which we return. */
7433 return gen_binary (inner_code, GET_MODE (x),
7434 apply_distributive_law (tem), other);
7437 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7440 Return an equivalent form, if different from X. Otherwise, return X. If
7441 X is zero, we are to always construct the equivalent form. */
7444 simplify_and_const_int (x, mode, varop, constop)
7446 enum machine_mode mode;
7448 unsigned HOST_WIDE_INT constop;
7450 unsigned HOST_WIDE_INT nonzero;
7453 /* Simplify VAROP knowing that we will be only looking at some of the
7455 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7457 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7458 CONST_INT, we are done. */
7459 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7462 /* See what bits may be nonzero in VAROP. Unlike the general case of
7463 a call to nonzero_bits, here we don't care about bits outside
7466 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7467 nonzero = trunc_int_for_mode (nonzero, mode);
7469 /* Turn off all bits in the constant that are known to already be zero.
7470 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7471 which is tested below. */
7475 /* If we don't have any bits left, return zero. */
7479 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7480 a power of two, we can replace this with a ASHIFT. */
7481 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7482 && (i = exact_log2 (constop)) >= 0)
7483 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7485 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7486 or XOR, then try to apply the distributive law. This may eliminate
7487 operations if either branch can be simplified because of the AND.
7488 It may also make some cases more complex, but those cases probably
7489 won't match a pattern either with or without this. */
7491 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7493 gen_lowpart_for_combine
7495 apply_distributive_law
7496 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7497 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7498 XEXP (varop, 0), constop),
7499 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7500 XEXP (varop, 1), constop))));
7502 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7503 if we already had one (just check for the simplest cases). */
7504 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7505 && GET_MODE (XEXP (x, 0)) == mode
7506 && SUBREG_REG (XEXP (x, 0)) == varop)
7507 varop = XEXP (x, 0);
7509 varop = gen_lowpart_for_combine (mode, varop);
7511 /* If we can't make the SUBREG, try to return what we were given. */
7512 if (GET_CODE (varop) == CLOBBER)
7513 return x ? x : varop;
7515 /* If we are only masking insignificant bits, return VAROP. */
7516 if (constop == nonzero)
7519 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7520 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7521 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7525 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7526 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7527 SUBST (XEXP (x, 1), GEN_INT (constop));
7529 SUBST (XEXP (x, 0), varop);
7535 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7536 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7537 is less useful. We can't allow both, because that results in exponential
7538 run time recursion. There is a nullstone testcase that triggered
7539 this. This macro avoids accidental uses of num_sign_bit_copies. */
7540 #define num_sign_bit_copies()
7542 /* Given an expression, X, compute which bits in X can be non-zero.
7543 We don't care about bits outside of those defined in MODE.
7545 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7546 a shift, AND, or zero_extract, we can do better. */
7548 static unsigned HOST_WIDE_INT
7549 nonzero_bits (x, mode)
7551 enum machine_mode mode;
7553 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7554 unsigned HOST_WIDE_INT inner_nz;
7556 int mode_width = GET_MODE_BITSIZE (mode);
7559 /* For floating-point values, assume all bits are needed. */
7560 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7563 /* If X is wider than MODE, use its mode instead. */
7564 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7566 mode = GET_MODE (x);
7567 nonzero = GET_MODE_MASK (mode);
7568 mode_width = GET_MODE_BITSIZE (mode);
7571 if (mode_width > HOST_BITS_PER_WIDE_INT)
7572 /* Our only callers in this case look for single bit values. So
7573 just return the mode mask. Those tests will then be false. */
7576 #ifndef WORD_REGISTER_OPERATIONS
7577 /* If MODE is wider than X, but both are a single word for both the host
7578 and target machines, we can compute this from which bits of the
7579 object might be nonzero in its own mode, taking into account the fact
7580 that on many CISC machines, accessing an object in a wider mode
7581 causes the high-order bits to become undefined. So they are
7582 not known to be zero. */
7584 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7585 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7586 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7587 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7589 nonzero &= nonzero_bits (x, GET_MODE (x));
7590 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7595 code = GET_CODE (x);
7599 #ifdef POINTERS_EXTEND_UNSIGNED
7600 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7601 all the bits above ptr_mode are known to be zero. */
7602 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7603 && REGNO_POINTER_FLAG (REGNO (x)))
7604 nonzero &= GET_MODE_MASK (ptr_mode);
7607 #ifdef STACK_BOUNDARY
7608 /* If this is the stack pointer, we may know something about its
7609 alignment. If PUSH_ROUNDING is defined, it is possible for the
7610 stack to be momentarily aligned only to that amount, so we pick
7611 the least alignment. */
7613 /* We can't check for arg_pointer_rtx here, because it is not
7614 guaranteed to have as much alignment as the stack pointer.
7615 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7616 alignment but the argument pointer has only 64 bit alignment. */
7618 if ((x == frame_pointer_rtx
7619 || x == stack_pointer_rtx
7620 || x == hard_frame_pointer_rtx
7621 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7622 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7628 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7630 #ifdef PUSH_ROUNDING
7631 if (REGNO (x) == STACK_POINTER_REGNUM)
7632 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7635 /* We must return here, otherwise we may get a worse result from
7636 one of the choices below. There is nothing useful below as
7637 far as the stack pointer is concerned. */
7638 return nonzero &= ~ (sp_alignment - 1);
7642 /* If X is a register whose nonzero bits value is current, use it.
7643 Otherwise, if X is a register whose value we can find, use that
7644 value. Otherwise, use the previously-computed global nonzero bits
7645 for this register. */
7647 if (reg_last_set_value[REGNO (x)] != 0
7648 && reg_last_set_mode[REGNO (x)] == mode
7649 && (reg_last_set_label[REGNO (x)] == label_tick
7650 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7651 && REG_N_SETS (REGNO (x)) == 1
7652 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7654 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7655 return reg_last_set_nonzero_bits[REGNO (x)];
7657 tem = get_last_value (x);
7661 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7662 /* If X is narrower than MODE and TEM is a non-negative
7663 constant that would appear negative in the mode of X,
7664 sign-extend it for use in reg_nonzero_bits because some
7665 machines (maybe most) will actually do the sign-extension
7666 and this is the conservative approach.
7668 ??? For 2.5, try to tighten up the MD files in this regard
7669 instead of this kludge. */
7671 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7672 && GET_CODE (tem) == CONST_INT
7674 && 0 != (INTVAL (tem)
7675 & ((HOST_WIDE_INT) 1
7676 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7677 tem = GEN_INT (INTVAL (tem)
7678 | ((HOST_WIDE_INT) (-1)
7679 << GET_MODE_BITSIZE (GET_MODE (x))));
7681 return nonzero_bits (tem, mode);
7683 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7684 return reg_nonzero_bits[REGNO (x)] & nonzero;
7689 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7690 /* If X is negative in MODE, sign-extend the value. */
7691 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7692 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7693 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7699 #ifdef LOAD_EXTEND_OP
7700 /* In many, if not most, RISC machines, reading a byte from memory
7701 zeros the rest of the register. Noticing that fact saves a lot
7702 of extra zero-extends. */
7703 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7704 nonzero &= GET_MODE_MASK (GET_MODE (x));
7714 /* If this produces an integer result, we know which bits are set.
7715 Code here used to clear bits outside the mode of X, but that is
7718 if (GET_MODE_CLASS (mode) == MODE_INT
7719 && mode_width <= HOST_BITS_PER_WIDE_INT)
7720 nonzero = STORE_FLAG_VALUE;
7725 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7726 and num_sign_bit_copies. */
7727 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7728 == GET_MODE_BITSIZE (GET_MODE (x)))
7732 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7733 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7738 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7739 and num_sign_bit_copies. */
7740 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7741 == GET_MODE_BITSIZE (GET_MODE (x)))
7747 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7751 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7752 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7753 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7757 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7758 Otherwise, show all the bits in the outer mode but not the inner
7760 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7761 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7763 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7765 & (((HOST_WIDE_INT) 1
7766 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7767 inner_nz |= (GET_MODE_MASK (mode)
7768 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7771 nonzero &= inner_nz;
7775 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7776 & nonzero_bits (XEXP (x, 1), mode));
7780 case UMIN: case UMAX: case SMIN: case SMAX:
7781 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7782 | nonzero_bits (XEXP (x, 1), mode));
7785 case PLUS: case MINUS:
7787 case DIV: case UDIV:
7788 case MOD: case UMOD:
7789 /* We can apply the rules of arithmetic to compute the number of
7790 high- and low-order zero bits of these operations. We start by
7791 computing the width (position of the highest-order non-zero bit)
7792 and the number of low-order zero bits for each value. */
7794 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7795 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7796 int width0 = floor_log2 (nz0) + 1;
7797 int width1 = floor_log2 (nz1) + 1;
7798 int low0 = floor_log2 (nz0 & -nz0);
7799 int low1 = floor_log2 (nz1 & -nz1);
7800 HOST_WIDE_INT op0_maybe_minusp
7801 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7802 HOST_WIDE_INT op1_maybe_minusp
7803 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7804 int result_width = mode_width;
7812 && (XEXP (x, 0) == stack_pointer_rtx
7813 || XEXP (x, 0) == frame_pointer_rtx)
7814 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7816 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7818 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7819 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7820 width0 = floor_log2 (nz0) + 1;
7821 width1 = floor_log2 (nz1) + 1;
7822 low0 = floor_log2 (nz0 & -nz0);
7823 low1 = floor_log2 (nz1 & -nz1);
7826 result_width = MAX (width0, width1) + 1;
7827 result_low = MIN (low0, low1);
7830 result_low = MIN (low0, low1);
7833 result_width = width0 + width1;
7834 result_low = low0 + low1;
7837 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7838 result_width = width0;
7841 result_width = width0;
7844 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7845 result_width = MIN (width0, width1);
7846 result_low = MIN (low0, low1);
7849 result_width = MIN (width0, width1);
7850 result_low = MIN (low0, low1);
7856 if (result_width < mode_width)
7857 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7860 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7865 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7866 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7867 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7871 /* If this is a SUBREG formed for a promoted variable that has
7872 been zero-extended, we know that at least the high-order bits
7873 are zero, though others might be too. */
7875 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7876 nonzero = (GET_MODE_MASK (GET_MODE (x))
7877 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7879 /* If the inner mode is a single word for both the host and target
7880 machines, we can compute this from which bits of the inner
7881 object might be nonzero. */
7882 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7883 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7884 <= HOST_BITS_PER_WIDE_INT))
7886 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7888 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7889 /* If this is a typical RISC machine, we only have to worry
7890 about the way loads are extended. */
7891 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7893 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7894 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7897 /* On many CISC machines, accessing an object in a wider mode
7898 causes the high-order bits to become undefined. So they are
7899 not known to be zero. */
7900 if (GET_MODE_SIZE (GET_MODE (x))
7901 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7902 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7903 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7912 /* The nonzero bits are in two classes: any bits within MODE
7913 that aren't in GET_MODE (x) are always significant. The rest of the
7914 nonzero bits are those that are significant in the operand of
7915 the shift when shifted the appropriate number of bits. This
7916 shows that high-order bits are cleared by the right shift and
7917 low-order bits by left shifts. */
7918 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7919 && INTVAL (XEXP (x, 1)) >= 0
7920 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7922 enum machine_mode inner_mode = GET_MODE (x);
7923 int width = GET_MODE_BITSIZE (inner_mode);
7924 int count = INTVAL (XEXP (x, 1));
7925 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7926 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7927 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7928 unsigned HOST_WIDE_INT outer = 0;
7930 if (mode_width > width)
7931 outer = (op_nonzero & nonzero & ~ mode_mask);
7933 if (code == LSHIFTRT)
7935 else if (code == ASHIFTRT)
7939 /* If the sign bit may have been nonzero before the shift, we
7940 need to mark all the places it could have been copied to
7941 by the shift as possibly nonzero. */
7942 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7943 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7945 else if (code == ASHIFT)
7948 inner = ((inner << (count % width)
7949 | (inner >> (width - (count % width)))) & mode_mask);
7951 nonzero &= (outer | inner);
7956 /* This is at most the number of bits in the mode. */
7957 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7961 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7962 | nonzero_bits (XEXP (x, 2), mode));
7972 /* See the macro definition above. */
7973 #undef num_sign_bit_copies
7975 /* Return the number of bits at the high-order end of X that are known to
7976 be equal to the sign bit. X will be used in mode MODE; if MODE is
7977 VOIDmode, X will be used in its own mode. The returned value will always
7978 be between 1 and the number of bits in MODE. */
7981 num_sign_bit_copies (x, mode)
7983 enum machine_mode mode;
7985 enum rtx_code code = GET_CODE (x);
7987 int num0, num1, result;
7988 unsigned HOST_WIDE_INT nonzero;
7991 /* If we weren't given a mode, use the mode of X. If the mode is still
7992 VOIDmode, we don't know anything. Likewise if one of the modes is
7995 if (mode == VOIDmode)
7996 mode = GET_MODE (x);
7998 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8001 bitwidth = GET_MODE_BITSIZE (mode);
8003 /* For a smaller object, just ignore the high bits. */
8004 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8005 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
8006 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
8008 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8010 #ifndef WORD_REGISTER_OPERATIONS
8011 /* If this machine does not do all register operations on the entire
8012 register and MODE is wider than the mode of X, we can say nothing
8013 at all about the high-order bits. */
8016 /* Likewise on machines that do, if the mode of the object is smaller
8017 than a word and loads of that size don't sign extend, we can say
8018 nothing about the high order bits. */
8019 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8020 #ifdef LOAD_EXTEND_OP
8021 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8032 #ifdef POINTERS_EXTEND_UNSIGNED
8033 /* If pointers extend signed and this is a pointer in Pmode, say that
8034 all the bits above ptr_mode are known to be sign bit copies. */
8035 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8036 && REGNO_POINTER_FLAG (REGNO (x)))
8037 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8040 if (reg_last_set_value[REGNO (x)] != 0
8041 && reg_last_set_mode[REGNO (x)] == mode
8042 && (reg_last_set_label[REGNO (x)] == label_tick
8043 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8044 && REG_N_SETS (REGNO (x)) == 1
8045 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8047 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8048 return reg_last_set_sign_bit_copies[REGNO (x)];
8050 tem = get_last_value (x);
8052 return num_sign_bit_copies (tem, mode);
8054 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8055 return reg_sign_bit_copies[REGNO (x)];
8059 #ifdef LOAD_EXTEND_OP
8060 /* Some RISC machines sign-extend all loads of smaller than a word. */
8061 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8062 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
8067 /* If the constant is negative, take its 1's complement and remask.
8068 Then see how many zero bits we have. */
8069 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8070 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8071 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8072 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
8074 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8077 /* If this is a SUBREG for a promoted object that is sign-extended
8078 and we are looking at it in a wider mode, we know that at least the
8079 high-order bits are known to be sign bit copies. */
8081 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8082 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8083 num_sign_bit_copies (SUBREG_REG (x), mode));
8085 /* For a smaller object, just ignore the high bits. */
8086 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8088 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8089 return MAX (1, (num0
8090 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8094 #ifdef WORD_REGISTER_OPERATIONS
8095 #ifdef LOAD_EXTEND_OP
8096 /* For paradoxical SUBREGs on machines where all register operations
8097 affect the entire register, just look inside. Note that we are
8098 passing MODE to the recursive call, so the number of sign bit copies
8099 will remain relative to that mode, not the inner mode. */
8101 /* This works only if loads sign extend. Otherwise, if we get a
8102 reload for the inner part, it may be loaded from the stack, and
8103 then we lose all sign bit copies that existed before the store
8106 if ((GET_MODE_SIZE (GET_MODE (x))
8107 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8108 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8109 return num_sign_bit_copies (SUBREG_REG (x), mode);
8115 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8116 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
8120 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8121 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8124 /* For a smaller object, just ignore the high bits. */
8125 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8126 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8130 return num_sign_bit_copies (XEXP (x, 0), mode);
8132 case ROTATE: case ROTATERT:
8133 /* If we are rotating left by a number of bits less than the number
8134 of sign bit copies, we can just subtract that amount from the
8136 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8137 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8139 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8140 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8141 : bitwidth - INTVAL (XEXP (x, 1))));
8146 /* In general, this subtracts one sign bit copy. But if the value
8147 is known to be positive, the number of sign bit copies is the
8148 same as that of the input. Finally, if the input has just one bit
8149 that might be nonzero, all the bits are copies of the sign bit. */
8150 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8151 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8152 return num0 > 1 ? num0 - 1 : 1;
8154 nonzero = nonzero_bits (XEXP (x, 0), mode);
8159 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8164 case IOR: case AND: case XOR:
8165 case SMIN: case SMAX: case UMIN: case UMAX:
8166 /* Logical operations will preserve the number of sign-bit copies.
8167 MIN and MAX operations always return one of the operands. */
8168 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8169 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8170 return MIN (num0, num1);
8172 case PLUS: case MINUS:
8173 /* For addition and subtraction, we can have a 1-bit carry. However,
8174 if we are subtracting 1 from a positive number, there will not
8175 be such a carry. Furthermore, if the positive number is known to
8176 be 0 or 1, we know the result is either -1 or 0. */
8178 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8179 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8181 nonzero = nonzero_bits (XEXP (x, 0), mode);
8182 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8183 return (nonzero == 1 || nonzero == 0 ? bitwidth
8184 : bitwidth - floor_log2 (nonzero) - 1);
8187 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8188 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8189 return MAX (1, MIN (num0, num1) - 1);
8192 /* The number of bits of the product is the sum of the number of
8193 bits of both terms. However, unless one of the terms if known
8194 to be positive, we must allow for an additional bit since negating
8195 a negative number can remove one sign bit copy. */
8197 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8198 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8200 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8202 && (bitwidth > HOST_BITS_PER_WIDE_INT
8203 || (((nonzero_bits (XEXP (x, 0), mode)
8204 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8205 && ((nonzero_bits (XEXP (x, 1), mode)
8206 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8209 return MAX (1, result);
8212 /* The result must be <= the first operand. If the first operand
8213 has the high bit set, we know nothing about the number of sign
8215 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8217 else if ((nonzero_bits (XEXP (x, 0), mode)
8218 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8221 return num_sign_bit_copies (XEXP (x, 0), mode);
8224 /* The result must be <= the scond operand. */
8225 return num_sign_bit_copies (XEXP (x, 1), mode);
8228 /* Similar to unsigned division, except that we have to worry about
8229 the case where the divisor is negative, in which case we have
8231 result = num_sign_bit_copies (XEXP (x, 0), mode);
8233 && (bitwidth > HOST_BITS_PER_WIDE_INT
8234 || (nonzero_bits (XEXP (x, 1), mode)
8235 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8241 result = num_sign_bit_copies (XEXP (x, 1), mode);
8243 && (bitwidth > HOST_BITS_PER_WIDE_INT
8244 || (nonzero_bits (XEXP (x, 1), mode)
8245 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8251 /* Shifts by a constant add to the number of bits equal to the
8253 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8254 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8255 && INTVAL (XEXP (x, 1)) > 0)
8256 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8261 /* Left shifts destroy copies. */
8262 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8263 || INTVAL (XEXP (x, 1)) < 0
8264 || INTVAL (XEXP (x, 1)) >= bitwidth)
8267 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8268 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8271 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8272 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8273 return MIN (num0, num1);
8275 case EQ: case NE: case GE: case GT: case LE: case LT:
8276 case GEU: case GTU: case LEU: case LTU:
8277 if (STORE_FLAG_VALUE == -1)
8285 /* If we haven't been able to figure it out by one of the above rules,
8286 see if some of the high-order bits are known to be zero. If so,
8287 count those bits and return one less than that amount. If we can't
8288 safely compute the mask for this mode, always return BITWIDTH. */
8290 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8293 nonzero = nonzero_bits (x, mode);
8294 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8295 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8298 /* Return the number of "extended" bits there are in X, when interpreted
8299 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8300 unsigned quantities, this is the number of high-order zero bits.
8301 For signed quantities, this is the number of copies of the sign bit
8302 minus 1. In both case, this function returns the number of "spare"
8303 bits. For example, if two quantities for which this function returns
8304 at least 1 are added, the addition is known not to overflow.
8306 This function will always return 0 unless called during combine, which
8307 implies that it must be called from a define_split. */
8310 extended_count (x, mode, unsignedp)
8312 enum machine_mode mode;
8315 if (nonzero_sign_valid == 0)
8319 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8320 && (GET_MODE_BITSIZE (mode) - 1
8321 - floor_log2 (nonzero_bits (x, mode))))
8322 : num_sign_bit_copies (x, mode) - 1);
8325 /* This function is called from `simplify_shift_const' to merge two
8326 outer operations. Specifically, we have already found that we need
8327 to perform operation *POP0 with constant *PCONST0 at the outermost
8328 position. We would now like to also perform OP1 with constant CONST1
8329 (with *POP0 being done last).
8331 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8332 the resulting operation. *PCOMP_P is set to 1 if we would need to
8333 complement the innermost operand, otherwise it is unchanged.
8335 MODE is the mode in which the operation will be done. No bits outside
8336 the width of this mode matter. It is assumed that the width of this mode
8337 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8339 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8340 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8341 result is simply *PCONST0.
8343 If the resulting operation cannot be expressed as one operation, we
8344 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8347 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8348 enum rtx_code *pop0;
8349 HOST_WIDE_INT *pconst0;
8351 HOST_WIDE_INT const1;
8352 enum machine_mode mode;
8355 enum rtx_code op0 = *pop0;
8356 HOST_WIDE_INT const0 = *pconst0;
8358 const0 &= GET_MODE_MASK (mode);
8359 const1 &= GET_MODE_MASK (mode);
8361 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8365 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8368 if (op1 == NIL || op0 == SET)
8371 else if (op0 == NIL)
8372 op0 = op1, const0 = const1;
8374 else if (op0 == op1)
8398 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8399 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8402 /* If the two constants aren't the same, we can't do anything. The
8403 remaining six cases can all be done. */
8404 else if (const0 != const1)
8412 /* (a & b) | b == b */
8414 else /* op1 == XOR */
8415 /* (a ^ b) | b == a | b */
8421 /* (a & b) ^ b == (~a) & b */
8422 op0 = AND, *pcomp_p = 1;
8423 else /* op1 == IOR */
8424 /* (a | b) ^ b == a & ~b */
8425 op0 = AND, *pconst0 = ~ const0;
8430 /* (a | b) & b == b */
8432 else /* op1 == XOR */
8433 /* (a ^ b) & b) == (~a) & b */
8440 /* Check for NO-OP cases. */
8441 const0 &= GET_MODE_MASK (mode);
8443 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8445 else if (const0 == 0 && op0 == AND)
8447 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8451 /* ??? Slightly redundant with the above mask, but not entirely.
8452 Moving this above means we'd have to sign-extend the mode mask
8453 for the final test. */
8454 const0 = trunc_int_for_mode (const0, mode);
8462 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8463 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8464 that we started with.
8466 The shift is normally computed in the widest mode we find in VAROP, as
8467 long as it isn't a different number of words than RESULT_MODE. Exceptions
8468 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8471 simplify_shift_const (x, code, result_mode, varop, count)
8474 enum machine_mode result_mode;
8478 enum rtx_code orig_code = code;
8479 int orig_count = count;
8480 enum machine_mode mode = result_mode;
8481 enum machine_mode shift_mode, tmode;
8483 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8484 /* We form (outer_op (code varop count) (outer_const)). */
8485 enum rtx_code outer_op = NIL;
8486 HOST_WIDE_INT outer_const = 0;
8488 int complement_p = 0;
8491 /* If we were given an invalid count, don't do anything except exactly
8492 what was requested. */
8494 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8499 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8502 /* Unless one of the branches of the `if' in this loop does a `continue',
8503 we will `break' the loop after the `if'. */
8507 /* If we have an operand of (clobber (const_int 0)), just return that
8509 if (GET_CODE (varop) == CLOBBER)
8512 /* If we discovered we had to complement VAROP, leave. Making a NOT
8513 here would cause an infinite loop. */
8517 /* Convert ROTATERT to ROTATE. */
8518 if (code == ROTATERT)
8519 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8521 /* We need to determine what mode we will do the shift in. If the
8522 shift is a right shift or a ROTATE, we must always do it in the mode
8523 it was originally done in. Otherwise, we can do it in MODE, the
8524 widest mode encountered. */
8526 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8527 ? result_mode : mode);
8529 /* Handle cases where the count is greater than the size of the mode
8530 minus 1. For ASHIFT, use the size minus one as the count (this can
8531 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8532 take the count modulo the size. For other shifts, the result is
8535 Since these shifts are being produced by the compiler by combining
8536 multiple operations, each of which are defined, we know what the
8537 result is supposed to be. */
8539 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8541 if (code == ASHIFTRT)
8542 count = GET_MODE_BITSIZE (shift_mode) - 1;
8543 else if (code == ROTATE || code == ROTATERT)
8544 count %= GET_MODE_BITSIZE (shift_mode);
8547 /* We can't simply return zero because there may be an
8555 /* Negative counts are invalid and should not have been made (a
8556 programmer-specified negative count should have been handled
8561 /* An arithmetic right shift of a quantity known to be -1 or 0
8563 if (code == ASHIFTRT
8564 && (num_sign_bit_copies (varop, shift_mode)
8565 == GET_MODE_BITSIZE (shift_mode)))
8571 /* If we are doing an arithmetic right shift and discarding all but
8572 the sign bit copies, this is equivalent to doing a shift by the
8573 bitsize minus one. Convert it into that shift because it will often
8574 allow other simplifications. */
8576 if (code == ASHIFTRT
8577 && (count + num_sign_bit_copies (varop, shift_mode)
8578 >= GET_MODE_BITSIZE (shift_mode)))
8579 count = GET_MODE_BITSIZE (shift_mode) - 1;
8581 /* We simplify the tests below and elsewhere by converting
8582 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8583 `make_compound_operation' will convert it to a ASHIFTRT for
8584 those machines (such as Vax) that don't have a LSHIFTRT. */
8585 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8587 && ((nonzero_bits (varop, shift_mode)
8588 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8592 switch (GET_CODE (varop))
8598 new = expand_compound_operation (varop);
8607 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8608 minus the width of a smaller mode, we can do this with a
8609 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8610 if ((code == ASHIFTRT || code == LSHIFTRT)
8611 && ! mode_dependent_address_p (XEXP (varop, 0))
8612 && ! MEM_VOLATILE_P (varop)
8613 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8614 MODE_INT, 1)) != BLKmode)
8616 if (BYTES_BIG_ENDIAN)
8617 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8619 new = gen_rtx_MEM (tmode,
8620 plus_constant (XEXP (varop, 0),
8621 count / BITS_PER_UNIT));
8622 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8623 MEM_COPY_ATTRIBUTES (new, varop);
8624 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8625 : ZERO_EXTEND, mode, new);
8632 /* Similar to the case above, except that we can only do this if
8633 the resulting mode is the same as that of the underlying
8634 MEM and adjust the address depending on the *bits* endianness
8635 because of the way that bit-field extract insns are defined. */
8636 if ((code == ASHIFTRT || code == LSHIFTRT)
8637 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8638 MODE_INT, 1)) != BLKmode
8639 && tmode == GET_MODE (XEXP (varop, 0)))
8641 if (BITS_BIG_ENDIAN)
8642 new = XEXP (varop, 0);
8645 new = copy_rtx (XEXP (varop, 0));
8646 SUBST (XEXP (new, 0),
8647 plus_constant (XEXP (new, 0),
8648 count / BITS_PER_UNIT));
8651 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8652 : ZERO_EXTEND, mode, new);
8659 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8660 the same number of words as what we've seen so far. Then store
8661 the widest mode in MODE. */
8662 if (subreg_lowpart_p (varop)
8663 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8664 > GET_MODE_SIZE (GET_MODE (varop)))
8665 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8666 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8669 varop = SUBREG_REG (varop);
8670 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8671 mode = GET_MODE (varop);
8677 /* Some machines use MULT instead of ASHIFT because MULT
8678 is cheaper. But it is still better on those machines to
8679 merge two shifts into one. */
8680 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8681 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8683 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8684 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8690 /* Similar, for when divides are cheaper. */
8691 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8692 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8694 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8695 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8701 /* If we are extracting just the sign bit of an arithmetic right
8702 shift, that shift is not needed. */
8703 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8705 varop = XEXP (varop, 0);
8709 /* ... fall through ... */
8714 /* Here we have two nested shifts. The result is usually the
8715 AND of a new shift with a mask. We compute the result below. */
8716 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8717 && INTVAL (XEXP (varop, 1)) >= 0
8718 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8719 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8720 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8722 enum rtx_code first_code = GET_CODE (varop);
8723 int first_count = INTVAL (XEXP (varop, 1));
8724 unsigned HOST_WIDE_INT mask;
8727 /* We have one common special case. We can't do any merging if
8728 the inner code is an ASHIFTRT of a smaller mode. However, if
8729 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8730 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8731 we can convert it to
8732 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8733 This simplifies certain SIGN_EXTEND operations. */
8734 if (code == ASHIFT && first_code == ASHIFTRT
8735 && (GET_MODE_BITSIZE (result_mode)
8736 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8738 /* C3 has the low-order C1 bits zero. */
8740 mask = (GET_MODE_MASK (mode)
8741 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8743 varop = simplify_and_const_int (NULL_RTX, result_mode,
8744 XEXP (varop, 0), mask);
8745 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8747 count = first_count;
8752 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8753 than C1 high-order bits equal to the sign bit, we can convert
8754 this to either an ASHIFT or a ASHIFTRT depending on the
8757 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8759 if (code == ASHIFTRT && first_code == ASHIFT
8760 && GET_MODE (varop) == shift_mode
8761 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8764 count -= first_count;
8766 count = - count, code = ASHIFT;
8767 varop = XEXP (varop, 0);
8771 /* There are some cases we can't do. If CODE is ASHIFTRT,
8772 we can only do this if FIRST_CODE is also ASHIFTRT.
8774 We can't do the case when CODE is ROTATE and FIRST_CODE is
8777 If the mode of this shift is not the mode of the outer shift,
8778 we can't do this if either shift is a right shift or ROTATE.
8780 Finally, we can't do any of these if the mode is too wide
8781 unless the codes are the same.
8783 Handle the case where the shift codes are the same
8786 if (code == first_code)
8788 if (GET_MODE (varop) != result_mode
8789 && (code == ASHIFTRT || code == LSHIFTRT
8793 count += first_count;
8794 varop = XEXP (varop, 0);
8798 if (code == ASHIFTRT
8799 || (code == ROTATE && first_code == ASHIFTRT)
8800 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8801 || (GET_MODE (varop) != result_mode
8802 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8803 || first_code == ROTATE
8804 || code == ROTATE)))
8807 /* To compute the mask to apply after the shift, shift the
8808 nonzero bits of the inner shift the same way the
8809 outer shift will. */
8811 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8814 = simplify_binary_operation (code, result_mode, mask_rtx,
8817 /* Give up if we can't compute an outer operation to use. */
8819 || GET_CODE (mask_rtx) != CONST_INT
8820 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8822 result_mode, &complement_p))
8825 /* If the shifts are in the same direction, we add the
8826 counts. Otherwise, we subtract them. */
8827 if ((code == ASHIFTRT || code == LSHIFTRT)
8828 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8829 count += first_count;
8831 count -= first_count;
8833 /* If COUNT is positive, the new shift is usually CODE,
8834 except for the two exceptions below, in which case it is
8835 FIRST_CODE. If the count is negative, FIRST_CODE should
8838 && ((first_code == ROTATE && code == ASHIFT)
8839 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8842 code = first_code, count = - count;
8844 varop = XEXP (varop, 0);
8848 /* If we have (A << B << C) for any shift, we can convert this to
8849 (A << C << B). This wins if A is a constant. Only try this if
8850 B is not a constant. */
8852 else if (GET_CODE (varop) == code
8853 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8855 = simplify_binary_operation (code, mode,
8859 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8866 /* Make this fit the case below. */
8867 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8868 GEN_INT (GET_MODE_MASK (mode)));
8874 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8875 with C the size of VAROP - 1 and the shift is logical if
8876 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8877 we have an (le X 0) operation. If we have an arithmetic shift
8878 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8879 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8881 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8882 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8883 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8884 && (code == LSHIFTRT || code == ASHIFTRT)
8885 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8886 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8889 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8892 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8893 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8898 /* If we have (shift (logical)), move the logical to the outside
8899 to allow it to possibly combine with another logical and the
8900 shift to combine with another shift. This also canonicalizes to
8901 what a ZERO_EXTRACT looks like. Also, some machines have
8902 (and (shift)) insns. */
8904 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8905 && (new = simplify_binary_operation (code, result_mode,
8907 GEN_INT (count))) != 0
8908 && GET_CODE(new) == CONST_INT
8909 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8910 INTVAL (new), result_mode, &complement_p))
8912 varop = XEXP (varop, 0);
8916 /* If we can't do that, try to simplify the shift in each arm of the
8917 logical expression, make a new logical expression, and apply
8918 the inverse distributive law. */
8920 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8921 XEXP (varop, 0), count);
8922 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8923 XEXP (varop, 1), count);
8925 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8926 varop = apply_distributive_law (varop);
8933 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8934 says that the sign bit can be tested, FOO has mode MODE, C is
8935 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8936 that may be nonzero. */
8937 if (code == LSHIFTRT
8938 && XEXP (varop, 1) == const0_rtx
8939 && GET_MODE (XEXP (varop, 0)) == result_mode
8940 && count == GET_MODE_BITSIZE (result_mode) - 1
8941 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8942 && ((STORE_FLAG_VALUE
8943 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8944 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8945 && merge_outer_ops (&outer_op, &outer_const, XOR,
8946 (HOST_WIDE_INT) 1, result_mode,
8949 varop = XEXP (varop, 0);
8956 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8957 than the number of bits in the mode is equivalent to A. */
8958 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8959 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8961 varop = XEXP (varop, 0);
8966 /* NEG commutes with ASHIFT since it is multiplication. Move the
8967 NEG outside to allow shifts to combine. */
8969 && merge_outer_ops (&outer_op, &outer_const, NEG,
8970 (HOST_WIDE_INT) 0, result_mode,
8973 varop = XEXP (varop, 0);
8979 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8980 is one less than the number of bits in the mode is
8981 equivalent to (xor A 1). */
8982 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8983 && XEXP (varop, 1) == constm1_rtx
8984 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8985 && merge_outer_ops (&outer_op, &outer_const, XOR,
8986 (HOST_WIDE_INT) 1, result_mode,
8990 varop = XEXP (varop, 0);
8994 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8995 that might be nonzero in BAR are those being shifted out and those
8996 bits are known zero in FOO, we can replace the PLUS with FOO.
8997 Similarly in the other operand order. This code occurs when
8998 we are computing the size of a variable-size array. */
9000 if ((code == ASHIFTRT || code == LSHIFTRT)
9001 && count < HOST_BITS_PER_WIDE_INT
9002 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9003 && (nonzero_bits (XEXP (varop, 1), result_mode)
9004 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9006 varop = XEXP (varop, 0);
9009 else if ((code == ASHIFTRT || code == LSHIFTRT)
9010 && count < HOST_BITS_PER_WIDE_INT
9011 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9012 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9014 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9015 & nonzero_bits (XEXP (varop, 1),
9018 varop = XEXP (varop, 1);
9022 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9024 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9025 && (new = simplify_binary_operation (ASHIFT, result_mode,
9027 GEN_INT (count))) != 0
9028 && GET_CODE(new) == CONST_INT
9029 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9030 INTVAL (new), result_mode, &complement_p))
9032 varop = XEXP (varop, 0);
9038 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9039 with C the size of VAROP - 1 and the shift is logical if
9040 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9041 we have a (gt X 0) operation. If the shift is arithmetic with
9042 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9043 we have a (neg (gt X 0)) operation. */
9045 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9046 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9047 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9048 && (code == LSHIFTRT || code == ASHIFTRT)
9049 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9050 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9051 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9054 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9057 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9058 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9065 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9066 if the truncate does not affect the value. */
9067 if (code == LSHIFTRT
9068 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9069 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9070 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9071 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9072 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9074 rtx varop_inner = XEXP (varop, 0);
9076 varop_inner = gen_rtx_combine (LSHIFTRT,
9077 GET_MODE (varop_inner),
9078 XEXP (varop_inner, 0),
9079 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
9080 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9094 /* We need to determine what mode to do the shift in. If the shift is
9095 a right shift or ROTATE, we must always do it in the mode it was
9096 originally done in. Otherwise, we can do it in MODE, the widest mode
9097 encountered. The code we care about is that of the shift that will
9098 actually be done, not the shift that was originally requested. */
9100 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9101 ? result_mode : mode);
9103 /* We have now finished analyzing the shift. The result should be
9104 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9105 OUTER_OP is non-NIL, it is an operation that needs to be applied
9106 to the result of the shift. OUTER_CONST is the relevant constant,
9107 but we must turn off all bits turned off in the shift.
9109 If we were passed a value for X, see if we can use any pieces of
9110 it. If not, make new rtx. */
9112 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9113 && GET_CODE (XEXP (x, 1)) == CONST_INT
9114 && INTVAL (XEXP (x, 1)) == count)
9115 const_rtx = XEXP (x, 1);
9117 const_rtx = GEN_INT (count);
9119 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9120 && GET_MODE (XEXP (x, 0)) == shift_mode
9121 && SUBREG_REG (XEXP (x, 0)) == varop)
9122 varop = XEXP (x, 0);
9123 else if (GET_MODE (varop) != shift_mode)
9124 varop = gen_lowpart_for_combine (shift_mode, varop);
9126 /* If we can't make the SUBREG, try to return what we were given. */
9127 if (GET_CODE (varop) == CLOBBER)
9128 return x ? x : varop;
9130 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9135 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9136 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9138 SUBST (XEXP (x, 0), varop);
9139 SUBST (XEXP (x, 1), const_rtx);
9142 /* If we have an outer operation and we just made a shift, it is
9143 possible that we could have simplified the shift were it not
9144 for the outer operation. So try to do the simplification
9147 if (outer_op != NIL && GET_CODE (x) == code
9148 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9149 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9150 INTVAL (XEXP (x, 1)));
9152 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9153 turn off all the bits that the shift would have turned off. */
9154 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9155 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9156 GET_MODE_MASK (result_mode) >> orig_count);
9158 /* Do the remainder of the processing in RESULT_MODE. */
9159 x = gen_lowpart_for_combine (result_mode, x);
9161 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9164 x = gen_unary (NOT, result_mode, result_mode, x);
9166 if (outer_op != NIL)
9168 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9169 outer_const = trunc_int_for_mode (outer_const, result_mode);
9171 if (outer_op == AND)
9172 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9173 else if (outer_op == SET)
9174 /* This means that we have determined that the result is
9175 equivalent to a constant. This should be rare. */
9176 x = GEN_INT (outer_const);
9177 else if (GET_RTX_CLASS (outer_op) == '1')
9178 x = gen_unary (outer_op, result_mode, result_mode, x);
9180 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9186 /* Like recog, but we receive the address of a pointer to a new pattern.
9187 We try to match the rtx that the pointer points to.
9188 If that fails, we may try to modify or replace the pattern,
9189 storing the replacement into the same pointer object.
9191 Modifications include deletion or addition of CLOBBERs.
9193 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9194 the CLOBBERs are placed.
9196 The value is the final insn code from the pattern ultimately matched,
9200 recog_for_combine (pnewpat, insn, pnotes)
9205 register rtx pat = *pnewpat;
9206 int insn_code_number;
9207 int num_clobbers_to_add = 0;
9211 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9212 we use to indicate that something didn't match. If we find such a
9213 thing, force rejection. */
9214 if (GET_CODE (pat) == PARALLEL)
9215 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9216 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9217 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9220 /* Is the result of combination a valid instruction? */
9221 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9223 /* If it isn't, there is the possibility that we previously had an insn
9224 that clobbered some register as a side effect, but the combined
9225 insn doesn't need to do that. So try once more without the clobbers
9226 unless this represents an ASM insn. */
9228 if (insn_code_number < 0 && ! check_asm_operands (pat)
9229 && GET_CODE (pat) == PARALLEL)
9233 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9234 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9237 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9241 SUBST_INT (XVECLEN (pat, 0), pos);
9244 pat = XVECEXP (pat, 0, 0);
9246 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9249 /* If we had any clobbers to add, make a new pattern than contains
9250 them. Then check to make sure that all of them are dead. */
9251 if (num_clobbers_to_add)
9253 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9254 gen_rtvec (GET_CODE (pat) == PARALLEL
9256 + num_clobbers_to_add)
9257 : num_clobbers_to_add + 1));
9259 if (GET_CODE (pat) == PARALLEL)
9260 for (i = 0; i < XVECLEN (pat, 0); i++)
9261 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9263 XVECEXP (newpat, 0, 0) = pat;
9265 add_clobbers (newpat, insn_code_number);
9267 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9268 i < XVECLEN (newpat, 0); i++)
9270 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9271 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9273 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9274 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9282 return insn_code_number;
9285 /* Like gen_lowpart but for use by combine. In combine it is not possible
9286 to create any new pseudoregs. However, it is safe to create
9287 invalid memory addresses, because combine will try to recognize
9288 them and all they will do is make the combine attempt fail.
9290 If for some reason this cannot do its job, an rtx
9291 (clobber (const_int 0)) is returned.
9292 An insn containing that will not be recognized. */
9297 gen_lowpart_for_combine (mode, x)
9298 enum machine_mode mode;
9303 if (GET_MODE (x) == mode)
9306 /* We can only support MODE being wider than a word if X is a
9307 constant integer or has a mode the same size. */
9309 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9310 && ! ((GET_MODE (x) == VOIDmode
9311 && (GET_CODE (x) == CONST_INT
9312 || GET_CODE (x) == CONST_DOUBLE))
9313 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9314 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9316 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9317 won't know what to do. So we will strip off the SUBREG here and
9318 process normally. */
9319 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9322 if (GET_MODE (x) == mode)
9326 result = gen_lowpart_common (mode, x);
9328 && GET_CODE (result) == SUBREG
9329 && GET_CODE (SUBREG_REG (result)) == REG
9330 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9331 && (GET_MODE_SIZE (GET_MODE (result))
9332 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9333 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9338 if (GET_CODE (x) == MEM)
9340 register int offset = 0;
9343 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9345 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9346 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9348 /* If we want to refer to something bigger than the original memref,
9349 generate a perverse subreg instead. That will force a reload
9350 of the original memref X. */
9351 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9352 return gen_rtx_SUBREG (mode, x, 0);
9354 if (WORDS_BIG_ENDIAN)
9355 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9356 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9358 if (BYTES_BIG_ENDIAN)
9360 /* Adjust the address so that the address-after-the-data is
9362 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9363 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9365 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9366 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9367 MEM_COPY_ATTRIBUTES (new, x);
9371 /* If X is a comparison operator, rewrite it in a new mode. This
9372 probably won't match, but may allow further simplifications. */
9373 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9374 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9376 /* If we couldn't simplify X any other way, just enclose it in a
9377 SUBREG. Normally, this SUBREG won't match, but some patterns may
9378 include an explicit SUBREG or we may simplify it further in combine. */
9383 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9384 word = ((GET_MODE_SIZE (GET_MODE (x))
9385 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9387 return gen_rtx_SUBREG (mode, x, word);
9391 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9392 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9394 If the identical expression was previously in the insn (in the undobuf),
9395 it will be returned. Only if it is not found will a new expression
9400 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9402 #ifndef ANSI_PROTOTYPES
9404 enum machine_mode mode;
9416 #ifndef ANSI_PROTOTYPES
9417 code = va_arg (p, enum rtx_code);
9418 mode = va_arg (p, enum machine_mode);
9421 n_args = GET_RTX_LENGTH (code);
9422 fmt = GET_RTX_FORMAT (code);
9424 if (n_args == 0 || n_args > 3)
9427 /* Get each arg and verify that it is supposed to be an expression. */
9428 for (j = 0; j < n_args; j++)
9433 args[j] = va_arg (p, rtx);
9438 /* See if this is in undobuf. Be sure we don't use objects that came
9439 from another insn; this could produce circular rtl structures. */
9441 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9443 && GET_CODE (undo->old_contents.r) == code
9444 && GET_MODE (undo->old_contents.r) == mode)
9446 for (j = 0; j < n_args; j++)
9447 if (XEXP (undo->old_contents.r, j) != args[j])
9451 return undo->old_contents.r;
9454 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9455 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9456 rt = rtx_alloc (code);
9457 PUT_MODE (rt, mode);
9458 XEXP (rt, 0) = args[0];
9461 XEXP (rt, 1) = args[1];
9463 XEXP (rt, 2) = args[2];
9468 /* These routines make binary and unary operations by first seeing if they
9469 fold; if not, a new expression is allocated. */
9472 gen_binary (code, mode, op0, op1)
9474 enum machine_mode mode;
9480 if (GET_RTX_CLASS (code) == 'c'
9481 && (GET_CODE (op0) == CONST_INT
9482 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9483 tem = op0, op0 = op1, op1 = tem;
9485 if (GET_RTX_CLASS (code) == '<')
9487 enum machine_mode op_mode = GET_MODE (op0);
9489 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9490 just (REL_OP X Y). */
9491 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9493 op1 = XEXP (op0, 1);
9494 op0 = XEXP (op0, 0);
9495 op_mode = GET_MODE (op0);
9498 if (op_mode == VOIDmode)
9499 op_mode = GET_MODE (op1);
9500 result = simplify_relational_operation (code, op_mode, op0, op1);
9503 result = simplify_binary_operation (code, mode, op0, op1);
9508 /* Put complex operands first and constants second. */
9509 if (GET_RTX_CLASS (code) == 'c'
9510 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9511 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9512 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9513 || (GET_CODE (op0) == SUBREG
9514 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9515 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9516 return gen_rtx_combine (code, mode, op1, op0);
9518 /* If we are turning off bits already known off in OP0, we need not do
9520 else if (code == AND && GET_CODE (op1) == CONST_INT
9521 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9522 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9525 return gen_rtx_combine (code, mode, op0, op1);
9529 gen_unary (code, mode, op0_mode, op0)
9531 enum machine_mode mode, op0_mode;
9534 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9539 return gen_rtx_combine (code, mode, op0);
9542 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9543 comparison code that will be tested.
9545 The result is a possibly different comparison code to use. *POP0 and
9546 *POP1 may be updated.
9548 It is possible that we might detect that a comparison is either always
9549 true or always false. However, we do not perform general constant
9550 folding in combine, so this knowledge isn't useful. Such tautologies
9551 should have been detected earlier. Hence we ignore all such cases. */
9553 static enum rtx_code
9554 simplify_comparison (code, pop0, pop1)
9563 enum machine_mode mode, tmode;
9565 /* Try a few ways of applying the same transformation to both operands. */
9568 #ifndef WORD_REGISTER_OPERATIONS
9569 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9570 so check specially. */
9571 if (code != GTU && code != GEU && code != LTU && code != LEU
9572 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9573 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9574 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9575 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9576 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9577 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9578 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9579 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9580 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9581 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9582 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9583 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9584 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9585 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9586 && (INTVAL (XEXP (op0, 1))
9587 == (GET_MODE_BITSIZE (GET_MODE (op0))
9589 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9591 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9592 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9596 /* If both operands are the same constant shift, see if we can ignore the
9597 shift. We can if the shift is a rotate or if the bits shifted out of
9598 this shift are known to be zero for both inputs and if the type of
9599 comparison is compatible with the shift. */
9600 if (GET_CODE (op0) == GET_CODE (op1)
9601 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9602 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9603 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9604 && (code != GT && code != LT && code != GE && code != LE))
9605 || (GET_CODE (op0) == ASHIFTRT
9606 && (code != GTU && code != LTU
9607 && code != GEU && code != GEU)))
9608 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9609 && INTVAL (XEXP (op0, 1)) >= 0
9610 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9611 && XEXP (op0, 1) == XEXP (op1, 1))
9613 enum machine_mode mode = GET_MODE (op0);
9614 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9615 int shift_count = INTVAL (XEXP (op0, 1));
9617 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9618 mask &= (mask >> shift_count) << shift_count;
9619 else if (GET_CODE (op0) == ASHIFT)
9620 mask = (mask & (mask << shift_count)) >> shift_count;
9622 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9623 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9624 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9629 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9630 SUBREGs are of the same mode, and, in both cases, the AND would
9631 be redundant if the comparison was done in the narrower mode,
9632 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9633 and the operand's possibly nonzero bits are 0xffffff01; in that case
9634 if we only care about QImode, we don't need the AND). This case
9635 occurs if the output mode of an scc insn is not SImode and
9636 STORE_FLAG_VALUE == 1 (e.g., the 386).
9638 Similarly, check for a case where the AND's are ZERO_EXTEND
9639 operations from some narrower mode even though a SUBREG is not
9642 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9643 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9644 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9646 rtx inner_op0 = XEXP (op0, 0);
9647 rtx inner_op1 = XEXP (op1, 0);
9648 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9649 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9652 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9653 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9654 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9655 && (GET_MODE (SUBREG_REG (inner_op0))
9656 == GET_MODE (SUBREG_REG (inner_op1)))
9657 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9658 <= HOST_BITS_PER_WIDE_INT)
9659 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9660 GET_MODE (SUBREG_REG (inner_op0)))))
9661 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9662 GET_MODE (SUBREG_REG (inner_op1))))))
9664 op0 = SUBREG_REG (inner_op0);
9665 op1 = SUBREG_REG (inner_op1);
9667 /* The resulting comparison is always unsigned since we masked
9668 off the original sign bit. */
9669 code = unsigned_condition (code);
9675 for (tmode = GET_CLASS_NARROWEST_MODE
9676 (GET_MODE_CLASS (GET_MODE (op0)));
9677 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9678 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9680 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9681 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9682 code = unsigned_condition (code);
9691 /* If both operands are NOT, we can strip off the outer operation
9692 and adjust the comparison code for swapped operands; similarly for
9693 NEG, except that this must be an equality comparison. */
9694 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9695 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9696 && (code == EQ || code == NE)))
9697 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9703 /* If the first operand is a constant, swap the operands and adjust the
9704 comparison code appropriately, but don't do this if the second operand
9705 is already a constant integer. */
9706 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9708 tem = op0, op0 = op1, op1 = tem;
9709 code = swap_condition (code);
9712 /* We now enter a loop during which we will try to simplify the comparison.
9713 For the most part, we only are concerned with comparisons with zero,
9714 but some things may really be comparisons with zero but not start
9715 out looking that way. */
9717 while (GET_CODE (op1) == CONST_INT)
9719 enum machine_mode mode = GET_MODE (op0);
9720 int mode_width = GET_MODE_BITSIZE (mode);
9721 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9722 int equality_comparison_p;
9723 int sign_bit_comparison_p;
9724 int unsigned_comparison_p;
9725 HOST_WIDE_INT const_op;
9727 /* We only want to handle integral modes. This catches VOIDmode,
9728 CCmode, and the floating-point modes. An exception is that we
9729 can handle VOIDmode if OP0 is a COMPARE or a comparison
9732 if (GET_MODE_CLASS (mode) != MODE_INT
9733 && ! (mode == VOIDmode
9734 && (GET_CODE (op0) == COMPARE
9735 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9738 /* Get the constant we are comparing against and turn off all bits
9739 not on in our mode. */
9740 const_op = INTVAL (op1);
9741 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9744 /* If we are comparing against a constant power of two and the value
9745 being compared can only have that single bit nonzero (e.g., it was
9746 `and'ed with that bit), we can replace this with a comparison
9749 && (code == EQ || code == NE || code == GE || code == GEU
9750 || code == LT || code == LTU)
9751 && mode_width <= HOST_BITS_PER_WIDE_INT
9752 && exact_log2 (const_op) >= 0
9753 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9755 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9756 op1 = const0_rtx, const_op = 0;
9759 /* Similarly, if we are comparing a value known to be either -1 or
9760 0 with -1, change it to the opposite comparison against zero. */
9763 && (code == EQ || code == NE || code == GT || code == LE
9764 || code == GEU || code == LTU)
9765 && num_sign_bit_copies (op0, mode) == mode_width)
9767 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9768 op1 = const0_rtx, const_op = 0;
9771 /* Do some canonicalizations based on the comparison code. We prefer
9772 comparisons against zero and then prefer equality comparisons.
9773 If we can reduce the size of a constant, we will do that too. */
9778 /* < C is equivalent to <= (C - 1) */
9782 op1 = GEN_INT (const_op);
9784 /* ... fall through to LE case below. */
9790 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9794 op1 = GEN_INT (const_op);
9798 /* If we are doing a <= 0 comparison on a value known to have
9799 a zero sign bit, we can replace this with == 0. */
9800 else if (const_op == 0
9801 && mode_width <= HOST_BITS_PER_WIDE_INT
9802 && (nonzero_bits (op0, mode)
9803 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9808 /* >= C is equivalent to > (C - 1). */
9812 op1 = GEN_INT (const_op);
9814 /* ... fall through to GT below. */
9820 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9824 op1 = GEN_INT (const_op);
9828 /* If we are doing a > 0 comparison on a value known to have
9829 a zero sign bit, we can replace this with != 0. */
9830 else if (const_op == 0
9831 && mode_width <= HOST_BITS_PER_WIDE_INT
9832 && (nonzero_bits (op0, mode)
9833 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9838 /* < C is equivalent to <= (C - 1). */
9842 op1 = GEN_INT (const_op);
9844 /* ... fall through ... */
9847 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9848 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9849 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9851 const_op = 0, op1 = const0_rtx;
9859 /* unsigned <= 0 is equivalent to == 0 */
9863 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9864 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9865 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9867 const_op = 0, op1 = const0_rtx;
9873 /* >= C is equivalent to < (C - 1). */
9877 op1 = GEN_INT (const_op);
9879 /* ... fall through ... */
9882 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9883 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9884 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9886 const_op = 0, op1 = const0_rtx;
9894 /* unsigned > 0 is equivalent to != 0 */
9898 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9899 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9900 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9902 const_op = 0, op1 = const0_rtx;
9911 /* Compute some predicates to simplify code below. */
9913 equality_comparison_p = (code == EQ || code == NE);
9914 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9915 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9918 /* If this is a sign bit comparison and we can do arithmetic in
9919 MODE, say that we will only be needing the sign bit of OP0. */
9920 if (sign_bit_comparison_p
9921 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9922 op0 = force_to_mode (op0, mode,
9924 << (GET_MODE_BITSIZE (mode) - 1)),
9927 /* Now try cases based on the opcode of OP0. If none of the cases
9928 does a "continue", we exit this loop immediately after the
9931 switch (GET_CODE (op0))
9934 /* If we are extracting a single bit from a variable position in
9935 a constant that has only a single bit set and are comparing it
9936 with zero, we can convert this into an equality comparison
9937 between the position and the location of the single bit. */
9939 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9940 && XEXP (op0, 1) == const1_rtx
9941 && equality_comparison_p && const_op == 0
9942 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9944 if (BITS_BIG_ENDIAN)
9947 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
9948 if (mode == VOIDmode)
9950 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9952 i = BITS_PER_WORD - 1 - i;
9956 op0 = XEXP (op0, 2);
9960 /* Result is nonzero iff shift count is equal to I. */
9961 code = reverse_condition (code);
9965 /* ... fall through ... */
9968 tem = expand_compound_operation (op0);
9977 /* If testing for equality, we can take the NOT of the constant. */
9978 if (equality_comparison_p
9979 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9981 op0 = XEXP (op0, 0);
9986 /* If just looking at the sign bit, reverse the sense of the
9988 if (sign_bit_comparison_p)
9990 op0 = XEXP (op0, 0);
9991 code = (code == GE ? LT : GE);
9997 /* If testing for equality, we can take the NEG of the constant. */
9998 if (equality_comparison_p
9999 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10001 op0 = XEXP (op0, 0);
10006 /* The remaining cases only apply to comparisons with zero. */
10010 /* When X is ABS or is known positive,
10011 (neg X) is < 0 if and only if X != 0. */
10013 if (sign_bit_comparison_p
10014 && (GET_CODE (XEXP (op0, 0)) == ABS
10015 || (mode_width <= HOST_BITS_PER_WIDE_INT
10016 && (nonzero_bits (XEXP (op0, 0), mode)
10017 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10019 op0 = XEXP (op0, 0);
10020 code = (code == LT ? NE : EQ);
10024 /* If we have NEG of something whose two high-order bits are the
10025 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10026 if (num_sign_bit_copies (op0, mode) >= 2)
10028 op0 = XEXP (op0, 0);
10029 code = swap_condition (code);
10035 /* If we are testing equality and our count is a constant, we
10036 can perform the inverse operation on our RHS. */
10037 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10038 && (tem = simplify_binary_operation (ROTATERT, mode,
10039 op1, XEXP (op0, 1))) != 0)
10041 op0 = XEXP (op0, 0);
10046 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10047 a particular bit. Convert it to an AND of a constant of that
10048 bit. This will be converted into a ZERO_EXTRACT. */
10049 if (const_op == 0 && sign_bit_comparison_p
10050 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10051 && mode_width <= HOST_BITS_PER_WIDE_INT)
10053 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10056 - INTVAL (XEXP (op0, 1)))));
10057 code = (code == LT ? NE : EQ);
10061 /* ... fall through ... */
10064 /* ABS is ignorable inside an equality comparison with zero. */
10065 if (const_op == 0 && equality_comparison_p)
10067 op0 = XEXP (op0, 0);
10074 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10075 to (compare FOO CONST) if CONST fits in FOO's mode and we
10076 are either testing inequality or have an unsigned comparison
10077 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10078 if (! unsigned_comparison_p
10079 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10080 <= HOST_BITS_PER_WIDE_INT)
10081 && ((unsigned HOST_WIDE_INT) const_op
10082 < (((unsigned HOST_WIDE_INT) 1
10083 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10085 op0 = XEXP (op0, 0);
10091 /* Check for the case where we are comparing A - C1 with C2,
10092 both constants are smaller than 1/2 the maximum positive
10093 value in MODE, and the comparison is equality or unsigned.
10094 In that case, if A is either zero-extended to MODE or has
10095 sufficient sign bits so that the high-order bit in MODE
10096 is a copy of the sign in the inner mode, we can prove that it is
10097 safe to do the operation in the wider mode. This simplifies
10098 many range checks. */
10100 if (mode_width <= HOST_BITS_PER_WIDE_INT
10101 && subreg_lowpart_p (op0)
10102 && GET_CODE (SUBREG_REG (op0)) == PLUS
10103 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10104 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10105 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
10106 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
10107 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10108 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10109 GET_MODE (SUBREG_REG (op0)))
10110 & ~ GET_MODE_MASK (mode))
10111 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10112 GET_MODE (SUBREG_REG (op0)))
10113 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10114 - GET_MODE_BITSIZE (mode)))))
10116 op0 = SUBREG_REG (op0);
10120 /* If the inner mode is narrower and we are extracting the low part,
10121 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10122 if (subreg_lowpart_p (op0)
10123 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10124 /* Fall through */ ;
10128 /* ... fall through ... */
10131 if ((unsigned_comparison_p || equality_comparison_p)
10132 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10133 <= HOST_BITS_PER_WIDE_INT)
10134 && ((unsigned HOST_WIDE_INT) const_op
10135 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10137 op0 = XEXP (op0, 0);
10143 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10144 this for equality comparisons due to pathological cases involving
10146 if (equality_comparison_p
10147 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10148 op1, XEXP (op0, 1))))
10150 op0 = XEXP (op0, 0);
10155 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10156 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10157 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10159 op0 = XEXP (XEXP (op0, 0), 0);
10160 code = (code == LT ? EQ : NE);
10166 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10167 (eq B (minus A C)), whichever simplifies. We can only do
10168 this for equality comparisons due to pathological cases involving
10170 if (equality_comparison_p
10171 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10172 XEXP (op0, 1), op1)))
10174 op0 = XEXP (op0, 0);
10179 if (equality_comparison_p
10180 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10181 XEXP (op0, 0), op1)))
10183 op0 = XEXP (op0, 1);
10188 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10189 of bits in X minus 1, is one iff X > 0. */
10190 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10191 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10192 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10193 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10195 op0 = XEXP (op0, 1);
10196 code = (code == GE ? LE : GT);
10202 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10203 if C is zero or B is a constant. */
10204 if (equality_comparison_p
10205 && 0 != (tem = simplify_binary_operation (XOR, mode,
10206 XEXP (op0, 1), op1)))
10208 op0 = XEXP (op0, 0);
10215 case LT: case LTU: case LE: case LEU:
10216 case GT: case GTU: case GE: case GEU:
10217 /* We can't do anything if OP0 is a condition code value, rather
10218 than an actual data value. */
10221 || XEXP (op0, 0) == cc0_rtx
10223 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10226 /* Get the two operands being compared. */
10227 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10228 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10230 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10232 /* Check for the cases where we simply want the result of the
10233 earlier test or the opposite of that result. */
10235 || (code == EQ && reversible_comparison_p (op0))
10236 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10237 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10238 && (STORE_FLAG_VALUE
10239 & (((HOST_WIDE_INT) 1
10240 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10242 || (code == GE && reversible_comparison_p (op0)))))
10244 code = (code == LT || code == NE
10245 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10246 op0 = tem, op1 = tem1;
10252 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10254 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10255 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10256 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10258 op0 = XEXP (op0, 1);
10259 code = (code == GE ? GT : LE);
10265 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10266 will be converted to a ZERO_EXTRACT later. */
10267 if (const_op == 0 && equality_comparison_p
10268 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10269 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10271 op0 = simplify_and_const_int
10272 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10274 XEXP (XEXP (op0, 0), 1)),
10275 (HOST_WIDE_INT) 1);
10279 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10280 zero and X is a comparison and C1 and C2 describe only bits set
10281 in STORE_FLAG_VALUE, we can compare with X. */
10282 if (const_op == 0 && equality_comparison_p
10283 && mode_width <= HOST_BITS_PER_WIDE_INT
10284 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10285 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10286 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10287 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10288 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10290 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10291 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10292 if ((~ STORE_FLAG_VALUE & mask) == 0
10293 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10294 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10295 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10297 op0 = XEXP (XEXP (op0, 0), 0);
10302 /* If we are doing an equality comparison of an AND of a bit equal
10303 to the sign bit, replace this with a LT or GE comparison of
10304 the underlying value. */
10305 if (equality_comparison_p
10307 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10308 && mode_width <= HOST_BITS_PER_WIDE_INT
10309 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10310 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10312 op0 = XEXP (op0, 0);
10313 code = (code == EQ ? GE : LT);
10317 /* If this AND operation is really a ZERO_EXTEND from a narrower
10318 mode, the constant fits within that mode, and this is either an
10319 equality or unsigned comparison, try to do this comparison in
10320 the narrower mode. */
10321 if ((equality_comparison_p || unsigned_comparison_p)
10322 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10323 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10324 & GET_MODE_MASK (mode))
10326 && const_op >> i == 0
10327 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10329 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10333 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10334 in both M1 and M2 and the SUBREG is either paradoxical or
10335 represents the low part, permute the SUBREG and the AND and
10337 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10339 #ifdef WORD_REGISTER_OPERATIONS
10341 > (GET_MODE_BITSIZE
10342 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10343 && mode_width <= BITS_PER_WORD)
10346 <= (GET_MODE_BITSIZE
10347 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10348 && subreg_lowpart_p (XEXP (op0, 0))))
10349 #ifndef WORD_REGISTER_OPERATIONS
10350 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10351 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10352 As originally written the upper bits have a defined value
10353 due to the AND operation. However, if we commute the AND
10354 inside the SUBREG then they no longer have defined values
10355 and the meaning of the code has been changed. */
10356 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10357 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10359 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10360 && mode_width <= HOST_BITS_PER_WIDE_INT
10361 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10362 <= HOST_BITS_PER_WIDE_INT)
10363 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10364 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10365 & INTVAL (XEXP (op0, 1)))
10366 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10367 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10368 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10372 = gen_lowpart_for_combine
10374 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10375 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10382 /* If we have (compare (ashift FOO N) (const_int C)) and
10383 the high order N bits of FOO (N+1 if an inequality comparison)
10384 are known to be zero, we can do this by comparing FOO with C
10385 shifted right N bits so long as the low-order N bits of C are
10387 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10388 && INTVAL (XEXP (op0, 1)) >= 0
10389 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10390 < HOST_BITS_PER_WIDE_INT)
10392 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10393 && mode_width <= HOST_BITS_PER_WIDE_INT
10394 && (nonzero_bits (XEXP (op0, 0), mode)
10395 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10396 + ! equality_comparison_p))) == 0)
10398 /* We must perform a logical shift, not an arithmetic one,
10399 as we want the top N bits of C to be zero. */
10400 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10402 temp >>= INTVAL (XEXP (op0, 1));
10403 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10404 op0 = XEXP (op0, 0);
10408 /* If we are doing a sign bit comparison, it means we are testing
10409 a particular bit. Convert it to the appropriate AND. */
10410 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10411 && mode_width <= HOST_BITS_PER_WIDE_INT)
10413 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10416 - INTVAL (XEXP (op0, 1)))));
10417 code = (code == LT ? NE : EQ);
10421 /* If this an equality comparison with zero and we are shifting
10422 the low bit to the sign bit, we can convert this to an AND of the
10424 if (const_op == 0 && equality_comparison_p
10425 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10426 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10428 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10429 (HOST_WIDE_INT) 1);
10435 /* If this is an equality comparison with zero, we can do this
10436 as a logical shift, which might be much simpler. */
10437 if (equality_comparison_p && const_op == 0
10438 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10440 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10442 INTVAL (XEXP (op0, 1)));
10446 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10447 do the comparison in a narrower mode. */
10448 if (! unsigned_comparison_p
10449 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10450 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10451 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10452 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10453 MODE_INT, 1)) != BLKmode
10454 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10455 || ((unsigned HOST_WIDE_INT) - const_op
10456 <= GET_MODE_MASK (tmode))))
10458 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10462 /* ... fall through ... */
10464 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10465 the low order N bits of FOO are known to be zero, we can do this
10466 by comparing FOO with C shifted left N bits so long as no
10467 overflow occurs. */
10468 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10469 && INTVAL (XEXP (op0, 1)) >= 0
10470 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10471 && mode_width <= HOST_BITS_PER_WIDE_INT
10472 && (nonzero_bits (XEXP (op0, 0), mode)
10473 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10475 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10478 const_op <<= INTVAL (XEXP (op0, 1));
10479 op1 = GEN_INT (const_op);
10480 op0 = XEXP (op0, 0);
10484 /* If we are using this shift to extract just the sign bit, we
10485 can replace this with an LT or GE comparison. */
10487 && (equality_comparison_p || sign_bit_comparison_p)
10488 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10489 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10491 op0 = XEXP (op0, 0);
10492 code = (code == NE || code == GT ? LT : GE);
10504 /* Now make any compound operations involved in this comparison. Then,
10505 check for an outmost SUBREG on OP0 that is not doing anything or is
10506 paradoxical. The latter case can only occur when it is known that the
10507 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10508 We can never remove a SUBREG for a non-equality comparison because the
10509 sign bit is in a different place in the underlying object. */
10511 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10512 op1 = make_compound_operation (op1, SET);
10514 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10515 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10516 && (code == NE || code == EQ)
10517 && ((GET_MODE_SIZE (GET_MODE (op0))
10518 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10520 op0 = SUBREG_REG (op0);
10521 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10524 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10525 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10526 && (code == NE || code == EQ)
10527 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10528 <= HOST_BITS_PER_WIDE_INT)
10529 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10530 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10531 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10533 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10534 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10535 op0 = SUBREG_REG (op0), op1 = tem;
10537 /* We now do the opposite procedure: Some machines don't have compare
10538 insns in all modes. If OP0's mode is an integer mode smaller than a
10539 word and we can't do a compare in that mode, see if there is a larger
10540 mode for which we can do the compare. There are a number of cases in
10541 which we can use the wider mode. */
10543 mode = GET_MODE (op0);
10544 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10545 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10546 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10547 for (tmode = GET_MODE_WIDER_MODE (mode);
10549 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10550 tmode = GET_MODE_WIDER_MODE (tmode))
10551 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10553 /* If the only nonzero bits in OP0 and OP1 are those in the
10554 narrower mode and this is an equality or unsigned comparison,
10555 we can use the wider mode. Similarly for sign-extended
10556 values, in which case it is true for all comparisons. */
10557 if (((code == EQ || code == NE
10558 || code == GEU || code == GTU || code == LEU || code == LTU)
10559 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10560 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10561 || ((num_sign_bit_copies (op0, tmode)
10562 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10563 && (num_sign_bit_copies (op1, tmode)
10564 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10566 op0 = gen_lowpart_for_combine (tmode, op0);
10567 op1 = gen_lowpart_for_combine (tmode, op1);
10571 /* If this is a test for negative, we can make an explicit
10572 test of the sign bit. */
10574 if (op1 == const0_rtx && (code == LT || code == GE)
10575 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10577 op0 = gen_binary (AND, tmode,
10578 gen_lowpart_for_combine (tmode, op0),
10579 GEN_INT ((HOST_WIDE_INT) 1
10580 << (GET_MODE_BITSIZE (mode) - 1)));
10581 code = (code == LT) ? NE : EQ;
10586 #ifdef CANONICALIZE_COMPARISON
10587 /* If this machine only supports a subset of valid comparisons, see if we
10588 can convert an unsupported one into a supported one. */
10589 CANONICALIZE_COMPARISON (code, op0, op1);
10598 /* Return 1 if we know that X, a comparison operation, is not operating
10599 on a floating-point value or is EQ or NE, meaning that we can safely
10603 reversible_comparison_p (x)
10606 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10608 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10611 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10614 case MODE_PARTIAL_INT:
10615 case MODE_COMPLEX_INT:
10619 /* If the mode of the condition codes tells us that this is safe,
10620 we need look no further. */
10621 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10624 /* Otherwise try and find where the condition codes were last set and
10626 x = get_last_value (XEXP (x, 0));
10627 return (x && GET_CODE (x) == COMPARE
10628 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10635 /* Utility function for following routine. Called when X is part of a value
10636 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10637 for each register mentioned. Similar to mention_regs in cse.c */
10640 update_table_tick (x)
10643 register enum rtx_code code = GET_CODE (x);
10644 register const char *fmt = GET_RTX_FORMAT (code);
10649 int regno = REGNO (x);
10650 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10651 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10653 for (i = regno; i < endregno; i++)
10654 reg_last_set_table_tick[i] = label_tick;
10659 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10660 /* Note that we can't have an "E" in values stored; see
10661 get_last_value_validate. */
10663 update_table_tick (XEXP (x, i));
10666 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10667 are saying that the register is clobbered and we no longer know its
10668 value. If INSN is zero, don't update reg_last_set; this is only permitted
10669 with VALUE also zero and is used to invalidate the register. */
10672 record_value_for_reg (reg, insn, value)
10677 int regno = REGNO (reg);
10678 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10679 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10682 /* If VALUE contains REG and we have a previous value for REG, substitute
10683 the previous value. */
10684 if (value && insn && reg_overlap_mentioned_p (reg, value))
10688 /* Set things up so get_last_value is allowed to see anything set up to
10690 subst_low_cuid = INSN_CUID (insn);
10691 tem = get_last_value (reg);
10694 value = replace_rtx (copy_rtx (value), reg, tem);
10697 /* For each register modified, show we don't know its value, that
10698 we don't know about its bitwise content, that its value has been
10699 updated, and that we don't know the location of the death of the
10701 for (i = regno; i < endregno; i ++)
10704 reg_last_set[i] = insn;
10705 reg_last_set_value[i] = 0;
10706 reg_last_set_mode[i] = 0;
10707 reg_last_set_nonzero_bits[i] = 0;
10708 reg_last_set_sign_bit_copies[i] = 0;
10709 reg_last_death[i] = 0;
10712 /* Mark registers that are being referenced in this value. */
10714 update_table_tick (value);
10716 /* Now update the status of each register being set.
10717 If someone is using this register in this block, set this register
10718 to invalid since we will get confused between the two lives in this
10719 basic block. This makes using this register always invalid. In cse, we
10720 scan the table to invalidate all entries using this register, but this
10721 is too much work for us. */
10723 for (i = regno; i < endregno; i++)
10725 reg_last_set_label[i] = label_tick;
10726 if (value && reg_last_set_table_tick[i] == label_tick)
10727 reg_last_set_invalid[i] = 1;
10729 reg_last_set_invalid[i] = 0;
10732 /* The value being assigned might refer to X (like in "x++;"). In that
10733 case, we must replace it with (clobber (const_int 0)) to prevent
10735 if (value && ! get_last_value_validate (&value, insn,
10736 reg_last_set_label[regno], 0))
10738 value = copy_rtx (value);
10739 if (! get_last_value_validate (&value, insn,
10740 reg_last_set_label[regno], 1))
10744 /* For the main register being modified, update the value, the mode, the
10745 nonzero bits, and the number of sign bit copies. */
10747 reg_last_set_value[regno] = value;
10751 subst_low_cuid = INSN_CUID (insn);
10752 reg_last_set_mode[regno] = GET_MODE (reg);
10753 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10754 reg_last_set_sign_bit_copies[regno]
10755 = num_sign_bit_copies (value, GET_MODE (reg));
10759 /* Called via note_stores from record_dead_and_set_regs to handle one
10760 SET or CLOBBER in an insn. DATA is the instruction in which the
10761 set is occurring. */
10764 record_dead_and_set_regs_1 (dest, setter, data)
10768 rtx record_dead_insn = (rtx) data;
10770 if (GET_CODE (dest) == SUBREG)
10771 dest = SUBREG_REG (dest);
10773 if (GET_CODE (dest) == REG)
10775 /* If we are setting the whole register, we know its value. Otherwise
10776 show that we don't know the value. We can handle SUBREG in
10778 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10779 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10780 else if (GET_CODE (setter) == SET
10781 && GET_CODE (SET_DEST (setter)) == SUBREG
10782 && SUBREG_REG (SET_DEST (setter)) == dest
10783 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10784 && subreg_lowpart_p (SET_DEST (setter)))
10785 record_value_for_reg (dest, record_dead_insn,
10786 gen_lowpart_for_combine (GET_MODE (dest),
10787 SET_SRC (setter)));
10789 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10791 else if (GET_CODE (dest) == MEM
10792 /* Ignore pushes, they clobber nothing. */
10793 && ! push_operand (dest, GET_MODE (dest)))
10794 mem_last_set = INSN_CUID (record_dead_insn);
10797 /* Update the records of when each REG was most recently set or killed
10798 for the things done by INSN. This is the last thing done in processing
10799 INSN in the combiner loop.
10801 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10802 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10803 and also the similar information mem_last_set (which insn most recently
10804 modified memory) and last_call_cuid (which insn was the most recent
10805 subroutine call). */
10808 record_dead_and_set_regs (insn)
10814 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10816 if (REG_NOTE_KIND (link) == REG_DEAD
10817 && GET_CODE (XEXP (link, 0)) == REG)
10819 int regno = REGNO (XEXP (link, 0));
10821 = regno + (regno < FIRST_PSEUDO_REGISTER
10822 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10825 for (i = regno; i < endregno; i++)
10826 reg_last_death[i] = insn;
10828 else if (REG_NOTE_KIND (link) == REG_INC)
10829 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10832 if (GET_CODE (insn) == CALL_INSN)
10834 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10835 if (call_used_regs[i])
10837 reg_last_set_value[i] = 0;
10838 reg_last_set_mode[i] = 0;
10839 reg_last_set_nonzero_bits[i] = 0;
10840 reg_last_set_sign_bit_copies[i] = 0;
10841 reg_last_death[i] = 0;
10844 last_call_cuid = mem_last_set = INSN_CUID (insn);
10847 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10850 /* Utility routine for the following function. Verify that all the registers
10851 mentioned in *LOC are valid when *LOC was part of a value set when
10852 label_tick == TICK. Return 0 if some are not.
10854 If REPLACE is non-zero, replace the invalid reference with
10855 (clobber (const_int 0)) and return 1. This replacement is useful because
10856 we often can get useful information about the form of a value (e.g., if
10857 it was produced by a shift that always produces -1 or 0) even though
10858 we don't know exactly what registers it was produced from. */
10861 get_last_value_validate (loc, insn, tick, replace)
10868 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10869 int len = GET_RTX_LENGTH (GET_CODE (x));
10872 if (GET_CODE (x) == REG)
10874 int regno = REGNO (x);
10875 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10876 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10879 for (j = regno; j < endregno; j++)
10880 if (reg_last_set_invalid[j]
10881 /* If this is a pseudo-register that was only set once and not
10882 live at the beginning of the function, it is always valid. */
10883 || (! (regno >= FIRST_PSEUDO_REGISTER
10884 && REG_N_SETS (regno) == 1
10885 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))
10886 && reg_last_set_label[j] > tick))
10889 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10895 /* If this is a memory reference, make sure that there were
10896 no stores after it that might have clobbered the value. We don't
10897 have alias info, so we assume any store invalidates it. */
10898 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10899 && INSN_CUID (insn) <= mem_last_set)
10902 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10906 for (i = 0; i < len; i++)
10908 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10909 /* Don't bother with these. They shouldn't occur anyway. */
10913 /* If we haven't found a reason for it to be invalid, it is valid. */
10917 /* Get the last value assigned to X, if known. Some registers
10918 in the value may be replaced with (clobber (const_int 0)) if their value
10919 is known longer known reliably. */
10928 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10929 then convert it to the desired mode. If this is a paradoxical SUBREG,
10930 we cannot predict what values the "extra" bits might have. */
10931 if (GET_CODE (x) == SUBREG
10932 && subreg_lowpart_p (x)
10933 && (GET_MODE_SIZE (GET_MODE (x))
10934 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10935 && (value = get_last_value (SUBREG_REG (x))) != 0)
10936 return gen_lowpart_for_combine (GET_MODE (x), value);
10938 if (GET_CODE (x) != REG)
10942 value = reg_last_set_value[regno];
10944 /* If we don't have a value, or if it isn't for this basic block and
10945 it's either a hard register, set more than once, or it's a live
10946 at the beginning of the function, return 0.
10948 Because if it's not live at the beginnning of the function then the reg
10949 is always set before being used (is never used without being set).
10950 And, if it's set only once, and it's always set before use, then all
10951 uses must have the same last value, even if it's not from this basic
10955 || (reg_last_set_label[regno] != label_tick
10956 && (regno < FIRST_PSEUDO_REGISTER
10957 || REG_N_SETS (regno) != 1
10958 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, regno))))
10961 /* If the value was set in a later insn than the ones we are processing,
10962 we can't use it even if the register was only set once. */
10963 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10966 /* If the value has all its registers valid, return it. */
10967 if (get_last_value_validate (&value, reg_last_set[regno],
10968 reg_last_set_label[regno], 0))
10971 /* Otherwise, make a copy and replace any invalid register with
10972 (clobber (const_int 0)). If that fails for some reason, return 0. */
10974 value = copy_rtx (value);
10975 if (get_last_value_validate (&value, reg_last_set[regno],
10976 reg_last_set_label[regno], 1))
10982 /* Return nonzero if expression X refers to a REG or to memory
10983 that is set in an instruction more recent than FROM_CUID. */
10986 use_crosses_set_p (x, from_cuid)
10990 register const char *fmt;
10992 register enum rtx_code code = GET_CODE (x);
10996 register int regno = REGNO (x);
10997 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10998 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11000 #ifdef PUSH_ROUNDING
11001 /* Don't allow uses of the stack pointer to be moved,
11002 because we don't know whether the move crosses a push insn. */
11003 if (regno == STACK_POINTER_REGNUM)
11006 for (;regno < endreg; regno++)
11007 if (reg_last_set[regno]
11008 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11013 if (code == MEM && mem_last_set > from_cuid)
11016 fmt = GET_RTX_FORMAT (code);
11018 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11023 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11024 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11027 else if (fmt[i] == 'e'
11028 && use_crosses_set_p (XEXP (x, i), from_cuid))
11034 /* Define three variables used for communication between the following
11037 static int reg_dead_regno, reg_dead_endregno;
11038 static int reg_dead_flag;
11040 /* Function called via note_stores from reg_dead_at_p.
11042 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11043 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11046 reg_dead_at_p_1 (dest, x, data)
11049 void *data ATTRIBUTE_UNUSED;
11051 int regno, endregno;
11053 if (GET_CODE (dest) != REG)
11056 regno = REGNO (dest);
11057 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11058 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11060 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11061 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11064 /* Return non-zero if REG is known to be dead at INSN.
11066 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11067 referencing REG, it is dead. If we hit a SET referencing REG, it is
11068 live. Otherwise, see if it is live or dead at the start of the basic
11069 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11070 must be assumed to be always live. */
11073 reg_dead_at_p (reg, insn)
11079 /* Set variables for reg_dead_at_p_1. */
11080 reg_dead_regno = REGNO (reg);
11081 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11082 ? HARD_REGNO_NREGS (reg_dead_regno,
11088 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11089 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11091 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11092 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11096 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11097 beginning of function. */
11098 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11099 insn = prev_nonnote_insn (insn))
11101 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11103 return reg_dead_flag == 1 ? 1 : 0;
11105 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11109 /* Get the basic block number that we were in. */
11114 for (block = 0; block < n_basic_blocks; block++)
11115 if (insn == BLOCK_HEAD (block))
11118 if (block == n_basic_blocks)
11122 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11123 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11129 /* Note hard registers in X that are used. This code is similar to
11130 that in flow.c, but much simpler since we don't care about pseudos. */
11133 mark_used_regs_combine (x)
11136 register RTX_CODE code = GET_CODE (x);
11137 register int regno;
11149 case ADDR_DIFF_VEC:
11152 /* CC0 must die in the insn after it is set, so we don't need to take
11153 special note of it here. */
11159 /* If we are clobbering a MEM, mark any hard registers inside the
11160 address as used. */
11161 if (GET_CODE (XEXP (x, 0)) == MEM)
11162 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11167 /* A hard reg in a wide mode may really be multiple registers.
11168 If so, mark all of them just like the first. */
11169 if (regno < FIRST_PSEUDO_REGISTER)
11171 /* None of this applies to the stack, frame or arg pointers */
11172 if (regno == STACK_POINTER_REGNUM
11173 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11174 || regno == HARD_FRAME_POINTER_REGNUM
11176 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11177 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11179 || regno == FRAME_POINTER_REGNUM)
11182 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11184 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11190 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11192 register rtx testreg = SET_DEST (x);
11194 while (GET_CODE (testreg) == SUBREG
11195 || GET_CODE (testreg) == ZERO_EXTRACT
11196 || GET_CODE (testreg) == SIGN_EXTRACT
11197 || GET_CODE (testreg) == STRICT_LOW_PART)
11198 testreg = XEXP (testreg, 0);
11200 if (GET_CODE (testreg) == MEM)
11201 mark_used_regs_combine (XEXP (testreg, 0));
11203 mark_used_regs_combine (SET_SRC (x));
11211 /* Recursively scan the operands of this expression. */
11214 register const char *fmt = GET_RTX_FORMAT (code);
11216 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11219 mark_used_regs_combine (XEXP (x, i));
11220 else if (fmt[i] == 'E')
11224 for (j = 0; j < XVECLEN (x, i); j++)
11225 mark_used_regs_combine (XVECEXP (x, i, j));
11232 /* Remove register number REGNO from the dead registers list of INSN.
11234 Return the note used to record the death, if there was one. */
11237 remove_death (regno, insn)
11241 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11245 REG_N_DEATHS (regno)--;
11246 remove_note (insn, note);
11252 /* For each register (hardware or pseudo) used within expression X, if its
11253 death is in an instruction with cuid between FROM_CUID (inclusive) and
11254 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11255 list headed by PNOTES.
11257 That said, don't move registers killed by maybe_kill_insn.
11259 This is done when X is being merged by combination into TO_INSN. These
11260 notes will then be distributed as needed. */
11263 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11265 rtx maybe_kill_insn;
11270 register const char *fmt;
11271 register int len, i;
11272 register enum rtx_code code = GET_CODE (x);
11276 register int regno = REGNO (x);
11277 register rtx where_dead = reg_last_death[regno];
11278 register rtx before_dead, after_dead;
11280 /* Don't move the register if it gets killed in between from and to */
11281 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11282 && !reg_referenced_p (x, maybe_kill_insn))
11285 /* WHERE_DEAD could be a USE insn made by combine, so first we
11286 make sure that we have insns with valid INSN_CUID values. */
11287 before_dead = where_dead;
11288 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11289 before_dead = PREV_INSN (before_dead);
11290 after_dead = where_dead;
11291 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11292 after_dead = NEXT_INSN (after_dead);
11294 if (before_dead && after_dead
11295 && INSN_CUID (before_dead) >= from_cuid
11296 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11297 || (where_dead != after_dead
11298 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11300 rtx note = remove_death (regno, where_dead);
11302 /* It is possible for the call above to return 0. This can occur
11303 when reg_last_death points to I2 or I1 that we combined with.
11304 In that case make a new note.
11306 We must also check for the case where X is a hard register
11307 and NOTE is a death note for a range of hard registers
11308 including X. In that case, we must put REG_DEAD notes for
11309 the remaining registers in place of NOTE. */
11311 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11312 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11313 > GET_MODE_SIZE (GET_MODE (x))))
11315 int deadregno = REGNO (XEXP (note, 0));
11317 = (deadregno + HARD_REGNO_NREGS (deadregno,
11318 GET_MODE (XEXP (note, 0))));
11319 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11322 for (i = deadregno; i < deadend; i++)
11323 if (i < regno || i >= ourend)
11324 REG_NOTES (where_dead)
11325 = gen_rtx_EXPR_LIST (REG_DEAD,
11326 gen_rtx_REG (reg_raw_mode[i], i),
11327 REG_NOTES (where_dead));
11329 /* If we didn't find any note, or if we found a REG_DEAD note that
11330 covers only part of the given reg, and we have a multi-reg hard
11331 register, then to be safe we must check for REG_DEAD notes
11332 for each register other than the first. They could have
11333 their own REG_DEAD notes lying around. */
11334 else if ((note == 0
11336 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11337 < GET_MODE_SIZE (GET_MODE (x)))))
11338 && regno < FIRST_PSEUDO_REGISTER
11339 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11341 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11346 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11350 for (i = regno + offset; i < ourend; i++)
11351 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11352 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11355 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11357 XEXP (note, 1) = *pnotes;
11361 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11363 REG_N_DEATHS (regno)++;
11369 else if (GET_CODE (x) == SET)
11371 rtx dest = SET_DEST (x);
11373 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11375 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11376 that accesses one word of a multi-word item, some
11377 piece of everything register in the expression is used by
11378 this insn, so remove any old death. */
11380 if (GET_CODE (dest) == ZERO_EXTRACT
11381 || GET_CODE (dest) == STRICT_LOW_PART
11382 || (GET_CODE (dest) == SUBREG
11383 && (((GET_MODE_SIZE (GET_MODE (dest))
11384 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11385 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11386 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11388 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11392 /* If this is some other SUBREG, we know it replaces the entire
11393 value, so use that as the destination. */
11394 if (GET_CODE (dest) == SUBREG)
11395 dest = SUBREG_REG (dest);
11397 /* If this is a MEM, adjust deaths of anything used in the address.
11398 For a REG (the only other possibility), the entire value is
11399 being replaced so the old value is not used in this insn. */
11401 if (GET_CODE (dest) == MEM)
11402 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11407 else if (GET_CODE (x) == CLOBBER)
11410 len = GET_RTX_LENGTH (code);
11411 fmt = GET_RTX_FORMAT (code);
11413 for (i = 0; i < len; i++)
11418 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11419 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11422 else if (fmt[i] == 'e')
11423 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11427 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11428 pattern of an insn. X must be a REG. */
11431 reg_bitfield_target_p (x, body)
11437 if (GET_CODE (body) == SET)
11439 rtx dest = SET_DEST (body);
11441 int regno, tregno, endregno, endtregno;
11443 if (GET_CODE (dest) == ZERO_EXTRACT)
11444 target = XEXP (dest, 0);
11445 else if (GET_CODE (dest) == STRICT_LOW_PART)
11446 target = SUBREG_REG (XEXP (dest, 0));
11450 if (GET_CODE (target) == SUBREG)
11451 target = SUBREG_REG (target);
11453 if (GET_CODE (target) != REG)
11456 tregno = REGNO (target), regno = REGNO (x);
11457 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11458 return target == x;
11460 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11461 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11463 return endregno > tregno && regno < endtregno;
11466 else if (GET_CODE (body) == PARALLEL)
11467 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11468 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11474 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11475 as appropriate. I3 and I2 are the insns resulting from the combination
11476 insns including FROM (I2 may be zero).
11478 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11479 not need REG_DEAD notes because they are being substituted for. This
11480 saves searching in the most common cases.
11482 Each note in the list is either ignored or placed on some insns, depending
11483 on the type of note. */
11486 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11490 rtx elim_i2, elim_i1;
11492 rtx note, next_note;
11495 for (note = notes; note; note = next_note)
11497 rtx place = 0, place2 = 0;
11499 /* If this NOTE references a pseudo register, ensure it references
11500 the latest copy of that register. */
11501 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11502 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11503 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11505 next_note = XEXP (note, 1);
11506 switch (REG_NOTE_KIND (note))
11509 case REG_EXEC_COUNT:
11510 /* Doesn't matter much where we put this, as long as it's somewhere.
11511 It is preferable to keep these notes on branches, which is most
11512 likely to be i3. */
11516 case REG_EH_REGION:
11517 case REG_EH_RETHROW:
11518 /* These notes must remain with the call. It should not be
11519 possible for both I2 and I3 to be a call. */
11520 if (GET_CODE (i3) == CALL_INSN)
11522 else if (i2 && GET_CODE (i2) == CALL_INSN)
11529 /* Any clobbers for i3 may still exist, and so we must process
11530 REG_UNUSED notes from that insn.
11532 Any clobbers from i2 or i1 can only exist if they were added by
11533 recog_for_combine. In that case, recog_for_combine created the
11534 necessary REG_UNUSED notes. Trying to keep any original
11535 REG_UNUSED notes from these insns can cause incorrect output
11536 if it is for the same register as the original i3 dest.
11537 In that case, we will notice that the register is set in i3,
11538 and then add a REG_UNUSED note for the destination of i3, which
11539 is wrong. However, it is possible to have REG_UNUSED notes from
11540 i2 or i1 for register which were both used and clobbered, so
11541 we keep notes from i2 or i1 if they will turn into REG_DEAD
11544 /* If this register is set or clobbered in I3, put the note there
11545 unless there is one already. */
11546 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11548 if (from_insn != i3)
11551 if (! (GET_CODE (XEXP (note, 0)) == REG
11552 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11553 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11556 /* Otherwise, if this register is used by I3, then this register
11557 now dies here, so we must put a REG_DEAD note here unless there
11559 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11560 && ! (GET_CODE (XEXP (note, 0)) == REG
11561 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11562 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11564 PUT_REG_NOTE_KIND (note, REG_DEAD);
11573 /* These notes say something about results of an insn. We can
11574 only support them if they used to be on I3 in which case they
11575 remain on I3. Otherwise they are ignored.
11577 If the note refers to an expression that is not a constant, we
11578 must also ignore the note since we cannot tell whether the
11579 equivalence is still true. It might be possible to do
11580 slightly better than this (we only have a problem if I2DEST
11581 or I1DEST is present in the expression), but it doesn't
11582 seem worth the trouble. */
11584 if (from_insn == i3
11585 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11590 case REG_NO_CONFLICT:
11591 /* These notes say something about how a register is used. They must
11592 be present on any use of the register in I2 or I3. */
11593 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11596 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11606 /* This can show up in several ways -- either directly in the
11607 pattern, or hidden off in the constant pool with (or without?)
11608 a REG_EQUAL note. */
11609 /* ??? Ignore the without-reg_equal-note problem for now. */
11610 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11611 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11612 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11613 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11617 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11618 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11619 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11620 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11630 /* It is too much trouble to try to see if this note is still
11631 correct in all situations. It is better to simply delete it. */
11635 /* If the insn previously containing this note still exists,
11636 put it back where it was. Otherwise move it to the previous
11637 insn. Adjust the corresponding REG_LIBCALL note. */
11638 if (GET_CODE (from_insn) != NOTE)
11642 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11643 place = prev_real_insn (from_insn);
11645 XEXP (tem, 0) = place;
11650 /* This is handled similarly to REG_RETVAL. */
11651 if (GET_CODE (from_insn) != NOTE)
11655 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11656 place = next_real_insn (from_insn);
11658 XEXP (tem, 0) = place;
11663 /* If the register is used as an input in I3, it dies there.
11664 Similarly for I2, if it is non-zero and adjacent to I3.
11666 If the register is not used as an input in either I3 or I2
11667 and it is not one of the registers we were supposed to eliminate,
11668 there are two possibilities. We might have a non-adjacent I2
11669 or we might have somehow eliminated an additional register
11670 from a computation. For example, we might have had A & B where
11671 we discover that B will always be zero. In this case we will
11672 eliminate the reference to A.
11674 In both cases, we must search to see if we can find a previous
11675 use of A and put the death note there. */
11678 && GET_CODE (from_insn) == CALL_INSN
11679 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11681 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11683 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11684 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11687 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11690 /* If the register is used in both I2 and I3 and it dies in I3,
11691 we might have added another reference to it. If reg_n_refs
11692 was 2, bump it to 3. This has to be correct since the
11693 register must have been set somewhere. The reason this is
11694 done is because local-alloc.c treats 2 references as a
11697 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11698 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11699 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11700 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11704 basic_block bb = BASIC_BLOCK (this_basic_block);
11706 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11708 if (GET_RTX_CLASS (GET_CODE (tem)) != 'i')
11710 if (tem == bb->head)
11715 /* If the register is being set at TEM, see if that is all
11716 TEM is doing. If so, delete TEM. Otherwise, make this
11717 into a REG_UNUSED note instead. */
11718 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11720 rtx set = single_set (tem);
11721 rtx inner_dest = 0;
11723 rtx cc0_setter = NULL_RTX;
11727 for (inner_dest = SET_DEST (set);
11728 GET_CODE (inner_dest) == STRICT_LOW_PART
11729 || GET_CODE (inner_dest) == SUBREG
11730 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11731 inner_dest = XEXP (inner_dest, 0))
11734 /* Verify that it was the set, and not a clobber that
11735 modified the register.
11737 CC0 targets must be careful to maintain setter/user
11738 pairs. If we cannot delete the setter due to side
11739 effects, mark the user with an UNUSED note instead
11742 if (set != 0 && ! side_effects_p (SET_SRC (set))
11743 && rtx_equal_p (XEXP (note, 0), inner_dest)
11745 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11746 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11747 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11751 /* Move the notes and links of TEM elsewhere.
11752 This might delete other dead insns recursively.
11753 First set the pattern to something that won't use
11756 PATTERN (tem) = pc_rtx;
11758 distribute_notes (REG_NOTES (tem), tem, tem,
11759 NULL_RTX, NULL_RTX, NULL_RTX);
11760 distribute_links (LOG_LINKS (tem));
11762 PUT_CODE (tem, NOTE);
11763 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11764 NOTE_SOURCE_FILE (tem) = 0;
11767 /* Delete the setter too. */
11770 PATTERN (cc0_setter) = pc_rtx;
11772 distribute_notes (REG_NOTES (cc0_setter),
11773 cc0_setter, cc0_setter,
11774 NULL_RTX, NULL_RTX, NULL_RTX);
11775 distribute_links (LOG_LINKS (cc0_setter));
11777 PUT_CODE (cc0_setter, NOTE);
11778 NOTE_LINE_NUMBER (cc0_setter)
11779 = NOTE_INSN_DELETED;
11780 NOTE_SOURCE_FILE (cc0_setter) = 0;
11784 /* If the register is both set and used here, put the
11785 REG_DEAD note here, but place a REG_UNUSED note
11786 here too unless there already is one. */
11787 else if (reg_referenced_p (XEXP (note, 0),
11792 if (! find_regno_note (tem, REG_UNUSED,
11793 REGNO (XEXP (note, 0))))
11795 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
11800 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11802 /* If there isn't already a REG_UNUSED note, put one
11804 if (! find_regno_note (tem, REG_UNUSED,
11805 REGNO (XEXP (note, 0))))
11810 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11811 || (GET_CODE (tem) == CALL_INSN
11812 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11816 /* If we are doing a 3->2 combination, and we have a
11817 register which formerly died in i3 and was not used
11818 by i2, which now no longer dies in i3 and is used in
11819 i2 but does not die in i2, and place is between i2
11820 and i3, then we may need to move a link from place to
11822 if (i2 && INSN_UID (place) <= max_uid_cuid
11823 && INSN_CUID (place) > INSN_CUID (i2)
11824 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11825 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11827 rtx links = LOG_LINKS (place);
11828 LOG_LINKS (place) = 0;
11829 distribute_links (links);
11834 if (tem == bb->head)
11838 /* We haven't found an insn for the death note and it
11839 is still a REG_DEAD note, but we have hit the beginning
11840 of the block. If the existing life info says the reg
11841 was dead, there's nothing left to do. Otherwise, we'll
11842 need to do a global life update after combine. */
11843 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0)
11845 int regno = REGNO (XEXP (note, 0));
11846 if (REGNO_REG_SET_P (bb->global_live_at_start, regno))
11848 SET_BIT (refresh_blocks, this_basic_block);
11854 /* If the register is set or already dead at PLACE, we needn't do
11855 anything with this note if it is still a REG_DEAD note.
11856 We can here if it is set at all, not if is it totally replace,
11857 which is what `dead_or_set_p' checks, so also check for it being
11860 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11862 int regno = REGNO (XEXP (note, 0));
11864 if (dead_or_set_p (place, XEXP (note, 0))
11865 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11867 /* Unless the register previously died in PLACE, clear
11868 reg_last_death. [I no longer understand why this is
11870 if (reg_last_death[regno] != place)
11871 reg_last_death[regno] = 0;
11875 reg_last_death[regno] = place;
11877 /* If this is a death note for a hard reg that is occupying
11878 multiple registers, ensure that we are still using all
11879 parts of the object. If we find a piece of the object
11880 that is unused, we must add a USE for that piece before
11881 PLACE and put the appropriate REG_DEAD note on it.
11883 An alternative would be to put a REG_UNUSED for the pieces
11884 on the insn that set the register, but that can't be done if
11885 it is not in the same block. It is simpler, though less
11886 efficient, to add the USE insns. */
11888 if (place && regno < FIRST_PSEUDO_REGISTER
11889 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11892 = regno + HARD_REGNO_NREGS (regno,
11893 GET_MODE (XEXP (note, 0)));
11897 for (i = regno; i < endregno; i++)
11898 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11899 && ! find_regno_fusage (place, USE, i))
11901 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11904 /* See if we already placed a USE note for this
11905 register in front of PLACE. */
11907 GET_CODE (PREV_INSN (p)) == INSN
11908 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11910 if (rtx_equal_p (piece,
11911 XEXP (PATTERN (PREV_INSN (p)), 0)))
11920 = emit_insn_before (gen_rtx_USE (VOIDmode,
11923 REG_NOTES (use_insn)
11924 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11925 REG_NOTES (use_insn));
11931 /* Check for the case where the register dying partially
11932 overlaps the register set by this insn. */
11934 for (i = regno; i < endregno; i++)
11935 if (dead_or_set_regno_p (place, i))
11943 /* Put only REG_DEAD notes for pieces that are
11944 still used and that are not already dead or set. */
11946 for (i = regno; i < endregno; i++)
11948 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11950 if ((reg_referenced_p (piece, PATTERN (place))
11951 || (GET_CODE (place) == CALL_INSN
11952 && find_reg_fusage (place, USE, piece)))
11953 && ! dead_or_set_p (place, piece)
11954 && ! reg_bitfield_target_p (piece,
11957 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11958 REG_NOTES (place));
11968 /* Any other notes should not be present at this point in the
11975 XEXP (note, 1) = REG_NOTES (place);
11976 REG_NOTES (place) = note;
11978 else if ((REG_NOTE_KIND (note) == REG_DEAD
11979 || REG_NOTE_KIND (note) == REG_UNUSED)
11980 && GET_CODE (XEXP (note, 0)) == REG)
11981 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11985 if ((REG_NOTE_KIND (note) == REG_DEAD
11986 || REG_NOTE_KIND (note) == REG_UNUSED)
11987 && GET_CODE (XEXP (note, 0)) == REG)
11988 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11990 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11991 REG_NOTE_KIND (note),
11993 REG_NOTES (place2));
11998 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11999 I3, I2, and I1 to new locations. This is also called in one case to
12000 add a link pointing at I3 when I3's destination is changed. */
12003 distribute_links (links)
12006 rtx link, next_link;
12008 for (link = links; link; link = next_link)
12014 next_link = XEXP (link, 1);
12016 /* If the insn that this link points to is a NOTE or isn't a single
12017 set, ignore it. In the latter case, it isn't clear what we
12018 can do other than ignore the link, since we can't tell which
12019 register it was for. Such links wouldn't be used by combine
12022 It is not possible for the destination of the target of the link to
12023 have been changed by combine. The only potential of this is if we
12024 replace I3, I2, and I1 by I3 and I2. But in that case the
12025 destination of I2 also remains unchanged. */
12027 if (GET_CODE (XEXP (link, 0)) == NOTE
12028 || (set = single_set (XEXP (link, 0))) == 0)
12031 reg = SET_DEST (set);
12032 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12033 || GET_CODE (reg) == SIGN_EXTRACT
12034 || GET_CODE (reg) == STRICT_LOW_PART)
12035 reg = XEXP (reg, 0);
12037 /* A LOG_LINK is defined as being placed on the first insn that uses
12038 a register and points to the insn that sets the register. Start
12039 searching at the next insn after the target of the link and stop
12040 when we reach a set of the register or the end of the basic block.
12042 Note that this correctly handles the link that used to point from
12043 I3 to I2. Also note that not much searching is typically done here
12044 since most links don't point very far away. */
12046 for (insn = NEXT_INSN (XEXP (link, 0));
12047 (insn && (this_basic_block == n_basic_blocks - 1
12048 || BLOCK_HEAD (this_basic_block + 1) != insn));
12049 insn = NEXT_INSN (insn))
12050 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
12051 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12053 if (reg_referenced_p (reg, PATTERN (insn)))
12057 else if (GET_CODE (insn) == CALL_INSN
12058 && find_reg_fusage (insn, USE, reg))
12064 /* If we found a place to put the link, place it there unless there
12065 is already a link to the same insn as LINK at that point. */
12071 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12072 if (XEXP (link2, 0) == XEXP (link, 0))
12077 XEXP (link, 1) = LOG_LINKS (place);
12078 LOG_LINKS (place) = link;
12080 /* Set added_links_insn to the earliest insn we added a
12082 if (added_links_insn == 0
12083 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12084 added_links_insn = place;
12090 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12096 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12097 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12098 insn = NEXT_INSN (insn);
12100 if (INSN_UID (insn) > max_uid_cuid)
12103 return INSN_CUID (insn);
12107 dump_combine_stats (file)
12112 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12113 combine_attempts, combine_merges, combine_extras, combine_successes);
12117 dump_combine_total_stats (file)
12122 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12123 total_attempts, total_merges, total_extras, total_successes);