1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each extended basic block in scanning order. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
924 if (!NONDEBUG_INSN_P (insn))
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1014 /* Main entry point for combiner. F is the first insn of the function.
1015 NREGS is the first unused pseudo-reg number.
1017 Return nonzero if the combiner has turned an indirect jump
1018 instruction into a direct jump. */
1020 combine_instructions (rtx f, unsigned int nregs)
1026 rtx links, nextlinks;
1028 basic_block last_bb;
1030 int new_direct_jump_p = 0;
1032 for (first = f; first && !INSN_P (first); )
1033 first = NEXT_INSN (first);
1037 combine_attempts = 0;
1040 combine_successes = 0;
1042 rtl_hooks = combine_rtl_hooks;
1044 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1046 init_recog_no_volatile ();
1048 /* Allocate array for insn info. */
1049 max_uid_known = get_max_uid ();
1050 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1051 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1053 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1055 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1056 problems when, for example, we have j <<= 1 in a loop. */
1058 nonzero_sign_valid = 0;
1059 label_tick = label_tick_ebb_start = 1;
1061 /* Scan all SETs and see if we can deduce anything about what
1062 bits are known to be zero for some registers and how many copies
1063 of the sign bit are known to exist for those registers.
1065 Also set any known values so that we can use it while searching
1066 for what bits are known to be set. */
1068 setup_incoming_promotions (first);
1069 /* Allow the entry block and the first block to fall into the same EBB.
1070 Conceptually the incoming promotions are assigned to the entry block. */
1071 last_bb = ENTRY_BLOCK_PTR;
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block)
1076 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1081 if (!single_pred_p (this_basic_block)
1082 || single_pred (this_basic_block) != last_bb)
1083 label_tick_ebb_start = label_tick;
1084 last_bb = this_basic_block;
1086 FOR_BB_INSNS (this_basic_block, insn)
1087 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1089 subst_low_luid = DF_INSN_LUID (insn);
1092 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1094 record_dead_and_set_regs (insn);
1097 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1098 if (REG_NOTE_KIND (links) == REG_INC)
1099 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1103 /* Record the current insn_rtx_cost of this instruction. */
1104 if (NONJUMP_INSN_P (insn))
1105 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1106 optimize_this_for_speed_p);
1108 fprintf(dump_file, "insn_cost %d: %d\n",
1109 INSN_UID (insn), INSN_COST (insn));
1113 nonzero_sign_valid = 1;
1115 /* Now scan all the insns in forward order. */
1116 label_tick = label_tick_ebb_start = 1;
1118 setup_incoming_promotions (first);
1119 last_bb = ENTRY_BLOCK_PTR;
1121 FOR_EACH_BB (this_basic_block)
1123 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1128 if (!single_pred_p (this_basic_block)
1129 || single_pred (this_basic_block) != last_bb)
1130 label_tick_ebb_start = label_tick;
1131 last_bb = this_basic_block;
1133 rtl_profile_for_bb (this_basic_block);
1134 for (insn = BB_HEAD (this_basic_block);
1135 insn != NEXT_INSN (BB_END (this_basic_block));
1136 insn = next ? next : NEXT_INSN (insn))
1139 if (NONDEBUG_INSN_P (insn))
1141 /* See if we know about function return values before this
1142 insn based upon SUBREG flags. */
1143 check_promoted_subreg (insn, PATTERN (insn));
1145 /* See if we can find hardregs and subreg of pseudos in
1146 narrower modes. This could help turning TRUNCATEs
1148 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1150 /* Try this insn with each insn it links back to. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1153 if ((next = try_combine (insn, XEXP (links, 0),
1154 NULL_RTX, &new_direct_jump_p)) != 0)
1157 /* Try each sequence of three linked insns ending with this one. */
1159 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1161 rtx link = XEXP (links, 0);
1163 /* If the linked insn has been replaced by a note, then there
1164 is no point in pursuing this chain any further. */
1168 for (nextlinks = LOG_LINKS (link);
1170 nextlinks = XEXP (nextlinks, 1))
1171 if ((next = try_combine (insn, link,
1172 XEXP (nextlinks, 0),
1173 &new_direct_jump_p)) != 0)
1178 /* Try to combine a jump insn that uses CC0
1179 with a preceding insn that sets CC0, and maybe with its
1180 logical predecessor as well.
1181 This is how we make decrement-and-branch insns.
1182 We need this special code because data flow connections
1183 via CC0 do not get entered in LOG_LINKS. */
1186 && (prev = prev_nonnote_insn (insn)) != 0
1187 && NONJUMP_INSN_P (prev)
1188 && sets_cc0_p (PATTERN (prev)))
1190 if ((next = try_combine (insn, prev,
1191 NULL_RTX, &new_direct_jump_p)) != 0)
1194 for (nextlinks = LOG_LINKS (prev); nextlinks;
1195 nextlinks = XEXP (nextlinks, 1))
1196 if ((next = try_combine (insn, prev,
1197 XEXP (nextlinks, 0),
1198 &new_direct_jump_p)) != 0)
1202 /* Do the same for an insn that explicitly references CC0. */
1203 if (NONJUMP_INSN_P (insn)
1204 && (prev = prev_nonnote_insn (insn)) != 0
1205 && NONJUMP_INSN_P (prev)
1206 && sets_cc0_p (PATTERN (prev))
1207 && GET_CODE (PATTERN (insn)) == SET
1208 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1210 if ((next = try_combine (insn, prev,
1211 NULL_RTX, &new_direct_jump_p)) != 0)
1214 for (nextlinks = LOG_LINKS (prev); nextlinks;
1215 nextlinks = XEXP (nextlinks, 1))
1216 if ((next = try_combine (insn, prev,
1217 XEXP (nextlinks, 0),
1218 &new_direct_jump_p)) != 0)
1222 /* Finally, see if any of the insns that this insn links to
1223 explicitly references CC0. If so, try this insn, that insn,
1224 and its predecessor if it sets CC0. */
1225 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1226 if (NONJUMP_INSN_P (XEXP (links, 0))
1227 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1228 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1229 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1230 && NONJUMP_INSN_P (prev)
1231 && sets_cc0_p (PATTERN (prev))
1232 && (next = try_combine (insn, XEXP (links, 0),
1233 prev, &new_direct_jump_p)) != 0)
1237 /* Try combining an insn with two different insns whose results it
1239 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1240 for (nextlinks = XEXP (links, 1); nextlinks;
1241 nextlinks = XEXP (nextlinks, 1))
1242 if ((next = try_combine (insn, XEXP (links, 0),
1243 XEXP (nextlinks, 0),
1244 &new_direct_jump_p)) != 0)
1247 /* Try this insn with each REG_EQUAL note it links back to. */
1248 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1251 rtx temp = XEXP (links, 0);
1252 if ((set = single_set (temp)) != 0
1253 && (note = find_reg_equal_equiv_note (temp)) != 0
1254 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1255 /* Avoid using a register that may already been marked
1256 dead by an earlier instruction. */
1257 && ! unmentioned_reg_p (note, SET_SRC (set))
1258 && (GET_MODE (note) == VOIDmode
1259 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1260 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1262 /* Temporarily replace the set's source with the
1263 contents of the REG_EQUAL note. The insn will
1264 be deleted or recognized by try_combine. */
1265 rtx orig = SET_SRC (set);
1266 SET_SRC (set) = note;
1268 i2mod_old_rhs = copy_rtx (orig);
1269 i2mod_new_rhs = copy_rtx (note);
1270 next = try_combine (insn, i2mod, NULL_RTX,
1271 &new_direct_jump_p);
1275 SET_SRC (set) = orig;
1280 record_dead_and_set_regs (insn);
1288 default_rtl_profile ();
1291 new_direct_jump_p |= purge_all_dead_edges ();
1292 delete_noop_moves ();
1295 free (uid_log_links);
1296 free (uid_insn_cost);
1297 VEC_free (reg_stat_type, heap, reg_stat);
1300 struct undo *undo, *next;
1301 for (undo = undobuf.frees; undo; undo = next)
1309 total_attempts += combine_attempts;
1310 total_merges += combine_merges;
1311 total_extras += combine_extras;
1312 total_successes += combine_successes;
1314 nonzero_sign_valid = 0;
1315 rtl_hooks = general_rtl_hooks;
1317 /* Make recognizer allow volatile MEMs again. */
1320 return new_direct_jump_p;
1323 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1326 init_reg_last (void)
1331 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1332 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1335 /* Set up any promoted values for incoming argument registers. */
1338 setup_incoming_promotions (rtx first)
1341 bool strictly_local = false;
1343 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1344 arg = TREE_CHAIN (arg))
1346 rtx reg = DECL_INCOMING_RTL (arg);
1348 enum machine_mode mode1, mode2, mode3, mode4;
1350 /* Only continue if the incoming argument is in a register. */
1354 /* Determine, if possible, whether all call sites of the current
1355 function lie within the current compilation unit. (This does
1356 take into account the exporting of a function via taking its
1357 address, and so forth.) */
1358 strictly_local = cgraph_local_info (current_function_decl)->local;
1360 /* The mode and signedness of the argument before any promotions happen
1361 (equal to the mode of the pseudo holding it at that stage). */
1362 mode1 = TYPE_MODE (TREE_TYPE (arg));
1363 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1365 /* The mode and signedness of the argument after any source language and
1366 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1367 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1368 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1370 /* The mode and signedness of the argument as it is actually passed,
1371 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1372 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1373 TREE_TYPE (cfun->decl), 0);
1375 /* The mode of the register in which the argument is being passed. */
1376 mode4 = GET_MODE (reg);
1378 /* Eliminate sign extensions in the callee when possible. Only
1380 (a) A mode promotion has occurred;
1381 (b) The mode of the register is the same as the mode of
1382 the argument as it is passed; and
1383 (c) Either there's no language level extension, or the extension
1384 from source to end result is valid. The later case is true
1385 when the signedness of the extensions match, or when the
1386 language level extension is unsigned. In the later case,
1387 a zero extension followed by a sign extension is the same
1388 as one big zero extension.
1389 (d) When no language-level promotions (which we cannot guarantee
1390 will have been done by an external caller) are necessary,
1391 unless we know that this function is only ever called from
1392 the current compilation unit -- all of whose call sites will
1393 do the mode1 --> mode2 promotion. */
1396 && (mode1 == mode2 || ((uns1 || !uns3) && strictly_local)))
1398 /* Record that the value was promoted from mode1 to mode3,
1399 so that any sign extension at the head of the current
1400 function may be eliminated. */
1402 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1403 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1404 record_value_for_reg (reg, first, x);
1409 /* Called via note_stores. If X is a pseudo that is narrower than
1410 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1412 If we are setting only a portion of X and we can't figure out what
1413 portion, assume all bits will be used since we don't know what will
1416 Similarly, set how many bits of X are known to be copies of the sign bit
1417 at all locations in the function. This is the smallest number implied
1421 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1423 rtx insn = (rtx) data;
1427 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1428 /* If this register is undefined at the start of the file, we can't
1429 say what its contents were. */
1430 && ! REGNO_REG_SET_P
1431 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1432 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1434 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1436 if (set == 0 || GET_CODE (set) == CLOBBER)
1438 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1439 rsp->sign_bit_copies = 1;
1443 /* If this register is being initialized using itself, and the
1444 register is uninitialized in this basic block, and there are
1445 no LOG_LINKS which set the register, then part of the
1446 register is uninitialized. In that case we can't assume
1447 anything about the number of nonzero bits.
1449 ??? We could do better if we checked this in
1450 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1451 could avoid making assumptions about the insn which initially
1452 sets the register, while still using the information in other
1453 insns. We would have to be careful to check every insn
1454 involved in the combination. */
1457 && reg_referenced_p (x, PATTERN (insn))
1458 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1463 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1465 if (dead_or_set_p (XEXP (link, 0), x))
1470 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1471 rsp->sign_bit_copies = 1;
1476 /* If this is a complex assignment, see if we can convert it into a
1477 simple assignment. */
1478 set = expand_field_assignment (set);
1480 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1481 set what we know about X. */
1483 if (SET_DEST (set) == x
1484 || (GET_CODE (SET_DEST (set)) == SUBREG
1485 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1486 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1487 && SUBREG_REG (SET_DEST (set)) == x))
1489 rtx src = SET_SRC (set);
1491 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1492 /* If X is narrower than a word and SRC is a non-negative
1493 constant that would appear negative in the mode of X,
1494 sign-extend it for use in reg_stat[].nonzero_bits because some
1495 machines (maybe most) will actually do the sign-extension
1496 and this is the conservative approach.
1498 ??? For 2.5, try to tighten up the MD files in this regard
1499 instead of this kludge. */
1501 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1502 && CONST_INT_P (src)
1504 && 0 != (INTVAL (src)
1505 & ((HOST_WIDE_INT) 1
1506 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1507 src = GEN_INT (INTVAL (src)
1508 | ((HOST_WIDE_INT) (-1)
1509 << GET_MODE_BITSIZE (GET_MODE (x))));
1512 /* Don't call nonzero_bits if it cannot change anything. */
1513 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1514 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1515 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1516 if (rsp->sign_bit_copies == 0
1517 || rsp->sign_bit_copies > num)
1518 rsp->sign_bit_copies = num;
1522 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1523 rsp->sign_bit_copies = 1;
1528 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1529 insns that were previously combined into I3 or that will be combined
1530 into the merger of INSN and I3.
1532 Return 0 if the combination is not allowed for any reason.
1534 If the combination is allowed, *PDEST will be set to the single
1535 destination of INSN and *PSRC to the single source, and this function
1539 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1540 rtx *pdest, rtx *psrc)
1549 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1550 && next_active_insn (succ) == i3)
1551 : next_active_insn (insn) == i3);
1553 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1554 or a PARALLEL consisting of such a SET and CLOBBERs.
1556 If INSN has CLOBBER parallel parts, ignore them for our processing.
1557 By definition, these happen during the execution of the insn. When it
1558 is merged with another insn, all bets are off. If they are, in fact,
1559 needed and aren't also supplied in I3, they may be added by
1560 recog_for_combine. Otherwise, it won't match.
1562 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1565 Get the source and destination of INSN. If more than one, can't
1568 if (GET_CODE (PATTERN (insn)) == SET)
1569 set = PATTERN (insn);
1570 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1571 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1573 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1575 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1577 switch (GET_CODE (elt))
1579 /* This is important to combine floating point insns
1580 for the SH4 port. */
1582 /* Combining an isolated USE doesn't make sense.
1583 We depend here on combinable_i3pat to reject them. */
1584 /* The code below this loop only verifies that the inputs of
1585 the SET in INSN do not change. We call reg_set_between_p
1586 to verify that the REG in the USE does not change between
1588 If the USE in INSN was for a pseudo register, the matching
1589 insn pattern will likely match any register; combining this
1590 with any other USE would only be safe if we knew that the
1591 used registers have identical values, or if there was
1592 something to tell them apart, e.g. different modes. For
1593 now, we forgo such complicated tests and simply disallow
1594 combining of USES of pseudo registers with any other USE. */
1595 if (REG_P (XEXP (elt, 0))
1596 && GET_CODE (PATTERN (i3)) == PARALLEL)
1598 rtx i3pat = PATTERN (i3);
1599 int i = XVECLEN (i3pat, 0) - 1;
1600 unsigned int regno = REGNO (XEXP (elt, 0));
1604 rtx i3elt = XVECEXP (i3pat, 0, i);
1606 if (GET_CODE (i3elt) == USE
1607 && REG_P (XEXP (i3elt, 0))
1608 && (REGNO (XEXP (i3elt, 0)) == regno
1609 ? reg_set_between_p (XEXP (elt, 0),
1610 PREV_INSN (insn), i3)
1611 : regno >= FIRST_PSEUDO_REGISTER))
1618 /* We can ignore CLOBBERs. */
1623 /* Ignore SETs whose result isn't used but not those that
1624 have side-effects. */
1625 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1626 && insn_nothrow_p (insn)
1627 && !side_effects_p (elt))
1630 /* If we have already found a SET, this is a second one and
1631 so we cannot combine with this insn. */
1639 /* Anything else means we can't combine. */
1645 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1646 so don't do anything with it. */
1647 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1656 set = expand_field_assignment (set);
1657 src = SET_SRC (set), dest = SET_DEST (set);
1659 /* Don't eliminate a store in the stack pointer. */
1660 if (dest == stack_pointer_rtx
1661 /* Don't combine with an insn that sets a register to itself if it has
1662 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1663 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1664 /* Can't merge an ASM_OPERANDS. */
1665 || GET_CODE (src) == ASM_OPERANDS
1666 /* Can't merge a function call. */
1667 || GET_CODE (src) == CALL
1668 /* Don't eliminate a function call argument. */
1670 && (find_reg_fusage (i3, USE, dest)
1672 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1673 && global_regs[REGNO (dest)])))
1674 /* Don't substitute into an incremented register. */
1675 || FIND_REG_INC_NOTE (i3, dest)
1676 || (succ && FIND_REG_INC_NOTE (succ, dest))
1677 /* Don't substitute into a non-local goto, this confuses CFG. */
1678 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1679 /* Make sure that DEST is not used after SUCC but before I3. */
1680 || (succ && ! all_adjacent
1681 && reg_used_between_p (dest, succ, i3))
1682 /* Make sure that the value that is to be substituted for the register
1683 does not use any registers whose values alter in between. However,
1684 If the insns are adjacent, a use can't cross a set even though we
1685 think it might (this can happen for a sequence of insns each setting
1686 the same destination; last_set of that register might point to
1687 a NOTE). If INSN has a REG_EQUIV note, the register is always
1688 equivalent to the memory so the substitution is valid even if there
1689 are intervening stores. Also, don't move a volatile asm or
1690 UNSPEC_VOLATILE across any other insns. */
1693 || ! find_reg_note (insn, REG_EQUIV, src))
1694 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1695 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1696 || GET_CODE (src) == UNSPEC_VOLATILE))
1697 /* Don't combine across a CALL_INSN, because that would possibly
1698 change whether the life span of some REGs crosses calls or not,
1699 and it is a pain to update that information.
1700 Exception: if source is a constant, moving it later can't hurt.
1701 Accept that as a special case. */
1702 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1705 /* DEST must either be a REG or CC0. */
1708 /* If register alignment is being enforced for multi-word items in all
1709 cases except for parameters, it is possible to have a register copy
1710 insn referencing a hard register that is not allowed to contain the
1711 mode being copied and which would not be valid as an operand of most
1712 insns. Eliminate this problem by not combining with such an insn.
1714 Also, on some machines we don't want to extend the life of a hard
1718 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1719 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1720 /* Don't extend the life of a hard register unless it is
1721 user variable (if we have few registers) or it can't
1722 fit into the desired register (meaning something special
1724 Also avoid substituting a return register into I3, because
1725 reload can't handle a conflict with constraints of other
1727 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1728 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1731 else if (GET_CODE (dest) != CC0)
1735 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1736 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1737 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1739 /* Don't substitute for a register intended as a clobberable
1741 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1742 if (rtx_equal_p (reg, dest))
1745 /* If the clobber represents an earlyclobber operand, we must not
1746 substitute an expression containing the clobbered register.
1747 As we do not analyze the constraint strings here, we have to
1748 make the conservative assumption. However, if the register is
1749 a fixed hard reg, the clobber cannot represent any operand;
1750 we leave it up to the machine description to either accept or
1751 reject use-and-clobber patterns. */
1753 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1754 || !fixed_regs[REGNO (reg)])
1755 if (reg_overlap_mentioned_p (reg, src))
1759 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1760 or not), reject, unless nothing volatile comes between it and I3 */
1762 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1764 /* Make sure succ doesn't contain a volatile reference. */
1765 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1768 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1769 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1773 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1774 to be an explicit register variable, and was chosen for a reason. */
1776 if (GET_CODE (src) == ASM_OPERANDS
1777 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1780 /* If there are any volatile insns between INSN and I3, reject, because
1781 they might affect machine state. */
1783 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1784 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1787 /* If INSN contains an autoincrement or autodecrement, make sure that
1788 register is not used between there and I3, and not already used in
1789 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1790 Also insist that I3 not be a jump; if it were one
1791 and the incremented register were spilled, we would lose. */
1794 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1795 if (REG_NOTE_KIND (link) == REG_INC
1797 || reg_used_between_p (XEXP (link, 0), insn, i3)
1798 || (pred != NULL_RTX
1799 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1800 || (succ != NULL_RTX
1801 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1802 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1807 /* Don't combine an insn that follows a CC0-setting insn.
1808 An insn that uses CC0 must not be separated from the one that sets it.
1809 We do, however, allow I2 to follow a CC0-setting insn if that insn
1810 is passed as I1; in that case it will be deleted also.
1811 We also allow combining in this case if all the insns are adjacent
1812 because that would leave the two CC0 insns adjacent as well.
1813 It would be more logical to test whether CC0 occurs inside I1 or I2,
1814 but that would be much slower, and this ought to be equivalent. */
1816 p = prev_nonnote_insn (insn);
1817 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1822 /* If we get here, we have passed all the tests and the combination is
1831 /* LOC is the location within I3 that contains its pattern or the component
1832 of a PARALLEL of the pattern. We validate that it is valid for combining.
1834 One problem is if I3 modifies its output, as opposed to replacing it
1835 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1836 so would produce an insn that is not equivalent to the original insns.
1840 (set (reg:DI 101) (reg:DI 100))
1841 (set (subreg:SI (reg:DI 101) 0) <foo>)
1843 This is NOT equivalent to:
1845 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1846 (set (reg:DI 101) (reg:DI 100))])
1848 Not only does this modify 100 (in which case it might still be valid
1849 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1851 We can also run into a problem if I2 sets a register that I1
1852 uses and I1 gets directly substituted into I3 (not via I2). In that
1853 case, we would be getting the wrong value of I2DEST into I3, so we
1854 must reject the combination. This case occurs when I2 and I1 both
1855 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1856 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1857 of a SET must prevent combination from occurring.
1859 Before doing the above check, we first try to expand a field assignment
1860 into a set of logical operations.
1862 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1863 we place a register that is both set and used within I3. If more than one
1864 such register is detected, we fail.
1866 Return 1 if the combination is valid, zero otherwise. */
1869 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1870 int i1_not_in_src, rtx *pi3dest_killed)
1874 if (GET_CODE (x) == SET)
1877 rtx dest = SET_DEST (set);
1878 rtx src = SET_SRC (set);
1879 rtx inner_dest = dest;
1882 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1883 || GET_CODE (inner_dest) == SUBREG
1884 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1885 inner_dest = XEXP (inner_dest, 0);
1887 /* Check for the case where I3 modifies its output, as discussed
1888 above. We don't want to prevent pseudos from being combined
1889 into the address of a MEM, so only prevent the combination if
1890 i1 or i2 set the same MEM. */
1891 if ((inner_dest != dest &&
1892 (!MEM_P (inner_dest)
1893 || rtx_equal_p (i2dest, inner_dest)
1894 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1895 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1896 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1898 /* This is the same test done in can_combine_p except we can't test
1899 all_adjacent; we don't have to, since this instruction will stay
1900 in place, thus we are not considering increasing the lifetime of
1903 Also, if this insn sets a function argument, combining it with
1904 something that might need a spill could clobber a previous
1905 function argument; the all_adjacent test in can_combine_p also
1906 checks this; here, we do a more specific test for this case. */
1908 || (REG_P (inner_dest)
1909 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1910 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1911 GET_MODE (inner_dest))))
1912 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1915 /* If DEST is used in I3, it is being killed in this insn, so
1916 record that for later. We have to consider paradoxical
1917 subregs here, since they kill the whole register, but we
1918 ignore partial subregs, STRICT_LOW_PART, etc.
1919 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1920 STACK_POINTER_REGNUM, since these are always considered to be
1921 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1923 if (GET_CODE (subdest) == SUBREG
1924 && (GET_MODE_SIZE (GET_MODE (subdest))
1925 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1926 subdest = SUBREG_REG (subdest);
1929 && reg_referenced_p (subdest, PATTERN (i3))
1930 && REGNO (subdest) != FRAME_POINTER_REGNUM
1931 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1932 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1934 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1935 && (REGNO (subdest) != ARG_POINTER_REGNUM
1936 || ! fixed_regs [REGNO (subdest)])
1938 && REGNO (subdest) != STACK_POINTER_REGNUM)
1940 if (*pi3dest_killed)
1943 *pi3dest_killed = subdest;
1947 else if (GET_CODE (x) == PARALLEL)
1951 for (i = 0; i < XVECLEN (x, 0); i++)
1952 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1953 i1_not_in_src, pi3dest_killed))
1960 /* Return 1 if X is an arithmetic expression that contains a multiplication
1961 and division. We don't count multiplications by powers of two here. */
1964 contains_muldiv (rtx x)
1966 switch (GET_CODE (x))
1968 case MOD: case DIV: case UMOD: case UDIV:
1972 return ! (CONST_INT_P (XEXP (x, 1))
1973 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1976 return contains_muldiv (XEXP (x, 0))
1977 || contains_muldiv (XEXP (x, 1));
1980 return contains_muldiv (XEXP (x, 0));
1986 /* Determine whether INSN can be used in a combination. Return nonzero if
1987 not. This is used in try_combine to detect early some cases where we
1988 can't perform combinations. */
1991 cant_combine_insn_p (rtx insn)
1996 /* If this isn't really an insn, we can't do anything.
1997 This can occur when flow deletes an insn that it has merged into an
1998 auto-increment address. */
1999 if (! INSN_P (insn))
2002 /* Never combine loads and stores involving hard regs that are likely
2003 to be spilled. The register allocator can usually handle such
2004 reg-reg moves by tying. If we allow the combiner to make
2005 substitutions of likely-spilled regs, reload might die.
2006 As an exception, we allow combinations involving fixed regs; these are
2007 not available to the register allocator so there's no risk involved. */
2009 set = single_set (insn);
2012 src = SET_SRC (set);
2013 dest = SET_DEST (set);
2014 if (GET_CODE (src) == SUBREG)
2015 src = SUBREG_REG (src);
2016 if (GET_CODE (dest) == SUBREG)
2017 dest = SUBREG_REG (dest);
2018 if (REG_P (src) && REG_P (dest)
2019 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2020 && ! fixed_regs[REGNO (src)]
2021 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2022 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2023 && ! fixed_regs[REGNO (dest)]
2024 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2030 struct likely_spilled_retval_info
2032 unsigned regno, nregs;
2036 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2037 hard registers that are known to be written to / clobbered in full. */
2039 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2041 struct likely_spilled_retval_info *const info =
2042 (struct likely_spilled_retval_info *) data;
2043 unsigned regno, nregs;
2046 if (!REG_P (XEXP (set, 0)))
2049 if (regno >= info->regno + info->nregs)
2051 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2052 if (regno + nregs <= info->regno)
2054 new_mask = (2U << (nregs - 1)) - 1;
2055 if (regno < info->regno)
2056 new_mask >>= info->regno - regno;
2058 new_mask <<= regno - info->regno;
2059 info->mask &= ~new_mask;
2062 /* Return nonzero iff part of the return value is live during INSN, and
2063 it is likely spilled. This can happen when more than one insn is needed
2064 to copy the return value, e.g. when we consider to combine into the
2065 second copy insn for a complex value. */
2068 likely_spilled_retval_p (rtx insn)
2070 rtx use = BB_END (this_basic_block);
2072 unsigned regno, nregs;
2073 /* We assume here that no machine mode needs more than
2074 32 hard registers when the value overlaps with a register
2075 for which FUNCTION_VALUE_REGNO_P is true. */
2077 struct likely_spilled_retval_info info;
2079 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2081 reg = XEXP (PATTERN (use), 0);
2082 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2084 regno = REGNO (reg);
2085 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2088 mask = (2U << (nregs - 1)) - 1;
2090 /* Disregard parts of the return value that are set later. */
2094 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2096 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2099 /* Check if any of the (probably) live return value registers is
2104 if ((mask & 1 << nregs)
2105 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2111 /* Adjust INSN after we made a change to its destination.
2113 Changing the destination can invalidate notes that say something about
2114 the results of the insn and a LOG_LINK pointing to the insn. */
2117 adjust_for_new_dest (rtx insn)
2119 /* For notes, be conservative and simply remove them. */
2120 remove_reg_equal_equiv_notes (insn);
2122 /* The new insn will have a destination that was previously the destination
2123 of an insn just above it. Call distribute_links to make a LOG_LINK from
2124 the next use of that destination. */
2125 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2127 df_insn_rescan (insn);
2130 /* Return TRUE if combine can reuse reg X in mode MODE.
2131 ADDED_SETS is nonzero if the original set is still required. */
2133 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2141 /* Allow hard registers if the new mode is legal, and occupies no more
2142 registers than the old mode. */
2143 if (regno < FIRST_PSEUDO_REGISTER)
2144 return (HARD_REGNO_MODE_OK (regno, mode)
2145 && (hard_regno_nregs[regno][GET_MODE (x)]
2146 >= hard_regno_nregs[regno][mode]));
2148 /* Or a pseudo that is only used once. */
2149 return (REG_N_SETS (regno) == 1 && !added_sets
2150 && !REG_USERVAR_P (x));
2154 /* Check whether X, the destination of a set, refers to part of
2155 the register specified by REG. */
2158 reg_subword_p (rtx x, rtx reg)
2160 /* Check that reg is an integer mode register. */
2161 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2164 if (GET_CODE (x) == STRICT_LOW_PART
2165 || GET_CODE (x) == ZERO_EXTRACT)
2168 return GET_CODE (x) == SUBREG
2169 && SUBREG_REG (x) == reg
2170 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2174 /* Replace auto-increment addressing modes with explicit operations to
2175 access the same addresses without modifying the corresponding
2176 registers. If AFTER holds, SRC is meant to be reused after the
2177 side effect, otherwise it is to be reused before that. */
2180 cleanup_auto_inc_dec (rtx src, bool after, enum machine_mode mem_mode)
2183 const RTX_CODE code = GET_CODE (x);
2199 /* SCRATCH must be shared because they represent distinct values. */
2202 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2207 if (shared_const_p (x))
2212 mem_mode = GET_MODE (x);
2219 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2220 if (after == (code == PRE_INC || code == PRE_DEC))
2221 x = cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode);
2223 x = gen_rtx_PLUS (GET_MODE (x),
2224 cleanup_auto_inc_dec (XEXP (x, 0), after, mem_mode),
2225 GEN_INT ((code == PRE_INC || code == POST_INC)
2226 ? GET_MODE_SIZE (mem_mode)
2227 : -GET_MODE_SIZE (mem_mode)));
2232 if (after == (code == PRE_MODIFY))
2236 return cleanup_auto_inc_dec (x, after, mem_mode);
2242 /* Copy the various flags, fields, and other information. We assume
2243 that all fields need copying, and then clear the fields that should
2244 not be copied. That is the sensible default behavior, and forces
2245 us to explicitly document why we are *not* copying a flag. */
2246 x = shallow_copy_rtx (x);
2248 /* We do not copy the USED flag, which is used as a mark bit during
2249 walks over the RTL. */
2250 RTX_FLAG (x, used) = 0;
2252 /* We do not copy FRAME_RELATED for INSNs. */
2254 RTX_FLAG (x, frame_related) = 0;
2256 fmt = GET_RTX_FORMAT (code);
2257 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2259 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), after, mem_mode);
2260 else if (fmt[i] == 'E' || fmt[i] == 'V')
2263 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2264 for (j = 0; j < XVECLEN (x, i); j++)
2266 = cleanup_auto_inc_dec (XVECEXP (src, i, j), after, mem_mode);
2272 /* Auxiliary data structure for propagate_for_debug_stmt. */
2274 struct rtx_subst_pair
2281 /* DATA points to an rtx_subst_pair. Return the value that should be
2285 propagate_for_debug_subst (rtx from ATTRIBUTE_UNUSED, void *data)
2287 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2289 if (!pair->adjusted)
2291 pair->adjusted = true;
2292 pair->to = cleanup_auto_inc_dec (pair->to, pair->after, VOIDmode);
2295 return copy_rtx (pair->to);
2299 /* Replace occurrences of DEST with SRC in DEBUG_INSNs between INSN
2300 and LAST. If MOVE holds, debug insns must also be moved past
2304 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src, bool move)
2306 rtx next, move_pos = move ? last : NULL_RTX, loc;
2309 struct rtx_subst_pair p;
2315 next = NEXT_INSN (insn);
2316 while (next != last)
2319 next = NEXT_INSN (insn);
2320 if (DEBUG_INSN_P (insn))
2323 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2324 dest, propagate_for_debug_subst, &p);
2326 loc = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), dest, src);
2328 if (loc == INSN_VAR_LOCATION_LOC (insn))
2330 INSN_VAR_LOCATION_LOC (insn) = loc;
2334 PREV_INSN (insn) = NEXT_INSN (insn) = NULL_RTX;
2335 move_pos = emit_debug_insn_after (insn, move_pos);
2338 df_insn_rescan (insn);
2343 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2344 Note that the INSN should be deleted *after* removing dead edges, so
2345 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2346 but not for a (set (pc) (label_ref FOO)). */
2349 update_cfg_for_uncondjump (rtx insn)
2351 basic_block bb = BLOCK_FOR_INSN (insn);
2352 bool at_end = (BB_END (bb) == insn);
2355 purge_dead_edges (bb);
2358 if (at_end && EDGE_COUNT (bb->succs) == 1)
2359 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2363 /* Try to combine the insns I1 and I2 into I3.
2364 Here I1 and I2 appear earlier than I3.
2365 I1 can be zero; then we combine just I2 into I3.
2367 If we are combining three insns and the resulting insn is not recognized,
2368 try splitting it into two insns. If that happens, I2 and I3 are retained
2369 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2372 Return 0 if the combination does not work. Then nothing is changed.
2373 If we did the combination, return the insn at which combine should
2376 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2377 new direct jump instruction. */
2380 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2382 /* New patterns for I3 and I2, respectively. */
2383 rtx newpat, newi2pat = 0;
2384 rtvec newpat_vec_with_clobbers = 0;
2385 int substed_i2 = 0, substed_i1 = 0;
2386 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2387 int added_sets_1, added_sets_2;
2388 /* Total number of SETs to put into I3. */
2390 /* Nonzero if I2's body now appears in I3. */
2392 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2393 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2394 /* Contains I3 if the destination of I3 is used in its source, which means
2395 that the old life of I3 is being killed. If that usage is placed into
2396 I2 and not in I3, a REG_DEAD note must be made. */
2397 rtx i3dest_killed = 0;
2398 /* SET_DEST and SET_SRC of I2 and I1. */
2399 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0;
2400 /* Set if I2DEST was reused as a scratch register. */
2401 bool i2scratch = false;
2402 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2403 rtx i1pat = 0, i2pat = 0;
2404 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2405 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2406 int i2dest_killed = 0, i1dest_killed = 0;
2407 int i1_feeds_i3 = 0;
2408 /* Notes that must be added to REG_NOTES in I3 and I2. */
2409 rtx new_i3_notes, new_i2_notes;
2410 /* Notes that we substituted I3 into I2 instead of the normal case. */
2411 int i3_subst_into_i2 = 0;
2412 /* Notes that I1, I2 or I3 is a MULT operation. */
2415 int changed_i3_dest = 0;
2421 rtx new_other_notes;
2424 /* Exit early if one of the insns involved can't be used for
2426 if (cant_combine_insn_p (i3)
2427 || cant_combine_insn_p (i2)
2428 || (i1 && cant_combine_insn_p (i1))
2429 || likely_spilled_retval_p (i3))
2433 undobuf.other_insn = 0;
2435 /* Reset the hard register usage information. */
2436 CLEAR_HARD_REG_SET (newpat_used_regs);
2438 if (dump_file && (dump_flags & TDF_DETAILS))
2441 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2442 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2444 fprintf (dump_file, "\nTrying %d -> %d:\n",
2445 INSN_UID (i2), INSN_UID (i3));
2448 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2449 code below, set I1 to be the earlier of the two insns. */
2450 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2451 temp = i1, i1 = i2, i2 = temp;
2453 added_links_insn = 0;
2455 /* First check for one important special-case that the code below will
2456 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2457 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2458 we may be able to replace that destination with the destination of I3.
2459 This occurs in the common code where we compute both a quotient and
2460 remainder into a structure, in which case we want to do the computation
2461 directly into the structure to avoid register-register copies.
2463 Note that this case handles both multiple sets in I2 and also
2464 cases where I2 has a number of CLOBBER or PARALLELs.
2466 We make very conservative checks below and only try to handle the
2467 most common cases of this. For example, we only handle the case
2468 where I2 and I3 are adjacent to avoid making difficult register
2471 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2472 && REG_P (SET_SRC (PATTERN (i3)))
2473 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2474 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2475 && GET_CODE (PATTERN (i2)) == PARALLEL
2476 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2477 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2478 below would need to check what is inside (and reg_overlap_mentioned_p
2479 doesn't support those codes anyway). Don't allow those destinations;
2480 the resulting insn isn't likely to be recognized anyway. */
2481 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2482 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2483 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2484 SET_DEST (PATTERN (i3)))
2485 && next_active_insn (i2) == i3)
2487 rtx p2 = PATTERN (i2);
2489 /* Make sure that the destination of I3,
2490 which we are going to substitute into one output of I2,
2491 is not used within another output of I2. We must avoid making this:
2492 (parallel [(set (mem (reg 69)) ...)
2493 (set (reg 69) ...)])
2494 which is not well-defined as to order of actions.
2495 (Besides, reload can't handle output reloads for this.)
2497 The problem can also happen if the dest of I3 is a memory ref,
2498 if another dest in I2 is an indirect memory ref. */
2499 for (i = 0; i < XVECLEN (p2, 0); i++)
2500 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2501 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2502 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2503 SET_DEST (XVECEXP (p2, 0, i))))
2506 if (i == XVECLEN (p2, 0))
2507 for (i = 0; i < XVECLEN (p2, 0); i++)
2508 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2509 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2510 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2515 subst_low_luid = DF_INSN_LUID (i2);
2517 added_sets_2 = added_sets_1 = 0;
2518 i2src = SET_DEST (PATTERN (i3));
2519 i2dest = SET_SRC (PATTERN (i3));
2520 i2dest_killed = dead_or_set_p (i2, i2dest);
2522 /* Replace the dest in I2 with our dest and make the resulting
2523 insn the new pattern for I3. Then skip to where we
2524 validate the pattern. Everything was set up above. */
2525 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2526 SET_DEST (PATTERN (i3)));
2529 i3_subst_into_i2 = 1;
2530 goto validate_replacement;
2534 /* If I2 is setting a pseudo to a constant and I3 is setting some
2535 sub-part of it to another constant, merge them by making a new
2538 && (temp = single_set (i2)) != 0
2539 && (CONST_INT_P (SET_SRC (temp))
2540 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2541 && GET_CODE (PATTERN (i3)) == SET
2542 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2543 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2544 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2546 rtx dest = SET_DEST (PATTERN (i3));
2550 if (GET_CODE (dest) == ZERO_EXTRACT)
2552 if (CONST_INT_P (XEXP (dest, 1))
2553 && CONST_INT_P (XEXP (dest, 2)))
2555 width = INTVAL (XEXP (dest, 1));
2556 offset = INTVAL (XEXP (dest, 2));
2557 dest = XEXP (dest, 0);
2558 if (BITS_BIG_ENDIAN)
2559 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2564 if (GET_CODE (dest) == STRICT_LOW_PART)
2565 dest = XEXP (dest, 0);
2566 width = GET_MODE_BITSIZE (GET_MODE (dest));
2572 /* If this is the low part, we're done. */
2573 if (subreg_lowpart_p (dest))
2575 /* Handle the case where inner is twice the size of outer. */
2576 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2577 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2578 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2579 /* Otherwise give up for now. */
2585 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2586 <= HOST_BITS_PER_WIDE_INT * 2))
2588 HOST_WIDE_INT mhi, ohi, ihi;
2589 HOST_WIDE_INT mlo, olo, ilo;
2590 rtx inner = SET_SRC (PATTERN (i3));
2591 rtx outer = SET_SRC (temp);
2593 if (CONST_INT_P (outer))
2595 olo = INTVAL (outer);
2596 ohi = olo < 0 ? -1 : 0;
2600 olo = CONST_DOUBLE_LOW (outer);
2601 ohi = CONST_DOUBLE_HIGH (outer);
2604 if (CONST_INT_P (inner))
2606 ilo = INTVAL (inner);
2607 ihi = ilo < 0 ? -1 : 0;
2611 ilo = CONST_DOUBLE_LOW (inner);
2612 ihi = CONST_DOUBLE_HIGH (inner);
2615 if (width < HOST_BITS_PER_WIDE_INT)
2617 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2620 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2622 mhi = ((unsigned HOST_WIDE_INT) 1
2623 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2635 if (offset >= HOST_BITS_PER_WIDE_INT)
2637 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2639 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2642 else if (offset > 0)
2644 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2645 >> (HOST_BITS_PER_WIDE_INT - offset));
2646 mlo = mlo << offset;
2647 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2648 >> (HOST_BITS_PER_WIDE_INT - offset));
2649 ilo = ilo << offset;
2652 olo = (olo & ~mlo) | ilo;
2653 ohi = (ohi & ~mhi) | ihi;
2657 subst_low_luid = DF_INSN_LUID (i2);
2658 added_sets_2 = added_sets_1 = 0;
2659 i2dest = SET_DEST (temp);
2660 i2dest_killed = dead_or_set_p (i2, i2dest);
2662 SUBST (SET_SRC (temp),
2663 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2665 newpat = PATTERN (i2);
2666 goto validate_replacement;
2671 /* If we have no I1 and I2 looks like:
2672 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2674 make up a dummy I1 that is
2677 (set (reg:CC X) (compare:CC Y (const_int 0)))
2679 (We can ignore any trailing CLOBBERs.)
2681 This undoes a previous combination and allows us to match a branch-and-
2684 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2685 && XVECLEN (PATTERN (i2), 0) >= 2
2686 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2687 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2689 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2690 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2691 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2692 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2693 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2694 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2696 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2697 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2702 /* We make I1 with the same INSN_UID as I2. This gives it
2703 the same DF_INSN_LUID for value tracking. Our fake I1 will
2704 never appear in the insn stream so giving it the same INSN_UID
2705 as I2 will not cause a problem. */
2707 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2708 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2709 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2711 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2712 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2713 SET_DEST (PATTERN (i1)));
2718 /* Verify that I2 and I1 are valid for combining. */
2719 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2720 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2726 /* Record whether I2DEST is used in I2SRC and similarly for the other
2727 cases. Knowing this will help in register status updating below. */
2728 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2729 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2730 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2731 i2dest_killed = dead_or_set_p (i2, i2dest);
2732 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2734 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2736 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2738 /* Ensure that I3's pattern can be the destination of combines. */
2739 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2740 i1 && i2dest_in_i1src && i1_feeds_i3,
2747 /* See if any of the insns is a MULT operation. Unless one is, we will
2748 reject a combination that is, since it must be slower. Be conservative
2750 if (GET_CODE (i2src) == MULT
2751 || (i1 != 0 && GET_CODE (i1src) == MULT)
2752 || (GET_CODE (PATTERN (i3)) == SET
2753 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2756 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2757 We used to do this EXCEPT in one case: I3 has a post-inc in an
2758 output operand. However, that exception can give rise to insns like
2760 which is a famous insn on the PDP-11 where the value of r3 used as the
2761 source was model-dependent. Avoid this sort of thing. */
2764 if (!(GET_CODE (PATTERN (i3)) == SET
2765 && REG_P (SET_SRC (PATTERN (i3)))
2766 && MEM_P (SET_DEST (PATTERN (i3)))
2767 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2768 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2769 /* It's not the exception. */
2772 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2773 if (REG_NOTE_KIND (link) == REG_INC
2774 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2776 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2783 /* See if the SETs in I1 or I2 need to be kept around in the merged
2784 instruction: whenever the value set there is still needed past I3.
2785 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2787 For the SET in I1, we have two cases: If I1 and I2 independently
2788 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2789 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2790 in I1 needs to be kept around unless I1DEST dies or is set in either
2791 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2792 I1DEST. If so, we know I1 feeds into I2. */
2794 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2797 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2798 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2800 /* If the set in I2 needs to be kept around, we must make a copy of
2801 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2802 PATTERN (I2), we are only substituting for the original I1DEST, not into
2803 an already-substituted copy. This also prevents making self-referential
2804 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2809 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2810 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2812 i2pat = copy_rtx (PATTERN (i2));
2817 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2818 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2820 i1pat = copy_rtx (PATTERN (i1));
2825 /* Substitute in the latest insn for the regs set by the earlier ones. */
2827 maxreg = max_reg_num ();
2832 /* Many machines that don't use CC0 have insns that can both perform an
2833 arithmetic operation and set the condition code. These operations will
2834 be represented as a PARALLEL with the first element of the vector
2835 being a COMPARE of an arithmetic operation with the constant zero.
2836 The second element of the vector will set some pseudo to the result
2837 of the same arithmetic operation. If we simplify the COMPARE, we won't
2838 match such a pattern and so will generate an extra insn. Here we test
2839 for this case, where both the comparison and the operation result are
2840 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2841 I2SRC. Later we will make the PARALLEL that contains I2. */
2843 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2844 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2845 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2846 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2848 #ifdef SELECT_CC_MODE
2850 enum machine_mode compare_mode;
2853 newpat = PATTERN (i3);
2854 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2858 #ifdef SELECT_CC_MODE
2859 /* See if a COMPARE with the operand we substituted in should be done
2860 with the mode that is currently being used. If not, do the same
2861 processing we do in `subst' for a SET; namely, if the destination
2862 is used only once, try to replace it with a register of the proper
2863 mode and also replace the COMPARE. */
2864 if (undobuf.other_insn == 0
2865 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2866 &undobuf.other_insn))
2867 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2869 != GET_MODE (SET_DEST (newpat))))
2871 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2874 unsigned int regno = REGNO (SET_DEST (newpat));
2877 if (regno < FIRST_PSEUDO_REGISTER)
2878 new_dest = gen_rtx_REG (compare_mode, regno);
2881 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2882 new_dest = regno_reg_rtx[regno];
2885 SUBST (SET_DEST (newpat), new_dest);
2886 SUBST (XEXP (*cc_use, 0), new_dest);
2887 SUBST (SET_SRC (newpat),
2888 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2891 undobuf.other_insn = 0;
2898 /* It is possible that the source of I2 or I1 may be performing
2899 an unneeded operation, such as a ZERO_EXTEND of something
2900 that is known to have the high part zero. Handle that case
2901 by letting subst look at the innermost one of them.
2903 Another way to do this would be to have a function that tries
2904 to simplify a single insn instead of merging two or more
2905 insns. We don't do this because of the potential of infinite
2906 loops and because of the potential extra memory required.
2907 However, doing it the way we are is a bit of a kludge and
2908 doesn't catch all cases.
2910 But only do this if -fexpensive-optimizations since it slows
2911 things down and doesn't usually win.
2913 This is not done in the COMPARE case above because the
2914 unmodified I2PAT is used in the PARALLEL and so a pattern
2915 with a modified I2SRC would not match. */
2917 if (flag_expensive_optimizations)
2919 /* Pass pc_rtx so no substitutions are done, just
2923 subst_low_luid = DF_INSN_LUID (i1);
2924 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2928 subst_low_luid = DF_INSN_LUID (i2);
2929 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2933 n_occurrences = 0; /* `subst' counts here */
2935 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2936 need to make a unique copy of I2SRC each time we substitute it
2937 to avoid self-referential rtl. */
2939 subst_low_luid = DF_INSN_LUID (i2);
2940 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2941 ! i1_feeds_i3 && i1dest_in_i1src);
2944 /* Record whether i2's body now appears within i3's body. */
2945 i2_is_used = n_occurrences;
2948 /* If we already got a failure, don't try to do more. Otherwise,
2949 try to substitute in I1 if we have it. */
2951 if (i1 && GET_CODE (newpat) != CLOBBER)
2953 /* Check that an autoincrement side-effect on I1 has not been lost.
2954 This happens if I1DEST is mentioned in I2 and dies there, and
2955 has disappeared from the new pattern. */
2956 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2958 && dead_or_set_p (i2, i1dest)
2959 && !reg_overlap_mentioned_p (i1dest, newpat))
2960 /* Before we can do this substitution, we must redo the test done
2961 above (see detailed comments there) that ensures that I1DEST
2962 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2963 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2970 subst_low_luid = DF_INSN_LUID (i1);
2971 newpat = subst (newpat, i1dest, i1src, 0, 0);
2975 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2976 to count all the ways that I2SRC and I1SRC can be used. */
2977 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2978 && i2_is_used + added_sets_2 > 1)
2979 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2980 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2982 /* Fail if we tried to make a new register. */
2983 || max_reg_num () != maxreg
2984 /* Fail if we couldn't do something and have a CLOBBER. */
2985 || GET_CODE (newpat) == CLOBBER
2986 /* Fail if this new pattern is a MULT and we didn't have one before
2987 at the outer level. */
2988 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2995 /* If the actions of the earlier insns must be kept
2996 in addition to substituting them into the latest one,
2997 we must make a new PARALLEL for the latest insn
2998 to hold additional the SETs. */
3000 if (added_sets_1 || added_sets_2)
3004 if (GET_CODE (newpat) == PARALLEL)
3006 rtvec old = XVEC (newpat, 0);
3007 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
3008 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3009 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3010 sizeof (old->elem[0]) * old->num_elem);
3015 total_sets = 1 + added_sets_1 + added_sets_2;
3016 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3017 XVECEXP (newpat, 0, 0) = old;
3021 XVECEXP (newpat, 0, --total_sets) = i1pat;
3025 /* If there is no I1, use I2's body as is. We used to also not do
3026 the subst call below if I2 was substituted into I3,
3027 but that could lose a simplification. */
3029 XVECEXP (newpat, 0, --total_sets) = i2pat;
3031 /* See comment where i2pat is assigned. */
3032 XVECEXP (newpat, 0, --total_sets)
3033 = subst (i2pat, i1dest, i1src, 0, 0);
3037 /* We come here when we are replacing a destination in I2 with the
3038 destination of I3. */
3039 validate_replacement:
3041 /* Note which hard regs this insn has as inputs. */
3042 mark_used_regs_combine (newpat);
3044 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3045 consider splitting this pattern, we might need these clobbers. */
3046 if (i1 && GET_CODE (newpat) == PARALLEL
3047 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3049 int len = XVECLEN (newpat, 0);
3051 newpat_vec_with_clobbers = rtvec_alloc (len);
3052 for (i = 0; i < len; i++)
3053 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3056 /* Is the result of combination a valid instruction? */
3057 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3059 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3060 the second SET's destination is a register that is unused and isn't
3061 marked as an instruction that might trap in an EH region. In that case,
3062 we just need the first SET. This can occur when simplifying a divmod
3063 insn. We *must* test for this case here because the code below that
3064 splits two independent SETs doesn't handle this case correctly when it
3065 updates the register status.
3067 It's pointless doing this if we originally had two sets, one from
3068 i3, and one from i2. Combining then splitting the parallel results
3069 in the original i2 again plus an invalid insn (which we delete).
3070 The net effect is only to move instructions around, which makes
3071 debug info less accurate.
3073 Also check the case where the first SET's destination is unused.
3074 That would not cause incorrect code, but does cause an unneeded
3077 if (insn_code_number < 0
3078 && !(added_sets_2 && i1 == 0)
3079 && GET_CODE (newpat) == PARALLEL
3080 && XVECLEN (newpat, 0) == 2
3081 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3082 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3083 && asm_noperands (newpat) < 0)
3085 rtx set0 = XVECEXP (newpat, 0, 0);
3086 rtx set1 = XVECEXP (newpat, 0, 1);
3088 if (((REG_P (SET_DEST (set1))
3089 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3090 || (GET_CODE (SET_DEST (set1)) == SUBREG
3091 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3092 && insn_nothrow_p (i3)
3093 && !side_effects_p (SET_SRC (set1)))
3096 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3099 else if (((REG_P (SET_DEST (set0))
3100 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3101 || (GET_CODE (SET_DEST (set0)) == SUBREG
3102 && find_reg_note (i3, REG_UNUSED,
3103 SUBREG_REG (SET_DEST (set0)))))
3104 && insn_nothrow_p (i3)
3105 && !side_effects_p (SET_SRC (set0)))
3108 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3110 if (insn_code_number >= 0)
3111 changed_i3_dest = 1;
3115 /* If we were combining three insns and the result is a simple SET
3116 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3117 insns. There are two ways to do this. It can be split using a
3118 machine-specific method (like when you have an addition of a large
3119 constant) or by combine in the function find_split_point. */
3121 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3122 && asm_noperands (newpat) < 0)
3124 rtx parallel, m_split, *split;
3126 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3127 use I2DEST as a scratch register will help. In the latter case,
3128 convert I2DEST to the mode of the source of NEWPAT if we can. */
3130 m_split = combine_split_insns (newpat, i3);
3132 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3133 inputs of NEWPAT. */
3135 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3136 possible to try that as a scratch reg. This would require adding
3137 more code to make it work though. */
3139 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3141 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3143 /* First try to split using the original register as a
3144 scratch register. */
3145 parallel = gen_rtx_PARALLEL (VOIDmode,
3146 gen_rtvec (2, newpat,
3147 gen_rtx_CLOBBER (VOIDmode,
3149 m_split = combine_split_insns (parallel, i3);
3151 /* If that didn't work, try changing the mode of I2DEST if
3154 && new_mode != GET_MODE (i2dest)
3155 && new_mode != VOIDmode
3156 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3158 enum machine_mode old_mode = GET_MODE (i2dest);
3161 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3162 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3165 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3166 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3169 parallel = (gen_rtx_PARALLEL
3171 gen_rtvec (2, newpat,
3172 gen_rtx_CLOBBER (VOIDmode,
3174 m_split = combine_split_insns (parallel, i3);
3177 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3181 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3182 buf = undobuf.undos;
3183 undobuf.undos = buf->next;
3184 buf->next = undobuf.frees;
3185 undobuf.frees = buf;
3189 i2scratch = m_split != 0;
3192 /* If recog_for_combine has discarded clobbers, try to use them
3193 again for the split. */
3194 if (m_split == 0 && newpat_vec_with_clobbers)
3196 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3197 m_split = combine_split_insns (parallel, i3);
3200 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3202 m_split = PATTERN (m_split);
3203 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3204 if (insn_code_number >= 0)
3207 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3208 && (next_real_insn (i2) == i3
3209 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3212 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3213 newi2pat = PATTERN (m_split);
3215 i3set = single_set (NEXT_INSN (m_split));
3216 i2set = single_set (m_split);
3218 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3220 /* If I2 or I3 has multiple SETs, we won't know how to track
3221 register status, so don't use these insns. If I2's destination
3222 is used between I2 and I3, we also can't use these insns. */
3224 if (i2_code_number >= 0 && i2set && i3set
3225 && (next_real_insn (i2) == i3
3226 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3227 insn_code_number = recog_for_combine (&newi3pat, i3,
3229 if (insn_code_number >= 0)
3232 /* It is possible that both insns now set the destination of I3.
3233 If so, we must show an extra use of it. */
3235 if (insn_code_number >= 0)
3237 rtx new_i3_dest = SET_DEST (i3set);
3238 rtx new_i2_dest = SET_DEST (i2set);
3240 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3241 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3242 || GET_CODE (new_i3_dest) == SUBREG)
3243 new_i3_dest = XEXP (new_i3_dest, 0);
3245 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3246 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3247 || GET_CODE (new_i2_dest) == SUBREG)
3248 new_i2_dest = XEXP (new_i2_dest, 0);
3250 if (REG_P (new_i3_dest)
3251 && REG_P (new_i2_dest)
3252 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3253 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3257 /* If we can split it and use I2DEST, go ahead and see if that
3258 helps things be recognized. Verify that none of the registers
3259 are set between I2 and I3. */
3260 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3264 /* We need I2DEST in the proper mode. If it is a hard register
3265 or the only use of a pseudo, we can change its mode.
3266 Make sure we don't change a hard register to have a mode that
3267 isn't valid for it, or change the number of registers. */
3268 && (GET_MODE (*split) == GET_MODE (i2dest)
3269 || GET_MODE (*split) == VOIDmode
3270 || can_change_dest_mode (i2dest, added_sets_2,
3272 && (next_real_insn (i2) == i3
3273 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3274 /* We can't overwrite I2DEST if its value is still used by
3276 && ! reg_referenced_p (i2dest, newpat))
3278 rtx newdest = i2dest;
3279 enum rtx_code split_code = GET_CODE (*split);
3280 enum machine_mode split_mode = GET_MODE (*split);
3281 bool subst_done = false;
3282 newi2pat = NULL_RTX;
3286 /* Get NEWDEST as a register in the proper mode. We have already
3287 validated that we can do this. */
3288 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3290 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3291 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3294 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3295 newdest = regno_reg_rtx[REGNO (i2dest)];
3299 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3300 an ASHIFT. This can occur if it was inside a PLUS and hence
3301 appeared to be a memory address. This is a kludge. */
3302 if (split_code == MULT
3303 && CONST_INT_P (XEXP (*split, 1))
3304 && INTVAL (XEXP (*split, 1)) > 0
3305 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3307 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3308 XEXP (*split, 0), GEN_INT (i)));
3309 /* Update split_code because we may not have a multiply
3311 split_code = GET_CODE (*split);
3314 #ifdef INSN_SCHEDULING
3315 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3316 be written as a ZERO_EXTEND. */
3317 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3319 #ifdef LOAD_EXTEND_OP
3320 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3321 what it really is. */
3322 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3324 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3325 SUBREG_REG (*split)));
3328 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3329 SUBREG_REG (*split)));
3333 /* Attempt to split binary operators using arithmetic identities. */
3334 if (BINARY_P (SET_SRC (newpat))
3335 && split_mode == GET_MODE (SET_SRC (newpat))
3336 && ! side_effects_p (SET_SRC (newpat)))
3338 rtx setsrc = SET_SRC (newpat);
3339 enum machine_mode mode = GET_MODE (setsrc);
3340 enum rtx_code code = GET_CODE (setsrc);
3341 rtx src_op0 = XEXP (setsrc, 0);
3342 rtx src_op1 = XEXP (setsrc, 1);
3344 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3345 if (rtx_equal_p (src_op0, src_op1))
3347 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3348 SUBST (XEXP (setsrc, 0), newdest);
3349 SUBST (XEXP (setsrc, 1), newdest);
3352 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3353 else if ((code == PLUS || code == MULT)
3354 && GET_CODE (src_op0) == code
3355 && GET_CODE (XEXP (src_op0, 0)) == code
3356 && (INTEGRAL_MODE_P (mode)
3357 || (FLOAT_MODE_P (mode)
3358 && flag_unsafe_math_optimizations)))
3360 rtx p = XEXP (XEXP (src_op0, 0), 0);
3361 rtx q = XEXP (XEXP (src_op0, 0), 1);
3362 rtx r = XEXP (src_op0, 1);
3365 /* Split both "((X op Y) op X) op Y" and
3366 "((X op Y) op Y) op X" as "T op T" where T is
3368 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3369 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3371 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3373 SUBST (XEXP (setsrc, 0), newdest);
3374 SUBST (XEXP (setsrc, 1), newdest);
3377 /* Split "((X op X) op Y) op Y)" as "T op T" where
3379 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3381 rtx tmp = simplify_gen_binary (code, mode, p, r);
3382 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3383 SUBST (XEXP (setsrc, 0), newdest);
3384 SUBST (XEXP (setsrc, 1), newdest);
3392 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3393 SUBST (*split, newdest);
3396 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3398 /* recog_for_combine might have added CLOBBERs to newi2pat.
3399 Make sure NEWPAT does not depend on the clobbered regs. */
3400 if (GET_CODE (newi2pat) == PARALLEL)
3401 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3402 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3404 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3405 if (reg_overlap_mentioned_p (reg, newpat))
3412 /* If the split point was a MULT and we didn't have one before,
3413 don't use one now. */
3414 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3415 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3419 /* Check for a case where we loaded from memory in a narrow mode and
3420 then sign extended it, but we need both registers. In that case,
3421 we have a PARALLEL with both loads from the same memory location.
3422 We can split this into a load from memory followed by a register-register
3423 copy. This saves at least one insn, more if register allocation can
3426 We cannot do this if the destination of the first assignment is a
3427 condition code register or cc0. We eliminate this case by making sure
3428 the SET_DEST and SET_SRC have the same mode.
3430 We cannot do this if the destination of the second assignment is
3431 a register that we have already assumed is zero-extended. Similarly
3432 for a SUBREG of such a register. */
3434 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3435 && GET_CODE (newpat) == PARALLEL
3436 && XVECLEN (newpat, 0) == 2
3437 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3438 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3439 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3440 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3441 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3442 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3443 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3444 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3446 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3447 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3448 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3450 && VEC_index (reg_stat_type, reg_stat,
3451 REGNO (temp))->nonzero_bits != 0
3452 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3453 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3454 && (VEC_index (reg_stat_type, reg_stat,
3455 REGNO (temp))->nonzero_bits
3456 != GET_MODE_MASK (word_mode))))
3457 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3458 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3460 && VEC_index (reg_stat_type, reg_stat,
3461 REGNO (temp))->nonzero_bits != 0
3462 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3463 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3464 && (VEC_index (reg_stat_type, reg_stat,
3465 REGNO (temp))->nonzero_bits
3466 != GET_MODE_MASK (word_mode)))))
3467 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3468 SET_SRC (XVECEXP (newpat, 0, 1)))
3469 && ! find_reg_note (i3, REG_UNUSED,
3470 SET_DEST (XVECEXP (newpat, 0, 0))))
3474 newi2pat = XVECEXP (newpat, 0, 0);
3475 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3476 newpat = XVECEXP (newpat, 0, 1);
3477 SUBST (SET_SRC (newpat),
3478 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3479 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3481 if (i2_code_number >= 0)
3482 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3484 if (insn_code_number >= 0)
3488 /* Similarly, check for a case where we have a PARALLEL of two independent
3489 SETs but we started with three insns. In this case, we can do the sets
3490 as two separate insns. This case occurs when some SET allows two
3491 other insns to combine, but the destination of that SET is still live. */
3493 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3494 && GET_CODE (newpat) == PARALLEL
3495 && XVECLEN (newpat, 0) == 2
3496 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3497 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3498 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3499 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3500 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3501 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3502 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3504 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3505 XVECEXP (newpat, 0, 0))
3506 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3507 XVECEXP (newpat, 0, 1))
3508 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3509 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3511 /* We cannot split the parallel into two sets if both sets
3513 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3514 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3518 /* Normally, it doesn't matter which of the two is done first,
3519 but it does if one references cc0. In that case, it has to
3522 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3524 newi2pat = XVECEXP (newpat, 0, 0);
3525 newpat = XVECEXP (newpat, 0, 1);
3530 newi2pat = XVECEXP (newpat, 0, 1);
3531 newpat = XVECEXP (newpat, 0, 0);
3534 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3536 if (i2_code_number >= 0)
3537 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3540 /* If it still isn't recognized, fail and change things back the way they
3542 if ((insn_code_number < 0
3543 /* Is the result a reasonable ASM_OPERANDS? */
3544 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3550 /* If we had to change another insn, make sure it is valid also. */
3551 if (undobuf.other_insn)
3553 CLEAR_HARD_REG_SET (newpat_used_regs);
3555 other_pat = PATTERN (undobuf.other_insn);
3556 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3559 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3567 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3568 they are adjacent to each other or not. */
3570 rtx p = prev_nonnote_insn (i3);
3571 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3572 && sets_cc0_p (newi2pat))
3580 /* Only allow this combination if insn_rtx_costs reports that the
3581 replacement instructions are cheaper than the originals. */
3582 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3588 if (MAY_HAVE_DEBUG_INSNS)
3592 for (undo = undobuf.undos; undo; undo = undo->next)
3593 if (undo->kind == UNDO_MODE)
3595 rtx reg = *undo->where.r;
3596 enum machine_mode new_mode = GET_MODE (reg);
3597 enum machine_mode old_mode = undo->old_contents.m;
3599 /* Temporarily revert mode back. */
3600 adjust_reg_mode (reg, old_mode);
3602 if (reg == i2dest && i2scratch)
3604 /* If we used i2dest as a scratch register with a
3605 different mode, substitute it for the original
3606 i2src while its original mode is temporarily
3607 restored, and then clear i2scratch so that we don't
3608 do it again later. */
3609 propagate_for_debug (i2, i3, reg, i2src, false);
3611 /* Put back the new mode. */
3612 adjust_reg_mode (reg, new_mode);
3616 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3627 last = undobuf.other_insn;
3631 /* We're dealing with a reg that changed mode but not
3632 meaning, so we want to turn it into a subreg for
3633 the new mode. However, because of REG sharing and
3634 because its mode had already changed, we have to do
3635 it in two steps. First, replace any debug uses of
3636 reg, with its original mode temporarily restored,
3637 with this copy we have created; then, replace the
3638 copy with the SUBREG of the original shared reg,
3639 once again changed to the new mode. */
3640 propagate_for_debug (first, last, reg, tempreg, false);
3641 adjust_reg_mode (reg, new_mode);
3642 propagate_for_debug (first, last, tempreg,
3643 lowpart_subreg (old_mode, reg, new_mode),
3649 /* If we will be able to accept this, we have made a
3650 change to the destination of I3. This requires us to
3651 do a few adjustments. */
3653 if (changed_i3_dest)
3655 PATTERN (i3) = newpat;
3656 adjust_for_new_dest (i3);
3659 /* We now know that we can do this combination. Merge the insns and
3660 update the status of registers and LOG_LINKS. */
3662 if (undobuf.other_insn)
3666 PATTERN (undobuf.other_insn) = other_pat;
3668 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3669 are still valid. Then add any non-duplicate notes added by
3670 recog_for_combine. */
3671 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3673 next = XEXP (note, 1);
3675 if (REG_NOTE_KIND (note) == REG_UNUSED
3676 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3677 remove_note (undobuf.other_insn, note);
3680 distribute_notes (new_other_notes, undobuf.other_insn,
3681 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3690 /* I3 now uses what used to be its destination and which is now
3691 I2's destination. This requires us to do a few adjustments. */
3692 PATTERN (i3) = newpat;
3693 adjust_for_new_dest (i3);
3695 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3698 However, some later insn might be using I2's dest and have
3699 a LOG_LINK pointing at I3. We must remove this link.
3700 The simplest way to remove the link is to point it at I1,
3701 which we know will be a NOTE. */
3703 /* newi2pat is usually a SET here; however, recog_for_combine might
3704 have added some clobbers. */
3705 if (GET_CODE (newi2pat) == PARALLEL)
3706 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3708 ni2dest = SET_DEST (newi2pat);
3710 for (insn = NEXT_INSN (i3);
3711 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3712 || insn != BB_HEAD (this_basic_block->next_bb));
3713 insn = NEXT_INSN (insn))
3715 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3717 for (link = LOG_LINKS (insn); link;
3718 link = XEXP (link, 1))
3719 if (XEXP (link, 0) == i3)
3720 XEXP (link, 0) = i1;
3728 rtx i3notes, i2notes, i1notes = 0;
3729 rtx i3links, i2links, i1links = 0;
3732 /* Compute which registers we expect to eliminate. newi2pat may be setting
3733 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3734 same as i3dest, in which case newi2pat may be setting i1dest. */
3735 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3736 || i2dest_in_i2src || i2dest_in_i1src
3739 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3740 || (newi2pat && reg_set_p (i1dest, newi2pat))
3744 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3746 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3747 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3749 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3751 /* Ensure that we do not have something that should not be shared but
3752 occurs multiple times in the new insns. Check this by first
3753 resetting all the `used' flags and then copying anything is shared. */
3755 reset_used_flags (i3notes);
3756 reset_used_flags (i2notes);
3757 reset_used_flags (i1notes);
3758 reset_used_flags (newpat);
3759 reset_used_flags (newi2pat);
3760 if (undobuf.other_insn)
3761 reset_used_flags (PATTERN (undobuf.other_insn));
3763 i3notes = copy_rtx_if_shared (i3notes);
3764 i2notes = copy_rtx_if_shared (i2notes);
3765 i1notes = copy_rtx_if_shared (i1notes);
3766 newpat = copy_rtx_if_shared (newpat);
3767 newi2pat = copy_rtx_if_shared (newi2pat);
3768 if (undobuf.other_insn)
3769 reset_used_flags (PATTERN (undobuf.other_insn));
3771 INSN_CODE (i3) = insn_code_number;
3772 PATTERN (i3) = newpat;
3774 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3776 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3778 reset_used_flags (call_usage);
3779 call_usage = copy_rtx (call_usage);
3782 replace_rtx (call_usage, i2dest, i2src);
3785 replace_rtx (call_usage, i1dest, i1src);
3787 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3790 if (undobuf.other_insn)
3791 INSN_CODE (undobuf.other_insn) = other_code_number;
3793 /* We had one special case above where I2 had more than one set and
3794 we replaced a destination of one of those sets with the destination
3795 of I3. In that case, we have to update LOG_LINKS of insns later
3796 in this basic block. Note that this (expensive) case is rare.
3798 Also, in this case, we must pretend that all REG_NOTEs for I2
3799 actually came from I3, so that REG_UNUSED notes from I2 will be
3800 properly handled. */
3802 if (i3_subst_into_i2)
3804 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3805 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3806 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3807 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3808 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3809 && ! find_reg_note (i2, REG_UNUSED,
3810 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3811 for (temp = NEXT_INSN (i2);
3812 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3813 || BB_HEAD (this_basic_block) != temp);
3814 temp = NEXT_INSN (temp))
3815 if (temp != i3 && INSN_P (temp))
3816 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3817 if (XEXP (link, 0) == i2)
3818 XEXP (link, 0) = i3;
3823 while (XEXP (link, 1))
3824 link = XEXP (link, 1);
3825 XEXP (link, 1) = i2notes;
3839 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
3840 propagate_for_debug (i2, i3, i2dest, i2src, false);
3841 INSN_CODE (i2) = i2_code_number;
3842 PATTERN (i2) = newi2pat;
3846 if (MAY_HAVE_DEBUG_INSNS && i2src)
3847 propagate_for_debug (i2, i3, i2dest, i2src, i3_subst_into_i2);
3848 SET_INSN_DELETED (i2);
3855 if (MAY_HAVE_DEBUG_INSNS)
3856 propagate_for_debug (i1, i3, i1dest, i1src, false);
3857 SET_INSN_DELETED (i1);
3860 /* Get death notes for everything that is now used in either I3 or
3861 I2 and used to die in a previous insn. If we built two new
3862 patterns, move from I1 to I2 then I2 to I3 so that we get the
3863 proper movement on registers that I2 modifies. */
3867 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3868 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3871 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3874 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3876 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3879 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3882 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3885 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3888 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3889 know these are REG_UNUSED and want them to go to the desired insn,
3890 so we always pass it as i3. */
3892 if (newi2pat && new_i2_notes)
3893 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3896 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3898 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3899 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3900 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3901 in that case, it might delete I2. Similarly for I2 and I1.
3902 Show an additional death due to the REG_DEAD note we make here. If
3903 we discard it in distribute_notes, we will decrement it again. */
3907 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3908 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3910 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3912 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3914 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3918 if (i2dest_in_i2src)
3920 if (newi2pat && reg_set_p (i2dest, newi2pat))
3921 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3922 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3924 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3925 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3926 NULL_RTX, NULL_RTX);
3929 if (i1dest_in_i1src)
3931 if (newi2pat && reg_set_p (i1dest, newi2pat))
3932 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3933 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3935 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3936 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3937 NULL_RTX, NULL_RTX);
3940 distribute_links (i3links);
3941 distribute_links (i2links);
3942 distribute_links (i1links);
3947 rtx i2_insn = 0, i2_val = 0, set;
3949 /* The insn that used to set this register doesn't exist, and
3950 this life of the register may not exist either. See if one of
3951 I3's links points to an insn that sets I2DEST. If it does,
3952 that is now the last known value for I2DEST. If we don't update
3953 this and I2 set the register to a value that depended on its old
3954 contents, we will get confused. If this insn is used, thing
3955 will be set correctly in combine_instructions. */
3957 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3958 if ((set = single_set (XEXP (link, 0))) != 0
3959 && rtx_equal_p (i2dest, SET_DEST (set)))
3960 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3962 record_value_for_reg (i2dest, i2_insn, i2_val);
3964 /* If the reg formerly set in I2 died only once and that was in I3,
3965 zero its use count so it won't make `reload' do any work. */
3967 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3968 && ! i2dest_in_i2src)
3970 regno = REGNO (i2dest);
3971 INC_REG_N_SETS (regno, -1);
3975 if (i1 && REG_P (i1dest))
3978 rtx i1_insn = 0, i1_val = 0, set;
3980 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3981 if ((set = single_set (XEXP (link, 0))) != 0
3982 && rtx_equal_p (i1dest, SET_DEST (set)))
3983 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3985 record_value_for_reg (i1dest, i1_insn, i1_val);
3987 regno = REGNO (i1dest);
3988 if (! added_sets_1 && ! i1dest_in_i1src)
3989 INC_REG_N_SETS (regno, -1);
3992 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3993 been made to this insn. The order of
3994 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3995 can affect nonzero_bits of newpat */
3997 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3998 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4001 if (undobuf.other_insn != NULL_RTX)
4005 fprintf (dump_file, "modifying other_insn ");
4006 dump_insn_slim (dump_file, undobuf.other_insn);
4008 df_insn_rescan (undobuf.other_insn);
4011 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4015 fprintf (dump_file, "modifying insn i1 ");
4016 dump_insn_slim (dump_file, i1);
4018 df_insn_rescan (i1);
4021 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4025 fprintf (dump_file, "modifying insn i2 ");
4026 dump_insn_slim (dump_file, i2);
4028 df_insn_rescan (i2);
4031 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4035 fprintf (dump_file, "modifying insn i3 ");
4036 dump_insn_slim (dump_file, i3);
4038 df_insn_rescan (i3);
4041 /* Set new_direct_jump_p if a new return or simple jump instruction
4042 has been created. Adjust the CFG accordingly. */
4044 if (returnjump_p (i3) || any_uncondjump_p (i3))
4046 *new_direct_jump_p = 1;
4047 mark_jump_label (PATTERN (i3), i3, 0);
4048 update_cfg_for_uncondjump (i3);
4051 if (undobuf.other_insn != NULL_RTX
4052 && (returnjump_p (undobuf.other_insn)
4053 || any_uncondjump_p (undobuf.other_insn)))
4055 *new_direct_jump_p = 1;
4056 update_cfg_for_uncondjump (undobuf.other_insn);
4059 /* A noop might also need cleaning up of CFG, if it comes from the
4060 simplification of a jump. */
4061 if (GET_CODE (newpat) == SET
4062 && SET_SRC (newpat) == pc_rtx
4063 && SET_DEST (newpat) == pc_rtx)
4065 *new_direct_jump_p = 1;
4066 update_cfg_for_uncondjump (i3);
4069 combine_successes++;
4072 if (added_links_insn
4073 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4074 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4075 return added_links_insn;
4077 return newi2pat ? i2 : i3;
4080 /* Undo all the modifications recorded in undobuf. */
4085 struct undo *undo, *next;
4087 for (undo = undobuf.undos; undo; undo = next)
4093 *undo->where.r = undo->old_contents.r;
4096 *undo->where.i = undo->old_contents.i;
4099 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4105 undo->next = undobuf.frees;
4106 undobuf.frees = undo;
4112 /* We've committed to accepting the changes we made. Move all
4113 of the undos to the free list. */
4118 struct undo *undo, *next;
4120 for (undo = undobuf.undos; undo; undo = next)
4123 undo->next = undobuf.frees;
4124 undobuf.frees = undo;
4129 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4130 where we have an arithmetic expression and return that point. LOC will
4133 try_combine will call this function to see if an insn can be split into
4137 find_split_point (rtx *loc, rtx insn)
4140 enum rtx_code code = GET_CODE (x);
4142 unsigned HOST_WIDE_INT len = 0;
4143 HOST_WIDE_INT pos = 0;
4145 rtx inner = NULL_RTX;
4147 /* First special-case some codes. */
4151 #ifdef INSN_SCHEDULING
4152 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4154 if (MEM_P (SUBREG_REG (x)))
4157 return find_split_point (&SUBREG_REG (x), insn);
4161 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4162 using LO_SUM and HIGH. */
4163 if (GET_CODE (XEXP (x, 0)) == CONST
4164 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4166 enum machine_mode address_mode
4167 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4170 gen_rtx_LO_SUM (address_mode,
4171 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4173 return &XEXP (XEXP (x, 0), 0);
4177 /* If we have a PLUS whose second operand is a constant and the
4178 address is not valid, perhaps will can split it up using
4179 the machine-specific way to split large constants. We use
4180 the first pseudo-reg (one of the virtual regs) as a placeholder;
4181 it will not remain in the result. */
4182 if (GET_CODE (XEXP (x, 0)) == PLUS
4183 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4184 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4185 MEM_ADDR_SPACE (x)))
4187 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4188 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4192 /* This should have produced two insns, each of which sets our
4193 placeholder. If the source of the second is a valid address,
4194 we can make put both sources together and make a split point
4198 && NEXT_INSN (seq) != NULL_RTX
4199 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4200 && NONJUMP_INSN_P (seq)
4201 && GET_CODE (PATTERN (seq)) == SET
4202 && SET_DEST (PATTERN (seq)) == reg
4203 && ! reg_mentioned_p (reg,
4204 SET_SRC (PATTERN (seq)))
4205 && NONJUMP_INSN_P (NEXT_INSN (seq))
4206 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4207 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4208 && memory_address_addr_space_p
4209 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4210 MEM_ADDR_SPACE (x)))
4212 rtx src1 = SET_SRC (PATTERN (seq));
4213 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4215 /* Replace the placeholder in SRC2 with SRC1. If we can
4216 find where in SRC2 it was placed, that can become our
4217 split point and we can replace this address with SRC2.
4218 Just try two obvious places. */
4220 src2 = replace_rtx (src2, reg, src1);
4222 if (XEXP (src2, 0) == src1)
4223 split = &XEXP (src2, 0);
4224 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4225 && XEXP (XEXP (src2, 0), 0) == src1)
4226 split = &XEXP (XEXP (src2, 0), 0);
4230 SUBST (XEXP (x, 0), src2);
4235 /* If that didn't work, perhaps the first operand is complex and
4236 needs to be computed separately, so make a split point there.
4237 This will occur on machines that just support REG + CONST
4238 and have a constant moved through some previous computation. */
4240 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4241 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4242 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4243 return &XEXP (XEXP (x, 0), 0);
4246 /* If we have a PLUS whose first operand is complex, try computing it
4247 separately by making a split there. */
4248 if (GET_CODE (XEXP (x, 0)) == PLUS
4249 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4251 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4252 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4253 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4254 return &XEXP (XEXP (x, 0), 0);
4259 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4260 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4261 we need to put the operand into a register. So split at that
4264 if (SET_DEST (x) == cc0_rtx
4265 && GET_CODE (SET_SRC (x)) != COMPARE
4266 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4267 && !OBJECT_P (SET_SRC (x))
4268 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4269 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4270 return &SET_SRC (x);
4273 /* See if we can split SET_SRC as it stands. */
4274 split = find_split_point (&SET_SRC (x), insn);
4275 if (split && split != &SET_SRC (x))
4278 /* See if we can split SET_DEST as it stands. */
4279 split = find_split_point (&SET_DEST (x), insn);
4280 if (split && split != &SET_DEST (x))
4283 /* See if this is a bitfield assignment with everything constant. If
4284 so, this is an IOR of an AND, so split it into that. */
4285 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4286 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4287 <= HOST_BITS_PER_WIDE_INT)
4288 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4289 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4290 && CONST_INT_P (SET_SRC (x))
4291 && ((INTVAL (XEXP (SET_DEST (x), 1))
4292 + INTVAL (XEXP (SET_DEST (x), 2)))
4293 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4294 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4296 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4297 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4298 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4299 rtx dest = XEXP (SET_DEST (x), 0);
4300 enum machine_mode mode = GET_MODE (dest);
4301 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4304 if (BITS_BIG_ENDIAN)
4305 pos = GET_MODE_BITSIZE (mode) - len - pos;
4307 or_mask = gen_int_mode (src << pos, mode);
4310 simplify_gen_binary (IOR, mode, dest, or_mask));
4313 rtx negmask = gen_int_mode (~(mask << pos), mode);
4315 simplify_gen_binary (IOR, mode,
4316 simplify_gen_binary (AND, mode,
4321 SUBST (SET_DEST (x), dest);
4323 split = find_split_point (&SET_SRC (x), insn);
4324 if (split && split != &SET_SRC (x))
4328 /* Otherwise, see if this is an operation that we can split into two.
4329 If so, try to split that. */
4330 code = GET_CODE (SET_SRC (x));
4335 /* If we are AND'ing with a large constant that is only a single
4336 bit and the result is only being used in a context where we
4337 need to know if it is zero or nonzero, replace it with a bit
4338 extraction. This will avoid the large constant, which might
4339 have taken more than one insn to make. If the constant were
4340 not a valid argument to the AND but took only one insn to make,
4341 this is no worse, but if it took more than one insn, it will
4344 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4345 && REG_P (XEXP (SET_SRC (x), 0))
4346 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4347 && REG_P (SET_DEST (x))
4348 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4349 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4350 && XEXP (*split, 0) == SET_DEST (x)
4351 && XEXP (*split, 1) == const0_rtx)
4353 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4354 XEXP (SET_SRC (x), 0),
4355 pos, NULL_RTX, 1, 1, 0, 0);
4356 if (extraction != 0)
4358 SUBST (SET_SRC (x), extraction);
4359 return find_split_point (loc, insn);
4365 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4366 is known to be on, this can be converted into a NEG of a shift. */
4367 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4368 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4369 && 1 <= (pos = exact_log2
4370 (nonzero_bits (XEXP (SET_SRC (x), 0),
4371 GET_MODE (XEXP (SET_SRC (x), 0))))))
4373 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4377 gen_rtx_LSHIFTRT (mode,
4378 XEXP (SET_SRC (x), 0),
4381 split = find_split_point (&SET_SRC (x), insn);
4382 if (split && split != &SET_SRC (x))
4388 inner = XEXP (SET_SRC (x), 0);
4390 /* We can't optimize if either mode is a partial integer
4391 mode as we don't know how many bits are significant
4393 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4394 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4398 len = GET_MODE_BITSIZE (GET_MODE (inner));
4404 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4405 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4407 inner = XEXP (SET_SRC (x), 0);
4408 len = INTVAL (XEXP (SET_SRC (x), 1));
4409 pos = INTVAL (XEXP (SET_SRC (x), 2));
4411 if (BITS_BIG_ENDIAN)
4412 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4413 unsignedp = (code == ZERO_EXTRACT);
4421 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4423 enum machine_mode mode = GET_MODE (SET_SRC (x));
4425 /* For unsigned, we have a choice of a shift followed by an
4426 AND or two shifts. Use two shifts for field sizes where the
4427 constant might be too large. We assume here that we can
4428 always at least get 8-bit constants in an AND insn, which is
4429 true for every current RISC. */
4431 if (unsignedp && len <= 8)
4436 (mode, gen_lowpart (mode, inner),
4438 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4440 split = find_split_point (&SET_SRC (x), insn);
4441 if (split && split != &SET_SRC (x))
4448 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4449 gen_rtx_ASHIFT (mode,
4450 gen_lowpart (mode, inner),
4451 GEN_INT (GET_MODE_BITSIZE (mode)
4453 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4455 split = find_split_point (&SET_SRC (x), insn);
4456 if (split && split != &SET_SRC (x))
4461 /* See if this is a simple operation with a constant as the second
4462 operand. It might be that this constant is out of range and hence
4463 could be used as a split point. */
4464 if (BINARY_P (SET_SRC (x))
4465 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4466 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4467 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4468 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4469 return &XEXP (SET_SRC (x), 1);
4471 /* Finally, see if this is a simple operation with its first operand
4472 not in a register. The operation might require this operand in a
4473 register, so return it as a split point. We can always do this
4474 because if the first operand were another operation, we would have
4475 already found it as a split point. */
4476 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4477 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4478 return &XEXP (SET_SRC (x), 0);
4484 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4485 it is better to write this as (not (ior A B)) so we can split it.
4486 Similarly for IOR. */
4487 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4490 gen_rtx_NOT (GET_MODE (x),
4491 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4493 XEXP (XEXP (x, 0), 0),
4494 XEXP (XEXP (x, 1), 0))));
4495 return find_split_point (loc, insn);
4498 /* Many RISC machines have a large set of logical insns. If the
4499 second operand is a NOT, put it first so we will try to split the
4500 other operand first. */
4501 if (GET_CODE (XEXP (x, 1)) == NOT)
4503 rtx tem = XEXP (x, 0);
4504 SUBST (XEXP (x, 0), XEXP (x, 1));
4505 SUBST (XEXP (x, 1), tem);
4513 /* Otherwise, select our actions depending on our rtx class. */
4514 switch (GET_RTX_CLASS (code))
4516 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4518 split = find_split_point (&XEXP (x, 2), insn);
4521 /* ... fall through ... */
4523 case RTX_COMM_ARITH:
4525 case RTX_COMM_COMPARE:
4526 split = find_split_point (&XEXP (x, 1), insn);
4529 /* ... fall through ... */
4531 /* Some machines have (and (shift ...) ...) insns. If X is not
4532 an AND, but XEXP (X, 0) is, use it as our split point. */
4533 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4534 return &XEXP (x, 0);
4536 split = find_split_point (&XEXP (x, 0), insn);
4542 /* Otherwise, we don't have a split point. */
4547 /* Throughout X, replace FROM with TO, and return the result.
4548 The result is TO if X is FROM;
4549 otherwise the result is X, but its contents may have been modified.
4550 If they were modified, a record was made in undobuf so that
4551 undo_all will (among other things) return X to its original state.
4553 If the number of changes necessary is too much to record to undo,
4554 the excess changes are not made, so the result is invalid.
4555 The changes already made can still be undone.
4556 undobuf.num_undo is incremented for such changes, so by testing that
4557 the caller can tell whether the result is valid.
4559 `n_occurrences' is incremented each time FROM is replaced.
4561 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4563 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4564 by copying if `n_occurrences' is nonzero. */
4567 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4569 enum rtx_code code = GET_CODE (x);
4570 enum machine_mode op0_mode = VOIDmode;
4575 /* Two expressions are equal if they are identical copies of a shared
4576 RTX or if they are both registers with the same register number
4579 #define COMBINE_RTX_EQUAL_P(X,Y) \
4581 || (REG_P (X) && REG_P (Y) \
4582 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4584 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4587 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4590 /* If X and FROM are the same register but different modes, they
4591 will not have been seen as equal above. However, the log links code
4592 will make a LOG_LINKS entry for that case. If we do nothing, we
4593 will try to rerecognize our original insn and, when it succeeds,
4594 we will delete the feeding insn, which is incorrect.
4596 So force this insn not to match in this (rare) case. */
4597 if (! in_dest && code == REG && REG_P (from)
4598 && reg_overlap_mentioned_p (x, from))
4599 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4601 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4602 of which may contain things that can be combined. */
4603 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4606 /* It is possible to have a subexpression appear twice in the insn.
4607 Suppose that FROM is a register that appears within TO.
4608 Then, after that subexpression has been scanned once by `subst',
4609 the second time it is scanned, TO may be found. If we were
4610 to scan TO here, we would find FROM within it and create a
4611 self-referent rtl structure which is completely wrong. */
4612 if (COMBINE_RTX_EQUAL_P (x, to))
4615 /* Parallel asm_operands need special attention because all of the
4616 inputs are shared across the arms. Furthermore, unsharing the
4617 rtl results in recognition failures. Failure to handle this case
4618 specially can result in circular rtl.
4620 Solve this by doing a normal pass across the first entry of the
4621 parallel, and only processing the SET_DESTs of the subsequent
4624 if (code == PARALLEL
4625 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4626 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4628 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4630 /* If this substitution failed, this whole thing fails. */
4631 if (GET_CODE (new_rtx) == CLOBBER
4632 && XEXP (new_rtx, 0) == const0_rtx)
4635 SUBST (XVECEXP (x, 0, 0), new_rtx);
4637 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4639 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4642 && GET_CODE (dest) != CC0
4643 && GET_CODE (dest) != PC)
4645 new_rtx = subst (dest, from, to, 0, unique_copy);
4647 /* If this substitution failed, this whole thing fails. */
4648 if (GET_CODE (new_rtx) == CLOBBER
4649 && XEXP (new_rtx, 0) == const0_rtx)
4652 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4658 len = GET_RTX_LENGTH (code);
4659 fmt = GET_RTX_FORMAT (code);
4661 /* We don't need to process a SET_DEST that is a register, CC0,
4662 or PC, so set up to skip this common case. All other cases
4663 where we want to suppress replacing something inside a
4664 SET_SRC are handled via the IN_DEST operand. */
4666 && (REG_P (SET_DEST (x))
4667 || GET_CODE (SET_DEST (x)) == CC0
4668 || GET_CODE (SET_DEST (x)) == PC))
4671 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4674 op0_mode = GET_MODE (XEXP (x, 0));
4676 for (i = 0; i < len; i++)
4681 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4683 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4685 new_rtx = (unique_copy && n_occurrences
4686 ? copy_rtx (to) : to);
4691 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4694 /* If this substitution failed, this whole thing
4696 if (GET_CODE (new_rtx) == CLOBBER
4697 && XEXP (new_rtx, 0) == const0_rtx)
4701 SUBST (XVECEXP (x, i, j), new_rtx);
4704 else if (fmt[i] == 'e')
4706 /* If this is a register being set, ignore it. */
4707 new_rtx = XEXP (x, i);
4710 && (((code == SUBREG || code == ZERO_EXTRACT)
4712 || code == STRICT_LOW_PART))
4715 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4717 /* In general, don't install a subreg involving two
4718 modes not tieable. It can worsen register
4719 allocation, and can even make invalid reload
4720 insns, since the reg inside may need to be copied
4721 from in the outside mode, and that may be invalid
4722 if it is an fp reg copied in integer mode.
4724 We allow two exceptions to this: It is valid if
4725 it is inside another SUBREG and the mode of that
4726 SUBREG and the mode of the inside of TO is
4727 tieable and it is valid if X is a SET that copies
4730 if (GET_CODE (to) == SUBREG
4731 && ! MODES_TIEABLE_P (GET_MODE (to),
4732 GET_MODE (SUBREG_REG (to)))
4733 && ! (code == SUBREG
4734 && MODES_TIEABLE_P (GET_MODE (x),
4735 GET_MODE (SUBREG_REG (to))))
4737 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4740 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4742 #ifdef CANNOT_CHANGE_MODE_CLASS
4745 && REGNO (to) < FIRST_PSEUDO_REGISTER
4746 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4749 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4752 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4756 /* If we are in a SET_DEST, suppress most cases unless we
4757 have gone inside a MEM, in which case we want to
4758 simplify the address. We assume here that things that
4759 are actually part of the destination have their inner
4760 parts in the first expression. This is true for SUBREG,
4761 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4762 things aside from REG and MEM that should appear in a
4764 new_rtx = subst (XEXP (x, i), from, to,
4766 && (code == SUBREG || code == STRICT_LOW_PART
4767 || code == ZERO_EXTRACT))
4769 && i == 0), unique_copy);
4771 /* If we found that we will have to reject this combination,
4772 indicate that by returning the CLOBBER ourselves, rather than
4773 an expression containing it. This will speed things up as
4774 well as prevent accidents where two CLOBBERs are considered
4775 to be equal, thus producing an incorrect simplification. */
4777 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4780 if (GET_CODE (x) == SUBREG
4781 && (CONST_INT_P (new_rtx)
4782 || GET_CODE (new_rtx) == CONST_DOUBLE))
4784 enum machine_mode mode = GET_MODE (x);
4786 x = simplify_subreg (GET_MODE (x), new_rtx,
4787 GET_MODE (SUBREG_REG (x)),
4790 x = gen_rtx_CLOBBER (mode, const0_rtx);
4792 else if (CONST_INT_P (new_rtx)
4793 && GET_CODE (x) == ZERO_EXTEND)
4795 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4796 new_rtx, GET_MODE (XEXP (x, 0)));
4800 SUBST (XEXP (x, i), new_rtx);
4805 /* Check if we are loading something from the constant pool via float
4806 extension; in this case we would undo compress_float_constant
4807 optimization and degenerate constant load to an immediate value. */
4808 if (GET_CODE (x) == FLOAT_EXTEND
4809 && MEM_P (XEXP (x, 0))
4810 && MEM_READONLY_P (XEXP (x, 0)))
4812 rtx tmp = avoid_constant_pool_reference (x);
4817 /* Try to simplify X. If the simplification changed the code, it is likely
4818 that further simplification will help, so loop, but limit the number
4819 of repetitions that will be performed. */
4821 for (i = 0; i < 4; i++)
4823 /* If X is sufficiently simple, don't bother trying to do anything
4825 if (code != CONST_INT && code != REG && code != CLOBBER)
4826 x = combine_simplify_rtx (x, op0_mode, in_dest);
4828 if (GET_CODE (x) == code)
4831 code = GET_CODE (x);
4833 /* We no longer know the original mode of operand 0 since we
4834 have changed the form of X) */
4835 op0_mode = VOIDmode;
4841 /* Simplify X, a piece of RTL. We just operate on the expression at the
4842 outer level; call `subst' to simplify recursively. Return the new
4845 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4846 if we are inside a SET_DEST. */
4849 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4851 enum rtx_code code = GET_CODE (x);
4852 enum machine_mode mode = GET_MODE (x);
4856 /* If this is a commutative operation, put a constant last and a complex
4857 expression first. We don't need to do this for comparisons here. */
4858 if (COMMUTATIVE_ARITH_P (x)
4859 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4862 SUBST (XEXP (x, 0), XEXP (x, 1));
4863 SUBST (XEXP (x, 1), temp);
4866 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4867 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4868 things. Check for cases where both arms are testing the same
4871 Don't do anything if all operands are very simple. */
4874 && ((!OBJECT_P (XEXP (x, 0))
4875 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4876 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4877 || (!OBJECT_P (XEXP (x, 1))
4878 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4879 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4881 && (!OBJECT_P (XEXP (x, 0))
4882 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4883 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4885 rtx cond, true_rtx, false_rtx;
4887 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4889 /* If everything is a comparison, what we have is highly unlikely
4890 to be simpler, so don't use it. */
4891 && ! (COMPARISON_P (x)
4892 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4894 rtx cop1 = const0_rtx;
4895 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4897 if (cond_code == NE && COMPARISON_P (cond))
4900 /* Simplify the alternative arms; this may collapse the true and
4901 false arms to store-flag values. Be careful to use copy_rtx
4902 here since true_rtx or false_rtx might share RTL with x as a
4903 result of the if_then_else_cond call above. */
4904 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4905 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4907 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4908 is unlikely to be simpler. */
4909 if (general_operand (true_rtx, VOIDmode)
4910 && general_operand (false_rtx, VOIDmode))
4912 enum rtx_code reversed;
4914 /* Restarting if we generate a store-flag expression will cause
4915 us to loop. Just drop through in this case. */
4917 /* If the result values are STORE_FLAG_VALUE and zero, we can
4918 just make the comparison operation. */
4919 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4920 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4922 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4923 && ((reversed = reversed_comparison_code_parts
4924 (cond_code, cond, cop1, NULL))
4926 x = simplify_gen_relational (reversed, mode, VOIDmode,
4929 /* Likewise, we can make the negate of a comparison operation
4930 if the result values are - STORE_FLAG_VALUE and zero. */
4931 else if (CONST_INT_P (true_rtx)
4932 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4933 && false_rtx == const0_rtx)
4934 x = simplify_gen_unary (NEG, mode,
4935 simplify_gen_relational (cond_code,
4939 else if (CONST_INT_P (false_rtx)
4940 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4941 && true_rtx == const0_rtx
4942 && ((reversed = reversed_comparison_code_parts
4943 (cond_code, cond, cop1, NULL))
4945 x = simplify_gen_unary (NEG, mode,
4946 simplify_gen_relational (reversed,
4951 return gen_rtx_IF_THEN_ELSE (mode,
4952 simplify_gen_relational (cond_code,
4957 true_rtx, false_rtx);
4959 code = GET_CODE (x);
4960 op0_mode = VOIDmode;
4965 /* Try to fold this expression in case we have constants that weren't
4968 switch (GET_RTX_CLASS (code))
4971 if (op0_mode == VOIDmode)
4972 op0_mode = GET_MODE (XEXP (x, 0));
4973 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4976 case RTX_COMM_COMPARE:
4978 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4979 if (cmp_mode == VOIDmode)
4981 cmp_mode = GET_MODE (XEXP (x, 1));
4982 if (cmp_mode == VOIDmode)
4983 cmp_mode = op0_mode;
4985 temp = simplify_relational_operation (code, mode, cmp_mode,
4986 XEXP (x, 0), XEXP (x, 1));
4989 case RTX_COMM_ARITH:
4991 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4993 case RTX_BITFIELD_OPS:
4995 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4996 XEXP (x, 1), XEXP (x, 2));
5005 code = GET_CODE (temp);
5006 op0_mode = VOIDmode;
5007 mode = GET_MODE (temp);
5010 /* First see if we can apply the inverse distributive law. */
5011 if (code == PLUS || code == MINUS
5012 || code == AND || code == IOR || code == XOR)
5014 x = apply_distributive_law (x);
5015 code = GET_CODE (x);
5016 op0_mode = VOIDmode;
5019 /* If CODE is an associative operation not otherwise handled, see if we
5020 can associate some operands. This can win if they are constants or
5021 if they are logically related (i.e. (a & b) & a). */
5022 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5023 || code == AND || code == IOR || code == XOR
5024 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5025 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5026 || (flag_associative_math && FLOAT_MODE_P (mode))))
5028 if (GET_CODE (XEXP (x, 0)) == code)
5030 rtx other = XEXP (XEXP (x, 0), 0);
5031 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5032 rtx inner_op1 = XEXP (x, 1);
5035 /* Make sure we pass the constant operand if any as the second
5036 one if this is a commutative operation. */
5037 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5039 rtx tem = inner_op0;
5040 inner_op0 = inner_op1;
5043 inner = simplify_binary_operation (code == MINUS ? PLUS
5044 : code == DIV ? MULT
5046 mode, inner_op0, inner_op1);
5048 /* For commutative operations, try the other pair if that one
5050 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5052 other = XEXP (XEXP (x, 0), 1);
5053 inner = simplify_binary_operation (code, mode,
5054 XEXP (XEXP (x, 0), 0),
5059 return simplify_gen_binary (code, mode, other, inner);
5063 /* A little bit of algebraic simplification here. */
5067 /* Ensure that our address has any ASHIFTs converted to MULT in case
5068 address-recognizing predicates are called later. */
5069 temp = make_compound_operation (XEXP (x, 0), MEM);
5070 SUBST (XEXP (x, 0), temp);
5074 if (op0_mode == VOIDmode)
5075 op0_mode = GET_MODE (SUBREG_REG (x));
5077 /* See if this can be moved to simplify_subreg. */
5078 if (CONSTANT_P (SUBREG_REG (x))
5079 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5080 /* Don't call gen_lowpart if the inner mode
5081 is VOIDmode and we cannot simplify it, as SUBREG without
5082 inner mode is invalid. */
5083 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5084 || gen_lowpart_common (mode, SUBREG_REG (x))))
5085 return gen_lowpart (mode, SUBREG_REG (x));
5087 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5091 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5097 /* Don't change the mode of the MEM if that would change the meaning
5099 if (MEM_P (SUBREG_REG (x))
5100 && (MEM_VOLATILE_P (SUBREG_REG (x))
5101 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5102 return gen_rtx_CLOBBER (mode, const0_rtx);
5104 /* Note that we cannot do any narrowing for non-constants since
5105 we might have been counting on using the fact that some bits were
5106 zero. We now do this in the SET. */
5111 temp = expand_compound_operation (XEXP (x, 0));
5113 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5114 replaced by (lshiftrt X C). This will convert
5115 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5117 if (GET_CODE (temp) == ASHIFTRT
5118 && CONST_INT_P (XEXP (temp, 1))
5119 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5120 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5121 INTVAL (XEXP (temp, 1)));
5123 /* If X has only a single bit that might be nonzero, say, bit I, convert
5124 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5125 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5126 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5127 or a SUBREG of one since we'd be making the expression more
5128 complex if it was just a register. */
5131 && ! (GET_CODE (temp) == SUBREG
5132 && REG_P (SUBREG_REG (temp)))
5133 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5135 rtx temp1 = simplify_shift_const
5136 (NULL_RTX, ASHIFTRT, mode,
5137 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5138 GET_MODE_BITSIZE (mode) - 1 - i),
5139 GET_MODE_BITSIZE (mode) - 1 - i);
5141 /* If all we did was surround TEMP with the two shifts, we
5142 haven't improved anything, so don't use it. Otherwise,
5143 we are better off with TEMP1. */
5144 if (GET_CODE (temp1) != ASHIFTRT
5145 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5146 || XEXP (XEXP (temp1, 0), 0) != temp)
5152 /* We can't handle truncation to a partial integer mode here
5153 because we don't know the real bitsize of the partial
5155 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5158 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5160 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5161 GET_MODE_MASK (mode), 0));
5163 /* We can truncate a constant value and return it. */
5164 if (CONST_INT_P (XEXP (x, 0)))
5165 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5167 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5168 whose value is a comparison can be replaced with a subreg if
5169 STORE_FLAG_VALUE permits. */
5170 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5171 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5172 && (temp = get_last_value (XEXP (x, 0)))
5173 && COMPARISON_P (temp))
5174 return gen_lowpart (mode, XEXP (x, 0));
5178 /* (const (const X)) can become (const X). Do it this way rather than
5179 returning the inner CONST since CONST can be shared with a
5181 if (GET_CODE (XEXP (x, 0)) == CONST)
5182 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5187 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5188 can add in an offset. find_split_point will split this address up
5189 again if it doesn't match. */
5190 if (GET_CODE (XEXP (x, 0)) == HIGH
5191 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5197 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5198 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5199 bit-field and can be replaced by either a sign_extend or a
5200 sign_extract. The `and' may be a zero_extend and the two
5201 <c>, -<c> constants may be reversed. */
5202 if (GET_CODE (XEXP (x, 0)) == XOR
5203 && CONST_INT_P (XEXP (x, 1))
5204 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5205 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5206 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5207 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5208 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5209 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5210 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5211 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5212 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
5213 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5214 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5215 == (unsigned int) i + 1))))
5216 return simplify_shift_const
5217 (NULL_RTX, ASHIFTRT, mode,
5218 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5219 XEXP (XEXP (XEXP (x, 0), 0), 0),
5220 GET_MODE_BITSIZE (mode) - (i + 1)),
5221 GET_MODE_BITSIZE (mode) - (i + 1));
5223 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5224 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5225 the bitsize of the mode - 1. This allows simplification of
5226 "a = (b & 8) == 0;" */
5227 if (XEXP (x, 1) == constm1_rtx
5228 && !REG_P (XEXP (x, 0))
5229 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5230 && REG_P (SUBREG_REG (XEXP (x, 0))))
5231 && nonzero_bits (XEXP (x, 0), mode) == 1)
5232 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5233 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5234 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5235 GET_MODE_BITSIZE (mode) - 1),
5236 GET_MODE_BITSIZE (mode) - 1);
5238 /* If we are adding two things that have no bits in common, convert
5239 the addition into an IOR. This will often be further simplified,
5240 for example in cases like ((a & 1) + (a & 2)), which can
5243 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5244 && (nonzero_bits (XEXP (x, 0), mode)
5245 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5247 /* Try to simplify the expression further. */
5248 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5249 temp = combine_simplify_rtx (tor, mode, in_dest);
5251 /* If we could, great. If not, do not go ahead with the IOR
5252 replacement, since PLUS appears in many special purpose
5253 address arithmetic instructions. */
5254 if (GET_CODE (temp) != CLOBBER && temp != tor)
5260 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5261 (and <foo> (const_int pow2-1)) */
5262 if (GET_CODE (XEXP (x, 1)) == AND
5263 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5264 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5265 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5266 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5267 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5271 /* If we have (mult (plus A B) C), apply the distributive law and then
5272 the inverse distributive law to see if things simplify. This
5273 occurs mostly in addresses, often when unrolling loops. */
5275 if (GET_CODE (XEXP (x, 0)) == PLUS)
5277 rtx result = distribute_and_simplify_rtx (x, 0);
5282 /* Try simplify a*(b/c) as (a*b)/c. */
5283 if (FLOAT_MODE_P (mode) && flag_associative_math
5284 && GET_CODE (XEXP (x, 0)) == DIV)
5286 rtx tem = simplify_binary_operation (MULT, mode,
5287 XEXP (XEXP (x, 0), 0),
5290 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5295 /* If this is a divide by a power of two, treat it as a shift if
5296 its first operand is a shift. */
5297 if (CONST_INT_P (XEXP (x, 1))
5298 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5299 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5300 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5301 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5302 || GET_CODE (XEXP (x, 0)) == ROTATE
5303 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5304 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5308 case GT: case GTU: case GE: case GEU:
5309 case LT: case LTU: case LE: case LEU:
5310 case UNEQ: case LTGT:
5311 case UNGT: case UNGE:
5312 case UNLT: case UNLE:
5313 case UNORDERED: case ORDERED:
5314 /* If the first operand is a condition code, we can't do anything
5316 if (GET_CODE (XEXP (x, 0)) == COMPARE
5317 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5318 && ! CC0_P (XEXP (x, 0))))
5320 rtx op0 = XEXP (x, 0);
5321 rtx op1 = XEXP (x, 1);
5322 enum rtx_code new_code;
5324 if (GET_CODE (op0) == COMPARE)
5325 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5327 /* Simplify our comparison, if possible. */
5328 new_code = simplify_comparison (code, &op0, &op1);
5330 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5331 if only the low-order bit is possibly nonzero in X (such as when
5332 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5333 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5334 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5337 Remove any ZERO_EXTRACT we made when thinking this was a
5338 comparison. It may now be simpler to use, e.g., an AND. If a
5339 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5340 the call to make_compound_operation in the SET case. */
5342 if (STORE_FLAG_VALUE == 1
5343 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5344 && op1 == const0_rtx
5345 && mode == GET_MODE (op0)
5346 && nonzero_bits (op0, mode) == 1)
5347 return gen_lowpart (mode,
5348 expand_compound_operation (op0));
5350 else if (STORE_FLAG_VALUE == 1
5351 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5352 && op1 == const0_rtx
5353 && mode == GET_MODE (op0)
5354 && (num_sign_bit_copies (op0, mode)
5355 == GET_MODE_BITSIZE (mode)))
5357 op0 = expand_compound_operation (op0);
5358 return simplify_gen_unary (NEG, mode,
5359 gen_lowpart (mode, op0),
5363 else if (STORE_FLAG_VALUE == 1
5364 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5365 && op1 == const0_rtx
5366 && mode == GET_MODE (op0)
5367 && nonzero_bits (op0, mode) == 1)
5369 op0 = expand_compound_operation (op0);
5370 return simplify_gen_binary (XOR, mode,
5371 gen_lowpart (mode, op0),
5375 else if (STORE_FLAG_VALUE == 1
5376 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5377 && op1 == const0_rtx
5378 && mode == GET_MODE (op0)
5379 && (num_sign_bit_copies (op0, mode)
5380 == GET_MODE_BITSIZE (mode)))
5382 op0 = expand_compound_operation (op0);
5383 return plus_constant (gen_lowpart (mode, op0), 1);
5386 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5388 if (STORE_FLAG_VALUE == -1
5389 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5390 && op1 == const0_rtx
5391 && (num_sign_bit_copies (op0, mode)
5392 == GET_MODE_BITSIZE (mode)))
5393 return gen_lowpart (mode,
5394 expand_compound_operation (op0));
5396 else if (STORE_FLAG_VALUE == -1
5397 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5398 && op1 == const0_rtx
5399 && mode == GET_MODE (op0)
5400 && nonzero_bits (op0, mode) == 1)
5402 op0 = expand_compound_operation (op0);
5403 return simplify_gen_unary (NEG, mode,
5404 gen_lowpart (mode, op0),
5408 else if (STORE_FLAG_VALUE == -1
5409 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5410 && op1 == const0_rtx
5411 && mode == GET_MODE (op0)
5412 && (num_sign_bit_copies (op0, mode)
5413 == GET_MODE_BITSIZE (mode)))
5415 op0 = expand_compound_operation (op0);
5416 return simplify_gen_unary (NOT, mode,
5417 gen_lowpart (mode, op0),
5421 /* If X is 0/1, (eq X 0) is X-1. */
5422 else if (STORE_FLAG_VALUE == -1
5423 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5424 && op1 == const0_rtx
5425 && mode == GET_MODE (op0)
5426 && nonzero_bits (op0, mode) == 1)
5428 op0 = expand_compound_operation (op0);
5429 return plus_constant (gen_lowpart (mode, op0), -1);
5432 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5433 one bit that might be nonzero, we can convert (ne x 0) to
5434 (ashift x c) where C puts the bit in the sign bit. Remove any
5435 AND with STORE_FLAG_VALUE when we are done, since we are only
5436 going to test the sign bit. */
5437 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5438 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5439 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5440 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5441 && op1 == const0_rtx
5442 && mode == GET_MODE (op0)
5443 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5445 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5446 expand_compound_operation (op0),
5447 GET_MODE_BITSIZE (mode) - 1 - i);
5448 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5454 /* If the code changed, return a whole new comparison. */
5455 if (new_code != code)
5456 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5458 /* Otherwise, keep this operation, but maybe change its operands.
5459 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5460 SUBST (XEXP (x, 0), op0);
5461 SUBST (XEXP (x, 1), op1);
5466 return simplify_if_then_else (x);
5472 /* If we are processing SET_DEST, we are done. */
5476 return expand_compound_operation (x);
5479 return simplify_set (x);
5483 return simplify_logical (x);
5490 /* If this is a shift by a constant amount, simplify it. */
5491 if (CONST_INT_P (XEXP (x, 1)))
5492 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5493 INTVAL (XEXP (x, 1)));
5495 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5497 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5499 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5511 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5514 simplify_if_then_else (rtx x)
5516 enum machine_mode mode = GET_MODE (x);
5517 rtx cond = XEXP (x, 0);
5518 rtx true_rtx = XEXP (x, 1);
5519 rtx false_rtx = XEXP (x, 2);
5520 enum rtx_code true_code = GET_CODE (cond);
5521 int comparison_p = COMPARISON_P (cond);
5524 enum rtx_code false_code;
5527 /* Simplify storing of the truth value. */
5528 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5529 return simplify_gen_relational (true_code, mode, VOIDmode,
5530 XEXP (cond, 0), XEXP (cond, 1));
5532 /* Also when the truth value has to be reversed. */
5534 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5535 && (reversed = reversed_comparison (cond, mode)))
5538 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5539 in it is being compared against certain values. Get the true and false
5540 comparisons and see if that says anything about the value of each arm. */
5543 && ((false_code = reversed_comparison_code (cond, NULL))
5545 && REG_P (XEXP (cond, 0)))
5548 rtx from = XEXP (cond, 0);
5549 rtx true_val = XEXP (cond, 1);
5550 rtx false_val = true_val;
5553 /* If FALSE_CODE is EQ, swap the codes and arms. */
5555 if (false_code == EQ)
5557 swapped = 1, true_code = EQ, false_code = NE;
5558 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5561 /* If we are comparing against zero and the expression being tested has
5562 only a single bit that might be nonzero, that is its value when it is
5563 not equal to zero. Similarly if it is known to be -1 or 0. */
5565 if (true_code == EQ && true_val == const0_rtx
5566 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5569 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5571 else if (true_code == EQ && true_val == const0_rtx
5572 && (num_sign_bit_copies (from, GET_MODE (from))
5573 == GET_MODE_BITSIZE (GET_MODE (from))))
5576 false_val = constm1_rtx;
5579 /* Now simplify an arm if we know the value of the register in the
5580 branch and it is used in the arm. Be careful due to the potential
5581 of locally-shared RTL. */
5583 if (reg_mentioned_p (from, true_rtx))
5584 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5586 pc_rtx, pc_rtx, 0, 0);
5587 if (reg_mentioned_p (from, false_rtx))
5588 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5590 pc_rtx, pc_rtx, 0, 0);
5592 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5593 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5595 true_rtx = XEXP (x, 1);
5596 false_rtx = XEXP (x, 2);
5597 true_code = GET_CODE (cond);
5600 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5601 reversed, do so to avoid needing two sets of patterns for
5602 subtract-and-branch insns. Similarly if we have a constant in the true
5603 arm, the false arm is the same as the first operand of the comparison, or
5604 the false arm is more complicated than the true arm. */
5607 && reversed_comparison_code (cond, NULL) != UNKNOWN
5608 && (true_rtx == pc_rtx
5609 || (CONSTANT_P (true_rtx)
5610 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5611 || true_rtx == const0_rtx
5612 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5613 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5614 && !OBJECT_P (false_rtx))
5615 || reg_mentioned_p (true_rtx, false_rtx)
5616 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5618 true_code = reversed_comparison_code (cond, NULL);
5619 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5620 SUBST (XEXP (x, 1), false_rtx);
5621 SUBST (XEXP (x, 2), true_rtx);
5623 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5626 /* It is possible that the conditional has been simplified out. */
5627 true_code = GET_CODE (cond);
5628 comparison_p = COMPARISON_P (cond);
5631 /* If the two arms are identical, we don't need the comparison. */
5633 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5636 /* Convert a == b ? b : a to "a". */
5637 if (true_code == EQ && ! side_effects_p (cond)
5638 && !HONOR_NANS (mode)
5639 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5640 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5642 else if (true_code == NE && ! side_effects_p (cond)
5643 && !HONOR_NANS (mode)
5644 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5645 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5648 /* Look for cases where we have (abs x) or (neg (abs X)). */
5650 if (GET_MODE_CLASS (mode) == MODE_INT
5652 && XEXP (cond, 1) == const0_rtx
5653 && GET_CODE (false_rtx) == NEG
5654 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5655 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5656 && ! side_effects_p (true_rtx))
5661 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5665 simplify_gen_unary (NEG, mode,
5666 simplify_gen_unary (ABS, mode, true_rtx, mode),
5672 /* Look for MIN or MAX. */
5674 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5676 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5677 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5678 && ! side_effects_p (cond))
5683 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5686 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5689 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5692 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5697 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5698 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5699 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5700 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5701 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5702 neither 1 or -1, but it isn't worth checking for. */
5704 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5706 && GET_MODE_CLASS (mode) == MODE_INT
5707 && ! side_effects_p (x))
5709 rtx t = make_compound_operation (true_rtx, SET);
5710 rtx f = make_compound_operation (false_rtx, SET);
5711 rtx cond_op0 = XEXP (cond, 0);
5712 rtx cond_op1 = XEXP (cond, 1);
5713 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5714 enum machine_mode m = mode;
5715 rtx z = 0, c1 = NULL_RTX;
5717 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5718 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5719 || GET_CODE (t) == ASHIFT
5720 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5721 && rtx_equal_p (XEXP (t, 0), f))
5722 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5724 /* If an identity-zero op is commutative, check whether there
5725 would be a match if we swapped the operands. */
5726 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5727 || GET_CODE (t) == XOR)
5728 && rtx_equal_p (XEXP (t, 1), f))
5729 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5730 else if (GET_CODE (t) == SIGN_EXTEND
5731 && (GET_CODE (XEXP (t, 0)) == PLUS
5732 || GET_CODE (XEXP (t, 0)) == MINUS
5733 || GET_CODE (XEXP (t, 0)) == IOR
5734 || GET_CODE (XEXP (t, 0)) == XOR
5735 || GET_CODE (XEXP (t, 0)) == ASHIFT
5736 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5737 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5738 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5739 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5740 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5741 && (num_sign_bit_copies (f, GET_MODE (f))
5743 (GET_MODE_BITSIZE (mode)
5744 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5746 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5747 extend_op = SIGN_EXTEND;
5748 m = GET_MODE (XEXP (t, 0));
5750 else if (GET_CODE (t) == SIGN_EXTEND
5751 && (GET_CODE (XEXP (t, 0)) == PLUS
5752 || GET_CODE (XEXP (t, 0)) == IOR
5753 || GET_CODE (XEXP (t, 0)) == XOR)
5754 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5755 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5756 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5757 && (num_sign_bit_copies (f, GET_MODE (f))
5759 (GET_MODE_BITSIZE (mode)
5760 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5762 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5763 extend_op = SIGN_EXTEND;
5764 m = GET_MODE (XEXP (t, 0));
5766 else if (GET_CODE (t) == ZERO_EXTEND
5767 && (GET_CODE (XEXP (t, 0)) == PLUS
5768 || GET_CODE (XEXP (t, 0)) == MINUS
5769 || GET_CODE (XEXP (t, 0)) == IOR
5770 || GET_CODE (XEXP (t, 0)) == XOR
5771 || GET_CODE (XEXP (t, 0)) == ASHIFT
5772 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5773 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5774 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5775 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5776 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5777 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5778 && ((nonzero_bits (f, GET_MODE (f))
5779 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5782 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5783 extend_op = ZERO_EXTEND;
5784 m = GET_MODE (XEXP (t, 0));
5786 else if (GET_CODE (t) == ZERO_EXTEND
5787 && (GET_CODE (XEXP (t, 0)) == PLUS
5788 || GET_CODE (XEXP (t, 0)) == IOR
5789 || GET_CODE (XEXP (t, 0)) == XOR)
5790 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5791 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5792 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5793 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5794 && ((nonzero_bits (f, GET_MODE (f))
5795 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5798 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5799 extend_op = ZERO_EXTEND;
5800 m = GET_MODE (XEXP (t, 0));
5805 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5806 cond_op0, cond_op1),
5807 pc_rtx, pc_rtx, 0, 0);
5808 temp = simplify_gen_binary (MULT, m, temp,
5809 simplify_gen_binary (MULT, m, c1,
5811 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5812 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5814 if (extend_op != UNKNOWN)
5815 temp = simplify_gen_unary (extend_op, mode, temp, m);
5821 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5822 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5823 negation of a single bit, we can convert this operation to a shift. We
5824 can actually do this more generally, but it doesn't seem worth it. */
5826 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5827 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5828 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5829 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5830 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5831 == GET_MODE_BITSIZE (mode))
5832 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5834 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5835 gen_lowpart (mode, XEXP (cond, 0)), i);
5837 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5838 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5839 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5840 && GET_MODE (XEXP (cond, 0)) == mode
5841 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5842 == nonzero_bits (XEXP (cond, 0), mode)
5843 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5844 return XEXP (cond, 0);
5849 /* Simplify X, a SET expression. Return the new expression. */
5852 simplify_set (rtx x)
5854 rtx src = SET_SRC (x);
5855 rtx dest = SET_DEST (x);
5856 enum machine_mode mode
5857 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5861 /* (set (pc) (return)) gets written as (return). */
5862 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5865 /* Now that we know for sure which bits of SRC we are using, see if we can
5866 simplify the expression for the object knowing that we only need the
5869 if (GET_MODE_CLASS (mode) == MODE_INT
5870 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5872 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5873 SUBST (SET_SRC (x), src);
5876 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5877 the comparison result and try to simplify it unless we already have used
5878 undobuf.other_insn. */
5879 if ((GET_MODE_CLASS (mode) == MODE_CC
5880 || GET_CODE (src) == COMPARE
5882 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5883 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5884 && COMPARISON_P (*cc_use)
5885 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5887 enum rtx_code old_code = GET_CODE (*cc_use);
5888 enum rtx_code new_code;
5890 int other_changed = 0;
5891 enum machine_mode compare_mode = GET_MODE (dest);
5893 if (GET_CODE (src) == COMPARE)
5894 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5896 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5898 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5901 new_code = old_code;
5902 else if (!CONSTANT_P (tmp))
5904 new_code = GET_CODE (tmp);
5905 op0 = XEXP (tmp, 0);
5906 op1 = XEXP (tmp, 1);
5910 rtx pat = PATTERN (other_insn);
5911 undobuf.other_insn = other_insn;
5912 SUBST (*cc_use, tmp);
5914 /* Attempt to simplify CC user. */
5915 if (GET_CODE (pat) == SET)
5917 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5918 if (new_rtx != NULL_RTX)
5919 SUBST (SET_SRC (pat), new_rtx);
5922 /* Convert X into a no-op move. */
5923 SUBST (SET_DEST (x), pc_rtx);
5924 SUBST (SET_SRC (x), pc_rtx);
5928 /* Simplify our comparison, if possible. */
5929 new_code = simplify_comparison (new_code, &op0, &op1);
5931 #ifdef SELECT_CC_MODE
5932 /* If this machine has CC modes other than CCmode, check to see if we
5933 need to use a different CC mode here. */
5934 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5935 compare_mode = GET_MODE (op0);
5937 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5940 /* If the mode changed, we have to change SET_DEST, the mode in the
5941 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5942 a hard register, just build new versions with the proper mode. If it
5943 is a pseudo, we lose unless it is only time we set the pseudo, in
5944 which case we can safely change its mode. */
5945 if (compare_mode != GET_MODE (dest))
5947 if (can_change_dest_mode (dest, 0, compare_mode))
5949 unsigned int regno = REGNO (dest);
5952 if (regno < FIRST_PSEUDO_REGISTER)
5953 new_dest = gen_rtx_REG (compare_mode, regno);
5956 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5957 new_dest = regno_reg_rtx[regno];
5960 SUBST (SET_DEST (x), new_dest);
5961 SUBST (XEXP (*cc_use, 0), new_dest);
5968 #endif /* SELECT_CC_MODE */
5970 /* If the code changed, we have to build a new comparison in
5971 undobuf.other_insn. */
5972 if (new_code != old_code)
5974 int other_changed_previously = other_changed;
5975 unsigned HOST_WIDE_INT mask;
5976 rtx old_cc_use = *cc_use;
5978 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5982 /* If the only change we made was to change an EQ into an NE or
5983 vice versa, OP0 has only one bit that might be nonzero, and OP1
5984 is zero, check if changing the user of the condition code will
5985 produce a valid insn. If it won't, we can keep the original code
5986 in that insn by surrounding our operation with an XOR. */
5988 if (((old_code == NE && new_code == EQ)
5989 || (old_code == EQ && new_code == NE))
5990 && ! other_changed_previously && op1 == const0_rtx
5991 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5992 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5994 rtx pat = PATTERN (other_insn), note = 0;
5996 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5997 && ! check_asm_operands (pat)))
5999 *cc_use = old_cc_use;
6002 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6003 op0, GEN_INT (mask));
6009 undobuf.other_insn = other_insn;
6011 /* Otherwise, if we didn't previously have a COMPARE in the
6012 correct mode, we need one. */
6013 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6015 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6018 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6020 SUBST (SET_SRC (x), op0);
6023 /* Otherwise, update the COMPARE if needed. */
6024 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6026 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6032 /* Get SET_SRC in a form where we have placed back any
6033 compound expressions. Then do the checks below. */
6034 src = make_compound_operation (src, SET);
6035 SUBST (SET_SRC (x), src);
6038 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6039 and X being a REG or (subreg (reg)), we may be able to convert this to
6040 (set (subreg:m2 x) (op)).
6042 We can always do this if M1 is narrower than M2 because that means that
6043 we only care about the low bits of the result.
6045 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6046 perform a narrower operation than requested since the high-order bits will
6047 be undefined. On machine where it is defined, this transformation is safe
6048 as long as M1 and M2 have the same number of words. */
6050 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6051 && !OBJECT_P (SUBREG_REG (src))
6052 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6054 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6055 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6056 #ifndef WORD_REGISTER_OPERATIONS
6057 && (GET_MODE_SIZE (GET_MODE (src))
6058 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6060 #ifdef CANNOT_CHANGE_MODE_CLASS
6061 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6062 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6063 GET_MODE (SUBREG_REG (src)),
6067 || (GET_CODE (dest) == SUBREG
6068 && REG_P (SUBREG_REG (dest)))))
6070 SUBST (SET_DEST (x),
6071 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6073 SUBST (SET_SRC (x), SUBREG_REG (src));
6075 src = SET_SRC (x), dest = SET_DEST (x);
6079 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6082 && GET_CODE (src) == SUBREG
6083 && subreg_lowpart_p (src)
6084 && (GET_MODE_BITSIZE (GET_MODE (src))
6085 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6087 rtx inner = SUBREG_REG (src);
6088 enum machine_mode inner_mode = GET_MODE (inner);
6090 /* Here we make sure that we don't have a sign bit on. */
6091 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6092 && (nonzero_bits (inner, inner_mode)
6093 < ((unsigned HOST_WIDE_INT) 1
6094 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6096 SUBST (SET_SRC (x), inner);
6102 #ifdef LOAD_EXTEND_OP
6103 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6104 would require a paradoxical subreg. Replace the subreg with a
6105 zero_extend to avoid the reload that would otherwise be required. */
6107 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6108 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6109 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6110 && SUBREG_BYTE (src) == 0
6111 && (GET_MODE_SIZE (GET_MODE (src))
6112 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6113 && MEM_P (SUBREG_REG (src)))
6116 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6117 GET_MODE (src), SUBREG_REG (src)));
6123 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6124 are comparing an item known to be 0 or -1 against 0, use a logical
6125 operation instead. Check for one of the arms being an IOR of the other
6126 arm with some value. We compute three terms to be IOR'ed together. In
6127 practice, at most two will be nonzero. Then we do the IOR's. */
6129 if (GET_CODE (dest) != PC
6130 && GET_CODE (src) == IF_THEN_ELSE
6131 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6132 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6133 && XEXP (XEXP (src, 0), 1) == const0_rtx
6134 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6135 #ifdef HAVE_conditional_move
6136 && ! can_conditionally_move_p (GET_MODE (src))
6138 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6139 GET_MODE (XEXP (XEXP (src, 0), 0)))
6140 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6141 && ! side_effects_p (src))
6143 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6144 ? XEXP (src, 1) : XEXP (src, 2));
6145 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6146 ? XEXP (src, 2) : XEXP (src, 1));
6147 rtx term1 = const0_rtx, term2, term3;
6149 if (GET_CODE (true_rtx) == IOR
6150 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6151 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6152 else if (GET_CODE (true_rtx) == IOR
6153 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6154 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6155 else if (GET_CODE (false_rtx) == IOR
6156 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6157 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6158 else if (GET_CODE (false_rtx) == IOR
6159 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6160 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6162 term2 = simplify_gen_binary (AND, GET_MODE (src),
6163 XEXP (XEXP (src, 0), 0), true_rtx);
6164 term3 = simplify_gen_binary (AND, GET_MODE (src),
6165 simplify_gen_unary (NOT, GET_MODE (src),
6166 XEXP (XEXP (src, 0), 0),
6171 simplify_gen_binary (IOR, GET_MODE (src),
6172 simplify_gen_binary (IOR, GET_MODE (src),
6179 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6180 whole thing fail. */
6181 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6183 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6186 /* Convert this into a field assignment operation, if possible. */
6187 return make_field_assignment (x);
6190 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6194 simplify_logical (rtx x)
6196 enum machine_mode mode = GET_MODE (x);
6197 rtx op0 = XEXP (x, 0);
6198 rtx op1 = XEXP (x, 1);
6200 switch (GET_CODE (x))
6203 /* We can call simplify_and_const_int only if we don't lose
6204 any (sign) bits when converting INTVAL (op1) to
6205 "unsigned HOST_WIDE_INT". */
6206 if (CONST_INT_P (op1)
6207 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6208 || INTVAL (op1) > 0))
6210 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6211 if (GET_CODE (x) != AND)
6218 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6219 apply the distributive law and then the inverse distributive
6220 law to see if things simplify. */
6221 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6223 rtx result = distribute_and_simplify_rtx (x, 0);
6227 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6229 rtx result = distribute_and_simplify_rtx (x, 1);
6236 /* If we have (ior (and A B) C), apply the distributive law and then
6237 the inverse distributive law to see if things simplify. */
6239 if (GET_CODE (op0) == AND)
6241 rtx result = distribute_and_simplify_rtx (x, 0);
6246 if (GET_CODE (op1) == AND)
6248 rtx result = distribute_and_simplify_rtx (x, 1);
6261 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6262 operations" because they can be replaced with two more basic operations.
6263 ZERO_EXTEND is also considered "compound" because it can be replaced with
6264 an AND operation, which is simpler, though only one operation.
6266 The function expand_compound_operation is called with an rtx expression
6267 and will convert it to the appropriate shifts and AND operations,
6268 simplifying at each stage.
6270 The function make_compound_operation is called to convert an expression
6271 consisting of shifts and ANDs into the equivalent compound expression.
6272 It is the inverse of this function, loosely speaking. */
6275 expand_compound_operation (rtx x)
6277 unsigned HOST_WIDE_INT pos = 0, len;
6279 unsigned int modewidth;
6282 switch (GET_CODE (x))
6287 /* We can't necessarily use a const_int for a multiword mode;
6288 it depends on implicitly extending the value.
6289 Since we don't know the right way to extend it,
6290 we can't tell whether the implicit way is right.
6292 Even for a mode that is no wider than a const_int,
6293 we can't win, because we need to sign extend one of its bits through
6294 the rest of it, and we don't know which bit. */
6295 if (CONST_INT_P (XEXP (x, 0)))
6298 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6299 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6300 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6301 reloaded. If not for that, MEM's would very rarely be safe.
6303 Reject MODEs bigger than a word, because we might not be able
6304 to reference a two-register group starting with an arbitrary register
6305 (and currently gen_lowpart might crash for a SUBREG). */
6307 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6310 /* Reject MODEs that aren't scalar integers because turning vector
6311 or complex modes into shifts causes problems. */
6313 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6316 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6317 /* If the inner object has VOIDmode (the only way this can happen
6318 is if it is an ASM_OPERANDS), we can't do anything since we don't
6319 know how much masking to do. */
6328 /* ... fall through ... */
6331 /* If the operand is a CLOBBER, just return it. */
6332 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6335 if (!CONST_INT_P (XEXP (x, 1))
6336 || !CONST_INT_P (XEXP (x, 2))
6337 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6340 /* Reject MODEs that aren't scalar integers because turning vector
6341 or complex modes into shifts causes problems. */
6343 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6346 len = INTVAL (XEXP (x, 1));
6347 pos = INTVAL (XEXP (x, 2));
6349 /* This should stay within the object being extracted, fail otherwise. */
6350 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6353 if (BITS_BIG_ENDIAN)
6354 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6361 /* Convert sign extension to zero extension, if we know that the high
6362 bit is not set, as this is easier to optimize. It will be converted
6363 back to cheaper alternative in make_extraction. */
6364 if (GET_CODE (x) == SIGN_EXTEND
6365 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6366 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6367 & ~(((unsigned HOST_WIDE_INT)
6368 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6372 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6373 rtx temp2 = expand_compound_operation (temp);
6375 /* Make sure this is a profitable operation. */
6376 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6377 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6379 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6380 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6386 /* We can optimize some special cases of ZERO_EXTEND. */
6387 if (GET_CODE (x) == ZERO_EXTEND)
6389 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6390 know that the last value didn't have any inappropriate bits
6392 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6393 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6394 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6395 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6396 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6397 return XEXP (XEXP (x, 0), 0);
6399 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6400 if (GET_CODE (XEXP (x, 0)) == SUBREG
6401 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6402 && subreg_lowpart_p (XEXP (x, 0))
6403 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6404 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6405 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6406 return SUBREG_REG (XEXP (x, 0));
6408 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6409 is a comparison and STORE_FLAG_VALUE permits. This is like
6410 the first case, but it works even when GET_MODE (x) is larger
6411 than HOST_WIDE_INT. */
6412 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6413 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6414 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6415 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6416 <= HOST_BITS_PER_WIDE_INT)
6417 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6418 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6419 return XEXP (XEXP (x, 0), 0);
6421 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6422 if (GET_CODE (XEXP (x, 0)) == SUBREG
6423 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6424 && subreg_lowpart_p (XEXP (x, 0))
6425 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6426 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6427 <= HOST_BITS_PER_WIDE_INT)
6428 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6429 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6430 return SUBREG_REG (XEXP (x, 0));
6434 /* If we reach here, we want to return a pair of shifts. The inner
6435 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6436 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6437 logical depending on the value of UNSIGNEDP.
6439 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6440 converted into an AND of a shift.
6442 We must check for the case where the left shift would have a negative
6443 count. This can happen in a case like (x >> 31) & 255 on machines
6444 that can't shift by a constant. On those machines, we would first
6445 combine the shift with the AND to produce a variable-position
6446 extraction. Then the constant of 31 would be substituted in to produce
6447 a such a position. */
6449 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6450 if (modewidth + len >= pos)
6452 enum machine_mode mode = GET_MODE (x);
6453 tem = gen_lowpart (mode, XEXP (x, 0));
6454 if (!tem || GET_CODE (tem) == CLOBBER)
6456 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6457 tem, modewidth - pos - len);
6458 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6459 mode, tem, modewidth - len);
6461 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6462 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6463 simplify_shift_const (NULL_RTX, LSHIFTRT,
6466 ((HOST_WIDE_INT) 1 << len) - 1);
6468 /* Any other cases we can't handle. */
6471 /* If we couldn't do this for some reason, return the original
6473 if (GET_CODE (tem) == CLOBBER)
6479 /* X is a SET which contains an assignment of one object into
6480 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6481 or certain SUBREGS). If possible, convert it into a series of
6484 We half-heartedly support variable positions, but do not at all
6485 support variable lengths. */
6488 expand_field_assignment (const_rtx x)
6491 rtx pos; /* Always counts from low bit. */
6493 rtx mask, cleared, masked;
6494 enum machine_mode compute_mode;
6496 /* Loop until we find something we can't simplify. */
6499 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6500 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6502 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6503 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6504 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6506 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6507 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6509 inner = XEXP (SET_DEST (x), 0);
6510 len = INTVAL (XEXP (SET_DEST (x), 1));
6511 pos = XEXP (SET_DEST (x), 2);
6513 /* A constant position should stay within the width of INNER. */
6514 if (CONST_INT_P (pos)
6515 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6518 if (BITS_BIG_ENDIAN)
6520 if (CONST_INT_P (pos))
6521 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6523 else if (GET_CODE (pos) == MINUS
6524 && CONST_INT_P (XEXP (pos, 1))
6525 && (INTVAL (XEXP (pos, 1))
6526 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6527 /* If position is ADJUST - X, new position is X. */
6528 pos = XEXP (pos, 0);
6530 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6531 GEN_INT (GET_MODE_BITSIZE (
6538 /* A SUBREG between two modes that occupy the same numbers of words
6539 can be done by moving the SUBREG to the source. */
6540 else if (GET_CODE (SET_DEST (x)) == SUBREG
6541 /* We need SUBREGs to compute nonzero_bits properly. */
6542 && nonzero_sign_valid
6543 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6544 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6545 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6546 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6548 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6550 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6557 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6558 inner = SUBREG_REG (inner);
6560 compute_mode = GET_MODE (inner);
6562 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6563 if (! SCALAR_INT_MODE_P (compute_mode))
6565 enum machine_mode imode;
6567 /* Don't do anything for vector or complex integral types. */
6568 if (! FLOAT_MODE_P (compute_mode))
6571 /* Try to find an integral mode to pun with. */
6572 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6573 if (imode == BLKmode)
6576 compute_mode = imode;
6577 inner = gen_lowpart (imode, inner);
6580 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6581 if (len >= HOST_BITS_PER_WIDE_INT)
6584 /* Now compute the equivalent expression. Make a copy of INNER
6585 for the SET_DEST in case it is a MEM into which we will substitute;
6586 we don't want shared RTL in that case. */
6587 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6588 cleared = simplify_gen_binary (AND, compute_mode,
6589 simplify_gen_unary (NOT, compute_mode,
6590 simplify_gen_binary (ASHIFT,
6595 masked = simplify_gen_binary (ASHIFT, compute_mode,
6596 simplify_gen_binary (
6598 gen_lowpart (compute_mode, SET_SRC (x)),
6602 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6603 simplify_gen_binary (IOR, compute_mode,
6610 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6611 it is an RTX that represents a variable starting position; otherwise,
6612 POS is the (constant) starting bit position (counted from the LSB).
6614 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6617 IN_DEST is nonzero if this is a reference in the destination of a
6618 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6619 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6622 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6623 ZERO_EXTRACT should be built even for bits starting at bit 0.
6625 MODE is the desired mode of the result (if IN_DEST == 0).
6627 The result is an RTX for the extraction or NULL_RTX if the target
6631 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6632 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6633 int in_dest, int in_compare)
6635 /* This mode describes the size of the storage area
6636 to fetch the overall value from. Within that, we
6637 ignore the POS lowest bits, etc. */
6638 enum machine_mode is_mode = GET_MODE (inner);
6639 enum machine_mode inner_mode;
6640 enum machine_mode wanted_inner_mode;
6641 enum machine_mode wanted_inner_reg_mode = word_mode;
6642 enum machine_mode pos_mode = word_mode;
6643 enum machine_mode extraction_mode = word_mode;
6644 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6646 rtx orig_pos_rtx = pos_rtx;
6647 HOST_WIDE_INT orig_pos;
6649 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6651 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6652 consider just the QI as the memory to extract from.
6653 The subreg adds or removes high bits; its mode is
6654 irrelevant to the meaning of this extraction,
6655 since POS and LEN count from the lsb. */
6656 if (MEM_P (SUBREG_REG (inner)))
6657 is_mode = GET_MODE (SUBREG_REG (inner));
6658 inner = SUBREG_REG (inner);
6660 else if (GET_CODE (inner) == ASHIFT
6661 && CONST_INT_P (XEXP (inner, 1))
6662 && pos_rtx == 0 && pos == 0
6663 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6665 /* We're extracting the least significant bits of an rtx
6666 (ashift X (const_int C)), where LEN > C. Extract the
6667 least significant (LEN - C) bits of X, giving an rtx
6668 whose mode is MODE, then shift it left C times. */
6669 new_rtx = make_extraction (mode, XEXP (inner, 0),
6670 0, 0, len - INTVAL (XEXP (inner, 1)),
6671 unsignedp, in_dest, in_compare);
6673 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6676 inner_mode = GET_MODE (inner);
6678 if (pos_rtx && CONST_INT_P (pos_rtx))
6679 pos = INTVAL (pos_rtx), pos_rtx = 0;
6681 /* See if this can be done without an extraction. We never can if the
6682 width of the field is not the same as that of some integer mode. For
6683 registers, we can only avoid the extraction if the position is at the
6684 low-order bit and this is either not in the destination or we have the
6685 appropriate STRICT_LOW_PART operation available.
6687 For MEM, we can avoid an extract if the field starts on an appropriate
6688 boundary and we can change the mode of the memory reference. */
6690 if (tmode != BLKmode
6691 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6693 && (inner_mode == tmode
6695 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6696 GET_MODE_BITSIZE (inner_mode))
6697 || reg_truncated_to_mode (tmode, inner))
6700 && have_insn_for (STRICT_LOW_PART, tmode))))
6701 || (MEM_P (inner) && pos_rtx == 0
6703 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6704 : BITS_PER_UNIT)) == 0
6705 /* We can't do this if we are widening INNER_MODE (it
6706 may not be aligned, for one thing). */
6707 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6708 && (inner_mode == tmode
6709 || (! mode_dependent_address_p (XEXP (inner, 0))
6710 && ! MEM_VOLATILE_P (inner))))))
6712 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6713 field. If the original and current mode are the same, we need not
6714 adjust the offset. Otherwise, we do if bytes big endian.
6716 If INNER is not a MEM, get a piece consisting of just the field
6717 of interest (in this case POS % BITS_PER_WORD must be 0). */
6721 HOST_WIDE_INT offset;
6723 /* POS counts from lsb, but make OFFSET count in memory order. */
6724 if (BYTES_BIG_ENDIAN)
6725 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6727 offset = pos / BITS_PER_UNIT;
6729 new_rtx = adjust_address_nv (inner, tmode, offset);
6731 else if (REG_P (inner))
6733 if (tmode != inner_mode)
6735 /* We can't call gen_lowpart in a DEST since we
6736 always want a SUBREG (see below) and it would sometimes
6737 return a new hard register. */
6740 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6742 if (WORDS_BIG_ENDIAN
6743 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6744 final_word = ((GET_MODE_SIZE (inner_mode)
6745 - GET_MODE_SIZE (tmode))
6746 / UNITS_PER_WORD) - final_word;
6748 final_word *= UNITS_PER_WORD;
6749 if (BYTES_BIG_ENDIAN &&
6750 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6751 final_word += (GET_MODE_SIZE (inner_mode)
6752 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6754 /* Avoid creating invalid subregs, for example when
6755 simplifying (x>>32)&255. */
6756 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6759 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6762 new_rtx = gen_lowpart (tmode, inner);
6768 new_rtx = force_to_mode (inner, tmode,
6769 len >= HOST_BITS_PER_WIDE_INT
6770 ? ~(unsigned HOST_WIDE_INT) 0
6771 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6774 /* If this extraction is going into the destination of a SET,
6775 make a STRICT_LOW_PART unless we made a MEM. */
6778 return (MEM_P (new_rtx) ? new_rtx
6779 : (GET_CODE (new_rtx) != SUBREG
6780 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6781 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6786 if (CONST_INT_P (new_rtx))
6787 return gen_int_mode (INTVAL (new_rtx), mode);
6789 /* If we know that no extraneous bits are set, and that the high
6790 bit is not set, convert the extraction to the cheaper of
6791 sign and zero extension, that are equivalent in these cases. */
6792 if (flag_expensive_optimizations
6793 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6794 && ((nonzero_bits (new_rtx, tmode)
6795 & ~(((unsigned HOST_WIDE_INT)
6796 GET_MODE_MASK (tmode))
6800 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6801 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6803 /* Prefer ZERO_EXTENSION, since it gives more information to
6805 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6806 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6811 /* Otherwise, sign- or zero-extend unless we already are in the
6814 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6818 /* Unless this is a COMPARE or we have a funny memory reference,
6819 don't do anything with zero-extending field extracts starting at
6820 the low-order bit since they are simple AND operations. */
6821 if (pos_rtx == 0 && pos == 0 && ! in_dest
6822 && ! in_compare && unsignedp)
6825 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6826 if the position is not a constant and the length is not 1. In all
6827 other cases, we would only be going outside our object in cases when
6828 an original shift would have been undefined. */
6830 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6831 || (pos_rtx != 0 && len != 1)))
6834 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6835 and the mode for the result. */
6836 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6838 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6839 pos_mode = mode_for_extraction (EP_insv, 2);
6840 extraction_mode = mode_for_extraction (EP_insv, 3);
6843 if (! in_dest && unsignedp
6844 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6846 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6847 pos_mode = mode_for_extraction (EP_extzv, 3);
6848 extraction_mode = mode_for_extraction (EP_extzv, 0);
6851 if (! in_dest && ! unsignedp
6852 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6854 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6855 pos_mode = mode_for_extraction (EP_extv, 3);
6856 extraction_mode = mode_for_extraction (EP_extv, 0);
6859 /* Never narrow an object, since that might not be safe. */
6861 if (mode != VOIDmode
6862 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6863 extraction_mode = mode;
6865 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6866 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6867 pos_mode = GET_MODE (pos_rtx);
6869 /* If this is not from memory, the desired mode is the preferred mode
6870 for an extraction pattern's first input operand, or word_mode if there
6873 wanted_inner_mode = wanted_inner_reg_mode;
6876 /* Be careful not to go beyond the extracted object and maintain the
6877 natural alignment of the memory. */
6878 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6879 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6880 > GET_MODE_BITSIZE (wanted_inner_mode))
6882 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6883 gcc_assert (wanted_inner_mode != VOIDmode);
6886 /* If we have to change the mode of memory and cannot, the desired mode
6887 is EXTRACTION_MODE. */
6888 if (inner_mode != wanted_inner_mode
6889 && (mode_dependent_address_p (XEXP (inner, 0))
6890 || MEM_VOLATILE_P (inner)
6892 wanted_inner_mode = extraction_mode;
6897 if (BITS_BIG_ENDIAN)
6899 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6900 BITS_BIG_ENDIAN style. If position is constant, compute new
6901 position. Otherwise, build subtraction.
6902 Note that POS is relative to the mode of the original argument.
6903 If it's a MEM we need to recompute POS relative to that.
6904 However, if we're extracting from (or inserting into) a register,
6905 we want to recompute POS relative to wanted_inner_mode. */
6906 int width = (MEM_P (inner)
6907 ? GET_MODE_BITSIZE (is_mode)
6908 : GET_MODE_BITSIZE (wanted_inner_mode));
6911 pos = width - len - pos;
6914 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6915 /* POS may be less than 0 now, but we check for that below.
6916 Note that it can only be less than 0 if !MEM_P (inner). */
6919 /* If INNER has a wider mode, and this is a constant extraction, try to
6920 make it smaller and adjust the byte to point to the byte containing
6922 if (wanted_inner_mode != VOIDmode
6923 && inner_mode != wanted_inner_mode
6925 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6927 && ! mode_dependent_address_p (XEXP (inner, 0))
6928 && ! MEM_VOLATILE_P (inner))
6932 /* The computations below will be correct if the machine is big
6933 endian in both bits and bytes or little endian in bits and bytes.
6934 If it is mixed, we must adjust. */
6936 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6937 adjust OFFSET to compensate. */
6938 if (BYTES_BIG_ENDIAN
6939 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6940 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6942 /* We can now move to the desired byte. */
6943 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6944 * GET_MODE_SIZE (wanted_inner_mode);
6945 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6947 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6948 && is_mode != wanted_inner_mode)
6949 offset = (GET_MODE_SIZE (is_mode)
6950 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6952 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6955 /* If INNER is not memory, get it into the proper mode. If we are changing
6956 its mode, POS must be a constant and smaller than the size of the new
6958 else if (!MEM_P (inner))
6960 /* On the LHS, don't create paradoxical subregs implicitely truncating
6961 the register unless TRULY_NOOP_TRUNCATION. */
6963 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
6964 GET_MODE_BITSIZE (wanted_inner_mode)))
6967 if (GET_MODE (inner) != wanted_inner_mode
6969 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6975 inner = force_to_mode (inner, wanted_inner_mode,
6977 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6978 ? ~(unsigned HOST_WIDE_INT) 0
6979 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6984 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6985 have to zero extend. Otherwise, we can just use a SUBREG. */
6987 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6989 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6991 /* If we know that no extraneous bits are set, and that the high
6992 bit is not set, convert extraction to cheaper one - either
6993 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6995 if (flag_expensive_optimizations
6996 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6997 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6998 & ~(((unsigned HOST_WIDE_INT)
6999 GET_MODE_MASK (GET_MODE (pos_rtx)))
7003 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7005 /* Prefer ZERO_EXTENSION, since it gives more information to
7007 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7008 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7013 else if (pos_rtx != 0
7014 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7015 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7017 /* Make POS_RTX unless we already have it and it is correct. If we don't
7018 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7020 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7021 pos_rtx = orig_pos_rtx;
7023 else if (pos_rtx == 0)
7024 pos_rtx = GEN_INT (pos);
7026 /* Make the required operation. See if we can use existing rtx. */
7027 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7028 extraction_mode, inner, GEN_INT (len), pos_rtx);
7030 new_rtx = gen_lowpart (mode, new_rtx);
7035 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7036 with any other operations in X. Return X without that shift if so. */
7039 extract_left_shift (rtx x, int count)
7041 enum rtx_code code = GET_CODE (x);
7042 enum machine_mode mode = GET_MODE (x);
7048 /* This is the shift itself. If it is wide enough, we will return
7049 either the value being shifted if the shift count is equal to
7050 COUNT or a shift for the difference. */
7051 if (CONST_INT_P (XEXP (x, 1))
7052 && INTVAL (XEXP (x, 1)) >= count)
7053 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7054 INTVAL (XEXP (x, 1)) - count);
7058 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7059 return simplify_gen_unary (code, mode, tem, mode);
7063 case PLUS: case IOR: case XOR: case AND:
7064 /* If we can safely shift this constant and we find the inner shift,
7065 make a new operation. */
7066 if (CONST_INT_P (XEXP (x, 1))
7067 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
7068 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7069 return simplify_gen_binary (code, mode, tem,
7070 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7081 /* Look at the expression rooted at X. Look for expressions
7082 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7083 Form these expressions.
7085 Return the new rtx, usually just X.
7087 Also, for machines like the VAX that don't have logical shift insns,
7088 try to convert logical to arithmetic shift operations in cases where
7089 they are equivalent. This undoes the canonicalizations to logical
7090 shifts done elsewhere.
7092 We try, as much as possible, to re-use rtl expressions to save memory.
7094 IN_CODE says what kind of expression we are processing. Normally, it is
7095 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7096 being kludges), it is MEM. When processing the arguments of a comparison
7097 or a COMPARE against zero, it is COMPARE. */
7100 make_compound_operation (rtx x, enum rtx_code in_code)
7102 enum rtx_code code = GET_CODE (x);
7103 enum machine_mode mode = GET_MODE (x);
7104 int mode_width = GET_MODE_BITSIZE (mode);
7106 enum rtx_code next_code;
7112 /* Select the code to be used in recursive calls. Once we are inside an
7113 address, we stay there. If we have a comparison, set to COMPARE,
7114 but once inside, go back to our default of SET. */
7116 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
7117 : ((code == COMPARE || COMPARISON_P (x))
7118 && XEXP (x, 1) == const0_rtx) ? COMPARE
7119 : in_code == COMPARE ? SET : in_code);
7121 /* Process depending on the code of this operation. If NEW is set
7122 nonzero, it will be returned. */
7127 /* Convert shifts by constants into multiplications if inside
7129 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7130 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7131 && INTVAL (XEXP (x, 1)) >= 0)
7133 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7134 new_rtx = gen_rtx_MULT (mode, new_rtx,
7135 GEN_INT ((HOST_WIDE_INT) 1
7136 << INTVAL (XEXP (x, 1))));
7141 /* If the second operand is not a constant, we can't do anything
7143 if (!CONST_INT_P (XEXP (x, 1)))
7146 /* If the constant is a power of two minus one and the first operand
7147 is a logical right shift, make an extraction. */
7148 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7149 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7151 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7152 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7153 0, in_code == COMPARE);
7156 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7157 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7158 && subreg_lowpart_p (XEXP (x, 0))
7159 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7160 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7162 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7164 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7165 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7166 0, in_code == COMPARE);
7168 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7169 else if ((GET_CODE (XEXP (x, 0)) == XOR
7170 || GET_CODE (XEXP (x, 0)) == IOR)
7171 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7172 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7173 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7175 /* Apply the distributive law, and then try to make extractions. */
7176 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7177 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7179 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7181 new_rtx = make_compound_operation (new_rtx, in_code);
7184 /* If we are have (and (rotate X C) M) and C is larger than the number
7185 of bits in M, this is an extraction. */
7187 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7188 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7189 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
7190 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7192 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7193 new_rtx = make_extraction (mode, new_rtx,
7194 (GET_MODE_BITSIZE (mode)
7195 - INTVAL (XEXP (XEXP (x, 0), 1))),
7196 NULL_RTX, i, 1, 0, in_code == COMPARE);
7199 /* On machines without logical shifts, if the operand of the AND is
7200 a logical shift and our mask turns off all the propagated sign
7201 bits, we can replace the logical shift with an arithmetic shift. */
7202 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7203 && !have_insn_for (LSHIFTRT, mode)
7204 && have_insn_for (ASHIFTRT, mode)
7205 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7206 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7207 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7208 && mode_width <= HOST_BITS_PER_WIDE_INT)
7210 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7212 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7213 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7215 gen_rtx_ASHIFTRT (mode,
7216 make_compound_operation
7217 (XEXP (XEXP (x, 0), 0), next_code),
7218 XEXP (XEXP (x, 0), 1)));
7221 /* If the constant is one less than a power of two, this might be
7222 representable by an extraction even if no shift is present.
7223 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7224 we are in a COMPARE. */
7225 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
7226 new_rtx = make_extraction (mode,
7227 make_compound_operation (XEXP (x, 0),
7229 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7231 /* If we are in a comparison and this is an AND with a power of two,
7232 convert this into the appropriate bit extract. */
7233 else if (in_code == COMPARE
7234 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
7235 new_rtx = make_extraction (mode,
7236 make_compound_operation (XEXP (x, 0),
7238 i, NULL_RTX, 1, 1, 0, 1);
7243 /* If the sign bit is known to be zero, replace this with an
7244 arithmetic shift. */
7245 if (have_insn_for (ASHIFTRT, mode)
7246 && ! have_insn_for (LSHIFTRT, mode)
7247 && mode_width <= HOST_BITS_PER_WIDE_INT
7248 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7250 new_rtx = gen_rtx_ASHIFTRT (mode,
7251 make_compound_operation (XEXP (x, 0),
7257 /* ... fall through ... */
7263 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7264 this is a SIGN_EXTRACT. */
7265 if (CONST_INT_P (rhs)
7266 && GET_CODE (lhs) == ASHIFT
7267 && CONST_INT_P (XEXP (lhs, 1))
7268 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7269 && INTVAL (rhs) < mode_width)
7271 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7272 new_rtx = make_extraction (mode, new_rtx,
7273 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7274 NULL_RTX, mode_width - INTVAL (rhs),
7275 code == LSHIFTRT, 0, in_code == COMPARE);
7279 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7280 If so, try to merge the shifts into a SIGN_EXTEND. We could
7281 also do this for some cases of SIGN_EXTRACT, but it doesn't
7282 seem worth the effort; the case checked for occurs on Alpha. */
7285 && ! (GET_CODE (lhs) == SUBREG
7286 && (OBJECT_P (SUBREG_REG (lhs))))
7287 && CONST_INT_P (rhs)
7288 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7289 && INTVAL (rhs) < mode_width
7290 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7291 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7292 0, NULL_RTX, mode_width - INTVAL (rhs),
7293 code == LSHIFTRT, 0, in_code == COMPARE);
7298 /* Call ourselves recursively on the inner expression. If we are
7299 narrowing the object and it has a different RTL code from
7300 what it originally did, do this SUBREG as a force_to_mode. */
7302 tem = make_compound_operation (SUBREG_REG (x), in_code);
7306 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7312 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7313 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7314 && subreg_lowpart_p (x))
7316 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7319 /* If we have something other than a SUBREG, we might have
7320 done an expansion, so rerun ourselves. */
7321 if (GET_CODE (newer) != SUBREG)
7322 newer = make_compound_operation (newer, in_code);
7324 /* force_to_mode can expand compounds. If it just re-expanded the
7325 compound use gen_lowpart instead to convert to the desired
7327 if (rtx_equal_p (newer, x))
7328 return gen_lowpart (GET_MODE (x), tem);
7344 x = gen_lowpart (mode, new_rtx);
7345 code = GET_CODE (x);
7348 /* Now recursively process each operand of this operation. */
7349 fmt = GET_RTX_FORMAT (code);
7350 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7353 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7354 SUBST (XEXP (x, i), new_rtx);
7356 else if (fmt[i] == 'E')
7357 for (j = 0; j < XVECLEN (x, i); j++)
7359 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7360 SUBST (XVECEXP (x, i, j), new_rtx);
7363 /* If this is a commutative operation, the changes to the operands
7364 may have made it noncanonical. */
7365 if (COMMUTATIVE_ARITH_P (x)
7366 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7369 SUBST (XEXP (x, 0), XEXP (x, 1));
7370 SUBST (XEXP (x, 1), tem);
7376 /* Given M see if it is a value that would select a field of bits
7377 within an item, but not the entire word. Return -1 if not.
7378 Otherwise, return the starting position of the field, where 0 is the
7381 *PLEN is set to the length of the field. */
7384 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7386 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7387 int pos = exact_log2 (m & -m);
7391 /* Now shift off the low-order zero bits and see if we have a
7392 power of two minus 1. */
7393 len = exact_log2 ((m >> pos) + 1);
7402 /* If X refers to a register that equals REG in value, replace these
7403 references with REG. */
7405 canon_reg_for_combine (rtx x, rtx reg)
7412 enum rtx_code code = GET_CODE (x);
7413 switch (GET_RTX_CLASS (code))
7416 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7417 if (op0 != XEXP (x, 0))
7418 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7423 case RTX_COMM_ARITH:
7424 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7425 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7426 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7427 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7431 case RTX_COMM_COMPARE:
7432 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7433 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7434 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7435 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7436 GET_MODE (op0), op0, op1);
7440 case RTX_BITFIELD_OPS:
7441 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7442 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7443 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7444 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7445 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7446 GET_MODE (op0), op0, op1, op2);
7451 if (rtx_equal_p (get_last_value (reg), x)
7452 || rtx_equal_p (reg, get_last_value (x)))
7461 fmt = GET_RTX_FORMAT (code);
7463 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7466 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7467 if (op != XEXP (x, i))
7477 else if (fmt[i] == 'E')
7480 for (j = 0; j < XVECLEN (x, i); j++)
7482 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7483 if (op != XVECEXP (x, i, j))
7490 XVECEXP (x, i, j) = op;
7501 /* Return X converted to MODE. If the value is already truncated to
7502 MODE we can just return a subreg even though in the general case we
7503 would need an explicit truncation. */
7506 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7508 if (!CONST_INT_P (x)
7509 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7510 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7511 GET_MODE_BITSIZE (GET_MODE (x)))
7512 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7514 /* Bit-cast X into an integer mode. */
7515 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7516 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7517 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
7521 return gen_lowpart (mode, x);
7524 /* See if X can be simplified knowing that we will only refer to it in
7525 MODE and will only refer to those bits that are nonzero in MASK.
7526 If other bits are being computed or if masking operations are done
7527 that select a superset of the bits in MASK, they can sometimes be
7530 Return a possibly simplified expression, but always convert X to
7531 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7533 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7534 are all off in X. This is used when X will be complemented, by either
7535 NOT, NEG, or XOR. */
7538 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7541 enum rtx_code code = GET_CODE (x);
7542 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7543 enum machine_mode op_mode;
7544 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7547 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7548 code below will do the wrong thing since the mode of such an
7549 expression is VOIDmode.
7551 Also do nothing if X is a CLOBBER; this can happen if X was
7552 the return value from a call to gen_lowpart. */
7553 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7556 /* We want to perform the operation is its present mode unless we know
7557 that the operation is valid in MODE, in which case we do the operation
7559 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7560 && have_insn_for (code, mode))
7561 ? mode : GET_MODE (x));
7563 /* It is not valid to do a right-shift in a narrower mode
7564 than the one it came in with. */
7565 if ((code == LSHIFTRT || code == ASHIFTRT)
7566 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7567 op_mode = GET_MODE (x);
7569 /* Truncate MASK to fit OP_MODE. */
7571 mask &= GET_MODE_MASK (op_mode);
7573 /* When we have an arithmetic operation, or a shift whose count we
7574 do not know, we need to assume that all bits up to the highest-order
7575 bit in MASK will be needed. This is how we form such a mask. */
7576 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7577 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7579 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7582 /* Determine what bits of X are guaranteed to be (non)zero. */
7583 nonzero = nonzero_bits (x, mode);
7585 /* If none of the bits in X are needed, return a zero. */
7586 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7589 /* If X is a CONST_INT, return a new one. Do this here since the
7590 test below will fail. */
7591 if (CONST_INT_P (x))
7593 if (SCALAR_INT_MODE_P (mode))
7594 return gen_int_mode (INTVAL (x) & mask, mode);
7597 x = GEN_INT (INTVAL (x) & mask);
7598 return gen_lowpart_common (mode, x);
7602 /* If X is narrower than MODE and we want all the bits in X's mode, just
7603 get X in the proper mode. */
7604 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7605 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7606 return gen_lowpart (mode, x);
7608 /* We can ignore the effect of a SUBREG if it narrows the mode or
7609 if the constant masks to zero all the bits the mode doesn't have. */
7610 if (GET_CODE (x) == SUBREG
7611 && subreg_lowpart_p (x)
7612 && ((GET_MODE_SIZE (GET_MODE (x))
7613 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7615 & GET_MODE_MASK (GET_MODE (x))
7616 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7617 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7619 /* The arithmetic simplifications here only work for scalar integer modes. */
7620 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
7621 return gen_lowpart_or_truncate (mode, x);
7626 /* If X is a (clobber (const_int)), return it since we know we are
7627 generating something that won't match. */
7634 x = expand_compound_operation (x);
7635 if (GET_CODE (x) != code)
7636 return force_to_mode (x, mode, mask, next_select);
7640 /* Similarly for a truncate. */
7641 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7644 /* If this is an AND with a constant, convert it into an AND
7645 whose constant is the AND of that constant with MASK. If it
7646 remains an AND of MASK, delete it since it is redundant. */
7648 if (CONST_INT_P (XEXP (x, 1)))
7650 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7651 mask & INTVAL (XEXP (x, 1)));
7653 /* If X is still an AND, see if it is an AND with a mask that
7654 is just some low-order bits. If so, and it is MASK, we don't
7657 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7658 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7662 /* If it remains an AND, try making another AND with the bits
7663 in the mode mask that aren't in MASK turned on. If the
7664 constant in the AND is wide enough, this might make a
7665 cheaper constant. */
7667 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7668 && GET_MODE_MASK (GET_MODE (x)) != mask
7669 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7671 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7672 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7673 int width = GET_MODE_BITSIZE (GET_MODE (x));
7676 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7677 number, sign extend it. */
7678 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7679 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7680 cval |= (HOST_WIDE_INT) -1 << width;
7682 y = simplify_gen_binary (AND, GET_MODE (x),
7683 XEXP (x, 0), GEN_INT (cval));
7684 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7685 < rtx_cost (x, SET, optimize_this_for_speed_p))
7695 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7696 low-order bits (as in an alignment operation) and FOO is already
7697 aligned to that boundary, mask C1 to that boundary as well.
7698 This may eliminate that PLUS and, later, the AND. */
7701 unsigned int width = GET_MODE_BITSIZE (mode);
7702 unsigned HOST_WIDE_INT smask = mask;
7704 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7705 number, sign extend it. */
7707 if (width < HOST_BITS_PER_WIDE_INT
7708 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7709 smask |= (HOST_WIDE_INT) -1 << width;
7711 if (CONST_INT_P (XEXP (x, 1))
7712 && exact_log2 (- smask) >= 0
7713 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7714 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7715 return force_to_mode (plus_constant (XEXP (x, 0),
7716 (INTVAL (XEXP (x, 1)) & smask)),
7717 mode, smask, next_select);
7720 /* ... fall through ... */
7723 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7724 most significant bit in MASK since carries from those bits will
7725 affect the bits we are interested in. */
7730 /* If X is (minus C Y) where C's least set bit is larger than any bit
7731 in the mask, then we may replace with (neg Y). */
7732 if (CONST_INT_P (XEXP (x, 0))
7733 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7734 & -INTVAL (XEXP (x, 0))))
7737 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7739 return force_to_mode (x, mode, mask, next_select);
7742 /* Similarly, if C contains every bit in the fuller_mask, then we may
7743 replace with (not Y). */
7744 if (CONST_INT_P (XEXP (x, 0))
7745 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7746 == INTVAL (XEXP (x, 0))))
7748 x = simplify_gen_unary (NOT, GET_MODE (x),
7749 XEXP (x, 1), GET_MODE (x));
7750 return force_to_mode (x, mode, mask, next_select);
7758 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7759 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7760 operation which may be a bitfield extraction. Ensure that the
7761 constant we form is not wider than the mode of X. */
7763 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7764 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7765 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7766 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7767 && CONST_INT_P (XEXP (x, 1))
7768 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7769 + floor_log2 (INTVAL (XEXP (x, 1))))
7770 < GET_MODE_BITSIZE (GET_MODE (x)))
7771 && (INTVAL (XEXP (x, 1))
7772 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7774 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7775 << INTVAL (XEXP (XEXP (x, 0), 1)));
7776 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7777 XEXP (XEXP (x, 0), 0), temp);
7778 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7779 XEXP (XEXP (x, 0), 1));
7780 return force_to_mode (x, mode, mask, next_select);
7784 /* For most binary operations, just propagate into the operation and
7785 change the mode if we have an operation of that mode. */
7787 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
7788 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
7790 /* If we ended up truncating both operands, truncate the result of the
7791 operation instead. */
7792 if (GET_CODE (op0) == TRUNCATE
7793 && GET_CODE (op1) == TRUNCATE)
7795 op0 = XEXP (op0, 0);
7796 op1 = XEXP (op1, 0);
7799 op0 = gen_lowpart_or_truncate (op_mode, op0);
7800 op1 = gen_lowpart_or_truncate (op_mode, op1);
7802 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7803 x = simplify_gen_binary (code, op_mode, op0, op1);
7807 /* For left shifts, do the same, but just for the first operand.
7808 However, we cannot do anything with shifts where we cannot
7809 guarantee that the counts are smaller than the size of the mode
7810 because such a count will have a different meaning in a
7813 if (! (CONST_INT_P (XEXP (x, 1))
7814 && INTVAL (XEXP (x, 1)) >= 0
7815 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7816 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7817 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7818 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7821 /* If the shift count is a constant and we can do arithmetic in
7822 the mode of the shift, refine which bits we need. Otherwise, use the
7823 conservative form of the mask. */
7824 if (CONST_INT_P (XEXP (x, 1))
7825 && INTVAL (XEXP (x, 1)) >= 0
7826 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7827 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7828 mask >>= INTVAL (XEXP (x, 1));
7832 op0 = gen_lowpart_or_truncate (op_mode,
7833 force_to_mode (XEXP (x, 0), op_mode,
7834 mask, next_select));
7836 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7837 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7841 /* Here we can only do something if the shift count is a constant,
7842 this shift constant is valid for the host, and we can do arithmetic
7845 if (CONST_INT_P (XEXP (x, 1))
7846 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7847 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7849 rtx inner = XEXP (x, 0);
7850 unsigned HOST_WIDE_INT inner_mask;
7852 /* Select the mask of the bits we need for the shift operand. */
7853 inner_mask = mask << INTVAL (XEXP (x, 1));
7855 /* We can only change the mode of the shift if we can do arithmetic
7856 in the mode of the shift and INNER_MASK is no wider than the
7857 width of X's mode. */
7858 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7859 op_mode = GET_MODE (x);
7861 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7863 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7864 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7867 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7868 shift and AND produces only copies of the sign bit (C2 is one less
7869 than a power of two), we can do this with just a shift. */
7871 if (GET_CODE (x) == LSHIFTRT
7872 && CONST_INT_P (XEXP (x, 1))
7873 /* The shift puts one of the sign bit copies in the least significant
7875 && ((INTVAL (XEXP (x, 1))
7876 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7877 >= GET_MODE_BITSIZE (GET_MODE (x)))
7878 && exact_log2 (mask + 1) >= 0
7879 /* Number of bits left after the shift must be more than the mask
7881 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7882 <= GET_MODE_BITSIZE (GET_MODE (x)))
7883 /* Must be more sign bit copies than the mask needs. */
7884 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7885 >= exact_log2 (mask + 1)))
7886 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7887 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7888 - exact_log2 (mask + 1)));
7893 /* If we are just looking for the sign bit, we don't need this shift at
7894 all, even if it has a variable count. */
7895 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7896 && (mask == ((unsigned HOST_WIDE_INT) 1
7897 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7898 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7900 /* If this is a shift by a constant, get a mask that contains those bits
7901 that are not copies of the sign bit. We then have two cases: If
7902 MASK only includes those bits, this can be a logical shift, which may
7903 allow simplifications. If MASK is a single-bit field not within
7904 those bits, we are requesting a copy of the sign bit and hence can
7905 shift the sign bit to the appropriate location. */
7907 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7908 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7912 /* If the considered data is wider than HOST_WIDE_INT, we can't
7913 represent a mask for all its bits in a single scalar.
7914 But we only care about the lower bits, so calculate these. */
7916 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7918 nonzero = ~(HOST_WIDE_INT) 0;
7920 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7921 is the number of bits a full-width mask would have set.
7922 We need only shift if these are fewer than nonzero can
7923 hold. If not, we must keep all bits set in nonzero. */
7925 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7926 < HOST_BITS_PER_WIDE_INT)
7927 nonzero >>= INTVAL (XEXP (x, 1))
7928 + HOST_BITS_PER_WIDE_INT
7929 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7933 nonzero = GET_MODE_MASK (GET_MODE (x));
7934 nonzero >>= INTVAL (XEXP (x, 1));
7937 if ((mask & ~nonzero) == 0)
7939 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7940 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7941 if (GET_CODE (x) != ASHIFTRT)
7942 return force_to_mode (x, mode, mask, next_select);
7945 else if ((i = exact_log2 (mask)) >= 0)
7947 x = simplify_shift_const
7948 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7949 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7951 if (GET_CODE (x) != ASHIFTRT)
7952 return force_to_mode (x, mode, mask, next_select);
7956 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7957 even if the shift count isn't a constant. */
7959 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7960 XEXP (x, 0), XEXP (x, 1));
7964 /* If this is a zero- or sign-extension operation that just affects bits
7965 we don't care about, remove it. Be sure the call above returned
7966 something that is still a shift. */
7968 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7969 && CONST_INT_P (XEXP (x, 1))
7970 && INTVAL (XEXP (x, 1)) >= 0
7971 && (INTVAL (XEXP (x, 1))
7972 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7973 && GET_CODE (XEXP (x, 0)) == ASHIFT
7974 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7975 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7982 /* If the shift count is constant and we can do computations
7983 in the mode of X, compute where the bits we care about are.
7984 Otherwise, we can't do anything. Don't change the mode of
7985 the shift or propagate MODE into the shift, though. */
7986 if (CONST_INT_P (XEXP (x, 1))
7987 && INTVAL (XEXP (x, 1)) >= 0)
7989 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7990 GET_MODE (x), GEN_INT (mask),
7992 if (temp && CONST_INT_P (temp))
7994 force_to_mode (XEXP (x, 0), GET_MODE (x),
7995 INTVAL (temp), next_select));
8000 /* If we just want the low-order bit, the NEG isn't needed since it
8001 won't change the low-order bit. */
8003 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8005 /* We need any bits less significant than the most significant bit in
8006 MASK since carries from those bits will affect the bits we are
8012 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8013 same as the XOR case above. Ensure that the constant we form is not
8014 wider than the mode of X. */
8016 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8017 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8018 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8019 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8020 < GET_MODE_BITSIZE (GET_MODE (x)))
8021 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8023 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8025 temp = simplify_gen_binary (XOR, GET_MODE (x),
8026 XEXP (XEXP (x, 0), 0), temp);
8027 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8028 temp, XEXP (XEXP (x, 0), 1));
8030 return force_to_mode (x, mode, mask, next_select);
8033 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8034 use the full mask inside the NOT. */
8038 op0 = gen_lowpart_or_truncate (op_mode,
8039 force_to_mode (XEXP (x, 0), mode, mask,
8041 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8042 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8046 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8047 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8048 which is equal to STORE_FLAG_VALUE. */
8049 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
8050 && GET_MODE (XEXP (x, 0)) == mode
8051 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8052 && (nonzero_bits (XEXP (x, 0), mode)
8053 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8054 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8059 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8060 written in a narrower mode. We play it safe and do not do so. */
8063 gen_lowpart_or_truncate (GET_MODE (x),
8064 force_to_mode (XEXP (x, 1), mode,
8065 mask, next_select)));
8067 gen_lowpart_or_truncate (GET_MODE (x),
8068 force_to_mode (XEXP (x, 2), mode,
8069 mask, next_select)));
8076 /* Ensure we return a value of the proper mode. */
8077 return gen_lowpart_or_truncate (mode, x);
8080 /* Return nonzero if X is an expression that has one of two values depending on
8081 whether some other value is zero or nonzero. In that case, we return the
8082 value that is being tested, *PTRUE is set to the value if the rtx being
8083 returned has a nonzero value, and *PFALSE is set to the other alternative.
8085 If we return zero, we set *PTRUE and *PFALSE to X. */
8088 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8090 enum machine_mode mode = GET_MODE (x);
8091 enum rtx_code code = GET_CODE (x);
8092 rtx cond0, cond1, true0, true1, false0, false1;
8093 unsigned HOST_WIDE_INT nz;
8095 /* If we are comparing a value against zero, we are done. */
8096 if ((code == NE || code == EQ)
8097 && XEXP (x, 1) == const0_rtx)
8099 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8100 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8104 /* If this is a unary operation whose operand has one of two values, apply
8105 our opcode to compute those values. */
8106 else if (UNARY_P (x)
8107 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8109 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8110 *pfalse = simplify_gen_unary (code, mode, false0,
8111 GET_MODE (XEXP (x, 0)));
8115 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8116 make can't possibly match and would suppress other optimizations. */
8117 else if (code == COMPARE)
8120 /* If this is a binary operation, see if either side has only one of two
8121 values. If either one does or if both do and they are conditional on
8122 the same value, compute the new true and false values. */
8123 else if (BINARY_P (x))
8125 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8126 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8128 if ((cond0 != 0 || cond1 != 0)
8129 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8131 /* If if_then_else_cond returned zero, then true/false are the
8132 same rtl. We must copy one of them to prevent invalid rtl
8135 true0 = copy_rtx (true0);
8136 else if (cond1 == 0)
8137 true1 = copy_rtx (true1);
8139 if (COMPARISON_P (x))
8141 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8143 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8148 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8149 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8152 return cond0 ? cond0 : cond1;
8155 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8156 operands is zero when the other is nonzero, and vice-versa,
8157 and STORE_FLAG_VALUE is 1 or -1. */
8159 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8160 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8162 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8164 rtx op0 = XEXP (XEXP (x, 0), 1);
8165 rtx op1 = XEXP (XEXP (x, 1), 1);
8167 cond0 = XEXP (XEXP (x, 0), 0);
8168 cond1 = XEXP (XEXP (x, 1), 0);
8170 if (COMPARISON_P (cond0)
8171 && COMPARISON_P (cond1)
8172 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8173 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8174 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8175 || ((swap_condition (GET_CODE (cond0))
8176 == reversed_comparison_code (cond1, NULL))
8177 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8178 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8179 && ! side_effects_p (x))
8181 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8182 *pfalse = simplify_gen_binary (MULT, mode,
8184 ? simplify_gen_unary (NEG, mode,
8192 /* Similarly for MULT, AND and UMIN, except that for these the result
8194 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8195 && (code == MULT || code == AND || code == UMIN)
8196 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8198 cond0 = XEXP (XEXP (x, 0), 0);
8199 cond1 = XEXP (XEXP (x, 1), 0);
8201 if (COMPARISON_P (cond0)
8202 && COMPARISON_P (cond1)
8203 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8204 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8205 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8206 || ((swap_condition (GET_CODE (cond0))
8207 == reversed_comparison_code (cond1, NULL))
8208 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8209 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8210 && ! side_effects_p (x))
8212 *ptrue = *pfalse = const0_rtx;
8218 else if (code == IF_THEN_ELSE)
8220 /* If we have IF_THEN_ELSE already, extract the condition and
8221 canonicalize it if it is NE or EQ. */
8222 cond0 = XEXP (x, 0);
8223 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8224 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8225 return XEXP (cond0, 0);
8226 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8228 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8229 return XEXP (cond0, 0);
8235 /* If X is a SUBREG, we can narrow both the true and false values
8236 if the inner expression, if there is a condition. */
8237 else if (code == SUBREG
8238 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8241 true0 = simplify_gen_subreg (mode, true0,
8242 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8243 false0 = simplify_gen_subreg (mode, false0,
8244 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8245 if (true0 && false0)
8253 /* If X is a constant, this isn't special and will cause confusions
8254 if we treat it as such. Likewise if it is equivalent to a constant. */
8255 else if (CONSTANT_P (x)
8256 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8259 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8260 will be least confusing to the rest of the compiler. */
8261 else if (mode == BImode)
8263 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8267 /* If X is known to be either 0 or -1, those are the true and
8268 false values when testing X. */
8269 else if (x == constm1_rtx || x == const0_rtx
8270 || (mode != VOIDmode
8271 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8273 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8277 /* Likewise for 0 or a single bit. */
8278 else if (SCALAR_INT_MODE_P (mode)
8279 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8280 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8282 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8286 /* Otherwise fail; show no condition with true and false values the same. */
8287 *ptrue = *pfalse = x;
8291 /* Return the value of expression X given the fact that condition COND
8292 is known to be true when applied to REG as its first operand and VAL
8293 as its second. X is known to not be shared and so can be modified in
8296 We only handle the simplest cases, and specifically those cases that
8297 arise with IF_THEN_ELSE expressions. */
8300 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8302 enum rtx_code code = GET_CODE (x);
8307 if (side_effects_p (x))
8310 /* If either operand of the condition is a floating point value,
8311 then we have to avoid collapsing an EQ comparison. */
8313 && rtx_equal_p (x, reg)
8314 && ! FLOAT_MODE_P (GET_MODE (x))
8315 && ! FLOAT_MODE_P (GET_MODE (val)))
8318 if (cond == UNEQ && rtx_equal_p (x, reg))
8321 /* If X is (abs REG) and we know something about REG's relationship
8322 with zero, we may be able to simplify this. */
8324 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8327 case GE: case GT: case EQ:
8330 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8332 GET_MODE (XEXP (x, 0)));
8337 /* The only other cases we handle are MIN, MAX, and comparisons if the
8338 operands are the same as REG and VAL. */
8340 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8342 if (rtx_equal_p (XEXP (x, 0), val))
8343 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8345 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8347 if (COMPARISON_P (x))
8349 if (comparison_dominates_p (cond, code))
8350 return const_true_rtx;
8352 code = reversed_comparison_code (x, NULL);
8354 && comparison_dominates_p (cond, code))
8359 else if (code == SMAX || code == SMIN
8360 || code == UMIN || code == UMAX)
8362 int unsignedp = (code == UMIN || code == UMAX);
8364 /* Do not reverse the condition when it is NE or EQ.
8365 This is because we cannot conclude anything about
8366 the value of 'SMAX (x, y)' when x is not equal to y,
8367 but we can when x equals y. */
8368 if ((code == SMAX || code == UMAX)
8369 && ! (cond == EQ || cond == NE))
8370 cond = reverse_condition (cond);
8375 return unsignedp ? x : XEXP (x, 1);
8377 return unsignedp ? x : XEXP (x, 0);
8379 return unsignedp ? XEXP (x, 1) : x;
8381 return unsignedp ? XEXP (x, 0) : x;
8388 else if (code == SUBREG)
8390 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8391 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8393 if (SUBREG_REG (x) != r)
8395 /* We must simplify subreg here, before we lose track of the
8396 original inner_mode. */
8397 new_rtx = simplify_subreg (GET_MODE (x), r,
8398 inner_mode, SUBREG_BYTE (x));
8402 SUBST (SUBREG_REG (x), r);
8407 /* We don't have to handle SIGN_EXTEND here, because even in the
8408 case of replacing something with a modeless CONST_INT, a
8409 CONST_INT is already (supposed to be) a valid sign extension for
8410 its narrower mode, which implies it's already properly
8411 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8412 story is different. */
8413 else if (code == ZERO_EXTEND)
8415 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8416 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8418 if (XEXP (x, 0) != r)
8420 /* We must simplify the zero_extend here, before we lose
8421 track of the original inner_mode. */
8422 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8427 SUBST (XEXP (x, 0), r);
8433 fmt = GET_RTX_FORMAT (code);
8434 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8437 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8438 else if (fmt[i] == 'E')
8439 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8440 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8447 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8448 assignment as a field assignment. */
8451 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8453 if (x == y || rtx_equal_p (x, y))
8456 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8459 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8460 Note that all SUBREGs of MEM are paradoxical; otherwise they
8461 would have been rewritten. */
8462 if (MEM_P (x) && GET_CODE (y) == SUBREG
8463 && MEM_P (SUBREG_REG (y))
8464 && rtx_equal_p (SUBREG_REG (y),
8465 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8468 if (MEM_P (y) && GET_CODE (x) == SUBREG
8469 && MEM_P (SUBREG_REG (x))
8470 && rtx_equal_p (SUBREG_REG (x),
8471 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8474 /* We used to see if get_last_value of X and Y were the same but that's
8475 not correct. In one direction, we'll cause the assignment to have
8476 the wrong destination and in the case, we'll import a register into this
8477 insn that might have already have been dead. So fail if none of the
8478 above cases are true. */
8482 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8483 Return that assignment if so.
8485 We only handle the most common cases. */
8488 make_field_assignment (rtx x)
8490 rtx dest = SET_DEST (x);
8491 rtx src = SET_SRC (x);
8496 unsigned HOST_WIDE_INT len;
8498 enum machine_mode mode;
8500 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8501 a clear of a one-bit field. We will have changed it to
8502 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8505 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8506 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8507 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8508 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8510 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8513 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8517 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8518 && subreg_lowpart_p (XEXP (src, 0))
8519 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8520 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8521 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8522 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8523 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8524 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8526 assign = make_extraction (VOIDmode, dest, 0,
8527 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8530 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8534 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8536 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8537 && XEXP (XEXP (src, 0), 0) == const1_rtx
8538 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8540 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8543 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8547 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8548 SRC is an AND with all bits of that field set, then we can discard
8550 if (GET_CODE (dest) == ZERO_EXTRACT
8551 && CONST_INT_P (XEXP (dest, 1))
8552 && GET_CODE (src) == AND
8553 && CONST_INT_P (XEXP (src, 1)))
8555 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8556 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8557 unsigned HOST_WIDE_INT ze_mask;
8559 if (width >= HOST_BITS_PER_WIDE_INT)
8562 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8564 /* Complete overlap. We can remove the source AND. */
8565 if ((and_mask & ze_mask) == ze_mask)
8566 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8568 /* Partial overlap. We can reduce the source AND. */
8569 if ((and_mask & ze_mask) != and_mask)
8571 mode = GET_MODE (src);
8572 src = gen_rtx_AND (mode, XEXP (src, 0),
8573 gen_int_mode (and_mask & ze_mask, mode));
8574 return gen_rtx_SET (VOIDmode, dest, src);
8578 /* The other case we handle is assignments into a constant-position
8579 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8580 a mask that has all one bits except for a group of zero bits and
8581 OTHER is known to have zeros where C1 has ones, this is such an
8582 assignment. Compute the position and length from C1. Shift OTHER
8583 to the appropriate position, force it to the required mode, and
8584 make the extraction. Check for the AND in both operands. */
8586 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8589 rhs = expand_compound_operation (XEXP (src, 0));
8590 lhs = expand_compound_operation (XEXP (src, 1));
8592 if (GET_CODE (rhs) == AND
8593 && CONST_INT_P (XEXP (rhs, 1))
8594 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8595 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8596 else if (GET_CODE (lhs) == AND
8597 && CONST_INT_P (XEXP (lhs, 1))
8598 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8599 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8603 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8604 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8605 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8606 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8609 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8613 /* The mode to use for the source is the mode of the assignment, or of
8614 what is inside a possible STRICT_LOW_PART. */
8615 mode = (GET_CODE (assign) == STRICT_LOW_PART
8616 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8618 /* Shift OTHER right POS places and make it the source, restricting it
8619 to the proper length and mode. */
8621 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8625 src = force_to_mode (src, mode,
8626 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8627 ? ~(unsigned HOST_WIDE_INT) 0
8628 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8631 /* If SRC is masked by an AND that does not make a difference in
8632 the value being stored, strip it. */
8633 if (GET_CODE (assign) == ZERO_EXTRACT
8634 && CONST_INT_P (XEXP (assign, 1))
8635 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8636 && GET_CODE (src) == AND
8637 && CONST_INT_P (XEXP (src, 1))
8638 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8639 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8640 src = XEXP (src, 0);
8642 return gen_rtx_SET (VOIDmode, assign, src);
8645 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8649 apply_distributive_law (rtx x)
8651 enum rtx_code code = GET_CODE (x);
8652 enum rtx_code inner_code;
8653 rtx lhs, rhs, other;
8656 /* Distributivity is not true for floating point as it can change the
8657 value. So we don't do it unless -funsafe-math-optimizations. */
8658 if (FLOAT_MODE_P (GET_MODE (x))
8659 && ! flag_unsafe_math_optimizations)
8662 /* The outer operation can only be one of the following: */
8663 if (code != IOR && code != AND && code != XOR
8664 && code != PLUS && code != MINUS)
8670 /* If either operand is a primitive we can't do anything, so get out
8672 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8675 lhs = expand_compound_operation (lhs);
8676 rhs = expand_compound_operation (rhs);
8677 inner_code = GET_CODE (lhs);
8678 if (inner_code != GET_CODE (rhs))
8681 /* See if the inner and outer operations distribute. */
8688 /* These all distribute except over PLUS. */
8689 if (code == PLUS || code == MINUS)
8694 if (code != PLUS && code != MINUS)
8699 /* This is also a multiply, so it distributes over everything. */
8703 /* Non-paradoxical SUBREGs distributes over all operations,
8704 provided the inner modes and byte offsets are the same, this
8705 is an extraction of a low-order part, we don't convert an fp
8706 operation to int or vice versa, this is not a vector mode,
8707 and we would not be converting a single-word operation into a
8708 multi-word operation. The latter test is not required, but
8709 it prevents generating unneeded multi-word operations. Some
8710 of the previous tests are redundant given the latter test,
8711 but are retained because they are required for correctness.
8713 We produce the result slightly differently in this case. */
8715 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8716 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8717 || ! subreg_lowpart_p (lhs)
8718 || (GET_MODE_CLASS (GET_MODE (lhs))
8719 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8720 || (GET_MODE_SIZE (GET_MODE (lhs))
8721 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8722 || VECTOR_MODE_P (GET_MODE (lhs))
8723 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8724 /* Result might need to be truncated. Don't change mode if
8725 explicit truncation is needed. */
8726 || !TRULY_NOOP_TRUNCATION
8727 (GET_MODE_BITSIZE (GET_MODE (x)),
8728 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8731 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8732 SUBREG_REG (lhs), SUBREG_REG (rhs));
8733 return gen_lowpart (GET_MODE (x), tem);
8739 /* Set LHS and RHS to the inner operands (A and B in the example
8740 above) and set OTHER to the common operand (C in the example).
8741 There is only one way to do this unless the inner operation is
8743 if (COMMUTATIVE_ARITH_P (lhs)
8744 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8745 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8746 else if (COMMUTATIVE_ARITH_P (lhs)
8747 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8748 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8749 else if (COMMUTATIVE_ARITH_P (lhs)
8750 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8751 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8752 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8753 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8757 /* Form the new inner operation, seeing if it simplifies first. */
8758 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8760 /* There is one exception to the general way of distributing:
8761 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8762 if (code == XOR && inner_code == IOR)
8765 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8768 /* We may be able to continuing distributing the result, so call
8769 ourselves recursively on the inner operation before forming the
8770 outer operation, which we return. */
8771 return simplify_gen_binary (inner_code, GET_MODE (x),
8772 apply_distributive_law (tem), other);
8775 /* See if X is of the form (* (+ A B) C), and if so convert to
8776 (+ (* A C) (* B C)) and try to simplify.
8778 Most of the time, this results in no change. However, if some of
8779 the operands are the same or inverses of each other, simplifications
8782 For example, (and (ior A B) (not B)) can occur as the result of
8783 expanding a bit field assignment. When we apply the distributive
8784 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8785 which then simplifies to (and (A (not B))).
8787 Note that no checks happen on the validity of applying the inverse
8788 distributive law. This is pointless since we can do it in the
8789 few places where this routine is called.
8791 N is the index of the term that is decomposed (the arithmetic operation,
8792 i.e. (+ A B) in the first example above). !N is the index of the term that
8793 is distributed, i.e. of C in the first example above. */
8795 distribute_and_simplify_rtx (rtx x, int n)
8797 enum machine_mode mode;
8798 enum rtx_code outer_code, inner_code;
8799 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8801 /* Distributivity is not true for floating point as it can change the
8802 value. So we don't do it unless -funsafe-math-optimizations. */
8803 if (FLOAT_MODE_P (GET_MODE (x))
8804 && ! flag_unsafe_math_optimizations)
8807 decomposed = XEXP (x, n);
8808 if (!ARITHMETIC_P (decomposed))
8811 mode = GET_MODE (x);
8812 outer_code = GET_CODE (x);
8813 distributed = XEXP (x, !n);
8815 inner_code = GET_CODE (decomposed);
8816 inner_op0 = XEXP (decomposed, 0);
8817 inner_op1 = XEXP (decomposed, 1);
8819 /* Special case (and (xor B C) (not A)), which is equivalent to
8820 (xor (ior A B) (ior A C)) */
8821 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8823 distributed = XEXP (distributed, 0);
8829 /* Distribute the second term. */
8830 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8831 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8835 /* Distribute the first term. */
8836 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8837 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8840 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8842 if (GET_CODE (tmp) != outer_code
8843 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8844 < rtx_cost (x, SET, optimize_this_for_speed_p))
8850 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8851 in MODE. Return an equivalent form, if different from (and VAROP
8852 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8855 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8856 unsigned HOST_WIDE_INT constop)
8858 unsigned HOST_WIDE_INT nonzero;
8859 unsigned HOST_WIDE_INT orig_constop;
8864 orig_constop = constop;
8865 if (GET_CODE (varop) == CLOBBER)
8868 /* Simplify VAROP knowing that we will be only looking at some of the
8871 Note by passing in CONSTOP, we guarantee that the bits not set in
8872 CONSTOP are not significant and will never be examined. We must
8873 ensure that is the case by explicitly masking out those bits
8874 before returning. */
8875 varop = force_to_mode (varop, mode, constop, 0);
8877 /* If VAROP is a CLOBBER, we will fail so return it. */
8878 if (GET_CODE (varop) == CLOBBER)
8881 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8882 to VAROP and return the new constant. */
8883 if (CONST_INT_P (varop))
8884 return gen_int_mode (INTVAL (varop) & constop, mode);
8886 /* See what bits may be nonzero in VAROP. Unlike the general case of
8887 a call to nonzero_bits, here we don't care about bits outside
8890 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8892 /* Turn off all bits in the constant that are known to already be zero.
8893 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8894 which is tested below. */
8898 /* If we don't have any bits left, return zero. */
8902 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8903 a power of two, we can replace this with an ASHIFT. */
8904 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8905 && (i = exact_log2 (constop)) >= 0)
8906 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8908 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8909 or XOR, then try to apply the distributive law. This may eliminate
8910 operations if either branch can be simplified because of the AND.
8911 It may also make some cases more complex, but those cases probably
8912 won't match a pattern either with or without this. */
8914 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8918 apply_distributive_law
8919 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8920 simplify_and_const_int (NULL_RTX,
8924 simplify_and_const_int (NULL_RTX,
8929 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8930 the AND and see if one of the operands simplifies to zero. If so, we
8931 may eliminate it. */
8933 if (GET_CODE (varop) == PLUS
8934 && exact_log2 (constop + 1) >= 0)
8938 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8939 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8940 if (o0 == const0_rtx)
8942 if (o1 == const0_rtx)
8946 /* Make a SUBREG if necessary. If we can't make it, fail. */
8947 varop = gen_lowpart (mode, varop);
8948 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8951 /* If we are only masking insignificant bits, return VAROP. */
8952 if (constop == nonzero)
8955 if (varop == orig_varop && constop == orig_constop)
8958 /* Otherwise, return an AND. */
8959 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8963 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8966 Return an equivalent form, if different from X. Otherwise, return X. If
8967 X is zero, we are to always construct the equivalent form. */
8970 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8971 unsigned HOST_WIDE_INT constop)
8973 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8978 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8979 gen_int_mode (constop, mode));
8980 if (GET_MODE (x) != mode)
8981 x = gen_lowpart (mode, x);
8985 /* Given a REG, X, compute which bits in X can be nonzero.
8986 We don't care about bits outside of those defined in MODE.
8988 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8989 a shift, AND, or zero_extract, we can do better. */
8992 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8993 const_rtx known_x ATTRIBUTE_UNUSED,
8994 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8995 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8996 unsigned HOST_WIDE_INT *nonzero)
9001 /* If X is a register whose nonzero bits value is current, use it.
9002 Otherwise, if X is a register whose value we can find, use that
9003 value. Otherwise, use the previously-computed global nonzero bits
9004 for this register. */
9006 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9007 if (rsp->last_set_value != 0
9008 && (rsp->last_set_mode == mode
9009 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9010 && GET_MODE_CLASS (mode) == MODE_INT))
9011 && ((rsp->last_set_label >= label_tick_ebb_start
9012 && rsp->last_set_label < label_tick)
9013 || (rsp->last_set_label == label_tick
9014 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9015 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9016 && REG_N_SETS (REGNO (x)) == 1
9018 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9020 *nonzero &= rsp->last_set_nonzero_bits;
9024 tem = get_last_value (x);
9028 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9029 /* If X is narrower than MODE and TEM is a non-negative
9030 constant that would appear negative in the mode of X,
9031 sign-extend it for use in reg_nonzero_bits because some
9032 machines (maybe most) will actually do the sign-extension
9033 and this is the conservative approach.
9035 ??? For 2.5, try to tighten up the MD files in this regard
9036 instead of this kludge. */
9038 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9039 && CONST_INT_P (tem)
9041 && 0 != (INTVAL (tem)
9042 & ((HOST_WIDE_INT) 1
9043 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9044 tem = GEN_INT (INTVAL (tem)
9045 | ((HOST_WIDE_INT) (-1)
9046 << GET_MODE_BITSIZE (GET_MODE (x))));
9050 else if (nonzero_sign_valid && rsp->nonzero_bits)
9052 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9054 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9055 /* We don't know anything about the upper bits. */
9056 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9063 /* Return the number of bits at the high-order end of X that are known to
9064 be equal to the sign bit. X will be used in mode MODE; if MODE is
9065 VOIDmode, X will be used in its own mode. The returned value will always
9066 be between 1 and the number of bits in MODE. */
9069 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9070 const_rtx known_x ATTRIBUTE_UNUSED,
9071 enum machine_mode known_mode
9073 unsigned int known_ret ATTRIBUTE_UNUSED,
9074 unsigned int *result)
9079 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9080 if (rsp->last_set_value != 0
9081 && rsp->last_set_mode == mode
9082 && ((rsp->last_set_label >= label_tick_ebb_start
9083 && rsp->last_set_label < label_tick)
9084 || (rsp->last_set_label == label_tick
9085 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9086 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9087 && REG_N_SETS (REGNO (x)) == 1
9089 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9091 *result = rsp->last_set_sign_bit_copies;
9095 tem = get_last_value (x);
9099 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9100 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9101 *result = rsp->sign_bit_copies;
9106 /* Return the number of "extended" bits there are in X, when interpreted
9107 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9108 unsigned quantities, this is the number of high-order zero bits.
9109 For signed quantities, this is the number of copies of the sign bit
9110 minus 1. In both case, this function returns the number of "spare"
9111 bits. For example, if two quantities for which this function returns
9112 at least 1 are added, the addition is known not to overflow.
9114 This function will always return 0 unless called during combine, which
9115 implies that it must be called from a define_split. */
9118 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9120 if (nonzero_sign_valid == 0)
9124 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9125 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9126 - floor_log2 (nonzero_bits (x, mode)))
9128 : num_sign_bit_copies (x, mode) - 1);
9131 /* This function is called from `simplify_shift_const' to merge two
9132 outer operations. Specifically, we have already found that we need
9133 to perform operation *POP0 with constant *PCONST0 at the outermost
9134 position. We would now like to also perform OP1 with constant CONST1
9135 (with *POP0 being done last).
9137 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9138 the resulting operation. *PCOMP_P is set to 1 if we would need to
9139 complement the innermost operand, otherwise it is unchanged.
9141 MODE is the mode in which the operation will be done. No bits outside
9142 the width of this mode matter. It is assumed that the width of this mode
9143 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9145 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9146 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9147 result is simply *PCONST0.
9149 If the resulting operation cannot be expressed as one operation, we
9150 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9153 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9155 enum rtx_code op0 = *pop0;
9156 HOST_WIDE_INT const0 = *pconst0;
9158 const0 &= GET_MODE_MASK (mode);
9159 const1 &= GET_MODE_MASK (mode);
9161 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9165 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9168 if (op1 == UNKNOWN || op0 == SET)
9171 else if (op0 == UNKNOWN)
9172 op0 = op1, const0 = const1;
9174 else if (op0 == op1)
9198 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9199 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9202 /* If the two constants aren't the same, we can't do anything. The
9203 remaining six cases can all be done. */
9204 else if (const0 != const1)
9212 /* (a & b) | b == b */
9214 else /* op1 == XOR */
9215 /* (a ^ b) | b == a | b */
9221 /* (a & b) ^ b == (~a) & b */
9222 op0 = AND, *pcomp_p = 1;
9223 else /* op1 == IOR */
9224 /* (a | b) ^ b == a & ~b */
9225 op0 = AND, const0 = ~const0;
9230 /* (a | b) & b == b */
9232 else /* op1 == XOR */
9233 /* (a ^ b) & b) == (~a) & b */
9240 /* Check for NO-OP cases. */
9241 const0 &= GET_MODE_MASK (mode);
9243 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9245 else if (const0 == 0 && op0 == AND)
9247 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9253 /* ??? Slightly redundant with the above mask, but not entirely.
9254 Moving this above means we'd have to sign-extend the mode mask
9255 for the final test. */
9256 if (op0 != UNKNOWN && op0 != NEG)
9257 *pconst0 = trunc_int_for_mode (const0, mode);
9262 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9263 the shift in. The original shift operation CODE is performed on OP in
9264 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9265 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9266 result of the shift is subject to operation OUTER_CODE with operand
9269 static enum machine_mode
9270 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9271 enum machine_mode orig_mode, enum machine_mode mode,
9272 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9274 if (orig_mode == mode)
9276 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9278 /* In general we can't perform in wider mode for right shift and rotate. */
9282 /* We can still widen if the bits brought in from the left are identical
9283 to the sign bit of ORIG_MODE. */
9284 if (num_sign_bit_copies (op, mode)
9285 > (unsigned) (GET_MODE_BITSIZE (mode)
9286 - GET_MODE_BITSIZE (orig_mode)))
9291 /* Similarly here but with zero bits. */
9292 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9293 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9296 /* We can also widen if the bits brought in will be masked off. This
9297 operation is performed in ORIG_MODE. */
9298 if (outer_code == AND)
9300 int care_bits = low_bitmask_len (orig_mode, outer_const);
9303 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9319 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9320 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9321 simplify it. Otherwise, return a simplified value.
9323 The shift is normally computed in the widest mode we find in VAROP, as
9324 long as it isn't a different number of words than RESULT_MODE. Exceptions
9325 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9328 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9329 rtx varop, int orig_count)
9331 enum rtx_code orig_code = code;
9332 rtx orig_varop = varop;
9334 enum machine_mode mode = result_mode;
9335 enum machine_mode shift_mode, tmode;
9336 unsigned int mode_words
9337 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9338 /* We form (outer_op (code varop count) (outer_const)). */
9339 enum rtx_code outer_op = UNKNOWN;
9340 HOST_WIDE_INT outer_const = 0;
9341 int complement_p = 0;
9344 /* Make sure and truncate the "natural" shift on the way in. We don't
9345 want to do this inside the loop as it makes it more difficult to
9347 if (SHIFT_COUNT_TRUNCATED)
9348 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9350 /* If we were given an invalid count, don't do anything except exactly
9351 what was requested. */
9353 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9358 /* Unless one of the branches of the `if' in this loop does a `continue',
9359 we will `break' the loop after the `if'. */
9363 /* If we have an operand of (clobber (const_int 0)), fail. */
9364 if (GET_CODE (varop) == CLOBBER)
9367 /* Convert ROTATERT to ROTATE. */
9368 if (code == ROTATERT)
9370 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9372 if (VECTOR_MODE_P (result_mode))
9373 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9375 count = bitsize - count;
9378 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9379 mode, outer_op, outer_const);
9381 /* Handle cases where the count is greater than the size of the mode
9382 minus 1. For ASHIFT, use the size minus one as the count (this can
9383 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9384 take the count modulo the size. For other shifts, the result is
9387 Since these shifts are being produced by the compiler by combining
9388 multiple operations, each of which are defined, we know what the
9389 result is supposed to be. */
9391 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9393 if (code == ASHIFTRT)
9394 count = GET_MODE_BITSIZE (shift_mode) - 1;
9395 else if (code == ROTATE || code == ROTATERT)
9396 count %= GET_MODE_BITSIZE (shift_mode);
9399 /* We can't simply return zero because there may be an
9407 /* If we discovered we had to complement VAROP, leave. Making a NOT
9408 here would cause an infinite loop. */
9412 /* An arithmetic right shift of a quantity known to be -1 or 0
9414 if (code == ASHIFTRT
9415 && (num_sign_bit_copies (varop, shift_mode)
9416 == GET_MODE_BITSIZE (shift_mode)))
9422 /* If we are doing an arithmetic right shift and discarding all but
9423 the sign bit copies, this is equivalent to doing a shift by the
9424 bitsize minus one. Convert it into that shift because it will often
9425 allow other simplifications. */
9427 if (code == ASHIFTRT
9428 && (count + num_sign_bit_copies (varop, shift_mode)
9429 >= GET_MODE_BITSIZE (shift_mode)))
9430 count = GET_MODE_BITSIZE (shift_mode) - 1;
9432 /* We simplify the tests below and elsewhere by converting
9433 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9434 `make_compound_operation' will convert it to an ASHIFTRT for
9435 those machines (such as VAX) that don't have an LSHIFTRT. */
9436 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9438 && ((nonzero_bits (varop, shift_mode)
9439 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9443 if (((code == LSHIFTRT
9444 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9445 && !(nonzero_bits (varop, shift_mode) >> count))
9447 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9448 && !((nonzero_bits (varop, shift_mode) << count)
9449 & GET_MODE_MASK (shift_mode))))
9450 && !side_effects_p (varop))
9453 switch (GET_CODE (varop))
9459 new_rtx = expand_compound_operation (varop);
9460 if (new_rtx != varop)
9468 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9469 minus the width of a smaller mode, we can do this with a
9470 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9471 if ((code == ASHIFTRT || code == LSHIFTRT)
9472 && ! mode_dependent_address_p (XEXP (varop, 0))
9473 && ! MEM_VOLATILE_P (varop)
9474 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9475 MODE_INT, 1)) != BLKmode)
9477 new_rtx = adjust_address_nv (varop, tmode,
9478 BYTES_BIG_ENDIAN ? 0
9479 : count / BITS_PER_UNIT);
9481 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9482 : ZERO_EXTEND, mode, new_rtx);
9489 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9490 the same number of words as what we've seen so far. Then store
9491 the widest mode in MODE. */
9492 if (subreg_lowpart_p (varop)
9493 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9494 > GET_MODE_SIZE (GET_MODE (varop)))
9495 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9496 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9499 varop = SUBREG_REG (varop);
9500 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9501 mode = GET_MODE (varop);
9507 /* Some machines use MULT instead of ASHIFT because MULT
9508 is cheaper. But it is still better on those machines to
9509 merge two shifts into one. */
9510 if (CONST_INT_P (XEXP (varop, 1))
9511 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9514 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9516 GEN_INT (exact_log2 (
9517 INTVAL (XEXP (varop, 1)))));
9523 /* Similar, for when divides are cheaper. */
9524 if (CONST_INT_P (XEXP (varop, 1))
9525 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9528 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9530 GEN_INT (exact_log2 (
9531 INTVAL (XEXP (varop, 1)))));
9537 /* If we are extracting just the sign bit of an arithmetic
9538 right shift, that shift is not needed. However, the sign
9539 bit of a wider mode may be different from what would be
9540 interpreted as the sign bit in a narrower mode, so, if
9541 the result is narrower, don't discard the shift. */
9542 if (code == LSHIFTRT
9543 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9544 && (GET_MODE_BITSIZE (result_mode)
9545 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9547 varop = XEXP (varop, 0);
9551 /* ... fall through ... */
9556 /* Here we have two nested shifts. The result is usually the
9557 AND of a new shift with a mask. We compute the result below. */
9558 if (CONST_INT_P (XEXP (varop, 1))
9559 && INTVAL (XEXP (varop, 1)) >= 0
9560 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9561 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9562 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9563 && !VECTOR_MODE_P (result_mode))
9565 enum rtx_code first_code = GET_CODE (varop);
9566 unsigned int first_count = INTVAL (XEXP (varop, 1));
9567 unsigned HOST_WIDE_INT mask;
9570 /* We have one common special case. We can't do any merging if
9571 the inner code is an ASHIFTRT of a smaller mode. However, if
9572 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9573 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9574 we can convert it to
9575 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9576 This simplifies certain SIGN_EXTEND operations. */
9577 if (code == ASHIFT && first_code == ASHIFTRT
9578 && count == (GET_MODE_BITSIZE (result_mode)
9579 - GET_MODE_BITSIZE (GET_MODE (varop))))
9581 /* C3 has the low-order C1 bits zero. */
9583 mask = (GET_MODE_MASK (mode)
9584 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9586 varop = simplify_and_const_int (NULL_RTX, result_mode,
9587 XEXP (varop, 0), mask);
9588 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9590 count = first_count;
9595 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9596 than C1 high-order bits equal to the sign bit, we can convert
9597 this to either an ASHIFT or an ASHIFTRT depending on the
9600 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9602 if (code == ASHIFTRT && first_code == ASHIFT
9603 && GET_MODE (varop) == shift_mode
9604 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9607 varop = XEXP (varop, 0);
9608 count -= first_count;
9618 /* There are some cases we can't do. If CODE is ASHIFTRT,
9619 we can only do this if FIRST_CODE is also ASHIFTRT.
9621 We can't do the case when CODE is ROTATE and FIRST_CODE is
9624 If the mode of this shift is not the mode of the outer shift,
9625 we can't do this if either shift is a right shift or ROTATE.
9627 Finally, we can't do any of these if the mode is too wide
9628 unless the codes are the same.
9630 Handle the case where the shift codes are the same
9633 if (code == first_code)
9635 if (GET_MODE (varop) != result_mode
9636 && (code == ASHIFTRT || code == LSHIFTRT
9640 count += first_count;
9641 varop = XEXP (varop, 0);
9645 if (code == ASHIFTRT
9646 || (code == ROTATE && first_code == ASHIFTRT)
9647 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9648 || (GET_MODE (varop) != result_mode
9649 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9650 || first_code == ROTATE
9651 || code == ROTATE)))
9654 /* To compute the mask to apply after the shift, shift the
9655 nonzero bits of the inner shift the same way the
9656 outer shift will. */
9658 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9661 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9664 /* Give up if we can't compute an outer operation to use. */
9666 || !CONST_INT_P (mask_rtx)
9667 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9669 result_mode, &complement_p))
9672 /* If the shifts are in the same direction, we add the
9673 counts. Otherwise, we subtract them. */
9674 if ((code == ASHIFTRT || code == LSHIFTRT)
9675 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9676 count += first_count;
9678 count -= first_count;
9680 /* If COUNT is positive, the new shift is usually CODE,
9681 except for the two exceptions below, in which case it is
9682 FIRST_CODE. If the count is negative, FIRST_CODE should
9685 && ((first_code == ROTATE && code == ASHIFT)
9686 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9689 code = first_code, count = -count;
9691 varop = XEXP (varop, 0);
9695 /* If we have (A << B << C) for any shift, we can convert this to
9696 (A << C << B). This wins if A is a constant. Only try this if
9697 B is not a constant. */
9699 else if (GET_CODE (varop) == code
9700 && CONST_INT_P (XEXP (varop, 0))
9701 && !CONST_INT_P (XEXP (varop, 1)))
9703 rtx new_rtx = simplify_const_binary_operation (code, mode,
9706 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9713 if (VECTOR_MODE_P (mode))
9716 /* Make this fit the case below. */
9717 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9718 GEN_INT (GET_MODE_MASK (mode)));
9724 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9725 with C the size of VAROP - 1 and the shift is logical if
9726 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9727 we have an (le X 0) operation. If we have an arithmetic shift
9728 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9729 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9731 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9732 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9733 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9734 && (code == LSHIFTRT || code == ASHIFTRT)
9735 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9736 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9739 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9742 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9743 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9748 /* If we have (shift (logical)), move the logical to the outside
9749 to allow it to possibly combine with another logical and the
9750 shift to combine with another shift. This also canonicalizes to
9751 what a ZERO_EXTRACT looks like. Also, some machines have
9752 (and (shift)) insns. */
9754 if (CONST_INT_P (XEXP (varop, 1))
9755 /* We can't do this if we have (ashiftrt (xor)) and the
9756 constant has its sign bit set in shift_mode. */
9757 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9758 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9760 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9762 GEN_INT (count))) != 0
9763 && CONST_INT_P (new_rtx)
9764 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9765 INTVAL (new_rtx), result_mode, &complement_p))
9767 varop = XEXP (varop, 0);
9771 /* If we can't do that, try to simplify the shift in each arm of the
9772 logical expression, make a new logical expression, and apply
9773 the inverse distributive law. This also can't be done
9774 for some (ashiftrt (xor)). */
9775 if (CONST_INT_P (XEXP (varop, 1))
9776 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9777 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9780 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9781 XEXP (varop, 0), count);
9782 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9783 XEXP (varop, 1), count);
9785 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9787 varop = apply_distributive_law (varop);
9795 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9796 says that the sign bit can be tested, FOO has mode MODE, C is
9797 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9798 that may be nonzero. */
9799 if (code == LSHIFTRT
9800 && XEXP (varop, 1) == const0_rtx
9801 && GET_MODE (XEXP (varop, 0)) == result_mode
9802 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9803 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9804 && STORE_FLAG_VALUE == -1
9805 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9806 && merge_outer_ops (&outer_op, &outer_const, XOR,
9807 (HOST_WIDE_INT) 1, result_mode,
9810 varop = XEXP (varop, 0);
9817 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9818 than the number of bits in the mode is equivalent to A. */
9819 if (code == LSHIFTRT
9820 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9821 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9823 varop = XEXP (varop, 0);
9828 /* NEG commutes with ASHIFT since it is multiplication. Move the
9829 NEG outside to allow shifts to combine. */
9831 && merge_outer_ops (&outer_op, &outer_const, NEG,
9832 (HOST_WIDE_INT) 0, result_mode,
9835 varop = XEXP (varop, 0);
9841 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9842 is one less than the number of bits in the mode is
9843 equivalent to (xor A 1). */
9844 if (code == LSHIFTRT
9845 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9846 && XEXP (varop, 1) == constm1_rtx
9847 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9848 && merge_outer_ops (&outer_op, &outer_const, XOR,
9849 (HOST_WIDE_INT) 1, result_mode,
9853 varop = XEXP (varop, 0);
9857 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9858 that might be nonzero in BAR are those being shifted out and those
9859 bits are known zero in FOO, we can replace the PLUS with FOO.
9860 Similarly in the other operand order. This code occurs when
9861 we are computing the size of a variable-size array. */
9863 if ((code == ASHIFTRT || code == LSHIFTRT)
9864 && count < HOST_BITS_PER_WIDE_INT
9865 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9866 && (nonzero_bits (XEXP (varop, 1), result_mode)
9867 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9869 varop = XEXP (varop, 0);
9872 else if ((code == ASHIFTRT || code == LSHIFTRT)
9873 && count < HOST_BITS_PER_WIDE_INT
9874 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9875 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9877 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9878 & nonzero_bits (XEXP (varop, 1),
9881 varop = XEXP (varop, 1);
9885 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9887 && CONST_INT_P (XEXP (varop, 1))
9888 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9890 GEN_INT (count))) != 0
9891 && CONST_INT_P (new_rtx)
9892 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9893 INTVAL (new_rtx), result_mode, &complement_p))
9895 varop = XEXP (varop, 0);
9899 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9900 signbit', and attempt to change the PLUS to an XOR and move it to
9901 the outer operation as is done above in the AND/IOR/XOR case
9902 leg for shift(logical). See details in logical handling above
9903 for reasoning in doing so. */
9904 if (code == LSHIFTRT
9905 && CONST_INT_P (XEXP (varop, 1))
9906 && mode_signbit_p (result_mode, XEXP (varop, 1))
9907 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9909 GEN_INT (count))) != 0
9910 && CONST_INT_P (new_rtx)
9911 && merge_outer_ops (&outer_op, &outer_const, XOR,
9912 INTVAL (new_rtx), result_mode, &complement_p))
9914 varop = XEXP (varop, 0);
9921 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9922 with C the size of VAROP - 1 and the shift is logical if
9923 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9924 we have a (gt X 0) operation. If the shift is arithmetic with
9925 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9926 we have a (neg (gt X 0)) operation. */
9928 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9929 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9930 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9931 && (code == LSHIFTRT || code == ASHIFTRT)
9932 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9933 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9934 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9937 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9940 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9941 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9948 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9949 if the truncate does not affect the value. */
9950 if (code == LSHIFTRT
9951 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9952 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9953 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9954 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9955 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9957 rtx varop_inner = XEXP (varop, 0);
9960 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9961 XEXP (varop_inner, 0),
9963 (count + INTVAL (XEXP (varop_inner, 1))));
9964 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9977 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
9978 outer_op, outer_const);
9980 /* We have now finished analyzing the shift. The result should be
9981 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9982 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9983 to the result of the shift. OUTER_CONST is the relevant constant,
9984 but we must turn off all bits turned off in the shift. */
9986 if (outer_op == UNKNOWN
9987 && orig_code == code && orig_count == count
9988 && varop == orig_varop
9989 && shift_mode == GET_MODE (varop))
9992 /* Make a SUBREG if necessary. If we can't make it, fail. */
9993 varop = gen_lowpart (shift_mode, varop);
9994 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9997 /* If we have an outer operation and we just made a shift, it is
9998 possible that we could have simplified the shift were it not
9999 for the outer operation. So try to do the simplification
10002 if (outer_op != UNKNOWN)
10003 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10008 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10010 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10011 turn off all the bits that the shift would have turned off. */
10012 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10013 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10014 GET_MODE_MASK (result_mode) >> orig_count);
10016 /* Do the remainder of the processing in RESULT_MODE. */
10017 x = gen_lowpart_or_truncate (result_mode, x);
10019 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10022 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10024 if (outer_op != UNKNOWN)
10026 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10027 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10028 outer_const = trunc_int_for_mode (outer_const, result_mode);
10030 if (outer_op == AND)
10031 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10032 else if (outer_op == SET)
10034 /* This means that we have determined that the result is
10035 equivalent to a constant. This should be rare. */
10036 if (!side_effects_p (x))
10037 x = GEN_INT (outer_const);
10039 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10040 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10042 x = simplify_gen_binary (outer_op, result_mode, x,
10043 GEN_INT (outer_const));
10049 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10050 The result of the shift is RESULT_MODE. If we cannot simplify it,
10051 return X or, if it is NULL, synthesize the expression with
10052 simplify_gen_binary. Otherwise, return a simplified value.
10054 The shift is normally computed in the widest mode we find in VAROP, as
10055 long as it isn't a different number of words than RESULT_MODE. Exceptions
10056 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10059 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10060 rtx varop, int count)
10062 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10067 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10068 if (GET_MODE (x) != result_mode)
10069 x = gen_lowpart (result_mode, x);
10074 /* Like recog, but we receive the address of a pointer to a new pattern.
10075 We try to match the rtx that the pointer points to.
10076 If that fails, we may try to modify or replace the pattern,
10077 storing the replacement into the same pointer object.
10079 Modifications include deletion or addition of CLOBBERs.
10081 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10082 the CLOBBERs are placed.
10084 The value is the final insn code from the pattern ultimately matched,
10088 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10090 rtx pat = *pnewpat;
10091 int insn_code_number;
10092 int num_clobbers_to_add = 0;
10095 rtx old_notes, old_pat;
10097 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10098 we use to indicate that something didn't match. If we find such a
10099 thing, force rejection. */
10100 if (GET_CODE (pat) == PARALLEL)
10101 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10102 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10103 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10106 old_pat = PATTERN (insn);
10107 old_notes = REG_NOTES (insn);
10108 PATTERN (insn) = pat;
10109 REG_NOTES (insn) = 0;
10111 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10112 if (dump_file && (dump_flags & TDF_DETAILS))
10114 if (insn_code_number < 0)
10115 fputs ("Failed to match this instruction:\n", dump_file);
10117 fputs ("Successfully matched this instruction:\n", dump_file);
10118 print_rtl_single (dump_file, pat);
10121 /* If it isn't, there is the possibility that we previously had an insn
10122 that clobbered some register as a side effect, but the combined
10123 insn doesn't need to do that. So try once more without the clobbers
10124 unless this represents an ASM insn. */
10126 if (insn_code_number < 0 && ! check_asm_operands (pat)
10127 && GET_CODE (pat) == PARALLEL)
10131 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10132 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10135 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10139 SUBST_INT (XVECLEN (pat, 0), pos);
10142 pat = XVECEXP (pat, 0, 0);
10144 PATTERN (insn) = pat;
10145 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10146 if (dump_file && (dump_flags & TDF_DETAILS))
10148 if (insn_code_number < 0)
10149 fputs ("Failed to match this instruction:\n", dump_file);
10151 fputs ("Successfully matched this instruction:\n", dump_file);
10152 print_rtl_single (dump_file, pat);
10155 PATTERN (insn) = old_pat;
10156 REG_NOTES (insn) = old_notes;
10158 /* Recognize all noop sets, these will be killed by followup pass. */
10159 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10160 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10162 /* If we had any clobbers to add, make a new pattern than contains
10163 them. Then check to make sure that all of them are dead. */
10164 if (num_clobbers_to_add)
10166 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10167 rtvec_alloc (GET_CODE (pat) == PARALLEL
10168 ? (XVECLEN (pat, 0)
10169 + num_clobbers_to_add)
10170 : num_clobbers_to_add + 1));
10172 if (GET_CODE (pat) == PARALLEL)
10173 for (i = 0; i < XVECLEN (pat, 0); i++)
10174 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10176 XVECEXP (newpat, 0, 0) = pat;
10178 add_clobbers (newpat, insn_code_number);
10180 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10181 i < XVECLEN (newpat, 0); i++)
10183 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10184 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10186 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10188 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10189 notes = alloc_reg_note (REG_UNUSED,
10190 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10199 return insn_code_number;
10202 /* Like gen_lowpart_general but for use by combine. In combine it
10203 is not possible to create any new pseudoregs. However, it is
10204 safe to create invalid memory addresses, because combine will
10205 try to recognize them and all they will do is make the combine
10208 If for some reason this cannot do its job, an rtx
10209 (clobber (const_int 0)) is returned.
10210 An insn containing that will not be recognized. */
10213 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10215 enum machine_mode imode = GET_MODE (x);
10216 unsigned int osize = GET_MODE_SIZE (omode);
10217 unsigned int isize = GET_MODE_SIZE (imode);
10220 if (omode == imode)
10223 /* Return identity if this is a CONST or symbolic reference. */
10225 && (GET_CODE (x) == CONST
10226 || GET_CODE (x) == SYMBOL_REF
10227 || GET_CODE (x) == LABEL_REF))
10230 /* We can only support MODE being wider than a word if X is a
10231 constant integer or has a mode the same size. */
10232 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10233 && ! ((imode == VOIDmode
10234 && (CONST_INT_P (x)
10235 || GET_CODE (x) == CONST_DOUBLE))
10236 || isize == osize))
10239 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10240 won't know what to do. So we will strip off the SUBREG here and
10241 process normally. */
10242 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10244 x = SUBREG_REG (x);
10246 /* For use in case we fall down into the address adjustments
10247 further below, we need to adjust the known mode and size of
10248 x; imode and isize, since we just adjusted x. */
10249 imode = GET_MODE (x);
10251 if (imode == omode)
10254 isize = GET_MODE_SIZE (imode);
10257 result = gen_lowpart_common (omode, x);
10266 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10268 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10271 /* If we want to refer to something bigger than the original memref,
10272 generate a paradoxical subreg instead. That will force a reload
10273 of the original memref X. */
10275 return gen_rtx_SUBREG (omode, x, 0);
10277 if (WORDS_BIG_ENDIAN)
10278 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10280 /* Adjust the address so that the address-after-the-data is
10282 if (BYTES_BIG_ENDIAN)
10283 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10285 return adjust_address_nv (x, omode, offset);
10288 /* If X is a comparison operator, rewrite it in a new mode. This
10289 probably won't match, but may allow further simplifications. */
10290 else if (COMPARISON_P (x))
10291 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10293 /* If we couldn't simplify X any other way, just enclose it in a
10294 SUBREG. Normally, this SUBREG won't match, but some patterns may
10295 include an explicit SUBREG or we may simplify it further in combine. */
10301 offset = subreg_lowpart_offset (omode, imode);
10302 if (imode == VOIDmode)
10304 imode = int_mode_for_mode (omode);
10305 x = gen_lowpart_common (imode, x);
10309 res = simplify_gen_subreg (omode, x, imode, offset);
10315 return gen_rtx_CLOBBER (omode, const0_rtx);
10318 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10319 comparison code that will be tested.
10321 The result is a possibly different comparison code to use. *POP0 and
10322 *POP1 may be updated.
10324 It is possible that we might detect that a comparison is either always
10325 true or always false. However, we do not perform general constant
10326 folding in combine, so this knowledge isn't useful. Such tautologies
10327 should have been detected earlier. Hence we ignore all such cases. */
10329 static enum rtx_code
10330 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10336 enum machine_mode mode, tmode;
10338 /* Try a few ways of applying the same transformation to both operands. */
10341 #ifndef WORD_REGISTER_OPERATIONS
10342 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10343 so check specially. */
10344 if (code != GTU && code != GEU && code != LTU && code != LEU
10345 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10346 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10347 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10348 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10349 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10350 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10351 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10352 && CONST_INT_P (XEXP (op0, 1))
10353 && XEXP (op0, 1) == XEXP (op1, 1)
10354 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10355 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10356 && (INTVAL (XEXP (op0, 1))
10357 == (GET_MODE_BITSIZE (GET_MODE (op0))
10358 - (GET_MODE_BITSIZE
10359 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10361 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10362 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10366 /* If both operands are the same constant shift, see if we can ignore the
10367 shift. We can if the shift is a rotate or if the bits shifted out of
10368 this shift are known to be zero for both inputs and if the type of
10369 comparison is compatible with the shift. */
10370 if (GET_CODE (op0) == GET_CODE (op1)
10371 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10372 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10373 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10374 && (code != GT && code != LT && code != GE && code != LE))
10375 || (GET_CODE (op0) == ASHIFTRT
10376 && (code != GTU && code != LTU
10377 && code != GEU && code != LEU)))
10378 && CONST_INT_P (XEXP (op0, 1))
10379 && INTVAL (XEXP (op0, 1)) >= 0
10380 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10381 && XEXP (op0, 1) == XEXP (op1, 1))
10383 enum machine_mode mode = GET_MODE (op0);
10384 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10385 int shift_count = INTVAL (XEXP (op0, 1));
10387 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10388 mask &= (mask >> shift_count) << shift_count;
10389 else if (GET_CODE (op0) == ASHIFT)
10390 mask = (mask & (mask << shift_count)) >> shift_count;
10392 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10393 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10394 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10399 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10400 SUBREGs are of the same mode, and, in both cases, the AND would
10401 be redundant if the comparison was done in the narrower mode,
10402 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10403 and the operand's possibly nonzero bits are 0xffffff01; in that case
10404 if we only care about QImode, we don't need the AND). This case
10405 occurs if the output mode of an scc insn is not SImode and
10406 STORE_FLAG_VALUE == 1 (e.g., the 386).
10408 Similarly, check for a case where the AND's are ZERO_EXTEND
10409 operations from some narrower mode even though a SUBREG is not
10412 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10413 && CONST_INT_P (XEXP (op0, 1))
10414 && CONST_INT_P (XEXP (op1, 1)))
10416 rtx inner_op0 = XEXP (op0, 0);
10417 rtx inner_op1 = XEXP (op1, 0);
10418 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10419 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10422 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10423 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10424 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10425 && (GET_MODE (SUBREG_REG (inner_op0))
10426 == GET_MODE (SUBREG_REG (inner_op1)))
10427 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10428 <= HOST_BITS_PER_WIDE_INT)
10429 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10430 GET_MODE (SUBREG_REG (inner_op0)))))
10431 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10432 GET_MODE (SUBREG_REG (inner_op1))))))
10434 op0 = SUBREG_REG (inner_op0);
10435 op1 = SUBREG_REG (inner_op1);
10437 /* The resulting comparison is always unsigned since we masked
10438 off the original sign bit. */
10439 code = unsigned_condition (code);
10445 for (tmode = GET_CLASS_NARROWEST_MODE
10446 (GET_MODE_CLASS (GET_MODE (op0)));
10447 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10448 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10450 op0 = gen_lowpart (tmode, inner_op0);
10451 op1 = gen_lowpart (tmode, inner_op1);
10452 code = unsigned_condition (code);
10461 /* If both operands are NOT, we can strip off the outer operation
10462 and adjust the comparison code for swapped operands; similarly for
10463 NEG, except that this must be an equality comparison. */
10464 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10465 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10466 && (code == EQ || code == NE)))
10467 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10473 /* If the first operand is a constant, swap the operands and adjust the
10474 comparison code appropriately, but don't do this if the second operand
10475 is already a constant integer. */
10476 if (swap_commutative_operands_p (op0, op1))
10478 tem = op0, op0 = op1, op1 = tem;
10479 code = swap_condition (code);
10482 /* We now enter a loop during which we will try to simplify the comparison.
10483 For the most part, we only are concerned with comparisons with zero,
10484 but some things may really be comparisons with zero but not start
10485 out looking that way. */
10487 while (CONST_INT_P (op1))
10489 enum machine_mode mode = GET_MODE (op0);
10490 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10491 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10492 int equality_comparison_p;
10493 int sign_bit_comparison_p;
10494 int unsigned_comparison_p;
10495 HOST_WIDE_INT const_op;
10497 /* We only want to handle integral modes. This catches VOIDmode,
10498 CCmode, and the floating-point modes. An exception is that we
10499 can handle VOIDmode if OP0 is a COMPARE or a comparison
10502 if (GET_MODE_CLASS (mode) != MODE_INT
10503 && ! (mode == VOIDmode
10504 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10507 /* Get the constant we are comparing against and turn off all bits
10508 not on in our mode. */
10509 const_op = INTVAL (op1);
10510 if (mode != VOIDmode)
10511 const_op = trunc_int_for_mode (const_op, mode);
10512 op1 = GEN_INT (const_op);
10514 /* If we are comparing against a constant power of two and the value
10515 being compared can only have that single bit nonzero (e.g., it was
10516 `and'ed with that bit), we can replace this with a comparison
10519 && (code == EQ || code == NE || code == GE || code == GEU
10520 || code == LT || code == LTU)
10521 && mode_width <= HOST_BITS_PER_WIDE_INT
10522 && exact_log2 (const_op) >= 0
10523 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10525 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10526 op1 = const0_rtx, const_op = 0;
10529 /* Similarly, if we are comparing a value known to be either -1 or
10530 0 with -1, change it to the opposite comparison against zero. */
10533 && (code == EQ || code == NE || code == GT || code == LE
10534 || code == GEU || code == LTU)
10535 && num_sign_bit_copies (op0, mode) == mode_width)
10537 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10538 op1 = const0_rtx, const_op = 0;
10541 /* Do some canonicalizations based on the comparison code. We prefer
10542 comparisons against zero and then prefer equality comparisons.
10543 If we can reduce the size of a constant, we will do that too. */
10548 /* < C is equivalent to <= (C - 1) */
10552 op1 = GEN_INT (const_op);
10554 /* ... fall through to LE case below. */
10560 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10564 op1 = GEN_INT (const_op);
10568 /* If we are doing a <= 0 comparison on a value known to have
10569 a zero sign bit, we can replace this with == 0. */
10570 else if (const_op == 0
10571 && mode_width <= HOST_BITS_PER_WIDE_INT
10572 && (nonzero_bits (op0, mode)
10573 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10578 /* >= C is equivalent to > (C - 1). */
10582 op1 = GEN_INT (const_op);
10584 /* ... fall through to GT below. */
10590 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10594 op1 = GEN_INT (const_op);
10598 /* If we are doing a > 0 comparison on a value known to have
10599 a zero sign bit, we can replace this with != 0. */
10600 else if (const_op == 0
10601 && mode_width <= HOST_BITS_PER_WIDE_INT
10602 && (nonzero_bits (op0, mode)
10603 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10608 /* < C is equivalent to <= (C - 1). */
10612 op1 = GEN_INT (const_op);
10614 /* ... fall through ... */
10617 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10618 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10619 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10621 const_op = 0, op1 = const0_rtx;
10629 /* unsigned <= 0 is equivalent to == 0 */
10633 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10634 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10635 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10637 const_op = 0, op1 = const0_rtx;
10643 /* >= C is equivalent to > (C - 1). */
10647 op1 = GEN_INT (const_op);
10649 /* ... fall through ... */
10652 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10653 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10654 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10656 const_op = 0, op1 = const0_rtx;
10664 /* unsigned > 0 is equivalent to != 0 */
10668 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10669 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10670 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10672 const_op = 0, op1 = const0_rtx;
10681 /* Compute some predicates to simplify code below. */
10683 equality_comparison_p = (code == EQ || code == NE);
10684 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10685 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10688 /* If this is a sign bit comparison and we can do arithmetic in
10689 MODE, say that we will only be needing the sign bit of OP0. */
10690 if (sign_bit_comparison_p
10691 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10692 op0 = force_to_mode (op0, mode,
10694 << (GET_MODE_BITSIZE (mode) - 1)),
10697 /* Now try cases based on the opcode of OP0. If none of the cases
10698 does a "continue", we exit this loop immediately after the
10701 switch (GET_CODE (op0))
10704 /* If we are extracting a single bit from a variable position in
10705 a constant that has only a single bit set and are comparing it
10706 with zero, we can convert this into an equality comparison
10707 between the position and the location of the single bit. */
10708 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10709 have already reduced the shift count modulo the word size. */
10710 if (!SHIFT_COUNT_TRUNCATED
10711 && CONST_INT_P (XEXP (op0, 0))
10712 && XEXP (op0, 1) == const1_rtx
10713 && equality_comparison_p && const_op == 0
10714 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10716 if (BITS_BIG_ENDIAN)
10718 enum machine_mode new_mode
10719 = mode_for_extraction (EP_extzv, 1);
10720 if (new_mode == MAX_MACHINE_MODE)
10721 i = BITS_PER_WORD - 1 - i;
10725 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10729 op0 = XEXP (op0, 2);
10733 /* Result is nonzero iff shift count is equal to I. */
10734 code = reverse_condition (code);
10738 /* ... fall through ... */
10741 tem = expand_compound_operation (op0);
10750 /* If testing for equality, we can take the NOT of the constant. */
10751 if (equality_comparison_p
10752 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10754 op0 = XEXP (op0, 0);
10759 /* If just looking at the sign bit, reverse the sense of the
10761 if (sign_bit_comparison_p)
10763 op0 = XEXP (op0, 0);
10764 code = (code == GE ? LT : GE);
10770 /* If testing for equality, we can take the NEG of the constant. */
10771 if (equality_comparison_p
10772 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10774 op0 = XEXP (op0, 0);
10779 /* The remaining cases only apply to comparisons with zero. */
10783 /* When X is ABS or is known positive,
10784 (neg X) is < 0 if and only if X != 0. */
10786 if (sign_bit_comparison_p
10787 && (GET_CODE (XEXP (op0, 0)) == ABS
10788 || (mode_width <= HOST_BITS_PER_WIDE_INT
10789 && (nonzero_bits (XEXP (op0, 0), mode)
10790 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10792 op0 = XEXP (op0, 0);
10793 code = (code == LT ? NE : EQ);
10797 /* If we have NEG of something whose two high-order bits are the
10798 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10799 if (num_sign_bit_copies (op0, mode) >= 2)
10801 op0 = XEXP (op0, 0);
10802 code = swap_condition (code);
10808 /* If we are testing equality and our count is a constant, we
10809 can perform the inverse operation on our RHS. */
10810 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10811 && (tem = simplify_binary_operation (ROTATERT, mode,
10812 op1, XEXP (op0, 1))) != 0)
10814 op0 = XEXP (op0, 0);
10819 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10820 a particular bit. Convert it to an AND of a constant of that
10821 bit. This will be converted into a ZERO_EXTRACT. */
10822 if (const_op == 0 && sign_bit_comparison_p
10823 && CONST_INT_P (XEXP (op0, 1))
10824 && mode_width <= HOST_BITS_PER_WIDE_INT)
10826 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10829 - INTVAL (XEXP (op0, 1)))));
10830 code = (code == LT ? NE : EQ);
10834 /* Fall through. */
10837 /* ABS is ignorable inside an equality comparison with zero. */
10838 if (const_op == 0 && equality_comparison_p)
10840 op0 = XEXP (op0, 0);
10846 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10847 (compare FOO CONST) if CONST fits in FOO's mode and we
10848 are either testing inequality or have an unsigned
10849 comparison with ZERO_EXTEND or a signed comparison with
10850 SIGN_EXTEND. But don't do it if we don't have a compare
10851 insn of the given mode, since we'd have to revert it
10852 later on, and then we wouldn't know whether to sign- or
10854 mode = GET_MODE (XEXP (op0, 0));
10855 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10856 && ! unsigned_comparison_p
10857 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10858 && ((unsigned HOST_WIDE_INT) const_op
10859 < (((unsigned HOST_WIDE_INT) 1
10860 << (GET_MODE_BITSIZE (mode) - 1))))
10861 && have_insn_for (COMPARE, mode))
10863 op0 = XEXP (op0, 0);
10869 /* Check for the case where we are comparing A - C1 with C2, that is
10871 (subreg:MODE (plus (A) (-C1))) op (C2)
10873 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10874 comparison in the wider mode. One of the following two conditions
10875 must be true in order for this to be valid:
10877 1. The mode extension results in the same bit pattern being added
10878 on both sides and the comparison is equality or unsigned. As
10879 C2 has been truncated to fit in MODE, the pattern can only be
10882 2. The mode extension results in the sign bit being copied on
10885 The difficulty here is that we have predicates for A but not for
10886 (A - C1) so we need to check that C1 is within proper bounds so
10887 as to perturbate A as little as possible. */
10889 if (mode_width <= HOST_BITS_PER_WIDE_INT
10890 && subreg_lowpart_p (op0)
10891 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10892 && GET_CODE (SUBREG_REG (op0)) == PLUS
10893 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10895 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10896 rtx a = XEXP (SUBREG_REG (op0), 0);
10897 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10900 && (unsigned HOST_WIDE_INT) c1
10901 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10902 && (equality_comparison_p || unsigned_comparison_p)
10903 /* (A - C1) zero-extends if it is positive and sign-extends
10904 if it is negative, C2 both zero- and sign-extends. */
10905 && ((0 == (nonzero_bits (a, inner_mode)
10906 & ~GET_MODE_MASK (mode))
10908 /* (A - C1) sign-extends if it is positive and 1-extends
10909 if it is negative, C2 both sign- and 1-extends. */
10910 || (num_sign_bit_copies (a, inner_mode)
10911 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10914 || ((unsigned HOST_WIDE_INT) c1
10915 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10916 /* (A - C1) always sign-extends, like C2. */
10917 && num_sign_bit_copies (a, inner_mode)
10918 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10919 - (mode_width - 1))))
10921 op0 = SUBREG_REG (op0);
10926 /* If the inner mode is narrower and we are extracting the low part,
10927 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10928 if (subreg_lowpart_p (op0)
10929 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10930 /* Fall through */ ;
10934 /* ... fall through ... */
10937 mode = GET_MODE (XEXP (op0, 0));
10938 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10939 && (unsigned_comparison_p || equality_comparison_p)
10940 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10941 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10942 && have_insn_for (COMPARE, mode))
10944 op0 = XEXP (op0, 0);
10950 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10951 this for equality comparisons due to pathological cases involving
10953 if (equality_comparison_p
10954 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10955 op1, XEXP (op0, 1))))
10957 op0 = XEXP (op0, 0);
10962 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10963 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10964 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10966 op0 = XEXP (XEXP (op0, 0), 0);
10967 code = (code == LT ? EQ : NE);
10973 /* We used to optimize signed comparisons against zero, but that
10974 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10975 arrive here as equality comparisons, or (GEU, LTU) are
10976 optimized away. No need to special-case them. */
10978 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10979 (eq B (minus A C)), whichever simplifies. We can only do
10980 this for equality comparisons due to pathological cases involving
10982 if (equality_comparison_p
10983 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10984 XEXP (op0, 1), op1)))
10986 op0 = XEXP (op0, 0);
10991 if (equality_comparison_p
10992 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10993 XEXP (op0, 0), op1)))
10995 op0 = XEXP (op0, 1);
11000 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11001 of bits in X minus 1, is one iff X > 0. */
11002 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11003 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11004 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
11006 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11008 op0 = XEXP (op0, 1);
11009 code = (code == GE ? LE : GT);
11015 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11016 if C is zero or B is a constant. */
11017 if (equality_comparison_p
11018 && 0 != (tem = simplify_binary_operation (XOR, mode,
11019 XEXP (op0, 1), op1)))
11021 op0 = XEXP (op0, 0);
11028 case UNEQ: case LTGT:
11029 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11030 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11031 case UNORDERED: case ORDERED:
11032 /* We can't do anything if OP0 is a condition code value, rather
11033 than an actual data value. */
11035 || CC0_P (XEXP (op0, 0))
11036 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11039 /* Get the two operands being compared. */
11040 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11041 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11043 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11045 /* Check for the cases where we simply want the result of the
11046 earlier test or the opposite of that result. */
11047 if (code == NE || code == EQ
11048 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11049 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11050 && (STORE_FLAG_VALUE
11051 & (((HOST_WIDE_INT) 1
11052 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11053 && (code == LT || code == GE)))
11055 enum rtx_code new_code;
11056 if (code == LT || code == NE)
11057 new_code = GET_CODE (op0);
11059 new_code = reversed_comparison_code (op0, NULL);
11061 if (new_code != UNKNOWN)
11072 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11074 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11075 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11076 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11078 op0 = XEXP (op0, 1);
11079 code = (code == GE ? GT : LE);
11085 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11086 will be converted to a ZERO_EXTRACT later. */
11087 if (const_op == 0 && equality_comparison_p
11088 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11089 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11091 op0 = simplify_and_const_int
11092 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
11094 XEXP (XEXP (op0, 0), 1)),
11095 (HOST_WIDE_INT) 1);
11099 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11100 zero and X is a comparison and C1 and C2 describe only bits set
11101 in STORE_FLAG_VALUE, we can compare with X. */
11102 if (const_op == 0 && equality_comparison_p
11103 && mode_width <= HOST_BITS_PER_WIDE_INT
11104 && CONST_INT_P (XEXP (op0, 1))
11105 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11106 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11107 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11108 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11110 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11111 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11112 if ((~STORE_FLAG_VALUE & mask) == 0
11113 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11114 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11115 && COMPARISON_P (tem))))
11117 op0 = XEXP (XEXP (op0, 0), 0);
11122 /* If we are doing an equality comparison of an AND of a bit equal
11123 to the sign bit, replace this with a LT or GE comparison of
11124 the underlying value. */
11125 if (equality_comparison_p
11127 && CONST_INT_P (XEXP (op0, 1))
11128 && mode_width <= HOST_BITS_PER_WIDE_INT
11129 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11130 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11132 op0 = XEXP (op0, 0);
11133 code = (code == EQ ? GE : LT);
11137 /* If this AND operation is really a ZERO_EXTEND from a narrower
11138 mode, the constant fits within that mode, and this is either an
11139 equality or unsigned comparison, try to do this comparison in
11144 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11145 -> (ne:DI (reg:SI 4) (const_int 0))
11147 unless TRULY_NOOP_TRUNCATION allows it or the register is
11148 known to hold a value of the required mode the
11149 transformation is invalid. */
11150 if ((equality_comparison_p || unsigned_comparison_p)
11151 && CONST_INT_P (XEXP (op0, 1))
11152 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
11153 & GET_MODE_MASK (mode))
11155 && const_op >> i == 0
11156 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11157 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11158 GET_MODE_BITSIZE (GET_MODE (op0)))
11159 || (REG_P (XEXP (op0, 0))
11160 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11162 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11166 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11167 fits in both M1 and M2 and the SUBREG is either paradoxical
11168 or represents the low part, permute the SUBREG and the AND
11170 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11172 unsigned HOST_WIDE_INT c1;
11173 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11174 /* Require an integral mode, to avoid creating something like
11176 if (SCALAR_INT_MODE_P (tmode)
11177 /* It is unsafe to commute the AND into the SUBREG if the
11178 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11179 not defined. As originally written the upper bits
11180 have a defined value due to the AND operation.
11181 However, if we commute the AND inside the SUBREG then
11182 they no longer have defined values and the meaning of
11183 the code has been changed. */
11185 #ifdef WORD_REGISTER_OPERATIONS
11186 || (mode_width > GET_MODE_BITSIZE (tmode)
11187 && mode_width <= BITS_PER_WORD)
11189 || (mode_width <= GET_MODE_BITSIZE (tmode)
11190 && subreg_lowpart_p (XEXP (op0, 0))))
11191 && CONST_INT_P (XEXP (op0, 1))
11192 && mode_width <= HOST_BITS_PER_WIDE_INT
11193 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11194 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11195 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11197 && c1 != GET_MODE_MASK (tmode))
11199 op0 = simplify_gen_binary (AND, tmode,
11200 SUBREG_REG (XEXP (op0, 0)),
11201 gen_int_mode (c1, tmode));
11202 op0 = gen_lowpart (mode, op0);
11207 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11208 if (const_op == 0 && equality_comparison_p
11209 && XEXP (op0, 1) == const1_rtx
11210 && GET_CODE (XEXP (op0, 0)) == NOT)
11212 op0 = simplify_and_const_int
11213 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
11214 code = (code == NE ? EQ : NE);
11218 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11219 (eq (and (lshiftrt X) 1) 0).
11220 Also handle the case where (not X) is expressed using xor. */
11221 if (const_op == 0 && equality_comparison_p
11222 && XEXP (op0, 1) == const1_rtx
11223 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11225 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11226 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11228 if (GET_CODE (shift_op) == NOT
11229 || (GET_CODE (shift_op) == XOR
11230 && CONST_INT_P (XEXP (shift_op, 1))
11231 && CONST_INT_P (shift_count)
11232 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11233 && (INTVAL (XEXP (shift_op, 1))
11234 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
11236 op0 = simplify_and_const_int
11238 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
11239 (HOST_WIDE_INT) 1);
11240 code = (code == NE ? EQ : NE);
11247 /* If we have (compare (ashift FOO N) (const_int C)) and
11248 the high order N bits of FOO (N+1 if an inequality comparison)
11249 are known to be zero, we can do this by comparing FOO with C
11250 shifted right N bits so long as the low-order N bits of C are
11252 if (CONST_INT_P (XEXP (op0, 1))
11253 && INTVAL (XEXP (op0, 1)) >= 0
11254 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11255 < HOST_BITS_PER_WIDE_INT)
11257 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11258 && mode_width <= HOST_BITS_PER_WIDE_INT
11259 && (nonzero_bits (XEXP (op0, 0), mode)
11260 & ~(mask >> (INTVAL (XEXP (op0, 1))
11261 + ! equality_comparison_p))) == 0)
11263 /* We must perform a logical shift, not an arithmetic one,
11264 as we want the top N bits of C to be zero. */
11265 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11267 temp >>= INTVAL (XEXP (op0, 1));
11268 op1 = gen_int_mode (temp, mode);
11269 op0 = XEXP (op0, 0);
11273 /* If we are doing a sign bit comparison, it means we are testing
11274 a particular bit. Convert it to the appropriate AND. */
11275 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11276 && mode_width <= HOST_BITS_PER_WIDE_INT)
11278 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11281 - INTVAL (XEXP (op0, 1)))));
11282 code = (code == LT ? NE : EQ);
11286 /* If this an equality comparison with zero and we are shifting
11287 the low bit to the sign bit, we can convert this to an AND of the
11289 if (const_op == 0 && equality_comparison_p
11290 && CONST_INT_P (XEXP (op0, 1))
11291 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11294 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11295 (HOST_WIDE_INT) 1);
11301 /* If this is an equality comparison with zero, we can do this
11302 as a logical shift, which might be much simpler. */
11303 if (equality_comparison_p && const_op == 0
11304 && CONST_INT_P (XEXP (op0, 1)))
11306 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11308 INTVAL (XEXP (op0, 1)));
11312 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11313 do the comparison in a narrower mode. */
11314 if (! unsigned_comparison_p
11315 && CONST_INT_P (XEXP (op0, 1))
11316 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11317 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11318 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11319 MODE_INT, 1)) != BLKmode
11320 && (((unsigned HOST_WIDE_INT) const_op
11321 + (GET_MODE_MASK (tmode) >> 1) + 1)
11322 <= GET_MODE_MASK (tmode)))
11324 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11328 /* Likewise if OP0 is a PLUS of a sign extension with a
11329 constant, which is usually represented with the PLUS
11330 between the shifts. */
11331 if (! unsigned_comparison_p
11332 && CONST_INT_P (XEXP (op0, 1))
11333 && GET_CODE (XEXP (op0, 0)) == PLUS
11334 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11335 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11336 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11337 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11338 MODE_INT, 1)) != BLKmode
11339 && (((unsigned HOST_WIDE_INT) const_op
11340 + (GET_MODE_MASK (tmode) >> 1) + 1)
11341 <= GET_MODE_MASK (tmode)))
11343 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11344 rtx add_const = XEXP (XEXP (op0, 0), 1);
11345 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11346 add_const, XEXP (op0, 1));
11348 op0 = simplify_gen_binary (PLUS, tmode,
11349 gen_lowpart (tmode, inner),
11354 /* ... fall through ... */
11356 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11357 the low order N bits of FOO are known to be zero, we can do this
11358 by comparing FOO with C shifted left N bits so long as no
11359 overflow occurs. */
11360 if (CONST_INT_P (XEXP (op0, 1))
11361 && INTVAL (XEXP (op0, 1)) >= 0
11362 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11363 && mode_width <= HOST_BITS_PER_WIDE_INT
11364 && (nonzero_bits (XEXP (op0, 0), mode)
11365 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11366 && (((unsigned HOST_WIDE_INT) const_op
11367 + (GET_CODE (op0) != LSHIFTRT
11368 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11371 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11373 /* If the shift was logical, then we must make the condition
11375 if (GET_CODE (op0) == LSHIFTRT)
11376 code = unsigned_condition (code);
11378 const_op <<= INTVAL (XEXP (op0, 1));
11379 op1 = GEN_INT (const_op);
11380 op0 = XEXP (op0, 0);
11384 /* If we are using this shift to extract just the sign bit, we
11385 can replace this with an LT or GE comparison. */
11387 && (equality_comparison_p || sign_bit_comparison_p)
11388 && CONST_INT_P (XEXP (op0, 1))
11389 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11392 op0 = XEXP (op0, 0);
11393 code = (code == NE || code == GT ? LT : GE);
11405 /* Now make any compound operations involved in this comparison. Then,
11406 check for an outmost SUBREG on OP0 that is not doing anything or is
11407 paradoxical. The latter transformation must only be performed when
11408 it is known that the "extra" bits will be the same in op0 and op1 or
11409 that they don't matter. There are three cases to consider:
11411 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11412 care bits and we can assume they have any convenient value. So
11413 making the transformation is safe.
11415 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11416 In this case the upper bits of op0 are undefined. We should not make
11417 the simplification in that case as we do not know the contents of
11420 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11421 UNKNOWN. In that case we know those bits are zeros or ones. We must
11422 also be sure that they are the same as the upper bits of op1.
11424 We can never remove a SUBREG for a non-equality comparison because
11425 the sign bit is in a different place in the underlying object. */
11427 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11428 op1 = make_compound_operation (op1, SET);
11430 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11431 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11432 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11433 && (code == NE || code == EQ))
11435 if (GET_MODE_SIZE (GET_MODE (op0))
11436 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11438 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11440 if (REG_P (SUBREG_REG (op0)))
11442 op0 = SUBREG_REG (op0);
11443 op1 = gen_lowpart (GET_MODE (op0), op1);
11446 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11447 <= HOST_BITS_PER_WIDE_INT)
11448 && (nonzero_bits (SUBREG_REG (op0),
11449 GET_MODE (SUBREG_REG (op0)))
11450 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11452 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11454 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11455 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11456 op0 = SUBREG_REG (op0), op1 = tem;
11460 /* We now do the opposite procedure: Some machines don't have compare
11461 insns in all modes. If OP0's mode is an integer mode smaller than a
11462 word and we can't do a compare in that mode, see if there is a larger
11463 mode for which we can do the compare. There are a number of cases in
11464 which we can use the wider mode. */
11466 mode = GET_MODE (op0);
11467 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11468 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11469 && ! have_insn_for (COMPARE, mode))
11470 for (tmode = GET_MODE_WIDER_MODE (mode);
11472 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11473 tmode = GET_MODE_WIDER_MODE (tmode))
11474 if (have_insn_for (COMPARE, tmode))
11478 /* If this is a test for negative, we can make an explicit
11479 test of the sign bit. Test this first so we can use
11480 a paradoxical subreg to extend OP0. */
11482 if (op1 == const0_rtx && (code == LT || code == GE)
11483 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11485 op0 = simplify_gen_binary (AND, tmode,
11486 gen_lowpart (tmode, op0),
11487 GEN_INT ((HOST_WIDE_INT) 1
11488 << (GET_MODE_BITSIZE (mode)
11490 code = (code == LT) ? NE : EQ;
11494 /* If the only nonzero bits in OP0 and OP1 are those in the
11495 narrower mode and this is an equality or unsigned comparison,
11496 we can use the wider mode. Similarly for sign-extended
11497 values, in which case it is true for all comparisons. */
11498 zero_extended = ((code == EQ || code == NE
11499 || code == GEU || code == GTU
11500 || code == LEU || code == LTU)
11501 && (nonzero_bits (op0, tmode)
11502 & ~GET_MODE_MASK (mode)) == 0
11503 && ((CONST_INT_P (op1)
11504 || (nonzero_bits (op1, tmode)
11505 & ~GET_MODE_MASK (mode)) == 0)));
11508 || ((num_sign_bit_copies (op0, tmode)
11509 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11510 - GET_MODE_BITSIZE (mode)))
11511 && (num_sign_bit_copies (op1, tmode)
11512 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11513 - GET_MODE_BITSIZE (mode)))))
11515 /* If OP0 is an AND and we don't have an AND in MODE either,
11516 make a new AND in the proper mode. */
11517 if (GET_CODE (op0) == AND
11518 && !have_insn_for (AND, mode))
11519 op0 = simplify_gen_binary (AND, tmode,
11520 gen_lowpart (tmode,
11522 gen_lowpart (tmode,
11528 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
11529 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
11533 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
11534 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
11541 #ifdef CANONICALIZE_COMPARISON
11542 /* If this machine only supports a subset of valid comparisons, see if we
11543 can convert an unsupported one into a supported one. */
11544 CANONICALIZE_COMPARISON (code, op0, op1);
11553 /* Utility function for record_value_for_reg. Count number of
11558 enum rtx_code code = GET_CODE (x);
11562 if (GET_RTX_CLASS (code) == '2'
11563 || GET_RTX_CLASS (code) == 'c')
11565 rtx x0 = XEXP (x, 0);
11566 rtx x1 = XEXP (x, 1);
11569 return 1 + 2 * count_rtxs (x0);
11571 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11572 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11573 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11574 return 2 + 2 * count_rtxs (x0)
11575 + count_rtxs (x == XEXP (x1, 0)
11576 ? XEXP (x1, 1) : XEXP (x1, 0));
11578 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11579 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11580 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11581 return 2 + 2 * count_rtxs (x1)
11582 + count_rtxs (x == XEXP (x0, 0)
11583 ? XEXP (x0, 1) : XEXP (x0, 0));
11586 fmt = GET_RTX_FORMAT (code);
11587 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11589 ret += count_rtxs (XEXP (x, i));
11590 else if (fmt[i] == 'E')
11591 for (j = 0; j < XVECLEN (x, i); j++)
11592 ret += count_rtxs (XVECEXP (x, i, j));
11597 /* Utility function for following routine. Called when X is part of a value
11598 being stored into last_set_value. Sets last_set_table_tick
11599 for each register mentioned. Similar to mention_regs in cse.c */
11602 update_table_tick (rtx x)
11604 enum rtx_code code = GET_CODE (x);
11605 const char *fmt = GET_RTX_FORMAT (code);
11610 unsigned int regno = REGNO (x);
11611 unsigned int endregno = END_REGNO (x);
11614 for (r = regno; r < endregno; r++)
11616 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11617 rsp->last_set_table_tick = label_tick;
11623 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11626 /* Check for identical subexpressions. If x contains
11627 identical subexpression we only have to traverse one of
11629 if (i == 0 && ARITHMETIC_P (x))
11631 /* Note that at this point x1 has already been
11633 rtx x0 = XEXP (x, 0);
11634 rtx x1 = XEXP (x, 1);
11636 /* If x0 and x1 are identical then there is no need to
11641 /* If x0 is identical to a subexpression of x1 then while
11642 processing x1, x0 has already been processed. Thus we
11643 are done with x. */
11644 if (ARITHMETIC_P (x1)
11645 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11648 /* If x1 is identical to a subexpression of x0 then we
11649 still have to process the rest of x0. */
11650 if (ARITHMETIC_P (x0)
11651 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11653 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11658 update_table_tick (XEXP (x, i));
11660 else if (fmt[i] == 'E')
11661 for (j = 0; j < XVECLEN (x, i); j++)
11662 update_table_tick (XVECEXP (x, i, j));
11665 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11666 are saying that the register is clobbered and we no longer know its
11667 value. If INSN is zero, don't update reg_stat[].last_set; this is
11668 only permitted with VALUE also zero and is used to invalidate the
11672 record_value_for_reg (rtx reg, rtx insn, rtx value)
11674 unsigned int regno = REGNO (reg);
11675 unsigned int endregno = END_REGNO (reg);
11677 reg_stat_type *rsp;
11679 /* If VALUE contains REG and we have a previous value for REG, substitute
11680 the previous value. */
11681 if (value && insn && reg_overlap_mentioned_p (reg, value))
11685 /* Set things up so get_last_value is allowed to see anything set up to
11687 subst_low_luid = DF_INSN_LUID (insn);
11688 tem = get_last_value (reg);
11690 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11691 it isn't going to be useful and will take a lot of time to process,
11692 so just use the CLOBBER. */
11696 if (ARITHMETIC_P (tem)
11697 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11698 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11699 tem = XEXP (tem, 0);
11700 else if (count_occurrences (value, reg, 1) >= 2)
11702 /* If there are two or more occurrences of REG in VALUE,
11703 prevent the value from growing too much. */
11704 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11705 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11708 value = replace_rtx (copy_rtx (value), reg, tem);
11712 /* For each register modified, show we don't know its value, that
11713 we don't know about its bitwise content, that its value has been
11714 updated, and that we don't know the location of the death of the
11716 for (i = regno; i < endregno; i++)
11718 rsp = VEC_index (reg_stat_type, reg_stat, i);
11721 rsp->last_set = insn;
11723 rsp->last_set_value = 0;
11724 rsp->last_set_mode = VOIDmode;
11725 rsp->last_set_nonzero_bits = 0;
11726 rsp->last_set_sign_bit_copies = 0;
11727 rsp->last_death = 0;
11728 rsp->truncated_to_mode = VOIDmode;
11731 /* Mark registers that are being referenced in this value. */
11733 update_table_tick (value);
11735 /* Now update the status of each register being set.
11736 If someone is using this register in this block, set this register
11737 to invalid since we will get confused between the two lives in this
11738 basic block. This makes using this register always invalid. In cse, we
11739 scan the table to invalidate all entries using this register, but this
11740 is too much work for us. */
11742 for (i = regno; i < endregno; i++)
11744 rsp = VEC_index (reg_stat_type, reg_stat, i);
11745 rsp->last_set_label = label_tick;
11747 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11748 rsp->last_set_invalid = 1;
11750 rsp->last_set_invalid = 0;
11753 /* The value being assigned might refer to X (like in "x++;"). In that
11754 case, we must replace it with (clobber (const_int 0)) to prevent
11756 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11757 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
11759 value = copy_rtx (value);
11760 if (!get_last_value_validate (&value, insn, label_tick, 1))
11764 /* For the main register being modified, update the value, the mode, the
11765 nonzero bits, and the number of sign bit copies. */
11767 rsp->last_set_value = value;
11771 enum machine_mode mode = GET_MODE (reg);
11772 subst_low_luid = DF_INSN_LUID (insn);
11773 rsp->last_set_mode = mode;
11774 if (GET_MODE_CLASS (mode) == MODE_INT
11775 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11776 mode = nonzero_bits_mode;
11777 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11778 rsp->last_set_sign_bit_copies
11779 = num_sign_bit_copies (value, GET_MODE (reg));
11783 /* Called via note_stores from record_dead_and_set_regs to handle one
11784 SET or CLOBBER in an insn. DATA is the instruction in which the
11785 set is occurring. */
11788 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11790 rtx record_dead_insn = (rtx) data;
11792 if (GET_CODE (dest) == SUBREG)
11793 dest = SUBREG_REG (dest);
11795 if (!record_dead_insn)
11798 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11804 /* If we are setting the whole register, we know its value. Otherwise
11805 show that we don't know the value. We can handle SUBREG in
11807 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11808 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11809 else if (GET_CODE (setter) == SET
11810 && GET_CODE (SET_DEST (setter)) == SUBREG
11811 && SUBREG_REG (SET_DEST (setter)) == dest
11812 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11813 && subreg_lowpart_p (SET_DEST (setter)))
11814 record_value_for_reg (dest, record_dead_insn,
11815 gen_lowpart (GET_MODE (dest),
11816 SET_SRC (setter)));
11818 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11820 else if (MEM_P (dest)
11821 /* Ignore pushes, they clobber nothing. */
11822 && ! push_operand (dest, GET_MODE (dest)))
11823 mem_last_set = DF_INSN_LUID (record_dead_insn);
11826 /* Update the records of when each REG was most recently set or killed
11827 for the things done by INSN. This is the last thing done in processing
11828 INSN in the combiner loop.
11830 We update reg_stat[], in particular fields last_set, last_set_value,
11831 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11832 last_death, and also the similar information mem_last_set (which insn
11833 most recently modified memory) and last_call_luid (which insn was the
11834 most recent subroutine call). */
11837 record_dead_and_set_regs (rtx insn)
11842 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11844 if (REG_NOTE_KIND (link) == REG_DEAD
11845 && REG_P (XEXP (link, 0)))
11847 unsigned int regno = REGNO (XEXP (link, 0));
11848 unsigned int endregno = END_REGNO (XEXP (link, 0));
11850 for (i = regno; i < endregno; i++)
11852 reg_stat_type *rsp;
11854 rsp = VEC_index (reg_stat_type, reg_stat, i);
11855 rsp->last_death = insn;
11858 else if (REG_NOTE_KIND (link) == REG_INC)
11859 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11864 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11865 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11867 reg_stat_type *rsp;
11869 rsp = VEC_index (reg_stat_type, reg_stat, i);
11870 rsp->last_set_invalid = 1;
11871 rsp->last_set = insn;
11872 rsp->last_set_value = 0;
11873 rsp->last_set_mode = VOIDmode;
11874 rsp->last_set_nonzero_bits = 0;
11875 rsp->last_set_sign_bit_copies = 0;
11876 rsp->last_death = 0;
11877 rsp->truncated_to_mode = VOIDmode;
11880 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11882 /* We can't combine into a call pattern. Remember, though, that
11883 the return value register is set at this LUID. We could
11884 still replace a register with the return value from the
11885 wrong subroutine call! */
11886 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11889 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11892 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11893 register present in the SUBREG, so for each such SUBREG go back and
11894 adjust nonzero and sign bit information of the registers that are
11895 known to have some zero/sign bits set.
11897 This is needed because when combine blows the SUBREGs away, the
11898 information on zero/sign bits is lost and further combines can be
11899 missed because of that. */
11902 record_promoted_value (rtx insn, rtx subreg)
11905 unsigned int regno = REGNO (SUBREG_REG (subreg));
11906 enum machine_mode mode = GET_MODE (subreg);
11908 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11911 for (links = LOG_LINKS (insn); links;)
11913 reg_stat_type *rsp;
11915 insn = XEXP (links, 0);
11916 set = single_set (insn);
11918 if (! set || !REG_P (SET_DEST (set))
11919 || REGNO (SET_DEST (set)) != regno
11920 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11922 links = XEXP (links, 1);
11926 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11927 if (rsp->last_set == insn)
11929 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11930 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11933 if (REG_P (SET_SRC (set)))
11935 regno = REGNO (SET_SRC (set));
11936 links = LOG_LINKS (insn);
11943 /* Check if X, a register, is known to contain a value already
11944 truncated to MODE. In this case we can use a subreg to refer to
11945 the truncated value even though in the generic case we would need
11946 an explicit truncation. */
11949 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11951 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11952 enum machine_mode truncated = rsp->truncated_to_mode;
11955 || rsp->truncation_label < label_tick_ebb_start)
11957 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11959 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11960 GET_MODE_BITSIZE (truncated)))
11965 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11966 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11967 might be able to turn a truncate into a subreg using this information.
11968 Return -1 if traversing *P is complete or 0 otherwise. */
11971 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11974 enum machine_mode truncated_mode;
11975 reg_stat_type *rsp;
11977 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11979 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11980 truncated_mode = GET_MODE (x);
11982 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11985 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11986 GET_MODE_BITSIZE (original_mode)))
11989 x = SUBREG_REG (x);
11991 /* ??? For hard-regs we now record everything. We might be able to
11992 optimize this using last_set_mode. */
11993 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11994 truncated_mode = GET_MODE (x);
11998 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11999 if (rsp->truncated_to_mode == 0
12000 || rsp->truncation_label < label_tick_ebb_start
12001 || (GET_MODE_SIZE (truncated_mode)
12002 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12004 rsp->truncated_to_mode = truncated_mode;
12005 rsp->truncation_label = label_tick;
12011 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12012 the modes they are used in. This can help truning TRUNCATEs into
12016 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12018 for_each_rtx (x, record_truncated_value, NULL);
12021 /* Scan X for promoted SUBREGs. For each one found,
12022 note what it implies to the registers used in it. */
12025 check_promoted_subreg (rtx insn, rtx x)
12027 if (GET_CODE (x) == SUBREG
12028 && SUBREG_PROMOTED_VAR_P (x)
12029 && REG_P (SUBREG_REG (x)))
12030 record_promoted_value (insn, x);
12033 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12036 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12040 check_promoted_subreg (insn, XEXP (x, i));
12044 if (XVEC (x, i) != 0)
12045 for (j = 0; j < XVECLEN (x, i); j++)
12046 check_promoted_subreg (insn, XVECEXP (x, i, j));
12052 /* Verify that all the registers and memory references mentioned in *LOC are
12053 still valid. *LOC was part of a value set in INSN when label_tick was
12054 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12055 the invalid references with (clobber (const_int 0)) and return 1. This
12056 replacement is useful because we often can get useful information about
12057 the form of a value (e.g., if it was produced by a shift that always
12058 produces -1 or 0) even though we don't know exactly what registers it
12059 was produced from. */
12062 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12065 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12066 int len = GET_RTX_LENGTH (GET_CODE (x));
12071 unsigned int regno = REGNO (x);
12072 unsigned int endregno = END_REGNO (x);
12075 for (j = regno; j < endregno; j++)
12077 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12078 if (rsp->last_set_invalid
12079 /* If this is a pseudo-register that was only set once and not
12080 live at the beginning of the function, it is always valid. */
12081 || (! (regno >= FIRST_PSEUDO_REGISTER
12082 && REG_N_SETS (regno) == 1
12083 && (!REGNO_REG_SET_P
12084 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12085 && rsp->last_set_label > tick))
12088 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12095 /* If this is a memory reference, make sure that there were no stores after
12096 it that might have clobbered the value. We don't have alias info, so we
12097 assume any store invalidates it. Moreover, we only have local UIDs, so
12098 we also assume that there were stores in the intervening basic blocks. */
12099 else if (MEM_P (x) && !MEM_READONLY_P (x)
12100 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12103 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12107 for (i = 0; i < len; i++)
12111 /* Check for identical subexpressions. If x contains
12112 identical subexpression we only have to traverse one of
12114 if (i == 1 && ARITHMETIC_P (x))
12116 /* Note that at this point x0 has already been checked
12117 and found valid. */
12118 rtx x0 = XEXP (x, 0);
12119 rtx x1 = XEXP (x, 1);
12121 /* If x0 and x1 are identical then x is also valid. */
12125 /* If x1 is identical to a subexpression of x0 then
12126 while checking x0, x1 has already been checked. Thus
12127 it is valid and so as x. */
12128 if (ARITHMETIC_P (x0)
12129 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12132 /* If x0 is identical to a subexpression of x1 then x is
12133 valid iff the rest of x1 is valid. */
12134 if (ARITHMETIC_P (x1)
12135 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12137 get_last_value_validate (&XEXP (x1,
12138 x0 == XEXP (x1, 0) ? 1 : 0),
12139 insn, tick, replace);
12142 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12146 else if (fmt[i] == 'E')
12147 for (j = 0; j < XVECLEN (x, i); j++)
12148 if (get_last_value_validate (&XVECEXP (x, i, j),
12149 insn, tick, replace) == 0)
12153 /* If we haven't found a reason for it to be invalid, it is valid. */
12157 /* Get the last value assigned to X, if known. Some registers
12158 in the value may be replaced with (clobber (const_int 0)) if their value
12159 is known longer known reliably. */
12162 get_last_value (const_rtx x)
12164 unsigned int regno;
12166 reg_stat_type *rsp;
12168 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12169 then convert it to the desired mode. If this is a paradoxical SUBREG,
12170 we cannot predict what values the "extra" bits might have. */
12171 if (GET_CODE (x) == SUBREG
12172 && subreg_lowpart_p (x)
12173 && (GET_MODE_SIZE (GET_MODE (x))
12174 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12175 && (value = get_last_value (SUBREG_REG (x))) != 0)
12176 return gen_lowpart (GET_MODE (x), value);
12182 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12183 value = rsp->last_set_value;
12185 /* If we don't have a value, or if it isn't for this basic block and
12186 it's either a hard register, set more than once, or it's a live
12187 at the beginning of the function, return 0.
12189 Because if it's not live at the beginning of the function then the reg
12190 is always set before being used (is never used without being set).
12191 And, if it's set only once, and it's always set before use, then all
12192 uses must have the same last value, even if it's not from this basic
12196 || (rsp->last_set_label < label_tick_ebb_start
12197 && (regno < FIRST_PSEUDO_REGISTER
12198 || REG_N_SETS (regno) != 1
12200 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12203 /* If the value was set in a later insn than the ones we are processing,
12204 we can't use it even if the register was only set once. */
12205 if (rsp->last_set_label == label_tick
12206 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12209 /* If the value has all its registers valid, return it. */
12210 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12213 /* Otherwise, make a copy and replace any invalid register with
12214 (clobber (const_int 0)). If that fails for some reason, return 0. */
12216 value = copy_rtx (value);
12217 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12223 /* Return nonzero if expression X refers to a REG or to memory
12224 that is set in an instruction more recent than FROM_LUID. */
12227 use_crosses_set_p (const_rtx x, int from_luid)
12231 enum rtx_code code = GET_CODE (x);
12235 unsigned int regno = REGNO (x);
12236 unsigned endreg = END_REGNO (x);
12238 #ifdef PUSH_ROUNDING
12239 /* Don't allow uses of the stack pointer to be moved,
12240 because we don't know whether the move crosses a push insn. */
12241 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12244 for (; regno < endreg; regno++)
12246 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12248 && rsp->last_set_label == label_tick
12249 && DF_INSN_LUID (rsp->last_set) > from_luid)
12255 if (code == MEM && mem_last_set > from_luid)
12258 fmt = GET_RTX_FORMAT (code);
12260 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12265 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12266 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12269 else if (fmt[i] == 'e'
12270 && use_crosses_set_p (XEXP (x, i), from_luid))
12276 /* Define three variables used for communication between the following
12279 static unsigned int reg_dead_regno, reg_dead_endregno;
12280 static int reg_dead_flag;
12282 /* Function called via note_stores from reg_dead_at_p.
12284 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12285 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12288 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12290 unsigned int regno, endregno;
12295 regno = REGNO (dest);
12296 endregno = END_REGNO (dest);
12297 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12298 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12301 /* Return nonzero if REG is known to be dead at INSN.
12303 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12304 referencing REG, it is dead. If we hit a SET referencing REG, it is
12305 live. Otherwise, see if it is live or dead at the start of the basic
12306 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12307 must be assumed to be always live. */
12310 reg_dead_at_p (rtx reg, rtx insn)
12315 /* Set variables for reg_dead_at_p_1. */
12316 reg_dead_regno = REGNO (reg);
12317 reg_dead_endregno = END_REGNO (reg);
12321 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12322 we allow the machine description to decide whether use-and-clobber
12323 patterns are OK. */
12324 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12326 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12327 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12331 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12332 beginning of basic block. */
12333 block = BLOCK_FOR_INSN (insn);
12338 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12340 return reg_dead_flag == 1 ? 1 : 0;
12342 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12346 if (insn == BB_HEAD (block))
12349 insn = PREV_INSN (insn);
12352 /* Look at live-in sets for the basic block that we were in. */
12353 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12354 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12360 /* Note hard registers in X that are used. */
12363 mark_used_regs_combine (rtx x)
12365 RTX_CODE code = GET_CODE (x);
12366 unsigned int regno;
12379 case ADDR_DIFF_VEC:
12382 /* CC0 must die in the insn after it is set, so we don't need to take
12383 special note of it here. */
12389 /* If we are clobbering a MEM, mark any hard registers inside the
12390 address as used. */
12391 if (MEM_P (XEXP (x, 0)))
12392 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12397 /* A hard reg in a wide mode may really be multiple registers.
12398 If so, mark all of them just like the first. */
12399 if (regno < FIRST_PSEUDO_REGISTER)
12401 /* None of this applies to the stack, frame or arg pointers. */
12402 if (regno == STACK_POINTER_REGNUM
12403 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12404 || regno == HARD_FRAME_POINTER_REGNUM
12406 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12407 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12409 || regno == FRAME_POINTER_REGNUM)
12412 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12418 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12420 rtx testreg = SET_DEST (x);
12422 while (GET_CODE (testreg) == SUBREG
12423 || GET_CODE (testreg) == ZERO_EXTRACT
12424 || GET_CODE (testreg) == STRICT_LOW_PART)
12425 testreg = XEXP (testreg, 0);
12427 if (MEM_P (testreg))
12428 mark_used_regs_combine (XEXP (testreg, 0));
12430 mark_used_regs_combine (SET_SRC (x));
12438 /* Recursively scan the operands of this expression. */
12441 const char *fmt = GET_RTX_FORMAT (code);
12443 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12446 mark_used_regs_combine (XEXP (x, i));
12447 else if (fmt[i] == 'E')
12451 for (j = 0; j < XVECLEN (x, i); j++)
12452 mark_used_regs_combine (XVECEXP (x, i, j));
12458 /* Remove register number REGNO from the dead registers list of INSN.
12460 Return the note used to record the death, if there was one. */
12463 remove_death (unsigned int regno, rtx insn)
12465 rtx note = find_regno_note (insn, REG_DEAD, regno);
12468 remove_note (insn, note);
12473 /* For each register (hardware or pseudo) used within expression X, if its
12474 death is in an instruction with luid between FROM_LUID (inclusive) and
12475 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12476 list headed by PNOTES.
12478 That said, don't move registers killed by maybe_kill_insn.
12480 This is done when X is being merged by combination into TO_INSN. These
12481 notes will then be distributed as needed. */
12484 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12489 enum rtx_code code = GET_CODE (x);
12493 unsigned int regno = REGNO (x);
12494 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12496 /* Don't move the register if it gets killed in between from and to. */
12497 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12498 && ! reg_referenced_p (x, maybe_kill_insn))
12502 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12503 && DF_INSN_LUID (where_dead) >= from_luid
12504 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12506 rtx note = remove_death (regno, where_dead);
12508 /* It is possible for the call above to return 0. This can occur
12509 when last_death points to I2 or I1 that we combined with.
12510 In that case make a new note.
12512 We must also check for the case where X is a hard register
12513 and NOTE is a death note for a range of hard registers
12514 including X. In that case, we must put REG_DEAD notes for
12515 the remaining registers in place of NOTE. */
12517 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12518 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12519 > GET_MODE_SIZE (GET_MODE (x))))
12521 unsigned int deadregno = REGNO (XEXP (note, 0));
12522 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12523 unsigned int ourend = END_HARD_REGNO (x);
12526 for (i = deadregno; i < deadend; i++)
12527 if (i < regno || i >= ourend)
12528 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12531 /* If we didn't find any note, or if we found a REG_DEAD note that
12532 covers only part of the given reg, and we have a multi-reg hard
12533 register, then to be safe we must check for REG_DEAD notes
12534 for each register other than the first. They could have
12535 their own REG_DEAD notes lying around. */
12536 else if ((note == 0
12538 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12539 < GET_MODE_SIZE (GET_MODE (x)))))
12540 && regno < FIRST_PSEUDO_REGISTER
12541 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12543 unsigned int ourend = END_HARD_REGNO (x);
12544 unsigned int i, offset;
12548 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12552 for (i = regno + offset; i < ourend; i++)
12553 move_deaths (regno_reg_rtx[i],
12554 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12557 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12559 XEXP (note, 1) = *pnotes;
12563 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12569 else if (GET_CODE (x) == SET)
12571 rtx dest = SET_DEST (x);
12573 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12575 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12576 that accesses one word of a multi-word item, some
12577 piece of everything register in the expression is used by
12578 this insn, so remove any old death. */
12579 /* ??? So why do we test for equality of the sizes? */
12581 if (GET_CODE (dest) == ZERO_EXTRACT
12582 || GET_CODE (dest) == STRICT_LOW_PART
12583 || (GET_CODE (dest) == SUBREG
12584 && (((GET_MODE_SIZE (GET_MODE (dest))
12585 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12586 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12587 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12589 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12593 /* If this is some other SUBREG, we know it replaces the entire
12594 value, so use that as the destination. */
12595 if (GET_CODE (dest) == SUBREG)
12596 dest = SUBREG_REG (dest);
12598 /* If this is a MEM, adjust deaths of anything used in the address.
12599 For a REG (the only other possibility), the entire value is
12600 being replaced so the old value is not used in this insn. */
12603 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12608 else if (GET_CODE (x) == CLOBBER)
12611 len = GET_RTX_LENGTH (code);
12612 fmt = GET_RTX_FORMAT (code);
12614 for (i = 0; i < len; i++)
12619 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12620 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12623 else if (fmt[i] == 'e')
12624 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12628 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12629 pattern of an insn. X must be a REG. */
12632 reg_bitfield_target_p (rtx x, rtx body)
12636 if (GET_CODE (body) == SET)
12638 rtx dest = SET_DEST (body);
12640 unsigned int regno, tregno, endregno, endtregno;
12642 if (GET_CODE (dest) == ZERO_EXTRACT)
12643 target = XEXP (dest, 0);
12644 else if (GET_CODE (dest) == STRICT_LOW_PART)
12645 target = SUBREG_REG (XEXP (dest, 0));
12649 if (GET_CODE (target) == SUBREG)
12650 target = SUBREG_REG (target);
12652 if (!REG_P (target))
12655 tregno = REGNO (target), regno = REGNO (x);
12656 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12657 return target == x;
12659 endtregno = end_hard_regno (GET_MODE (target), tregno);
12660 endregno = end_hard_regno (GET_MODE (x), regno);
12662 return endregno > tregno && regno < endtregno;
12665 else if (GET_CODE (body) == PARALLEL)
12666 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12667 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12673 /* Return the next insn after INSN that is neither a NOTE nor a
12674 DEBUG_INSN. This routine does not look inside SEQUENCEs. */
12677 next_nonnote_nondebug_insn (rtx insn)
12681 insn = NEXT_INSN (insn);
12686 if (DEBUG_INSN_P (insn))
12696 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12697 as appropriate. I3 and I2 are the insns resulting from the combination
12698 insns including FROM (I2 may be zero).
12700 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12701 not need REG_DEAD notes because they are being substituted for. This
12702 saves searching in the most common cases.
12704 Each note in the list is either ignored or placed on some insns, depending
12705 on the type of note. */
12708 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12711 rtx note, next_note;
12714 for (note = notes; note; note = next_note)
12716 rtx place = 0, place2 = 0;
12718 next_note = XEXP (note, 1);
12719 switch (REG_NOTE_KIND (note))
12723 /* Doesn't matter much where we put this, as long as it's somewhere.
12724 It is preferable to keep these notes on branches, which is most
12725 likely to be i3. */
12729 case REG_VALUE_PROFILE:
12730 /* Just get rid of this note, as it is unused later anyway. */
12733 case REG_NON_LOCAL_GOTO:
12738 gcc_assert (i2 && JUMP_P (i2));
12743 case REG_EH_REGION:
12744 /* These notes must remain with the call or trapping instruction. */
12747 else if (i2 && CALL_P (i2))
12751 gcc_assert (flag_non_call_exceptions);
12752 if (may_trap_p (i3))
12754 else if (i2 && may_trap_p (i2))
12756 /* ??? Otherwise assume we've combined things such that we
12757 can now prove that the instructions can't trap. Drop the
12758 note in this case. */
12764 /* These notes must remain with the call. It should not be
12765 possible for both I2 and I3 to be a call. */
12770 gcc_assert (i2 && CALL_P (i2));
12776 /* Any clobbers for i3 may still exist, and so we must process
12777 REG_UNUSED notes from that insn.
12779 Any clobbers from i2 or i1 can only exist if they were added by
12780 recog_for_combine. In that case, recog_for_combine created the
12781 necessary REG_UNUSED notes. Trying to keep any original
12782 REG_UNUSED notes from these insns can cause incorrect output
12783 if it is for the same register as the original i3 dest.
12784 In that case, we will notice that the register is set in i3,
12785 and then add a REG_UNUSED note for the destination of i3, which
12786 is wrong. However, it is possible to have REG_UNUSED notes from
12787 i2 or i1 for register which were both used and clobbered, so
12788 we keep notes from i2 or i1 if they will turn into REG_DEAD
12791 /* If this register is set or clobbered in I3, put the note there
12792 unless there is one already. */
12793 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12795 if (from_insn != i3)
12798 if (! (REG_P (XEXP (note, 0))
12799 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12800 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12803 /* Otherwise, if this register is used by I3, then this register
12804 now dies here, so we must put a REG_DEAD note here unless there
12806 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12807 && ! (REG_P (XEXP (note, 0))
12808 ? find_regno_note (i3, REG_DEAD,
12809 REGNO (XEXP (note, 0)))
12810 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12812 PUT_REG_NOTE_KIND (note, REG_DEAD);
12820 /* These notes say something about results of an insn. We can
12821 only support them if they used to be on I3 in which case they
12822 remain on I3. Otherwise they are ignored.
12824 If the note refers to an expression that is not a constant, we
12825 must also ignore the note since we cannot tell whether the
12826 equivalence is still true. It might be possible to do
12827 slightly better than this (we only have a problem if I2DEST
12828 or I1DEST is present in the expression), but it doesn't
12829 seem worth the trouble. */
12831 if (from_insn == i3
12832 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12837 /* These notes say something about how a register is used. They must
12838 be present on any use of the register in I2 or I3. */
12839 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12842 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12851 case REG_LABEL_TARGET:
12852 case REG_LABEL_OPERAND:
12853 /* This can show up in several ways -- either directly in the
12854 pattern, or hidden off in the constant pool with (or without?)
12855 a REG_EQUAL note. */
12856 /* ??? Ignore the without-reg_equal-note problem for now. */
12857 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12858 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12859 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12860 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12864 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12865 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12866 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12867 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12875 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12876 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12878 if (place && JUMP_P (place)
12879 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12880 && (JUMP_LABEL (place) == NULL
12881 || JUMP_LABEL (place) == XEXP (note, 0)))
12883 rtx label = JUMP_LABEL (place);
12886 JUMP_LABEL (place) = XEXP (note, 0);
12887 else if (LABEL_P (label))
12888 LABEL_NUSES (label)--;
12891 if (place2 && JUMP_P (place2)
12892 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12893 && (JUMP_LABEL (place2) == NULL
12894 || JUMP_LABEL (place2) == XEXP (note, 0)))
12896 rtx label = JUMP_LABEL (place2);
12899 JUMP_LABEL (place2) = XEXP (note, 0);
12900 else if (LABEL_P (label))
12901 LABEL_NUSES (label)--;
12907 /* This note says something about the value of a register prior
12908 to the execution of an insn. It is too much trouble to see
12909 if the note is still correct in all situations. It is better
12910 to simply delete it. */
12914 /* If we replaced the right hand side of FROM_INSN with a
12915 REG_EQUAL note, the original use of the dying register
12916 will not have been combined into I3 and I2. In such cases,
12917 FROM_INSN is guaranteed to be the first of the combined
12918 instructions, so we simply need to search back before
12919 FROM_INSN for the previous use or set of this register,
12920 then alter the notes there appropriately.
12922 If the register is used as an input in I3, it dies there.
12923 Similarly for I2, if it is nonzero and adjacent to I3.
12925 If the register is not used as an input in either I3 or I2
12926 and it is not one of the registers we were supposed to eliminate,
12927 there are two possibilities. We might have a non-adjacent I2
12928 or we might have somehow eliminated an additional register
12929 from a computation. For example, we might have had A & B where
12930 we discover that B will always be zero. In this case we will
12931 eliminate the reference to A.
12933 In both cases, we must search to see if we can find a previous
12934 use of A and put the death note there. */
12937 && from_insn == i2mod
12938 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12943 && CALL_P (from_insn)
12944 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12946 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12948 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
12949 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12951 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12953 && reg_overlap_mentioned_p (XEXP (note, 0),
12955 || rtx_equal_p (XEXP (note, 0), elim_i1))
12962 basic_block bb = this_basic_block;
12964 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12966 if (!NONDEBUG_INSN_P (tem))
12968 if (tem == BB_HEAD (bb))
12973 /* If the register is being set at TEM, see if that is all
12974 TEM is doing. If so, delete TEM. Otherwise, make this
12975 into a REG_UNUSED note instead. Don't delete sets to
12976 global register vars. */
12977 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12978 || !global_regs[REGNO (XEXP (note, 0))])
12979 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12981 rtx set = single_set (tem);
12982 rtx inner_dest = 0;
12984 rtx cc0_setter = NULL_RTX;
12988 for (inner_dest = SET_DEST (set);
12989 (GET_CODE (inner_dest) == STRICT_LOW_PART
12990 || GET_CODE (inner_dest) == SUBREG
12991 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12992 inner_dest = XEXP (inner_dest, 0))
12995 /* Verify that it was the set, and not a clobber that
12996 modified the register.
12998 CC0 targets must be careful to maintain setter/user
12999 pairs. If we cannot delete the setter due to side
13000 effects, mark the user with an UNUSED note instead
13003 if (set != 0 && ! side_effects_p (SET_SRC (set))
13004 && rtx_equal_p (XEXP (note, 0), inner_dest)
13006 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13007 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13008 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13012 /* Move the notes and links of TEM elsewhere.
13013 This might delete other dead insns recursively.
13014 First set the pattern to something that won't use
13016 rtx old_notes = REG_NOTES (tem);
13018 PATTERN (tem) = pc_rtx;
13019 REG_NOTES (tem) = NULL;
13021 distribute_notes (old_notes, tem, tem, NULL_RTX,
13022 NULL_RTX, NULL_RTX);
13023 distribute_links (LOG_LINKS (tem));
13025 SET_INSN_DELETED (tem);
13030 /* Delete the setter too. */
13033 PATTERN (cc0_setter) = pc_rtx;
13034 old_notes = REG_NOTES (cc0_setter);
13035 REG_NOTES (cc0_setter) = NULL;
13037 distribute_notes (old_notes, cc0_setter,
13038 cc0_setter, NULL_RTX,
13039 NULL_RTX, NULL_RTX);
13040 distribute_links (LOG_LINKS (cc0_setter));
13042 SET_INSN_DELETED (cc0_setter);
13043 if (cc0_setter == i2)
13050 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13052 /* If there isn't already a REG_UNUSED note, put one
13053 here. Do not place a REG_DEAD note, even if
13054 the register is also used here; that would not
13055 match the algorithm used in lifetime analysis
13056 and can cause the consistency check in the
13057 scheduler to fail. */
13058 if (! find_regno_note (tem, REG_UNUSED,
13059 REGNO (XEXP (note, 0))))
13064 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13066 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13070 /* If we are doing a 3->2 combination, and we have a
13071 register which formerly died in i3 and was not used
13072 by i2, which now no longer dies in i3 and is used in
13073 i2 but does not die in i2, and place is between i2
13074 and i3, then we may need to move a link from place to
13076 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13078 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13079 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13081 rtx links = LOG_LINKS (place);
13082 LOG_LINKS (place) = 0;
13083 distribute_links (links);
13088 if (tem == BB_HEAD (bb))
13094 /* If the register is set or already dead at PLACE, we needn't do
13095 anything with this note if it is still a REG_DEAD note.
13096 We check here if it is set at all, not if is it totally replaced,
13097 which is what `dead_or_set_p' checks, so also check for it being
13100 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13102 unsigned int regno = REGNO (XEXP (note, 0));
13103 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13105 if (dead_or_set_p (place, XEXP (note, 0))
13106 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13108 /* Unless the register previously died in PLACE, clear
13109 last_death. [I no longer understand why this is
13111 if (rsp->last_death != place)
13112 rsp->last_death = 0;
13116 rsp->last_death = place;
13118 /* If this is a death note for a hard reg that is occupying
13119 multiple registers, ensure that we are still using all
13120 parts of the object. If we find a piece of the object
13121 that is unused, we must arrange for an appropriate REG_DEAD
13122 note to be added for it. However, we can't just emit a USE
13123 and tag the note to it, since the register might actually
13124 be dead; so we recourse, and the recursive call then finds
13125 the previous insn that used this register. */
13127 if (place && regno < FIRST_PSEUDO_REGISTER
13128 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13130 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13134 for (i = regno; i < endregno; i++)
13135 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13136 && ! find_regno_fusage (place, USE, i))
13137 || dead_or_set_regno_p (place, i))
13142 /* Put only REG_DEAD notes for pieces that are
13143 not already dead or set. */
13145 for (i = regno; i < endregno;
13146 i += hard_regno_nregs[i][reg_raw_mode[i]])
13148 rtx piece = regno_reg_rtx[i];
13149 basic_block bb = this_basic_block;
13151 if (! dead_or_set_p (place, piece)
13152 && ! reg_bitfield_target_p (piece,
13155 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13158 distribute_notes (new_note, place, place,
13159 NULL_RTX, NULL_RTX, NULL_RTX);
13161 else if (! refers_to_regno_p (i, i + 1,
13162 PATTERN (place), 0)
13163 && ! find_regno_fusage (place, USE, i))
13164 for (tem = PREV_INSN (place); ;
13165 tem = PREV_INSN (tem))
13167 if (!NONDEBUG_INSN_P (tem))
13169 if (tem == BB_HEAD (bb))
13173 if (dead_or_set_p (tem, piece)
13174 || reg_bitfield_target_p (piece,
13177 add_reg_note (tem, REG_UNUSED, piece);
13191 /* Any other notes should not be present at this point in the
13193 gcc_unreachable ();
13198 XEXP (note, 1) = REG_NOTES (place);
13199 REG_NOTES (place) = note;
13203 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13207 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13208 I3, I2, and I1 to new locations. This is also called to add a link
13209 pointing at I3 when I3's destination is changed. */
13212 distribute_links (rtx links)
13214 rtx link, next_link;
13216 for (link = links; link; link = next_link)
13222 next_link = XEXP (link, 1);
13224 /* If the insn that this link points to is a NOTE or isn't a single
13225 set, ignore it. In the latter case, it isn't clear what we
13226 can do other than ignore the link, since we can't tell which
13227 register it was for. Such links wouldn't be used by combine
13230 It is not possible for the destination of the target of the link to
13231 have been changed by combine. The only potential of this is if we
13232 replace I3, I2, and I1 by I3 and I2. But in that case the
13233 destination of I2 also remains unchanged. */
13235 if (NOTE_P (XEXP (link, 0))
13236 || (set = single_set (XEXP (link, 0))) == 0)
13239 reg = SET_DEST (set);
13240 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13241 || GET_CODE (reg) == STRICT_LOW_PART)
13242 reg = XEXP (reg, 0);
13244 /* A LOG_LINK is defined as being placed on the first insn that uses
13245 a register and points to the insn that sets the register. Start
13246 searching at the next insn after the target of the link and stop
13247 when we reach a set of the register or the end of the basic block.
13249 Note that this correctly handles the link that used to point from
13250 I3 to I2. Also note that not much searching is typically done here
13251 since most links don't point very far away. */
13253 for (insn = NEXT_INSN (XEXP (link, 0));
13254 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13255 || BB_HEAD (this_basic_block->next_bb) != insn));
13256 insn = NEXT_INSN (insn))
13257 if (DEBUG_INSN_P (insn))
13259 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13261 if (reg_referenced_p (reg, PATTERN (insn)))
13265 else if (CALL_P (insn)
13266 && find_reg_fusage (insn, USE, reg))
13271 else if (INSN_P (insn) && reg_set_p (reg, insn))
13274 /* If we found a place to put the link, place it there unless there
13275 is already a link to the same insn as LINK at that point. */
13281 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13282 if (XEXP (link2, 0) == XEXP (link, 0))
13287 XEXP (link, 1) = LOG_LINKS (place);
13288 LOG_LINKS (place) = link;
13290 /* Set added_links_insn to the earliest insn we added a
13292 if (added_links_insn == 0
13293 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13294 added_links_insn = place;
13300 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13301 Check whether the expression pointer to by LOC is a register or
13302 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13303 Otherwise return zero. */
13306 unmentioned_reg_p_1 (rtx *loc, void *expr)
13311 && (REG_P (x) || MEM_P (x))
13312 && ! reg_mentioned_p (x, (rtx) expr))
13317 /* Check for any register or memory mentioned in EQUIV that is not
13318 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13319 of EXPR where some registers may have been replaced by constants. */
13322 unmentioned_reg_p (rtx equiv, rtx expr)
13324 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13328 dump_combine_stats (FILE *file)
13332 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13333 combine_attempts, combine_merges, combine_extras, combine_successes);
13337 dump_combine_total_stats (FILE *file)
13341 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13342 total_attempts, total_merges, total_extras, total_successes);
13346 gate_handle_combine (void)
13348 return (optimize > 0);
13351 /* Try combining insns through substitution. */
13352 static unsigned int
13353 rest_of_handle_combine (void)
13355 int rebuild_jump_labels_after_combine;
13357 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13358 df_note_add_problem ();
13361 regstat_init_n_sets_and_refs ();
13363 rebuild_jump_labels_after_combine
13364 = combine_instructions (get_insns (), max_reg_num ());
13366 /* Combining insns may have turned an indirect jump into a
13367 direct jump. Rebuild the JUMP_LABEL fields of jumping
13369 if (rebuild_jump_labels_after_combine)
13371 timevar_push (TV_JUMP);
13372 rebuild_jump_labels (get_insns ());
13374 timevar_pop (TV_JUMP);
13377 regstat_free_n_sets_and_refs ();
13381 struct rtl_opt_pass pass_combine =
13385 "combine", /* name */
13386 gate_handle_combine, /* gate */
13387 rest_of_handle_combine, /* execute */
13390 0, /* static_pass_number */
13391 TV_COMBINE, /* tv_id */
13392 PROP_cfglayout, /* properties_required */
13393 0, /* properties_provided */
13394 0, /* properties_destroyed */
13395 0, /* todo_flags_start */
13397 TODO_df_finish | TODO_verify_rtl_sharing |
13398 TODO_ggc_collect, /* todo_flags_finish */