1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
140 /* Maximum register number, which is the size of the tables below. */
142 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* A bitmap indicating which blocks had registers go dead at entry.
199 After combine, we'll need to re-do global life analysis with
200 those blocks as starting points. */
201 static sbitmap refresh_blocks;
202 static int need_refresh;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if a
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to non-zero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is non-zero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set non-zero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set non-zero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; unsigned int i;} old_contents;
318 union {rtx *r; unsigned int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST PARAMS ((rtx *, rtx));
342 static void do_SUBST_INT PARAMS ((unsigned int *,
344 static void init_reg_last_arrays PARAMS ((void));
345 static void setup_incoming_promotions PARAMS ((void));
346 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
347 static int cant_combine_insn_p PARAMS ((rtx));
348 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
349 static int sets_function_arg_p PARAMS ((rtx));
350 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
351 static int contains_muldiv PARAMS ((rtx));
352 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
353 static void undo_all PARAMS ((void));
354 static void undo_commit PARAMS ((void));
355 static rtx *find_split_point PARAMS ((rtx *, rtx));
356 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
357 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
358 static rtx simplify_if_then_else PARAMS ((rtx));
359 static rtx simplify_set PARAMS ((rtx));
360 static rtx simplify_logical PARAMS ((rtx, int));
361 static rtx expand_compound_operation PARAMS ((rtx));
362 static rtx expand_field_assignment PARAMS ((rtx));
363 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
364 rtx, unsigned HOST_WIDE_INT, int,
366 static rtx extract_left_shift PARAMS ((rtx, int));
367 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
368 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
369 unsigned HOST_WIDE_INT *));
370 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
371 unsigned HOST_WIDE_INT, rtx, int));
372 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
373 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
374 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
375 static rtx make_field_assignment PARAMS ((rtx));
376 static rtx apply_distributive_law PARAMS ((rtx));
377 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
378 unsigned HOST_WIDE_INT));
379 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
380 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
381 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
382 enum rtx_code, HOST_WIDE_INT,
383 enum machine_mode, int *));
384 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
386 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
387 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
388 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
390 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
391 static void update_table_tick PARAMS ((rtx));
392 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
393 static void check_promoted_subreg PARAMS ((rtx, rtx));
394 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
395 static void record_dead_and_set_regs PARAMS ((rtx));
396 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
397 static rtx get_last_value PARAMS ((rtx));
398 static int use_crosses_set_p PARAMS ((rtx, int));
399 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
400 static int reg_dead_at_p PARAMS ((rtx, rtx));
401 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
402 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
403 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
404 static void distribute_links PARAMS ((rtx));
405 static void mark_used_regs_combine PARAMS ((rtx));
406 static int insn_cuid PARAMS ((rtx));
407 static void record_promoted_value PARAMS ((rtx, rtx));
408 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
409 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
411 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
412 insn. The substitution can be undone by undo_all. If INTO is already
413 set to NEWVAL, do not record this change. Because computing NEWVAL might
414 also call SUBST, we have to compute it before we put anything into
418 do_SUBST (into, newval)
424 if (oldval == newval)
428 buf = undobuf.frees, undobuf.frees = buf->next;
430 buf = (struct undo *) xmalloc (sizeof (struct undo));
434 buf->old_contents.r = oldval;
437 buf->next = undobuf.undos, undobuf.undos = buf;
440 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
442 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
443 for the value of a HOST_WIDE_INT value (including CONST_INT) is
447 do_SUBST_INT (into, newval)
448 unsigned int *into, newval;
451 unsigned int oldval = *into;
453 if (oldval == newval)
457 buf = undobuf.frees, undobuf.frees = buf->next;
459 buf = (struct undo *) xmalloc (sizeof (struct undo));
463 buf->old_contents.i = oldval;
466 buf->next = undobuf.undos, undobuf.undos = buf;
469 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
471 /* Main entry point for combiner. F is the first insn of the function.
472 NREGS is the first unused pseudo-reg number.
474 Return non-zero if the combiner has turned an indirect jump
475 instruction into a direct jump. */
477 combine_instructions (f, nregs)
486 rtx links, nextlinks;
488 int new_direct_jump_p = 0;
490 combine_attempts = 0;
493 combine_successes = 0;
495 combine_max_regno = nregs;
497 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
498 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
500 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
502 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
503 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
504 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
505 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
506 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
507 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
509 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
510 reg_last_set_nonzero_bits
511 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
512 reg_last_set_sign_bit_copies
513 = (char *) xmalloc (nregs * sizeof (char));
515 init_reg_last_arrays ();
517 init_recog_no_volatile ();
519 /* Compute maximum uid value so uid_cuid can be allocated. */
521 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
522 if (INSN_UID (insn) > i)
525 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
528 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
530 /* Don't use reg_nonzero_bits when computing it. This can cause problems
531 when, for example, we have j <<= 1 in a loop. */
533 nonzero_sign_valid = 0;
535 /* Compute the mapping from uids to cuids.
536 Cuids are numbers assigned to insns, like uids,
537 except that cuids increase monotonically through the code.
539 Scan all SETs and see if we can deduce anything about what
540 bits are known to be zero for some registers and how many copies
541 of the sign bit are known to exist for those registers.
543 Also set any known values so that we can use it while searching
544 for what bits are known to be set. */
548 /* We need to initialize it here, because record_dead_and_set_regs may call
550 subst_prev_insn = NULL_RTX;
552 setup_incoming_promotions ();
554 refresh_blocks = sbitmap_alloc (n_basic_blocks);
555 sbitmap_zero (refresh_blocks);
558 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
560 uid_cuid[INSN_UID (insn)] = ++i;
566 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
568 record_dead_and_set_regs (insn);
571 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
572 if (REG_NOTE_KIND (links) == REG_INC)
573 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
578 if (GET_CODE (insn) == CODE_LABEL)
582 nonzero_sign_valid = 1;
584 /* Now scan all the insns in forward order. */
586 this_basic_block = -1;
590 init_reg_last_arrays ();
591 setup_incoming_promotions ();
593 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
597 /* If INSN starts a new basic block, update our basic block number. */
598 if (this_basic_block + 1 < n_basic_blocks
599 && BLOCK_HEAD (this_basic_block + 1) == insn)
602 if (GET_CODE (insn) == CODE_LABEL)
605 else if (INSN_P (insn))
607 /* See if we know about function return values before this
608 insn based upon SUBREG flags. */
609 check_promoted_subreg (insn, PATTERN (insn));
611 /* Try this insn with each insn it links back to. */
613 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
614 if ((next = try_combine (insn, XEXP (links, 0),
615 NULL_RTX, &new_direct_jump_p)) != 0)
618 /* Try each sequence of three linked insns ending with this one. */
620 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
622 rtx link = XEXP (links, 0);
624 /* If the linked insn has been replaced by a note, then there
625 is no point in pursuing this chain any further. */
626 if (GET_CODE (link) == NOTE)
629 for (nextlinks = LOG_LINKS (link);
631 nextlinks = XEXP (nextlinks, 1))
632 if ((next = try_combine (insn, XEXP (links, 0),
634 &new_direct_jump_p)) != 0)
639 /* Try to combine a jump insn that uses CC0
640 with a preceding insn that sets CC0, and maybe with its
641 logical predecessor as well.
642 This is how we make decrement-and-branch insns.
643 We need this special code because data flow connections
644 via CC0 do not get entered in LOG_LINKS. */
646 if (GET_CODE (insn) == JUMP_INSN
647 && (prev = prev_nonnote_insn (insn)) != 0
648 && GET_CODE (prev) == INSN
649 && sets_cc0_p (PATTERN (prev)))
651 if ((next = try_combine (insn, prev,
652 NULL_RTX, &new_direct_jump_p)) != 0)
655 for (nextlinks = LOG_LINKS (prev); nextlinks;
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, prev,
659 &new_direct_jump_p)) != 0)
663 /* Do the same for an insn that explicitly references CC0. */
664 if (GET_CODE (insn) == INSN
665 && (prev = prev_nonnote_insn (insn)) != 0
666 && GET_CODE (prev) == INSN
667 && sets_cc0_p (PATTERN (prev))
668 && GET_CODE (PATTERN (insn)) == SET
669 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
671 if ((next = try_combine (insn, prev,
672 NULL_RTX, &new_direct_jump_p)) != 0)
675 for (nextlinks = LOG_LINKS (prev); nextlinks;
676 nextlinks = XEXP (nextlinks, 1))
677 if ((next = try_combine (insn, prev,
679 &new_direct_jump_p)) != 0)
683 /* Finally, see if any of the insns that this insn links to
684 explicitly references CC0. If so, try this insn, that insn,
685 and its predecessor if it sets CC0. */
686 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
687 if (GET_CODE (XEXP (links, 0)) == INSN
688 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
689 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
690 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && (next = try_combine (insn, XEXP (links, 0),
694 prev, &new_direct_jump_p)) != 0)
698 /* Try combining an insn with two different insns whose results it
700 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
701 for (nextlinks = XEXP (links, 1); nextlinks;
702 nextlinks = XEXP (nextlinks, 1))
703 if ((next = try_combine (insn, XEXP (links, 0),
705 &new_direct_jump_p)) != 0)
708 if (GET_CODE (insn) != NOTE)
709 record_dead_and_set_regs (insn);
716 delete_noop_moves (f);
720 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
725 sbitmap_free (refresh_blocks);
726 free (reg_nonzero_bits);
727 free (reg_sign_bit_copies);
728 free (reg_last_death);
730 free (reg_last_set_value);
731 free (reg_last_set_table_tick);
732 free (reg_last_set_label);
733 free (reg_last_set_invalid);
734 free (reg_last_set_mode);
735 free (reg_last_set_nonzero_bits);
736 free (reg_last_set_sign_bit_copies);
740 struct undo *undo, *next;
741 for (undo = undobuf.frees; undo; undo = next)
749 total_attempts += combine_attempts;
750 total_merges += combine_merges;
751 total_extras += combine_extras;
752 total_successes += combine_successes;
754 nonzero_sign_valid = 0;
756 /* Make recognizer allow volatile MEMs again. */
759 return new_direct_jump_p;
762 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
765 init_reg_last_arrays ()
767 unsigned int nregs = combine_max_regno;
769 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
770 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
771 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
772 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
773 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
774 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
775 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
776 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
777 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
780 /* Set up any promoted values for incoming argument registers. */
783 setup_incoming_promotions ()
785 #ifdef PROMOTE_FUNCTION_ARGS
788 enum machine_mode mode;
790 rtx first = get_insns ();
792 #ifndef OUTGOING_REGNO
793 #define OUTGOING_REGNO(N) N
795 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
796 /* Check whether this register can hold an incoming pointer
797 argument. FUNCTION_ARG_REGNO_P tests outgoing register
798 numbers, so translate if necessary due to register windows. */
799 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
800 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
803 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
806 gen_rtx_CLOBBER (mode, const0_rtx)));
811 /* Called via note_stores. If X is a pseudo that is narrower than
812 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
814 If we are setting only a portion of X and we can't figure out what
815 portion, assume all bits will be used since we don't know what will
818 Similarly, set how many bits of X are known to be copies of the sign bit
819 at all locations in the function. This is the smallest number implied
823 set_nonzero_bits_and_sign_copies (x, set, data)
826 void *data ATTRIBUTE_UNUSED;
830 if (GET_CODE (x) == REG
831 && REGNO (x) >= FIRST_PSEUDO_REGISTER
832 /* If this register is undefined at the start of the file, we can't
833 say what its contents were. */
834 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
835 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
837 if (set == 0 || GET_CODE (set) == CLOBBER)
839 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
840 reg_sign_bit_copies[REGNO (x)] = 1;
844 /* If this is a complex assignment, see if we can convert it into a
845 simple assignment. */
846 set = expand_field_assignment (set);
848 /* If this is a simple assignment, or we have a paradoxical SUBREG,
849 set what we know about X. */
851 if (SET_DEST (set) == x
852 || (GET_CODE (SET_DEST (set)) == SUBREG
853 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
855 && SUBREG_REG (SET_DEST (set)) == x))
857 rtx src = SET_SRC (set);
859 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
860 /* If X is narrower than a word and SRC is a non-negative
861 constant that would appear negative in the mode of X,
862 sign-extend it for use in reg_nonzero_bits because some
863 machines (maybe most) will actually do the sign-extension
864 and this is the conservative approach.
866 ??? For 2.5, try to tighten up the MD files in this regard
867 instead of this kludge. */
869 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
870 && GET_CODE (src) == CONST_INT
872 && 0 != (INTVAL (src)
874 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
875 src = GEN_INT (INTVAL (src)
876 | ((HOST_WIDE_INT) (-1)
877 << GET_MODE_BITSIZE (GET_MODE (x))));
880 reg_nonzero_bits[REGNO (x)]
881 |= nonzero_bits (src, nonzero_bits_mode);
882 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
883 if (reg_sign_bit_copies[REGNO (x)] == 0
884 || reg_sign_bit_copies[REGNO (x)] > num)
885 reg_sign_bit_copies[REGNO (x)] = num;
889 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
890 reg_sign_bit_copies[REGNO (x)] = 1;
895 /* See if INSN can be combined into I3. PRED and SUCC are optionally
896 insns that were previously combined into I3 or that will be combined
897 into the merger of INSN and I3.
899 Return 0 if the combination is not allowed for any reason.
901 If the combination is allowed, *PDEST will be set to the single
902 destination of INSN and *PSRC to the single source, and this function
906 can_combine_p (insn, i3, pred, succ, pdest, psrc)
909 rtx pred ATTRIBUTE_UNUSED;
914 rtx set = 0, src, dest;
919 int all_adjacent = (succ ? (next_active_insn (insn) == succ
920 && next_active_insn (succ) == i3)
921 : next_active_insn (insn) == i3);
923 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
924 or a PARALLEL consisting of such a SET and CLOBBERs.
926 If INSN has CLOBBER parallel parts, ignore them for our processing.
927 By definition, these happen during the execution of the insn. When it
928 is merged with another insn, all bets are off. If they are, in fact,
929 needed and aren't also supplied in I3, they may be added by
930 recog_for_combine. Otherwise, it won't match.
932 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
935 Get the source and destination of INSN. If more than one, can't
938 if (GET_CODE (PATTERN (insn)) == SET)
939 set = PATTERN (insn);
940 else if (GET_CODE (PATTERN (insn)) == PARALLEL
941 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
943 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
945 rtx elt = XVECEXP (PATTERN (insn), 0, i);
947 switch (GET_CODE (elt))
949 /* This is important to combine floating point insns
952 /* Combining an isolated USE doesn't make sense.
953 We depend here on combinable_i3_pat to reject them. */
954 /* The code below this loop only verifies that the inputs of
955 the SET in INSN do not change. We call reg_set_between_p
956 to verify that the REG in the USE does not change between
958 If the USE in INSN was for a pseudo register, the matching
959 insn pattern will likely match any register; combining this
960 with any other USE would only be safe if we knew that the
961 used registers have identical values, or if there was
962 something to tell them apart, e.g. different modes. For
963 now, we forgo such complicated tests and simply disallow
964 combining of USES of pseudo registers with any other USE. */
965 if (GET_CODE (XEXP (elt, 0)) == REG
966 && GET_CODE (PATTERN (i3)) == PARALLEL)
968 rtx i3pat = PATTERN (i3);
969 int i = XVECLEN (i3pat, 0) - 1;
970 unsigned int regno = REGNO (XEXP (elt, 0));
974 rtx i3elt = XVECEXP (i3pat, 0, i);
976 if (GET_CODE (i3elt) == USE
977 && GET_CODE (XEXP (i3elt, 0)) == REG
978 && (REGNO (XEXP (i3elt, 0)) == regno
979 ? reg_set_between_p (XEXP (elt, 0),
980 PREV_INSN (insn), i3)
981 : regno >= FIRST_PSEUDO_REGISTER))
988 /* We can ignore CLOBBERs. */
993 /* Ignore SETs whose result isn't used but not those that
994 have side-effects. */
995 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
996 && ! side_effects_p (elt))
999 /* If we have already found a SET, this is a second one and
1000 so we cannot combine with this insn. */
1008 /* Anything else means we can't combine. */
1014 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1015 so don't do anything with it. */
1016 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1025 set = expand_field_assignment (set);
1026 src = SET_SRC (set), dest = SET_DEST (set);
1028 /* Don't eliminate a store in the stack pointer. */
1029 if (dest == stack_pointer_rtx
1030 /* If we couldn't eliminate a field assignment, we can't combine. */
1031 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1032 /* Don't combine with an insn that sets a register to itself if it has
1033 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1034 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1035 /* Can't merge an ASM_OPERANDS. */
1036 || GET_CODE (src) == ASM_OPERANDS
1037 /* Can't merge a function call. */
1038 || GET_CODE (src) == CALL
1039 /* Don't eliminate a function call argument. */
1040 || (GET_CODE (i3) == CALL_INSN
1041 && (find_reg_fusage (i3, USE, dest)
1042 || (GET_CODE (dest) == REG
1043 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1044 && global_regs[REGNO (dest)])))
1045 /* Don't substitute into an incremented register. */
1046 || FIND_REG_INC_NOTE (i3, dest)
1047 || (succ && FIND_REG_INC_NOTE (succ, dest))
1049 /* Don't combine the end of a libcall into anything. */
1050 /* ??? This gives worse code, and appears to be unnecessary, since no
1051 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1052 use REG_RETVAL notes for noconflict blocks, but other code here
1053 makes sure that those insns don't disappear. */
1054 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1056 /* Make sure that DEST is not used after SUCC but before I3. */
1057 || (succ && ! all_adjacent
1058 && reg_used_between_p (dest, succ, i3))
1059 /* Make sure that the value that is to be substituted for the register
1060 does not use any registers whose values alter in between. However,
1061 If the insns are adjacent, a use can't cross a set even though we
1062 think it might (this can happen for a sequence of insns each setting
1063 the same destination; reg_last_set of that register might point to
1064 a NOTE). If INSN has a REG_EQUIV note, the register is always
1065 equivalent to the memory so the substitution is valid even if there
1066 are intervening stores. Also, don't move a volatile asm or
1067 UNSPEC_VOLATILE across any other insns. */
1069 && (((GET_CODE (src) != MEM
1070 || ! find_reg_note (insn, REG_EQUIV, src))
1071 && use_crosses_set_p (src, INSN_CUID (insn)))
1072 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1073 || GET_CODE (src) == UNSPEC_VOLATILE))
1074 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1075 better register allocation by not doing the combine. */
1076 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1077 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1078 /* Don't combine across a CALL_INSN, because that would possibly
1079 change whether the life span of some REGs crosses calls or not,
1080 and it is a pain to update that information.
1081 Exception: if source is a constant, moving it later can't hurt.
1082 Accept that special case, because it helps -fforce-addr a lot. */
1083 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1086 /* DEST must either be a REG or CC0. */
1087 if (GET_CODE (dest) == REG)
1089 /* If register alignment is being enforced for multi-word items in all
1090 cases except for parameters, it is possible to have a register copy
1091 insn referencing a hard register that is not allowed to contain the
1092 mode being copied and which would not be valid as an operand of most
1093 insns. Eliminate this problem by not combining with such an insn.
1095 Also, on some machines we don't want to extend the life of a hard
1098 if (GET_CODE (src) == REG
1099 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1100 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1101 /* Don't extend the life of a hard register unless it is
1102 user variable (if we have few registers) or it can't
1103 fit into the desired register (meaning something special
1105 Also avoid substituting a return register into I3, because
1106 reload can't handle a conflict with constraints of other
1108 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1109 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1112 else if (GET_CODE (dest) != CC0)
1115 /* Don't substitute for a register intended as a clobberable operand.
1116 Similarly, don't substitute an expression containing a register that
1117 will be clobbered in I3. */
1118 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1119 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1120 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1121 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1123 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1126 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1127 or not), reject, unless nothing volatile comes between it and I3 */
1129 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1131 /* Make sure succ doesn't contain a volatile reference. */
1132 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1135 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1136 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1140 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1141 to be an explicit register variable, and was chosen for a reason. */
1143 if (GET_CODE (src) == ASM_OPERANDS
1144 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1147 /* If there are any volatile insns between INSN and I3, reject, because
1148 they might affect machine state. */
1150 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1151 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1154 /* If INSN or I2 contains an autoincrement or autodecrement,
1155 make sure that register is not used between there and I3,
1156 and not already used in I3 either.
1157 Also insist that I3 not be a jump; if it were one
1158 and the incremented register were spilled, we would lose. */
1161 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1162 if (REG_NOTE_KIND (link) == REG_INC
1163 && (GET_CODE (i3) == JUMP_INSN
1164 || reg_used_between_p (XEXP (link, 0), insn, i3)
1165 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1170 /* Don't combine an insn that follows a CC0-setting insn.
1171 An insn that uses CC0 must not be separated from the one that sets it.
1172 We do, however, allow I2 to follow a CC0-setting insn if that insn
1173 is passed as I1; in that case it will be deleted also.
1174 We also allow combining in this case if all the insns are adjacent
1175 because that would leave the two CC0 insns adjacent as well.
1176 It would be more logical to test whether CC0 occurs inside I1 or I2,
1177 but that would be much slower, and this ought to be equivalent. */
1179 p = prev_nonnote_insn (insn);
1180 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1185 /* If we get here, we have passed all the tests and the combination is
1194 /* Check if PAT is an insn - or a part of it - used to set up an
1195 argument for a function in a hard register. */
1198 sets_function_arg_p (pat)
1204 switch (GET_CODE (pat))
1207 return sets_function_arg_p (PATTERN (pat));
1210 for (i = XVECLEN (pat, 0); --i >= 0;)
1211 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1217 inner_dest = SET_DEST (pat);
1218 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1219 || GET_CODE (inner_dest) == SUBREG
1220 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1221 inner_dest = XEXP (inner_dest, 0);
1223 return (GET_CODE (inner_dest) == REG
1224 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1225 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1234 /* LOC is the location within I3 that contains its pattern or the component
1235 of a PARALLEL of the pattern. We validate that it is valid for combining.
1237 One problem is if I3 modifies its output, as opposed to replacing it
1238 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1239 so would produce an insn that is not equivalent to the original insns.
1243 (set (reg:DI 101) (reg:DI 100))
1244 (set (subreg:SI (reg:DI 101) 0) <foo>)
1246 This is NOT equivalent to:
1248 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1249 (set (reg:DI 101) (reg:DI 100))])
1251 Not only does this modify 100 (in which case it might still be valid
1252 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1254 We can also run into a problem if I2 sets a register that I1
1255 uses and I1 gets directly substituted into I3 (not via I2). In that
1256 case, we would be getting the wrong value of I2DEST into I3, so we
1257 must reject the combination. This case occurs when I2 and I1 both
1258 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1259 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1260 of a SET must prevent combination from occurring.
1262 Before doing the above check, we first try to expand a field assignment
1263 into a set of logical operations.
1265 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1266 we place a register that is both set and used within I3. If more than one
1267 such register is detected, we fail.
1269 Return 1 if the combination is valid, zero otherwise. */
1272 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1278 rtx *pi3dest_killed;
1282 if (GET_CODE (x) == SET)
1284 rtx set = expand_field_assignment (x);
1285 rtx dest = SET_DEST (set);
1286 rtx src = SET_SRC (set);
1287 rtx inner_dest = dest;
1290 rtx inner_src = src;
1295 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1296 || GET_CODE (inner_dest) == SUBREG
1297 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1298 inner_dest = XEXP (inner_dest, 0);
1300 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1303 while (GET_CODE (inner_src) == STRICT_LOW_PART
1304 || GET_CODE (inner_src) == SUBREG
1305 || GET_CODE (inner_src) == ZERO_EXTRACT)
1306 inner_src = XEXP (inner_src, 0);
1308 /* If it is better that two different modes keep two different pseudos,
1309 avoid combining them. This avoids producing the following pattern
1311 (set (subreg:SI (reg/v:QI 21) 0)
1312 (lshiftrt:SI (reg/v:SI 20)
1314 If that were made, reload could not handle the pair of
1315 reg 20/21, since it would try to get any GENERAL_REGS
1316 but some of them don't handle QImode. */
1318 if (rtx_equal_p (inner_src, i2dest)
1319 && GET_CODE (inner_dest) == REG
1320 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1324 /* Check for the case where I3 modifies its output, as
1326 if ((inner_dest != dest
1327 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1328 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1330 /* This is the same test done in can_combine_p except we can't test
1331 all_adjacent; we don't have to, since this instruction will stay
1332 in place, thus we are not considering increasing the lifetime of
1335 Also, if this insn sets a function argument, combining it with
1336 something that might need a spill could clobber a previous
1337 function argument; the all_adjacent test in can_combine_p also
1338 checks this; here, we do a more specific test for this case. */
1340 || (GET_CODE (inner_dest) == REG
1341 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1342 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1343 GET_MODE (inner_dest))))
1344 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1347 /* If DEST is used in I3, it is being killed in this insn,
1348 so record that for later.
1349 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1350 STACK_POINTER_REGNUM, since these are always considered to be
1351 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1352 if (pi3dest_killed && GET_CODE (dest) == REG
1353 && reg_referenced_p (dest, PATTERN (i3))
1354 && REGNO (dest) != FRAME_POINTER_REGNUM
1355 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1356 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1358 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1359 && (REGNO (dest) != ARG_POINTER_REGNUM
1360 || ! fixed_regs [REGNO (dest)])
1362 && REGNO (dest) != STACK_POINTER_REGNUM)
1364 if (*pi3dest_killed)
1367 *pi3dest_killed = dest;
1371 else if (GET_CODE (x) == PARALLEL)
1375 for (i = 0; i < XVECLEN (x, 0); i++)
1376 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1377 i1_not_in_src, pi3dest_killed))
1384 /* Return 1 if X is an arithmetic expression that contains a multiplication
1385 and division. We don't count multiplications by powers of two here. */
1391 switch (GET_CODE (x))
1393 case MOD: case DIV: case UMOD: case UDIV:
1397 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1398 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1400 switch (GET_RTX_CLASS (GET_CODE (x)))
1402 case 'c': case '<': case '2':
1403 return contains_muldiv (XEXP (x, 0))
1404 || contains_muldiv (XEXP (x, 1));
1407 return contains_muldiv (XEXP (x, 0));
1415 /* Determine whether INSN can be used in a combination. Return nonzero if
1416 not. This is used in try_combine to detect early some cases where we
1417 can't perform combinations. */
1420 cant_combine_insn_p (insn)
1426 /* If this isn't really an insn, we can't do anything.
1427 This can occur when flow deletes an insn that it has merged into an
1428 auto-increment address. */
1429 if (! INSN_P (insn))
1432 /* Never combine loads and stores involving hard regs. The register
1433 allocator can usually handle such reg-reg moves by tying. If we allow
1434 the combiner to make substitutions of hard regs, we risk aborting in
1435 reload on machines that have SMALL_REGISTER_CLASSES.
1436 As an exception, we allow combinations involving fixed regs; these are
1437 not available to the register allocator so there's no risk involved. */
1439 set = single_set (insn);
1442 src = SET_SRC (set);
1443 dest = SET_DEST (set);
1444 if (GET_CODE (src) == SUBREG)
1445 src = SUBREG_REG (src);
1446 if (GET_CODE (dest) == SUBREG)
1447 dest = SUBREG_REG (dest);
1448 if (REG_P (src) && REG_P (dest)
1449 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1450 && ! fixed_regs[REGNO (src)])
1451 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1452 && ! fixed_regs[REGNO (dest)])))
1458 /* Try to combine the insns I1 and I2 into I3.
1459 Here I1 and I2 appear earlier than I3.
1460 I1 can be zero; then we combine just I2 into I3.
1462 If we are combining three insns and the resulting insn is not recognized,
1463 try splitting it into two insns. If that happens, I2 and I3 are retained
1464 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1467 Return 0 if the combination does not work. Then nothing is changed.
1468 If we did the combination, return the insn at which combine should
1471 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1472 new direct jump instruction. */
1475 try_combine (i3, i2, i1, new_direct_jump_p)
1477 int *new_direct_jump_p;
1479 /* New patterns for I3 and I2, respectively. */
1480 rtx newpat, newi2pat = 0;
1481 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1482 int added_sets_1, added_sets_2;
1483 /* Total number of SETs to put into I3. */
1485 /* Nonzero is I2's body now appears in I3. */
1487 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1488 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1489 /* Contains I3 if the destination of I3 is used in its source, which means
1490 that the old life of I3 is being killed. If that usage is placed into
1491 I2 and not in I3, a REG_DEAD note must be made. */
1492 rtx i3dest_killed = 0;
1493 /* SET_DEST and SET_SRC of I2 and I1. */
1494 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1495 /* PATTERN (I2), or a copy of it in certain cases. */
1497 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1498 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1499 int i1_feeds_i3 = 0;
1500 /* Notes that must be added to REG_NOTES in I3 and I2. */
1501 rtx new_i3_notes, new_i2_notes;
1502 /* Notes that we substituted I3 into I2 instead of the normal case. */
1503 int i3_subst_into_i2 = 0;
1504 /* Notes that I1, I2 or I3 is a MULT operation. */
1512 /* Exit early if one of the insns involved can't be used for
1514 if (cant_combine_insn_p (i3)
1515 || cant_combine_insn_p (i2)
1516 || (i1 && cant_combine_insn_p (i1))
1517 /* We also can't do anything if I3 has a
1518 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1521 /* ??? This gives worse code, and appears to be unnecessary, since no
1522 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1523 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1529 undobuf.other_insn = 0;
1531 /* Reset the hard register usage information. */
1532 CLEAR_HARD_REG_SET (newpat_used_regs);
1534 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1535 code below, set I1 to be the earlier of the two insns. */
1536 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1537 temp = i1, i1 = i2, i2 = temp;
1539 added_links_insn = 0;
1541 /* First check for one important special-case that the code below will
1542 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1543 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1544 we may be able to replace that destination with the destination of I3.
1545 This occurs in the common code where we compute both a quotient and
1546 remainder into a structure, in which case we want to do the computation
1547 directly into the structure to avoid register-register copies.
1549 Note that this case handles both multiple sets in I2 and also
1550 cases where I2 has a number of CLOBBER or PARALLELs.
1552 We make very conservative checks below and only try to handle the
1553 most common cases of this. For example, we only handle the case
1554 where I2 and I3 are adjacent to avoid making difficult register
1557 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1558 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1559 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1560 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1561 && GET_CODE (PATTERN (i2)) == PARALLEL
1562 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1563 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1564 below would need to check what is inside (and reg_overlap_mentioned_p
1565 doesn't support those codes anyway). Don't allow those destinations;
1566 the resulting insn isn't likely to be recognized anyway. */
1567 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1568 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1569 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1570 SET_DEST (PATTERN (i3)))
1571 && next_real_insn (i2) == i3)
1573 rtx p2 = PATTERN (i2);
1575 /* Make sure that the destination of I3,
1576 which we are going to substitute into one output of I2,
1577 is not used within another output of I2. We must avoid making this:
1578 (parallel [(set (mem (reg 69)) ...)
1579 (set (reg 69) ...)])
1580 which is not well-defined as to order of actions.
1581 (Besides, reload can't handle output reloads for this.)
1583 The problem can also happen if the dest of I3 is a memory ref,
1584 if another dest in I2 is an indirect memory ref. */
1585 for (i = 0; i < XVECLEN (p2, 0); i++)
1586 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1587 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1588 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1589 SET_DEST (XVECEXP (p2, 0, i))))
1592 if (i == XVECLEN (p2, 0))
1593 for (i = 0; i < XVECLEN (p2, 0); i++)
1594 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1595 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1596 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1601 subst_low_cuid = INSN_CUID (i2);
1603 added_sets_2 = added_sets_1 = 0;
1604 i2dest = SET_SRC (PATTERN (i3));
1606 /* Replace the dest in I2 with our dest and make the resulting
1607 insn the new pattern for I3. Then skip to where we
1608 validate the pattern. Everything was set up above. */
1609 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1610 SET_DEST (PATTERN (i3)));
1613 i3_subst_into_i2 = 1;
1614 goto validate_replacement;
1618 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1619 one of those words to another constant, merge them by making a new
1622 && (temp = single_set (i2)) != 0
1623 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1624 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1625 && GET_CODE (SET_DEST (temp)) == REG
1626 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1627 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1628 && GET_CODE (PATTERN (i3)) == SET
1629 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1630 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1631 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1632 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1633 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1635 HOST_WIDE_INT lo, hi;
1637 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1638 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1641 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1642 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1645 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1647 /* We don't handle the case of the target word being wider
1648 than a host wide int. */
1649 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1652 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1653 lo |= INTVAL (SET_SRC (PATTERN (i3)));
1655 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1656 hi = INTVAL (SET_SRC (PATTERN (i3)));
1657 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1659 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1660 >> (HOST_BITS_PER_WIDE_INT - 1));
1662 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1663 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1664 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1665 (INTVAL (SET_SRC (PATTERN (i3)))));
1667 hi = lo < 0 ? -1 : 0;
1670 /* We don't handle the case of the higher word not fitting
1671 entirely in either hi or lo. */
1676 subst_low_cuid = INSN_CUID (i2);
1677 added_sets_2 = added_sets_1 = 0;
1678 i2dest = SET_DEST (temp);
1680 SUBST (SET_SRC (temp),
1681 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1683 newpat = PATTERN (i2);
1684 goto validate_replacement;
1688 /* If we have no I1 and I2 looks like:
1689 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1691 make up a dummy I1 that is
1694 (set (reg:CC X) (compare:CC Y (const_int 0)))
1696 (We can ignore any trailing CLOBBERs.)
1698 This undoes a previous combination and allows us to match a branch-and-
1701 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1702 && XVECLEN (PATTERN (i2), 0) >= 2
1703 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1704 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1706 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1707 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1708 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1709 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1710 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1711 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1713 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1714 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1719 /* We make I1 with the same INSN_UID as I2. This gives it
1720 the same INSN_CUID for value tracking. Our fake I1 will
1721 never appear in the insn stream so giving it the same INSN_UID
1722 as I2 will not cause a problem. */
1724 subst_prev_insn = i1
1725 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1726 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1729 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1730 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1731 SET_DEST (PATTERN (i1)));
1736 /* Verify that I2 and I1 are valid for combining. */
1737 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1738 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1744 /* Record whether I2DEST is used in I2SRC and similarly for the other
1745 cases. Knowing this will help in register status updating below. */
1746 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1747 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1748 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1750 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1752 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1754 /* Ensure that I3's pattern can be the destination of combines. */
1755 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1756 i1 && i2dest_in_i1src && i1_feeds_i3,
1763 /* See if any of the insns is a MULT operation. Unless one is, we will
1764 reject a combination that is, since it must be slower. Be conservative
1766 if (GET_CODE (i2src) == MULT
1767 || (i1 != 0 && GET_CODE (i1src) == MULT)
1768 || (GET_CODE (PATTERN (i3)) == SET
1769 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1772 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1773 We used to do this EXCEPT in one case: I3 has a post-inc in an
1774 output operand. However, that exception can give rise to insns like
1776 which is a famous insn on the PDP-11 where the value of r3 used as the
1777 source was model-dependent. Avoid this sort of thing. */
1780 if (!(GET_CODE (PATTERN (i3)) == SET
1781 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1782 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1783 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1784 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1785 /* It's not the exception. */
1788 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1789 if (REG_NOTE_KIND (link) == REG_INC
1790 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1792 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1799 /* See if the SETs in I1 or I2 need to be kept around in the merged
1800 instruction: whenever the value set there is still needed past I3.
1801 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1803 For the SET in I1, we have two cases: If I1 and I2 independently
1804 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1805 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1806 in I1 needs to be kept around unless I1DEST dies or is set in either
1807 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1808 I1DEST. If so, we know I1 feeds into I2. */
1810 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1813 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1814 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1816 /* If the set in I2 needs to be kept around, we must make a copy of
1817 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1818 PATTERN (I2), we are only substituting for the original I1DEST, not into
1819 an already-substituted copy. This also prevents making self-referential
1820 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1823 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1824 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1828 i2pat = copy_rtx (i2pat);
1832 /* Substitute in the latest insn for the regs set by the earlier ones. */
1834 maxreg = max_reg_num ();
1838 /* It is possible that the source of I2 or I1 may be performing an
1839 unneeded operation, such as a ZERO_EXTEND of something that is known
1840 to have the high part zero. Handle that case by letting subst look at
1841 the innermost one of them.
1843 Another way to do this would be to have a function that tries to
1844 simplify a single insn instead of merging two or more insns. We don't
1845 do this because of the potential of infinite loops and because
1846 of the potential extra memory required. However, doing it the way
1847 we are is a bit of a kludge and doesn't catch all cases.
1849 But only do this if -fexpensive-optimizations since it slows things down
1850 and doesn't usually win. */
1852 if (flag_expensive_optimizations)
1854 /* Pass pc_rtx so no substitutions are done, just simplifications.
1855 The cases that we are interested in here do not involve the few
1856 cases were is_replaced is checked. */
1859 subst_low_cuid = INSN_CUID (i1);
1860 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1864 subst_low_cuid = INSN_CUID (i2);
1865 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1870 /* Many machines that don't use CC0 have insns that can both perform an
1871 arithmetic operation and set the condition code. These operations will
1872 be represented as a PARALLEL with the first element of the vector
1873 being a COMPARE of an arithmetic operation with the constant zero.
1874 The second element of the vector will set some pseudo to the result
1875 of the same arithmetic operation. If we simplify the COMPARE, we won't
1876 match such a pattern and so will generate an extra insn. Here we test
1877 for this case, where both the comparison and the operation result are
1878 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1879 I2SRC. Later we will make the PARALLEL that contains I2. */
1881 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1882 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1883 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1884 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1886 #ifdef EXTRA_CC_MODES
1888 enum machine_mode compare_mode;
1891 newpat = PATTERN (i3);
1892 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1896 #ifdef EXTRA_CC_MODES
1897 /* See if a COMPARE with the operand we substituted in should be done
1898 with the mode that is currently being used. If not, do the same
1899 processing we do in `subst' for a SET; namely, if the destination
1900 is used only once, try to replace it with a register of the proper
1901 mode and also replace the COMPARE. */
1902 if (undobuf.other_insn == 0
1903 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1904 &undobuf.other_insn))
1905 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1907 != GET_MODE (SET_DEST (newpat))))
1909 unsigned int regno = REGNO (SET_DEST (newpat));
1910 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1912 if (regno < FIRST_PSEUDO_REGISTER
1913 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1914 && ! REG_USERVAR_P (SET_DEST (newpat))))
1916 if (regno >= FIRST_PSEUDO_REGISTER)
1917 SUBST (regno_reg_rtx[regno], new_dest);
1919 SUBST (SET_DEST (newpat), new_dest);
1920 SUBST (XEXP (*cc_use, 0), new_dest);
1921 SUBST (SET_SRC (newpat),
1922 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1925 undobuf.other_insn = 0;
1932 n_occurrences = 0; /* `subst' counts here */
1934 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1935 need to make a unique copy of I2SRC each time we substitute it
1936 to avoid self-referential rtl. */
1938 subst_low_cuid = INSN_CUID (i2);
1939 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1940 ! i1_feeds_i3 && i1dest_in_i1src);
1942 /* Record whether i2's body now appears within i3's body. */
1943 i2_is_used = n_occurrences;
1946 /* If we already got a failure, don't try to do more. Otherwise,
1947 try to substitute in I1 if we have it. */
1949 if (i1 && GET_CODE (newpat) != CLOBBER)
1951 /* Before we can do this substitution, we must redo the test done
1952 above (see detailed comments there) that ensures that I1DEST
1953 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1955 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1963 subst_low_cuid = INSN_CUID (i1);
1964 newpat = subst (newpat, i1dest, i1src, 0, 0);
1967 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1968 to count all the ways that I2SRC and I1SRC can be used. */
1969 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1970 && i2_is_used + added_sets_2 > 1)
1971 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1972 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1974 /* Fail if we tried to make a new register (we used to abort, but there's
1975 really no reason to). */
1976 || max_reg_num () != maxreg
1977 /* Fail if we couldn't do something and have a CLOBBER. */
1978 || GET_CODE (newpat) == CLOBBER
1979 /* Fail if this new pattern is a MULT and we didn't have one before
1980 at the outer level. */
1981 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1988 /* If the actions of the earlier insns must be kept
1989 in addition to substituting them into the latest one,
1990 we must make a new PARALLEL for the latest insn
1991 to hold additional the SETs. */
1993 if (added_sets_1 || added_sets_2)
1997 if (GET_CODE (newpat) == PARALLEL)
1999 rtvec old = XVEC (newpat, 0);
2000 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2001 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2002 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2003 sizeof (old->elem[0]) * old->num_elem);
2008 total_sets = 1 + added_sets_1 + added_sets_2;
2009 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2010 XVECEXP (newpat, 0, 0) = old;
2014 XVECEXP (newpat, 0, --total_sets)
2015 = (GET_CODE (PATTERN (i1)) == PARALLEL
2016 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2020 /* If there is no I1, use I2's body as is. We used to also not do
2021 the subst call below if I2 was substituted into I3,
2022 but that could lose a simplification. */
2024 XVECEXP (newpat, 0, --total_sets) = i2pat;
2026 /* See comment where i2pat is assigned. */
2027 XVECEXP (newpat, 0, --total_sets)
2028 = subst (i2pat, i1dest, i1src, 0, 0);
2032 /* We come here when we are replacing a destination in I2 with the
2033 destination of I3. */
2034 validate_replacement:
2036 /* Note which hard regs this insn has as inputs. */
2037 mark_used_regs_combine (newpat);
2039 /* Is the result of combination a valid instruction? */
2040 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2042 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2043 the second SET's destination is a register that is unused. In that case,
2044 we just need the first SET. This can occur when simplifying a divmod
2045 insn. We *must* test for this case here because the code below that
2046 splits two independent SETs doesn't handle this case correctly when it
2047 updates the register status. Also check the case where the first
2048 SET's destination is unused. That would not cause incorrect code, but
2049 does cause an unneeded insn to remain. */
2051 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2052 && XVECLEN (newpat, 0) == 2
2053 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2054 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2055 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2056 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2057 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2058 && asm_noperands (newpat) < 0)
2060 newpat = XVECEXP (newpat, 0, 0);
2061 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2064 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2065 && XVECLEN (newpat, 0) == 2
2066 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2067 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2068 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2069 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2070 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2071 && asm_noperands (newpat) < 0)
2073 newpat = XVECEXP (newpat, 0, 1);
2074 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2077 /* If we were combining three insns and the result is a simple SET
2078 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2079 insns. There are two ways to do this. It can be split using a
2080 machine-specific method (like when you have an addition of a large
2081 constant) or by combine in the function find_split_point. */
2083 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2084 && asm_noperands (newpat) < 0)
2086 rtx m_split, *split;
2087 rtx ni2dest = i2dest;
2089 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2090 use I2DEST as a scratch register will help. In the latter case,
2091 convert I2DEST to the mode of the source of NEWPAT if we can. */
2093 m_split = split_insns (newpat, i3);
2095 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2096 inputs of NEWPAT. */
2098 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2099 possible to try that as a scratch reg. This would require adding
2100 more code to make it work though. */
2102 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2104 /* If I2DEST is a hard register or the only use of a pseudo,
2105 we can change its mode. */
2106 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2107 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2108 && GET_CODE (i2dest) == REG
2109 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2110 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2111 && ! REG_USERVAR_P (i2dest))))
2112 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2115 m_split = split_insns (gen_rtx_PARALLEL
2117 gen_rtvec (2, newpat,
2118 gen_rtx_CLOBBER (VOIDmode,
2121 /* If the split with the mode-changed register didn't work, try
2122 the original register. */
2123 if (! m_split && ni2dest != i2dest)
2126 m_split = split_insns (gen_rtx_PARALLEL
2128 gen_rtvec (2, newpat,
2129 gen_rtx_CLOBBER (VOIDmode,
2135 /* If we've split a jump pattern, we'll wind up with a sequence even
2136 with one instruction. We can handle that below, so extract it. */
2137 if (m_split && GET_CODE (m_split) == SEQUENCE
2138 && XVECLEN (m_split, 0) == 1)
2139 m_split = PATTERN (XVECEXP (m_split, 0, 0));
2141 if (m_split && GET_CODE (m_split) != SEQUENCE)
2143 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2144 if (insn_code_number >= 0)
2147 else if (m_split && GET_CODE (m_split) == SEQUENCE
2148 && XVECLEN (m_split, 0) == 2
2149 && (next_real_insn (i2) == i3
2150 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2154 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2155 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2157 i3set = single_set (XVECEXP (m_split, 0, 1));
2158 i2set = single_set (XVECEXP (m_split, 0, 0));
2160 /* In case we changed the mode of I2DEST, replace it in the
2161 pseudo-register table here. We can't do it above in case this
2162 code doesn't get executed and we do a split the other way. */
2164 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2165 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2167 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2169 /* If I2 or I3 has multiple SETs, we won't know how to track
2170 register status, so don't use these insns. If I2's destination
2171 is used between I2 and I3, we also can't use these insns. */
2173 if (i2_code_number >= 0 && i2set && i3set
2174 && (next_real_insn (i2) == i3
2175 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2176 insn_code_number = recog_for_combine (&newi3pat, i3,
2178 if (insn_code_number >= 0)
2181 /* It is possible that both insns now set the destination of I3.
2182 If so, we must show an extra use of it. */
2184 if (insn_code_number >= 0)
2186 rtx new_i3_dest = SET_DEST (i3set);
2187 rtx new_i2_dest = SET_DEST (i2set);
2189 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2190 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2191 || GET_CODE (new_i3_dest) == SUBREG)
2192 new_i3_dest = XEXP (new_i3_dest, 0);
2194 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2195 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2196 || GET_CODE (new_i2_dest) == SUBREG)
2197 new_i2_dest = XEXP (new_i2_dest, 0);
2199 if (GET_CODE (new_i3_dest) == REG
2200 && GET_CODE (new_i2_dest) == REG
2201 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2202 REG_N_SETS (REGNO (new_i2_dest))++;
2206 /* If we can split it and use I2DEST, go ahead and see if that
2207 helps things be recognized. Verify that none of the registers
2208 are set between I2 and I3. */
2209 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2211 && GET_CODE (i2dest) == REG
2213 /* We need I2DEST in the proper mode. If it is a hard register
2214 or the only use of a pseudo, we can change its mode. */
2215 && (GET_MODE (*split) == GET_MODE (i2dest)
2216 || GET_MODE (*split) == VOIDmode
2217 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2218 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2219 && ! REG_USERVAR_P (i2dest)))
2220 && (next_real_insn (i2) == i3
2221 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2222 /* We can't overwrite I2DEST if its value is still used by
2224 && ! reg_referenced_p (i2dest, newpat))
2226 rtx newdest = i2dest;
2227 enum rtx_code split_code = GET_CODE (*split);
2228 enum machine_mode split_mode = GET_MODE (*split);
2230 /* Get NEWDEST as a register in the proper mode. We have already
2231 validated that we can do this. */
2232 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2234 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2236 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2237 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2240 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2241 an ASHIFT. This can occur if it was inside a PLUS and hence
2242 appeared to be a memory address. This is a kludge. */
2243 if (split_code == MULT
2244 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2245 && INTVAL (XEXP (*split, 1)) > 0
2246 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2248 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2249 XEXP (*split, 0), GEN_INT (i)));
2250 /* Update split_code because we may not have a multiply
2252 split_code = GET_CODE (*split);
2255 #ifdef INSN_SCHEDULING
2256 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2257 be written as a ZERO_EXTEND. */
2258 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2259 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2260 SUBREG_REG (*split)));
2263 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2264 SUBST (*split, newdest);
2265 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2267 /* If the split point was a MULT and we didn't have one before,
2268 don't use one now. */
2269 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2270 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2274 /* Check for a case where we loaded from memory in a narrow mode and
2275 then sign extended it, but we need both registers. In that case,
2276 we have a PARALLEL with both loads from the same memory location.
2277 We can split this into a load from memory followed by a register-register
2278 copy. This saves at least one insn, more if register allocation can
2281 We cannot do this if the destination of the second assignment is
2282 a register that we have already assumed is zero-extended. Similarly
2283 for a SUBREG of such a register. */
2285 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2286 && GET_CODE (newpat) == PARALLEL
2287 && XVECLEN (newpat, 0) == 2
2288 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2289 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2290 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2291 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2292 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2293 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2295 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2296 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2297 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2298 (GET_CODE (temp) == REG
2299 && reg_nonzero_bits[REGNO (temp)] != 0
2300 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2301 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2302 && (reg_nonzero_bits[REGNO (temp)]
2303 != GET_MODE_MASK (word_mode))))
2304 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2305 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2306 (GET_CODE (temp) == REG
2307 && reg_nonzero_bits[REGNO (temp)] != 0
2308 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2309 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2310 && (reg_nonzero_bits[REGNO (temp)]
2311 != GET_MODE_MASK (word_mode)))))
2312 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2313 SET_SRC (XVECEXP (newpat, 0, 1)))
2314 && ! find_reg_note (i3, REG_UNUSED,
2315 SET_DEST (XVECEXP (newpat, 0, 0))))
2319 newi2pat = XVECEXP (newpat, 0, 0);
2320 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2321 newpat = XVECEXP (newpat, 0, 1);
2322 SUBST (SET_SRC (newpat),
2323 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2324 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2326 if (i2_code_number >= 0)
2327 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2329 if (insn_code_number >= 0)
2334 /* If we will be able to accept this, we have made a change to the
2335 destination of I3. This can invalidate a LOG_LINKS pointing
2336 to I3. No other part of combine.c makes such a transformation.
2338 The new I3 will have a destination that was previously the
2339 destination of I1 or I2 and which was used in i2 or I3. Call
2340 distribute_links to make a LOG_LINK from the next use of
2341 that destination. */
2343 PATTERN (i3) = newpat;
2344 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2346 /* I3 now uses what used to be its destination and which is
2347 now I2's destination. That means we need a LOG_LINK from
2348 I3 to I2. But we used to have one, so we still will.
2350 However, some later insn might be using I2's dest and have
2351 a LOG_LINK pointing at I3. We must remove this link.
2352 The simplest way to remove the link is to point it at I1,
2353 which we know will be a NOTE. */
2355 for (insn = NEXT_INSN (i3);
2356 insn && (this_basic_block == n_basic_blocks - 1
2357 || insn != BLOCK_HEAD (this_basic_block + 1));
2358 insn = NEXT_INSN (insn))
2360 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2362 for (link = LOG_LINKS (insn); link;
2363 link = XEXP (link, 1))
2364 if (XEXP (link, 0) == i3)
2365 XEXP (link, 0) = i1;
2373 /* Similarly, check for a case where we have a PARALLEL of two independent
2374 SETs but we started with three insns. In this case, we can do the sets
2375 as two separate insns. This case occurs when some SET allows two
2376 other insns to combine, but the destination of that SET is still live. */
2378 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2379 && GET_CODE (newpat) == PARALLEL
2380 && XVECLEN (newpat, 0) == 2
2381 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2382 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2383 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2384 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2385 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2386 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2387 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2389 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2390 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2391 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2392 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2393 XVECEXP (newpat, 0, 0))
2394 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2395 XVECEXP (newpat, 0, 1))
2396 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2397 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2399 /* Normally, it doesn't matter which of the two is done first,
2400 but it does if one references cc0. In that case, it has to
2403 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2405 newi2pat = XVECEXP (newpat, 0, 0);
2406 newpat = XVECEXP (newpat, 0, 1);
2411 newi2pat = XVECEXP (newpat, 0, 1);
2412 newpat = XVECEXP (newpat, 0, 0);
2415 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2417 if (i2_code_number >= 0)
2418 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2421 /* If it still isn't recognized, fail and change things back the way they
2423 if ((insn_code_number < 0
2424 /* Is the result a reasonable ASM_OPERANDS? */
2425 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2431 /* If we had to change another insn, make sure it is valid also. */
2432 if (undobuf.other_insn)
2434 rtx other_pat = PATTERN (undobuf.other_insn);
2435 rtx new_other_notes;
2438 CLEAR_HARD_REG_SET (newpat_used_regs);
2440 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2443 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2449 PATTERN (undobuf.other_insn) = other_pat;
2451 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2452 are still valid. Then add any non-duplicate notes added by
2453 recog_for_combine. */
2454 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2456 next = XEXP (note, 1);
2458 if (REG_NOTE_KIND (note) == REG_UNUSED
2459 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2461 if (GET_CODE (XEXP (note, 0)) == REG)
2462 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2464 remove_note (undobuf.other_insn, note);
2468 for (note = new_other_notes; note; note = XEXP (note, 1))
2469 if (GET_CODE (XEXP (note, 0)) == REG)
2470 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2472 distribute_notes (new_other_notes, undobuf.other_insn,
2473 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2476 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2477 they are adjacent to each other or not. */
2479 rtx p = prev_nonnote_insn (i3);
2480 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2481 && sets_cc0_p (newi2pat))
2489 /* We now know that we can do this combination. Merge the insns and
2490 update the status of registers and LOG_LINKS. */
2493 rtx i3notes, i2notes, i1notes = 0;
2494 rtx i3links, i2links, i1links = 0;
2497 /* Compute which registers we expect to eliminate. newi2pat may be setting
2498 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2499 same as i3dest, in which case newi2pat may be setting i1dest. */
2500 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2501 || i2dest_in_i2src || i2dest_in_i1src
2503 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2504 || (newi2pat && reg_set_p (i1dest, newi2pat))
2507 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2509 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2510 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2512 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2514 /* Ensure that we do not have something that should not be shared but
2515 occurs multiple times in the new insns. Check this by first
2516 resetting all the `used' flags and then copying anything is shared. */
2518 reset_used_flags (i3notes);
2519 reset_used_flags (i2notes);
2520 reset_used_flags (i1notes);
2521 reset_used_flags (newpat);
2522 reset_used_flags (newi2pat);
2523 if (undobuf.other_insn)
2524 reset_used_flags (PATTERN (undobuf.other_insn));
2526 i3notes = copy_rtx_if_shared (i3notes);
2527 i2notes = copy_rtx_if_shared (i2notes);
2528 i1notes = copy_rtx_if_shared (i1notes);
2529 newpat = copy_rtx_if_shared (newpat);
2530 newi2pat = copy_rtx_if_shared (newi2pat);
2531 if (undobuf.other_insn)
2532 reset_used_flags (PATTERN (undobuf.other_insn));
2534 INSN_CODE (i3) = insn_code_number;
2535 PATTERN (i3) = newpat;
2536 if (undobuf.other_insn)
2537 INSN_CODE (undobuf.other_insn) = other_code_number;
2539 /* We had one special case above where I2 had more than one set and
2540 we replaced a destination of one of those sets with the destination
2541 of I3. In that case, we have to update LOG_LINKS of insns later
2542 in this basic block. Note that this (expensive) case is rare.
2544 Also, in this case, we must pretend that all REG_NOTEs for I2
2545 actually came from I3, so that REG_UNUSED notes from I2 will be
2546 properly handled. */
2548 if (i3_subst_into_i2)
2550 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2551 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2552 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2553 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2554 && ! find_reg_note (i2, REG_UNUSED,
2555 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2556 for (temp = NEXT_INSN (i2);
2557 temp && (this_basic_block == n_basic_blocks - 1
2558 || BLOCK_HEAD (this_basic_block) != temp);
2559 temp = NEXT_INSN (temp))
2560 if (temp != i3 && INSN_P (temp))
2561 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2562 if (XEXP (link, 0) == i2)
2563 XEXP (link, 0) = i3;
2568 while (XEXP (link, 1))
2569 link = XEXP (link, 1);
2570 XEXP (link, 1) = i2notes;
2584 INSN_CODE (i2) = i2_code_number;
2585 PATTERN (i2) = newi2pat;
2589 PUT_CODE (i2, NOTE);
2590 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2591 NOTE_SOURCE_FILE (i2) = 0;
2598 PUT_CODE (i1, NOTE);
2599 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2600 NOTE_SOURCE_FILE (i1) = 0;
2603 /* Get death notes for everything that is now used in either I3 or
2604 I2 and used to die in a previous insn. If we built two new
2605 patterns, move from I1 to I2 then I2 to I3 so that we get the
2606 proper movement on registers that I2 modifies. */
2610 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2611 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2614 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2617 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2619 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2622 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2625 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2628 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2631 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2632 know these are REG_UNUSED and want them to go to the desired insn,
2633 so we always pass it as i3. We have not counted the notes in
2634 reg_n_deaths yet, so we need to do so now. */
2636 if (newi2pat && new_i2_notes)
2638 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2639 if (GET_CODE (XEXP (temp, 0)) == REG)
2640 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2642 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2647 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2648 if (GET_CODE (XEXP (temp, 0)) == REG)
2649 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2651 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2654 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2655 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2656 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2657 in that case, it might delete I2. Similarly for I2 and I1.
2658 Show an additional death due to the REG_DEAD note we make here. If
2659 we discard it in distribute_notes, we will decrement it again. */
2663 if (GET_CODE (i3dest_killed) == REG)
2664 REG_N_DEATHS (REGNO (i3dest_killed))++;
2666 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2667 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2669 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2671 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2673 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2677 if (i2dest_in_i2src)
2679 if (GET_CODE (i2dest) == REG)
2680 REG_N_DEATHS (REGNO (i2dest))++;
2682 if (newi2pat && reg_set_p (i2dest, newi2pat))
2683 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2684 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2686 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2687 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2688 NULL_RTX, NULL_RTX);
2691 if (i1dest_in_i1src)
2693 if (GET_CODE (i1dest) == REG)
2694 REG_N_DEATHS (REGNO (i1dest))++;
2696 if (newi2pat && reg_set_p (i1dest, newi2pat))
2697 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2698 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2700 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2701 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2702 NULL_RTX, NULL_RTX);
2705 distribute_links (i3links);
2706 distribute_links (i2links);
2707 distribute_links (i1links);
2709 if (GET_CODE (i2dest) == REG)
2712 rtx i2_insn = 0, i2_val = 0, set;
2714 /* The insn that used to set this register doesn't exist, and
2715 this life of the register may not exist either. See if one of
2716 I3's links points to an insn that sets I2DEST. If it does,
2717 that is now the last known value for I2DEST. If we don't update
2718 this and I2 set the register to a value that depended on its old
2719 contents, we will get confused. If this insn is used, thing
2720 will be set correctly in combine_instructions. */
2722 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2723 if ((set = single_set (XEXP (link, 0))) != 0
2724 && rtx_equal_p (i2dest, SET_DEST (set)))
2725 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2727 record_value_for_reg (i2dest, i2_insn, i2_val);
2729 /* If the reg formerly set in I2 died only once and that was in I3,
2730 zero its use count so it won't make `reload' do any work. */
2732 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2733 && ! i2dest_in_i2src)
2735 regno = REGNO (i2dest);
2736 REG_N_SETS (regno)--;
2740 if (i1 && GET_CODE (i1dest) == REG)
2743 rtx i1_insn = 0, i1_val = 0, set;
2745 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2746 if ((set = single_set (XEXP (link, 0))) != 0
2747 && rtx_equal_p (i1dest, SET_DEST (set)))
2748 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2750 record_value_for_reg (i1dest, i1_insn, i1_val);
2752 regno = REGNO (i1dest);
2753 if (! added_sets_1 && ! i1dest_in_i1src)
2754 REG_N_SETS (regno)--;
2757 /* Update reg_nonzero_bits et al for any changes that may have been made
2758 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2759 important. Because newi2pat can affect nonzero_bits of newpat */
2761 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2762 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2764 /* Set new_direct_jump_p if a new return or simple jump instruction
2767 If I3 is now an unconditional jump, ensure that it has a
2768 BARRIER following it since it may have initially been a
2769 conditional jump. It may also be the last nonnote insn. */
2771 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2773 *new_direct_jump_p = 1;
2775 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2776 || GET_CODE (temp) != BARRIER)
2777 emit_barrier_after (i3);
2779 /* An NOOP jump does not need barrier, but it does need cleaning up
2781 if (GET_CODE (newpat) == SET
2782 && SET_SRC (newpat) == pc_rtx
2783 && SET_DEST (newpat) == pc_rtx)
2784 *new_direct_jump_p = 1;
2787 combine_successes++;
2790 /* Clear this here, so that subsequent get_last_value calls are not
2792 subst_prev_insn = NULL_RTX;
2794 if (added_links_insn
2795 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2796 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2797 return added_links_insn;
2799 return newi2pat ? i2 : i3;
2802 /* Undo all the modifications recorded in undobuf. */
2807 struct undo *undo, *next;
2809 for (undo = undobuf.undos; undo; undo = next)
2813 *undo->where.i = undo->old_contents.i;
2815 *undo->where.r = undo->old_contents.r;
2817 undo->next = undobuf.frees;
2818 undobuf.frees = undo;
2823 /* Clear this here, so that subsequent get_last_value calls are not
2825 subst_prev_insn = NULL_RTX;
2828 /* We've committed to accepting the changes we made. Move all
2829 of the undos to the free list. */
2834 struct undo *undo, *next;
2836 for (undo = undobuf.undos; undo; undo = next)
2839 undo->next = undobuf.frees;
2840 undobuf.frees = undo;
2846 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2847 where we have an arithmetic expression and return that point. LOC will
2850 try_combine will call this function to see if an insn can be split into
2854 find_split_point (loc, insn)
2859 enum rtx_code code = GET_CODE (x);
2861 unsigned HOST_WIDE_INT len = 0;
2862 HOST_WIDE_INT pos = 0;
2864 rtx inner = NULL_RTX;
2866 /* First special-case some codes. */
2870 #ifdef INSN_SCHEDULING
2871 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2873 if (GET_CODE (SUBREG_REG (x)) == MEM)
2876 return find_split_point (&SUBREG_REG (x), insn);
2880 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2881 using LO_SUM and HIGH. */
2882 if (GET_CODE (XEXP (x, 0)) == CONST
2883 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2886 gen_rtx_LO_SUM (Pmode,
2887 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2889 return &XEXP (XEXP (x, 0), 0);
2893 /* If we have a PLUS whose second operand is a constant and the
2894 address is not valid, perhaps will can split it up using
2895 the machine-specific way to split large constants. We use
2896 the first pseudo-reg (one of the virtual regs) as a placeholder;
2897 it will not remain in the result. */
2898 if (GET_CODE (XEXP (x, 0)) == PLUS
2899 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2900 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2902 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2903 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2906 /* This should have produced two insns, each of which sets our
2907 placeholder. If the source of the second is a valid address,
2908 we can make put both sources together and make a split point
2911 if (seq && XVECLEN (seq, 0) == 2
2912 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2913 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2914 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2915 && ! reg_mentioned_p (reg,
2916 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2917 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2918 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2919 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2920 && memory_address_p (GET_MODE (x),
2921 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2923 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2924 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2926 /* Replace the placeholder in SRC2 with SRC1. If we can
2927 find where in SRC2 it was placed, that can become our
2928 split point and we can replace this address with SRC2.
2929 Just try two obvious places. */
2931 src2 = replace_rtx (src2, reg, src1);
2933 if (XEXP (src2, 0) == src1)
2934 split = &XEXP (src2, 0);
2935 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2936 && XEXP (XEXP (src2, 0), 0) == src1)
2937 split = &XEXP (XEXP (src2, 0), 0);
2941 SUBST (XEXP (x, 0), src2);
2946 /* If that didn't work, perhaps the first operand is complex and
2947 needs to be computed separately, so make a split point there.
2948 This will occur on machines that just support REG + CONST
2949 and have a constant moved through some previous computation. */
2951 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2952 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2953 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2955 return &XEXP (XEXP (x, 0), 0);
2961 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2962 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2963 we need to put the operand into a register. So split at that
2966 if (SET_DEST (x) == cc0_rtx
2967 && GET_CODE (SET_SRC (x)) != COMPARE
2968 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2969 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2970 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2971 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2972 return &SET_SRC (x);
2975 /* See if we can split SET_SRC as it stands. */
2976 split = find_split_point (&SET_SRC (x), insn);
2977 if (split && split != &SET_SRC (x))
2980 /* See if we can split SET_DEST as it stands. */
2981 split = find_split_point (&SET_DEST (x), insn);
2982 if (split && split != &SET_DEST (x))
2985 /* See if this is a bitfield assignment with everything constant. If
2986 so, this is an IOR of an AND, so split it into that. */
2987 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2988 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2989 <= HOST_BITS_PER_WIDE_INT)
2990 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2991 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2992 && GET_CODE (SET_SRC (x)) == CONST_INT
2993 && ((INTVAL (XEXP (SET_DEST (x), 1))
2994 + INTVAL (XEXP (SET_DEST (x), 2)))
2995 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2996 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2998 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2999 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3000 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3001 rtx dest = XEXP (SET_DEST (x), 0);
3002 enum machine_mode mode = GET_MODE (dest);
3003 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3005 if (BITS_BIG_ENDIAN)
3006 pos = GET_MODE_BITSIZE (mode) - len - pos;
3010 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3013 gen_binary (IOR, mode,
3014 gen_binary (AND, mode, dest,
3015 GEN_INT (~(mask << pos)
3016 & GET_MODE_MASK (mode))),
3017 GEN_INT (src << pos)));
3019 SUBST (SET_DEST (x), dest);
3021 split = find_split_point (&SET_SRC (x), insn);
3022 if (split && split != &SET_SRC (x))
3026 /* Otherwise, see if this is an operation that we can split into two.
3027 If so, try to split that. */
3028 code = GET_CODE (SET_SRC (x));
3033 /* If we are AND'ing with a large constant that is only a single
3034 bit and the result is only being used in a context where we
3035 need to know if it is zero or non-zero, replace it with a bit
3036 extraction. This will avoid the large constant, which might
3037 have taken more than one insn to make. If the constant were
3038 not a valid argument to the AND but took only one insn to make,
3039 this is no worse, but if it took more than one insn, it will
3042 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3043 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3044 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3045 && GET_CODE (SET_DEST (x)) == REG
3046 && (split = find_single_use (SET_DEST (x), insn, (rtx*)0)) != 0
3047 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3048 && XEXP (*split, 0) == SET_DEST (x)
3049 && XEXP (*split, 1) == const0_rtx)
3051 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3052 XEXP (SET_SRC (x), 0),
3053 pos, NULL_RTX, 1, 1, 0, 0);
3054 if (extraction != 0)
3056 SUBST (SET_SRC (x), extraction);
3057 return find_split_point (loc, insn);
3063 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3064 is known to be on, this can be converted into a NEG of a shift. */
3065 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3066 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3067 && 1 <= (pos = exact_log2
3068 (nonzero_bits (XEXP (SET_SRC (x), 0),
3069 GET_MODE (XEXP (SET_SRC (x), 0))))))
3071 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3075 gen_rtx_LSHIFTRT (mode,
3076 XEXP (SET_SRC (x), 0),
3079 split = find_split_point (&SET_SRC (x), insn);
3080 if (split && split != &SET_SRC (x))
3086 inner = XEXP (SET_SRC (x), 0);
3088 /* We can't optimize if either mode is a partial integer
3089 mode as we don't know how many bits are significant
3091 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3092 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3096 len = GET_MODE_BITSIZE (GET_MODE (inner));
3102 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3103 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3105 inner = XEXP (SET_SRC (x), 0);
3106 len = INTVAL (XEXP (SET_SRC (x), 1));
3107 pos = INTVAL (XEXP (SET_SRC (x), 2));
3109 if (BITS_BIG_ENDIAN)
3110 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3111 unsignedp = (code == ZERO_EXTRACT);
3119 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3121 enum machine_mode mode = GET_MODE (SET_SRC (x));
3123 /* For unsigned, we have a choice of a shift followed by an
3124 AND or two shifts. Use two shifts for field sizes where the
3125 constant might be too large. We assume here that we can
3126 always at least get 8-bit constants in an AND insn, which is
3127 true for every current RISC. */
3129 if (unsignedp && len <= 8)
3134 (mode, gen_lowpart_for_combine (mode, inner),
3136 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3138 split = find_split_point (&SET_SRC (x), insn);
3139 if (split && split != &SET_SRC (x))
3146 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3147 gen_rtx_ASHIFT (mode,
3148 gen_lowpart_for_combine (mode, inner),
3149 GEN_INT (GET_MODE_BITSIZE (mode)
3151 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3153 split = find_split_point (&SET_SRC (x), insn);
3154 if (split && split != &SET_SRC (x))
3159 /* See if this is a simple operation with a constant as the second
3160 operand. It might be that this constant is out of range and hence
3161 could be used as a split point. */
3162 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3163 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3165 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3166 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3167 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3168 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3170 return &XEXP (SET_SRC (x), 1);
3172 /* Finally, see if this is a simple operation with its first operand
3173 not in a register. The operation might require this operand in a
3174 register, so return it as a split point. We can always do this
3175 because if the first operand were another operation, we would have
3176 already found it as a split point. */
3177 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3179 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3180 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3181 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3182 return &XEXP (SET_SRC (x), 0);
3188 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3189 it is better to write this as (not (ior A B)) so we can split it.
3190 Similarly for IOR. */
3191 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3194 gen_rtx_NOT (GET_MODE (x),
3195 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3197 XEXP (XEXP (x, 0), 0),
3198 XEXP (XEXP (x, 1), 0))));
3199 return find_split_point (loc, insn);
3202 /* Many RISC machines have a large set of logical insns. If the
3203 second operand is a NOT, put it first so we will try to split the
3204 other operand first. */
3205 if (GET_CODE (XEXP (x, 1)) == NOT)
3207 rtx tem = XEXP (x, 0);
3208 SUBST (XEXP (x, 0), XEXP (x, 1));
3209 SUBST (XEXP (x, 1), tem);
3217 /* Otherwise, select our actions depending on our rtx class. */
3218 switch (GET_RTX_CLASS (code))
3220 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3222 split = find_split_point (&XEXP (x, 2), insn);
3225 /* ... fall through ... */
3229 split = find_split_point (&XEXP (x, 1), insn);
3232 /* ... fall through ... */
3234 /* Some machines have (and (shift ...) ...) insns. If X is not
3235 an AND, but XEXP (X, 0) is, use it as our split point. */
3236 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3237 return &XEXP (x, 0);
3239 split = find_split_point (&XEXP (x, 0), insn);
3245 /* Otherwise, we don't have a split point. */
3249 /* Throughout X, replace FROM with TO, and return the result.
3250 The result is TO if X is FROM;
3251 otherwise the result is X, but its contents may have been modified.
3252 If they were modified, a record was made in undobuf so that
3253 undo_all will (among other things) return X to its original state.
3255 If the number of changes necessary is too much to record to undo,
3256 the excess changes are not made, so the result is invalid.
3257 The changes already made can still be undone.
3258 undobuf.num_undo is incremented for such changes, so by testing that
3259 the caller can tell whether the result is valid.
3261 `n_occurrences' is incremented each time FROM is replaced.
3263 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3265 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3266 by copying if `n_occurrences' is non-zero. */
3269 subst (x, from, to, in_dest, unique_copy)
3274 enum rtx_code code = GET_CODE (x);
3275 enum machine_mode op0_mode = VOIDmode;
3280 /* Two expressions are equal if they are identical copies of a shared
3281 RTX or if they are both registers with the same register number
3284 #define COMBINE_RTX_EQUAL_P(X,Y) \
3286 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3287 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3289 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3292 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3295 /* If X and FROM are the same register but different modes, they will
3296 not have been seen as equal above. However, flow.c will make a
3297 LOG_LINKS entry for that case. If we do nothing, we will try to
3298 rerecognize our original insn and, when it succeeds, we will
3299 delete the feeding insn, which is incorrect.
3301 So force this insn not to match in this (rare) case. */
3302 if (! in_dest && code == REG && GET_CODE (from) == REG
3303 && REGNO (x) == REGNO (from))
3304 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3306 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3307 of which may contain things that can be combined. */
3308 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3311 /* It is possible to have a subexpression appear twice in the insn.
3312 Suppose that FROM is a register that appears within TO.
3313 Then, after that subexpression has been scanned once by `subst',
3314 the second time it is scanned, TO may be found. If we were
3315 to scan TO here, we would find FROM within it and create a
3316 self-referent rtl structure which is completely wrong. */
3317 if (COMBINE_RTX_EQUAL_P (x, to))
3320 /* Parallel asm_operands need special attention because all of the
3321 inputs are shared across the arms. Furthermore, unsharing the
3322 rtl results in recognition failures. Failure to handle this case
3323 specially can result in circular rtl.
3325 Solve this by doing a normal pass across the first entry of the
3326 parallel, and only processing the SET_DESTs of the subsequent
3329 if (code == PARALLEL
3330 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3331 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3333 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3335 /* If this substitution failed, this whole thing fails. */
3336 if (GET_CODE (new) == CLOBBER
3337 && XEXP (new, 0) == const0_rtx)
3340 SUBST (XVECEXP (x, 0, 0), new);
3342 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3344 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3346 if (GET_CODE (dest) != REG
3347 && GET_CODE (dest) != CC0
3348 && GET_CODE (dest) != PC)
3350 new = subst (dest, from, to, 0, unique_copy);
3352 /* If this substitution failed, this whole thing fails. */
3353 if (GET_CODE (new) == CLOBBER
3354 && XEXP (new, 0) == const0_rtx)
3357 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3363 len = GET_RTX_LENGTH (code);
3364 fmt = GET_RTX_FORMAT (code);
3366 /* We don't need to process a SET_DEST that is a register, CC0,
3367 or PC, so set up to skip this common case. All other cases
3368 where we want to suppress replacing something inside a
3369 SET_SRC are handled via the IN_DEST operand. */
3371 && (GET_CODE (SET_DEST (x)) == REG
3372 || GET_CODE (SET_DEST (x)) == CC0
3373 || GET_CODE (SET_DEST (x)) == PC))
3376 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3379 op0_mode = GET_MODE (XEXP (x, 0));
3381 for (i = 0; i < len; i++)
3386 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3388 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3390 new = (unique_copy && n_occurrences
3391 ? copy_rtx (to) : to);
3396 new = subst (XVECEXP (x, i, j), from, to, 0,
3399 /* If this substitution failed, this whole thing
3401 if (GET_CODE (new) == CLOBBER
3402 && XEXP (new, 0) == const0_rtx)
3406 SUBST (XVECEXP (x, i, j), new);
3409 else if (fmt[i] == 'e')
3411 /* If this is a register being set, ignore it. */
3414 && (code == SUBREG || code == STRICT_LOW_PART
3415 || code == ZERO_EXTRACT)
3417 && GET_CODE (new) == REG)
3420 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3422 /* In general, don't install a subreg involving two
3423 modes not tieable. It can worsen register
3424 allocation, and can even make invalid reload
3425 insns, since the reg inside may need to be copied
3426 from in the outside mode, and that may be invalid
3427 if it is an fp reg copied in integer mode.
3429 We allow two exceptions to this: It is valid if
3430 it is inside another SUBREG and the mode of that
3431 SUBREG and the mode of the inside of TO is
3432 tieable and it is valid if X is a SET that copies
3435 if (GET_CODE (to) == SUBREG
3436 && ! MODES_TIEABLE_P (GET_MODE (to),
3437 GET_MODE (SUBREG_REG (to)))
3438 && ! (code == SUBREG
3439 && MODES_TIEABLE_P (GET_MODE (x),
3440 GET_MODE (SUBREG_REG (to))))
3442 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3445 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3447 #ifdef CLASS_CANNOT_CHANGE_MODE
3449 && GET_CODE (to) == REG
3450 && REGNO (to) < FIRST_PSEUDO_REGISTER
3451 && (TEST_HARD_REG_BIT
3452 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3454 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3456 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3459 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3463 /* If we are in a SET_DEST, suppress most cases unless we
3464 have gone inside a MEM, in which case we want to
3465 simplify the address. We assume here that things that
3466 are actually part of the destination have their inner
3467 parts in the first expression. This is true for SUBREG,
3468 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3469 things aside from REG and MEM that should appear in a
3471 new = subst (XEXP (x, i), from, to,
3473 && (code == SUBREG || code == STRICT_LOW_PART
3474 || code == ZERO_EXTRACT))
3476 && i == 0), unique_copy);
3478 /* If we found that we will have to reject this combination,
3479 indicate that by returning the CLOBBER ourselves, rather than
3480 an expression containing it. This will speed things up as
3481 well as prevent accidents where two CLOBBERs are considered
3482 to be equal, thus producing an incorrect simplification. */
3484 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3487 SUBST (XEXP (x, i), new);
3492 /* Try to simplify X. If the simplification changed the code, it is likely
3493 that further simplification will help, so loop, but limit the number
3494 of repetitions that will be performed. */
3496 for (i = 0; i < 4; i++)
3498 /* If X is sufficiently simple, don't bother trying to do anything
3500 if (code != CONST_INT && code != REG && code != CLOBBER)
3501 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3503 if (GET_CODE (x) == code)
3506 code = GET_CODE (x);
3508 /* We no longer know the original mode of operand 0 since we
3509 have changed the form of X) */
3510 op0_mode = VOIDmode;
3516 /* Simplify X, a piece of RTL. We just operate on the expression at the
3517 outer level; call `subst' to simplify recursively. Return the new
3520 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3521 will be the iteration even if an expression with a code different from
3522 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3525 combine_simplify_rtx (x, op0_mode, last, in_dest)
3527 enum machine_mode op0_mode;
3531 enum rtx_code code = GET_CODE (x);
3532 enum machine_mode mode = GET_MODE (x);
3537 /* If this is a commutative operation, put a constant last and a complex
3538 expression first. We don't need to do this for comparisons here. */
3539 if (GET_RTX_CLASS (code) == 'c'
3540 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3543 SUBST (XEXP (x, 0), XEXP (x, 1));
3544 SUBST (XEXP (x, 1), temp);
3547 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3548 sign extension of a PLUS with a constant, reverse the order of the sign
3549 extension and the addition. Note that this not the same as the original
3550 code, but overflow is undefined for signed values. Also note that the
3551 PLUS will have been partially moved "inside" the sign-extension, so that
3552 the first operand of X will really look like:
3553 (ashiftrt (plus (ashift A C4) C5) C4).
3555 (plus (ashiftrt (ashift A C4) C2) C4)
3556 and replace the first operand of X with that expression. Later parts
3557 of this function may simplify the expression further.
3559 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3560 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3561 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3563 We do this to simplify address expressions. */
3565 if ((code == PLUS || code == MINUS || code == MULT)
3566 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3567 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3568 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3569 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3570 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3571 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3572 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3573 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3574 XEXP (XEXP (XEXP (x, 0), 0), 1),
3575 XEXP (XEXP (x, 0), 1))) != 0)
3578 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3579 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3580 INTVAL (XEXP (XEXP (x, 0), 1)));
3582 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3583 INTVAL (XEXP (XEXP (x, 0), 1)));
3585 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3588 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3589 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3590 things. Check for cases where both arms are testing the same
3593 Don't do anything if all operands are very simple. */
3595 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3596 || GET_RTX_CLASS (code) == '<')
3597 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3598 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3599 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3601 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3602 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3603 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3605 || (GET_RTX_CLASS (code) == '1'
3606 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3607 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3608 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3611 rtx cond, true_rtx, false_rtx;
3613 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3615 /* If everything is a comparison, what we have is highly unlikely
3616 to be simpler, so don't use it. */
3617 && ! (GET_RTX_CLASS (code) == '<'
3618 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3619 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3621 rtx cop1 = const0_rtx;
3622 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3624 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3627 /* Simplify the alternative arms; this may collapse the true and
3628 false arms to store-flag values. */
3629 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3630 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3632 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3633 is unlikely to be simpler. */
3634 if (general_operand (true_rtx, VOIDmode)
3635 && general_operand (false_rtx, VOIDmode))
3637 /* Restarting if we generate a store-flag expression will cause
3638 us to loop. Just drop through in this case. */
3640 /* If the result values are STORE_FLAG_VALUE and zero, we can
3641 just make the comparison operation. */
3642 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3643 x = gen_binary (cond_code, mode, cond, cop1);
3644 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3645 && reverse_condition (cond_code) != UNKNOWN)
3646 x = gen_binary (reverse_condition (cond_code),
3649 /* Likewise, we can make the negate of a comparison operation
3650 if the result values are - STORE_FLAG_VALUE and zero. */
3651 else if (GET_CODE (true_rtx) == CONST_INT
3652 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3653 && false_rtx == const0_rtx)
3654 x = simplify_gen_unary (NEG, mode,
3655 gen_binary (cond_code, mode, cond,
3658 else if (GET_CODE (false_rtx) == CONST_INT
3659 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3660 && true_rtx == const0_rtx)
3661 x = simplify_gen_unary (NEG, mode,
3662 gen_binary (reverse_condition
3667 return gen_rtx_IF_THEN_ELSE (mode,
3668 gen_binary (cond_code, VOIDmode,
3670 true_rtx, false_rtx);
3672 code = GET_CODE (x);
3673 op0_mode = VOIDmode;
3678 /* Try to fold this expression in case we have constants that weren't
3681 switch (GET_RTX_CLASS (code))
3684 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3688 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3689 if (cmp_mode == VOIDmode)
3691 cmp_mode = GET_MODE (XEXP (x, 1));
3692 if (cmp_mode == VOIDmode)
3693 cmp_mode = op0_mode;
3695 temp = simplify_relational_operation (code, cmp_mode,
3696 XEXP (x, 0), XEXP (x, 1));
3698 #ifdef FLOAT_STORE_FLAG_VALUE
3699 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3701 if (temp == const0_rtx)
3702 temp = CONST0_RTX (mode);
3704 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3710 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3714 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3715 XEXP (x, 1), XEXP (x, 2));
3722 code = GET_CODE (temp);
3723 op0_mode = VOIDmode;
3724 mode = GET_MODE (temp);
3727 /* First see if we can apply the inverse distributive law. */
3728 if (code == PLUS || code == MINUS
3729 || code == AND || code == IOR || code == XOR)
3731 x = apply_distributive_law (x);
3732 code = GET_CODE (x);
3733 op0_mode = VOIDmode;
3736 /* If CODE is an associative operation not otherwise handled, see if we
3737 can associate some operands. This can win if they are constants or
3738 if they are logically related (i.e. (a & b) & a). */
3739 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3740 || code == AND || code == IOR || code == XOR
3741 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3742 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3743 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3745 if (GET_CODE (XEXP (x, 0)) == code)
3747 rtx other = XEXP (XEXP (x, 0), 0);
3748 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3749 rtx inner_op1 = XEXP (x, 1);
3752 /* Make sure we pass the constant operand if any as the second
3753 one if this is a commutative operation. */
3754 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3756 rtx tem = inner_op0;
3757 inner_op0 = inner_op1;
3760 inner = simplify_binary_operation (code == MINUS ? PLUS
3761 : code == DIV ? MULT
3763 mode, inner_op0, inner_op1);
3765 /* For commutative operations, try the other pair if that one
3767 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3769 other = XEXP (XEXP (x, 0), 1);
3770 inner = simplify_binary_operation (code, mode,
3771 XEXP (XEXP (x, 0), 0),
3776 return gen_binary (code, mode, other, inner);
3780 /* A little bit of algebraic simplification here. */
3784 /* Ensure that our address has any ASHIFTs converted to MULT in case
3785 address-recognizing predicates are called later. */
3786 temp = make_compound_operation (XEXP (x, 0), MEM);
3787 SUBST (XEXP (x, 0), temp);
3791 if (op0_mode == VOIDmode)
3792 op0_mode = GET_MODE (SUBREG_REG (x));
3794 /* simplify_subreg can't use gen_lowpart_for_combine. */
3795 if (CONSTANT_P (SUBREG_REG (x))
3796 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x))
3797 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3799 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3803 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3809 /* Note that we cannot do any narrowing for non-constants since
3810 we might have been counting on using the fact that some bits were
3811 zero. We now do this in the SET. */
3816 /* (not (plus X -1)) can become (neg X). */
3817 if (GET_CODE (XEXP (x, 0)) == PLUS
3818 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3819 return gen_rtx_NEG (mode, XEXP (XEXP (x, 0), 0));
3821 /* Similarly, (not (neg X)) is (plus X -1). */
3822 if (GET_CODE (XEXP (x, 0)) == NEG)
3823 return gen_rtx_PLUS (mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3825 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3826 if (GET_CODE (XEXP (x, 0)) == XOR
3827 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3828 && (temp = simplify_unary_operation (NOT, mode,
3829 XEXP (XEXP (x, 0), 1),
3831 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3833 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3834 other than 1, but that is not valid. We could do a similar
3835 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3836 but this doesn't seem common enough to bother with. */
3837 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3838 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3839 return gen_rtx_ROTATE (mode, simplify_gen_unary (NOT, mode,
3841 XEXP (XEXP (x, 0), 1));
3843 if (GET_CODE (XEXP (x, 0)) == SUBREG
3844 && subreg_lowpart_p (XEXP (x, 0))
3845 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3846 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3847 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3848 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3850 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3852 x = gen_rtx_ROTATE (inner_mode,
3853 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3855 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3856 return gen_lowpart_for_combine (mode, x);
3859 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3860 reversing the comparison code if valid. */
3861 if (STORE_FLAG_VALUE == -1
3862 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3863 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3864 XEXP (XEXP (x, 0), 1))))
3867 /* (not (ashiftrt foo C)) where C is the number of bits in FOO minus 1
3868 is (ge foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3869 perform the above simplification. */
3871 if (STORE_FLAG_VALUE == -1
3872 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3873 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3874 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3875 return gen_rtx_GE (mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3877 /* Apply De Morgan's laws to reduce number of patterns for machines
3878 with negating logical insns (and-not, nand, etc.). If result has
3879 only one NOT, put it first, since that is how the patterns are
3882 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3884 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3885 enum machine_mode op_mode;
3887 op_mode = GET_MODE (in1);
3888 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3890 op_mode = GET_MODE (in2);
3891 if (op_mode == VOIDmode)
3893 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3895 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3898 in2 = in1; in1 = tem;
3901 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3907 /* (neg (plus X 1)) can become (not X). */
3908 if (GET_CODE (XEXP (x, 0)) == PLUS
3909 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3910 return gen_rtx_NOT (mode, XEXP (XEXP (x, 0), 0));
3912 /* Similarly, (neg (not X)) is (plus X 1). */
3913 if (GET_CODE (XEXP (x, 0)) == NOT)
3914 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3916 /* (neg (minus X Y)) can become (minus Y X). */
3917 if (GET_CODE (XEXP (x, 0)) == MINUS
3918 && (! FLOAT_MODE_P (mode)
3919 /* x-y != -(y-x) with IEEE floating point. */
3920 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3921 || flag_unsafe_math_optimizations))
3922 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3923 XEXP (XEXP (x, 0), 0));
3925 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3926 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3927 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3928 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3930 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3931 if we can then eliminate the NEG (e.g.,
3932 if the operand is a constant). */
3934 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3936 temp = simplify_unary_operation (NEG, mode,
3937 XEXP (XEXP (x, 0), 0), mode);
3939 return gen_binary (ASHIFT, mode, temp, XEXP (XEXP (x, 0), 1));
3942 temp = expand_compound_operation (XEXP (x, 0));
3944 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3945 replaced by (lshiftrt X C). This will convert
3946 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3948 if (GET_CODE (temp) == ASHIFTRT
3949 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3950 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3951 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3952 INTVAL (XEXP (temp, 1)));
3954 /* If X has only a single bit that might be nonzero, say, bit I, convert
3955 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3956 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3957 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3958 or a SUBREG of one since we'd be making the expression more
3959 complex if it was just a register. */
3961 if (GET_CODE (temp) != REG
3962 && ! (GET_CODE (temp) == SUBREG
3963 && GET_CODE (SUBREG_REG (temp)) == REG)
3964 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3966 rtx temp1 = simplify_shift_const
3967 (NULL_RTX, ASHIFTRT, mode,
3968 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3969 GET_MODE_BITSIZE (mode) - 1 - i),
3970 GET_MODE_BITSIZE (mode) - 1 - i);
3972 /* If all we did was surround TEMP with the two shifts, we
3973 haven't improved anything, so don't use it. Otherwise,
3974 we are better off with TEMP1. */
3975 if (GET_CODE (temp1) != ASHIFTRT
3976 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3977 || XEXP (XEXP (temp1, 0), 0) != temp)
3983 /* We can't handle truncation to a partial integer mode here
3984 because we don't know the real bitsize of the partial
3986 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3989 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3990 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3991 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3993 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3994 GET_MODE_MASK (mode), NULL_RTX, 0));
3996 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3997 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3998 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3999 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4000 return XEXP (XEXP (x, 0), 0);
4002 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4003 (OP:SI foo:SI) if OP is NEG or ABS. */
4004 if ((GET_CODE (XEXP (x, 0)) == ABS
4005 || GET_CODE (XEXP (x, 0)) == NEG)
4006 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4007 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4008 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4009 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4010 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4012 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4014 if (GET_CODE (XEXP (x, 0)) == SUBREG
4015 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4016 && subreg_lowpart_p (XEXP (x, 0)))
4017 return SUBREG_REG (XEXP (x, 0));
4019 /* If we know that the value is already truncated, we can
4020 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4021 is nonzero for the corresponding modes. But don't do this
4022 for an (LSHIFTRT (MULT ...)) since this will cause problems
4023 with the umulXi3_highpart patterns. */
4024 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4025 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4026 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4027 >= GET_MODE_BITSIZE (mode) + 1
4028 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4029 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4030 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4032 /* A truncate of a comparison can be replaced with a subreg if
4033 STORE_FLAG_VALUE permits. This is like the previous test,
4034 but it works even if the comparison is done in a mode larger
4035 than HOST_BITS_PER_WIDE_INT. */
4036 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4037 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4038 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4039 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4041 /* Similarly, a truncate of a register whose value is a
4042 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4044 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4045 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4046 && (temp = get_last_value (XEXP (x, 0)))
4047 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4048 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4052 case FLOAT_TRUNCATE:
4053 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4054 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4055 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4056 return XEXP (XEXP (x, 0), 0);
4058 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4059 (OP:SF foo:SF) if OP is NEG or ABS. */
4060 if ((GET_CODE (XEXP (x, 0)) == ABS
4061 || GET_CODE (XEXP (x, 0)) == NEG)
4062 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4063 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4064 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4065 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4067 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4068 is (float_truncate:SF x). */
4069 if (GET_CODE (XEXP (x, 0)) == SUBREG
4070 && subreg_lowpart_p (XEXP (x, 0))
4071 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4072 return SUBREG_REG (XEXP (x, 0));
4077 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4078 using cc0, in which case we want to leave it as a COMPARE
4079 so we can distinguish it from a register-register-copy. */
4080 if (XEXP (x, 1) == const0_rtx)
4083 /* In IEEE floating point, x-0 is not the same as x. */
4084 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4085 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4086 || flag_unsafe_math_optimizations)
4087 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4093 /* (const (const X)) can become (const X). Do it this way rather than
4094 returning the inner CONST since CONST can be shared with a
4096 if (GET_CODE (XEXP (x, 0)) == CONST)
4097 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4102 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4103 can add in an offset. find_split_point will split this address up
4104 again if it doesn't match. */
4105 if (GET_CODE (XEXP (x, 0)) == HIGH
4106 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4112 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4113 outermost. That's because that's the way indexed addresses are
4114 supposed to appear. This code used to check many more cases, but
4115 they are now checked elsewhere. */
4116 if (GET_CODE (XEXP (x, 0)) == PLUS
4117 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4118 return gen_binary (PLUS, mode,
4119 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4121 XEXP (XEXP (x, 0), 1));
4123 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4124 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4125 bit-field and can be replaced by either a sign_extend or a
4126 sign_extract. The `and' may be a zero_extend and the two
4127 <c>, -<c> constants may be reversed. */
4128 if (GET_CODE (XEXP (x, 0)) == XOR
4129 && GET_CODE (XEXP (x, 1)) == CONST_INT
4130 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4131 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4132 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4133 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4134 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4135 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4136 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4137 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4138 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4139 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4140 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4141 == (unsigned int) i + 1))))
4142 return simplify_shift_const
4143 (NULL_RTX, ASHIFTRT, mode,
4144 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4145 XEXP (XEXP (XEXP (x, 0), 0), 0),
4146 GET_MODE_BITSIZE (mode) - (i + 1)),
4147 GET_MODE_BITSIZE (mode) - (i + 1));
4149 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4150 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4151 is 1. This produces better code than the alternative immediately
4153 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4154 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4155 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4156 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4157 XEXP (XEXP (x, 0), 0),
4158 XEXP (XEXP (x, 0), 1))))
4160 simplify_gen_unary (NEG, mode, reversed, mode);
4162 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4163 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4164 the bitsize of the mode - 1. This allows simplification of
4165 "a = (b & 8) == 0;" */
4166 if (XEXP (x, 1) == constm1_rtx
4167 && GET_CODE (XEXP (x, 0)) != REG
4168 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4169 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4170 && nonzero_bits (XEXP (x, 0), mode) == 1)
4171 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4172 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4173 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4174 GET_MODE_BITSIZE (mode) - 1),
4175 GET_MODE_BITSIZE (mode) - 1);
4177 /* If we are adding two things that have no bits in common, convert
4178 the addition into an IOR. This will often be further simplified,
4179 for example in cases like ((a & 1) + (a & 2)), which can
4182 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4183 && (nonzero_bits (XEXP (x, 0), mode)
4184 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4186 /* Try to simplify the expression further. */
4187 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4188 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4190 /* If we could, great. If not, do not go ahead with the IOR
4191 replacement, since PLUS appears in many special purpose
4192 address arithmetic instructions. */
4193 if (GET_CODE (temp) != CLOBBER && temp != tor)
4199 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4200 by reversing the comparison code if valid. */
4201 if (STORE_FLAG_VALUE == 1
4202 && XEXP (x, 0) == const1_rtx
4203 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4204 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4205 XEXP (XEXP (x, 1), 0),
4206 XEXP (XEXP (x, 1), 1))))
4209 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4210 (and <foo> (const_int pow2-1)) */
4211 if (GET_CODE (XEXP (x, 1)) == AND
4212 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4213 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4214 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4215 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4216 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4218 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4220 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4221 return gen_binary (MINUS, mode,
4222 gen_binary (MINUS, mode, XEXP (x, 0),
4223 XEXP (XEXP (x, 1), 0)),
4224 XEXP (XEXP (x, 1), 1));
4228 /* If we have (mult (plus A B) C), apply the distributive law and then
4229 the inverse distributive law to see if things simplify. This
4230 occurs mostly in addresses, often when unrolling loops. */
4232 if (GET_CODE (XEXP (x, 0)) == PLUS)
4234 x = apply_distributive_law
4235 (gen_binary (PLUS, mode,
4236 gen_binary (MULT, mode,
4237 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4238 gen_binary (MULT, mode,
4239 XEXP (XEXP (x, 0), 1),
4240 copy_rtx (XEXP (x, 1)))));
4242 if (GET_CODE (x) != MULT)
4245 /* Try simplify a*(b/c) as (a*b)/c. */
4246 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4247 && GET_CODE (XEXP (x, 0)) == DIV)
4249 rtx tem = simplify_binary_operation (MULT, mode,
4250 XEXP (XEXP (x, 0), 0),
4253 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4258 /* If this is a divide by a power of two, treat it as a shift if
4259 its first operand is a shift. */
4260 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4261 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4262 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4263 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4264 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4265 || GET_CODE (XEXP (x, 0)) == ROTATE
4266 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4267 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4271 case GT: case GTU: case GE: case GEU:
4272 case LT: case LTU: case LE: case LEU:
4273 case UNEQ: case LTGT:
4274 case UNGT: case UNGE:
4275 case UNLT: case UNLE:
4276 case UNORDERED: case ORDERED:
4277 /* If the first operand is a condition code, we can't do anything
4279 if (GET_CODE (XEXP (x, 0)) == COMPARE
4280 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4282 && XEXP (x, 0) != cc0_rtx
4286 rtx op0 = XEXP (x, 0);
4287 rtx op1 = XEXP (x, 1);
4288 enum rtx_code new_code;
4290 if (GET_CODE (op0) == COMPARE)
4291 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4293 /* Simplify our comparison, if possible. */
4294 new_code = simplify_comparison (code, &op0, &op1);
4296 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4297 if only the low-order bit is possibly nonzero in X (such as when
4298 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4299 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4300 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4303 Remove any ZERO_EXTRACT we made when thinking this was a
4304 comparison. It may now be simpler to use, e.g., an AND. If a
4305 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4306 the call to make_compound_operation in the SET case. */
4308 if (STORE_FLAG_VALUE == 1
4309 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4310 && op1 == const0_rtx
4311 && mode == GET_MODE (op0)
4312 && nonzero_bits (op0, mode) == 1)
4313 return gen_lowpart_for_combine (mode,
4314 expand_compound_operation (op0));
4316 else if (STORE_FLAG_VALUE == 1
4317 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4318 && op1 == const0_rtx
4319 && mode == GET_MODE (op0)
4320 && (num_sign_bit_copies (op0, mode)
4321 == GET_MODE_BITSIZE (mode)))
4323 op0 = expand_compound_operation (op0);
4324 return simplify_gen_unary (NEG, mode,
4325 gen_lowpart_for_combine (mode, op0),
4329 else if (STORE_FLAG_VALUE == 1
4330 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4331 && op1 == const0_rtx
4332 && mode == GET_MODE (op0)
4333 && nonzero_bits (op0, mode) == 1)
4335 op0 = expand_compound_operation (op0);
4336 return gen_binary (XOR, mode,
4337 gen_lowpart_for_combine (mode, op0),
4341 else if (STORE_FLAG_VALUE == 1
4342 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4343 && op1 == const0_rtx
4344 && mode == GET_MODE (op0)
4345 && (num_sign_bit_copies (op0, mode)
4346 == GET_MODE_BITSIZE (mode)))
4348 op0 = expand_compound_operation (op0);
4349 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4352 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4354 if (STORE_FLAG_VALUE == -1
4355 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4356 && op1 == const0_rtx
4357 && (num_sign_bit_copies (op0, mode)
4358 == GET_MODE_BITSIZE (mode)))
4359 return gen_lowpart_for_combine (mode,
4360 expand_compound_operation (op0));
4362 else if (STORE_FLAG_VALUE == -1
4363 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4364 && op1 == const0_rtx
4365 && mode == GET_MODE (op0)
4366 && nonzero_bits (op0, mode) == 1)
4368 op0 = expand_compound_operation (op0);
4369 return simplify_gen_unary (NEG, mode,
4370 gen_lowpart_for_combine (mode, op0),
4374 else if (STORE_FLAG_VALUE == -1
4375 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4376 && op1 == const0_rtx
4377 && mode == GET_MODE (op0)
4378 && (num_sign_bit_copies (op0, mode)
4379 == GET_MODE_BITSIZE (mode)))
4381 op0 = expand_compound_operation (op0);
4382 return simplify_gen_unary (NOT, mode,
4383 gen_lowpart_for_combine (mode, op0),
4387 /* If X is 0/1, (eq X 0) is X-1. */
4388 else if (STORE_FLAG_VALUE == -1
4389 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4390 && op1 == const0_rtx
4391 && mode == GET_MODE (op0)
4392 && nonzero_bits (op0, mode) == 1)
4394 op0 = expand_compound_operation (op0);
4395 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4398 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4399 one bit that might be nonzero, we can convert (ne x 0) to
4400 (ashift x c) where C puts the bit in the sign bit. Remove any
4401 AND with STORE_FLAG_VALUE when we are done, since we are only
4402 going to test the sign bit. */
4403 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4404 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4405 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4406 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4407 && op1 == const0_rtx
4408 && mode == GET_MODE (op0)
4409 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4411 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4412 expand_compound_operation (op0),
4413 GET_MODE_BITSIZE (mode) - 1 - i);
4414 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4420 /* If the code changed, return a whole new comparison. */
4421 if (new_code != code)
4422 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4424 /* Otherwise, keep this operation, but maybe change its operands.
4425 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4426 SUBST (XEXP (x, 0), op0);
4427 SUBST (XEXP (x, 1), op1);
4432 return simplify_if_then_else (x);
4438 /* If we are processing SET_DEST, we are done. */
4442 return expand_compound_operation (x);
4445 return simplify_set (x);
4450 return simplify_logical (x, last);
4453 /* (abs (neg <foo>)) -> (abs <foo>) */
4454 if (GET_CODE (XEXP (x, 0)) == NEG)
4455 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4457 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4459 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4462 /* If operand is something known to be positive, ignore the ABS. */
4463 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4464 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4465 <= HOST_BITS_PER_WIDE_INT)
4466 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4467 & ((HOST_WIDE_INT) 1
4468 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4472 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4473 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4474 return gen_rtx_NEG (mode, XEXP (x, 0));
4479 /* (ffs (*_extend <X>)) = (ffs <X>) */
4480 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4481 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4482 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4486 /* (float (sign_extend <X>)) = (float <X>). */
4487 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4488 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4496 /* If this is a shift by a constant amount, simplify it. */
4497 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4498 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4499 INTVAL (XEXP (x, 1)));
4501 #ifdef SHIFT_COUNT_TRUNCATED
4502 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4504 force_to_mode (XEXP (x, 1), GET_MODE (x),
4506 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4515 rtx op0 = XEXP (x, 0);
4516 rtx op1 = XEXP (x, 1);
4519 if (GET_CODE (op1) != PARALLEL)
4521 len = XVECLEN (op1, 0);
4523 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4524 && GET_CODE (op0) == VEC_CONCAT)
4526 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4528 /* Try to find the element in the VEC_CONCAT. */
4531 if (GET_MODE (op0) == GET_MODE (x))
4533 if (GET_CODE (op0) == VEC_CONCAT)
4535 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4536 if (op0_size < offset)
4537 op0 = XEXP (op0, 0);
4541 op0 = XEXP (op0, 1);
4559 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4562 simplify_if_then_else (x)
4565 enum machine_mode mode = GET_MODE (x);
4566 rtx cond = XEXP (x, 0);
4567 rtx true_rtx = XEXP (x, 1);
4568 rtx false_rtx = XEXP (x, 2);
4569 enum rtx_code true_code = GET_CODE (cond);
4570 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4573 enum rtx_code false_code;
4576 /* Simplify storing of the truth value. */
4577 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4578 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4580 /* Also when the truth value has to be reversed. */
4582 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4583 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4587 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4588 in it is being compared against certain values. Get the true and false
4589 comparisons and see if that says anything about the value of each arm. */
4592 && ((false_code = combine_reversed_comparison_code (cond))
4594 && GET_CODE (XEXP (cond, 0)) == REG)
4597 rtx from = XEXP (cond, 0);
4598 rtx true_val = XEXP (cond, 1);
4599 rtx false_val = true_val;
4602 /* If FALSE_CODE is EQ, swap the codes and arms. */
4604 if (false_code == EQ)
4606 swapped = 1, true_code = EQ, false_code = NE;
4607 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4610 /* If we are comparing against zero and the expression being tested has
4611 only a single bit that might be nonzero, that is its value when it is
4612 not equal to zero. Similarly if it is known to be -1 or 0. */
4614 if (true_code == EQ && true_val == const0_rtx
4615 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4616 false_code = EQ, false_val = GEN_INT (nzb);
4617 else if (true_code == EQ && true_val == const0_rtx
4618 && (num_sign_bit_copies (from, GET_MODE (from))
4619 == GET_MODE_BITSIZE (GET_MODE (from))))
4620 false_code = EQ, false_val = constm1_rtx;
4622 /* Now simplify an arm if we know the value of the register in the
4623 branch and it is used in the arm. Be careful due to the potential
4624 of locally-shared RTL. */
4626 if (reg_mentioned_p (from, true_rtx))
4627 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4629 pc_rtx, pc_rtx, 0, 0);
4630 if (reg_mentioned_p (from, false_rtx))
4631 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4633 pc_rtx, pc_rtx, 0, 0);
4635 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4636 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4638 true_rtx = XEXP (x, 1);
4639 false_rtx = XEXP (x, 2);
4640 true_code = GET_CODE (cond);
4643 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4644 reversed, do so to avoid needing two sets of patterns for
4645 subtract-and-branch insns. Similarly if we have a constant in the true
4646 arm, the false arm is the same as the first operand of the comparison, or
4647 the false arm is more complicated than the true arm. */
4650 && combine_reversed_comparison_code (cond) != UNKNOWN
4651 && (true_rtx == pc_rtx
4652 || (CONSTANT_P (true_rtx)
4653 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4654 || true_rtx == const0_rtx
4655 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4656 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4657 || (GET_CODE (true_rtx) == SUBREG
4658 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4659 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4660 || reg_mentioned_p (true_rtx, false_rtx)
4661 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4663 true_code = reversed_comparison_code (cond, NULL);
4665 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4668 SUBST (XEXP (x, 1), false_rtx);
4669 SUBST (XEXP (x, 2), true_rtx);
4671 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4674 /* It is possible that the conditional has been simplified out. */
4675 true_code = GET_CODE (cond);
4676 comparison_p = GET_RTX_CLASS (true_code) == '<';
4679 /* If the two arms are identical, we don't need the comparison. */
4681 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4684 /* Convert a == b ? b : a to "a". */
4685 if (true_code == EQ && ! side_effects_p (cond)
4686 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4687 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4688 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4690 else if (true_code == NE && ! side_effects_p (cond)
4691 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4692 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4693 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4696 /* Look for cases where we have (abs x) or (neg (abs X)). */
4698 if (GET_MODE_CLASS (mode) == MODE_INT
4699 && GET_CODE (false_rtx) == NEG
4700 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4702 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4703 && ! side_effects_p (true_rtx))
4708 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4712 simplify_gen_unary (NEG, mode,
4713 simplify_gen_unary (ABS, mode, true_rtx, mode),
4719 /* Look for MIN or MAX. */
4721 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4723 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4724 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4725 && ! side_effects_p (cond))
4730 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4733 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4736 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4739 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4744 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4745 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4746 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4747 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4748 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4749 neither 1 or -1, but it isn't worth checking for. */
4751 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4752 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4754 rtx t = make_compound_operation (true_rtx, SET);
4755 rtx f = make_compound_operation (false_rtx, SET);
4756 rtx cond_op0 = XEXP (cond, 0);
4757 rtx cond_op1 = XEXP (cond, 1);
4758 enum rtx_code op = NIL, extend_op = NIL;
4759 enum machine_mode m = mode;
4760 rtx z = 0, c1 = NULL_RTX;
4762 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4763 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4764 || GET_CODE (t) == ASHIFT
4765 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4766 && rtx_equal_p (XEXP (t, 0), f))
4767 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4769 /* If an identity-zero op is commutative, check whether there
4770 would be a match if we swapped the operands. */
4771 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4772 || GET_CODE (t) == XOR)
4773 && rtx_equal_p (XEXP (t, 1), f))
4774 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4775 else if (GET_CODE (t) == SIGN_EXTEND
4776 && (GET_CODE (XEXP (t, 0)) == PLUS
4777 || GET_CODE (XEXP (t, 0)) == MINUS
4778 || GET_CODE (XEXP (t, 0)) == IOR
4779 || GET_CODE (XEXP (t, 0)) == XOR
4780 || GET_CODE (XEXP (t, 0)) == ASHIFT
4781 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4782 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4783 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4784 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4785 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4786 && (num_sign_bit_copies (f, GET_MODE (f))
4787 > (GET_MODE_BITSIZE (mode)
4788 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4790 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4791 extend_op = SIGN_EXTEND;
4792 m = GET_MODE (XEXP (t, 0));
4794 else if (GET_CODE (t) == SIGN_EXTEND
4795 && (GET_CODE (XEXP (t, 0)) == PLUS
4796 || GET_CODE (XEXP (t, 0)) == IOR
4797 || GET_CODE (XEXP (t, 0)) == XOR)
4798 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4799 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4800 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4801 && (num_sign_bit_copies (f, GET_MODE (f))
4802 > (GET_MODE_BITSIZE (mode)
4803 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4805 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4806 extend_op = SIGN_EXTEND;
4807 m = GET_MODE (XEXP (t, 0));
4809 else if (GET_CODE (t) == ZERO_EXTEND
4810 && (GET_CODE (XEXP (t, 0)) == PLUS
4811 || GET_CODE (XEXP (t, 0)) == MINUS
4812 || GET_CODE (XEXP (t, 0)) == IOR
4813 || GET_CODE (XEXP (t, 0)) == XOR
4814 || GET_CODE (XEXP (t, 0)) == ASHIFT
4815 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4816 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4817 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4818 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4819 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4820 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4821 && ((nonzero_bits (f, GET_MODE (f))
4822 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4825 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4826 extend_op = ZERO_EXTEND;
4827 m = GET_MODE (XEXP (t, 0));
4829 else if (GET_CODE (t) == ZERO_EXTEND
4830 && (GET_CODE (XEXP (t, 0)) == PLUS
4831 || GET_CODE (XEXP (t, 0)) == IOR
4832 || GET_CODE (XEXP (t, 0)) == XOR)
4833 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4834 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4835 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4836 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4837 && ((nonzero_bits (f, GET_MODE (f))
4838 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4841 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4842 extend_op = ZERO_EXTEND;
4843 m = GET_MODE (XEXP (t, 0));
4848 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4849 pc_rtx, pc_rtx, 0, 0);
4850 temp = gen_binary (MULT, m, temp,
4851 gen_binary (MULT, m, c1, const_true_rtx));
4852 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4853 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4855 if (extend_op != NIL)
4856 temp = simplify_gen_unary (extend_op, mode, temp, m);
4862 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4863 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4864 negation of a single bit, we can convert this operation to a shift. We
4865 can actually do this more generally, but it doesn't seem worth it. */
4867 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4868 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4869 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4870 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4871 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4872 == GET_MODE_BITSIZE (mode))
4873 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4875 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4876 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4881 /* Simplify X, a SET expression. Return the new expression. */
4887 rtx src = SET_SRC (x);
4888 rtx dest = SET_DEST (x);
4889 enum machine_mode mode
4890 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4894 /* (set (pc) (return)) gets written as (return). */
4895 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4898 /* Now that we know for sure which bits of SRC we are using, see if we can
4899 simplify the expression for the object knowing that we only need the
4902 if (GET_MODE_CLASS (mode) == MODE_INT)
4904 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4905 SUBST (SET_SRC (x), src);
4908 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4909 the comparison result and try to simplify it unless we already have used
4910 undobuf.other_insn. */
4911 if ((GET_CODE (src) == COMPARE
4916 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4917 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4918 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4919 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4921 enum rtx_code old_code = GET_CODE (*cc_use);
4922 enum rtx_code new_code;
4924 int other_changed = 0;
4925 enum machine_mode compare_mode = GET_MODE (dest);
4927 if (GET_CODE (src) == COMPARE)
4928 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4930 op0 = src, op1 = const0_rtx;
4932 /* Simplify our comparison, if possible. */
4933 new_code = simplify_comparison (old_code, &op0, &op1);
4935 #ifdef EXTRA_CC_MODES
4936 /* If this machine has CC modes other than CCmode, check to see if we
4937 need to use a different CC mode here. */
4938 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4939 #endif /* EXTRA_CC_MODES */
4941 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4942 /* If the mode changed, we have to change SET_DEST, the mode in the
4943 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4944 a hard register, just build new versions with the proper mode. If it
4945 is a pseudo, we lose unless it is only time we set the pseudo, in
4946 which case we can safely change its mode. */
4947 if (compare_mode != GET_MODE (dest))
4949 unsigned int regno = REGNO (dest);
4950 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4952 if (regno < FIRST_PSEUDO_REGISTER
4953 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4955 if (regno >= FIRST_PSEUDO_REGISTER)
4956 SUBST (regno_reg_rtx[regno], new_dest);
4958 SUBST (SET_DEST (x), new_dest);
4959 SUBST (XEXP (*cc_use, 0), new_dest);
4967 /* If the code changed, we have to build a new comparison in
4968 undobuf.other_insn. */
4969 if (new_code != old_code)
4971 unsigned HOST_WIDE_INT mask;
4973 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
4976 /* If the only change we made was to change an EQ into an NE or
4977 vice versa, OP0 has only one bit that might be nonzero, and OP1
4978 is zero, check if changing the user of the condition code will
4979 produce a valid insn. If it won't, we can keep the original code
4980 in that insn by surrounding our operation with an XOR. */
4982 if (((old_code == NE && new_code == EQ)
4983 || (old_code == EQ && new_code == NE))
4984 && ! other_changed && op1 == const0_rtx
4985 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4986 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4988 rtx pat = PATTERN (other_insn), note = 0;
4990 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4991 && ! check_asm_operands (pat)))
4993 PUT_CODE (*cc_use, old_code);
4996 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5004 undobuf.other_insn = other_insn;
5007 /* If we are now comparing against zero, change our source if
5008 needed. If we do not use cc0, we always have a COMPARE. */
5009 if (op1 == const0_rtx && dest == cc0_rtx)
5011 SUBST (SET_SRC (x), op0);
5017 /* Otherwise, if we didn't previously have a COMPARE in the
5018 correct mode, we need one. */
5019 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5021 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5026 /* Otherwise, update the COMPARE if needed. */
5027 SUBST (XEXP (src, 0), op0);
5028 SUBST (XEXP (src, 1), op1);
5033 /* Get SET_SRC in a form where we have placed back any
5034 compound expressions. Then do the checks below. */
5035 src = make_compound_operation (src, SET);
5036 SUBST (SET_SRC (x), src);
5039 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5040 and X being a REG or (subreg (reg)), we may be able to convert this to
5041 (set (subreg:m2 x) (op)).
5043 We can always do this if M1 is narrower than M2 because that means that
5044 we only care about the low bits of the result.
5046 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5047 perform a narrower operation than requested since the high-order bits will
5048 be undefined. On machine where it is defined, this transformation is safe
5049 as long as M1 and M2 have the same number of words. */
5051 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5052 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5053 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5055 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5056 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5057 #ifndef WORD_REGISTER_OPERATIONS
5058 && (GET_MODE_SIZE (GET_MODE (src))
5059 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5061 #ifdef CLASS_CANNOT_CHANGE_MODE
5062 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5063 && (TEST_HARD_REG_BIT
5064 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5066 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5067 GET_MODE (SUBREG_REG (src))))
5069 && (GET_CODE (dest) == REG
5070 || (GET_CODE (dest) == SUBREG
5071 && GET_CODE (SUBREG_REG (dest)) == REG)))
5073 SUBST (SET_DEST (x),
5074 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5076 SUBST (SET_SRC (x), SUBREG_REG (src));
5078 src = SET_SRC (x), dest = SET_DEST (x);
5081 #ifdef LOAD_EXTEND_OP
5082 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5083 would require a paradoxical subreg. Replace the subreg with a
5084 zero_extend to avoid the reload that would otherwise be required. */
5086 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5087 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5088 && SUBREG_BYTE (src) == 0
5089 && (GET_MODE_SIZE (GET_MODE (src))
5090 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5091 && GET_CODE (SUBREG_REG (src)) == MEM)
5094 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5095 GET_MODE (src), SUBREG_REG (src)));
5101 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5102 are comparing an item known to be 0 or -1 against 0, use a logical
5103 operation instead. Check for one of the arms being an IOR of the other
5104 arm with some value. We compute three terms to be IOR'ed together. In
5105 practice, at most two will be nonzero. Then we do the IOR's. */
5107 if (GET_CODE (dest) != PC
5108 && GET_CODE (src) == IF_THEN_ELSE
5109 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5110 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5111 && XEXP (XEXP (src, 0), 1) == const0_rtx
5112 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5113 #ifdef HAVE_conditional_move
5114 && ! can_conditionally_move_p (GET_MODE (src))
5116 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5117 GET_MODE (XEXP (XEXP (src, 0), 0)))
5118 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5119 && ! side_effects_p (src))
5121 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5122 ? XEXP (src, 1) : XEXP (src, 2));
5123 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5124 ? XEXP (src, 2) : XEXP (src, 1));
5125 rtx term1 = const0_rtx, term2, term3;
5127 if (GET_CODE (true_rtx) == IOR
5128 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5129 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5130 else if (GET_CODE (true_rtx) == IOR
5131 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5132 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5133 else if (GET_CODE (false_rtx) == IOR
5134 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5135 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5136 else if (GET_CODE (false_rtx) == IOR
5137 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5138 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5140 term2 = gen_binary (AND, GET_MODE (src),
5141 XEXP (XEXP (src, 0), 0), true_rtx);
5142 term3 = gen_binary (AND, GET_MODE (src),
5143 simplify_gen_unary (NOT, GET_MODE (src),
5144 XEXP (XEXP (src, 0), 0),
5149 gen_binary (IOR, GET_MODE (src),
5150 gen_binary (IOR, GET_MODE (src), term1, term2),
5156 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5157 whole thing fail. */
5158 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5160 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5163 /* Convert this into a field assignment operation, if possible. */
5164 return make_field_assignment (x);
5167 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5168 result. LAST is nonzero if this is the last retry. */
5171 simplify_logical (x, last)
5175 enum machine_mode mode = GET_MODE (x);
5176 rtx op0 = XEXP (x, 0);
5177 rtx op1 = XEXP (x, 1);
5180 switch (GET_CODE (x))
5183 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5184 insn (and may simplify more). */
5185 if (GET_CODE (op0) == XOR
5186 && rtx_equal_p (XEXP (op0, 0), op1)
5187 && ! side_effects_p (op1))
5188 x = gen_binary (AND, mode,
5189 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5192 if (GET_CODE (op0) == XOR
5193 && rtx_equal_p (XEXP (op0, 1), op1)
5194 && ! side_effects_p (op1))
5195 x = gen_binary (AND, mode,
5196 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5199 /* Similarly for (~(A ^ B)) & A. */
5200 if (GET_CODE (op0) == NOT
5201 && GET_CODE (XEXP (op0, 0)) == XOR
5202 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5203 && ! side_effects_p (op1))
5204 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5206 if (GET_CODE (op0) == NOT
5207 && GET_CODE (XEXP (op0, 0)) == XOR
5208 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5209 && ! side_effects_p (op1))
5210 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5212 /* We can call simplify_and_const_int only if we don't lose
5213 any (sign) bits when converting INTVAL (op1) to
5214 "unsigned HOST_WIDE_INT". */
5215 if (GET_CODE (op1) == CONST_INT
5216 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5217 || INTVAL (op1) > 0))
5219 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5221 /* If we have (ior (and (X C1) C2)) and the next restart would be
5222 the last, simplify this by making C1 as small as possible
5225 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5226 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5227 && GET_CODE (op1) == CONST_INT)
5228 return gen_binary (IOR, mode,
5229 gen_binary (AND, mode, XEXP (op0, 0),
5230 GEN_INT (INTVAL (XEXP (op0, 1))
5231 & ~INTVAL (op1))), op1);
5233 if (GET_CODE (x) != AND)
5236 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5237 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5238 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5241 /* Convert (A | B) & A to A. */
5242 if (GET_CODE (op0) == IOR
5243 && (rtx_equal_p (XEXP (op0, 0), op1)
5244 || rtx_equal_p (XEXP (op0, 1), op1))
5245 && ! side_effects_p (XEXP (op0, 0))
5246 && ! side_effects_p (XEXP (op0, 1)))
5249 /* In the following group of tests (and those in case IOR below),
5250 we start with some combination of logical operations and apply
5251 the distributive law followed by the inverse distributive law.
5252 Most of the time, this results in no change. However, if some of
5253 the operands are the same or inverses of each other, simplifications
5256 For example, (and (ior A B) (not B)) can occur as the result of
5257 expanding a bit field assignment. When we apply the distributive
5258 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5259 which then simplifies to (and (A (not B))).
5261 If we have (and (ior A B) C), apply the distributive law and then
5262 the inverse distributive law to see if things simplify. */
5264 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5266 x = apply_distributive_law
5267 (gen_binary (GET_CODE (op0), mode,
5268 gen_binary (AND, mode, XEXP (op0, 0), op1),
5269 gen_binary (AND, mode, XEXP (op0, 1),
5271 if (GET_CODE (x) != AND)
5275 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5276 return apply_distributive_law
5277 (gen_binary (GET_CODE (op1), mode,
5278 gen_binary (AND, mode, XEXP (op1, 0), op0),
5279 gen_binary (AND, mode, XEXP (op1, 1),
5282 /* Similarly, taking advantage of the fact that
5283 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5285 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5286 return apply_distributive_law
5287 (gen_binary (XOR, mode,
5288 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5289 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5292 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5293 return apply_distributive_law
5294 (gen_binary (XOR, mode,
5295 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5296 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5300 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5301 if (GET_CODE (op1) == CONST_INT
5302 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5303 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5306 /* Convert (A & B) | A to A. */
5307 if (GET_CODE (op0) == AND
5308 && (rtx_equal_p (XEXP (op0, 0), op1)
5309 || rtx_equal_p (XEXP (op0, 1), op1))
5310 && ! side_effects_p (XEXP (op0, 0))
5311 && ! side_effects_p (XEXP (op0, 1)))
5314 /* If we have (ior (and A B) C), apply the distributive law and then
5315 the inverse distributive law to see if things simplify. */
5317 if (GET_CODE (op0) == AND)
5319 x = apply_distributive_law
5320 (gen_binary (AND, mode,
5321 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5322 gen_binary (IOR, mode, XEXP (op0, 1),
5325 if (GET_CODE (x) != IOR)
5329 if (GET_CODE (op1) == AND)
5331 x = apply_distributive_law
5332 (gen_binary (AND, mode,
5333 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5334 gen_binary (IOR, mode, XEXP (op1, 1),
5337 if (GET_CODE (x) != IOR)
5341 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5342 mode size to (rotate A CX). */
5344 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5345 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5346 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5347 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5348 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5349 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5350 == GET_MODE_BITSIZE (mode)))
5351 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5352 (GET_CODE (op0) == ASHIFT
5353 ? XEXP (op0, 1) : XEXP (op1, 1)));
5355 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5356 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5357 does not affect any of the bits in OP1, it can really be done
5358 as a PLUS and we can associate. We do this by seeing if OP1
5359 can be safely shifted left C bits. */
5360 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5361 && GET_CODE (XEXP (op0, 0)) == PLUS
5362 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5363 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5364 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5366 int count = INTVAL (XEXP (op0, 1));
5367 HOST_WIDE_INT mask = INTVAL (op1) << count;
5369 if (mask >> count == INTVAL (op1)
5370 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5372 SUBST (XEXP (XEXP (op0, 0), 1),
5373 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5380 /* If we are XORing two things that have no bits in common,
5381 convert them into an IOR. This helps to detect rotation encoded
5382 using those methods and possibly other simplifications. */
5384 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5385 && (nonzero_bits (op0, mode)
5386 & nonzero_bits (op1, mode)) == 0)
5387 return (gen_binary (IOR, mode, op0, op1));
5389 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5390 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5393 int num_negated = 0;
5395 if (GET_CODE (op0) == NOT)
5396 num_negated++, op0 = XEXP (op0, 0);
5397 if (GET_CODE (op1) == NOT)
5398 num_negated++, op1 = XEXP (op1, 0);
5400 if (num_negated == 2)
5402 SUBST (XEXP (x, 0), op0);
5403 SUBST (XEXP (x, 1), op1);
5405 else if (num_negated == 1)
5407 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5411 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5412 correspond to a machine insn or result in further simplifications
5413 if B is a constant. */
5415 if (GET_CODE (op0) == AND
5416 && rtx_equal_p (XEXP (op0, 1), op1)
5417 && ! side_effects_p (op1))
5418 return gen_binary (AND, mode,
5419 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5422 else if (GET_CODE (op0) == AND
5423 && rtx_equal_p (XEXP (op0, 0), op1)
5424 && ! side_effects_p (op1))
5425 return gen_binary (AND, mode,
5426 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5429 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5430 comparison if STORE_FLAG_VALUE is 1. */
5431 if (STORE_FLAG_VALUE == 1
5432 && op1 == const1_rtx
5433 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5434 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5438 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5439 is (lt foo (const_int 0)), so we can perform the above
5440 simplification if STORE_FLAG_VALUE is 1. */
5442 if (STORE_FLAG_VALUE == 1
5443 && op1 == const1_rtx
5444 && GET_CODE (op0) == LSHIFTRT
5445 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5446 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5447 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5449 /* (xor (comparison foo bar) (const_int sign-bit))
5450 when STORE_FLAG_VALUE is the sign bit. */
5451 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5452 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5453 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5454 && op1 == const_true_rtx
5455 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5456 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5469 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5470 operations" because they can be replaced with two more basic operations.
5471 ZERO_EXTEND is also considered "compound" because it can be replaced with
5472 an AND operation, which is simpler, though only one operation.
5474 The function expand_compound_operation is called with an rtx expression
5475 and will convert it to the appropriate shifts and AND operations,
5476 simplifying at each stage.
5478 The function make_compound_operation is called to convert an expression
5479 consisting of shifts and ANDs into the equivalent compound expression.
5480 It is the inverse of this function, loosely speaking. */
5483 expand_compound_operation (x)
5486 unsigned HOST_WIDE_INT pos = 0, len;
5488 unsigned int modewidth;
5491 switch (GET_CODE (x))
5496 /* We can't necessarily use a const_int for a multiword mode;
5497 it depends on implicitly extending the value.
5498 Since we don't know the right way to extend it,
5499 we can't tell whether the implicit way is right.
5501 Even for a mode that is no wider than a const_int,
5502 we can't win, because we need to sign extend one of its bits through
5503 the rest of it, and we don't know which bit. */
5504 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5507 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5508 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5509 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5510 reloaded. If not for that, MEM's would very rarely be safe.
5512 Reject MODEs bigger than a word, because we might not be able
5513 to reference a two-register group starting with an arbitrary register
5514 (and currently gen_lowpart might crash for a SUBREG). */
5516 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5519 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5520 /* If the inner object has VOIDmode (the only way this can happen
5521 is if it is a ASM_OPERANDS), we can't do anything since we don't
5522 know how much masking to do. */
5531 /* If the operand is a CLOBBER, just return it. */
5532 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5535 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5536 || GET_CODE (XEXP (x, 2)) != CONST_INT
5537 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5540 len = INTVAL (XEXP (x, 1));
5541 pos = INTVAL (XEXP (x, 2));
5543 /* If this goes outside the object being extracted, replace the object
5544 with a (use (mem ...)) construct that only combine understands
5545 and is used only for this purpose. */
5546 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5547 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5549 if (BITS_BIG_ENDIAN)
5550 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5557 /* Convert sign extension to zero extension, if we know that the high
5558 bit is not set, as this is easier to optimize. It will be converted
5559 back to cheaper alternative in make_extraction. */
5560 if (GET_CODE (x) == SIGN_EXTEND
5561 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5562 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5563 & ~(((unsigned HOST_WIDE_INT)
5564 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5568 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5569 return expand_compound_operation (temp);
5572 /* We can optimize some special cases of ZERO_EXTEND. */
5573 if (GET_CODE (x) == ZERO_EXTEND)
5575 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5576 know that the last value didn't have any inappropriate bits
5578 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5579 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5580 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5581 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5582 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5583 return XEXP (XEXP (x, 0), 0);
5585 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5586 if (GET_CODE (XEXP (x, 0)) == SUBREG
5587 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5588 && subreg_lowpart_p (XEXP (x, 0))
5589 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5590 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5591 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5592 return SUBREG_REG (XEXP (x, 0));
5594 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5595 is a comparison and STORE_FLAG_VALUE permits. This is like
5596 the first case, but it works even when GET_MODE (x) is larger
5597 than HOST_WIDE_INT. */
5598 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5599 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5600 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5601 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5602 <= HOST_BITS_PER_WIDE_INT)
5603 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5604 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5605 return XEXP (XEXP (x, 0), 0);
5607 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5608 if (GET_CODE (XEXP (x, 0)) == SUBREG
5609 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5610 && subreg_lowpart_p (XEXP (x, 0))
5611 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5612 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5613 <= HOST_BITS_PER_WIDE_INT)
5614 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5615 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5616 return SUBREG_REG (XEXP (x, 0));
5620 /* If we reach here, we want to return a pair of shifts. The inner
5621 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5622 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5623 logical depending on the value of UNSIGNEDP.
5625 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5626 converted into an AND of a shift.
5628 We must check for the case where the left shift would have a negative
5629 count. This can happen in a case like (x >> 31) & 255 on machines
5630 that can't shift by a constant. On those machines, we would first
5631 combine the shift with the AND to produce a variable-position
5632 extraction. Then the constant of 31 would be substituted in to produce
5633 a such a position. */
5635 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5636 if (modewidth + len >= pos)
5637 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5639 simplify_shift_const (NULL_RTX, ASHIFT,
5642 modewidth - pos - len),
5645 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5646 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5647 simplify_shift_const (NULL_RTX, LSHIFTRT,
5650 ((HOST_WIDE_INT) 1 << len) - 1);
5652 /* Any other cases we can't handle. */
5655 /* If we couldn't do this for some reason, return the original
5657 if (GET_CODE (tem) == CLOBBER)
5663 /* X is a SET which contains an assignment of one object into
5664 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5665 or certain SUBREGS). If possible, convert it into a series of
5668 We half-heartedly support variable positions, but do not at all
5669 support variable lengths. */
5672 expand_field_assignment (x)
5676 rtx pos; /* Always counts from low bit. */
5679 enum machine_mode compute_mode;
5681 /* Loop until we find something we can't simplify. */
5684 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5685 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5687 int byte_offset = SUBREG_BYTE (XEXP (SET_DEST (x), 0));
5689 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5690 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5691 pos = GEN_INT (BITS_PER_WORD * (byte_offset / UNITS_PER_WORD));
5693 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5694 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5696 inner = XEXP (SET_DEST (x), 0);
5697 len = INTVAL (XEXP (SET_DEST (x), 1));
5698 pos = XEXP (SET_DEST (x), 2);
5700 /* If the position is constant and spans the width of INNER,
5701 surround INNER with a USE to indicate this. */
5702 if (GET_CODE (pos) == CONST_INT
5703 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5704 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5706 if (BITS_BIG_ENDIAN)
5708 if (GET_CODE (pos) == CONST_INT)
5709 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5711 else if (GET_CODE (pos) == MINUS
5712 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5713 && (INTVAL (XEXP (pos, 1))
5714 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5715 /* If position is ADJUST - X, new position is X. */
5716 pos = XEXP (pos, 0);
5718 pos = gen_binary (MINUS, GET_MODE (pos),
5719 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5725 /* A SUBREG between two modes that occupy the same numbers of words
5726 can be done by moving the SUBREG to the source. */
5727 else if (GET_CODE (SET_DEST (x)) == SUBREG
5728 /* We need SUBREGs to compute nonzero_bits properly. */
5729 && nonzero_sign_valid
5730 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5731 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5732 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5733 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5735 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5736 gen_lowpart_for_combine
5737 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5744 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5745 inner = SUBREG_REG (inner);
5747 compute_mode = GET_MODE (inner);
5749 /* Don't attempt bitwise arithmetic on non-integral modes. */
5750 if (! INTEGRAL_MODE_P (compute_mode))
5752 enum machine_mode imode;
5754 /* Something is probably seriously wrong if this matches. */
5755 if (! FLOAT_MODE_P (compute_mode))
5758 /* Try to find an integral mode to pun with. */
5759 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5760 if (imode == BLKmode)
5763 compute_mode = imode;
5764 inner = gen_lowpart_for_combine (imode, inner);
5767 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5768 if (len < HOST_BITS_PER_WIDE_INT)
5769 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5773 /* Now compute the equivalent expression. Make a copy of INNER
5774 for the SET_DEST in case it is a MEM into which we will substitute;
5775 we don't want shared RTL in that case. */
5777 (VOIDmode, copy_rtx (inner),
5778 gen_binary (IOR, compute_mode,
5779 gen_binary (AND, compute_mode,
5780 simplify_gen_unary (NOT, compute_mode,
5786 gen_binary (ASHIFT, compute_mode,
5787 gen_binary (AND, compute_mode,
5788 gen_lowpart_for_combine
5789 (compute_mode, SET_SRC (x)),
5797 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5798 it is an RTX that represents a variable starting position; otherwise,
5799 POS is the (constant) starting bit position (counted from the LSB).
5801 INNER may be a USE. This will occur when we started with a bitfield
5802 that went outside the boundary of the object in memory, which is
5803 allowed on most machines. To isolate this case, we produce a USE
5804 whose mode is wide enough and surround the MEM with it. The only
5805 code that understands the USE is this routine. If it is not removed,
5806 it will cause the resulting insn not to match.
5808 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5811 IN_DEST is non-zero if this is a reference in the destination of a
5812 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5813 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5816 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5817 ZERO_EXTRACT should be built even for bits starting at bit 0.
5819 MODE is the desired mode of the result (if IN_DEST == 0).
5821 The result is an RTX for the extraction or NULL_RTX if the target
5825 make_extraction (mode, inner, pos, pos_rtx, len,
5826 unsignedp, in_dest, in_compare)
5827 enum machine_mode mode;
5831 unsigned HOST_WIDE_INT len;
5833 int in_dest, in_compare;
5835 /* This mode describes the size of the storage area
5836 to fetch the overall value from. Within that, we
5837 ignore the POS lowest bits, etc. */
5838 enum machine_mode is_mode = GET_MODE (inner);
5839 enum machine_mode inner_mode;
5840 enum machine_mode wanted_inner_mode = byte_mode;
5841 enum machine_mode wanted_inner_reg_mode = word_mode;
5842 enum machine_mode pos_mode = word_mode;
5843 enum machine_mode extraction_mode = word_mode;
5844 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5847 rtx orig_pos_rtx = pos_rtx;
5848 HOST_WIDE_INT orig_pos;
5850 /* Get some information about INNER and get the innermost object. */
5851 if (GET_CODE (inner) == USE)
5852 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5853 /* We don't need to adjust the position because we set up the USE
5854 to pretend that it was a full-word object. */
5855 spans_byte = 1, inner = XEXP (inner, 0);
5856 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5858 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5859 consider just the QI as the memory to extract from.
5860 The subreg adds or removes high bits; its mode is
5861 irrelevant to the meaning of this extraction,
5862 since POS and LEN count from the lsb. */
5863 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5864 is_mode = GET_MODE (SUBREG_REG (inner));
5865 inner = SUBREG_REG (inner);
5868 inner_mode = GET_MODE (inner);
5870 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5871 pos = INTVAL (pos_rtx), pos_rtx = 0;
5873 /* See if this can be done without an extraction. We never can if the
5874 width of the field is not the same as that of some integer mode. For
5875 registers, we can only avoid the extraction if the position is at the
5876 low-order bit and this is either not in the destination or we have the
5877 appropriate STRICT_LOW_PART operation available.
5879 For MEM, we can avoid an extract if the field starts on an appropriate
5880 boundary and we can change the mode of the memory reference. However,
5881 we cannot directly access the MEM if we have a USE and the underlying
5882 MEM is not TMODE. This combination means that MEM was being used in a
5883 context where bits outside its mode were being referenced; that is only
5884 valid in bit-field insns. */
5886 if (tmode != BLKmode
5887 && ! (spans_byte && inner_mode != tmode)
5888 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5889 && GET_CODE (inner) != MEM
5891 || (GET_CODE (inner) == REG
5892 && have_insn_for (STRICT_LOW_PART, tmode))))
5893 || (GET_CODE (inner) == MEM && pos_rtx == 0
5895 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5896 : BITS_PER_UNIT)) == 0
5897 /* We can't do this if we are widening INNER_MODE (it
5898 may not be aligned, for one thing). */
5899 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5900 && (inner_mode == tmode
5901 || (! mode_dependent_address_p (XEXP (inner, 0))
5902 && ! MEM_VOLATILE_P (inner))))))
5904 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5905 field. If the original and current mode are the same, we need not
5906 adjust the offset. Otherwise, we do if bytes big endian.
5908 If INNER is not a MEM, get a piece consisting of just the field
5909 of interest (in this case POS % BITS_PER_WORD must be 0). */
5911 if (GET_CODE (inner) == MEM)
5913 HOST_WIDE_INT offset;
5915 /* POS counts from lsb, but make OFFSET count in memory order. */
5916 if (BYTES_BIG_ENDIAN)
5917 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5919 offset = pos / BITS_PER_UNIT;
5921 new = adjust_address_nv (inner, tmode, offset);
5923 else if (GET_CODE (inner) == REG)
5925 /* We can't call gen_lowpart_for_combine here since we always want
5926 a SUBREG and it would sometimes return a new hard register. */
5927 if (tmode != inner_mode)
5929 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5931 if (WORDS_BIG_ENDIAN
5932 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5933 final_word = ((GET_MODE_SIZE (inner_mode)
5934 - GET_MODE_SIZE (tmode))
5935 / UNITS_PER_WORD) - final_word;
5937 final_word *= UNITS_PER_WORD;
5938 if (BYTES_BIG_ENDIAN &&
5939 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5940 final_word += (GET_MODE_SIZE (inner_mode)
5941 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5943 new = gen_rtx_SUBREG (tmode, inner, final_word);
5949 new = force_to_mode (inner, tmode,
5950 len >= HOST_BITS_PER_WIDE_INT
5951 ? ~(unsigned HOST_WIDE_INT) 0
5952 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5955 /* If this extraction is going into the destination of a SET,
5956 make a STRICT_LOW_PART unless we made a MEM. */
5959 return (GET_CODE (new) == MEM ? new
5960 : (GET_CODE (new) != SUBREG
5961 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5962 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
5967 /* If we know that no extraneous bits are set, and that the high
5968 bit is not set, convert the extraction to the cheaper of
5969 sign and zero extension, that are equivalent in these cases. */
5970 if (flag_expensive_optimizations
5971 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5972 && ((nonzero_bits (new, tmode)
5973 & ~(((unsigned HOST_WIDE_INT)
5974 GET_MODE_MASK (tmode))
5978 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5979 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5981 /* Prefer ZERO_EXTENSION, since it gives more information to
5983 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
5988 /* Otherwise, sign- or zero-extend unless we already are in the
5991 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5995 /* Unless this is a COMPARE or we have a funny memory reference,
5996 don't do anything with zero-extending field extracts starting at
5997 the low-order bit since they are simple AND operations. */
5998 if (pos_rtx == 0 && pos == 0 && ! in_dest
5999 && ! in_compare && ! spans_byte && unsignedp)
6002 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6003 we would be spanning bytes or if the position is not a constant and the
6004 length is not 1. In all other cases, we would only be going outside
6005 our object in cases when an original shift would have been
6007 if (! spans_byte && GET_CODE (inner) == MEM
6008 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6009 || (pos_rtx != 0 && len != 1)))
6012 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6013 and the mode for the result. */
6014 if (in_dest && mode_for_extraction(EP_insv, -1) != MAX_MACHINE_MODE)
6016 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6017 pos_mode = mode_for_extraction (EP_insv, 2);
6018 extraction_mode = mode_for_extraction (EP_insv, 3);
6021 if (! in_dest && unsignedp
6022 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6024 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6025 pos_mode = mode_for_extraction (EP_extzv, 3);
6026 extraction_mode = mode_for_extraction (EP_extzv, 0);
6029 if (! in_dest && ! unsignedp
6030 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6032 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6033 pos_mode = mode_for_extraction (EP_extv, 3);
6034 extraction_mode = mode_for_extraction (EP_extv, 0);
6037 /* Never narrow an object, since that might not be safe. */
6039 if (mode != VOIDmode
6040 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6041 extraction_mode = mode;
6043 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6044 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6045 pos_mode = GET_MODE (pos_rtx);
6047 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6048 if we have to change the mode of memory and cannot, the desired mode is
6050 if (GET_CODE (inner) != MEM)
6051 wanted_inner_mode = wanted_inner_reg_mode;
6052 else if (inner_mode != wanted_inner_mode
6053 && (mode_dependent_address_p (XEXP (inner, 0))
6054 || MEM_VOLATILE_P (inner)))
6055 wanted_inner_mode = extraction_mode;
6059 if (BITS_BIG_ENDIAN)
6061 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6062 BITS_BIG_ENDIAN style. If position is constant, compute new
6063 position. Otherwise, build subtraction.
6064 Note that POS is relative to the mode of the original argument.
6065 If it's a MEM we need to recompute POS relative to that.
6066 However, if we're extracting from (or inserting into) a register,
6067 we want to recompute POS relative to wanted_inner_mode. */
6068 int width = (GET_CODE (inner) == MEM
6069 ? GET_MODE_BITSIZE (is_mode)
6070 : GET_MODE_BITSIZE (wanted_inner_mode));
6073 pos = width - len - pos;
6076 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6077 /* POS may be less than 0 now, but we check for that below.
6078 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6081 /* If INNER has a wider mode, make it smaller. If this is a constant
6082 extract, try to adjust the byte to point to the byte containing
6084 if (wanted_inner_mode != VOIDmode
6085 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6086 && ((GET_CODE (inner) == MEM
6087 && (inner_mode == wanted_inner_mode
6088 || (! mode_dependent_address_p (XEXP (inner, 0))
6089 && ! MEM_VOLATILE_P (inner))))))
6093 /* The computations below will be correct if the machine is big
6094 endian in both bits and bytes or little endian in bits and bytes.
6095 If it is mixed, we must adjust. */
6097 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6098 adjust OFFSET to compensate. */
6099 if (BYTES_BIG_ENDIAN
6101 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6102 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6104 /* If this is a constant position, we can move to the desired byte. */
6107 offset += pos / BITS_PER_UNIT;
6108 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6111 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6113 && is_mode != wanted_inner_mode)
6114 offset = (GET_MODE_SIZE (is_mode)
6115 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6117 if (offset != 0 || inner_mode != wanted_inner_mode)
6118 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6121 /* If INNER is not memory, we can always get it into the proper mode. If we
6122 are changing its mode, POS must be a constant and smaller than the size
6124 else if (GET_CODE (inner) != MEM)
6126 if (GET_MODE (inner) != wanted_inner_mode
6128 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6131 inner = force_to_mode (inner, wanted_inner_mode,
6133 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6134 ? ~(unsigned HOST_WIDE_INT) 0
6135 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6140 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6141 have to zero extend. Otherwise, we can just use a SUBREG. */
6143 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6145 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6147 /* If we know that no extraneous bits are set, and that the high
6148 bit is not set, convert extraction to cheaper one - either
6149 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6151 if (flag_expensive_optimizations
6152 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6153 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6154 & ~(((unsigned HOST_WIDE_INT)
6155 GET_MODE_MASK (GET_MODE (pos_rtx)))
6159 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6161 /* Prefer ZERO_EXTENSION, since it gives more information to
6163 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6168 else if (pos_rtx != 0
6169 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6170 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6172 /* Make POS_RTX unless we already have it and it is correct. If we don't
6173 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6175 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6176 pos_rtx = orig_pos_rtx;
6178 else if (pos_rtx == 0)
6179 pos_rtx = GEN_INT (pos);
6181 /* Make the required operation. See if we can use existing rtx. */
6182 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6183 extraction_mode, inner, GEN_INT (len), pos_rtx);
6185 new = gen_lowpart_for_combine (mode, new);
6190 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6191 with any other operations in X. Return X without that shift if so. */
6194 extract_left_shift (x, count)
6198 enum rtx_code code = GET_CODE (x);
6199 enum machine_mode mode = GET_MODE (x);
6205 /* This is the shift itself. If it is wide enough, we will return
6206 either the value being shifted if the shift count is equal to
6207 COUNT or a shift for the difference. */
6208 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6209 && INTVAL (XEXP (x, 1)) >= count)
6210 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6211 INTVAL (XEXP (x, 1)) - count);
6215 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6216 return simplify_gen_unary (code, mode, tem, mode);
6220 case PLUS: case IOR: case XOR: case AND:
6221 /* If we can safely shift this constant and we find the inner shift,
6222 make a new operation. */
6223 if (GET_CODE (XEXP (x,1)) == CONST_INT
6224 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6225 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6226 return gen_binary (code, mode, tem,
6227 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6238 /* Look at the expression rooted at X. Look for expressions
6239 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6240 Form these expressions.
6242 Return the new rtx, usually just X.
6244 Also, for machines like the VAX that don't have logical shift insns,
6245 try to convert logical to arithmetic shift operations in cases where
6246 they are equivalent. This undoes the canonicalizations to logical
6247 shifts done elsewhere.
6249 We try, as much as possible, to re-use rtl expressions to save memory.
6251 IN_CODE says what kind of expression we are processing. Normally, it is
6252 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6253 being kludges), it is MEM. When processing the arguments of a comparison
6254 or a COMPARE against zero, it is COMPARE. */
6257 make_compound_operation (x, in_code)
6259 enum rtx_code in_code;
6261 enum rtx_code code = GET_CODE (x);
6262 enum machine_mode mode = GET_MODE (x);
6263 int mode_width = GET_MODE_BITSIZE (mode);
6265 enum rtx_code next_code;
6271 /* Select the code to be used in recursive calls. Once we are inside an
6272 address, we stay there. If we have a comparison, set to COMPARE,
6273 but once inside, go back to our default of SET. */
6275 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6276 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6277 && XEXP (x, 1) == const0_rtx) ? COMPARE
6278 : in_code == COMPARE ? SET : in_code);
6280 /* Process depending on the code of this operation. If NEW is set
6281 non-zero, it will be returned. */
6286 /* Convert shifts by constants into multiplications if inside
6288 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6289 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6290 && INTVAL (XEXP (x, 1)) >= 0)
6292 new = make_compound_operation (XEXP (x, 0), next_code);
6293 new = gen_rtx_MULT (mode, new,
6294 GEN_INT ((HOST_WIDE_INT) 1
6295 << INTVAL (XEXP (x, 1))));
6300 /* If the second operand is not a constant, we can't do anything
6302 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6305 /* If the constant is a power of two minus one and the first operand
6306 is a logical right shift, make an extraction. */
6307 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6308 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6310 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6311 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6312 0, in_code == COMPARE);
6315 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6316 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6317 && subreg_lowpart_p (XEXP (x, 0))
6318 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6319 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6321 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6323 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6324 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6325 0, in_code == COMPARE);
6327 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6328 else if ((GET_CODE (XEXP (x, 0)) == XOR
6329 || GET_CODE (XEXP (x, 0)) == IOR)
6330 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6331 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6332 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6334 /* Apply the distributive law, and then try to make extractions. */
6335 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6336 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6338 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6340 new = make_compound_operation (new, in_code);
6343 /* If we are have (and (rotate X C) M) and C is larger than the number
6344 of bits in M, this is an extraction. */
6346 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6347 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6348 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6349 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6351 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6352 new = make_extraction (mode, new,
6353 (GET_MODE_BITSIZE (mode)
6354 - INTVAL (XEXP (XEXP (x, 0), 1))),
6355 NULL_RTX, i, 1, 0, in_code == COMPARE);
6358 /* On machines without logical shifts, if the operand of the AND is
6359 a logical shift and our mask turns off all the propagated sign
6360 bits, we can replace the logical shift with an arithmetic shift. */
6361 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6362 && !have_insn_for (LSHIFTRT, mode)
6363 && have_insn_for (ASHIFTRT, mode)
6364 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6365 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6366 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6367 && mode_width <= HOST_BITS_PER_WIDE_INT)
6369 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6371 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6372 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6374 gen_rtx_ASHIFTRT (mode,
6375 make_compound_operation
6376 (XEXP (XEXP (x, 0), 0), next_code),
6377 XEXP (XEXP (x, 0), 1)));
6380 /* If the constant is one less than a power of two, this might be
6381 representable by an extraction even if no shift is present.
6382 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6383 we are in a COMPARE. */
6384 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6385 new = make_extraction (mode,
6386 make_compound_operation (XEXP (x, 0),
6388 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6390 /* If we are in a comparison and this is an AND with a power of two,
6391 convert this into the appropriate bit extract. */
6392 else if (in_code == COMPARE
6393 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6394 new = make_extraction (mode,
6395 make_compound_operation (XEXP (x, 0),
6397 i, NULL_RTX, 1, 1, 0, 1);
6402 /* If the sign bit is known to be zero, replace this with an
6403 arithmetic shift. */
6404 if (have_insn_for (ASHIFTRT, mode)
6405 && ! have_insn_for (LSHIFTRT, mode)
6406 && mode_width <= HOST_BITS_PER_WIDE_INT
6407 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6409 new = gen_rtx_ASHIFTRT (mode,
6410 make_compound_operation (XEXP (x, 0),
6416 /* ... fall through ... */
6422 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6423 this is a SIGN_EXTRACT. */
6424 if (GET_CODE (rhs) == CONST_INT
6425 && GET_CODE (lhs) == ASHIFT
6426 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6427 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6429 new = make_compound_operation (XEXP (lhs, 0), next_code);
6430 new = make_extraction (mode, new,
6431 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6432 NULL_RTX, mode_width - INTVAL (rhs),
6433 code == LSHIFTRT, 0, in_code == COMPARE);
6437 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6438 If so, try to merge the shifts into a SIGN_EXTEND. We could
6439 also do this for some cases of SIGN_EXTRACT, but it doesn't
6440 seem worth the effort; the case checked for occurs on Alpha. */
6442 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6443 && ! (GET_CODE (lhs) == SUBREG
6444 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6445 && GET_CODE (rhs) == CONST_INT
6446 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6447 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6448 new = make_extraction (mode, make_compound_operation (new, next_code),
6449 0, NULL_RTX, mode_width - INTVAL (rhs),
6450 code == LSHIFTRT, 0, in_code == COMPARE);
6455 /* Call ourselves recursively on the inner expression. If we are
6456 narrowing the object and it has a different RTL code from
6457 what it originally did, do this SUBREG as a force_to_mode. */
6459 tem = make_compound_operation (SUBREG_REG (x), in_code);
6460 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6461 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6462 && subreg_lowpart_p (x))
6464 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6467 /* If we have something other than a SUBREG, we might have
6468 done an expansion, so rerun ourselves. */
6469 if (GET_CODE (newer) != SUBREG)
6470 newer = make_compound_operation (newer, in_code);
6475 /* If this is a paradoxical subreg, and the new code is a sign or
6476 zero extension, omit the subreg and widen the extension. If it
6477 is a regular subreg, we can still get rid of the subreg by not
6478 widening so much, or in fact removing the extension entirely. */
6479 if ((GET_CODE (tem) == SIGN_EXTEND
6480 || GET_CODE (tem) == ZERO_EXTEND)
6481 && subreg_lowpart_p (x))
6483 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6484 || (GET_MODE_SIZE (mode) >
6485 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6486 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6488 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6499 x = gen_lowpart_for_combine (mode, new);
6500 code = GET_CODE (x);
6503 /* Now recursively process each operand of this operation. */
6504 fmt = GET_RTX_FORMAT (code);
6505 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6508 new = make_compound_operation (XEXP (x, i), next_code);
6509 SUBST (XEXP (x, i), new);
6515 /* Given M see if it is a value that would select a field of bits
6516 within an item, but not the entire word. Return -1 if not.
6517 Otherwise, return the starting position of the field, where 0 is the
6520 *PLEN is set to the length of the field. */
6523 get_pos_from_mask (m, plen)
6524 unsigned HOST_WIDE_INT m;
6525 unsigned HOST_WIDE_INT *plen;
6527 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6528 int pos = exact_log2 (m & -m);
6534 /* Now shift off the low-order zero bits and see if we have a power of
6536 len = exact_log2 ((m >> pos) + 1);
6545 /* See if X can be simplified knowing that we will only refer to it in
6546 MODE and will only refer to those bits that are nonzero in MASK.
6547 If other bits are being computed or if masking operations are done
6548 that select a superset of the bits in MASK, they can sometimes be
6551 Return a possibly simplified expression, but always convert X to
6552 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6554 Also, if REG is non-zero and X is a register equal in value to REG,
6557 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6558 are all off in X. This is used when X will be complemented, by either
6559 NOT, NEG, or XOR. */
6562 force_to_mode (x, mode, mask, reg, just_select)
6564 enum machine_mode mode;
6565 unsigned HOST_WIDE_INT mask;
6569 enum rtx_code code = GET_CODE (x);
6570 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6571 enum machine_mode op_mode;
6572 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6575 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6576 code below will do the wrong thing since the mode of such an
6577 expression is VOIDmode.
6579 Also do nothing if X is a CLOBBER; this can happen if X was
6580 the return value from a call to gen_lowpart_for_combine. */
6581 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6584 /* We want to perform the operation is its present mode unless we know
6585 that the operation is valid in MODE, in which case we do the operation
6587 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6588 && have_insn_for (code, mode))
6589 ? mode : GET_MODE (x));
6591 /* It is not valid to do a right-shift in a narrower mode
6592 than the one it came in with. */
6593 if ((code == LSHIFTRT || code == ASHIFTRT)
6594 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6595 op_mode = GET_MODE (x);
6597 /* Truncate MASK to fit OP_MODE. */
6599 mask &= GET_MODE_MASK (op_mode);
6601 /* When we have an arithmetic operation, or a shift whose count we
6602 do not know, we need to assume that all bit the up to the highest-order
6603 bit in MASK will be needed. This is how we form such a mask. */
6605 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6606 ? GET_MODE_MASK (op_mode)
6607 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6610 fuller_mask = ~(HOST_WIDE_INT) 0;
6612 /* Determine what bits of X are guaranteed to be (non)zero. */
6613 nonzero = nonzero_bits (x, mode);
6615 /* If none of the bits in X are needed, return a zero. */
6616 if (! just_select && (nonzero & mask) == 0)
6619 /* If X is a CONST_INT, return a new one. Do this here since the
6620 test below will fail. */
6621 if (GET_CODE (x) == CONST_INT)
6623 HOST_WIDE_INT cval = INTVAL (x) & mask;
6624 int width = GET_MODE_BITSIZE (mode);
6626 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6627 number, sign extend it. */
6628 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6629 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6630 cval |= (HOST_WIDE_INT) -1 << width;
6632 return GEN_INT (cval);
6635 /* If X is narrower than MODE and we want all the bits in X's mode, just
6636 get X in the proper mode. */
6637 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6638 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6639 return gen_lowpart_for_combine (mode, x);
6641 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6642 MASK are already known to be zero in X, we need not do anything. */
6643 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6649 /* If X is a (clobber (const_int)), return it since we know we are
6650 generating something that won't match. */
6654 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6655 spanned the boundary of the MEM. If we are now masking so it is
6656 within that boundary, we don't need the USE any more. */
6657 if (! BITS_BIG_ENDIAN
6658 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6659 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6666 x = expand_compound_operation (x);
6667 if (GET_CODE (x) != code)
6668 return force_to_mode (x, mode, mask, reg, next_select);
6672 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6673 || rtx_equal_p (reg, get_last_value (x))))
6678 if (subreg_lowpart_p (x)
6679 /* We can ignore the effect of this SUBREG if it narrows the mode or
6680 if the constant masks to zero all the bits the mode doesn't
6682 && ((GET_MODE_SIZE (GET_MODE (x))
6683 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6685 & GET_MODE_MASK (GET_MODE (x))
6686 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6687 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6691 /* If this is an AND with a constant, convert it into an AND
6692 whose constant is the AND of that constant with MASK. If it
6693 remains an AND of MASK, delete it since it is redundant. */
6695 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6697 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6698 mask & INTVAL (XEXP (x, 1)));
6700 /* If X is still an AND, see if it is an AND with a mask that
6701 is just some low-order bits. If so, and it is MASK, we don't
6704 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6705 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6708 /* If it remains an AND, try making another AND with the bits
6709 in the mode mask that aren't in MASK turned on. If the
6710 constant in the AND is wide enough, this might make a
6711 cheaper constant. */
6713 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6714 && GET_MODE_MASK (GET_MODE (x)) != mask
6715 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6717 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6718 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6719 int width = GET_MODE_BITSIZE (GET_MODE (x));
6722 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6723 number, sign extend it. */
6724 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6725 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6726 cval |= (HOST_WIDE_INT) -1 << width;
6728 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6729 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6739 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6740 low-order bits (as in an alignment operation) and FOO is already
6741 aligned to that boundary, mask C1 to that boundary as well.
6742 This may eliminate that PLUS and, later, the AND. */
6745 unsigned int width = GET_MODE_BITSIZE (mode);
6746 unsigned HOST_WIDE_INT smask = mask;
6748 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6749 number, sign extend it. */
6751 if (width < HOST_BITS_PER_WIDE_INT
6752 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6753 smask |= (HOST_WIDE_INT) -1 << width;
6755 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6756 && exact_log2 (- smask) >= 0)
6760 && (XEXP (x, 0) == stack_pointer_rtx
6761 || XEXP (x, 0) == frame_pointer_rtx))
6763 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6764 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6766 sp_mask &= ~(sp_alignment - 1);
6767 if ((sp_mask & ~smask) == 0
6768 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
6769 return force_to_mode (plus_constant (XEXP (x, 0),
6770 ((INTVAL (XEXP (x, 1)) -
6771 STACK_BIAS) & smask)
6773 mode, smask, reg, next_select);
6776 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6777 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6778 return force_to_mode (plus_constant (XEXP (x, 0),
6779 (INTVAL (XEXP (x, 1))
6781 mode, smask, reg, next_select);
6785 /* ... fall through ... */
6788 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6789 most significant bit in MASK since carries from those bits will
6790 affect the bits we are interested in. */
6795 /* If X is (minus C Y) where C's least set bit is larger than any bit
6796 in the mask, then we may replace with (neg Y). */
6797 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6798 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6799 & -INTVAL (XEXP (x, 0))))
6802 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6804 return force_to_mode (x, mode, mask, reg, next_select);
6807 /* Similarly, if C contains every bit in the mask, then we may
6808 replace with (not Y). */
6809 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6810 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6811 == INTVAL (XEXP (x, 0))))
6813 x = simplify_gen_unary (NOT, GET_MODE (x),
6814 XEXP (x, 1), GET_MODE (x));
6815 return force_to_mode (x, mode, mask, reg, next_select);
6823 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6824 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6825 operation which may be a bitfield extraction. Ensure that the
6826 constant we form is not wider than the mode of X. */
6828 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6829 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6830 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6831 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6832 && GET_CODE (XEXP (x, 1)) == CONST_INT
6833 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6834 + floor_log2 (INTVAL (XEXP (x, 1))))
6835 < GET_MODE_BITSIZE (GET_MODE (x)))
6836 && (INTVAL (XEXP (x, 1))
6837 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6839 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6840 << INTVAL (XEXP (XEXP (x, 0), 1)));
6841 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6842 XEXP (XEXP (x, 0), 0), temp);
6843 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6844 XEXP (XEXP (x, 0), 1));
6845 return force_to_mode (x, mode, mask, reg, next_select);
6849 /* For most binary operations, just propagate into the operation and
6850 change the mode if we have an operation of that mode. */
6852 op0 = gen_lowpart_for_combine (op_mode,
6853 force_to_mode (XEXP (x, 0), mode, mask,
6855 op1 = gen_lowpart_for_combine (op_mode,
6856 force_to_mode (XEXP (x, 1), mode, mask,
6859 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6860 MASK since OP1 might have been sign-extended but we never want
6861 to turn on extra bits, since combine might have previously relied
6862 on them being off. */
6863 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6864 && (INTVAL (op1) & mask) != 0)
6865 op1 = GEN_INT (INTVAL (op1) & mask);
6867 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6868 x = gen_binary (code, op_mode, op0, op1);
6872 /* For left shifts, do the same, but just for the first operand.
6873 However, we cannot do anything with shifts where we cannot
6874 guarantee that the counts are smaller than the size of the mode
6875 because such a count will have a different meaning in a
6878 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6879 && INTVAL (XEXP (x, 1)) >= 0
6880 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6881 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6882 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6883 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6886 /* If the shift count is a constant and we can do arithmetic in
6887 the mode of the shift, refine which bits we need. Otherwise, use the
6888 conservative form of the mask. */
6889 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6890 && INTVAL (XEXP (x, 1)) >= 0
6891 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6892 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6893 mask >>= INTVAL (XEXP (x, 1));
6897 op0 = gen_lowpart_for_combine (op_mode,
6898 force_to_mode (XEXP (x, 0), op_mode,
6899 mask, reg, next_select));
6901 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6902 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6906 /* Here we can only do something if the shift count is a constant,
6907 this shift constant is valid for the host, and we can do arithmetic
6910 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6911 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6912 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6914 rtx inner = XEXP (x, 0);
6915 unsigned HOST_WIDE_INT inner_mask;
6917 /* Select the mask of the bits we need for the shift operand. */
6918 inner_mask = mask << INTVAL (XEXP (x, 1));
6920 /* We can only change the mode of the shift if we can do arithmetic
6921 in the mode of the shift and INNER_MASK is no wider than the
6922 width of OP_MODE. */
6923 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6924 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
6925 op_mode = GET_MODE (x);
6927 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
6929 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6930 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6933 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6934 shift and AND produces only copies of the sign bit (C2 is one less
6935 than a power of two), we can do this with just a shift. */
6937 if (GET_CODE (x) == LSHIFTRT
6938 && GET_CODE (XEXP (x, 1)) == CONST_INT
6939 /* The shift puts one of the sign bit copies in the least significant
6941 && ((INTVAL (XEXP (x, 1))
6942 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6943 >= GET_MODE_BITSIZE (GET_MODE (x)))
6944 && exact_log2 (mask + 1) >= 0
6945 /* Number of bits left after the shift must be more than the mask
6947 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6948 <= GET_MODE_BITSIZE (GET_MODE (x)))
6949 /* Must be more sign bit copies than the mask needs. */
6950 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6951 >= exact_log2 (mask + 1)))
6952 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6953 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6954 - exact_log2 (mask + 1)));
6959 /* If we are just looking for the sign bit, we don't need this shift at
6960 all, even if it has a variable count. */
6961 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6962 && (mask == ((unsigned HOST_WIDE_INT) 1
6963 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6964 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6966 /* If this is a shift by a constant, get a mask that contains those bits
6967 that are not copies of the sign bit. We then have two cases: If
6968 MASK only includes those bits, this can be a logical shift, which may
6969 allow simplifications. If MASK is a single-bit field not within
6970 those bits, we are requesting a copy of the sign bit and hence can
6971 shift the sign bit to the appropriate location. */
6973 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6974 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6978 /* If the considered data is wider then HOST_WIDE_INT, we can't
6979 represent a mask for all its bits in a single scalar.
6980 But we only care about the lower bits, so calculate these. */
6982 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6984 nonzero = ~(HOST_WIDE_INT) 0;
6986 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6987 is the number of bits a full-width mask would have set.
6988 We need only shift if these are fewer than nonzero can
6989 hold. If not, we must keep all bits set in nonzero. */
6991 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6992 < HOST_BITS_PER_WIDE_INT)
6993 nonzero >>= INTVAL (XEXP (x, 1))
6994 + HOST_BITS_PER_WIDE_INT
6995 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6999 nonzero = GET_MODE_MASK (GET_MODE (x));
7000 nonzero >>= INTVAL (XEXP (x, 1));
7003 if ((mask & ~nonzero) == 0
7004 || (i = exact_log2 (mask)) >= 0)
7006 x = simplify_shift_const
7007 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7008 i < 0 ? INTVAL (XEXP (x, 1))
7009 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7011 if (GET_CODE (x) != ASHIFTRT)
7012 return force_to_mode (x, mode, mask, reg, next_select);
7016 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7017 even if the shift count isn't a constant. */
7019 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7023 /* If this is a zero- or sign-extension operation that just affects bits
7024 we don't care about, remove it. Be sure the call above returned
7025 something that is still a shift. */
7027 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7028 && GET_CODE (XEXP (x, 1)) == CONST_INT
7029 && INTVAL (XEXP (x, 1)) >= 0
7030 && (INTVAL (XEXP (x, 1))
7031 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7032 && GET_CODE (XEXP (x, 0)) == ASHIFT
7033 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7034 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7035 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7042 /* If the shift count is constant and we can do computations
7043 in the mode of X, compute where the bits we care about are.
7044 Otherwise, we can't do anything. Don't change the mode of
7045 the shift or propagate MODE into the shift, though. */
7046 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7047 && INTVAL (XEXP (x, 1)) >= 0)
7049 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7050 GET_MODE (x), GEN_INT (mask),
7052 if (temp && GET_CODE(temp) == CONST_INT)
7054 force_to_mode (XEXP (x, 0), GET_MODE (x),
7055 INTVAL (temp), reg, next_select));
7060 /* If we just want the low-order bit, the NEG isn't needed since it
7061 won't change the low-order bit. */
7063 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7065 /* We need any bits less significant than the most significant bit in
7066 MASK since carries from those bits will affect the bits we are
7072 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7073 same as the XOR case above. Ensure that the constant we form is not
7074 wider than the mode of X. */
7076 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7077 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7078 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7079 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7080 < GET_MODE_BITSIZE (GET_MODE (x)))
7081 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7083 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7084 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7085 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7087 return force_to_mode (x, mode, mask, reg, next_select);
7090 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7091 use the full mask inside the NOT. */
7095 op0 = gen_lowpart_for_combine (op_mode,
7096 force_to_mode (XEXP (x, 0), mode, mask,
7098 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7099 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7103 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7104 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7105 which is equal to STORE_FLAG_VALUE. */
7106 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7107 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7108 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7109 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7114 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7115 written in a narrower mode. We play it safe and do not do so. */
7118 gen_lowpart_for_combine (GET_MODE (x),
7119 force_to_mode (XEXP (x, 1), mode,
7120 mask, reg, next_select)));
7122 gen_lowpart_for_combine (GET_MODE (x),
7123 force_to_mode (XEXP (x, 2), mode,
7124 mask, reg,next_select)));
7131 /* Ensure we return a value of the proper mode. */
7132 return gen_lowpart_for_combine (mode, x);
7135 /* Return nonzero if X is an expression that has one of two values depending on
7136 whether some other value is zero or nonzero. In that case, we return the
7137 value that is being tested, *PTRUE is set to the value if the rtx being
7138 returned has a nonzero value, and *PFALSE is set to the other alternative.
7140 If we return zero, we set *PTRUE and *PFALSE to X. */
7143 if_then_else_cond (x, ptrue, pfalse)
7145 rtx *ptrue, *pfalse;
7147 enum machine_mode mode = GET_MODE (x);
7148 enum rtx_code code = GET_CODE (x);
7149 rtx cond0, cond1, true0, true1, false0, false1;
7150 unsigned HOST_WIDE_INT nz;
7152 /* If we are comparing a value against zero, we are done. */
7153 if ((code == NE || code == EQ)
7154 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7156 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7157 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7161 /* If this is a unary operation whose operand has one of two values, apply
7162 our opcode to compute those values. */
7163 else if (GET_RTX_CLASS (code) == '1'
7164 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7166 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7167 *pfalse = simplify_gen_unary (code, mode, false0,
7168 GET_MODE (XEXP (x, 0)));
7172 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7173 make can't possibly match and would suppress other optimizations. */
7174 else if (code == COMPARE)
7177 /* If this is a binary operation, see if either side has only one of two
7178 values. If either one does or if both do and they are conditional on
7179 the same value, compute the new true and false values. */
7180 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7181 || GET_RTX_CLASS (code) == '<')
7183 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7184 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7186 if ((cond0 != 0 || cond1 != 0)
7187 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7189 /* If if_then_else_cond returned zero, then true/false are the
7190 same rtl. We must copy one of them to prevent invalid rtl
7193 true0 = copy_rtx (true0);
7194 else if (cond1 == 0)
7195 true1 = copy_rtx (true1);
7197 *ptrue = gen_binary (code, mode, true0, true1);
7198 *pfalse = gen_binary (code, mode, false0, false1);
7199 return cond0 ? cond0 : cond1;
7202 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7203 operands is zero when the other is non-zero, and vice-versa,
7204 and STORE_FLAG_VALUE is 1 or -1. */
7206 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7207 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7209 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7211 rtx op0 = XEXP (XEXP (x, 0), 1);
7212 rtx op1 = XEXP (XEXP (x, 1), 1);
7214 cond0 = XEXP (XEXP (x, 0), 0);
7215 cond1 = XEXP (XEXP (x, 1), 0);
7217 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7218 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7219 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7220 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7221 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7222 || ((swap_condition (GET_CODE (cond0))
7223 == combine_reversed_comparison_code (cond1))
7224 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7225 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7226 && ! side_effects_p (x))
7228 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7229 *pfalse = gen_binary (MULT, mode,
7231 ? simplify_gen_unary (NEG, mode, op1,
7239 /* Similarly for MULT, AND and UMIN, except that for these the result
7241 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7242 && (code == MULT || code == AND || code == UMIN)
7243 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7245 cond0 = XEXP (XEXP (x, 0), 0);
7246 cond1 = XEXP (XEXP (x, 1), 0);
7248 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7249 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7250 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7251 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7252 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7253 || ((swap_condition (GET_CODE (cond0))
7254 == combine_reversed_comparison_code (cond1))
7255 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7256 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7257 && ! side_effects_p (x))
7259 *ptrue = *pfalse = const0_rtx;
7265 else if (code == IF_THEN_ELSE)
7267 /* If we have IF_THEN_ELSE already, extract the condition and
7268 canonicalize it if it is NE or EQ. */
7269 cond0 = XEXP (x, 0);
7270 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7271 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7272 return XEXP (cond0, 0);
7273 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7275 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7276 return XEXP (cond0, 0);
7282 /* If X is a SUBREG, we can narrow both the true and false values
7283 if the inner expression, if there is a condition. */
7284 else if (code == SUBREG
7285 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7288 *ptrue = simplify_gen_subreg (mode, true0,
7289 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7290 *pfalse = simplify_gen_subreg (mode, false0,
7291 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7296 /* If X is a constant, this isn't special and will cause confusions
7297 if we treat it as such. Likewise if it is equivalent to a constant. */
7298 else if (CONSTANT_P (x)
7299 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7302 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7303 will be least confusing to the rest of the compiler. */
7304 else if (mode == BImode)
7306 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7310 /* If X is known to be either 0 or -1, those are the true and
7311 false values when testing X. */
7312 else if (x == constm1_rtx || x == const0_rtx
7313 || (mode != VOIDmode
7314 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7316 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7320 /* Likewise for 0 or a single bit. */
7321 else if (mode != VOIDmode
7322 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7323 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7325 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7329 /* Otherwise fail; show no condition with true and false values the same. */
7330 *ptrue = *pfalse = x;
7334 /* Return the value of expression X given the fact that condition COND
7335 is known to be true when applied to REG as its first operand and VAL
7336 as its second. X is known to not be shared and so can be modified in
7339 We only handle the simplest cases, and specifically those cases that
7340 arise with IF_THEN_ELSE expressions. */
7343 known_cond (x, cond, reg, val)
7348 enum rtx_code code = GET_CODE (x);
7353 if (side_effects_p (x))
7356 /* If either operand of the condition is a floating point value,
7357 then we have to avoid collapsing an EQ comparison. */
7359 && rtx_equal_p (x, reg)
7360 && ! FLOAT_MODE_P (GET_MODE (x))
7361 && ! FLOAT_MODE_P (GET_MODE (val)))
7364 if (cond == UNEQ && rtx_equal_p (x, reg))
7367 /* If X is (abs REG) and we know something about REG's relationship
7368 with zero, we may be able to simplify this. */
7370 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7373 case GE: case GT: case EQ:
7376 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7378 GET_MODE (XEXP (x, 0)));
7383 /* The only other cases we handle are MIN, MAX, and comparisons if the
7384 operands are the same as REG and VAL. */
7386 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7388 if (rtx_equal_p (XEXP (x, 0), val))
7389 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7391 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7393 if (GET_RTX_CLASS (code) == '<')
7395 if (comparison_dominates_p (cond, code))
7396 return const_true_rtx;
7398 code = combine_reversed_comparison_code (x);
7400 && comparison_dominates_p (cond, code))
7405 else if (code == SMAX || code == SMIN
7406 || code == UMIN || code == UMAX)
7408 int unsignedp = (code == UMIN || code == UMAX);
7410 /* Do not reverse the condition when it is NE or EQ.
7411 This is because we cannot conclude anything about
7412 the value of 'SMAX (x, y)' when x is not equal to y,
7413 but we can when x equals y. */
7414 if ((code == SMAX || code == UMAX)
7415 && ! (cond == EQ || cond == NE))
7416 cond = reverse_condition (cond);
7421 return unsignedp ? x : XEXP (x, 1);
7423 return unsignedp ? x : XEXP (x, 0);
7425 return unsignedp ? XEXP (x, 1) : x;
7427 return unsignedp ? XEXP (x, 0) : x;
7435 fmt = GET_RTX_FORMAT (code);
7436 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7439 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7440 else if (fmt[i] == 'E')
7441 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7442 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7449 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7450 assignment as a field assignment. */
7453 rtx_equal_for_field_assignment_p (x, y)
7457 if (x == y || rtx_equal_p (x, y))
7460 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7463 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7464 Note that all SUBREGs of MEM are paradoxical; otherwise they
7465 would have been rewritten. */
7466 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7467 && GET_CODE (SUBREG_REG (y)) == MEM
7468 && rtx_equal_p (SUBREG_REG (y),
7469 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7472 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7473 && GET_CODE (SUBREG_REG (x)) == MEM
7474 && rtx_equal_p (SUBREG_REG (x),
7475 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7478 /* We used to see if get_last_value of X and Y were the same but that's
7479 not correct. In one direction, we'll cause the assignment to have
7480 the wrong destination and in the case, we'll import a register into this
7481 insn that might have already have been dead. So fail if none of the
7482 above cases are true. */
7486 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7487 Return that assignment if so.
7489 We only handle the most common cases. */
7492 make_field_assignment (x)
7495 rtx dest = SET_DEST (x);
7496 rtx src = SET_SRC (x);
7501 unsigned HOST_WIDE_INT len;
7503 enum machine_mode mode;
7505 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7506 a clear of a one-bit field. We will have changed it to
7507 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7510 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7511 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7512 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7513 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7515 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7518 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7522 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7523 && subreg_lowpart_p (XEXP (src, 0))
7524 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7525 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7526 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7527 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7528 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7530 assign = make_extraction (VOIDmode, dest, 0,
7531 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7534 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7538 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7540 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7541 && XEXP (XEXP (src, 0), 0) == const1_rtx
7542 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7544 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7547 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7551 /* The other case we handle is assignments into a constant-position
7552 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7553 a mask that has all one bits except for a group of zero bits and
7554 OTHER is known to have zeros where C1 has ones, this is such an
7555 assignment. Compute the position and length from C1. Shift OTHER
7556 to the appropriate position, force it to the required mode, and
7557 make the extraction. Check for the AND in both operands. */
7559 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7562 rhs = expand_compound_operation (XEXP (src, 0));
7563 lhs = expand_compound_operation (XEXP (src, 1));
7565 if (GET_CODE (rhs) == AND
7566 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7567 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7568 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7569 else if (GET_CODE (lhs) == AND
7570 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7571 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7572 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7576 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7577 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7578 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7579 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7582 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7586 /* The mode to use for the source is the mode of the assignment, or of
7587 what is inside a possible STRICT_LOW_PART. */
7588 mode = (GET_CODE (assign) == STRICT_LOW_PART
7589 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7591 /* Shift OTHER right POS places and make it the source, restricting it
7592 to the proper length and mode. */
7594 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7595 GET_MODE (src), other, pos),
7597 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7598 ? ~(unsigned HOST_WIDE_INT) 0
7599 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7602 return gen_rtx_SET (VOIDmode, assign, src);
7605 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7609 apply_distributive_law (x)
7612 enum rtx_code code = GET_CODE (x);
7613 rtx lhs, rhs, other;
7615 enum rtx_code inner_code;
7617 /* Distributivity is not true for floating point.
7618 It can change the value. So don't do it.
7619 -- rms and moshier@world.std.com. */
7620 if (FLOAT_MODE_P (GET_MODE (x)))
7623 /* The outer operation can only be one of the following: */
7624 if (code != IOR && code != AND && code != XOR
7625 && code != PLUS && code != MINUS)
7628 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7630 /* If either operand is a primitive we can't do anything, so get out
7632 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7633 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7636 lhs = expand_compound_operation (lhs);
7637 rhs = expand_compound_operation (rhs);
7638 inner_code = GET_CODE (lhs);
7639 if (inner_code != GET_CODE (rhs))
7642 /* See if the inner and outer operations distribute. */
7649 /* These all distribute except over PLUS. */
7650 if (code == PLUS || code == MINUS)
7655 if (code != PLUS && code != MINUS)
7660 /* This is also a multiply, so it distributes over everything. */
7664 /* Non-paradoxical SUBREGs distributes over all operations, provided
7665 the inner modes and byte offsets are the same, this is an extraction
7666 of a low-order part, we don't convert an fp operation to int or
7667 vice versa, and we would not be converting a single-word
7668 operation into a multi-word operation. The latter test is not
7669 required, but it prevents generating unneeded multi-word operations.
7670 Some of the previous tests are redundant given the latter test, but
7671 are retained because they are required for correctness.
7673 We produce the result slightly differently in this case. */
7675 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7676 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7677 || ! subreg_lowpart_p (lhs)
7678 || (GET_MODE_CLASS (GET_MODE (lhs))
7679 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7680 || (GET_MODE_SIZE (GET_MODE (lhs))
7681 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7682 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7685 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7686 SUBREG_REG (lhs), SUBREG_REG (rhs));
7687 return gen_lowpart_for_combine (GET_MODE (x), tem);
7693 /* Set LHS and RHS to the inner operands (A and B in the example
7694 above) and set OTHER to the common operand (C in the example).
7695 These is only one way to do this unless the inner operation is
7697 if (GET_RTX_CLASS (inner_code) == 'c'
7698 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7699 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7700 else if (GET_RTX_CLASS (inner_code) == 'c'
7701 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7702 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7703 else if (GET_RTX_CLASS (inner_code) == 'c'
7704 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7705 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7706 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7707 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7711 /* Form the new inner operation, seeing if it simplifies first. */
7712 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7714 /* There is one exception to the general way of distributing:
7715 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7716 if (code == XOR && inner_code == IOR)
7719 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7722 /* We may be able to continuing distributing the result, so call
7723 ourselves recursively on the inner operation before forming the
7724 outer operation, which we return. */
7725 return gen_binary (inner_code, GET_MODE (x),
7726 apply_distributive_law (tem), other);
7729 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7732 Return an equivalent form, if different from X. Otherwise, return X. If
7733 X is zero, we are to always construct the equivalent form. */
7736 simplify_and_const_int (x, mode, varop, constop)
7738 enum machine_mode mode;
7740 unsigned HOST_WIDE_INT constop;
7742 unsigned HOST_WIDE_INT nonzero;
7745 /* Simplify VAROP knowing that we will be only looking at some of the
7747 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7749 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7750 CONST_INT, we are done. */
7751 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7754 /* See what bits may be nonzero in VAROP. Unlike the general case of
7755 a call to nonzero_bits, here we don't care about bits outside
7758 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7759 nonzero = trunc_int_for_mode (nonzero, mode);
7761 /* Turn off all bits in the constant that are known to already be zero.
7762 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7763 which is tested below. */
7767 /* If we don't have any bits left, return zero. */
7771 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7772 a power of two, we can replace this with a ASHIFT. */
7773 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7774 && (i = exact_log2 (constop)) >= 0)
7775 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7777 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7778 or XOR, then try to apply the distributive law. This may eliminate
7779 operations if either branch can be simplified because of the AND.
7780 It may also make some cases more complex, but those cases probably
7781 won't match a pattern either with or without this. */
7783 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7785 gen_lowpart_for_combine
7787 apply_distributive_law
7788 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7789 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7790 XEXP (varop, 0), constop),
7791 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7792 XEXP (varop, 1), constop))));
7794 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7795 the AND and see if one of the operands simplifies to zero. If so, we
7796 may eliminate it. */
7798 if (GET_CODE (varop) == PLUS
7799 && exact_log2 (constop + 1) >= 0)
7803 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7804 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7805 if (o0 == const0_rtx)
7807 if (o1 == const0_rtx)
7811 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7812 if we already had one (just check for the simplest cases). */
7813 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7814 && GET_MODE (XEXP (x, 0)) == mode
7815 && SUBREG_REG (XEXP (x, 0)) == varop)
7816 varop = XEXP (x, 0);
7818 varop = gen_lowpart_for_combine (mode, varop);
7820 /* If we can't make the SUBREG, try to return what we were given. */
7821 if (GET_CODE (varop) == CLOBBER)
7822 return x ? x : varop;
7824 /* If we are only masking insignificant bits, return VAROP. */
7825 if (constop == nonzero)
7828 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7829 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7830 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7834 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7835 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7836 SUBST (XEXP (x, 1), GEN_INT (constop));
7838 SUBST (XEXP (x, 0), varop);
7844 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7845 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7846 is less useful. We can't allow both, because that results in exponential
7847 run time recursion. There is a nullstone testcase that triggered
7848 this. This macro avoids accidental uses of num_sign_bit_copies. */
7849 #define num_sign_bit_copies()
7851 /* Given an expression, X, compute which bits in X can be non-zero.
7852 We don't care about bits outside of those defined in MODE.
7854 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7855 a shift, AND, or zero_extract, we can do better. */
7857 static unsigned HOST_WIDE_INT
7858 nonzero_bits (x, mode)
7860 enum machine_mode mode;
7862 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7863 unsigned HOST_WIDE_INT inner_nz;
7865 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7868 /* For floating-point values, assume all bits are needed. */
7869 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7872 /* If X is wider than MODE, use its mode instead. */
7873 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7875 mode = GET_MODE (x);
7876 nonzero = GET_MODE_MASK (mode);
7877 mode_width = GET_MODE_BITSIZE (mode);
7880 if (mode_width > HOST_BITS_PER_WIDE_INT)
7881 /* Our only callers in this case look for single bit values. So
7882 just return the mode mask. Those tests will then be false. */
7885 #ifndef WORD_REGISTER_OPERATIONS
7886 /* If MODE is wider than X, but both are a single word for both the host
7887 and target machines, we can compute this from which bits of the
7888 object might be nonzero in its own mode, taking into account the fact
7889 that on many CISC machines, accessing an object in a wider mode
7890 causes the high-order bits to become undefined. So they are
7891 not known to be zero. */
7893 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7894 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7895 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7896 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7898 nonzero &= nonzero_bits (x, GET_MODE (x));
7899 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
7904 code = GET_CODE (x);
7908 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
7909 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7910 all the bits above ptr_mode are known to be zero. */
7911 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7913 nonzero &= GET_MODE_MASK (ptr_mode);
7916 #ifdef STACK_BOUNDARY
7917 /* If this is the stack pointer, we may know something about its
7918 alignment. If PUSH_ROUNDING is defined, it is possible for the
7919 stack to be momentarily aligned only to that amount, so we pick
7920 the least alignment. */
7922 /* We can't check for arg_pointer_rtx here, because it is not
7923 guaranteed to have as much alignment as the stack pointer.
7924 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7925 alignment but the argument pointer has only 64 bit alignment. */
7927 if ((x == frame_pointer_rtx
7928 || x == stack_pointer_rtx
7929 || x == hard_frame_pointer_rtx
7930 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7931 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7937 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7939 #ifdef PUSH_ROUNDING
7940 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
7941 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7944 /* We must return here, otherwise we may get a worse result from
7945 one of the choices below. There is nothing useful below as
7946 far as the stack pointer is concerned. */
7947 return nonzero &= ~(sp_alignment - 1);
7951 /* If X is a register whose nonzero bits value is current, use it.
7952 Otherwise, if X is a register whose value we can find, use that
7953 value. Otherwise, use the previously-computed global nonzero bits
7954 for this register. */
7956 if (reg_last_set_value[REGNO (x)] != 0
7957 && reg_last_set_mode[REGNO (x)] == mode
7958 && (reg_last_set_label[REGNO (x)] == label_tick
7959 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7960 && REG_N_SETS (REGNO (x)) == 1
7961 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
7963 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7964 return reg_last_set_nonzero_bits[REGNO (x)];
7966 tem = get_last_value (x);
7970 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7971 /* If X is narrower than MODE and TEM is a non-negative
7972 constant that would appear negative in the mode of X,
7973 sign-extend it for use in reg_nonzero_bits because some
7974 machines (maybe most) will actually do the sign-extension
7975 and this is the conservative approach.
7977 ??? For 2.5, try to tighten up the MD files in this regard
7978 instead of this kludge. */
7980 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7981 && GET_CODE (tem) == CONST_INT
7983 && 0 != (INTVAL (tem)
7984 & ((HOST_WIDE_INT) 1
7985 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7986 tem = GEN_INT (INTVAL (tem)
7987 | ((HOST_WIDE_INT) (-1)
7988 << GET_MODE_BITSIZE (GET_MODE (x))));
7990 return nonzero_bits (tem, mode);
7992 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7993 return reg_nonzero_bits[REGNO (x)] & nonzero;
7998 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7999 /* If X is negative in MODE, sign-extend the value. */
8000 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8001 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8002 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8008 #ifdef LOAD_EXTEND_OP
8009 /* In many, if not most, RISC machines, reading a byte from memory
8010 zeros the rest of the register. Noticing that fact saves a lot
8011 of extra zero-extends. */
8012 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8013 nonzero &= GET_MODE_MASK (GET_MODE (x));
8018 case UNEQ: case LTGT:
8019 case GT: case GTU: case UNGT:
8020 case LT: case LTU: case UNLT:
8021 case GE: case GEU: case UNGE:
8022 case LE: case LEU: case UNLE:
8023 case UNORDERED: case ORDERED:
8025 /* If this produces an integer result, we know which bits are set.
8026 Code here used to clear bits outside the mode of X, but that is
8029 if (GET_MODE_CLASS (mode) == MODE_INT
8030 && mode_width <= HOST_BITS_PER_WIDE_INT)
8031 nonzero = STORE_FLAG_VALUE;
8036 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8037 and num_sign_bit_copies. */
8038 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8039 == GET_MODE_BITSIZE (GET_MODE (x)))
8043 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8044 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8049 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8050 and num_sign_bit_copies. */
8051 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8052 == GET_MODE_BITSIZE (GET_MODE (x)))
8058 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8062 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8063 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8064 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8068 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8069 Otherwise, show all the bits in the outer mode but not the inner
8071 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8072 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8074 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8076 & (((HOST_WIDE_INT) 1
8077 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8078 inner_nz |= (GET_MODE_MASK (mode)
8079 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8082 nonzero &= inner_nz;
8086 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8087 & nonzero_bits (XEXP (x, 1), mode));
8091 case UMIN: case UMAX: case SMIN: case SMAX:
8092 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8093 | nonzero_bits (XEXP (x, 1), mode));
8096 case PLUS: case MINUS:
8098 case DIV: case UDIV:
8099 case MOD: case UMOD:
8100 /* We can apply the rules of arithmetic to compute the number of
8101 high- and low-order zero bits of these operations. We start by
8102 computing the width (position of the highest-order non-zero bit)
8103 and the number of low-order zero bits for each value. */
8105 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8106 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8107 int width0 = floor_log2 (nz0) + 1;
8108 int width1 = floor_log2 (nz1) + 1;
8109 int low0 = floor_log2 (nz0 & -nz0);
8110 int low1 = floor_log2 (nz1 & -nz1);
8111 HOST_WIDE_INT op0_maybe_minusp
8112 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8113 HOST_WIDE_INT op1_maybe_minusp
8114 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8115 unsigned int result_width = mode_width;
8123 && (XEXP (x, 0) == stack_pointer_rtx
8124 || XEXP (x, 0) == frame_pointer_rtx)
8125 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8127 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8129 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
8130 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8131 width0 = floor_log2 (nz0) + 1;
8132 width1 = floor_log2 (nz1) + 1;
8133 low0 = floor_log2 (nz0 & -nz0);
8134 low1 = floor_log2 (nz1 & -nz1);
8137 result_width = MAX (width0, width1) + 1;
8138 result_low = MIN (low0, low1);
8141 result_low = MIN (low0, low1);
8144 result_width = width0 + width1;
8145 result_low = low0 + low1;
8150 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8151 result_width = width0;
8156 result_width = width0;
8161 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8162 result_width = MIN (width0, width1);
8163 result_low = MIN (low0, low1);
8168 result_width = MIN (width0, width1);
8169 result_low = MIN (low0, low1);
8175 if (result_width < mode_width)
8176 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8179 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8181 #ifdef POINTERS_EXTEND_UNSIGNED
8182 /* If pointers extend unsigned and this is an addition or subtraction
8183 to a pointer in Pmode, all the bits above ptr_mode are known to be
8185 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8186 && (code == PLUS || code == MINUS)
8187 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8188 nonzero &= GET_MODE_MASK (ptr_mode);
8194 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8195 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8196 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8200 /* If this is a SUBREG formed for a promoted variable that has
8201 been zero-extended, we know that at least the high-order bits
8202 are zero, though others might be too. */
8204 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8205 nonzero = (GET_MODE_MASK (GET_MODE (x))
8206 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8208 /* If the inner mode is a single word for both the host and target
8209 machines, we can compute this from which bits of the inner
8210 object might be nonzero. */
8211 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8212 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8213 <= HOST_BITS_PER_WIDE_INT))
8215 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8217 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8218 /* If this is a typical RISC machine, we only have to worry
8219 about the way loads are extended. */
8220 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8222 & (((unsigned HOST_WIDE_INT) 1
8223 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8225 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8228 /* On many CISC machines, accessing an object in a wider mode
8229 causes the high-order bits to become undefined. So they are
8230 not known to be zero. */
8231 if (GET_MODE_SIZE (GET_MODE (x))
8232 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8233 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8234 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8243 /* The nonzero bits are in two classes: any bits within MODE
8244 that aren't in GET_MODE (x) are always significant. The rest of the
8245 nonzero bits are those that are significant in the operand of
8246 the shift when shifted the appropriate number of bits. This
8247 shows that high-order bits are cleared by the right shift and
8248 low-order bits by left shifts. */
8249 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8250 && INTVAL (XEXP (x, 1)) >= 0
8251 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8253 enum machine_mode inner_mode = GET_MODE (x);
8254 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8255 int count = INTVAL (XEXP (x, 1));
8256 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8257 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8258 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8259 unsigned HOST_WIDE_INT outer = 0;
8261 if (mode_width > width)
8262 outer = (op_nonzero & nonzero & ~mode_mask);
8264 if (code == LSHIFTRT)
8266 else if (code == ASHIFTRT)
8270 /* If the sign bit may have been nonzero before the shift, we
8271 need to mark all the places it could have been copied to
8272 by the shift as possibly nonzero. */
8273 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8274 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8276 else if (code == ASHIFT)
8279 inner = ((inner << (count % width)
8280 | (inner >> (width - (count % width)))) & mode_mask);
8282 nonzero &= (outer | inner);
8287 /* This is at most the number of bits in the mode. */
8288 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8292 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8293 | nonzero_bits (XEXP (x, 2), mode));
8303 /* See the macro definition above. */
8304 #undef num_sign_bit_copies
8306 /* Return the number of bits at the high-order end of X that are known to
8307 be equal to the sign bit. X will be used in mode MODE; if MODE is
8308 VOIDmode, X will be used in its own mode. The returned value will always
8309 be between 1 and the number of bits in MODE. */
8312 num_sign_bit_copies (x, mode)
8314 enum machine_mode mode;
8316 enum rtx_code code = GET_CODE (x);
8317 unsigned int bitwidth;
8318 int num0, num1, result;
8319 unsigned HOST_WIDE_INT nonzero;
8322 /* If we weren't given a mode, use the mode of X. If the mode is still
8323 VOIDmode, we don't know anything. Likewise if one of the modes is
8326 if (mode == VOIDmode)
8327 mode = GET_MODE (x);
8329 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8332 bitwidth = GET_MODE_BITSIZE (mode);
8334 /* For a smaller object, just ignore the high bits. */
8335 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8337 num0 = num_sign_bit_copies (x, GET_MODE (x));
8339 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8342 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8344 #ifndef WORD_REGISTER_OPERATIONS
8345 /* If this machine does not do all register operations on the entire
8346 register and MODE is wider than the mode of X, we can say nothing
8347 at all about the high-order bits. */
8350 /* Likewise on machines that do, if the mode of the object is smaller
8351 than a word and loads of that size don't sign extend, we can say
8352 nothing about the high order bits. */
8353 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8354 #ifdef LOAD_EXTEND_OP
8355 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8366 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8367 /* If pointers extend signed and this is a pointer in Pmode, say that
8368 all the bits above ptr_mode are known to be sign bit copies. */
8369 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8371 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8374 if (reg_last_set_value[REGNO (x)] != 0
8375 && reg_last_set_mode[REGNO (x)] == mode
8376 && (reg_last_set_label[REGNO (x)] == label_tick
8377 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8378 && REG_N_SETS (REGNO (x)) == 1
8379 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8381 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8382 return reg_last_set_sign_bit_copies[REGNO (x)];
8384 tem = get_last_value (x);
8386 return num_sign_bit_copies (tem, mode);
8388 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8389 return reg_sign_bit_copies[REGNO (x)];
8393 #ifdef LOAD_EXTEND_OP
8394 /* Some RISC machines sign-extend all loads of smaller than a word. */
8395 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8396 return MAX (1, ((int) bitwidth
8397 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8402 /* If the constant is negative, take its 1's complement and remask.
8403 Then see how many zero bits we have. */
8404 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8405 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8406 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8407 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8409 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8412 /* If this is a SUBREG for a promoted object that is sign-extended
8413 and we are looking at it in a wider mode, we know that at least the
8414 high-order bits are known to be sign bit copies. */
8416 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8418 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8419 return MAX ((int) bitwidth
8420 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8424 /* For a smaller object, just ignore the high bits. */
8425 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8427 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8428 return MAX (1, (num0
8429 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8433 #ifdef WORD_REGISTER_OPERATIONS
8434 #ifdef LOAD_EXTEND_OP
8435 /* For paradoxical SUBREGs on machines where all register operations
8436 affect the entire register, just look inside. Note that we are
8437 passing MODE to the recursive call, so the number of sign bit copies
8438 will remain relative to that mode, not the inner mode. */
8440 /* This works only if loads sign extend. Otherwise, if we get a
8441 reload for the inner part, it may be loaded from the stack, and
8442 then we lose all sign bit copies that existed before the store
8445 if ((GET_MODE_SIZE (GET_MODE (x))
8446 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8447 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8448 return num_sign_bit_copies (SUBREG_REG (x), mode);
8454 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8455 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8459 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8460 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8463 /* For a smaller object, just ignore the high bits. */
8464 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8465 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8469 return num_sign_bit_copies (XEXP (x, 0), mode);
8471 case ROTATE: case ROTATERT:
8472 /* If we are rotating left by a number of bits less than the number
8473 of sign bit copies, we can just subtract that amount from the
8475 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8476 && INTVAL (XEXP (x, 1)) >= 0
8477 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8479 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8480 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8481 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8486 /* In general, this subtracts one sign bit copy. But if the value
8487 is known to be positive, the number of sign bit copies is the
8488 same as that of the input. Finally, if the input has just one bit
8489 that might be nonzero, all the bits are copies of the sign bit. */
8490 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8491 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8492 return num0 > 1 ? num0 - 1 : 1;
8494 nonzero = nonzero_bits (XEXP (x, 0), mode);
8499 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8504 case IOR: case AND: case XOR:
8505 case SMIN: case SMAX: case UMIN: case UMAX:
8506 /* Logical operations will preserve the number of sign-bit copies.
8507 MIN and MAX operations always return one of the operands. */
8508 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8509 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8510 return MIN (num0, num1);
8512 case PLUS: case MINUS:
8513 /* For addition and subtraction, we can have a 1-bit carry. However,
8514 if we are subtracting 1 from a positive number, there will not
8515 be such a carry. Furthermore, if the positive number is known to
8516 be 0 or 1, we know the result is either -1 or 0. */
8518 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8519 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8521 nonzero = nonzero_bits (XEXP (x, 0), mode);
8522 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8523 return (nonzero == 1 || nonzero == 0 ? bitwidth
8524 : bitwidth - floor_log2 (nonzero) - 1);
8527 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8528 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8529 result = MAX (1, MIN (num0, num1) - 1);
8531 #ifdef POINTERS_EXTEND_UNSIGNED
8532 /* If pointers extend signed and this is an addition or subtraction
8533 to a pointer in Pmode, all the bits above ptr_mode are known to be
8535 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8536 && (code == PLUS || code == MINUS)
8537 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8538 result = MAX ((int)(GET_MODE_BITSIZE (Pmode)
8539 - GET_MODE_BITSIZE (ptr_mode) + 1),
8545 /* The number of bits of the product is the sum of the number of
8546 bits of both terms. However, unless one of the terms if known
8547 to be positive, we must allow for an additional bit since negating
8548 a negative number can remove one sign bit copy. */
8550 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8551 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8553 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8555 && (bitwidth > HOST_BITS_PER_WIDE_INT
8556 || (((nonzero_bits (XEXP (x, 0), mode)
8557 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8558 && ((nonzero_bits (XEXP (x, 1), mode)
8559 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8562 return MAX (1, result);
8565 /* The result must be <= the first operand. If the first operand
8566 has the high bit set, we know nothing about the number of sign
8568 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8570 else if ((nonzero_bits (XEXP (x, 0), mode)
8571 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8574 return num_sign_bit_copies (XEXP (x, 0), mode);
8577 /* The result must be <= the second operand. */
8578 return num_sign_bit_copies (XEXP (x, 1), mode);
8581 /* Similar to unsigned division, except that we have to worry about
8582 the case where the divisor is negative, in which case we have
8584 result = num_sign_bit_copies (XEXP (x, 0), mode);
8586 && (bitwidth > HOST_BITS_PER_WIDE_INT
8587 || (nonzero_bits (XEXP (x, 1), mode)
8588 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8594 result = num_sign_bit_copies (XEXP (x, 1), mode);
8596 && (bitwidth > HOST_BITS_PER_WIDE_INT
8597 || (nonzero_bits (XEXP (x, 1), mode)
8598 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8604 /* Shifts by a constant add to the number of bits equal to the
8606 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8607 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8608 && INTVAL (XEXP (x, 1)) > 0)
8609 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8614 /* Left shifts destroy copies. */
8615 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8616 || INTVAL (XEXP (x, 1)) < 0
8617 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8620 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8621 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8624 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8625 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8626 return MIN (num0, num1);
8628 case EQ: case NE: case GE: case GT: case LE: case LT:
8629 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8630 case GEU: case GTU: case LEU: case LTU:
8631 case UNORDERED: case ORDERED:
8632 /* If the constant is negative, take its 1's complement and remask.
8633 Then see how many zero bits we have. */
8634 nonzero = STORE_FLAG_VALUE;
8635 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8636 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8637 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8639 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8646 /* If we haven't been able to figure it out by one of the above rules,
8647 see if some of the high-order bits are known to be zero. If so,
8648 count those bits and return one less than that amount. If we can't
8649 safely compute the mask for this mode, always return BITWIDTH. */
8651 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8654 nonzero = nonzero_bits (x, mode);
8655 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8656 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8659 /* Return the number of "extended" bits there are in X, when interpreted
8660 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8661 unsigned quantities, this is the number of high-order zero bits.
8662 For signed quantities, this is the number of copies of the sign bit
8663 minus 1. In both case, this function returns the number of "spare"
8664 bits. For example, if two quantities for which this function returns
8665 at least 1 are added, the addition is known not to overflow.
8667 This function will always return 0 unless called during combine, which
8668 implies that it must be called from a define_split. */
8671 extended_count (x, mode, unsignedp)
8673 enum machine_mode mode;
8676 if (nonzero_sign_valid == 0)
8680 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8681 ? (GET_MODE_BITSIZE (mode) - 1
8682 - floor_log2 (nonzero_bits (x, mode)))
8684 : num_sign_bit_copies (x, mode) - 1);
8687 /* This function is called from `simplify_shift_const' to merge two
8688 outer operations. Specifically, we have already found that we need
8689 to perform operation *POP0 with constant *PCONST0 at the outermost
8690 position. We would now like to also perform OP1 with constant CONST1
8691 (with *POP0 being done last).
8693 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8694 the resulting operation. *PCOMP_P is set to 1 if we would need to
8695 complement the innermost operand, otherwise it is unchanged.
8697 MODE is the mode in which the operation will be done. No bits outside
8698 the width of this mode matter. It is assumed that the width of this mode
8699 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8701 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8702 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8703 result is simply *PCONST0.
8705 If the resulting operation cannot be expressed as one operation, we
8706 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8709 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8710 enum rtx_code *pop0;
8711 HOST_WIDE_INT *pconst0;
8713 HOST_WIDE_INT const1;
8714 enum machine_mode mode;
8717 enum rtx_code op0 = *pop0;
8718 HOST_WIDE_INT const0 = *pconst0;
8720 const0 &= GET_MODE_MASK (mode);
8721 const1 &= GET_MODE_MASK (mode);
8723 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8727 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8730 if (op1 == NIL || op0 == SET)
8733 else if (op0 == NIL)
8734 op0 = op1, const0 = const1;
8736 else if (op0 == op1)
8760 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8761 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8764 /* If the two constants aren't the same, we can't do anything. The
8765 remaining six cases can all be done. */
8766 else if (const0 != const1)
8774 /* (a & b) | b == b */
8776 else /* op1 == XOR */
8777 /* (a ^ b) | b == a | b */
8783 /* (a & b) ^ b == (~a) & b */
8784 op0 = AND, *pcomp_p = 1;
8785 else /* op1 == IOR */
8786 /* (a | b) ^ b == a & ~b */
8787 op0 = AND, *pconst0 = ~const0;
8792 /* (a | b) & b == b */
8794 else /* op1 == XOR */
8795 /* (a ^ b) & b) == (~a) & b */
8802 /* Check for NO-OP cases. */
8803 const0 &= GET_MODE_MASK (mode);
8805 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8807 else if (const0 == 0 && op0 == AND)
8809 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8813 /* ??? Slightly redundant with the above mask, but not entirely.
8814 Moving this above means we'd have to sign-extend the mode mask
8815 for the final test. */
8816 const0 = trunc_int_for_mode (const0, mode);
8824 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8825 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8826 that we started with.
8828 The shift is normally computed in the widest mode we find in VAROP, as
8829 long as it isn't a different number of words than RESULT_MODE. Exceptions
8830 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8833 simplify_shift_const (x, code, result_mode, varop, orig_count)
8836 enum machine_mode result_mode;
8840 enum rtx_code orig_code = code;
8843 enum machine_mode mode = result_mode;
8844 enum machine_mode shift_mode, tmode;
8845 unsigned int mode_words
8846 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8847 /* We form (outer_op (code varop count) (outer_const)). */
8848 enum rtx_code outer_op = NIL;
8849 HOST_WIDE_INT outer_const = 0;
8851 int complement_p = 0;
8854 /* Make sure and truncate the "natural" shift on the way in. We don't
8855 want to do this inside the loop as it makes it more difficult to
8857 #ifdef SHIFT_COUNT_TRUNCATED
8858 if (SHIFT_COUNT_TRUNCATED)
8859 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8862 /* If we were given an invalid count, don't do anything except exactly
8863 what was requested. */
8865 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8870 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8875 /* Unless one of the branches of the `if' in this loop does a `continue',
8876 we will `break' the loop after the `if'. */
8880 /* If we have an operand of (clobber (const_int 0)), just return that
8882 if (GET_CODE (varop) == CLOBBER)
8885 /* If we discovered we had to complement VAROP, leave. Making a NOT
8886 here would cause an infinite loop. */
8890 /* Convert ROTATERT to ROTATE. */
8891 if (code == ROTATERT)
8892 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8894 /* We need to determine what mode we will do the shift in. If the
8895 shift is a right shift or a ROTATE, we must always do it in the mode
8896 it was originally done in. Otherwise, we can do it in MODE, the
8897 widest mode encountered. */
8899 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8900 ? result_mode : mode);
8902 /* Handle cases where the count is greater than the size of the mode
8903 minus 1. For ASHIFT, use the size minus one as the count (this can
8904 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8905 take the count modulo the size. For other shifts, the result is
8908 Since these shifts are being produced by the compiler by combining
8909 multiple operations, each of which are defined, we know what the
8910 result is supposed to be. */
8912 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8914 if (code == ASHIFTRT)
8915 count = GET_MODE_BITSIZE (shift_mode) - 1;
8916 else if (code == ROTATE || code == ROTATERT)
8917 count %= GET_MODE_BITSIZE (shift_mode);
8920 /* We can't simply return zero because there may be an
8928 /* An arithmetic right shift of a quantity known to be -1 or 0
8930 if (code == ASHIFTRT
8931 && (num_sign_bit_copies (varop, shift_mode)
8932 == GET_MODE_BITSIZE (shift_mode)))
8938 /* If we are doing an arithmetic right shift and discarding all but
8939 the sign bit copies, this is equivalent to doing a shift by the
8940 bitsize minus one. Convert it into that shift because it will often
8941 allow other simplifications. */
8943 if (code == ASHIFTRT
8944 && (count + num_sign_bit_copies (varop, shift_mode)
8945 >= GET_MODE_BITSIZE (shift_mode)))
8946 count = GET_MODE_BITSIZE (shift_mode) - 1;
8948 /* We simplify the tests below and elsewhere by converting
8949 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8950 `make_compound_operation' will convert it to a ASHIFTRT for
8951 those machines (such as VAX) that don't have a LSHIFTRT. */
8952 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8954 && ((nonzero_bits (varop, shift_mode)
8955 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8959 switch (GET_CODE (varop))
8965 new = expand_compound_operation (varop);
8974 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8975 minus the width of a smaller mode, we can do this with a
8976 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8977 if ((code == ASHIFTRT || code == LSHIFTRT)
8978 && ! mode_dependent_address_p (XEXP (varop, 0))
8979 && ! MEM_VOLATILE_P (varop)
8980 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8981 MODE_INT, 1)) != BLKmode)
8983 new = adjust_address_nv (varop, tmode,
8984 BYTES_BIG_ENDIAN ? 0
8985 : count / BITS_PER_UNIT);
8987 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8988 : ZERO_EXTEND, mode, new);
8995 /* Similar to the case above, except that we can only do this if
8996 the resulting mode is the same as that of the underlying
8997 MEM and adjust the address depending on the *bits* endianness
8998 because of the way that bit-field extract insns are defined. */
8999 if ((code == ASHIFTRT || code == LSHIFTRT)
9000 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9001 MODE_INT, 1)) != BLKmode
9002 && tmode == GET_MODE (XEXP (varop, 0)))
9004 if (BITS_BIG_ENDIAN)
9005 new = XEXP (varop, 0);
9008 new = copy_rtx (XEXP (varop, 0));
9009 SUBST (XEXP (new, 0),
9010 plus_constant (XEXP (new, 0),
9011 count / BITS_PER_UNIT));
9014 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9015 : ZERO_EXTEND, mode, new);
9022 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9023 the same number of words as what we've seen so far. Then store
9024 the widest mode in MODE. */
9025 if (subreg_lowpart_p (varop)
9026 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9027 > GET_MODE_SIZE (GET_MODE (varop)))
9028 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9029 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9032 varop = SUBREG_REG (varop);
9033 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9034 mode = GET_MODE (varop);
9040 /* Some machines use MULT instead of ASHIFT because MULT
9041 is cheaper. But it is still better on those machines to
9042 merge two shifts into one. */
9043 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9044 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9047 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9048 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9054 /* Similar, for when divides are cheaper. */
9055 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9056 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9059 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9060 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9066 /* If we are extracting just the sign bit of an arithmetic
9067 right shift, that shift is not needed. However, the sign
9068 bit of a wider mode may be different from what would be
9069 interpreted as the sign bit in a narrower mode, so, if
9070 the result is narrower, don't discard the shift. */
9071 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9072 && (GET_MODE_BITSIZE (result_mode)
9073 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9075 varop = XEXP (varop, 0);
9079 /* ... fall through ... */
9084 /* Here we have two nested shifts. The result is usually the
9085 AND of a new shift with a mask. We compute the result below. */
9086 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9087 && INTVAL (XEXP (varop, 1)) >= 0
9088 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9089 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9090 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9092 enum rtx_code first_code = GET_CODE (varop);
9093 unsigned int first_count = INTVAL (XEXP (varop, 1));
9094 unsigned HOST_WIDE_INT mask;
9097 /* We have one common special case. We can't do any merging if
9098 the inner code is an ASHIFTRT of a smaller mode. However, if
9099 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9100 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9101 we can convert it to
9102 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9103 This simplifies certain SIGN_EXTEND operations. */
9104 if (code == ASHIFT && first_code == ASHIFTRT
9105 && (GET_MODE_BITSIZE (result_mode)
9106 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9108 /* C3 has the low-order C1 bits zero. */
9110 mask = (GET_MODE_MASK (mode)
9111 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9113 varop = simplify_and_const_int (NULL_RTX, result_mode,
9114 XEXP (varop, 0), mask);
9115 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9117 count = first_count;
9122 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9123 than C1 high-order bits equal to the sign bit, we can convert
9124 this to either an ASHIFT or a ASHIFTRT depending on the
9127 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9129 if (code == ASHIFTRT && first_code == ASHIFT
9130 && GET_MODE (varop) == shift_mode
9131 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9134 varop = XEXP (varop, 0);
9136 signed_count = count - first_count;
9137 if (signed_count < 0)
9138 count = -signed_count, code = ASHIFT;
9140 count = signed_count;
9145 /* There are some cases we can't do. If CODE is ASHIFTRT,
9146 we can only do this if FIRST_CODE is also ASHIFTRT.
9148 We can't do the case when CODE is ROTATE and FIRST_CODE is
9151 If the mode of this shift is not the mode of the outer shift,
9152 we can't do this if either shift is a right shift or ROTATE.
9154 Finally, we can't do any of these if the mode is too wide
9155 unless the codes are the same.
9157 Handle the case where the shift codes are the same
9160 if (code == first_code)
9162 if (GET_MODE (varop) != result_mode
9163 && (code == ASHIFTRT || code == LSHIFTRT
9167 count += first_count;
9168 varop = XEXP (varop, 0);
9172 if (code == ASHIFTRT
9173 || (code == ROTATE && first_code == ASHIFTRT)
9174 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9175 || (GET_MODE (varop) != result_mode
9176 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9177 || first_code == ROTATE
9178 || code == ROTATE)))
9181 /* To compute the mask to apply after the shift, shift the
9182 nonzero bits of the inner shift the same way the
9183 outer shift will. */
9185 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9188 = simplify_binary_operation (code, result_mode, mask_rtx,
9191 /* Give up if we can't compute an outer operation to use. */
9193 || GET_CODE (mask_rtx) != CONST_INT
9194 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9196 result_mode, &complement_p))
9199 /* If the shifts are in the same direction, we add the
9200 counts. Otherwise, we subtract them. */
9201 signed_count = count;
9202 if ((code == ASHIFTRT || code == LSHIFTRT)
9203 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9204 signed_count += first_count;
9206 signed_count -= first_count;
9208 /* If COUNT is positive, the new shift is usually CODE,
9209 except for the two exceptions below, in which case it is
9210 FIRST_CODE. If the count is negative, FIRST_CODE should
9212 if (signed_count > 0
9213 && ((first_code == ROTATE && code == ASHIFT)
9214 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9215 code = first_code, count = signed_count;
9216 else if (signed_count < 0)
9217 code = first_code, count = -signed_count;
9219 count = signed_count;
9221 varop = XEXP (varop, 0);
9225 /* If we have (A << B << C) for any shift, we can convert this to
9226 (A << C << B). This wins if A is a constant. Only try this if
9227 B is not a constant. */
9229 else if (GET_CODE (varop) == code
9230 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9232 = simplify_binary_operation (code, mode,
9236 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9243 /* Make this fit the case below. */
9244 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9245 GEN_INT (GET_MODE_MASK (mode)));
9251 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9252 with C the size of VAROP - 1 and the shift is logical if
9253 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9254 we have an (le X 0) operation. If we have an arithmetic shift
9255 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9256 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9258 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9259 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9260 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9261 && (code == LSHIFTRT || code == ASHIFTRT)
9262 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9263 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9266 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9269 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9270 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9275 /* If we have (shift (logical)), move the logical to the outside
9276 to allow it to possibly combine with another logical and the
9277 shift to combine with another shift. This also canonicalizes to
9278 what a ZERO_EXTRACT looks like. Also, some machines have
9279 (and (shift)) insns. */
9281 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9282 && (new = simplify_binary_operation (code, result_mode,
9284 GEN_INT (count))) != 0
9285 && GET_CODE (new) == CONST_INT
9286 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9287 INTVAL (new), result_mode, &complement_p))
9289 varop = XEXP (varop, 0);
9293 /* If we can't do that, try to simplify the shift in each arm of the
9294 logical expression, make a new logical expression, and apply
9295 the inverse distributive law. */
9297 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9298 XEXP (varop, 0), count);
9299 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9300 XEXP (varop, 1), count);
9302 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9303 varop = apply_distributive_law (varop);
9310 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9311 says that the sign bit can be tested, FOO has mode MODE, C is
9312 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9313 that may be nonzero. */
9314 if (code == LSHIFTRT
9315 && XEXP (varop, 1) == const0_rtx
9316 && GET_MODE (XEXP (varop, 0)) == result_mode
9317 && count == GET_MODE_BITSIZE (result_mode) - 1
9318 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9319 && ((STORE_FLAG_VALUE
9320 & ((HOST_WIDE_INT) 1
9321 < (GET_MODE_BITSIZE (result_mode) - 1))))
9322 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9323 && merge_outer_ops (&outer_op, &outer_const, XOR,
9324 (HOST_WIDE_INT) 1, result_mode,
9327 varop = XEXP (varop, 0);
9334 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9335 than the number of bits in the mode is equivalent to A. */
9336 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9337 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9339 varop = XEXP (varop, 0);
9344 /* NEG commutes with ASHIFT since it is multiplication. Move the
9345 NEG outside to allow shifts to combine. */
9347 && merge_outer_ops (&outer_op, &outer_const, NEG,
9348 (HOST_WIDE_INT) 0, result_mode,
9351 varop = XEXP (varop, 0);
9357 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9358 is one less than the number of bits in the mode is
9359 equivalent to (xor A 1). */
9360 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9361 && XEXP (varop, 1) == constm1_rtx
9362 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9363 && merge_outer_ops (&outer_op, &outer_const, XOR,
9364 (HOST_WIDE_INT) 1, result_mode,
9368 varop = XEXP (varop, 0);
9372 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9373 that might be nonzero in BAR are those being shifted out and those
9374 bits are known zero in FOO, we can replace the PLUS with FOO.
9375 Similarly in the other operand order. This code occurs when
9376 we are computing the size of a variable-size array. */
9378 if ((code == ASHIFTRT || code == LSHIFTRT)
9379 && count < HOST_BITS_PER_WIDE_INT
9380 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9381 && (nonzero_bits (XEXP (varop, 1), result_mode)
9382 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9384 varop = XEXP (varop, 0);
9387 else if ((code == ASHIFTRT || code == LSHIFTRT)
9388 && count < HOST_BITS_PER_WIDE_INT
9389 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9390 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9392 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9393 & nonzero_bits (XEXP (varop, 1),
9396 varop = XEXP (varop, 1);
9400 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9402 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9403 && (new = simplify_binary_operation (ASHIFT, result_mode,
9405 GEN_INT (count))) != 0
9406 && GET_CODE (new) == CONST_INT
9407 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9408 INTVAL (new), result_mode, &complement_p))
9410 varop = XEXP (varop, 0);
9416 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9417 with C the size of VAROP - 1 and the shift is logical if
9418 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9419 we have a (gt X 0) operation. If the shift is arithmetic with
9420 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9421 we have a (neg (gt X 0)) operation. */
9423 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9424 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9425 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9426 && (code == LSHIFTRT || code == ASHIFTRT)
9427 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9428 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9429 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9432 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9435 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9436 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9443 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9444 if the truncate does not affect the value. */
9445 if (code == LSHIFTRT
9446 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9447 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9448 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9449 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9450 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9452 rtx varop_inner = XEXP (varop, 0);
9455 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9456 XEXP (varop_inner, 0),
9458 (count + INTVAL (XEXP (varop_inner, 1))));
9459 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9472 /* We need to determine what mode to do the shift in. If the shift is
9473 a right shift or ROTATE, we must always do it in the mode it was
9474 originally done in. Otherwise, we can do it in MODE, the widest mode
9475 encountered. The code we care about is that of the shift that will
9476 actually be done, not the shift that was originally requested. */
9478 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9479 ? result_mode : mode);
9481 /* We have now finished analyzing the shift. The result should be
9482 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9483 OUTER_OP is non-NIL, it is an operation that needs to be applied
9484 to the result of the shift. OUTER_CONST is the relevant constant,
9485 but we must turn off all bits turned off in the shift.
9487 If we were passed a value for X, see if we can use any pieces of
9488 it. If not, make new rtx. */
9490 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9491 && GET_CODE (XEXP (x, 1)) == CONST_INT
9492 && INTVAL (XEXP (x, 1)) == count)
9493 const_rtx = XEXP (x, 1);
9495 const_rtx = GEN_INT (count);
9497 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9498 && GET_MODE (XEXP (x, 0)) == shift_mode
9499 && SUBREG_REG (XEXP (x, 0)) == varop)
9500 varop = XEXP (x, 0);
9501 else if (GET_MODE (varop) != shift_mode)
9502 varop = gen_lowpart_for_combine (shift_mode, varop);
9504 /* If we can't make the SUBREG, try to return what we were given. */
9505 if (GET_CODE (varop) == CLOBBER)
9506 return x ? x : varop;
9508 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9513 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9514 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9516 SUBST (XEXP (x, 0), varop);
9517 SUBST (XEXP (x, 1), const_rtx);
9520 /* If we have an outer operation and we just made a shift, it is
9521 possible that we could have simplified the shift were it not
9522 for the outer operation. So try to do the simplification
9525 if (outer_op != NIL && GET_CODE (x) == code
9526 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9527 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9528 INTVAL (XEXP (x, 1)));
9530 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9531 turn off all the bits that the shift would have turned off. */
9532 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9533 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9534 GET_MODE_MASK (result_mode) >> orig_count);
9536 /* Do the remainder of the processing in RESULT_MODE. */
9537 x = gen_lowpart_for_combine (result_mode, x);
9539 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9542 x =simplify_gen_unary (NOT, result_mode, x, result_mode);
9544 if (outer_op != NIL)
9546 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9547 outer_const = trunc_int_for_mode (outer_const, result_mode);
9549 if (outer_op == AND)
9550 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9551 else if (outer_op == SET)
9552 /* This means that we have determined that the result is
9553 equivalent to a constant. This should be rare. */
9554 x = GEN_INT (outer_const);
9555 else if (GET_RTX_CLASS (outer_op) == '1')
9556 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9558 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9564 /* Like recog, but we receive the address of a pointer to a new pattern.
9565 We try to match the rtx that the pointer points to.
9566 If that fails, we may try to modify or replace the pattern,
9567 storing the replacement into the same pointer object.
9569 Modifications include deletion or addition of CLOBBERs.
9571 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9572 the CLOBBERs are placed.
9574 The value is the final insn code from the pattern ultimately matched,
9578 recog_for_combine (pnewpat, insn, pnotes)
9584 int insn_code_number;
9585 int num_clobbers_to_add = 0;
9590 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9591 we use to indicate that something didn't match. If we find such a
9592 thing, force rejection. */
9593 if (GET_CODE (pat) == PARALLEL)
9594 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9595 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9596 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9599 /* Remove the old notes prior to trying to recognize the new pattern. */
9600 old_notes = REG_NOTES (insn);
9601 REG_NOTES (insn) = 0;
9603 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9605 /* If it isn't, there is the possibility that we previously had an insn
9606 that clobbered some register as a side effect, but the combined
9607 insn doesn't need to do that. So try once more without the clobbers
9608 unless this represents an ASM insn. */
9610 if (insn_code_number < 0 && ! check_asm_operands (pat)
9611 && GET_CODE (pat) == PARALLEL)
9615 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9616 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9619 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9623 SUBST_INT (XVECLEN (pat, 0), pos);
9626 pat = XVECEXP (pat, 0, 0);
9628 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9631 /* Recognize all noop sets, these will be killed by followup pass. */
9632 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9633 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9635 REG_NOTES (insn) = old_notes;
9637 /* If we had any clobbers to add, make a new pattern than contains
9638 them. Then check to make sure that all of them are dead. */
9639 if (num_clobbers_to_add)
9641 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9642 rtvec_alloc (GET_CODE (pat) == PARALLEL
9644 + num_clobbers_to_add)
9645 : num_clobbers_to_add + 1));
9647 if (GET_CODE (pat) == PARALLEL)
9648 for (i = 0; i < XVECLEN (pat, 0); i++)
9649 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9651 XVECEXP (newpat, 0, 0) = pat;
9653 add_clobbers (newpat, insn_code_number);
9655 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9656 i < XVECLEN (newpat, 0); i++)
9658 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9659 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9661 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9662 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9670 return insn_code_number;
9673 /* Like gen_lowpart but for use by combine. In combine it is not possible
9674 to create any new pseudoregs. However, it is safe to create
9675 invalid memory addresses, because combine will try to recognize
9676 them and all they will do is make the combine attempt fail.
9678 If for some reason this cannot do its job, an rtx
9679 (clobber (const_int 0)) is returned.
9680 An insn containing that will not be recognized. */
9685 gen_lowpart_for_combine (mode, x)
9686 enum machine_mode mode;
9691 if (GET_MODE (x) == mode)
9694 /* We can only support MODE being wider than a word if X is a
9695 constant integer or has a mode the same size. */
9697 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9698 && ! ((GET_MODE (x) == VOIDmode
9699 && (GET_CODE (x) == CONST_INT
9700 || GET_CODE (x) == CONST_DOUBLE))
9701 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9702 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9704 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9705 won't know what to do. So we will strip off the SUBREG here and
9706 process normally. */
9707 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9710 if (GET_MODE (x) == mode)
9714 result = gen_lowpart_common (mode, x);
9715 #ifdef CLASS_CANNOT_CHANGE_MODE
9717 && GET_CODE (result) == SUBREG
9718 && GET_CODE (SUBREG_REG (result)) == REG
9719 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9720 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9721 GET_MODE (SUBREG_REG (result))))
9722 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9728 if (GET_CODE (x) == MEM)
9732 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9734 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9735 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9737 /* If we want to refer to something bigger than the original memref,
9738 generate a perverse subreg instead. That will force a reload
9739 of the original memref X. */
9740 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9741 return gen_rtx_SUBREG (mode, x, 0);
9743 if (WORDS_BIG_ENDIAN)
9744 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9745 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9747 if (BYTES_BIG_ENDIAN)
9749 /* Adjust the address so that the address-after-the-data is
9751 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9752 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9755 return adjust_address_nv (x, mode, offset);
9758 /* If X is a comparison operator, rewrite it in a new mode. This
9759 probably won't match, but may allow further simplifications. */
9760 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9761 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9763 /* If we couldn't simplify X any other way, just enclose it in a
9764 SUBREG. Normally, this SUBREG won't match, but some patterns may
9765 include an explicit SUBREG or we may simplify it further in combine. */
9771 offset = subreg_lowpart_offset (mode, GET_MODE (x));
9772 res = simplify_gen_subreg (mode, x, GET_MODE (x), offset);
9775 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9779 /* These routines make binary and unary operations by first seeing if they
9780 fold; if not, a new expression is allocated. */
9783 gen_binary (code, mode, op0, op1)
9785 enum machine_mode mode;
9791 if (GET_RTX_CLASS (code) == 'c'
9792 && swap_commutative_operands_p (op0, op1))
9793 tem = op0, op0 = op1, op1 = tem;
9795 if (GET_RTX_CLASS (code) == '<')
9797 enum machine_mode op_mode = GET_MODE (op0);
9799 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9800 just (REL_OP X Y). */
9801 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9803 op1 = XEXP (op0, 1);
9804 op0 = XEXP (op0, 0);
9805 op_mode = GET_MODE (op0);
9808 if (op_mode == VOIDmode)
9809 op_mode = GET_MODE (op1);
9810 result = simplify_relational_operation (code, op_mode, op0, op1);
9813 result = simplify_binary_operation (code, mode, op0, op1);
9818 /* Put complex operands first and constants second. */
9819 if (GET_RTX_CLASS (code) == 'c'
9820 && swap_commutative_operands_p (op0, op1))
9821 return gen_rtx_fmt_ee (code, mode, op1, op0);
9823 /* If we are turning off bits already known off in OP0, we need not do
9825 else if (code == AND && GET_CODE (op1) == CONST_INT
9826 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9827 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9830 return gen_rtx_fmt_ee (code, mode, op0, op1);
9833 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9834 comparison code that will be tested.
9836 The result is a possibly different comparison code to use. *POP0 and
9837 *POP1 may be updated.
9839 It is possible that we might detect that a comparison is either always
9840 true or always false. However, we do not perform general constant
9841 folding in combine, so this knowledge isn't useful. Such tautologies
9842 should have been detected earlier. Hence we ignore all such cases. */
9844 static enum rtx_code
9845 simplify_comparison (code, pop0, pop1)
9854 enum machine_mode mode, tmode;
9856 /* Try a few ways of applying the same transformation to both operands. */
9859 #ifndef WORD_REGISTER_OPERATIONS
9860 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9861 so check specially. */
9862 if (code != GTU && code != GEU && code != LTU && code != LEU
9863 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9864 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9865 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9866 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9867 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9868 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9869 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9870 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9871 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9872 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9873 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9874 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9875 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9876 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9877 && (INTVAL (XEXP (op0, 1))
9878 == (GET_MODE_BITSIZE (GET_MODE (op0))
9880 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9882 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9883 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9887 /* If both operands are the same constant shift, see if we can ignore the
9888 shift. We can if the shift is a rotate or if the bits shifted out of
9889 this shift are known to be zero for both inputs and if the type of
9890 comparison is compatible with the shift. */
9891 if (GET_CODE (op0) == GET_CODE (op1)
9892 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9893 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9894 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9895 && (code != GT && code != LT && code != GE && code != LE))
9896 || (GET_CODE (op0) == ASHIFTRT
9897 && (code != GTU && code != LTU
9898 && code != GEU && code != LEU)))
9899 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9900 && INTVAL (XEXP (op0, 1)) >= 0
9901 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9902 && XEXP (op0, 1) == XEXP (op1, 1))
9904 enum machine_mode mode = GET_MODE (op0);
9905 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9906 int shift_count = INTVAL (XEXP (op0, 1));
9908 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9909 mask &= (mask >> shift_count) << shift_count;
9910 else if (GET_CODE (op0) == ASHIFT)
9911 mask = (mask & (mask << shift_count)) >> shift_count;
9913 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9914 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9915 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9920 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9921 SUBREGs are of the same mode, and, in both cases, the AND would
9922 be redundant if the comparison was done in the narrower mode,
9923 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9924 and the operand's possibly nonzero bits are 0xffffff01; in that case
9925 if we only care about QImode, we don't need the AND). This case
9926 occurs if the output mode of an scc insn is not SImode and
9927 STORE_FLAG_VALUE == 1 (e.g., the 386).
9929 Similarly, check for a case where the AND's are ZERO_EXTEND
9930 operations from some narrower mode even though a SUBREG is not
9933 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9934 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9935 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9937 rtx inner_op0 = XEXP (op0, 0);
9938 rtx inner_op1 = XEXP (op1, 0);
9939 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9940 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9943 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9944 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9945 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9946 && (GET_MODE (SUBREG_REG (inner_op0))
9947 == GET_MODE (SUBREG_REG (inner_op1)))
9948 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9949 <= HOST_BITS_PER_WIDE_INT)
9950 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9951 GET_MODE (SUBREG_REG (inner_op0)))))
9952 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9953 GET_MODE (SUBREG_REG (inner_op1))))))
9955 op0 = SUBREG_REG (inner_op0);
9956 op1 = SUBREG_REG (inner_op1);
9958 /* The resulting comparison is always unsigned since we masked
9959 off the original sign bit. */
9960 code = unsigned_condition (code);
9966 for (tmode = GET_CLASS_NARROWEST_MODE
9967 (GET_MODE_CLASS (GET_MODE (op0)));
9968 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9969 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9971 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9972 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9973 code = unsigned_condition (code);
9982 /* If both operands are NOT, we can strip off the outer operation
9983 and adjust the comparison code for swapped operands; similarly for
9984 NEG, except that this must be an equality comparison. */
9985 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9986 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9987 && (code == EQ || code == NE)))
9988 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9994 /* If the first operand is a constant, swap the operands and adjust the
9995 comparison code appropriately, but don't do this if the second operand
9996 is already a constant integer. */
9997 if (swap_commutative_operands_p (op0, op1))
9999 tem = op0, op0 = op1, op1 = tem;
10000 code = swap_condition (code);
10003 /* We now enter a loop during which we will try to simplify the comparison.
10004 For the most part, we only are concerned with comparisons with zero,
10005 but some things may really be comparisons with zero but not start
10006 out looking that way. */
10008 while (GET_CODE (op1) == CONST_INT)
10010 enum machine_mode mode = GET_MODE (op0);
10011 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10012 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10013 int equality_comparison_p;
10014 int sign_bit_comparison_p;
10015 int unsigned_comparison_p;
10016 HOST_WIDE_INT const_op;
10018 /* We only want to handle integral modes. This catches VOIDmode,
10019 CCmode, and the floating-point modes. An exception is that we
10020 can handle VOIDmode if OP0 is a COMPARE or a comparison
10023 if (GET_MODE_CLASS (mode) != MODE_INT
10024 && ! (mode == VOIDmode
10025 && (GET_CODE (op0) == COMPARE
10026 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10029 /* Get the constant we are comparing against and turn off all bits
10030 not on in our mode. */
10031 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10032 op1 = GEN_INT (const_op);
10034 /* If we are comparing against a constant power of two and the value
10035 being compared can only have that single bit nonzero (e.g., it was
10036 `and'ed with that bit), we can replace this with a comparison
10039 && (code == EQ || code == NE || code == GE || code == GEU
10040 || code == LT || code == LTU)
10041 && mode_width <= HOST_BITS_PER_WIDE_INT
10042 && exact_log2 (const_op) >= 0
10043 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10045 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10046 op1 = const0_rtx, const_op = 0;
10049 /* Similarly, if we are comparing a value known to be either -1 or
10050 0 with -1, change it to the opposite comparison against zero. */
10053 && (code == EQ || code == NE || code == GT || code == LE
10054 || code == GEU || code == LTU)
10055 && num_sign_bit_copies (op0, mode) == mode_width)
10057 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10058 op1 = const0_rtx, const_op = 0;
10061 /* Do some canonicalizations based on the comparison code. We prefer
10062 comparisons against zero and then prefer equality comparisons.
10063 If we can reduce the size of a constant, we will do that too. */
10068 /* < C is equivalent to <= (C - 1) */
10072 op1 = GEN_INT (const_op);
10074 /* ... fall through to LE case below. */
10080 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10084 op1 = GEN_INT (const_op);
10088 /* If we are doing a <= 0 comparison on a value known to have
10089 a zero sign bit, we can replace this with == 0. */
10090 else if (const_op == 0
10091 && mode_width <= HOST_BITS_PER_WIDE_INT
10092 && (nonzero_bits (op0, mode)
10093 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10098 /* >= C is equivalent to > (C - 1). */
10102 op1 = GEN_INT (const_op);
10104 /* ... fall through to GT below. */
10110 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10114 op1 = GEN_INT (const_op);
10118 /* If we are doing a > 0 comparison on a value known to have
10119 a zero sign bit, we can replace this with != 0. */
10120 else if (const_op == 0
10121 && mode_width <= HOST_BITS_PER_WIDE_INT
10122 && (nonzero_bits (op0, mode)
10123 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10128 /* < C is equivalent to <= (C - 1). */
10132 op1 = GEN_INT (const_op);
10134 /* ... fall through ... */
10137 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10138 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10139 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10141 const_op = 0, op1 = const0_rtx;
10149 /* unsigned <= 0 is equivalent to == 0 */
10153 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10154 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10155 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10157 const_op = 0, op1 = const0_rtx;
10163 /* >= C is equivalent to < (C - 1). */
10167 op1 = GEN_INT (const_op);
10169 /* ... fall through ... */
10172 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10173 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10174 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10176 const_op = 0, op1 = const0_rtx;
10184 /* unsigned > 0 is equivalent to != 0 */
10188 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10189 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10190 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10192 const_op = 0, op1 = const0_rtx;
10201 /* Compute some predicates to simplify code below. */
10203 equality_comparison_p = (code == EQ || code == NE);
10204 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10205 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10208 /* If this is a sign bit comparison and we can do arithmetic in
10209 MODE, say that we will only be needing the sign bit of OP0. */
10210 if (sign_bit_comparison_p
10211 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10212 op0 = force_to_mode (op0, mode,
10214 << (GET_MODE_BITSIZE (mode) - 1)),
10217 /* Now try cases based on the opcode of OP0. If none of the cases
10218 does a "continue", we exit this loop immediately after the
10221 switch (GET_CODE (op0))
10224 /* If we are extracting a single bit from a variable position in
10225 a constant that has only a single bit set and are comparing it
10226 with zero, we can convert this into an equality comparison
10227 between the position and the location of the single bit. */
10229 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10230 && XEXP (op0, 1) == const1_rtx
10231 && equality_comparison_p && const_op == 0
10232 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10234 if (BITS_BIG_ENDIAN)
10236 enum machine_mode new_mode
10237 = mode_for_extraction (EP_extzv, 1);
10238 if (new_mode == MAX_MACHINE_MODE)
10239 i = BITS_PER_WORD - 1 - i;
10243 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10247 op0 = XEXP (op0, 2);
10251 /* Result is nonzero iff shift count is equal to I. */
10252 code = reverse_condition (code);
10256 /* ... fall through ... */
10259 tem = expand_compound_operation (op0);
10268 /* If testing for equality, we can take the NOT of the constant. */
10269 if (equality_comparison_p
10270 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10272 op0 = XEXP (op0, 0);
10277 /* If just looking at the sign bit, reverse the sense of the
10279 if (sign_bit_comparison_p)
10281 op0 = XEXP (op0, 0);
10282 code = (code == GE ? LT : GE);
10288 /* If testing for equality, we can take the NEG of the constant. */
10289 if (equality_comparison_p
10290 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10292 op0 = XEXP (op0, 0);
10297 /* The remaining cases only apply to comparisons with zero. */
10301 /* When X is ABS or is known positive,
10302 (neg X) is < 0 if and only if X != 0. */
10304 if (sign_bit_comparison_p
10305 && (GET_CODE (XEXP (op0, 0)) == ABS
10306 || (mode_width <= HOST_BITS_PER_WIDE_INT
10307 && (nonzero_bits (XEXP (op0, 0), mode)
10308 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10310 op0 = XEXP (op0, 0);
10311 code = (code == LT ? NE : EQ);
10315 /* If we have NEG of something whose two high-order bits are the
10316 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10317 if (num_sign_bit_copies (op0, mode) >= 2)
10319 op0 = XEXP (op0, 0);
10320 code = swap_condition (code);
10326 /* If we are testing equality and our count is a constant, we
10327 can perform the inverse operation on our RHS. */
10328 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10329 && (tem = simplify_binary_operation (ROTATERT, mode,
10330 op1, XEXP (op0, 1))) != 0)
10332 op0 = XEXP (op0, 0);
10337 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10338 a particular bit. Convert it to an AND of a constant of that
10339 bit. This will be converted into a ZERO_EXTRACT. */
10340 if (const_op == 0 && sign_bit_comparison_p
10341 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10342 && mode_width <= HOST_BITS_PER_WIDE_INT)
10344 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10347 - INTVAL (XEXP (op0, 1)))));
10348 code = (code == LT ? NE : EQ);
10352 /* Fall through. */
10355 /* ABS is ignorable inside an equality comparison with zero. */
10356 if (const_op == 0 && equality_comparison_p)
10358 op0 = XEXP (op0, 0);
10364 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10365 to (compare FOO CONST) if CONST fits in FOO's mode and we
10366 are either testing inequality or have an unsigned comparison
10367 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10368 if (! unsigned_comparison_p
10369 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10370 <= HOST_BITS_PER_WIDE_INT)
10371 && ((unsigned HOST_WIDE_INT) const_op
10372 < (((unsigned HOST_WIDE_INT) 1
10373 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10375 op0 = XEXP (op0, 0);
10381 /* Check for the case where we are comparing A - C1 with C2,
10382 both constants are smaller than 1/2 the maximum positive
10383 value in MODE, and the comparison is equality or unsigned.
10384 In that case, if A is either zero-extended to MODE or has
10385 sufficient sign bits so that the high-order bit in MODE
10386 is a copy of the sign in the inner mode, we can prove that it is
10387 safe to do the operation in the wider mode. This simplifies
10388 many range checks. */
10390 if (mode_width <= HOST_BITS_PER_WIDE_INT
10391 && subreg_lowpart_p (op0)
10392 && GET_CODE (SUBREG_REG (op0)) == PLUS
10393 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10394 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10395 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10396 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10397 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10398 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10399 GET_MODE (SUBREG_REG (op0)))
10400 & ~GET_MODE_MASK (mode))
10401 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10402 GET_MODE (SUBREG_REG (op0)))
10403 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10404 - GET_MODE_BITSIZE (mode)))))
10406 op0 = SUBREG_REG (op0);
10410 /* If the inner mode is narrower and we are extracting the low part,
10411 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10412 if (subreg_lowpart_p (op0)
10413 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10414 /* Fall through */ ;
10418 /* ... fall through ... */
10421 if ((unsigned_comparison_p || equality_comparison_p)
10422 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10423 <= HOST_BITS_PER_WIDE_INT)
10424 && ((unsigned HOST_WIDE_INT) const_op
10425 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10427 op0 = XEXP (op0, 0);
10433 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10434 this for equality comparisons due to pathological cases involving
10436 if (equality_comparison_p
10437 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10438 op1, XEXP (op0, 1))))
10440 op0 = XEXP (op0, 0);
10445 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10446 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10447 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10449 op0 = XEXP (XEXP (op0, 0), 0);
10450 code = (code == LT ? EQ : NE);
10456 /* We used to optimize signed comparisons against zero, but that
10457 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10458 arrive here as equality comparisons, or (GEU, LTU) are
10459 optimized away. No need to special-case them. */
10461 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10462 (eq B (minus A C)), whichever simplifies. We can only do
10463 this for equality comparisons due to pathological cases involving
10465 if (equality_comparison_p
10466 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10467 XEXP (op0, 1), op1)))
10469 op0 = XEXP (op0, 0);
10474 if (equality_comparison_p
10475 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10476 XEXP (op0, 0), op1)))
10478 op0 = XEXP (op0, 1);
10483 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10484 of bits in X minus 1, is one iff X > 0. */
10485 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10486 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10487 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10488 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10490 op0 = XEXP (op0, 1);
10491 code = (code == GE ? LE : GT);
10497 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10498 if C is zero or B is a constant. */
10499 if (equality_comparison_p
10500 && 0 != (tem = simplify_binary_operation (XOR, mode,
10501 XEXP (op0, 1), op1)))
10503 op0 = XEXP (op0, 0);
10510 case UNEQ: case LTGT:
10511 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10512 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10513 case UNORDERED: case ORDERED:
10514 /* We can't do anything if OP0 is a condition code value, rather
10515 than an actual data value. */
10518 || XEXP (op0, 0) == cc0_rtx
10520 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10523 /* Get the two operands being compared. */
10524 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10525 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10527 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10529 /* Check for the cases where we simply want the result of the
10530 earlier test or the opposite of that result. */
10531 if (code == NE || code == EQ
10532 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10533 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10534 && (STORE_FLAG_VALUE
10535 & (((HOST_WIDE_INT) 1
10536 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10537 && (code == LT || code == GE)))
10539 enum rtx_code new_code;
10540 if (code == LT || code == NE)
10541 new_code = GET_CODE (op0);
10543 new_code = combine_reversed_comparison_code (op0);
10545 if (new_code != UNKNOWN)
10556 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10558 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10559 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10560 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10562 op0 = XEXP (op0, 1);
10563 code = (code == GE ? GT : LE);
10569 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10570 will be converted to a ZERO_EXTRACT later. */
10571 if (const_op == 0 && equality_comparison_p
10572 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10573 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10575 op0 = simplify_and_const_int
10576 (op0, mode, gen_rtx_LSHIFTRT (mode,
10578 XEXP (XEXP (op0, 0), 1)),
10579 (HOST_WIDE_INT) 1);
10583 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10584 zero and X is a comparison and C1 and C2 describe only bits set
10585 in STORE_FLAG_VALUE, we can compare with X. */
10586 if (const_op == 0 && equality_comparison_p
10587 && mode_width <= HOST_BITS_PER_WIDE_INT
10588 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10589 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10590 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10591 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10592 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10594 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10595 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10596 if ((~STORE_FLAG_VALUE & mask) == 0
10597 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10598 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10599 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10601 op0 = XEXP (XEXP (op0, 0), 0);
10606 /* If we are doing an equality comparison of an AND of a bit equal
10607 to the sign bit, replace this with a LT or GE comparison of
10608 the underlying value. */
10609 if (equality_comparison_p
10611 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10612 && mode_width <= HOST_BITS_PER_WIDE_INT
10613 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10614 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10616 op0 = XEXP (op0, 0);
10617 code = (code == EQ ? GE : LT);
10621 /* If this AND operation is really a ZERO_EXTEND from a narrower
10622 mode, the constant fits within that mode, and this is either an
10623 equality or unsigned comparison, try to do this comparison in
10624 the narrower mode. */
10625 if ((equality_comparison_p || unsigned_comparison_p)
10626 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10627 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10628 & GET_MODE_MASK (mode))
10630 && const_op >> i == 0
10631 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10633 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10637 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10638 in both M1 and M2 and the SUBREG is either paradoxical or
10639 represents the low part, permute the SUBREG and the AND and
10641 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10643 #ifdef WORD_REGISTER_OPERATIONS
10645 > (GET_MODE_BITSIZE
10646 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10647 && mode_width <= BITS_PER_WORD)
10650 <= (GET_MODE_BITSIZE
10651 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10652 && subreg_lowpart_p (XEXP (op0, 0))))
10653 #ifndef WORD_REGISTER_OPERATIONS
10654 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10655 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10656 As originally written the upper bits have a defined value
10657 due to the AND operation. However, if we commute the AND
10658 inside the SUBREG then they no longer have defined values
10659 and the meaning of the code has been changed. */
10660 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10661 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10663 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10664 && mode_width <= HOST_BITS_PER_WIDE_INT
10665 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10666 <= HOST_BITS_PER_WIDE_INT)
10667 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10668 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10669 & INTVAL (XEXP (op0, 1)))
10670 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10671 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10672 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10676 = gen_lowpart_for_combine
10678 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10679 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10683 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10684 (eq (and (lshiftrt X) 1) 0). */
10685 if (const_op == 0 && equality_comparison_p
10686 && XEXP (op0, 1) == const1_rtx
10687 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10688 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10690 op0 = simplify_and_const_int
10692 gen_rtx_LSHIFTRT (mode, XEXP (XEXP (XEXP (op0, 0), 0), 0),
10693 XEXP (XEXP (op0, 0), 1)),
10694 (HOST_WIDE_INT) 1);
10695 code = (code == NE ? EQ : NE);
10701 /* If we have (compare (ashift FOO N) (const_int C)) and
10702 the high order N bits of FOO (N+1 if an inequality comparison)
10703 are known to be zero, we can do this by comparing FOO with C
10704 shifted right N bits so long as the low-order N bits of C are
10706 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10707 && INTVAL (XEXP (op0, 1)) >= 0
10708 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10709 < HOST_BITS_PER_WIDE_INT)
10711 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10712 && mode_width <= HOST_BITS_PER_WIDE_INT
10713 && (nonzero_bits (XEXP (op0, 0), mode)
10714 & ~(mask >> (INTVAL (XEXP (op0, 1))
10715 + ! equality_comparison_p))) == 0)
10717 /* We must perform a logical shift, not an arithmetic one,
10718 as we want the top N bits of C to be zero. */
10719 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10721 temp >>= INTVAL (XEXP (op0, 1));
10722 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10723 op0 = XEXP (op0, 0);
10727 /* If we are doing a sign bit comparison, it means we are testing
10728 a particular bit. Convert it to the appropriate AND. */
10729 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10730 && mode_width <= HOST_BITS_PER_WIDE_INT)
10732 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10735 - INTVAL (XEXP (op0, 1)))));
10736 code = (code == LT ? NE : EQ);
10740 /* If this an equality comparison with zero and we are shifting
10741 the low bit to the sign bit, we can convert this to an AND of the
10743 if (const_op == 0 && equality_comparison_p
10744 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10745 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10747 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10748 (HOST_WIDE_INT) 1);
10754 /* If this is an equality comparison with zero, we can do this
10755 as a logical shift, which might be much simpler. */
10756 if (equality_comparison_p && const_op == 0
10757 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10759 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10761 INTVAL (XEXP (op0, 1)));
10765 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10766 do the comparison in a narrower mode. */
10767 if (! unsigned_comparison_p
10768 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10769 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10770 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10771 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10772 MODE_INT, 1)) != BLKmode
10773 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10774 || ((unsigned HOST_WIDE_INT) -const_op
10775 <= GET_MODE_MASK (tmode))))
10777 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10781 /* Likewise if OP0 is a PLUS of a sign extension with a
10782 constant, which is usually represented with the PLUS
10783 between the shifts. */
10784 if (! unsigned_comparison_p
10785 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10786 && GET_CODE (XEXP (op0, 0)) == PLUS
10787 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10788 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10789 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10790 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10791 MODE_INT, 1)) != BLKmode
10792 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10793 || ((unsigned HOST_WIDE_INT) -const_op
10794 <= GET_MODE_MASK (tmode))))
10796 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10797 rtx add_const = XEXP (XEXP (op0, 0), 1);
10798 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10801 op0 = gen_binary (PLUS, tmode,
10802 gen_lowpart_for_combine (tmode, inner),
10807 /* ... fall through ... */
10809 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10810 the low order N bits of FOO are known to be zero, we can do this
10811 by comparing FOO with C shifted left N bits so long as no
10812 overflow occurs. */
10813 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10814 && INTVAL (XEXP (op0, 1)) >= 0
10815 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10816 && mode_width <= HOST_BITS_PER_WIDE_INT
10817 && (nonzero_bits (XEXP (op0, 0), mode)
10818 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10820 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10823 const_op <<= INTVAL (XEXP (op0, 1));
10824 op1 = GEN_INT (const_op);
10825 op0 = XEXP (op0, 0);
10829 /* If we are using this shift to extract just the sign bit, we
10830 can replace this with an LT or GE comparison. */
10832 && (equality_comparison_p || sign_bit_comparison_p)
10833 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10834 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10836 op0 = XEXP (op0, 0);
10837 code = (code == NE || code == GT ? LT : GE);
10849 /* Now make any compound operations involved in this comparison. Then,
10850 check for an outmost SUBREG on OP0 that is not doing anything or is
10851 paradoxical. The latter case can only occur when it is known that the
10852 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10853 We can never remove a SUBREG for a non-equality comparison because the
10854 sign bit is in a different place in the underlying object. */
10856 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10857 op1 = make_compound_operation (op1, SET);
10859 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10860 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10861 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10862 && (code == NE || code == EQ)
10863 && ((GET_MODE_SIZE (GET_MODE (op0))
10864 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10866 op0 = SUBREG_REG (op0);
10867 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10870 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10871 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10872 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10873 && (code == NE || code == EQ)
10874 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10875 <= HOST_BITS_PER_WIDE_INT)
10876 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10877 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
10878 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10880 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10881 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
10882 op0 = SUBREG_REG (op0), op1 = tem;
10884 /* We now do the opposite procedure: Some machines don't have compare
10885 insns in all modes. If OP0's mode is an integer mode smaller than a
10886 word and we can't do a compare in that mode, see if there is a larger
10887 mode for which we can do the compare. There are a number of cases in
10888 which we can use the wider mode. */
10890 mode = GET_MODE (op0);
10891 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10892 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10893 && ! have_insn_for (COMPARE, mode))
10894 for (tmode = GET_MODE_WIDER_MODE (mode);
10896 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10897 tmode = GET_MODE_WIDER_MODE (tmode))
10898 if (have_insn_for (COMPARE, tmode))
10900 /* If the only nonzero bits in OP0 and OP1 are those in the
10901 narrower mode and this is an equality or unsigned comparison,
10902 we can use the wider mode. Similarly for sign-extended
10903 values, in which case it is true for all comparisons. */
10904 if (((code == EQ || code == NE
10905 || code == GEU || code == GTU || code == LEU || code == LTU)
10906 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
10907 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
10908 || ((num_sign_bit_copies (op0, tmode)
10909 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10910 && (num_sign_bit_copies (op1, tmode)
10911 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10913 /* If OP0 is an AND and we don't have an AND in MODE either,
10914 make a new AND in the proper mode. */
10915 if (GET_CODE (op0) == AND
10916 && !have_insn_for (AND, mode))
10917 op0 = gen_binary (AND, tmode,
10918 gen_lowpart_for_combine (tmode,
10920 gen_lowpart_for_combine (tmode,
10923 op0 = gen_lowpart_for_combine (tmode, op0);
10924 op1 = gen_lowpart_for_combine (tmode, op1);
10928 /* If this is a test for negative, we can make an explicit
10929 test of the sign bit. */
10931 if (op1 == const0_rtx && (code == LT || code == GE)
10932 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10934 op0 = gen_binary (AND, tmode,
10935 gen_lowpart_for_combine (tmode, op0),
10936 GEN_INT ((HOST_WIDE_INT) 1
10937 << (GET_MODE_BITSIZE (mode) - 1)));
10938 code = (code == LT) ? NE : EQ;
10943 #ifdef CANONICALIZE_COMPARISON
10944 /* If this machine only supports a subset of valid comparisons, see if we
10945 can convert an unsupported one into a supported one. */
10946 CANONICALIZE_COMPARISON (code, op0, op1);
10955 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10956 searching backward. */
10957 static enum rtx_code
10958 combine_reversed_comparison_code (exp)
10961 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10964 if (code1 != UNKNOWN
10965 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10967 /* Otherwise try and find where the condition codes were last set and
10969 x = get_last_value (XEXP (exp, 0));
10970 if (!x || GET_CODE (x) != COMPARE)
10972 return reversed_comparison_code_parts (GET_CODE (exp),
10973 XEXP (x, 0), XEXP (x, 1), NULL);
10975 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10976 Return NULL_RTX in case we fail to do the reversal. */
10978 reversed_comparison (exp, mode, op0, op1)
10980 enum machine_mode mode;
10982 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10983 if (reversed_code == UNKNOWN)
10986 return gen_binary (reversed_code, mode, op0, op1);
10989 /* Utility function for following routine. Called when X is part of a value
10990 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10991 for each register mentioned. Similar to mention_regs in cse.c */
10994 update_table_tick (x)
10997 enum rtx_code code = GET_CODE (x);
10998 const char *fmt = GET_RTX_FORMAT (code);
11003 unsigned int regno = REGNO (x);
11004 unsigned int endregno
11005 = regno + (regno < FIRST_PSEUDO_REGISTER
11006 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11009 for (r = regno; r < endregno; r++)
11010 reg_last_set_table_tick[r] = label_tick;
11015 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11016 /* Note that we can't have an "E" in values stored; see
11017 get_last_value_validate. */
11019 update_table_tick (XEXP (x, i));
11022 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11023 are saying that the register is clobbered and we no longer know its
11024 value. If INSN is zero, don't update reg_last_set; this is only permitted
11025 with VALUE also zero and is used to invalidate the register. */
11028 record_value_for_reg (reg, insn, value)
11033 unsigned int regno = REGNO (reg);
11034 unsigned int endregno
11035 = regno + (regno < FIRST_PSEUDO_REGISTER
11036 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11039 /* If VALUE contains REG and we have a previous value for REG, substitute
11040 the previous value. */
11041 if (value && insn && reg_overlap_mentioned_p (reg, value))
11045 /* Set things up so get_last_value is allowed to see anything set up to
11047 subst_low_cuid = INSN_CUID (insn);
11048 tem = get_last_value (reg);
11050 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11051 it isn't going to be useful and will take a lot of time to process,
11052 so just use the CLOBBER. */
11056 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11057 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11058 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11059 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11060 tem = XEXP (tem, 0);
11062 value = replace_rtx (copy_rtx (value), reg, tem);
11066 /* For each register modified, show we don't know its value, that
11067 we don't know about its bitwise content, that its value has been
11068 updated, and that we don't know the location of the death of the
11070 for (i = regno; i < endregno; i++)
11073 reg_last_set[i] = insn;
11075 reg_last_set_value[i] = 0;
11076 reg_last_set_mode[i] = 0;
11077 reg_last_set_nonzero_bits[i] = 0;
11078 reg_last_set_sign_bit_copies[i] = 0;
11079 reg_last_death[i] = 0;
11082 /* Mark registers that are being referenced in this value. */
11084 update_table_tick (value);
11086 /* Now update the status of each register being set.
11087 If someone is using this register in this block, set this register
11088 to invalid since we will get confused between the two lives in this
11089 basic block. This makes using this register always invalid. In cse, we
11090 scan the table to invalidate all entries using this register, but this
11091 is too much work for us. */
11093 for (i = regno; i < endregno; i++)
11095 reg_last_set_label[i] = label_tick;
11096 if (value && reg_last_set_table_tick[i] == label_tick)
11097 reg_last_set_invalid[i] = 1;
11099 reg_last_set_invalid[i] = 0;
11102 /* The value being assigned might refer to X (like in "x++;"). In that
11103 case, we must replace it with (clobber (const_int 0)) to prevent
11105 if (value && ! get_last_value_validate (&value, insn,
11106 reg_last_set_label[regno], 0))
11108 value = copy_rtx (value);
11109 if (! get_last_value_validate (&value, insn,
11110 reg_last_set_label[regno], 1))
11114 /* For the main register being modified, update the value, the mode, the
11115 nonzero bits, and the number of sign bit copies. */
11117 reg_last_set_value[regno] = value;
11121 subst_low_cuid = INSN_CUID (insn);
11122 reg_last_set_mode[regno] = GET_MODE (reg);
11123 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11124 reg_last_set_sign_bit_copies[regno]
11125 = num_sign_bit_copies (value, GET_MODE (reg));
11129 /* Called via note_stores from record_dead_and_set_regs to handle one
11130 SET or CLOBBER in an insn. DATA is the instruction in which the
11131 set is occurring. */
11134 record_dead_and_set_regs_1 (dest, setter, data)
11138 rtx record_dead_insn = (rtx) data;
11140 if (GET_CODE (dest) == SUBREG)
11141 dest = SUBREG_REG (dest);
11143 if (GET_CODE (dest) == REG)
11145 /* If we are setting the whole register, we know its value. Otherwise
11146 show that we don't know the value. We can handle SUBREG in
11148 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11149 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11150 else if (GET_CODE (setter) == SET
11151 && GET_CODE (SET_DEST (setter)) == SUBREG
11152 && SUBREG_REG (SET_DEST (setter)) == dest
11153 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11154 && subreg_lowpart_p (SET_DEST (setter)))
11155 record_value_for_reg (dest, record_dead_insn,
11156 gen_lowpart_for_combine (GET_MODE (dest),
11157 SET_SRC (setter)));
11159 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11161 else if (GET_CODE (dest) == MEM
11162 /* Ignore pushes, they clobber nothing. */
11163 && ! push_operand (dest, GET_MODE (dest)))
11164 mem_last_set = INSN_CUID (record_dead_insn);
11167 /* Update the records of when each REG was most recently set or killed
11168 for the things done by INSN. This is the last thing done in processing
11169 INSN in the combiner loop.
11171 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11172 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11173 and also the similar information mem_last_set (which insn most recently
11174 modified memory) and last_call_cuid (which insn was the most recent
11175 subroutine call). */
11178 record_dead_and_set_regs (insn)
11184 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11186 if (REG_NOTE_KIND (link) == REG_DEAD
11187 && GET_CODE (XEXP (link, 0)) == REG)
11189 unsigned int regno = REGNO (XEXP (link, 0));
11190 unsigned int endregno
11191 = regno + (regno < FIRST_PSEUDO_REGISTER
11192 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11195 for (i = regno; i < endregno; i++)
11196 reg_last_death[i] = insn;
11198 else if (REG_NOTE_KIND (link) == REG_INC)
11199 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11202 if (GET_CODE (insn) == CALL_INSN)
11204 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11205 if (call_used_regs[i])
11207 reg_last_set_value[i] = 0;
11208 reg_last_set_mode[i] = 0;
11209 reg_last_set_nonzero_bits[i] = 0;
11210 reg_last_set_sign_bit_copies[i] = 0;
11211 reg_last_death[i] = 0;
11214 last_call_cuid = mem_last_set = INSN_CUID (insn);
11217 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11220 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11221 register present in the SUBREG, so for each such SUBREG go back and
11222 adjust nonzero and sign bit information of the registers that are
11223 known to have some zero/sign bits set.
11225 This is needed because when combine blows the SUBREGs away, the
11226 information on zero/sign bits is lost and further combines can be
11227 missed because of that. */
11230 record_promoted_value (insn, subreg)
11235 unsigned int regno = REGNO (SUBREG_REG (subreg));
11236 enum machine_mode mode = GET_MODE (subreg);
11238 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11241 for (links = LOG_LINKS (insn); links;)
11243 insn = XEXP (links, 0);
11244 set = single_set (insn);
11246 if (! set || GET_CODE (SET_DEST (set)) != REG
11247 || REGNO (SET_DEST (set)) != regno
11248 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11250 links = XEXP (links, 1);
11254 if (reg_last_set[regno] == insn)
11256 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11257 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11260 if (GET_CODE (SET_SRC (set)) == REG)
11262 regno = REGNO (SET_SRC (set));
11263 links = LOG_LINKS (insn);
11270 /* Scan X for promoted SUBREGs. For each one found,
11271 note what it implies to the registers used in it. */
11274 check_promoted_subreg (insn, x)
11278 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11279 && GET_CODE (SUBREG_REG (x)) == REG)
11280 record_promoted_value (insn, x);
11283 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11286 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11290 check_promoted_subreg (insn, XEXP (x, i));
11294 if (XVEC (x, i) != 0)
11295 for (j = 0; j < XVECLEN (x, i); j++)
11296 check_promoted_subreg (insn, XVECEXP (x, i, j));
11302 /* Utility routine for the following function. Verify that all the registers
11303 mentioned in *LOC are valid when *LOC was part of a value set when
11304 label_tick == TICK. Return 0 if some are not.
11306 If REPLACE is non-zero, replace the invalid reference with
11307 (clobber (const_int 0)) and return 1. This replacement is useful because
11308 we often can get useful information about the form of a value (e.g., if
11309 it was produced by a shift that always produces -1 or 0) even though
11310 we don't know exactly what registers it was produced from. */
11313 get_last_value_validate (loc, insn, tick, replace)
11320 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11321 int len = GET_RTX_LENGTH (GET_CODE (x));
11324 if (GET_CODE (x) == REG)
11326 unsigned int regno = REGNO (x);
11327 unsigned int endregno
11328 = regno + (regno < FIRST_PSEUDO_REGISTER
11329 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11332 for (j = regno; j < endregno; j++)
11333 if (reg_last_set_invalid[j]
11334 /* If this is a pseudo-register that was only set once and not
11335 live at the beginning of the function, it is always valid. */
11336 || (! (regno >= FIRST_PSEUDO_REGISTER
11337 && REG_N_SETS (regno) == 1
11338 && (! REGNO_REG_SET_P
11339 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11340 && reg_last_set_label[j] > tick))
11343 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11349 /* If this is a memory reference, make sure that there were
11350 no stores after it that might have clobbered the value. We don't
11351 have alias info, so we assume any store invalidates it. */
11352 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11353 && INSN_CUID (insn) <= mem_last_set)
11356 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11360 for (i = 0; i < len; i++)
11362 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11363 /* Don't bother with these. They shouldn't occur anyway. */
11367 /* If we haven't found a reason for it to be invalid, it is valid. */
11371 /* Get the last value assigned to X, if known. Some registers
11372 in the value may be replaced with (clobber (const_int 0)) if their value
11373 is known longer known reliably. */
11379 unsigned int regno;
11382 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11383 then convert it to the desired mode. If this is a paradoxical SUBREG,
11384 we cannot predict what values the "extra" bits might have. */
11385 if (GET_CODE (x) == SUBREG
11386 && subreg_lowpart_p (x)
11387 && (GET_MODE_SIZE (GET_MODE (x))
11388 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11389 && (value = get_last_value (SUBREG_REG (x))) != 0)
11390 return gen_lowpart_for_combine (GET_MODE (x), value);
11392 if (GET_CODE (x) != REG)
11396 value = reg_last_set_value[regno];
11398 /* If we don't have a value, or if it isn't for this basic block and
11399 it's either a hard register, set more than once, or it's a live
11400 at the beginning of the function, return 0.
11402 Because if it's not live at the beginning of the function then the reg
11403 is always set before being used (is never used without being set).
11404 And, if it's set only once, and it's always set before use, then all
11405 uses must have the same last value, even if it's not from this basic
11409 || (reg_last_set_label[regno] != label_tick
11410 && (regno < FIRST_PSEUDO_REGISTER
11411 || REG_N_SETS (regno) != 1
11412 || (REGNO_REG_SET_P
11413 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11416 /* If the value was set in a later insn than the ones we are processing,
11417 we can't use it even if the register was only set once. */
11418 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11421 /* If the value has all its registers valid, return it. */
11422 if (get_last_value_validate (&value, reg_last_set[regno],
11423 reg_last_set_label[regno], 0))
11426 /* Otherwise, make a copy and replace any invalid register with
11427 (clobber (const_int 0)). If that fails for some reason, return 0. */
11429 value = copy_rtx (value);
11430 if (get_last_value_validate (&value, reg_last_set[regno],
11431 reg_last_set_label[regno], 1))
11437 /* Return nonzero if expression X refers to a REG or to memory
11438 that is set in an instruction more recent than FROM_CUID. */
11441 use_crosses_set_p (x, from_cuid)
11447 enum rtx_code code = GET_CODE (x);
11451 unsigned int regno = REGNO (x);
11452 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11453 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11455 #ifdef PUSH_ROUNDING
11456 /* Don't allow uses of the stack pointer to be moved,
11457 because we don't know whether the move crosses a push insn. */
11458 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11461 for (; regno < endreg; regno++)
11462 if (reg_last_set[regno]
11463 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11468 if (code == MEM && mem_last_set > from_cuid)
11471 fmt = GET_RTX_FORMAT (code);
11473 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11478 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11479 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11482 else if (fmt[i] == 'e'
11483 && use_crosses_set_p (XEXP (x, i), from_cuid))
11489 /* Define three variables used for communication between the following
11492 static unsigned int reg_dead_regno, reg_dead_endregno;
11493 static int reg_dead_flag;
11495 /* Function called via note_stores from reg_dead_at_p.
11497 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11498 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11501 reg_dead_at_p_1 (dest, x, data)
11504 void *data ATTRIBUTE_UNUSED;
11506 unsigned int regno, endregno;
11508 if (GET_CODE (dest) != REG)
11511 regno = REGNO (dest);
11512 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11513 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11515 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11516 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11519 /* Return non-zero if REG is known to be dead at INSN.
11521 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11522 referencing REG, it is dead. If we hit a SET referencing REG, it is
11523 live. Otherwise, see if it is live or dead at the start of the basic
11524 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11525 must be assumed to be always live. */
11528 reg_dead_at_p (reg, insn)
11535 /* Set variables for reg_dead_at_p_1. */
11536 reg_dead_regno = REGNO (reg);
11537 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11538 ? HARD_REGNO_NREGS (reg_dead_regno,
11544 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11545 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11547 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11548 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11552 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11553 beginning of function. */
11554 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11555 insn = prev_nonnote_insn (insn))
11557 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11559 return reg_dead_flag == 1 ? 1 : 0;
11561 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11565 /* Get the basic block number that we were in. */
11570 for (block = 0; block < n_basic_blocks; block++)
11571 if (insn == BLOCK_HEAD (block))
11574 if (block == n_basic_blocks)
11578 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11579 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11585 /* Note hard registers in X that are used. This code is similar to
11586 that in flow.c, but much simpler since we don't care about pseudos. */
11589 mark_used_regs_combine (x)
11592 RTX_CODE code = GET_CODE (x);
11593 unsigned int regno;
11605 case ADDR_DIFF_VEC:
11608 /* CC0 must die in the insn after it is set, so we don't need to take
11609 special note of it here. */
11615 /* If we are clobbering a MEM, mark any hard registers inside the
11616 address as used. */
11617 if (GET_CODE (XEXP (x, 0)) == MEM)
11618 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11623 /* A hard reg in a wide mode may really be multiple registers.
11624 If so, mark all of them just like the first. */
11625 if (regno < FIRST_PSEUDO_REGISTER)
11627 unsigned int endregno, r;
11629 /* None of this applies to the stack, frame or arg pointers */
11630 if (regno == STACK_POINTER_REGNUM
11631 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11632 || regno == HARD_FRAME_POINTER_REGNUM
11634 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11635 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11637 || regno == FRAME_POINTER_REGNUM)
11640 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11641 for (r = regno; r < endregno; r++)
11642 SET_HARD_REG_BIT (newpat_used_regs, r);
11648 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11650 rtx testreg = SET_DEST (x);
11652 while (GET_CODE (testreg) == SUBREG
11653 || GET_CODE (testreg) == ZERO_EXTRACT
11654 || GET_CODE (testreg) == SIGN_EXTRACT
11655 || GET_CODE (testreg) == STRICT_LOW_PART)
11656 testreg = XEXP (testreg, 0);
11658 if (GET_CODE (testreg) == MEM)
11659 mark_used_regs_combine (XEXP (testreg, 0));
11661 mark_used_regs_combine (SET_SRC (x));
11669 /* Recursively scan the operands of this expression. */
11672 const char *fmt = GET_RTX_FORMAT (code);
11674 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11677 mark_used_regs_combine (XEXP (x, i));
11678 else if (fmt[i] == 'E')
11682 for (j = 0; j < XVECLEN (x, i); j++)
11683 mark_used_regs_combine (XVECEXP (x, i, j));
11689 /* Remove register number REGNO from the dead registers list of INSN.
11691 Return the note used to record the death, if there was one. */
11694 remove_death (regno, insn)
11695 unsigned int regno;
11698 rtx note = find_regno_note (insn, REG_DEAD, regno);
11702 REG_N_DEATHS (regno)--;
11703 remove_note (insn, note);
11709 /* For each register (hardware or pseudo) used within expression X, if its
11710 death is in an instruction with cuid between FROM_CUID (inclusive) and
11711 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11712 list headed by PNOTES.
11714 That said, don't move registers killed by maybe_kill_insn.
11716 This is done when X is being merged by combination into TO_INSN. These
11717 notes will then be distributed as needed. */
11720 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11722 rtx maybe_kill_insn;
11729 enum rtx_code code = GET_CODE (x);
11733 unsigned int regno = REGNO (x);
11734 rtx where_dead = reg_last_death[regno];
11735 rtx before_dead, after_dead;
11737 /* Don't move the register if it gets killed in between from and to */
11738 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11739 && ! reg_referenced_p (x, maybe_kill_insn))
11742 /* WHERE_DEAD could be a USE insn made by combine, so first we
11743 make sure that we have insns with valid INSN_CUID values. */
11744 before_dead = where_dead;
11745 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11746 before_dead = PREV_INSN (before_dead);
11748 after_dead = where_dead;
11749 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11750 after_dead = NEXT_INSN (after_dead);
11752 if (before_dead && after_dead
11753 && INSN_CUID (before_dead) >= from_cuid
11754 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11755 || (where_dead != after_dead
11756 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11758 rtx note = remove_death (regno, where_dead);
11760 /* It is possible for the call above to return 0. This can occur
11761 when reg_last_death points to I2 or I1 that we combined with.
11762 In that case make a new note.
11764 We must also check for the case where X is a hard register
11765 and NOTE is a death note for a range of hard registers
11766 including X. In that case, we must put REG_DEAD notes for
11767 the remaining registers in place of NOTE. */
11769 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11770 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11771 > GET_MODE_SIZE (GET_MODE (x))))
11773 unsigned int deadregno = REGNO (XEXP (note, 0));
11774 unsigned int deadend
11775 = (deadregno + HARD_REGNO_NREGS (deadregno,
11776 GET_MODE (XEXP (note, 0))));
11777 unsigned int ourend
11778 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11781 for (i = deadregno; i < deadend; i++)
11782 if (i < regno || i >= ourend)
11783 REG_NOTES (where_dead)
11784 = gen_rtx_EXPR_LIST (REG_DEAD,
11785 gen_rtx_REG (reg_raw_mode[i], i),
11786 REG_NOTES (where_dead));
11789 /* If we didn't find any note, or if we found a REG_DEAD note that
11790 covers only part of the given reg, and we have a multi-reg hard
11791 register, then to be safe we must check for REG_DEAD notes
11792 for each register other than the first. They could have
11793 their own REG_DEAD notes lying around. */
11794 else if ((note == 0
11796 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11797 < GET_MODE_SIZE (GET_MODE (x)))))
11798 && regno < FIRST_PSEUDO_REGISTER
11799 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11801 unsigned int ourend
11802 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11803 unsigned int i, offset;
11807 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11811 for (i = regno + offset; i < ourend; i++)
11812 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11813 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11816 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11818 XEXP (note, 1) = *pnotes;
11822 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11824 REG_N_DEATHS (regno)++;
11830 else if (GET_CODE (x) == SET)
11832 rtx dest = SET_DEST (x);
11834 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11836 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11837 that accesses one word of a multi-word item, some
11838 piece of everything register in the expression is used by
11839 this insn, so remove any old death. */
11840 /* ??? So why do we test for equality of the sizes? */
11842 if (GET_CODE (dest) == ZERO_EXTRACT
11843 || GET_CODE (dest) == STRICT_LOW_PART
11844 || (GET_CODE (dest) == SUBREG
11845 && (((GET_MODE_SIZE (GET_MODE (dest))
11846 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11847 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11848 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11850 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11854 /* If this is some other SUBREG, we know it replaces the entire
11855 value, so use that as the destination. */
11856 if (GET_CODE (dest) == SUBREG)
11857 dest = SUBREG_REG (dest);
11859 /* If this is a MEM, adjust deaths of anything used in the address.
11860 For a REG (the only other possibility), the entire value is
11861 being replaced so the old value is not used in this insn. */
11863 if (GET_CODE (dest) == MEM)
11864 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11869 else if (GET_CODE (x) == CLOBBER)
11872 len = GET_RTX_LENGTH (code);
11873 fmt = GET_RTX_FORMAT (code);
11875 for (i = 0; i < len; i++)
11880 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11881 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11884 else if (fmt[i] == 'e')
11885 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11889 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11890 pattern of an insn. X must be a REG. */
11893 reg_bitfield_target_p (x, body)
11899 if (GET_CODE (body) == SET)
11901 rtx dest = SET_DEST (body);
11903 unsigned int regno, tregno, endregno, endtregno;
11905 if (GET_CODE (dest) == ZERO_EXTRACT)
11906 target = XEXP (dest, 0);
11907 else if (GET_CODE (dest) == STRICT_LOW_PART)
11908 target = SUBREG_REG (XEXP (dest, 0));
11912 if (GET_CODE (target) == SUBREG)
11913 target = SUBREG_REG (target);
11915 if (GET_CODE (target) != REG)
11918 tregno = REGNO (target), regno = REGNO (x);
11919 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11920 return target == x;
11922 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11923 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11925 return endregno > tregno && regno < endtregno;
11928 else if (GET_CODE (body) == PARALLEL)
11929 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11930 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11936 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11937 as appropriate. I3 and I2 are the insns resulting from the combination
11938 insns including FROM (I2 may be zero).
11940 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11941 not need REG_DEAD notes because they are being substituted for. This
11942 saves searching in the most common cases.
11944 Each note in the list is either ignored or placed on some insns, depending
11945 on the type of note. */
11948 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11952 rtx elim_i2, elim_i1;
11954 rtx note, next_note;
11957 for (note = notes; note; note = next_note)
11959 rtx place = 0, place2 = 0;
11961 /* If this NOTE references a pseudo register, ensure it references
11962 the latest copy of that register. */
11963 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11964 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11965 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11967 next_note = XEXP (note, 1);
11968 switch (REG_NOTE_KIND (note))
11972 case REG_EXEC_COUNT:
11973 /* Doesn't matter much where we put this, as long as it's somewhere.
11974 It is preferable to keep these notes on branches, which is most
11975 likely to be i3. */
11979 case REG_VTABLE_REF:
11980 /* ??? Should remain with *a particular* memory load. Given the
11981 nature of vtable data, the last insn seems relatively safe. */
11985 case REG_NON_LOCAL_GOTO:
11986 if (GET_CODE (i3) == JUMP_INSN)
11988 else if (i2 && GET_CODE (i2) == JUMP_INSN)
11994 case REG_EH_REGION:
11995 /* These notes must remain with the call or trapping instruction. */
11996 if (GET_CODE (i3) == CALL_INSN)
11998 else if (i2 && GET_CODE (i2) == CALL_INSN)
12000 else if (flag_non_call_exceptions)
12002 if (may_trap_p (i3))
12004 else if (i2 && may_trap_p (i2))
12006 /* ??? Otherwise assume we've combined things such that we
12007 can now prove that the instructions can't trap. Drop the
12008 note in this case. */
12016 /* These notes must remain with the call. It should not be
12017 possible for both I2 and I3 to be a call. */
12018 if (GET_CODE (i3) == CALL_INSN)
12020 else if (i2 && GET_CODE (i2) == CALL_INSN)
12027 /* Any clobbers for i3 may still exist, and so we must process
12028 REG_UNUSED notes from that insn.
12030 Any clobbers from i2 or i1 can only exist if they were added by
12031 recog_for_combine. In that case, recog_for_combine created the
12032 necessary REG_UNUSED notes. Trying to keep any original
12033 REG_UNUSED notes from these insns can cause incorrect output
12034 if it is for the same register as the original i3 dest.
12035 In that case, we will notice that the register is set in i3,
12036 and then add a REG_UNUSED note for the destination of i3, which
12037 is wrong. However, it is possible to have REG_UNUSED notes from
12038 i2 or i1 for register which were both used and clobbered, so
12039 we keep notes from i2 or i1 if they will turn into REG_DEAD
12042 /* If this register is set or clobbered in I3, put the note there
12043 unless there is one already. */
12044 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12046 if (from_insn != i3)
12049 if (! (GET_CODE (XEXP (note, 0)) == REG
12050 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12051 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12054 /* Otherwise, if this register is used by I3, then this register
12055 now dies here, so we must put a REG_DEAD note here unless there
12057 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12058 && ! (GET_CODE (XEXP (note, 0)) == REG
12059 ? find_regno_note (i3, REG_DEAD,
12060 REGNO (XEXP (note, 0)))
12061 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12063 PUT_REG_NOTE_KIND (note, REG_DEAD);
12071 /* These notes say something about results of an insn. We can
12072 only support them if they used to be on I3 in which case they
12073 remain on I3. Otherwise they are ignored.
12075 If the note refers to an expression that is not a constant, we
12076 must also ignore the note since we cannot tell whether the
12077 equivalence is still true. It might be possible to do
12078 slightly better than this (we only have a problem if I2DEST
12079 or I1DEST is present in the expression), but it doesn't
12080 seem worth the trouble. */
12082 if (from_insn == i3
12083 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12088 case REG_NO_CONFLICT:
12089 /* These notes say something about how a register is used. They must
12090 be present on any use of the register in I2 or I3. */
12091 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12094 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12104 /* This can show up in several ways -- either directly in the
12105 pattern, or hidden off in the constant pool with (or without?)
12106 a REG_EQUAL note. */
12107 /* ??? Ignore the without-reg_equal-note problem for now. */
12108 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12109 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12110 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12111 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12115 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12116 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12117 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12118 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12129 /* These notes say something about the value of a register prior
12130 to the execution of an insn. It is too much trouble to see
12131 if the note is still correct in all situations. It is better
12132 to simply delete it. */
12136 /* If the insn previously containing this note still exists,
12137 put it back where it was. Otherwise move it to the previous
12138 insn. Adjust the corresponding REG_LIBCALL note. */
12139 if (GET_CODE (from_insn) != NOTE)
12143 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12144 place = prev_real_insn (from_insn);
12146 XEXP (tem, 0) = place;
12147 /* If we're deleting the last remaining instruction of a
12148 libcall sequence, don't add the notes. */
12149 else if (XEXP (note, 0) == from_insn)
12155 /* This is handled similarly to REG_RETVAL. */
12156 if (GET_CODE (from_insn) != NOTE)
12160 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12161 place = next_real_insn (from_insn);
12163 XEXP (tem, 0) = place;
12164 /* If we're deleting the last remaining instruction of a
12165 libcall sequence, don't add the notes. */
12166 else if (XEXP (note, 0) == from_insn)
12172 /* If the register is used as an input in I3, it dies there.
12173 Similarly for I2, if it is non-zero and adjacent to I3.
12175 If the register is not used as an input in either I3 or I2
12176 and it is not one of the registers we were supposed to eliminate,
12177 there are two possibilities. We might have a non-adjacent I2
12178 or we might have somehow eliminated an additional register
12179 from a computation. For example, we might have had A & B where
12180 we discover that B will always be zero. In this case we will
12181 eliminate the reference to A.
12183 In both cases, we must search to see if we can find a previous
12184 use of A and put the death note there. */
12187 && GET_CODE (from_insn) == CALL_INSN
12188 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12190 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12192 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12193 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12196 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12197 || rtx_equal_p (XEXP (note, 0), elim_i1))
12202 basic_block bb = BASIC_BLOCK (this_basic_block);
12204 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12206 if (! INSN_P (tem))
12208 if (tem == bb->head)
12213 /* If the register is being set at TEM, see if that is all
12214 TEM is doing. If so, delete TEM. Otherwise, make this
12215 into a REG_UNUSED note instead. */
12216 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12218 rtx set = single_set (tem);
12219 rtx inner_dest = 0;
12221 rtx cc0_setter = NULL_RTX;
12225 for (inner_dest = SET_DEST (set);
12226 (GET_CODE (inner_dest) == STRICT_LOW_PART
12227 || GET_CODE (inner_dest) == SUBREG
12228 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12229 inner_dest = XEXP (inner_dest, 0))
12232 /* Verify that it was the set, and not a clobber that
12233 modified the register.
12235 CC0 targets must be careful to maintain setter/user
12236 pairs. If we cannot delete the setter due to side
12237 effects, mark the user with an UNUSED note instead
12240 if (set != 0 && ! side_effects_p (SET_SRC (set))
12241 && rtx_equal_p (XEXP (note, 0), inner_dest)
12243 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12244 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12245 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12249 /* Move the notes and links of TEM elsewhere.
12250 This might delete other dead insns recursively.
12251 First set the pattern to something that won't use
12254 PATTERN (tem) = pc_rtx;
12256 distribute_notes (REG_NOTES (tem), tem, tem,
12257 NULL_RTX, NULL_RTX, NULL_RTX);
12258 distribute_links (LOG_LINKS (tem));
12260 PUT_CODE (tem, NOTE);
12261 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12262 NOTE_SOURCE_FILE (tem) = 0;
12265 /* Delete the setter too. */
12268 PATTERN (cc0_setter) = pc_rtx;
12270 distribute_notes (REG_NOTES (cc0_setter),
12271 cc0_setter, cc0_setter,
12272 NULL_RTX, NULL_RTX, NULL_RTX);
12273 distribute_links (LOG_LINKS (cc0_setter));
12275 PUT_CODE (cc0_setter, NOTE);
12276 NOTE_LINE_NUMBER (cc0_setter)
12277 = NOTE_INSN_DELETED;
12278 NOTE_SOURCE_FILE (cc0_setter) = 0;
12282 /* If the register is both set and used here, put the
12283 REG_DEAD note here, but place a REG_UNUSED note
12284 here too unless there already is one. */
12285 else if (reg_referenced_p (XEXP (note, 0),
12290 if (! find_regno_note (tem, REG_UNUSED,
12291 REGNO (XEXP (note, 0))))
12293 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12298 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12300 /* If there isn't already a REG_UNUSED note, put one
12302 if (! find_regno_note (tem, REG_UNUSED,
12303 REGNO (XEXP (note, 0))))
12308 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12309 || (GET_CODE (tem) == CALL_INSN
12310 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12314 /* If we are doing a 3->2 combination, and we have a
12315 register which formerly died in i3 and was not used
12316 by i2, which now no longer dies in i3 and is used in
12317 i2 but does not die in i2, and place is between i2
12318 and i3, then we may need to move a link from place to
12320 if (i2 && INSN_UID (place) <= max_uid_cuid
12321 && INSN_CUID (place) > INSN_CUID (i2)
12323 && INSN_CUID (from_insn) > INSN_CUID (i2)
12324 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12326 rtx links = LOG_LINKS (place);
12327 LOG_LINKS (place) = 0;
12328 distribute_links (links);
12333 if (tem == bb->head)
12337 /* We haven't found an insn for the death note and it
12338 is still a REG_DEAD note, but we have hit the beginning
12339 of the block. If the existing life info says the reg
12340 was dead, there's nothing left to do. Otherwise, we'll
12341 need to do a global life update after combine. */
12342 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12343 && REGNO_REG_SET_P (bb->global_live_at_start,
12344 REGNO (XEXP (note, 0))))
12346 SET_BIT (refresh_blocks, this_basic_block);
12351 /* If the register is set or already dead at PLACE, we needn't do
12352 anything with this note if it is still a REG_DEAD note.
12353 We can here if it is set at all, not if is it totally replace,
12354 which is what `dead_or_set_p' checks, so also check for it being
12357 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12359 unsigned int regno = REGNO (XEXP (note, 0));
12361 /* Similarly, if the instruction on which we want to place
12362 the note is a noop, we'll need do a global live update
12363 after we remove them in delete_noop_moves. */
12364 if (noop_move_p (place))
12366 SET_BIT (refresh_blocks, this_basic_block);
12370 if (dead_or_set_p (place, XEXP (note, 0))
12371 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12373 /* Unless the register previously died in PLACE, clear
12374 reg_last_death. [I no longer understand why this is
12376 if (reg_last_death[regno] != place)
12377 reg_last_death[regno] = 0;
12381 reg_last_death[regno] = place;
12383 /* If this is a death note for a hard reg that is occupying
12384 multiple registers, ensure that we are still using all
12385 parts of the object. If we find a piece of the object
12386 that is unused, we must arrange for an appropriate REG_DEAD
12387 note to be added for it. However, we can't just emit a USE
12388 and tag the note to it, since the register might actually
12389 be dead; so we recourse, and the recursive call then finds
12390 the previous insn that used this register. */
12392 if (place && regno < FIRST_PSEUDO_REGISTER
12393 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12395 unsigned int endregno
12396 = regno + HARD_REGNO_NREGS (regno,
12397 GET_MODE (XEXP (note, 0)));
12401 for (i = regno; i < endregno; i++)
12402 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12403 && ! find_regno_fusage (place, USE, i))
12404 || dead_or_set_regno_p (place, i))
12409 /* Put only REG_DEAD notes for pieces that are
12410 not already dead or set. */
12412 for (i = regno; i < endregno;
12413 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12415 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12416 basic_block bb = BASIC_BLOCK (this_basic_block);
12418 if (! dead_or_set_p (place, piece)
12419 && ! reg_bitfield_target_p (piece,
12423 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12425 distribute_notes (new_note, place, place,
12426 NULL_RTX, NULL_RTX, NULL_RTX);
12428 else if (! refers_to_regno_p (i, i + 1,
12429 PATTERN (place), 0)
12430 && ! find_regno_fusage (place, USE, i))
12431 for (tem = PREV_INSN (place); ;
12432 tem = PREV_INSN (tem))
12434 if (! INSN_P (tem))
12436 if (tem == bb->head)
12438 SET_BIT (refresh_blocks,
12445 if (dead_or_set_p (tem, piece)
12446 || reg_bitfield_target_p (piece,
12450 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12465 /* Any other notes should not be present at this point in the
12472 XEXP (note, 1) = REG_NOTES (place);
12473 REG_NOTES (place) = note;
12475 else if ((REG_NOTE_KIND (note) == REG_DEAD
12476 || REG_NOTE_KIND (note) == REG_UNUSED)
12477 && GET_CODE (XEXP (note, 0)) == REG)
12478 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12482 if ((REG_NOTE_KIND (note) == REG_DEAD
12483 || REG_NOTE_KIND (note) == REG_UNUSED)
12484 && GET_CODE (XEXP (note, 0)) == REG)
12485 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12487 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12488 REG_NOTE_KIND (note),
12490 REG_NOTES (place2));
12495 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12496 I3, I2, and I1 to new locations. This is also called in one case to
12497 add a link pointing at I3 when I3's destination is changed. */
12500 distribute_links (links)
12503 rtx link, next_link;
12505 for (link = links; link; link = next_link)
12511 next_link = XEXP (link, 1);
12513 /* If the insn that this link points to is a NOTE or isn't a single
12514 set, ignore it. In the latter case, it isn't clear what we
12515 can do other than ignore the link, since we can't tell which
12516 register it was for. Such links wouldn't be used by combine
12519 It is not possible for the destination of the target of the link to
12520 have been changed by combine. The only potential of this is if we
12521 replace I3, I2, and I1 by I3 and I2. But in that case the
12522 destination of I2 also remains unchanged. */
12524 if (GET_CODE (XEXP (link, 0)) == NOTE
12525 || (set = single_set (XEXP (link, 0))) == 0)
12528 reg = SET_DEST (set);
12529 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12530 || GET_CODE (reg) == SIGN_EXTRACT
12531 || GET_CODE (reg) == STRICT_LOW_PART)
12532 reg = XEXP (reg, 0);
12534 /* A LOG_LINK is defined as being placed on the first insn that uses
12535 a register and points to the insn that sets the register. Start
12536 searching at the next insn after the target of the link and stop
12537 when we reach a set of the register or the end of the basic block.
12539 Note that this correctly handles the link that used to point from
12540 I3 to I2. Also note that not much searching is typically done here
12541 since most links don't point very far away. */
12543 for (insn = NEXT_INSN (XEXP (link, 0));
12544 (insn && (this_basic_block == n_basic_blocks - 1
12545 || BLOCK_HEAD (this_basic_block + 1) != insn));
12546 insn = NEXT_INSN (insn))
12547 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12549 if (reg_referenced_p (reg, PATTERN (insn)))
12553 else if (GET_CODE (insn) == CALL_INSN
12554 && find_reg_fusage (insn, USE, reg))
12560 /* If we found a place to put the link, place it there unless there
12561 is already a link to the same insn as LINK at that point. */
12567 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12568 if (XEXP (link2, 0) == XEXP (link, 0))
12573 XEXP (link, 1) = LOG_LINKS (place);
12574 LOG_LINKS (place) = link;
12576 /* Set added_links_insn to the earliest insn we added a
12578 if (added_links_insn == 0
12579 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12580 added_links_insn = place;
12586 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12592 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12593 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12594 insn = NEXT_INSN (insn);
12596 if (INSN_UID (insn) > max_uid_cuid)
12599 return INSN_CUID (insn);
12603 dump_combine_stats (file)
12608 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12609 combine_attempts, combine_merges, combine_extras, combine_successes);
12613 dump_combine_total_stats (file)
12618 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12619 total_attempts, total_merges, total_extras, total_successes);