1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
119 /* Vector mapping INSN_UIDs to cuids.
120 The cuids are like uids but increase monotonically always.
121 Combine always uses cuids so that it can compare them.
122 But actually renumbering the uids, which we used to do,
123 proves to be a bad idea because it makes it hard to compare
124 the dumps produced by earlier passes with those from later passes. */
126 static int *uid_cuid;
127 static int max_uid_cuid;
129 /* Get the cuid of an insn. */
131 #define INSN_CUID(INSN) \
132 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
134 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
135 BITS_PER_WORD would invoke undefined behavior. Work around it. */
137 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
138 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
140 #define nonzero_bits(X, M) \
141 cached_nonzero_bits (X, M, NULL_RTX, VOIDmode, 0)
143 #define num_sign_bit_copies(X, M) \
144 cached_num_sign_bit_copies (X, M, NULL_RTX, VOIDmode, 0)
146 /* Maximum register number, which is the size of the tables below. */
148 static unsigned int combine_max_regno;
150 /* Record last point of death of (hard or pseudo) register n. */
152 static rtx *reg_last_death;
154 /* Record last point of modification of (hard or pseudo) register n. */
156 static rtx *reg_last_set;
158 /* Record the cuid of the last insn that invalidated memory
159 (anything that writes memory, and subroutine calls, but not pushes). */
161 static int mem_last_set;
163 /* Record the cuid of the last CALL_INSN
164 so we can tell whether a potential combination crosses any calls. */
166 static int last_call_cuid;
168 /* When `subst' is called, this is the insn that is being modified
169 (by combining in a previous insn). The PATTERN of this insn
170 is still the old pattern partially modified and it should not be
171 looked at, but this may be used to examine the successors of the insn
172 to judge whether a simplification is valid. */
174 static rtx subst_insn;
176 /* This is the lowest CUID that `subst' is currently dealing with.
177 get_last_value will not return a value if the register was set at or
178 after this CUID. If not for this mechanism, we could get confused if
179 I2 or I1 in try_combine were an insn that used the old value of a register
180 to obtain a new value. In that case, we might erroneously get the
181 new value of the register when we wanted the old one. */
183 static int subst_low_cuid;
185 /* This contains any hard registers that are used in newpat; reg_dead_at_p
186 must consider all these registers to be always live. */
188 static HARD_REG_SET newpat_used_regs;
190 /* This is an insn to which a LOG_LINKS entry has been added. If this
191 insn is the earlier than I2 or I3, combine should rescan starting at
194 static rtx added_links_insn;
196 /* Basic block in which we are performing combines. */
197 static basic_block this_basic_block;
199 /* A bitmap indicating which blocks had registers go dead at entry.
200 After combine, we'll need to re-do global life analysis with
201 those blocks as starting points. */
202 static sbitmap refresh_blocks;
204 /* The next group of arrays allows the recording of the last value assigned
205 to (hard or pseudo) register n. We use this information to see if an
206 operation being processed is redundant given a prior operation performed
207 on the register. For example, an `and' with a constant is redundant if
208 all the zero bits are already known to be turned off.
210 We use an approach similar to that used by cse, but change it in the
213 (1) We do not want to reinitialize at each label.
214 (2) It is useful, but not critical, to know the actual value assigned
215 to a register. Often just its form is helpful.
217 Therefore, we maintain the following arrays:
219 reg_last_set_value the last value assigned
220 reg_last_set_label records the value of label_tick when the
221 register was assigned
222 reg_last_set_table_tick records the value of label_tick when a
223 value using the register is assigned
224 reg_last_set_invalid set to nonzero when it is not valid
225 to use the value of this register in some
228 To understand the usage of these tables, it is important to understand
229 the distinction between the value in reg_last_set_value being valid
230 and the register being validly contained in some other expression in the
233 Entry I in reg_last_set_value is valid if it is nonzero, and either
234 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
236 Register I may validly appear in any expression returned for the value
237 of another register if reg_n_sets[i] is 1. It may also appear in the
238 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
239 reg_last_set_invalid[j] is zero.
241 If an expression is found in the table containing a register which may
242 not validly appear in an expression, the register is replaced by
243 something that won't match, (clobber (const_int 0)).
245 reg_last_set_invalid[i] is set nonzero when register I is being assigned
246 to and reg_last_set_table_tick[i] == label_tick. */
248 /* Record last value assigned to (hard or pseudo) register n. */
250 static rtx *reg_last_set_value;
252 /* Record the value of label_tick when the value for register n is placed in
253 reg_last_set_value[n]. */
255 static int *reg_last_set_label;
257 /* Record the value of label_tick when an expression involving register n
258 is placed in reg_last_set_value. */
260 static int *reg_last_set_table_tick;
262 /* Set nonzero if references to register n in expressions should not be
265 static char *reg_last_set_invalid;
267 /* Incremented for each label. */
269 static int label_tick;
271 /* Some registers that are set more than once and used in more than one
272 basic block are nevertheless always set in similar ways. For example,
273 a QImode register may be loaded from memory in two places on a machine
274 where byte loads zero extend.
276 We record in the following array what we know about the nonzero
277 bits of a register, specifically which bits are known to be zero.
279 If an entry is zero, it means that we don't know anything special. */
281 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
283 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
284 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
286 static enum machine_mode nonzero_bits_mode;
288 /* Nonzero if we know that a register has some leading bits that are always
289 equal to the sign bit. */
291 static unsigned char *reg_sign_bit_copies;
293 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
294 It is zero while computing them and after combine has completed. This
295 former test prevents propagating values based on previously set values,
296 which can be incorrect if a variable is modified in a loop. */
298 static int nonzero_sign_valid;
300 /* These arrays are maintained in parallel with reg_last_set_value
301 and are used to store the mode in which the register was last set,
302 the bits that were known to be zero when it was last set, and the
303 number of sign bits copies it was known to have when it was last set. */
305 static enum machine_mode *reg_last_set_mode;
306 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
307 static char *reg_last_set_sign_bit_copies;
309 /* Record one modification to rtl structure
310 to be undone by storing old_contents into *where.
311 is_int is 1 if the contents are an int. */
317 union {rtx r; int i;} old_contents;
318 union {rtx *r; int *i;} where;
321 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
322 num_undo says how many are currently recorded.
324 other_insn is nonzero if we have modified some other insn in the process
325 of working on subst_insn. It must be verified too. */
334 static struct undobuf undobuf;
336 /* Number of times the pseudo being substituted for
337 was found and replaced. */
339 static int n_occurrences;
341 static void do_SUBST (rtx *, rtx);
342 static void do_SUBST_INT (int *, int);
343 static void init_reg_last_arrays (void);
344 static void setup_incoming_promotions (void);
345 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
346 static int cant_combine_insn_p (rtx);
347 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
348 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
349 static int contains_muldiv (rtx);
350 static rtx try_combine (rtx, rtx, rtx, int *);
351 static void undo_all (void);
352 static void undo_commit (void);
353 static rtx *find_split_point (rtx *, rtx);
354 static rtx subst (rtx, rtx, rtx, int, int);
355 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
356 static rtx simplify_if_then_else (rtx);
357 static rtx simplify_set (rtx);
358 static rtx simplify_logical (rtx, int);
359 static rtx expand_compound_operation (rtx);
360 static rtx expand_field_assignment (rtx);
361 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
362 rtx, unsigned HOST_WIDE_INT, int, int, int);
363 static rtx extract_left_shift (rtx, int);
364 static rtx make_compound_operation (rtx, enum rtx_code);
365 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
366 unsigned HOST_WIDE_INT *);
367 static rtx force_to_mode (rtx, enum machine_mode,
368 unsigned HOST_WIDE_INT, rtx, int);
369 static rtx if_then_else_cond (rtx, rtx *, rtx *);
370 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
371 static int rtx_equal_for_field_assignment_p (rtx, rtx);
372 static rtx make_field_assignment (rtx);
373 static rtx apply_distributive_law (rtx);
374 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
375 unsigned HOST_WIDE_INT);
376 static unsigned HOST_WIDE_INT cached_nonzero_bits (rtx, enum machine_mode,
377 rtx, enum machine_mode,
378 unsigned HOST_WIDE_INT);
379 static unsigned HOST_WIDE_INT nonzero_bits1 (rtx, enum machine_mode, rtx,
381 unsigned HOST_WIDE_INT);
382 static unsigned int cached_num_sign_bit_copies (rtx, enum machine_mode, rtx,
385 static unsigned int num_sign_bit_copies1 (rtx, enum machine_mode, rtx,
386 enum machine_mode, unsigned int);
387 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
388 HOST_WIDE_INT, enum machine_mode, int *);
389 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
391 static int recog_for_combine (rtx *, rtx, rtx *);
392 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
393 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
394 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
395 static void update_table_tick (rtx);
396 static void record_value_for_reg (rtx, rtx, rtx);
397 static void check_promoted_subreg (rtx, rtx);
398 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
399 static void record_dead_and_set_regs (rtx);
400 static int get_last_value_validate (rtx *, rtx, int, int);
401 static rtx get_last_value (rtx);
402 static int use_crosses_set_p (rtx, int);
403 static void reg_dead_at_p_1 (rtx, rtx, void *);
404 static int reg_dead_at_p (rtx, rtx);
405 static void move_deaths (rtx, rtx, int, rtx, rtx *);
406 static int reg_bitfield_target_p (rtx, rtx);
407 static void distribute_notes (rtx, rtx, rtx, rtx);
408 static void distribute_links (rtx);
409 static void mark_used_regs_combine (rtx);
410 static int insn_cuid (rtx);
411 static void record_promoted_value (rtx, rtx);
412 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
413 static enum rtx_code combine_reversed_comparison_code (rtx);
415 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
416 insn. The substitution can be undone by undo_all. If INTO is already
417 set to NEWVAL, do not record this change. Because computing NEWVAL might
418 also call SUBST, we have to compute it before we put anything into
422 do_SUBST (rtx *into, rtx newval)
427 if (oldval == newval)
430 /* We'd like to catch as many invalid transformations here as
431 possible. Unfortunately, there are way too many mode changes
432 that are perfectly valid, so we'd waste too much effort for
433 little gain doing the checks here. Focus on catching invalid
434 transformations involving integer constants. */
435 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
436 && GET_CODE (newval) == CONST_INT)
438 /* Sanity check that we're replacing oldval with a CONST_INT
439 that is a valid sign-extension for the original mode. */
440 if (INTVAL (newval) != trunc_int_for_mode (INTVAL (newval),
444 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
445 CONST_INT is not valid, because after the replacement, the
446 original mode would be gone. Unfortunately, we can't tell
447 when do_SUBST is called to replace the operand thereof, so we
448 perform this test on oldval instead, checking whether an
449 invalid replacement took place before we got here. */
450 if ((GET_CODE (oldval) == SUBREG
451 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT)
452 || (GET_CODE (oldval) == ZERO_EXTEND
453 && GET_CODE (XEXP (oldval, 0)) == CONST_INT))
458 buf = undobuf.frees, undobuf.frees = buf->next;
460 buf = xmalloc (sizeof (struct undo));
464 buf->old_contents.r = oldval;
467 buf->next = undobuf.undos, undobuf.undos = buf;
470 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
472 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
473 for the value of a HOST_WIDE_INT value (including CONST_INT) is
477 do_SUBST_INT (int *into, int newval)
482 if (oldval == newval)
486 buf = undobuf.frees, undobuf.frees = buf->next;
488 buf = xmalloc (sizeof (struct undo));
492 buf->old_contents.i = oldval;
495 buf->next = undobuf.undos, undobuf.undos = buf;
498 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
500 /* Main entry point for combiner. F is the first insn of the function.
501 NREGS is the first unused pseudo-reg number.
503 Return nonzero if the combiner has turned an indirect jump
504 instruction into a direct jump. */
506 combine_instructions (rtx f, unsigned int nregs)
513 rtx links, nextlinks;
515 int new_direct_jump_p = 0;
517 combine_attempts = 0;
520 combine_successes = 0;
522 combine_max_regno = nregs;
524 reg_nonzero_bits = xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT));
525 reg_sign_bit_copies = xcalloc (nregs, sizeof (unsigned char));
527 reg_last_death = xmalloc (nregs * sizeof (rtx));
528 reg_last_set = xmalloc (nregs * sizeof (rtx));
529 reg_last_set_value = xmalloc (nregs * sizeof (rtx));
530 reg_last_set_table_tick = xmalloc (nregs * sizeof (int));
531 reg_last_set_label = xmalloc (nregs * sizeof (int));
532 reg_last_set_invalid = xmalloc (nregs * sizeof (char));
533 reg_last_set_mode = xmalloc (nregs * sizeof (enum machine_mode));
534 reg_last_set_nonzero_bits = xmalloc (nregs * sizeof (HOST_WIDE_INT));
535 reg_last_set_sign_bit_copies = xmalloc (nregs * sizeof (char));
537 init_reg_last_arrays ();
539 init_recog_no_volatile ();
541 /* Compute maximum uid value so uid_cuid can be allocated. */
543 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
544 if (INSN_UID (insn) > i)
547 uid_cuid = xmalloc ((i + 1) * sizeof (int));
550 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
552 /* Don't use reg_nonzero_bits when computing it. This can cause problems
553 when, for example, we have j <<= 1 in a loop. */
555 nonzero_sign_valid = 0;
557 /* Compute the mapping from uids to cuids.
558 Cuids are numbers assigned to insns, like uids,
559 except that cuids increase monotonically through the code.
561 Scan all SETs and see if we can deduce anything about what
562 bits are known to be zero for some registers and how many copies
563 of the sign bit are known to exist for those registers.
565 Also set any known values so that we can use it while searching
566 for what bits are known to be set. */
570 setup_incoming_promotions ();
572 refresh_blocks = sbitmap_alloc (last_basic_block);
573 sbitmap_zero (refresh_blocks);
575 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
577 uid_cuid[INSN_UID (insn)] = ++i;
583 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
585 record_dead_and_set_regs (insn);
588 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
589 if (REG_NOTE_KIND (links) == REG_INC)
590 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
595 if (GET_CODE (insn) == CODE_LABEL)
599 nonzero_sign_valid = 1;
601 /* Now scan all the insns in forward order. */
606 init_reg_last_arrays ();
607 setup_incoming_promotions ();
609 FOR_EACH_BB (this_basic_block)
611 for (insn = BB_HEAD (this_basic_block);
612 insn != NEXT_INSN (BB_END (this_basic_block));
613 insn = next ? next : NEXT_INSN (insn))
617 if (GET_CODE (insn) == CODE_LABEL)
620 else if (INSN_P (insn))
622 /* See if we know about function return values before this
623 insn based upon SUBREG flags. */
624 check_promoted_subreg (insn, PATTERN (insn));
626 /* Try this insn with each insn it links back to. */
628 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
629 if ((next = try_combine (insn, XEXP (links, 0),
630 NULL_RTX, &new_direct_jump_p)) != 0)
633 /* Try each sequence of three linked insns ending with this one. */
635 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
637 rtx link = XEXP (links, 0);
639 /* If the linked insn has been replaced by a note, then there
640 is no point in pursuing this chain any further. */
641 if (GET_CODE (link) == NOTE)
644 for (nextlinks = LOG_LINKS (link);
646 nextlinks = XEXP (nextlinks, 1))
647 if ((next = try_combine (insn, link,
649 &new_direct_jump_p)) != 0)
654 /* Try to combine a jump insn that uses CC0
655 with a preceding insn that sets CC0, and maybe with its
656 logical predecessor as well.
657 This is how we make decrement-and-branch insns.
658 We need this special code because data flow connections
659 via CC0 do not get entered in LOG_LINKS. */
661 if (GET_CODE (insn) == JUMP_INSN
662 && (prev = prev_nonnote_insn (insn)) != 0
663 && GET_CODE (prev) == INSN
664 && sets_cc0_p (PATTERN (prev)))
666 if ((next = try_combine (insn, prev,
667 NULL_RTX, &new_direct_jump_p)) != 0)
670 for (nextlinks = LOG_LINKS (prev); nextlinks;
671 nextlinks = XEXP (nextlinks, 1))
672 if ((next = try_combine (insn, prev,
674 &new_direct_jump_p)) != 0)
678 /* Do the same for an insn that explicitly references CC0. */
679 if (GET_CODE (insn) == INSN
680 && (prev = prev_nonnote_insn (insn)) != 0
681 && GET_CODE (prev) == INSN
682 && sets_cc0_p (PATTERN (prev))
683 && GET_CODE (PATTERN (insn)) == SET
684 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
686 if ((next = try_combine (insn, prev,
687 NULL_RTX, &new_direct_jump_p)) != 0)
690 for (nextlinks = LOG_LINKS (prev); nextlinks;
691 nextlinks = XEXP (nextlinks, 1))
692 if ((next = try_combine (insn, prev,
694 &new_direct_jump_p)) != 0)
698 /* Finally, see if any of the insns that this insn links to
699 explicitly references CC0. If so, try this insn, that insn,
700 and its predecessor if it sets CC0. */
701 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
702 if (GET_CODE (XEXP (links, 0)) == INSN
703 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
704 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
705 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
706 && GET_CODE (prev) == INSN
707 && sets_cc0_p (PATTERN (prev))
708 && (next = try_combine (insn, XEXP (links, 0),
709 prev, &new_direct_jump_p)) != 0)
713 /* Try combining an insn with two different insns whose results it
715 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
716 for (nextlinks = XEXP (links, 1); nextlinks;
717 nextlinks = XEXP (nextlinks, 1))
718 if ((next = try_combine (insn, XEXP (links, 0),
720 &new_direct_jump_p)) != 0)
723 if (GET_CODE (insn) != NOTE)
724 record_dead_and_set_regs (insn);
733 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
734 BASIC_BLOCK (i)->flags |= BB_DIRTY);
735 new_direct_jump_p |= purge_all_dead_edges (0);
736 delete_noop_moves (f);
738 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
739 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
740 | PROP_KILL_DEAD_CODE);
743 sbitmap_free (refresh_blocks);
744 free (reg_nonzero_bits);
745 free (reg_sign_bit_copies);
746 free (reg_last_death);
748 free (reg_last_set_value);
749 free (reg_last_set_table_tick);
750 free (reg_last_set_label);
751 free (reg_last_set_invalid);
752 free (reg_last_set_mode);
753 free (reg_last_set_nonzero_bits);
754 free (reg_last_set_sign_bit_copies);
758 struct undo *undo, *next;
759 for (undo = undobuf.frees; undo; undo = next)
767 total_attempts += combine_attempts;
768 total_merges += combine_merges;
769 total_extras += combine_extras;
770 total_successes += combine_successes;
772 nonzero_sign_valid = 0;
774 /* Make recognizer allow volatile MEMs again. */
777 return new_direct_jump_p;
780 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
783 init_reg_last_arrays (void)
785 unsigned int nregs = combine_max_regno;
787 memset (reg_last_death, 0, nregs * sizeof (rtx));
788 memset (reg_last_set, 0, nregs * sizeof (rtx));
789 memset (reg_last_set_value, 0, nregs * sizeof (rtx));
790 memset (reg_last_set_table_tick, 0, nregs * sizeof (int));
791 memset (reg_last_set_label, 0, nregs * sizeof (int));
792 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
793 memset (reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
794 memset (reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
795 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
798 /* Set up any promoted values for incoming argument registers. */
801 setup_incoming_promotions (void)
805 enum machine_mode mode;
807 rtx first = get_insns ();
809 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
811 #ifndef OUTGOING_REGNO
812 #define OUTGOING_REGNO(N) N
814 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
815 /* Check whether this register can hold an incoming pointer
816 argument. FUNCTION_ARG_REGNO_P tests outgoing register
817 numbers, so translate if necessary due to register windows. */
818 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
819 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
822 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
825 gen_rtx_CLOBBER (mode, const0_rtx)));
830 /* Called via note_stores. If X is a pseudo that is narrower than
831 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
833 If we are setting only a portion of X and we can't figure out what
834 portion, assume all bits will be used since we don't know what will
837 Similarly, set how many bits of X are known to be copies of the sign bit
838 at all locations in the function. This is the smallest number implied
842 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
843 void *data ATTRIBUTE_UNUSED)
847 if (GET_CODE (x) == REG
848 && REGNO (x) >= FIRST_PSEUDO_REGISTER
849 /* If this register is undefined at the start of the file, we can't
850 say what its contents were. */
851 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
852 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
854 if (set == 0 || GET_CODE (set) == CLOBBER)
856 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
857 reg_sign_bit_copies[REGNO (x)] = 1;
861 /* If this is a complex assignment, see if we can convert it into a
862 simple assignment. */
863 set = expand_field_assignment (set);
865 /* If this is a simple assignment, or we have a paradoxical SUBREG,
866 set what we know about X. */
868 if (SET_DEST (set) == x
869 || (GET_CODE (SET_DEST (set)) == SUBREG
870 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
871 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
872 && SUBREG_REG (SET_DEST (set)) == x))
874 rtx src = SET_SRC (set);
876 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
877 /* If X is narrower than a word and SRC is a non-negative
878 constant that would appear negative in the mode of X,
879 sign-extend it for use in reg_nonzero_bits because some
880 machines (maybe most) will actually do the sign-extension
881 and this is the conservative approach.
883 ??? For 2.5, try to tighten up the MD files in this regard
884 instead of this kludge. */
886 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
887 && GET_CODE (src) == CONST_INT
889 && 0 != (INTVAL (src)
891 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
892 src = GEN_INT (INTVAL (src)
893 | ((HOST_WIDE_INT) (-1)
894 << GET_MODE_BITSIZE (GET_MODE (x))));
897 /* Don't call nonzero_bits if it cannot change anything. */
898 if (reg_nonzero_bits[REGNO (x)] != ~(unsigned HOST_WIDE_INT) 0)
899 reg_nonzero_bits[REGNO (x)]
900 |= nonzero_bits (src, nonzero_bits_mode);
901 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
902 if (reg_sign_bit_copies[REGNO (x)] == 0
903 || reg_sign_bit_copies[REGNO (x)] > num)
904 reg_sign_bit_copies[REGNO (x)] = num;
908 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
909 reg_sign_bit_copies[REGNO (x)] = 1;
914 /* See if INSN can be combined into I3. PRED and SUCC are optionally
915 insns that were previously combined into I3 or that will be combined
916 into the merger of INSN and I3.
918 Return 0 if the combination is not allowed for any reason.
920 If the combination is allowed, *PDEST will be set to the single
921 destination of INSN and *PSRC to the single source, and this function
925 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
926 rtx *pdest, rtx *psrc)
929 rtx set = 0, src, dest;
934 int all_adjacent = (succ ? (next_active_insn (insn) == succ
935 && next_active_insn (succ) == i3)
936 : next_active_insn (insn) == i3);
938 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
939 or a PARALLEL consisting of such a SET and CLOBBERs.
941 If INSN has CLOBBER parallel parts, ignore them for our processing.
942 By definition, these happen during the execution of the insn. When it
943 is merged with another insn, all bets are off. If they are, in fact,
944 needed and aren't also supplied in I3, they may be added by
945 recog_for_combine. Otherwise, it won't match.
947 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
950 Get the source and destination of INSN. If more than one, can't
953 if (GET_CODE (PATTERN (insn)) == SET)
954 set = PATTERN (insn);
955 else if (GET_CODE (PATTERN (insn)) == PARALLEL
956 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
958 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
960 rtx elt = XVECEXP (PATTERN (insn), 0, i);
962 switch (GET_CODE (elt))
964 /* This is important to combine floating point insns
967 /* Combining an isolated USE doesn't make sense.
968 We depend here on combinable_i3pat to reject them. */
969 /* The code below this loop only verifies that the inputs of
970 the SET in INSN do not change. We call reg_set_between_p
971 to verify that the REG in the USE does not change between
973 If the USE in INSN was for a pseudo register, the matching
974 insn pattern will likely match any register; combining this
975 with any other USE would only be safe if we knew that the
976 used registers have identical values, or if there was
977 something to tell them apart, e.g. different modes. For
978 now, we forgo such complicated tests and simply disallow
979 combining of USES of pseudo registers with any other USE. */
980 if (GET_CODE (XEXP (elt, 0)) == REG
981 && GET_CODE (PATTERN (i3)) == PARALLEL)
983 rtx i3pat = PATTERN (i3);
984 int i = XVECLEN (i3pat, 0) - 1;
985 unsigned int regno = REGNO (XEXP (elt, 0));
989 rtx i3elt = XVECEXP (i3pat, 0, i);
991 if (GET_CODE (i3elt) == USE
992 && GET_CODE (XEXP (i3elt, 0)) == REG
993 && (REGNO (XEXP (i3elt, 0)) == regno
994 ? reg_set_between_p (XEXP (elt, 0),
995 PREV_INSN (insn), i3)
996 : regno >= FIRST_PSEUDO_REGISTER))
1003 /* We can ignore CLOBBERs. */
1008 /* Ignore SETs whose result isn't used but not those that
1009 have side-effects. */
1010 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1011 && ! side_effects_p (elt))
1014 /* If we have already found a SET, this is a second one and
1015 so we cannot combine with this insn. */
1023 /* Anything else means we can't combine. */
1029 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1030 so don't do anything with it. */
1031 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1040 set = expand_field_assignment (set);
1041 src = SET_SRC (set), dest = SET_DEST (set);
1043 /* Don't eliminate a store in the stack pointer. */
1044 if (dest == stack_pointer_rtx
1045 /* Don't combine with an insn that sets a register to itself if it has
1046 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1047 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1048 /* Can't merge an ASM_OPERANDS. */
1049 || GET_CODE (src) == ASM_OPERANDS
1050 /* Can't merge a function call. */
1051 || GET_CODE (src) == CALL
1052 /* Don't eliminate a function call argument. */
1053 || (GET_CODE (i3) == CALL_INSN
1054 && (find_reg_fusage (i3, USE, dest)
1055 || (GET_CODE (dest) == REG
1056 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1057 && global_regs[REGNO (dest)])))
1058 /* Don't substitute into an incremented register. */
1059 || FIND_REG_INC_NOTE (i3, dest)
1060 || (succ && FIND_REG_INC_NOTE (succ, dest))
1062 /* Don't combine the end of a libcall into anything. */
1063 /* ??? This gives worse code, and appears to be unnecessary, since no
1064 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1065 use REG_RETVAL notes for noconflict blocks, but other code here
1066 makes sure that those insns don't disappear. */
1067 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1069 /* Make sure that DEST is not used after SUCC but before I3. */
1070 || (succ && ! all_adjacent
1071 && reg_used_between_p (dest, succ, i3))
1072 /* Make sure that the value that is to be substituted for the register
1073 does not use any registers whose values alter in between. However,
1074 If the insns are adjacent, a use can't cross a set even though we
1075 think it might (this can happen for a sequence of insns each setting
1076 the same destination; reg_last_set of that register might point to
1077 a NOTE). If INSN has a REG_EQUIV note, the register is always
1078 equivalent to the memory so the substitution is valid even if there
1079 are intervening stores. Also, don't move a volatile asm or
1080 UNSPEC_VOLATILE across any other insns. */
1082 && (((GET_CODE (src) != MEM
1083 || ! find_reg_note (insn, REG_EQUIV, src))
1084 && use_crosses_set_p (src, INSN_CUID (insn)))
1085 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1086 || GET_CODE (src) == UNSPEC_VOLATILE))
1087 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1088 better register allocation by not doing the combine. */
1089 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1090 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1091 /* Don't combine across a CALL_INSN, because that would possibly
1092 change whether the life span of some REGs crosses calls or not,
1093 and it is a pain to update that information.
1094 Exception: if source is a constant, moving it later can't hurt.
1095 Accept that special case, because it helps -fforce-addr a lot. */
1096 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1099 /* DEST must either be a REG or CC0. */
1100 if (GET_CODE (dest) == REG)
1102 /* If register alignment is being enforced for multi-word items in all
1103 cases except for parameters, it is possible to have a register copy
1104 insn referencing a hard register that is not allowed to contain the
1105 mode being copied and which would not be valid as an operand of most
1106 insns. Eliminate this problem by not combining with such an insn.
1108 Also, on some machines we don't want to extend the life of a hard
1111 if (GET_CODE (src) == REG
1112 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1113 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1114 /* Don't extend the life of a hard register unless it is
1115 user variable (if we have few registers) or it can't
1116 fit into the desired register (meaning something special
1118 Also avoid substituting a return register into I3, because
1119 reload can't handle a conflict with constraints of other
1121 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1122 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1125 else if (GET_CODE (dest) != CC0)
1128 /* Don't substitute for a register intended as a clobberable operand.
1129 Similarly, don't substitute an expression containing a register that
1130 will be clobbered in I3. */
1131 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1132 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1133 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1134 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1136 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1139 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1140 or not), reject, unless nothing volatile comes between it and I3 */
1142 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1144 /* Make sure succ doesn't contain a volatile reference. */
1145 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1148 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1149 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1153 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1154 to be an explicit register variable, and was chosen for a reason. */
1156 if (GET_CODE (src) == ASM_OPERANDS
1157 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1160 /* If there are any volatile insns between INSN and I3, reject, because
1161 they might affect machine state. */
1163 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1164 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1167 /* If INSN or I2 contains an autoincrement or autodecrement,
1168 make sure that register is not used between there and I3,
1169 and not already used in I3 either.
1170 Also insist that I3 not be a jump; if it were one
1171 and the incremented register were spilled, we would lose. */
1174 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1175 if (REG_NOTE_KIND (link) == REG_INC
1176 && (GET_CODE (i3) == JUMP_INSN
1177 || reg_used_between_p (XEXP (link, 0), insn, i3)
1178 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1183 /* Don't combine an insn that follows a CC0-setting insn.
1184 An insn that uses CC0 must not be separated from the one that sets it.
1185 We do, however, allow I2 to follow a CC0-setting insn if that insn
1186 is passed as I1; in that case it will be deleted also.
1187 We also allow combining in this case if all the insns are adjacent
1188 because that would leave the two CC0 insns adjacent as well.
1189 It would be more logical to test whether CC0 occurs inside I1 or I2,
1190 but that would be much slower, and this ought to be equivalent. */
1192 p = prev_nonnote_insn (insn);
1193 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1198 /* If we get here, we have passed all the tests and the combination is
1207 /* LOC is the location within I3 that contains its pattern or the component
1208 of a PARALLEL of the pattern. We validate that it is valid for combining.
1210 One problem is if I3 modifies its output, as opposed to replacing it
1211 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1212 so would produce an insn that is not equivalent to the original insns.
1216 (set (reg:DI 101) (reg:DI 100))
1217 (set (subreg:SI (reg:DI 101) 0) <foo>)
1219 This is NOT equivalent to:
1221 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1222 (set (reg:DI 101) (reg:DI 100))])
1224 Not only does this modify 100 (in which case it might still be valid
1225 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1227 We can also run into a problem if I2 sets a register that I1
1228 uses and I1 gets directly substituted into I3 (not via I2). In that
1229 case, we would be getting the wrong value of I2DEST into I3, so we
1230 must reject the combination. This case occurs when I2 and I1 both
1231 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1232 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1233 of a SET must prevent combination from occurring.
1235 Before doing the above check, we first try to expand a field assignment
1236 into a set of logical operations.
1238 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1239 we place a register that is both set and used within I3. If more than one
1240 such register is detected, we fail.
1242 Return 1 if the combination is valid, zero otherwise. */
1245 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1246 int i1_not_in_src, rtx *pi3dest_killed)
1250 if (GET_CODE (x) == SET)
1253 rtx dest = SET_DEST (set);
1254 rtx src = SET_SRC (set);
1255 rtx inner_dest = dest;
1257 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1258 || GET_CODE (inner_dest) == SUBREG
1259 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1260 inner_dest = XEXP (inner_dest, 0);
1262 /* Check for the case where I3 modifies its output, as discussed
1263 above. We don't want to prevent pseudos from being combined
1264 into the address of a MEM, so only prevent the combination if
1265 i1 or i2 set the same MEM. */
1266 if ((inner_dest != dest &&
1267 (GET_CODE (inner_dest) != MEM
1268 || rtx_equal_p (i2dest, inner_dest)
1269 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1270 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1271 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1273 /* This is the same test done in can_combine_p except we can't test
1274 all_adjacent; we don't have to, since this instruction will stay
1275 in place, thus we are not considering increasing the lifetime of
1278 Also, if this insn sets a function argument, combining it with
1279 something that might need a spill could clobber a previous
1280 function argument; the all_adjacent test in can_combine_p also
1281 checks this; here, we do a more specific test for this case. */
1283 || (GET_CODE (inner_dest) == REG
1284 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1285 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1286 GET_MODE (inner_dest))))
1287 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1290 /* If DEST is used in I3, it is being killed in this insn,
1291 so record that for later.
1292 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1293 STACK_POINTER_REGNUM, since these are always considered to be
1294 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1295 if (pi3dest_killed && GET_CODE (dest) == REG
1296 && reg_referenced_p (dest, PATTERN (i3))
1297 && REGNO (dest) != FRAME_POINTER_REGNUM
1298 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1299 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1301 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1302 && (REGNO (dest) != ARG_POINTER_REGNUM
1303 || ! fixed_regs [REGNO (dest)])
1305 && REGNO (dest) != STACK_POINTER_REGNUM)
1307 if (*pi3dest_killed)
1310 *pi3dest_killed = dest;
1314 else if (GET_CODE (x) == PARALLEL)
1318 for (i = 0; i < XVECLEN (x, 0); i++)
1319 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1320 i1_not_in_src, pi3dest_killed))
1327 /* Return 1 if X is an arithmetic expression that contains a multiplication
1328 and division. We don't count multiplications by powers of two here. */
1331 contains_muldiv (rtx x)
1333 switch (GET_CODE (x))
1335 case MOD: case DIV: case UMOD: case UDIV:
1339 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1340 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1342 switch (GET_RTX_CLASS (GET_CODE (x)))
1344 case 'c': case '<': case '2':
1345 return contains_muldiv (XEXP (x, 0))
1346 || contains_muldiv (XEXP (x, 1));
1349 return contains_muldiv (XEXP (x, 0));
1357 /* Determine whether INSN can be used in a combination. Return nonzero if
1358 not. This is used in try_combine to detect early some cases where we
1359 can't perform combinations. */
1362 cant_combine_insn_p (rtx insn)
1367 /* If this isn't really an insn, we can't do anything.
1368 This can occur when flow deletes an insn that it has merged into an
1369 auto-increment address. */
1370 if (! INSN_P (insn))
1373 /* Never combine loads and stores involving hard regs that are likely
1374 to be spilled. The register allocator can usually handle such
1375 reg-reg moves by tying. If we allow the combiner to make
1376 substitutions of likely-spilled regs, we may abort in reload.
1377 As an exception, we allow combinations involving fixed regs; these are
1378 not available to the register allocator so there's no risk involved. */
1380 set = single_set (insn);
1383 src = SET_SRC (set);
1384 dest = SET_DEST (set);
1385 if (GET_CODE (src) == SUBREG)
1386 src = SUBREG_REG (src);
1387 if (GET_CODE (dest) == SUBREG)
1388 dest = SUBREG_REG (dest);
1389 if (REG_P (src) && REG_P (dest)
1390 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1391 && ! fixed_regs[REGNO (src)]
1392 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1393 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1394 && ! fixed_regs[REGNO (dest)]
1395 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1401 /* Adjust INSN after we made a change to its destination.
1403 Changing the destination can invalidate notes that say something about
1404 the results of the insn and a LOG_LINK pointing to the insn. */
1407 adjust_for_new_dest (rtx insn)
1411 /* For notes, be conservative and simply remove them. */
1412 loc = ®_NOTES (insn);
1415 enum reg_note kind = REG_NOTE_KIND (*loc);
1416 if (kind == REG_EQUAL || kind == REG_EQUIV)
1417 *loc = XEXP (*loc, 1);
1419 loc = &XEXP (*loc, 1);
1422 /* The new insn will have a destination that was previously the destination
1423 of an insn just above it. Call distribute_links to make a LOG_LINK from
1424 the next use of that destination. */
1425 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1428 /* Try to combine the insns I1 and I2 into I3.
1429 Here I1 and I2 appear earlier than I3.
1430 I1 can be zero; then we combine just I2 into I3.
1432 If we are combining three insns and the resulting insn is not recognized,
1433 try splitting it into two insns. If that happens, I2 and I3 are retained
1434 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1437 Return 0 if the combination does not work. Then nothing is changed.
1438 If we did the combination, return the insn at which combine should
1441 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1442 new direct jump instruction. */
1445 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1447 /* New patterns for I3 and I2, respectively. */
1448 rtx newpat, newi2pat = 0;
1449 int substed_i2 = 0, substed_i1 = 0;
1450 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1451 int added_sets_1, added_sets_2;
1452 /* Total number of SETs to put into I3. */
1454 /* Nonzero is I2's body now appears in I3. */
1456 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1457 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1458 /* Contains I3 if the destination of I3 is used in its source, which means
1459 that the old life of I3 is being killed. If that usage is placed into
1460 I2 and not in I3, a REG_DEAD note must be made. */
1461 rtx i3dest_killed = 0;
1462 /* SET_DEST and SET_SRC of I2 and I1. */
1463 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1464 /* PATTERN (I2), or a copy of it in certain cases. */
1466 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1467 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1468 int i1_feeds_i3 = 0;
1469 /* Notes that must be added to REG_NOTES in I3 and I2. */
1470 rtx new_i3_notes, new_i2_notes;
1471 /* Notes that we substituted I3 into I2 instead of the normal case. */
1472 int i3_subst_into_i2 = 0;
1473 /* Notes that I1, I2 or I3 is a MULT operation. */
1481 /* Exit early if one of the insns involved can't be used for
1483 if (cant_combine_insn_p (i3)
1484 || cant_combine_insn_p (i2)
1485 || (i1 && cant_combine_insn_p (i1))
1486 /* We also can't do anything if I3 has a
1487 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1490 /* ??? This gives worse code, and appears to be unnecessary, since no
1491 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1492 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1498 undobuf.other_insn = 0;
1500 /* Reset the hard register usage information. */
1501 CLEAR_HARD_REG_SET (newpat_used_regs);
1503 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1504 code below, set I1 to be the earlier of the two insns. */
1505 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1506 temp = i1, i1 = i2, i2 = temp;
1508 added_links_insn = 0;
1510 /* First check for one important special-case that the code below will
1511 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1512 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1513 we may be able to replace that destination with the destination of I3.
1514 This occurs in the common code where we compute both a quotient and
1515 remainder into a structure, in which case we want to do the computation
1516 directly into the structure to avoid register-register copies.
1518 Note that this case handles both multiple sets in I2 and also
1519 cases where I2 has a number of CLOBBER or PARALLELs.
1521 We make very conservative checks below and only try to handle the
1522 most common cases of this. For example, we only handle the case
1523 where I2 and I3 are adjacent to avoid making difficult register
1526 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1527 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1528 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1529 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1530 && GET_CODE (PATTERN (i2)) == PARALLEL
1531 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1532 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1533 below would need to check what is inside (and reg_overlap_mentioned_p
1534 doesn't support those codes anyway). Don't allow those destinations;
1535 the resulting insn isn't likely to be recognized anyway. */
1536 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1537 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1538 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1539 SET_DEST (PATTERN (i3)))
1540 && next_real_insn (i2) == i3)
1542 rtx p2 = PATTERN (i2);
1544 /* Make sure that the destination of I3,
1545 which we are going to substitute into one output of I2,
1546 is not used within another output of I2. We must avoid making this:
1547 (parallel [(set (mem (reg 69)) ...)
1548 (set (reg 69) ...)])
1549 which is not well-defined as to order of actions.
1550 (Besides, reload can't handle output reloads for this.)
1552 The problem can also happen if the dest of I3 is a memory ref,
1553 if another dest in I2 is an indirect memory ref. */
1554 for (i = 0; i < XVECLEN (p2, 0); i++)
1555 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1556 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1557 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1558 SET_DEST (XVECEXP (p2, 0, i))))
1561 if (i == XVECLEN (p2, 0))
1562 for (i = 0; i < XVECLEN (p2, 0); i++)
1563 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1564 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1565 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1570 subst_low_cuid = INSN_CUID (i2);
1572 added_sets_2 = added_sets_1 = 0;
1573 i2dest = SET_SRC (PATTERN (i3));
1575 /* Replace the dest in I2 with our dest and make the resulting
1576 insn the new pattern for I3. Then skip to where we
1577 validate the pattern. Everything was set up above. */
1578 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1579 SET_DEST (PATTERN (i3)));
1582 i3_subst_into_i2 = 1;
1583 goto validate_replacement;
1587 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1588 one of those words to another constant, merge them by making a new
1591 && (temp = single_set (i2)) != 0
1592 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1593 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1594 && GET_CODE (SET_DEST (temp)) == REG
1595 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1596 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1597 && GET_CODE (PATTERN (i3)) == SET
1598 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1599 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1600 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1601 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1602 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1604 HOST_WIDE_INT lo, hi;
1606 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1607 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1610 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1611 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1614 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1616 /* We don't handle the case of the target word being wider
1617 than a host wide int. */
1618 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1621 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1622 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1623 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1625 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1626 hi = INTVAL (SET_SRC (PATTERN (i3)));
1627 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1629 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1630 >> (HOST_BITS_PER_WIDE_INT - 1));
1632 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1633 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1634 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1635 (INTVAL (SET_SRC (PATTERN (i3)))));
1637 hi = lo < 0 ? -1 : 0;
1640 /* We don't handle the case of the higher word not fitting
1641 entirely in either hi or lo. */
1646 subst_low_cuid = INSN_CUID (i2);
1647 added_sets_2 = added_sets_1 = 0;
1648 i2dest = SET_DEST (temp);
1650 SUBST (SET_SRC (temp),
1651 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1653 newpat = PATTERN (i2);
1654 goto validate_replacement;
1658 /* If we have no I1 and I2 looks like:
1659 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1661 make up a dummy I1 that is
1664 (set (reg:CC X) (compare:CC Y (const_int 0)))
1666 (We can ignore any trailing CLOBBERs.)
1668 This undoes a previous combination and allows us to match a branch-and-
1671 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1672 && XVECLEN (PATTERN (i2), 0) >= 2
1673 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1674 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1676 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1677 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1678 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1679 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1680 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1681 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1683 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1684 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1689 /* We make I1 with the same INSN_UID as I2. This gives it
1690 the same INSN_CUID for value tracking. Our fake I1 will
1691 never appear in the insn stream so giving it the same INSN_UID
1692 as I2 will not cause a problem. */
1694 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1695 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1696 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1699 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1700 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1701 SET_DEST (PATTERN (i1)));
1706 /* Verify that I2 and I1 are valid for combining. */
1707 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1708 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1714 /* Record whether I2DEST is used in I2SRC and similarly for the other
1715 cases. Knowing this will help in register status updating below. */
1716 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1717 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1718 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1720 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1722 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1724 /* Ensure that I3's pattern can be the destination of combines. */
1725 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1726 i1 && i2dest_in_i1src && i1_feeds_i3,
1733 /* See if any of the insns is a MULT operation. Unless one is, we will
1734 reject a combination that is, since it must be slower. Be conservative
1736 if (GET_CODE (i2src) == MULT
1737 || (i1 != 0 && GET_CODE (i1src) == MULT)
1738 || (GET_CODE (PATTERN (i3)) == SET
1739 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1742 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1743 We used to do this EXCEPT in one case: I3 has a post-inc in an
1744 output operand. However, that exception can give rise to insns like
1746 which is a famous insn on the PDP-11 where the value of r3 used as the
1747 source was model-dependent. Avoid this sort of thing. */
1750 if (!(GET_CODE (PATTERN (i3)) == SET
1751 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1752 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1753 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1754 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1755 /* It's not the exception. */
1758 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1759 if (REG_NOTE_KIND (link) == REG_INC
1760 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1762 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1769 /* See if the SETs in I1 or I2 need to be kept around in the merged
1770 instruction: whenever the value set there is still needed past I3.
1771 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1773 For the SET in I1, we have two cases: If I1 and I2 independently
1774 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1775 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1776 in I1 needs to be kept around unless I1DEST dies or is set in either
1777 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1778 I1DEST. If so, we know I1 feeds into I2. */
1780 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1783 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1784 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1786 /* If the set in I2 needs to be kept around, we must make a copy of
1787 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1788 PATTERN (I2), we are only substituting for the original I1DEST, not into
1789 an already-substituted copy. This also prevents making self-referential
1790 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1793 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1794 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1798 i2pat = copy_rtx (i2pat);
1802 /* Substitute in the latest insn for the regs set by the earlier ones. */
1804 maxreg = max_reg_num ();
1808 /* It is possible that the source of I2 or I1 may be performing an
1809 unneeded operation, such as a ZERO_EXTEND of something that is known
1810 to have the high part zero. Handle that case by letting subst look at
1811 the innermost one of them.
1813 Another way to do this would be to have a function that tries to
1814 simplify a single insn instead of merging two or more insns. We don't
1815 do this because of the potential of infinite loops and because
1816 of the potential extra memory required. However, doing it the way
1817 we are is a bit of a kludge and doesn't catch all cases.
1819 But only do this if -fexpensive-optimizations since it slows things down
1820 and doesn't usually win. */
1822 if (flag_expensive_optimizations)
1824 /* Pass pc_rtx so no substitutions are done, just simplifications.
1825 The cases that we are interested in here do not involve the few
1826 cases were is_replaced is checked. */
1829 subst_low_cuid = INSN_CUID (i1);
1830 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1834 subst_low_cuid = INSN_CUID (i2);
1835 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1840 /* Many machines that don't use CC0 have insns that can both perform an
1841 arithmetic operation and set the condition code. These operations will
1842 be represented as a PARALLEL with the first element of the vector
1843 being a COMPARE of an arithmetic operation with the constant zero.
1844 The second element of the vector will set some pseudo to the result
1845 of the same arithmetic operation. If we simplify the COMPARE, we won't
1846 match such a pattern and so will generate an extra insn. Here we test
1847 for this case, where both the comparison and the operation result are
1848 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1849 I2SRC. Later we will make the PARALLEL that contains I2. */
1851 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1852 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1853 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1854 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1856 #ifdef SELECT_CC_MODE
1858 enum machine_mode compare_mode;
1861 newpat = PATTERN (i3);
1862 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1866 #ifdef SELECT_CC_MODE
1867 /* See if a COMPARE with the operand we substituted in should be done
1868 with the mode that is currently being used. If not, do the same
1869 processing we do in `subst' for a SET; namely, if the destination
1870 is used only once, try to replace it with a register of the proper
1871 mode and also replace the COMPARE. */
1872 if (undobuf.other_insn == 0
1873 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1874 &undobuf.other_insn))
1875 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1877 != GET_MODE (SET_DEST (newpat))))
1879 unsigned int regno = REGNO (SET_DEST (newpat));
1880 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1882 if (regno < FIRST_PSEUDO_REGISTER
1883 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1884 && ! REG_USERVAR_P (SET_DEST (newpat))))
1886 if (regno >= FIRST_PSEUDO_REGISTER)
1887 SUBST (regno_reg_rtx[regno], new_dest);
1889 SUBST (SET_DEST (newpat), new_dest);
1890 SUBST (XEXP (*cc_use, 0), new_dest);
1891 SUBST (SET_SRC (newpat),
1892 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
1895 undobuf.other_insn = 0;
1902 n_occurrences = 0; /* `subst' counts here */
1904 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1905 need to make a unique copy of I2SRC each time we substitute it
1906 to avoid self-referential rtl. */
1908 subst_low_cuid = INSN_CUID (i2);
1909 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1910 ! i1_feeds_i3 && i1dest_in_i1src);
1913 /* Record whether i2's body now appears within i3's body. */
1914 i2_is_used = n_occurrences;
1917 /* If we already got a failure, don't try to do more. Otherwise,
1918 try to substitute in I1 if we have it. */
1920 if (i1 && GET_CODE (newpat) != CLOBBER)
1922 /* Before we can do this substitution, we must redo the test done
1923 above (see detailed comments there) that ensures that I1DEST
1924 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1926 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1934 subst_low_cuid = INSN_CUID (i1);
1935 newpat = subst (newpat, i1dest, i1src, 0, 0);
1939 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1940 to count all the ways that I2SRC and I1SRC can be used. */
1941 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1942 && i2_is_used + added_sets_2 > 1)
1943 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1944 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1946 /* Fail if we tried to make a new register (we used to abort, but there's
1947 really no reason to). */
1948 || max_reg_num () != maxreg
1949 /* Fail if we couldn't do something and have a CLOBBER. */
1950 || GET_CODE (newpat) == CLOBBER
1951 /* Fail if this new pattern is a MULT and we didn't have one before
1952 at the outer level. */
1953 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1960 /* If the actions of the earlier insns must be kept
1961 in addition to substituting them into the latest one,
1962 we must make a new PARALLEL for the latest insn
1963 to hold additional the SETs. */
1965 if (added_sets_1 || added_sets_2)
1969 if (GET_CODE (newpat) == PARALLEL)
1971 rtvec old = XVEC (newpat, 0);
1972 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1973 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1974 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
1975 sizeof (old->elem[0]) * old->num_elem);
1980 total_sets = 1 + added_sets_1 + added_sets_2;
1981 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1982 XVECEXP (newpat, 0, 0) = old;
1986 XVECEXP (newpat, 0, --total_sets)
1987 = (GET_CODE (PATTERN (i1)) == PARALLEL
1988 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1992 /* If there is no I1, use I2's body as is. We used to also not do
1993 the subst call below if I2 was substituted into I3,
1994 but that could lose a simplification. */
1996 XVECEXP (newpat, 0, --total_sets) = i2pat;
1998 /* See comment where i2pat is assigned. */
1999 XVECEXP (newpat, 0, --total_sets)
2000 = subst (i2pat, i1dest, i1src, 0, 0);
2004 /* We come here when we are replacing a destination in I2 with the
2005 destination of I3. */
2006 validate_replacement:
2008 /* Note which hard regs this insn has as inputs. */
2009 mark_used_regs_combine (newpat);
2011 /* Is the result of combination a valid instruction? */
2012 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2014 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2015 the second SET's destination is a register that is unused. In that case,
2016 we just need the first SET. This can occur when simplifying a divmod
2017 insn. We *must* test for this case here because the code below that
2018 splits two independent SETs doesn't handle this case correctly when it
2019 updates the register status. Also check the case where the first
2020 SET's destination is unused. That would not cause incorrect code, but
2021 does cause an unneeded insn to remain. */
2023 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2024 && XVECLEN (newpat, 0) == 2
2025 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2026 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2027 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2028 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2029 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2030 && asm_noperands (newpat) < 0)
2032 newpat = XVECEXP (newpat, 0, 0);
2033 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2036 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2037 && XVECLEN (newpat, 0) == 2
2038 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2039 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2040 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2041 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2042 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2043 && asm_noperands (newpat) < 0)
2045 newpat = XVECEXP (newpat, 0, 1);
2046 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2048 if (insn_code_number >= 0)
2050 /* If we will be able to accept this, we have made a change to the
2051 destination of I3. This requires us to do a few adjustments. */
2052 PATTERN (i3) = newpat;
2053 adjust_for_new_dest (i3);
2057 /* If we were combining three insns and the result is a simple SET
2058 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2059 insns. There are two ways to do this. It can be split using a
2060 machine-specific method (like when you have an addition of a large
2061 constant) or by combine in the function find_split_point. */
2063 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2064 && asm_noperands (newpat) < 0)
2066 rtx m_split, *split;
2067 rtx ni2dest = i2dest;
2069 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2070 use I2DEST as a scratch register will help. In the latter case,
2071 convert I2DEST to the mode of the source of NEWPAT if we can. */
2073 m_split = split_insns (newpat, i3);
2075 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2076 inputs of NEWPAT. */
2078 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2079 possible to try that as a scratch reg. This would require adding
2080 more code to make it work though. */
2082 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2084 /* If I2DEST is a hard register or the only use of a pseudo,
2085 we can change its mode. */
2086 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2087 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2088 && GET_CODE (i2dest) == REG
2089 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2090 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2091 && ! REG_USERVAR_P (i2dest))))
2092 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2095 m_split = split_insns (gen_rtx_PARALLEL
2097 gen_rtvec (2, newpat,
2098 gen_rtx_CLOBBER (VOIDmode,
2101 /* If the split with the mode-changed register didn't work, try
2102 the original register. */
2103 if (! m_split && ni2dest != i2dest)
2106 m_split = split_insns (gen_rtx_PARALLEL
2108 gen_rtvec (2, newpat,
2109 gen_rtx_CLOBBER (VOIDmode,
2115 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2117 m_split = PATTERN (m_split);
2118 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2119 if (insn_code_number >= 0)
2122 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2123 && (next_real_insn (i2) == i3
2124 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2127 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2128 newi2pat = PATTERN (m_split);
2130 i3set = single_set (NEXT_INSN (m_split));
2131 i2set = single_set (m_split);
2133 /* In case we changed the mode of I2DEST, replace it in the
2134 pseudo-register table here. We can't do it above in case this
2135 code doesn't get executed and we do a split the other way. */
2137 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2138 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2140 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2142 /* If I2 or I3 has multiple SETs, we won't know how to track
2143 register status, so don't use these insns. If I2's destination
2144 is used between I2 and I3, we also can't use these insns. */
2146 if (i2_code_number >= 0 && i2set && i3set
2147 && (next_real_insn (i2) == i3
2148 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2149 insn_code_number = recog_for_combine (&newi3pat, i3,
2151 if (insn_code_number >= 0)
2154 /* It is possible that both insns now set the destination of I3.
2155 If so, we must show an extra use of it. */
2157 if (insn_code_number >= 0)
2159 rtx new_i3_dest = SET_DEST (i3set);
2160 rtx new_i2_dest = SET_DEST (i2set);
2162 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2163 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2164 || GET_CODE (new_i3_dest) == SUBREG)
2165 new_i3_dest = XEXP (new_i3_dest, 0);
2167 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2168 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2169 || GET_CODE (new_i2_dest) == SUBREG)
2170 new_i2_dest = XEXP (new_i2_dest, 0);
2172 if (GET_CODE (new_i3_dest) == REG
2173 && GET_CODE (new_i2_dest) == REG
2174 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2175 REG_N_SETS (REGNO (new_i2_dest))++;
2179 /* If we can split it and use I2DEST, go ahead and see if that
2180 helps things be recognized. Verify that none of the registers
2181 are set between I2 and I3. */
2182 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2184 && GET_CODE (i2dest) == REG
2186 /* We need I2DEST in the proper mode. If it is a hard register
2187 or the only use of a pseudo, we can change its mode. */
2188 && (GET_MODE (*split) == GET_MODE (i2dest)
2189 || GET_MODE (*split) == VOIDmode
2190 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2191 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2192 && ! REG_USERVAR_P (i2dest)))
2193 && (next_real_insn (i2) == i3
2194 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2195 /* We can't overwrite I2DEST if its value is still used by
2197 && ! reg_referenced_p (i2dest, newpat))
2199 rtx newdest = i2dest;
2200 enum rtx_code split_code = GET_CODE (*split);
2201 enum machine_mode split_mode = GET_MODE (*split);
2203 /* Get NEWDEST as a register in the proper mode. We have already
2204 validated that we can do this. */
2205 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2207 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2209 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2210 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2213 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2214 an ASHIFT. This can occur if it was inside a PLUS and hence
2215 appeared to be a memory address. This is a kludge. */
2216 if (split_code == MULT
2217 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2218 && INTVAL (XEXP (*split, 1)) > 0
2219 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2221 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2222 XEXP (*split, 0), GEN_INT (i)));
2223 /* Update split_code because we may not have a multiply
2225 split_code = GET_CODE (*split);
2228 #ifdef INSN_SCHEDULING
2229 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2230 be written as a ZERO_EXTEND. */
2231 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2233 #ifdef LOAD_EXTEND_OP
2234 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2235 what it really is. */
2236 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2238 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2239 SUBREG_REG (*split)));
2242 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2243 SUBREG_REG (*split)));
2247 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2248 SUBST (*split, newdest);
2249 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2251 /* If the split point was a MULT and we didn't have one before,
2252 don't use one now. */
2253 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2254 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2258 /* Check for a case where we loaded from memory in a narrow mode and
2259 then sign extended it, but we need both registers. In that case,
2260 we have a PARALLEL with both loads from the same memory location.
2261 We can split this into a load from memory followed by a register-register
2262 copy. This saves at least one insn, more if register allocation can
2265 We cannot do this if the destination of the first assignment is a
2266 condition code register or cc0. We eliminate this case by making sure
2267 the SET_DEST and SET_SRC have the same mode.
2269 We cannot do this if the destination of the second assignment is
2270 a register that we have already assumed is zero-extended. Similarly
2271 for a SUBREG of such a register. */
2273 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2274 && GET_CODE (newpat) == PARALLEL
2275 && XVECLEN (newpat, 0) == 2
2276 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2277 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2278 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2279 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2280 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2281 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2282 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2283 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2285 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2286 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2287 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2288 (GET_CODE (temp) == REG
2289 && reg_nonzero_bits[REGNO (temp)] != 0
2290 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2291 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2292 && (reg_nonzero_bits[REGNO (temp)]
2293 != GET_MODE_MASK (word_mode))))
2294 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2295 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2296 (GET_CODE (temp) == REG
2297 && reg_nonzero_bits[REGNO (temp)] != 0
2298 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2299 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2300 && (reg_nonzero_bits[REGNO (temp)]
2301 != GET_MODE_MASK (word_mode)))))
2302 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2303 SET_SRC (XVECEXP (newpat, 0, 1)))
2304 && ! find_reg_note (i3, REG_UNUSED,
2305 SET_DEST (XVECEXP (newpat, 0, 0))))
2309 newi2pat = XVECEXP (newpat, 0, 0);
2310 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2311 newpat = XVECEXP (newpat, 0, 1);
2312 SUBST (SET_SRC (newpat),
2313 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2314 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2316 if (i2_code_number >= 0)
2317 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2319 if (insn_code_number >= 0)
2324 /* If we will be able to accept this, we have made a change to the
2325 destination of I3. This requires us to do a few adjustments. */
2326 PATTERN (i3) = newpat;
2327 adjust_for_new_dest (i3);
2329 /* I3 now uses what used to be its destination and which is
2330 now I2's destination. That means we need a LOG_LINK from
2331 I3 to I2. But we used to have one, so we still will.
2333 However, some later insn might be using I2's dest and have
2334 a LOG_LINK pointing at I3. We must remove this link.
2335 The simplest way to remove the link is to point it at I1,
2336 which we know will be a NOTE. */
2338 for (insn = NEXT_INSN (i3);
2339 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2340 || insn != BB_HEAD (this_basic_block->next_bb));
2341 insn = NEXT_INSN (insn))
2343 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2345 for (link = LOG_LINKS (insn); link;
2346 link = XEXP (link, 1))
2347 if (XEXP (link, 0) == i3)
2348 XEXP (link, 0) = i1;
2356 /* Similarly, check for a case where we have a PARALLEL of two independent
2357 SETs but we started with three insns. In this case, we can do the sets
2358 as two separate insns. This case occurs when some SET allows two
2359 other insns to combine, but the destination of that SET is still live. */
2361 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2362 && GET_CODE (newpat) == PARALLEL
2363 && XVECLEN (newpat, 0) == 2
2364 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2365 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2366 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2367 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2368 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2369 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2370 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2372 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2373 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2374 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2375 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2376 XVECEXP (newpat, 0, 0))
2377 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2378 XVECEXP (newpat, 0, 1))
2379 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2380 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2382 /* Normally, it doesn't matter which of the two is done first,
2383 but it does if one references cc0. In that case, it has to
2386 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2388 newi2pat = XVECEXP (newpat, 0, 0);
2389 newpat = XVECEXP (newpat, 0, 1);
2394 newi2pat = XVECEXP (newpat, 0, 1);
2395 newpat = XVECEXP (newpat, 0, 0);
2398 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2400 if (i2_code_number >= 0)
2401 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2404 /* If it still isn't recognized, fail and change things back the way they
2406 if ((insn_code_number < 0
2407 /* Is the result a reasonable ASM_OPERANDS? */
2408 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2414 /* If we had to change another insn, make sure it is valid also. */
2415 if (undobuf.other_insn)
2417 rtx other_pat = PATTERN (undobuf.other_insn);
2418 rtx new_other_notes;
2421 CLEAR_HARD_REG_SET (newpat_used_regs);
2423 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2426 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2432 PATTERN (undobuf.other_insn) = other_pat;
2434 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2435 are still valid. Then add any non-duplicate notes added by
2436 recog_for_combine. */
2437 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2439 next = XEXP (note, 1);
2441 if (REG_NOTE_KIND (note) == REG_UNUSED
2442 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2444 if (GET_CODE (XEXP (note, 0)) == REG)
2445 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2447 remove_note (undobuf.other_insn, note);
2451 for (note = new_other_notes; note; note = XEXP (note, 1))
2452 if (GET_CODE (XEXP (note, 0)) == REG)
2453 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2455 distribute_notes (new_other_notes, undobuf.other_insn,
2456 undobuf.other_insn, NULL_RTX);
2459 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2460 they are adjacent to each other or not. */
2462 rtx p = prev_nonnote_insn (i3);
2463 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2464 && sets_cc0_p (newi2pat))
2472 /* We now know that we can do this combination. Merge the insns and
2473 update the status of registers and LOG_LINKS. */
2476 rtx i3notes, i2notes, i1notes = 0;
2477 rtx i3links, i2links, i1links = 0;
2481 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2483 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2484 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2486 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2488 /* Ensure that we do not have something that should not be shared but
2489 occurs multiple times in the new insns. Check this by first
2490 resetting all the `used' flags and then copying anything is shared. */
2492 reset_used_flags (i3notes);
2493 reset_used_flags (i2notes);
2494 reset_used_flags (i1notes);
2495 reset_used_flags (newpat);
2496 reset_used_flags (newi2pat);
2497 if (undobuf.other_insn)
2498 reset_used_flags (PATTERN (undobuf.other_insn));
2500 i3notes = copy_rtx_if_shared (i3notes);
2501 i2notes = copy_rtx_if_shared (i2notes);
2502 i1notes = copy_rtx_if_shared (i1notes);
2503 newpat = copy_rtx_if_shared (newpat);
2504 newi2pat = copy_rtx_if_shared (newi2pat);
2505 if (undobuf.other_insn)
2506 reset_used_flags (PATTERN (undobuf.other_insn));
2508 INSN_CODE (i3) = insn_code_number;
2509 PATTERN (i3) = newpat;
2511 if (GET_CODE (i3) == CALL_INSN && CALL_INSN_FUNCTION_USAGE (i3))
2513 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2515 reset_used_flags (call_usage);
2516 call_usage = copy_rtx (call_usage);
2519 replace_rtx (call_usage, i2dest, i2src);
2522 replace_rtx (call_usage, i1dest, i1src);
2524 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2527 if (undobuf.other_insn)
2528 INSN_CODE (undobuf.other_insn) = other_code_number;
2530 /* We had one special case above where I2 had more than one set and
2531 we replaced a destination of one of those sets with the destination
2532 of I3. In that case, we have to update LOG_LINKS of insns later
2533 in this basic block. Note that this (expensive) case is rare.
2535 Also, in this case, we must pretend that all REG_NOTEs for I2
2536 actually came from I3, so that REG_UNUSED notes from I2 will be
2537 properly handled. */
2539 if (i3_subst_into_i2)
2541 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2542 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2543 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2544 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2545 && ! find_reg_note (i2, REG_UNUSED,
2546 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2547 for (temp = NEXT_INSN (i2);
2548 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2549 || BB_HEAD (this_basic_block) != temp);
2550 temp = NEXT_INSN (temp))
2551 if (temp != i3 && INSN_P (temp))
2552 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2553 if (XEXP (link, 0) == i2)
2554 XEXP (link, 0) = i3;
2559 while (XEXP (link, 1))
2560 link = XEXP (link, 1);
2561 XEXP (link, 1) = i2notes;
2575 INSN_CODE (i2) = i2_code_number;
2576 PATTERN (i2) = newi2pat;
2580 PUT_CODE (i2, NOTE);
2581 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2582 NOTE_SOURCE_FILE (i2) = 0;
2589 PUT_CODE (i1, NOTE);
2590 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2591 NOTE_SOURCE_FILE (i1) = 0;
2594 /* Get death notes for everything that is now used in either I3 or
2595 I2 and used to die in a previous insn. If we built two new
2596 patterns, move from I1 to I2 then I2 to I3 so that we get the
2597 proper movement on registers that I2 modifies. */
2601 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2602 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2605 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2608 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2610 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2612 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2614 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2616 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2618 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2619 know these are REG_UNUSED and want them to go to the desired insn,
2620 so we always pass it as i3. We have not counted the notes in
2621 reg_n_deaths yet, so we need to do so now. */
2623 if (newi2pat && new_i2_notes)
2625 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2626 if (GET_CODE (XEXP (temp, 0)) == REG)
2627 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2629 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2634 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2635 if (GET_CODE (XEXP (temp, 0)) == REG)
2636 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2638 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2641 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2642 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2643 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2644 in that case, it might delete I2. Similarly for I2 and I1.
2645 Show an additional death due to the REG_DEAD note we make here. If
2646 we discard it in distribute_notes, we will decrement it again. */
2650 if (GET_CODE (i3dest_killed) == REG)
2651 REG_N_DEATHS (REGNO (i3dest_killed))++;
2653 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2654 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2656 NULL_RTX, i2, NULL_RTX);
2658 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2660 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2663 if (i2dest_in_i2src)
2665 if (GET_CODE (i2dest) == REG)
2666 REG_N_DEATHS (REGNO (i2dest))++;
2668 if (newi2pat && reg_set_p (i2dest, newi2pat))
2669 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2670 NULL_RTX, i2, NULL_RTX);
2672 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2673 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2676 if (i1dest_in_i1src)
2678 if (GET_CODE (i1dest) == REG)
2679 REG_N_DEATHS (REGNO (i1dest))++;
2681 if (newi2pat && reg_set_p (i1dest, newi2pat))
2682 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2683 NULL_RTX, i2, NULL_RTX);
2685 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2686 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2689 distribute_links (i3links);
2690 distribute_links (i2links);
2691 distribute_links (i1links);
2693 if (GET_CODE (i2dest) == REG)
2696 rtx i2_insn = 0, i2_val = 0, set;
2698 /* The insn that used to set this register doesn't exist, and
2699 this life of the register may not exist either. See if one of
2700 I3's links points to an insn that sets I2DEST. If it does,
2701 that is now the last known value for I2DEST. If we don't update
2702 this and I2 set the register to a value that depended on its old
2703 contents, we will get confused. If this insn is used, thing
2704 will be set correctly in combine_instructions. */
2706 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2707 if ((set = single_set (XEXP (link, 0))) != 0
2708 && rtx_equal_p (i2dest, SET_DEST (set)))
2709 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2711 record_value_for_reg (i2dest, i2_insn, i2_val);
2713 /* If the reg formerly set in I2 died only once and that was in I3,
2714 zero its use count so it won't make `reload' do any work. */
2716 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2717 && ! i2dest_in_i2src)
2719 regno = REGNO (i2dest);
2720 REG_N_SETS (regno)--;
2724 if (i1 && GET_CODE (i1dest) == REG)
2727 rtx i1_insn = 0, i1_val = 0, set;
2729 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2730 if ((set = single_set (XEXP (link, 0))) != 0
2731 && rtx_equal_p (i1dest, SET_DEST (set)))
2732 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2734 record_value_for_reg (i1dest, i1_insn, i1_val);
2736 regno = REGNO (i1dest);
2737 if (! added_sets_1 && ! i1dest_in_i1src)
2738 REG_N_SETS (regno)--;
2741 /* Update reg_nonzero_bits et al for any changes that may have been made
2742 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2743 important. Because newi2pat can affect nonzero_bits of newpat */
2745 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2746 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2748 /* Set new_direct_jump_p if a new return or simple jump instruction
2751 If I3 is now an unconditional jump, ensure that it has a
2752 BARRIER following it since it may have initially been a
2753 conditional jump. It may also be the last nonnote insn. */
2755 if (returnjump_p (i3) || any_uncondjump_p (i3))
2757 *new_direct_jump_p = 1;
2758 mark_jump_label (PATTERN (i3), i3, 0);
2760 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2761 || GET_CODE (temp) != BARRIER)
2762 emit_barrier_after (i3);
2765 if (undobuf.other_insn != NULL_RTX
2766 && (returnjump_p (undobuf.other_insn)
2767 || any_uncondjump_p (undobuf.other_insn)))
2769 *new_direct_jump_p = 1;
2771 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2772 || GET_CODE (temp) != BARRIER)
2773 emit_barrier_after (undobuf.other_insn);
2776 /* An NOOP jump does not need barrier, but it does need cleaning up
2778 if (GET_CODE (newpat) == SET
2779 && SET_SRC (newpat) == pc_rtx
2780 && SET_DEST (newpat) == pc_rtx)
2781 *new_direct_jump_p = 1;
2784 combine_successes++;
2787 if (added_links_insn
2788 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2789 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2790 return added_links_insn;
2792 return newi2pat ? i2 : i3;
2795 /* Undo all the modifications recorded in undobuf. */
2800 struct undo *undo, *next;
2802 for (undo = undobuf.undos; undo; undo = next)
2806 *undo->where.i = undo->old_contents.i;
2808 *undo->where.r = undo->old_contents.r;
2810 undo->next = undobuf.frees;
2811 undobuf.frees = undo;
2817 /* We've committed to accepting the changes we made. Move all
2818 of the undos to the free list. */
2823 struct undo *undo, *next;
2825 for (undo = undobuf.undos; undo; undo = next)
2828 undo->next = undobuf.frees;
2829 undobuf.frees = undo;
2835 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2836 where we have an arithmetic expression and return that point. LOC will
2839 try_combine will call this function to see if an insn can be split into
2843 find_split_point (rtx *loc, rtx insn)
2846 enum rtx_code code = GET_CODE (x);
2848 unsigned HOST_WIDE_INT len = 0;
2849 HOST_WIDE_INT pos = 0;
2851 rtx inner = NULL_RTX;
2853 /* First special-case some codes. */
2857 #ifdef INSN_SCHEDULING
2858 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2860 if (GET_CODE (SUBREG_REG (x)) == MEM)
2863 return find_split_point (&SUBREG_REG (x), insn);
2867 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2868 using LO_SUM and HIGH. */
2869 if (GET_CODE (XEXP (x, 0)) == CONST
2870 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2873 gen_rtx_LO_SUM (Pmode,
2874 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
2876 return &XEXP (XEXP (x, 0), 0);
2880 /* If we have a PLUS whose second operand is a constant and the
2881 address is not valid, perhaps will can split it up using
2882 the machine-specific way to split large constants. We use
2883 the first pseudo-reg (one of the virtual regs) as a placeholder;
2884 it will not remain in the result. */
2885 if (GET_CODE (XEXP (x, 0)) == PLUS
2886 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2887 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2889 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2890 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2893 /* This should have produced two insns, each of which sets our
2894 placeholder. If the source of the second is a valid address,
2895 we can make put both sources together and make a split point
2899 && NEXT_INSN (seq) != NULL_RTX
2900 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
2901 && GET_CODE (seq) == INSN
2902 && GET_CODE (PATTERN (seq)) == SET
2903 && SET_DEST (PATTERN (seq)) == reg
2904 && ! reg_mentioned_p (reg,
2905 SET_SRC (PATTERN (seq)))
2906 && GET_CODE (NEXT_INSN (seq)) == INSN
2907 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
2908 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
2909 && memory_address_p (GET_MODE (x),
2910 SET_SRC (PATTERN (NEXT_INSN (seq)))))
2912 rtx src1 = SET_SRC (PATTERN (seq));
2913 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
2915 /* Replace the placeholder in SRC2 with SRC1. If we can
2916 find where in SRC2 it was placed, that can become our
2917 split point and we can replace this address with SRC2.
2918 Just try two obvious places. */
2920 src2 = replace_rtx (src2, reg, src1);
2922 if (XEXP (src2, 0) == src1)
2923 split = &XEXP (src2, 0);
2924 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2925 && XEXP (XEXP (src2, 0), 0) == src1)
2926 split = &XEXP (XEXP (src2, 0), 0);
2930 SUBST (XEXP (x, 0), src2);
2935 /* If that didn't work, perhaps the first operand is complex and
2936 needs to be computed separately, so make a split point there.
2937 This will occur on machines that just support REG + CONST
2938 and have a constant moved through some previous computation. */
2940 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2941 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2942 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2944 return &XEXP (XEXP (x, 0), 0);
2950 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2951 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2952 we need to put the operand into a register. So split at that
2955 if (SET_DEST (x) == cc0_rtx
2956 && GET_CODE (SET_SRC (x)) != COMPARE
2957 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2958 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2959 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2960 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2961 return &SET_SRC (x);
2964 /* See if we can split SET_SRC as it stands. */
2965 split = find_split_point (&SET_SRC (x), insn);
2966 if (split && split != &SET_SRC (x))
2969 /* See if we can split SET_DEST as it stands. */
2970 split = find_split_point (&SET_DEST (x), insn);
2971 if (split && split != &SET_DEST (x))
2974 /* See if this is a bitfield assignment with everything constant. If
2975 so, this is an IOR of an AND, so split it into that. */
2976 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2977 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2978 <= HOST_BITS_PER_WIDE_INT)
2979 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2980 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2981 && GET_CODE (SET_SRC (x)) == CONST_INT
2982 && ((INTVAL (XEXP (SET_DEST (x), 1))
2983 + INTVAL (XEXP (SET_DEST (x), 2)))
2984 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2985 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2987 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
2988 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
2989 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
2990 rtx dest = XEXP (SET_DEST (x), 0);
2991 enum machine_mode mode = GET_MODE (dest);
2992 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2994 if (BITS_BIG_ENDIAN)
2995 pos = GET_MODE_BITSIZE (mode) - len - pos;
2999 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3002 gen_binary (IOR, mode,
3003 gen_binary (AND, mode, dest,
3004 gen_int_mode (~(mask << pos),
3006 GEN_INT (src << pos)));
3008 SUBST (SET_DEST (x), dest);
3010 split = find_split_point (&SET_SRC (x), insn);
3011 if (split && split != &SET_SRC (x))
3015 /* Otherwise, see if this is an operation that we can split into two.
3016 If so, try to split that. */
3017 code = GET_CODE (SET_SRC (x));
3022 /* If we are AND'ing with a large constant that is only a single
3023 bit and the result is only being used in a context where we
3024 need to know if it is zero or nonzero, replace it with a bit
3025 extraction. This will avoid the large constant, which might
3026 have taken more than one insn to make. If the constant were
3027 not a valid argument to the AND but took only one insn to make,
3028 this is no worse, but if it took more than one insn, it will
3031 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3032 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3033 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3034 && GET_CODE (SET_DEST (x)) == REG
3035 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3036 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3037 && XEXP (*split, 0) == SET_DEST (x)
3038 && XEXP (*split, 1) == const0_rtx)
3040 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3041 XEXP (SET_SRC (x), 0),
3042 pos, NULL_RTX, 1, 1, 0, 0);
3043 if (extraction != 0)
3045 SUBST (SET_SRC (x), extraction);
3046 return find_split_point (loc, insn);
3052 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3053 is known to be on, this can be converted into a NEG of a shift. */
3054 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3055 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3056 && 1 <= (pos = exact_log2
3057 (nonzero_bits (XEXP (SET_SRC (x), 0),
3058 GET_MODE (XEXP (SET_SRC (x), 0))))))
3060 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3064 gen_rtx_LSHIFTRT (mode,
3065 XEXP (SET_SRC (x), 0),
3068 split = find_split_point (&SET_SRC (x), insn);
3069 if (split && split != &SET_SRC (x))
3075 inner = XEXP (SET_SRC (x), 0);
3077 /* We can't optimize if either mode is a partial integer
3078 mode as we don't know how many bits are significant
3080 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3081 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3085 len = GET_MODE_BITSIZE (GET_MODE (inner));
3091 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3092 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3094 inner = XEXP (SET_SRC (x), 0);
3095 len = INTVAL (XEXP (SET_SRC (x), 1));
3096 pos = INTVAL (XEXP (SET_SRC (x), 2));
3098 if (BITS_BIG_ENDIAN)
3099 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3100 unsignedp = (code == ZERO_EXTRACT);
3108 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3110 enum machine_mode mode = GET_MODE (SET_SRC (x));
3112 /* For unsigned, we have a choice of a shift followed by an
3113 AND or two shifts. Use two shifts for field sizes where the
3114 constant might be too large. We assume here that we can
3115 always at least get 8-bit constants in an AND insn, which is
3116 true for every current RISC. */
3118 if (unsignedp && len <= 8)
3123 (mode, gen_lowpart_for_combine (mode, inner),
3125 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3127 split = find_split_point (&SET_SRC (x), insn);
3128 if (split && split != &SET_SRC (x))
3135 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3136 gen_rtx_ASHIFT (mode,
3137 gen_lowpart_for_combine (mode, inner),
3138 GEN_INT (GET_MODE_BITSIZE (mode)
3140 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3142 split = find_split_point (&SET_SRC (x), insn);
3143 if (split && split != &SET_SRC (x))
3148 /* See if this is a simple operation with a constant as the second
3149 operand. It might be that this constant is out of range and hence
3150 could be used as a split point. */
3151 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3152 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3153 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3154 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3155 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3156 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3157 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3159 return &XEXP (SET_SRC (x), 1);
3161 /* Finally, see if this is a simple operation with its first operand
3162 not in a register. The operation might require this operand in a
3163 register, so return it as a split point. We can always do this
3164 because if the first operand were another operation, we would have
3165 already found it as a split point. */
3166 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3167 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3168 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3169 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3170 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3171 return &XEXP (SET_SRC (x), 0);
3177 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3178 it is better to write this as (not (ior A B)) so we can split it.
3179 Similarly for IOR. */
3180 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3183 gen_rtx_NOT (GET_MODE (x),
3184 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3186 XEXP (XEXP (x, 0), 0),
3187 XEXP (XEXP (x, 1), 0))));
3188 return find_split_point (loc, insn);
3191 /* Many RISC machines have a large set of logical insns. If the
3192 second operand is a NOT, put it first so we will try to split the
3193 other operand first. */
3194 if (GET_CODE (XEXP (x, 1)) == NOT)
3196 rtx tem = XEXP (x, 0);
3197 SUBST (XEXP (x, 0), XEXP (x, 1));
3198 SUBST (XEXP (x, 1), tem);
3206 /* Otherwise, select our actions depending on our rtx class. */
3207 switch (GET_RTX_CLASS (code))
3209 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3211 split = find_split_point (&XEXP (x, 2), insn);
3214 /* ... fall through ... */
3218 split = find_split_point (&XEXP (x, 1), insn);
3221 /* ... fall through ... */
3223 /* Some machines have (and (shift ...) ...) insns. If X is not
3224 an AND, but XEXP (X, 0) is, use it as our split point. */
3225 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3226 return &XEXP (x, 0);
3228 split = find_split_point (&XEXP (x, 0), insn);
3234 /* Otherwise, we don't have a split point. */
3238 /* Throughout X, replace FROM with TO, and return the result.
3239 The result is TO if X is FROM;
3240 otherwise the result is X, but its contents may have been modified.
3241 If they were modified, a record was made in undobuf so that
3242 undo_all will (among other things) return X to its original state.
3244 If the number of changes necessary is too much to record to undo,
3245 the excess changes are not made, so the result is invalid.
3246 The changes already made can still be undone.
3247 undobuf.num_undo is incremented for such changes, so by testing that
3248 the caller can tell whether the result is valid.
3250 `n_occurrences' is incremented each time FROM is replaced.
3252 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3254 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3255 by copying if `n_occurrences' is nonzero. */
3258 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3260 enum rtx_code code = GET_CODE (x);
3261 enum machine_mode op0_mode = VOIDmode;
3266 /* Two expressions are equal if they are identical copies of a shared
3267 RTX or if they are both registers with the same register number
3270 #define COMBINE_RTX_EQUAL_P(X,Y) \
3272 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3273 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3275 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3278 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3281 /* If X and FROM are the same register but different modes, they will
3282 not have been seen as equal above. However, flow.c will make a
3283 LOG_LINKS entry for that case. If we do nothing, we will try to
3284 rerecognize our original insn and, when it succeeds, we will
3285 delete the feeding insn, which is incorrect.
3287 So force this insn not to match in this (rare) case. */
3288 if (! in_dest && code == REG && GET_CODE (from) == REG
3289 && REGNO (x) == REGNO (from))
3290 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3292 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3293 of which may contain things that can be combined. */
3294 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3297 /* It is possible to have a subexpression appear twice in the insn.
3298 Suppose that FROM is a register that appears within TO.
3299 Then, after that subexpression has been scanned once by `subst',
3300 the second time it is scanned, TO may be found. If we were
3301 to scan TO here, we would find FROM within it and create a
3302 self-referent rtl structure which is completely wrong. */
3303 if (COMBINE_RTX_EQUAL_P (x, to))
3306 /* Parallel asm_operands need special attention because all of the
3307 inputs are shared across the arms. Furthermore, unsharing the
3308 rtl results in recognition failures. Failure to handle this case
3309 specially can result in circular rtl.
3311 Solve this by doing a normal pass across the first entry of the
3312 parallel, and only processing the SET_DESTs of the subsequent
3315 if (code == PARALLEL
3316 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3317 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3319 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3321 /* If this substitution failed, this whole thing fails. */
3322 if (GET_CODE (new) == CLOBBER
3323 && XEXP (new, 0) == const0_rtx)
3326 SUBST (XVECEXP (x, 0, 0), new);
3328 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3330 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3332 if (GET_CODE (dest) != REG
3333 && GET_CODE (dest) != CC0
3334 && GET_CODE (dest) != PC)
3336 new = subst (dest, from, to, 0, unique_copy);
3338 /* If this substitution failed, this whole thing fails. */
3339 if (GET_CODE (new) == CLOBBER
3340 && XEXP (new, 0) == const0_rtx)
3343 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3349 len = GET_RTX_LENGTH (code);
3350 fmt = GET_RTX_FORMAT (code);
3352 /* We don't need to process a SET_DEST that is a register, CC0,
3353 or PC, so set up to skip this common case. All other cases
3354 where we want to suppress replacing something inside a
3355 SET_SRC are handled via the IN_DEST operand. */
3357 && (GET_CODE (SET_DEST (x)) == REG
3358 || GET_CODE (SET_DEST (x)) == CC0
3359 || GET_CODE (SET_DEST (x)) == PC))
3362 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3365 op0_mode = GET_MODE (XEXP (x, 0));
3367 for (i = 0; i < len; i++)
3372 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3374 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3376 new = (unique_copy && n_occurrences
3377 ? copy_rtx (to) : to);
3382 new = subst (XVECEXP (x, i, j), from, to, 0,
3385 /* If this substitution failed, this whole thing
3387 if (GET_CODE (new) == CLOBBER
3388 && XEXP (new, 0) == const0_rtx)
3392 SUBST (XVECEXP (x, i, j), new);
3395 else if (fmt[i] == 'e')
3397 /* If this is a register being set, ignore it. */
3400 && (code == SUBREG || code == STRICT_LOW_PART
3401 || code == ZERO_EXTRACT)
3403 && GET_CODE (new) == REG)
3406 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3408 /* In general, don't install a subreg involving two
3409 modes not tieable. It can worsen register
3410 allocation, and can even make invalid reload
3411 insns, since the reg inside may need to be copied
3412 from in the outside mode, and that may be invalid
3413 if it is an fp reg copied in integer mode.
3415 We allow two exceptions to this: It is valid if
3416 it is inside another SUBREG and the mode of that
3417 SUBREG and the mode of the inside of TO is
3418 tieable and it is valid if X is a SET that copies
3421 if (GET_CODE (to) == SUBREG
3422 && ! MODES_TIEABLE_P (GET_MODE (to),
3423 GET_MODE (SUBREG_REG (to)))
3424 && ! (code == SUBREG
3425 && MODES_TIEABLE_P (GET_MODE (x),
3426 GET_MODE (SUBREG_REG (to))))
3428 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3431 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3433 #ifdef CANNOT_CHANGE_MODE_CLASS
3435 && GET_CODE (to) == REG
3436 && REGNO (to) < FIRST_PSEUDO_REGISTER
3437 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3440 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3443 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3447 /* If we are in a SET_DEST, suppress most cases unless we
3448 have gone inside a MEM, in which case we want to
3449 simplify the address. We assume here that things that
3450 are actually part of the destination have their inner
3451 parts in the first expression. This is true for SUBREG,
3452 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3453 things aside from REG and MEM that should appear in a
3455 new = subst (XEXP (x, i), from, to,
3457 && (code == SUBREG || code == STRICT_LOW_PART
3458 || code == ZERO_EXTRACT))
3460 && i == 0), unique_copy);
3462 /* If we found that we will have to reject this combination,
3463 indicate that by returning the CLOBBER ourselves, rather than
3464 an expression containing it. This will speed things up as
3465 well as prevent accidents where two CLOBBERs are considered
3466 to be equal, thus producing an incorrect simplification. */
3468 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3471 if (GET_CODE (x) == SUBREG
3472 && (GET_CODE (new) == CONST_INT
3473 || GET_CODE (new) == CONST_DOUBLE))
3475 enum machine_mode mode = GET_MODE (x);
3477 x = simplify_subreg (GET_MODE (x), new,
3478 GET_MODE (SUBREG_REG (x)),
3481 x = gen_rtx_CLOBBER (mode, const0_rtx);
3483 else if (GET_CODE (new) == CONST_INT
3484 && GET_CODE (x) == ZERO_EXTEND)
3486 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3487 new, GET_MODE (XEXP (x, 0)));
3492 SUBST (XEXP (x, i), new);
3497 /* Try to simplify X. If the simplification changed the code, it is likely
3498 that further simplification will help, so loop, but limit the number
3499 of repetitions that will be performed. */
3501 for (i = 0; i < 4; i++)
3503 /* If X is sufficiently simple, don't bother trying to do anything
3505 if (code != CONST_INT && code != REG && code != CLOBBER)
3506 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3508 if (GET_CODE (x) == code)
3511 code = GET_CODE (x);
3513 /* We no longer know the original mode of operand 0 since we
3514 have changed the form of X) */
3515 op0_mode = VOIDmode;
3521 /* Simplify X, a piece of RTL. We just operate on the expression at the
3522 outer level; call `subst' to simplify recursively. Return the new
3525 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3526 will be the iteration even if an expression with a code different from
3527 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3530 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int last,
3533 enum rtx_code code = GET_CODE (x);
3534 enum machine_mode mode = GET_MODE (x);
3539 /* If this is a commutative operation, put a constant last and a complex
3540 expression first. We don't need to do this for comparisons here. */
3541 if (GET_RTX_CLASS (code) == 'c'
3542 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3545 SUBST (XEXP (x, 0), XEXP (x, 1));
3546 SUBST (XEXP (x, 1), temp);
3549 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3550 sign extension of a PLUS with a constant, reverse the order of the sign
3551 extension and the addition. Note that this not the same as the original
3552 code, but overflow is undefined for signed values. Also note that the
3553 PLUS will have been partially moved "inside" the sign-extension, so that
3554 the first operand of X will really look like:
3555 (ashiftrt (plus (ashift A C4) C5) C4).
3557 (plus (ashiftrt (ashift A C4) C2) C4)
3558 and replace the first operand of X with that expression. Later parts
3559 of this function may simplify the expression further.
3561 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3562 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3563 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3565 We do this to simplify address expressions. */
3567 if ((code == PLUS || code == MINUS || code == MULT)
3568 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3569 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3570 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3571 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3572 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3573 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3574 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3575 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3576 XEXP (XEXP (XEXP (x, 0), 0), 1),
3577 XEXP (XEXP (x, 0), 1))) != 0)
3580 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3581 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3582 INTVAL (XEXP (XEXP (x, 0), 1)));
3584 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3585 INTVAL (XEXP (XEXP (x, 0), 1)));
3587 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3590 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3591 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3592 things. Check for cases where both arms are testing the same
3595 Don't do anything if all operands are very simple. */
3597 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3598 || GET_RTX_CLASS (code) == '<')
3599 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3600 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3601 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3603 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3604 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3605 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3607 || (GET_RTX_CLASS (code) == '1'
3608 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3609 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3610 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3613 rtx cond, true_rtx, false_rtx;
3615 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3617 /* If everything is a comparison, what we have is highly unlikely
3618 to be simpler, so don't use it. */
3619 && ! (GET_RTX_CLASS (code) == '<'
3620 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3621 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3623 rtx cop1 = const0_rtx;
3624 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3626 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3629 /* Simplify the alternative arms; this may collapse the true and
3630 false arms to store-flag values. Be careful to use copy_rtx
3631 here since true_rtx or false_rtx might share RTL with x as a
3632 result of the if_then_else_cond call above. */
3633 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3634 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3636 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3637 is unlikely to be simpler. */
3638 if (general_operand (true_rtx, VOIDmode)
3639 && general_operand (false_rtx, VOIDmode))
3641 enum rtx_code reversed;
3643 /* Restarting if we generate a store-flag expression will cause
3644 us to loop. Just drop through in this case. */
3646 /* If the result values are STORE_FLAG_VALUE and zero, we can
3647 just make the comparison operation. */
3648 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3649 x = gen_binary (cond_code, mode, cond, cop1);
3650 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3651 && ((reversed = reversed_comparison_code_parts
3652 (cond_code, cond, cop1, NULL))
3654 x = gen_binary (reversed, mode, cond, cop1);
3656 /* Likewise, we can make the negate of a comparison operation
3657 if the result values are - STORE_FLAG_VALUE and zero. */
3658 else if (GET_CODE (true_rtx) == CONST_INT
3659 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3660 && false_rtx == const0_rtx)
3661 x = simplify_gen_unary (NEG, mode,
3662 gen_binary (cond_code, mode, cond,
3665 else if (GET_CODE (false_rtx) == CONST_INT
3666 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3667 && true_rtx == const0_rtx
3668 && ((reversed = reversed_comparison_code_parts
3669 (cond_code, cond, cop1, NULL))
3671 x = simplify_gen_unary (NEG, mode,
3672 gen_binary (reversed, mode,
3676 return gen_rtx_IF_THEN_ELSE (mode,
3677 gen_binary (cond_code, VOIDmode,
3679 true_rtx, false_rtx);
3681 code = GET_CODE (x);
3682 op0_mode = VOIDmode;
3687 /* Try to fold this expression in case we have constants that weren't
3690 switch (GET_RTX_CLASS (code))
3693 if (op0_mode == VOIDmode)
3694 op0_mode = GET_MODE (XEXP (x, 0));
3695 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3699 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3700 if (cmp_mode == VOIDmode)
3702 cmp_mode = GET_MODE (XEXP (x, 1));
3703 if (cmp_mode == VOIDmode)
3704 cmp_mode = op0_mode;
3706 temp = simplify_relational_operation (code, cmp_mode,
3707 XEXP (x, 0), XEXP (x, 1));
3709 #ifdef FLOAT_STORE_FLAG_VALUE
3710 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3712 if (temp == const0_rtx)
3713 temp = CONST0_RTX (mode);
3715 temp = CONST_DOUBLE_FROM_REAL_VALUE (FLOAT_STORE_FLAG_VALUE (mode),
3722 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3726 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3727 XEXP (x, 1), XEXP (x, 2));
3734 code = GET_CODE (temp);
3735 op0_mode = VOIDmode;
3736 mode = GET_MODE (temp);
3739 /* First see if we can apply the inverse distributive law. */
3740 if (code == PLUS || code == MINUS
3741 || code == AND || code == IOR || code == XOR)
3743 x = apply_distributive_law (x);
3744 code = GET_CODE (x);
3745 op0_mode = VOIDmode;
3748 /* If CODE is an associative operation not otherwise handled, see if we
3749 can associate some operands. This can win if they are constants or
3750 if they are logically related (i.e. (a & b) & a). */
3751 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3752 || code == AND || code == IOR || code == XOR
3753 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3754 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3755 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3757 if (GET_CODE (XEXP (x, 0)) == code)
3759 rtx other = XEXP (XEXP (x, 0), 0);
3760 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3761 rtx inner_op1 = XEXP (x, 1);
3764 /* Make sure we pass the constant operand if any as the second
3765 one if this is a commutative operation. */
3766 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3768 rtx tem = inner_op0;
3769 inner_op0 = inner_op1;
3772 inner = simplify_binary_operation (code == MINUS ? PLUS
3773 : code == DIV ? MULT
3775 mode, inner_op0, inner_op1);
3777 /* For commutative operations, try the other pair if that one
3779 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3781 other = XEXP (XEXP (x, 0), 1);
3782 inner = simplify_binary_operation (code, mode,
3783 XEXP (XEXP (x, 0), 0),
3788 return gen_binary (code, mode, other, inner);
3792 /* A little bit of algebraic simplification here. */
3796 /* Ensure that our address has any ASHIFTs converted to MULT in case
3797 address-recognizing predicates are called later. */
3798 temp = make_compound_operation (XEXP (x, 0), MEM);
3799 SUBST (XEXP (x, 0), temp);
3803 if (op0_mode == VOIDmode)
3804 op0_mode = GET_MODE (SUBREG_REG (x));
3806 /* simplify_subreg can't use gen_lowpart_for_combine. */
3807 if (CONSTANT_P (SUBREG_REG (x))
3808 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3809 /* Don't call gen_lowpart_for_combine if the inner mode
3810 is VOIDmode and we cannot simplify it, as SUBREG without
3811 inner mode is invalid. */
3812 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3813 || gen_lowpart_common (mode, SUBREG_REG (x))))
3814 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3816 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3820 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3826 /* Don't change the mode of the MEM if that would change the meaning
3828 if (GET_CODE (SUBREG_REG (x)) == MEM
3829 && (MEM_VOLATILE_P (SUBREG_REG (x))
3830 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3831 return gen_rtx_CLOBBER (mode, const0_rtx);
3833 /* Note that we cannot do any narrowing for non-constants since
3834 we might have been counting on using the fact that some bits were
3835 zero. We now do this in the SET. */
3840 if (GET_CODE (XEXP (x, 0)) == SUBREG
3841 && subreg_lowpart_p (XEXP (x, 0))
3842 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3843 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3844 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3845 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3847 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3849 x = gen_rtx_ROTATE (inner_mode,
3850 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3852 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3853 return gen_lowpart_for_combine (mode, x);
3856 /* Apply De Morgan's laws to reduce number of patterns for machines
3857 with negating logical insns (and-not, nand, etc.). If result has
3858 only one NOT, put it first, since that is how the patterns are
3861 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3863 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3864 enum machine_mode op_mode;
3866 op_mode = GET_MODE (in1);
3867 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
3869 op_mode = GET_MODE (in2);
3870 if (op_mode == VOIDmode)
3872 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
3874 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
3877 in2 = in1; in1 = tem;
3880 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3886 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3887 if (GET_CODE (XEXP (x, 0)) == XOR
3888 && XEXP (XEXP (x, 0), 1) == const1_rtx
3889 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3890 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3892 temp = expand_compound_operation (XEXP (x, 0));
3894 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3895 replaced by (lshiftrt X C). This will convert
3896 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3898 if (GET_CODE (temp) == ASHIFTRT
3899 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3900 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3901 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3902 INTVAL (XEXP (temp, 1)));
3904 /* If X has only a single bit that might be nonzero, say, bit I, convert
3905 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3906 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3907 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3908 or a SUBREG of one since we'd be making the expression more
3909 complex if it was just a register. */
3911 if (GET_CODE (temp) != REG
3912 && ! (GET_CODE (temp) == SUBREG
3913 && GET_CODE (SUBREG_REG (temp)) == REG)
3914 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3916 rtx temp1 = simplify_shift_const
3917 (NULL_RTX, ASHIFTRT, mode,
3918 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3919 GET_MODE_BITSIZE (mode) - 1 - i),
3920 GET_MODE_BITSIZE (mode) - 1 - i);
3922 /* If all we did was surround TEMP with the two shifts, we
3923 haven't improved anything, so don't use it. Otherwise,
3924 we are better off with TEMP1. */
3925 if (GET_CODE (temp1) != ASHIFTRT
3926 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3927 || XEXP (XEXP (temp1, 0), 0) != temp)
3933 /* We can't handle truncation to a partial integer mode here
3934 because we don't know the real bitsize of the partial
3936 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3939 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3940 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3941 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3943 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3944 GET_MODE_MASK (mode), NULL_RTX, 0));
3946 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3947 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3948 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3949 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3950 return XEXP (XEXP (x, 0), 0);
3952 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3953 (OP:SI foo:SI) if OP is NEG or ABS. */
3954 if ((GET_CODE (XEXP (x, 0)) == ABS
3955 || GET_CODE (XEXP (x, 0)) == NEG)
3956 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3957 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3958 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3959 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
3960 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
3962 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3964 if (GET_CODE (XEXP (x, 0)) == SUBREG
3965 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3966 && subreg_lowpart_p (XEXP (x, 0)))
3967 return SUBREG_REG (XEXP (x, 0));
3969 /* If we know that the value is already truncated, we can
3970 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
3971 is nonzero for the corresponding modes. But don't do this
3972 for an (LSHIFTRT (MULT ...)) since this will cause problems
3973 with the umulXi3_highpart patterns. */
3974 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3975 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3976 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3977 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
3978 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
3979 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
3980 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3982 /* A truncate of a comparison can be replaced with a subreg if
3983 STORE_FLAG_VALUE permits. This is like the previous test,
3984 but it works even if the comparison is done in a mode larger
3985 than HOST_BITS_PER_WIDE_INT. */
3986 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3987 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3988 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
3989 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3991 /* Similarly, a truncate of a register whose value is a
3992 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3994 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3995 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
3996 && (temp = get_last_value (XEXP (x, 0)))
3997 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3998 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4002 case FLOAT_TRUNCATE:
4003 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4004 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4005 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4006 return XEXP (XEXP (x, 0), 0);
4008 /* (float_truncate:SF (float_truncate:DF foo:XF))
4009 = (float_truncate:SF foo:XF).
4010 This may eliminate double rounding, so it is unsafe.
4012 (float_truncate:SF (float_extend:XF foo:DF))
4013 = (float_truncate:SF foo:DF).
4015 (float_truncate:DF (float_extend:XF foo:SF))
4016 = (float_extend:SF foo:DF). */
4017 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4018 && flag_unsafe_math_optimizations)
4019 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4020 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4022 > GET_MODE_SIZE (mode)
4023 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4025 XEXP (XEXP (x, 0), 0), mode);
4027 /* (float_truncate (float x)) is (float x) */
4028 if (GET_CODE (XEXP (x, 0)) == FLOAT
4029 && (flag_unsafe_math_optimizations
4030 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4031 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4032 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4033 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4034 return simplify_gen_unary (FLOAT, mode,
4035 XEXP (XEXP (x, 0), 0),
4036 GET_MODE (XEXP (XEXP (x, 0), 0)));
4038 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4039 (OP:SF foo:SF) if OP is NEG or ABS. */
4040 if ((GET_CODE (XEXP (x, 0)) == ABS
4041 || GET_CODE (XEXP (x, 0)) == NEG)
4042 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4043 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4044 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4045 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4047 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4048 is (float_truncate:SF x). */
4049 if (GET_CODE (XEXP (x, 0)) == SUBREG
4050 && subreg_lowpart_p (XEXP (x, 0))
4051 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4052 return SUBREG_REG (XEXP (x, 0));
4055 /* (float_extend (float_extend x)) is (float_extend x)
4057 (float_extend (float x)) is (float x) assuming that double
4058 rounding can't happen.
4060 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4061 || (GET_CODE (XEXP (x, 0)) == FLOAT
4062 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4063 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4064 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4065 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4066 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4067 XEXP (XEXP (x, 0), 0),
4068 GET_MODE (XEXP (XEXP (x, 0), 0)));
4073 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4074 using cc0, in which case we want to leave it as a COMPARE
4075 so we can distinguish it from a register-register-copy. */
4076 if (XEXP (x, 1) == const0_rtx)
4079 /* x - 0 is the same as x unless x's mode has signed zeros and
4080 allows rounding towards -infinity. Under those conditions,
4082 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4083 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4084 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4090 /* (const (const X)) can become (const X). Do it this way rather than
4091 returning the inner CONST since CONST can be shared with a
4093 if (GET_CODE (XEXP (x, 0)) == CONST)
4094 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4099 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4100 can add in an offset. find_split_point will split this address up
4101 again if it doesn't match. */
4102 if (GET_CODE (XEXP (x, 0)) == HIGH
4103 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4109 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4111 if (GET_CODE (XEXP (x, 0)) == MULT
4112 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4116 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4117 in2 = XEXP (XEXP (x, 0), 1);
4118 return gen_binary (MINUS, mode, XEXP (x, 1),
4119 gen_binary (MULT, mode, in1, in2));
4122 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4123 outermost. That's because that's the way indexed addresses are
4124 supposed to appear. This code used to check many more cases, but
4125 they are now checked elsewhere. */
4126 if (GET_CODE (XEXP (x, 0)) == PLUS
4127 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4128 return gen_binary (PLUS, mode,
4129 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4131 XEXP (XEXP (x, 0), 1));
4133 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4134 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4135 bit-field and can be replaced by either a sign_extend or a
4136 sign_extract. The `and' may be a zero_extend and the two
4137 <c>, -<c> constants may be reversed. */
4138 if (GET_CODE (XEXP (x, 0)) == XOR
4139 && GET_CODE (XEXP (x, 1)) == CONST_INT
4140 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4141 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4142 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4143 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4144 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4145 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4146 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4147 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4148 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4149 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4150 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4151 == (unsigned int) i + 1))))
4152 return simplify_shift_const
4153 (NULL_RTX, ASHIFTRT, mode,
4154 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4155 XEXP (XEXP (XEXP (x, 0), 0), 0),
4156 GET_MODE_BITSIZE (mode) - (i + 1)),
4157 GET_MODE_BITSIZE (mode) - (i + 1));
4159 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4160 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4161 is 1. This produces better code than the alternative immediately
4163 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4164 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4165 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4166 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4167 XEXP (XEXP (x, 0), 0),
4168 XEXP (XEXP (x, 0), 1))))
4170 simplify_gen_unary (NEG, mode, reversed, mode);
4172 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4173 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4174 the bitsize of the mode - 1. This allows simplification of
4175 "a = (b & 8) == 0;" */
4176 if (XEXP (x, 1) == constm1_rtx
4177 && GET_CODE (XEXP (x, 0)) != REG
4178 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4179 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4180 && nonzero_bits (XEXP (x, 0), mode) == 1)
4181 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4182 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4183 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4184 GET_MODE_BITSIZE (mode) - 1),
4185 GET_MODE_BITSIZE (mode) - 1);
4187 /* If we are adding two things that have no bits in common, convert
4188 the addition into an IOR. This will often be further simplified,
4189 for example in cases like ((a & 1) + (a & 2)), which can
4192 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4193 && (nonzero_bits (XEXP (x, 0), mode)
4194 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4196 /* Try to simplify the expression further. */
4197 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4198 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4200 /* If we could, great. If not, do not go ahead with the IOR
4201 replacement, since PLUS appears in many special purpose
4202 address arithmetic instructions. */
4203 if (GET_CODE (temp) != CLOBBER && temp != tor)
4209 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4210 by reversing the comparison code if valid. */
4211 if (STORE_FLAG_VALUE == 1
4212 && XEXP (x, 0) == const1_rtx
4213 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4214 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4215 XEXP (XEXP (x, 1), 0),
4216 XEXP (XEXP (x, 1), 1))))
4219 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4220 (and <foo> (const_int pow2-1)) */
4221 if (GET_CODE (XEXP (x, 1)) == AND
4222 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4223 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4224 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4225 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4226 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4228 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4230 if (GET_CODE (XEXP (x, 1)) == MULT
4231 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4235 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4236 in2 = XEXP (XEXP (x, 1), 1);
4237 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4241 /* Canonicalize (minus (neg A) (mult B C)) to
4242 (minus (mult (neg B) C) A). */
4243 if (GET_CODE (XEXP (x, 1)) == MULT
4244 && GET_CODE (XEXP (x, 0)) == NEG)
4248 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4249 in2 = XEXP (XEXP (x, 1), 1);
4250 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4251 XEXP (XEXP (x, 0), 0));
4254 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4256 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4257 return gen_binary (MINUS, mode,
4258 gen_binary (MINUS, mode, XEXP (x, 0),
4259 XEXP (XEXP (x, 1), 0)),
4260 XEXP (XEXP (x, 1), 1));
4264 /* If we have (mult (plus A B) C), apply the distributive law and then
4265 the inverse distributive law to see if things simplify. This
4266 occurs mostly in addresses, often when unrolling loops. */
4268 if (GET_CODE (XEXP (x, 0)) == PLUS)
4270 x = apply_distributive_law
4271 (gen_binary (PLUS, mode,
4272 gen_binary (MULT, mode,
4273 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4274 gen_binary (MULT, mode,
4275 XEXP (XEXP (x, 0), 1),
4276 copy_rtx (XEXP (x, 1)))));
4278 if (GET_CODE (x) != MULT)
4281 /* Try simplify a*(b/c) as (a*b)/c. */
4282 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4283 && GET_CODE (XEXP (x, 0)) == DIV)
4285 rtx tem = simplify_binary_operation (MULT, mode,
4286 XEXP (XEXP (x, 0), 0),
4289 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4294 /* If this is a divide by a power of two, treat it as a shift if
4295 its first operand is a shift. */
4296 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4297 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4298 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4299 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4300 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4301 || GET_CODE (XEXP (x, 0)) == ROTATE
4302 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4303 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4307 case GT: case GTU: case GE: case GEU:
4308 case LT: case LTU: case LE: case LEU:
4309 case UNEQ: case LTGT:
4310 case UNGT: case UNGE:
4311 case UNLT: case UNLE:
4312 case UNORDERED: case ORDERED:
4313 /* If the first operand is a condition code, we can't do anything
4315 if (GET_CODE (XEXP (x, 0)) == COMPARE
4316 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4317 && ! CC0_P (XEXP (x, 0))))
4319 rtx op0 = XEXP (x, 0);
4320 rtx op1 = XEXP (x, 1);
4321 enum rtx_code new_code;
4323 if (GET_CODE (op0) == COMPARE)
4324 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4326 /* Simplify our comparison, if possible. */
4327 new_code = simplify_comparison (code, &op0, &op1);
4329 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4330 if only the low-order bit is possibly nonzero in X (such as when
4331 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4332 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4333 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4336 Remove any ZERO_EXTRACT we made when thinking this was a
4337 comparison. It may now be simpler to use, e.g., an AND. If a
4338 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4339 the call to make_compound_operation in the SET case. */
4341 if (STORE_FLAG_VALUE == 1
4342 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4343 && op1 == const0_rtx
4344 && mode == GET_MODE (op0)
4345 && nonzero_bits (op0, mode) == 1)
4346 return gen_lowpart_for_combine (mode,
4347 expand_compound_operation (op0));
4349 else if (STORE_FLAG_VALUE == 1
4350 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4351 && op1 == const0_rtx
4352 && mode == GET_MODE (op0)
4353 && (num_sign_bit_copies (op0, mode)
4354 == GET_MODE_BITSIZE (mode)))
4356 op0 = expand_compound_operation (op0);
4357 return simplify_gen_unary (NEG, mode,
4358 gen_lowpart_for_combine (mode, op0),
4362 else if (STORE_FLAG_VALUE == 1
4363 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4364 && op1 == const0_rtx
4365 && mode == GET_MODE (op0)
4366 && nonzero_bits (op0, mode) == 1)
4368 op0 = expand_compound_operation (op0);
4369 return gen_binary (XOR, mode,
4370 gen_lowpart_for_combine (mode, op0),
4374 else if (STORE_FLAG_VALUE == 1
4375 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4376 && op1 == const0_rtx
4377 && mode == GET_MODE (op0)
4378 && (num_sign_bit_copies (op0, mode)
4379 == GET_MODE_BITSIZE (mode)))
4381 op0 = expand_compound_operation (op0);
4382 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4385 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4387 if (STORE_FLAG_VALUE == -1
4388 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4389 && op1 == const0_rtx
4390 && (num_sign_bit_copies (op0, mode)
4391 == GET_MODE_BITSIZE (mode)))
4392 return gen_lowpart_for_combine (mode,
4393 expand_compound_operation (op0));
4395 else if (STORE_FLAG_VALUE == -1
4396 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4397 && op1 == const0_rtx
4398 && mode == GET_MODE (op0)
4399 && nonzero_bits (op0, mode) == 1)
4401 op0 = expand_compound_operation (op0);
4402 return simplify_gen_unary (NEG, mode,
4403 gen_lowpart_for_combine (mode, op0),
4407 else if (STORE_FLAG_VALUE == -1
4408 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4409 && op1 == const0_rtx
4410 && mode == GET_MODE (op0)
4411 && (num_sign_bit_copies (op0, mode)
4412 == GET_MODE_BITSIZE (mode)))
4414 op0 = expand_compound_operation (op0);
4415 return simplify_gen_unary (NOT, mode,
4416 gen_lowpart_for_combine (mode, op0),
4420 /* If X is 0/1, (eq X 0) is X-1. */
4421 else if (STORE_FLAG_VALUE == -1
4422 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4423 && op1 == const0_rtx
4424 && mode == GET_MODE (op0)
4425 && nonzero_bits (op0, mode) == 1)
4427 op0 = expand_compound_operation (op0);
4428 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4431 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4432 one bit that might be nonzero, we can convert (ne x 0) to
4433 (ashift x c) where C puts the bit in the sign bit. Remove any
4434 AND with STORE_FLAG_VALUE when we are done, since we are only
4435 going to test the sign bit. */
4436 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4437 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4438 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4439 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4440 && op1 == const0_rtx
4441 && mode == GET_MODE (op0)
4442 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4444 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4445 expand_compound_operation (op0),
4446 GET_MODE_BITSIZE (mode) - 1 - i);
4447 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4453 /* If the code changed, return a whole new comparison. */
4454 if (new_code != code)
4455 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4457 /* Otherwise, keep this operation, but maybe change its operands.
4458 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4459 SUBST (XEXP (x, 0), op0);
4460 SUBST (XEXP (x, 1), op1);
4465 return simplify_if_then_else (x);
4471 /* If we are processing SET_DEST, we are done. */
4475 return expand_compound_operation (x);
4478 return simplify_set (x);
4483 return simplify_logical (x, last);
4486 /* (abs (neg <foo>)) -> (abs <foo>) */
4487 if (GET_CODE (XEXP (x, 0)) == NEG)
4488 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4490 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4492 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4495 /* If operand is something known to be positive, ignore the ABS. */
4496 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4497 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4498 <= HOST_BITS_PER_WIDE_INT)
4499 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4500 & ((HOST_WIDE_INT) 1
4501 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4505 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4506 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4507 return gen_rtx_NEG (mode, XEXP (x, 0));
4512 /* (ffs (*_extend <X>)) = (ffs <X>) */
4513 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4514 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4515 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4520 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4521 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4522 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4526 /* (float (sign_extend <X>)) = (float <X>). */
4527 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4528 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4536 /* If this is a shift by a constant amount, simplify it. */
4537 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4538 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4539 INTVAL (XEXP (x, 1)));
4541 #ifdef SHIFT_COUNT_TRUNCATED
4542 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4544 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4546 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4555 rtx op0 = XEXP (x, 0);
4556 rtx op1 = XEXP (x, 1);
4559 if (GET_CODE (op1) != PARALLEL)
4561 len = XVECLEN (op1, 0);
4563 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4564 && GET_CODE (op0) == VEC_CONCAT)
4566 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4568 /* Try to find the element in the VEC_CONCAT. */
4571 if (GET_MODE (op0) == GET_MODE (x))
4573 if (GET_CODE (op0) == VEC_CONCAT)
4575 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4576 if (op0_size < offset)
4577 op0 = XEXP (op0, 0);
4581 op0 = XEXP (op0, 1);
4599 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4602 simplify_if_then_else (rtx x)
4604 enum machine_mode mode = GET_MODE (x);
4605 rtx cond = XEXP (x, 0);
4606 rtx true_rtx = XEXP (x, 1);
4607 rtx false_rtx = XEXP (x, 2);
4608 enum rtx_code true_code = GET_CODE (cond);
4609 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4612 enum rtx_code false_code;
4615 /* Simplify storing of the truth value. */
4616 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4617 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4619 /* Also when the truth value has to be reversed. */
4621 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4622 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4626 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4627 in it is being compared against certain values. Get the true and false
4628 comparisons and see if that says anything about the value of each arm. */
4631 && ((false_code = combine_reversed_comparison_code (cond))
4633 && GET_CODE (XEXP (cond, 0)) == REG)
4636 rtx from = XEXP (cond, 0);
4637 rtx true_val = XEXP (cond, 1);
4638 rtx false_val = true_val;
4641 /* If FALSE_CODE is EQ, swap the codes and arms. */
4643 if (false_code == EQ)
4645 swapped = 1, true_code = EQ, false_code = NE;
4646 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4649 /* If we are comparing against zero and the expression being tested has
4650 only a single bit that might be nonzero, that is its value when it is
4651 not equal to zero. Similarly if it is known to be -1 or 0. */
4653 if (true_code == EQ && true_val == const0_rtx
4654 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4655 false_code = EQ, false_val = GEN_INT (nzb);
4656 else if (true_code == EQ && true_val == const0_rtx
4657 && (num_sign_bit_copies (from, GET_MODE (from))
4658 == GET_MODE_BITSIZE (GET_MODE (from))))
4659 false_code = EQ, false_val = constm1_rtx;
4661 /* Now simplify an arm if we know the value of the register in the
4662 branch and it is used in the arm. Be careful due to the potential
4663 of locally-shared RTL. */
4665 if (reg_mentioned_p (from, true_rtx))
4666 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4668 pc_rtx, pc_rtx, 0, 0);
4669 if (reg_mentioned_p (from, false_rtx))
4670 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4672 pc_rtx, pc_rtx, 0, 0);
4674 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4675 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4677 true_rtx = XEXP (x, 1);
4678 false_rtx = XEXP (x, 2);
4679 true_code = GET_CODE (cond);
4682 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4683 reversed, do so to avoid needing two sets of patterns for
4684 subtract-and-branch insns. Similarly if we have a constant in the true
4685 arm, the false arm is the same as the first operand of the comparison, or
4686 the false arm is more complicated than the true arm. */
4689 && combine_reversed_comparison_code (cond) != UNKNOWN
4690 && (true_rtx == pc_rtx
4691 || (CONSTANT_P (true_rtx)
4692 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4693 || true_rtx == const0_rtx
4694 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4695 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4696 || (GET_CODE (true_rtx) == SUBREG
4697 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4698 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4699 || reg_mentioned_p (true_rtx, false_rtx)
4700 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4702 true_code = reversed_comparison_code (cond, NULL);
4704 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4707 SUBST (XEXP (x, 1), false_rtx);
4708 SUBST (XEXP (x, 2), true_rtx);
4710 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4713 /* It is possible that the conditional has been simplified out. */
4714 true_code = GET_CODE (cond);
4715 comparison_p = GET_RTX_CLASS (true_code) == '<';
4718 /* If the two arms are identical, we don't need the comparison. */
4720 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4723 /* Convert a == b ? b : a to "a". */
4724 if (true_code == EQ && ! side_effects_p (cond)
4725 && !HONOR_NANS (mode)
4726 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4727 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4729 else if (true_code == NE && ! side_effects_p (cond)
4730 && !HONOR_NANS (mode)
4731 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4732 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4735 /* Look for cases where we have (abs x) or (neg (abs X)). */
4737 if (GET_MODE_CLASS (mode) == MODE_INT
4738 && GET_CODE (false_rtx) == NEG
4739 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4741 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4742 && ! side_effects_p (true_rtx))
4747 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4751 simplify_gen_unary (NEG, mode,
4752 simplify_gen_unary (ABS, mode, true_rtx, mode),
4758 /* Look for MIN or MAX. */
4760 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4762 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4763 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4764 && ! side_effects_p (cond))
4769 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4772 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4775 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4778 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4783 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4784 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4785 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4786 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4787 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4788 neither 1 or -1, but it isn't worth checking for. */
4790 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4792 && GET_MODE_CLASS (mode) == MODE_INT
4793 && ! side_effects_p (x))
4795 rtx t = make_compound_operation (true_rtx, SET);
4796 rtx f = make_compound_operation (false_rtx, SET);
4797 rtx cond_op0 = XEXP (cond, 0);
4798 rtx cond_op1 = XEXP (cond, 1);
4799 enum rtx_code op = NIL, extend_op = NIL;
4800 enum machine_mode m = mode;
4801 rtx z = 0, c1 = NULL_RTX;
4803 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4804 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4805 || GET_CODE (t) == ASHIFT
4806 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4807 && rtx_equal_p (XEXP (t, 0), f))
4808 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4810 /* If an identity-zero op is commutative, check whether there
4811 would be a match if we swapped the operands. */
4812 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4813 || GET_CODE (t) == XOR)
4814 && rtx_equal_p (XEXP (t, 1), f))
4815 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4816 else if (GET_CODE (t) == SIGN_EXTEND
4817 && (GET_CODE (XEXP (t, 0)) == PLUS
4818 || GET_CODE (XEXP (t, 0)) == MINUS
4819 || GET_CODE (XEXP (t, 0)) == IOR
4820 || GET_CODE (XEXP (t, 0)) == XOR
4821 || GET_CODE (XEXP (t, 0)) == ASHIFT
4822 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4823 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4824 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4825 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4826 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4827 && (num_sign_bit_copies (f, GET_MODE (f))
4829 (GET_MODE_BITSIZE (mode)
4830 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4832 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4833 extend_op = SIGN_EXTEND;
4834 m = GET_MODE (XEXP (t, 0));
4836 else if (GET_CODE (t) == SIGN_EXTEND
4837 && (GET_CODE (XEXP (t, 0)) == PLUS
4838 || GET_CODE (XEXP (t, 0)) == IOR
4839 || GET_CODE (XEXP (t, 0)) == XOR)
4840 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4841 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4842 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4843 && (num_sign_bit_copies (f, GET_MODE (f))
4845 (GET_MODE_BITSIZE (mode)
4846 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4848 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4849 extend_op = SIGN_EXTEND;
4850 m = GET_MODE (XEXP (t, 0));
4852 else if (GET_CODE (t) == ZERO_EXTEND
4853 && (GET_CODE (XEXP (t, 0)) == PLUS
4854 || GET_CODE (XEXP (t, 0)) == MINUS
4855 || GET_CODE (XEXP (t, 0)) == IOR
4856 || GET_CODE (XEXP (t, 0)) == XOR
4857 || GET_CODE (XEXP (t, 0)) == ASHIFT
4858 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4859 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4860 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4861 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4862 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4863 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4864 && ((nonzero_bits (f, GET_MODE (f))
4865 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4868 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4869 extend_op = ZERO_EXTEND;
4870 m = GET_MODE (XEXP (t, 0));
4872 else if (GET_CODE (t) == ZERO_EXTEND
4873 && (GET_CODE (XEXP (t, 0)) == PLUS
4874 || GET_CODE (XEXP (t, 0)) == IOR
4875 || GET_CODE (XEXP (t, 0)) == XOR)
4876 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4877 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4878 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4879 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4880 && ((nonzero_bits (f, GET_MODE (f))
4881 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4884 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4885 extend_op = ZERO_EXTEND;
4886 m = GET_MODE (XEXP (t, 0));
4891 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4892 pc_rtx, pc_rtx, 0, 0);
4893 temp = gen_binary (MULT, m, temp,
4894 gen_binary (MULT, m, c1, const_true_rtx));
4895 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4896 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4898 if (extend_op != NIL)
4899 temp = simplify_gen_unary (extend_op, mode, temp, m);
4905 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4906 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4907 negation of a single bit, we can convert this operation to a shift. We
4908 can actually do this more generally, but it doesn't seem worth it. */
4910 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4911 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4912 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4913 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4914 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4915 == GET_MODE_BITSIZE (mode))
4916 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4918 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4919 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4921 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4922 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4923 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4924 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4925 == nonzero_bits (XEXP (cond, 0), mode)
4926 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4927 return XEXP (cond, 0);
4932 /* Simplify X, a SET expression. Return the new expression. */
4935 simplify_set (rtx x)
4937 rtx src = SET_SRC (x);
4938 rtx dest = SET_DEST (x);
4939 enum machine_mode mode
4940 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4944 /* (set (pc) (return)) gets written as (return). */
4945 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4948 /* Now that we know for sure which bits of SRC we are using, see if we can
4949 simplify the expression for the object knowing that we only need the
4952 if (GET_MODE_CLASS (mode) == MODE_INT
4953 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4955 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4956 SUBST (SET_SRC (x), src);
4959 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4960 the comparison result and try to simplify it unless we already have used
4961 undobuf.other_insn. */
4962 if ((GET_MODE_CLASS (mode) == MODE_CC
4963 || GET_CODE (src) == COMPARE
4965 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4966 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4967 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4968 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4970 enum rtx_code old_code = GET_CODE (*cc_use);
4971 enum rtx_code new_code;
4973 int other_changed = 0;
4974 enum machine_mode compare_mode = GET_MODE (dest);
4975 enum machine_mode tmp_mode;
4977 if (GET_CODE (src) == COMPARE)
4978 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4980 op0 = src, op1 = const0_rtx;
4982 /* Check whether the comparison is known at compile time. */
4983 if (GET_MODE (op0) != VOIDmode)
4984 tmp_mode = GET_MODE (op0);
4985 else if (GET_MODE (op1) != VOIDmode)
4986 tmp_mode = GET_MODE (op1);
4988 tmp_mode = compare_mode;
4989 tmp = simplify_relational_operation (old_code, tmp_mode, op0, op1);
4990 if (tmp != NULL_RTX)
4992 rtx pat = PATTERN (other_insn);
4993 undobuf.other_insn = other_insn;
4994 SUBST (*cc_use, tmp);
4996 /* Attempt to simplify CC user. */
4997 if (GET_CODE (pat) == SET)
4999 rtx new = simplify_rtx (SET_SRC (pat));
5000 if (new != NULL_RTX)
5001 SUBST (SET_SRC (pat), new);
5004 /* Convert X into a no-op move. */
5005 SUBST (SET_DEST (x), pc_rtx);
5006 SUBST (SET_SRC (x), pc_rtx);
5010 /* Simplify our comparison, if possible. */
5011 new_code = simplify_comparison (old_code, &op0, &op1);
5013 #ifdef SELECT_CC_MODE
5014 /* If this machine has CC modes other than CCmode, check to see if we
5015 need to use a different CC mode here. */
5016 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5019 /* If the mode changed, we have to change SET_DEST, the mode in the
5020 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5021 a hard register, just build new versions with the proper mode. If it
5022 is a pseudo, we lose unless it is only time we set the pseudo, in
5023 which case we can safely change its mode. */
5024 if (compare_mode != GET_MODE (dest))
5026 unsigned int regno = REGNO (dest);
5027 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5029 if (regno < FIRST_PSEUDO_REGISTER
5030 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5032 if (regno >= FIRST_PSEUDO_REGISTER)
5033 SUBST (regno_reg_rtx[regno], new_dest);
5035 SUBST (SET_DEST (x), new_dest);
5036 SUBST (XEXP (*cc_use, 0), new_dest);
5043 #endif /* SELECT_CC_MODE */
5045 /* If the code changed, we have to build a new comparison in
5046 undobuf.other_insn. */
5047 if (new_code != old_code)
5049 int other_changed_previously = other_changed;
5050 unsigned HOST_WIDE_INT mask;
5052 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5056 /* If the only change we made was to change an EQ into an NE or
5057 vice versa, OP0 has only one bit that might be nonzero, and OP1
5058 is zero, check if changing the user of the condition code will
5059 produce a valid insn. If it won't, we can keep the original code
5060 in that insn by surrounding our operation with an XOR. */
5062 if (((old_code == NE && new_code == EQ)
5063 || (old_code == EQ && new_code == NE))
5064 && ! other_changed_previously && op1 == const0_rtx
5065 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5066 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5068 rtx pat = PATTERN (other_insn), note = 0;
5070 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5071 && ! check_asm_operands (pat)))
5073 PUT_CODE (*cc_use, old_code);
5076 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5082 undobuf.other_insn = other_insn;
5085 /* If we are now comparing against zero, change our source if
5086 needed. If we do not use cc0, we always have a COMPARE. */
5087 if (op1 == const0_rtx && dest == cc0_rtx)
5089 SUBST (SET_SRC (x), op0);
5095 /* Otherwise, if we didn't previously have a COMPARE in the
5096 correct mode, we need one. */
5097 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5099 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5104 /* Otherwise, update the COMPARE if needed. */
5105 SUBST (XEXP (src, 0), op0);
5106 SUBST (XEXP (src, 1), op1);
5111 /* Get SET_SRC in a form where we have placed back any
5112 compound expressions. Then do the checks below. */
5113 src = make_compound_operation (src, SET);
5114 SUBST (SET_SRC (x), src);
5117 #ifdef WORD_REGISTER_OPERATIONS
5118 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5119 and X being a REG or (subreg (reg)), we may be able to convert this to
5120 (set (subreg:m2 x) (op)).
5122 On a machine where WORD_REGISTER_OPERATIONS is defined, this
5123 transformation is safe as long as M1 and M2 have the same number
5126 However, on a machine without WORD_REGISTER_OPERATIONS defined,
5127 we cannot apply this transformation because it would create a
5128 paradoxical subreg in SET_DEST. */
5130 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5131 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5132 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5134 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5135 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5136 #ifdef CANNOT_CHANGE_MODE_CLASS
5137 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5138 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5139 GET_MODE (SUBREG_REG (src)),
5142 && (GET_CODE (dest) == REG
5143 || (GET_CODE (dest) == SUBREG
5144 && GET_CODE (SUBREG_REG (dest)) == REG)))
5146 SUBST (SET_DEST (x),
5147 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5149 SUBST (SET_SRC (x), SUBREG_REG (src));
5151 src = SET_SRC (x), dest = SET_DEST (x);
5156 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5159 && GET_CODE (src) == SUBREG
5160 && subreg_lowpart_p (src)
5161 && (GET_MODE_BITSIZE (GET_MODE (src))
5162 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5164 rtx inner = SUBREG_REG (src);
5165 enum machine_mode inner_mode = GET_MODE (inner);
5167 /* Here we make sure that we don't have a sign bit on. */
5168 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5169 && (nonzero_bits (inner, inner_mode)
5170 < ((unsigned HOST_WIDE_INT) 1
5171 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5173 SUBST (SET_SRC (x), inner);
5179 #ifdef LOAD_EXTEND_OP
5180 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5181 would require a paradoxical subreg. Replace the subreg with a
5182 zero_extend to avoid the reload that would otherwise be required. */
5184 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5185 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5186 && SUBREG_BYTE (src) == 0
5187 && (GET_MODE_SIZE (GET_MODE (src))
5188 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5189 && GET_CODE (SUBREG_REG (src)) == MEM)
5192 gen_rtx (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5193 GET_MODE (src), SUBREG_REG (src)));
5199 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5200 are comparing an item known to be 0 or -1 against 0, use a logical
5201 operation instead. Check for one of the arms being an IOR of the other
5202 arm with some value. We compute three terms to be IOR'ed together. In
5203 practice, at most two will be nonzero. Then we do the IOR's. */
5205 if (GET_CODE (dest) != PC
5206 && GET_CODE (src) == IF_THEN_ELSE
5207 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5208 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5209 && XEXP (XEXP (src, 0), 1) == const0_rtx
5210 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5211 #ifdef HAVE_conditional_move
5212 && ! can_conditionally_move_p (GET_MODE (src))
5214 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5215 GET_MODE (XEXP (XEXP (src, 0), 0)))
5216 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5217 && ! side_effects_p (src))
5219 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5220 ? XEXP (src, 1) : XEXP (src, 2));
5221 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5222 ? XEXP (src, 2) : XEXP (src, 1));
5223 rtx term1 = const0_rtx, term2, term3;
5225 if (GET_CODE (true_rtx) == IOR
5226 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5227 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5228 else if (GET_CODE (true_rtx) == IOR
5229 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5230 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5231 else if (GET_CODE (false_rtx) == IOR
5232 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5233 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5234 else if (GET_CODE (false_rtx) == IOR
5235 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5236 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5238 term2 = gen_binary (AND, GET_MODE (src),
5239 XEXP (XEXP (src, 0), 0), true_rtx);
5240 term3 = gen_binary (AND, GET_MODE (src),
5241 simplify_gen_unary (NOT, GET_MODE (src),
5242 XEXP (XEXP (src, 0), 0),
5247 gen_binary (IOR, GET_MODE (src),
5248 gen_binary (IOR, GET_MODE (src), term1, term2),
5254 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5255 whole thing fail. */
5256 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5258 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5261 /* Convert this into a field assignment operation, if possible. */
5262 return make_field_assignment (x);
5265 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5266 result. LAST is nonzero if this is the last retry. */
5269 simplify_logical (rtx x, int last)
5271 enum machine_mode mode = GET_MODE (x);
5272 rtx op0 = XEXP (x, 0);
5273 rtx op1 = XEXP (x, 1);
5276 switch (GET_CODE (x))
5279 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5280 insn (and may simplify more). */
5281 if (GET_CODE (op0) == XOR
5282 && rtx_equal_p (XEXP (op0, 0), op1)
5283 && ! side_effects_p (op1))
5284 x = gen_binary (AND, mode,
5285 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5288 if (GET_CODE (op0) == XOR
5289 && rtx_equal_p (XEXP (op0, 1), op1)
5290 && ! side_effects_p (op1))
5291 x = gen_binary (AND, mode,
5292 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5295 /* Similarly for (~(A ^ B)) & A. */
5296 if (GET_CODE (op0) == NOT
5297 && GET_CODE (XEXP (op0, 0)) == XOR
5298 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5299 && ! side_effects_p (op1))
5300 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5302 if (GET_CODE (op0) == NOT
5303 && GET_CODE (XEXP (op0, 0)) == XOR
5304 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5305 && ! side_effects_p (op1))
5306 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5308 /* We can call simplify_and_const_int only if we don't lose
5309 any (sign) bits when converting INTVAL (op1) to
5310 "unsigned HOST_WIDE_INT". */
5311 if (GET_CODE (op1) == CONST_INT
5312 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5313 || INTVAL (op1) > 0))
5315 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5317 /* If we have (ior (and (X C1) C2)) and the next restart would be
5318 the last, simplify this by making C1 as small as possible
5321 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5322 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5323 && GET_CODE (op1) == CONST_INT)
5324 return gen_binary (IOR, mode,
5325 gen_binary (AND, mode, XEXP (op0, 0),
5326 GEN_INT (INTVAL (XEXP (op0, 1))
5327 & ~INTVAL (op1))), op1);
5329 if (GET_CODE (x) != AND)
5332 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5333 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5334 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5337 /* Convert (A | B) & A to A. */
5338 if (GET_CODE (op0) == IOR
5339 && (rtx_equal_p (XEXP (op0, 0), op1)
5340 || rtx_equal_p (XEXP (op0, 1), op1))
5341 && ! side_effects_p (XEXP (op0, 0))
5342 && ! side_effects_p (XEXP (op0, 1)))
5345 /* In the following group of tests (and those in case IOR below),
5346 we start with some combination of logical operations and apply
5347 the distributive law followed by the inverse distributive law.
5348 Most of the time, this results in no change. However, if some of
5349 the operands are the same or inverses of each other, simplifications
5352 For example, (and (ior A B) (not B)) can occur as the result of
5353 expanding a bit field assignment. When we apply the distributive
5354 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5355 which then simplifies to (and (A (not B))).
5357 If we have (and (ior A B) C), apply the distributive law and then
5358 the inverse distributive law to see if things simplify. */
5360 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5362 x = apply_distributive_law
5363 (gen_binary (GET_CODE (op0), mode,
5364 gen_binary (AND, mode, XEXP (op0, 0), op1),
5365 gen_binary (AND, mode, XEXP (op0, 1),
5367 if (GET_CODE (x) != AND)
5371 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5372 return apply_distributive_law
5373 (gen_binary (GET_CODE (op1), mode,
5374 gen_binary (AND, mode, XEXP (op1, 0), op0),
5375 gen_binary (AND, mode, XEXP (op1, 1),
5378 /* Similarly, taking advantage of the fact that
5379 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5381 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5382 return apply_distributive_law
5383 (gen_binary (XOR, mode,
5384 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5385 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5388 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5389 return apply_distributive_law
5390 (gen_binary (XOR, mode,
5391 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5392 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5396 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5397 if (GET_CODE (op1) == CONST_INT
5398 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5399 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5402 /* Convert (A & B) | A to A. */
5403 if (GET_CODE (op0) == AND
5404 && (rtx_equal_p (XEXP (op0, 0), op1)
5405 || rtx_equal_p (XEXP (op0, 1), op1))
5406 && ! side_effects_p (XEXP (op0, 0))
5407 && ! side_effects_p (XEXP (op0, 1)))
5410 /* If we have (ior (and A B) C), apply the distributive law and then
5411 the inverse distributive law to see if things simplify. */
5413 if (GET_CODE (op0) == AND)
5415 x = apply_distributive_law
5416 (gen_binary (AND, mode,
5417 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5418 gen_binary (IOR, mode, XEXP (op0, 1),
5421 if (GET_CODE (x) != IOR)
5425 if (GET_CODE (op1) == AND)
5427 x = apply_distributive_law
5428 (gen_binary (AND, mode,
5429 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5430 gen_binary (IOR, mode, XEXP (op1, 1),
5433 if (GET_CODE (x) != IOR)
5437 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5438 mode size to (rotate A CX). */
5440 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5441 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5442 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5443 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5444 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5445 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5446 == GET_MODE_BITSIZE (mode)))
5447 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5448 (GET_CODE (op0) == ASHIFT
5449 ? XEXP (op0, 1) : XEXP (op1, 1)));
5451 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5452 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5453 does not affect any of the bits in OP1, it can really be done
5454 as a PLUS and we can associate. We do this by seeing if OP1
5455 can be safely shifted left C bits. */
5456 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5457 && GET_CODE (XEXP (op0, 0)) == PLUS
5458 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5459 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5460 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5462 int count = INTVAL (XEXP (op0, 1));
5463 HOST_WIDE_INT mask = INTVAL (op1) << count;
5465 if (mask >> count == INTVAL (op1)
5466 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5468 SUBST (XEXP (XEXP (op0, 0), 1),
5469 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5476 /* If we are XORing two things that have no bits in common,
5477 convert them into an IOR. This helps to detect rotation encoded
5478 using those methods and possibly other simplifications. */
5480 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5481 && (nonzero_bits (op0, mode)
5482 & nonzero_bits (op1, mode)) == 0)
5483 return (gen_binary (IOR, mode, op0, op1));
5485 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5486 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5489 int num_negated = 0;
5491 if (GET_CODE (op0) == NOT)
5492 num_negated++, op0 = XEXP (op0, 0);
5493 if (GET_CODE (op1) == NOT)
5494 num_negated++, op1 = XEXP (op1, 0);
5496 if (num_negated == 2)
5498 SUBST (XEXP (x, 0), op0);
5499 SUBST (XEXP (x, 1), op1);
5501 else if (num_negated == 1)
5503 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5507 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5508 correspond to a machine insn or result in further simplifications
5509 if B is a constant. */
5511 if (GET_CODE (op0) == AND
5512 && rtx_equal_p (XEXP (op0, 1), op1)
5513 && ! side_effects_p (op1))
5514 return gen_binary (AND, mode,
5515 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5518 else if (GET_CODE (op0) == AND
5519 && rtx_equal_p (XEXP (op0, 0), op1)
5520 && ! side_effects_p (op1))
5521 return gen_binary (AND, mode,
5522 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5525 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5526 comparison if STORE_FLAG_VALUE is 1. */
5527 if (STORE_FLAG_VALUE == 1
5528 && op1 == const1_rtx
5529 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5530 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5534 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5535 is (lt foo (const_int 0)), so we can perform the above
5536 simplification if STORE_FLAG_VALUE is 1. */
5538 if (STORE_FLAG_VALUE == 1
5539 && op1 == const1_rtx
5540 && GET_CODE (op0) == LSHIFTRT
5541 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5542 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5543 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5545 /* (xor (comparison foo bar) (const_int sign-bit))
5546 when STORE_FLAG_VALUE is the sign bit. */
5547 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5548 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5549 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5550 && op1 == const_true_rtx
5551 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5552 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5565 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5566 operations" because they can be replaced with two more basic operations.
5567 ZERO_EXTEND is also considered "compound" because it can be replaced with
5568 an AND operation, which is simpler, though only one operation.
5570 The function expand_compound_operation is called with an rtx expression
5571 and will convert it to the appropriate shifts and AND operations,
5572 simplifying at each stage.
5574 The function make_compound_operation is called to convert an expression
5575 consisting of shifts and ANDs into the equivalent compound expression.
5576 It is the inverse of this function, loosely speaking. */
5579 expand_compound_operation (rtx x)
5581 unsigned HOST_WIDE_INT pos = 0, len;
5583 unsigned int modewidth;
5586 switch (GET_CODE (x))
5591 /* We can't necessarily use a const_int for a multiword mode;
5592 it depends on implicitly extending the value.
5593 Since we don't know the right way to extend it,
5594 we can't tell whether the implicit way is right.
5596 Even for a mode that is no wider than a const_int,
5597 we can't win, because we need to sign extend one of its bits through
5598 the rest of it, and we don't know which bit. */
5599 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5602 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5603 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5604 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5605 reloaded. If not for that, MEM's would very rarely be safe.
5607 Reject MODEs bigger than a word, because we might not be able
5608 to reference a two-register group starting with an arbitrary register
5609 (and currently gen_lowpart might crash for a SUBREG). */
5611 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5614 /* Reject MODEs that aren't scalar integers because turning vector
5615 or complex modes into shifts causes problems. */
5617 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5620 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5621 /* If the inner object has VOIDmode (the only way this can happen
5622 is if it is an ASM_OPERANDS), we can't do anything since we don't
5623 know how much masking to do. */
5632 /* If the operand is a CLOBBER, just return it. */
5633 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5636 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5637 || GET_CODE (XEXP (x, 2)) != CONST_INT
5638 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5641 /* Reject MODEs that aren't scalar integers because turning vector
5642 or complex modes into shifts causes problems. */
5644 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5647 len = INTVAL (XEXP (x, 1));
5648 pos = INTVAL (XEXP (x, 2));
5650 /* If this goes outside the object being extracted, replace the object
5651 with a (use (mem ...)) construct that only combine understands
5652 and is used only for this purpose. */
5653 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5654 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5656 if (BITS_BIG_ENDIAN)
5657 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5664 /* Convert sign extension to zero extension, if we know that the high
5665 bit is not set, as this is easier to optimize. It will be converted
5666 back to cheaper alternative in make_extraction. */
5667 if (GET_CODE (x) == SIGN_EXTEND
5668 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5669 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5670 & ~(((unsigned HOST_WIDE_INT)
5671 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5675 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5676 rtx temp2 = expand_compound_operation (temp);
5678 /* Make sure this is a profitable operation. */
5679 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5681 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5687 /* We can optimize some special cases of ZERO_EXTEND. */
5688 if (GET_CODE (x) == ZERO_EXTEND)
5690 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5691 know that the last value didn't have any inappropriate bits
5693 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5694 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5695 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5696 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5697 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5698 return XEXP (XEXP (x, 0), 0);
5700 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5701 if (GET_CODE (XEXP (x, 0)) == SUBREG
5702 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5703 && subreg_lowpart_p (XEXP (x, 0))
5704 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5705 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5706 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5707 return SUBREG_REG (XEXP (x, 0));
5709 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5710 is a comparison and STORE_FLAG_VALUE permits. This is like
5711 the first case, but it works even when GET_MODE (x) is larger
5712 than HOST_WIDE_INT. */
5713 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5714 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5715 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5716 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5717 <= HOST_BITS_PER_WIDE_INT)
5718 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5719 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5720 return XEXP (XEXP (x, 0), 0);
5722 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5723 if (GET_CODE (XEXP (x, 0)) == SUBREG
5724 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5725 && subreg_lowpart_p (XEXP (x, 0))
5726 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5727 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5728 <= HOST_BITS_PER_WIDE_INT)
5729 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5730 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5731 return SUBREG_REG (XEXP (x, 0));
5735 /* If we reach here, we want to return a pair of shifts. The inner
5736 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5737 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5738 logical depending on the value of UNSIGNEDP.
5740 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5741 converted into an AND of a shift.
5743 We must check for the case where the left shift would have a negative
5744 count. This can happen in a case like (x >> 31) & 255 on machines
5745 that can't shift by a constant. On those machines, we would first
5746 combine the shift with the AND to produce a variable-position
5747 extraction. Then the constant of 31 would be substituted in to produce
5748 a such a position. */
5750 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5751 if (modewidth + len >= pos)
5752 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5754 simplify_shift_const (NULL_RTX, ASHIFT,
5757 modewidth - pos - len),
5760 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5761 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5762 simplify_shift_const (NULL_RTX, LSHIFTRT,
5765 ((HOST_WIDE_INT) 1 << len) - 1);
5767 /* Any other cases we can't handle. */
5770 /* If we couldn't do this for some reason, return the original
5772 if (GET_CODE (tem) == CLOBBER)
5778 /* X is a SET which contains an assignment of one object into
5779 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5780 or certain SUBREGS). If possible, convert it into a series of
5783 We half-heartedly support variable positions, but do not at all
5784 support variable lengths. */
5787 expand_field_assignment (rtx x)
5790 rtx pos; /* Always counts from low bit. */
5793 enum machine_mode compute_mode;
5795 /* Loop until we find something we can't simplify. */
5798 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5799 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5801 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5802 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5803 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5805 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5806 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5808 inner = XEXP (SET_DEST (x), 0);
5809 len = INTVAL (XEXP (SET_DEST (x), 1));
5810 pos = XEXP (SET_DEST (x), 2);
5812 /* If the position is constant and spans the width of INNER,
5813 surround INNER with a USE to indicate this. */
5814 if (GET_CODE (pos) == CONST_INT
5815 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5816 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5818 if (BITS_BIG_ENDIAN)
5820 if (GET_CODE (pos) == CONST_INT)
5821 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5823 else if (GET_CODE (pos) == MINUS
5824 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5825 && (INTVAL (XEXP (pos, 1))
5826 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5827 /* If position is ADJUST - X, new position is X. */
5828 pos = XEXP (pos, 0);
5830 pos = gen_binary (MINUS, GET_MODE (pos),
5831 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5837 /* A SUBREG between two modes that occupy the same numbers of words
5838 can be done by moving the SUBREG to the source. */
5839 else if (GET_CODE (SET_DEST (x)) == SUBREG
5840 /* We need SUBREGs to compute nonzero_bits properly. */
5841 && nonzero_sign_valid
5842 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5843 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5844 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5845 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5847 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5848 gen_lowpart_for_combine
5849 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5856 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5857 inner = SUBREG_REG (inner);
5859 compute_mode = GET_MODE (inner);
5861 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5862 if (! SCALAR_INT_MODE_P (compute_mode))
5864 enum machine_mode imode;
5866 /* Don't do anything for vector or complex integral types. */
5867 if (! FLOAT_MODE_P (compute_mode))
5870 /* Try to find an integral mode to pun with. */
5871 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5872 if (imode == BLKmode)
5875 compute_mode = imode;
5876 inner = gen_lowpart_for_combine (imode, inner);
5879 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5880 if (len < HOST_BITS_PER_WIDE_INT)
5881 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5885 /* Now compute the equivalent expression. Make a copy of INNER
5886 for the SET_DEST in case it is a MEM into which we will substitute;
5887 we don't want shared RTL in that case. */
5889 (VOIDmode, copy_rtx (inner),
5890 gen_binary (IOR, compute_mode,
5891 gen_binary (AND, compute_mode,
5892 simplify_gen_unary (NOT, compute_mode,
5898 gen_binary (ASHIFT, compute_mode,
5899 gen_binary (AND, compute_mode,
5900 gen_lowpart_for_combine
5901 (compute_mode, SET_SRC (x)),
5909 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5910 it is an RTX that represents a variable starting position; otherwise,
5911 POS is the (constant) starting bit position (counted from the LSB).
5913 INNER may be a USE. This will occur when we started with a bitfield
5914 that went outside the boundary of the object in memory, which is
5915 allowed on most machines. To isolate this case, we produce a USE
5916 whose mode is wide enough and surround the MEM with it. The only
5917 code that understands the USE is this routine. If it is not removed,
5918 it will cause the resulting insn not to match.
5920 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5923 IN_DEST is nonzero if this is a reference in the destination of a
5924 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5925 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5928 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5929 ZERO_EXTRACT should be built even for bits starting at bit 0.
5931 MODE is the desired mode of the result (if IN_DEST == 0).
5933 The result is an RTX for the extraction or NULL_RTX if the target
5937 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5938 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5939 int in_dest, int in_compare)
5941 /* This mode describes the size of the storage area
5942 to fetch the overall value from. Within that, we
5943 ignore the POS lowest bits, etc. */
5944 enum machine_mode is_mode = GET_MODE (inner);
5945 enum machine_mode inner_mode;
5946 enum machine_mode wanted_inner_mode = byte_mode;
5947 enum machine_mode wanted_inner_reg_mode = word_mode;
5948 enum machine_mode pos_mode = word_mode;
5949 enum machine_mode extraction_mode = word_mode;
5950 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5953 rtx orig_pos_rtx = pos_rtx;
5954 HOST_WIDE_INT orig_pos;
5956 /* Get some information about INNER and get the innermost object. */
5957 if (GET_CODE (inner) == USE)
5958 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5959 /* We don't need to adjust the position because we set up the USE
5960 to pretend that it was a full-word object. */
5961 spans_byte = 1, inner = XEXP (inner, 0);
5962 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5964 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5965 consider just the QI as the memory to extract from.
5966 The subreg adds or removes high bits; its mode is
5967 irrelevant to the meaning of this extraction,
5968 since POS and LEN count from the lsb. */
5969 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5970 is_mode = GET_MODE (SUBREG_REG (inner));
5971 inner = SUBREG_REG (inner);
5973 else if (GET_CODE (inner) == ASHIFT
5974 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5975 && pos_rtx == 0 && pos == 0
5976 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5978 /* We're extracting the least significant bits of an rtx
5979 (ashift X (const_int C)), where LEN > C. Extract the
5980 least significant (LEN - C) bits of X, giving an rtx
5981 whose mode is MODE, then shift it left C times. */
5982 new = make_extraction (mode, XEXP (inner, 0),
5983 0, 0, len - INTVAL (XEXP (inner, 1)),
5984 unsignedp, in_dest, in_compare);
5986 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5989 inner_mode = GET_MODE (inner);
5991 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5992 pos = INTVAL (pos_rtx), pos_rtx = 0;
5994 /* See if this can be done without an extraction. We never can if the
5995 width of the field is not the same as that of some integer mode. For
5996 registers, we can only avoid the extraction if the position is at the
5997 low-order bit and this is either not in the destination or we have the
5998 appropriate STRICT_LOW_PART operation available.
6000 For MEM, we can avoid an extract if the field starts on an appropriate
6001 boundary and we can change the mode of the memory reference. However,
6002 we cannot directly access the MEM if we have a USE and the underlying
6003 MEM is not TMODE. This combination means that MEM was being used in a
6004 context where bits outside its mode were being referenced; that is only
6005 valid in bit-field insns. */
6007 if (tmode != BLKmode
6008 && ! (spans_byte && inner_mode != tmode)
6009 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6010 && GET_CODE (inner) != MEM
6012 || (GET_CODE (inner) == REG
6013 && have_insn_for (STRICT_LOW_PART, tmode))))
6014 || (GET_CODE (inner) == MEM && pos_rtx == 0
6016 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6017 : BITS_PER_UNIT)) == 0
6018 /* We can't do this if we are widening INNER_MODE (it
6019 may not be aligned, for one thing). */
6020 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6021 && (inner_mode == tmode
6022 || (! mode_dependent_address_p (XEXP (inner, 0))
6023 && ! MEM_VOLATILE_P (inner))))))
6025 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6026 field. If the original and current mode are the same, we need not
6027 adjust the offset. Otherwise, we do if bytes big endian.
6029 If INNER is not a MEM, get a piece consisting of just the field
6030 of interest (in this case POS % BITS_PER_WORD must be 0). */
6032 if (GET_CODE (inner) == MEM)
6034 HOST_WIDE_INT offset;
6036 /* POS counts from lsb, but make OFFSET count in memory order. */
6037 if (BYTES_BIG_ENDIAN)
6038 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6040 offset = pos / BITS_PER_UNIT;
6042 new = adjust_address_nv (inner, tmode, offset);
6044 else if (GET_CODE (inner) == REG)
6046 if (tmode != inner_mode)
6048 /* We can't call gen_lowpart_for_combine in a DEST since we
6049 always want a SUBREG (see below) and it would sometimes
6050 return a new hard register. */
6053 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6055 if (WORDS_BIG_ENDIAN
6056 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6057 final_word = ((GET_MODE_SIZE (inner_mode)
6058 - GET_MODE_SIZE (tmode))
6059 / UNITS_PER_WORD) - final_word;
6061 final_word *= UNITS_PER_WORD;
6062 if (BYTES_BIG_ENDIAN &&
6063 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6064 final_word += (GET_MODE_SIZE (inner_mode)
6065 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6067 /* Avoid creating invalid subregs, for example when
6068 simplifying (x>>32)&255. */
6069 if (final_word >= GET_MODE_SIZE (inner_mode))
6072 new = gen_rtx_SUBREG (tmode, inner, final_word);
6075 new = gen_lowpart_for_combine (tmode, inner);
6081 new = force_to_mode (inner, tmode,
6082 len >= HOST_BITS_PER_WIDE_INT
6083 ? ~(unsigned HOST_WIDE_INT) 0
6084 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6087 /* If this extraction is going into the destination of a SET,
6088 make a STRICT_LOW_PART unless we made a MEM. */
6091 return (GET_CODE (new) == MEM ? new
6092 : (GET_CODE (new) != SUBREG
6093 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6094 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6099 if (GET_CODE (new) == CONST_INT)
6100 return gen_int_mode (INTVAL (new), mode);
6102 /* If we know that no extraneous bits are set, and that the high
6103 bit is not set, convert the extraction to the cheaper of
6104 sign and zero extension, that are equivalent in these cases. */
6105 if (flag_expensive_optimizations
6106 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6107 && ((nonzero_bits (new, tmode)
6108 & ~(((unsigned HOST_WIDE_INT)
6109 GET_MODE_MASK (tmode))
6113 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6114 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6116 /* Prefer ZERO_EXTENSION, since it gives more information to
6118 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6123 /* Otherwise, sign- or zero-extend unless we already are in the
6126 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6130 /* Unless this is a COMPARE or we have a funny memory reference,
6131 don't do anything with zero-extending field extracts starting at
6132 the low-order bit since they are simple AND operations. */
6133 if (pos_rtx == 0 && pos == 0 && ! in_dest
6134 && ! in_compare && ! spans_byte && unsignedp)
6137 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6138 we would be spanning bytes or if the position is not a constant and the
6139 length is not 1. In all other cases, we would only be going outside
6140 our object in cases when an original shift would have been
6142 if (! spans_byte && GET_CODE (inner) == MEM
6143 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6144 || (pos_rtx != 0 && len != 1)))
6147 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6148 and the mode for the result. */
6149 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6151 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6152 pos_mode = mode_for_extraction (EP_insv, 2);
6153 extraction_mode = mode_for_extraction (EP_insv, 3);
6156 if (! in_dest && unsignedp
6157 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6159 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6160 pos_mode = mode_for_extraction (EP_extzv, 3);
6161 extraction_mode = mode_for_extraction (EP_extzv, 0);
6164 if (! in_dest && ! unsignedp
6165 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6167 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6168 pos_mode = mode_for_extraction (EP_extv, 3);
6169 extraction_mode = mode_for_extraction (EP_extv, 0);
6172 /* Never narrow an object, since that might not be safe. */
6174 if (mode != VOIDmode
6175 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6176 extraction_mode = mode;
6178 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6179 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6180 pos_mode = GET_MODE (pos_rtx);
6182 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6183 if we have to change the mode of memory and cannot, the desired mode is
6185 if (GET_CODE (inner) != MEM)
6186 wanted_inner_mode = wanted_inner_reg_mode;
6187 else if (inner_mode != wanted_inner_mode
6188 && (mode_dependent_address_p (XEXP (inner, 0))
6189 || MEM_VOLATILE_P (inner)))
6190 wanted_inner_mode = extraction_mode;
6194 if (BITS_BIG_ENDIAN)
6196 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6197 BITS_BIG_ENDIAN style. If position is constant, compute new
6198 position. Otherwise, build subtraction.
6199 Note that POS is relative to the mode of the original argument.
6200 If it's a MEM we need to recompute POS relative to that.
6201 However, if we're extracting from (or inserting into) a register,
6202 we want to recompute POS relative to wanted_inner_mode. */
6203 int width = (GET_CODE (inner) == MEM
6204 ? GET_MODE_BITSIZE (is_mode)
6205 : GET_MODE_BITSIZE (wanted_inner_mode));
6208 pos = width - len - pos;
6211 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6212 /* POS may be less than 0 now, but we check for that below.
6213 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6216 /* If INNER has a wider mode, make it smaller. If this is a constant
6217 extract, try to adjust the byte to point to the byte containing
6219 if (wanted_inner_mode != VOIDmode
6220 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6221 && ((GET_CODE (inner) == MEM
6222 && (inner_mode == wanted_inner_mode
6223 || (! mode_dependent_address_p (XEXP (inner, 0))
6224 && ! MEM_VOLATILE_P (inner))))))
6228 /* The computations below will be correct if the machine is big
6229 endian in both bits and bytes or little endian in bits and bytes.
6230 If it is mixed, we must adjust. */
6232 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6233 adjust OFFSET to compensate. */
6234 if (BYTES_BIG_ENDIAN
6236 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6237 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6239 /* If this is a constant position, we can move to the desired byte. */
6242 offset += pos / BITS_PER_UNIT;
6243 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6246 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6248 && is_mode != wanted_inner_mode)
6249 offset = (GET_MODE_SIZE (is_mode)
6250 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6252 if (offset != 0 || inner_mode != wanted_inner_mode)
6253 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6256 /* If INNER is not memory, we can always get it into the proper mode. If we
6257 are changing its mode, POS must be a constant and smaller than the size
6259 else if (GET_CODE (inner) != MEM)
6261 if (GET_MODE (inner) != wanted_inner_mode
6263 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6266 inner = force_to_mode (inner, wanted_inner_mode,
6268 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6269 ? ~(unsigned HOST_WIDE_INT) 0
6270 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6275 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6276 have to zero extend. Otherwise, we can just use a SUBREG. */
6278 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6280 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6282 /* If we know that no extraneous bits are set, and that the high
6283 bit is not set, convert extraction to cheaper one - either
6284 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6286 if (flag_expensive_optimizations
6287 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6288 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6289 & ~(((unsigned HOST_WIDE_INT)
6290 GET_MODE_MASK (GET_MODE (pos_rtx)))
6294 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6296 /* Prefer ZERO_EXTENSION, since it gives more information to
6298 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6303 else if (pos_rtx != 0
6304 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6305 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6307 /* Make POS_RTX unless we already have it and it is correct. If we don't
6308 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6310 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6311 pos_rtx = orig_pos_rtx;
6313 else if (pos_rtx == 0)
6314 pos_rtx = GEN_INT (pos);
6316 /* Make the required operation. See if we can use existing rtx. */
6317 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6318 extraction_mode, inner, GEN_INT (len), pos_rtx);
6320 new = gen_lowpart_for_combine (mode, new);
6325 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6326 with any other operations in X. Return X without that shift if so. */
6329 extract_left_shift (rtx x, int count)
6331 enum rtx_code code = GET_CODE (x);
6332 enum machine_mode mode = GET_MODE (x);
6338 /* This is the shift itself. If it is wide enough, we will return
6339 either the value being shifted if the shift count is equal to
6340 COUNT or a shift for the difference. */
6341 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6342 && INTVAL (XEXP (x, 1)) >= count)
6343 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6344 INTVAL (XEXP (x, 1)) - count);
6348 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6349 return simplify_gen_unary (code, mode, tem, mode);
6353 case PLUS: case IOR: case XOR: case AND:
6354 /* If we can safely shift this constant and we find the inner shift,
6355 make a new operation. */
6356 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6357 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6358 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6359 return gen_binary (code, mode, tem,
6360 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6371 /* Look at the expression rooted at X. Look for expressions
6372 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6373 Form these expressions.
6375 Return the new rtx, usually just X.
6377 Also, for machines like the VAX that don't have logical shift insns,
6378 try to convert logical to arithmetic shift operations in cases where
6379 they are equivalent. This undoes the canonicalizations to logical
6380 shifts done elsewhere.
6382 We try, as much as possible, to re-use rtl expressions to save memory.
6384 IN_CODE says what kind of expression we are processing. Normally, it is
6385 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6386 being kludges), it is MEM. When processing the arguments of a comparison
6387 or a COMPARE against zero, it is COMPARE. */
6390 make_compound_operation (rtx x, enum rtx_code in_code)
6392 enum rtx_code code = GET_CODE (x);
6393 enum machine_mode mode = GET_MODE (x);
6394 int mode_width = GET_MODE_BITSIZE (mode);
6396 enum rtx_code next_code;
6402 /* Select the code to be used in recursive calls. Once we are inside an
6403 address, we stay there. If we have a comparison, set to COMPARE,
6404 but once inside, go back to our default of SET. */
6406 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6407 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6408 && XEXP (x, 1) == const0_rtx) ? COMPARE
6409 : in_code == COMPARE ? SET : in_code);
6411 /* Process depending on the code of this operation. If NEW is set
6412 nonzero, it will be returned. */
6417 /* Convert shifts by constants into multiplications if inside
6419 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6420 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6421 && INTVAL (XEXP (x, 1)) >= 0)
6423 new = make_compound_operation (XEXP (x, 0), next_code);
6424 new = gen_rtx_MULT (mode, new,
6425 GEN_INT ((HOST_WIDE_INT) 1
6426 << INTVAL (XEXP (x, 1))));
6431 /* If the second operand is not a constant, we can't do anything
6433 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6436 /* If the constant is a power of two minus one and the first operand
6437 is a logical right shift, make an extraction. */
6438 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6439 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6441 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6442 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6443 0, in_code == COMPARE);
6446 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6447 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6448 && subreg_lowpart_p (XEXP (x, 0))
6449 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6450 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6452 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6454 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6455 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6456 0, in_code == COMPARE);
6458 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6459 else if ((GET_CODE (XEXP (x, 0)) == XOR
6460 || GET_CODE (XEXP (x, 0)) == IOR)
6461 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6462 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6463 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6465 /* Apply the distributive law, and then try to make extractions. */
6466 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6467 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6469 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6471 new = make_compound_operation (new, in_code);
6474 /* If we are have (and (rotate X C) M) and C is larger than the number
6475 of bits in M, this is an extraction. */
6477 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6478 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6479 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6480 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6482 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6483 new = make_extraction (mode, new,
6484 (GET_MODE_BITSIZE (mode)
6485 - INTVAL (XEXP (XEXP (x, 0), 1))),
6486 NULL_RTX, i, 1, 0, in_code == COMPARE);
6489 /* On machines without logical shifts, if the operand of the AND is
6490 a logical shift and our mask turns off all the propagated sign
6491 bits, we can replace the logical shift with an arithmetic shift. */
6492 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6493 && !have_insn_for (LSHIFTRT, mode)
6494 && have_insn_for (ASHIFTRT, mode)
6495 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6496 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6497 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6498 && mode_width <= HOST_BITS_PER_WIDE_INT)
6500 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6502 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6503 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6505 gen_rtx_ASHIFTRT (mode,
6506 make_compound_operation
6507 (XEXP (XEXP (x, 0), 0), next_code),
6508 XEXP (XEXP (x, 0), 1)));
6511 /* If the constant is one less than a power of two, this might be
6512 representable by an extraction even if no shift is present.
6513 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6514 we are in a COMPARE. */
6515 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6516 new = make_extraction (mode,
6517 make_compound_operation (XEXP (x, 0),
6519 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6521 /* If we are in a comparison and this is an AND with a power of two,
6522 convert this into the appropriate bit extract. */
6523 else if (in_code == COMPARE
6524 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6525 new = make_extraction (mode,
6526 make_compound_operation (XEXP (x, 0),
6528 i, NULL_RTX, 1, 1, 0, 1);
6533 /* If the sign bit is known to be zero, replace this with an
6534 arithmetic shift. */
6535 if (have_insn_for (ASHIFTRT, mode)
6536 && ! have_insn_for (LSHIFTRT, mode)
6537 && mode_width <= HOST_BITS_PER_WIDE_INT
6538 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6540 new = gen_rtx_ASHIFTRT (mode,
6541 make_compound_operation (XEXP (x, 0),
6547 /* ... fall through ... */
6553 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6554 this is a SIGN_EXTRACT. */
6555 if (GET_CODE (rhs) == CONST_INT
6556 && GET_CODE (lhs) == ASHIFT
6557 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6558 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6560 new = make_compound_operation (XEXP (lhs, 0), next_code);
6561 new = make_extraction (mode, new,
6562 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6563 NULL_RTX, mode_width - INTVAL (rhs),
6564 code == LSHIFTRT, 0, in_code == COMPARE);
6568 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6569 If so, try to merge the shifts into a SIGN_EXTEND. We could
6570 also do this for some cases of SIGN_EXTRACT, but it doesn't
6571 seem worth the effort; the case checked for occurs on Alpha. */
6573 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6574 && ! (GET_CODE (lhs) == SUBREG
6575 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6576 && GET_CODE (rhs) == CONST_INT
6577 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6578 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6579 new = make_extraction (mode, make_compound_operation (new, next_code),
6580 0, NULL_RTX, mode_width - INTVAL (rhs),
6581 code == LSHIFTRT, 0, in_code == COMPARE);
6586 /* Call ourselves recursively on the inner expression. If we are
6587 narrowing the object and it has a different RTL code from
6588 what it originally did, do this SUBREG as a force_to_mode. */
6590 tem = make_compound_operation (SUBREG_REG (x), in_code);
6591 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6592 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6593 && subreg_lowpart_p (x))
6595 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6598 /* If we have something other than a SUBREG, we might have
6599 done an expansion, so rerun ourselves. */
6600 if (GET_CODE (newer) != SUBREG)
6601 newer = make_compound_operation (newer, in_code);
6606 /* If this is a paradoxical subreg, and the new code is a sign or
6607 zero extension, omit the subreg and widen the extension. If it
6608 is a regular subreg, we can still get rid of the subreg by not
6609 widening so much, or in fact removing the extension entirely. */
6610 if ((GET_CODE (tem) == SIGN_EXTEND
6611 || GET_CODE (tem) == ZERO_EXTEND)
6612 && subreg_lowpart_p (x))
6614 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6615 || (GET_MODE_SIZE (mode) >
6616 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6618 if (! SCALAR_INT_MODE_P (mode))
6620 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6623 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6634 x = gen_lowpart_for_combine (mode, new);
6635 code = GET_CODE (x);
6638 /* Now recursively process each operand of this operation. */
6639 fmt = GET_RTX_FORMAT (code);
6640 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6643 new = make_compound_operation (XEXP (x, i), next_code);
6644 SUBST (XEXP (x, i), new);
6650 /* Given M see if it is a value that would select a field of bits
6651 within an item, but not the entire word. Return -1 if not.
6652 Otherwise, return the starting position of the field, where 0 is the
6655 *PLEN is set to the length of the field. */
6658 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6660 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6661 int pos = exact_log2 (m & -m);
6667 /* Now shift off the low-order zero bits and see if we have a power of
6669 len = exact_log2 ((m >> pos) + 1);
6678 /* See if X can be simplified knowing that we will only refer to it in
6679 MODE and will only refer to those bits that are nonzero in MASK.
6680 If other bits are being computed or if masking operations are done
6681 that select a superset of the bits in MASK, they can sometimes be
6684 Return a possibly simplified expression, but always convert X to
6685 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6687 Also, if REG is nonzero and X is a register equal in value to REG,
6690 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6691 are all off in X. This is used when X will be complemented, by either
6692 NOT, NEG, or XOR. */
6695 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6696 rtx reg, int just_select)
6698 enum rtx_code code = GET_CODE (x);
6699 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6700 enum machine_mode op_mode;
6701 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6704 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6705 code below will do the wrong thing since the mode of such an
6706 expression is VOIDmode.
6708 Also do nothing if X is a CLOBBER; this can happen if X was
6709 the return value from a call to gen_lowpart_for_combine. */
6710 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6713 /* We want to perform the operation is its present mode unless we know
6714 that the operation is valid in MODE, in which case we do the operation
6716 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6717 && have_insn_for (code, mode))
6718 ? mode : GET_MODE (x));
6720 /* It is not valid to do a right-shift in a narrower mode
6721 than the one it came in with. */
6722 if ((code == LSHIFTRT || code == ASHIFTRT)
6723 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6724 op_mode = GET_MODE (x);
6726 /* Truncate MASK to fit OP_MODE. */
6728 mask &= GET_MODE_MASK (op_mode);
6730 /* When we have an arithmetic operation, or a shift whose count we
6731 do not know, we need to assume that all bits up to the highest-order
6732 bit in MASK will be needed. This is how we form such a mask. */
6733 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6734 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6736 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6739 /* Determine what bits of X are guaranteed to be (non)zero. */
6740 nonzero = nonzero_bits (x, mode);
6742 /* If none of the bits in X are needed, return a zero. */
6743 if (! just_select && (nonzero & mask) == 0)
6746 /* If X is a CONST_INT, return a new one. Do this here since the
6747 test below will fail. */
6748 if (GET_CODE (x) == CONST_INT)
6750 if (SCALAR_INT_MODE_P (mode))
6751 return gen_int_mode (INTVAL (x) & mask, mode);
6754 x = GEN_INT (INTVAL (x) & mask);
6755 return gen_lowpart_common (mode, x);
6759 /* If X is narrower than MODE and we want all the bits in X's mode, just
6760 get X in the proper mode. */
6761 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6762 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6763 return gen_lowpart_for_combine (mode, x);
6765 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6766 MASK are already known to be zero in X, we need not do anything. */
6767 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6773 /* If X is a (clobber (const_int)), return it since we know we are
6774 generating something that won't match. */
6778 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6779 spanned the boundary of the MEM. If we are now masking so it is
6780 within that boundary, we don't need the USE any more. */
6781 if (! BITS_BIG_ENDIAN
6782 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6783 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6790 x = expand_compound_operation (x);
6791 if (GET_CODE (x) != code)
6792 return force_to_mode (x, mode, mask, reg, next_select);
6796 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6797 || rtx_equal_p (reg, get_last_value (x))))
6802 if (subreg_lowpart_p (x)
6803 /* We can ignore the effect of this SUBREG if it narrows the mode or
6804 if the constant masks to zero all the bits the mode doesn't
6806 && ((GET_MODE_SIZE (GET_MODE (x))
6807 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6809 & GET_MODE_MASK (GET_MODE (x))
6810 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6811 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6815 /* If this is an AND with a constant, convert it into an AND
6816 whose constant is the AND of that constant with MASK. If it
6817 remains an AND of MASK, delete it since it is redundant. */
6819 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6821 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6822 mask & INTVAL (XEXP (x, 1)));
6824 /* If X is still an AND, see if it is an AND with a mask that
6825 is just some low-order bits. If so, and it is MASK, we don't
6828 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6829 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6833 /* If it remains an AND, try making another AND with the bits
6834 in the mode mask that aren't in MASK turned on. If the
6835 constant in the AND is wide enough, this might make a
6836 cheaper constant. */
6838 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6839 && GET_MODE_MASK (GET_MODE (x)) != mask
6840 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6842 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6843 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6844 int width = GET_MODE_BITSIZE (GET_MODE (x));
6847 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6848 number, sign extend it. */
6849 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6850 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6851 cval |= (HOST_WIDE_INT) -1 << width;
6853 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6854 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6864 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6865 low-order bits (as in an alignment operation) and FOO is already
6866 aligned to that boundary, mask C1 to that boundary as well.
6867 This may eliminate that PLUS and, later, the AND. */
6870 unsigned int width = GET_MODE_BITSIZE (mode);
6871 unsigned HOST_WIDE_INT smask = mask;
6873 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6874 number, sign extend it. */
6876 if (width < HOST_BITS_PER_WIDE_INT
6877 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6878 smask |= (HOST_WIDE_INT) -1 << width;
6880 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6881 && exact_log2 (- smask) >= 0
6882 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6883 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6884 return force_to_mode (plus_constant (XEXP (x, 0),
6885 (INTVAL (XEXP (x, 1)) & smask)),
6886 mode, smask, reg, next_select);
6889 /* ... fall through ... */
6892 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6893 most significant bit in MASK since carries from those bits will
6894 affect the bits we are interested in. */
6899 /* If X is (minus C Y) where C's least set bit is larger than any bit
6900 in the mask, then we may replace with (neg Y). */
6901 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6902 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6903 & -INTVAL (XEXP (x, 0))))
6906 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6908 return force_to_mode (x, mode, mask, reg, next_select);
6911 /* Similarly, if C contains every bit in the fuller_mask, then we may
6912 replace with (not Y). */
6913 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6914 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6915 == INTVAL (XEXP (x, 0))))
6917 x = simplify_gen_unary (NOT, GET_MODE (x),
6918 XEXP (x, 1), GET_MODE (x));
6919 return force_to_mode (x, mode, mask, reg, next_select);
6927 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6928 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6929 operation which may be a bitfield extraction. Ensure that the
6930 constant we form is not wider than the mode of X. */
6932 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6933 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6934 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6935 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6936 && GET_CODE (XEXP (x, 1)) == CONST_INT
6937 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6938 + floor_log2 (INTVAL (XEXP (x, 1))))
6939 < GET_MODE_BITSIZE (GET_MODE (x)))
6940 && (INTVAL (XEXP (x, 1))
6941 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6943 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6944 << INTVAL (XEXP (XEXP (x, 0), 1)));
6945 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6946 XEXP (XEXP (x, 0), 0), temp);
6947 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6948 XEXP (XEXP (x, 0), 1));
6949 return force_to_mode (x, mode, mask, reg, next_select);
6953 /* For most binary operations, just propagate into the operation and
6954 change the mode if we have an operation of that mode. */
6956 op0 = gen_lowpart_for_combine (op_mode,
6957 force_to_mode (XEXP (x, 0), mode, mask,
6959 op1 = gen_lowpart_for_combine (op_mode,
6960 force_to_mode (XEXP (x, 1), mode, mask,
6963 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6964 x = gen_binary (code, op_mode, op0, op1);
6968 /* For left shifts, do the same, but just for the first operand.
6969 However, we cannot do anything with shifts where we cannot
6970 guarantee that the counts are smaller than the size of the mode
6971 because such a count will have a different meaning in a
6974 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6975 && INTVAL (XEXP (x, 1)) >= 0
6976 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6977 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6978 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6979 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6982 /* If the shift count is a constant and we can do arithmetic in
6983 the mode of the shift, refine which bits we need. Otherwise, use the
6984 conservative form of the mask. */
6985 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6986 && INTVAL (XEXP (x, 1)) >= 0
6987 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6988 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6989 mask >>= INTVAL (XEXP (x, 1));
6993 op0 = gen_lowpart_for_combine (op_mode,
6994 force_to_mode (XEXP (x, 0), op_mode,
6995 mask, reg, next_select));
6997 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6998 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7002 /* Here we can only do something if the shift count is a constant,
7003 this shift constant is valid for the host, and we can do arithmetic
7006 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7007 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7008 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7010 rtx inner = XEXP (x, 0);
7011 unsigned HOST_WIDE_INT inner_mask;
7013 /* Select the mask of the bits we need for the shift operand. */
7014 inner_mask = mask << INTVAL (XEXP (x, 1));
7016 /* We can only change the mode of the shift if we can do arithmetic
7017 in the mode of the shift and INNER_MASK is no wider than the
7018 width of OP_MODE. */
7019 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7020 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7021 op_mode = GET_MODE (x);
7023 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7025 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7026 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7029 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7030 shift and AND produces only copies of the sign bit (C2 is one less
7031 than a power of two), we can do this with just a shift. */
7033 if (GET_CODE (x) == LSHIFTRT
7034 && GET_CODE (XEXP (x, 1)) == CONST_INT
7035 /* The shift puts one of the sign bit copies in the least significant
7037 && ((INTVAL (XEXP (x, 1))
7038 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7039 >= GET_MODE_BITSIZE (GET_MODE (x)))
7040 && exact_log2 (mask + 1) >= 0
7041 /* Number of bits left after the shift must be more than the mask
7043 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7044 <= GET_MODE_BITSIZE (GET_MODE (x)))
7045 /* Must be more sign bit copies than the mask needs. */
7046 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7047 >= exact_log2 (mask + 1)))
7048 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7049 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7050 - exact_log2 (mask + 1)));
7055 /* If we are just looking for the sign bit, we don't need this shift at
7056 all, even if it has a variable count. */
7057 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7058 && (mask == ((unsigned HOST_WIDE_INT) 1
7059 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7060 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7062 /* If this is a shift by a constant, get a mask that contains those bits
7063 that are not copies of the sign bit. We then have two cases: If
7064 MASK only includes those bits, this can be a logical shift, which may
7065 allow simplifications. If MASK is a single-bit field not within
7066 those bits, we are requesting a copy of the sign bit and hence can
7067 shift the sign bit to the appropriate location. */
7069 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7070 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7074 /* If the considered data is wider than HOST_WIDE_INT, we can't
7075 represent a mask for all its bits in a single scalar.
7076 But we only care about the lower bits, so calculate these. */
7078 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7080 nonzero = ~(HOST_WIDE_INT) 0;
7082 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7083 is the number of bits a full-width mask would have set.
7084 We need only shift if these are fewer than nonzero can
7085 hold. If not, we must keep all bits set in nonzero. */
7087 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7088 < HOST_BITS_PER_WIDE_INT)
7089 nonzero >>= INTVAL (XEXP (x, 1))
7090 + HOST_BITS_PER_WIDE_INT
7091 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7095 nonzero = GET_MODE_MASK (GET_MODE (x));
7096 nonzero >>= INTVAL (XEXP (x, 1));
7099 if ((mask & ~nonzero) == 0
7100 || (i = exact_log2 (mask)) >= 0)
7102 x = simplify_shift_const
7103 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7104 i < 0 ? INTVAL (XEXP (x, 1))
7105 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7107 if (GET_CODE (x) != ASHIFTRT)
7108 return force_to_mode (x, mode, mask, reg, next_select);
7112 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7113 even if the shift count isn't a constant. */
7115 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7119 /* If this is a zero- or sign-extension operation that just affects bits
7120 we don't care about, remove it. Be sure the call above returned
7121 something that is still a shift. */
7123 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7124 && GET_CODE (XEXP (x, 1)) == CONST_INT
7125 && INTVAL (XEXP (x, 1)) >= 0
7126 && (INTVAL (XEXP (x, 1))
7127 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7128 && GET_CODE (XEXP (x, 0)) == ASHIFT
7129 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7130 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7137 /* If the shift count is constant and we can do computations
7138 in the mode of X, compute where the bits we care about are.
7139 Otherwise, we can't do anything. Don't change the mode of
7140 the shift or propagate MODE into the shift, though. */
7141 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7142 && INTVAL (XEXP (x, 1)) >= 0)
7144 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7145 GET_MODE (x), GEN_INT (mask),
7147 if (temp && GET_CODE (temp) == CONST_INT)
7149 force_to_mode (XEXP (x, 0), GET_MODE (x),
7150 INTVAL (temp), reg, next_select));
7155 /* If we just want the low-order bit, the NEG isn't needed since it
7156 won't change the low-order bit. */
7158 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7160 /* We need any bits less significant than the most significant bit in
7161 MASK since carries from those bits will affect the bits we are
7167 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7168 same as the XOR case above. Ensure that the constant we form is not
7169 wider than the mode of X. */
7171 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7172 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7173 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7174 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7175 < GET_MODE_BITSIZE (GET_MODE (x)))
7176 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7178 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7180 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7181 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7183 return force_to_mode (x, mode, mask, reg, next_select);
7186 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7187 use the full mask inside the NOT. */
7191 op0 = gen_lowpart_for_combine (op_mode,
7192 force_to_mode (XEXP (x, 0), mode, mask,
7194 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7195 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7199 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7200 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7201 which is equal to STORE_FLAG_VALUE. */
7202 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7203 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7204 && (nonzero_bits (XEXP (x, 0), mode)
7205 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7206 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7211 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7212 written in a narrower mode. We play it safe and do not do so. */
7215 gen_lowpart_for_combine (GET_MODE (x),
7216 force_to_mode (XEXP (x, 1), mode,
7217 mask, reg, next_select)));
7219 gen_lowpart_for_combine (GET_MODE (x),
7220 force_to_mode (XEXP (x, 2), mode,
7221 mask, reg, next_select)));
7228 /* Ensure we return a value of the proper mode. */
7229 return gen_lowpart_for_combine (mode, x);
7232 /* Return nonzero if X is an expression that has one of two values depending on
7233 whether some other value is zero or nonzero. In that case, we return the
7234 value that is being tested, *PTRUE is set to the value if the rtx being
7235 returned has a nonzero value, and *PFALSE is set to the other alternative.
7237 If we return zero, we set *PTRUE and *PFALSE to X. */
7240 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7242 enum machine_mode mode = GET_MODE (x);
7243 enum rtx_code code = GET_CODE (x);
7244 rtx cond0, cond1, true0, true1, false0, false1;
7245 unsigned HOST_WIDE_INT nz;
7247 /* If we are comparing a value against zero, we are done. */
7248 if ((code == NE || code == EQ)
7249 && XEXP (x, 1) == const0_rtx)
7251 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7252 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7256 /* If this is a unary operation whose operand has one of two values, apply
7257 our opcode to compute those values. */
7258 else if (GET_RTX_CLASS (code) == '1'
7259 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7261 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7262 *pfalse = simplify_gen_unary (code, mode, false0,
7263 GET_MODE (XEXP (x, 0)));
7267 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7268 make can't possibly match and would suppress other optimizations. */
7269 else if (code == COMPARE)
7272 /* If this is a binary operation, see if either side has only one of two
7273 values. If either one does or if both do and they are conditional on
7274 the same value, compute the new true and false values. */
7275 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7276 || GET_RTX_CLASS (code) == '<')
7278 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7279 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7281 if ((cond0 != 0 || cond1 != 0)
7282 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7284 /* If if_then_else_cond returned zero, then true/false are the
7285 same rtl. We must copy one of them to prevent invalid rtl
7288 true0 = copy_rtx (true0);
7289 else if (cond1 == 0)
7290 true1 = copy_rtx (true1);
7292 *ptrue = gen_binary (code, mode, true0, true1);
7293 *pfalse = gen_binary (code, mode, false0, false1);
7294 return cond0 ? cond0 : cond1;
7297 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7298 operands is zero when the other is nonzero, and vice-versa,
7299 and STORE_FLAG_VALUE is 1 or -1. */
7301 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7302 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7304 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7306 rtx op0 = XEXP (XEXP (x, 0), 1);
7307 rtx op1 = XEXP (XEXP (x, 1), 1);
7309 cond0 = XEXP (XEXP (x, 0), 0);
7310 cond1 = XEXP (XEXP (x, 1), 0);
7312 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7313 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7314 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7315 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7316 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7317 || ((swap_condition (GET_CODE (cond0))
7318 == combine_reversed_comparison_code (cond1))
7319 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7320 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7321 && ! side_effects_p (x))
7323 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7324 *pfalse = gen_binary (MULT, mode,
7326 ? simplify_gen_unary (NEG, mode, op1,
7334 /* Similarly for MULT, AND and UMIN, except that for these the result
7336 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7337 && (code == MULT || code == AND || code == UMIN)
7338 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7340 cond0 = XEXP (XEXP (x, 0), 0);
7341 cond1 = XEXP (XEXP (x, 1), 0);
7343 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7344 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7345 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7346 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7347 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7348 || ((swap_condition (GET_CODE (cond0))
7349 == combine_reversed_comparison_code (cond1))
7350 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7351 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7352 && ! side_effects_p (x))
7354 *ptrue = *pfalse = const0_rtx;
7360 else if (code == IF_THEN_ELSE)
7362 /* If we have IF_THEN_ELSE already, extract the condition and
7363 canonicalize it if it is NE or EQ. */
7364 cond0 = XEXP (x, 0);
7365 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7366 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7367 return XEXP (cond0, 0);
7368 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7370 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7371 return XEXP (cond0, 0);
7377 /* If X is a SUBREG, we can narrow both the true and false values
7378 if the inner expression, if there is a condition. */
7379 else if (code == SUBREG
7380 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7383 *ptrue = simplify_gen_subreg (mode, true0,
7384 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7385 *pfalse = simplify_gen_subreg (mode, false0,
7386 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7391 /* If X is a constant, this isn't special and will cause confusions
7392 if we treat it as such. Likewise if it is equivalent to a constant. */
7393 else if (CONSTANT_P (x)
7394 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7397 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7398 will be least confusing to the rest of the compiler. */
7399 else if (mode == BImode)
7401 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7405 /* If X is known to be either 0 or -1, those are the true and
7406 false values when testing X. */
7407 else if (x == constm1_rtx || x == const0_rtx
7408 || (mode != VOIDmode
7409 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7411 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7415 /* Likewise for 0 or a single bit. */
7416 else if (SCALAR_INT_MODE_P (mode)
7417 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7418 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7420 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7424 /* Otherwise fail; show no condition with true and false values the same. */
7425 *ptrue = *pfalse = x;
7429 /* Return the value of expression X given the fact that condition COND
7430 is known to be true when applied to REG as its first operand and VAL
7431 as its second. X is known to not be shared and so can be modified in
7434 We only handle the simplest cases, and specifically those cases that
7435 arise with IF_THEN_ELSE expressions. */
7438 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7440 enum rtx_code code = GET_CODE (x);
7445 if (side_effects_p (x))
7448 /* If either operand of the condition is a floating point value,
7449 then we have to avoid collapsing an EQ comparison. */
7451 && rtx_equal_p (x, reg)
7452 && ! FLOAT_MODE_P (GET_MODE (x))
7453 && ! FLOAT_MODE_P (GET_MODE (val)))
7456 if (cond == UNEQ && rtx_equal_p (x, reg))
7459 /* If X is (abs REG) and we know something about REG's relationship
7460 with zero, we may be able to simplify this. */
7462 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7465 case GE: case GT: case EQ:
7468 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7470 GET_MODE (XEXP (x, 0)));
7475 /* The only other cases we handle are MIN, MAX, and comparisons if the
7476 operands are the same as REG and VAL. */
7478 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7480 if (rtx_equal_p (XEXP (x, 0), val))
7481 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7483 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7485 if (GET_RTX_CLASS (code) == '<')
7487 if (comparison_dominates_p (cond, code))
7488 return const_true_rtx;
7490 code = combine_reversed_comparison_code (x);
7492 && comparison_dominates_p (cond, code))
7497 else if (code == SMAX || code == SMIN
7498 || code == UMIN || code == UMAX)
7500 int unsignedp = (code == UMIN || code == UMAX);
7502 /* Do not reverse the condition when it is NE or EQ.
7503 This is because we cannot conclude anything about
7504 the value of 'SMAX (x, y)' when x is not equal to y,
7505 but we can when x equals y. */
7506 if ((code == SMAX || code == UMAX)
7507 && ! (cond == EQ || cond == NE))
7508 cond = reverse_condition (cond);
7513 return unsignedp ? x : XEXP (x, 1);
7515 return unsignedp ? x : XEXP (x, 0);
7517 return unsignedp ? XEXP (x, 1) : x;
7519 return unsignedp ? XEXP (x, 0) : x;
7526 else if (code == SUBREG)
7528 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7529 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7531 if (SUBREG_REG (x) != r)
7533 /* We must simplify subreg here, before we lose track of the
7534 original inner_mode. */
7535 new = simplify_subreg (GET_MODE (x), r,
7536 inner_mode, SUBREG_BYTE (x));
7540 SUBST (SUBREG_REG (x), r);
7545 /* We don't have to handle SIGN_EXTEND here, because even in the
7546 case of replacing something with a modeless CONST_INT, a
7547 CONST_INT is already (supposed to be) a valid sign extension for
7548 its narrower mode, which implies it's already properly
7549 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7550 story is different. */
7551 else if (code == ZERO_EXTEND)
7553 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7554 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7556 if (XEXP (x, 0) != r)
7558 /* We must simplify the zero_extend here, before we lose
7559 track of the original inner_mode. */
7560 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7565 SUBST (XEXP (x, 0), r);
7571 fmt = GET_RTX_FORMAT (code);
7572 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7575 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7576 else if (fmt[i] == 'E')
7577 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7578 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7585 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7586 assignment as a field assignment. */
7589 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7591 if (x == y || rtx_equal_p (x, y))
7594 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7597 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7598 Note that all SUBREGs of MEM are paradoxical; otherwise they
7599 would have been rewritten. */
7600 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7601 && GET_CODE (SUBREG_REG (y)) == MEM
7602 && rtx_equal_p (SUBREG_REG (y),
7603 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7606 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7607 && GET_CODE (SUBREG_REG (x)) == MEM
7608 && rtx_equal_p (SUBREG_REG (x),
7609 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7612 /* We used to see if get_last_value of X and Y were the same but that's
7613 not correct. In one direction, we'll cause the assignment to have
7614 the wrong destination and in the case, we'll import a register into this
7615 insn that might have already have been dead. So fail if none of the
7616 above cases are true. */
7620 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7621 Return that assignment if so.
7623 We only handle the most common cases. */
7626 make_field_assignment (rtx x)
7628 rtx dest = SET_DEST (x);
7629 rtx src = SET_SRC (x);
7634 unsigned HOST_WIDE_INT len;
7636 enum machine_mode mode;
7638 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7639 a clear of a one-bit field. We will have changed it to
7640 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7643 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7644 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7645 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7646 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7648 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7651 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7655 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7656 && subreg_lowpart_p (XEXP (src, 0))
7657 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7658 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7659 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7660 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7661 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7662 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7664 assign = make_extraction (VOIDmode, dest, 0,
7665 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7668 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7672 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7674 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7675 && XEXP (XEXP (src, 0), 0) == const1_rtx
7676 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7678 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7681 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7685 /* The other case we handle is assignments into a constant-position
7686 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7687 a mask that has all one bits except for a group of zero bits and
7688 OTHER is known to have zeros where C1 has ones, this is such an
7689 assignment. Compute the position and length from C1. Shift OTHER
7690 to the appropriate position, force it to the required mode, and
7691 make the extraction. Check for the AND in both operands. */
7693 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7696 rhs = expand_compound_operation (XEXP (src, 0));
7697 lhs = expand_compound_operation (XEXP (src, 1));
7699 if (GET_CODE (rhs) == AND
7700 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7701 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7702 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7703 else if (GET_CODE (lhs) == AND
7704 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7705 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7706 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7710 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7711 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7712 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7713 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7716 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7720 /* The mode to use for the source is the mode of the assignment, or of
7721 what is inside a possible STRICT_LOW_PART. */
7722 mode = (GET_CODE (assign) == STRICT_LOW_PART
7723 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7725 /* Shift OTHER right POS places and make it the source, restricting it
7726 to the proper length and mode. */
7728 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7729 GET_MODE (src), other, pos),
7731 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7732 ? ~(unsigned HOST_WIDE_INT) 0
7733 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7736 /* If SRC is masked by an AND that does not make a difference in
7737 the value being stored, strip it. */
7738 if (GET_CODE (assign) == ZERO_EXTRACT
7739 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7740 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7741 && GET_CODE (src) == AND
7742 && GET_CODE (XEXP (src, 1)) == CONST_INT
7743 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7744 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7745 src = XEXP (src, 0);
7747 return gen_rtx_SET (VOIDmode, assign, src);
7750 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7754 apply_distributive_law (rtx x)
7756 enum rtx_code code = GET_CODE (x);
7757 enum rtx_code inner_code;
7758 rtx lhs, rhs, other;
7761 /* Distributivity is not true for floating point as it can change the
7762 value. So we don't do it unless -funsafe-math-optimizations. */
7763 if (FLOAT_MODE_P (GET_MODE (x))
7764 && ! flag_unsafe_math_optimizations)
7767 /* The outer operation can only be one of the following: */
7768 if (code != IOR && code != AND && code != XOR
7769 && code != PLUS && code != MINUS)
7775 /* If either operand is a primitive we can't do anything, so get out
7777 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7778 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7781 lhs = expand_compound_operation (lhs);
7782 rhs = expand_compound_operation (rhs);
7783 inner_code = GET_CODE (lhs);
7784 if (inner_code != GET_CODE (rhs))
7787 /* See if the inner and outer operations distribute. */
7794 /* These all distribute except over PLUS. */
7795 if (code == PLUS || code == MINUS)
7800 if (code != PLUS && code != MINUS)
7805 /* This is also a multiply, so it distributes over everything. */
7809 /* Non-paradoxical SUBREGs distributes over all operations, provided
7810 the inner modes and byte offsets are the same, this is an extraction
7811 of a low-order part, we don't convert an fp operation to int or
7812 vice versa, and we would not be converting a single-word
7813 operation into a multi-word operation. The latter test is not
7814 required, but it prevents generating unneeded multi-word operations.
7815 Some of the previous tests are redundant given the latter test, but
7816 are retained because they are required for correctness.
7818 We produce the result slightly differently in this case. */
7820 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7821 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7822 || ! subreg_lowpart_p (lhs)
7823 || (GET_MODE_CLASS (GET_MODE (lhs))
7824 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7825 || (GET_MODE_SIZE (GET_MODE (lhs))
7826 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7827 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7830 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7831 SUBREG_REG (lhs), SUBREG_REG (rhs));
7832 return gen_lowpart_for_combine (GET_MODE (x), tem);
7838 /* Set LHS and RHS to the inner operands (A and B in the example
7839 above) and set OTHER to the common operand (C in the example).
7840 These is only one way to do this unless the inner operation is
7842 if (GET_RTX_CLASS (inner_code) == 'c'
7843 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7844 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7845 else if (GET_RTX_CLASS (inner_code) == 'c'
7846 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7847 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7848 else if (GET_RTX_CLASS (inner_code) == 'c'
7849 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7850 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7851 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7852 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7856 /* Form the new inner operation, seeing if it simplifies first. */
7857 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7859 /* There is one exception to the general way of distributing:
7860 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7861 if (code == XOR && inner_code == IOR)
7864 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7867 /* We may be able to continuing distributing the result, so call
7868 ourselves recursively on the inner operation before forming the
7869 outer operation, which we return. */
7870 return gen_binary (inner_code, GET_MODE (x),
7871 apply_distributive_law (tem), other);
7874 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7877 Return an equivalent form, if different from X. Otherwise, return X. If
7878 X is zero, we are to always construct the equivalent form. */
7881 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7882 unsigned HOST_WIDE_INT constop)
7884 unsigned HOST_WIDE_INT nonzero;
7887 /* Simplify VAROP knowing that we will be only looking at some of the
7890 Note by passing in CONSTOP, we guarantee that the bits not set in
7891 CONSTOP are not significant and will never be examined. We must
7892 ensure that is the case by explicitly masking out those bits
7893 before returning. */
7894 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7896 /* If VAROP is a CLOBBER, we will fail so return it. */
7897 if (GET_CODE (varop) == CLOBBER)
7900 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7901 to VAROP and return the new constant. */
7902 if (GET_CODE (varop) == CONST_INT)
7903 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
7905 /* See what bits may be nonzero in VAROP. Unlike the general case of
7906 a call to nonzero_bits, here we don't care about bits outside
7909 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7911 /* Turn off all bits in the constant that are known to already be zero.
7912 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7913 which is tested below. */
7917 /* If we don't have any bits left, return zero. */
7921 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7922 a power of two, we can replace this with an ASHIFT. */
7923 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7924 && (i = exact_log2 (constop)) >= 0)
7925 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7927 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7928 or XOR, then try to apply the distributive law. This may eliminate
7929 operations if either branch can be simplified because of the AND.
7930 It may also make some cases more complex, but those cases probably
7931 won't match a pattern either with or without this. */
7933 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7935 gen_lowpart_for_combine
7937 apply_distributive_law
7938 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7939 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7940 XEXP (varop, 0), constop),
7941 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7942 XEXP (varop, 1), constop))));
7944 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
7945 the AND and see if one of the operands simplifies to zero. If so, we
7946 may eliminate it. */
7948 if (GET_CODE (varop) == PLUS
7949 && exact_log2 (constop + 1) >= 0)
7953 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7954 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7955 if (o0 == const0_rtx)
7957 if (o1 == const0_rtx)
7961 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7962 if we already had one (just check for the simplest cases). */
7963 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7964 && GET_MODE (XEXP (x, 0)) == mode
7965 && SUBREG_REG (XEXP (x, 0)) == varop)
7966 varop = XEXP (x, 0);
7968 varop = gen_lowpart_for_combine (mode, varop);
7970 /* If we can't make the SUBREG, try to return what we were given. */
7971 if (GET_CODE (varop) == CLOBBER)
7972 return x ? x : varop;
7974 /* If we are only masking insignificant bits, return VAROP. */
7975 if (constop == nonzero)
7979 /* Otherwise, return an AND. */
7980 constop = trunc_int_for_mode (constop, mode);
7981 /* See how much, if any, of X we can use. */
7982 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7983 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7987 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7988 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7989 SUBST (XEXP (x, 1), GEN_INT (constop));
7991 SUBST (XEXP (x, 0), varop);
7998 #define nonzero_bits_with_known(X, MODE) \
7999 cached_nonzero_bits (X, MODE, known_x, known_mode, known_ret)
8001 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
8002 It avoids exponential behavior in nonzero_bits1 when X has
8003 identical subexpressions on the first or the second level. */
8005 static unsigned HOST_WIDE_INT
8006 cached_nonzero_bits (rtx x, enum machine_mode mode, rtx known_x,
8007 enum machine_mode known_mode,
8008 unsigned HOST_WIDE_INT known_ret)
8010 if (x == known_x && mode == known_mode)
8013 /* Try to find identical subexpressions. If found call
8014 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
8015 precomputed value for the subexpression as KNOWN_RET. */
8017 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8018 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8020 rtx x0 = XEXP (x, 0);
8021 rtx x1 = XEXP (x, 1);
8023 /* Check the first level. */
8025 return nonzero_bits1 (x, mode, x0, mode,
8026 nonzero_bits_with_known (x0, mode));
8028 /* Check the second level. */
8029 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8030 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8031 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8032 return nonzero_bits1 (x, mode, x1, mode,
8033 nonzero_bits_with_known (x1, mode));
8035 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8036 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8037 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8038 return nonzero_bits1 (x, mode, x0, mode,
8039 nonzero_bits_with_known (x0, mode));
8042 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
8045 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
8046 We don't let nonzero_bits recur into num_sign_bit_copies, because that
8047 is less useful. We can't allow both, because that results in exponential
8048 run time recursion. There is a nullstone testcase that triggered
8049 this. This macro avoids accidental uses of num_sign_bit_copies. */
8050 #define cached_num_sign_bit_copies()
8052 /* Given an expression, X, compute which bits in X can be nonzero.
8053 We don't care about bits outside of those defined in MODE.
8055 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8056 a shift, AND, or zero_extract, we can do better. */
8058 static unsigned HOST_WIDE_INT
8059 nonzero_bits1 (rtx x, enum machine_mode mode, rtx known_x,
8060 enum machine_mode known_mode,
8061 unsigned HOST_WIDE_INT known_ret)
8063 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
8064 unsigned HOST_WIDE_INT inner_nz;
8066 unsigned int mode_width = GET_MODE_BITSIZE (mode);
8069 /* For floating-point values, assume all bits are needed. */
8070 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
8073 /* If X is wider than MODE, use its mode instead. */
8074 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
8076 mode = GET_MODE (x);
8077 nonzero = GET_MODE_MASK (mode);
8078 mode_width = GET_MODE_BITSIZE (mode);
8081 if (mode_width > HOST_BITS_PER_WIDE_INT)
8082 /* Our only callers in this case look for single bit values. So
8083 just return the mode mask. Those tests will then be false. */
8086 #ifndef WORD_REGISTER_OPERATIONS
8087 /* If MODE is wider than X, but both are a single word for both the host
8088 and target machines, we can compute this from which bits of the
8089 object might be nonzero in its own mode, taking into account the fact
8090 that on many CISC machines, accessing an object in a wider mode
8091 causes the high-order bits to become undefined. So they are
8092 not known to be zero. */
8094 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
8095 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
8096 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8097 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8099 nonzero &= nonzero_bits_with_known (x, GET_MODE (x));
8100 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8105 code = GET_CODE (x);
8109 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8110 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8111 all the bits above ptr_mode are known to be zero. */
8112 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8114 nonzero &= GET_MODE_MASK (ptr_mode);
8117 /* Include declared information about alignment of pointers. */
8118 /* ??? We don't properly preserve REG_POINTER changes across
8119 pointer-to-integer casts, so we can't trust it except for
8120 things that we know must be pointers. See execute/960116-1.c. */
8121 if ((x == stack_pointer_rtx
8122 || x == frame_pointer_rtx
8123 || x == arg_pointer_rtx)
8124 && REGNO_POINTER_ALIGN (REGNO (x)))
8126 unsigned HOST_WIDE_INT alignment
8127 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
8129 #ifdef PUSH_ROUNDING
8130 /* If PUSH_ROUNDING is defined, it is possible for the
8131 stack to be momentarily aligned only to that amount,
8132 so we pick the least alignment. */
8133 if (x == stack_pointer_rtx && PUSH_ARGS)
8134 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1),
8138 nonzero &= ~(alignment - 1);
8141 /* If X is a register whose nonzero bits value is current, use it.
8142 Otherwise, if X is a register whose value we can find, use that
8143 value. Otherwise, use the previously-computed global nonzero bits
8144 for this register. */
8146 if (reg_last_set_value[REGNO (x)] != 0
8147 && (reg_last_set_mode[REGNO (x)] == mode
8148 || (GET_MODE_CLASS (reg_last_set_mode[REGNO (x)]) == MODE_INT
8149 && GET_MODE_CLASS (mode) == MODE_INT))
8150 && (reg_last_set_label[REGNO (x)] == label_tick
8151 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8152 && REG_N_SETS (REGNO (x)) == 1
8153 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8155 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8156 return reg_last_set_nonzero_bits[REGNO (x)] & nonzero;
8158 tem = get_last_value (x);
8162 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8163 /* If X is narrower than MODE and TEM is a non-negative
8164 constant that would appear negative in the mode of X,
8165 sign-extend it for use in reg_nonzero_bits because some
8166 machines (maybe most) will actually do the sign-extension
8167 and this is the conservative approach.
8169 ??? For 2.5, try to tighten up the MD files in this regard
8170 instead of this kludge. */
8172 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8173 && GET_CODE (tem) == CONST_INT
8175 && 0 != (INTVAL (tem)
8176 & ((HOST_WIDE_INT) 1
8177 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8178 tem = GEN_INT (INTVAL (tem)
8179 | ((HOST_WIDE_INT) (-1)
8180 << GET_MODE_BITSIZE (GET_MODE (x))));
8182 return nonzero_bits_with_known (tem, mode) & nonzero;
8184 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8186 unsigned HOST_WIDE_INT mask = reg_nonzero_bits[REGNO (x)];
8188 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width)
8189 /* We don't know anything about the upper bits. */
8190 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8191 return nonzero & mask;
8197 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8198 /* If X is negative in MODE, sign-extend the value. */
8199 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8200 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8201 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8207 #ifdef LOAD_EXTEND_OP
8208 /* In many, if not most, RISC machines, reading a byte from memory
8209 zeros the rest of the register. Noticing that fact saves a lot
8210 of extra zero-extends. */
8211 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8212 nonzero &= GET_MODE_MASK (GET_MODE (x));
8217 case UNEQ: case LTGT:
8218 case GT: case GTU: case UNGT:
8219 case LT: case LTU: case UNLT:
8220 case GE: case GEU: case UNGE:
8221 case LE: case LEU: case UNLE:
8222 case UNORDERED: case ORDERED:
8224 /* If this produces an integer result, we know which bits are set.
8225 Code here used to clear bits outside the mode of X, but that is
8228 if (GET_MODE_CLASS (mode) == MODE_INT
8229 && mode_width <= HOST_BITS_PER_WIDE_INT)
8230 nonzero = STORE_FLAG_VALUE;
8235 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8236 and num_sign_bit_copies. */
8237 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8238 == GET_MODE_BITSIZE (GET_MODE (x)))
8242 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8243 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8248 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8249 and num_sign_bit_copies. */
8250 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8251 == GET_MODE_BITSIZE (GET_MODE (x)))
8257 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8258 & GET_MODE_MASK (mode));
8262 nonzero &= nonzero_bits_with_known (XEXP (x, 0), mode);
8263 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8264 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8268 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8269 Otherwise, show all the bits in the outer mode but not the inner
8271 inner_nz = nonzero_bits_with_known (XEXP (x, 0), mode);
8272 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8274 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8276 & (((HOST_WIDE_INT) 1
8277 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8278 inner_nz |= (GET_MODE_MASK (mode)
8279 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8282 nonzero &= inner_nz;
8286 nonzero &= (nonzero_bits_with_known (XEXP (x, 0), mode)
8287 & nonzero_bits_with_known (XEXP (x, 1), mode));
8291 case UMIN: case UMAX: case SMIN: case SMAX:
8293 unsigned HOST_WIDE_INT nonzero0 =
8294 nonzero_bits_with_known (XEXP (x, 0), mode);
8296 /* Don't call nonzero_bits for the second time if it cannot change
8298 if ((nonzero & nonzero0) != nonzero)
8299 nonzero &= (nonzero0
8300 | nonzero_bits_with_known (XEXP (x, 1), mode));
8304 case PLUS: case MINUS:
8306 case DIV: case UDIV:
8307 case MOD: case UMOD:
8308 /* We can apply the rules of arithmetic to compute the number of
8309 high- and low-order zero bits of these operations. We start by
8310 computing the width (position of the highest-order nonzero bit)
8311 and the number of low-order zero bits for each value. */
8313 unsigned HOST_WIDE_INT nz0 =
8314 nonzero_bits_with_known (XEXP (x, 0), mode);
8315 unsigned HOST_WIDE_INT nz1 =
8316 nonzero_bits_with_known (XEXP (x, 1), mode);
8317 int sign_index = GET_MODE_BITSIZE (GET_MODE (x)) - 1;
8318 int width0 = floor_log2 (nz0) + 1;
8319 int width1 = floor_log2 (nz1) + 1;
8320 int low0 = floor_log2 (nz0 & -nz0);
8321 int low1 = floor_log2 (nz1 & -nz1);
8322 HOST_WIDE_INT op0_maybe_minusp
8323 = (nz0 & ((HOST_WIDE_INT) 1 << sign_index));
8324 HOST_WIDE_INT op1_maybe_minusp
8325 = (nz1 & ((HOST_WIDE_INT) 1 << sign_index));
8326 unsigned int result_width = mode_width;
8332 result_width = MAX (width0, width1) + 1;
8333 result_low = MIN (low0, low1);
8336 result_low = MIN (low0, low1);
8339 result_width = width0 + width1;
8340 result_low = low0 + low1;
8345 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8346 result_width = width0;
8351 result_width = width0;
8356 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8357 result_width = MIN (width0, width1);
8358 result_low = MIN (low0, low1);
8363 result_width = MIN (width0, width1);
8364 result_low = MIN (low0, low1);
8370 if (result_width < mode_width)
8371 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8374 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8376 #ifdef POINTERS_EXTEND_UNSIGNED
8377 /* If pointers extend unsigned and this is an addition or subtraction
8378 to a pointer in Pmode, all the bits above ptr_mode are known to be
8380 if (POINTERS_EXTEND_UNSIGNED > 0 && GET_MODE (x) == Pmode
8381 && (code == PLUS || code == MINUS)
8382 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8383 nonzero &= GET_MODE_MASK (ptr_mode);
8389 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8390 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8391 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8395 /* If this is a SUBREG formed for a promoted variable that has
8396 been zero-extended, we know that at least the high-order bits
8397 are zero, though others might be too. */
8399 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0)
8400 nonzero = (GET_MODE_MASK (GET_MODE (x))
8401 & nonzero_bits_with_known (SUBREG_REG (x), GET_MODE (x)));
8403 /* If the inner mode is a single word for both the host and target
8404 machines, we can compute this from which bits of the inner
8405 object might be nonzero. */
8406 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8407 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8408 <= HOST_BITS_PER_WIDE_INT))
8410 nonzero &= nonzero_bits_with_known (SUBREG_REG (x), mode);
8412 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8413 /* If this is a typical RISC machine, we only have to worry
8414 about the way loads are extended. */
8415 if ((LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8417 & (((unsigned HOST_WIDE_INT) 1
8418 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8420 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8421 || GET_CODE (SUBREG_REG (x)) != MEM)
8424 /* On many CISC machines, accessing an object in a wider mode
8425 causes the high-order bits to become undefined. So they are
8426 not known to be zero. */
8427 if (GET_MODE_SIZE (GET_MODE (x))
8428 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8429 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8430 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8439 /* The nonzero bits are in two classes: any bits within MODE
8440 that aren't in GET_MODE (x) are always significant. The rest of the
8441 nonzero bits are those that are significant in the operand of
8442 the shift when shifted the appropriate number of bits. This
8443 shows that high-order bits are cleared by the right shift and
8444 low-order bits by left shifts. */
8445 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8446 && INTVAL (XEXP (x, 1)) >= 0
8447 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8449 enum machine_mode inner_mode = GET_MODE (x);
8450 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8451 int count = INTVAL (XEXP (x, 1));
8452 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8453 unsigned HOST_WIDE_INT op_nonzero =
8454 nonzero_bits_with_known (XEXP (x, 0), mode);
8455 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8456 unsigned HOST_WIDE_INT outer = 0;
8458 if (mode_width > width)
8459 outer = (op_nonzero & nonzero & ~mode_mask);
8461 if (code == LSHIFTRT)
8463 else if (code == ASHIFTRT)
8467 /* If the sign bit may have been nonzero before the shift, we
8468 need to mark all the places it could have been copied to
8469 by the shift as possibly nonzero. */
8470 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8471 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8473 else if (code == ASHIFT)
8476 inner = ((inner << (count % width)
8477 | (inner >> (width - (count % width)))) & mode_mask);
8479 nonzero &= (outer | inner);
8485 /* This is at most the number of bits in the mode. */
8486 nonzero = ((HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1;
8490 /* If CLZ has a known value at zero, then the nonzero bits are
8491 that value, plus the number of bits in the mode minus one. */
8492 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8493 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8499 /* If CTZ has a known value at zero, then the nonzero bits are
8500 that value, plus the number of bits in the mode minus one. */
8501 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
8502 nonzero |= ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1;
8512 nonzero &= (nonzero_bits_with_known (XEXP (x, 1), mode)
8513 | nonzero_bits_with_known (XEXP (x, 2), mode));
8523 /* See the macro definition above. */
8524 #undef cached_num_sign_bit_copies
8526 #define num_sign_bit_copies_with_known(X, M) \
8527 cached_num_sign_bit_copies (X, M, known_x, known_mode, known_ret)
8529 /* The function cached_num_sign_bit_copies is a wrapper around
8530 num_sign_bit_copies1. It avoids exponential behavior in
8531 num_sign_bit_copies1 when X has identical subexpressions on the
8532 first or the second level. */
8535 cached_num_sign_bit_copies (rtx x, enum machine_mode mode, rtx known_x,
8536 enum machine_mode known_mode,
8537 unsigned int known_ret)
8539 if (x == known_x && mode == known_mode)
8542 /* Try to find identical subexpressions. If found call
8543 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
8544 the precomputed value for the subexpression as KNOWN_RET. */
8546 if (GET_RTX_CLASS (GET_CODE (x)) == '2'
8547 || GET_RTX_CLASS (GET_CODE (x)) == 'c')
8549 rtx x0 = XEXP (x, 0);
8550 rtx x1 = XEXP (x, 1);
8552 /* Check the first level. */
8555 num_sign_bit_copies1 (x, mode, x0, mode,
8556 num_sign_bit_copies_with_known (x0, mode));
8558 /* Check the second level. */
8559 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
8560 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
8561 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
8563 num_sign_bit_copies1 (x, mode, x1, mode,
8564 num_sign_bit_copies_with_known (x1, mode));
8566 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
8567 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
8568 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
8570 num_sign_bit_copies1 (x, mode, x0, mode,
8571 num_sign_bit_copies_with_known (x0, mode));
8574 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
8577 /* Return the number of bits at the high-order end of X that are known to
8578 be equal to the sign bit. X will be used in mode MODE; if MODE is
8579 VOIDmode, X will be used in its own mode. The returned value will always
8580 be between 1 and the number of bits in MODE. */
8583 num_sign_bit_copies1 (rtx x, enum machine_mode mode, rtx known_x,
8584 enum machine_mode known_mode,
8585 unsigned int known_ret)
8587 enum rtx_code code = GET_CODE (x);
8588 unsigned int bitwidth;
8589 int num0, num1, result;
8590 unsigned HOST_WIDE_INT nonzero;
8593 /* If we weren't given a mode, use the mode of X. If the mode is still
8594 VOIDmode, we don't know anything. Likewise if one of the modes is
8597 if (mode == VOIDmode)
8598 mode = GET_MODE (x);
8600 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8603 bitwidth = GET_MODE_BITSIZE (mode);
8605 /* For a smaller object, just ignore the high bits. */
8606 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8608 num0 = num_sign_bit_copies_with_known (x, GET_MODE (x));
8610 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8613 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8615 #ifndef WORD_REGISTER_OPERATIONS
8616 /* If this machine does not do all register operations on the entire
8617 register and MODE is wider than the mode of X, we can say nothing
8618 at all about the high-order bits. */
8621 /* Likewise on machines that do, if the mode of the object is smaller
8622 than a word and loads of that size don't sign extend, we can say
8623 nothing about the high order bits. */
8624 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8625 #ifdef LOAD_EXTEND_OP
8626 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8637 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend)
8638 /* If pointers extend signed and this is a pointer in Pmode, say that
8639 all the bits above ptr_mode are known to be sign bit copies. */
8640 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8642 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8645 if (reg_last_set_value[REGNO (x)] != 0
8646 && reg_last_set_mode[REGNO (x)] == mode
8647 && (reg_last_set_label[REGNO (x)] == label_tick
8648 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8649 && REG_N_SETS (REGNO (x)) == 1
8650 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8652 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8653 return reg_last_set_sign_bit_copies[REGNO (x)];
8655 tem = get_last_value (x);
8657 return num_sign_bit_copies_with_known (tem, mode);
8659 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0
8660 && GET_MODE_BITSIZE (GET_MODE (x)) == bitwidth)
8661 return reg_sign_bit_copies[REGNO (x)];
8665 #ifdef LOAD_EXTEND_OP
8666 /* Some RISC machines sign-extend all loads of smaller than a word. */
8667 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8668 return MAX (1, ((int) bitwidth
8669 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8674 /* If the constant is negative, take its 1's complement and remask.
8675 Then see how many zero bits we have. */
8676 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8677 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8678 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8679 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8681 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8684 /* If this is a SUBREG for a promoted object that is sign-extended
8685 and we are looking at it in a wider mode, we know that at least the
8686 high-order bits are known to be sign bit copies. */
8688 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8690 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8691 return MAX ((int) bitwidth
8692 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8696 /* For a smaller object, just ignore the high bits. */
8697 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8699 num0 = num_sign_bit_copies_with_known (SUBREG_REG (x), VOIDmode);
8700 return MAX (1, (num0
8701 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8705 #ifdef WORD_REGISTER_OPERATIONS
8706 #ifdef LOAD_EXTEND_OP
8707 /* For paradoxical SUBREGs on machines where all register operations
8708 affect the entire register, just look inside. Note that we are
8709 passing MODE to the recursive call, so the number of sign bit copies
8710 will remain relative to that mode, not the inner mode. */
8712 /* This works only if loads sign extend. Otherwise, if we get a
8713 reload for the inner part, it may be loaded from the stack, and
8714 then we lose all sign bit copies that existed before the store
8717 if ((GET_MODE_SIZE (GET_MODE (x))
8718 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8719 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8720 && GET_CODE (SUBREG_REG (x)) == MEM)
8721 return num_sign_bit_copies_with_known (SUBREG_REG (x), mode);
8727 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8728 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8732 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8733 + num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode));
8736 /* For a smaller object, just ignore the high bits. */
8737 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), VOIDmode);
8738 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8742 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8744 case ROTATE: case ROTATERT:
8745 /* If we are rotating left by a number of bits less than the number
8746 of sign bit copies, we can just subtract that amount from the
8748 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8749 && INTVAL (XEXP (x, 1)) >= 0
8750 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
8752 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8753 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8754 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8759 /* In general, this subtracts one sign bit copy. But if the value
8760 is known to be positive, the number of sign bit copies is the
8761 same as that of the input. Finally, if the input has just one bit
8762 that might be nonzero, all the bits are copies of the sign bit. */
8763 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8764 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8765 return num0 > 1 ? num0 - 1 : 1;
8767 nonzero = nonzero_bits (XEXP (x, 0), mode);
8772 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8777 case IOR: case AND: case XOR:
8778 case SMIN: case SMAX: case UMIN: case UMAX:
8779 /* Logical operations will preserve the number of sign-bit copies.
8780 MIN and MAX operations always return one of the operands. */
8781 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8782 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8783 return MIN (num0, num1);
8785 case PLUS: case MINUS:
8786 /* For addition and subtraction, we can have a 1-bit carry. However,
8787 if we are subtracting 1 from a positive number, there will not
8788 be such a carry. Furthermore, if the positive number is known to
8789 be 0 or 1, we know the result is either -1 or 0. */
8791 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8792 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8794 nonzero = nonzero_bits (XEXP (x, 0), mode);
8795 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8796 return (nonzero == 1 || nonzero == 0 ? bitwidth
8797 : bitwidth - floor_log2 (nonzero) - 1);
8800 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8801 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8802 result = MAX (1, MIN (num0, num1) - 1);
8804 #ifdef POINTERS_EXTEND_UNSIGNED
8805 /* If pointers extend signed and this is an addition or subtraction
8806 to a pointer in Pmode, all the bits above ptr_mode are known to be
8808 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8809 && (code == PLUS || code == MINUS)
8810 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8811 result = MAX ((int) (GET_MODE_BITSIZE (Pmode)
8812 - GET_MODE_BITSIZE (ptr_mode) + 1),
8818 /* The number of bits of the product is the sum of the number of
8819 bits of both terms. However, unless one of the terms if known
8820 to be positive, we must allow for an additional bit since negating
8821 a negative number can remove one sign bit copy. */
8823 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8824 num1 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8826 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8828 && (bitwidth > HOST_BITS_PER_WIDE_INT
8829 || (((nonzero_bits (XEXP (x, 0), mode)
8830 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8831 && ((nonzero_bits (XEXP (x, 1), mode)
8832 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8835 return MAX (1, result);
8838 /* The result must be <= the first operand. If the first operand
8839 has the high bit set, we know nothing about the number of sign
8841 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8843 else if ((nonzero_bits (XEXP (x, 0), mode)
8844 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8847 return num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8850 /* The result must be <= the second operand. */
8851 return num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8854 /* Similar to unsigned division, except that we have to worry about
8855 the case where the divisor is negative, in which case we have
8857 result = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8859 && (bitwidth > HOST_BITS_PER_WIDE_INT
8860 || (nonzero_bits (XEXP (x, 1), mode)
8861 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8867 result = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8869 && (bitwidth > HOST_BITS_PER_WIDE_INT
8870 || (nonzero_bits (XEXP (x, 1), mode)
8871 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8877 /* Shifts by a constant add to the number of bits equal to the
8879 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8880 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8881 && INTVAL (XEXP (x, 1)) > 0)
8882 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
8887 /* Left shifts destroy copies. */
8888 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8889 || INTVAL (XEXP (x, 1)) < 0
8890 || INTVAL (XEXP (x, 1)) >= (int) bitwidth)
8893 num0 = num_sign_bit_copies_with_known (XEXP (x, 0), mode);
8894 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8897 num0 = num_sign_bit_copies_with_known (XEXP (x, 1), mode);
8898 num1 = num_sign_bit_copies_with_known (XEXP (x, 2), mode);
8899 return MIN (num0, num1);
8901 case EQ: case NE: case GE: case GT: case LE: case LT:
8902 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8903 case GEU: case GTU: case LEU: case LTU:
8904 case UNORDERED: case ORDERED:
8905 /* If the constant is negative, take its 1's complement and remask.
8906 Then see how many zero bits we have. */
8907 nonzero = STORE_FLAG_VALUE;
8908 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8909 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8910 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8912 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8919 /* If we haven't been able to figure it out by one of the above rules,
8920 see if some of the high-order bits are known to be zero. If so,
8921 count those bits and return one less than that amount. If we can't
8922 safely compute the mask for this mode, always return BITWIDTH. */
8924 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8927 nonzero = nonzero_bits (x, mode);
8928 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8929 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8932 /* Return the number of "extended" bits there are in X, when interpreted
8933 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8934 unsigned quantities, this is the number of high-order zero bits.
8935 For signed quantities, this is the number of copies of the sign bit
8936 minus 1. In both case, this function returns the number of "spare"
8937 bits. For example, if two quantities for which this function returns
8938 at least 1 are added, the addition is known not to overflow.
8940 This function will always return 0 unless called during combine, which
8941 implies that it must be called from a define_split. */
8944 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8946 if (nonzero_sign_valid == 0)
8950 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8951 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8952 - floor_log2 (nonzero_bits (x, mode)))
8954 : num_sign_bit_copies (x, mode) - 1);
8957 /* This function is called from `simplify_shift_const' to merge two
8958 outer operations. Specifically, we have already found that we need
8959 to perform operation *POP0 with constant *PCONST0 at the outermost
8960 position. We would now like to also perform OP1 with constant CONST1
8961 (with *POP0 being done last).
8963 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8964 the resulting operation. *PCOMP_P is set to 1 if we would need to
8965 complement the innermost operand, otherwise it is unchanged.
8967 MODE is the mode in which the operation will be done. No bits outside
8968 the width of this mode matter. It is assumed that the width of this mode
8969 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8971 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8972 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8973 result is simply *PCONST0.
8975 If the resulting operation cannot be expressed as one operation, we
8976 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8979 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8981 enum rtx_code op0 = *pop0;
8982 HOST_WIDE_INT const0 = *pconst0;
8984 const0 &= GET_MODE_MASK (mode);
8985 const1 &= GET_MODE_MASK (mode);
8987 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8991 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8994 if (op1 == NIL || op0 == SET)
8997 else if (op0 == NIL)
8998 op0 = op1, const0 = const1;
9000 else if (op0 == op1)
9024 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9025 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9028 /* If the two constants aren't the same, we can't do anything. The
9029 remaining six cases can all be done. */
9030 else if (const0 != const1)
9038 /* (a & b) | b == b */
9040 else /* op1 == XOR */
9041 /* (a ^ b) | b == a | b */
9047 /* (a & b) ^ b == (~a) & b */
9048 op0 = AND, *pcomp_p = 1;
9049 else /* op1 == IOR */
9050 /* (a | b) ^ b == a & ~b */
9051 op0 = AND, const0 = ~const0;
9056 /* (a | b) & b == b */
9058 else /* op1 == XOR */
9059 /* (a ^ b) & b) == (~a) & b */
9066 /* Check for NO-OP cases. */
9067 const0 &= GET_MODE_MASK (mode);
9069 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9071 else if (const0 == 0 && op0 == AND)
9073 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9077 /* ??? Slightly redundant with the above mask, but not entirely.
9078 Moving this above means we'd have to sign-extend the mode mask
9079 for the final test. */
9080 const0 = trunc_int_for_mode (const0, mode);
9088 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9089 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
9090 that we started with.
9092 The shift is normally computed in the widest mode we find in VAROP, as
9093 long as it isn't a different number of words than RESULT_MODE. Exceptions
9094 are ASHIFTRT and ROTATE, which are always done in their original mode, */
9097 simplify_shift_const (rtx x, enum rtx_code code,
9098 enum machine_mode result_mode, rtx varop,
9101 enum rtx_code orig_code = code;
9104 enum machine_mode mode = result_mode;
9105 enum machine_mode shift_mode, tmode;
9106 unsigned int mode_words
9107 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9108 /* We form (outer_op (code varop count) (outer_const)). */
9109 enum rtx_code outer_op = NIL;
9110 HOST_WIDE_INT outer_const = 0;
9112 int complement_p = 0;
9115 /* Make sure and truncate the "natural" shift on the way in. We don't
9116 want to do this inside the loop as it makes it more difficult to
9118 #ifdef SHIFT_COUNT_TRUNCATED
9119 if (SHIFT_COUNT_TRUNCATED)
9120 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9123 /* If we were given an invalid count, don't do anything except exactly
9124 what was requested. */
9126 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9131 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
9136 /* Unless one of the branches of the `if' in this loop does a `continue',
9137 we will `break' the loop after the `if'. */
9141 /* If we have an operand of (clobber (const_int 0)), just return that
9143 if (GET_CODE (varop) == CLOBBER)
9146 /* If we discovered we had to complement VAROP, leave. Making a NOT
9147 here would cause an infinite loop. */
9151 /* Convert ROTATERT to ROTATE. */
9152 if (code == ROTATERT)
9154 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9156 if (VECTOR_MODE_P (result_mode))
9157 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9159 count = bitsize - count;
9162 /* We need to determine what mode we will do the shift in. If the
9163 shift is a right shift or a ROTATE, we must always do it in the mode
9164 it was originally done in. Otherwise, we can do it in MODE, the
9165 widest mode encountered. */
9167 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9168 ? result_mode : mode);
9170 /* Handle cases where the count is greater than the size of the mode
9171 minus 1. For ASHIFT, use the size minus one as the count (this can
9172 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9173 take the count modulo the size. For other shifts, the result is
9176 Since these shifts are being produced by the compiler by combining
9177 multiple operations, each of which are defined, we know what the
9178 result is supposed to be. */
9180 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
9182 if (code == ASHIFTRT)
9183 count = GET_MODE_BITSIZE (shift_mode) - 1;
9184 else if (code == ROTATE || code == ROTATERT)
9185 count %= GET_MODE_BITSIZE (shift_mode);
9188 /* We can't simply return zero because there may be an
9196 /* An arithmetic right shift of a quantity known to be -1 or 0
9198 if (code == ASHIFTRT
9199 && (num_sign_bit_copies (varop, shift_mode)
9200 == GET_MODE_BITSIZE (shift_mode)))
9206 /* If we are doing an arithmetic right shift and discarding all but
9207 the sign bit copies, this is equivalent to doing a shift by the
9208 bitsize minus one. Convert it into that shift because it will often
9209 allow other simplifications. */
9211 if (code == ASHIFTRT
9212 && (count + num_sign_bit_copies (varop, shift_mode)
9213 >= GET_MODE_BITSIZE (shift_mode)))
9214 count = GET_MODE_BITSIZE (shift_mode) - 1;
9216 /* We simplify the tests below and elsewhere by converting
9217 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9218 `make_compound_operation' will convert it to an ASHIFTRT for
9219 those machines (such as VAX) that don't have an LSHIFTRT. */
9220 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9222 && ((nonzero_bits (varop, shift_mode)
9223 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9227 if (code == LSHIFTRT
9228 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9229 && !(nonzero_bits (varop, shift_mode) >> count))
9232 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9233 && !((nonzero_bits (varop, shift_mode) << count)
9234 & GET_MODE_MASK (shift_mode)))
9237 switch (GET_CODE (varop))
9243 new = expand_compound_operation (varop);
9252 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9253 minus the width of a smaller mode, we can do this with a
9254 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9255 if ((code == ASHIFTRT || code == LSHIFTRT)
9256 && ! mode_dependent_address_p (XEXP (varop, 0))
9257 && ! MEM_VOLATILE_P (varop)
9258 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9259 MODE_INT, 1)) != BLKmode)
9261 new = adjust_address_nv (varop, tmode,
9262 BYTES_BIG_ENDIAN ? 0
9263 : count / BITS_PER_UNIT);
9265 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9266 : ZERO_EXTEND, mode, new);
9273 /* Similar to the case above, except that we can only do this if
9274 the resulting mode is the same as that of the underlying
9275 MEM and adjust the address depending on the *bits* endianness
9276 because of the way that bit-field extract insns are defined. */
9277 if ((code == ASHIFTRT || code == LSHIFTRT)
9278 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9279 MODE_INT, 1)) != BLKmode
9280 && tmode == GET_MODE (XEXP (varop, 0)))
9282 if (BITS_BIG_ENDIAN)
9283 new = XEXP (varop, 0);
9286 new = copy_rtx (XEXP (varop, 0));
9287 SUBST (XEXP (new, 0),
9288 plus_constant (XEXP (new, 0),
9289 count / BITS_PER_UNIT));
9292 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9293 : ZERO_EXTEND, mode, new);
9300 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9301 the same number of words as what we've seen so far. Then store
9302 the widest mode in MODE. */
9303 if (subreg_lowpart_p (varop)
9304 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9305 > GET_MODE_SIZE (GET_MODE (varop)))
9306 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9307 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9310 varop = SUBREG_REG (varop);
9311 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9312 mode = GET_MODE (varop);
9318 /* Some machines use MULT instead of ASHIFT because MULT
9319 is cheaper. But it is still better on those machines to
9320 merge two shifts into one. */
9321 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9322 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9325 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9326 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9332 /* Similar, for when divides are cheaper. */
9333 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9334 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9337 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9338 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9344 /* If we are extracting just the sign bit of an arithmetic
9345 right shift, that shift is not needed. However, the sign
9346 bit of a wider mode may be different from what would be
9347 interpreted as the sign bit in a narrower mode, so, if
9348 the result is narrower, don't discard the shift. */
9349 if (code == LSHIFTRT
9350 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9351 && (GET_MODE_BITSIZE (result_mode)
9352 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9354 varop = XEXP (varop, 0);
9358 /* ... fall through ... */
9363 /* Here we have two nested shifts. The result is usually the
9364 AND of a new shift with a mask. We compute the result below. */
9365 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9366 && INTVAL (XEXP (varop, 1)) >= 0
9367 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9368 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9369 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9371 enum rtx_code first_code = GET_CODE (varop);
9372 unsigned int first_count = INTVAL (XEXP (varop, 1));
9373 unsigned HOST_WIDE_INT mask;
9376 /* We have one common special case. We can't do any merging if
9377 the inner code is an ASHIFTRT of a smaller mode. However, if
9378 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9379 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9380 we can convert it to
9381 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9382 This simplifies certain SIGN_EXTEND operations. */
9383 if (code == ASHIFT && first_code == ASHIFTRT
9384 && count == (unsigned int)
9385 (GET_MODE_BITSIZE (result_mode)
9386 - GET_MODE_BITSIZE (GET_MODE (varop))))
9388 /* C3 has the low-order C1 bits zero. */
9390 mask = (GET_MODE_MASK (mode)
9391 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9393 varop = simplify_and_const_int (NULL_RTX, result_mode,
9394 XEXP (varop, 0), mask);
9395 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9397 count = first_count;
9402 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9403 than C1 high-order bits equal to the sign bit, we can convert
9404 this to either an ASHIFT or an ASHIFTRT depending on the
9407 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9409 if (code == ASHIFTRT && first_code == ASHIFT
9410 && GET_MODE (varop) == shift_mode
9411 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9414 varop = XEXP (varop, 0);
9416 signed_count = count - first_count;
9417 if (signed_count < 0)
9418 count = -signed_count, code = ASHIFT;
9420 count = signed_count;
9425 /* There are some cases we can't do. If CODE is ASHIFTRT,
9426 we can only do this if FIRST_CODE is also ASHIFTRT.
9428 We can't do the case when CODE is ROTATE and FIRST_CODE is
9431 If the mode of this shift is not the mode of the outer shift,
9432 we can't do this if either shift is a right shift or ROTATE.
9434 Finally, we can't do any of these if the mode is too wide
9435 unless the codes are the same.
9437 Handle the case where the shift codes are the same
9440 if (code == first_code)
9442 if (GET_MODE (varop) != result_mode
9443 && (code == ASHIFTRT || code == LSHIFTRT
9447 count += first_count;
9448 varop = XEXP (varop, 0);
9452 if (code == ASHIFTRT
9453 || (code == ROTATE && first_code == ASHIFTRT)
9454 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9455 || (GET_MODE (varop) != result_mode
9456 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9457 || first_code == ROTATE
9458 || code == ROTATE)))
9461 /* To compute the mask to apply after the shift, shift the
9462 nonzero bits of the inner shift the same way the
9463 outer shift will. */
9465 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9468 = simplify_binary_operation (code, result_mode, mask_rtx,
9471 /* Give up if we can't compute an outer operation to use. */
9473 || GET_CODE (mask_rtx) != CONST_INT
9474 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9476 result_mode, &complement_p))
9479 /* If the shifts are in the same direction, we add the
9480 counts. Otherwise, we subtract them. */
9481 signed_count = count;
9482 if ((code == ASHIFTRT || code == LSHIFTRT)
9483 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9484 signed_count += first_count;
9486 signed_count -= first_count;
9488 /* If COUNT is positive, the new shift is usually CODE,
9489 except for the two exceptions below, in which case it is
9490 FIRST_CODE. If the count is negative, FIRST_CODE should
9492 if (signed_count > 0
9493 && ((first_code == ROTATE && code == ASHIFT)
9494 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9495 code = first_code, count = signed_count;
9496 else if (signed_count < 0)
9497 code = first_code, count = -signed_count;
9499 count = signed_count;
9501 varop = XEXP (varop, 0);
9505 /* If we have (A << B << C) for any shift, we can convert this to
9506 (A << C << B). This wins if A is a constant. Only try this if
9507 B is not a constant. */
9509 else if (GET_CODE (varop) == code
9510 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9512 = simplify_binary_operation (code, mode,
9516 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9523 /* Make this fit the case below. */
9524 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9525 GEN_INT (GET_MODE_MASK (mode)));
9531 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9532 with C the size of VAROP - 1 and the shift is logical if
9533 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9534 we have an (le X 0) operation. If we have an arithmetic shift
9535 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9536 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9538 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9539 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9540 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9541 && (code == LSHIFTRT || code == ASHIFTRT)
9542 && count == (unsigned int)
9543 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9544 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9547 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9550 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9551 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9556 /* If we have (shift (logical)), move the logical to the outside
9557 to allow it to possibly combine with another logical and the
9558 shift to combine with another shift. This also canonicalizes to
9559 what a ZERO_EXTRACT looks like. Also, some machines have
9560 (and (shift)) insns. */
9562 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9563 && (new = simplify_binary_operation (code, result_mode,
9565 GEN_INT (count))) != 0
9566 && GET_CODE (new) == CONST_INT
9567 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9568 INTVAL (new), result_mode, &complement_p))
9570 varop = XEXP (varop, 0);
9574 /* If we can't do that, try to simplify the shift in each arm of the
9575 logical expression, make a new logical expression, and apply
9576 the inverse distributive law. */
9578 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9579 XEXP (varop, 0), count);
9580 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9581 XEXP (varop, 1), count);
9583 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9584 varop = apply_distributive_law (varop);
9591 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9592 says that the sign bit can be tested, FOO has mode MODE, C is
9593 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9594 that may be nonzero. */
9595 if (code == LSHIFTRT
9596 && XEXP (varop, 1) == const0_rtx
9597 && GET_MODE (XEXP (varop, 0)) == result_mode
9598 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9599 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9600 && ((STORE_FLAG_VALUE
9601 & ((HOST_WIDE_INT) 1
9602 < (GET_MODE_BITSIZE (result_mode) - 1))))
9603 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9604 && merge_outer_ops (&outer_op, &outer_const, XOR,
9605 (HOST_WIDE_INT) 1, result_mode,
9608 varop = XEXP (varop, 0);
9615 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9616 than the number of bits in the mode is equivalent to A. */
9617 if (code == LSHIFTRT
9618 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9619 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9621 varop = XEXP (varop, 0);
9626 /* NEG commutes with ASHIFT since it is multiplication. Move the
9627 NEG outside to allow shifts to combine. */
9629 && merge_outer_ops (&outer_op, &outer_const, NEG,
9630 (HOST_WIDE_INT) 0, result_mode,
9633 varop = XEXP (varop, 0);
9639 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9640 is one less than the number of bits in the mode is
9641 equivalent to (xor A 1). */
9642 if (code == LSHIFTRT
9643 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9644 && XEXP (varop, 1) == constm1_rtx
9645 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9646 && merge_outer_ops (&outer_op, &outer_const, XOR,
9647 (HOST_WIDE_INT) 1, result_mode,
9651 varop = XEXP (varop, 0);
9655 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9656 that might be nonzero in BAR are those being shifted out and those
9657 bits are known zero in FOO, we can replace the PLUS with FOO.
9658 Similarly in the other operand order. This code occurs when
9659 we are computing the size of a variable-size array. */
9661 if ((code == ASHIFTRT || code == LSHIFTRT)
9662 && count < HOST_BITS_PER_WIDE_INT
9663 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9664 && (nonzero_bits (XEXP (varop, 1), result_mode)
9665 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9667 varop = XEXP (varop, 0);
9670 else if ((code == ASHIFTRT || code == LSHIFTRT)
9671 && count < HOST_BITS_PER_WIDE_INT
9672 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9673 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9675 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9676 & nonzero_bits (XEXP (varop, 1),
9679 varop = XEXP (varop, 1);
9683 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9685 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9686 && (new = simplify_binary_operation (ASHIFT, result_mode,
9688 GEN_INT (count))) != 0
9689 && GET_CODE (new) == CONST_INT
9690 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9691 INTVAL (new), result_mode, &complement_p))
9693 varop = XEXP (varop, 0);
9699 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9700 with C the size of VAROP - 1 and the shift is logical if
9701 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9702 we have a (gt X 0) operation. If the shift is arithmetic with
9703 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9704 we have a (neg (gt X 0)) operation. */
9706 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9707 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9708 && count == (unsigned int)
9709 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9710 && (code == LSHIFTRT || code == ASHIFTRT)
9711 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9712 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9714 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9717 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9720 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9721 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9728 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9729 if the truncate does not affect the value. */
9730 if (code == LSHIFTRT
9731 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9732 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9733 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9734 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9735 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9737 rtx varop_inner = XEXP (varop, 0);
9740 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9741 XEXP (varop_inner, 0),
9743 (count + INTVAL (XEXP (varop_inner, 1))));
9744 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9757 /* We need to determine what mode to do the shift in. If the shift is
9758 a right shift or ROTATE, we must always do it in the mode it was
9759 originally done in. Otherwise, we can do it in MODE, the widest mode
9760 encountered. The code we care about is that of the shift that will
9761 actually be done, not the shift that was originally requested. */
9763 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9764 ? result_mode : mode);
9766 /* We have now finished analyzing the shift. The result should be
9767 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9768 OUTER_OP is non-NIL, it is an operation that needs to be applied
9769 to the result of the shift. OUTER_CONST is the relevant constant,
9770 but we must turn off all bits turned off in the shift.
9772 If we were passed a value for X, see if we can use any pieces of
9773 it. If not, make new rtx. */
9775 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9776 && GET_CODE (XEXP (x, 1)) == CONST_INT
9777 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9778 const_rtx = XEXP (x, 1);
9780 const_rtx = GEN_INT (count);
9782 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9783 && GET_MODE (XEXP (x, 0)) == shift_mode
9784 && SUBREG_REG (XEXP (x, 0)) == varop)
9785 varop = XEXP (x, 0);
9786 else if (GET_MODE (varop) != shift_mode)
9787 varop = gen_lowpart_for_combine (shift_mode, varop);
9789 /* If we can't make the SUBREG, try to return what we were given. */
9790 if (GET_CODE (varop) == CLOBBER)
9791 return x ? x : varop;
9793 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9797 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9799 /* If we have an outer operation and we just made a shift, it is
9800 possible that we could have simplified the shift were it not
9801 for the outer operation. So try to do the simplification
9804 if (outer_op != NIL && GET_CODE (x) == code
9805 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9806 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9807 INTVAL (XEXP (x, 1)));
9809 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9810 turn off all the bits that the shift would have turned off. */
9811 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9812 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9813 GET_MODE_MASK (result_mode) >> orig_count);
9815 /* Do the remainder of the processing in RESULT_MODE. */
9816 x = gen_lowpart_for_combine (result_mode, x);
9818 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9821 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9823 if (outer_op != NIL)
9825 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9826 outer_const = trunc_int_for_mode (outer_const, result_mode);
9828 if (outer_op == AND)
9829 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9830 else if (outer_op == SET)
9831 /* This means that we have determined that the result is
9832 equivalent to a constant. This should be rare. */
9833 x = GEN_INT (outer_const);
9834 else if (GET_RTX_CLASS (outer_op) == '1')
9835 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9837 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9843 /* Like recog, but we receive the address of a pointer to a new pattern.
9844 We try to match the rtx that the pointer points to.
9845 If that fails, we may try to modify or replace the pattern,
9846 storing the replacement into the same pointer object.
9848 Modifications include deletion or addition of CLOBBERs.
9850 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9851 the CLOBBERs are placed.
9853 The value is the final insn code from the pattern ultimately matched,
9857 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9860 int insn_code_number;
9861 int num_clobbers_to_add = 0;
9866 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9867 we use to indicate that something didn't match. If we find such a
9868 thing, force rejection. */
9869 if (GET_CODE (pat) == PARALLEL)
9870 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9871 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9872 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9875 /* *pnewpat does not have to be actual PATTERN (insn), so make a dummy
9876 instruction for pattern recognition. */
9877 dummy_insn = shallow_copy_rtx (insn);
9878 PATTERN (dummy_insn) = pat;
9879 REG_NOTES (dummy_insn) = 0;
9881 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9883 /* If it isn't, there is the possibility that we previously had an insn
9884 that clobbered some register as a side effect, but the combined
9885 insn doesn't need to do that. So try once more without the clobbers
9886 unless this represents an ASM insn. */
9888 if (insn_code_number < 0 && ! check_asm_operands (pat)
9889 && GET_CODE (pat) == PARALLEL)
9893 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9894 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9897 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9901 SUBST_INT (XVECLEN (pat, 0), pos);
9904 pat = XVECEXP (pat, 0, 0);
9906 PATTERN (dummy_insn) = pat;
9907 insn_code_number = recog (pat, dummy_insn, &num_clobbers_to_add);
9910 /* Recognize all noop sets, these will be killed by followup pass. */
9911 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9912 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9914 /* If we had any clobbers to add, make a new pattern than contains
9915 them. Then check to make sure that all of them are dead. */
9916 if (num_clobbers_to_add)
9918 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9919 rtvec_alloc (GET_CODE (pat) == PARALLEL
9921 + num_clobbers_to_add)
9922 : num_clobbers_to_add + 1));
9924 if (GET_CODE (pat) == PARALLEL)
9925 for (i = 0; i < XVECLEN (pat, 0); i++)
9926 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9928 XVECEXP (newpat, 0, 0) = pat;
9930 add_clobbers (newpat, insn_code_number);
9932 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9933 i < XVECLEN (newpat, 0); i++)
9935 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9936 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9938 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9939 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9947 return insn_code_number;
9950 /* Like gen_lowpart but for use by combine. In combine it is not possible
9951 to create any new pseudoregs. However, it is safe to create
9952 invalid memory addresses, because combine will try to recognize
9953 them and all they will do is make the combine attempt fail.
9955 If for some reason this cannot do its job, an rtx
9956 (clobber (const_int 0)) is returned.
9957 An insn containing that will not be recognized. */
9962 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9966 if (GET_MODE (x) == mode)
9969 /* Return identity if this is a CONST or symbolic
9972 && (GET_CODE (x) == CONST
9973 || GET_CODE (x) == SYMBOL_REF
9974 || GET_CODE (x) == LABEL_REF))
9977 /* We can only support MODE being wider than a word if X is a
9978 constant integer or has a mode the same size. */
9980 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9981 && ! ((GET_MODE (x) == VOIDmode
9982 && (GET_CODE (x) == CONST_INT
9983 || GET_CODE (x) == CONST_DOUBLE))
9984 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9985 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9987 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9988 won't know what to do. So we will strip off the SUBREG here and
9989 process normally. */
9990 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9993 if (GET_MODE (x) == mode)
9997 result = gen_lowpart_common (mode, x);
9998 #ifdef CANNOT_CHANGE_MODE_CLASS
10000 && GET_CODE (result) == SUBREG
10001 && GET_CODE (SUBREG_REG (result)) == REG
10002 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
10003 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
10005 + GET_MODE (result));
10011 if (GET_CODE (x) == MEM)
10015 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10017 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10018 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10020 /* If we want to refer to something bigger than the original memref,
10021 generate a perverse subreg instead. That will force a reload
10022 of the original memref X. */
10023 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
10024 return gen_rtx_SUBREG (mode, x, 0);
10026 if (WORDS_BIG_ENDIAN)
10027 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
10028 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
10030 if (BYTES_BIG_ENDIAN)
10032 /* Adjust the address so that the address-after-the-data is
10034 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
10035 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
10038 return adjust_address_nv (x, mode, offset);
10041 /* If X is a comparison operator, rewrite it in a new mode. This
10042 probably won't match, but may allow further simplifications. */
10043 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
10044 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
10046 /* If we couldn't simplify X any other way, just enclose it in a
10047 SUBREG. Normally, this SUBREG won't match, but some patterns may
10048 include an explicit SUBREG or we may simplify it further in combine. */
10053 enum machine_mode sub_mode = GET_MODE (x);
10055 offset = subreg_lowpart_offset (mode, sub_mode);
10056 if (sub_mode == VOIDmode)
10058 sub_mode = int_mode_for_mode (mode);
10059 x = gen_lowpart_common (sub_mode, x);
10061 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
10063 res = simplify_gen_subreg (mode, x, sub_mode, offset);
10066 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10070 /* These routines make binary and unary operations by first seeing if they
10071 fold; if not, a new expression is allocated. */
10074 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
10079 if (GET_CODE (op0) == CLOBBER)
10081 else if (GET_CODE (op1) == CLOBBER)
10084 if (GET_RTX_CLASS (code) == 'c'
10085 && swap_commutative_operands_p (op0, op1))
10086 tem = op0, op0 = op1, op1 = tem;
10088 if (GET_RTX_CLASS (code) == '<')
10090 enum machine_mode op_mode = GET_MODE (op0);
10092 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
10093 just (REL_OP X Y). */
10094 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
10096 op1 = XEXP (op0, 1);
10097 op0 = XEXP (op0, 0);
10098 op_mode = GET_MODE (op0);
10101 if (op_mode == VOIDmode)
10102 op_mode = GET_MODE (op1);
10103 result = simplify_relational_operation (code, op_mode, op0, op1);
10106 result = simplify_binary_operation (code, mode, op0, op1);
10111 /* Put complex operands first and constants second. */
10112 if (GET_RTX_CLASS (code) == 'c'
10113 && swap_commutative_operands_p (op0, op1))
10114 return gen_rtx_fmt_ee (code, mode, op1, op0);
10116 /* If we are turning off bits already known off in OP0, we need not do
10118 else if (code == AND && GET_CODE (op1) == CONST_INT
10119 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10120 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10123 return gen_rtx_fmt_ee (code, mode, op0, op1);
10126 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10127 comparison code that will be tested.
10129 The result is a possibly different comparison code to use. *POP0 and
10130 *POP1 may be updated.
10132 It is possible that we might detect that a comparison is either always
10133 true or always false. However, we do not perform general constant
10134 folding in combine, so this knowledge isn't useful. Such tautologies
10135 should have been detected earlier. Hence we ignore all such cases. */
10137 static enum rtx_code
10138 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10144 enum machine_mode mode, tmode;
10146 /* Try a few ways of applying the same transformation to both operands. */
10149 #ifndef WORD_REGISTER_OPERATIONS
10150 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10151 so check specially. */
10152 if (code != GTU && code != GEU && code != LTU && code != LEU
10153 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10154 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10155 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10156 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10157 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10158 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10159 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10160 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10161 && XEXP (op0, 1) == XEXP (op1, 1)
10162 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10163 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10164 && (INTVAL (XEXP (op0, 1))
10165 == (GET_MODE_BITSIZE (GET_MODE (op0))
10166 - (GET_MODE_BITSIZE
10167 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10169 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10170 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10174 /* If both operands are the same constant shift, see if we can ignore the
10175 shift. We can if the shift is a rotate or if the bits shifted out of
10176 this shift are known to be zero for both inputs and if the type of
10177 comparison is compatible with the shift. */
10178 if (GET_CODE (op0) == GET_CODE (op1)
10179 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10180 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10181 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10182 && (code != GT && code != LT && code != GE && code != LE))
10183 || (GET_CODE (op0) == ASHIFTRT
10184 && (code != GTU && code != LTU
10185 && code != GEU && code != LEU)))
10186 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10187 && INTVAL (XEXP (op0, 1)) >= 0
10188 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10189 && XEXP (op0, 1) == XEXP (op1, 1))
10191 enum machine_mode mode = GET_MODE (op0);
10192 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10193 int shift_count = INTVAL (XEXP (op0, 1));
10195 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10196 mask &= (mask >> shift_count) << shift_count;
10197 else if (GET_CODE (op0) == ASHIFT)
10198 mask = (mask & (mask << shift_count)) >> shift_count;
10200 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10201 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10202 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10207 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10208 SUBREGs are of the same mode, and, in both cases, the AND would
10209 be redundant if the comparison was done in the narrower mode,
10210 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10211 and the operand's possibly nonzero bits are 0xffffff01; in that case
10212 if we only care about QImode, we don't need the AND). This case
10213 occurs if the output mode of an scc insn is not SImode and
10214 STORE_FLAG_VALUE == 1 (e.g., the 386).
10216 Similarly, check for a case where the AND's are ZERO_EXTEND
10217 operations from some narrower mode even though a SUBREG is not
10220 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10221 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10222 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10224 rtx inner_op0 = XEXP (op0, 0);
10225 rtx inner_op1 = XEXP (op1, 0);
10226 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10227 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10230 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10231 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10232 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10233 && (GET_MODE (SUBREG_REG (inner_op0))
10234 == GET_MODE (SUBREG_REG (inner_op1)))
10235 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10236 <= HOST_BITS_PER_WIDE_INT)
10237 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10238 GET_MODE (SUBREG_REG (inner_op0)))))
10239 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10240 GET_MODE (SUBREG_REG (inner_op1))))))
10242 op0 = SUBREG_REG (inner_op0);
10243 op1 = SUBREG_REG (inner_op1);
10245 /* The resulting comparison is always unsigned since we masked
10246 off the original sign bit. */
10247 code = unsigned_condition (code);
10253 for (tmode = GET_CLASS_NARROWEST_MODE
10254 (GET_MODE_CLASS (GET_MODE (op0)));
10255 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10256 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10258 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10259 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10260 code = unsigned_condition (code);
10269 /* If both operands are NOT, we can strip off the outer operation
10270 and adjust the comparison code for swapped operands; similarly for
10271 NEG, except that this must be an equality comparison. */
10272 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10273 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10274 && (code == EQ || code == NE)))
10275 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10281 /* If the first operand is a constant, swap the operands and adjust the
10282 comparison code appropriately, but don't do this if the second operand
10283 is already a constant integer. */
10284 if (swap_commutative_operands_p (op0, op1))
10286 tem = op0, op0 = op1, op1 = tem;
10287 code = swap_condition (code);
10290 /* We now enter a loop during which we will try to simplify the comparison.
10291 For the most part, we only are concerned with comparisons with zero,
10292 but some things may really be comparisons with zero but not start
10293 out looking that way. */
10295 while (GET_CODE (op1) == CONST_INT)
10297 enum machine_mode mode = GET_MODE (op0);
10298 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10299 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10300 int equality_comparison_p;
10301 int sign_bit_comparison_p;
10302 int unsigned_comparison_p;
10303 HOST_WIDE_INT const_op;
10305 /* We only want to handle integral modes. This catches VOIDmode,
10306 CCmode, and the floating-point modes. An exception is that we
10307 can handle VOIDmode if OP0 is a COMPARE or a comparison
10310 if (GET_MODE_CLASS (mode) != MODE_INT
10311 && ! (mode == VOIDmode
10312 && (GET_CODE (op0) == COMPARE
10313 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10316 /* Get the constant we are comparing against and turn off all bits
10317 not on in our mode. */
10318 const_op = INTVAL (op1);
10319 if (mode != VOIDmode)
10320 const_op = trunc_int_for_mode (const_op, mode);
10321 op1 = GEN_INT (const_op);
10323 /* If we are comparing against a constant power of two and the value
10324 being compared can only have that single bit nonzero (e.g., it was
10325 `and'ed with that bit), we can replace this with a comparison
10328 && (code == EQ || code == NE || code == GE || code == GEU
10329 || code == LT || code == LTU)
10330 && mode_width <= HOST_BITS_PER_WIDE_INT
10331 && exact_log2 (const_op) >= 0
10332 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10334 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10335 op1 = const0_rtx, const_op = 0;
10338 /* Similarly, if we are comparing a value known to be either -1 or
10339 0 with -1, change it to the opposite comparison against zero. */
10342 && (code == EQ || code == NE || code == GT || code == LE
10343 || code == GEU || code == LTU)
10344 && num_sign_bit_copies (op0, mode) == mode_width)
10346 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10347 op1 = const0_rtx, const_op = 0;
10350 /* Do some canonicalizations based on the comparison code. We prefer
10351 comparisons against zero and then prefer equality comparisons.
10352 If we can reduce the size of a constant, we will do that too. */
10357 /* < C is equivalent to <= (C - 1) */
10361 op1 = GEN_INT (const_op);
10363 /* ... fall through to LE case below. */
10369 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10373 op1 = GEN_INT (const_op);
10377 /* If we are doing a <= 0 comparison on a value known to have
10378 a zero sign bit, we can replace this with == 0. */
10379 else if (const_op == 0
10380 && mode_width <= HOST_BITS_PER_WIDE_INT
10381 && (nonzero_bits (op0, mode)
10382 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10387 /* >= C is equivalent to > (C - 1). */
10391 op1 = GEN_INT (const_op);
10393 /* ... fall through to GT below. */
10399 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10403 op1 = GEN_INT (const_op);
10407 /* If we are doing a > 0 comparison on a value known to have
10408 a zero sign bit, we can replace this with != 0. */
10409 else if (const_op == 0
10410 && mode_width <= HOST_BITS_PER_WIDE_INT
10411 && (nonzero_bits (op0, mode)
10412 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10417 /* < C is equivalent to <= (C - 1). */
10421 op1 = GEN_INT (const_op);
10423 /* ... fall through ... */
10426 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10427 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10428 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10430 const_op = 0, op1 = const0_rtx;
10438 /* unsigned <= 0 is equivalent to == 0 */
10442 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10443 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10444 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10446 const_op = 0, op1 = const0_rtx;
10452 /* >= C is equivalent to < (C - 1). */
10456 op1 = GEN_INT (const_op);
10458 /* ... fall through ... */
10461 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10462 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10463 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10465 const_op = 0, op1 = const0_rtx;
10473 /* unsigned > 0 is equivalent to != 0 */
10477 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10478 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10479 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10481 const_op = 0, op1 = const0_rtx;
10490 /* Compute some predicates to simplify code below. */
10492 equality_comparison_p = (code == EQ || code == NE);
10493 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10494 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10497 /* If this is a sign bit comparison and we can do arithmetic in
10498 MODE, say that we will only be needing the sign bit of OP0. */
10499 if (sign_bit_comparison_p
10500 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10501 op0 = force_to_mode (op0, mode,
10503 << (GET_MODE_BITSIZE (mode) - 1)),
10506 /* Now try cases based on the opcode of OP0. If none of the cases
10507 does a "continue", we exit this loop immediately after the
10510 switch (GET_CODE (op0))
10513 /* If we are extracting a single bit from a variable position in
10514 a constant that has only a single bit set and are comparing it
10515 with zero, we can convert this into an equality comparison
10516 between the position and the location of the single bit. */
10518 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10519 && XEXP (op0, 1) == const1_rtx
10520 && equality_comparison_p && const_op == 0
10521 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10523 if (BITS_BIG_ENDIAN)
10525 enum machine_mode new_mode
10526 = mode_for_extraction (EP_extzv, 1);
10527 if (new_mode == MAX_MACHINE_MODE)
10528 i = BITS_PER_WORD - 1 - i;
10532 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10536 op0 = XEXP (op0, 2);
10540 /* Result is nonzero iff shift count is equal to I. */
10541 code = reverse_condition (code);
10545 /* ... fall through ... */
10548 tem = expand_compound_operation (op0);
10557 /* If testing for equality, we can take the NOT of the constant. */
10558 if (equality_comparison_p
10559 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10561 op0 = XEXP (op0, 0);
10566 /* If just looking at the sign bit, reverse the sense of the
10568 if (sign_bit_comparison_p)
10570 op0 = XEXP (op0, 0);
10571 code = (code == GE ? LT : GE);
10577 /* If testing for equality, we can take the NEG of the constant. */
10578 if (equality_comparison_p
10579 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10581 op0 = XEXP (op0, 0);
10586 /* The remaining cases only apply to comparisons with zero. */
10590 /* When X is ABS or is known positive,
10591 (neg X) is < 0 if and only if X != 0. */
10593 if (sign_bit_comparison_p
10594 && (GET_CODE (XEXP (op0, 0)) == ABS
10595 || (mode_width <= HOST_BITS_PER_WIDE_INT
10596 && (nonzero_bits (XEXP (op0, 0), mode)
10597 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10599 op0 = XEXP (op0, 0);
10600 code = (code == LT ? NE : EQ);
10604 /* If we have NEG of something whose two high-order bits are the
10605 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10606 if (num_sign_bit_copies (op0, mode) >= 2)
10608 op0 = XEXP (op0, 0);
10609 code = swap_condition (code);
10615 /* If we are testing equality and our count is a constant, we
10616 can perform the inverse operation on our RHS. */
10617 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10618 && (tem = simplify_binary_operation (ROTATERT, mode,
10619 op1, XEXP (op0, 1))) != 0)
10621 op0 = XEXP (op0, 0);
10626 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10627 a particular bit. Convert it to an AND of a constant of that
10628 bit. This will be converted into a ZERO_EXTRACT. */
10629 if (const_op == 0 && sign_bit_comparison_p
10630 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10631 && mode_width <= HOST_BITS_PER_WIDE_INT)
10633 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10636 - INTVAL (XEXP (op0, 1)))));
10637 code = (code == LT ? NE : EQ);
10641 /* Fall through. */
10644 /* ABS is ignorable inside an equality comparison with zero. */
10645 if (const_op == 0 && equality_comparison_p)
10647 op0 = XEXP (op0, 0);
10653 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10654 to (compare FOO CONST) if CONST fits in FOO's mode and we
10655 are either testing inequality or have an unsigned comparison
10656 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10657 if (! unsigned_comparison_p
10658 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10659 <= HOST_BITS_PER_WIDE_INT)
10660 && ((unsigned HOST_WIDE_INT) const_op
10661 < (((unsigned HOST_WIDE_INT) 1
10662 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10664 op0 = XEXP (op0, 0);
10670 /* Check for the case where we are comparing A - C1 with C2,
10671 both constants are smaller than 1/2 the maximum positive
10672 value in MODE, and the comparison is equality or unsigned.
10673 In that case, if A is either zero-extended to MODE or has
10674 sufficient sign bits so that the high-order bit in MODE
10675 is a copy of the sign in the inner mode, we can prove that it is
10676 safe to do the operation in the wider mode. This simplifies
10677 many range checks. */
10679 if (mode_width <= HOST_BITS_PER_WIDE_INT
10680 && subreg_lowpart_p (op0)
10681 && GET_CODE (SUBREG_REG (op0)) == PLUS
10682 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10683 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10684 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10685 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10686 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10687 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10688 GET_MODE (SUBREG_REG (op0)))
10689 & ~GET_MODE_MASK (mode))
10690 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10691 GET_MODE (SUBREG_REG (op0)))
10693 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10694 - GET_MODE_BITSIZE (mode)))))
10696 op0 = SUBREG_REG (op0);
10700 /* If the inner mode is narrower and we are extracting the low part,
10701 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10702 if (subreg_lowpart_p (op0)
10703 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10704 /* Fall through */ ;
10708 /* ... fall through ... */
10711 if ((unsigned_comparison_p || equality_comparison_p)
10712 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10713 <= HOST_BITS_PER_WIDE_INT)
10714 && ((unsigned HOST_WIDE_INT) const_op
10715 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10717 op0 = XEXP (op0, 0);
10723 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10724 this for equality comparisons due to pathological cases involving
10726 if (equality_comparison_p
10727 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10728 op1, XEXP (op0, 1))))
10730 op0 = XEXP (op0, 0);
10735 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10736 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10737 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10739 op0 = XEXP (XEXP (op0, 0), 0);
10740 code = (code == LT ? EQ : NE);
10746 /* We used to optimize signed comparisons against zero, but that
10747 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10748 arrive here as equality comparisons, or (GEU, LTU) are
10749 optimized away. No need to special-case them. */
10751 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10752 (eq B (minus A C)), whichever simplifies. We can only do
10753 this for equality comparisons due to pathological cases involving
10755 if (equality_comparison_p
10756 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10757 XEXP (op0, 1), op1)))
10759 op0 = XEXP (op0, 0);
10764 if (equality_comparison_p
10765 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10766 XEXP (op0, 0), op1)))
10768 op0 = XEXP (op0, 1);
10773 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10774 of bits in X minus 1, is one iff X > 0. */
10775 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10776 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10777 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10779 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10781 op0 = XEXP (op0, 1);
10782 code = (code == GE ? LE : GT);
10788 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10789 if C is zero or B is a constant. */
10790 if (equality_comparison_p
10791 && 0 != (tem = simplify_binary_operation (XOR, mode,
10792 XEXP (op0, 1), op1)))
10794 op0 = XEXP (op0, 0);
10801 case UNEQ: case LTGT:
10802 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10803 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10804 case UNORDERED: case ORDERED:
10805 /* We can't do anything if OP0 is a condition code value, rather
10806 than an actual data value. */
10808 || CC0_P (XEXP (op0, 0))
10809 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10812 /* Get the two operands being compared. */
10813 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10814 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10816 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10818 /* Check for the cases where we simply want the result of the
10819 earlier test or the opposite of that result. */
10820 if (code == NE || code == EQ
10821 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10822 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10823 && (STORE_FLAG_VALUE
10824 & (((HOST_WIDE_INT) 1
10825 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10826 && (code == LT || code == GE)))
10828 enum rtx_code new_code;
10829 if (code == LT || code == NE)
10830 new_code = GET_CODE (op0);
10832 new_code = combine_reversed_comparison_code (op0);
10834 if (new_code != UNKNOWN)
10845 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10847 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10848 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10849 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10851 op0 = XEXP (op0, 1);
10852 code = (code == GE ? GT : LE);
10858 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10859 will be converted to a ZERO_EXTRACT later. */
10860 if (const_op == 0 && equality_comparison_p
10861 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10862 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10864 op0 = simplify_and_const_int
10865 (op0, mode, gen_rtx_LSHIFTRT (mode,
10867 XEXP (XEXP (op0, 0), 1)),
10868 (HOST_WIDE_INT) 1);
10872 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10873 zero and X is a comparison and C1 and C2 describe only bits set
10874 in STORE_FLAG_VALUE, we can compare with X. */
10875 if (const_op == 0 && equality_comparison_p
10876 && mode_width <= HOST_BITS_PER_WIDE_INT
10877 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10878 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10879 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10880 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10881 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10883 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10884 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10885 if ((~STORE_FLAG_VALUE & mask) == 0
10886 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10887 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10888 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10890 op0 = XEXP (XEXP (op0, 0), 0);
10895 /* If we are doing an equality comparison of an AND of a bit equal
10896 to the sign bit, replace this with a LT or GE comparison of
10897 the underlying value. */
10898 if (equality_comparison_p
10900 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10901 && mode_width <= HOST_BITS_PER_WIDE_INT
10902 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10903 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10905 op0 = XEXP (op0, 0);
10906 code = (code == EQ ? GE : LT);
10910 /* If this AND operation is really a ZERO_EXTEND from a narrower
10911 mode, the constant fits within that mode, and this is either an
10912 equality or unsigned comparison, try to do this comparison in
10913 the narrower mode. */
10914 if ((equality_comparison_p || unsigned_comparison_p)
10915 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10916 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10917 & GET_MODE_MASK (mode))
10919 && const_op >> i == 0
10920 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10922 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10926 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10927 fits in both M1 and M2 and the SUBREG is either paradoxical
10928 or represents the low part, permute the SUBREG and the AND
10930 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10932 unsigned HOST_WIDE_INT c1;
10933 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10934 /* Require an integral mode, to avoid creating something like
10936 if (SCALAR_INT_MODE_P (tmode)
10937 /* It is unsafe to commute the AND into the SUBREG if the
10938 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10939 not defined. As originally written the upper bits
10940 have a defined value due to the AND operation.
10941 However, if we commute the AND inside the SUBREG then
10942 they no longer have defined values and the meaning of
10943 the code has been changed. */
10945 #ifdef WORD_REGISTER_OPERATIONS
10946 || (mode_width > GET_MODE_BITSIZE (tmode)
10947 && mode_width <= BITS_PER_WORD)
10949 || (mode_width <= GET_MODE_BITSIZE (tmode)
10950 && subreg_lowpart_p (XEXP (op0, 0))))
10951 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10952 && mode_width <= HOST_BITS_PER_WIDE_INT
10953 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10954 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10955 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10957 && c1 != GET_MODE_MASK (tmode))
10959 op0 = gen_binary (AND, tmode,
10960 SUBREG_REG (XEXP (op0, 0)),
10961 gen_int_mode (c1, tmode));
10962 op0 = gen_lowpart_for_combine (mode, op0);
10967 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10968 if (const_op == 0 && equality_comparison_p
10969 && XEXP (op0, 1) == const1_rtx
10970 && GET_CODE (XEXP (op0, 0)) == NOT)
10972 op0 = simplify_and_const_int
10973 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10974 code = (code == NE ? EQ : NE);
10978 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10979 (eq (and (lshiftrt X) 1) 0).
10980 Also handle the case where (not X) is expressed using xor. */
10981 if (const_op == 0 && equality_comparison_p
10982 && XEXP (op0, 1) == const1_rtx
10983 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10985 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10986 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10988 if (GET_CODE (shift_op) == NOT
10989 || (GET_CODE (shift_op) == XOR
10990 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10991 && GET_CODE (shift_count) == CONST_INT
10992 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10993 && (INTVAL (XEXP (shift_op, 1))
10994 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10996 op0 = simplify_and_const_int
10998 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10999 (HOST_WIDE_INT) 1);
11000 code = (code == NE ? EQ : NE);
11007 /* If we have (compare (ashift FOO N) (const_int C)) and
11008 the high order N bits of FOO (N+1 if an inequality comparison)
11009 are known to be zero, we can do this by comparing FOO with C
11010 shifted right N bits so long as the low-order N bits of C are
11012 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11013 && INTVAL (XEXP (op0, 1)) >= 0
11014 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11015 < HOST_BITS_PER_WIDE_INT)
11017 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
11018 && mode_width <= HOST_BITS_PER_WIDE_INT
11019 && (nonzero_bits (XEXP (op0, 0), mode)
11020 & ~(mask >> (INTVAL (XEXP (op0, 1))
11021 + ! equality_comparison_p))) == 0)
11023 /* We must perform a logical shift, not an arithmetic one,
11024 as we want the top N bits of C to be zero. */
11025 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11027 temp >>= INTVAL (XEXP (op0, 1));
11028 op1 = gen_int_mode (temp, mode);
11029 op0 = XEXP (op0, 0);
11033 /* If we are doing a sign bit comparison, it means we are testing
11034 a particular bit. Convert it to the appropriate AND. */
11035 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
11036 && mode_width <= HOST_BITS_PER_WIDE_INT)
11038 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11041 - INTVAL (XEXP (op0, 1)))));
11042 code = (code == LT ? NE : EQ);
11046 /* If this an equality comparison with zero and we are shifting
11047 the low bit to the sign bit, we can convert this to an AND of the
11049 if (const_op == 0 && equality_comparison_p
11050 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11051 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11054 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11055 (HOST_WIDE_INT) 1);
11061 /* If this is an equality comparison with zero, we can do this
11062 as a logical shift, which might be much simpler. */
11063 if (equality_comparison_p && const_op == 0
11064 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
11066 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11068 INTVAL (XEXP (op0, 1)));
11072 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11073 do the comparison in a narrower mode. */
11074 if (! unsigned_comparison_p
11075 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11076 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11077 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11078 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11079 MODE_INT, 1)) != BLKmode
11080 && (((unsigned HOST_WIDE_INT) const_op
11081 + (GET_MODE_MASK (tmode) >> 1) + 1)
11082 <= GET_MODE_MASK (tmode)))
11084 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
11088 /* Likewise if OP0 is a PLUS of a sign extension with a
11089 constant, which is usually represented with the PLUS
11090 between the shifts. */
11091 if (! unsigned_comparison_p
11092 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11093 && GET_CODE (XEXP (op0, 0)) == PLUS
11094 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
11095 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11096 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11097 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11098 MODE_INT, 1)) != BLKmode
11099 && (((unsigned HOST_WIDE_INT) const_op
11100 + (GET_MODE_MASK (tmode) >> 1) + 1)
11101 <= GET_MODE_MASK (tmode)))
11103 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11104 rtx add_const = XEXP (XEXP (op0, 0), 1);
11105 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
11108 op0 = gen_binary (PLUS, tmode,
11109 gen_lowpart_for_combine (tmode, inner),
11114 /* ... fall through ... */
11116 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11117 the low order N bits of FOO are known to be zero, we can do this
11118 by comparing FOO with C shifted left N bits so long as no
11119 overflow occurs. */
11120 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11121 && INTVAL (XEXP (op0, 1)) >= 0
11122 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11123 && mode_width <= HOST_BITS_PER_WIDE_INT
11124 && (nonzero_bits (XEXP (op0, 0), mode)
11125 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11126 && (((unsigned HOST_WIDE_INT) const_op
11127 + (GET_CODE (op0) != LSHIFTRT
11128 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11131 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11133 /* If the shift was logical, then we must make the condition
11135 if (GET_CODE (op0) == LSHIFTRT)
11136 code = unsigned_condition (code);
11138 const_op <<= INTVAL (XEXP (op0, 1));
11139 op1 = GEN_INT (const_op);
11140 op0 = XEXP (op0, 0);
11144 /* If we are using this shift to extract just the sign bit, we
11145 can replace this with an LT or GE comparison. */
11147 && (equality_comparison_p || sign_bit_comparison_p)
11148 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11149 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11152 op0 = XEXP (op0, 0);
11153 code = (code == NE || code == GT ? LT : GE);
11165 /* Now make any compound operations involved in this comparison. Then,
11166 check for an outmost SUBREG on OP0 that is not doing anything or is
11167 paradoxical. The latter transformation must only be performed when
11168 it is known that the "extra" bits will be the same in op0 and op1 or
11169 that they don't matter. There are three cases to consider:
11171 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11172 care bits and we can assume they have any convenient value. So
11173 making the transformation is safe.
11175 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11176 In this case the upper bits of op0 are undefined. We should not make
11177 the simplification in that case as we do not know the contents of
11180 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11181 NIL. In that case we know those bits are zeros or ones. We must
11182 also be sure that they are the same as the upper bits of op1.
11184 We can never remove a SUBREG for a non-equality comparison because
11185 the sign bit is in a different place in the underlying object. */
11187 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11188 op1 = make_compound_operation (op1, SET);
11190 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11191 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11192 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11193 && (code == NE || code == EQ))
11195 if (GET_MODE_SIZE (GET_MODE (op0))
11196 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11198 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11200 if (GET_CODE (SUBREG_REG (op0)) == REG)
11202 op0 = SUBREG_REG (op0);
11203 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11206 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11207 <= HOST_BITS_PER_WIDE_INT)
11208 && (nonzero_bits (SUBREG_REG (op0),
11209 GET_MODE (SUBREG_REG (op0)))
11210 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11212 tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)), op1);
11214 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11215 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11216 op0 = SUBREG_REG (op0), op1 = tem;
11220 /* We now do the opposite procedure: Some machines don't have compare
11221 insns in all modes. If OP0's mode is an integer mode smaller than a
11222 word and we can't do a compare in that mode, see if there is a larger
11223 mode for which we can do the compare. There are a number of cases in
11224 which we can use the wider mode. */
11226 mode = GET_MODE (op0);
11227 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11228 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11229 && ! have_insn_for (COMPARE, mode))
11230 for (tmode = GET_MODE_WIDER_MODE (mode);
11232 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11233 tmode = GET_MODE_WIDER_MODE (tmode))
11234 if (have_insn_for (COMPARE, tmode))
11238 /* If the only nonzero bits in OP0 and OP1 are those in the
11239 narrower mode and this is an equality or unsigned comparison,
11240 we can use the wider mode. Similarly for sign-extended
11241 values, in which case it is true for all comparisons. */
11242 zero_extended = ((code == EQ || code == NE
11243 || code == GEU || code == GTU
11244 || code == LEU || code == LTU)
11245 && (nonzero_bits (op0, tmode)
11246 & ~GET_MODE_MASK (mode)) == 0
11247 && ((GET_CODE (op1) == CONST_INT
11248 || (nonzero_bits (op1, tmode)
11249 & ~GET_MODE_MASK (mode)) == 0)));
11252 || ((num_sign_bit_copies (op0, tmode)
11253 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11254 - GET_MODE_BITSIZE (mode)))
11255 && (num_sign_bit_copies (op1, tmode)
11256 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11257 - GET_MODE_BITSIZE (mode)))))
11259 /* If OP0 is an AND and we don't have an AND in MODE either,
11260 make a new AND in the proper mode. */
11261 if (GET_CODE (op0) == AND
11262 && !have_insn_for (AND, mode))
11263 op0 = gen_binary (AND, tmode,
11264 gen_lowpart_for_combine (tmode,
11266 gen_lowpart_for_combine (tmode,
11269 op0 = gen_lowpart_for_combine (tmode, op0);
11270 if (zero_extended && GET_CODE (op1) == CONST_INT)
11271 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11272 op1 = gen_lowpart_for_combine (tmode, op1);
11276 /* If this is a test for negative, we can make an explicit
11277 test of the sign bit. */
11279 if (op1 == const0_rtx && (code == LT || code == GE)
11280 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11282 op0 = gen_binary (AND, tmode,
11283 gen_lowpart_for_combine (tmode, op0),
11284 GEN_INT ((HOST_WIDE_INT) 1
11285 << (GET_MODE_BITSIZE (mode) - 1)));
11286 code = (code == LT) ? NE : EQ;
11291 #ifdef CANONICALIZE_COMPARISON
11292 /* If this machine only supports a subset of valid comparisons, see if we
11293 can convert an unsupported one into a supported one. */
11294 CANONICALIZE_COMPARISON (code, op0, op1);
11303 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11304 searching backward. */
11305 static enum rtx_code
11306 combine_reversed_comparison_code (rtx exp)
11308 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11311 if (code1 != UNKNOWN
11312 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11314 /* Otherwise try and find where the condition codes were last set and
11316 x = get_last_value (XEXP (exp, 0));
11317 if (!x || GET_CODE (x) != COMPARE)
11319 return reversed_comparison_code_parts (GET_CODE (exp),
11320 XEXP (x, 0), XEXP (x, 1), NULL);
11323 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11324 Return NULL_RTX in case we fail to do the reversal. */
11326 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
11328 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11329 if (reversed_code == UNKNOWN)
11332 return gen_binary (reversed_code, mode, op0, op1);
11335 /* Utility function for following routine. Called when X is part of a value
11336 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11337 for each register mentioned. Similar to mention_regs in cse.c */
11340 update_table_tick (rtx x)
11342 enum rtx_code code = GET_CODE (x);
11343 const char *fmt = GET_RTX_FORMAT (code);
11348 unsigned int regno = REGNO (x);
11349 unsigned int endregno
11350 = regno + (regno < FIRST_PSEUDO_REGISTER
11351 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11354 for (r = regno; r < endregno; r++)
11355 reg_last_set_table_tick[r] = label_tick;
11360 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11361 /* Note that we can't have an "E" in values stored; see
11362 get_last_value_validate. */
11365 /* Check for identical subexpressions. If x contains
11366 identical subexpression we only have to traverse one of
11369 && (GET_RTX_CLASS (code) == '2'
11370 || GET_RTX_CLASS (code) == 'c'))
11372 /* Note that at this point x1 has already been
11374 rtx x0 = XEXP (x, 0);
11375 rtx x1 = XEXP (x, 1);
11377 /* If x0 and x1 are identical then there is no need to
11382 /* If x0 is identical to a subexpression of x1 then while
11383 processing x1, x0 has already been processed. Thus we
11384 are done with x. */
11385 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11386 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11387 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11390 /* If x1 is identical to a subexpression of x0 then we
11391 still have to process the rest of x0. */
11392 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11393 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11394 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11396 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11401 update_table_tick (XEXP (x, i));
11405 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11406 are saying that the register is clobbered and we no longer know its
11407 value. If INSN is zero, don't update reg_last_set; this is only permitted
11408 with VALUE also zero and is used to invalidate the register. */
11411 record_value_for_reg (rtx reg, rtx insn, rtx value)
11413 unsigned int regno = REGNO (reg);
11414 unsigned int endregno
11415 = regno + (regno < FIRST_PSEUDO_REGISTER
11416 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11419 /* If VALUE contains REG and we have a previous value for REG, substitute
11420 the previous value. */
11421 if (value && insn && reg_overlap_mentioned_p (reg, value))
11425 /* Set things up so get_last_value is allowed to see anything set up to
11427 subst_low_cuid = INSN_CUID (insn);
11428 tem = get_last_value (reg);
11430 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11431 it isn't going to be useful and will take a lot of time to process,
11432 so just use the CLOBBER. */
11436 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11437 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11438 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11439 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11440 tem = XEXP (tem, 0);
11442 value = replace_rtx (copy_rtx (value), reg, tem);
11446 /* For each register modified, show we don't know its value, that
11447 we don't know about its bitwise content, that its value has been
11448 updated, and that we don't know the location of the death of the
11450 for (i = regno; i < endregno; i++)
11453 reg_last_set[i] = insn;
11455 reg_last_set_value[i] = 0;
11456 reg_last_set_mode[i] = 0;
11457 reg_last_set_nonzero_bits[i] = 0;
11458 reg_last_set_sign_bit_copies[i] = 0;
11459 reg_last_death[i] = 0;
11462 /* Mark registers that are being referenced in this value. */
11464 update_table_tick (value);
11466 /* Now update the status of each register being set.
11467 If someone is using this register in this block, set this register
11468 to invalid since we will get confused between the two lives in this
11469 basic block. This makes using this register always invalid. In cse, we
11470 scan the table to invalidate all entries using this register, but this
11471 is too much work for us. */
11473 for (i = regno; i < endregno; i++)
11475 reg_last_set_label[i] = label_tick;
11476 if (value && reg_last_set_table_tick[i] == label_tick)
11477 reg_last_set_invalid[i] = 1;
11479 reg_last_set_invalid[i] = 0;
11482 /* The value being assigned might refer to X (like in "x++;"). In that
11483 case, we must replace it with (clobber (const_int 0)) to prevent
11485 if (value && ! get_last_value_validate (&value, insn,
11486 reg_last_set_label[regno], 0))
11488 value = copy_rtx (value);
11489 if (! get_last_value_validate (&value, insn,
11490 reg_last_set_label[regno], 1))
11494 /* For the main register being modified, update the value, the mode, the
11495 nonzero bits, and the number of sign bit copies. */
11497 reg_last_set_value[regno] = value;
11501 enum machine_mode mode = GET_MODE (reg);
11502 subst_low_cuid = INSN_CUID (insn);
11503 reg_last_set_mode[regno] = mode;
11504 if (GET_MODE_CLASS (mode) == MODE_INT
11505 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11506 mode = nonzero_bits_mode;
11507 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, mode);
11508 reg_last_set_sign_bit_copies[regno]
11509 = num_sign_bit_copies (value, GET_MODE (reg));
11513 /* Called via note_stores from record_dead_and_set_regs to handle one
11514 SET or CLOBBER in an insn. DATA is the instruction in which the
11515 set is occurring. */
11518 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11520 rtx record_dead_insn = (rtx) data;
11522 if (GET_CODE (dest) == SUBREG)
11523 dest = SUBREG_REG (dest);
11525 if (GET_CODE (dest) == REG)
11527 /* If we are setting the whole register, we know its value. Otherwise
11528 show that we don't know the value. We can handle SUBREG in
11530 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11531 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11532 else if (GET_CODE (setter) == SET
11533 && GET_CODE (SET_DEST (setter)) == SUBREG
11534 && SUBREG_REG (SET_DEST (setter)) == dest
11535 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11536 && subreg_lowpart_p (SET_DEST (setter)))
11537 record_value_for_reg (dest, record_dead_insn,
11538 gen_lowpart_for_combine (GET_MODE (dest),
11539 SET_SRC (setter)));
11541 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11543 else if (GET_CODE (dest) == MEM
11544 /* Ignore pushes, they clobber nothing. */
11545 && ! push_operand (dest, GET_MODE (dest)))
11546 mem_last_set = INSN_CUID (record_dead_insn);
11549 /* Update the records of when each REG was most recently set or killed
11550 for the things done by INSN. This is the last thing done in processing
11551 INSN in the combiner loop.
11553 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11554 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11555 and also the similar information mem_last_set (which insn most recently
11556 modified memory) and last_call_cuid (which insn was the most recent
11557 subroutine call). */
11560 record_dead_and_set_regs (rtx insn)
11565 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11567 if (REG_NOTE_KIND (link) == REG_DEAD
11568 && GET_CODE (XEXP (link, 0)) == REG)
11570 unsigned int regno = REGNO (XEXP (link, 0));
11571 unsigned int endregno
11572 = regno + (regno < FIRST_PSEUDO_REGISTER
11573 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11576 for (i = regno; i < endregno; i++)
11577 reg_last_death[i] = insn;
11579 else if (REG_NOTE_KIND (link) == REG_INC)
11580 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11583 if (GET_CODE (insn) == CALL_INSN)
11585 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11586 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11588 reg_last_set_value[i] = 0;
11589 reg_last_set_mode[i] = 0;
11590 reg_last_set_nonzero_bits[i] = 0;
11591 reg_last_set_sign_bit_copies[i] = 0;
11592 reg_last_death[i] = 0;
11595 last_call_cuid = mem_last_set = INSN_CUID (insn);
11597 /* Don't bother recording what this insn does. It might set the
11598 return value register, but we can't combine into a call
11599 pattern anyway, so there's no point trying (and it may cause
11600 a crash, if e.g. we wind up asking for last_set_value of a
11601 SUBREG of the return value register). */
11605 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11608 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11609 register present in the SUBREG, so for each such SUBREG go back and
11610 adjust nonzero and sign bit information of the registers that are
11611 known to have some zero/sign bits set.
11613 This is needed because when combine blows the SUBREGs away, the
11614 information on zero/sign bits is lost and further combines can be
11615 missed because of that. */
11618 record_promoted_value (rtx insn, rtx subreg)
11621 unsigned int regno = REGNO (SUBREG_REG (subreg));
11622 enum machine_mode mode = GET_MODE (subreg);
11624 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11627 for (links = LOG_LINKS (insn); links;)
11629 insn = XEXP (links, 0);
11630 set = single_set (insn);
11632 if (! set || GET_CODE (SET_DEST (set)) != REG
11633 || REGNO (SET_DEST (set)) != regno
11634 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11636 links = XEXP (links, 1);
11640 if (reg_last_set[regno] == insn)
11642 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11643 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11646 if (GET_CODE (SET_SRC (set)) == REG)
11648 regno = REGNO (SET_SRC (set));
11649 links = LOG_LINKS (insn);
11656 /* Scan X for promoted SUBREGs. For each one found,
11657 note what it implies to the registers used in it. */
11660 check_promoted_subreg (rtx insn, rtx x)
11662 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11663 && GET_CODE (SUBREG_REG (x)) == REG)
11664 record_promoted_value (insn, x);
11667 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11670 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11674 check_promoted_subreg (insn, XEXP (x, i));
11678 if (XVEC (x, i) != 0)
11679 for (j = 0; j < XVECLEN (x, i); j++)
11680 check_promoted_subreg (insn, XVECEXP (x, i, j));
11686 /* Utility routine for the following function. Verify that all the registers
11687 mentioned in *LOC are valid when *LOC was part of a value set when
11688 label_tick == TICK. Return 0 if some are not.
11690 If REPLACE is nonzero, replace the invalid reference with
11691 (clobber (const_int 0)) and return 1. This replacement is useful because
11692 we often can get useful information about the form of a value (e.g., if
11693 it was produced by a shift that always produces -1 or 0) even though
11694 we don't know exactly what registers it was produced from. */
11697 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11700 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11701 int len = GET_RTX_LENGTH (GET_CODE (x));
11704 if (GET_CODE (x) == REG)
11706 unsigned int regno = REGNO (x);
11707 unsigned int endregno
11708 = regno + (regno < FIRST_PSEUDO_REGISTER
11709 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11712 for (j = regno; j < endregno; j++)
11713 if (reg_last_set_invalid[j]
11714 /* If this is a pseudo-register that was only set once and not
11715 live at the beginning of the function, it is always valid. */
11716 || (! (regno >= FIRST_PSEUDO_REGISTER
11717 && REG_N_SETS (regno) == 1
11718 && (! REGNO_REG_SET_P
11719 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11720 && reg_last_set_label[j] > tick))
11723 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11729 /* If this is a memory reference, make sure that there were
11730 no stores after it that might have clobbered the value. We don't
11731 have alias info, so we assume any store invalidates it. */
11732 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11733 && INSN_CUID (insn) <= mem_last_set)
11736 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11740 for (i = 0; i < len; i++)
11744 /* Check for identical subexpressions. If x contains
11745 identical subexpression we only have to traverse one of
11748 && (GET_RTX_CLASS (GET_CODE (x)) == '2'
11749 || GET_RTX_CLASS (GET_CODE (x)) == 'c'))
11751 /* Note that at this point x0 has already been checked
11752 and found valid. */
11753 rtx x0 = XEXP (x, 0);
11754 rtx x1 = XEXP (x, 1);
11756 /* If x0 and x1 are identical then x is also valid. */
11760 /* If x1 is identical to a subexpression of x0 then
11761 while checking x0, x1 has already been checked. Thus
11762 it is valid and so as x. */
11763 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11764 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11765 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11768 /* If x0 is identical to a subexpression of x1 then x is
11769 valid iff the rest of x1 is valid. */
11770 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11771 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11772 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11774 get_last_value_validate (&XEXP (x1,
11775 x0 == XEXP (x1, 0) ? 1 : 0),
11776 insn, tick, replace);
11779 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11783 /* Don't bother with these. They shouldn't occur anyway. */
11784 else if (fmt[i] == 'E')
11788 /* If we haven't found a reason for it to be invalid, it is valid. */
11792 /* Get the last value assigned to X, if known. Some registers
11793 in the value may be replaced with (clobber (const_int 0)) if their value
11794 is known longer known reliably. */
11797 get_last_value (rtx x)
11799 unsigned int regno;
11802 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11803 then convert it to the desired mode. If this is a paradoxical SUBREG,
11804 we cannot predict what values the "extra" bits might have. */
11805 if (GET_CODE (x) == SUBREG
11806 && subreg_lowpart_p (x)
11807 && (GET_MODE_SIZE (GET_MODE (x))
11808 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11809 && (value = get_last_value (SUBREG_REG (x))) != 0)
11810 return gen_lowpart_for_combine (GET_MODE (x), value);
11812 if (GET_CODE (x) != REG)
11816 value = reg_last_set_value[regno];
11818 /* If we don't have a value, or if it isn't for this basic block and
11819 it's either a hard register, set more than once, or it's a live
11820 at the beginning of the function, return 0.
11822 Because if it's not live at the beginning of the function then the reg
11823 is always set before being used (is never used without being set).
11824 And, if it's set only once, and it's always set before use, then all
11825 uses must have the same last value, even if it's not from this basic
11829 || (reg_last_set_label[regno] != label_tick
11830 && (regno < FIRST_PSEUDO_REGISTER
11831 || REG_N_SETS (regno) != 1
11832 || (REGNO_REG_SET_P
11833 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11836 /* If the value was set in a later insn than the ones we are processing,
11837 we can't use it even if the register was only set once. */
11838 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11841 /* If the value has all its registers valid, return it. */
11842 if (get_last_value_validate (&value, reg_last_set[regno],
11843 reg_last_set_label[regno], 0))
11846 /* Otherwise, make a copy and replace any invalid register with
11847 (clobber (const_int 0)). If that fails for some reason, return 0. */
11849 value = copy_rtx (value);
11850 if (get_last_value_validate (&value, reg_last_set[regno],
11851 reg_last_set_label[regno], 1))
11857 /* Return nonzero if expression X refers to a REG or to memory
11858 that is set in an instruction more recent than FROM_CUID. */
11861 use_crosses_set_p (rtx x, int from_cuid)
11865 enum rtx_code code = GET_CODE (x);
11869 unsigned int regno = REGNO (x);
11870 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11871 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11873 #ifdef PUSH_ROUNDING
11874 /* Don't allow uses of the stack pointer to be moved,
11875 because we don't know whether the move crosses a push insn. */
11876 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11879 for (; regno < endreg; regno++)
11880 if (reg_last_set[regno]
11881 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11886 if (code == MEM && mem_last_set > from_cuid)
11889 fmt = GET_RTX_FORMAT (code);
11891 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11896 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11897 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11900 else if (fmt[i] == 'e'
11901 && use_crosses_set_p (XEXP (x, i), from_cuid))
11907 /* Define three variables used for communication between the following
11910 static unsigned int reg_dead_regno, reg_dead_endregno;
11911 static int reg_dead_flag;
11913 /* Function called via note_stores from reg_dead_at_p.
11915 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11916 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11919 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11921 unsigned int regno, endregno;
11923 if (GET_CODE (dest) != REG)
11926 regno = REGNO (dest);
11927 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11928 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11930 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11931 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11934 /* Return nonzero if REG is known to be dead at INSN.
11936 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11937 referencing REG, it is dead. If we hit a SET referencing REG, it is
11938 live. Otherwise, see if it is live or dead at the start of the basic
11939 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11940 must be assumed to be always live. */
11943 reg_dead_at_p (rtx reg, rtx insn)
11948 /* Set variables for reg_dead_at_p_1. */
11949 reg_dead_regno = REGNO (reg);
11950 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11951 ? HARD_REGNO_NREGS (reg_dead_regno,
11957 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11958 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11960 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11961 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11965 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11966 beginning of function. */
11967 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11968 insn = prev_nonnote_insn (insn))
11970 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11972 return reg_dead_flag == 1 ? 1 : 0;
11974 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11978 /* Get the basic block that we were in. */
11980 block = ENTRY_BLOCK_PTR->next_bb;
11983 FOR_EACH_BB (block)
11984 if (insn == BB_HEAD (block))
11987 if (block == EXIT_BLOCK_PTR)
11991 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11992 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11998 /* Note hard registers in X that are used. This code is similar to
11999 that in flow.c, but much simpler since we don't care about pseudos. */
12002 mark_used_regs_combine (rtx x)
12004 RTX_CODE code = GET_CODE (x);
12005 unsigned int regno;
12018 case ADDR_DIFF_VEC:
12021 /* CC0 must die in the insn after it is set, so we don't need to take
12022 special note of it here. */
12028 /* If we are clobbering a MEM, mark any hard registers inside the
12029 address as used. */
12030 if (GET_CODE (XEXP (x, 0)) == MEM)
12031 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12036 /* A hard reg in a wide mode may really be multiple registers.
12037 If so, mark all of them just like the first. */
12038 if (regno < FIRST_PSEUDO_REGISTER)
12040 unsigned int endregno, r;
12042 /* None of this applies to the stack, frame or arg pointers. */
12043 if (regno == STACK_POINTER_REGNUM
12044 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12045 || regno == HARD_FRAME_POINTER_REGNUM
12047 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12048 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12050 || regno == FRAME_POINTER_REGNUM)
12053 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12054 for (r = regno; r < endregno; r++)
12055 SET_HARD_REG_BIT (newpat_used_regs, r);
12061 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12063 rtx testreg = SET_DEST (x);
12065 while (GET_CODE (testreg) == SUBREG
12066 || GET_CODE (testreg) == ZERO_EXTRACT
12067 || GET_CODE (testreg) == SIGN_EXTRACT
12068 || GET_CODE (testreg) == STRICT_LOW_PART)
12069 testreg = XEXP (testreg, 0);
12071 if (GET_CODE (testreg) == MEM)
12072 mark_used_regs_combine (XEXP (testreg, 0));
12074 mark_used_regs_combine (SET_SRC (x));
12082 /* Recursively scan the operands of this expression. */
12085 const char *fmt = GET_RTX_FORMAT (code);
12087 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12090 mark_used_regs_combine (XEXP (x, i));
12091 else if (fmt[i] == 'E')
12095 for (j = 0; j < XVECLEN (x, i); j++)
12096 mark_used_regs_combine (XVECEXP (x, i, j));
12102 /* Remove register number REGNO from the dead registers list of INSN.
12104 Return the note used to record the death, if there was one. */
12107 remove_death (unsigned int regno, rtx insn)
12109 rtx note = find_regno_note (insn, REG_DEAD, regno);
12113 REG_N_DEATHS (regno)--;
12114 remove_note (insn, note);
12120 /* For each register (hardware or pseudo) used within expression X, if its
12121 death is in an instruction with cuid between FROM_CUID (inclusive) and
12122 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12123 list headed by PNOTES.
12125 That said, don't move registers killed by maybe_kill_insn.
12127 This is done when X is being merged by combination into TO_INSN. These
12128 notes will then be distributed as needed. */
12131 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
12136 enum rtx_code code = GET_CODE (x);
12140 unsigned int regno = REGNO (x);
12141 rtx where_dead = reg_last_death[regno];
12142 rtx before_dead, after_dead;
12144 /* Don't move the register if it gets killed in between from and to. */
12145 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12146 && ! reg_referenced_p (x, maybe_kill_insn))
12149 /* WHERE_DEAD could be a USE insn made by combine, so first we
12150 make sure that we have insns with valid INSN_CUID values. */
12151 before_dead = where_dead;
12152 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
12153 before_dead = PREV_INSN (before_dead);
12155 after_dead = where_dead;
12156 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
12157 after_dead = NEXT_INSN (after_dead);
12159 if (before_dead && after_dead
12160 && INSN_CUID (before_dead) >= from_cuid
12161 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
12162 || (where_dead != after_dead
12163 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
12165 rtx note = remove_death (regno, where_dead);
12167 /* It is possible for the call above to return 0. This can occur
12168 when reg_last_death points to I2 or I1 that we combined with.
12169 In that case make a new note.
12171 We must also check for the case where X is a hard register
12172 and NOTE is a death note for a range of hard registers
12173 including X. In that case, we must put REG_DEAD notes for
12174 the remaining registers in place of NOTE. */
12176 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12177 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12178 > GET_MODE_SIZE (GET_MODE (x))))
12180 unsigned int deadregno = REGNO (XEXP (note, 0));
12181 unsigned int deadend
12182 = (deadregno + HARD_REGNO_NREGS (deadregno,
12183 GET_MODE (XEXP (note, 0))));
12184 unsigned int ourend
12185 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12188 for (i = deadregno; i < deadend; i++)
12189 if (i < regno || i >= ourend)
12190 REG_NOTES (where_dead)
12191 = gen_rtx_EXPR_LIST (REG_DEAD,
12193 REG_NOTES (where_dead));
12196 /* If we didn't find any note, or if we found a REG_DEAD note that
12197 covers only part of the given reg, and we have a multi-reg hard
12198 register, then to be safe we must check for REG_DEAD notes
12199 for each register other than the first. They could have
12200 their own REG_DEAD notes lying around. */
12201 else if ((note == 0
12203 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12204 < GET_MODE_SIZE (GET_MODE (x)))))
12205 && regno < FIRST_PSEUDO_REGISTER
12206 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
12208 unsigned int ourend
12209 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12210 unsigned int i, offset;
12214 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12218 for (i = regno + offset; i < ourend; i++)
12219 move_deaths (regno_reg_rtx[i],
12220 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12223 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12225 XEXP (note, 1) = *pnotes;
12229 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12231 REG_N_DEATHS (regno)++;
12237 else if (GET_CODE (x) == SET)
12239 rtx dest = SET_DEST (x);
12241 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12243 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12244 that accesses one word of a multi-word item, some
12245 piece of everything register in the expression is used by
12246 this insn, so remove any old death. */
12247 /* ??? So why do we test for equality of the sizes? */
12249 if (GET_CODE (dest) == ZERO_EXTRACT
12250 || GET_CODE (dest) == STRICT_LOW_PART
12251 || (GET_CODE (dest) == SUBREG
12252 && (((GET_MODE_SIZE (GET_MODE (dest))
12253 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12254 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12255 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12257 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12261 /* If this is some other SUBREG, we know it replaces the entire
12262 value, so use that as the destination. */
12263 if (GET_CODE (dest) == SUBREG)
12264 dest = SUBREG_REG (dest);
12266 /* If this is a MEM, adjust deaths of anything used in the address.
12267 For a REG (the only other possibility), the entire value is
12268 being replaced so the old value is not used in this insn. */
12270 if (GET_CODE (dest) == MEM)
12271 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12276 else if (GET_CODE (x) == CLOBBER)
12279 len = GET_RTX_LENGTH (code);
12280 fmt = GET_RTX_FORMAT (code);
12282 for (i = 0; i < len; i++)
12287 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12288 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12291 else if (fmt[i] == 'e')
12292 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12296 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12297 pattern of an insn. X must be a REG. */
12300 reg_bitfield_target_p (rtx x, rtx body)
12304 if (GET_CODE (body) == SET)
12306 rtx dest = SET_DEST (body);
12308 unsigned int regno, tregno, endregno, endtregno;
12310 if (GET_CODE (dest) == ZERO_EXTRACT)
12311 target = XEXP (dest, 0);
12312 else if (GET_CODE (dest) == STRICT_LOW_PART)
12313 target = SUBREG_REG (XEXP (dest, 0));
12317 if (GET_CODE (target) == SUBREG)
12318 target = SUBREG_REG (target);
12320 if (GET_CODE (target) != REG)
12323 tregno = REGNO (target), regno = REGNO (x);
12324 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12325 return target == x;
12327 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12328 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12330 return endregno > tregno && regno < endtregno;
12333 else if (GET_CODE (body) == PARALLEL)
12334 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12335 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12341 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12342 as appropriate. I3 and I2 are the insns resulting from the combination
12343 insns including FROM (I2 may be zero).
12345 Each note in the list is either ignored or placed on some insns, depending
12346 on the type of note. */
12349 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
12351 rtx note, next_note;
12354 for (note = notes; note; note = next_note)
12356 rtx place = 0, place2 = 0;
12358 /* If this NOTE references a pseudo register, ensure it references
12359 the latest copy of that register. */
12360 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12361 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12362 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12364 next_note = XEXP (note, 1);
12365 switch (REG_NOTE_KIND (note))
12369 /* Doesn't matter much where we put this, as long as it's somewhere.
12370 It is preferable to keep these notes on branches, which is most
12371 likely to be i3. */
12375 case REG_VALUE_PROFILE:
12376 /* Just get rid of this note, as it is unused later anyway. */
12379 case REG_VTABLE_REF:
12380 /* ??? Should remain with *a particular* memory load. Given the
12381 nature of vtable data, the last insn seems relatively safe. */
12385 case REG_NON_LOCAL_GOTO:
12386 if (GET_CODE (i3) == JUMP_INSN)
12388 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12394 case REG_EH_REGION:
12395 /* These notes must remain with the call or trapping instruction. */
12396 if (GET_CODE (i3) == CALL_INSN)
12398 else if (i2 && GET_CODE (i2) == CALL_INSN)
12400 else if (flag_non_call_exceptions)
12402 if (may_trap_p (i3))
12404 else if (i2 && may_trap_p (i2))
12406 /* ??? Otherwise assume we've combined things such that we
12407 can now prove that the instructions can't trap. Drop the
12408 note in this case. */
12414 case REG_ALWAYS_RETURN:
12417 /* These notes must remain with the call. It should not be
12418 possible for both I2 and I3 to be a call. */
12419 if (GET_CODE (i3) == CALL_INSN)
12421 else if (i2 && GET_CODE (i2) == CALL_INSN)
12428 /* Any clobbers for i3 may still exist, and so we must process
12429 REG_UNUSED notes from that insn.
12431 Any clobbers from i2 or i1 can only exist if they were added by
12432 recog_for_combine. In that case, recog_for_combine created the
12433 necessary REG_UNUSED notes. Trying to keep any original
12434 REG_UNUSED notes from these insns can cause incorrect output
12435 if it is for the same register as the original i3 dest.
12436 In that case, we will notice that the register is set in i3,
12437 and then add a REG_UNUSED note for the destination of i3, which
12438 is wrong. However, it is possible to have REG_UNUSED notes from
12439 i2 or i1 for register which were both used and clobbered, so
12440 we keep notes from i2 or i1 if they will turn into REG_DEAD
12443 /* If this register is set or clobbered in I3, put the note there
12444 unless there is one already. */
12445 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12447 if (from_insn != i3)
12450 if (! (GET_CODE (XEXP (note, 0)) == REG
12451 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12452 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12455 /* Otherwise, if this register is used by I3, then this register
12456 now dies here, so we must put a REG_DEAD note here unless there
12458 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12459 && ! (GET_CODE (XEXP (note, 0)) == REG
12460 ? find_regno_note (i3, REG_DEAD,
12461 REGNO (XEXP (note, 0)))
12462 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12464 PUT_REG_NOTE_KIND (note, REG_DEAD);
12472 /* These notes say something about results of an insn. We can
12473 only support them if they used to be on I3 in which case they
12474 remain on I3. Otherwise they are ignored.
12476 If the note refers to an expression that is not a constant, we
12477 must also ignore the note since we cannot tell whether the
12478 equivalence is still true. It might be possible to do
12479 slightly better than this (we only have a problem if I2DEST
12480 or I1DEST is present in the expression), but it doesn't
12481 seem worth the trouble. */
12483 if (from_insn == i3
12484 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12489 case REG_NO_CONFLICT:
12490 /* These notes say something about how a register is used. They must
12491 be present on any use of the register in I2 or I3. */
12492 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12495 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12505 /* This can show up in several ways -- either directly in the
12506 pattern, or hidden off in the constant pool with (or without?)
12507 a REG_EQUAL note. */
12508 /* ??? Ignore the without-reg_equal-note problem for now. */
12509 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12510 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12511 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12512 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12516 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12517 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12518 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12519 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12527 /* Don't attach REG_LABEL note to a JUMP_INSN which has
12528 JUMP_LABEL already. Instead, decrement LABEL_NUSES. */
12529 if (place && GET_CODE (place) == JUMP_INSN && JUMP_LABEL (place))
12531 if (JUMP_LABEL (place) != XEXP (note, 0))
12533 if (GET_CODE (JUMP_LABEL (place)) == CODE_LABEL)
12534 LABEL_NUSES (JUMP_LABEL (place))--;
12537 if (place2 && GET_CODE (place2) == JUMP_INSN && JUMP_LABEL (place2))
12539 if (JUMP_LABEL (place2) != XEXP (note, 0))
12541 if (GET_CODE (JUMP_LABEL (place2)) == CODE_LABEL)
12542 LABEL_NUSES (JUMP_LABEL (place2))--;
12548 /* This note says something about the value of a register prior
12549 to the execution of an insn. It is too much trouble to see
12550 if the note is still correct in all situations. It is better
12551 to simply delete it. */
12555 /* If the insn previously containing this note still exists,
12556 put it back where it was. Otherwise move it to the previous
12557 insn. Adjust the corresponding REG_LIBCALL note. */
12558 if (GET_CODE (from_insn) != NOTE)
12562 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12563 place = prev_real_insn (from_insn);
12565 XEXP (tem, 0) = place;
12566 /* If we're deleting the last remaining instruction of a
12567 libcall sequence, don't add the notes. */
12568 else if (XEXP (note, 0) == from_insn)
12574 /* This is handled similarly to REG_RETVAL. */
12575 if (GET_CODE (from_insn) != NOTE)
12579 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12580 place = next_real_insn (from_insn);
12582 XEXP (tem, 0) = place;
12583 /* If we're deleting the last remaining instruction of a
12584 libcall sequence, don't add the notes. */
12585 else if (XEXP (note, 0) == from_insn)
12591 /* If the register is used as an input in I3, it dies there.
12592 Similarly for I2, if it is nonzero and adjacent to I3.
12594 If the register is not used as an input in either I3 or I2
12595 and it is not one of the registers we were supposed to eliminate,
12596 there are two possibilities. We might have a non-adjacent I2
12597 or we might have somehow eliminated an additional register
12598 from a computation. For example, we might have had A & B where
12599 we discover that B will always be zero. In this case we will
12600 eliminate the reference to A.
12602 In both cases, we must search to see if we can find a previous
12603 use of A and put the death note there. */
12606 && GET_CODE (from_insn) == CALL_INSN
12607 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12609 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12611 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12612 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12617 basic_block bb = this_basic_block;
12619 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12621 if (! INSN_P (tem))
12623 if (tem == BB_HEAD (bb))
12628 /* If the register is being set at TEM, see if that is all
12629 TEM is doing. If so, delete TEM. Otherwise, make this
12630 into a REG_UNUSED note instead. */
12631 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12633 rtx set = single_set (tem);
12634 rtx inner_dest = 0;
12636 rtx cc0_setter = NULL_RTX;
12640 for (inner_dest = SET_DEST (set);
12641 (GET_CODE (inner_dest) == STRICT_LOW_PART
12642 || GET_CODE (inner_dest) == SUBREG
12643 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12644 inner_dest = XEXP (inner_dest, 0))
12647 /* Verify that it was the set, and not a clobber that
12648 modified the register.
12650 CC0 targets must be careful to maintain setter/user
12651 pairs. If we cannot delete the setter due to side
12652 effects, mark the user with an UNUSED note instead
12655 if (set != 0 && ! side_effects_p (SET_SRC (set))
12656 && rtx_equal_p (XEXP (note, 0), inner_dest)
12658 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12659 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12660 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12664 /* Move the notes and links of TEM elsewhere.
12665 This might delete other dead insns recursively.
12666 First set the pattern to something that won't use
12668 rtx old_notes = REG_NOTES (tem);
12670 PATTERN (tem) = pc_rtx;
12671 REG_NOTES (tem) = NULL;
12673 distribute_notes (old_notes, tem, tem, NULL_RTX);
12674 distribute_links (LOG_LINKS (tem));
12676 PUT_CODE (tem, NOTE);
12677 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12678 NOTE_SOURCE_FILE (tem) = 0;
12681 /* Delete the setter too. */
12684 PATTERN (cc0_setter) = pc_rtx;
12685 old_notes = REG_NOTES (cc0_setter);
12686 REG_NOTES (cc0_setter) = NULL;
12688 distribute_notes (old_notes, cc0_setter,
12689 cc0_setter, NULL_RTX);
12690 distribute_links (LOG_LINKS (cc0_setter));
12692 PUT_CODE (cc0_setter, NOTE);
12693 NOTE_LINE_NUMBER (cc0_setter)
12694 = NOTE_INSN_DELETED;
12695 NOTE_SOURCE_FILE (cc0_setter) = 0;
12699 /* If the register is both set and used here, put the
12700 REG_DEAD note here, but place a REG_UNUSED note
12701 here too unless there already is one. */
12702 else if (reg_referenced_p (XEXP (note, 0),
12707 if (! find_regno_note (tem, REG_UNUSED,
12708 REGNO (XEXP (note, 0))))
12710 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12715 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12717 /* If there isn't already a REG_UNUSED note, put one
12719 if (! find_regno_note (tem, REG_UNUSED,
12720 REGNO (XEXP (note, 0))))
12725 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12726 || (GET_CODE (tem) == CALL_INSN
12727 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12731 /* If we are doing a 3->2 combination, and we have a
12732 register which formerly died in i3 and was not used
12733 by i2, which now no longer dies in i3 and is used in
12734 i2 but does not die in i2, and place is between i2
12735 and i3, then we may need to move a link from place to
12737 if (i2 && INSN_UID (place) <= max_uid_cuid
12738 && INSN_CUID (place) > INSN_CUID (i2)
12740 && INSN_CUID (from_insn) > INSN_CUID (i2)
12741 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12743 rtx links = LOG_LINKS (place);
12744 LOG_LINKS (place) = 0;
12745 distribute_links (links);
12750 if (tem == BB_HEAD (bb))
12754 /* We haven't found an insn for the death note and it
12755 is still a REG_DEAD note, but we have hit the beginning
12756 of the block. If the existing life info says the reg
12757 was dead, there's nothing left to do. Otherwise, we'll
12758 need to do a global life update after combine. */
12759 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12760 && REGNO_REG_SET_P (bb->global_live_at_start,
12761 REGNO (XEXP (note, 0))))
12762 SET_BIT (refresh_blocks, this_basic_block->index);
12765 /* If the register is set or already dead at PLACE, we needn't do
12766 anything with this note if it is still a REG_DEAD note.
12767 We can here if it is set at all, not if is it totally replace,
12768 which is what `dead_or_set_p' checks, so also check for it being
12771 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12773 unsigned int regno = REGNO (XEXP (note, 0));
12775 /* Similarly, if the instruction on which we want to place
12776 the note is a noop, we'll need do a global live update
12777 after we remove them in delete_noop_moves. */
12778 if (noop_move_p (place))
12779 SET_BIT (refresh_blocks, this_basic_block->index);
12781 if (dead_or_set_p (place, XEXP (note, 0))
12782 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12784 /* Unless the register previously died in PLACE, clear
12785 reg_last_death. [I no longer understand why this is
12787 if (reg_last_death[regno] != place)
12788 reg_last_death[regno] = 0;
12792 reg_last_death[regno] = place;
12794 /* If this is a death note for a hard reg that is occupying
12795 multiple registers, ensure that we are still using all
12796 parts of the object. If we find a piece of the object
12797 that is unused, we must arrange for an appropriate REG_DEAD
12798 note to be added for it. However, we can't just emit a USE
12799 and tag the note to it, since the register might actually
12800 be dead; so we recourse, and the recursive call then finds
12801 the previous insn that used this register. */
12803 if (place && regno < FIRST_PSEUDO_REGISTER
12804 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12806 unsigned int endregno
12807 = regno + HARD_REGNO_NREGS (regno,
12808 GET_MODE (XEXP (note, 0)));
12812 for (i = regno; i < endregno; i++)
12813 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12814 && ! find_regno_fusage (place, USE, i))
12815 || dead_or_set_regno_p (place, i))
12820 /* Put only REG_DEAD notes for pieces that are
12821 not already dead or set. */
12823 for (i = regno; i < endregno;
12824 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12826 rtx piece = regno_reg_rtx[i];
12827 basic_block bb = this_basic_block;
12829 if (! dead_or_set_p (place, piece)
12830 && ! reg_bitfield_target_p (piece,
12834 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12836 distribute_notes (new_note, place, place,
12839 else if (! refers_to_regno_p (i, i + 1,
12840 PATTERN (place), 0)
12841 && ! find_regno_fusage (place, USE, i))
12842 for (tem = PREV_INSN (place); ;
12843 tem = PREV_INSN (tem))
12845 if (! INSN_P (tem))
12847 if (tem == BB_HEAD (bb))
12849 SET_BIT (refresh_blocks,
12850 this_basic_block->index);
12855 if (dead_or_set_p (tem, piece)
12856 || reg_bitfield_target_p (piece,
12860 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12875 /* Any other notes should not be present at this point in the
12882 XEXP (note, 1) = REG_NOTES (place);
12883 REG_NOTES (place) = note;
12885 else if ((REG_NOTE_KIND (note) == REG_DEAD
12886 || REG_NOTE_KIND (note) == REG_UNUSED)
12887 && GET_CODE (XEXP (note, 0)) == REG)
12888 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12892 if ((REG_NOTE_KIND (note) == REG_DEAD
12893 || REG_NOTE_KIND (note) == REG_UNUSED)
12894 && GET_CODE (XEXP (note, 0)) == REG)
12895 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12897 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12898 REG_NOTE_KIND (note),
12900 REG_NOTES (place2));
12905 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12906 I3, I2, and I1 to new locations. This is also called to add a link
12907 pointing at I3 when I3's destination is changed. */
12910 distribute_links (rtx links)
12912 rtx link, next_link;
12914 for (link = links; link; link = next_link)
12920 next_link = XEXP (link, 1);
12922 /* If the insn that this link points to is a NOTE or isn't a single
12923 set, ignore it. In the latter case, it isn't clear what we
12924 can do other than ignore the link, since we can't tell which
12925 register it was for. Such links wouldn't be used by combine
12928 It is not possible for the destination of the target of the link to
12929 have been changed by combine. The only potential of this is if we
12930 replace I3, I2, and I1 by I3 and I2. But in that case the
12931 destination of I2 also remains unchanged. */
12933 if (GET_CODE (XEXP (link, 0)) == NOTE
12934 || (set = single_set (XEXP (link, 0))) == 0)
12937 reg = SET_DEST (set);
12938 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12939 || GET_CODE (reg) == SIGN_EXTRACT
12940 || GET_CODE (reg) == STRICT_LOW_PART)
12941 reg = XEXP (reg, 0);
12943 /* A LOG_LINK is defined as being placed on the first insn that uses
12944 a register and points to the insn that sets the register. Start
12945 searching at the next insn after the target of the link and stop
12946 when we reach a set of the register or the end of the basic block.
12948 Note that this correctly handles the link that used to point from
12949 I3 to I2. Also note that not much searching is typically done here
12950 since most links don't point very far away. */
12952 for (insn = NEXT_INSN (XEXP (link, 0));
12953 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12954 || BB_HEAD (this_basic_block->next_bb) != insn));
12955 insn = NEXT_INSN (insn))
12956 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12958 if (reg_referenced_p (reg, PATTERN (insn)))
12962 else if (GET_CODE (insn) == CALL_INSN
12963 && find_reg_fusage (insn, USE, reg))
12968 else if (INSN_P (insn) && reg_set_p (reg, insn))
12971 /* If we found a place to put the link, place it there unless there
12972 is already a link to the same insn as LINK at that point. */
12978 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12979 if (XEXP (link2, 0) == XEXP (link, 0))
12984 XEXP (link, 1) = LOG_LINKS (place);
12985 LOG_LINKS (place) = link;
12987 /* Set added_links_insn to the earliest insn we added a
12989 if (added_links_insn == 0
12990 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12991 added_links_insn = place;
12997 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
13000 insn_cuid (rtx insn)
13002 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
13003 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
13004 insn = NEXT_INSN (insn);
13006 if (INSN_UID (insn) > max_uid_cuid)
13009 return INSN_CUID (insn);
13013 dump_combine_stats (FILE *file)
13017 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13018 combine_attempts, combine_merges, combine_extras, combine_successes);
13022 dump_combine_total_stats (FILE *file)
13026 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13027 total_attempts, total_merges, total_extras, total_successes);