1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int max_uid_known;
305 /* The following array records the insn_rtx_cost for every insn
306 in the instruction stream. */
308 static int *uid_insn_cost;
310 /* The following array records the LOG_LINKS for every insn in the
311 instruction stream as an INSN_LIST rtx. */
313 static rtx *uid_log_links;
315 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
316 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
318 /* Incremented for each basic block. */
320 static int label_tick;
322 /* Reset to label_tick for each label. */
324 static int label_tick_ebb_start;
326 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
327 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
329 static enum machine_mode nonzero_bits_mode;
331 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
332 be safely used. It is zero while computing them and after combine has
333 completed. This former test prevents propagating values based on
334 previously set values, which can be incorrect if a variable is modified
337 static int nonzero_sign_valid;
340 /* Record one modification to rtl structure
341 to be undone by storing old_contents into *where. */
346 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
347 union { rtx r; int i; enum machine_mode m; } old_contents;
348 union { rtx *r; int *i; } where;
351 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
352 num_undo says how many are currently recorded.
354 other_insn is nonzero if we have modified some other insn in the process
355 of working on subst_insn. It must be verified too. */
364 static struct undobuf undobuf;
366 /* Number of times the pseudo being substituted for
367 was found and replaced. */
369 static int n_occurrences;
371 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
373 unsigned HOST_WIDE_INT,
374 unsigned HOST_WIDE_INT *);
375 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned int, unsigned int *);
378 static void do_SUBST (rtx *, rtx);
379 static void do_SUBST_INT (int *, int);
380 static void init_reg_last (void);
381 static void setup_incoming_promotions (rtx);
382 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
383 static int cant_combine_insn_p (rtx);
384 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
385 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
386 static int contains_muldiv (rtx);
387 static rtx try_combine (rtx, rtx, rtx, int *);
388 static void undo_all (void);
389 static void undo_commit (void);
390 static rtx *find_split_point (rtx *, rtx);
391 static rtx subst (rtx, rtx, rtx, int, int);
392 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
393 static rtx simplify_if_then_else (rtx);
394 static rtx simplify_set (rtx);
395 static rtx simplify_logical (rtx);
396 static rtx expand_compound_operation (rtx);
397 static rtx expand_field_assignment (rtx);
398 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
399 rtx, unsigned HOST_WIDE_INT, int, int, int);
400 static rtx extract_left_shift (rtx, int);
401 static rtx make_compound_operation (rtx, enum rtx_code);
402 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx canon_reg_for_combine (rtx, rtx);
405 static rtx force_to_mode (rtx, enum machine_mode,
406 unsigned HOST_WIDE_INT, int);
407 static rtx if_then_else_cond (rtx, rtx *, rtx *);
408 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
409 static int rtx_equal_for_field_assignment_p (rtx, rtx);
410 static rtx make_field_assignment (rtx);
411 static rtx apply_distributive_law (rtx);
412 static rtx distribute_and_simplify_rtx (rtx, int);
413 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
414 unsigned HOST_WIDE_INT);
415 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
416 unsigned HOST_WIDE_INT);
417 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
418 HOST_WIDE_INT, enum machine_mode, int *);
419 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
420 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
422 static int recog_for_combine (rtx *, rtx, rtx *);
423 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
424 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
425 static void update_table_tick (rtx);
426 static void record_value_for_reg (rtx, rtx, rtx);
427 static void check_conversions (rtx, rtx);
428 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
429 static void record_dead_and_set_regs (rtx);
430 static int get_last_value_validate (rtx *, rtx, int, int);
431 static rtx get_last_value (const_rtx);
432 static int use_crosses_set_p (rtx, int);
433 static void reg_dead_at_p_1 (rtx, rtx, void *);
434 static int reg_dead_at_p (rtx, rtx);
435 static void move_deaths (rtx, rtx, int, rtx, rtx *);
436 static int reg_bitfield_target_p (rtx, rtx);
437 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
438 static void distribute_links (rtx);
439 static void mark_used_regs_combine (rtx);
440 static void record_promoted_value (rtx, rtx);
441 static int unmentioned_reg_p_1 (rtx *, void *);
442 static bool unmentioned_reg_p (rtx, rtx);
443 static void record_truncated_value (rtx);
444 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
445 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
448 /* It is not safe to use ordinary gen_lowpart in combine.
449 See comments in gen_lowpart_for_combine. */
450 #undef RTL_HOOKS_GEN_LOWPART
451 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
453 /* Our implementation of gen_lowpart never emits a new pseudo. */
454 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
455 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
457 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
458 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
460 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
461 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
463 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
464 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
466 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
469 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
470 PATTERN can not be split. Otherwise, it returns an insn sequence.
471 This is a wrapper around split_insns which ensures that the
472 reg_stat vector is made larger if the splitter creates a new
476 combine_split_insns (rtx pattern, rtx insn)
481 ret = split_insns (pattern, insn);
482 nregs = max_reg_num ();
483 if (nregs > VEC_length (reg_stat_type, reg_stat))
484 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
488 /* This is used by find_single_use to locate an rtx in LOC that
489 contains exactly one use of DEST, which is typically either a REG
490 or CC0. It returns a pointer to the innermost rtx expression
491 containing DEST. Appearances of DEST that are being used to
492 totally replace it are not counted. */
495 find_single_use_1 (rtx dest, rtx *loc)
498 enum rtx_code code = GET_CODE (x);
516 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
517 of a REG that occupies all of the REG, the insn uses DEST if
518 it is mentioned in the destination or the source. Otherwise, we
519 need just check the source. */
520 if (GET_CODE (SET_DEST (x)) != CC0
521 && GET_CODE (SET_DEST (x)) != PC
522 && !REG_P (SET_DEST (x))
523 && ! (GET_CODE (SET_DEST (x)) == SUBREG
524 && REG_P (SUBREG_REG (SET_DEST (x)))
525 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
526 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
527 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
528 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
531 return find_single_use_1 (dest, &SET_SRC (x));
535 return find_single_use_1 (dest, &XEXP (x, 0));
541 /* If it wasn't one of the common cases above, check each expression and
542 vector of this code. Look for a unique usage of DEST. */
544 fmt = GET_RTX_FORMAT (code);
545 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
549 if (dest == XEXP (x, i)
550 || (REG_P (dest) && REG_P (XEXP (x, i))
551 && REGNO (dest) == REGNO (XEXP (x, i))))
554 this_result = find_single_use_1 (dest, &XEXP (x, i));
557 result = this_result;
558 else if (this_result)
559 /* Duplicate usage. */
562 else if (fmt[i] == 'E')
566 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
568 if (XVECEXP (x, i, j) == dest
570 && REG_P (XVECEXP (x, i, j))
571 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
574 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
577 result = this_result;
578 else if (this_result)
588 /* See if DEST, produced in INSN, is used only a single time in the
589 sequel. If so, return a pointer to the innermost rtx expression in which
592 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
594 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
595 care about REG_DEAD notes or LOG_LINKS.
597 Otherwise, we find the single use by finding an insn that has a
598 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
599 only referenced once in that insn, we know that it must be the first
600 and last insn referencing DEST. */
603 find_single_use (rtx dest, rtx insn, rtx *ploc)
612 next = NEXT_INSN (insn);
614 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
617 result = find_single_use_1 (dest, &PATTERN (next));
627 for (next = next_nonnote_insn (insn);
628 next != 0 && !LABEL_P (next);
629 next = next_nonnote_insn (next))
630 if (INSN_P (next) && dead_or_set_p (next, dest))
632 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
633 if (XEXP (link, 0) == insn)
638 result = find_single_use_1 (dest, &PATTERN (next));
648 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
649 insn. The substitution can be undone by undo_all. If INTO is already
650 set to NEWVAL, do not record this change. Because computing NEWVAL might
651 also call SUBST, we have to compute it before we put anything into
655 do_SUBST (rtx *into, rtx newval)
660 if (oldval == newval)
663 /* We'd like to catch as many invalid transformations here as
664 possible. Unfortunately, there are way too many mode changes
665 that are perfectly valid, so we'd waste too much effort for
666 little gain doing the checks here. Focus on catching invalid
667 transformations involving integer constants. */
668 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
669 && GET_CODE (newval) == CONST_INT)
671 /* Sanity check that we're replacing oldval with a CONST_INT
672 that is a valid sign-extension for the original mode. */
673 gcc_assert (INTVAL (newval)
674 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
676 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
677 CONST_INT is not valid, because after the replacement, the
678 original mode would be gone. Unfortunately, we can't tell
679 when do_SUBST is called to replace the operand thereof, so we
680 perform this test on oldval instead, checking whether an
681 invalid replacement took place before we got here. */
682 gcc_assert (!(GET_CODE (oldval) == SUBREG
683 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
684 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
685 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
689 buf = undobuf.frees, undobuf.frees = buf->next;
691 buf = XNEW (struct undo);
693 buf->kind = UNDO_RTX;
695 buf->old_contents.r = oldval;
698 buf->next = undobuf.undos, undobuf.undos = buf;
701 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
703 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
704 for the value of a HOST_WIDE_INT value (including CONST_INT) is
708 do_SUBST_INT (int *into, int newval)
713 if (oldval == newval)
717 buf = undobuf.frees, undobuf.frees = buf->next;
719 buf = XNEW (struct undo);
721 buf->kind = UNDO_INT;
723 buf->old_contents.i = oldval;
726 buf->next = undobuf.undos, undobuf.undos = buf;
729 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
731 /* Similar to SUBST, but just substitute the mode. This is used when
732 changing the mode of a pseudo-register, so that any other
733 references to the entry in the regno_reg_rtx array will change as
737 do_SUBST_MODE (rtx *into, enum machine_mode newval)
740 enum machine_mode oldval = GET_MODE (*into);
742 if (oldval == newval)
746 buf = undobuf.frees, undobuf.frees = buf->next;
748 buf = XNEW (struct undo);
750 buf->kind = UNDO_MODE;
752 buf->old_contents.m = oldval;
753 PUT_MODE (*into, newval);
755 buf->next = undobuf.undos, undobuf.undos = buf;
758 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
760 /* Subroutine of try_combine. Determine whether the combine replacement
761 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
762 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
763 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
764 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
765 function returns false, if the costs of all instructions can be
766 estimated, and the replacements are more expensive than the original
770 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
773 int i1_cost, i2_cost, i3_cost;
774 int new_i2_cost, new_i3_cost;
775 int old_cost, new_cost;
777 /* Lookup the original insn_rtx_costs. */
778 i2_cost = INSN_COST (i2);
779 i3_cost = INSN_COST (i3);
783 i1_cost = INSN_COST (i1);
784 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
785 ? i1_cost + i2_cost + i3_cost : 0;
789 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
793 /* Calculate the replacement insn_rtx_costs. */
794 new_i3_cost = insn_rtx_cost (newpat);
797 new_i2_cost = insn_rtx_cost (newi2pat);
798 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
799 ? new_i2_cost + new_i3_cost : 0;
803 new_cost = new_i3_cost;
807 if (undobuf.other_insn)
809 int old_other_cost, new_other_cost;
811 old_other_cost = INSN_COST (undobuf.other_insn);
812 new_other_cost = insn_rtx_cost (newotherpat);
813 if (old_other_cost > 0 && new_other_cost > 0)
815 old_cost += old_other_cost;
816 new_cost += new_other_cost;
822 /* Disallow this recombination if both new_cost and old_cost are
823 greater than zero, and new_cost is greater than old cost. */
825 && new_cost > old_cost)
832 "rejecting combination of insns %d, %d and %d\n",
833 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
834 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
835 i1_cost, i2_cost, i3_cost, old_cost);
840 "rejecting combination of insns %d and %d\n",
841 INSN_UID (i2), INSN_UID (i3));
842 fprintf (dump_file, "original costs %d + %d = %d\n",
843 i2_cost, i3_cost, old_cost);
848 fprintf (dump_file, "replacement costs %d + %d = %d\n",
849 new_i2_cost, new_i3_cost, new_cost);
852 fprintf (dump_file, "replacement cost %d\n", new_cost);
858 /* Update the uid_insn_cost array with the replacement costs. */
859 INSN_COST (i2) = new_i2_cost;
860 INSN_COST (i3) = new_i3_cost;
868 /* Delete any insns that copy a register to itself. */
871 delete_noop_moves (void)
878 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
880 next = NEXT_INSN (insn);
881 if (INSN_P (insn) && noop_move_p (insn))
885 /* If we're about to remove the first insn of a libcall
886 then move the libcall note to the next real insn and
887 update the retval note. */
888 if ((note = find_reg_note (insn, REG_LIBCALL, NULL_RTX))
889 && XEXP (note, 0) != insn)
891 rtx new_libcall_insn = next_real_insn (insn);
892 rtx retval_note = find_reg_note (XEXP (note, 0),
893 REG_RETVAL, NULL_RTX);
894 REG_NOTES (new_libcall_insn)
895 = gen_rtx_INSN_LIST (REG_LIBCALL, XEXP (note, 0),
896 REG_NOTES (new_libcall_insn));
897 XEXP (retval_note, 0) = new_libcall_insn;
901 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
903 delete_insn_and_edges (insn);
910 /* Fill in log links field for all insns. */
913 create_log_links (void)
917 struct df_ref **def_vec, **use_vec;
919 next_use = XCNEWVEC (rtx, max_reg_num ());
921 /* Pass through each block from the end, recording the uses of each
922 register and establishing log links when def is encountered.
923 Note that we do not clear next_use array in order to save time,
924 so we have to test whether the use is in the same basic block as def.
926 There are a few cases below when we do not consider the definition or
927 usage -- these are taken from original flow.c did. Don't ask me why it is
928 done this way; I don't know and if it works, I don't want to know. */
932 FOR_BB_INSNS_REVERSE (bb, insn)
937 /* Log links are created only once. */
938 gcc_assert (!LOG_LINKS (insn));
940 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
942 struct df_ref *def = *def_vec;
943 int regno = DF_REF_REGNO (def);
946 if (!next_use[regno])
949 /* Do not consider if it is pre/post modification in MEM. */
950 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
953 /* Do not make the log link for frame pointer. */
954 if ((regno == FRAME_POINTER_REGNUM
955 && (! reload_completed || frame_pointer_needed))
956 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
957 || (regno == HARD_FRAME_POINTER_REGNUM
958 && (! reload_completed || frame_pointer_needed))
960 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
961 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
966 use_insn = next_use[regno];
967 if (BLOCK_FOR_INSN (use_insn) == bb)
971 We don't build a LOG_LINK for hard registers contained
972 in ASM_OPERANDs. If these registers get replaced,
973 we might wind up changing the semantics of the insn,
974 even if reload can make what appear to be valid
975 assignments later. */
976 if (regno >= FIRST_PSEUDO_REGISTER
977 || asm_noperands (PATTERN (use_insn)) < 0)
978 LOG_LINKS (use_insn) =
979 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 struct df_ref *use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1017 /* Main entry point for combiner. F is the first insn of the function.
1018 NREGS is the first unused pseudo-reg number.
1020 Return nonzero if the combiner has turned an indirect jump
1021 instruction into a direct jump. */
1023 combine_instructions (rtx f, unsigned int nregs)
1029 rtx links, nextlinks;
1032 int new_direct_jump_p = 0;
1034 for (first = f; first && !INSN_P (first); )
1035 first = NEXT_INSN (first);
1039 combine_attempts = 0;
1042 combine_successes = 0;
1044 rtl_hooks = combine_rtl_hooks;
1046 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1048 init_recog_no_volatile ();
1050 /* Allocate array for insn info. */
1051 max_uid_known = get_max_uid ();
1052 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1053 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1055 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1057 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1058 problems when, for example, we have j <<= 1 in a loop. */
1060 nonzero_sign_valid = 0;
1062 /* Scan all SETs and see if we can deduce anything about what
1063 bits are known to be zero for some registers and how many copies
1064 of the sign bit are known to exist for those registers.
1066 Also set any known values so that we can use it while searching
1067 for what bits are known to be set. */
1069 label_tick = label_tick_ebb_start = 1;
1071 setup_incoming_promotions (first);
1073 create_log_links ();
1074 FOR_EACH_BB (this_basic_block)
1079 FOR_BB_INSNS (this_basic_block, insn)
1080 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1082 subst_low_luid = DF_INSN_LUID (insn);
1085 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1087 record_dead_and_set_regs (insn);
1090 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1091 if (REG_NOTE_KIND (links) == REG_INC)
1092 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1096 /* Record the current insn_rtx_cost of this instruction. */
1097 if (NONJUMP_INSN_P (insn))
1098 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn));
1100 fprintf(dump_file, "insn_cost %d: %d\n",
1101 INSN_UID (insn), INSN_COST (insn));
1103 else if (LABEL_P (insn))
1104 label_tick_ebb_start = label_tick;
1107 nonzero_sign_valid = 1;
1109 /* Now scan all the insns in forward order. */
1111 label_tick = label_tick_ebb_start = 1;
1113 setup_incoming_promotions (first);
1115 FOR_EACH_BB (this_basic_block)
1120 for (insn = BB_HEAD (this_basic_block);
1121 insn != NEXT_INSN (BB_END (this_basic_block));
1122 insn = next ? next : NEXT_INSN (insn))
1127 /* See if we know about function return values before this
1128 insn based upon SUBREG flags. */
1129 check_conversions (insn, PATTERN (insn));
1131 /* Try this insn with each insn it links back to. */
1133 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1134 if ((next = try_combine (insn, XEXP (links, 0),
1135 NULL_RTX, &new_direct_jump_p)) != 0)
1138 /* Try each sequence of three linked insns ending with this one. */
1140 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1142 rtx link = XEXP (links, 0);
1144 /* If the linked insn has been replaced by a note, then there
1145 is no point in pursuing this chain any further. */
1149 for (nextlinks = LOG_LINKS (link);
1151 nextlinks = XEXP (nextlinks, 1))
1152 if ((next = try_combine (insn, link,
1153 XEXP (nextlinks, 0),
1154 &new_direct_jump_p)) != 0)
1159 /* Try to combine a jump insn that uses CC0
1160 with a preceding insn that sets CC0, and maybe with its
1161 logical predecessor as well.
1162 This is how we make decrement-and-branch insns.
1163 We need this special code because data flow connections
1164 via CC0 do not get entered in LOG_LINKS. */
1167 && (prev = prev_nonnote_insn (insn)) != 0
1168 && NONJUMP_INSN_P (prev)
1169 && sets_cc0_p (PATTERN (prev)))
1171 if ((next = try_combine (insn, prev,
1172 NULL_RTX, &new_direct_jump_p)) != 0)
1175 for (nextlinks = LOG_LINKS (prev); nextlinks;
1176 nextlinks = XEXP (nextlinks, 1))
1177 if ((next = try_combine (insn, prev,
1178 XEXP (nextlinks, 0),
1179 &new_direct_jump_p)) != 0)
1183 /* Do the same for an insn that explicitly references CC0. */
1184 if (NONJUMP_INSN_P (insn)
1185 && (prev = prev_nonnote_insn (insn)) != 0
1186 && NONJUMP_INSN_P (prev)
1187 && sets_cc0_p (PATTERN (prev))
1188 && GET_CODE (PATTERN (insn)) == SET
1189 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1191 if ((next = try_combine (insn, prev,
1192 NULL_RTX, &new_direct_jump_p)) != 0)
1195 for (nextlinks = LOG_LINKS (prev); nextlinks;
1196 nextlinks = XEXP (nextlinks, 1))
1197 if ((next = try_combine (insn, prev,
1198 XEXP (nextlinks, 0),
1199 &new_direct_jump_p)) != 0)
1203 /* Finally, see if any of the insns that this insn links to
1204 explicitly references CC0. If so, try this insn, that insn,
1205 and its predecessor if it sets CC0. */
1206 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1207 if (NONJUMP_INSN_P (XEXP (links, 0))
1208 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1209 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1210 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1211 && NONJUMP_INSN_P (prev)
1212 && sets_cc0_p (PATTERN (prev))
1213 && (next = try_combine (insn, XEXP (links, 0),
1214 prev, &new_direct_jump_p)) != 0)
1218 /* Try combining an insn with two different insns whose results it
1220 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1221 for (nextlinks = XEXP (links, 1); nextlinks;
1222 nextlinks = XEXP (nextlinks, 1))
1223 if ((next = try_combine (insn, XEXP (links, 0),
1224 XEXP (nextlinks, 0),
1225 &new_direct_jump_p)) != 0)
1228 /* Try this insn with each REG_EQUAL note it links back to. */
1229 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1232 rtx temp = XEXP (links, 0);
1233 if ((set = single_set (temp)) != 0
1234 && (note = find_reg_equal_equiv_note (temp)) != 0
1235 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1236 /* Avoid using a register that may already been marked
1237 dead by an earlier instruction. */
1238 && ! unmentioned_reg_p (note, SET_SRC (set))
1239 && (GET_MODE (note) == VOIDmode
1240 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1241 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1243 /* Temporarily replace the set's source with the
1244 contents of the REG_EQUAL note. The insn will
1245 be deleted or recognized by try_combine. */
1246 rtx orig = SET_SRC (set);
1247 SET_SRC (set) = note;
1249 i2mod_old_rhs = copy_rtx (orig);
1250 i2mod_new_rhs = copy_rtx (note);
1251 next = try_combine (insn, i2mod, NULL_RTX,
1252 &new_direct_jump_p);
1256 SET_SRC (set) = orig;
1261 record_dead_and_set_regs (insn);
1266 else if (LABEL_P (insn))
1267 label_tick_ebb_start = label_tick;
1273 new_direct_jump_p |= purge_all_dead_edges ();
1274 delete_noop_moves ();
1277 free (uid_log_links);
1278 free (uid_insn_cost);
1279 VEC_free (reg_stat_type, heap, reg_stat);
1282 struct undo *undo, *next;
1283 for (undo = undobuf.frees; undo; undo = next)
1291 total_attempts += combine_attempts;
1292 total_merges += combine_merges;
1293 total_extras += combine_extras;
1294 total_successes += combine_successes;
1296 nonzero_sign_valid = 0;
1297 rtl_hooks = general_rtl_hooks;
1299 /* Make recognizer allow volatile MEMs again. */
1302 return new_direct_jump_p;
1305 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1308 init_reg_last (void)
1313 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1314 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1317 /* Set up any promoted values for incoming argument registers. */
1320 setup_incoming_promotions (rtx first)
1324 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1327 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1328 arg = TREE_CHAIN (arg))
1330 rtx reg = DECL_INCOMING_RTL (arg);
1335 if (TYPE_MODE (DECL_ARG_TYPE (arg)) == TYPE_MODE (TREE_TYPE (arg)))
1337 enum machine_mode mode = TYPE_MODE (TREE_TYPE (arg));
1338 int uns = TYPE_UNSIGNED (TREE_TYPE (arg));
1340 mode = promote_mode (TREE_TYPE (arg), mode, &uns, 1);
1341 if (mode == GET_MODE (reg) && mode != DECL_MODE (arg))
1344 x = gen_rtx_CLOBBER (DECL_MODE (arg), const0_rtx);
1345 x = gen_rtx_fmt_e ((uns ? ZERO_EXTEND : SIGN_EXTEND), mode, x);
1346 record_value_for_reg (reg, first, x);
1352 /* Called via note_stores. If X is a pseudo that is narrower than
1353 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1355 If we are setting only a portion of X and we can't figure out what
1356 portion, assume all bits will be used since we don't know what will
1359 Similarly, set how many bits of X are known to be copies of the sign bit
1360 at all locations in the function. This is the smallest number implied
1364 set_nonzero_bits_and_sign_copies (rtx x, rtx set, void *data)
1366 rtx insn = (rtx) data;
1370 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1371 /* If this register is undefined at the start of the file, we can't
1372 say what its contents were. */
1373 && ! REGNO_REG_SET_P
1374 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1375 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1377 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1379 if (set == 0 || GET_CODE (set) == CLOBBER)
1381 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1382 rsp->sign_bit_copies = 1;
1386 /* If this register is being initialized using itself, and the
1387 register is uninitialized in this basic block, and there are
1388 no LOG_LINKS which set the register, then part of the
1389 register is uninitialized. In that case we can't assume
1390 anything about the number of nonzero bits.
1392 ??? We could do better if we checked this in
1393 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1394 could avoid making assumptions about the insn which initially
1395 sets the register, while still using the information in other
1396 insns. We would have to be careful to check every insn
1397 involved in the combination. */
1400 && reg_referenced_p (x, PATTERN (insn))
1401 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1406 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1408 if (dead_or_set_p (XEXP (link, 0), x))
1413 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1414 rsp->sign_bit_copies = 1;
1419 /* If this is a complex assignment, see if we can convert it into a
1420 simple assignment. */
1421 set = expand_field_assignment (set);
1423 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1424 set what we know about X. */
1426 if (SET_DEST (set) == x
1427 || (GET_CODE (SET_DEST (set)) == SUBREG
1428 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1429 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1430 && SUBREG_REG (SET_DEST (set)) == x))
1432 rtx src = SET_SRC (set);
1434 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1435 /* If X is narrower than a word and SRC is a non-negative
1436 constant that would appear negative in the mode of X,
1437 sign-extend it for use in reg_stat[].nonzero_bits because some
1438 machines (maybe most) will actually do the sign-extension
1439 and this is the conservative approach.
1441 ??? For 2.5, try to tighten up the MD files in this regard
1442 instead of this kludge. */
1444 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1445 && GET_CODE (src) == CONST_INT
1447 && 0 != (INTVAL (src)
1448 & ((HOST_WIDE_INT) 1
1449 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1450 src = GEN_INT (INTVAL (src)
1451 | ((HOST_WIDE_INT) (-1)
1452 << GET_MODE_BITSIZE (GET_MODE (x))));
1455 /* Don't call nonzero_bits if it cannot change anything. */
1456 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1457 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1458 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1459 if (rsp->sign_bit_copies == 0
1460 || rsp->sign_bit_copies > num)
1461 rsp->sign_bit_copies = num;
1465 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1466 rsp->sign_bit_copies = 1;
1471 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1472 insns that were previously combined into I3 or that will be combined
1473 into the merger of INSN and I3.
1475 Return 0 if the combination is not allowed for any reason.
1477 If the combination is allowed, *PDEST will be set to the single
1478 destination of INSN and *PSRC to the single source, and this function
1482 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1483 rtx *pdest, rtx *psrc)
1486 rtx set = 0, src, dest;
1491 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1492 && next_active_insn (succ) == i3)
1493 : next_active_insn (insn) == i3);
1495 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1496 or a PARALLEL consisting of such a SET and CLOBBERs.
1498 If INSN has CLOBBER parallel parts, ignore them for our processing.
1499 By definition, these happen during the execution of the insn. When it
1500 is merged with another insn, all bets are off. If they are, in fact,
1501 needed and aren't also supplied in I3, they may be added by
1502 recog_for_combine. Otherwise, it won't match.
1504 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1507 Get the source and destination of INSN. If more than one, can't
1510 if (GET_CODE (PATTERN (insn)) == SET)
1511 set = PATTERN (insn);
1512 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1513 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1515 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1517 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1520 switch (GET_CODE (elt))
1522 /* This is important to combine floating point insns
1523 for the SH4 port. */
1525 /* Combining an isolated USE doesn't make sense.
1526 We depend here on combinable_i3pat to reject them. */
1527 /* The code below this loop only verifies that the inputs of
1528 the SET in INSN do not change. We call reg_set_between_p
1529 to verify that the REG in the USE does not change between
1531 If the USE in INSN was for a pseudo register, the matching
1532 insn pattern will likely match any register; combining this
1533 with any other USE would only be safe if we knew that the
1534 used registers have identical values, or if there was
1535 something to tell them apart, e.g. different modes. For
1536 now, we forgo such complicated tests and simply disallow
1537 combining of USES of pseudo registers with any other USE. */
1538 if (REG_P (XEXP (elt, 0))
1539 && GET_CODE (PATTERN (i3)) == PARALLEL)
1541 rtx i3pat = PATTERN (i3);
1542 int i = XVECLEN (i3pat, 0) - 1;
1543 unsigned int regno = REGNO (XEXP (elt, 0));
1547 rtx i3elt = XVECEXP (i3pat, 0, i);
1549 if (GET_CODE (i3elt) == USE
1550 && REG_P (XEXP (i3elt, 0))
1551 && (REGNO (XEXP (i3elt, 0)) == regno
1552 ? reg_set_between_p (XEXP (elt, 0),
1553 PREV_INSN (insn), i3)
1554 : regno >= FIRST_PSEUDO_REGISTER))
1561 /* We can ignore CLOBBERs. */
1566 /* Ignore SETs whose result isn't used but not those that
1567 have side-effects. */
1568 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1569 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1570 || INTVAL (XEXP (note, 0)) <= 0)
1571 && ! side_effects_p (elt))
1574 /* If we have already found a SET, this is a second one and
1575 so we cannot combine with this insn. */
1583 /* Anything else means we can't combine. */
1589 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1590 so don't do anything with it. */
1591 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1600 set = expand_field_assignment (set);
1601 src = SET_SRC (set), dest = SET_DEST (set);
1603 /* Don't eliminate a store in the stack pointer. */
1604 if (dest == stack_pointer_rtx
1605 /* Don't combine with an insn that sets a register to itself if it has
1606 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1607 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1608 /* Can't merge an ASM_OPERANDS. */
1609 || GET_CODE (src) == ASM_OPERANDS
1610 /* Can't merge a function call. */
1611 || GET_CODE (src) == CALL
1612 /* Don't eliminate a function call argument. */
1614 && (find_reg_fusage (i3, USE, dest)
1616 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1617 && global_regs[REGNO (dest)])))
1618 /* Don't substitute into an incremented register. */
1619 || FIND_REG_INC_NOTE (i3, dest)
1620 || (succ && FIND_REG_INC_NOTE (succ, dest))
1621 /* Don't substitute into a non-local goto, this confuses CFG. */
1622 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1624 /* Don't combine the end of a libcall into anything. */
1625 /* ??? This gives worse code, and appears to be unnecessary, since no
1626 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1627 use REG_RETVAL notes for noconflict blocks, but other code here
1628 makes sure that those insns don't disappear. */
1629 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1631 /* Make sure that DEST is not used after SUCC but before I3. */
1632 || (succ && ! all_adjacent
1633 && reg_used_between_p (dest, succ, i3))
1634 /* Make sure that the value that is to be substituted for the register
1635 does not use any registers whose values alter in between. However,
1636 If the insns are adjacent, a use can't cross a set even though we
1637 think it might (this can happen for a sequence of insns each setting
1638 the same destination; last_set of that register might point to
1639 a NOTE). If INSN has a REG_EQUIV note, the register is always
1640 equivalent to the memory so the substitution is valid even if there
1641 are intervening stores. Also, don't move a volatile asm or
1642 UNSPEC_VOLATILE across any other insns. */
1645 || ! find_reg_note (insn, REG_EQUIV, src))
1646 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1647 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1648 || GET_CODE (src) == UNSPEC_VOLATILE))
1649 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1650 better register allocation by not doing the combine. */
1651 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1652 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1653 /* Don't combine across a CALL_INSN, because that would possibly
1654 change whether the life span of some REGs crosses calls or not,
1655 and it is a pain to update that information.
1656 Exception: if source is a constant, moving it later can't hurt.
1657 Accept that special case, because it helps -fforce-addr a lot. */
1658 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1661 /* DEST must either be a REG or CC0. */
1664 /* If register alignment is being enforced for multi-word items in all
1665 cases except for parameters, it is possible to have a register copy
1666 insn referencing a hard register that is not allowed to contain the
1667 mode being copied and which would not be valid as an operand of most
1668 insns. Eliminate this problem by not combining with such an insn.
1670 Also, on some machines we don't want to extend the life of a hard
1674 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1675 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1676 /* Don't extend the life of a hard register unless it is
1677 user variable (if we have few registers) or it can't
1678 fit into the desired register (meaning something special
1680 Also avoid substituting a return register into I3, because
1681 reload can't handle a conflict with constraints of other
1683 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1684 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1687 else if (GET_CODE (dest) != CC0)
1691 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1692 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1693 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1695 /* Don't substitute for a register intended as a clobberable
1697 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1698 if (rtx_equal_p (reg, dest))
1701 /* If the clobber represents an earlyclobber operand, we must not
1702 substitute an expression containing the clobbered register.
1703 As we do not analyze the constraint strings here, we have to
1704 make the conservative assumption. However, if the register is
1705 a fixed hard reg, the clobber cannot represent any operand;
1706 we leave it up to the machine description to either accept or
1707 reject use-and-clobber patterns. */
1709 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1710 || !fixed_regs[REGNO (reg)])
1711 if (reg_overlap_mentioned_p (reg, src))
1715 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1716 or not), reject, unless nothing volatile comes between it and I3 */
1718 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1720 /* Make sure succ doesn't contain a volatile reference. */
1721 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1724 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1725 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1729 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1730 to be an explicit register variable, and was chosen for a reason. */
1732 if (GET_CODE (src) == ASM_OPERANDS
1733 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1736 /* If there are any volatile insns between INSN and I3, reject, because
1737 they might affect machine state. */
1739 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1740 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1743 /* If INSN contains an autoincrement or autodecrement, make sure that
1744 register is not used between there and I3, and not already used in
1745 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1746 Also insist that I3 not be a jump; if it were one
1747 and the incremented register were spilled, we would lose. */
1750 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1751 if (REG_NOTE_KIND (link) == REG_INC
1753 || reg_used_between_p (XEXP (link, 0), insn, i3)
1754 || (pred != NULL_RTX
1755 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1756 || (succ != NULL_RTX
1757 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1758 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1763 /* Don't combine an insn that follows a CC0-setting insn.
1764 An insn that uses CC0 must not be separated from the one that sets it.
1765 We do, however, allow I2 to follow a CC0-setting insn if that insn
1766 is passed as I1; in that case it will be deleted also.
1767 We also allow combining in this case if all the insns are adjacent
1768 because that would leave the two CC0 insns adjacent as well.
1769 It would be more logical to test whether CC0 occurs inside I1 or I2,
1770 but that would be much slower, and this ought to be equivalent. */
1772 p = prev_nonnote_insn (insn);
1773 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1778 /* If we get here, we have passed all the tests and the combination is
1787 /* LOC is the location within I3 that contains its pattern or the component
1788 of a PARALLEL of the pattern. We validate that it is valid for combining.
1790 One problem is if I3 modifies its output, as opposed to replacing it
1791 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1792 so would produce an insn that is not equivalent to the original insns.
1796 (set (reg:DI 101) (reg:DI 100))
1797 (set (subreg:SI (reg:DI 101) 0) <foo>)
1799 This is NOT equivalent to:
1801 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1802 (set (reg:DI 101) (reg:DI 100))])
1804 Not only does this modify 100 (in which case it might still be valid
1805 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1807 We can also run into a problem if I2 sets a register that I1
1808 uses and I1 gets directly substituted into I3 (not via I2). In that
1809 case, we would be getting the wrong value of I2DEST into I3, so we
1810 must reject the combination. This case occurs when I2 and I1 both
1811 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1812 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1813 of a SET must prevent combination from occurring.
1815 Before doing the above check, we first try to expand a field assignment
1816 into a set of logical operations.
1818 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1819 we place a register that is both set and used within I3. If more than one
1820 such register is detected, we fail.
1822 Return 1 if the combination is valid, zero otherwise. */
1825 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1826 int i1_not_in_src, rtx *pi3dest_killed)
1830 if (GET_CODE (x) == SET)
1833 rtx dest = SET_DEST (set);
1834 rtx src = SET_SRC (set);
1835 rtx inner_dest = dest;
1838 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1839 || GET_CODE (inner_dest) == SUBREG
1840 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1841 inner_dest = XEXP (inner_dest, 0);
1843 /* Check for the case where I3 modifies its output, as discussed
1844 above. We don't want to prevent pseudos from being combined
1845 into the address of a MEM, so only prevent the combination if
1846 i1 or i2 set the same MEM. */
1847 if ((inner_dest != dest &&
1848 (!MEM_P (inner_dest)
1849 || rtx_equal_p (i2dest, inner_dest)
1850 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1851 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1852 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1854 /* This is the same test done in can_combine_p except we can't test
1855 all_adjacent; we don't have to, since this instruction will stay
1856 in place, thus we are not considering increasing the lifetime of
1859 Also, if this insn sets a function argument, combining it with
1860 something that might need a spill could clobber a previous
1861 function argument; the all_adjacent test in can_combine_p also
1862 checks this; here, we do a more specific test for this case. */
1864 || (REG_P (inner_dest)
1865 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1866 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1867 GET_MODE (inner_dest))))
1868 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1871 /* If DEST is used in I3, it is being killed in this insn, so
1872 record that for later. We have to consider paradoxical
1873 subregs here, since they kill the whole register, but we
1874 ignore partial subregs, STRICT_LOW_PART, etc.
1875 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1876 STACK_POINTER_REGNUM, since these are always considered to be
1877 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1879 if (GET_CODE (subdest) == SUBREG
1880 && (GET_MODE_SIZE (GET_MODE (subdest))
1881 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1882 subdest = SUBREG_REG (subdest);
1885 && reg_referenced_p (subdest, PATTERN (i3))
1886 && REGNO (subdest) != FRAME_POINTER_REGNUM
1887 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1888 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1890 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1891 && (REGNO (subdest) != ARG_POINTER_REGNUM
1892 || ! fixed_regs [REGNO (subdest)])
1894 && REGNO (subdest) != STACK_POINTER_REGNUM)
1896 if (*pi3dest_killed)
1899 *pi3dest_killed = subdest;
1903 else if (GET_CODE (x) == PARALLEL)
1907 for (i = 0; i < XVECLEN (x, 0); i++)
1908 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1909 i1_not_in_src, pi3dest_killed))
1916 /* Return 1 if X is an arithmetic expression that contains a multiplication
1917 and division. We don't count multiplications by powers of two here. */
1920 contains_muldiv (rtx x)
1922 switch (GET_CODE (x))
1924 case MOD: case DIV: case UMOD: case UDIV:
1928 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1929 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1932 return contains_muldiv (XEXP (x, 0))
1933 || contains_muldiv (XEXP (x, 1));
1936 return contains_muldiv (XEXP (x, 0));
1942 /* Determine whether INSN can be used in a combination. Return nonzero if
1943 not. This is used in try_combine to detect early some cases where we
1944 can't perform combinations. */
1947 cant_combine_insn_p (rtx insn)
1952 /* If this isn't really an insn, we can't do anything.
1953 This can occur when flow deletes an insn that it has merged into an
1954 auto-increment address. */
1955 if (! INSN_P (insn))
1958 /* Never combine loads and stores involving hard regs that are likely
1959 to be spilled. The register allocator can usually handle such
1960 reg-reg moves by tying. If we allow the combiner to make
1961 substitutions of likely-spilled regs, reload might die.
1962 As an exception, we allow combinations involving fixed regs; these are
1963 not available to the register allocator so there's no risk involved. */
1965 set = single_set (insn);
1968 src = SET_SRC (set);
1969 dest = SET_DEST (set);
1970 if (GET_CODE (src) == SUBREG)
1971 src = SUBREG_REG (src);
1972 if (GET_CODE (dest) == SUBREG)
1973 dest = SUBREG_REG (dest);
1974 if (REG_P (src) && REG_P (dest)
1975 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1976 && ! fixed_regs[REGNO (src)]
1977 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1978 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1979 && ! fixed_regs[REGNO (dest)]
1980 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1986 struct likely_spilled_retval_info
1988 unsigned regno, nregs;
1992 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1993 hard registers that are known to be written to / clobbered in full. */
1995 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1997 struct likely_spilled_retval_info *info = data;
1998 unsigned regno, nregs;
2001 if (!REG_P (XEXP (set, 0)))
2004 if (regno >= info->regno + info->nregs)
2006 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2007 if (regno + nregs <= info->regno)
2009 new_mask = (2U << (nregs - 1)) - 1;
2010 if (regno < info->regno)
2011 new_mask >>= info->regno - regno;
2013 new_mask <<= regno - info->regno;
2014 info->mask &= ~new_mask;
2017 /* Return nonzero iff part of the return value is live during INSN, and
2018 it is likely spilled. This can happen when more than one insn is needed
2019 to copy the return value, e.g. when we consider to combine into the
2020 second copy insn for a complex value. */
2023 likely_spilled_retval_p (rtx insn)
2025 rtx use = BB_END (this_basic_block);
2027 unsigned regno, nregs;
2028 /* We assume here that no machine mode needs more than
2029 32 hard registers when the value overlaps with a register
2030 for which FUNCTION_VALUE_REGNO_P is true. */
2032 struct likely_spilled_retval_info info;
2034 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2036 reg = XEXP (PATTERN (use), 0);
2037 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2039 regno = REGNO (reg);
2040 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2043 mask = (2U << (nregs - 1)) - 1;
2045 /* Disregard parts of the return value that are set later. */
2049 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2051 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2054 /* Check if any of the (probably) live return value registers is
2059 if ((mask & 1 << nregs)
2060 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2066 /* Adjust INSN after we made a change to its destination.
2068 Changing the destination can invalidate notes that say something about
2069 the results of the insn and a LOG_LINK pointing to the insn. */
2072 adjust_for_new_dest (rtx insn)
2074 /* For notes, be conservative and simply remove them. */
2075 remove_reg_equal_equiv_notes (insn);
2077 /* The new insn will have a destination that was previously the destination
2078 of an insn just above it. Call distribute_links to make a LOG_LINK from
2079 the next use of that destination. */
2080 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2082 df_insn_rescan (insn);
2085 /* Return TRUE if combine can reuse reg X in mode MODE.
2086 ADDED_SETS is nonzero if the original set is still required. */
2088 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2096 /* Allow hard registers if the new mode is legal, and occupies no more
2097 registers than the old mode. */
2098 if (regno < FIRST_PSEUDO_REGISTER)
2099 return (HARD_REGNO_MODE_OK (regno, mode)
2100 && (hard_regno_nregs[regno][GET_MODE (x)]
2101 >= hard_regno_nregs[regno][mode]));
2103 /* Or a pseudo that is only used once. */
2104 return (REG_N_SETS (regno) == 1 && !added_sets
2105 && !REG_USERVAR_P (x));
2109 /* Check whether X, the destination of a set, refers to part of
2110 the register specified by REG. */
2113 reg_subword_p (rtx x, rtx reg)
2115 /* Check that reg is an integer mode register. */
2116 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2119 if (GET_CODE (x) == STRICT_LOW_PART
2120 || GET_CODE (x) == ZERO_EXTRACT)
2123 return GET_CODE (x) == SUBREG
2124 && SUBREG_REG (x) == reg
2125 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2129 /* Try to combine the insns I1 and I2 into I3.
2130 Here I1 and I2 appear earlier than I3.
2131 I1 can be zero; then we combine just I2 into I3.
2133 If we are combining three insns and the resulting insn is not recognized,
2134 try splitting it into two insns. If that happens, I2 and I3 are retained
2135 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2138 Return 0 if the combination does not work. Then nothing is changed.
2139 If we did the combination, return the insn at which combine should
2142 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2143 new direct jump instruction. */
2146 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2148 /* New patterns for I3 and I2, respectively. */
2149 rtx newpat, newi2pat = 0;
2150 rtvec newpat_vec_with_clobbers = 0;
2151 int substed_i2 = 0, substed_i1 = 0;
2152 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2153 int added_sets_1, added_sets_2;
2154 /* Total number of SETs to put into I3. */
2156 /* Nonzero if I2's body now appears in I3. */
2158 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2159 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2160 /* Contains I3 if the destination of I3 is used in its source, which means
2161 that the old life of I3 is being killed. If that usage is placed into
2162 I2 and not in I3, a REG_DEAD note must be made. */
2163 rtx i3dest_killed = 0;
2164 /* SET_DEST and SET_SRC of I2 and I1. */
2165 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2166 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2167 rtx i1pat = 0, i2pat = 0;
2168 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2169 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2170 int i2dest_killed = 0, i1dest_killed = 0;
2171 int i1_feeds_i3 = 0;
2172 /* Notes that must be added to REG_NOTES in I3 and I2. */
2173 rtx new_i3_notes, new_i2_notes;
2174 /* Notes that we substituted I3 into I2 instead of the normal case. */
2175 int i3_subst_into_i2 = 0;
2176 /* Notes that I1, I2 or I3 is a MULT operation. */
2184 rtx new_other_notes;
2187 /* Exit early if one of the insns involved can't be used for
2189 if (cant_combine_insn_p (i3)
2190 || cant_combine_insn_p (i2)
2191 || (i1 && cant_combine_insn_p (i1))
2192 || likely_spilled_retval_p (i3)
2193 /* We also can't do anything if I3 has a
2194 REG_LIBCALL note since we don't want to disrupt the contiguity of a
2197 /* ??? This gives worse code, and appears to be unnecessary, since no
2198 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
2199 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
2205 undobuf.other_insn = 0;
2207 /* Reset the hard register usage information. */
2208 CLEAR_HARD_REG_SET (newpat_used_regs);
2210 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2211 code below, set I1 to be the earlier of the two insns. */
2212 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2213 temp = i1, i1 = i2, i2 = temp;
2215 added_links_insn = 0;
2217 /* First check for one important special-case that the code below will
2218 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2219 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2220 we may be able to replace that destination with the destination of I3.
2221 This occurs in the common code where we compute both a quotient and
2222 remainder into a structure, in which case we want to do the computation
2223 directly into the structure to avoid register-register copies.
2225 Note that this case handles both multiple sets in I2 and also
2226 cases where I2 has a number of CLOBBER or PARALLELs.
2228 We make very conservative checks below and only try to handle the
2229 most common cases of this. For example, we only handle the case
2230 where I2 and I3 are adjacent to avoid making difficult register
2233 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2234 && REG_P (SET_SRC (PATTERN (i3)))
2235 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2236 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2237 && GET_CODE (PATTERN (i2)) == PARALLEL
2238 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2239 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2240 below would need to check what is inside (and reg_overlap_mentioned_p
2241 doesn't support those codes anyway). Don't allow those destinations;
2242 the resulting insn isn't likely to be recognized anyway. */
2243 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2244 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2245 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2246 SET_DEST (PATTERN (i3)))
2247 && next_real_insn (i2) == i3)
2249 rtx p2 = PATTERN (i2);
2251 /* Make sure that the destination of I3,
2252 which we are going to substitute into one output of I2,
2253 is not used within another output of I2. We must avoid making this:
2254 (parallel [(set (mem (reg 69)) ...)
2255 (set (reg 69) ...)])
2256 which is not well-defined as to order of actions.
2257 (Besides, reload can't handle output reloads for this.)
2259 The problem can also happen if the dest of I3 is a memory ref,
2260 if another dest in I2 is an indirect memory ref. */
2261 for (i = 0; i < XVECLEN (p2, 0); i++)
2262 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2263 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2264 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2265 SET_DEST (XVECEXP (p2, 0, i))))
2268 if (i == XVECLEN (p2, 0))
2269 for (i = 0; i < XVECLEN (p2, 0); i++)
2270 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2271 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2272 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2277 subst_low_luid = DF_INSN_LUID (i2);
2279 added_sets_2 = added_sets_1 = 0;
2280 i2dest = SET_SRC (PATTERN (i3));
2281 i2dest_killed = dead_or_set_p (i2, i2dest);
2283 /* Replace the dest in I2 with our dest and make the resulting
2284 insn the new pattern for I3. Then skip to where we
2285 validate the pattern. Everything was set up above. */
2286 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2287 SET_DEST (PATTERN (i3)));
2290 i3_subst_into_i2 = 1;
2291 goto validate_replacement;
2295 /* If I2 is setting a pseudo to a constant and I3 is setting some
2296 sub-part of it to another constant, merge them by making a new
2299 && (temp = single_set (i2)) != 0
2300 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2301 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2302 && GET_CODE (PATTERN (i3)) == SET
2303 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2304 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2305 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2307 rtx dest = SET_DEST (PATTERN (i3));
2311 if (GET_CODE (dest) == ZERO_EXTRACT)
2313 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2314 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2316 width = INTVAL (XEXP (dest, 1));
2317 offset = INTVAL (XEXP (dest, 2));
2318 dest = XEXP (dest, 0);
2319 if (BITS_BIG_ENDIAN)
2320 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2325 if (GET_CODE (dest) == STRICT_LOW_PART)
2326 dest = XEXP (dest, 0);
2327 width = GET_MODE_BITSIZE (GET_MODE (dest));
2333 /* If this is the low part, we're done. */
2334 if (subreg_lowpart_p (dest))
2336 /* Handle the case where inner is twice the size of outer. */
2337 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2338 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2339 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2340 /* Otherwise give up for now. */
2346 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2347 <= HOST_BITS_PER_WIDE_INT * 2))
2349 HOST_WIDE_INT mhi, ohi, ihi;
2350 HOST_WIDE_INT mlo, olo, ilo;
2351 rtx inner = SET_SRC (PATTERN (i3));
2352 rtx outer = SET_SRC (temp);
2354 if (GET_CODE (outer) == CONST_INT)
2356 olo = INTVAL (outer);
2357 ohi = olo < 0 ? -1 : 0;
2361 olo = CONST_DOUBLE_LOW (outer);
2362 ohi = CONST_DOUBLE_HIGH (outer);
2365 if (GET_CODE (inner) == CONST_INT)
2367 ilo = INTVAL (inner);
2368 ihi = ilo < 0 ? -1 : 0;
2372 ilo = CONST_DOUBLE_LOW (inner);
2373 ihi = CONST_DOUBLE_HIGH (inner);
2376 if (width < HOST_BITS_PER_WIDE_INT)
2378 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2381 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2383 mhi = ((unsigned HOST_WIDE_INT) 1
2384 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2396 if (offset >= HOST_BITS_PER_WIDE_INT)
2398 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2400 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2403 else if (offset > 0)
2405 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2406 >> (HOST_BITS_PER_WIDE_INT - offset));
2407 mlo = mlo << offset;
2408 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2409 >> (HOST_BITS_PER_WIDE_INT - offset));
2410 ilo = ilo << offset;
2413 olo = (olo & ~mlo) | ilo;
2414 ohi = (ohi & ~mhi) | ihi;
2418 subst_low_luid = DF_INSN_LUID (i2);
2419 added_sets_2 = added_sets_1 = 0;
2420 i2dest = SET_DEST (temp);
2421 i2dest_killed = dead_or_set_p (i2, i2dest);
2423 SUBST (SET_SRC (temp),
2424 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2426 newpat = PATTERN (i2);
2427 goto validate_replacement;
2432 /* If we have no I1 and I2 looks like:
2433 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2435 make up a dummy I1 that is
2438 (set (reg:CC X) (compare:CC Y (const_int 0)))
2440 (We can ignore any trailing CLOBBERs.)
2442 This undoes a previous combination and allows us to match a branch-and-
2445 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2446 && XVECLEN (PATTERN (i2), 0) >= 2
2447 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2448 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2450 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2451 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2452 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2453 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2454 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2455 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2457 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2458 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2463 /* We make I1 with the same INSN_UID as I2. This gives it
2464 the same DF_INSN_LUID for value tracking. Our fake I1 will
2465 never appear in the insn stream so giving it the same INSN_UID
2466 as I2 will not cause a problem. */
2468 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2469 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2470 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2472 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2473 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2474 SET_DEST (PATTERN (i1)));
2479 /* Verify that I2 and I1 are valid for combining. */
2480 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2481 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2487 /* Record whether I2DEST is used in I2SRC and similarly for the other
2488 cases. Knowing this will help in register status updating below. */
2489 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2490 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2491 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2492 i2dest_killed = dead_or_set_p (i2, i2dest);
2493 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2495 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2497 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2499 /* Ensure that I3's pattern can be the destination of combines. */
2500 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2501 i1 && i2dest_in_i1src && i1_feeds_i3,
2508 /* See if any of the insns is a MULT operation. Unless one is, we will
2509 reject a combination that is, since it must be slower. Be conservative
2511 if (GET_CODE (i2src) == MULT
2512 || (i1 != 0 && GET_CODE (i1src) == MULT)
2513 || (GET_CODE (PATTERN (i3)) == SET
2514 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2517 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2518 We used to do this EXCEPT in one case: I3 has a post-inc in an
2519 output operand. However, that exception can give rise to insns like
2521 which is a famous insn on the PDP-11 where the value of r3 used as the
2522 source was model-dependent. Avoid this sort of thing. */
2525 if (!(GET_CODE (PATTERN (i3)) == SET
2526 && REG_P (SET_SRC (PATTERN (i3)))
2527 && MEM_P (SET_DEST (PATTERN (i3)))
2528 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2529 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2530 /* It's not the exception. */
2533 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2534 if (REG_NOTE_KIND (link) == REG_INC
2535 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2537 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2544 /* See if the SETs in I1 or I2 need to be kept around in the merged
2545 instruction: whenever the value set there is still needed past I3.
2546 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2548 For the SET in I1, we have two cases: If I1 and I2 independently
2549 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2550 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2551 in I1 needs to be kept around unless I1DEST dies or is set in either
2552 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2553 I1DEST. If so, we know I1 feeds into I2. */
2555 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2558 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2559 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2561 /* If the set in I2 needs to be kept around, we must make a copy of
2562 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2563 PATTERN (I2), we are only substituting for the original I1DEST, not into
2564 an already-substituted copy. This also prevents making self-referential
2565 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2570 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2571 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2573 i2pat = copy_rtx (PATTERN (i2));
2578 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2579 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2581 i1pat = copy_rtx (PATTERN (i1));
2586 /* Substitute in the latest insn for the regs set by the earlier ones. */
2588 maxreg = max_reg_num ();
2593 /* Many machines that don't use CC0 have insns that can both perform an
2594 arithmetic operation and set the condition code. These operations will
2595 be represented as a PARALLEL with the first element of the vector
2596 being a COMPARE of an arithmetic operation with the constant zero.
2597 The second element of the vector will set some pseudo to the result
2598 of the same arithmetic operation. If we simplify the COMPARE, we won't
2599 match such a pattern and so will generate an extra insn. Here we test
2600 for this case, where both the comparison and the operation result are
2601 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2602 I2SRC. Later we will make the PARALLEL that contains I2. */
2604 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2605 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2606 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2607 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2609 #ifdef SELECT_CC_MODE
2611 enum machine_mode compare_mode;
2614 newpat = PATTERN (i3);
2615 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2619 #ifdef SELECT_CC_MODE
2620 /* See if a COMPARE with the operand we substituted in should be done
2621 with the mode that is currently being used. If not, do the same
2622 processing we do in `subst' for a SET; namely, if the destination
2623 is used only once, try to replace it with a register of the proper
2624 mode and also replace the COMPARE. */
2625 if (undobuf.other_insn == 0
2626 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2627 &undobuf.other_insn))
2628 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2630 != GET_MODE (SET_DEST (newpat))))
2632 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2635 unsigned int regno = REGNO (SET_DEST (newpat));
2638 if (regno < FIRST_PSEUDO_REGISTER)
2639 new_dest = gen_rtx_REG (compare_mode, regno);
2642 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2643 new_dest = regno_reg_rtx[regno];
2646 SUBST (SET_DEST (newpat), new_dest);
2647 SUBST (XEXP (*cc_use, 0), new_dest);
2648 SUBST (SET_SRC (newpat),
2649 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2652 undobuf.other_insn = 0;
2659 /* It is possible that the source of I2 or I1 may be performing
2660 an unneeded operation, such as a ZERO_EXTEND of something
2661 that is known to have the high part zero. Handle that case
2662 by letting subst look at the innermost one of them.
2664 Another way to do this would be to have a function that tries
2665 to simplify a single insn instead of merging two or more
2666 insns. We don't do this because of the potential of infinite
2667 loops and because of the potential extra memory required.
2668 However, doing it the way we are is a bit of a kludge and
2669 doesn't catch all cases.
2671 But only do this if -fexpensive-optimizations since it slows
2672 things down and doesn't usually win.
2674 This is not done in the COMPARE case above because the
2675 unmodified I2PAT is used in the PARALLEL and so a pattern
2676 with a modified I2SRC would not match. */
2678 if (flag_expensive_optimizations)
2680 /* Pass pc_rtx so no substitutions are done, just
2684 subst_low_luid = DF_INSN_LUID (i1);
2685 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2689 subst_low_luid = DF_INSN_LUID (i2);
2690 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2694 n_occurrences = 0; /* `subst' counts here */
2696 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2697 need to make a unique copy of I2SRC each time we substitute it
2698 to avoid self-referential rtl. */
2700 subst_low_luid = DF_INSN_LUID (i2);
2701 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2702 ! i1_feeds_i3 && i1dest_in_i1src);
2705 /* Record whether i2's body now appears within i3's body. */
2706 i2_is_used = n_occurrences;
2709 /* If we already got a failure, don't try to do more. Otherwise,
2710 try to substitute in I1 if we have it. */
2712 if (i1 && GET_CODE (newpat) != CLOBBER)
2714 /* Before we can do this substitution, we must redo the test done
2715 above (see detailed comments there) that ensures that I1DEST
2716 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2718 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2726 subst_low_luid = DF_INSN_LUID (i1);
2727 newpat = subst (newpat, i1dest, i1src, 0, 0);
2731 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2732 to count all the ways that I2SRC and I1SRC can be used. */
2733 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2734 && i2_is_used + added_sets_2 > 1)
2735 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2736 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2738 /* Fail if we tried to make a new register. */
2739 || max_reg_num () != maxreg
2740 /* Fail if we couldn't do something and have a CLOBBER. */
2741 || GET_CODE (newpat) == CLOBBER
2742 /* Fail if this new pattern is a MULT and we didn't have one before
2743 at the outer level. */
2744 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2751 /* If the actions of the earlier insns must be kept
2752 in addition to substituting them into the latest one,
2753 we must make a new PARALLEL for the latest insn
2754 to hold additional the SETs. */
2756 if (added_sets_1 || added_sets_2)
2760 if (GET_CODE (newpat) == PARALLEL)
2762 rtvec old = XVEC (newpat, 0);
2763 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2764 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2765 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2766 sizeof (old->elem[0]) * old->num_elem);
2771 total_sets = 1 + added_sets_1 + added_sets_2;
2772 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2773 XVECEXP (newpat, 0, 0) = old;
2777 XVECEXP (newpat, 0, --total_sets) = i1pat;
2781 /* If there is no I1, use I2's body as is. We used to also not do
2782 the subst call below if I2 was substituted into I3,
2783 but that could lose a simplification. */
2785 XVECEXP (newpat, 0, --total_sets) = i2pat;
2787 /* See comment where i2pat is assigned. */
2788 XVECEXP (newpat, 0, --total_sets)
2789 = subst (i2pat, i1dest, i1src, 0, 0);
2793 /* We come here when we are replacing a destination in I2 with the
2794 destination of I3. */
2795 validate_replacement:
2797 /* Note which hard regs this insn has as inputs. */
2798 mark_used_regs_combine (newpat);
2800 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2801 consider splitting this pattern, we might need these clobbers. */
2802 if (i1 && GET_CODE (newpat) == PARALLEL
2803 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2805 int len = XVECLEN (newpat, 0);
2807 newpat_vec_with_clobbers = rtvec_alloc (len);
2808 for (i = 0; i < len; i++)
2809 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2812 /* Is the result of combination a valid instruction? */
2813 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2815 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2816 the second SET's destination is a register that is unused and isn't
2817 marked as an instruction that might trap in an EH region. In that case,
2818 we just need the first SET. This can occur when simplifying a divmod
2819 insn. We *must* test for this case here because the code below that
2820 splits two independent SETs doesn't handle this case correctly when it
2821 updates the register status.
2823 It's pointless doing this if we originally had two sets, one from
2824 i3, and one from i2. Combining then splitting the parallel results
2825 in the original i2 again plus an invalid insn (which we delete).
2826 The net effect is only to move instructions around, which makes
2827 debug info less accurate.
2829 Also check the case where the first SET's destination is unused.
2830 That would not cause incorrect code, but does cause an unneeded
2833 if (insn_code_number < 0
2834 && !(added_sets_2 && i1 == 0)
2835 && GET_CODE (newpat) == PARALLEL
2836 && XVECLEN (newpat, 0) == 2
2837 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2838 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2839 && asm_noperands (newpat) < 0)
2841 rtx set0 = XVECEXP (newpat, 0, 0);
2842 rtx set1 = XVECEXP (newpat, 0, 1);
2845 if (((REG_P (SET_DEST (set1))
2846 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2847 || (GET_CODE (SET_DEST (set1)) == SUBREG
2848 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2849 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2850 || INTVAL (XEXP (note, 0)) <= 0)
2851 && ! side_effects_p (SET_SRC (set1)))
2854 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2857 else if (((REG_P (SET_DEST (set0))
2858 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2859 || (GET_CODE (SET_DEST (set0)) == SUBREG
2860 && find_reg_note (i3, REG_UNUSED,
2861 SUBREG_REG (SET_DEST (set0)))))
2862 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2863 || INTVAL (XEXP (note, 0)) <= 0)
2864 && ! side_effects_p (SET_SRC (set0)))
2867 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2869 if (insn_code_number >= 0)
2871 /* If we will be able to accept this, we have made a
2872 change to the destination of I3. This requires us to
2873 do a few adjustments. */
2875 PATTERN (i3) = newpat;
2876 adjust_for_new_dest (i3);
2881 /* If we were combining three insns and the result is a simple SET
2882 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2883 insns. There are two ways to do this. It can be split using a
2884 machine-specific method (like when you have an addition of a large
2885 constant) or by combine in the function find_split_point. */
2887 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2888 && asm_noperands (newpat) < 0)
2890 rtx parallel, m_split, *split;
2892 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2893 use I2DEST as a scratch register will help. In the latter case,
2894 convert I2DEST to the mode of the source of NEWPAT if we can. */
2896 m_split = combine_split_insns (newpat, i3);
2898 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2899 inputs of NEWPAT. */
2901 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2902 possible to try that as a scratch reg. This would require adding
2903 more code to make it work though. */
2905 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2907 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2909 /* First try to split using the original register as a
2910 scratch register. */
2911 parallel = gen_rtx_PARALLEL (VOIDmode,
2912 gen_rtvec (2, newpat,
2913 gen_rtx_CLOBBER (VOIDmode,
2915 m_split = combine_split_insns (parallel, i3);
2917 /* If that didn't work, try changing the mode of I2DEST if
2920 && new_mode != GET_MODE (i2dest)
2921 && new_mode != VOIDmode
2922 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2924 enum machine_mode old_mode = GET_MODE (i2dest);
2927 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2928 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2931 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2932 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2935 parallel = (gen_rtx_PARALLEL
2937 gen_rtvec (2, newpat,
2938 gen_rtx_CLOBBER (VOIDmode,
2940 m_split = combine_split_insns (parallel, i3);
2943 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2947 PUT_MODE (regno_reg_rtx[REGNO (i2dest)], old_mode);
2948 buf = undobuf.undos;
2949 undobuf.undos = buf->next;
2950 buf->next = undobuf.frees;
2951 undobuf.frees = buf;
2956 /* If recog_for_combine has discarded clobbers, try to use them
2957 again for the split. */
2958 if (m_split == 0 && newpat_vec_with_clobbers)
2960 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
2961 m_split = combine_split_insns (parallel, i3);
2964 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2966 m_split = PATTERN (m_split);
2967 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2968 if (insn_code_number >= 0)
2971 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2972 && (next_real_insn (i2) == i3
2973 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
2976 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2977 newi2pat = PATTERN (m_split);
2979 i3set = single_set (NEXT_INSN (m_split));
2980 i2set = single_set (m_split);
2982 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2984 /* If I2 or I3 has multiple SETs, we won't know how to track
2985 register status, so don't use these insns. If I2's destination
2986 is used between I2 and I3, we also can't use these insns. */
2988 if (i2_code_number >= 0 && i2set && i3set
2989 && (next_real_insn (i2) == i3
2990 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2991 insn_code_number = recog_for_combine (&newi3pat, i3,
2993 if (insn_code_number >= 0)
2996 /* It is possible that both insns now set the destination of I3.
2997 If so, we must show an extra use of it. */
2999 if (insn_code_number >= 0)
3001 rtx new_i3_dest = SET_DEST (i3set);
3002 rtx new_i2_dest = SET_DEST (i2set);
3004 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3005 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3006 || GET_CODE (new_i3_dest) == SUBREG)
3007 new_i3_dest = XEXP (new_i3_dest, 0);
3009 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3010 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3011 || GET_CODE (new_i2_dest) == SUBREG)
3012 new_i2_dest = XEXP (new_i2_dest, 0);
3014 if (REG_P (new_i3_dest)
3015 && REG_P (new_i2_dest)
3016 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3017 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3021 /* If we can split it and use I2DEST, go ahead and see if that
3022 helps things be recognized. Verify that none of the registers
3023 are set between I2 and I3. */
3024 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3028 /* We need I2DEST in the proper mode. If it is a hard register
3029 or the only use of a pseudo, we can change its mode.
3030 Make sure we don't change a hard register to have a mode that
3031 isn't valid for it, or change the number of registers. */
3032 && (GET_MODE (*split) == GET_MODE (i2dest)
3033 || GET_MODE (*split) == VOIDmode
3034 || can_change_dest_mode (i2dest, added_sets_2,
3036 && (next_real_insn (i2) == i3
3037 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3038 /* We can't overwrite I2DEST if its value is still used by
3040 && ! reg_referenced_p (i2dest, newpat))
3042 rtx newdest = i2dest;
3043 enum rtx_code split_code = GET_CODE (*split);
3044 enum machine_mode split_mode = GET_MODE (*split);
3045 bool subst_done = false;
3046 newi2pat = NULL_RTX;
3048 /* Get NEWDEST as a register in the proper mode. We have already
3049 validated that we can do this. */
3050 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3052 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3053 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3056 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3057 newdest = regno_reg_rtx[REGNO (i2dest)];
3061 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3062 an ASHIFT. This can occur if it was inside a PLUS and hence
3063 appeared to be a memory address. This is a kludge. */
3064 if (split_code == MULT
3065 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3066 && INTVAL (XEXP (*split, 1)) > 0
3067 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3069 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3070 XEXP (*split, 0), GEN_INT (i)));
3071 /* Update split_code because we may not have a multiply
3073 split_code = GET_CODE (*split);
3076 #ifdef INSN_SCHEDULING
3077 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3078 be written as a ZERO_EXTEND. */
3079 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3081 #ifdef LOAD_EXTEND_OP
3082 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3083 what it really is. */
3084 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3086 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3087 SUBREG_REG (*split)));
3090 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3091 SUBREG_REG (*split)));
3095 /* Attempt to split binary operators using arithmetic identities. */
3096 if (BINARY_P (SET_SRC (newpat))
3097 && split_mode == GET_MODE (SET_SRC (newpat))
3098 && ! side_effects_p (SET_SRC (newpat)))
3100 rtx setsrc = SET_SRC (newpat);
3101 enum machine_mode mode = GET_MODE (setsrc);
3102 enum rtx_code code = GET_CODE (setsrc);
3103 rtx src_op0 = XEXP (setsrc, 0);
3104 rtx src_op1 = XEXP (setsrc, 1);
3106 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3107 if (rtx_equal_p (src_op0, src_op1))
3109 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3110 SUBST (XEXP (setsrc, 0), newdest);
3111 SUBST (XEXP (setsrc, 1), newdest);
3114 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3115 else if ((code == PLUS || code == MULT)
3116 && GET_CODE (src_op0) == code
3117 && GET_CODE (XEXP (src_op0, 0)) == code
3118 && (INTEGRAL_MODE_P (mode)
3119 || (FLOAT_MODE_P (mode)
3120 && flag_unsafe_math_optimizations)))
3122 rtx p = XEXP (XEXP (src_op0, 0), 0);
3123 rtx q = XEXP (XEXP (src_op0, 0), 1);
3124 rtx r = XEXP (src_op0, 1);
3127 /* Split both "((X op Y) op X) op Y" and
3128 "((X op Y) op Y) op X" as "T op T" where T is
3130 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3131 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3133 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3135 SUBST (XEXP (setsrc, 0), newdest);
3136 SUBST (XEXP (setsrc, 1), newdest);
3139 /* Split "((X op X) op Y) op Y)" as "T op T" where
3141 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3143 rtx tmp = simplify_gen_binary (code, mode, p, r);
3144 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3145 SUBST (XEXP (setsrc, 0), newdest);
3146 SUBST (XEXP (setsrc, 1), newdest);
3154 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3155 SUBST (*split, newdest);
3158 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3160 /* recog_for_combine might have added CLOBBERs to newi2pat.
3161 Make sure NEWPAT does not depend on the clobbered regs. */
3162 if (GET_CODE (newi2pat) == PARALLEL)
3163 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3164 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3166 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3167 if (reg_overlap_mentioned_p (reg, newpat))
3174 /* If the split point was a MULT and we didn't have one before,
3175 don't use one now. */
3176 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3177 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3181 /* Check for a case where we loaded from memory in a narrow mode and
3182 then sign extended it, but we need both registers. In that case,
3183 we have a PARALLEL with both loads from the same memory location.
3184 We can split this into a load from memory followed by a register-register
3185 copy. This saves at least one insn, more if register allocation can
3188 We cannot do this if the destination of the first assignment is a
3189 condition code register or cc0. We eliminate this case by making sure
3190 the SET_DEST and SET_SRC have the same mode.
3192 We cannot do this if the destination of the second assignment is
3193 a register that we have already assumed is zero-extended. Similarly
3194 for a SUBREG of such a register. */
3196 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3197 && GET_CODE (newpat) == PARALLEL
3198 && XVECLEN (newpat, 0) == 2
3199 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3200 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3201 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3202 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3203 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3204 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3205 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3206 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3208 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3209 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3210 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3212 && VEC_index (reg_stat_type, reg_stat,
3213 REGNO (temp))->nonzero_bits != 0
3214 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3215 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3216 && (VEC_index (reg_stat_type, reg_stat,
3217 REGNO (temp))->nonzero_bits
3218 != GET_MODE_MASK (word_mode))))
3219 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3220 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3222 && VEC_index (reg_stat_type, reg_stat,
3223 REGNO (temp))->nonzero_bits != 0
3224 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3225 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3226 && (VEC_index (reg_stat_type, reg_stat,
3227 REGNO (temp))->nonzero_bits
3228 != GET_MODE_MASK (word_mode)))))
3229 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3230 SET_SRC (XVECEXP (newpat, 0, 1)))
3231 && ! find_reg_note (i3, REG_UNUSED,
3232 SET_DEST (XVECEXP (newpat, 0, 0))))
3236 newi2pat = XVECEXP (newpat, 0, 0);
3237 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3238 newpat = XVECEXP (newpat, 0, 1);
3239 SUBST (SET_SRC (newpat),
3240 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3241 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3243 if (i2_code_number >= 0)
3244 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3246 if (insn_code_number >= 0)
3250 /* Similarly, check for a case where we have a PARALLEL of two independent
3251 SETs but we started with three insns. In this case, we can do the sets
3252 as two separate insns. This case occurs when some SET allows two
3253 other insns to combine, but the destination of that SET is still live. */
3255 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3256 && GET_CODE (newpat) == PARALLEL
3257 && XVECLEN (newpat, 0) == 2
3258 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3259 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3260 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3261 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3262 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3263 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3264 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3266 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3267 XVECEXP (newpat, 0, 0))
3268 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3269 XVECEXP (newpat, 0, 1))
3270 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3271 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3273 /* We cannot split the parallel into two sets if both sets
3275 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3276 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3280 /* Normally, it doesn't matter which of the two is done first,
3281 but it does if one references cc0. In that case, it has to
3284 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3286 newi2pat = XVECEXP (newpat, 0, 0);
3287 newpat = XVECEXP (newpat, 0, 1);
3292 newi2pat = XVECEXP (newpat, 0, 1);
3293 newpat = XVECEXP (newpat, 0, 0);
3296 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3298 if (i2_code_number >= 0)
3299 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3302 /* If it still isn't recognized, fail and change things back the way they
3304 if ((insn_code_number < 0
3305 /* Is the result a reasonable ASM_OPERANDS? */
3306 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3312 /* If we had to change another insn, make sure it is valid also. */
3313 if (undobuf.other_insn)
3315 CLEAR_HARD_REG_SET (newpat_used_regs);
3317 other_pat = PATTERN (undobuf.other_insn);
3318 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3321 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3329 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3330 they are adjacent to each other or not. */
3332 rtx p = prev_nonnote_insn (i3);
3333 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3334 && sets_cc0_p (newi2pat))
3342 /* Only allow this combination if insn_rtx_costs reports that the
3343 replacement instructions are cheaper than the originals. */
3344 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3350 /* We now know that we can do this combination. Merge the insns and
3351 update the status of registers and LOG_LINKS. */
3353 if (undobuf.other_insn)
3357 PATTERN (undobuf.other_insn) = other_pat;
3359 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3360 are still valid. Then add any non-duplicate notes added by
3361 recog_for_combine. */
3362 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3364 next = XEXP (note, 1);
3366 if (REG_NOTE_KIND (note) == REG_UNUSED
3367 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3368 remove_note (undobuf.other_insn, note);
3371 distribute_notes (new_other_notes, undobuf.other_insn,
3372 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3381 /* I3 now uses what used to be its destination and which is now
3382 I2's destination. This requires us to do a few adjustments. */
3383 PATTERN (i3) = newpat;
3384 adjust_for_new_dest (i3);
3386 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3389 However, some later insn might be using I2's dest and have
3390 a LOG_LINK pointing at I3. We must remove this link.
3391 The simplest way to remove the link is to point it at I1,
3392 which we know will be a NOTE. */
3394 /* newi2pat is usually a SET here; however, recog_for_combine might
3395 have added some clobbers. */
3396 if (GET_CODE (newi2pat) == PARALLEL)
3397 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3399 ni2dest = SET_DEST (newi2pat);
3401 for (insn = NEXT_INSN (i3);
3402 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3403 || insn != BB_HEAD (this_basic_block->next_bb));
3404 insn = NEXT_INSN (insn))
3406 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3408 for (link = LOG_LINKS (insn); link;
3409 link = XEXP (link, 1))
3410 if (XEXP (link, 0) == i3)
3411 XEXP (link, 0) = i1;
3419 rtx i3notes, i2notes, i1notes = 0;
3420 rtx i3links, i2links, i1links = 0;
3423 /* Compute which registers we expect to eliminate. newi2pat may be setting
3424 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3425 same as i3dest, in which case newi2pat may be setting i1dest. */
3426 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3427 || i2dest_in_i2src || i2dest_in_i1src
3430 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3431 || (newi2pat && reg_set_p (i1dest, newi2pat))
3435 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3437 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3438 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3440 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3442 /* Ensure that we do not have something that should not be shared but
3443 occurs multiple times in the new insns. Check this by first
3444 resetting all the `used' flags and then copying anything is shared. */
3446 reset_used_flags (i3notes);
3447 reset_used_flags (i2notes);
3448 reset_used_flags (i1notes);
3449 reset_used_flags (newpat);
3450 reset_used_flags (newi2pat);
3451 if (undobuf.other_insn)
3452 reset_used_flags (PATTERN (undobuf.other_insn));
3454 i3notes = copy_rtx_if_shared (i3notes);
3455 i2notes = copy_rtx_if_shared (i2notes);
3456 i1notes = copy_rtx_if_shared (i1notes);
3457 newpat = copy_rtx_if_shared (newpat);
3458 newi2pat = copy_rtx_if_shared (newi2pat);
3459 if (undobuf.other_insn)
3460 reset_used_flags (PATTERN (undobuf.other_insn));
3462 INSN_CODE (i3) = insn_code_number;
3463 PATTERN (i3) = newpat;
3465 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3467 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3469 reset_used_flags (call_usage);
3470 call_usage = copy_rtx (call_usage);
3473 replace_rtx (call_usage, i2dest, i2src);
3476 replace_rtx (call_usage, i1dest, i1src);
3478 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3481 if (undobuf.other_insn)
3482 INSN_CODE (undobuf.other_insn) = other_code_number;
3484 /* We had one special case above where I2 had more than one set and
3485 we replaced a destination of one of those sets with the destination
3486 of I3. In that case, we have to update LOG_LINKS of insns later
3487 in this basic block. Note that this (expensive) case is rare.
3489 Also, in this case, we must pretend that all REG_NOTEs for I2
3490 actually came from I3, so that REG_UNUSED notes from I2 will be
3491 properly handled. */
3493 if (i3_subst_into_i2)
3495 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3496 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3497 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3498 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3499 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3500 && ! find_reg_note (i2, REG_UNUSED,
3501 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3502 for (temp = NEXT_INSN (i2);
3503 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3504 || BB_HEAD (this_basic_block) != temp);
3505 temp = NEXT_INSN (temp))
3506 if (temp != i3 && INSN_P (temp))
3507 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3508 if (XEXP (link, 0) == i2)
3509 XEXP (link, 0) = i3;
3514 while (XEXP (link, 1))
3515 link = XEXP (link, 1);
3516 XEXP (link, 1) = i2notes;
3530 INSN_CODE (i2) = i2_code_number;
3531 PATTERN (i2) = newi2pat;
3534 SET_INSN_DELETED (i2);
3540 SET_INSN_DELETED (i1);
3543 /* Get death notes for everything that is now used in either I3 or
3544 I2 and used to die in a previous insn. If we built two new
3545 patterns, move from I1 to I2 then I2 to I3 so that we get the
3546 proper movement on registers that I2 modifies. */
3550 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3551 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3554 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3557 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3559 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3562 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3565 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3568 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3571 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3572 know these are REG_UNUSED and want them to go to the desired insn,
3573 so we always pass it as i3. */
3575 if (newi2pat && new_i2_notes)
3576 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3579 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3581 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3582 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3583 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3584 in that case, it might delete I2. Similarly for I2 and I1.
3585 Show an additional death due to the REG_DEAD note we make here. If
3586 we discard it in distribute_notes, we will decrement it again. */
3590 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3591 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3593 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3595 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3597 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3601 if (i2dest_in_i2src)
3603 if (newi2pat && reg_set_p (i2dest, newi2pat))
3604 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3605 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3607 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3608 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3609 NULL_RTX, NULL_RTX);
3612 if (i1dest_in_i1src)
3614 if (newi2pat && reg_set_p (i1dest, newi2pat))
3615 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3616 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3618 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3619 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3620 NULL_RTX, NULL_RTX);
3623 distribute_links (i3links);
3624 distribute_links (i2links);
3625 distribute_links (i1links);
3630 rtx i2_insn = 0, i2_val = 0, set;
3632 /* The insn that used to set this register doesn't exist, and
3633 this life of the register may not exist either. See if one of
3634 I3's links points to an insn that sets I2DEST. If it does,
3635 that is now the last known value for I2DEST. If we don't update
3636 this and I2 set the register to a value that depended on its old
3637 contents, we will get confused. If this insn is used, thing
3638 will be set correctly in combine_instructions. */
3640 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3641 if ((set = single_set (XEXP (link, 0))) != 0
3642 && rtx_equal_p (i2dest, SET_DEST (set)))
3643 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3645 record_value_for_reg (i2dest, i2_insn, i2_val);
3647 /* If the reg formerly set in I2 died only once and that was in I3,
3648 zero its use count so it won't make `reload' do any work. */
3650 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3651 && ! i2dest_in_i2src)
3653 regno = REGNO (i2dest);
3654 INC_REG_N_SETS (regno, -1);
3658 if (i1 && REG_P (i1dest))
3661 rtx i1_insn = 0, i1_val = 0, set;
3663 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3664 if ((set = single_set (XEXP (link, 0))) != 0
3665 && rtx_equal_p (i1dest, SET_DEST (set)))
3666 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3668 record_value_for_reg (i1dest, i1_insn, i1_val);
3670 regno = REGNO (i1dest);
3671 if (! added_sets_1 && ! i1dest_in_i1src)
3672 INC_REG_N_SETS (regno, -1);
3675 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3676 been made to this insn. The order of
3677 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3678 can affect nonzero_bits of newpat */
3680 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3681 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3683 /* Set new_direct_jump_p if a new return or simple jump instruction
3686 If I3 is now an unconditional jump, ensure that it has a
3687 BARRIER following it since it may have initially been a
3688 conditional jump. It may also be the last nonnote insn. */
3690 if (returnjump_p (i3) || any_uncondjump_p (i3))
3692 *new_direct_jump_p = 1;
3693 mark_jump_label (PATTERN (i3), i3, 0);
3695 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3696 || !BARRIER_P (temp))
3697 emit_barrier_after (i3);
3700 if (undobuf.other_insn != NULL_RTX
3701 && (returnjump_p (undobuf.other_insn)
3702 || any_uncondjump_p (undobuf.other_insn)))
3704 *new_direct_jump_p = 1;
3706 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3707 || !BARRIER_P (temp))
3708 emit_barrier_after (undobuf.other_insn);
3711 /* An NOOP jump does not need barrier, but it does need cleaning up
3713 if (GET_CODE (newpat) == SET
3714 && SET_SRC (newpat) == pc_rtx
3715 && SET_DEST (newpat) == pc_rtx)
3716 *new_direct_jump_p = 1;
3719 if (undobuf.other_insn != NULL_RTX)
3723 fprintf (dump_file, "modifying other_insn ");
3724 dump_insn_slim (dump_file, undobuf.other_insn);
3726 df_insn_rescan (undobuf.other_insn);
3729 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3733 fprintf (dump_file, "modifying insn i1 ");
3734 dump_insn_slim (dump_file, i1);
3736 df_insn_rescan (i1);
3739 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3743 fprintf (dump_file, "modifying insn i2 ");
3744 dump_insn_slim (dump_file, i2);
3746 df_insn_rescan (i2);
3749 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3753 fprintf (dump_file, "modifying insn i3 ");
3754 dump_insn_slim (dump_file, i3);
3756 df_insn_rescan (i3);
3759 combine_successes++;
3762 if (added_links_insn
3763 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3764 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3765 return added_links_insn;
3767 return newi2pat ? i2 : i3;
3770 /* Undo all the modifications recorded in undobuf. */
3775 struct undo *undo, *next;
3777 for (undo = undobuf.undos; undo; undo = next)
3783 *undo->where.r = undo->old_contents.r;
3786 *undo->where.i = undo->old_contents.i;
3789 PUT_MODE (*undo->where.r, undo->old_contents.m);
3795 undo->next = undobuf.frees;
3796 undobuf.frees = undo;
3802 /* We've committed to accepting the changes we made. Move all
3803 of the undos to the free list. */
3808 struct undo *undo, *next;
3810 for (undo = undobuf.undos; undo; undo = next)
3813 undo->next = undobuf.frees;
3814 undobuf.frees = undo;
3819 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3820 where we have an arithmetic expression and return that point. LOC will
3823 try_combine will call this function to see if an insn can be split into
3827 find_split_point (rtx *loc, rtx insn)
3830 enum rtx_code code = GET_CODE (x);
3832 unsigned HOST_WIDE_INT len = 0;
3833 HOST_WIDE_INT pos = 0;
3835 rtx inner = NULL_RTX;
3837 /* First special-case some codes. */
3841 #ifdef INSN_SCHEDULING
3842 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3844 if (MEM_P (SUBREG_REG (x)))
3847 return find_split_point (&SUBREG_REG (x), insn);
3851 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3852 using LO_SUM and HIGH. */
3853 if (GET_CODE (XEXP (x, 0)) == CONST
3854 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3857 gen_rtx_LO_SUM (Pmode,
3858 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3860 return &XEXP (XEXP (x, 0), 0);
3864 /* If we have a PLUS whose second operand is a constant and the
3865 address is not valid, perhaps will can split it up using
3866 the machine-specific way to split large constants. We use
3867 the first pseudo-reg (one of the virtual regs) as a placeholder;
3868 it will not remain in the result. */
3869 if (GET_CODE (XEXP (x, 0)) == PLUS
3870 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3871 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3873 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3874 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3878 /* This should have produced two insns, each of which sets our
3879 placeholder. If the source of the second is a valid address,
3880 we can make put both sources together and make a split point
3884 && NEXT_INSN (seq) != NULL_RTX
3885 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3886 && NONJUMP_INSN_P (seq)
3887 && GET_CODE (PATTERN (seq)) == SET
3888 && SET_DEST (PATTERN (seq)) == reg
3889 && ! reg_mentioned_p (reg,
3890 SET_SRC (PATTERN (seq)))
3891 && NONJUMP_INSN_P (NEXT_INSN (seq))
3892 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3893 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3894 && memory_address_p (GET_MODE (x),
3895 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3897 rtx src1 = SET_SRC (PATTERN (seq));
3898 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3900 /* Replace the placeholder in SRC2 with SRC1. If we can
3901 find where in SRC2 it was placed, that can become our
3902 split point and we can replace this address with SRC2.
3903 Just try two obvious places. */
3905 src2 = replace_rtx (src2, reg, src1);
3907 if (XEXP (src2, 0) == src1)
3908 split = &XEXP (src2, 0);
3909 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3910 && XEXP (XEXP (src2, 0), 0) == src1)
3911 split = &XEXP (XEXP (src2, 0), 0);
3915 SUBST (XEXP (x, 0), src2);
3920 /* If that didn't work, perhaps the first operand is complex and
3921 needs to be computed separately, so make a split point there.
3922 This will occur on machines that just support REG + CONST
3923 and have a constant moved through some previous computation. */
3925 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3926 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3927 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3928 return &XEXP (XEXP (x, 0), 0);
3934 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3935 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3936 we need to put the operand into a register. So split at that
3939 if (SET_DEST (x) == cc0_rtx
3940 && GET_CODE (SET_SRC (x)) != COMPARE
3941 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3942 && !OBJECT_P (SET_SRC (x))
3943 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3944 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3945 return &SET_SRC (x);
3948 /* See if we can split SET_SRC as it stands. */
3949 split = find_split_point (&SET_SRC (x), insn);
3950 if (split && split != &SET_SRC (x))
3953 /* See if we can split SET_DEST as it stands. */
3954 split = find_split_point (&SET_DEST (x), insn);
3955 if (split && split != &SET_DEST (x))
3958 /* See if this is a bitfield assignment with everything constant. If
3959 so, this is an IOR of an AND, so split it into that. */
3960 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3961 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3962 <= HOST_BITS_PER_WIDE_INT)
3963 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3964 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3965 && GET_CODE (SET_SRC (x)) == CONST_INT
3966 && ((INTVAL (XEXP (SET_DEST (x), 1))
3967 + INTVAL (XEXP (SET_DEST (x), 2)))
3968 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3969 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3971 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3972 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3973 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3974 rtx dest = XEXP (SET_DEST (x), 0);
3975 enum machine_mode mode = GET_MODE (dest);
3976 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3979 if (BITS_BIG_ENDIAN)
3980 pos = GET_MODE_BITSIZE (mode) - len - pos;
3982 or_mask = gen_int_mode (src << pos, mode);
3985 simplify_gen_binary (IOR, mode, dest, or_mask));
3988 rtx negmask = gen_int_mode (~(mask << pos), mode);
3990 simplify_gen_binary (IOR, mode,
3991 simplify_gen_binary (AND, mode,
3996 SUBST (SET_DEST (x), dest);
3998 split = find_split_point (&SET_SRC (x), insn);
3999 if (split && split != &SET_SRC (x))
4003 /* Otherwise, see if this is an operation that we can split into two.
4004 If so, try to split that. */
4005 code = GET_CODE (SET_SRC (x));
4010 /* If we are AND'ing with a large constant that is only a single
4011 bit and the result is only being used in a context where we
4012 need to know if it is zero or nonzero, replace it with a bit
4013 extraction. This will avoid the large constant, which might
4014 have taken more than one insn to make. If the constant were
4015 not a valid argument to the AND but took only one insn to make,
4016 this is no worse, but if it took more than one insn, it will
4019 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4020 && REG_P (XEXP (SET_SRC (x), 0))
4021 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4022 && REG_P (SET_DEST (x))
4023 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4024 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4025 && XEXP (*split, 0) == SET_DEST (x)
4026 && XEXP (*split, 1) == const0_rtx)
4028 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4029 XEXP (SET_SRC (x), 0),
4030 pos, NULL_RTX, 1, 1, 0, 0);
4031 if (extraction != 0)
4033 SUBST (SET_SRC (x), extraction);
4034 return find_split_point (loc, insn);
4040 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4041 is known to be on, this can be converted into a NEG of a shift. */
4042 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4043 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4044 && 1 <= (pos = exact_log2
4045 (nonzero_bits (XEXP (SET_SRC (x), 0),
4046 GET_MODE (XEXP (SET_SRC (x), 0))))))
4048 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4052 gen_rtx_LSHIFTRT (mode,
4053 XEXP (SET_SRC (x), 0),
4056 split = find_split_point (&SET_SRC (x), insn);
4057 if (split && split != &SET_SRC (x))
4063 inner = XEXP (SET_SRC (x), 0);
4065 /* We can't optimize if either mode is a partial integer
4066 mode as we don't know how many bits are significant
4068 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4069 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4073 len = GET_MODE_BITSIZE (GET_MODE (inner));
4079 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4080 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4082 inner = XEXP (SET_SRC (x), 0);
4083 len = INTVAL (XEXP (SET_SRC (x), 1));
4084 pos = INTVAL (XEXP (SET_SRC (x), 2));
4086 if (BITS_BIG_ENDIAN)
4087 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4088 unsignedp = (code == ZERO_EXTRACT);
4096 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4098 enum machine_mode mode = GET_MODE (SET_SRC (x));
4100 /* For unsigned, we have a choice of a shift followed by an
4101 AND or two shifts. Use two shifts for field sizes where the
4102 constant might be too large. We assume here that we can
4103 always at least get 8-bit constants in an AND insn, which is
4104 true for every current RISC. */
4106 if (unsignedp && len <= 8)
4111 (mode, gen_lowpart (mode, inner),
4113 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4115 split = find_split_point (&SET_SRC (x), insn);
4116 if (split && split != &SET_SRC (x))
4123 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4124 gen_rtx_ASHIFT (mode,
4125 gen_lowpart (mode, inner),
4126 GEN_INT (GET_MODE_BITSIZE (mode)
4128 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4130 split = find_split_point (&SET_SRC (x), insn);
4131 if (split && split != &SET_SRC (x))
4136 /* See if this is a simple operation with a constant as the second
4137 operand. It might be that this constant is out of range and hence
4138 could be used as a split point. */
4139 if (BINARY_P (SET_SRC (x))
4140 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4141 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4142 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4143 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4144 return &XEXP (SET_SRC (x), 1);
4146 /* Finally, see if this is a simple operation with its first operand
4147 not in a register. The operation might require this operand in a
4148 register, so return it as a split point. We can always do this
4149 because if the first operand were another operation, we would have
4150 already found it as a split point. */
4151 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4152 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4153 return &XEXP (SET_SRC (x), 0);
4159 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4160 it is better to write this as (not (ior A B)) so we can split it.
4161 Similarly for IOR. */
4162 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4165 gen_rtx_NOT (GET_MODE (x),
4166 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4168 XEXP (XEXP (x, 0), 0),
4169 XEXP (XEXP (x, 1), 0))));
4170 return find_split_point (loc, insn);
4173 /* Many RISC machines have a large set of logical insns. If the
4174 second operand is a NOT, put it first so we will try to split the
4175 other operand first. */
4176 if (GET_CODE (XEXP (x, 1)) == NOT)
4178 rtx tem = XEXP (x, 0);
4179 SUBST (XEXP (x, 0), XEXP (x, 1));
4180 SUBST (XEXP (x, 1), tem);
4188 /* Otherwise, select our actions depending on our rtx class. */
4189 switch (GET_RTX_CLASS (code))
4191 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4193 split = find_split_point (&XEXP (x, 2), insn);
4196 /* ... fall through ... */
4198 case RTX_COMM_ARITH:
4200 case RTX_COMM_COMPARE:
4201 split = find_split_point (&XEXP (x, 1), insn);
4204 /* ... fall through ... */
4206 /* Some machines have (and (shift ...) ...) insns. If X is not
4207 an AND, but XEXP (X, 0) is, use it as our split point. */
4208 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4209 return &XEXP (x, 0);
4211 split = find_split_point (&XEXP (x, 0), insn);
4217 /* Otherwise, we don't have a split point. */
4222 /* Throughout X, replace FROM with TO, and return the result.
4223 The result is TO if X is FROM;
4224 otherwise the result is X, but its contents may have been modified.
4225 If they were modified, a record was made in undobuf so that
4226 undo_all will (among other things) return X to its original state.
4228 If the number of changes necessary is too much to record to undo,
4229 the excess changes are not made, so the result is invalid.
4230 The changes already made can still be undone.
4231 undobuf.num_undo is incremented for such changes, so by testing that
4232 the caller can tell whether the result is valid.
4234 `n_occurrences' is incremented each time FROM is replaced.
4236 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4238 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4239 by copying if `n_occurrences' is nonzero. */
4242 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4244 enum rtx_code code = GET_CODE (x);
4245 enum machine_mode op0_mode = VOIDmode;
4250 /* Two expressions are equal if they are identical copies of a shared
4251 RTX or if they are both registers with the same register number
4254 #define COMBINE_RTX_EQUAL_P(X,Y) \
4256 || (REG_P (X) && REG_P (Y) \
4257 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4259 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4262 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4265 /* If X and FROM are the same register but different modes, they
4266 will not have been seen as equal above. However, the log links code
4267 will make a LOG_LINKS entry for that case. If we do nothing, we
4268 will try to rerecognize our original insn and, when it succeeds,
4269 we will delete the feeding insn, which is incorrect.
4271 So force this insn not to match in this (rare) case. */
4272 if (! in_dest && code == REG && REG_P (from)
4273 && reg_overlap_mentioned_p (x, from))
4274 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4276 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4277 of which may contain things that can be combined. */
4278 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4281 /* It is possible to have a subexpression appear twice in the insn.
4282 Suppose that FROM is a register that appears within TO.
4283 Then, after that subexpression has been scanned once by `subst',
4284 the second time it is scanned, TO may be found. If we were
4285 to scan TO here, we would find FROM within it and create a
4286 self-referent rtl structure which is completely wrong. */
4287 if (COMBINE_RTX_EQUAL_P (x, to))
4290 /* Parallel asm_operands need special attention because all of the
4291 inputs are shared across the arms. Furthermore, unsharing the
4292 rtl results in recognition failures. Failure to handle this case
4293 specially can result in circular rtl.
4295 Solve this by doing a normal pass across the first entry of the
4296 parallel, and only processing the SET_DESTs of the subsequent
4299 if (code == PARALLEL
4300 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4301 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4303 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4305 /* If this substitution failed, this whole thing fails. */
4306 if (GET_CODE (new) == CLOBBER
4307 && XEXP (new, 0) == const0_rtx)
4310 SUBST (XVECEXP (x, 0, 0), new);
4312 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4314 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4317 && GET_CODE (dest) != CC0
4318 && GET_CODE (dest) != PC)
4320 new = subst (dest, from, to, 0, unique_copy);
4322 /* If this substitution failed, this whole thing fails. */
4323 if (GET_CODE (new) == CLOBBER
4324 && XEXP (new, 0) == const0_rtx)
4327 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
4333 len = GET_RTX_LENGTH (code);
4334 fmt = GET_RTX_FORMAT (code);
4336 /* We don't need to process a SET_DEST that is a register, CC0,
4337 or PC, so set up to skip this common case. All other cases
4338 where we want to suppress replacing something inside a
4339 SET_SRC are handled via the IN_DEST operand. */
4341 && (REG_P (SET_DEST (x))
4342 || GET_CODE (SET_DEST (x)) == CC0
4343 || GET_CODE (SET_DEST (x)) == PC))
4346 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4349 op0_mode = GET_MODE (XEXP (x, 0));
4351 for (i = 0; i < len; i++)
4356 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4358 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4360 new = (unique_copy && n_occurrences
4361 ? copy_rtx (to) : to);
4366 new = subst (XVECEXP (x, i, j), from, to, 0,
4369 /* If this substitution failed, this whole thing
4371 if (GET_CODE (new) == CLOBBER
4372 && XEXP (new, 0) == const0_rtx)
4376 SUBST (XVECEXP (x, i, j), new);
4379 else if (fmt[i] == 'e')
4381 /* If this is a register being set, ignore it. */
4385 && (((code == SUBREG || code == ZERO_EXTRACT)
4387 || code == STRICT_LOW_PART))
4390 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4392 /* In general, don't install a subreg involving two
4393 modes not tieable. It can worsen register
4394 allocation, and can even make invalid reload
4395 insns, since the reg inside may need to be copied
4396 from in the outside mode, and that may be invalid
4397 if it is an fp reg copied in integer mode.
4399 We allow two exceptions to this: It is valid if
4400 it is inside another SUBREG and the mode of that
4401 SUBREG and the mode of the inside of TO is
4402 tieable and it is valid if X is a SET that copies
4405 if (GET_CODE (to) == SUBREG
4406 && ! MODES_TIEABLE_P (GET_MODE (to),
4407 GET_MODE (SUBREG_REG (to)))
4408 && ! (code == SUBREG
4409 && MODES_TIEABLE_P (GET_MODE (x),
4410 GET_MODE (SUBREG_REG (to))))
4412 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4415 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4417 #ifdef CANNOT_CHANGE_MODE_CLASS
4420 && REGNO (to) < FIRST_PSEUDO_REGISTER
4421 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4424 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4427 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4431 /* If we are in a SET_DEST, suppress most cases unless we
4432 have gone inside a MEM, in which case we want to
4433 simplify the address. We assume here that things that
4434 are actually part of the destination have their inner
4435 parts in the first expression. This is true for SUBREG,
4436 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4437 things aside from REG and MEM that should appear in a
4439 new = subst (XEXP (x, i), from, to,
4441 && (code == SUBREG || code == STRICT_LOW_PART
4442 || code == ZERO_EXTRACT))
4444 && i == 0), unique_copy);
4446 /* If we found that we will have to reject this combination,
4447 indicate that by returning the CLOBBER ourselves, rather than
4448 an expression containing it. This will speed things up as
4449 well as prevent accidents where two CLOBBERs are considered
4450 to be equal, thus producing an incorrect simplification. */
4452 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
4455 if (GET_CODE (x) == SUBREG
4456 && (GET_CODE (new) == CONST_INT
4457 || GET_CODE (new) == CONST_DOUBLE))
4459 enum machine_mode mode = GET_MODE (x);
4461 x = simplify_subreg (GET_MODE (x), new,
4462 GET_MODE (SUBREG_REG (x)),
4465 x = gen_rtx_CLOBBER (mode, const0_rtx);
4467 else if (GET_CODE (new) == CONST_INT
4468 && GET_CODE (x) == ZERO_EXTEND)
4470 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4471 new, GET_MODE (XEXP (x, 0)));
4475 SUBST (XEXP (x, i), new);
4480 /* Try to simplify X. If the simplification changed the code, it is likely
4481 that further simplification will help, so loop, but limit the number
4482 of repetitions that will be performed. */
4484 for (i = 0; i < 4; i++)
4486 /* If X is sufficiently simple, don't bother trying to do anything
4488 if (code != CONST_INT && code != REG && code != CLOBBER)
4489 x = combine_simplify_rtx (x, op0_mode, in_dest);
4491 if (GET_CODE (x) == code)
4494 code = GET_CODE (x);
4496 /* We no longer know the original mode of operand 0 since we
4497 have changed the form of X) */
4498 op0_mode = VOIDmode;
4504 /* Simplify X, a piece of RTL. We just operate on the expression at the
4505 outer level; call `subst' to simplify recursively. Return the new
4508 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4509 if we are inside a SET_DEST. */
4512 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4514 enum rtx_code code = GET_CODE (x);
4515 enum machine_mode mode = GET_MODE (x);
4519 /* If this is a commutative operation, put a constant last and a complex
4520 expression first. We don't need to do this for comparisons here. */
4521 if (COMMUTATIVE_ARITH_P (x)
4522 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4525 SUBST (XEXP (x, 0), XEXP (x, 1));
4526 SUBST (XEXP (x, 1), temp);
4529 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4530 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4531 things. Check for cases where both arms are testing the same
4534 Don't do anything if all operands are very simple. */
4537 && ((!OBJECT_P (XEXP (x, 0))
4538 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4539 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4540 || (!OBJECT_P (XEXP (x, 1))
4541 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4542 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4544 && (!OBJECT_P (XEXP (x, 0))
4545 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4546 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4548 rtx cond, true_rtx, false_rtx;
4550 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4552 /* If everything is a comparison, what we have is highly unlikely
4553 to be simpler, so don't use it. */
4554 && ! (COMPARISON_P (x)
4555 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4557 rtx cop1 = const0_rtx;
4558 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4560 if (cond_code == NE && COMPARISON_P (cond))
4563 /* Simplify the alternative arms; this may collapse the true and
4564 false arms to store-flag values. Be careful to use copy_rtx
4565 here since true_rtx or false_rtx might share RTL with x as a
4566 result of the if_then_else_cond call above. */
4567 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4568 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4570 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4571 is unlikely to be simpler. */
4572 if (general_operand (true_rtx, VOIDmode)
4573 && general_operand (false_rtx, VOIDmode))
4575 enum rtx_code reversed;
4577 /* Restarting if we generate a store-flag expression will cause
4578 us to loop. Just drop through in this case. */
4580 /* If the result values are STORE_FLAG_VALUE and zero, we can
4581 just make the comparison operation. */
4582 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4583 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4585 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4586 && ((reversed = reversed_comparison_code_parts
4587 (cond_code, cond, cop1, NULL))
4589 x = simplify_gen_relational (reversed, mode, VOIDmode,
4592 /* Likewise, we can make the negate of a comparison operation
4593 if the result values are - STORE_FLAG_VALUE and zero. */
4594 else if (GET_CODE (true_rtx) == CONST_INT
4595 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4596 && false_rtx == const0_rtx)
4597 x = simplify_gen_unary (NEG, mode,
4598 simplify_gen_relational (cond_code,
4602 else if (GET_CODE (false_rtx) == CONST_INT
4603 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4604 && true_rtx == const0_rtx
4605 && ((reversed = reversed_comparison_code_parts
4606 (cond_code, cond, cop1, NULL))
4608 x = simplify_gen_unary (NEG, mode,
4609 simplify_gen_relational (reversed,
4614 return gen_rtx_IF_THEN_ELSE (mode,
4615 simplify_gen_relational (cond_code,
4620 true_rtx, false_rtx);
4622 code = GET_CODE (x);
4623 op0_mode = VOIDmode;
4628 /* Try to fold this expression in case we have constants that weren't
4631 switch (GET_RTX_CLASS (code))
4634 if (op0_mode == VOIDmode)
4635 op0_mode = GET_MODE (XEXP (x, 0));
4636 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4639 case RTX_COMM_COMPARE:
4641 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4642 if (cmp_mode == VOIDmode)
4644 cmp_mode = GET_MODE (XEXP (x, 1));
4645 if (cmp_mode == VOIDmode)
4646 cmp_mode = op0_mode;
4648 temp = simplify_relational_operation (code, mode, cmp_mode,
4649 XEXP (x, 0), XEXP (x, 1));
4652 case RTX_COMM_ARITH:
4654 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4656 case RTX_BITFIELD_OPS:
4658 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4659 XEXP (x, 1), XEXP (x, 2));
4668 code = GET_CODE (temp);
4669 op0_mode = VOIDmode;
4670 mode = GET_MODE (temp);
4673 /* First see if we can apply the inverse distributive law. */
4674 if (code == PLUS || code == MINUS
4675 || code == AND || code == IOR || code == XOR)
4677 x = apply_distributive_law (x);
4678 code = GET_CODE (x);
4679 op0_mode = VOIDmode;
4682 /* If CODE is an associative operation not otherwise handled, see if we
4683 can associate some operands. This can win if they are constants or
4684 if they are logically related (i.e. (a & b) & a). */
4685 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4686 || code == AND || code == IOR || code == XOR
4687 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4688 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4689 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4691 if (GET_CODE (XEXP (x, 0)) == code)
4693 rtx other = XEXP (XEXP (x, 0), 0);
4694 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4695 rtx inner_op1 = XEXP (x, 1);
4698 /* Make sure we pass the constant operand if any as the second
4699 one if this is a commutative operation. */
4700 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4702 rtx tem = inner_op0;
4703 inner_op0 = inner_op1;
4706 inner = simplify_binary_operation (code == MINUS ? PLUS
4707 : code == DIV ? MULT
4709 mode, inner_op0, inner_op1);
4711 /* For commutative operations, try the other pair if that one
4713 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4715 other = XEXP (XEXP (x, 0), 1);
4716 inner = simplify_binary_operation (code, mode,
4717 XEXP (XEXP (x, 0), 0),
4722 return simplify_gen_binary (code, mode, other, inner);
4726 /* A little bit of algebraic simplification here. */
4730 /* Ensure that our address has any ASHIFTs converted to MULT in case
4731 address-recognizing predicates are called later. */
4732 temp = make_compound_operation (XEXP (x, 0), MEM);
4733 SUBST (XEXP (x, 0), temp);
4737 if (op0_mode == VOIDmode)
4738 op0_mode = GET_MODE (SUBREG_REG (x));
4740 /* See if this can be moved to simplify_subreg. */
4741 if (CONSTANT_P (SUBREG_REG (x))
4742 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4743 /* Don't call gen_lowpart if the inner mode
4744 is VOIDmode and we cannot simplify it, as SUBREG without
4745 inner mode is invalid. */
4746 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4747 || gen_lowpart_common (mode, SUBREG_REG (x))))
4748 return gen_lowpart (mode, SUBREG_REG (x));
4750 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4754 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4760 /* Don't change the mode of the MEM if that would change the meaning
4762 if (MEM_P (SUBREG_REG (x))
4763 && (MEM_VOLATILE_P (SUBREG_REG (x))
4764 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4765 return gen_rtx_CLOBBER (mode, const0_rtx);
4767 /* Note that we cannot do any narrowing for non-constants since
4768 we might have been counting on using the fact that some bits were
4769 zero. We now do this in the SET. */
4774 temp = expand_compound_operation (XEXP (x, 0));
4776 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4777 replaced by (lshiftrt X C). This will convert
4778 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4780 if (GET_CODE (temp) == ASHIFTRT
4781 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4782 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4783 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4784 INTVAL (XEXP (temp, 1)));
4786 /* If X has only a single bit that might be nonzero, say, bit I, convert
4787 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4788 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4789 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4790 or a SUBREG of one since we'd be making the expression more
4791 complex if it was just a register. */
4794 && ! (GET_CODE (temp) == SUBREG
4795 && REG_P (SUBREG_REG (temp)))
4796 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4798 rtx temp1 = simplify_shift_const
4799 (NULL_RTX, ASHIFTRT, mode,
4800 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4801 GET_MODE_BITSIZE (mode) - 1 - i),
4802 GET_MODE_BITSIZE (mode) - 1 - i);
4804 /* If all we did was surround TEMP with the two shifts, we
4805 haven't improved anything, so don't use it. Otherwise,
4806 we are better off with TEMP1. */
4807 if (GET_CODE (temp1) != ASHIFTRT
4808 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4809 || XEXP (XEXP (temp1, 0), 0) != temp)
4815 /* We can't handle truncation to a partial integer mode here
4816 because we don't know the real bitsize of the partial
4818 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4821 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4822 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4823 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4825 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4826 GET_MODE_MASK (mode), 0));
4828 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4829 whose value is a comparison can be replaced with a subreg if
4830 STORE_FLAG_VALUE permits. */
4831 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4832 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4833 && (temp = get_last_value (XEXP (x, 0)))
4834 && COMPARISON_P (temp))
4835 return gen_lowpart (mode, XEXP (x, 0));
4840 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4841 using cc0, in which case we want to leave it as a COMPARE
4842 so we can distinguish it from a register-register-copy. */
4843 if (XEXP (x, 1) == const0_rtx)
4846 /* x - 0 is the same as x unless x's mode has signed zeros and
4847 allows rounding towards -infinity. Under those conditions,
4849 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4850 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4851 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4857 /* (const (const X)) can become (const X). Do it this way rather than
4858 returning the inner CONST since CONST can be shared with a
4860 if (GET_CODE (XEXP (x, 0)) == CONST)
4861 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4866 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4867 can add in an offset. find_split_point will split this address up
4868 again if it doesn't match. */
4869 if (GET_CODE (XEXP (x, 0)) == HIGH
4870 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4876 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4877 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4878 bit-field and can be replaced by either a sign_extend or a
4879 sign_extract. The `and' may be a zero_extend and the two
4880 <c>, -<c> constants may be reversed. */
4881 if (GET_CODE (XEXP (x, 0)) == XOR
4882 && GET_CODE (XEXP (x, 1)) == CONST_INT
4883 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4884 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4885 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4886 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4887 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4888 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4889 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4890 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4891 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4892 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4893 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4894 == (unsigned int) i + 1))))
4895 return simplify_shift_const
4896 (NULL_RTX, ASHIFTRT, mode,
4897 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4898 XEXP (XEXP (XEXP (x, 0), 0), 0),
4899 GET_MODE_BITSIZE (mode) - (i + 1)),
4900 GET_MODE_BITSIZE (mode) - (i + 1));
4902 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4903 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4904 the bitsize of the mode - 1. This allows simplification of
4905 "a = (b & 8) == 0;" */
4906 if (XEXP (x, 1) == constm1_rtx
4907 && !REG_P (XEXP (x, 0))
4908 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4909 && REG_P (SUBREG_REG (XEXP (x, 0))))
4910 && nonzero_bits (XEXP (x, 0), mode) == 1)
4911 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4912 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4913 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4914 GET_MODE_BITSIZE (mode) - 1),
4915 GET_MODE_BITSIZE (mode) - 1);
4917 /* If we are adding two things that have no bits in common, convert
4918 the addition into an IOR. This will often be further simplified,
4919 for example in cases like ((a & 1) + (a & 2)), which can
4922 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4923 && (nonzero_bits (XEXP (x, 0), mode)
4924 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4926 /* Try to simplify the expression further. */
4927 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4928 temp = combine_simplify_rtx (tor, mode, in_dest);
4930 /* If we could, great. If not, do not go ahead with the IOR
4931 replacement, since PLUS appears in many special purpose
4932 address arithmetic instructions. */
4933 if (GET_CODE (temp) != CLOBBER && temp != tor)
4939 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4940 (and <foo> (const_int pow2-1)) */
4941 if (GET_CODE (XEXP (x, 1)) == AND
4942 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4943 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4944 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4945 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4946 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4950 /* If we have (mult (plus A B) C), apply the distributive law and then
4951 the inverse distributive law to see if things simplify. This
4952 occurs mostly in addresses, often when unrolling loops. */
4954 if (GET_CODE (XEXP (x, 0)) == PLUS)
4956 rtx result = distribute_and_simplify_rtx (x, 0);
4961 /* Try simplify a*(b/c) as (a*b)/c. */
4962 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4963 && GET_CODE (XEXP (x, 0)) == DIV)
4965 rtx tem = simplify_binary_operation (MULT, mode,
4966 XEXP (XEXP (x, 0), 0),
4969 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4974 /* If this is a divide by a power of two, treat it as a shift if
4975 its first operand is a shift. */
4976 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4977 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4978 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4979 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4980 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4981 || GET_CODE (XEXP (x, 0)) == ROTATE
4982 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4983 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4987 case GT: case GTU: case GE: case GEU:
4988 case LT: case LTU: case LE: case LEU:
4989 case UNEQ: case LTGT:
4990 case UNGT: case UNGE:
4991 case UNLT: case UNLE:
4992 case UNORDERED: case ORDERED:
4993 /* If the first operand is a condition code, we can't do anything
4995 if (GET_CODE (XEXP (x, 0)) == COMPARE
4996 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4997 && ! CC0_P (XEXP (x, 0))))
4999 rtx op0 = XEXP (x, 0);
5000 rtx op1 = XEXP (x, 1);
5001 enum rtx_code new_code;
5003 if (GET_CODE (op0) == COMPARE)
5004 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5006 /* Simplify our comparison, if possible. */
5007 new_code = simplify_comparison (code, &op0, &op1);
5009 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5010 if only the low-order bit is possibly nonzero in X (such as when
5011 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5012 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5013 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5016 Remove any ZERO_EXTRACT we made when thinking this was a
5017 comparison. It may now be simpler to use, e.g., an AND. If a
5018 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5019 the call to make_compound_operation in the SET case. */
5021 if (STORE_FLAG_VALUE == 1
5022 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5023 && op1 == const0_rtx
5024 && mode == GET_MODE (op0)
5025 && nonzero_bits (op0, mode) == 1)
5026 return gen_lowpart (mode,
5027 expand_compound_operation (op0));
5029 else if (STORE_FLAG_VALUE == 1
5030 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5031 && op1 == const0_rtx
5032 && mode == GET_MODE (op0)
5033 && (num_sign_bit_copies (op0, mode)
5034 == GET_MODE_BITSIZE (mode)))
5036 op0 = expand_compound_operation (op0);
5037 return simplify_gen_unary (NEG, mode,
5038 gen_lowpart (mode, op0),
5042 else if (STORE_FLAG_VALUE == 1
5043 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5044 && op1 == const0_rtx
5045 && mode == GET_MODE (op0)
5046 && nonzero_bits (op0, mode) == 1)
5048 op0 = expand_compound_operation (op0);
5049 return simplify_gen_binary (XOR, mode,
5050 gen_lowpart (mode, op0),
5054 else if (STORE_FLAG_VALUE == 1
5055 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5056 && op1 == const0_rtx
5057 && mode == GET_MODE (op0)
5058 && (num_sign_bit_copies (op0, mode)
5059 == GET_MODE_BITSIZE (mode)))
5061 op0 = expand_compound_operation (op0);
5062 return plus_constant (gen_lowpart (mode, op0), 1);
5065 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5067 if (STORE_FLAG_VALUE == -1
5068 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5069 && op1 == const0_rtx
5070 && (num_sign_bit_copies (op0, mode)
5071 == GET_MODE_BITSIZE (mode)))
5072 return gen_lowpart (mode,
5073 expand_compound_operation (op0));
5075 else if (STORE_FLAG_VALUE == -1
5076 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5077 && op1 == const0_rtx
5078 && mode == GET_MODE (op0)
5079 && nonzero_bits (op0, mode) == 1)
5081 op0 = expand_compound_operation (op0);
5082 return simplify_gen_unary (NEG, mode,
5083 gen_lowpart (mode, op0),
5087 else if (STORE_FLAG_VALUE == -1
5088 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5089 && op1 == const0_rtx
5090 && mode == GET_MODE (op0)
5091 && (num_sign_bit_copies (op0, mode)
5092 == GET_MODE_BITSIZE (mode)))
5094 op0 = expand_compound_operation (op0);
5095 return simplify_gen_unary (NOT, mode,
5096 gen_lowpart (mode, op0),
5100 /* If X is 0/1, (eq X 0) is X-1. */
5101 else if (STORE_FLAG_VALUE == -1
5102 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5103 && op1 == const0_rtx
5104 && mode == GET_MODE (op0)
5105 && nonzero_bits (op0, mode) == 1)
5107 op0 = expand_compound_operation (op0);
5108 return plus_constant (gen_lowpart (mode, op0), -1);
5111 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5112 one bit that might be nonzero, we can convert (ne x 0) to
5113 (ashift x c) where C puts the bit in the sign bit. Remove any
5114 AND with STORE_FLAG_VALUE when we are done, since we are only
5115 going to test the sign bit. */
5116 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5117 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5118 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5119 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5120 && op1 == const0_rtx
5121 && mode == GET_MODE (op0)
5122 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5124 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5125 expand_compound_operation (op0),
5126 GET_MODE_BITSIZE (mode) - 1 - i);
5127 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5133 /* If the code changed, return a whole new comparison. */
5134 if (new_code != code)
5135 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5137 /* Otherwise, keep this operation, but maybe change its operands.
5138 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5139 SUBST (XEXP (x, 0), op0);
5140 SUBST (XEXP (x, 1), op1);
5145 return simplify_if_then_else (x);
5151 /* If we are processing SET_DEST, we are done. */
5155 return expand_compound_operation (x);
5158 return simplify_set (x);
5162 return simplify_logical (x);
5169 /* If this is a shift by a constant amount, simplify it. */
5170 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5171 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5172 INTVAL (XEXP (x, 1)));
5174 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5176 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5178 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5190 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5193 simplify_if_then_else (rtx x)
5195 enum machine_mode mode = GET_MODE (x);
5196 rtx cond = XEXP (x, 0);
5197 rtx true_rtx = XEXP (x, 1);
5198 rtx false_rtx = XEXP (x, 2);
5199 enum rtx_code true_code = GET_CODE (cond);
5200 int comparison_p = COMPARISON_P (cond);
5203 enum rtx_code false_code;
5206 /* Simplify storing of the truth value. */
5207 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5208 return simplify_gen_relational (true_code, mode, VOIDmode,
5209 XEXP (cond, 0), XEXP (cond, 1));
5211 /* Also when the truth value has to be reversed. */
5213 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5214 && (reversed = reversed_comparison (cond, mode)))
5217 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5218 in it is being compared against certain values. Get the true and false
5219 comparisons and see if that says anything about the value of each arm. */
5222 && ((false_code = reversed_comparison_code (cond, NULL))
5224 && REG_P (XEXP (cond, 0)))
5227 rtx from = XEXP (cond, 0);
5228 rtx true_val = XEXP (cond, 1);
5229 rtx false_val = true_val;
5232 /* If FALSE_CODE is EQ, swap the codes and arms. */
5234 if (false_code == EQ)
5236 swapped = 1, true_code = EQ, false_code = NE;
5237 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5240 /* If we are comparing against zero and the expression being tested has
5241 only a single bit that might be nonzero, that is its value when it is
5242 not equal to zero. Similarly if it is known to be -1 or 0. */
5244 if (true_code == EQ && true_val == const0_rtx
5245 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5248 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5250 else if (true_code == EQ && true_val == const0_rtx
5251 && (num_sign_bit_copies (from, GET_MODE (from))
5252 == GET_MODE_BITSIZE (GET_MODE (from))))
5255 false_val = constm1_rtx;
5258 /* Now simplify an arm if we know the value of the register in the
5259 branch and it is used in the arm. Be careful due to the potential
5260 of locally-shared RTL. */
5262 if (reg_mentioned_p (from, true_rtx))
5263 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5265 pc_rtx, pc_rtx, 0, 0);
5266 if (reg_mentioned_p (from, false_rtx))
5267 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5269 pc_rtx, pc_rtx, 0, 0);
5271 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5272 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5274 true_rtx = XEXP (x, 1);
5275 false_rtx = XEXP (x, 2);
5276 true_code = GET_CODE (cond);
5279 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5280 reversed, do so to avoid needing two sets of patterns for
5281 subtract-and-branch insns. Similarly if we have a constant in the true
5282 arm, the false arm is the same as the first operand of the comparison, or
5283 the false arm is more complicated than the true arm. */
5286 && reversed_comparison_code (cond, NULL) != UNKNOWN
5287 && (true_rtx == pc_rtx
5288 || (CONSTANT_P (true_rtx)
5289 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5290 || true_rtx == const0_rtx
5291 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5292 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5293 && !OBJECT_P (false_rtx))
5294 || reg_mentioned_p (true_rtx, false_rtx)
5295 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5297 true_code = reversed_comparison_code (cond, NULL);
5298 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5299 SUBST (XEXP (x, 1), false_rtx);
5300 SUBST (XEXP (x, 2), true_rtx);
5302 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5305 /* It is possible that the conditional has been simplified out. */
5306 true_code = GET_CODE (cond);
5307 comparison_p = COMPARISON_P (cond);
5310 /* If the two arms are identical, we don't need the comparison. */
5312 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5315 /* Convert a == b ? b : a to "a". */
5316 if (true_code == EQ && ! side_effects_p (cond)
5317 && !HONOR_NANS (mode)
5318 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5319 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5321 else if (true_code == NE && ! side_effects_p (cond)
5322 && !HONOR_NANS (mode)
5323 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5324 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5327 /* Look for cases where we have (abs x) or (neg (abs X)). */
5329 if (GET_MODE_CLASS (mode) == MODE_INT
5330 && GET_CODE (false_rtx) == NEG
5331 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5333 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5334 && ! side_effects_p (true_rtx))
5339 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5343 simplify_gen_unary (NEG, mode,
5344 simplify_gen_unary (ABS, mode, true_rtx, mode),
5350 /* Look for MIN or MAX. */
5352 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5354 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5355 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5356 && ! side_effects_p (cond))
5361 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5364 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5367 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5370 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5375 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5376 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5377 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5378 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5379 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5380 neither 1 or -1, but it isn't worth checking for. */
5382 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5384 && GET_MODE_CLASS (mode) == MODE_INT
5385 && ! side_effects_p (x))
5387 rtx t = make_compound_operation (true_rtx, SET);
5388 rtx f = make_compound_operation (false_rtx, SET);
5389 rtx cond_op0 = XEXP (cond, 0);
5390 rtx cond_op1 = XEXP (cond, 1);
5391 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5392 enum machine_mode m = mode;
5393 rtx z = 0, c1 = NULL_RTX;
5395 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5396 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5397 || GET_CODE (t) == ASHIFT
5398 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5399 && rtx_equal_p (XEXP (t, 0), f))
5400 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5402 /* If an identity-zero op is commutative, check whether there
5403 would be a match if we swapped the operands. */
5404 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5405 || GET_CODE (t) == XOR)
5406 && rtx_equal_p (XEXP (t, 1), f))
5407 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5408 else if (GET_CODE (t) == SIGN_EXTEND
5409 && (GET_CODE (XEXP (t, 0)) == PLUS
5410 || GET_CODE (XEXP (t, 0)) == MINUS
5411 || GET_CODE (XEXP (t, 0)) == IOR
5412 || GET_CODE (XEXP (t, 0)) == XOR
5413 || GET_CODE (XEXP (t, 0)) == ASHIFT
5414 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5415 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5416 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5417 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5418 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5419 && (num_sign_bit_copies (f, GET_MODE (f))
5421 (GET_MODE_BITSIZE (mode)
5422 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5424 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5425 extend_op = SIGN_EXTEND;
5426 m = GET_MODE (XEXP (t, 0));
5428 else if (GET_CODE (t) == SIGN_EXTEND
5429 && (GET_CODE (XEXP (t, 0)) == PLUS
5430 || GET_CODE (XEXP (t, 0)) == IOR
5431 || GET_CODE (XEXP (t, 0)) == XOR)
5432 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5433 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5434 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5435 && (num_sign_bit_copies (f, GET_MODE (f))
5437 (GET_MODE_BITSIZE (mode)
5438 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5440 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5441 extend_op = SIGN_EXTEND;
5442 m = GET_MODE (XEXP (t, 0));
5444 else if (GET_CODE (t) == ZERO_EXTEND
5445 && (GET_CODE (XEXP (t, 0)) == PLUS
5446 || GET_CODE (XEXP (t, 0)) == MINUS
5447 || GET_CODE (XEXP (t, 0)) == IOR
5448 || GET_CODE (XEXP (t, 0)) == XOR
5449 || GET_CODE (XEXP (t, 0)) == ASHIFT
5450 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5451 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5452 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5453 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5454 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5455 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5456 && ((nonzero_bits (f, GET_MODE (f))
5457 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5460 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5461 extend_op = ZERO_EXTEND;
5462 m = GET_MODE (XEXP (t, 0));
5464 else if (GET_CODE (t) == ZERO_EXTEND
5465 && (GET_CODE (XEXP (t, 0)) == PLUS
5466 || GET_CODE (XEXP (t, 0)) == IOR
5467 || GET_CODE (XEXP (t, 0)) == XOR)
5468 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5469 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5470 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5471 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5472 && ((nonzero_bits (f, GET_MODE (f))
5473 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5476 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5477 extend_op = ZERO_EXTEND;
5478 m = GET_MODE (XEXP (t, 0));
5483 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5484 cond_op0, cond_op1),
5485 pc_rtx, pc_rtx, 0, 0);
5486 temp = simplify_gen_binary (MULT, m, temp,
5487 simplify_gen_binary (MULT, m, c1,
5489 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5490 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5492 if (extend_op != UNKNOWN)
5493 temp = simplify_gen_unary (extend_op, mode, temp, m);
5499 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5500 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5501 negation of a single bit, we can convert this operation to a shift. We
5502 can actually do this more generally, but it doesn't seem worth it. */
5504 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5505 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5506 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5507 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5508 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5509 == GET_MODE_BITSIZE (mode))
5510 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5512 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5513 gen_lowpart (mode, XEXP (cond, 0)), i);
5515 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5516 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5517 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5518 && GET_MODE (XEXP (cond, 0)) == mode
5519 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5520 == nonzero_bits (XEXP (cond, 0), mode)
5521 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5522 return XEXP (cond, 0);
5527 /* Simplify X, a SET expression. Return the new expression. */
5530 simplify_set (rtx x)
5532 rtx src = SET_SRC (x);
5533 rtx dest = SET_DEST (x);
5534 enum machine_mode mode
5535 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5539 /* (set (pc) (return)) gets written as (return). */
5540 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5543 /* Now that we know for sure which bits of SRC we are using, see if we can
5544 simplify the expression for the object knowing that we only need the
5547 if (GET_MODE_CLASS (mode) == MODE_INT
5548 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5550 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5551 SUBST (SET_SRC (x), src);
5554 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5555 the comparison result and try to simplify it unless we already have used
5556 undobuf.other_insn. */
5557 if ((GET_MODE_CLASS (mode) == MODE_CC
5558 || GET_CODE (src) == COMPARE
5560 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5561 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5562 && COMPARISON_P (*cc_use)
5563 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5565 enum rtx_code old_code = GET_CODE (*cc_use);
5566 enum rtx_code new_code;
5568 int other_changed = 0;
5569 enum machine_mode compare_mode = GET_MODE (dest);
5571 if (GET_CODE (src) == COMPARE)
5572 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5574 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5576 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5579 new_code = old_code;
5580 else if (!CONSTANT_P (tmp))
5582 new_code = GET_CODE (tmp);
5583 op0 = XEXP (tmp, 0);
5584 op1 = XEXP (tmp, 1);
5588 rtx pat = PATTERN (other_insn);
5589 undobuf.other_insn = other_insn;
5590 SUBST (*cc_use, tmp);
5592 /* Attempt to simplify CC user. */
5593 if (GET_CODE (pat) == SET)
5595 rtx new = simplify_rtx (SET_SRC (pat));
5596 if (new != NULL_RTX)
5597 SUBST (SET_SRC (pat), new);
5600 /* Convert X into a no-op move. */
5601 SUBST (SET_DEST (x), pc_rtx);
5602 SUBST (SET_SRC (x), pc_rtx);
5606 /* Simplify our comparison, if possible. */
5607 new_code = simplify_comparison (new_code, &op0, &op1);
5609 #ifdef SELECT_CC_MODE
5610 /* If this machine has CC modes other than CCmode, check to see if we
5611 need to use a different CC mode here. */
5612 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5613 compare_mode = GET_MODE (op0);
5615 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5618 /* If the mode changed, we have to change SET_DEST, the mode in the
5619 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5620 a hard register, just build new versions with the proper mode. If it
5621 is a pseudo, we lose unless it is only time we set the pseudo, in
5622 which case we can safely change its mode. */
5623 if (compare_mode != GET_MODE (dest))
5625 if (can_change_dest_mode (dest, 0, compare_mode))
5627 unsigned int regno = REGNO (dest);
5630 if (regno < FIRST_PSEUDO_REGISTER)
5631 new_dest = gen_rtx_REG (compare_mode, regno);
5634 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5635 new_dest = regno_reg_rtx[regno];
5638 SUBST (SET_DEST (x), new_dest);
5639 SUBST (XEXP (*cc_use, 0), new_dest);
5646 #endif /* SELECT_CC_MODE */
5648 /* If the code changed, we have to build a new comparison in
5649 undobuf.other_insn. */
5650 if (new_code != old_code)
5652 int other_changed_previously = other_changed;
5653 unsigned HOST_WIDE_INT mask;
5655 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5659 /* If the only change we made was to change an EQ into an NE or
5660 vice versa, OP0 has only one bit that might be nonzero, and OP1
5661 is zero, check if changing the user of the condition code will
5662 produce a valid insn. If it won't, we can keep the original code
5663 in that insn by surrounding our operation with an XOR. */
5665 if (((old_code == NE && new_code == EQ)
5666 || (old_code == EQ && new_code == NE))
5667 && ! other_changed_previously && op1 == const0_rtx
5668 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5669 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5671 rtx pat = PATTERN (other_insn), note = 0;
5673 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5674 && ! check_asm_operands (pat)))
5676 PUT_CODE (*cc_use, old_code);
5679 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5680 op0, GEN_INT (mask));
5686 undobuf.other_insn = other_insn;
5689 /* If we are now comparing against zero, change our source if
5690 needed. If we do not use cc0, we always have a COMPARE. */
5691 if (op1 == const0_rtx && dest == cc0_rtx)
5693 SUBST (SET_SRC (x), op0);
5699 /* Otherwise, if we didn't previously have a COMPARE in the
5700 correct mode, we need one. */
5701 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5703 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5706 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5708 SUBST (SET_SRC (x), op0);
5711 /* Otherwise, update the COMPARE if needed. */
5712 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5714 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5720 /* Get SET_SRC in a form where we have placed back any
5721 compound expressions. Then do the checks below. */
5722 src = make_compound_operation (src, SET);
5723 SUBST (SET_SRC (x), src);
5726 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5727 and X being a REG or (subreg (reg)), we may be able to convert this to
5728 (set (subreg:m2 x) (op)).
5730 We can always do this if M1 is narrower than M2 because that means that
5731 we only care about the low bits of the result.
5733 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5734 perform a narrower operation than requested since the high-order bits will
5735 be undefined. On machine where it is defined, this transformation is safe
5736 as long as M1 and M2 have the same number of words. */
5738 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5739 && !OBJECT_P (SUBREG_REG (src))
5740 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5742 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5743 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5744 #ifndef WORD_REGISTER_OPERATIONS
5745 && (GET_MODE_SIZE (GET_MODE (src))
5746 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5748 #ifdef CANNOT_CHANGE_MODE_CLASS
5749 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5750 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5751 GET_MODE (SUBREG_REG (src)),
5755 || (GET_CODE (dest) == SUBREG
5756 && REG_P (SUBREG_REG (dest)))))
5758 SUBST (SET_DEST (x),
5759 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5761 SUBST (SET_SRC (x), SUBREG_REG (src));
5763 src = SET_SRC (x), dest = SET_DEST (x);
5767 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5770 && GET_CODE (src) == SUBREG
5771 && subreg_lowpart_p (src)
5772 && (GET_MODE_BITSIZE (GET_MODE (src))
5773 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5775 rtx inner = SUBREG_REG (src);
5776 enum machine_mode inner_mode = GET_MODE (inner);
5778 /* Here we make sure that we don't have a sign bit on. */
5779 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5780 && (nonzero_bits (inner, inner_mode)
5781 < ((unsigned HOST_WIDE_INT) 1
5782 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5784 SUBST (SET_SRC (x), inner);
5790 #ifdef LOAD_EXTEND_OP
5791 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5792 would require a paradoxical subreg. Replace the subreg with a
5793 zero_extend to avoid the reload that would otherwise be required. */
5795 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5796 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5797 && SUBREG_BYTE (src) == 0
5798 && (GET_MODE_SIZE (GET_MODE (src))
5799 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5800 && MEM_P (SUBREG_REG (src)))
5803 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5804 GET_MODE (src), SUBREG_REG (src)));
5810 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5811 are comparing an item known to be 0 or -1 against 0, use a logical
5812 operation instead. Check for one of the arms being an IOR of the other
5813 arm with some value. We compute three terms to be IOR'ed together. In
5814 practice, at most two will be nonzero. Then we do the IOR's. */
5816 if (GET_CODE (dest) != PC
5817 && GET_CODE (src) == IF_THEN_ELSE
5818 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5819 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5820 && XEXP (XEXP (src, 0), 1) == const0_rtx
5821 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5822 #ifdef HAVE_conditional_move
5823 && ! can_conditionally_move_p (GET_MODE (src))
5825 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5826 GET_MODE (XEXP (XEXP (src, 0), 0)))
5827 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5828 && ! side_effects_p (src))
5830 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5831 ? XEXP (src, 1) : XEXP (src, 2));
5832 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5833 ? XEXP (src, 2) : XEXP (src, 1));
5834 rtx term1 = const0_rtx, term2, term3;
5836 if (GET_CODE (true_rtx) == IOR
5837 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5838 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5839 else if (GET_CODE (true_rtx) == IOR
5840 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5841 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5842 else if (GET_CODE (false_rtx) == IOR
5843 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5844 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5845 else if (GET_CODE (false_rtx) == IOR
5846 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5847 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5849 term2 = simplify_gen_binary (AND, GET_MODE (src),
5850 XEXP (XEXP (src, 0), 0), true_rtx);
5851 term3 = simplify_gen_binary (AND, GET_MODE (src),
5852 simplify_gen_unary (NOT, GET_MODE (src),
5853 XEXP (XEXP (src, 0), 0),
5858 simplify_gen_binary (IOR, GET_MODE (src),
5859 simplify_gen_binary (IOR, GET_MODE (src),
5866 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5867 whole thing fail. */
5868 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5870 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5873 /* Convert this into a field assignment operation, if possible. */
5874 return make_field_assignment (x);
5877 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5881 simplify_logical (rtx x)
5883 enum machine_mode mode = GET_MODE (x);
5884 rtx op0 = XEXP (x, 0);
5885 rtx op1 = XEXP (x, 1);
5887 switch (GET_CODE (x))
5890 /* We can call simplify_and_const_int only if we don't lose
5891 any (sign) bits when converting INTVAL (op1) to
5892 "unsigned HOST_WIDE_INT". */
5893 if (GET_CODE (op1) == CONST_INT
5894 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5895 || INTVAL (op1) > 0))
5897 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5898 if (GET_CODE (x) != AND)
5905 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5906 apply the distributive law and then the inverse distributive
5907 law to see if things simplify. */
5908 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5910 rtx result = distribute_and_simplify_rtx (x, 0);
5914 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5916 rtx result = distribute_and_simplify_rtx (x, 1);
5923 /* If we have (ior (and A B) C), apply the distributive law and then
5924 the inverse distributive law to see if things simplify. */
5926 if (GET_CODE (op0) == AND)
5928 rtx result = distribute_and_simplify_rtx (x, 0);
5933 if (GET_CODE (op1) == AND)
5935 rtx result = distribute_and_simplify_rtx (x, 1);
5948 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5949 operations" because they can be replaced with two more basic operations.
5950 ZERO_EXTEND is also considered "compound" because it can be replaced with
5951 an AND operation, which is simpler, though only one operation.
5953 The function expand_compound_operation is called with an rtx expression
5954 and will convert it to the appropriate shifts and AND operations,
5955 simplifying at each stage.
5957 The function make_compound_operation is called to convert an expression
5958 consisting of shifts and ANDs into the equivalent compound expression.
5959 It is the inverse of this function, loosely speaking. */
5962 expand_compound_operation (rtx x)
5964 unsigned HOST_WIDE_INT pos = 0, len;
5966 unsigned int modewidth;
5969 switch (GET_CODE (x))
5974 /* We can't necessarily use a const_int for a multiword mode;
5975 it depends on implicitly extending the value.
5976 Since we don't know the right way to extend it,
5977 we can't tell whether the implicit way is right.
5979 Even for a mode that is no wider than a const_int,
5980 we can't win, because we need to sign extend one of its bits through
5981 the rest of it, and we don't know which bit. */
5982 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5985 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5986 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5987 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5988 reloaded. If not for that, MEM's would very rarely be safe.
5990 Reject MODEs bigger than a word, because we might not be able
5991 to reference a two-register group starting with an arbitrary register
5992 (and currently gen_lowpart might crash for a SUBREG). */
5994 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5997 /* Reject MODEs that aren't scalar integers because turning vector
5998 or complex modes into shifts causes problems. */
6000 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6003 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6004 /* If the inner object has VOIDmode (the only way this can happen
6005 is if it is an ASM_OPERANDS), we can't do anything since we don't
6006 know how much masking to do. */
6015 /* ... fall through ... */
6018 /* If the operand is a CLOBBER, just return it. */
6019 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6022 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6023 || GET_CODE (XEXP (x, 2)) != CONST_INT
6024 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6027 /* Reject MODEs that aren't scalar integers because turning vector
6028 or complex modes into shifts causes problems. */
6030 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6033 len = INTVAL (XEXP (x, 1));
6034 pos = INTVAL (XEXP (x, 2));
6036 /* This should stay within the object being extracted, fail otherwise. */
6037 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6040 if (BITS_BIG_ENDIAN)
6041 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6048 /* Convert sign extension to zero extension, if we know that the high
6049 bit is not set, as this is easier to optimize. It will be converted
6050 back to cheaper alternative in make_extraction. */
6051 if (GET_CODE (x) == SIGN_EXTEND
6052 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6053 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6054 & ~(((unsigned HOST_WIDE_INT)
6055 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6059 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6060 rtx temp2 = expand_compound_operation (temp);
6062 /* Make sure this is a profitable operation. */
6063 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
6065 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
6071 /* We can optimize some special cases of ZERO_EXTEND. */
6072 if (GET_CODE (x) == ZERO_EXTEND)
6074 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6075 know that the last value didn't have any inappropriate bits
6077 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6078 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6079 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6080 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6081 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6082 return XEXP (XEXP (x, 0), 0);
6084 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6085 if (GET_CODE (XEXP (x, 0)) == SUBREG
6086 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6087 && subreg_lowpart_p (XEXP (x, 0))
6088 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6089 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6090 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6091 return SUBREG_REG (XEXP (x, 0));
6093 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6094 is a comparison and STORE_FLAG_VALUE permits. This is like
6095 the first case, but it works even when GET_MODE (x) is larger
6096 than HOST_WIDE_INT. */
6097 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6098 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6099 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6100 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6101 <= HOST_BITS_PER_WIDE_INT)
6102 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6103 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6104 return XEXP (XEXP (x, 0), 0);
6106 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6107 if (GET_CODE (XEXP (x, 0)) == SUBREG
6108 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6109 && subreg_lowpart_p (XEXP (x, 0))
6110 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6111 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6112 <= HOST_BITS_PER_WIDE_INT)
6113 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6114 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6115 return SUBREG_REG (XEXP (x, 0));
6119 /* If we reach here, we want to return a pair of shifts. The inner
6120 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6121 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6122 logical depending on the value of UNSIGNEDP.
6124 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6125 converted into an AND of a shift.
6127 We must check for the case where the left shift would have a negative
6128 count. This can happen in a case like (x >> 31) & 255 on machines
6129 that can't shift by a constant. On those machines, we would first
6130 combine the shift with the AND to produce a variable-position
6131 extraction. Then the constant of 31 would be substituted in to produce
6132 a such a position. */
6134 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6135 if (modewidth + len >= pos)
6137 enum machine_mode mode = GET_MODE (x);
6138 tem = gen_lowpart (mode, XEXP (x, 0));
6139 if (!tem || GET_CODE (tem) == CLOBBER)
6141 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6142 tem, modewidth - pos - len);
6143 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6144 mode, tem, modewidth - len);
6146 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6147 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6148 simplify_shift_const (NULL_RTX, LSHIFTRT,
6151 ((HOST_WIDE_INT) 1 << len) - 1);
6153 /* Any other cases we can't handle. */
6156 /* If we couldn't do this for some reason, return the original
6158 if (GET_CODE (tem) == CLOBBER)
6164 /* X is a SET which contains an assignment of one object into
6165 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6166 or certain SUBREGS). If possible, convert it into a series of
6169 We half-heartedly support variable positions, but do not at all
6170 support variable lengths. */
6173 expand_field_assignment (rtx x)
6176 rtx pos; /* Always counts from low bit. */
6178 rtx mask, cleared, masked;
6179 enum machine_mode compute_mode;
6181 /* Loop until we find something we can't simplify. */
6184 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6185 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6187 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6188 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6189 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6191 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6192 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6194 inner = XEXP (SET_DEST (x), 0);
6195 len = INTVAL (XEXP (SET_DEST (x), 1));
6196 pos = XEXP (SET_DEST (x), 2);
6198 /* A constant position should stay within the width of INNER. */
6199 if (GET_CODE (pos) == CONST_INT
6200 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6203 if (BITS_BIG_ENDIAN)
6205 if (GET_CODE (pos) == CONST_INT)
6206 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6208 else if (GET_CODE (pos) == MINUS
6209 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6210 && (INTVAL (XEXP (pos, 1))
6211 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6212 /* If position is ADJUST - X, new position is X. */
6213 pos = XEXP (pos, 0);
6215 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6216 GEN_INT (GET_MODE_BITSIZE (
6223 /* A SUBREG between two modes that occupy the same numbers of words
6224 can be done by moving the SUBREG to the source. */
6225 else if (GET_CODE (SET_DEST (x)) == SUBREG
6226 /* We need SUBREGs to compute nonzero_bits properly. */
6227 && nonzero_sign_valid
6228 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6229 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6230 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6231 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6233 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6235 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6242 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6243 inner = SUBREG_REG (inner);
6245 compute_mode = GET_MODE (inner);
6247 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6248 if (! SCALAR_INT_MODE_P (compute_mode))
6250 enum machine_mode imode;
6252 /* Don't do anything for vector or complex integral types. */
6253 if (! FLOAT_MODE_P (compute_mode))
6256 /* Try to find an integral mode to pun with. */
6257 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6258 if (imode == BLKmode)
6261 compute_mode = imode;
6262 inner = gen_lowpart (imode, inner);
6265 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6266 if (len >= HOST_BITS_PER_WIDE_INT)
6269 /* Now compute the equivalent expression. Make a copy of INNER
6270 for the SET_DEST in case it is a MEM into which we will substitute;
6271 we don't want shared RTL in that case. */
6272 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6273 cleared = simplify_gen_binary (AND, compute_mode,
6274 simplify_gen_unary (NOT, compute_mode,
6275 simplify_gen_binary (ASHIFT,
6280 masked = simplify_gen_binary (ASHIFT, compute_mode,
6281 simplify_gen_binary (
6283 gen_lowpart (compute_mode, SET_SRC (x)),
6287 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6288 simplify_gen_binary (IOR, compute_mode,
6295 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6296 it is an RTX that represents a variable starting position; otherwise,
6297 POS is the (constant) starting bit position (counted from the LSB).
6299 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6302 IN_DEST is nonzero if this is a reference in the destination of a
6303 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6304 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6307 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6308 ZERO_EXTRACT should be built even for bits starting at bit 0.
6310 MODE is the desired mode of the result (if IN_DEST == 0).
6312 The result is an RTX for the extraction or NULL_RTX if the target
6316 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6317 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6318 int in_dest, int in_compare)
6320 /* This mode describes the size of the storage area
6321 to fetch the overall value from. Within that, we
6322 ignore the POS lowest bits, etc. */
6323 enum machine_mode is_mode = GET_MODE (inner);
6324 enum machine_mode inner_mode;
6325 enum machine_mode wanted_inner_mode;
6326 enum machine_mode wanted_inner_reg_mode = word_mode;
6327 enum machine_mode pos_mode = word_mode;
6328 enum machine_mode extraction_mode = word_mode;
6329 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6331 rtx orig_pos_rtx = pos_rtx;
6332 HOST_WIDE_INT orig_pos;
6334 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6336 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6337 consider just the QI as the memory to extract from.
6338 The subreg adds or removes high bits; its mode is
6339 irrelevant to the meaning of this extraction,
6340 since POS and LEN count from the lsb. */
6341 if (MEM_P (SUBREG_REG (inner)))
6342 is_mode = GET_MODE (SUBREG_REG (inner));
6343 inner = SUBREG_REG (inner);
6345 else if (GET_CODE (inner) == ASHIFT
6346 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6347 && pos_rtx == 0 && pos == 0
6348 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6350 /* We're extracting the least significant bits of an rtx
6351 (ashift X (const_int C)), where LEN > C. Extract the
6352 least significant (LEN - C) bits of X, giving an rtx
6353 whose mode is MODE, then shift it left C times. */
6354 new = make_extraction (mode, XEXP (inner, 0),
6355 0, 0, len - INTVAL (XEXP (inner, 1)),
6356 unsignedp, in_dest, in_compare);
6358 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6361 inner_mode = GET_MODE (inner);
6363 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6364 pos = INTVAL (pos_rtx), pos_rtx = 0;
6366 /* See if this can be done without an extraction. We never can if the
6367 width of the field is not the same as that of some integer mode. For
6368 registers, we can only avoid the extraction if the position is at the
6369 low-order bit and this is either not in the destination or we have the
6370 appropriate STRICT_LOW_PART operation available.
6372 For MEM, we can avoid an extract if the field starts on an appropriate
6373 boundary and we can change the mode of the memory reference. */
6375 if (tmode != BLKmode
6376 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6378 && (inner_mode == tmode
6380 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6381 GET_MODE_BITSIZE (inner_mode))
6382 || reg_truncated_to_mode (tmode, inner))
6385 && have_insn_for (STRICT_LOW_PART, tmode))))
6386 || (MEM_P (inner) && pos_rtx == 0
6388 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6389 : BITS_PER_UNIT)) == 0
6390 /* We can't do this if we are widening INNER_MODE (it
6391 may not be aligned, for one thing). */
6392 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6393 && (inner_mode == tmode
6394 || (! mode_dependent_address_p (XEXP (inner, 0))
6395 && ! MEM_VOLATILE_P (inner))))))
6397 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6398 field. If the original and current mode are the same, we need not
6399 adjust the offset. Otherwise, we do if bytes big endian.
6401 If INNER is not a MEM, get a piece consisting of just the field
6402 of interest (in this case POS % BITS_PER_WORD must be 0). */
6406 HOST_WIDE_INT offset;
6408 /* POS counts from lsb, but make OFFSET count in memory order. */
6409 if (BYTES_BIG_ENDIAN)
6410 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6412 offset = pos / BITS_PER_UNIT;
6414 new = adjust_address_nv (inner, tmode, offset);
6416 else if (REG_P (inner))
6418 if (tmode != inner_mode)
6420 /* We can't call gen_lowpart in a DEST since we
6421 always want a SUBREG (see below) and it would sometimes
6422 return a new hard register. */
6425 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6427 if (WORDS_BIG_ENDIAN
6428 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6429 final_word = ((GET_MODE_SIZE (inner_mode)
6430 - GET_MODE_SIZE (tmode))
6431 / UNITS_PER_WORD) - final_word;
6433 final_word *= UNITS_PER_WORD;
6434 if (BYTES_BIG_ENDIAN &&
6435 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6436 final_word += (GET_MODE_SIZE (inner_mode)
6437 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6439 /* Avoid creating invalid subregs, for example when
6440 simplifying (x>>32)&255. */
6441 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6444 new = gen_rtx_SUBREG (tmode, inner, final_word);
6447 new = gen_lowpart (tmode, inner);
6453 new = force_to_mode (inner, tmode,
6454 len >= HOST_BITS_PER_WIDE_INT
6455 ? ~(unsigned HOST_WIDE_INT) 0
6456 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6459 /* If this extraction is going into the destination of a SET,
6460 make a STRICT_LOW_PART unless we made a MEM. */
6463 return (MEM_P (new) ? new
6464 : (GET_CODE (new) != SUBREG
6465 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6466 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6471 if (GET_CODE (new) == CONST_INT)
6472 return gen_int_mode (INTVAL (new), mode);
6474 /* If we know that no extraneous bits are set, and that the high
6475 bit is not set, convert the extraction to the cheaper of
6476 sign and zero extension, that are equivalent in these cases. */
6477 if (flag_expensive_optimizations
6478 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6479 && ((nonzero_bits (new, tmode)
6480 & ~(((unsigned HOST_WIDE_INT)
6481 GET_MODE_MASK (tmode))
6485 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6486 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6488 /* Prefer ZERO_EXTENSION, since it gives more information to
6490 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6495 /* Otherwise, sign- or zero-extend unless we already are in the
6498 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6502 /* Unless this is a COMPARE or we have a funny memory reference,
6503 don't do anything with zero-extending field extracts starting at
6504 the low-order bit since they are simple AND operations. */
6505 if (pos_rtx == 0 && pos == 0 && ! in_dest
6506 && ! in_compare && unsignedp)
6509 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6510 if the position is not a constant and the length is not 1. In all
6511 other cases, we would only be going outside our object in cases when
6512 an original shift would have been undefined. */
6514 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6515 || (pos_rtx != 0 && len != 1)))
6518 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6519 and the mode for the result. */
6520 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6522 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6523 pos_mode = mode_for_extraction (EP_insv, 2);
6524 extraction_mode = mode_for_extraction (EP_insv, 3);
6527 if (! in_dest && unsignedp
6528 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6530 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6531 pos_mode = mode_for_extraction (EP_extzv, 3);
6532 extraction_mode = mode_for_extraction (EP_extzv, 0);
6535 if (! in_dest && ! unsignedp
6536 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6538 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6539 pos_mode = mode_for_extraction (EP_extv, 3);
6540 extraction_mode = mode_for_extraction (EP_extv, 0);
6543 /* Never narrow an object, since that might not be safe. */
6545 if (mode != VOIDmode
6546 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6547 extraction_mode = mode;
6549 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6550 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6551 pos_mode = GET_MODE (pos_rtx);
6553 /* If this is not from memory, the desired mode is the preferred mode
6554 for an extraction pattern's first input operand, or word_mode if there
6557 wanted_inner_mode = wanted_inner_reg_mode;
6560 /* Be careful not to go beyond the extracted object and maintain the
6561 natural alignment of the memory. */
6562 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6563 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6564 > GET_MODE_BITSIZE (wanted_inner_mode))
6566 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6567 gcc_assert (wanted_inner_mode != VOIDmode);
6570 /* If we have to change the mode of memory and cannot, the desired mode
6571 is EXTRACTION_MODE. */
6572 if (inner_mode != wanted_inner_mode
6573 && (mode_dependent_address_p (XEXP (inner, 0))
6574 || MEM_VOLATILE_P (inner)
6576 wanted_inner_mode = extraction_mode;
6581 if (BITS_BIG_ENDIAN)
6583 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6584 BITS_BIG_ENDIAN style. If position is constant, compute new
6585 position. Otherwise, build subtraction.
6586 Note that POS is relative to the mode of the original argument.
6587 If it's a MEM we need to recompute POS relative to that.
6588 However, if we're extracting from (or inserting into) a register,
6589 we want to recompute POS relative to wanted_inner_mode. */
6590 int width = (MEM_P (inner)
6591 ? GET_MODE_BITSIZE (is_mode)
6592 : GET_MODE_BITSIZE (wanted_inner_mode));
6595 pos = width - len - pos;
6598 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6599 /* POS may be less than 0 now, but we check for that below.
6600 Note that it can only be less than 0 if !MEM_P (inner). */
6603 /* If INNER has a wider mode, and this is a constant extraction, try to
6604 make it smaller and adjust the byte to point to the byte containing
6606 if (wanted_inner_mode != VOIDmode
6607 && inner_mode != wanted_inner_mode
6609 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6611 && ! mode_dependent_address_p (XEXP (inner, 0))
6612 && ! MEM_VOLATILE_P (inner))
6616 /* The computations below will be correct if the machine is big
6617 endian in both bits and bytes or little endian in bits and bytes.
6618 If it is mixed, we must adjust. */
6620 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6621 adjust OFFSET to compensate. */
6622 if (BYTES_BIG_ENDIAN
6623 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6624 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6626 /* We can now move to the desired byte. */
6627 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6628 * GET_MODE_SIZE (wanted_inner_mode);
6629 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6631 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6632 && is_mode != wanted_inner_mode)
6633 offset = (GET_MODE_SIZE (is_mode)
6634 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6636 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6639 /* If INNER is not memory, we can always get it into the proper mode. If we
6640 are changing its mode, POS must be a constant and smaller than the size
6642 else if (!MEM_P (inner))
6644 if (GET_MODE (inner) != wanted_inner_mode
6646 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6652 inner = force_to_mode (inner, wanted_inner_mode,
6654 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6655 ? ~(unsigned HOST_WIDE_INT) 0
6656 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6661 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6662 have to zero extend. Otherwise, we can just use a SUBREG. */
6664 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6666 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6668 /* If we know that no extraneous bits are set, and that the high
6669 bit is not set, convert extraction to cheaper one - either
6670 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6672 if (flag_expensive_optimizations
6673 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6674 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6675 & ~(((unsigned HOST_WIDE_INT)
6676 GET_MODE_MASK (GET_MODE (pos_rtx)))
6680 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6682 /* Prefer ZERO_EXTENSION, since it gives more information to
6684 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6689 else if (pos_rtx != 0
6690 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6691 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6693 /* Make POS_RTX unless we already have it and it is correct. If we don't
6694 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6696 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6697 pos_rtx = orig_pos_rtx;
6699 else if (pos_rtx == 0)
6700 pos_rtx = GEN_INT (pos);
6702 /* Make the required operation. See if we can use existing rtx. */
6703 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6704 extraction_mode, inner, GEN_INT (len), pos_rtx);
6706 new = gen_lowpart (mode, new);
6711 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6712 with any other operations in X. Return X without that shift if so. */
6715 extract_left_shift (rtx x, int count)
6717 enum rtx_code code = GET_CODE (x);
6718 enum machine_mode mode = GET_MODE (x);
6724 /* This is the shift itself. If it is wide enough, we will return
6725 either the value being shifted if the shift count is equal to
6726 COUNT or a shift for the difference. */
6727 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6728 && INTVAL (XEXP (x, 1)) >= count)
6729 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6730 INTVAL (XEXP (x, 1)) - count);
6734 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6735 return simplify_gen_unary (code, mode, tem, mode);
6739 case PLUS: case IOR: case XOR: case AND:
6740 /* If we can safely shift this constant and we find the inner shift,
6741 make a new operation. */
6742 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6743 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6744 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6745 return simplify_gen_binary (code, mode, tem,
6746 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6757 /* Look at the expression rooted at X. Look for expressions
6758 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6759 Form these expressions.
6761 Return the new rtx, usually just X.
6763 Also, for machines like the VAX that don't have logical shift insns,
6764 try to convert logical to arithmetic shift operations in cases where
6765 they are equivalent. This undoes the canonicalizations to logical
6766 shifts done elsewhere.
6768 We try, as much as possible, to re-use rtl expressions to save memory.
6770 IN_CODE says what kind of expression we are processing. Normally, it is
6771 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6772 being kludges), it is MEM. When processing the arguments of a comparison
6773 or a COMPARE against zero, it is COMPARE. */
6776 make_compound_operation (rtx x, enum rtx_code in_code)
6778 enum rtx_code code = GET_CODE (x);
6779 enum machine_mode mode = GET_MODE (x);
6780 int mode_width = GET_MODE_BITSIZE (mode);
6782 enum rtx_code next_code;
6788 /* Select the code to be used in recursive calls. Once we are inside an
6789 address, we stay there. If we have a comparison, set to COMPARE,
6790 but once inside, go back to our default of SET. */
6792 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6793 : ((code == COMPARE || COMPARISON_P (x))
6794 && XEXP (x, 1) == const0_rtx) ? COMPARE
6795 : in_code == COMPARE ? SET : in_code);
6797 /* Process depending on the code of this operation. If NEW is set
6798 nonzero, it will be returned. */
6803 /* Convert shifts by constants into multiplications if inside
6805 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6806 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6807 && INTVAL (XEXP (x, 1)) >= 0)
6809 new = make_compound_operation (XEXP (x, 0), next_code);
6810 new = gen_rtx_MULT (mode, new,
6811 GEN_INT ((HOST_WIDE_INT) 1
6812 << INTVAL (XEXP (x, 1))));
6817 /* If the second operand is not a constant, we can't do anything
6819 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6822 /* If the constant is a power of two minus one and the first operand
6823 is a logical right shift, make an extraction. */
6824 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6825 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6827 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6828 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6829 0, in_code == COMPARE);
6832 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6833 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6834 && subreg_lowpart_p (XEXP (x, 0))
6835 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6836 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6838 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6840 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6841 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6842 0, in_code == COMPARE);
6844 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6845 else if ((GET_CODE (XEXP (x, 0)) == XOR
6846 || GET_CODE (XEXP (x, 0)) == IOR)
6847 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6848 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6849 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6851 /* Apply the distributive law, and then try to make extractions. */
6852 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6853 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6855 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6857 new = make_compound_operation (new, in_code);
6860 /* If we are have (and (rotate X C) M) and C is larger than the number
6861 of bits in M, this is an extraction. */
6863 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6864 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6865 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6866 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6868 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6869 new = make_extraction (mode, new,
6870 (GET_MODE_BITSIZE (mode)
6871 - INTVAL (XEXP (XEXP (x, 0), 1))),
6872 NULL_RTX, i, 1, 0, in_code == COMPARE);
6875 /* On machines without logical shifts, if the operand of the AND is
6876 a logical shift and our mask turns off all the propagated sign
6877 bits, we can replace the logical shift with an arithmetic shift. */
6878 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6879 && !have_insn_for (LSHIFTRT, mode)
6880 && have_insn_for (ASHIFTRT, mode)
6881 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6882 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6883 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6884 && mode_width <= HOST_BITS_PER_WIDE_INT)
6886 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6888 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6889 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6891 gen_rtx_ASHIFTRT (mode,
6892 make_compound_operation
6893 (XEXP (XEXP (x, 0), 0), next_code),
6894 XEXP (XEXP (x, 0), 1)));
6897 /* If the constant is one less than a power of two, this might be
6898 representable by an extraction even if no shift is present.
6899 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6900 we are in a COMPARE. */
6901 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6902 new = make_extraction (mode,
6903 make_compound_operation (XEXP (x, 0),
6905 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6907 /* If we are in a comparison and this is an AND with a power of two,
6908 convert this into the appropriate bit extract. */
6909 else if (in_code == COMPARE
6910 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6911 new = make_extraction (mode,
6912 make_compound_operation (XEXP (x, 0),
6914 i, NULL_RTX, 1, 1, 0, 1);
6919 /* If the sign bit is known to be zero, replace this with an
6920 arithmetic shift. */
6921 if (have_insn_for (ASHIFTRT, mode)
6922 && ! have_insn_for (LSHIFTRT, mode)
6923 && mode_width <= HOST_BITS_PER_WIDE_INT
6924 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6926 new = gen_rtx_ASHIFTRT (mode,
6927 make_compound_operation (XEXP (x, 0),
6933 /* ... fall through ... */
6939 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6940 this is a SIGN_EXTRACT. */
6941 if (GET_CODE (rhs) == CONST_INT
6942 && GET_CODE (lhs) == ASHIFT
6943 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6944 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6946 new = make_compound_operation (XEXP (lhs, 0), next_code);
6947 new = make_extraction (mode, new,
6948 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6949 NULL_RTX, mode_width - INTVAL (rhs),
6950 code == LSHIFTRT, 0, in_code == COMPARE);
6954 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6955 If so, try to merge the shifts into a SIGN_EXTEND. We could
6956 also do this for some cases of SIGN_EXTRACT, but it doesn't
6957 seem worth the effort; the case checked for occurs on Alpha. */
6960 && ! (GET_CODE (lhs) == SUBREG
6961 && (OBJECT_P (SUBREG_REG (lhs))))
6962 && GET_CODE (rhs) == CONST_INT
6963 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6964 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6965 new = make_extraction (mode, make_compound_operation (new, next_code),
6966 0, NULL_RTX, mode_width - INTVAL (rhs),
6967 code == LSHIFTRT, 0, in_code == COMPARE);
6972 /* Call ourselves recursively on the inner expression. If we are
6973 narrowing the object and it has a different RTL code from
6974 what it originally did, do this SUBREG as a force_to_mode. */
6976 tem = make_compound_operation (SUBREG_REG (x), in_code);
6980 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6986 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6987 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6988 && subreg_lowpart_p (x))
6990 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6993 /* If we have something other than a SUBREG, we might have
6994 done an expansion, so rerun ourselves. */
6995 if (GET_CODE (newer) != SUBREG)
6996 newer = make_compound_operation (newer, in_code);
7012 x = gen_lowpart (mode, new);
7013 code = GET_CODE (x);
7016 /* Now recursively process each operand of this operation. */
7017 fmt = GET_RTX_FORMAT (code);
7018 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7021 new = make_compound_operation (XEXP (x, i), next_code);
7022 SUBST (XEXP (x, i), new);
7025 /* If this is a commutative operation, the changes to the operands
7026 may have made it noncanonical. */
7027 if (COMMUTATIVE_ARITH_P (x)
7028 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7031 SUBST (XEXP (x, 0), XEXP (x, 1));
7032 SUBST (XEXP (x, 1), tem);
7038 /* Given M see if it is a value that would select a field of bits
7039 within an item, but not the entire word. Return -1 if not.
7040 Otherwise, return the starting position of the field, where 0 is the
7043 *PLEN is set to the length of the field. */
7046 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7048 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7049 int pos = exact_log2 (m & -m);
7053 /* Now shift off the low-order zero bits and see if we have a
7054 power of two minus 1. */
7055 len = exact_log2 ((m >> pos) + 1);
7064 /* If X refers to a register that equals REG in value, replace these
7065 references with REG. */
7067 canon_reg_for_combine (rtx x, rtx reg)
7074 enum rtx_code code = GET_CODE (x);
7075 switch (GET_RTX_CLASS (code))
7078 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7079 if (op0 != XEXP (x, 0))
7080 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7085 case RTX_COMM_ARITH:
7086 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7087 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7088 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7089 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7093 case RTX_COMM_COMPARE:
7094 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7095 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7096 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7097 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7098 GET_MODE (op0), op0, op1);
7102 case RTX_BITFIELD_OPS:
7103 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7104 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7105 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7106 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7107 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7108 GET_MODE (op0), op0, op1, op2);
7113 if (rtx_equal_p (get_last_value (reg), x)
7114 || rtx_equal_p (reg, get_last_value (x)))
7123 fmt = GET_RTX_FORMAT (code);
7125 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7128 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7129 if (op != XEXP (x, i))
7139 else if (fmt[i] == 'E')
7142 for (j = 0; j < XVECLEN (x, i); j++)
7144 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7145 if (op != XVECEXP (x, i, j))
7152 XVECEXP (x, i, j) = op;
7163 /* Return X converted to MODE. If the value is already truncated to
7164 MODE we can just return a subreg even though in the general case we
7165 would need an explicit truncation. */
7168 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7170 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7171 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7172 GET_MODE_BITSIZE (GET_MODE (x)))
7173 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7174 return gen_lowpart (mode, x);
7176 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7179 /* See if X can be simplified knowing that we will only refer to it in
7180 MODE and will only refer to those bits that are nonzero in MASK.
7181 If other bits are being computed or if masking operations are done
7182 that select a superset of the bits in MASK, they can sometimes be
7185 Return a possibly simplified expression, but always convert X to
7186 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7188 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7189 are all off in X. This is used when X will be complemented, by either
7190 NOT, NEG, or XOR. */
7193 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7196 enum rtx_code code = GET_CODE (x);
7197 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7198 enum machine_mode op_mode;
7199 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7202 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7203 code below will do the wrong thing since the mode of such an
7204 expression is VOIDmode.
7206 Also do nothing if X is a CLOBBER; this can happen if X was
7207 the return value from a call to gen_lowpart. */
7208 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7211 /* We want to perform the operation is its present mode unless we know
7212 that the operation is valid in MODE, in which case we do the operation
7214 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7215 && have_insn_for (code, mode))
7216 ? mode : GET_MODE (x));
7218 /* It is not valid to do a right-shift in a narrower mode
7219 than the one it came in with. */
7220 if ((code == LSHIFTRT || code == ASHIFTRT)
7221 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7222 op_mode = GET_MODE (x);
7224 /* Truncate MASK to fit OP_MODE. */
7226 mask &= GET_MODE_MASK (op_mode);
7228 /* When we have an arithmetic operation, or a shift whose count we
7229 do not know, we need to assume that all bits up to the highest-order
7230 bit in MASK will be needed. This is how we form such a mask. */
7231 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7232 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7234 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7237 /* Determine what bits of X are guaranteed to be (non)zero. */
7238 nonzero = nonzero_bits (x, mode);
7240 /* If none of the bits in X are needed, return a zero. */
7241 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7244 /* If X is a CONST_INT, return a new one. Do this here since the
7245 test below will fail. */
7246 if (GET_CODE (x) == CONST_INT)
7248 if (SCALAR_INT_MODE_P (mode))
7249 return gen_int_mode (INTVAL (x) & mask, mode);
7252 x = GEN_INT (INTVAL (x) & mask);
7253 return gen_lowpart_common (mode, x);
7257 /* If X is narrower than MODE and we want all the bits in X's mode, just
7258 get X in the proper mode. */
7259 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7260 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7261 return gen_lowpart (mode, x);
7266 /* If X is a (clobber (const_int)), return it since we know we are
7267 generating something that won't match. */
7274 x = expand_compound_operation (x);
7275 if (GET_CODE (x) != code)
7276 return force_to_mode (x, mode, mask, next_select);
7280 if (subreg_lowpart_p (x)
7281 /* We can ignore the effect of this SUBREG if it narrows the mode or
7282 if the constant masks to zero all the bits the mode doesn't
7284 && ((GET_MODE_SIZE (GET_MODE (x))
7285 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7287 & GET_MODE_MASK (GET_MODE (x))
7288 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7289 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7293 /* If this is an AND with a constant, convert it into an AND
7294 whose constant is the AND of that constant with MASK. If it
7295 remains an AND of MASK, delete it since it is redundant. */
7297 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7299 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7300 mask & INTVAL (XEXP (x, 1)));
7302 /* If X is still an AND, see if it is an AND with a mask that
7303 is just some low-order bits. If so, and it is MASK, we don't
7306 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7307 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7311 /* If it remains an AND, try making another AND with the bits
7312 in the mode mask that aren't in MASK turned on. If the
7313 constant in the AND is wide enough, this might make a
7314 cheaper constant. */
7316 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7317 && GET_MODE_MASK (GET_MODE (x)) != mask
7318 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7320 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7321 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7322 int width = GET_MODE_BITSIZE (GET_MODE (x));
7325 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7326 number, sign extend it. */
7327 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7328 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7329 cval |= (HOST_WIDE_INT) -1 << width;
7331 y = simplify_gen_binary (AND, GET_MODE (x),
7332 XEXP (x, 0), GEN_INT (cval));
7333 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7343 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7344 low-order bits (as in an alignment operation) and FOO is already
7345 aligned to that boundary, mask C1 to that boundary as well.
7346 This may eliminate that PLUS and, later, the AND. */
7349 unsigned int width = GET_MODE_BITSIZE (mode);
7350 unsigned HOST_WIDE_INT smask = mask;
7352 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7353 number, sign extend it. */
7355 if (width < HOST_BITS_PER_WIDE_INT
7356 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7357 smask |= (HOST_WIDE_INT) -1 << width;
7359 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7360 && exact_log2 (- smask) >= 0
7361 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7362 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7363 return force_to_mode (plus_constant (XEXP (x, 0),
7364 (INTVAL (XEXP (x, 1)) & smask)),
7365 mode, smask, next_select);
7368 /* ... fall through ... */
7371 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7372 most significant bit in MASK since carries from those bits will
7373 affect the bits we are interested in. */
7378 /* If X is (minus C Y) where C's least set bit is larger than any bit
7379 in the mask, then we may replace with (neg Y). */
7380 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7381 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7382 & -INTVAL (XEXP (x, 0))))
7385 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7387 return force_to_mode (x, mode, mask, next_select);
7390 /* Similarly, if C contains every bit in the fuller_mask, then we may
7391 replace with (not Y). */
7392 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7393 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7394 == INTVAL (XEXP (x, 0))))
7396 x = simplify_gen_unary (NOT, GET_MODE (x),
7397 XEXP (x, 1), GET_MODE (x));
7398 return force_to_mode (x, mode, mask, next_select);
7406 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7407 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7408 operation which may be a bitfield extraction. Ensure that the
7409 constant we form is not wider than the mode of X. */
7411 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7412 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7413 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7414 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7415 && GET_CODE (XEXP (x, 1)) == CONST_INT
7416 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7417 + floor_log2 (INTVAL (XEXP (x, 1))))
7418 < GET_MODE_BITSIZE (GET_MODE (x)))
7419 && (INTVAL (XEXP (x, 1))
7420 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7422 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7423 << INTVAL (XEXP (XEXP (x, 0), 1)));
7424 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7425 XEXP (XEXP (x, 0), 0), temp);
7426 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7427 XEXP (XEXP (x, 0), 1));
7428 return force_to_mode (x, mode, mask, next_select);
7432 /* For most binary operations, just propagate into the operation and
7433 change the mode if we have an operation of that mode. */
7435 op0 = gen_lowpart_or_truncate (op_mode,
7436 force_to_mode (XEXP (x, 0), mode, mask,
7438 op1 = gen_lowpart_or_truncate (op_mode,
7439 force_to_mode (XEXP (x, 1), mode, mask,
7442 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7443 x = simplify_gen_binary (code, op_mode, op0, op1);
7447 /* For left shifts, do the same, but just for the first operand.
7448 However, we cannot do anything with shifts where we cannot
7449 guarantee that the counts are smaller than the size of the mode
7450 because such a count will have a different meaning in a
7453 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7454 && INTVAL (XEXP (x, 1)) >= 0
7455 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7456 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7457 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7458 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7461 /* If the shift count is a constant and we can do arithmetic in
7462 the mode of the shift, refine which bits we need. Otherwise, use the
7463 conservative form of the mask. */
7464 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7465 && INTVAL (XEXP (x, 1)) >= 0
7466 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7467 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7468 mask >>= INTVAL (XEXP (x, 1));
7472 op0 = gen_lowpart_or_truncate (op_mode,
7473 force_to_mode (XEXP (x, 0), op_mode,
7474 mask, next_select));
7476 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7477 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7481 /* Here we can only do something if the shift count is a constant,
7482 this shift constant is valid for the host, and we can do arithmetic
7485 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7486 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7487 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7489 rtx inner = XEXP (x, 0);
7490 unsigned HOST_WIDE_INT inner_mask;
7492 /* Select the mask of the bits we need for the shift operand. */
7493 inner_mask = mask << INTVAL (XEXP (x, 1));
7495 /* We can only change the mode of the shift if we can do arithmetic
7496 in the mode of the shift and INNER_MASK is no wider than the
7497 width of X's mode. */
7498 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7499 op_mode = GET_MODE (x);
7501 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7503 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7504 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7507 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7508 shift and AND produces only copies of the sign bit (C2 is one less
7509 than a power of two), we can do this with just a shift. */
7511 if (GET_CODE (x) == LSHIFTRT
7512 && GET_CODE (XEXP (x, 1)) == CONST_INT
7513 /* The shift puts one of the sign bit copies in the least significant
7515 && ((INTVAL (XEXP (x, 1))
7516 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7517 >= GET_MODE_BITSIZE (GET_MODE (x)))
7518 && exact_log2 (mask + 1) >= 0
7519 /* Number of bits left after the shift must be more than the mask
7521 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7522 <= GET_MODE_BITSIZE (GET_MODE (x)))
7523 /* Must be more sign bit copies than the mask needs. */
7524 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7525 >= exact_log2 (mask + 1)))
7526 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7527 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7528 - exact_log2 (mask + 1)));
7533 /* If we are just looking for the sign bit, we don't need this shift at
7534 all, even if it has a variable count. */
7535 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7536 && (mask == ((unsigned HOST_WIDE_INT) 1
7537 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7538 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7540 /* If this is a shift by a constant, get a mask that contains those bits
7541 that are not copies of the sign bit. We then have two cases: If
7542 MASK only includes those bits, this can be a logical shift, which may
7543 allow simplifications. If MASK is a single-bit field not within
7544 those bits, we are requesting a copy of the sign bit and hence can
7545 shift the sign bit to the appropriate location. */
7547 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7548 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7552 /* If the considered data is wider than HOST_WIDE_INT, we can't
7553 represent a mask for all its bits in a single scalar.
7554 But we only care about the lower bits, so calculate these. */
7556 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7558 nonzero = ~(HOST_WIDE_INT) 0;
7560 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7561 is the number of bits a full-width mask would have set.
7562 We need only shift if these are fewer than nonzero can
7563 hold. If not, we must keep all bits set in nonzero. */
7565 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7566 < HOST_BITS_PER_WIDE_INT)
7567 nonzero >>= INTVAL (XEXP (x, 1))
7568 + HOST_BITS_PER_WIDE_INT
7569 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7573 nonzero = GET_MODE_MASK (GET_MODE (x));
7574 nonzero >>= INTVAL (XEXP (x, 1));
7577 if ((mask & ~nonzero) == 0)
7579 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7580 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7581 if (GET_CODE (x) != ASHIFTRT)
7582 return force_to_mode (x, mode, mask, next_select);
7585 else if ((i = exact_log2 (mask)) >= 0)
7587 x = simplify_shift_const
7588 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7589 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7591 if (GET_CODE (x) != ASHIFTRT)
7592 return force_to_mode (x, mode, mask, next_select);
7596 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7597 even if the shift count isn't a constant. */
7599 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7600 XEXP (x, 0), XEXP (x, 1));
7604 /* If this is a zero- or sign-extension operation that just affects bits
7605 we don't care about, remove it. Be sure the call above returned
7606 something that is still a shift. */
7608 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7609 && GET_CODE (XEXP (x, 1)) == CONST_INT
7610 && INTVAL (XEXP (x, 1)) >= 0
7611 && (INTVAL (XEXP (x, 1))
7612 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7613 && GET_CODE (XEXP (x, 0)) == ASHIFT
7614 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7615 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7622 /* If the shift count is constant and we can do computations
7623 in the mode of X, compute where the bits we care about are.
7624 Otherwise, we can't do anything. Don't change the mode of
7625 the shift or propagate MODE into the shift, though. */
7626 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7627 && INTVAL (XEXP (x, 1)) >= 0)
7629 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7630 GET_MODE (x), GEN_INT (mask),
7632 if (temp && GET_CODE (temp) == CONST_INT)
7634 force_to_mode (XEXP (x, 0), GET_MODE (x),
7635 INTVAL (temp), next_select));
7640 /* If we just want the low-order bit, the NEG isn't needed since it
7641 won't change the low-order bit. */
7643 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7645 /* We need any bits less significant than the most significant bit in
7646 MASK since carries from those bits will affect the bits we are
7652 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7653 same as the XOR case above. Ensure that the constant we form is not
7654 wider than the mode of X. */
7656 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7657 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7658 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7659 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7660 < GET_MODE_BITSIZE (GET_MODE (x)))
7661 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7663 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7665 temp = simplify_gen_binary (XOR, GET_MODE (x),
7666 XEXP (XEXP (x, 0), 0), temp);
7667 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7668 temp, XEXP (XEXP (x, 0), 1));
7670 return force_to_mode (x, mode, mask, next_select);
7673 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7674 use the full mask inside the NOT. */
7678 op0 = gen_lowpart_or_truncate (op_mode,
7679 force_to_mode (XEXP (x, 0), mode, mask,
7681 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7682 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7686 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7687 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7688 which is equal to STORE_FLAG_VALUE. */
7689 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7690 && GET_MODE (XEXP (x, 0)) == mode
7691 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7692 && (nonzero_bits (XEXP (x, 0), mode)
7693 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7694 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7699 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7700 written in a narrower mode. We play it safe and do not do so. */
7703 gen_lowpart_or_truncate (GET_MODE (x),
7704 force_to_mode (XEXP (x, 1), mode,
7705 mask, next_select)));
7707 gen_lowpart_or_truncate (GET_MODE (x),
7708 force_to_mode (XEXP (x, 2), mode,
7709 mask, next_select)));
7716 /* Ensure we return a value of the proper mode. */
7717 return gen_lowpart_or_truncate (mode, x);
7720 /* Return nonzero if X is an expression that has one of two values depending on
7721 whether some other value is zero or nonzero. In that case, we return the
7722 value that is being tested, *PTRUE is set to the value if the rtx being
7723 returned has a nonzero value, and *PFALSE is set to the other alternative.
7725 If we return zero, we set *PTRUE and *PFALSE to X. */
7728 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7730 enum machine_mode mode = GET_MODE (x);
7731 enum rtx_code code = GET_CODE (x);
7732 rtx cond0, cond1, true0, true1, false0, false1;
7733 unsigned HOST_WIDE_INT nz;
7735 /* If we are comparing a value against zero, we are done. */
7736 if ((code == NE || code == EQ)
7737 && XEXP (x, 1) == const0_rtx)
7739 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7740 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7744 /* If this is a unary operation whose operand has one of two values, apply
7745 our opcode to compute those values. */
7746 else if (UNARY_P (x)
7747 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7749 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7750 *pfalse = simplify_gen_unary (code, mode, false0,
7751 GET_MODE (XEXP (x, 0)));
7755 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7756 make can't possibly match and would suppress other optimizations. */
7757 else if (code == COMPARE)
7760 /* If this is a binary operation, see if either side has only one of two
7761 values. If either one does or if both do and they are conditional on
7762 the same value, compute the new true and false values. */
7763 else if (BINARY_P (x))
7765 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7766 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7768 if ((cond0 != 0 || cond1 != 0)
7769 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7771 /* If if_then_else_cond returned zero, then true/false are the
7772 same rtl. We must copy one of them to prevent invalid rtl
7775 true0 = copy_rtx (true0);
7776 else if (cond1 == 0)
7777 true1 = copy_rtx (true1);
7779 if (COMPARISON_P (x))
7781 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7783 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7788 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7789 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7792 return cond0 ? cond0 : cond1;
7795 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7796 operands is zero when the other is nonzero, and vice-versa,
7797 and STORE_FLAG_VALUE is 1 or -1. */
7799 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7800 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7802 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7804 rtx op0 = XEXP (XEXP (x, 0), 1);
7805 rtx op1 = XEXP (XEXP (x, 1), 1);
7807 cond0 = XEXP (XEXP (x, 0), 0);
7808 cond1 = XEXP (XEXP (x, 1), 0);
7810 if (COMPARISON_P (cond0)
7811 && COMPARISON_P (cond1)
7812 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7813 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7814 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7815 || ((swap_condition (GET_CODE (cond0))
7816 == reversed_comparison_code (cond1, NULL))
7817 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7818 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7819 && ! side_effects_p (x))
7821 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7822 *pfalse = simplify_gen_binary (MULT, mode,
7824 ? simplify_gen_unary (NEG, mode,
7832 /* Similarly for MULT, AND and UMIN, except that for these the result
7834 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7835 && (code == MULT || code == AND || code == UMIN)
7836 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7838 cond0 = XEXP (XEXP (x, 0), 0);
7839 cond1 = XEXP (XEXP (x, 1), 0);
7841 if (COMPARISON_P (cond0)
7842 && COMPARISON_P (cond1)
7843 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7844 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7845 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7846 || ((swap_condition (GET_CODE (cond0))
7847 == reversed_comparison_code (cond1, NULL))
7848 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7849 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7850 && ! side_effects_p (x))
7852 *ptrue = *pfalse = const0_rtx;
7858 else if (code == IF_THEN_ELSE)
7860 /* If we have IF_THEN_ELSE already, extract the condition and
7861 canonicalize it if it is NE or EQ. */
7862 cond0 = XEXP (x, 0);
7863 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7864 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7865 return XEXP (cond0, 0);
7866 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7868 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7869 return XEXP (cond0, 0);
7875 /* If X is a SUBREG, we can narrow both the true and false values
7876 if the inner expression, if there is a condition. */
7877 else if (code == SUBREG
7878 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7881 true0 = simplify_gen_subreg (mode, true0,
7882 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7883 false0 = simplify_gen_subreg (mode, false0,
7884 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7885 if (true0 && false0)
7893 /* If X is a constant, this isn't special and will cause confusions
7894 if we treat it as such. Likewise if it is equivalent to a constant. */
7895 else if (CONSTANT_P (x)
7896 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7899 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7900 will be least confusing to the rest of the compiler. */
7901 else if (mode == BImode)
7903 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7907 /* If X is known to be either 0 or -1, those are the true and
7908 false values when testing X. */
7909 else if (x == constm1_rtx || x == const0_rtx
7910 || (mode != VOIDmode
7911 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7913 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7917 /* Likewise for 0 or a single bit. */
7918 else if (SCALAR_INT_MODE_P (mode)
7919 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7920 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7922 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7926 /* Otherwise fail; show no condition with true and false values the same. */
7927 *ptrue = *pfalse = x;
7931 /* Return the value of expression X given the fact that condition COND
7932 is known to be true when applied to REG as its first operand and VAL
7933 as its second. X is known to not be shared and so can be modified in
7936 We only handle the simplest cases, and specifically those cases that
7937 arise with IF_THEN_ELSE expressions. */
7940 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7942 enum rtx_code code = GET_CODE (x);
7947 if (side_effects_p (x))
7950 /* If either operand of the condition is a floating point value,
7951 then we have to avoid collapsing an EQ comparison. */
7953 && rtx_equal_p (x, reg)
7954 && ! FLOAT_MODE_P (GET_MODE (x))
7955 && ! FLOAT_MODE_P (GET_MODE (val)))
7958 if (cond == UNEQ && rtx_equal_p (x, reg))
7961 /* If X is (abs REG) and we know something about REG's relationship
7962 with zero, we may be able to simplify this. */
7964 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7967 case GE: case GT: case EQ:
7970 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7972 GET_MODE (XEXP (x, 0)));
7977 /* The only other cases we handle are MIN, MAX, and comparisons if the
7978 operands are the same as REG and VAL. */
7980 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7982 if (rtx_equal_p (XEXP (x, 0), val))
7983 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7985 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7987 if (COMPARISON_P (x))
7989 if (comparison_dominates_p (cond, code))
7990 return const_true_rtx;
7992 code = reversed_comparison_code (x, NULL);
7994 && comparison_dominates_p (cond, code))
7999 else if (code == SMAX || code == SMIN
8000 || code == UMIN || code == UMAX)
8002 int unsignedp = (code == UMIN || code == UMAX);
8004 /* Do not reverse the condition when it is NE or EQ.
8005 This is because we cannot conclude anything about
8006 the value of 'SMAX (x, y)' when x is not equal to y,
8007 but we can when x equals y. */
8008 if ((code == SMAX || code == UMAX)
8009 && ! (cond == EQ || cond == NE))
8010 cond = reverse_condition (cond);
8015 return unsignedp ? x : XEXP (x, 1);
8017 return unsignedp ? x : XEXP (x, 0);
8019 return unsignedp ? XEXP (x, 1) : x;
8021 return unsignedp ? XEXP (x, 0) : x;
8028 else if (code == SUBREG)
8030 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8031 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
8033 if (SUBREG_REG (x) != r)
8035 /* We must simplify subreg here, before we lose track of the
8036 original inner_mode. */
8037 new = simplify_subreg (GET_MODE (x), r,
8038 inner_mode, SUBREG_BYTE (x));
8042 SUBST (SUBREG_REG (x), r);
8047 /* We don't have to handle SIGN_EXTEND here, because even in the
8048 case of replacing something with a modeless CONST_INT, a
8049 CONST_INT is already (supposed to be) a valid sign extension for
8050 its narrower mode, which implies it's already properly
8051 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8052 story is different. */
8053 else if (code == ZERO_EXTEND)
8055 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8056 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
8058 if (XEXP (x, 0) != r)
8060 /* We must simplify the zero_extend here, before we lose
8061 track of the original inner_mode. */
8062 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8067 SUBST (XEXP (x, 0), r);
8073 fmt = GET_RTX_FORMAT (code);
8074 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8077 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8078 else if (fmt[i] == 'E')
8079 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8080 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8087 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8088 assignment as a field assignment. */
8091 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8093 if (x == y || rtx_equal_p (x, y))
8096 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8099 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8100 Note that all SUBREGs of MEM are paradoxical; otherwise they
8101 would have been rewritten. */
8102 if (MEM_P (x) && GET_CODE (y) == SUBREG
8103 && MEM_P (SUBREG_REG (y))
8104 && rtx_equal_p (SUBREG_REG (y),
8105 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8108 if (MEM_P (y) && GET_CODE (x) == SUBREG
8109 && MEM_P (SUBREG_REG (x))
8110 && rtx_equal_p (SUBREG_REG (x),
8111 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8114 /* We used to see if get_last_value of X and Y were the same but that's
8115 not correct. In one direction, we'll cause the assignment to have
8116 the wrong destination and in the case, we'll import a register into this
8117 insn that might have already have been dead. So fail if none of the
8118 above cases are true. */
8122 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8123 Return that assignment if so.
8125 We only handle the most common cases. */
8128 make_field_assignment (rtx x)
8130 rtx dest = SET_DEST (x);
8131 rtx src = SET_SRC (x);
8136 unsigned HOST_WIDE_INT len;
8138 enum machine_mode mode;
8140 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8141 a clear of a one-bit field. We will have changed it to
8142 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8145 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8146 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8147 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8148 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8150 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8153 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8157 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8158 && subreg_lowpart_p (XEXP (src, 0))
8159 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8160 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8161 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8162 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8163 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8164 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8166 assign = make_extraction (VOIDmode, dest, 0,
8167 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8170 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8174 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8176 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8177 && XEXP (XEXP (src, 0), 0) == const1_rtx
8178 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8180 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8183 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8187 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8188 SRC is an AND with all bits of that field set, then we can discard
8190 if (GET_CODE (dest) == ZERO_EXTRACT
8191 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8192 && GET_CODE (src) == AND
8193 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8195 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8196 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8197 unsigned HOST_WIDE_INT ze_mask;
8199 if (width >= HOST_BITS_PER_WIDE_INT)
8202 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8204 /* Complete overlap. We can remove the source AND. */
8205 if ((and_mask & ze_mask) == ze_mask)
8206 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8208 /* Partial overlap. We can reduce the source AND. */
8209 if ((and_mask & ze_mask) != and_mask)
8211 mode = GET_MODE (src);
8212 src = gen_rtx_AND (mode, XEXP (src, 0),
8213 gen_int_mode (and_mask & ze_mask, mode));
8214 return gen_rtx_SET (VOIDmode, dest, src);
8218 /* The other case we handle is assignments into a constant-position
8219 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8220 a mask that has all one bits except for a group of zero bits and
8221 OTHER is known to have zeros where C1 has ones, this is such an
8222 assignment. Compute the position and length from C1. Shift OTHER
8223 to the appropriate position, force it to the required mode, and
8224 make the extraction. Check for the AND in both operands. */
8226 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8229 rhs = expand_compound_operation (XEXP (src, 0));
8230 lhs = expand_compound_operation (XEXP (src, 1));
8232 if (GET_CODE (rhs) == AND
8233 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8234 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8235 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8236 else if (GET_CODE (lhs) == AND
8237 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8238 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8239 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8243 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8244 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8245 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8246 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8249 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8253 /* The mode to use for the source is the mode of the assignment, or of
8254 what is inside a possible STRICT_LOW_PART. */
8255 mode = (GET_CODE (assign) == STRICT_LOW_PART
8256 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8258 /* Shift OTHER right POS places and make it the source, restricting it
8259 to the proper length and mode. */
8261 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8265 src = force_to_mode (src, mode,
8266 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8267 ? ~(unsigned HOST_WIDE_INT) 0
8268 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8271 /* If SRC is masked by an AND that does not make a difference in
8272 the value being stored, strip it. */
8273 if (GET_CODE (assign) == ZERO_EXTRACT
8274 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8275 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8276 && GET_CODE (src) == AND
8277 && GET_CODE (XEXP (src, 1)) == CONST_INT
8278 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8279 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8280 src = XEXP (src, 0);
8282 return gen_rtx_SET (VOIDmode, assign, src);
8285 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8289 apply_distributive_law (rtx x)
8291 enum rtx_code code = GET_CODE (x);
8292 enum rtx_code inner_code;
8293 rtx lhs, rhs, other;
8296 /* Distributivity is not true for floating point as it can change the
8297 value. So we don't do it unless -funsafe-math-optimizations. */
8298 if (FLOAT_MODE_P (GET_MODE (x))
8299 && ! flag_unsafe_math_optimizations)
8302 /* The outer operation can only be one of the following: */
8303 if (code != IOR && code != AND && code != XOR
8304 && code != PLUS && code != MINUS)
8310 /* If either operand is a primitive we can't do anything, so get out
8312 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8315 lhs = expand_compound_operation (lhs);
8316 rhs = expand_compound_operation (rhs);
8317 inner_code = GET_CODE (lhs);
8318 if (inner_code != GET_CODE (rhs))
8321 /* See if the inner and outer operations distribute. */
8328 /* These all distribute except over PLUS. */
8329 if (code == PLUS || code == MINUS)
8334 if (code != PLUS && code != MINUS)
8339 /* This is also a multiply, so it distributes over everything. */
8343 /* Non-paradoxical SUBREGs distributes over all operations,
8344 provided the inner modes and byte offsets are the same, this
8345 is an extraction of a low-order part, we don't convert an fp
8346 operation to int or vice versa, this is not a vector mode,
8347 and we would not be converting a single-word operation into a
8348 multi-word operation. The latter test is not required, but
8349 it prevents generating unneeded multi-word operations. Some
8350 of the previous tests are redundant given the latter test,
8351 but are retained because they are required for correctness.
8353 We produce the result slightly differently in this case. */
8355 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8356 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8357 || ! subreg_lowpart_p (lhs)
8358 || (GET_MODE_CLASS (GET_MODE (lhs))
8359 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8360 || (GET_MODE_SIZE (GET_MODE (lhs))
8361 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8362 || VECTOR_MODE_P (GET_MODE (lhs))
8363 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8364 /* Result might need to be truncated. Don't change mode if
8365 explicit truncation is needed. */
8366 || !TRULY_NOOP_TRUNCATION
8367 (GET_MODE_BITSIZE (GET_MODE (x)),
8368 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8371 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8372 SUBREG_REG (lhs), SUBREG_REG (rhs));
8373 return gen_lowpart (GET_MODE (x), tem);
8379 /* Set LHS and RHS to the inner operands (A and B in the example
8380 above) and set OTHER to the common operand (C in the example).
8381 There is only one way to do this unless the inner operation is
8383 if (COMMUTATIVE_ARITH_P (lhs)
8384 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8385 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8386 else if (COMMUTATIVE_ARITH_P (lhs)
8387 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8388 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8389 else if (COMMUTATIVE_ARITH_P (lhs)
8390 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8391 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8392 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8393 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8397 /* Form the new inner operation, seeing if it simplifies first. */
8398 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8400 /* There is one exception to the general way of distributing:
8401 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8402 if (code == XOR && inner_code == IOR)
8405 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8408 /* We may be able to continuing distributing the result, so call
8409 ourselves recursively on the inner operation before forming the
8410 outer operation, which we return. */
8411 return simplify_gen_binary (inner_code, GET_MODE (x),
8412 apply_distributive_law (tem), other);
8415 /* See if X is of the form (* (+ A B) C), and if so convert to
8416 (+ (* A C) (* B C)) and try to simplify.
8418 Most of the time, this results in no change. However, if some of
8419 the operands are the same or inverses of each other, simplifications
8422 For example, (and (ior A B) (not B)) can occur as the result of
8423 expanding a bit field assignment. When we apply the distributive
8424 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8425 which then simplifies to (and (A (not B))).
8427 Note that no checks happen on the validity of applying the inverse
8428 distributive law. This is pointless since we can do it in the
8429 few places where this routine is called.
8431 N is the index of the term that is decomposed (the arithmetic operation,
8432 i.e. (+ A B) in the first example above). !N is the index of the term that
8433 is distributed, i.e. of C in the first example above. */
8435 distribute_and_simplify_rtx (rtx x, int n)
8437 enum machine_mode mode;
8438 enum rtx_code outer_code, inner_code;
8439 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8441 decomposed = XEXP (x, n);
8442 if (!ARITHMETIC_P (decomposed))
8445 mode = GET_MODE (x);
8446 outer_code = GET_CODE (x);
8447 distributed = XEXP (x, !n);
8449 inner_code = GET_CODE (decomposed);
8450 inner_op0 = XEXP (decomposed, 0);
8451 inner_op1 = XEXP (decomposed, 1);
8453 /* Special case (and (xor B C) (not A)), which is equivalent to
8454 (xor (ior A B) (ior A C)) */
8455 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8457 distributed = XEXP (distributed, 0);
8463 /* Distribute the second term. */
8464 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8465 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8469 /* Distribute the first term. */
8470 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8471 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8474 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8476 if (GET_CODE (tmp) != outer_code
8477 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8483 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8484 in MODE. Return an equivalent form, if different from (and VAROP
8485 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8488 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8489 unsigned HOST_WIDE_INT constop)
8491 unsigned HOST_WIDE_INT nonzero;
8492 unsigned HOST_WIDE_INT orig_constop;
8497 orig_constop = constop;
8498 if (GET_CODE (varop) == CLOBBER)
8501 /* Simplify VAROP knowing that we will be only looking at some of the
8504 Note by passing in CONSTOP, we guarantee that the bits not set in
8505 CONSTOP are not significant and will never be examined. We must
8506 ensure that is the case by explicitly masking out those bits
8507 before returning. */
8508 varop = force_to_mode (varop, mode, constop, 0);
8510 /* If VAROP is a CLOBBER, we will fail so return it. */
8511 if (GET_CODE (varop) == CLOBBER)
8514 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8515 to VAROP and return the new constant. */
8516 if (GET_CODE (varop) == CONST_INT)
8517 return gen_int_mode (INTVAL (varop) & constop, mode);
8519 /* See what bits may be nonzero in VAROP. Unlike the general case of
8520 a call to nonzero_bits, here we don't care about bits outside
8523 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8525 /* Turn off all bits in the constant that are known to already be zero.
8526 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8527 which is tested below. */
8531 /* If we don't have any bits left, return zero. */
8535 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8536 a power of two, we can replace this with an ASHIFT. */
8537 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8538 && (i = exact_log2 (constop)) >= 0)
8539 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8541 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8542 or XOR, then try to apply the distributive law. This may eliminate
8543 operations if either branch can be simplified because of the AND.
8544 It may also make some cases more complex, but those cases probably
8545 won't match a pattern either with or without this. */
8547 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8551 apply_distributive_law
8552 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8553 simplify_and_const_int (NULL_RTX,
8557 simplify_and_const_int (NULL_RTX,
8562 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8563 the AND and see if one of the operands simplifies to zero. If so, we
8564 may eliminate it. */
8566 if (GET_CODE (varop) == PLUS
8567 && exact_log2 (constop + 1) >= 0)
8571 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8572 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8573 if (o0 == const0_rtx)
8575 if (o1 == const0_rtx)
8579 /* Make a SUBREG if necessary. If we can't make it, fail. */
8580 varop = gen_lowpart (mode, varop);
8581 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8584 /* If we are only masking insignificant bits, return VAROP. */
8585 if (constop == nonzero)
8588 if (varop == orig_varop && constop == orig_constop)
8591 /* Otherwise, return an AND. */
8592 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8596 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8599 Return an equivalent form, if different from X. Otherwise, return X. If
8600 X is zero, we are to always construct the equivalent form. */
8603 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8604 unsigned HOST_WIDE_INT constop)
8606 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8611 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8612 gen_int_mode (constop, mode));
8613 if (GET_MODE (x) != mode)
8614 x = gen_lowpart (mode, x);
8618 /* Given a REG, X, compute which bits in X can be nonzero.
8619 We don't care about bits outside of those defined in MODE.
8621 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8622 a shift, AND, or zero_extract, we can do better. */
8625 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8626 const_rtx known_x ATTRIBUTE_UNUSED,
8627 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8628 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8629 unsigned HOST_WIDE_INT *nonzero)
8634 /* If X is a register whose nonzero bits value is current, use it.
8635 Otherwise, if X is a register whose value we can find, use that
8636 value. Otherwise, use the previously-computed global nonzero bits
8637 for this register. */
8639 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8640 if (rsp->last_set_value != 0
8641 && (rsp->last_set_mode == mode
8642 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8643 && GET_MODE_CLASS (mode) == MODE_INT))
8644 && ((rsp->last_set_label >= label_tick_ebb_start
8645 && rsp->last_set_label < label_tick)
8646 || (rsp->last_set_label == label_tick
8647 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8648 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8649 && REG_N_SETS (REGNO (x)) == 1
8651 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8653 *nonzero &= rsp->last_set_nonzero_bits;
8657 tem = get_last_value (x);
8661 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8662 /* If X is narrower than MODE and TEM is a non-negative
8663 constant that would appear negative in the mode of X,
8664 sign-extend it for use in reg_nonzero_bits because some
8665 machines (maybe most) will actually do the sign-extension
8666 and this is the conservative approach.
8668 ??? For 2.5, try to tighten up the MD files in this regard
8669 instead of this kludge. */
8671 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8672 && GET_CODE (tem) == CONST_INT
8674 && 0 != (INTVAL (tem)
8675 & ((HOST_WIDE_INT) 1
8676 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8677 tem = GEN_INT (INTVAL (tem)
8678 | ((HOST_WIDE_INT) (-1)
8679 << GET_MODE_BITSIZE (GET_MODE (x))));
8683 else if (nonzero_sign_valid && rsp->nonzero_bits)
8685 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8687 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8688 /* We don't know anything about the upper bits. */
8689 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8696 /* Return the number of bits at the high-order end of X that are known to
8697 be equal to the sign bit. X will be used in mode MODE; if MODE is
8698 VOIDmode, X will be used in its own mode. The returned value will always
8699 be between 1 and the number of bits in MODE. */
8702 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8703 const_rtx known_x ATTRIBUTE_UNUSED,
8704 enum machine_mode known_mode
8706 unsigned int known_ret ATTRIBUTE_UNUSED,
8707 unsigned int *result)
8712 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8713 if (rsp->last_set_value != 0
8714 && rsp->last_set_mode == mode
8715 && ((rsp->last_set_label >= label_tick_ebb_start
8716 && rsp->last_set_label < label_tick)
8717 || (rsp->last_set_label == label_tick
8718 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8719 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8720 && REG_N_SETS (REGNO (x)) == 1
8722 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8724 *result = rsp->last_set_sign_bit_copies;
8728 tem = get_last_value (x);
8732 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8733 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8734 *result = rsp->sign_bit_copies;
8739 /* Return the number of "extended" bits there are in X, when interpreted
8740 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8741 unsigned quantities, this is the number of high-order zero bits.
8742 For signed quantities, this is the number of copies of the sign bit
8743 minus 1. In both case, this function returns the number of "spare"
8744 bits. For example, if two quantities for which this function returns
8745 at least 1 are added, the addition is known not to overflow.
8747 This function will always return 0 unless called during combine, which
8748 implies that it must be called from a define_split. */
8751 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8753 if (nonzero_sign_valid == 0)
8757 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8758 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8759 - floor_log2 (nonzero_bits (x, mode)))
8761 : num_sign_bit_copies (x, mode) - 1);
8764 /* This function is called from `simplify_shift_const' to merge two
8765 outer operations. Specifically, we have already found that we need
8766 to perform operation *POP0 with constant *PCONST0 at the outermost
8767 position. We would now like to also perform OP1 with constant CONST1
8768 (with *POP0 being done last).
8770 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8771 the resulting operation. *PCOMP_P is set to 1 if we would need to
8772 complement the innermost operand, otherwise it is unchanged.
8774 MODE is the mode in which the operation will be done. No bits outside
8775 the width of this mode matter. It is assumed that the width of this mode
8776 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8778 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8779 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8780 result is simply *PCONST0.
8782 If the resulting operation cannot be expressed as one operation, we
8783 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8786 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8788 enum rtx_code op0 = *pop0;
8789 HOST_WIDE_INT const0 = *pconst0;
8791 const0 &= GET_MODE_MASK (mode);
8792 const1 &= GET_MODE_MASK (mode);
8794 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8798 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8801 if (op1 == UNKNOWN || op0 == SET)
8804 else if (op0 == UNKNOWN)
8805 op0 = op1, const0 = const1;
8807 else if (op0 == op1)
8831 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8832 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8835 /* If the two constants aren't the same, we can't do anything. The
8836 remaining six cases can all be done. */
8837 else if (const0 != const1)
8845 /* (a & b) | b == b */
8847 else /* op1 == XOR */
8848 /* (a ^ b) | b == a | b */
8854 /* (a & b) ^ b == (~a) & b */
8855 op0 = AND, *pcomp_p = 1;
8856 else /* op1 == IOR */
8857 /* (a | b) ^ b == a & ~b */
8858 op0 = AND, const0 = ~const0;
8863 /* (a | b) & b == b */
8865 else /* op1 == XOR */
8866 /* (a ^ b) & b) == (~a) & b */
8873 /* Check for NO-OP cases. */
8874 const0 &= GET_MODE_MASK (mode);
8876 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8878 else if (const0 == 0 && op0 == AND)
8880 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8884 /* ??? Slightly redundant with the above mask, but not entirely.
8885 Moving this above means we'd have to sign-extend the mode mask
8886 for the final test. */
8887 const0 = trunc_int_for_mode (const0, mode);
8895 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8896 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8897 simplify it. Otherwise, return a simplified value.
8899 The shift is normally computed in the widest mode we find in VAROP, as
8900 long as it isn't a different number of words than RESULT_MODE. Exceptions
8901 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8904 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8905 rtx varop, int orig_count)
8907 enum rtx_code orig_code = code;
8908 rtx orig_varop = varop;
8910 enum machine_mode mode = result_mode;
8911 enum machine_mode shift_mode, tmode;
8912 unsigned int mode_words
8913 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8914 /* We form (outer_op (code varop count) (outer_const)). */
8915 enum rtx_code outer_op = UNKNOWN;
8916 HOST_WIDE_INT outer_const = 0;
8917 int complement_p = 0;
8920 /* Make sure and truncate the "natural" shift on the way in. We don't
8921 want to do this inside the loop as it makes it more difficult to
8923 if (SHIFT_COUNT_TRUNCATED)
8924 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8926 /* If we were given an invalid count, don't do anything except exactly
8927 what was requested. */
8929 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8934 /* Unless one of the branches of the `if' in this loop does a `continue',
8935 we will `break' the loop after the `if'. */
8939 /* If we have an operand of (clobber (const_int 0)), fail. */
8940 if (GET_CODE (varop) == CLOBBER)
8943 /* If we discovered we had to complement VAROP, leave. Making a NOT
8944 here would cause an infinite loop. */
8948 /* Convert ROTATERT to ROTATE. */
8949 if (code == ROTATERT)
8951 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8953 if (VECTOR_MODE_P (result_mode))
8954 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8956 count = bitsize - count;
8959 /* We need to determine what mode we will do the shift in. If the
8960 shift is a right shift or a ROTATE, we must always do it in the mode
8961 it was originally done in. Otherwise, we can do it in MODE, the
8962 widest mode encountered. */
8964 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8965 ? result_mode : mode);
8967 /* Handle cases where the count is greater than the size of the mode
8968 minus 1. For ASHIFT, use the size minus one as the count (this can
8969 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8970 take the count modulo the size. For other shifts, the result is
8973 Since these shifts are being produced by the compiler by combining
8974 multiple operations, each of which are defined, we know what the
8975 result is supposed to be. */
8977 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
8979 if (code == ASHIFTRT)
8980 count = GET_MODE_BITSIZE (shift_mode) - 1;
8981 else if (code == ROTATE || code == ROTATERT)
8982 count %= GET_MODE_BITSIZE (shift_mode);
8985 /* We can't simply return zero because there may be an
8993 /* An arithmetic right shift of a quantity known to be -1 or 0
8995 if (code == ASHIFTRT
8996 && (num_sign_bit_copies (varop, shift_mode)
8997 == GET_MODE_BITSIZE (shift_mode)))
9003 /* If we are doing an arithmetic right shift and discarding all but
9004 the sign bit copies, this is equivalent to doing a shift by the
9005 bitsize minus one. Convert it into that shift because it will often
9006 allow other simplifications. */
9008 if (code == ASHIFTRT
9009 && (count + num_sign_bit_copies (varop, shift_mode)
9010 >= GET_MODE_BITSIZE (shift_mode)))
9011 count = GET_MODE_BITSIZE (shift_mode) - 1;
9013 /* We simplify the tests below and elsewhere by converting
9014 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9015 `make_compound_operation' will convert it to an ASHIFTRT for
9016 those machines (such as VAX) that don't have an LSHIFTRT. */
9017 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9019 && ((nonzero_bits (varop, shift_mode)
9020 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9024 if (((code == LSHIFTRT
9025 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9026 && !(nonzero_bits (varop, shift_mode) >> count))
9028 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9029 && !((nonzero_bits (varop, shift_mode) << count)
9030 & GET_MODE_MASK (shift_mode))))
9031 && !side_effects_p (varop))
9034 switch (GET_CODE (varop))
9040 new = expand_compound_operation (varop);
9049 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9050 minus the width of a smaller mode, we can do this with a
9051 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9052 if ((code == ASHIFTRT || code == LSHIFTRT)
9053 && ! mode_dependent_address_p (XEXP (varop, 0))
9054 && ! MEM_VOLATILE_P (varop)
9055 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9056 MODE_INT, 1)) != BLKmode)
9058 new = adjust_address_nv (varop, tmode,
9059 BYTES_BIG_ENDIAN ? 0
9060 : count / BITS_PER_UNIT);
9062 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9063 : ZERO_EXTEND, mode, new);
9070 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9071 the same number of words as what we've seen so far. Then store
9072 the widest mode in MODE. */
9073 if (subreg_lowpart_p (varop)
9074 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9075 > GET_MODE_SIZE (GET_MODE (varop)))
9076 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9077 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9080 varop = SUBREG_REG (varop);
9081 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9082 mode = GET_MODE (varop);
9088 /* Some machines use MULT instead of ASHIFT because MULT
9089 is cheaper. But it is still better on those machines to
9090 merge two shifts into one. */
9091 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9092 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9095 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9097 GEN_INT (exact_log2 (
9098 INTVAL (XEXP (varop, 1)))));
9104 /* Similar, for when divides are cheaper. */
9105 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9106 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9109 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9111 GEN_INT (exact_log2 (
9112 INTVAL (XEXP (varop, 1)))));
9118 /* If we are extracting just the sign bit of an arithmetic
9119 right shift, that shift is not needed. However, the sign
9120 bit of a wider mode may be different from what would be
9121 interpreted as the sign bit in a narrower mode, so, if
9122 the result is narrower, don't discard the shift. */
9123 if (code == LSHIFTRT
9124 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9125 && (GET_MODE_BITSIZE (result_mode)
9126 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9128 varop = XEXP (varop, 0);
9132 /* ... fall through ... */
9137 /* Here we have two nested shifts. The result is usually the
9138 AND of a new shift with a mask. We compute the result below. */
9139 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9140 && INTVAL (XEXP (varop, 1)) >= 0
9141 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9142 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9143 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9144 && !VECTOR_MODE_P (result_mode))
9146 enum rtx_code first_code = GET_CODE (varop);
9147 unsigned int first_count = INTVAL (XEXP (varop, 1));
9148 unsigned HOST_WIDE_INT mask;
9151 /* We have one common special case. We can't do any merging if
9152 the inner code is an ASHIFTRT of a smaller mode. However, if
9153 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9154 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9155 we can convert it to
9156 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9157 This simplifies certain SIGN_EXTEND operations. */
9158 if (code == ASHIFT && first_code == ASHIFTRT
9159 && count == (GET_MODE_BITSIZE (result_mode)
9160 - GET_MODE_BITSIZE (GET_MODE (varop))))
9162 /* C3 has the low-order C1 bits zero. */
9164 mask = (GET_MODE_MASK (mode)
9165 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9167 varop = simplify_and_const_int (NULL_RTX, result_mode,
9168 XEXP (varop, 0), mask);
9169 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9171 count = first_count;
9176 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9177 than C1 high-order bits equal to the sign bit, we can convert
9178 this to either an ASHIFT or an ASHIFTRT depending on the
9181 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9183 if (code == ASHIFTRT && first_code == ASHIFT
9184 && GET_MODE (varop) == shift_mode
9185 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9188 varop = XEXP (varop, 0);
9189 count -= first_count;
9199 /* There are some cases we can't do. If CODE is ASHIFTRT,
9200 we can only do this if FIRST_CODE is also ASHIFTRT.
9202 We can't do the case when CODE is ROTATE and FIRST_CODE is
9205 If the mode of this shift is not the mode of the outer shift,
9206 we can't do this if either shift is a right shift or ROTATE.
9208 Finally, we can't do any of these if the mode is too wide
9209 unless the codes are the same.
9211 Handle the case where the shift codes are the same
9214 if (code == first_code)
9216 if (GET_MODE (varop) != result_mode
9217 && (code == ASHIFTRT || code == LSHIFTRT
9221 count += first_count;
9222 varop = XEXP (varop, 0);
9226 if (code == ASHIFTRT
9227 || (code == ROTATE && first_code == ASHIFTRT)
9228 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9229 || (GET_MODE (varop) != result_mode
9230 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9231 || first_code == ROTATE
9232 || code == ROTATE)))
9235 /* To compute the mask to apply after the shift, shift the
9236 nonzero bits of the inner shift the same way the
9237 outer shift will. */
9239 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9242 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9245 /* Give up if we can't compute an outer operation to use. */
9247 || GET_CODE (mask_rtx) != CONST_INT
9248 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9250 result_mode, &complement_p))
9253 /* If the shifts are in the same direction, we add the
9254 counts. Otherwise, we subtract them. */
9255 if ((code == ASHIFTRT || code == LSHIFTRT)
9256 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9257 count += first_count;
9259 count -= first_count;
9261 /* If COUNT is positive, the new shift is usually CODE,
9262 except for the two exceptions below, in which case it is
9263 FIRST_CODE. If the count is negative, FIRST_CODE should
9266 && ((first_code == ROTATE && code == ASHIFT)
9267 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9270 code = first_code, count = -count;
9272 varop = XEXP (varop, 0);
9276 /* If we have (A << B << C) for any shift, we can convert this to
9277 (A << C << B). This wins if A is a constant. Only try this if
9278 B is not a constant. */
9280 else if (GET_CODE (varop) == code
9281 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9282 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9284 rtx new = simplify_const_binary_operation (code, mode,
9287 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
9294 /* Make this fit the case below. */
9295 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9296 GEN_INT (GET_MODE_MASK (mode)));
9302 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9303 with C the size of VAROP - 1 and the shift is logical if
9304 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9305 we have an (le X 0) operation. If we have an arithmetic shift
9306 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9307 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9309 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9310 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9311 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9312 && (code == LSHIFTRT || code == ASHIFTRT)
9313 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9314 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9317 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9320 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9321 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9326 /* If we have (shift (logical)), move the logical to the outside
9327 to allow it to possibly combine with another logical and the
9328 shift to combine with another shift. This also canonicalizes to
9329 what a ZERO_EXTRACT looks like. Also, some machines have
9330 (and (shift)) insns. */
9332 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9333 /* We can't do this if we have (ashiftrt (xor)) and the
9334 constant has its sign bit set in shift_mode. */
9335 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9336 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9338 && (new = simplify_const_binary_operation (code, result_mode,
9340 GEN_INT (count))) != 0
9341 && GET_CODE (new) == CONST_INT
9342 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9343 INTVAL (new), result_mode, &complement_p))
9345 varop = XEXP (varop, 0);
9349 /* If we can't do that, try to simplify the shift in each arm of the
9350 logical expression, make a new logical expression, and apply
9351 the inverse distributive law. This also can't be done
9352 for some (ashiftrt (xor)). */
9353 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9354 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9355 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9358 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9359 XEXP (varop, 0), count);
9360 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9361 XEXP (varop, 1), count);
9363 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9365 varop = apply_distributive_law (varop);
9373 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9374 says that the sign bit can be tested, FOO has mode MODE, C is
9375 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9376 that may be nonzero. */
9377 if (code == LSHIFTRT
9378 && XEXP (varop, 1) == const0_rtx
9379 && GET_MODE (XEXP (varop, 0)) == result_mode
9380 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9381 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9382 && STORE_FLAG_VALUE == -1
9383 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9384 && merge_outer_ops (&outer_op, &outer_const, XOR,
9385 (HOST_WIDE_INT) 1, result_mode,
9388 varop = XEXP (varop, 0);
9395 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9396 than the number of bits in the mode is equivalent to A. */
9397 if (code == LSHIFTRT
9398 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9399 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9401 varop = XEXP (varop, 0);
9406 /* NEG commutes with ASHIFT since it is multiplication. Move the
9407 NEG outside to allow shifts to combine. */
9409 && merge_outer_ops (&outer_op, &outer_const, NEG,
9410 (HOST_WIDE_INT) 0, result_mode,
9413 varop = XEXP (varop, 0);
9419 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9420 is one less than the number of bits in the mode is
9421 equivalent to (xor A 1). */
9422 if (code == LSHIFTRT
9423 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9424 && XEXP (varop, 1) == constm1_rtx
9425 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9426 && merge_outer_ops (&outer_op, &outer_const, XOR,
9427 (HOST_WIDE_INT) 1, result_mode,
9431 varop = XEXP (varop, 0);
9435 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9436 that might be nonzero in BAR are those being shifted out and those
9437 bits are known zero in FOO, we can replace the PLUS with FOO.
9438 Similarly in the other operand order. This code occurs when
9439 we are computing the size of a variable-size array. */
9441 if ((code == ASHIFTRT || code == LSHIFTRT)
9442 && count < HOST_BITS_PER_WIDE_INT
9443 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9444 && (nonzero_bits (XEXP (varop, 1), result_mode)
9445 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9447 varop = XEXP (varop, 0);
9450 else if ((code == ASHIFTRT || code == LSHIFTRT)
9451 && count < HOST_BITS_PER_WIDE_INT
9452 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9453 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9455 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9456 & nonzero_bits (XEXP (varop, 1),
9459 varop = XEXP (varop, 1);
9463 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9465 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9466 && (new = simplify_const_binary_operation (ASHIFT, result_mode,
9468 GEN_INT (count))) != 0
9469 && GET_CODE (new) == CONST_INT
9470 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9471 INTVAL (new), result_mode, &complement_p))
9473 varop = XEXP (varop, 0);
9477 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9478 signbit', and attempt to change the PLUS to an XOR and move it to
9479 the outer operation as is done above in the AND/IOR/XOR case
9480 leg for shift(logical). See details in logical handling above
9481 for reasoning in doing so. */
9482 if (code == LSHIFTRT
9483 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9484 && mode_signbit_p (result_mode, XEXP (varop, 1))
9485 && (new = simplify_const_binary_operation (code, result_mode,
9487 GEN_INT (count))) != 0
9488 && GET_CODE (new) == CONST_INT
9489 && merge_outer_ops (&outer_op, &outer_const, XOR,
9490 INTVAL (new), result_mode, &complement_p))
9492 varop = XEXP (varop, 0);
9499 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9500 with C the size of VAROP - 1 and the shift is logical if
9501 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9502 we have a (gt X 0) operation. If the shift is arithmetic with
9503 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9504 we have a (neg (gt X 0)) operation. */
9506 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9507 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9508 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9509 && (code == LSHIFTRT || code == ASHIFTRT)
9510 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9511 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9512 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9515 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9518 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9519 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9526 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9527 if the truncate does not affect the value. */
9528 if (code == LSHIFTRT
9529 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9530 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9531 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9532 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9533 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9535 rtx varop_inner = XEXP (varop, 0);
9538 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9539 XEXP (varop_inner, 0),
9541 (count + INTVAL (XEXP (varop_inner, 1))));
9542 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9555 /* We need to determine what mode to do the shift in. If the shift is
9556 a right shift or ROTATE, we must always do it in the mode it was
9557 originally done in. Otherwise, we can do it in MODE, the widest mode
9558 encountered. The code we care about is that of the shift that will
9559 actually be done, not the shift that was originally requested. */
9561 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9562 ? result_mode : mode);
9564 /* We have now finished analyzing the shift. The result should be
9565 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9566 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9567 to the result of the shift. OUTER_CONST is the relevant constant,
9568 but we must turn off all bits turned off in the shift. */
9570 if (outer_op == UNKNOWN
9571 && orig_code == code && orig_count == count
9572 && varop == orig_varop
9573 && shift_mode == GET_MODE (varop))
9576 /* Make a SUBREG if necessary. If we can't make it, fail. */
9577 varop = gen_lowpart (shift_mode, varop);
9578 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9581 /* If we have an outer operation and we just made a shift, it is
9582 possible that we could have simplified the shift were it not
9583 for the outer operation. So try to do the simplification
9586 if (outer_op != UNKNOWN)
9587 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9592 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9594 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9595 turn off all the bits that the shift would have turned off. */
9596 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9597 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9598 GET_MODE_MASK (result_mode) >> orig_count);
9600 /* Do the remainder of the processing in RESULT_MODE. */
9601 x = gen_lowpart_or_truncate (result_mode, x);
9603 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9606 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9608 if (outer_op != UNKNOWN)
9610 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9611 outer_const = trunc_int_for_mode (outer_const, result_mode);
9613 if (outer_op == AND)
9614 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9615 else if (outer_op == SET)
9617 /* This means that we have determined that the result is
9618 equivalent to a constant. This should be rare. */
9619 if (!side_effects_p (x))
9620 x = GEN_INT (outer_const);
9622 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9623 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9625 x = simplify_gen_binary (outer_op, result_mode, x,
9626 GEN_INT (outer_const));
9632 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9633 The result of the shift is RESULT_MODE. If we cannot simplify it,
9634 return X or, if it is NULL, synthesize the expression with
9635 simplify_gen_binary. Otherwise, return a simplified value.
9637 The shift is normally computed in the widest mode we find in VAROP, as
9638 long as it isn't a different number of words than RESULT_MODE. Exceptions
9639 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9642 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9643 rtx varop, int count)
9645 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9650 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9651 if (GET_MODE (x) != result_mode)
9652 x = gen_lowpart (result_mode, x);
9657 /* Like recog, but we receive the address of a pointer to a new pattern.
9658 We try to match the rtx that the pointer points to.
9659 If that fails, we may try to modify or replace the pattern,
9660 storing the replacement into the same pointer object.
9662 Modifications include deletion or addition of CLOBBERs.
9664 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9665 the CLOBBERs are placed.
9667 The value is the final insn code from the pattern ultimately matched,
9671 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9674 int insn_code_number;
9675 int num_clobbers_to_add = 0;
9678 rtx old_notes, old_pat;
9680 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9681 we use to indicate that something didn't match. If we find such a
9682 thing, force rejection. */
9683 if (GET_CODE (pat) == PARALLEL)
9684 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9685 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9686 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9689 old_pat = PATTERN (insn);
9690 old_notes = REG_NOTES (insn);
9691 PATTERN (insn) = pat;
9692 REG_NOTES (insn) = 0;
9694 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9695 if (dump_file && (dump_flags & TDF_DETAILS))
9697 if (insn_code_number < 0)
9698 fputs ("Failed to match this instruction:\n", dump_file);
9700 fputs ("Successfully matched this instruction:\n", dump_file);
9701 print_rtl_single (dump_file, pat);
9704 /* If it isn't, there is the possibility that we previously had an insn
9705 that clobbered some register as a side effect, but the combined
9706 insn doesn't need to do that. So try once more without the clobbers
9707 unless this represents an ASM insn. */
9709 if (insn_code_number < 0 && ! check_asm_operands (pat)
9710 && GET_CODE (pat) == PARALLEL)
9714 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9715 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9718 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9722 SUBST_INT (XVECLEN (pat, 0), pos);
9725 pat = XVECEXP (pat, 0, 0);
9727 PATTERN (insn) = pat;
9728 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9729 if (dump_file && (dump_flags & TDF_DETAILS))
9731 if (insn_code_number < 0)
9732 fputs ("Failed to match this instruction:\n", dump_file);
9734 fputs ("Successfully matched this instruction:\n", dump_file);
9735 print_rtl_single (dump_file, pat);
9738 PATTERN (insn) = old_pat;
9739 REG_NOTES (insn) = old_notes;
9741 /* Recognize all noop sets, these will be killed by followup pass. */
9742 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9743 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9745 /* If we had any clobbers to add, make a new pattern than contains
9746 them. Then check to make sure that all of them are dead. */
9747 if (num_clobbers_to_add)
9749 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9750 rtvec_alloc (GET_CODE (pat) == PARALLEL
9752 + num_clobbers_to_add)
9753 : num_clobbers_to_add + 1));
9755 if (GET_CODE (pat) == PARALLEL)
9756 for (i = 0; i < XVECLEN (pat, 0); i++)
9757 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9759 XVECEXP (newpat, 0, 0) = pat;
9761 add_clobbers (newpat, insn_code_number);
9763 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9764 i < XVECLEN (newpat, 0); i++)
9766 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9767 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9769 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9771 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9772 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9773 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9782 return insn_code_number;
9785 /* Like gen_lowpart_general but for use by combine. In combine it
9786 is not possible to create any new pseudoregs. However, it is
9787 safe to create invalid memory addresses, because combine will
9788 try to recognize them and all they will do is make the combine
9791 If for some reason this cannot do its job, an rtx
9792 (clobber (const_int 0)) is returned.
9793 An insn containing that will not be recognized. */
9796 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9798 enum machine_mode imode = GET_MODE (x);
9799 unsigned int osize = GET_MODE_SIZE (omode);
9800 unsigned int isize = GET_MODE_SIZE (imode);
9806 /* Return identity if this is a CONST or symbolic reference. */
9808 && (GET_CODE (x) == CONST
9809 || GET_CODE (x) == SYMBOL_REF
9810 || GET_CODE (x) == LABEL_REF))
9813 /* We can only support MODE being wider than a word if X is a
9814 constant integer or has a mode the same size. */
9815 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9816 && ! ((imode == VOIDmode
9817 && (GET_CODE (x) == CONST_INT
9818 || GET_CODE (x) == CONST_DOUBLE))
9822 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9823 won't know what to do. So we will strip off the SUBREG here and
9824 process normally. */
9825 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9829 /* For use in case we fall down into the address adjustments
9830 further below, we need to adjust the known mode and size of
9831 x; imode and isize, since we just adjusted x. */
9832 imode = GET_MODE (x);
9837 isize = GET_MODE_SIZE (imode);
9840 result = gen_lowpart_common (omode, x);
9849 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9851 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9854 /* If we want to refer to something bigger than the original memref,
9855 generate a paradoxical subreg instead. That will force a reload
9856 of the original memref X. */
9858 return gen_rtx_SUBREG (omode, x, 0);
9860 if (WORDS_BIG_ENDIAN)
9861 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9863 /* Adjust the address so that the address-after-the-data is
9865 if (BYTES_BIG_ENDIAN)
9866 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9868 return adjust_address_nv (x, omode, offset);
9871 /* If X is a comparison operator, rewrite it in a new mode. This
9872 probably won't match, but may allow further simplifications. */
9873 else if (COMPARISON_P (x))
9874 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9876 /* If we couldn't simplify X any other way, just enclose it in a
9877 SUBREG. Normally, this SUBREG won't match, but some patterns may
9878 include an explicit SUBREG or we may simplify it further in combine. */
9884 offset = subreg_lowpart_offset (omode, imode);
9885 if (imode == VOIDmode)
9887 imode = int_mode_for_mode (omode);
9888 x = gen_lowpart_common (imode, x);
9892 res = simplify_gen_subreg (omode, x, imode, offset);
9898 return gen_rtx_CLOBBER (imode, const0_rtx);
9901 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9902 comparison code that will be tested.
9904 The result is a possibly different comparison code to use. *POP0 and
9905 *POP1 may be updated.
9907 It is possible that we might detect that a comparison is either always
9908 true or always false. However, we do not perform general constant
9909 folding in combine, so this knowledge isn't useful. Such tautologies
9910 should have been detected earlier. Hence we ignore all such cases. */
9912 static enum rtx_code
9913 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9919 enum machine_mode mode, tmode;
9921 /* Try a few ways of applying the same transformation to both operands. */
9924 #ifndef WORD_REGISTER_OPERATIONS
9925 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9926 so check specially. */
9927 if (code != GTU && code != GEU && code != LTU && code != LEU
9928 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9929 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9930 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9931 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9932 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9933 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9934 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9935 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9936 && XEXP (op0, 1) == XEXP (op1, 1)
9937 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9938 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9939 && (INTVAL (XEXP (op0, 1))
9940 == (GET_MODE_BITSIZE (GET_MODE (op0))
9942 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9944 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9945 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9949 /* If both operands are the same constant shift, see if we can ignore the
9950 shift. We can if the shift is a rotate or if the bits shifted out of
9951 this shift are known to be zero for both inputs and if the type of
9952 comparison is compatible with the shift. */
9953 if (GET_CODE (op0) == GET_CODE (op1)
9954 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9955 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9956 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9957 && (code != GT && code != LT && code != GE && code != LE))
9958 || (GET_CODE (op0) == ASHIFTRT
9959 && (code != GTU && code != LTU
9960 && code != GEU && code != LEU)))
9961 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9962 && INTVAL (XEXP (op0, 1)) >= 0
9963 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9964 && XEXP (op0, 1) == XEXP (op1, 1))
9966 enum machine_mode mode = GET_MODE (op0);
9967 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9968 int shift_count = INTVAL (XEXP (op0, 1));
9970 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9971 mask &= (mask >> shift_count) << shift_count;
9972 else if (GET_CODE (op0) == ASHIFT)
9973 mask = (mask & (mask << shift_count)) >> shift_count;
9975 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9976 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9977 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9982 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9983 SUBREGs are of the same mode, and, in both cases, the AND would
9984 be redundant if the comparison was done in the narrower mode,
9985 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9986 and the operand's possibly nonzero bits are 0xffffff01; in that case
9987 if we only care about QImode, we don't need the AND). This case
9988 occurs if the output mode of an scc insn is not SImode and
9989 STORE_FLAG_VALUE == 1 (e.g., the 386).
9991 Similarly, check for a case where the AND's are ZERO_EXTEND
9992 operations from some narrower mode even though a SUBREG is not
9995 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9996 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9997 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9999 rtx inner_op0 = XEXP (op0, 0);
10000 rtx inner_op1 = XEXP (op1, 0);
10001 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10002 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10005 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10006 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10007 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10008 && (GET_MODE (SUBREG_REG (inner_op0))
10009 == GET_MODE (SUBREG_REG (inner_op1)))
10010 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10011 <= HOST_BITS_PER_WIDE_INT)
10012 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10013 GET_MODE (SUBREG_REG (inner_op0)))))
10014 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10015 GET_MODE (SUBREG_REG (inner_op1))))))
10017 op0 = SUBREG_REG (inner_op0);
10018 op1 = SUBREG_REG (inner_op1);
10020 /* The resulting comparison is always unsigned since we masked
10021 off the original sign bit. */
10022 code = unsigned_condition (code);
10028 for (tmode = GET_CLASS_NARROWEST_MODE
10029 (GET_MODE_CLASS (GET_MODE (op0)));
10030 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10031 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10033 op0 = gen_lowpart (tmode, inner_op0);
10034 op1 = gen_lowpart (tmode, inner_op1);
10035 code = unsigned_condition (code);
10044 /* If both operands are NOT, we can strip off the outer operation
10045 and adjust the comparison code for swapped operands; similarly for
10046 NEG, except that this must be an equality comparison. */
10047 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10048 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10049 && (code == EQ || code == NE)))
10050 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10056 /* If the first operand is a constant, swap the operands and adjust the
10057 comparison code appropriately, but don't do this if the second operand
10058 is already a constant integer. */
10059 if (swap_commutative_operands_p (op0, op1))
10061 tem = op0, op0 = op1, op1 = tem;
10062 code = swap_condition (code);
10065 /* We now enter a loop during which we will try to simplify the comparison.
10066 For the most part, we only are concerned with comparisons with zero,
10067 but some things may really be comparisons with zero but not start
10068 out looking that way. */
10070 while (GET_CODE (op1) == CONST_INT)
10072 enum machine_mode mode = GET_MODE (op0);
10073 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10074 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10075 int equality_comparison_p;
10076 int sign_bit_comparison_p;
10077 int unsigned_comparison_p;
10078 HOST_WIDE_INT const_op;
10080 /* We only want to handle integral modes. This catches VOIDmode,
10081 CCmode, and the floating-point modes. An exception is that we
10082 can handle VOIDmode if OP0 is a COMPARE or a comparison
10085 if (GET_MODE_CLASS (mode) != MODE_INT
10086 && ! (mode == VOIDmode
10087 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10090 /* Get the constant we are comparing against and turn off all bits
10091 not on in our mode. */
10092 const_op = INTVAL (op1);
10093 if (mode != VOIDmode)
10094 const_op = trunc_int_for_mode (const_op, mode);
10095 op1 = GEN_INT (const_op);
10097 /* If we are comparing against a constant power of two and the value
10098 being compared can only have that single bit nonzero (e.g., it was
10099 `and'ed with that bit), we can replace this with a comparison
10102 && (code == EQ || code == NE || code == GE || code == GEU
10103 || code == LT || code == LTU)
10104 && mode_width <= HOST_BITS_PER_WIDE_INT
10105 && exact_log2 (const_op) >= 0
10106 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10108 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10109 op1 = const0_rtx, const_op = 0;
10112 /* Similarly, if we are comparing a value known to be either -1 or
10113 0 with -1, change it to the opposite comparison against zero. */
10116 && (code == EQ || code == NE || code == GT || code == LE
10117 || code == GEU || code == LTU)
10118 && num_sign_bit_copies (op0, mode) == mode_width)
10120 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10121 op1 = const0_rtx, const_op = 0;
10124 /* Do some canonicalizations based on the comparison code. We prefer
10125 comparisons against zero and then prefer equality comparisons.
10126 If we can reduce the size of a constant, we will do that too. */
10131 /* < C is equivalent to <= (C - 1) */
10135 op1 = GEN_INT (const_op);
10137 /* ... fall through to LE case below. */
10143 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10147 op1 = GEN_INT (const_op);
10151 /* If we are doing a <= 0 comparison on a value known to have
10152 a zero sign bit, we can replace this with == 0. */
10153 else if (const_op == 0
10154 && mode_width <= HOST_BITS_PER_WIDE_INT
10155 && (nonzero_bits (op0, mode)
10156 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10161 /* >= C is equivalent to > (C - 1). */
10165 op1 = GEN_INT (const_op);
10167 /* ... fall through to GT below. */
10173 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10177 op1 = GEN_INT (const_op);
10181 /* If we are doing a > 0 comparison on a value known to have
10182 a zero sign bit, we can replace this with != 0. */
10183 else if (const_op == 0
10184 && mode_width <= HOST_BITS_PER_WIDE_INT
10185 && (nonzero_bits (op0, mode)
10186 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10191 /* < C is equivalent to <= (C - 1). */
10195 op1 = GEN_INT (const_op);
10197 /* ... fall through ... */
10200 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10201 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10202 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10204 const_op = 0, op1 = const0_rtx;
10212 /* unsigned <= 0 is equivalent to == 0 */
10216 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10217 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10218 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10220 const_op = 0, op1 = const0_rtx;
10226 /* >= C is equivalent to > (C - 1). */
10230 op1 = GEN_INT (const_op);
10232 /* ... fall through ... */
10235 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10236 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10237 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10239 const_op = 0, op1 = const0_rtx;
10247 /* unsigned > 0 is equivalent to != 0 */
10251 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10252 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10253 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10255 const_op = 0, op1 = const0_rtx;
10264 /* Compute some predicates to simplify code below. */
10266 equality_comparison_p = (code == EQ || code == NE);
10267 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10268 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10271 /* If this is a sign bit comparison and we can do arithmetic in
10272 MODE, say that we will only be needing the sign bit of OP0. */
10273 if (sign_bit_comparison_p
10274 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10275 op0 = force_to_mode (op0, mode,
10277 << (GET_MODE_BITSIZE (mode) - 1)),
10280 /* Now try cases based on the opcode of OP0. If none of the cases
10281 does a "continue", we exit this loop immediately after the
10284 switch (GET_CODE (op0))
10287 /* If we are extracting a single bit from a variable position in
10288 a constant that has only a single bit set and are comparing it
10289 with zero, we can convert this into an equality comparison
10290 between the position and the location of the single bit. */
10291 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10292 have already reduced the shift count modulo the word size. */
10293 if (!SHIFT_COUNT_TRUNCATED
10294 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10295 && XEXP (op0, 1) == const1_rtx
10296 && equality_comparison_p && const_op == 0
10297 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10299 if (BITS_BIG_ENDIAN)
10301 enum machine_mode new_mode
10302 = mode_for_extraction (EP_extzv, 1);
10303 if (new_mode == MAX_MACHINE_MODE)
10304 i = BITS_PER_WORD - 1 - i;
10308 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10312 op0 = XEXP (op0, 2);
10316 /* Result is nonzero iff shift count is equal to I. */
10317 code = reverse_condition (code);
10321 /* ... fall through ... */
10324 tem = expand_compound_operation (op0);
10333 /* If testing for equality, we can take the NOT of the constant. */
10334 if (equality_comparison_p
10335 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10337 op0 = XEXP (op0, 0);
10342 /* If just looking at the sign bit, reverse the sense of the
10344 if (sign_bit_comparison_p)
10346 op0 = XEXP (op0, 0);
10347 code = (code == GE ? LT : GE);
10353 /* If testing for equality, we can take the NEG of the constant. */
10354 if (equality_comparison_p
10355 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10357 op0 = XEXP (op0, 0);
10362 /* The remaining cases only apply to comparisons with zero. */
10366 /* When X is ABS or is known positive,
10367 (neg X) is < 0 if and only if X != 0. */
10369 if (sign_bit_comparison_p
10370 && (GET_CODE (XEXP (op0, 0)) == ABS
10371 || (mode_width <= HOST_BITS_PER_WIDE_INT
10372 && (nonzero_bits (XEXP (op0, 0), mode)
10373 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10375 op0 = XEXP (op0, 0);
10376 code = (code == LT ? NE : EQ);
10380 /* If we have NEG of something whose two high-order bits are the
10381 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10382 if (num_sign_bit_copies (op0, mode) >= 2)
10384 op0 = XEXP (op0, 0);
10385 code = swap_condition (code);
10391 /* If we are testing equality and our count is a constant, we
10392 can perform the inverse operation on our RHS. */
10393 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10394 && (tem = simplify_binary_operation (ROTATERT, mode,
10395 op1, XEXP (op0, 1))) != 0)
10397 op0 = XEXP (op0, 0);
10402 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10403 a particular bit. Convert it to an AND of a constant of that
10404 bit. This will be converted into a ZERO_EXTRACT. */
10405 if (const_op == 0 && sign_bit_comparison_p
10406 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10407 && mode_width <= HOST_BITS_PER_WIDE_INT)
10409 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10412 - INTVAL (XEXP (op0, 1)))));
10413 code = (code == LT ? NE : EQ);
10417 /* Fall through. */
10420 /* ABS is ignorable inside an equality comparison with zero. */
10421 if (const_op == 0 && equality_comparison_p)
10423 op0 = XEXP (op0, 0);
10429 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10430 (compare FOO CONST) if CONST fits in FOO's mode and we
10431 are either testing inequality or have an unsigned
10432 comparison with ZERO_EXTEND or a signed comparison with
10433 SIGN_EXTEND. But don't do it if we don't have a compare
10434 insn of the given mode, since we'd have to revert it
10435 later on, and then we wouldn't know whether to sign- or
10437 mode = GET_MODE (XEXP (op0, 0));
10438 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10439 && ! unsigned_comparison_p
10440 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10441 && ((unsigned HOST_WIDE_INT) const_op
10442 < (((unsigned HOST_WIDE_INT) 1
10443 << (GET_MODE_BITSIZE (mode) - 1))))
10444 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10446 op0 = XEXP (op0, 0);
10452 /* Check for the case where we are comparing A - C1 with C2, that is
10454 (subreg:MODE (plus (A) (-C1))) op (C2)
10456 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10457 comparison in the wider mode. One of the following two conditions
10458 must be true in order for this to be valid:
10460 1. The mode extension results in the same bit pattern being added
10461 on both sides and the comparison is equality or unsigned. As
10462 C2 has been truncated to fit in MODE, the pattern can only be
10465 2. The mode extension results in the sign bit being copied on
10468 The difficulty here is that we have predicates for A but not for
10469 (A - C1) so we need to check that C1 is within proper bounds so
10470 as to perturbate A as little as possible. */
10472 if (mode_width <= HOST_BITS_PER_WIDE_INT
10473 && subreg_lowpart_p (op0)
10474 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10475 && GET_CODE (SUBREG_REG (op0)) == PLUS
10476 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10478 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10479 rtx a = XEXP (SUBREG_REG (op0), 0);
10480 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10483 && (unsigned HOST_WIDE_INT) c1
10484 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10485 && (equality_comparison_p || unsigned_comparison_p)
10486 /* (A - C1) zero-extends if it is positive and sign-extends
10487 if it is negative, C2 both zero- and sign-extends. */
10488 && ((0 == (nonzero_bits (a, inner_mode)
10489 & ~GET_MODE_MASK (mode))
10491 /* (A - C1) sign-extends if it is positive and 1-extends
10492 if it is negative, C2 both sign- and 1-extends. */
10493 || (num_sign_bit_copies (a, inner_mode)
10494 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10497 || ((unsigned HOST_WIDE_INT) c1
10498 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10499 /* (A - C1) always sign-extends, like C2. */
10500 && num_sign_bit_copies (a, inner_mode)
10501 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10502 - (mode_width - 1))))
10504 op0 = SUBREG_REG (op0);
10509 /* If the inner mode is narrower and we are extracting the low part,
10510 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10511 if (subreg_lowpart_p (op0)
10512 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10513 /* Fall through */ ;
10517 /* ... fall through ... */
10520 mode = GET_MODE (XEXP (op0, 0));
10521 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10522 && (unsigned_comparison_p || equality_comparison_p)
10523 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10524 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10525 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10527 op0 = XEXP (op0, 0);
10533 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10534 this for equality comparisons due to pathological cases involving
10536 if (equality_comparison_p
10537 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10538 op1, XEXP (op0, 1))))
10540 op0 = XEXP (op0, 0);
10545 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10546 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10547 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10549 op0 = XEXP (XEXP (op0, 0), 0);
10550 code = (code == LT ? EQ : NE);
10556 /* We used to optimize signed comparisons against zero, but that
10557 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10558 arrive here as equality comparisons, or (GEU, LTU) are
10559 optimized away. No need to special-case them. */
10561 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10562 (eq B (minus A C)), whichever simplifies. We can only do
10563 this for equality comparisons due to pathological cases involving
10565 if (equality_comparison_p
10566 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10567 XEXP (op0, 1), op1)))
10569 op0 = XEXP (op0, 0);
10574 if (equality_comparison_p
10575 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10576 XEXP (op0, 0), op1)))
10578 op0 = XEXP (op0, 1);
10583 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10584 of bits in X minus 1, is one iff X > 0. */
10585 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10586 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10587 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10589 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10591 op0 = XEXP (op0, 1);
10592 code = (code == GE ? LE : GT);
10598 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10599 if C is zero or B is a constant. */
10600 if (equality_comparison_p
10601 && 0 != (tem = simplify_binary_operation (XOR, mode,
10602 XEXP (op0, 1), op1)))
10604 op0 = XEXP (op0, 0);
10611 case UNEQ: case LTGT:
10612 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10613 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10614 case UNORDERED: case ORDERED:
10615 /* We can't do anything if OP0 is a condition code value, rather
10616 than an actual data value. */
10618 || CC0_P (XEXP (op0, 0))
10619 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10622 /* Get the two operands being compared. */
10623 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10624 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10626 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10628 /* Check for the cases where we simply want the result of the
10629 earlier test or the opposite of that result. */
10630 if (code == NE || code == EQ
10631 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10632 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10633 && (STORE_FLAG_VALUE
10634 & (((HOST_WIDE_INT) 1
10635 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10636 && (code == LT || code == GE)))
10638 enum rtx_code new_code;
10639 if (code == LT || code == NE)
10640 new_code = GET_CODE (op0);
10642 new_code = reversed_comparison_code (op0, NULL);
10644 if (new_code != UNKNOWN)
10655 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10657 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10658 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10659 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10661 op0 = XEXP (op0, 1);
10662 code = (code == GE ? GT : LE);
10668 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10669 will be converted to a ZERO_EXTRACT later. */
10670 if (const_op == 0 && equality_comparison_p
10671 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10672 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10674 op0 = simplify_and_const_int
10675 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10677 XEXP (XEXP (op0, 0), 1)),
10678 (HOST_WIDE_INT) 1);
10682 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10683 zero and X is a comparison and C1 and C2 describe only bits set
10684 in STORE_FLAG_VALUE, we can compare with X. */
10685 if (const_op == 0 && equality_comparison_p
10686 && mode_width <= HOST_BITS_PER_WIDE_INT
10687 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10688 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10689 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10690 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10691 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10693 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10694 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10695 if ((~STORE_FLAG_VALUE & mask) == 0
10696 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10697 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10698 && COMPARISON_P (tem))))
10700 op0 = XEXP (XEXP (op0, 0), 0);
10705 /* If we are doing an equality comparison of an AND of a bit equal
10706 to the sign bit, replace this with a LT or GE comparison of
10707 the underlying value. */
10708 if (equality_comparison_p
10710 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10711 && mode_width <= HOST_BITS_PER_WIDE_INT
10712 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10713 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10715 op0 = XEXP (op0, 0);
10716 code = (code == EQ ? GE : LT);
10720 /* If this AND operation is really a ZERO_EXTEND from a narrower
10721 mode, the constant fits within that mode, and this is either an
10722 equality or unsigned comparison, try to do this comparison in
10727 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10728 -> (ne:DI (reg:SI 4) (const_int 0))
10730 unless TRULY_NOOP_TRUNCATION allows it or the register is
10731 known to hold a value of the required mode the
10732 transformation is invalid. */
10733 if ((equality_comparison_p || unsigned_comparison_p)
10734 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10735 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10736 & GET_MODE_MASK (mode))
10738 && const_op >> i == 0
10739 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10740 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10741 GET_MODE_BITSIZE (GET_MODE (op0)))
10742 || (REG_P (XEXP (op0, 0))
10743 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10745 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10749 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10750 fits in both M1 and M2 and the SUBREG is either paradoxical
10751 or represents the low part, permute the SUBREG and the AND
10753 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10755 unsigned HOST_WIDE_INT c1;
10756 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10757 /* Require an integral mode, to avoid creating something like
10759 if (SCALAR_INT_MODE_P (tmode)
10760 /* It is unsafe to commute the AND into the SUBREG if the
10761 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10762 not defined. As originally written the upper bits
10763 have a defined value due to the AND operation.
10764 However, if we commute the AND inside the SUBREG then
10765 they no longer have defined values and the meaning of
10766 the code has been changed. */
10768 #ifdef WORD_REGISTER_OPERATIONS
10769 || (mode_width > GET_MODE_BITSIZE (tmode)
10770 && mode_width <= BITS_PER_WORD)
10772 || (mode_width <= GET_MODE_BITSIZE (tmode)
10773 && subreg_lowpart_p (XEXP (op0, 0))))
10774 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10775 && mode_width <= HOST_BITS_PER_WIDE_INT
10776 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10777 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10778 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10780 && c1 != GET_MODE_MASK (tmode))
10782 op0 = simplify_gen_binary (AND, tmode,
10783 SUBREG_REG (XEXP (op0, 0)),
10784 gen_int_mode (c1, tmode));
10785 op0 = gen_lowpart (mode, op0);
10790 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10791 if (const_op == 0 && equality_comparison_p
10792 && XEXP (op0, 1) == const1_rtx
10793 && GET_CODE (XEXP (op0, 0)) == NOT)
10795 op0 = simplify_and_const_int
10796 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10797 code = (code == NE ? EQ : NE);
10801 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10802 (eq (and (lshiftrt X) 1) 0).
10803 Also handle the case where (not X) is expressed using xor. */
10804 if (const_op == 0 && equality_comparison_p
10805 && XEXP (op0, 1) == const1_rtx
10806 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10808 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10809 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10811 if (GET_CODE (shift_op) == NOT
10812 || (GET_CODE (shift_op) == XOR
10813 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10814 && GET_CODE (shift_count) == CONST_INT
10815 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10816 && (INTVAL (XEXP (shift_op, 1))
10817 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10819 op0 = simplify_and_const_int
10821 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10822 (HOST_WIDE_INT) 1);
10823 code = (code == NE ? EQ : NE);
10830 /* If we have (compare (ashift FOO N) (const_int C)) and
10831 the high order N bits of FOO (N+1 if an inequality comparison)
10832 are known to be zero, we can do this by comparing FOO with C
10833 shifted right N bits so long as the low-order N bits of C are
10835 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10836 && INTVAL (XEXP (op0, 1)) >= 0
10837 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10838 < HOST_BITS_PER_WIDE_INT)
10840 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10841 && mode_width <= HOST_BITS_PER_WIDE_INT
10842 && (nonzero_bits (XEXP (op0, 0), mode)
10843 & ~(mask >> (INTVAL (XEXP (op0, 1))
10844 + ! equality_comparison_p))) == 0)
10846 /* We must perform a logical shift, not an arithmetic one,
10847 as we want the top N bits of C to be zero. */
10848 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10850 temp >>= INTVAL (XEXP (op0, 1));
10851 op1 = gen_int_mode (temp, mode);
10852 op0 = XEXP (op0, 0);
10856 /* If we are doing a sign bit comparison, it means we are testing
10857 a particular bit. Convert it to the appropriate AND. */
10858 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10859 && mode_width <= HOST_BITS_PER_WIDE_INT)
10861 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10864 - INTVAL (XEXP (op0, 1)))));
10865 code = (code == LT ? NE : EQ);
10869 /* If this an equality comparison with zero and we are shifting
10870 the low bit to the sign bit, we can convert this to an AND of the
10872 if (const_op == 0 && equality_comparison_p
10873 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10874 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10877 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10878 (HOST_WIDE_INT) 1);
10884 /* If this is an equality comparison with zero, we can do this
10885 as a logical shift, which might be much simpler. */
10886 if (equality_comparison_p && const_op == 0
10887 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10889 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10891 INTVAL (XEXP (op0, 1)));
10895 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10896 do the comparison in a narrower mode. */
10897 if (! unsigned_comparison_p
10898 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10899 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10900 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10901 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10902 MODE_INT, 1)) != BLKmode
10903 && (((unsigned HOST_WIDE_INT) const_op
10904 + (GET_MODE_MASK (tmode) >> 1) + 1)
10905 <= GET_MODE_MASK (tmode)))
10907 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10911 /* Likewise if OP0 is a PLUS of a sign extension with a
10912 constant, which is usually represented with the PLUS
10913 between the shifts. */
10914 if (! unsigned_comparison_p
10915 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10916 && GET_CODE (XEXP (op0, 0)) == PLUS
10917 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10918 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10919 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10920 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10921 MODE_INT, 1)) != BLKmode
10922 && (((unsigned HOST_WIDE_INT) const_op
10923 + (GET_MODE_MASK (tmode) >> 1) + 1)
10924 <= GET_MODE_MASK (tmode)))
10926 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10927 rtx add_const = XEXP (XEXP (op0, 0), 1);
10928 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10929 add_const, XEXP (op0, 1));
10931 op0 = simplify_gen_binary (PLUS, tmode,
10932 gen_lowpart (tmode, inner),
10937 /* ... fall through ... */
10939 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10940 the low order N bits of FOO are known to be zero, we can do this
10941 by comparing FOO with C shifted left N bits so long as no
10942 overflow occurs. */
10943 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10944 && INTVAL (XEXP (op0, 1)) >= 0
10945 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10946 && mode_width <= HOST_BITS_PER_WIDE_INT
10947 && (nonzero_bits (XEXP (op0, 0), mode)
10948 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10949 && (((unsigned HOST_WIDE_INT) const_op
10950 + (GET_CODE (op0) != LSHIFTRT
10951 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10954 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10956 /* If the shift was logical, then we must make the condition
10958 if (GET_CODE (op0) == LSHIFTRT)
10959 code = unsigned_condition (code);
10961 const_op <<= INTVAL (XEXP (op0, 1));
10962 op1 = GEN_INT (const_op);
10963 op0 = XEXP (op0, 0);
10967 /* If we are using this shift to extract just the sign bit, we
10968 can replace this with an LT or GE comparison. */
10970 && (equality_comparison_p || sign_bit_comparison_p)
10971 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10972 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10975 op0 = XEXP (op0, 0);
10976 code = (code == NE || code == GT ? LT : GE);
10988 /* Now make any compound operations involved in this comparison. Then,
10989 check for an outmost SUBREG on OP0 that is not doing anything or is
10990 paradoxical. The latter transformation must only be performed when
10991 it is known that the "extra" bits will be the same in op0 and op1 or
10992 that they don't matter. There are three cases to consider:
10994 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10995 care bits and we can assume they have any convenient value. So
10996 making the transformation is safe.
10998 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10999 In this case the upper bits of op0 are undefined. We should not make
11000 the simplification in that case as we do not know the contents of
11003 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11004 UNKNOWN. In that case we know those bits are zeros or ones. We must
11005 also be sure that they are the same as the upper bits of op1.
11007 We can never remove a SUBREG for a non-equality comparison because
11008 the sign bit is in a different place in the underlying object. */
11010 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11011 op1 = make_compound_operation (op1, SET);
11013 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11014 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11015 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11016 && (code == NE || code == EQ))
11018 if (GET_MODE_SIZE (GET_MODE (op0))
11019 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11021 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11023 if (REG_P (SUBREG_REG (op0)))
11025 op0 = SUBREG_REG (op0);
11026 op1 = gen_lowpart (GET_MODE (op0), op1);
11029 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11030 <= HOST_BITS_PER_WIDE_INT)
11031 && (nonzero_bits (SUBREG_REG (op0),
11032 GET_MODE (SUBREG_REG (op0)))
11033 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11035 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11037 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11038 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11039 op0 = SUBREG_REG (op0), op1 = tem;
11043 /* We now do the opposite procedure: Some machines don't have compare
11044 insns in all modes. If OP0's mode is an integer mode smaller than a
11045 word and we can't do a compare in that mode, see if there is a larger
11046 mode for which we can do the compare. There are a number of cases in
11047 which we can use the wider mode. */
11049 mode = GET_MODE (op0);
11050 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11051 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11052 && ! have_insn_for (COMPARE, mode))
11053 for (tmode = GET_MODE_WIDER_MODE (mode);
11055 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11056 tmode = GET_MODE_WIDER_MODE (tmode))
11057 if (have_insn_for (COMPARE, tmode))
11061 /* If the only nonzero bits in OP0 and OP1 are those in the
11062 narrower mode and this is an equality or unsigned comparison,
11063 we can use the wider mode. Similarly for sign-extended
11064 values, in which case it is true for all comparisons. */
11065 zero_extended = ((code == EQ || code == NE
11066 || code == GEU || code == GTU
11067 || code == LEU || code == LTU)
11068 && (nonzero_bits (op0, tmode)
11069 & ~GET_MODE_MASK (mode)) == 0
11070 && ((GET_CODE (op1) == CONST_INT
11071 || (nonzero_bits (op1, tmode)
11072 & ~GET_MODE_MASK (mode)) == 0)));
11075 || ((num_sign_bit_copies (op0, tmode)
11076 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11077 - GET_MODE_BITSIZE (mode)))
11078 && (num_sign_bit_copies (op1, tmode)
11079 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11080 - GET_MODE_BITSIZE (mode)))))
11082 /* If OP0 is an AND and we don't have an AND in MODE either,
11083 make a new AND in the proper mode. */
11084 if (GET_CODE (op0) == AND
11085 && !have_insn_for (AND, mode))
11086 op0 = simplify_gen_binary (AND, tmode,
11087 gen_lowpart (tmode,
11089 gen_lowpart (tmode,
11092 op0 = gen_lowpart (tmode, op0);
11093 if (zero_extended && GET_CODE (op1) == CONST_INT)
11094 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11095 op1 = gen_lowpart (tmode, op1);
11099 /* If this is a test for negative, we can make an explicit
11100 test of the sign bit. */
11102 if (op1 == const0_rtx && (code == LT || code == GE)
11103 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11105 op0 = simplify_gen_binary (AND, tmode,
11106 gen_lowpart (tmode, op0),
11107 GEN_INT ((HOST_WIDE_INT) 1
11108 << (GET_MODE_BITSIZE (mode)
11110 code = (code == LT) ? NE : EQ;
11115 #ifdef CANONICALIZE_COMPARISON
11116 /* If this machine only supports a subset of valid comparisons, see if we
11117 can convert an unsupported one into a supported one. */
11118 CANONICALIZE_COMPARISON (code, op0, op1);
11127 /* Utility function for record_value_for_reg. Count number of
11132 enum rtx_code code = GET_CODE (x);
11136 if (GET_RTX_CLASS (code) == '2'
11137 || GET_RTX_CLASS (code) == 'c')
11139 rtx x0 = XEXP (x, 0);
11140 rtx x1 = XEXP (x, 1);
11143 return 1 + 2 * count_rtxs (x0);
11145 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11146 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11147 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11148 return 2 + 2 * count_rtxs (x0)
11149 + count_rtxs (x == XEXP (x1, 0)
11150 ? XEXP (x1, 1) : XEXP (x1, 0));
11152 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11153 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11154 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11155 return 2 + 2 * count_rtxs (x1)
11156 + count_rtxs (x == XEXP (x0, 0)
11157 ? XEXP (x0, 1) : XEXP (x0, 0));
11160 fmt = GET_RTX_FORMAT (code);
11161 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11163 ret += count_rtxs (XEXP (x, i));
11168 /* Utility function for following routine. Called when X is part of a value
11169 being stored into last_set_value. Sets last_set_table_tick
11170 for each register mentioned. Similar to mention_regs in cse.c */
11173 update_table_tick (rtx x)
11175 enum rtx_code code = GET_CODE (x);
11176 const char *fmt = GET_RTX_FORMAT (code);
11181 unsigned int regno = REGNO (x);
11182 unsigned int endregno = END_REGNO (x);
11185 for (r = regno; r < endregno; r++)
11187 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11188 rsp->last_set_table_tick = label_tick;
11194 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11195 /* Note that we can't have an "E" in values stored; see
11196 get_last_value_validate. */
11199 /* Check for identical subexpressions. If x contains
11200 identical subexpression we only have to traverse one of
11202 if (i == 0 && ARITHMETIC_P (x))
11204 /* Note that at this point x1 has already been
11206 rtx x0 = XEXP (x, 0);
11207 rtx x1 = XEXP (x, 1);
11209 /* If x0 and x1 are identical then there is no need to
11214 /* If x0 is identical to a subexpression of x1 then while
11215 processing x1, x0 has already been processed. Thus we
11216 are done with x. */
11217 if (ARITHMETIC_P (x1)
11218 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11221 /* If x1 is identical to a subexpression of x0 then we
11222 still have to process the rest of x0. */
11223 if (ARITHMETIC_P (x0)
11224 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11226 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11231 update_table_tick (XEXP (x, i));
11235 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11236 are saying that the register is clobbered and we no longer know its
11237 value. If INSN is zero, don't update reg_stat[].last_set; this is
11238 only permitted with VALUE also zero and is used to invalidate the
11242 record_value_for_reg (rtx reg, rtx insn, rtx value)
11244 unsigned int regno = REGNO (reg);
11245 unsigned int endregno = END_REGNO (reg);
11247 reg_stat_type *rsp;
11249 /* If VALUE contains REG and we have a previous value for REG, substitute
11250 the previous value. */
11251 if (value && insn && reg_overlap_mentioned_p (reg, value))
11255 /* Set things up so get_last_value is allowed to see anything set up to
11257 subst_low_luid = DF_INSN_LUID (insn);
11258 tem = get_last_value (reg);
11260 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11261 it isn't going to be useful and will take a lot of time to process,
11262 so just use the CLOBBER. */
11266 if (ARITHMETIC_P (tem)
11267 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11268 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11269 tem = XEXP (tem, 0);
11270 else if (count_occurrences (value, reg, 1) >= 2)
11272 /* If there are two or more occurrences of REG in VALUE,
11273 prevent the value from growing too much. */
11274 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11275 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11278 value = replace_rtx (copy_rtx (value), reg, tem);
11282 /* For each register modified, show we don't know its value, that
11283 we don't know about its bitwise content, that its value has been
11284 updated, and that we don't know the location of the death of the
11286 for (i = regno; i < endregno; i++)
11288 rsp = VEC_index (reg_stat_type, reg_stat, i);
11291 rsp->last_set = insn;
11293 rsp->last_set_value = 0;
11294 rsp->last_set_mode = 0;
11295 rsp->last_set_nonzero_bits = 0;
11296 rsp->last_set_sign_bit_copies = 0;
11297 rsp->last_death = 0;
11298 rsp->truncated_to_mode = 0;
11301 /* Mark registers that are being referenced in this value. */
11303 update_table_tick (value);
11305 /* Now update the status of each register being set.
11306 If someone is using this register in this block, set this register
11307 to invalid since we will get confused between the two lives in this
11308 basic block. This makes using this register always invalid. In cse, we
11309 scan the table to invalidate all entries using this register, but this
11310 is too much work for us. */
11312 for (i = regno; i < endregno; i++)
11314 rsp = VEC_index (reg_stat_type, reg_stat, i);
11315 rsp->last_set_label = label_tick;
11317 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11318 rsp->last_set_invalid = 1;
11320 rsp->last_set_invalid = 0;
11323 /* The value being assigned might refer to X (like in "x++;"). In that
11324 case, we must replace it with (clobber (const_int 0)) to prevent
11326 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11327 if (value && ! get_last_value_validate (&value, insn,
11328 rsp->last_set_label, 0))
11330 value = copy_rtx (value);
11331 if (! get_last_value_validate (&value, insn,
11332 rsp->last_set_label, 1))
11336 /* For the main register being modified, update the value, the mode, the
11337 nonzero bits, and the number of sign bit copies. */
11339 rsp->last_set_value = value;
11343 enum machine_mode mode = GET_MODE (reg);
11344 subst_low_luid = DF_INSN_LUID (insn);
11345 rsp->last_set_mode = mode;
11346 if (GET_MODE_CLASS (mode) == MODE_INT
11347 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11348 mode = nonzero_bits_mode;
11349 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11350 rsp->last_set_sign_bit_copies
11351 = num_sign_bit_copies (value, GET_MODE (reg));
11355 /* Called via note_stores from record_dead_and_set_regs to handle one
11356 SET or CLOBBER in an insn. DATA is the instruction in which the
11357 set is occurring. */
11360 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
11362 rtx record_dead_insn = (rtx) data;
11364 if (GET_CODE (dest) == SUBREG)
11365 dest = SUBREG_REG (dest);
11367 if (!record_dead_insn)
11370 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11376 /* If we are setting the whole register, we know its value. Otherwise
11377 show that we don't know the value. We can handle SUBREG in
11379 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11380 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11381 else if (GET_CODE (setter) == SET
11382 && GET_CODE (SET_DEST (setter)) == SUBREG
11383 && SUBREG_REG (SET_DEST (setter)) == dest
11384 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11385 && subreg_lowpart_p (SET_DEST (setter)))
11386 record_value_for_reg (dest, record_dead_insn,
11387 gen_lowpart (GET_MODE (dest),
11388 SET_SRC (setter)));
11390 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11392 else if (MEM_P (dest)
11393 /* Ignore pushes, they clobber nothing. */
11394 && ! push_operand (dest, GET_MODE (dest)))
11395 mem_last_set = DF_INSN_LUID (record_dead_insn);
11398 /* Update the records of when each REG was most recently set or killed
11399 for the things done by INSN. This is the last thing done in processing
11400 INSN in the combiner loop.
11402 We update reg_stat[], in particular fields last_set, last_set_value,
11403 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11404 last_death, and also the similar information mem_last_set (which insn
11405 most recently modified memory) and last_call_luid (which insn was the
11406 most recent subroutine call). */
11409 record_dead_and_set_regs (rtx insn)
11414 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11416 if (REG_NOTE_KIND (link) == REG_DEAD
11417 && REG_P (XEXP (link, 0)))
11419 unsigned int regno = REGNO (XEXP (link, 0));
11420 unsigned int endregno = END_REGNO (XEXP (link, 0));
11422 for (i = regno; i < endregno; i++)
11424 reg_stat_type *rsp;
11426 rsp = VEC_index (reg_stat_type, reg_stat, i);
11427 rsp->last_death = insn;
11430 else if (REG_NOTE_KIND (link) == REG_INC)
11431 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11436 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11437 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11439 reg_stat_type *rsp;
11441 rsp = VEC_index (reg_stat_type, reg_stat, i);
11442 rsp->last_set_invalid = 1;
11443 rsp->last_set = insn;
11444 rsp->last_set_value = 0;
11445 rsp->last_set_mode = 0;
11446 rsp->last_set_nonzero_bits = 0;
11447 rsp->last_set_sign_bit_copies = 0;
11448 rsp->last_death = 0;
11449 rsp->truncated_to_mode = 0;
11452 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11454 /* We can't combine into a call pattern. Remember, though, that
11455 the return value register is set at this LUID. We could
11456 still replace a register with the return value from the
11457 wrong subroutine call! */
11458 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11461 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11464 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11465 register present in the SUBREG, so for each such SUBREG go back and
11466 adjust nonzero and sign bit information of the registers that are
11467 known to have some zero/sign bits set.
11469 This is needed because when combine blows the SUBREGs away, the
11470 information on zero/sign bits is lost and further combines can be
11471 missed because of that. */
11474 record_promoted_value (rtx insn, rtx subreg)
11477 unsigned int regno = REGNO (SUBREG_REG (subreg));
11478 enum machine_mode mode = GET_MODE (subreg);
11480 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11483 for (links = LOG_LINKS (insn); links;)
11485 reg_stat_type *rsp;
11487 insn = XEXP (links, 0);
11488 set = single_set (insn);
11490 if (! set || !REG_P (SET_DEST (set))
11491 || REGNO (SET_DEST (set)) != regno
11492 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11494 links = XEXP (links, 1);
11498 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11499 if (rsp->last_set == insn)
11501 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11502 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11505 if (REG_P (SET_SRC (set)))
11507 regno = REGNO (SET_SRC (set));
11508 links = LOG_LINKS (insn);
11515 /* Check if X, a register, is known to contain a value already
11516 truncated to MODE. In this case we can use a subreg to refer to
11517 the truncated value even though in the generic case we would need
11518 an explicit truncation. */
11521 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11523 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11524 enum machine_mode truncated = rsp->truncated_to_mode;
11527 || rsp->truncation_label < label_tick_ebb_start)
11529 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11531 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11532 GET_MODE_BITSIZE (truncated)))
11537 /* X is a REG or a SUBREG. If X is some sort of a truncation record
11538 it. For non-TRULY_NOOP_TRUNCATION targets we might be able to turn
11539 a truncate into a subreg using this information. */
11542 record_truncated_value (rtx x)
11544 enum machine_mode truncated_mode;
11545 reg_stat_type *rsp;
11547 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11549 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11550 truncated_mode = GET_MODE (x);
11552 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11555 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11556 GET_MODE_BITSIZE (original_mode)))
11559 x = SUBREG_REG (x);
11561 /* ??? For hard-regs we now record everything. We might be able to
11562 optimize this using last_set_mode. */
11563 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11564 truncated_mode = GET_MODE (x);
11568 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11569 if (rsp->truncated_to_mode == 0
11570 || rsp->truncation_label < label_tick_ebb_start
11571 || (GET_MODE_SIZE (truncated_mode)
11572 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11574 rsp->truncated_to_mode = truncated_mode;
11575 rsp->truncation_label = label_tick;
11579 /* Scan X for promoted SUBREGs and truncated REGs. For each one
11580 found, note what it implies to the registers used in it. */
11583 check_conversions (rtx insn, rtx x)
11585 if (GET_CODE (x) == SUBREG || REG_P (x))
11587 if (GET_CODE (x) == SUBREG
11588 && SUBREG_PROMOTED_VAR_P (x)
11589 && REG_P (SUBREG_REG (x)))
11590 record_promoted_value (insn, x);
11592 record_truncated_value (x);
11596 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11599 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11603 check_conversions (insn, XEXP (x, i));
11607 if (XVEC (x, i) != 0)
11608 for (j = 0; j < XVECLEN (x, i); j++)
11609 check_conversions (insn, XVECEXP (x, i, j));
11615 /* Utility routine for the following function. Verify that all the registers
11616 mentioned in *LOC are valid when *LOC was part of a value set when
11617 label_tick == TICK. Return 0 if some are not.
11619 If REPLACE is nonzero, replace the invalid reference with
11620 (clobber (const_int 0)) and return 1. This replacement is useful because
11621 we often can get useful information about the form of a value (e.g., if
11622 it was produced by a shift that always produces -1 or 0) even though
11623 we don't know exactly what registers it was produced from. */
11626 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11629 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11630 int len = GET_RTX_LENGTH (GET_CODE (x));
11635 unsigned int regno = REGNO (x);
11636 unsigned int endregno = END_REGNO (x);
11639 for (j = regno; j < endregno; j++)
11641 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11642 if (rsp->last_set_invalid
11643 /* If this is a pseudo-register that was only set once and not
11644 live at the beginning of the function, it is always valid. */
11645 || (! (regno >= FIRST_PSEUDO_REGISTER
11646 && REG_N_SETS (regno) == 1
11647 && (!REGNO_REG_SET_P
11648 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11649 && rsp->last_set_label > tick))
11652 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11659 /* If this is a memory reference, make sure that there were
11660 no stores after it that might have clobbered the value. We don't
11661 have alias info, so we assume any store invalidates it. */
11662 else if (MEM_P (x) && !MEM_READONLY_P (x)
11663 && DF_INSN_LUID (insn) <= mem_last_set)
11666 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11670 for (i = 0; i < len; i++)
11674 /* Check for identical subexpressions. If x contains
11675 identical subexpression we only have to traverse one of
11677 if (i == 1 && ARITHMETIC_P (x))
11679 /* Note that at this point x0 has already been checked
11680 and found valid. */
11681 rtx x0 = XEXP (x, 0);
11682 rtx x1 = XEXP (x, 1);
11684 /* If x0 and x1 are identical then x is also valid. */
11688 /* If x1 is identical to a subexpression of x0 then
11689 while checking x0, x1 has already been checked. Thus
11690 it is valid and so as x. */
11691 if (ARITHMETIC_P (x0)
11692 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11695 /* If x0 is identical to a subexpression of x1 then x is
11696 valid iff the rest of x1 is valid. */
11697 if (ARITHMETIC_P (x1)
11698 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11700 get_last_value_validate (&XEXP (x1,
11701 x0 == XEXP (x1, 0) ? 1 : 0),
11702 insn, tick, replace);
11705 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11709 /* Don't bother with these. They shouldn't occur anyway. */
11710 else if (fmt[i] == 'E')
11714 /* If we haven't found a reason for it to be invalid, it is valid. */
11718 /* Get the last value assigned to X, if known. Some registers
11719 in the value may be replaced with (clobber (const_int 0)) if their value
11720 is known longer known reliably. */
11723 get_last_value (const_rtx x)
11725 unsigned int regno;
11727 reg_stat_type *rsp;
11729 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11730 then convert it to the desired mode. If this is a paradoxical SUBREG,
11731 we cannot predict what values the "extra" bits might have. */
11732 if (GET_CODE (x) == SUBREG
11733 && subreg_lowpart_p (x)
11734 && (GET_MODE_SIZE (GET_MODE (x))
11735 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11736 && (value = get_last_value (SUBREG_REG (x))) != 0)
11737 return gen_lowpart (GET_MODE (x), value);
11743 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11744 value = rsp->last_set_value;
11746 /* If we don't have a value, or if it isn't for this basic block and
11747 it's either a hard register, set more than once, or it's a live
11748 at the beginning of the function, return 0.
11750 Because if it's not live at the beginning of the function then the reg
11751 is always set before being used (is never used without being set).
11752 And, if it's set only once, and it's always set before use, then all
11753 uses must have the same last value, even if it's not from this basic
11757 || (rsp->last_set_label < label_tick_ebb_start
11758 && (regno < FIRST_PSEUDO_REGISTER
11759 || REG_N_SETS (regno) != 1
11761 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11764 /* If the value was set in a later insn than the ones we are processing,
11765 we can't use it even if the register was only set once. */
11766 if (rsp->last_set_label == label_tick
11767 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11770 /* If the value has all its registers valid, return it. */
11771 if (get_last_value_validate (&value, rsp->last_set,
11772 rsp->last_set_label, 0))
11775 /* Otherwise, make a copy and replace any invalid register with
11776 (clobber (const_int 0)). If that fails for some reason, return 0. */
11778 value = copy_rtx (value);
11779 if (get_last_value_validate (&value, rsp->last_set,
11780 rsp->last_set_label, 1))
11786 /* Return nonzero if expression X refers to a REG or to memory
11787 that is set in an instruction more recent than FROM_LUID. */
11790 use_crosses_set_p (rtx x, int from_luid)
11794 enum rtx_code code = GET_CODE (x);
11798 unsigned int regno = REGNO (x);
11799 unsigned endreg = END_REGNO (x);
11801 #ifdef PUSH_ROUNDING
11802 /* Don't allow uses of the stack pointer to be moved,
11803 because we don't know whether the move crosses a push insn. */
11804 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11807 for (; regno < endreg; regno++)
11809 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11811 && rsp->last_set_label == label_tick
11812 && DF_INSN_LUID (rsp->last_set) > from_luid)
11818 if (code == MEM && mem_last_set > from_luid)
11821 fmt = GET_RTX_FORMAT (code);
11823 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11828 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11829 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11832 else if (fmt[i] == 'e'
11833 && use_crosses_set_p (XEXP (x, i), from_luid))
11839 /* Define three variables used for communication between the following
11842 static unsigned int reg_dead_regno, reg_dead_endregno;
11843 static int reg_dead_flag;
11845 /* Function called via note_stores from reg_dead_at_p.
11847 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11848 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11851 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11853 unsigned int regno, endregno;
11858 regno = REGNO (dest);
11859 endregno = END_REGNO (dest);
11860 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11861 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11864 /* Return nonzero if REG is known to be dead at INSN.
11866 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11867 referencing REG, it is dead. If we hit a SET referencing REG, it is
11868 live. Otherwise, see if it is live or dead at the start of the basic
11869 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11870 must be assumed to be always live. */
11873 reg_dead_at_p (rtx reg, rtx insn)
11878 /* Set variables for reg_dead_at_p_1. */
11879 reg_dead_regno = REGNO (reg);
11880 reg_dead_endregno = END_REGNO (reg);
11884 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11885 we allow the machine description to decide whether use-and-clobber
11886 patterns are OK. */
11887 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11889 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11890 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11894 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11895 beginning of function. */
11896 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11897 insn = prev_nonnote_insn (insn))
11899 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11901 return reg_dead_flag == 1 ? 1 : 0;
11903 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11907 /* Get the basic block that we were in. */
11909 block = ENTRY_BLOCK_PTR->next_bb;
11912 FOR_EACH_BB (block)
11913 if (insn == BB_HEAD (block))
11916 if (block == EXIT_BLOCK_PTR)
11920 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11921 if (REGNO_REG_SET_P (df_get_live_in (block), i))
11927 /* Note hard registers in X that are used. */
11930 mark_used_regs_combine (rtx x)
11932 RTX_CODE code = GET_CODE (x);
11933 unsigned int regno;
11946 case ADDR_DIFF_VEC:
11949 /* CC0 must die in the insn after it is set, so we don't need to take
11950 special note of it here. */
11956 /* If we are clobbering a MEM, mark any hard registers inside the
11957 address as used. */
11958 if (MEM_P (XEXP (x, 0)))
11959 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11964 /* A hard reg in a wide mode may really be multiple registers.
11965 If so, mark all of them just like the first. */
11966 if (regno < FIRST_PSEUDO_REGISTER)
11968 /* None of this applies to the stack, frame or arg pointers. */
11969 if (regno == STACK_POINTER_REGNUM
11970 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11971 || regno == HARD_FRAME_POINTER_REGNUM
11973 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11974 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11976 || regno == FRAME_POINTER_REGNUM)
11979 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
11985 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11987 rtx testreg = SET_DEST (x);
11989 while (GET_CODE (testreg) == SUBREG
11990 || GET_CODE (testreg) == ZERO_EXTRACT
11991 || GET_CODE (testreg) == STRICT_LOW_PART)
11992 testreg = XEXP (testreg, 0);
11994 if (MEM_P (testreg))
11995 mark_used_regs_combine (XEXP (testreg, 0));
11997 mark_used_regs_combine (SET_SRC (x));
12005 /* Recursively scan the operands of this expression. */
12008 const char *fmt = GET_RTX_FORMAT (code);
12010 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12013 mark_used_regs_combine (XEXP (x, i));
12014 else if (fmt[i] == 'E')
12018 for (j = 0; j < XVECLEN (x, i); j++)
12019 mark_used_regs_combine (XVECEXP (x, i, j));
12025 /* Remove register number REGNO from the dead registers list of INSN.
12027 Return the note used to record the death, if there was one. */
12030 remove_death (unsigned int regno, rtx insn)
12032 rtx note = find_regno_note (insn, REG_DEAD, regno);
12035 remove_note (insn, note);
12040 /* For each register (hardware or pseudo) used within expression X, if its
12041 death is in an instruction with luid between FROM_LUID (inclusive) and
12042 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12043 list headed by PNOTES.
12045 That said, don't move registers killed by maybe_kill_insn.
12047 This is done when X is being merged by combination into TO_INSN. These
12048 notes will then be distributed as needed. */
12051 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12056 enum rtx_code code = GET_CODE (x);
12060 unsigned int regno = REGNO (x);
12061 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12063 /* Don't move the register if it gets killed in between from and to. */
12064 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12065 && ! reg_referenced_p (x, maybe_kill_insn))
12069 && DF_INSN_LUID (where_dead) >= from_luid
12070 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12072 rtx note = remove_death (regno, where_dead);
12074 /* It is possible for the call above to return 0. This can occur
12075 when last_death points to I2 or I1 that we combined with.
12076 In that case make a new note.
12078 We must also check for the case where X is a hard register
12079 and NOTE is a death note for a range of hard registers
12080 including X. In that case, we must put REG_DEAD notes for
12081 the remaining registers in place of NOTE. */
12083 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12084 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12085 > GET_MODE_SIZE (GET_MODE (x))))
12087 unsigned int deadregno = REGNO (XEXP (note, 0));
12088 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12089 unsigned int ourend = END_HARD_REGNO (x);
12092 for (i = deadregno; i < deadend; i++)
12093 if (i < regno || i >= ourend)
12094 REG_NOTES (where_dead)
12095 = gen_rtx_EXPR_LIST (REG_DEAD,
12097 REG_NOTES (where_dead));
12100 /* If we didn't find any note, or if we found a REG_DEAD note that
12101 covers only part of the given reg, and we have a multi-reg hard
12102 register, then to be safe we must check for REG_DEAD notes
12103 for each register other than the first. They could have
12104 their own REG_DEAD notes lying around. */
12105 else if ((note == 0
12107 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12108 < GET_MODE_SIZE (GET_MODE (x)))))
12109 && regno < FIRST_PSEUDO_REGISTER
12110 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12112 unsigned int ourend = END_HARD_REGNO (x);
12113 unsigned int i, offset;
12117 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12121 for (i = regno + offset; i < ourend; i++)
12122 move_deaths (regno_reg_rtx[i],
12123 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12126 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12128 XEXP (note, 1) = *pnotes;
12132 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12138 else if (GET_CODE (x) == SET)
12140 rtx dest = SET_DEST (x);
12142 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12144 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12145 that accesses one word of a multi-word item, some
12146 piece of everything register in the expression is used by
12147 this insn, so remove any old death. */
12148 /* ??? So why do we test for equality of the sizes? */
12150 if (GET_CODE (dest) == ZERO_EXTRACT
12151 || GET_CODE (dest) == STRICT_LOW_PART
12152 || (GET_CODE (dest) == SUBREG
12153 && (((GET_MODE_SIZE (GET_MODE (dest))
12154 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12155 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12156 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12158 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12162 /* If this is some other SUBREG, we know it replaces the entire
12163 value, so use that as the destination. */
12164 if (GET_CODE (dest) == SUBREG)
12165 dest = SUBREG_REG (dest);
12167 /* If this is a MEM, adjust deaths of anything used in the address.
12168 For a REG (the only other possibility), the entire value is
12169 being replaced so the old value is not used in this insn. */
12172 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12177 else if (GET_CODE (x) == CLOBBER)
12180 len = GET_RTX_LENGTH (code);
12181 fmt = GET_RTX_FORMAT (code);
12183 for (i = 0; i < len; i++)
12188 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12189 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12192 else if (fmt[i] == 'e')
12193 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12197 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12198 pattern of an insn. X must be a REG. */
12201 reg_bitfield_target_p (rtx x, rtx body)
12205 if (GET_CODE (body) == SET)
12207 rtx dest = SET_DEST (body);
12209 unsigned int regno, tregno, endregno, endtregno;
12211 if (GET_CODE (dest) == ZERO_EXTRACT)
12212 target = XEXP (dest, 0);
12213 else if (GET_CODE (dest) == STRICT_LOW_PART)
12214 target = SUBREG_REG (XEXP (dest, 0));
12218 if (GET_CODE (target) == SUBREG)
12219 target = SUBREG_REG (target);
12221 if (!REG_P (target))
12224 tregno = REGNO (target), regno = REGNO (x);
12225 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12226 return target == x;
12228 endtregno = end_hard_regno (GET_MODE (target), tregno);
12229 endregno = end_hard_regno (GET_MODE (x), regno);
12231 return endregno > tregno && regno < endtregno;
12234 else if (GET_CODE (body) == PARALLEL)
12235 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12236 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12242 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12243 as appropriate. I3 and I2 are the insns resulting from the combination
12244 insns including FROM (I2 may be zero).
12246 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12247 not need REG_DEAD notes because they are being substituted for. This
12248 saves searching in the most common cases.
12250 Each note in the list is either ignored or placed on some insns, depending
12251 on the type of note. */
12254 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12257 rtx note, next_note;
12260 for (note = notes; note; note = next_note)
12262 rtx place = 0, place2 = 0;
12264 next_note = XEXP (note, 1);
12265 switch (REG_NOTE_KIND (note))
12269 /* Doesn't matter much where we put this, as long as it's somewhere.
12270 It is preferable to keep these notes on branches, which is most
12271 likely to be i3. */
12275 case REG_VALUE_PROFILE:
12276 /* Just get rid of this note, as it is unused later anyway. */
12279 case REG_NON_LOCAL_GOTO:
12284 gcc_assert (i2 && JUMP_P (i2));
12289 case REG_EH_REGION:
12290 /* These notes must remain with the call or trapping instruction. */
12293 else if (i2 && CALL_P (i2))
12297 gcc_assert (flag_non_call_exceptions);
12298 if (may_trap_p (i3))
12300 else if (i2 && may_trap_p (i2))
12302 /* ??? Otherwise assume we've combined things such that we
12303 can now prove that the instructions can't trap. Drop the
12304 note in this case. */
12310 /* These notes must remain with the call. It should not be
12311 possible for both I2 and I3 to be a call. */
12316 gcc_assert (i2 && CALL_P (i2));
12322 /* Any clobbers for i3 may still exist, and so we must process
12323 REG_UNUSED notes from that insn.
12325 Any clobbers from i2 or i1 can only exist if they were added by
12326 recog_for_combine. In that case, recog_for_combine created the
12327 necessary REG_UNUSED notes. Trying to keep any original
12328 REG_UNUSED notes from these insns can cause incorrect output
12329 if it is for the same register as the original i3 dest.
12330 In that case, we will notice that the register is set in i3,
12331 and then add a REG_UNUSED note for the destination of i3, which
12332 is wrong. However, it is possible to have REG_UNUSED notes from
12333 i2 or i1 for register which were both used and clobbered, so
12334 we keep notes from i2 or i1 if they will turn into REG_DEAD
12337 /* If this register is set or clobbered in I3, put the note there
12338 unless there is one already. */
12339 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12341 if (from_insn != i3)
12344 if (! (REG_P (XEXP (note, 0))
12345 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12346 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12349 /* Otherwise, if this register is used by I3, then this register
12350 now dies here, so we must put a REG_DEAD note here unless there
12352 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12353 && ! (REG_P (XEXP (note, 0))
12354 ? find_regno_note (i3, REG_DEAD,
12355 REGNO (XEXP (note, 0)))
12356 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12358 PUT_REG_NOTE_KIND (note, REG_DEAD);
12366 /* These notes say something about results of an insn. We can
12367 only support them if they used to be on I3 in which case they
12368 remain on I3. Otherwise they are ignored.
12370 If the note refers to an expression that is not a constant, we
12371 must also ignore the note since we cannot tell whether the
12372 equivalence is still true. It might be possible to do
12373 slightly better than this (we only have a problem if I2DEST
12374 or I1DEST is present in the expression), but it doesn't
12375 seem worth the trouble. */
12377 if (from_insn == i3
12378 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12383 case REG_NO_CONFLICT:
12384 /* These notes say something about how a register is used. They must
12385 be present on any use of the register in I2 or I3. */
12386 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12389 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12399 /* This can show up in several ways -- either directly in the
12400 pattern, or hidden off in the constant pool with (or without?)
12401 a REG_EQUAL note. */
12402 /* ??? Ignore the without-reg_equal-note problem for now. */
12403 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12404 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12405 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12406 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12410 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12411 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12412 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12413 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12421 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
12422 a JUMP_LABEL instead or decrement LABEL_NUSES. */
12423 if (place && JUMP_P (place))
12425 rtx label = JUMP_LABEL (place);
12428 JUMP_LABEL (place) = XEXP (note, 0);
12431 gcc_assert (label == XEXP (note, 0));
12432 if (LABEL_P (label))
12433 LABEL_NUSES (label)--;
12437 if (place2 && JUMP_P (place2))
12439 rtx label = JUMP_LABEL (place2);
12442 JUMP_LABEL (place2) = XEXP (note, 0);
12445 gcc_assert (label == XEXP (note, 0));
12446 if (LABEL_P (label))
12447 LABEL_NUSES (label)--;
12454 /* This note says something about the value of a register prior
12455 to the execution of an insn. It is too much trouble to see
12456 if the note is still correct in all situations. It is better
12457 to simply delete it. */
12460 case REG_LIBCALL_ID:
12461 /* If the insn previously containing this note still exists,
12462 put it back where it was. Otherwise move it to the previous
12464 if (!NOTE_P (from_insn))
12467 place = prev_real_insn (from_insn);
12470 /* If the insn previously containing this note still exists,
12471 put it back where it was. Otherwise move it to the previous
12472 insn. Adjust the corresponding REG_LIBCALL note. */
12473 if (!NOTE_P (from_insn))
12477 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12478 place = prev_real_insn (from_insn);
12480 XEXP (tem, 0) = place;
12481 /* If we're deleting the last remaining instruction of a
12482 libcall sequence, don't add the notes. */
12483 else if (XEXP (note, 0) == from_insn)
12485 /* Don't add the dangling REG_RETVAL note. */
12492 /* This is handled similarly to REG_RETVAL. */
12493 if (!NOTE_P (from_insn))
12497 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12498 place = next_real_insn (from_insn);
12500 XEXP (tem, 0) = place;
12501 /* If we're deleting the last remaining instruction of a
12502 libcall sequence, don't add the notes. */
12503 else if (XEXP (note, 0) == from_insn)
12505 /* Don't add the dangling REG_LIBCALL note. */
12512 /* If we replaced the right hand side of FROM_INSN with a
12513 REG_EQUAL note, the original use of the dying register
12514 will not have been combined into I3 and I2. In such cases,
12515 FROM_INSN is guaranteed to be the first of the combined
12516 instructions, so we simply need to search back before
12517 FROM_INSN for the previous use or set of this register,
12518 then alter the notes there appropriately.
12520 If the register is used as an input in I3, it dies there.
12521 Similarly for I2, if it is nonzero and adjacent to I3.
12523 If the register is not used as an input in either I3 or I2
12524 and it is not one of the registers we were supposed to eliminate,
12525 there are two possibilities. We might have a non-adjacent I2
12526 or we might have somehow eliminated an additional register
12527 from a computation. For example, we might have had A & B where
12528 we discover that B will always be zero. In this case we will
12529 eliminate the reference to A.
12531 In both cases, we must search to see if we can find a previous
12532 use of A and put the death note there. */
12535 && from_insn == i2mod
12536 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12541 && CALL_P (from_insn)
12542 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12544 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12546 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12547 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12549 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12551 && reg_overlap_mentioned_p (XEXP (note, 0),
12553 || rtx_equal_p (XEXP (note, 0), elim_i1))
12560 basic_block bb = this_basic_block;
12562 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12564 if (! INSN_P (tem))
12566 if (tem == BB_HEAD (bb))
12571 /* If the register is being set at TEM, see if that is all
12572 TEM is doing. If so, delete TEM. Otherwise, make this
12573 into a REG_UNUSED note instead. Don't delete sets to
12574 global register vars. */
12575 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12576 || !global_regs[REGNO (XEXP (note, 0))])
12577 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12579 rtx set = single_set (tem);
12580 rtx inner_dest = 0;
12582 rtx cc0_setter = NULL_RTX;
12586 for (inner_dest = SET_DEST (set);
12587 (GET_CODE (inner_dest) == STRICT_LOW_PART
12588 || GET_CODE (inner_dest) == SUBREG
12589 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12590 inner_dest = XEXP (inner_dest, 0))
12593 /* Verify that it was the set, and not a clobber that
12594 modified the register.
12596 CC0 targets must be careful to maintain setter/user
12597 pairs. If we cannot delete the setter due to side
12598 effects, mark the user with an UNUSED note instead
12601 if (set != 0 && ! side_effects_p (SET_SRC (set))
12602 && rtx_equal_p (XEXP (note, 0), inner_dest)
12604 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12605 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12606 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12610 /* Move the notes and links of TEM elsewhere.
12611 This might delete other dead insns recursively.
12612 First set the pattern to something that won't use
12614 rtx old_notes = REG_NOTES (tem);
12616 PATTERN (tem) = pc_rtx;
12617 REG_NOTES (tem) = NULL;
12619 distribute_notes (old_notes, tem, tem, NULL_RTX,
12620 NULL_RTX, NULL_RTX);
12621 distribute_links (LOG_LINKS (tem));
12623 SET_INSN_DELETED (tem);
12626 /* Delete the setter too. */
12629 PATTERN (cc0_setter) = pc_rtx;
12630 old_notes = REG_NOTES (cc0_setter);
12631 REG_NOTES (cc0_setter) = NULL;
12633 distribute_notes (old_notes, cc0_setter,
12634 cc0_setter, NULL_RTX,
12635 NULL_RTX, NULL_RTX);
12636 distribute_links (LOG_LINKS (cc0_setter));
12638 SET_INSN_DELETED (cc0_setter);
12644 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12646 /* If there isn't already a REG_UNUSED note, put one
12647 here. Do not place a REG_DEAD note, even if
12648 the register is also used here; that would not
12649 match the algorithm used in lifetime analysis
12650 and can cause the consistency check in the
12651 scheduler to fail. */
12652 if (! find_regno_note (tem, REG_UNUSED,
12653 REGNO (XEXP (note, 0))))
12658 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12660 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12664 /* If we are doing a 3->2 combination, and we have a
12665 register which formerly died in i3 and was not used
12666 by i2, which now no longer dies in i3 and is used in
12667 i2 but does not die in i2, and place is between i2
12668 and i3, then we may need to move a link from place to
12670 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12672 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12673 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12675 rtx links = LOG_LINKS (place);
12676 LOG_LINKS (place) = 0;
12677 distribute_links (links);
12682 if (tem == BB_HEAD (bb))
12688 /* If the register is set or already dead at PLACE, we needn't do
12689 anything with this note if it is still a REG_DEAD note.
12690 We check here if it is set at all, not if is it totally replaced,
12691 which is what `dead_or_set_p' checks, so also check for it being
12694 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12696 unsigned int regno = REGNO (XEXP (note, 0));
12697 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12699 if (dead_or_set_p (place, XEXP (note, 0))
12700 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12702 /* Unless the register previously died in PLACE, clear
12703 last_death. [I no longer understand why this is
12705 if (rsp->last_death != place)
12706 rsp->last_death = 0;
12710 rsp->last_death = place;
12712 /* If this is a death note for a hard reg that is occupying
12713 multiple registers, ensure that we are still using all
12714 parts of the object. If we find a piece of the object
12715 that is unused, we must arrange for an appropriate REG_DEAD
12716 note to be added for it. However, we can't just emit a USE
12717 and tag the note to it, since the register might actually
12718 be dead; so we recourse, and the recursive call then finds
12719 the previous insn that used this register. */
12721 if (place && regno < FIRST_PSEUDO_REGISTER
12722 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12724 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12728 for (i = regno; i < endregno; i++)
12729 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12730 && ! find_regno_fusage (place, USE, i))
12731 || dead_or_set_regno_p (place, i))
12736 /* Put only REG_DEAD notes for pieces that are
12737 not already dead or set. */
12739 for (i = regno; i < endregno;
12740 i += hard_regno_nregs[i][reg_raw_mode[i]])
12742 rtx piece = regno_reg_rtx[i];
12743 basic_block bb = this_basic_block;
12745 if (! dead_or_set_p (place, piece)
12746 && ! reg_bitfield_target_p (piece,
12750 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12752 distribute_notes (new_note, place, place,
12753 NULL_RTX, NULL_RTX, NULL_RTX);
12755 else if (! refers_to_regno_p (i, i + 1,
12756 PATTERN (place), 0)
12757 && ! find_regno_fusage (place, USE, i))
12758 for (tem = PREV_INSN (place); ;
12759 tem = PREV_INSN (tem))
12761 if (! INSN_P (tem))
12763 if (tem == BB_HEAD (bb))
12767 if (dead_or_set_p (tem, piece)
12768 || reg_bitfield_target_p (piece,
12772 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12787 /* Any other notes should not be present at this point in the
12789 gcc_unreachable ();
12794 XEXP (note, 1) = REG_NOTES (place);
12795 REG_NOTES (place) = note;
12800 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12801 XEXP (note, 0), REG_NOTES (place2));
12805 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12806 I3, I2, and I1 to new locations. This is also called to add a link
12807 pointing at I3 when I3's destination is changed. */
12810 distribute_links (rtx links)
12812 rtx link, next_link;
12814 for (link = links; link; link = next_link)
12820 next_link = XEXP (link, 1);
12822 /* If the insn that this link points to is a NOTE or isn't a single
12823 set, ignore it. In the latter case, it isn't clear what we
12824 can do other than ignore the link, since we can't tell which
12825 register it was for. Such links wouldn't be used by combine
12828 It is not possible for the destination of the target of the link to
12829 have been changed by combine. The only potential of this is if we
12830 replace I3, I2, and I1 by I3 and I2. But in that case the
12831 destination of I2 also remains unchanged. */
12833 if (NOTE_P (XEXP (link, 0))
12834 || (set = single_set (XEXP (link, 0))) == 0)
12837 reg = SET_DEST (set);
12838 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12839 || GET_CODE (reg) == STRICT_LOW_PART)
12840 reg = XEXP (reg, 0);
12842 /* A LOG_LINK is defined as being placed on the first insn that uses
12843 a register and points to the insn that sets the register. Start
12844 searching at the next insn after the target of the link and stop
12845 when we reach a set of the register or the end of the basic block.
12847 Note that this correctly handles the link that used to point from
12848 I3 to I2. Also note that not much searching is typically done here
12849 since most links don't point very far away. */
12851 for (insn = NEXT_INSN (XEXP (link, 0));
12852 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12853 || BB_HEAD (this_basic_block->next_bb) != insn));
12854 insn = NEXT_INSN (insn))
12855 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12857 if (reg_referenced_p (reg, PATTERN (insn)))
12861 else if (CALL_P (insn)
12862 && find_reg_fusage (insn, USE, reg))
12867 else if (INSN_P (insn) && reg_set_p (reg, insn))
12870 /* If we found a place to put the link, place it there unless there
12871 is already a link to the same insn as LINK at that point. */
12877 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12878 if (XEXP (link2, 0) == XEXP (link, 0))
12883 XEXP (link, 1) = LOG_LINKS (place);
12884 LOG_LINKS (place) = link;
12886 /* Set added_links_insn to the earliest insn we added a
12888 if (added_links_insn == 0
12889 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12890 added_links_insn = place;
12896 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12897 Check whether the expression pointer to by LOC is a register or
12898 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12899 Otherwise return zero. */
12902 unmentioned_reg_p_1 (rtx *loc, void *expr)
12907 && (REG_P (x) || MEM_P (x))
12908 && ! reg_mentioned_p (x, (rtx) expr))
12913 /* Check for any register or memory mentioned in EQUIV that is not
12914 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12915 of EXPR where some registers may have been replaced by constants. */
12918 unmentioned_reg_p (rtx equiv, rtx expr)
12920 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12924 dump_combine_stats (FILE *file)
12928 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12929 combine_attempts, combine_merges, combine_extras, combine_successes);
12933 dump_combine_total_stats (FILE *file)
12937 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12938 total_attempts, total_merges, total_extras, total_successes);
12942 gate_handle_combine (void)
12944 return (optimize > 0);
12947 /* Try combining insns through substitution. */
12948 static unsigned int
12949 rest_of_handle_combine (void)
12951 int rebuild_jump_labels_after_combine;
12953 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
12954 df_note_add_problem ();
12957 regstat_init_n_sets_and_refs ();
12959 rebuild_jump_labels_after_combine
12960 = combine_instructions (get_insns (), max_reg_num ());
12962 /* Combining insns may have turned an indirect jump into a
12963 direct jump. Rebuild the JUMP_LABEL fields of jumping
12965 if (rebuild_jump_labels_after_combine)
12967 timevar_push (TV_JUMP);
12968 rebuild_jump_labels (get_insns ());
12970 timevar_pop (TV_JUMP);
12973 regstat_free_n_sets_and_refs ();
12977 struct tree_opt_pass pass_combine =
12979 "combine", /* name */
12980 gate_handle_combine, /* gate */
12981 rest_of_handle_combine, /* execute */
12984 0, /* static_pass_number */
12985 TV_COMBINE, /* tv_id */
12986 0, /* properties_required */
12987 0, /* properties_provided */
12988 0, /* properties_destroyed */
12989 0, /* todo_flags_start */
12992 TODO_ggc_collect, /* todo_flags_finish */