1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
108 /* Number of attempts to combine instructions in this function. */
110 static int combine_attempts;
112 /* Number of attempts that got as far as substitution in this function. */
114 static int combine_merges;
116 /* Number of instructions combined with added SETs in this function. */
118 static int combine_extras;
120 /* Number of instructions combined in this function. */
122 static int combine_successes;
124 /* Totals over entire compilation. */
126 static int total_attempts, total_merges, total_extras, total_successes;
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
139 static rtx i2mod_old_rhs;
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
143 static rtx i2mod_new_rhs;
145 typedef struct reg_stat_struct {
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
202 int last_set_table_tick;
204 /* Record the value of label_tick when the value for register n is placed in
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
214 unsigned HOST_WIDE_INT last_set_nonzero_bits;
215 char last_set_sign_bit_copies;
216 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
222 char last_set_invalid;
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
234 If an entry is zero, it means that we don't know anything special. */
236 unsigned char sign_bit_copies;
238 unsigned HOST_WIDE_INT nonzero_bits;
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
244 int truncation_label;
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
251 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
254 DEF_VEC_O(reg_stat_type);
255 DEF_VEC_ALLOC_O(reg_stat_type,heap);
257 static VEC(reg_stat_type,heap) *reg_stat;
259 /* Record the luid of the last insn that invalidated memory
260 (anything that writes memory, and subroutine calls, but not pushes). */
262 static int mem_last_set;
264 /* Record the luid of the last CALL_INSN
265 so we can tell whether a potential combination crosses any calls. */
267 static int last_call_luid;
269 /* When `subst' is called, this is the insn that is being modified
270 (by combining in a previous insn). The PATTERN of this insn
271 is still the old pattern partially modified and it should not be
272 looked at, but this may be used to examine the successors of the insn
273 to judge whether a simplification is valid. */
275 static rtx subst_insn;
277 /* This is the lowest LUID that `subst' is currently dealing with.
278 get_last_value will not return a value if the register was set at or
279 after this LUID. If not for this mechanism, we could get confused if
280 I2 or I1 in try_combine were an insn that used the old value of a register
281 to obtain a new value. In that case, we might erroneously get the
282 new value of the register when we wanted the old one. */
284 static int subst_low_luid;
286 /* This contains any hard registers that are used in newpat; reg_dead_at_p
287 must consider all these registers to be always live. */
289 static HARD_REG_SET newpat_used_regs;
291 /* This is an insn to which a LOG_LINKS entry has been added. If this
292 insn is the earlier than I2 or I3, combine should rescan starting at
295 static rtx added_links_insn;
297 /* Basic block in which we are performing combines. */
298 static basic_block this_basic_block;
299 static bool optimize_this_for_speed_p;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each extended basic block in scanning order. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
344 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
350 union { rtx r; int i; enum machine_mode m; } old_contents;
351 union { rtx *r; int *i; } where;
354 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
355 num_undo says how many are currently recorded.
357 other_insn is nonzero if we have modified some other insn in the process
358 of working on subst_insn. It must be verified too. */
367 static struct undobuf undobuf;
369 /* Number of times the pseudo being substituted for
370 was found and replaced. */
372 static int n_occurrences;
374 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
376 unsigned HOST_WIDE_INT,
377 unsigned HOST_WIDE_INT *);
378 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
380 unsigned int, unsigned int *);
381 static void do_SUBST (rtx *, rtx);
382 static void do_SUBST_INT (int *, int);
383 static void init_reg_last (void);
384 static void setup_incoming_promotions (rtx);
385 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
386 static int cant_combine_insn_p (rtx);
387 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
388 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
389 static int contains_muldiv (rtx);
390 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
391 static void undo_all (void);
392 static void undo_commit (void);
393 static rtx *find_split_point (rtx *, rtx, bool);
394 static rtx subst (rtx, rtx, rtx, int, int);
395 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
396 static rtx simplify_if_then_else (rtx);
397 static rtx simplify_set (rtx);
398 static rtx simplify_logical (rtx);
399 static rtx expand_compound_operation (rtx);
400 static const_rtx expand_field_assignment (const_rtx);
401 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
402 rtx, unsigned HOST_WIDE_INT, int, int, int);
403 static rtx extract_left_shift (rtx, int);
404 static rtx make_compound_operation (rtx, enum rtx_code);
405 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
406 unsigned HOST_WIDE_INT *);
407 static rtx canon_reg_for_combine (rtx, rtx);
408 static rtx force_to_mode (rtx, enum machine_mode,
409 unsigned HOST_WIDE_INT, int);
410 static rtx if_then_else_cond (rtx, rtx *, rtx *);
411 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
412 static int rtx_equal_for_field_assignment_p (rtx, rtx);
413 static rtx make_field_assignment (rtx);
414 static rtx apply_distributive_law (rtx);
415 static rtx distribute_and_simplify_rtx (rtx, int);
416 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
419 unsigned HOST_WIDE_INT);
420 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
421 HOST_WIDE_INT, enum machine_mode, int *);
422 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
423 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
425 static int recog_for_combine (rtx *, rtx, rtx *);
426 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
427 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
428 static void update_table_tick (rtx);
429 static void record_value_for_reg (rtx, rtx, rtx);
430 static void check_promoted_subreg (rtx, rtx);
431 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
432 static void record_dead_and_set_regs (rtx);
433 static int get_last_value_validate (rtx *, rtx, int, int);
434 static rtx get_last_value (const_rtx);
435 static int use_crosses_set_p (const_rtx, int);
436 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
437 static int reg_dead_at_p (rtx, rtx);
438 static void move_deaths (rtx, rtx, int, rtx, rtx *);
439 static int reg_bitfield_target_p (rtx, rtx);
440 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
441 static void distribute_links (rtx);
442 static void mark_used_regs_combine (rtx);
443 static void record_promoted_value (rtx, rtx);
444 static int unmentioned_reg_p_1 (rtx *, void *);
445 static bool unmentioned_reg_p (rtx, rtx);
446 static int record_truncated_value (rtx *, void *);
447 static void record_truncated_values (rtx *, void *);
448 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
449 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
452 /* It is not safe to use ordinary gen_lowpart in combine.
453 See comments in gen_lowpart_for_combine. */
454 #undef RTL_HOOKS_GEN_LOWPART
455 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
457 /* Our implementation of gen_lowpart never emits a new pseudo. */
458 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
459 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
461 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
462 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
464 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
465 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
467 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
468 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
470 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
473 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
474 PATTERN can not be split. Otherwise, it returns an insn sequence.
475 This is a wrapper around split_insns which ensures that the
476 reg_stat vector is made larger if the splitter creates a new
480 combine_split_insns (rtx pattern, rtx insn)
485 ret = split_insns (pattern, insn);
486 nregs = max_reg_num ();
487 if (nregs > VEC_length (reg_stat_type, reg_stat))
488 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
492 /* This is used by find_single_use to locate an rtx in LOC that
493 contains exactly one use of DEST, which is typically either a REG
494 or CC0. It returns a pointer to the innermost rtx expression
495 containing DEST. Appearances of DEST that are being used to
496 totally replace it are not counted. */
499 find_single_use_1 (rtx dest, rtx *loc)
502 enum rtx_code code = GET_CODE (x);
520 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
521 of a REG that occupies all of the REG, the insn uses DEST if
522 it is mentioned in the destination or the source. Otherwise, we
523 need just check the source. */
524 if (GET_CODE (SET_DEST (x)) != CC0
525 && GET_CODE (SET_DEST (x)) != PC
526 && !REG_P (SET_DEST (x))
527 && ! (GET_CODE (SET_DEST (x)) == SUBREG
528 && REG_P (SUBREG_REG (SET_DEST (x)))
529 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
531 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
532 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
535 return find_single_use_1 (dest, &SET_SRC (x));
539 return find_single_use_1 (dest, &XEXP (x, 0));
545 /* If it wasn't one of the common cases above, check each expression and
546 vector of this code. Look for a unique usage of DEST. */
548 fmt = GET_RTX_FORMAT (code);
549 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
553 if (dest == XEXP (x, i)
554 || (REG_P (dest) && REG_P (XEXP (x, i))
555 && REGNO (dest) == REGNO (XEXP (x, i))))
558 this_result = find_single_use_1 (dest, &XEXP (x, i));
561 result = this_result;
562 else if (this_result)
563 /* Duplicate usage. */
566 else if (fmt[i] == 'E')
570 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
572 if (XVECEXP (x, i, j) == dest
574 && REG_P (XVECEXP (x, i, j))
575 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
578 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
581 result = this_result;
582 else if (this_result)
592 /* See if DEST, produced in INSN, is used only a single time in the
593 sequel. If so, return a pointer to the innermost rtx expression in which
596 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
598 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
599 care about REG_DEAD notes or LOG_LINKS.
601 Otherwise, we find the single use by finding an insn that has a
602 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
603 only referenced once in that insn, we know that it must be the first
604 and last insn referencing DEST. */
607 find_single_use (rtx dest, rtx insn, rtx *ploc)
617 next = NEXT_INSN (insn);
619 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
622 result = find_single_use_1 (dest, &PATTERN (next));
632 bb = BLOCK_FOR_INSN (insn);
633 for (next = NEXT_INSN (insn);
634 next && BLOCK_FOR_INSN (next) == bb;
635 next = NEXT_INSN (next))
636 if (INSN_P (next) && dead_or_set_p (next, dest))
638 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
639 if (XEXP (link, 0) == insn)
644 result = find_single_use_1 (dest, &PATTERN (next));
654 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
655 insn. The substitution can be undone by undo_all. If INTO is already
656 set to NEWVAL, do not record this change. Because computing NEWVAL might
657 also call SUBST, we have to compute it before we put anything into
661 do_SUBST (rtx *into, rtx newval)
666 if (oldval == newval)
669 /* We'd like to catch as many invalid transformations here as
670 possible. Unfortunately, there are way too many mode changes
671 that are perfectly valid, so we'd waste too much effort for
672 little gain doing the checks here. Focus on catching invalid
673 transformations involving integer constants. */
674 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
675 && CONST_INT_P (newval))
677 /* Sanity check that we're replacing oldval with a CONST_INT
678 that is a valid sign-extension for the original mode. */
679 gcc_assert (INTVAL (newval)
680 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
682 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
683 CONST_INT is not valid, because after the replacement, the
684 original mode would be gone. Unfortunately, we can't tell
685 when do_SUBST is called to replace the operand thereof, so we
686 perform this test on oldval instead, checking whether an
687 invalid replacement took place before we got here. */
688 gcc_assert (!(GET_CODE (oldval) == SUBREG
689 && CONST_INT_P (SUBREG_REG (oldval))));
690 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
691 && CONST_INT_P (XEXP (oldval, 0))));
695 buf = undobuf.frees, undobuf.frees = buf->next;
697 buf = XNEW (struct undo);
699 buf->kind = UNDO_RTX;
701 buf->old_contents.r = oldval;
704 buf->next = undobuf.undos, undobuf.undos = buf;
707 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
709 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
710 for the value of a HOST_WIDE_INT value (including CONST_INT) is
714 do_SUBST_INT (int *into, int newval)
719 if (oldval == newval)
723 buf = undobuf.frees, undobuf.frees = buf->next;
725 buf = XNEW (struct undo);
727 buf->kind = UNDO_INT;
729 buf->old_contents.i = oldval;
732 buf->next = undobuf.undos, undobuf.undos = buf;
735 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
737 /* Similar to SUBST, but just substitute the mode. This is used when
738 changing the mode of a pseudo-register, so that any other
739 references to the entry in the regno_reg_rtx array will change as
743 do_SUBST_MODE (rtx *into, enum machine_mode newval)
746 enum machine_mode oldval = GET_MODE (*into);
748 if (oldval == newval)
752 buf = undobuf.frees, undobuf.frees = buf->next;
754 buf = XNEW (struct undo);
756 buf->kind = UNDO_MODE;
758 buf->old_contents.m = oldval;
759 adjust_reg_mode (*into, newval);
761 buf->next = undobuf.undos, undobuf.undos = buf;
764 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
766 /* Subroutine of try_combine. Determine whether the combine replacement
767 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
768 insn_rtx_cost that the original instruction sequence I0, I1, I2, I3 and
769 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
770 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
771 function returns false, if the costs of all instructions can be
772 estimated, and the replacements are more expensive than the original
776 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
777 rtx newi2pat, rtx newotherpat)
779 int i0_cost, i1_cost, i2_cost, i3_cost;
780 int new_i2_cost, new_i3_cost;
781 int old_cost, new_cost;
783 /* Lookup the original insn_rtx_costs. */
784 i2_cost = INSN_COST (i2);
785 i3_cost = INSN_COST (i3);
789 i1_cost = INSN_COST (i1);
792 i0_cost = INSN_COST (i0);
793 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
794 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
798 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
799 ? i1_cost + i2_cost + i3_cost : 0);
805 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
806 i1_cost = i0_cost = 0;
809 /* Calculate the replacement insn_rtx_costs. */
810 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
813 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
814 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
815 ? new_i2_cost + new_i3_cost : 0;
819 new_cost = new_i3_cost;
823 if (undobuf.other_insn)
825 int old_other_cost, new_other_cost;
827 old_other_cost = INSN_COST (undobuf.other_insn);
828 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
829 if (old_other_cost > 0 && new_other_cost > 0)
831 old_cost += old_other_cost;
832 new_cost += new_other_cost;
838 /* Disallow this recombination if both new_cost and old_cost are
839 greater than zero, and new_cost is greater than old cost. */
841 && new_cost > old_cost)
848 "rejecting combination of insns %d, %d, %d and %d\n",
849 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
851 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
852 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
857 "rejecting combination of insns %d, %d and %d\n",
858 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
859 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
860 i1_cost, i2_cost, i3_cost, old_cost);
865 "rejecting combination of insns %d and %d\n",
866 INSN_UID (i2), INSN_UID (i3));
867 fprintf (dump_file, "original costs %d + %d = %d\n",
868 i2_cost, i3_cost, old_cost);
873 fprintf (dump_file, "replacement costs %d + %d = %d\n",
874 new_i2_cost, new_i3_cost, new_cost);
877 fprintf (dump_file, "replacement cost %d\n", new_cost);
883 /* Update the uid_insn_cost array with the replacement costs. */
884 INSN_COST (i2) = new_i2_cost;
885 INSN_COST (i3) = new_i3_cost;
893 /* Delete any insns that copy a register to itself. */
896 delete_noop_moves (void)
903 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
905 next = NEXT_INSN (insn);
906 if (INSN_P (insn) && noop_move_p (insn))
909 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
911 delete_insn_and_edges (insn);
918 /* Fill in log links field for all insns. */
921 create_log_links (void)
925 df_ref *def_vec, *use_vec;
927 next_use = XCNEWVEC (rtx, max_reg_num ());
929 /* Pass through each block from the end, recording the uses of each
930 register and establishing log links when def is encountered.
931 Note that we do not clear next_use array in order to save time,
932 so we have to test whether the use is in the same basic block as def.
934 There are a few cases below when we do not consider the definition or
935 usage -- these are taken from original flow.c did. Don't ask me why it is
936 done this way; I don't know and if it works, I don't want to know. */
940 FOR_BB_INSNS_REVERSE (bb, insn)
942 if (!NONDEBUG_INSN_P (insn))
945 /* Log links are created only once. */
946 gcc_assert (!LOG_LINKS (insn));
948 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
950 df_ref def = *def_vec;
951 int regno = DF_REF_REGNO (def);
954 if (!next_use[regno])
957 /* Do not consider if it is pre/post modification in MEM. */
958 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
961 /* Do not make the log link for frame pointer. */
962 if ((regno == FRAME_POINTER_REGNUM
963 && (! reload_completed || frame_pointer_needed))
964 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
965 || (regno == HARD_FRAME_POINTER_REGNUM
966 && (! reload_completed || frame_pointer_needed))
968 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
969 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
974 use_insn = next_use[regno];
975 if (BLOCK_FOR_INSN (use_insn) == bb)
979 We don't build a LOG_LINK for hard registers contained
980 in ASM_OPERANDs. If these registers get replaced,
981 we might wind up changing the semantics of the insn,
982 even if reload can make what appear to be valid
983 assignments later. */
984 if (regno >= FIRST_PSEUDO_REGISTER
985 || asm_noperands (PATTERN (use_insn)) < 0)
987 /* Don't add duplicate links between instructions. */
989 for (links = LOG_LINKS (use_insn); links;
990 links = XEXP (links, 1))
991 if (insn == XEXP (links, 0))
995 LOG_LINKS (use_insn) =
996 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
999 next_use[regno] = NULL_RTX;
1002 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1004 df_ref use = *use_vec;
1005 int regno = DF_REF_REGNO (use);
1007 /* Do not consider the usage of the stack pointer
1008 by function call. */
1009 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1012 next_use[regno] = insn;
1020 /* Clear LOG_LINKS fields of insns. */
1023 clear_log_links (void)
1027 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1029 free_INSN_LIST_list (&LOG_LINKS (insn));
1032 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1033 true if we found a LOG_LINK that proves that A feeds B. This only works
1034 if there are no instructions between A and B which could have a link
1035 depending on A, since in that case we would not record a link for B.
1036 We also check the implicit dependency created by a cc0 setter/user
1040 insn_a_feeds_b (rtx a, rtx b)
1043 for (links = LOG_LINKS (b); links; links = XEXP (links, 1))
1044 if (XEXP (links, 0) == a)
1053 /* Main entry point for combiner. F is the first insn of the function.
1054 NREGS is the first unused pseudo-reg number.
1056 Return nonzero if the combiner has turned an indirect jump
1057 instruction into a direct jump. */
1059 combine_instructions (rtx f, unsigned int nregs)
1065 rtx links, nextlinks;
1067 basic_block last_bb;
1069 int new_direct_jump_p = 0;
1071 for (first = f; first && !INSN_P (first); )
1072 first = NEXT_INSN (first);
1076 combine_attempts = 0;
1079 combine_successes = 0;
1081 rtl_hooks = combine_rtl_hooks;
1083 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1085 init_recog_no_volatile ();
1087 /* Allocate array for insn info. */
1088 max_uid_known = get_max_uid ();
1089 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1090 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1092 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1094 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1095 problems when, for example, we have j <<= 1 in a loop. */
1097 nonzero_sign_valid = 0;
1098 label_tick = label_tick_ebb_start = 1;
1100 /* Scan all SETs and see if we can deduce anything about what
1101 bits are known to be zero for some registers and how many copies
1102 of the sign bit are known to exist for those registers.
1104 Also set any known values so that we can use it while searching
1105 for what bits are known to be set. */
1107 setup_incoming_promotions (first);
1108 /* Allow the entry block and the first block to fall into the same EBB.
1109 Conceptually the incoming promotions are assigned to the entry block. */
1110 last_bb = ENTRY_BLOCK_PTR;
1112 create_log_links ();
1113 FOR_EACH_BB (this_basic_block)
1115 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1120 if (!single_pred_p (this_basic_block)
1121 || single_pred (this_basic_block) != last_bb)
1122 label_tick_ebb_start = label_tick;
1123 last_bb = this_basic_block;
1125 FOR_BB_INSNS (this_basic_block, insn)
1126 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1128 subst_low_luid = DF_INSN_LUID (insn);
1131 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1133 record_dead_and_set_regs (insn);
1136 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1137 if (REG_NOTE_KIND (links) == REG_INC)
1138 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1142 /* Record the current insn_rtx_cost of this instruction. */
1143 if (NONJUMP_INSN_P (insn))
1144 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1145 optimize_this_for_speed_p);
1147 fprintf(dump_file, "insn_cost %d: %d\n",
1148 INSN_UID (insn), INSN_COST (insn));
1152 nonzero_sign_valid = 1;
1154 /* Now scan all the insns in forward order. */
1155 label_tick = label_tick_ebb_start = 1;
1157 setup_incoming_promotions (first);
1158 last_bb = ENTRY_BLOCK_PTR;
1160 FOR_EACH_BB (this_basic_block)
1162 rtx last_combined_insn = NULL_RTX;
1163 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1168 if (!single_pred_p (this_basic_block)
1169 || single_pred (this_basic_block) != last_bb)
1170 label_tick_ebb_start = label_tick;
1171 last_bb = this_basic_block;
1173 rtl_profile_for_bb (this_basic_block);
1174 for (insn = BB_HEAD (this_basic_block);
1175 insn != NEXT_INSN (BB_END (this_basic_block));
1176 insn = next ? next : NEXT_INSN (insn))
1179 if (NONDEBUG_INSN_P (insn))
1181 while (last_combined_insn
1182 && INSN_DELETED_P (last_combined_insn))
1183 last_combined_insn = PREV_INSN (last_combined_insn);
1184 if (last_combined_insn == NULL_RTX
1185 || BARRIER_P (last_combined_insn)
1186 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1187 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1188 last_combined_insn = insn;
1190 /* See if we know about function return values before this
1191 insn based upon SUBREG flags. */
1192 check_promoted_subreg (insn, PATTERN (insn));
1194 /* See if we can find hardregs and subreg of pseudos in
1195 narrower modes. This could help turning TRUNCATEs
1197 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1199 /* Try this insn with each insn it links back to. */
1201 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1202 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX,
1203 NULL_RTX, &new_direct_jump_p,
1204 last_combined_insn)) != 0)
1207 /* Try each sequence of three linked insns ending with this one. */
1209 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1211 rtx link = XEXP (links, 0);
1213 /* If the linked insn has been replaced by a note, then there
1214 is no point in pursuing this chain any further. */
1218 for (nextlinks = LOG_LINKS (link);
1220 nextlinks = XEXP (nextlinks, 1))
1221 if ((next = try_combine (insn, link, XEXP (nextlinks, 0),
1222 NULL_RTX, &new_direct_jump_p,
1223 last_combined_insn)) != 0)
1228 /* Try to combine a jump insn that uses CC0
1229 with a preceding insn that sets CC0, and maybe with its
1230 logical predecessor as well.
1231 This is how we make decrement-and-branch insns.
1232 We need this special code because data flow connections
1233 via CC0 do not get entered in LOG_LINKS. */
1236 && (prev = prev_nonnote_insn (insn)) != 0
1237 && NONJUMP_INSN_P (prev)
1238 && sets_cc0_p (PATTERN (prev)))
1240 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1242 last_combined_insn)) != 0)
1245 for (nextlinks = LOG_LINKS (prev); nextlinks;
1246 nextlinks = XEXP (nextlinks, 1))
1247 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1248 NULL_RTX, &new_direct_jump_p,
1249 last_combined_insn)) != 0)
1253 /* Do the same for an insn that explicitly references CC0. */
1254 if (NONJUMP_INSN_P (insn)
1255 && (prev = prev_nonnote_insn (insn)) != 0
1256 && NONJUMP_INSN_P (prev)
1257 && sets_cc0_p (PATTERN (prev))
1258 && GET_CODE (PATTERN (insn)) == SET
1259 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1261 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1263 last_combined_insn)) != 0)
1266 for (nextlinks = LOG_LINKS (prev); nextlinks;
1267 nextlinks = XEXP (nextlinks, 1))
1268 if ((next = try_combine (insn, prev, XEXP (nextlinks, 0),
1269 NULL_RTX, &new_direct_jump_p,
1270 last_combined_insn)) != 0)
1274 /* Finally, see if any of the insns that this insn links to
1275 explicitly references CC0. If so, try this insn, that insn,
1276 and its predecessor if it sets CC0. */
1277 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1278 if (NONJUMP_INSN_P (XEXP (links, 0))
1279 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1280 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1281 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1282 && NONJUMP_INSN_P (prev)
1283 && sets_cc0_p (PATTERN (prev))
1284 && (next = try_combine (insn, XEXP (links, 0),
1285 prev, NULL_RTX, &new_direct_jump_p,
1286 last_combined_insn)) != 0)
1290 /* Try combining an insn with two different insns whose results it
1292 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1293 for (nextlinks = XEXP (links, 1); nextlinks;
1294 nextlinks = XEXP (nextlinks, 1))
1295 if ((next = try_combine (insn, XEXP (links, 0),
1296 XEXP (nextlinks, 0), NULL_RTX,
1298 last_combined_insn)) != 0)
1301 /* Try four-instruction combinations. */
1302 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1305 rtx link = XEXP (links, 0);
1307 /* If the linked insn has been replaced by a note, then there
1308 is no point in pursuing this chain any further. */
1312 for (next1 = LOG_LINKS (link); next1; next1 = XEXP (next1, 1))
1314 rtx link1 = XEXP (next1, 0);
1317 /* I0 -> I1 -> I2 -> I3. */
1318 for (nextlinks = LOG_LINKS (link1); nextlinks;
1319 nextlinks = XEXP (nextlinks, 1))
1320 if ((next = try_combine (insn, link, link1,
1321 XEXP (nextlinks, 0),
1323 last_combined_insn)) != 0)
1325 /* I0, I1 -> I2, I2 -> I3. */
1326 for (nextlinks = XEXP (next1, 1); nextlinks;
1327 nextlinks = XEXP (nextlinks, 1))
1328 if ((next = try_combine (insn, link, link1,
1329 XEXP (nextlinks, 0),
1331 last_combined_insn)) != 0)
1335 for (next1 = XEXP (links, 1); next1; next1 = XEXP (next1, 1))
1337 rtx link1 = XEXP (next1, 0);
1340 /* I0 -> I2; I1, I2 -> I3. */
1341 for (nextlinks = LOG_LINKS (link); nextlinks;
1342 nextlinks = XEXP (nextlinks, 1))
1343 if ((next = try_combine (insn, link, link1,
1344 XEXP (nextlinks, 0),
1346 last_combined_insn)) != 0)
1348 /* I0 -> I1; I1, I2 -> I3. */
1349 for (nextlinks = LOG_LINKS (link1); nextlinks;
1350 nextlinks = XEXP (nextlinks, 1))
1351 if ((next = try_combine (insn, link, link1,
1352 XEXP (nextlinks, 0),
1354 last_combined_insn)) != 0)
1359 /* Try this insn with each REG_EQUAL note it links back to. */
1360 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1363 rtx temp = XEXP (links, 0);
1364 if ((set = single_set (temp)) != 0
1365 && (note = find_reg_equal_equiv_note (temp)) != 0
1366 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1367 /* Avoid using a register that may already been marked
1368 dead by an earlier instruction. */
1369 && ! unmentioned_reg_p (note, SET_SRC (set))
1370 && (GET_MODE (note) == VOIDmode
1371 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1372 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1374 /* Temporarily replace the set's source with the
1375 contents of the REG_EQUAL note. The insn will
1376 be deleted or recognized by try_combine. */
1377 rtx orig = SET_SRC (set);
1378 SET_SRC (set) = note;
1380 i2mod_old_rhs = copy_rtx (orig);
1381 i2mod_new_rhs = copy_rtx (note);
1382 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1384 last_combined_insn);
1388 SET_SRC (set) = orig;
1393 record_dead_and_set_regs (insn);
1401 default_rtl_profile ();
1404 new_direct_jump_p |= purge_all_dead_edges ();
1405 delete_noop_moves ();
1408 free (uid_log_links);
1409 free (uid_insn_cost);
1410 VEC_free (reg_stat_type, heap, reg_stat);
1413 struct undo *undo, *next;
1414 for (undo = undobuf.frees; undo; undo = next)
1422 total_attempts += combine_attempts;
1423 total_merges += combine_merges;
1424 total_extras += combine_extras;
1425 total_successes += combine_successes;
1427 nonzero_sign_valid = 0;
1428 rtl_hooks = general_rtl_hooks;
1430 /* Make recognizer allow volatile MEMs again. */
1433 return new_direct_jump_p;
1436 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1439 init_reg_last (void)
1444 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1445 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1448 /* Set up any promoted values for incoming argument registers. */
1451 setup_incoming_promotions (rtx first)
1454 bool strictly_local = false;
1456 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1457 arg = DECL_CHAIN (arg))
1459 rtx x, reg = DECL_INCOMING_RTL (arg);
1461 enum machine_mode mode1, mode2, mode3, mode4;
1463 /* Only continue if the incoming argument is in a register. */
1467 /* Determine, if possible, whether all call sites of the current
1468 function lie within the current compilation unit. (This does
1469 take into account the exporting of a function via taking its
1470 address, and so forth.) */
1471 strictly_local = cgraph_local_info (current_function_decl)->local;
1473 /* The mode and signedness of the argument before any promotions happen
1474 (equal to the mode of the pseudo holding it at that stage). */
1475 mode1 = TYPE_MODE (TREE_TYPE (arg));
1476 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1478 /* The mode and signedness of the argument after any source language and
1479 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1480 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1481 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1483 /* The mode and signedness of the argument as it is actually passed,
1484 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1485 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1486 TREE_TYPE (cfun->decl), 0);
1488 /* The mode of the register in which the argument is being passed. */
1489 mode4 = GET_MODE (reg);
1491 /* Eliminate sign extensions in the callee when:
1492 (a) A mode promotion has occurred; */
1495 /* (b) The mode of the register is the same as the mode of
1496 the argument as it is passed; */
1499 /* (c) There's no language level extension; */
1502 /* (c.1) All callers are from the current compilation unit. If that's
1503 the case we don't have to rely on an ABI, we only have to know
1504 what we're generating right now, and we know that we will do the
1505 mode1 to mode2 promotion with the given sign. */
1506 else if (!strictly_local)
1508 /* (c.2) The combination of the two promotions is useful. This is
1509 true when the signs match, or if the first promotion is unsigned.
1510 In the later case, (sign_extend (zero_extend x)) is the same as
1511 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1517 /* Record that the value was promoted from mode1 to mode3,
1518 so that any sign extension at the head of the current
1519 function may be eliminated. */
1520 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1521 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1522 record_value_for_reg (reg, first, x);
1526 /* Called via note_stores. If X is a pseudo that is narrower than
1527 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1529 If we are setting only a portion of X and we can't figure out what
1530 portion, assume all bits will be used since we don't know what will
1533 Similarly, set how many bits of X are known to be copies of the sign bit
1534 at all locations in the function. This is the smallest number implied
1538 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1540 rtx insn = (rtx) data;
1544 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1545 /* If this register is undefined at the start of the file, we can't
1546 say what its contents were. */
1547 && ! REGNO_REG_SET_P
1548 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1549 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1551 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1553 if (set == 0 || GET_CODE (set) == CLOBBER)
1555 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1556 rsp->sign_bit_copies = 1;
1560 /* If this register is being initialized using itself, and the
1561 register is uninitialized in this basic block, and there are
1562 no LOG_LINKS which set the register, then part of the
1563 register is uninitialized. In that case we can't assume
1564 anything about the number of nonzero bits.
1566 ??? We could do better if we checked this in
1567 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1568 could avoid making assumptions about the insn which initially
1569 sets the register, while still using the information in other
1570 insns. We would have to be careful to check every insn
1571 involved in the combination. */
1574 && reg_referenced_p (x, PATTERN (insn))
1575 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1580 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1582 if (dead_or_set_p (XEXP (link, 0), x))
1587 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1588 rsp->sign_bit_copies = 1;
1593 /* If this is a complex assignment, see if we can convert it into a
1594 simple assignment. */
1595 set = expand_field_assignment (set);
1597 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1598 set what we know about X. */
1600 if (SET_DEST (set) == x
1601 || (GET_CODE (SET_DEST (set)) == SUBREG
1602 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1603 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1604 && SUBREG_REG (SET_DEST (set)) == x))
1606 rtx src = SET_SRC (set);
1608 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1609 /* If X is narrower than a word and SRC is a non-negative
1610 constant that would appear negative in the mode of X,
1611 sign-extend it for use in reg_stat[].nonzero_bits because some
1612 machines (maybe most) will actually do the sign-extension
1613 and this is the conservative approach.
1615 ??? For 2.5, try to tighten up the MD files in this regard
1616 instead of this kludge. */
1618 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1619 && CONST_INT_P (src)
1621 && 0 != (UINTVAL (src)
1622 & ((unsigned HOST_WIDE_INT) 1
1623 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1624 src = GEN_INT (UINTVAL (src)
1625 | ((unsigned HOST_WIDE_INT) (-1)
1626 << GET_MODE_BITSIZE (GET_MODE (x))));
1629 /* Don't call nonzero_bits if it cannot change anything. */
1630 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1631 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1632 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1633 if (rsp->sign_bit_copies == 0
1634 || rsp->sign_bit_copies > num)
1635 rsp->sign_bit_copies = num;
1639 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1640 rsp->sign_bit_copies = 1;
1645 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1646 optionally insns that were previously combined into I3 or that will be
1647 combined into the merger of INSN and I3. The order is PRED, PRED2,
1648 INSN, SUCC, SUCC2, I3.
1650 Return 0 if the combination is not allowed for any reason.
1652 If the combination is allowed, *PDEST will be set to the single
1653 destination of INSN and *PSRC to the single source, and this function
1657 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1658 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1659 rtx *pdest, rtx *psrc)
1668 bool all_adjacent = true;
1669 int (*is_volatile_p) (const_rtx);
1675 if (next_active_insn (succ2) != i3)
1676 all_adjacent = false;
1677 if (next_active_insn (succ) != succ2)
1678 all_adjacent = false;
1680 else if (next_active_insn (succ) != i3)
1681 all_adjacent = false;
1682 if (next_active_insn (insn) != succ)
1683 all_adjacent = false;
1685 else if (next_active_insn (insn) != i3)
1686 all_adjacent = false;
1688 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1689 or a PARALLEL consisting of such a SET and CLOBBERs.
1691 If INSN has CLOBBER parallel parts, ignore them for our processing.
1692 By definition, these happen during the execution of the insn. When it
1693 is merged with another insn, all bets are off. If they are, in fact,
1694 needed and aren't also supplied in I3, they may be added by
1695 recog_for_combine. Otherwise, it won't match.
1697 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1700 Get the source and destination of INSN. If more than one, can't
1703 if (GET_CODE (PATTERN (insn)) == SET)
1704 set = PATTERN (insn);
1705 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1706 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1708 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1710 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1712 switch (GET_CODE (elt))
1714 /* This is important to combine floating point insns
1715 for the SH4 port. */
1717 /* Combining an isolated USE doesn't make sense.
1718 We depend here on combinable_i3pat to reject them. */
1719 /* The code below this loop only verifies that the inputs of
1720 the SET in INSN do not change. We call reg_set_between_p
1721 to verify that the REG in the USE does not change between
1723 If the USE in INSN was for a pseudo register, the matching
1724 insn pattern will likely match any register; combining this
1725 with any other USE would only be safe if we knew that the
1726 used registers have identical values, or if there was
1727 something to tell them apart, e.g. different modes. For
1728 now, we forgo such complicated tests and simply disallow
1729 combining of USES of pseudo registers with any other USE. */
1730 if (REG_P (XEXP (elt, 0))
1731 && GET_CODE (PATTERN (i3)) == PARALLEL)
1733 rtx i3pat = PATTERN (i3);
1734 int i = XVECLEN (i3pat, 0) - 1;
1735 unsigned int regno = REGNO (XEXP (elt, 0));
1739 rtx i3elt = XVECEXP (i3pat, 0, i);
1741 if (GET_CODE (i3elt) == USE
1742 && REG_P (XEXP (i3elt, 0))
1743 && (REGNO (XEXP (i3elt, 0)) == regno
1744 ? reg_set_between_p (XEXP (elt, 0),
1745 PREV_INSN (insn), i3)
1746 : regno >= FIRST_PSEUDO_REGISTER))
1753 /* We can ignore CLOBBERs. */
1758 /* Ignore SETs whose result isn't used but not those that
1759 have side-effects. */
1760 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1761 && insn_nothrow_p (insn)
1762 && !side_effects_p (elt))
1765 /* If we have already found a SET, this is a second one and
1766 so we cannot combine with this insn. */
1774 /* Anything else means we can't combine. */
1780 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1781 so don't do anything with it. */
1782 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1791 /* The simplification in expand_field_assignment may call back to
1792 get_last_value, so set safe guard here. */
1793 subst_low_luid = DF_INSN_LUID (insn);
1795 set = expand_field_assignment (set);
1796 src = SET_SRC (set), dest = SET_DEST (set);
1798 /* Don't eliminate a store in the stack pointer. */
1799 if (dest == stack_pointer_rtx
1800 /* Don't combine with an insn that sets a register to itself if it has
1801 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1802 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1803 /* Can't merge an ASM_OPERANDS. */
1804 || GET_CODE (src) == ASM_OPERANDS
1805 /* Can't merge a function call. */
1806 || GET_CODE (src) == CALL
1807 /* Don't eliminate a function call argument. */
1809 && (find_reg_fusage (i3, USE, dest)
1811 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1812 && global_regs[REGNO (dest)])))
1813 /* Don't substitute into an incremented register. */
1814 || FIND_REG_INC_NOTE (i3, dest)
1815 || (succ && FIND_REG_INC_NOTE (succ, dest))
1816 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1817 /* Don't substitute into a non-local goto, this confuses CFG. */
1818 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1819 /* Make sure that DEST is not used after SUCC but before I3. */
1822 && (reg_used_between_p (dest, succ2, i3)
1823 || reg_used_between_p (dest, succ, succ2)))
1824 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1825 /* Make sure that the value that is to be substituted for the register
1826 does not use any registers whose values alter in between. However,
1827 If the insns are adjacent, a use can't cross a set even though we
1828 think it might (this can happen for a sequence of insns each setting
1829 the same destination; last_set of that register might point to
1830 a NOTE). If INSN has a REG_EQUIV note, the register is always
1831 equivalent to the memory so the substitution is valid even if there
1832 are intervening stores. Also, don't move a volatile asm or
1833 UNSPEC_VOLATILE across any other insns. */
1836 || ! find_reg_note (insn, REG_EQUIV, src))
1837 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1838 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1839 || GET_CODE (src) == UNSPEC_VOLATILE))
1840 /* Don't combine across a CALL_INSN, because that would possibly
1841 change whether the life span of some REGs crosses calls or not,
1842 and it is a pain to update that information.
1843 Exception: if source is a constant, moving it later can't hurt.
1844 Accept that as a special case. */
1845 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1848 /* DEST must either be a REG or CC0. */
1851 /* If register alignment is being enforced for multi-word items in all
1852 cases except for parameters, it is possible to have a register copy
1853 insn referencing a hard register that is not allowed to contain the
1854 mode being copied and which would not be valid as an operand of most
1855 insns. Eliminate this problem by not combining with such an insn.
1857 Also, on some machines we don't want to extend the life of a hard
1861 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1862 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1863 /* Don't extend the life of a hard register unless it is
1864 user variable (if we have few registers) or it can't
1865 fit into the desired register (meaning something special
1867 Also avoid substituting a return register into I3, because
1868 reload can't handle a conflict with constraints of other
1870 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1871 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1874 else if (GET_CODE (dest) != CC0)
1878 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1879 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1880 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1882 /* Don't substitute for a register intended as a clobberable
1884 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1885 if (rtx_equal_p (reg, dest))
1888 /* If the clobber represents an earlyclobber operand, we must not
1889 substitute an expression containing the clobbered register.
1890 As we do not analyze the constraint strings here, we have to
1891 make the conservative assumption. However, if the register is
1892 a fixed hard reg, the clobber cannot represent any operand;
1893 we leave it up to the machine description to either accept or
1894 reject use-and-clobber patterns. */
1896 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1897 || !fixed_regs[REGNO (reg)])
1898 if (reg_overlap_mentioned_p (reg, src))
1902 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1903 or not), reject, unless nothing volatile comes between it and I3 */
1905 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1907 /* Make sure neither succ nor succ2 contains a volatile reference. */
1908 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1910 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1912 /* We'll check insns between INSN and I3 below. */
1915 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1916 to be an explicit register variable, and was chosen for a reason. */
1918 if (GET_CODE (src) == ASM_OPERANDS
1919 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1922 /* If INSN contains volatile references (specifically volatile MEMs),
1923 we cannot combine across any other volatile references.
1924 Even if INSN doesn't contain volatile references, any intervening
1925 volatile insn might affect machine state. */
1927 is_volatile_p = volatile_refs_p (PATTERN (insn))
1931 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1932 if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
1935 /* If INSN contains an autoincrement or autodecrement, make sure that
1936 register is not used between there and I3, and not already used in
1937 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1938 Also insist that I3 not be a jump; if it were one
1939 and the incremented register were spilled, we would lose. */
1942 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1943 if (REG_NOTE_KIND (link) == REG_INC
1945 || reg_used_between_p (XEXP (link, 0), insn, i3)
1946 || (pred != NULL_RTX
1947 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1948 || (pred2 != NULL_RTX
1949 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1950 || (succ != NULL_RTX
1951 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1952 || (succ2 != NULL_RTX
1953 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1954 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1959 /* Don't combine an insn that follows a CC0-setting insn.
1960 An insn that uses CC0 must not be separated from the one that sets it.
1961 We do, however, allow I2 to follow a CC0-setting insn if that insn
1962 is passed as I1; in that case it will be deleted also.
1963 We also allow combining in this case if all the insns are adjacent
1964 because that would leave the two CC0 insns adjacent as well.
1965 It would be more logical to test whether CC0 occurs inside I1 or I2,
1966 but that would be much slower, and this ought to be equivalent. */
1968 p = prev_nonnote_insn (insn);
1969 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1974 /* If we get here, we have passed all the tests and the combination is
1983 /* LOC is the location within I3 that contains its pattern or the component
1984 of a PARALLEL of the pattern. We validate that it is valid for combining.
1986 One problem is if I3 modifies its output, as opposed to replacing it
1987 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
1988 doing so would produce an insn that is not equivalent to the original insns.
1992 (set (reg:DI 101) (reg:DI 100))
1993 (set (subreg:SI (reg:DI 101) 0) <foo>)
1995 This is NOT equivalent to:
1997 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1998 (set (reg:DI 101) (reg:DI 100))])
2000 Not only does this modify 100 (in which case it might still be valid
2001 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2003 We can also run into a problem if I2 sets a register that I1
2004 uses and I1 gets directly substituted into I3 (not via I2). In that
2005 case, we would be getting the wrong value of I2DEST into I3, so we
2006 must reject the combination. This case occurs when I2 and I1 both
2007 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2008 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2009 of a SET must prevent combination from occurring. The same situation
2010 can occur for I0, in which case I0_NOT_IN_SRC is set.
2012 Before doing the above check, we first try to expand a field assignment
2013 into a set of logical operations.
2015 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2016 we place a register that is both set and used within I3. If more than one
2017 such register is detected, we fail.
2019 Return 1 if the combination is valid, zero otherwise. */
2022 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2023 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2027 if (GET_CODE (x) == SET)
2030 rtx dest = SET_DEST (set);
2031 rtx src = SET_SRC (set);
2032 rtx inner_dest = dest;
2035 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2036 || GET_CODE (inner_dest) == SUBREG
2037 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2038 inner_dest = XEXP (inner_dest, 0);
2040 /* Check for the case where I3 modifies its output, as discussed
2041 above. We don't want to prevent pseudos from being combined
2042 into the address of a MEM, so only prevent the combination if
2043 i1 or i2 set the same MEM. */
2044 if ((inner_dest != dest &&
2045 (!MEM_P (inner_dest)
2046 || rtx_equal_p (i2dest, inner_dest)
2047 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2048 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2049 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2050 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2051 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2053 /* This is the same test done in can_combine_p except we can't test
2054 all_adjacent; we don't have to, since this instruction will stay
2055 in place, thus we are not considering increasing the lifetime of
2058 Also, if this insn sets a function argument, combining it with
2059 something that might need a spill could clobber a previous
2060 function argument; the all_adjacent test in can_combine_p also
2061 checks this; here, we do a more specific test for this case. */
2063 || (REG_P (inner_dest)
2064 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2065 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2066 GET_MODE (inner_dest))))
2067 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2068 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2071 /* If DEST is used in I3, it is being killed in this insn, so
2072 record that for later. We have to consider paradoxical
2073 subregs here, since they kill the whole register, but we
2074 ignore partial subregs, STRICT_LOW_PART, etc.
2075 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2076 STACK_POINTER_REGNUM, since these are always considered to be
2077 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2079 if (GET_CODE (subdest) == SUBREG
2080 && (GET_MODE_SIZE (GET_MODE (subdest))
2081 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2082 subdest = SUBREG_REG (subdest);
2085 && reg_referenced_p (subdest, PATTERN (i3))
2086 && REGNO (subdest) != FRAME_POINTER_REGNUM
2087 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2088 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2090 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2091 && (REGNO (subdest) != ARG_POINTER_REGNUM
2092 || ! fixed_regs [REGNO (subdest)])
2094 && REGNO (subdest) != STACK_POINTER_REGNUM)
2096 if (*pi3dest_killed)
2099 *pi3dest_killed = subdest;
2103 else if (GET_CODE (x) == PARALLEL)
2107 for (i = 0; i < XVECLEN (x, 0); i++)
2108 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2109 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2116 /* Return 1 if X is an arithmetic expression that contains a multiplication
2117 and division. We don't count multiplications by powers of two here. */
2120 contains_muldiv (rtx x)
2122 switch (GET_CODE (x))
2124 case MOD: case DIV: case UMOD: case UDIV:
2128 return ! (CONST_INT_P (XEXP (x, 1))
2129 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2132 return contains_muldiv (XEXP (x, 0))
2133 || contains_muldiv (XEXP (x, 1));
2136 return contains_muldiv (XEXP (x, 0));
2142 /* Determine whether INSN can be used in a combination. Return nonzero if
2143 not. This is used in try_combine to detect early some cases where we
2144 can't perform combinations. */
2147 cant_combine_insn_p (rtx insn)
2152 /* If this isn't really an insn, we can't do anything.
2153 This can occur when flow deletes an insn that it has merged into an
2154 auto-increment address. */
2155 if (! INSN_P (insn))
2158 /* Never combine loads and stores involving hard regs that are likely
2159 to be spilled. The register allocator can usually handle such
2160 reg-reg moves by tying. If we allow the combiner to make
2161 substitutions of likely-spilled regs, reload might die.
2162 As an exception, we allow combinations involving fixed regs; these are
2163 not available to the register allocator so there's no risk involved. */
2165 set = single_set (insn);
2168 src = SET_SRC (set);
2169 dest = SET_DEST (set);
2170 if (GET_CODE (src) == SUBREG)
2171 src = SUBREG_REG (src);
2172 if (GET_CODE (dest) == SUBREG)
2173 dest = SUBREG_REG (dest);
2174 if (REG_P (src) && REG_P (dest)
2175 && ((HARD_REGISTER_P (src)
2176 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2177 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2178 || (HARD_REGISTER_P (dest)
2179 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2180 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2186 struct likely_spilled_retval_info
2188 unsigned regno, nregs;
2192 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2193 hard registers that are known to be written to / clobbered in full. */
2195 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2197 struct likely_spilled_retval_info *const info =
2198 (struct likely_spilled_retval_info *) data;
2199 unsigned regno, nregs;
2202 if (!REG_P (XEXP (set, 0)))
2205 if (regno >= info->regno + info->nregs)
2207 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2208 if (regno + nregs <= info->regno)
2210 new_mask = (2U << (nregs - 1)) - 1;
2211 if (regno < info->regno)
2212 new_mask >>= info->regno - regno;
2214 new_mask <<= regno - info->regno;
2215 info->mask &= ~new_mask;
2218 /* Return nonzero iff part of the return value is live during INSN, and
2219 it is likely spilled. This can happen when more than one insn is needed
2220 to copy the return value, e.g. when we consider to combine into the
2221 second copy insn for a complex value. */
2224 likely_spilled_retval_p (rtx insn)
2226 rtx use = BB_END (this_basic_block);
2228 unsigned regno, nregs;
2229 /* We assume here that no machine mode needs more than
2230 32 hard registers when the value overlaps with a register
2231 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2233 struct likely_spilled_retval_info info;
2235 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2237 reg = XEXP (PATTERN (use), 0);
2238 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2240 regno = REGNO (reg);
2241 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2244 mask = (2U << (nregs - 1)) - 1;
2246 /* Disregard parts of the return value that are set later. */
2250 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2252 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2255 /* Check if any of the (probably) live return value registers is
2260 if ((mask & 1 << nregs)
2261 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2267 /* Adjust INSN after we made a change to its destination.
2269 Changing the destination can invalidate notes that say something about
2270 the results of the insn and a LOG_LINK pointing to the insn. */
2273 adjust_for_new_dest (rtx insn)
2275 /* For notes, be conservative and simply remove them. */
2276 remove_reg_equal_equiv_notes (insn);
2278 /* The new insn will have a destination that was previously the destination
2279 of an insn just above it. Call distribute_links to make a LOG_LINK from
2280 the next use of that destination. */
2281 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2283 df_insn_rescan (insn);
2286 /* Return TRUE if combine can reuse reg X in mode MODE.
2287 ADDED_SETS is nonzero if the original set is still required. */
2289 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2297 /* Allow hard registers if the new mode is legal, and occupies no more
2298 registers than the old mode. */
2299 if (regno < FIRST_PSEUDO_REGISTER)
2300 return (HARD_REGNO_MODE_OK (regno, mode)
2301 && (hard_regno_nregs[regno][GET_MODE (x)]
2302 >= hard_regno_nregs[regno][mode]));
2304 /* Or a pseudo that is only used once. */
2305 return (REG_N_SETS (regno) == 1 && !added_sets
2306 && !REG_USERVAR_P (x));
2310 /* Check whether X, the destination of a set, refers to part of
2311 the register specified by REG. */
2314 reg_subword_p (rtx x, rtx reg)
2316 /* Check that reg is an integer mode register. */
2317 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2320 if (GET_CODE (x) == STRICT_LOW_PART
2321 || GET_CODE (x) == ZERO_EXTRACT)
2324 return GET_CODE (x) == SUBREG
2325 && SUBREG_REG (x) == reg
2326 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2330 /* Replace auto-increment addressing modes with explicit operations to access
2331 the same addresses without modifying the corresponding registers. */
2334 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2337 const RTX_CODE code = GET_CODE (x);
2353 /* SCRATCH must be shared because they represent distinct values. */
2356 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2361 if (shared_const_p (x))
2366 mem_mode = GET_MODE (x);
2371 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2372 return gen_rtx_PLUS (GET_MODE (x),
2373 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2374 GEN_INT (code == PRE_INC
2375 ? GET_MODE_SIZE (mem_mode)
2376 : -GET_MODE_SIZE (mem_mode)));
2382 return cleanup_auto_inc_dec (code == PRE_MODIFY
2383 ? XEXP (x, 1) : XEXP (x, 0),
2390 /* Copy the various flags, fields, and other information. We assume
2391 that all fields need copying, and then clear the fields that should
2392 not be copied. That is the sensible default behavior, and forces
2393 us to explicitly document why we are *not* copying a flag. */
2394 x = shallow_copy_rtx (x);
2396 /* We do not copy the USED flag, which is used as a mark bit during
2397 walks over the RTL. */
2398 RTX_FLAG (x, used) = 0;
2400 /* We do not copy FRAME_RELATED for INSNs. */
2402 RTX_FLAG (x, frame_related) = 0;
2404 fmt = GET_RTX_FORMAT (code);
2405 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2407 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2408 else if (fmt[i] == 'E' || fmt[i] == 'V')
2411 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2412 for (j = 0; j < XVECLEN (x, i); j++)
2414 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2421 /* Auxiliary data structure for propagate_for_debug_stmt. */
2423 struct rtx_subst_pair
2429 /* DATA points to an rtx_subst_pair. Return the value that should be
2433 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2435 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2437 if (!rtx_equal_p (from, old_rtx))
2439 if (!pair->adjusted)
2441 pair->adjusted = true;
2443 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2445 pair->to = copy_rtx (pair->to);
2447 pair->to = make_compound_operation (pair->to, SET);
2450 return copy_rtx (pair->to);
2453 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2454 and LAST, not including INSN, but including LAST. Also stop at the end
2455 of THIS_BASIC_BLOCK. */
2458 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2460 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2462 struct rtx_subst_pair p;
2466 next = NEXT_INSN (insn);
2467 last = NEXT_INSN (last);
2468 while (next != last && next != end)
2471 next = NEXT_INSN (insn);
2472 if (DEBUG_INSN_P (insn))
2474 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2475 dest, propagate_for_debug_subst, &p);
2476 if (loc == INSN_VAR_LOCATION_LOC (insn))
2478 INSN_VAR_LOCATION_LOC (insn) = loc;
2479 df_insn_rescan (insn);
2484 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2485 Note that the INSN should be deleted *after* removing dead edges, so
2486 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2487 but not for a (set (pc) (label_ref FOO)). */
2490 update_cfg_for_uncondjump (rtx insn)
2492 basic_block bb = BLOCK_FOR_INSN (insn);
2493 bool at_end = (BB_END (bb) == insn);
2496 purge_dead_edges (bb);
2499 if (at_end && EDGE_COUNT (bb->succs) == 1)
2503 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2505 /* Remove barriers from the footer if there are any. */
2506 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2507 if (BARRIER_P (insn))
2509 if (PREV_INSN (insn))
2510 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2512 bb->il.rtl->footer = NEXT_INSN (insn);
2513 if (NEXT_INSN (insn))
2514 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2516 else if (LABEL_P (insn))
2521 /* Try to combine the insns I0, I1 and I2 into I3.
2522 Here I0, I1 and I2 appear earlier than I3.
2523 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2526 If we are combining more than two insns and the resulting insn is not
2527 recognized, try splitting it into two insns. If that happens, I2 and I3
2528 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2529 Otherwise, I0, I1 and I2 are pseudo-deleted.
2531 Return 0 if the combination does not work. Then nothing is changed.
2532 If we did the combination, return the insn at which combine should
2535 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2536 new direct jump instruction.
2538 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2539 been I3 passed to an earlier try_combine within the same basic
2543 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2544 rtx last_combined_insn)
2546 /* New patterns for I3 and I2, respectively. */
2547 rtx newpat, newi2pat = 0;
2548 rtvec newpat_vec_with_clobbers = 0;
2549 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2550 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2552 int added_sets_0, added_sets_1, added_sets_2;
2553 /* Total number of SETs to put into I3. */
2555 /* Nonzero if I2's or I1's body now appears in I3. */
2556 int i2_is_used = 0, i1_is_used = 0;
2557 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2558 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2559 /* Contains I3 if the destination of I3 is used in its source, which means
2560 that the old life of I3 is being killed. If that usage is placed into
2561 I2 and not in I3, a REG_DEAD note must be made. */
2562 rtx i3dest_killed = 0;
2563 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2564 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2565 /* Copy of SET_SRC of I1 and I0, if needed. */
2566 rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2567 /* Set if I2DEST was reused as a scratch register. */
2568 bool i2scratch = false;
2569 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2570 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2571 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2572 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2573 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2574 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2575 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2576 /* Notes that must be added to REG_NOTES in I3 and I2. */
2577 rtx new_i3_notes, new_i2_notes;
2578 /* Notes that we substituted I3 into I2 instead of the normal case. */
2579 int i3_subst_into_i2 = 0;
2580 /* Notes that I1, I2 or I3 is a MULT operation. */
2583 int changed_i3_dest = 0;
2589 rtx new_other_notes;
2592 /* Only try four-insn combinations when there's high likelihood of
2593 success. Look for simple insns, such as loads of constants or
2594 binary operations involving a constant. */
2601 if (!flag_expensive_optimizations)
2604 for (i = 0; i < 4; i++)
2606 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2607 rtx set = single_set (insn);
2611 src = SET_SRC (set);
2612 if (CONSTANT_P (src))
2617 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2619 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2620 || GET_CODE (src) == LSHIFTRT)
2623 if (ngood < 2 && nshift < 2)
2627 /* Exit early if one of the insns involved can't be used for
2629 if (cant_combine_insn_p (i3)
2630 || cant_combine_insn_p (i2)
2631 || (i1 && cant_combine_insn_p (i1))
2632 || (i0 && cant_combine_insn_p (i0))
2633 || likely_spilled_retval_p (i3))
2637 undobuf.other_insn = 0;
2639 /* Reset the hard register usage information. */
2640 CLEAR_HARD_REG_SET (newpat_used_regs);
2642 if (dump_file && (dump_flags & TDF_DETAILS))
2645 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2646 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2648 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2649 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2651 fprintf (dump_file, "\nTrying %d -> %d:\n",
2652 INSN_UID (i2), INSN_UID (i3));
2655 /* If multiple insns feed into one of I2 or I3, they can be in any
2656 order. To simplify the code below, reorder them in sequence. */
2657 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2658 temp = i2, i2 = i0, i0 = temp;
2659 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2660 temp = i1, i1 = i0, i0 = temp;
2661 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2662 temp = i1, i1 = i2, i2 = temp;
2664 added_links_insn = 0;
2666 /* First check for one important special case that the code below will
2667 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2668 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2669 we may be able to replace that destination with the destination of I3.
2670 This occurs in the common code where we compute both a quotient and
2671 remainder into a structure, in which case we want to do the computation
2672 directly into the structure to avoid register-register copies.
2674 Note that this case handles both multiple sets in I2 and also cases
2675 where I2 has a number of CLOBBERs inside the PARALLEL.
2677 We make very conservative checks below and only try to handle the
2678 most common cases of this. For example, we only handle the case
2679 where I2 and I3 are adjacent to avoid making difficult register
2682 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2683 && REG_P (SET_SRC (PATTERN (i3)))
2684 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2685 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2686 && GET_CODE (PATTERN (i2)) == PARALLEL
2687 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2688 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2689 below would need to check what is inside (and reg_overlap_mentioned_p
2690 doesn't support those codes anyway). Don't allow those destinations;
2691 the resulting insn isn't likely to be recognized anyway. */
2692 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2693 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2694 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2695 SET_DEST (PATTERN (i3)))
2696 && next_active_insn (i2) == i3)
2698 rtx p2 = PATTERN (i2);
2700 /* Make sure that the destination of I3,
2701 which we are going to substitute into one output of I2,
2702 is not used within another output of I2. We must avoid making this:
2703 (parallel [(set (mem (reg 69)) ...)
2704 (set (reg 69) ...)])
2705 which is not well-defined as to order of actions.
2706 (Besides, reload can't handle output reloads for this.)
2708 The problem can also happen if the dest of I3 is a memory ref,
2709 if another dest in I2 is an indirect memory ref. */
2710 for (i = 0; i < XVECLEN (p2, 0); i++)
2711 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2712 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2713 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2714 SET_DEST (XVECEXP (p2, 0, i))))
2717 if (i == XVECLEN (p2, 0))
2718 for (i = 0; i < XVECLEN (p2, 0); i++)
2719 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2720 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2725 subst_low_luid = DF_INSN_LUID (i2);
2727 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2728 i2src = SET_SRC (XVECEXP (p2, 0, i));
2729 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2730 i2dest_killed = dead_or_set_p (i2, i2dest);
2732 /* Replace the dest in I2 with our dest and make the resulting
2733 insn the new pattern for I3. Then skip to where we validate
2734 the pattern. Everything was set up above. */
2735 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2737 i3_subst_into_i2 = 1;
2738 goto validate_replacement;
2742 /* If I2 is setting a pseudo to a constant and I3 is setting some
2743 sub-part of it to another constant, merge them by making a new
2746 && (temp = single_set (i2)) != 0
2747 && (CONST_INT_P (SET_SRC (temp))
2748 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2749 && GET_CODE (PATTERN (i3)) == SET
2750 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2751 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2752 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2754 rtx dest = SET_DEST (PATTERN (i3));
2758 if (GET_CODE (dest) == ZERO_EXTRACT)
2760 if (CONST_INT_P (XEXP (dest, 1))
2761 && CONST_INT_P (XEXP (dest, 2)))
2763 width = INTVAL (XEXP (dest, 1));
2764 offset = INTVAL (XEXP (dest, 2));
2765 dest = XEXP (dest, 0);
2766 if (BITS_BIG_ENDIAN)
2767 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2772 if (GET_CODE (dest) == STRICT_LOW_PART)
2773 dest = XEXP (dest, 0);
2774 width = GET_MODE_BITSIZE (GET_MODE (dest));
2780 /* If this is the low part, we're done. */
2781 if (subreg_lowpart_p (dest))
2783 /* Handle the case where inner is twice the size of outer. */
2784 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2785 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2786 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2787 /* Otherwise give up for now. */
2793 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2794 <= HOST_BITS_PER_DOUBLE_INT))
2797 rtx inner = SET_SRC (PATTERN (i3));
2798 rtx outer = SET_SRC (temp);
2800 o = rtx_to_double_int (outer);
2801 i = rtx_to_double_int (inner);
2803 m = double_int_mask (width);
2804 i = double_int_and (i, m);
2805 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2806 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2807 o = double_int_ior (double_int_and_not (o, m), i);
2811 subst_low_luid = DF_INSN_LUID (i2);
2812 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2813 i2dest = SET_DEST (temp);
2814 i2dest_killed = dead_or_set_p (i2, i2dest);
2816 /* Replace the source in I2 with the new constant and make the
2817 resulting insn the new pattern for I3. Then skip to where we
2818 validate the pattern. Everything was set up above. */
2819 SUBST (SET_SRC (temp),
2820 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2822 newpat = PATTERN (i2);
2824 /* The dest of I3 has been replaced with the dest of I2. */
2825 changed_i3_dest = 1;
2826 goto validate_replacement;
2831 /* If we have no I1 and I2 looks like:
2832 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2834 make up a dummy I1 that is
2837 (set (reg:CC X) (compare:CC Y (const_int 0)))
2839 (We can ignore any trailing CLOBBERs.)
2841 This undoes a previous combination and allows us to match a branch-and-
2844 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2845 && XVECLEN (PATTERN (i2), 0) >= 2
2846 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2847 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2849 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2850 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2851 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2852 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2853 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2854 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2856 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2857 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2862 /* We make I1 with the same INSN_UID as I2. This gives it
2863 the same DF_INSN_LUID for value tracking. Our fake I1 will
2864 never appear in the insn stream so giving it the same INSN_UID
2865 as I2 will not cause a problem. */
2867 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2868 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2869 INSN_LOCATOR (i2), -1, NULL_RTX);
2871 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2872 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2873 SET_DEST (PATTERN (i1)));
2878 /* Verify that I2 and I1 are valid for combining. */
2879 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2880 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2882 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2889 /* Record whether I2DEST is used in I2SRC and similarly for the other
2890 cases. Knowing this will help in register status updating below. */
2891 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2892 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2893 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2894 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2895 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2896 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2897 i2dest_killed = dead_or_set_p (i2, i2dest);
2898 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2899 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2901 /* For the earlier insns, determine which of the subsequent ones they
2903 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2904 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2905 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2906 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2907 && reg_overlap_mentioned_p (i0dest, i2src))));
2909 /* Ensure that I3's pattern can be the destination of combines. */
2910 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2911 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2912 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2913 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2920 /* See if any of the insns is a MULT operation. Unless one is, we will
2921 reject a combination that is, since it must be slower. Be conservative
2923 if (GET_CODE (i2src) == MULT
2924 || (i1 != 0 && GET_CODE (i1src) == MULT)
2925 || (i0 != 0 && GET_CODE (i0src) == MULT)
2926 || (GET_CODE (PATTERN (i3)) == SET
2927 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2930 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2931 We used to do this EXCEPT in one case: I3 has a post-inc in an
2932 output operand. However, that exception can give rise to insns like
2934 which is a famous insn on the PDP-11 where the value of r3 used as the
2935 source was model-dependent. Avoid this sort of thing. */
2938 if (!(GET_CODE (PATTERN (i3)) == SET
2939 && REG_P (SET_SRC (PATTERN (i3)))
2940 && MEM_P (SET_DEST (PATTERN (i3)))
2941 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2942 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2943 /* It's not the exception. */
2946 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2947 if (REG_NOTE_KIND (link) == REG_INC
2948 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2950 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2957 /* See if the SETs in I1 or I2 need to be kept around in the merged
2958 instruction: whenever the value set there is still needed past I3.
2959 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2961 For the SET in I1, we have two cases: If I1 and I2 independently
2962 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2963 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2964 in I1 needs to be kept around unless I1DEST dies or is set in either
2965 I2 or I3. The same consideration applies to I0. */
2967 added_sets_2 = !dead_or_set_p (i3, i2dest);
2970 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2971 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2976 added_sets_0 = !(dead_or_set_p (i3, i0dest)
2977 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
2978 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
2982 /* We are about to copy insns for the case where they need to be kept
2983 around. Check that they can be copied in the merged instruction. */
2985 if (targetm.cannot_copy_insn_p
2986 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2987 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2988 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2994 /* If the set in I2 needs to be kept around, we must make a copy of
2995 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2996 PATTERN (I2), we are only substituting for the original I1DEST, not into
2997 an already-substituted copy. This also prevents making self-referential
2998 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3003 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3004 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3006 i2pat = copy_rtx (PATTERN (i2));
3011 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3012 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3014 i1pat = copy_rtx (PATTERN (i1));
3019 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3020 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3022 i0pat = copy_rtx (PATTERN (i0));
3027 /* Substitute in the latest insn for the regs set by the earlier ones. */
3029 maxreg = max_reg_num ();
3034 /* Many machines that don't use CC0 have insns that can both perform an
3035 arithmetic operation and set the condition code. These operations will
3036 be represented as a PARALLEL with the first element of the vector
3037 being a COMPARE of an arithmetic operation with the constant zero.
3038 The second element of the vector will set some pseudo to the result
3039 of the same arithmetic operation. If we simplify the COMPARE, we won't
3040 match such a pattern and so will generate an extra insn. Here we test
3041 for this case, where both the comparison and the operation result are
3042 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3043 I2SRC. Later we will make the PARALLEL that contains I2. */
3045 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3046 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3047 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
3048 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3050 #ifdef SELECT_CC_MODE
3052 enum machine_mode compare_mode;
3055 newpat = PATTERN (i3);
3056 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
3060 #ifdef SELECT_CC_MODE
3061 /* See if a COMPARE with the operand we substituted in should be done
3062 with the mode that is currently being used. If not, do the same
3063 processing we do in `subst' for a SET; namely, if the destination
3064 is used only once, try to replace it with a register of the proper
3065 mode and also replace the COMPARE. */
3066 if (undobuf.other_insn == 0
3067 && (cc_use = find_single_use (SET_DEST (newpat), i3,
3068 &undobuf.other_insn))
3069 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
3071 != GET_MODE (SET_DEST (newpat))))
3073 if (can_change_dest_mode (SET_DEST (newpat), added_sets_2,
3076 unsigned int regno = REGNO (SET_DEST (newpat));
3079 if (regno < FIRST_PSEUDO_REGISTER)
3080 new_dest = gen_rtx_REG (compare_mode, regno);
3083 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3084 new_dest = regno_reg_rtx[regno];
3087 SUBST (SET_DEST (newpat), new_dest);
3088 SUBST (XEXP (*cc_use, 0), new_dest);
3089 SUBST (SET_SRC (newpat),
3090 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
3093 undobuf.other_insn = 0;
3100 /* It is possible that the source of I2 or I1 may be performing
3101 an unneeded operation, such as a ZERO_EXTEND of something
3102 that is known to have the high part zero. Handle that case
3103 by letting subst look at the innermost one of them.
3105 Another way to do this would be to have a function that tries
3106 to simplify a single insn instead of merging two or more
3107 insns. We don't do this because of the potential of infinite
3108 loops and because of the potential extra memory required.
3109 However, doing it the way we are is a bit of a kludge and
3110 doesn't catch all cases.
3112 But only do this if -fexpensive-optimizations since it slows
3113 things down and doesn't usually win.
3115 This is not done in the COMPARE case above because the
3116 unmodified I2PAT is used in the PARALLEL and so a pattern
3117 with a modified I2SRC would not match. */
3119 if (flag_expensive_optimizations)
3121 /* Pass pc_rtx so no substitutions are done, just
3125 subst_low_luid = DF_INSN_LUID (i1);
3126 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
3130 subst_low_luid = DF_INSN_LUID (i2);
3131 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
3135 n_occurrences = 0; /* `subst' counts here */
3136 subst_low_luid = DF_INSN_LUID (i2);
3138 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3139 copy of I2SRC each time we substitute it, in order to avoid creating
3140 self-referential RTL when we will be substituting I1SRC for I1DEST
3141 later. Likewise if I0 feeds into I2, either directly or indirectly
3142 through I1, and I0DEST is in I0SRC. */
3143 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
3144 (i1_feeds_i2_n && i1dest_in_i1src)
3145 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3146 && i0dest_in_i0src));
3149 /* Record whether I2's body now appears within I3's body. */
3150 i2_is_used = n_occurrences;
3153 /* If we already got a failure, don't try to do more. Otherwise, try to
3154 substitute I1 if we have it. */
3156 if (i1 && GET_CODE (newpat) != CLOBBER)
3158 /* Check that an autoincrement side-effect on I1 has not been lost.
3159 This happens if I1DEST is mentioned in I2 and dies there, and
3160 has disappeared from the new pattern. */
3161 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3163 && dead_or_set_p (i2, i1dest)
3164 && !reg_overlap_mentioned_p (i1dest, newpat))
3165 /* Before we can do this substitution, we must redo the test done
3166 above (see detailed comments there) that ensures I1DEST isn't
3167 mentioned in any SETs in NEWPAT that are field assignments. */
3168 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3176 subst_low_luid = DF_INSN_LUID (i1);
3178 /* If the following substitution will modify I1SRC, make a copy of it
3179 for the case where it is substituted for I1DEST in I2PAT later. */
3180 if (added_sets_2 && i1_feeds_i2_n)
3181 i1src_copy = copy_rtx (i1src);
3183 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3184 copy of I1SRC each time we substitute it, in order to avoid creating
3185 self-referential RTL when we will be substituting I0SRC for I0DEST
3187 newpat = subst (newpat, i1dest, i1src, 0,
3188 i0_feeds_i1_n && i0dest_in_i0src);
3191 /* Record whether I1's body now appears within I3's body. */
3192 i1_is_used = n_occurrences;
3195 /* Likewise for I0 if we have it. */
3197 if (i0 && GET_CODE (newpat) != CLOBBER)
3199 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3200 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3201 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3202 && !reg_overlap_mentioned_p (i0dest, newpat))
3203 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3210 /* If the following substitution will modify I0SRC, make a copy of it
3211 for the case where it is substituted for I0DEST in I1PAT later. */
3212 if (added_sets_1 && i0_feeds_i1_n)
3213 i0src_copy = copy_rtx (i0src);
3214 /* And a copy for I0DEST in I2PAT substitution. */
3215 if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3216 || (i0_feeds_i2_n)))
3217 i0src_copy2 = copy_rtx (i0src);
3220 subst_low_luid = DF_INSN_LUID (i0);
3221 newpat = subst (newpat, i0dest, i0src, 0, 0);
3225 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3226 to count all the ways that I2SRC and I1SRC can be used. */
3227 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3228 && i2_is_used + added_sets_2 > 1)
3229 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3230 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3232 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3233 && (n_occurrences + added_sets_0
3234 + (added_sets_1 && i0_feeds_i1_n)
3235 + (added_sets_2 && i0_feeds_i2_n)
3237 /* Fail if we tried to make a new register. */
3238 || max_reg_num () != maxreg
3239 /* Fail if we couldn't do something and have a CLOBBER. */
3240 || GET_CODE (newpat) == CLOBBER
3241 /* Fail if this new pattern is a MULT and we didn't have one before
3242 at the outer level. */
3243 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3250 /* If the actions of the earlier insns must be kept
3251 in addition to substituting them into the latest one,
3252 we must make a new PARALLEL for the latest insn
3253 to hold additional the SETs. */
3255 if (added_sets_0 || added_sets_1 || added_sets_2)
3257 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3260 if (GET_CODE (newpat) == PARALLEL)
3262 rtvec old = XVEC (newpat, 0);
3263 total_sets = XVECLEN (newpat, 0) + extra_sets;
3264 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3265 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3266 sizeof (old->elem[0]) * old->num_elem);
3271 total_sets = 1 + extra_sets;
3272 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3273 XVECEXP (newpat, 0, 0) = old;
3277 XVECEXP (newpat, 0, --total_sets) = i0pat;
3283 t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0);
3285 XVECEXP (newpat, 0, --total_sets) = t;
3291 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0,
3292 i0_feeds_i1_n && i0dest_in_i0src);
3293 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3294 t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0);
3296 XVECEXP (newpat, 0, --total_sets) = t;
3300 validate_replacement:
3302 /* Note which hard regs this insn has as inputs. */
3303 mark_used_regs_combine (newpat);
3305 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3306 consider splitting this pattern, we might need these clobbers. */
3307 if (i1 && GET_CODE (newpat) == PARALLEL
3308 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3310 int len = XVECLEN (newpat, 0);
3312 newpat_vec_with_clobbers = rtvec_alloc (len);
3313 for (i = 0; i < len; i++)
3314 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3317 /* Is the result of combination a valid instruction? */
3318 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3320 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3321 the second SET's destination is a register that is unused and isn't
3322 marked as an instruction that might trap in an EH region. In that case,
3323 we just need the first SET. This can occur when simplifying a divmod
3324 insn. We *must* test for this case here because the code below that
3325 splits two independent SETs doesn't handle this case correctly when it
3326 updates the register status.
3328 It's pointless doing this if we originally had two sets, one from
3329 i3, and one from i2. Combining then splitting the parallel results
3330 in the original i2 again plus an invalid insn (which we delete).
3331 The net effect is only to move instructions around, which makes
3332 debug info less accurate.
3334 Also check the case where the first SET's destination is unused.
3335 That would not cause incorrect code, but does cause an unneeded
3338 if (insn_code_number < 0
3339 && !(added_sets_2 && i1 == 0)
3340 && GET_CODE (newpat) == PARALLEL
3341 && XVECLEN (newpat, 0) == 2
3342 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3343 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3344 && asm_noperands (newpat) < 0)
3346 rtx set0 = XVECEXP (newpat, 0, 0);
3347 rtx set1 = XVECEXP (newpat, 0, 1);
3349 if (((REG_P (SET_DEST (set1))
3350 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3351 || (GET_CODE (SET_DEST (set1)) == SUBREG
3352 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3353 && insn_nothrow_p (i3)
3354 && !side_effects_p (SET_SRC (set1)))
3357 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3360 else if (((REG_P (SET_DEST (set0))
3361 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3362 || (GET_CODE (SET_DEST (set0)) == SUBREG
3363 && find_reg_note (i3, REG_UNUSED,
3364 SUBREG_REG (SET_DEST (set0)))))
3365 && insn_nothrow_p (i3)
3366 && !side_effects_p (SET_SRC (set0)))
3369 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3371 if (insn_code_number >= 0)
3372 changed_i3_dest = 1;
3376 /* If we were combining three insns and the result is a simple SET
3377 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3378 insns. There are two ways to do this. It can be split using a
3379 machine-specific method (like when you have an addition of a large
3380 constant) or by combine in the function find_split_point. */
3382 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3383 && asm_noperands (newpat) < 0)
3385 rtx parallel, m_split, *split;
3387 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3388 use I2DEST as a scratch register will help. In the latter case,
3389 convert I2DEST to the mode of the source of NEWPAT if we can. */
3391 m_split = combine_split_insns (newpat, i3);
3393 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3394 inputs of NEWPAT. */
3396 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3397 possible to try that as a scratch reg. This would require adding
3398 more code to make it work though. */
3400 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3402 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3404 /* First try to split using the original register as a
3405 scratch register. */
3406 parallel = gen_rtx_PARALLEL (VOIDmode,
3407 gen_rtvec (2, newpat,
3408 gen_rtx_CLOBBER (VOIDmode,
3410 m_split = combine_split_insns (parallel, i3);
3412 /* If that didn't work, try changing the mode of I2DEST if
3415 && new_mode != GET_MODE (i2dest)
3416 && new_mode != VOIDmode
3417 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3419 enum machine_mode old_mode = GET_MODE (i2dest);
3422 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3423 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3426 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3427 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3430 parallel = (gen_rtx_PARALLEL
3432 gen_rtvec (2, newpat,
3433 gen_rtx_CLOBBER (VOIDmode,
3435 m_split = combine_split_insns (parallel, i3);
3438 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3442 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3443 buf = undobuf.undos;
3444 undobuf.undos = buf->next;
3445 buf->next = undobuf.frees;
3446 undobuf.frees = buf;
3450 i2scratch = m_split != 0;
3453 /* If recog_for_combine has discarded clobbers, try to use them
3454 again for the split. */
3455 if (m_split == 0 && newpat_vec_with_clobbers)
3457 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3458 m_split = combine_split_insns (parallel, i3);
3461 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3463 m_split = PATTERN (m_split);
3464 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3465 if (insn_code_number >= 0)
3468 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3469 && (next_real_insn (i2) == i3
3470 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3473 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3474 newi2pat = PATTERN (m_split);
3476 i3set = single_set (NEXT_INSN (m_split));
3477 i2set = single_set (m_split);
3479 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3481 /* If I2 or I3 has multiple SETs, we won't know how to track
3482 register status, so don't use these insns. If I2's destination
3483 is used between I2 and I3, we also can't use these insns. */
3485 if (i2_code_number >= 0 && i2set && i3set
3486 && (next_real_insn (i2) == i3
3487 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3488 insn_code_number = recog_for_combine (&newi3pat, i3,
3490 if (insn_code_number >= 0)
3493 /* It is possible that both insns now set the destination of I3.
3494 If so, we must show an extra use of it. */
3496 if (insn_code_number >= 0)
3498 rtx new_i3_dest = SET_DEST (i3set);
3499 rtx new_i2_dest = SET_DEST (i2set);
3501 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3502 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3503 || GET_CODE (new_i3_dest) == SUBREG)
3504 new_i3_dest = XEXP (new_i3_dest, 0);
3506 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3507 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3508 || GET_CODE (new_i2_dest) == SUBREG)
3509 new_i2_dest = XEXP (new_i2_dest, 0);
3511 if (REG_P (new_i3_dest)
3512 && REG_P (new_i2_dest)
3513 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3514 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3518 /* If we can split it and use I2DEST, go ahead and see if that
3519 helps things be recognized. Verify that none of the registers
3520 are set between I2 and I3. */
3521 if (insn_code_number < 0
3522 && (split = find_split_point (&newpat, i3, false)) != 0
3526 /* We need I2DEST in the proper mode. If it is a hard register
3527 or the only use of a pseudo, we can change its mode.
3528 Make sure we don't change a hard register to have a mode that
3529 isn't valid for it, or change the number of registers. */
3530 && (GET_MODE (*split) == GET_MODE (i2dest)
3531 || GET_MODE (*split) == VOIDmode
3532 || can_change_dest_mode (i2dest, added_sets_2,
3534 && (next_real_insn (i2) == i3
3535 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3536 /* We can't overwrite I2DEST if its value is still used by
3538 && ! reg_referenced_p (i2dest, newpat))
3540 rtx newdest = i2dest;
3541 enum rtx_code split_code = GET_CODE (*split);
3542 enum machine_mode split_mode = GET_MODE (*split);
3543 bool subst_done = false;
3544 newi2pat = NULL_RTX;
3548 /* *SPLIT may be part of I2SRC, so make sure we have the
3549 original expression around for later debug processing.
3550 We should not need I2SRC any more in other cases. */
3551 if (MAY_HAVE_DEBUG_INSNS)
3552 i2src = copy_rtx (i2src);
3556 /* Get NEWDEST as a register in the proper mode. We have already
3557 validated that we can do this. */
3558 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3560 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3561 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3564 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3565 newdest = regno_reg_rtx[REGNO (i2dest)];
3569 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3570 an ASHIFT. This can occur if it was inside a PLUS and hence
3571 appeared to be a memory address. This is a kludge. */
3572 if (split_code == MULT
3573 && CONST_INT_P (XEXP (*split, 1))
3574 && INTVAL (XEXP (*split, 1)) > 0
3575 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3577 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3578 XEXP (*split, 0), GEN_INT (i)));
3579 /* Update split_code because we may not have a multiply
3581 split_code = GET_CODE (*split);
3584 #ifdef INSN_SCHEDULING
3585 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3586 be written as a ZERO_EXTEND. */
3587 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3589 #ifdef LOAD_EXTEND_OP
3590 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3591 what it really is. */
3592 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3594 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3595 SUBREG_REG (*split)));
3598 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3599 SUBREG_REG (*split)));
3603 /* Attempt to split binary operators using arithmetic identities. */
3604 if (BINARY_P (SET_SRC (newpat))
3605 && split_mode == GET_MODE (SET_SRC (newpat))
3606 && ! side_effects_p (SET_SRC (newpat)))
3608 rtx setsrc = SET_SRC (newpat);
3609 enum machine_mode mode = GET_MODE (setsrc);
3610 enum rtx_code code = GET_CODE (setsrc);
3611 rtx src_op0 = XEXP (setsrc, 0);
3612 rtx src_op1 = XEXP (setsrc, 1);
3614 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3615 if (rtx_equal_p (src_op0, src_op1))
3617 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3618 SUBST (XEXP (setsrc, 0), newdest);
3619 SUBST (XEXP (setsrc, 1), newdest);
3622 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3623 else if ((code == PLUS || code == MULT)
3624 && GET_CODE (src_op0) == code
3625 && GET_CODE (XEXP (src_op0, 0)) == code
3626 && (INTEGRAL_MODE_P (mode)
3627 || (FLOAT_MODE_P (mode)
3628 && flag_unsafe_math_optimizations)))
3630 rtx p = XEXP (XEXP (src_op0, 0), 0);
3631 rtx q = XEXP (XEXP (src_op0, 0), 1);
3632 rtx r = XEXP (src_op0, 1);
3635 /* Split both "((X op Y) op X) op Y" and
3636 "((X op Y) op Y) op X" as "T op T" where T is
3638 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3639 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3641 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3643 SUBST (XEXP (setsrc, 0), newdest);
3644 SUBST (XEXP (setsrc, 1), newdest);
3647 /* Split "((X op X) op Y) op Y)" as "T op T" where
3649 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3651 rtx tmp = simplify_gen_binary (code, mode, p, r);
3652 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3653 SUBST (XEXP (setsrc, 0), newdest);
3654 SUBST (XEXP (setsrc, 1), newdest);
3662 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3663 SUBST (*split, newdest);
3666 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3668 /* recog_for_combine might have added CLOBBERs to newi2pat.
3669 Make sure NEWPAT does not depend on the clobbered regs. */
3670 if (GET_CODE (newi2pat) == PARALLEL)
3671 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3672 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3674 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3675 if (reg_overlap_mentioned_p (reg, newpat))
3682 /* If the split point was a MULT and we didn't have one before,
3683 don't use one now. */
3684 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3685 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3689 /* Check for a case where we loaded from memory in a narrow mode and
3690 then sign extended it, but we need both registers. In that case,
3691 we have a PARALLEL with both loads from the same memory location.
3692 We can split this into a load from memory followed by a register-register
3693 copy. This saves at least one insn, more if register allocation can
3696 We cannot do this if the destination of the first assignment is a
3697 condition code register or cc0. We eliminate this case by making sure
3698 the SET_DEST and SET_SRC have the same mode.
3700 We cannot do this if the destination of the second assignment is
3701 a register that we have already assumed is zero-extended. Similarly
3702 for a SUBREG of such a register. */
3704 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3705 && GET_CODE (newpat) == PARALLEL
3706 && XVECLEN (newpat, 0) == 2
3707 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3708 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3709 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3710 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3711 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3712 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3713 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3714 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3716 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3717 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3718 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3720 && VEC_index (reg_stat_type, reg_stat,
3721 REGNO (temp))->nonzero_bits != 0
3722 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3723 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3724 && (VEC_index (reg_stat_type, reg_stat,
3725 REGNO (temp))->nonzero_bits
3726 != GET_MODE_MASK (word_mode))))
3727 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3728 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3730 && VEC_index (reg_stat_type, reg_stat,
3731 REGNO (temp))->nonzero_bits != 0
3732 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3733 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3734 && (VEC_index (reg_stat_type, reg_stat,
3735 REGNO (temp))->nonzero_bits
3736 != GET_MODE_MASK (word_mode)))))
3737 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3738 SET_SRC (XVECEXP (newpat, 0, 1)))
3739 && ! find_reg_note (i3, REG_UNUSED,
3740 SET_DEST (XVECEXP (newpat, 0, 0))))
3744 newi2pat = XVECEXP (newpat, 0, 0);
3745 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3746 newpat = XVECEXP (newpat, 0, 1);
3747 SUBST (SET_SRC (newpat),
3748 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3749 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3751 if (i2_code_number >= 0)
3752 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3754 if (insn_code_number >= 0)
3758 /* Similarly, check for a case where we have a PARALLEL of two independent
3759 SETs but we started with three insns. In this case, we can do the sets
3760 as two separate insns. This case occurs when some SET allows two
3761 other insns to combine, but the destination of that SET is still live. */
3763 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3764 && GET_CODE (newpat) == PARALLEL
3765 && XVECLEN (newpat, 0) == 2
3766 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3767 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3768 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3769 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3770 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3771 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3772 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3773 XVECEXP (newpat, 0, 0))
3774 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3775 XVECEXP (newpat, 0, 1))
3776 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3777 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3779 /* Normally, it doesn't matter which of the two is done first,
3780 but the one that references cc0 can't be the second, and
3781 one which uses any regs/memory set in between i2 and i3 can't
3783 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3786 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3790 newi2pat = XVECEXP (newpat, 0, 1);
3791 newpat = XVECEXP (newpat, 0, 0);
3793 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3796 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3800 newi2pat = XVECEXP (newpat, 0, 0);
3801 newpat = XVECEXP (newpat, 0, 1);
3809 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3811 if (i2_code_number >= 0)
3813 /* recog_for_combine might have added CLOBBERs to newi2pat.
3814 Make sure NEWPAT does not depend on the clobbered regs. */
3815 if (GET_CODE (newi2pat) == PARALLEL)
3817 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3818 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3820 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3821 if (reg_overlap_mentioned_p (reg, newpat))
3829 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3833 /* If it still isn't recognized, fail and change things back the way they
3835 if ((insn_code_number < 0
3836 /* Is the result a reasonable ASM_OPERANDS? */
3837 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3843 /* If we had to change another insn, make sure it is valid also. */
3844 if (undobuf.other_insn)
3846 CLEAR_HARD_REG_SET (newpat_used_regs);
3848 other_pat = PATTERN (undobuf.other_insn);
3849 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3852 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3860 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3861 they are adjacent to each other or not. */
3863 rtx p = prev_nonnote_insn (i3);
3864 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3865 && sets_cc0_p (newi2pat))
3873 /* Only allow this combination if insn_rtx_costs reports that the
3874 replacement instructions are cheaper than the originals. */
3875 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3881 if (MAY_HAVE_DEBUG_INSNS)
3885 for (undo = undobuf.undos; undo; undo = undo->next)
3886 if (undo->kind == UNDO_MODE)
3888 rtx reg = *undo->where.r;
3889 enum machine_mode new_mode = GET_MODE (reg);
3890 enum machine_mode old_mode = undo->old_contents.m;
3892 /* Temporarily revert mode back. */
3893 adjust_reg_mode (reg, old_mode);
3895 if (reg == i2dest && i2scratch)
3897 /* If we used i2dest as a scratch register with a
3898 different mode, substitute it for the original
3899 i2src while its original mode is temporarily
3900 restored, and then clear i2scratch so that we don't
3901 do it again later. */
3902 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3904 /* Put back the new mode. */
3905 adjust_reg_mode (reg, new_mode);
3909 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3915 last = last_combined_insn;
3920 last = undobuf.other_insn;
3922 if (DF_INSN_LUID (last)
3923 < DF_INSN_LUID (last_combined_insn))
3924 last = last_combined_insn;
3927 /* We're dealing with a reg that changed mode but not
3928 meaning, so we want to turn it into a subreg for
3929 the new mode. However, because of REG sharing and
3930 because its mode had already changed, we have to do
3931 it in two steps. First, replace any debug uses of
3932 reg, with its original mode temporarily restored,
3933 with this copy we have created; then, replace the
3934 copy with the SUBREG of the original shared reg,
3935 once again changed to the new mode. */
3936 propagate_for_debug (first, last, reg, tempreg);
3937 adjust_reg_mode (reg, new_mode);
3938 propagate_for_debug (first, last, tempreg,
3939 lowpart_subreg (old_mode, reg, new_mode));
3944 /* If we will be able to accept this, we have made a
3945 change to the destination of I3. This requires us to
3946 do a few adjustments. */
3948 if (changed_i3_dest)
3950 PATTERN (i3) = newpat;
3951 adjust_for_new_dest (i3);
3954 /* We now know that we can do this combination. Merge the insns and
3955 update the status of registers and LOG_LINKS. */
3957 if (undobuf.other_insn)
3961 PATTERN (undobuf.other_insn) = other_pat;
3963 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3964 are still valid. Then add any non-duplicate notes added by
3965 recog_for_combine. */
3966 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3968 next = XEXP (note, 1);
3970 if (REG_NOTE_KIND (note) == REG_UNUSED
3971 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3972 remove_note (undobuf.other_insn, note);
3975 distribute_notes (new_other_notes, undobuf.other_insn,
3976 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
3986 /* I3 now uses what used to be its destination and which is now
3987 I2's destination. This requires us to do a few adjustments. */
3988 PATTERN (i3) = newpat;
3989 adjust_for_new_dest (i3);
3991 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3994 However, some later insn might be using I2's dest and have
3995 a LOG_LINK pointing at I3. We must remove this link.
3996 The simplest way to remove the link is to point it at I1,
3997 which we know will be a NOTE. */
3999 /* newi2pat is usually a SET here; however, recog_for_combine might
4000 have added some clobbers. */
4001 if (GET_CODE (newi2pat) == PARALLEL)
4002 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4004 ni2dest = SET_DEST (newi2pat);
4006 for (insn = NEXT_INSN (i3);
4007 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4008 || insn != BB_HEAD (this_basic_block->next_bb));
4009 insn = NEXT_INSN (insn))
4011 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4013 for (link = LOG_LINKS (insn); link;
4014 link = XEXP (link, 1))
4015 if (XEXP (link, 0) == i3)
4016 XEXP (link, 0) = i1;
4024 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4025 rtx i3links, i2links, i1links = 0, i0links = 0;
4029 /* Compute which registers we expect to eliminate. newi2pat may be setting
4030 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4031 same as i3dest, in which case newi2pat may be setting i1dest. */
4032 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4033 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4036 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4037 || (newi2pat && reg_set_p (i1dest, newi2pat))
4040 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4041 || (newi2pat && reg_set_p (i0dest, newi2pat))
4045 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4047 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4048 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4050 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4052 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4054 /* Ensure that we do not have something that should not be shared but
4055 occurs multiple times in the new insns. Check this by first
4056 resetting all the `used' flags and then copying anything is shared. */
4058 reset_used_flags (i3notes);
4059 reset_used_flags (i2notes);
4060 reset_used_flags (i1notes);
4061 reset_used_flags (i0notes);
4062 reset_used_flags (newpat);
4063 reset_used_flags (newi2pat);
4064 if (undobuf.other_insn)
4065 reset_used_flags (PATTERN (undobuf.other_insn));
4067 i3notes = copy_rtx_if_shared (i3notes);
4068 i2notes = copy_rtx_if_shared (i2notes);
4069 i1notes = copy_rtx_if_shared (i1notes);
4070 i0notes = copy_rtx_if_shared (i0notes);
4071 newpat = copy_rtx_if_shared (newpat);
4072 newi2pat = copy_rtx_if_shared (newi2pat);
4073 if (undobuf.other_insn)
4074 reset_used_flags (PATTERN (undobuf.other_insn));
4076 INSN_CODE (i3) = insn_code_number;
4077 PATTERN (i3) = newpat;
4079 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4081 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4083 reset_used_flags (call_usage);
4084 call_usage = copy_rtx (call_usage);
4088 /* I2SRC must still be meaningful at this point. Some splitting
4089 operations can invalidate I2SRC, but those operations do not
4092 replace_rtx (call_usage, i2dest, i2src);
4096 replace_rtx (call_usage, i1dest, i1src);
4098 replace_rtx (call_usage, i0dest, i0src);
4100 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4103 if (undobuf.other_insn)
4104 INSN_CODE (undobuf.other_insn) = other_code_number;
4106 /* We had one special case above where I2 had more than one set and
4107 we replaced a destination of one of those sets with the destination
4108 of I3. In that case, we have to update LOG_LINKS of insns later
4109 in this basic block. Note that this (expensive) case is rare.
4111 Also, in this case, we must pretend that all REG_NOTEs for I2
4112 actually came from I3, so that REG_UNUSED notes from I2 will be
4113 properly handled. */
4115 if (i3_subst_into_i2)
4117 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4118 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4119 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4120 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4121 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4122 && ! find_reg_note (i2, REG_UNUSED,
4123 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4124 for (temp = NEXT_INSN (i2);
4125 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4126 || BB_HEAD (this_basic_block) != temp);
4127 temp = NEXT_INSN (temp))
4128 if (temp != i3 && INSN_P (temp))
4129 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
4130 if (XEXP (link, 0) == i2)
4131 XEXP (link, 0) = i3;
4136 while (XEXP (link, 1))
4137 link = XEXP (link, 1);
4138 XEXP (link, 1) = i2notes;
4152 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4153 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4154 INSN_CODE (i2) = i2_code_number;
4155 PATTERN (i2) = newi2pat;
4159 if (MAY_HAVE_DEBUG_INSNS && i2src)
4160 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4161 SET_INSN_DELETED (i2);
4168 if (MAY_HAVE_DEBUG_INSNS)
4169 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4170 SET_INSN_DELETED (i1);
4177 if (MAY_HAVE_DEBUG_INSNS)
4178 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4179 SET_INSN_DELETED (i0);
4182 /* Get death notes for everything that is now used in either I3 or
4183 I2 and used to die in a previous insn. If we built two new
4184 patterns, move from I1 to I2 then I2 to I3 so that we get the
4185 proper movement on registers that I2 modifies. */
4188 from_luid = DF_INSN_LUID (i0);
4190 from_luid = DF_INSN_LUID (i1);
4192 from_luid = DF_INSN_LUID (i2);
4194 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4195 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4197 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4199 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4200 elim_i2, elim_i1, elim_i0);
4202 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4203 elim_i2, elim_i1, elim_i0);
4205 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4206 elim_i2, elim_i1, elim_i0);
4208 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4209 elim_i2, elim_i1, elim_i0);
4211 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4212 elim_i2, elim_i1, elim_i0);
4214 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4215 know these are REG_UNUSED and want them to go to the desired insn,
4216 so we always pass it as i3. */
4218 if (newi2pat && new_i2_notes)
4219 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4223 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4226 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4227 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4228 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4229 in that case, it might delete I2. Similarly for I2 and I1.
4230 Show an additional death due to the REG_DEAD note we make here. If
4231 we discard it in distribute_notes, we will decrement it again. */
4235 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4236 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4238 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4240 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4242 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4243 elim_i2, elim_i1, elim_i0);
4246 if (i2dest_in_i2src)
4248 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4249 if (newi2pat && reg_set_p (i2dest, newi2pat))
4250 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4251 NULL_RTX, NULL_RTX);
4253 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4254 NULL_RTX, NULL_RTX, NULL_RTX);
4257 if (i1dest_in_i1src)
4259 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4260 if (newi2pat && reg_set_p (i1dest, newi2pat))
4261 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4262 NULL_RTX, NULL_RTX);
4264 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4265 NULL_RTX, NULL_RTX, NULL_RTX);
4268 if (i0dest_in_i0src)
4270 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4271 if (newi2pat && reg_set_p (i0dest, newi2pat))
4272 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4273 NULL_RTX, NULL_RTX);
4275 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4276 NULL_RTX, NULL_RTX, NULL_RTX);
4279 distribute_links (i3links);
4280 distribute_links (i2links);
4281 distribute_links (i1links);
4282 distribute_links (i0links);
4287 rtx i2_insn = 0, i2_val = 0, set;
4289 /* The insn that used to set this register doesn't exist, and
4290 this life of the register may not exist either. See if one of
4291 I3's links points to an insn that sets I2DEST. If it does,
4292 that is now the last known value for I2DEST. If we don't update
4293 this and I2 set the register to a value that depended on its old
4294 contents, we will get confused. If this insn is used, thing
4295 will be set correctly in combine_instructions. */
4297 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4298 if ((set = single_set (XEXP (link, 0))) != 0
4299 && rtx_equal_p (i2dest, SET_DEST (set)))
4300 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
4302 record_value_for_reg (i2dest, i2_insn, i2_val);
4304 /* If the reg formerly set in I2 died only once and that was in I3,
4305 zero its use count so it won't make `reload' do any work. */
4307 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4308 && ! i2dest_in_i2src)
4310 regno = REGNO (i2dest);
4311 INC_REG_N_SETS (regno, -1);
4315 if (i1 && REG_P (i1dest))
4318 rtx i1_insn = 0, i1_val = 0, set;
4320 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4321 if ((set = single_set (XEXP (link, 0))) != 0
4322 && rtx_equal_p (i1dest, SET_DEST (set)))
4323 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
4325 record_value_for_reg (i1dest, i1_insn, i1_val);
4327 regno = REGNO (i1dest);
4328 if (! added_sets_1 && ! i1dest_in_i1src)
4329 INC_REG_N_SETS (regno, -1);
4332 if (i0 && REG_P (i0dest))
4335 rtx i0_insn = 0, i0_val = 0, set;
4337 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
4338 if ((set = single_set (XEXP (link, 0))) != 0
4339 && rtx_equal_p (i0dest, SET_DEST (set)))
4340 i0_insn = XEXP (link, 0), i0_val = SET_SRC (set);
4342 record_value_for_reg (i0dest, i0_insn, i0_val);
4344 regno = REGNO (i0dest);
4345 if (! added_sets_0 && ! i0dest_in_i0src)
4346 INC_REG_N_SETS (regno, -1);
4349 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4350 been made to this insn. The order of
4351 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4352 can affect nonzero_bits of newpat */
4354 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4355 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4358 if (undobuf.other_insn != NULL_RTX)
4362 fprintf (dump_file, "modifying other_insn ");
4363 dump_insn_slim (dump_file, undobuf.other_insn);
4365 df_insn_rescan (undobuf.other_insn);
4368 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4372 fprintf (dump_file, "modifying insn i1 ");
4373 dump_insn_slim (dump_file, i0);
4375 df_insn_rescan (i0);
4378 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4382 fprintf (dump_file, "modifying insn i1 ");
4383 dump_insn_slim (dump_file, i1);
4385 df_insn_rescan (i1);
4388 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4392 fprintf (dump_file, "modifying insn i2 ");
4393 dump_insn_slim (dump_file, i2);
4395 df_insn_rescan (i2);
4398 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4402 fprintf (dump_file, "modifying insn i3 ");
4403 dump_insn_slim (dump_file, i3);
4405 df_insn_rescan (i3);
4408 /* Set new_direct_jump_p if a new return or simple jump instruction
4409 has been created. Adjust the CFG accordingly. */
4411 if (returnjump_p (i3) || any_uncondjump_p (i3))
4413 *new_direct_jump_p = 1;
4414 mark_jump_label (PATTERN (i3), i3, 0);
4415 update_cfg_for_uncondjump (i3);
4418 if (undobuf.other_insn != NULL_RTX
4419 && (returnjump_p (undobuf.other_insn)
4420 || any_uncondjump_p (undobuf.other_insn)))
4422 *new_direct_jump_p = 1;
4423 update_cfg_for_uncondjump (undobuf.other_insn);
4426 /* A noop might also need cleaning up of CFG, if it comes from the
4427 simplification of a jump. */
4428 if (GET_CODE (newpat) == SET
4429 && SET_SRC (newpat) == pc_rtx
4430 && SET_DEST (newpat) == pc_rtx)
4432 *new_direct_jump_p = 1;
4433 update_cfg_for_uncondjump (i3);
4436 if (undobuf.other_insn != NULL_RTX
4437 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4438 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4439 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4441 *new_direct_jump_p = 1;
4442 update_cfg_for_uncondjump (undobuf.other_insn);
4445 combine_successes++;
4448 if (added_links_insn
4449 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4450 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4451 return added_links_insn;
4453 return newi2pat ? i2 : i3;
4456 /* Undo all the modifications recorded in undobuf. */
4461 struct undo *undo, *next;
4463 for (undo = undobuf.undos; undo; undo = next)
4469 *undo->where.r = undo->old_contents.r;
4472 *undo->where.i = undo->old_contents.i;
4475 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4481 undo->next = undobuf.frees;
4482 undobuf.frees = undo;
4488 /* We've committed to accepting the changes we made. Move all
4489 of the undos to the free list. */
4494 struct undo *undo, *next;
4496 for (undo = undobuf.undos; undo; undo = next)
4499 undo->next = undobuf.frees;
4500 undobuf.frees = undo;
4505 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4506 where we have an arithmetic expression and return that point. LOC will
4509 try_combine will call this function to see if an insn can be split into
4513 find_split_point (rtx *loc, rtx insn, bool set_src)
4516 enum rtx_code code = GET_CODE (x);
4518 unsigned HOST_WIDE_INT len = 0;
4519 HOST_WIDE_INT pos = 0;
4521 rtx inner = NULL_RTX;
4523 /* First special-case some codes. */
4527 #ifdef INSN_SCHEDULING
4528 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4530 if (MEM_P (SUBREG_REG (x)))
4533 return find_split_point (&SUBREG_REG (x), insn, false);
4537 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4538 using LO_SUM and HIGH. */
4539 if (GET_CODE (XEXP (x, 0)) == CONST
4540 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4542 enum machine_mode address_mode
4543 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4546 gen_rtx_LO_SUM (address_mode,
4547 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4549 return &XEXP (XEXP (x, 0), 0);
4553 /* If we have a PLUS whose second operand is a constant and the
4554 address is not valid, perhaps will can split it up using
4555 the machine-specific way to split large constants. We use
4556 the first pseudo-reg (one of the virtual regs) as a placeholder;
4557 it will not remain in the result. */
4558 if (GET_CODE (XEXP (x, 0)) == PLUS
4559 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4560 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4561 MEM_ADDR_SPACE (x)))
4563 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4564 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4568 /* This should have produced two insns, each of which sets our
4569 placeholder. If the source of the second is a valid address,
4570 we can make put both sources together and make a split point
4574 && NEXT_INSN (seq) != NULL_RTX
4575 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4576 && NONJUMP_INSN_P (seq)
4577 && GET_CODE (PATTERN (seq)) == SET
4578 && SET_DEST (PATTERN (seq)) == reg
4579 && ! reg_mentioned_p (reg,
4580 SET_SRC (PATTERN (seq)))
4581 && NONJUMP_INSN_P (NEXT_INSN (seq))
4582 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4583 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4584 && memory_address_addr_space_p
4585 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4586 MEM_ADDR_SPACE (x)))
4588 rtx src1 = SET_SRC (PATTERN (seq));
4589 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4591 /* Replace the placeholder in SRC2 with SRC1. If we can
4592 find where in SRC2 it was placed, that can become our
4593 split point and we can replace this address with SRC2.
4594 Just try two obvious places. */
4596 src2 = replace_rtx (src2, reg, src1);
4598 if (XEXP (src2, 0) == src1)
4599 split = &XEXP (src2, 0);
4600 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4601 && XEXP (XEXP (src2, 0), 0) == src1)
4602 split = &XEXP (XEXP (src2, 0), 0);
4606 SUBST (XEXP (x, 0), src2);
4611 /* If that didn't work, perhaps the first operand is complex and
4612 needs to be computed separately, so make a split point there.
4613 This will occur on machines that just support REG + CONST
4614 and have a constant moved through some previous computation. */
4616 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4617 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4618 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4619 return &XEXP (XEXP (x, 0), 0);
4622 /* If we have a PLUS whose first operand is complex, try computing it
4623 separately by making a split there. */
4624 if (GET_CODE (XEXP (x, 0)) == PLUS
4625 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4627 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4628 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4629 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4630 return &XEXP (XEXP (x, 0), 0);
4635 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4636 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4637 we need to put the operand into a register. So split at that
4640 if (SET_DEST (x) == cc0_rtx
4641 && GET_CODE (SET_SRC (x)) != COMPARE
4642 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4643 && !OBJECT_P (SET_SRC (x))
4644 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4645 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4646 return &SET_SRC (x);
4649 /* See if we can split SET_SRC as it stands. */
4650 split = find_split_point (&SET_SRC (x), insn, true);
4651 if (split && split != &SET_SRC (x))
4654 /* See if we can split SET_DEST as it stands. */
4655 split = find_split_point (&SET_DEST (x), insn, false);
4656 if (split && split != &SET_DEST (x))
4659 /* See if this is a bitfield assignment with everything constant. If
4660 so, this is an IOR of an AND, so split it into that. */
4661 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4662 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4663 <= HOST_BITS_PER_WIDE_INT)
4664 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4665 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4666 && CONST_INT_P (SET_SRC (x))
4667 && ((INTVAL (XEXP (SET_DEST (x), 1))
4668 + INTVAL (XEXP (SET_DEST (x), 2)))
4669 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4670 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4672 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4673 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4674 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4675 rtx dest = XEXP (SET_DEST (x), 0);
4676 enum machine_mode mode = GET_MODE (dest);
4677 unsigned HOST_WIDE_INT mask
4678 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4681 if (BITS_BIG_ENDIAN)
4682 pos = GET_MODE_BITSIZE (mode) - len - pos;
4684 or_mask = gen_int_mode (src << pos, mode);
4687 simplify_gen_binary (IOR, mode, dest, or_mask));
4690 rtx negmask = gen_int_mode (~(mask << pos), mode);
4692 simplify_gen_binary (IOR, mode,
4693 simplify_gen_binary (AND, mode,
4698 SUBST (SET_DEST (x), dest);
4700 split = find_split_point (&SET_SRC (x), insn, true);
4701 if (split && split != &SET_SRC (x))
4705 /* Otherwise, see if this is an operation that we can split into two.
4706 If so, try to split that. */
4707 code = GET_CODE (SET_SRC (x));
4712 /* If we are AND'ing with a large constant that is only a single
4713 bit and the result is only being used in a context where we
4714 need to know if it is zero or nonzero, replace it with a bit
4715 extraction. This will avoid the large constant, which might
4716 have taken more than one insn to make. If the constant were
4717 not a valid argument to the AND but took only one insn to make,
4718 this is no worse, but if it took more than one insn, it will
4721 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4722 && REG_P (XEXP (SET_SRC (x), 0))
4723 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4724 && REG_P (SET_DEST (x))
4725 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4726 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4727 && XEXP (*split, 0) == SET_DEST (x)
4728 && XEXP (*split, 1) == const0_rtx)
4730 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4731 XEXP (SET_SRC (x), 0),
4732 pos, NULL_RTX, 1, 1, 0, 0);
4733 if (extraction != 0)
4735 SUBST (SET_SRC (x), extraction);
4736 return find_split_point (loc, insn, false);
4742 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4743 is known to be on, this can be converted into a NEG of a shift. */
4744 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4745 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4746 && 1 <= (pos = exact_log2
4747 (nonzero_bits (XEXP (SET_SRC (x), 0),
4748 GET_MODE (XEXP (SET_SRC (x), 0))))))
4750 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4754 gen_rtx_LSHIFTRT (mode,
4755 XEXP (SET_SRC (x), 0),
4758 split = find_split_point (&SET_SRC (x), insn, true);
4759 if (split && split != &SET_SRC (x))
4765 inner = XEXP (SET_SRC (x), 0);
4767 /* We can't optimize if either mode is a partial integer
4768 mode as we don't know how many bits are significant
4770 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4771 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4775 len = GET_MODE_BITSIZE (GET_MODE (inner));
4781 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4782 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4784 inner = XEXP (SET_SRC (x), 0);
4785 len = INTVAL (XEXP (SET_SRC (x), 1));
4786 pos = INTVAL (XEXP (SET_SRC (x), 2));
4788 if (BITS_BIG_ENDIAN)
4789 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4790 unsignedp = (code == ZERO_EXTRACT);
4798 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4800 enum machine_mode mode = GET_MODE (SET_SRC (x));
4802 /* For unsigned, we have a choice of a shift followed by an
4803 AND or two shifts. Use two shifts for field sizes where the
4804 constant might be too large. We assume here that we can
4805 always at least get 8-bit constants in an AND insn, which is
4806 true for every current RISC. */
4808 if (unsignedp && len <= 8)
4813 (mode, gen_lowpart (mode, inner),
4815 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4818 split = find_split_point (&SET_SRC (x), insn, true);
4819 if (split && split != &SET_SRC (x))
4826 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4827 gen_rtx_ASHIFT (mode,
4828 gen_lowpart (mode, inner),
4829 GEN_INT (GET_MODE_BITSIZE (mode)
4831 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4833 split = find_split_point (&SET_SRC (x), insn, true);
4834 if (split && split != &SET_SRC (x))
4839 /* See if this is a simple operation with a constant as the second
4840 operand. It might be that this constant is out of range and hence
4841 could be used as a split point. */
4842 if (BINARY_P (SET_SRC (x))
4843 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4844 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4845 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4846 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4847 return &XEXP (SET_SRC (x), 1);
4849 /* Finally, see if this is a simple operation with its first operand
4850 not in a register. The operation might require this operand in a
4851 register, so return it as a split point. We can always do this
4852 because if the first operand were another operation, we would have
4853 already found it as a split point. */
4854 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4855 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4856 return &XEXP (SET_SRC (x), 0);
4862 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4863 it is better to write this as (not (ior A B)) so we can split it.
4864 Similarly for IOR. */
4865 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4868 gen_rtx_NOT (GET_MODE (x),
4869 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4871 XEXP (XEXP (x, 0), 0),
4872 XEXP (XEXP (x, 1), 0))));
4873 return find_split_point (loc, insn, set_src);
4876 /* Many RISC machines have a large set of logical insns. If the
4877 second operand is a NOT, put it first so we will try to split the
4878 other operand first. */
4879 if (GET_CODE (XEXP (x, 1)) == NOT)
4881 rtx tem = XEXP (x, 0);
4882 SUBST (XEXP (x, 0), XEXP (x, 1));
4883 SUBST (XEXP (x, 1), tem);
4889 /* Canonicalization can produce (minus A (mult B C)), where C is a
4890 constant. It may be better to try splitting (plus (mult B -C) A)
4891 instead if this isn't a multiply by a power of two. */
4892 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4893 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4894 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4896 enum machine_mode mode = GET_MODE (x);
4897 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4898 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4899 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4900 XEXP (XEXP (x, 1), 0),
4901 GEN_INT (other_int)),
4903 return find_split_point (loc, insn, set_src);
4906 /* Split at a multiply-accumulate instruction. However if this is
4907 the SET_SRC, we likely do not have such an instruction and it's
4908 worthless to try this split. */
4909 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4916 /* Otherwise, select our actions depending on our rtx class. */
4917 switch (GET_RTX_CLASS (code))
4919 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4921 split = find_split_point (&XEXP (x, 2), insn, false);
4924 /* ... fall through ... */
4926 case RTX_COMM_ARITH:
4928 case RTX_COMM_COMPARE:
4929 split = find_split_point (&XEXP (x, 1), insn, false);
4932 /* ... fall through ... */
4934 /* Some machines have (and (shift ...) ...) insns. If X is not
4935 an AND, but XEXP (X, 0) is, use it as our split point. */
4936 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4937 return &XEXP (x, 0);
4939 split = find_split_point (&XEXP (x, 0), insn, false);
4945 /* Otherwise, we don't have a split point. */
4950 /* Throughout X, replace FROM with TO, and return the result.
4951 The result is TO if X is FROM;
4952 otherwise the result is X, but its contents may have been modified.
4953 If they were modified, a record was made in undobuf so that
4954 undo_all will (among other things) return X to its original state.
4956 If the number of changes necessary is too much to record to undo,
4957 the excess changes are not made, so the result is invalid.
4958 The changes already made can still be undone.
4959 undobuf.num_undo is incremented for such changes, so by testing that
4960 the caller can tell whether the result is valid.
4962 `n_occurrences' is incremented each time FROM is replaced.
4964 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4966 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4967 by copying if `n_occurrences' is nonzero. */
4970 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4972 enum rtx_code code = GET_CODE (x);
4973 enum machine_mode op0_mode = VOIDmode;
4978 /* Two expressions are equal if they are identical copies of a shared
4979 RTX or if they are both registers with the same register number
4982 #define COMBINE_RTX_EQUAL_P(X,Y) \
4984 || (REG_P (X) && REG_P (Y) \
4985 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4987 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4990 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4993 /* If X and FROM are the same register but different modes, they
4994 will not have been seen as equal above. However, the log links code
4995 will make a LOG_LINKS entry for that case. If we do nothing, we
4996 will try to rerecognize our original insn and, when it succeeds,
4997 we will delete the feeding insn, which is incorrect.
4999 So force this insn not to match in this (rare) case. */
5000 if (! in_dest && code == REG && REG_P (from)
5001 && reg_overlap_mentioned_p (x, from))
5002 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5004 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5005 of which may contain things that can be combined. */
5006 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5009 /* It is possible to have a subexpression appear twice in the insn.
5010 Suppose that FROM is a register that appears within TO.
5011 Then, after that subexpression has been scanned once by `subst',
5012 the second time it is scanned, TO may be found. If we were
5013 to scan TO here, we would find FROM within it and create a
5014 self-referent rtl structure which is completely wrong. */
5015 if (COMBINE_RTX_EQUAL_P (x, to))
5018 /* Parallel asm_operands need special attention because all of the
5019 inputs are shared across the arms. Furthermore, unsharing the
5020 rtl results in recognition failures. Failure to handle this case
5021 specially can result in circular rtl.
5023 Solve this by doing a normal pass across the first entry of the
5024 parallel, and only processing the SET_DESTs of the subsequent
5027 if (code == PARALLEL
5028 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5029 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5031 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
5033 /* If this substitution failed, this whole thing fails. */
5034 if (GET_CODE (new_rtx) == CLOBBER
5035 && XEXP (new_rtx, 0) == const0_rtx)
5038 SUBST (XVECEXP (x, 0, 0), new_rtx);
5040 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5042 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5045 && GET_CODE (dest) != CC0
5046 && GET_CODE (dest) != PC)
5048 new_rtx = subst (dest, from, to, 0, unique_copy);
5050 /* If this substitution failed, this whole thing fails. */
5051 if (GET_CODE (new_rtx) == CLOBBER
5052 && XEXP (new_rtx, 0) == const0_rtx)
5055 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5061 len = GET_RTX_LENGTH (code);
5062 fmt = GET_RTX_FORMAT (code);
5064 /* We don't need to process a SET_DEST that is a register, CC0,
5065 or PC, so set up to skip this common case. All other cases
5066 where we want to suppress replacing something inside a
5067 SET_SRC are handled via the IN_DEST operand. */
5069 && (REG_P (SET_DEST (x))
5070 || GET_CODE (SET_DEST (x)) == CC0
5071 || GET_CODE (SET_DEST (x)) == PC))
5074 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5077 op0_mode = GET_MODE (XEXP (x, 0));
5079 for (i = 0; i < len; i++)
5084 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5086 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5088 new_rtx = (unique_copy && n_occurrences
5089 ? copy_rtx (to) : to);
5094 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
5097 /* If this substitution failed, this whole thing
5099 if (GET_CODE (new_rtx) == CLOBBER
5100 && XEXP (new_rtx, 0) == const0_rtx)
5104 SUBST (XVECEXP (x, i, j), new_rtx);
5107 else if (fmt[i] == 'e')
5109 /* If this is a register being set, ignore it. */
5110 new_rtx = XEXP (x, i);
5113 && (((code == SUBREG || code == ZERO_EXTRACT)
5115 || code == STRICT_LOW_PART))
5118 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5120 /* In general, don't install a subreg involving two
5121 modes not tieable. It can worsen register
5122 allocation, and can even make invalid reload
5123 insns, since the reg inside may need to be copied
5124 from in the outside mode, and that may be invalid
5125 if it is an fp reg copied in integer mode.
5127 We allow two exceptions to this: It is valid if
5128 it is inside another SUBREG and the mode of that
5129 SUBREG and the mode of the inside of TO is
5130 tieable and it is valid if X is a SET that copies
5133 if (GET_CODE (to) == SUBREG
5134 && ! MODES_TIEABLE_P (GET_MODE (to),
5135 GET_MODE (SUBREG_REG (to)))
5136 && ! (code == SUBREG
5137 && MODES_TIEABLE_P (GET_MODE (x),
5138 GET_MODE (SUBREG_REG (to))))
5140 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5143 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5145 #ifdef CANNOT_CHANGE_MODE_CLASS
5148 && REGNO (to) < FIRST_PSEUDO_REGISTER
5149 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5152 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5155 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5159 /* If we are in a SET_DEST, suppress most cases unless we
5160 have gone inside a MEM, in which case we want to
5161 simplify the address. We assume here that things that
5162 are actually part of the destination have their inner
5163 parts in the first expression. This is true for SUBREG,
5164 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5165 things aside from REG and MEM that should appear in a
5167 new_rtx = subst (XEXP (x, i), from, to,
5169 && (code == SUBREG || code == STRICT_LOW_PART
5170 || code == ZERO_EXTRACT))
5172 && i == 0), unique_copy);
5174 /* If we found that we will have to reject this combination,
5175 indicate that by returning the CLOBBER ourselves, rather than
5176 an expression containing it. This will speed things up as
5177 well as prevent accidents where two CLOBBERs are considered
5178 to be equal, thus producing an incorrect simplification. */
5180 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5183 if (GET_CODE (x) == SUBREG
5184 && (CONST_INT_P (new_rtx)
5185 || GET_CODE (new_rtx) == CONST_DOUBLE))
5187 enum machine_mode mode = GET_MODE (x);
5189 x = simplify_subreg (GET_MODE (x), new_rtx,
5190 GET_MODE (SUBREG_REG (x)),
5193 x = gen_rtx_CLOBBER (mode, const0_rtx);
5195 else if (CONST_INT_P (new_rtx)
5196 && GET_CODE (x) == ZERO_EXTEND)
5198 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5199 new_rtx, GET_MODE (XEXP (x, 0)));
5203 SUBST (XEXP (x, i), new_rtx);
5208 /* Check if we are loading something from the constant pool via float
5209 extension; in this case we would undo compress_float_constant
5210 optimization and degenerate constant load to an immediate value. */
5211 if (GET_CODE (x) == FLOAT_EXTEND
5212 && MEM_P (XEXP (x, 0))
5213 && MEM_READONLY_P (XEXP (x, 0)))
5215 rtx tmp = avoid_constant_pool_reference (x);
5220 /* Try to simplify X. If the simplification changed the code, it is likely
5221 that further simplification will help, so loop, but limit the number
5222 of repetitions that will be performed. */
5224 for (i = 0; i < 4; i++)
5226 /* If X is sufficiently simple, don't bother trying to do anything
5228 if (code != CONST_INT && code != REG && code != CLOBBER)
5229 x = combine_simplify_rtx (x, op0_mode, in_dest);
5231 if (GET_CODE (x) == code)
5234 code = GET_CODE (x);
5236 /* We no longer know the original mode of operand 0 since we
5237 have changed the form of X) */
5238 op0_mode = VOIDmode;
5244 /* Simplify X, a piece of RTL. We just operate on the expression at the
5245 outer level; call `subst' to simplify recursively. Return the new
5248 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5249 if we are inside a SET_DEST. */
5252 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
5254 enum rtx_code code = GET_CODE (x);
5255 enum machine_mode mode = GET_MODE (x);
5259 /* If this is a commutative operation, put a constant last and a complex
5260 expression first. We don't need to do this for comparisons here. */
5261 if (COMMUTATIVE_ARITH_P (x)
5262 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5265 SUBST (XEXP (x, 0), XEXP (x, 1));
5266 SUBST (XEXP (x, 1), temp);
5269 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5270 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5271 things. Check for cases where both arms are testing the same
5274 Don't do anything if all operands are very simple. */
5277 && ((!OBJECT_P (XEXP (x, 0))
5278 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5279 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5280 || (!OBJECT_P (XEXP (x, 1))
5281 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5282 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5284 && (!OBJECT_P (XEXP (x, 0))
5285 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5286 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5288 rtx cond, true_rtx, false_rtx;
5290 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5292 /* If everything is a comparison, what we have is highly unlikely
5293 to be simpler, so don't use it. */
5294 && ! (COMPARISON_P (x)
5295 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5297 rtx cop1 = const0_rtx;
5298 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5300 if (cond_code == NE && COMPARISON_P (cond))
5303 /* Simplify the alternative arms; this may collapse the true and
5304 false arms to store-flag values. Be careful to use copy_rtx
5305 here since true_rtx or false_rtx might share RTL with x as a
5306 result of the if_then_else_cond call above. */
5307 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
5308 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
5310 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5311 is unlikely to be simpler. */
5312 if (general_operand (true_rtx, VOIDmode)
5313 && general_operand (false_rtx, VOIDmode))
5315 enum rtx_code reversed;
5317 /* Restarting if we generate a store-flag expression will cause
5318 us to loop. Just drop through in this case. */
5320 /* If the result values are STORE_FLAG_VALUE and zero, we can
5321 just make the comparison operation. */
5322 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5323 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5325 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5326 && ((reversed = reversed_comparison_code_parts
5327 (cond_code, cond, cop1, NULL))
5329 x = simplify_gen_relational (reversed, mode, VOIDmode,
5332 /* Likewise, we can make the negate of a comparison operation
5333 if the result values are - STORE_FLAG_VALUE and zero. */
5334 else if (CONST_INT_P (true_rtx)
5335 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5336 && false_rtx == const0_rtx)
5337 x = simplify_gen_unary (NEG, mode,
5338 simplify_gen_relational (cond_code,
5342 else if (CONST_INT_P (false_rtx)
5343 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5344 && true_rtx == const0_rtx
5345 && ((reversed = reversed_comparison_code_parts
5346 (cond_code, cond, cop1, NULL))
5348 x = simplify_gen_unary (NEG, mode,
5349 simplify_gen_relational (reversed,
5354 return gen_rtx_IF_THEN_ELSE (mode,
5355 simplify_gen_relational (cond_code,
5360 true_rtx, false_rtx);
5362 code = GET_CODE (x);
5363 op0_mode = VOIDmode;
5368 /* Try to fold this expression in case we have constants that weren't
5371 switch (GET_RTX_CLASS (code))
5374 if (op0_mode == VOIDmode)
5375 op0_mode = GET_MODE (XEXP (x, 0));
5376 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5379 case RTX_COMM_COMPARE:
5381 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5382 if (cmp_mode == VOIDmode)
5384 cmp_mode = GET_MODE (XEXP (x, 1));
5385 if (cmp_mode == VOIDmode)
5386 cmp_mode = op0_mode;
5388 temp = simplify_relational_operation (code, mode, cmp_mode,
5389 XEXP (x, 0), XEXP (x, 1));
5392 case RTX_COMM_ARITH:
5394 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5396 case RTX_BITFIELD_OPS:
5398 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5399 XEXP (x, 1), XEXP (x, 2));
5408 code = GET_CODE (temp);
5409 op0_mode = VOIDmode;
5410 mode = GET_MODE (temp);
5413 /* First see if we can apply the inverse distributive law. */
5414 if (code == PLUS || code == MINUS
5415 || code == AND || code == IOR || code == XOR)
5417 x = apply_distributive_law (x);
5418 code = GET_CODE (x);
5419 op0_mode = VOIDmode;
5422 /* If CODE is an associative operation not otherwise handled, see if we
5423 can associate some operands. This can win if they are constants or
5424 if they are logically related (i.e. (a & b) & a). */
5425 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5426 || code == AND || code == IOR || code == XOR
5427 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5428 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5429 || (flag_associative_math && FLOAT_MODE_P (mode))))
5431 if (GET_CODE (XEXP (x, 0)) == code)
5433 rtx other = XEXP (XEXP (x, 0), 0);
5434 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5435 rtx inner_op1 = XEXP (x, 1);
5438 /* Make sure we pass the constant operand if any as the second
5439 one if this is a commutative operation. */
5440 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5442 rtx tem = inner_op0;
5443 inner_op0 = inner_op1;
5446 inner = simplify_binary_operation (code == MINUS ? PLUS
5447 : code == DIV ? MULT
5449 mode, inner_op0, inner_op1);
5451 /* For commutative operations, try the other pair if that one
5453 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5455 other = XEXP (XEXP (x, 0), 1);
5456 inner = simplify_binary_operation (code, mode,
5457 XEXP (XEXP (x, 0), 0),
5462 return simplify_gen_binary (code, mode, other, inner);
5466 /* A little bit of algebraic simplification here. */
5470 /* Ensure that our address has any ASHIFTs converted to MULT in case
5471 address-recognizing predicates are called later. */
5472 temp = make_compound_operation (XEXP (x, 0), MEM);
5473 SUBST (XEXP (x, 0), temp);
5477 if (op0_mode == VOIDmode)
5478 op0_mode = GET_MODE (SUBREG_REG (x));
5480 /* See if this can be moved to simplify_subreg. */
5481 if (CONSTANT_P (SUBREG_REG (x))
5482 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5483 /* Don't call gen_lowpart if the inner mode
5484 is VOIDmode and we cannot simplify it, as SUBREG without
5485 inner mode is invalid. */
5486 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5487 || gen_lowpart_common (mode, SUBREG_REG (x))))
5488 return gen_lowpart (mode, SUBREG_REG (x));
5490 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5494 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5500 /* Don't change the mode of the MEM if that would change the meaning
5502 if (MEM_P (SUBREG_REG (x))
5503 && (MEM_VOLATILE_P (SUBREG_REG (x))
5504 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5505 return gen_rtx_CLOBBER (mode, const0_rtx);
5507 /* Note that we cannot do any narrowing for non-constants since
5508 we might have been counting on using the fact that some bits were
5509 zero. We now do this in the SET. */
5514 temp = expand_compound_operation (XEXP (x, 0));
5516 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5517 replaced by (lshiftrt X C). This will convert
5518 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5520 if (GET_CODE (temp) == ASHIFTRT
5521 && CONST_INT_P (XEXP (temp, 1))
5522 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
5523 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5524 INTVAL (XEXP (temp, 1)));
5526 /* If X has only a single bit that might be nonzero, say, bit I, convert
5527 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5528 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5529 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5530 or a SUBREG of one since we'd be making the expression more
5531 complex if it was just a register. */
5534 && ! (GET_CODE (temp) == SUBREG
5535 && REG_P (SUBREG_REG (temp)))
5536 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5538 rtx temp1 = simplify_shift_const
5539 (NULL_RTX, ASHIFTRT, mode,
5540 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5541 GET_MODE_BITSIZE (mode) - 1 - i),
5542 GET_MODE_BITSIZE (mode) - 1 - i);
5544 /* If all we did was surround TEMP with the two shifts, we
5545 haven't improved anything, so don't use it. Otherwise,
5546 we are better off with TEMP1. */
5547 if (GET_CODE (temp1) != ASHIFTRT
5548 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5549 || XEXP (XEXP (temp1, 0), 0) != temp)
5555 /* We can't handle truncation to a partial integer mode here
5556 because we don't know the real bitsize of the partial
5558 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5561 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5563 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5564 GET_MODE_MASK (mode), 0));
5566 /* We can truncate a constant value and return it. */
5567 if (CONST_INT_P (XEXP (x, 0)))
5568 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5570 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5571 whose value is a comparison can be replaced with a subreg if
5572 STORE_FLAG_VALUE permits. */
5573 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5574 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5575 && (temp = get_last_value (XEXP (x, 0)))
5576 && COMPARISON_P (temp))
5577 return gen_lowpart (mode, XEXP (x, 0));
5581 /* (const (const X)) can become (const X). Do it this way rather than
5582 returning the inner CONST since CONST can be shared with a
5584 if (GET_CODE (XEXP (x, 0)) == CONST)
5585 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5590 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5591 can add in an offset. find_split_point will split this address up
5592 again if it doesn't match. */
5593 if (GET_CODE (XEXP (x, 0)) == HIGH
5594 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5600 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5601 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5602 bit-field and can be replaced by either a sign_extend or a
5603 sign_extract. The `and' may be a zero_extend and the two
5604 <c>, -<c> constants may be reversed. */
5605 if (GET_CODE (XEXP (x, 0)) == XOR
5606 && CONST_INT_P (XEXP (x, 1))
5607 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5608 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5609 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5610 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5611 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5612 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5613 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5614 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5615 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5616 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5617 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5618 == (unsigned int) i + 1))))
5619 return simplify_shift_const
5620 (NULL_RTX, ASHIFTRT, mode,
5621 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5622 XEXP (XEXP (XEXP (x, 0), 0), 0),
5623 GET_MODE_BITSIZE (mode) - (i + 1)),
5624 GET_MODE_BITSIZE (mode) - (i + 1));
5626 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5627 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5628 the bitsize of the mode - 1. This allows simplification of
5629 "a = (b & 8) == 0;" */
5630 if (XEXP (x, 1) == constm1_rtx
5631 && !REG_P (XEXP (x, 0))
5632 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5633 && REG_P (SUBREG_REG (XEXP (x, 0))))
5634 && nonzero_bits (XEXP (x, 0), mode) == 1)
5635 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5636 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5637 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5638 GET_MODE_BITSIZE (mode) - 1),
5639 GET_MODE_BITSIZE (mode) - 1);
5641 /* If we are adding two things that have no bits in common, convert
5642 the addition into an IOR. This will often be further simplified,
5643 for example in cases like ((a & 1) + (a & 2)), which can
5646 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5647 && (nonzero_bits (XEXP (x, 0), mode)
5648 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5650 /* Try to simplify the expression further. */
5651 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5652 temp = combine_simplify_rtx (tor, VOIDmode, in_dest);
5654 /* If we could, great. If not, do not go ahead with the IOR
5655 replacement, since PLUS appears in many special purpose
5656 address arithmetic instructions. */
5657 if (GET_CODE (temp) != CLOBBER && temp != tor)
5663 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5664 (and <foo> (const_int pow2-1)) */
5665 if (GET_CODE (XEXP (x, 1)) == AND
5666 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5667 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5668 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5669 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5670 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5674 /* If we have (mult (plus A B) C), apply the distributive law and then
5675 the inverse distributive law to see if things simplify. This
5676 occurs mostly in addresses, often when unrolling loops. */
5678 if (GET_CODE (XEXP (x, 0)) == PLUS)
5680 rtx result = distribute_and_simplify_rtx (x, 0);
5685 /* Try simplify a*(b/c) as (a*b)/c. */
5686 if (FLOAT_MODE_P (mode) && flag_associative_math
5687 && GET_CODE (XEXP (x, 0)) == DIV)
5689 rtx tem = simplify_binary_operation (MULT, mode,
5690 XEXP (XEXP (x, 0), 0),
5693 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5698 /* If this is a divide by a power of two, treat it as a shift if
5699 its first operand is a shift. */
5700 if (CONST_INT_P (XEXP (x, 1))
5701 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5702 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5703 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5704 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5705 || GET_CODE (XEXP (x, 0)) == ROTATE
5706 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5707 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5711 case GT: case GTU: case GE: case GEU:
5712 case LT: case LTU: case LE: case LEU:
5713 case UNEQ: case LTGT:
5714 case UNGT: case UNGE:
5715 case UNLT: case UNLE:
5716 case UNORDERED: case ORDERED:
5717 /* If the first operand is a condition code, we can't do anything
5719 if (GET_CODE (XEXP (x, 0)) == COMPARE
5720 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5721 && ! CC0_P (XEXP (x, 0))))
5723 rtx op0 = XEXP (x, 0);
5724 rtx op1 = XEXP (x, 1);
5725 enum rtx_code new_code;
5727 if (GET_CODE (op0) == COMPARE)
5728 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5730 /* Simplify our comparison, if possible. */
5731 new_code = simplify_comparison (code, &op0, &op1);
5733 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5734 if only the low-order bit is possibly nonzero in X (such as when
5735 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5736 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5737 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5740 Remove any ZERO_EXTRACT we made when thinking this was a
5741 comparison. It may now be simpler to use, e.g., an AND. If a
5742 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5743 the call to make_compound_operation in the SET case. */
5745 if (STORE_FLAG_VALUE == 1
5746 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5747 && op1 == const0_rtx
5748 && mode == GET_MODE (op0)
5749 && nonzero_bits (op0, mode) == 1)
5750 return gen_lowpart (mode,
5751 expand_compound_operation (op0));
5753 else if (STORE_FLAG_VALUE == 1
5754 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5755 && op1 == const0_rtx
5756 && mode == GET_MODE (op0)
5757 && (num_sign_bit_copies (op0, mode)
5758 == GET_MODE_BITSIZE (mode)))
5760 op0 = expand_compound_operation (op0);
5761 return simplify_gen_unary (NEG, mode,
5762 gen_lowpart (mode, op0),
5766 else if (STORE_FLAG_VALUE == 1
5767 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5768 && op1 == const0_rtx
5769 && mode == GET_MODE (op0)
5770 && nonzero_bits (op0, mode) == 1)
5772 op0 = expand_compound_operation (op0);
5773 return simplify_gen_binary (XOR, mode,
5774 gen_lowpart (mode, op0),
5778 else if (STORE_FLAG_VALUE == 1
5779 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5780 && op1 == const0_rtx
5781 && mode == GET_MODE (op0)
5782 && (num_sign_bit_copies (op0, mode)
5783 == GET_MODE_BITSIZE (mode)))
5785 op0 = expand_compound_operation (op0);
5786 return plus_constant (gen_lowpart (mode, op0), 1);
5789 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5791 if (STORE_FLAG_VALUE == -1
5792 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5793 && op1 == const0_rtx
5794 && (num_sign_bit_copies (op0, mode)
5795 == GET_MODE_BITSIZE (mode)))
5796 return gen_lowpart (mode,
5797 expand_compound_operation (op0));
5799 else if (STORE_FLAG_VALUE == -1
5800 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5801 && op1 == const0_rtx
5802 && mode == GET_MODE (op0)
5803 && nonzero_bits (op0, mode) == 1)
5805 op0 = expand_compound_operation (op0);
5806 return simplify_gen_unary (NEG, mode,
5807 gen_lowpart (mode, op0),
5811 else if (STORE_FLAG_VALUE == -1
5812 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5813 && op1 == const0_rtx
5814 && mode == GET_MODE (op0)
5815 && (num_sign_bit_copies (op0, mode)
5816 == GET_MODE_BITSIZE (mode)))
5818 op0 = expand_compound_operation (op0);
5819 return simplify_gen_unary (NOT, mode,
5820 gen_lowpart (mode, op0),
5824 /* If X is 0/1, (eq X 0) is X-1. */
5825 else if (STORE_FLAG_VALUE == -1
5826 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5827 && op1 == const0_rtx
5828 && mode == GET_MODE (op0)
5829 && nonzero_bits (op0, mode) == 1)
5831 op0 = expand_compound_operation (op0);
5832 return plus_constant (gen_lowpart (mode, op0), -1);
5835 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5836 one bit that might be nonzero, we can convert (ne x 0) to
5837 (ashift x c) where C puts the bit in the sign bit. Remove any
5838 AND with STORE_FLAG_VALUE when we are done, since we are only
5839 going to test the sign bit. */
5840 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5841 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5842 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5843 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5844 && op1 == const0_rtx
5845 && mode == GET_MODE (op0)
5846 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5848 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5849 expand_compound_operation (op0),
5850 GET_MODE_BITSIZE (mode) - 1 - i);
5851 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5857 /* If the code changed, return a whole new comparison. */
5858 if (new_code != code)
5859 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5861 /* Otherwise, keep this operation, but maybe change its operands.
5862 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5863 SUBST (XEXP (x, 0), op0);
5864 SUBST (XEXP (x, 1), op1);
5869 return simplify_if_then_else (x);
5875 /* If we are processing SET_DEST, we are done. */
5879 return expand_compound_operation (x);
5882 return simplify_set (x);
5886 return simplify_logical (x);
5893 /* If this is a shift by a constant amount, simplify it. */
5894 if (CONST_INT_P (XEXP (x, 1)))
5895 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5896 INTVAL (XEXP (x, 1)));
5898 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5900 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5901 ((unsigned HOST_WIDE_INT) 1
5902 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5914 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5917 simplify_if_then_else (rtx x)
5919 enum machine_mode mode = GET_MODE (x);
5920 rtx cond = XEXP (x, 0);
5921 rtx true_rtx = XEXP (x, 1);
5922 rtx false_rtx = XEXP (x, 2);
5923 enum rtx_code true_code = GET_CODE (cond);
5924 int comparison_p = COMPARISON_P (cond);
5927 enum rtx_code false_code;
5930 /* Simplify storing of the truth value. */
5931 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5932 return simplify_gen_relational (true_code, mode, VOIDmode,
5933 XEXP (cond, 0), XEXP (cond, 1));
5935 /* Also when the truth value has to be reversed. */
5937 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5938 && (reversed = reversed_comparison (cond, mode)))
5941 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5942 in it is being compared against certain values. Get the true and false
5943 comparisons and see if that says anything about the value of each arm. */
5946 && ((false_code = reversed_comparison_code (cond, NULL))
5948 && REG_P (XEXP (cond, 0)))
5951 rtx from = XEXP (cond, 0);
5952 rtx true_val = XEXP (cond, 1);
5953 rtx false_val = true_val;
5956 /* If FALSE_CODE is EQ, swap the codes and arms. */
5958 if (false_code == EQ)
5960 swapped = 1, true_code = EQ, false_code = NE;
5961 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5964 /* If we are comparing against zero and the expression being tested has
5965 only a single bit that might be nonzero, that is its value when it is
5966 not equal to zero. Similarly if it is known to be -1 or 0. */
5968 if (true_code == EQ && true_val == const0_rtx
5969 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5972 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5974 else if (true_code == EQ && true_val == const0_rtx
5975 && (num_sign_bit_copies (from, GET_MODE (from))
5976 == GET_MODE_BITSIZE (GET_MODE (from))))
5979 false_val = constm1_rtx;
5982 /* Now simplify an arm if we know the value of the register in the
5983 branch and it is used in the arm. Be careful due to the potential
5984 of locally-shared RTL. */
5986 if (reg_mentioned_p (from, true_rtx))
5987 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5989 pc_rtx, pc_rtx, 0, 0);
5990 if (reg_mentioned_p (from, false_rtx))
5991 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5993 pc_rtx, pc_rtx, 0, 0);
5995 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5996 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5998 true_rtx = XEXP (x, 1);
5999 false_rtx = XEXP (x, 2);
6000 true_code = GET_CODE (cond);
6003 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6004 reversed, do so to avoid needing two sets of patterns for
6005 subtract-and-branch insns. Similarly if we have a constant in the true
6006 arm, the false arm is the same as the first operand of the comparison, or
6007 the false arm is more complicated than the true arm. */
6010 && reversed_comparison_code (cond, NULL) != UNKNOWN
6011 && (true_rtx == pc_rtx
6012 || (CONSTANT_P (true_rtx)
6013 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6014 || true_rtx == const0_rtx
6015 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6016 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6017 && !OBJECT_P (false_rtx))
6018 || reg_mentioned_p (true_rtx, false_rtx)
6019 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6021 true_code = reversed_comparison_code (cond, NULL);
6022 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6023 SUBST (XEXP (x, 1), false_rtx);
6024 SUBST (XEXP (x, 2), true_rtx);
6026 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6029 /* It is possible that the conditional has been simplified out. */
6030 true_code = GET_CODE (cond);
6031 comparison_p = COMPARISON_P (cond);
6034 /* If the two arms are identical, we don't need the comparison. */
6036 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6039 /* Convert a == b ? b : a to "a". */
6040 if (true_code == EQ && ! side_effects_p (cond)
6041 && !HONOR_NANS (mode)
6042 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6043 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6045 else if (true_code == NE && ! side_effects_p (cond)
6046 && !HONOR_NANS (mode)
6047 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6048 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6051 /* Look for cases where we have (abs x) or (neg (abs X)). */
6053 if (GET_MODE_CLASS (mode) == MODE_INT
6055 && XEXP (cond, 1) == const0_rtx
6056 && GET_CODE (false_rtx) == NEG
6057 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6058 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6059 && ! side_effects_p (true_rtx))
6064 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6068 simplify_gen_unary (NEG, mode,
6069 simplify_gen_unary (ABS, mode, true_rtx, mode),
6075 /* Look for MIN or MAX. */
6077 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6079 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6080 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6081 && ! side_effects_p (cond))
6086 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6089 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6092 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6095 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6100 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6101 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6102 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6103 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6104 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6105 neither 1 or -1, but it isn't worth checking for. */
6107 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6109 && GET_MODE_CLASS (mode) == MODE_INT
6110 && ! side_effects_p (x))
6112 rtx t = make_compound_operation (true_rtx, SET);
6113 rtx f = make_compound_operation (false_rtx, SET);
6114 rtx cond_op0 = XEXP (cond, 0);
6115 rtx cond_op1 = XEXP (cond, 1);
6116 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6117 enum machine_mode m = mode;
6118 rtx z = 0, c1 = NULL_RTX;
6120 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6121 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6122 || GET_CODE (t) == ASHIFT
6123 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6124 && rtx_equal_p (XEXP (t, 0), f))
6125 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6127 /* If an identity-zero op is commutative, check whether there
6128 would be a match if we swapped the operands. */
6129 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6130 || GET_CODE (t) == XOR)
6131 && rtx_equal_p (XEXP (t, 1), f))
6132 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6133 else if (GET_CODE (t) == SIGN_EXTEND
6134 && (GET_CODE (XEXP (t, 0)) == PLUS
6135 || GET_CODE (XEXP (t, 0)) == MINUS
6136 || GET_CODE (XEXP (t, 0)) == IOR
6137 || GET_CODE (XEXP (t, 0)) == XOR
6138 || GET_CODE (XEXP (t, 0)) == ASHIFT
6139 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6140 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6141 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6142 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6143 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6144 && (num_sign_bit_copies (f, GET_MODE (f))
6146 (GET_MODE_BITSIZE (mode)
6147 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6149 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6150 extend_op = SIGN_EXTEND;
6151 m = GET_MODE (XEXP (t, 0));
6153 else if (GET_CODE (t) == SIGN_EXTEND
6154 && (GET_CODE (XEXP (t, 0)) == PLUS
6155 || GET_CODE (XEXP (t, 0)) == IOR
6156 || GET_CODE (XEXP (t, 0)) == XOR)
6157 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6158 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6159 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6160 && (num_sign_bit_copies (f, GET_MODE (f))
6162 (GET_MODE_BITSIZE (mode)
6163 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6165 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6166 extend_op = SIGN_EXTEND;
6167 m = GET_MODE (XEXP (t, 0));
6169 else if (GET_CODE (t) == ZERO_EXTEND
6170 && (GET_CODE (XEXP (t, 0)) == PLUS
6171 || GET_CODE (XEXP (t, 0)) == MINUS
6172 || GET_CODE (XEXP (t, 0)) == IOR
6173 || GET_CODE (XEXP (t, 0)) == XOR
6174 || GET_CODE (XEXP (t, 0)) == ASHIFT
6175 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6176 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6177 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6179 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6180 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6181 && ((nonzero_bits (f, GET_MODE (f))
6182 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6185 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6186 extend_op = ZERO_EXTEND;
6187 m = GET_MODE (XEXP (t, 0));
6189 else if (GET_CODE (t) == ZERO_EXTEND
6190 && (GET_CODE (XEXP (t, 0)) == PLUS
6191 || GET_CODE (XEXP (t, 0)) == IOR
6192 || GET_CODE (XEXP (t, 0)) == XOR)
6193 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6194 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6195 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6196 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6197 && ((nonzero_bits (f, GET_MODE (f))
6198 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6201 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6202 extend_op = ZERO_EXTEND;
6203 m = GET_MODE (XEXP (t, 0));
6208 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6209 cond_op0, cond_op1),
6210 pc_rtx, pc_rtx, 0, 0);
6211 temp = simplify_gen_binary (MULT, m, temp,
6212 simplify_gen_binary (MULT, m, c1,
6214 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
6215 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6217 if (extend_op != UNKNOWN)
6218 temp = simplify_gen_unary (extend_op, mode, temp, m);
6224 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6225 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6226 negation of a single bit, we can convert this operation to a shift. We
6227 can actually do this more generally, but it doesn't seem worth it. */
6229 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6230 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6231 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6232 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6233 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6234 == GET_MODE_BITSIZE (mode))
6235 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6237 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6238 gen_lowpart (mode, XEXP (cond, 0)), i);
6240 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6241 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6242 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6243 && GET_MODE (XEXP (cond, 0)) == mode
6244 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6245 == nonzero_bits (XEXP (cond, 0), mode)
6246 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6247 return XEXP (cond, 0);
6252 /* Simplify X, a SET expression. Return the new expression. */
6255 simplify_set (rtx x)
6257 rtx src = SET_SRC (x);
6258 rtx dest = SET_DEST (x);
6259 enum machine_mode mode
6260 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6264 /* (set (pc) (return)) gets written as (return). */
6265 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
6268 /* Now that we know for sure which bits of SRC we are using, see if we can
6269 simplify the expression for the object knowing that we only need the
6272 if (GET_MODE_CLASS (mode) == MODE_INT
6273 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
6275 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6276 SUBST (SET_SRC (x), src);
6279 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6280 the comparison result and try to simplify it unless we already have used
6281 undobuf.other_insn. */
6282 if ((GET_MODE_CLASS (mode) == MODE_CC
6283 || GET_CODE (src) == COMPARE
6285 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6286 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6287 && COMPARISON_P (*cc_use)
6288 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6290 enum rtx_code old_code = GET_CODE (*cc_use);
6291 enum rtx_code new_code;
6293 int other_changed = 0;
6294 enum machine_mode compare_mode = GET_MODE (dest);
6296 if (GET_CODE (src) == COMPARE)
6297 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6299 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6301 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6304 new_code = old_code;
6305 else if (!CONSTANT_P (tmp))
6307 new_code = GET_CODE (tmp);
6308 op0 = XEXP (tmp, 0);
6309 op1 = XEXP (tmp, 1);
6313 rtx pat = PATTERN (other_insn);
6314 undobuf.other_insn = other_insn;
6315 SUBST (*cc_use, tmp);
6317 /* Attempt to simplify CC user. */
6318 if (GET_CODE (pat) == SET)
6320 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6321 if (new_rtx != NULL_RTX)
6322 SUBST (SET_SRC (pat), new_rtx);
6325 /* Convert X into a no-op move. */
6326 SUBST (SET_DEST (x), pc_rtx);
6327 SUBST (SET_SRC (x), pc_rtx);
6331 /* Simplify our comparison, if possible. */
6332 new_code = simplify_comparison (new_code, &op0, &op1);
6334 #ifdef SELECT_CC_MODE
6335 /* If this machine has CC modes other than CCmode, check to see if we
6336 need to use a different CC mode here. */
6337 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6338 compare_mode = GET_MODE (op0);
6340 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6343 /* If the mode changed, we have to change SET_DEST, the mode in the
6344 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6345 a hard register, just build new versions with the proper mode. If it
6346 is a pseudo, we lose unless it is only time we set the pseudo, in
6347 which case we can safely change its mode. */
6348 if (compare_mode != GET_MODE (dest))
6350 if (can_change_dest_mode (dest, 0, compare_mode))
6352 unsigned int regno = REGNO (dest);
6355 if (regno < FIRST_PSEUDO_REGISTER)
6356 new_dest = gen_rtx_REG (compare_mode, regno);
6359 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6360 new_dest = regno_reg_rtx[regno];
6363 SUBST (SET_DEST (x), new_dest);
6364 SUBST (XEXP (*cc_use, 0), new_dest);
6371 #endif /* SELECT_CC_MODE */
6373 /* If the code changed, we have to build a new comparison in
6374 undobuf.other_insn. */
6375 if (new_code != old_code)
6377 int other_changed_previously = other_changed;
6378 unsigned HOST_WIDE_INT mask;
6379 rtx old_cc_use = *cc_use;
6381 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6385 /* If the only change we made was to change an EQ into an NE or
6386 vice versa, OP0 has only one bit that might be nonzero, and OP1
6387 is zero, check if changing the user of the condition code will
6388 produce a valid insn. If it won't, we can keep the original code
6389 in that insn by surrounding our operation with an XOR. */
6391 if (((old_code == NE && new_code == EQ)
6392 || (old_code == EQ && new_code == NE))
6393 && ! other_changed_previously && op1 == const0_rtx
6394 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
6395 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6397 rtx pat = PATTERN (other_insn), note = 0;
6399 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6400 && ! check_asm_operands (pat)))
6402 *cc_use = old_cc_use;
6405 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6406 op0, GEN_INT (mask));
6412 undobuf.other_insn = other_insn;
6414 /* Otherwise, if we didn't previously have a COMPARE in the
6415 correct mode, we need one. */
6416 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6418 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6421 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6423 SUBST (SET_SRC (x), op0);
6426 /* Otherwise, update the COMPARE if needed. */
6427 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6429 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6435 /* Get SET_SRC in a form where we have placed back any
6436 compound expressions. Then do the checks below. */
6437 src = make_compound_operation (src, SET);
6438 SUBST (SET_SRC (x), src);
6441 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6442 and X being a REG or (subreg (reg)), we may be able to convert this to
6443 (set (subreg:m2 x) (op)).
6445 We can always do this if M1 is narrower than M2 because that means that
6446 we only care about the low bits of the result.
6448 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6449 perform a narrower operation than requested since the high-order bits will
6450 be undefined. On machine where it is defined, this transformation is safe
6451 as long as M1 and M2 have the same number of words. */
6453 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6454 && !OBJECT_P (SUBREG_REG (src))
6455 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6457 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6458 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6459 #ifndef WORD_REGISTER_OPERATIONS
6460 && (GET_MODE_SIZE (GET_MODE (src))
6461 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6463 #ifdef CANNOT_CHANGE_MODE_CLASS
6464 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6465 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6466 GET_MODE (SUBREG_REG (src)),
6470 || (GET_CODE (dest) == SUBREG
6471 && REG_P (SUBREG_REG (dest)))))
6473 SUBST (SET_DEST (x),
6474 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6476 SUBST (SET_SRC (x), SUBREG_REG (src));
6478 src = SET_SRC (x), dest = SET_DEST (x);
6482 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6485 && GET_CODE (src) == SUBREG
6486 && subreg_lowpart_p (src)
6487 && (GET_MODE_BITSIZE (GET_MODE (src))
6488 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
6490 rtx inner = SUBREG_REG (src);
6491 enum machine_mode inner_mode = GET_MODE (inner);
6493 /* Here we make sure that we don't have a sign bit on. */
6494 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
6495 && (nonzero_bits (inner, inner_mode)
6496 < ((unsigned HOST_WIDE_INT) 1
6497 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
6499 SUBST (SET_SRC (x), inner);
6505 #ifdef LOAD_EXTEND_OP
6506 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6507 would require a paradoxical subreg. Replace the subreg with a
6508 zero_extend to avoid the reload that would otherwise be required. */
6510 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6511 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6512 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6513 && SUBREG_BYTE (src) == 0
6514 && (GET_MODE_SIZE (GET_MODE (src))
6515 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6516 && MEM_P (SUBREG_REG (src)))
6519 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6520 GET_MODE (src), SUBREG_REG (src)));
6526 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6527 are comparing an item known to be 0 or -1 against 0, use a logical
6528 operation instead. Check for one of the arms being an IOR of the other
6529 arm with some value. We compute three terms to be IOR'ed together. In
6530 practice, at most two will be nonzero. Then we do the IOR's. */
6532 if (GET_CODE (dest) != PC
6533 && GET_CODE (src) == IF_THEN_ELSE
6534 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6535 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6536 && XEXP (XEXP (src, 0), 1) == const0_rtx
6537 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6538 #ifdef HAVE_conditional_move
6539 && ! can_conditionally_move_p (GET_MODE (src))
6541 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6542 GET_MODE (XEXP (XEXP (src, 0), 0)))
6543 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
6544 && ! side_effects_p (src))
6546 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6547 ? XEXP (src, 1) : XEXP (src, 2));
6548 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6549 ? XEXP (src, 2) : XEXP (src, 1));
6550 rtx term1 = const0_rtx, term2, term3;
6552 if (GET_CODE (true_rtx) == IOR
6553 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6554 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6555 else if (GET_CODE (true_rtx) == IOR
6556 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6557 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6558 else if (GET_CODE (false_rtx) == IOR
6559 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6560 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6561 else if (GET_CODE (false_rtx) == IOR
6562 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6563 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6565 term2 = simplify_gen_binary (AND, GET_MODE (src),
6566 XEXP (XEXP (src, 0), 0), true_rtx);
6567 term3 = simplify_gen_binary (AND, GET_MODE (src),
6568 simplify_gen_unary (NOT, GET_MODE (src),
6569 XEXP (XEXP (src, 0), 0),
6574 simplify_gen_binary (IOR, GET_MODE (src),
6575 simplify_gen_binary (IOR, GET_MODE (src),
6582 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6583 whole thing fail. */
6584 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6586 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6589 /* Convert this into a field assignment operation, if possible. */
6590 return make_field_assignment (x);
6593 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6597 simplify_logical (rtx x)
6599 enum machine_mode mode = GET_MODE (x);
6600 rtx op0 = XEXP (x, 0);
6601 rtx op1 = XEXP (x, 1);
6603 switch (GET_CODE (x))
6606 /* We can call simplify_and_const_int only if we don't lose
6607 any (sign) bits when converting INTVAL (op1) to
6608 "unsigned HOST_WIDE_INT". */
6609 if (CONST_INT_P (op1)
6610 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6611 || INTVAL (op1) > 0))
6613 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6614 if (GET_CODE (x) != AND)
6621 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6622 apply the distributive law and then the inverse distributive
6623 law to see if things simplify. */
6624 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6626 rtx result = distribute_and_simplify_rtx (x, 0);
6630 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6632 rtx result = distribute_and_simplify_rtx (x, 1);
6639 /* If we have (ior (and A B) C), apply the distributive law and then
6640 the inverse distributive law to see if things simplify. */
6642 if (GET_CODE (op0) == AND)
6644 rtx result = distribute_and_simplify_rtx (x, 0);
6649 if (GET_CODE (op1) == AND)
6651 rtx result = distribute_and_simplify_rtx (x, 1);
6664 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6665 operations" because they can be replaced with two more basic operations.
6666 ZERO_EXTEND is also considered "compound" because it can be replaced with
6667 an AND operation, which is simpler, though only one operation.
6669 The function expand_compound_operation is called with an rtx expression
6670 and will convert it to the appropriate shifts and AND operations,
6671 simplifying at each stage.
6673 The function make_compound_operation is called to convert an expression
6674 consisting of shifts and ANDs into the equivalent compound expression.
6675 It is the inverse of this function, loosely speaking. */
6678 expand_compound_operation (rtx x)
6680 unsigned HOST_WIDE_INT pos = 0, len;
6682 unsigned int modewidth;
6685 switch (GET_CODE (x))
6690 /* We can't necessarily use a const_int for a multiword mode;
6691 it depends on implicitly extending the value.
6692 Since we don't know the right way to extend it,
6693 we can't tell whether the implicit way is right.
6695 Even for a mode that is no wider than a const_int,
6696 we can't win, because we need to sign extend one of its bits through
6697 the rest of it, and we don't know which bit. */
6698 if (CONST_INT_P (XEXP (x, 0)))
6701 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6702 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6703 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6704 reloaded. If not for that, MEM's would very rarely be safe.
6706 Reject MODEs bigger than a word, because we might not be able
6707 to reference a two-register group starting with an arbitrary register
6708 (and currently gen_lowpart might crash for a SUBREG). */
6710 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6713 /* Reject MODEs that aren't scalar integers because turning vector
6714 or complex modes into shifts causes problems. */
6716 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6719 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6720 /* If the inner object has VOIDmode (the only way this can happen
6721 is if it is an ASM_OPERANDS), we can't do anything since we don't
6722 know how much masking to do. */
6731 /* ... fall through ... */
6734 /* If the operand is a CLOBBER, just return it. */
6735 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6738 if (!CONST_INT_P (XEXP (x, 1))
6739 || !CONST_INT_P (XEXP (x, 2))
6740 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6743 /* Reject MODEs that aren't scalar integers because turning vector
6744 or complex modes into shifts causes problems. */
6746 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6749 len = INTVAL (XEXP (x, 1));
6750 pos = INTVAL (XEXP (x, 2));
6752 /* This should stay within the object being extracted, fail otherwise. */
6753 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6756 if (BITS_BIG_ENDIAN)
6757 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6764 /* Convert sign extension to zero extension, if we know that the high
6765 bit is not set, as this is easier to optimize. It will be converted
6766 back to cheaper alternative in make_extraction. */
6767 if (GET_CODE (x) == SIGN_EXTEND
6768 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6769 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6770 & ~(((unsigned HOST_WIDE_INT)
6771 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6775 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6776 rtx temp2 = expand_compound_operation (temp);
6778 /* Make sure this is a profitable operation. */
6779 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6780 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6782 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6783 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6789 /* We can optimize some special cases of ZERO_EXTEND. */
6790 if (GET_CODE (x) == ZERO_EXTEND)
6792 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6793 know that the last value didn't have any inappropriate bits
6795 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6796 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6797 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6798 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6799 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6800 return XEXP (XEXP (x, 0), 0);
6802 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6803 if (GET_CODE (XEXP (x, 0)) == SUBREG
6804 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6805 && subreg_lowpart_p (XEXP (x, 0))
6806 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6807 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6808 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6809 return SUBREG_REG (XEXP (x, 0));
6811 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6812 is a comparison and STORE_FLAG_VALUE permits. This is like
6813 the first case, but it works even when GET_MODE (x) is larger
6814 than HOST_WIDE_INT. */
6815 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6816 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6817 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6818 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6819 <= HOST_BITS_PER_WIDE_INT)
6820 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6821 return XEXP (XEXP (x, 0), 0);
6823 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6824 if (GET_CODE (XEXP (x, 0)) == SUBREG
6825 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6826 && subreg_lowpart_p (XEXP (x, 0))
6827 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6828 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6829 <= HOST_BITS_PER_WIDE_INT)
6830 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6831 return SUBREG_REG (XEXP (x, 0));
6835 /* If we reach here, we want to return a pair of shifts. The inner
6836 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6837 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6838 logical depending on the value of UNSIGNEDP.
6840 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6841 converted into an AND of a shift.
6843 We must check for the case where the left shift would have a negative
6844 count. This can happen in a case like (x >> 31) & 255 on machines
6845 that can't shift by a constant. On those machines, we would first
6846 combine the shift with the AND to produce a variable-position
6847 extraction. Then the constant of 31 would be substituted in
6848 to produce such a position. */
6850 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6851 if (modewidth >= pos + len)
6853 enum machine_mode mode = GET_MODE (x);
6854 tem = gen_lowpart (mode, XEXP (x, 0));
6855 if (!tem || GET_CODE (tem) == CLOBBER)
6857 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6858 tem, modewidth - pos - len);
6859 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6860 mode, tem, modewidth - len);
6862 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6863 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6864 simplify_shift_const (NULL_RTX, LSHIFTRT,
6867 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6869 /* Any other cases we can't handle. */
6872 /* If we couldn't do this for some reason, return the original
6874 if (GET_CODE (tem) == CLOBBER)
6880 /* X is a SET which contains an assignment of one object into
6881 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6882 or certain SUBREGS). If possible, convert it into a series of
6885 We half-heartedly support variable positions, but do not at all
6886 support variable lengths. */
6889 expand_field_assignment (const_rtx x)
6892 rtx pos; /* Always counts from low bit. */
6894 rtx mask, cleared, masked;
6895 enum machine_mode compute_mode;
6897 /* Loop until we find something we can't simplify. */
6900 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6901 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6903 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6904 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6905 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6907 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6908 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6910 inner = XEXP (SET_DEST (x), 0);
6911 len = INTVAL (XEXP (SET_DEST (x), 1));
6912 pos = XEXP (SET_DEST (x), 2);
6914 /* A constant position should stay within the width of INNER. */
6915 if (CONST_INT_P (pos)
6916 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6919 if (BITS_BIG_ENDIAN)
6921 if (CONST_INT_P (pos))
6922 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6924 else if (GET_CODE (pos) == MINUS
6925 && CONST_INT_P (XEXP (pos, 1))
6926 && (INTVAL (XEXP (pos, 1))
6927 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6928 /* If position is ADJUST - X, new position is X. */
6929 pos = XEXP (pos, 0);
6931 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6932 GEN_INT (GET_MODE_BITSIZE (
6939 /* A SUBREG between two modes that occupy the same numbers of words
6940 can be done by moving the SUBREG to the source. */
6941 else if (GET_CODE (SET_DEST (x)) == SUBREG
6942 /* We need SUBREGs to compute nonzero_bits properly. */
6943 && nonzero_sign_valid
6944 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6945 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6946 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6947 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6949 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6951 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6958 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6959 inner = SUBREG_REG (inner);
6961 compute_mode = GET_MODE (inner);
6963 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6964 if (! SCALAR_INT_MODE_P (compute_mode))
6966 enum machine_mode imode;
6968 /* Don't do anything for vector or complex integral types. */
6969 if (! FLOAT_MODE_P (compute_mode))
6972 /* Try to find an integral mode to pun with. */
6973 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6974 if (imode == BLKmode)
6977 compute_mode = imode;
6978 inner = gen_lowpart (imode, inner);
6981 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6982 if (len >= HOST_BITS_PER_WIDE_INT)
6985 /* Now compute the equivalent expression. Make a copy of INNER
6986 for the SET_DEST in case it is a MEM into which we will substitute;
6987 we don't want shared RTL in that case. */
6988 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
6989 cleared = simplify_gen_binary (AND, compute_mode,
6990 simplify_gen_unary (NOT, compute_mode,
6991 simplify_gen_binary (ASHIFT,
6996 masked = simplify_gen_binary (ASHIFT, compute_mode,
6997 simplify_gen_binary (
6999 gen_lowpart (compute_mode, SET_SRC (x)),
7003 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7004 simplify_gen_binary (IOR, compute_mode,
7011 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7012 it is an RTX that represents a variable starting position; otherwise,
7013 POS is the (constant) starting bit position (counted from the LSB).
7015 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7018 IN_DEST is nonzero if this is a reference in the destination of a
7019 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7020 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7023 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7024 ZERO_EXTRACT should be built even for bits starting at bit 0.
7026 MODE is the desired mode of the result (if IN_DEST == 0).
7028 The result is an RTX for the extraction or NULL_RTX if the target
7032 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7033 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7034 int in_dest, int in_compare)
7036 /* This mode describes the size of the storage area
7037 to fetch the overall value from. Within that, we
7038 ignore the POS lowest bits, etc. */
7039 enum machine_mode is_mode = GET_MODE (inner);
7040 enum machine_mode inner_mode;
7041 enum machine_mode wanted_inner_mode;
7042 enum machine_mode wanted_inner_reg_mode = word_mode;
7043 enum machine_mode pos_mode = word_mode;
7044 enum machine_mode extraction_mode = word_mode;
7045 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7047 rtx orig_pos_rtx = pos_rtx;
7048 HOST_WIDE_INT orig_pos;
7050 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7052 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7053 consider just the QI as the memory to extract from.
7054 The subreg adds or removes high bits; its mode is
7055 irrelevant to the meaning of this extraction,
7056 since POS and LEN count from the lsb. */
7057 if (MEM_P (SUBREG_REG (inner)))
7058 is_mode = GET_MODE (SUBREG_REG (inner));
7059 inner = SUBREG_REG (inner);
7061 else if (GET_CODE (inner) == ASHIFT
7062 && CONST_INT_P (XEXP (inner, 1))
7063 && pos_rtx == 0 && pos == 0
7064 && len > UINTVAL (XEXP (inner, 1)))
7066 /* We're extracting the least significant bits of an rtx
7067 (ashift X (const_int C)), where LEN > C. Extract the
7068 least significant (LEN - C) bits of X, giving an rtx
7069 whose mode is MODE, then shift it left C times. */
7070 new_rtx = make_extraction (mode, XEXP (inner, 0),
7071 0, 0, len - INTVAL (XEXP (inner, 1)),
7072 unsignedp, in_dest, in_compare);
7074 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7077 inner_mode = GET_MODE (inner);
7079 if (pos_rtx && CONST_INT_P (pos_rtx))
7080 pos = INTVAL (pos_rtx), pos_rtx = 0;
7082 /* See if this can be done without an extraction. We never can if the
7083 width of the field is not the same as that of some integer mode. For
7084 registers, we can only avoid the extraction if the position is at the
7085 low-order bit and this is either not in the destination or we have the
7086 appropriate STRICT_LOW_PART operation available.
7088 For MEM, we can avoid an extract if the field starts on an appropriate
7089 boundary and we can change the mode of the memory reference. */
7091 if (tmode != BLKmode
7092 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7094 && (inner_mode == tmode
7096 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
7097 GET_MODE_BITSIZE (inner_mode))
7098 || reg_truncated_to_mode (tmode, inner))
7101 && have_insn_for (STRICT_LOW_PART, tmode))))
7102 || (MEM_P (inner) && pos_rtx == 0
7104 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7105 : BITS_PER_UNIT)) == 0
7106 /* We can't do this if we are widening INNER_MODE (it
7107 may not be aligned, for one thing). */
7108 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
7109 && (inner_mode == tmode
7110 || (! mode_dependent_address_p (XEXP (inner, 0))
7111 && ! MEM_VOLATILE_P (inner))))))
7113 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7114 field. If the original and current mode are the same, we need not
7115 adjust the offset. Otherwise, we do if bytes big endian.
7117 If INNER is not a MEM, get a piece consisting of just the field
7118 of interest (in this case POS % BITS_PER_WORD must be 0). */
7122 HOST_WIDE_INT offset;
7124 /* POS counts from lsb, but make OFFSET count in memory order. */
7125 if (BYTES_BIG_ENDIAN)
7126 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
7128 offset = pos / BITS_PER_UNIT;
7130 new_rtx = adjust_address_nv (inner, tmode, offset);
7132 else if (REG_P (inner))
7134 if (tmode != inner_mode)
7136 /* We can't call gen_lowpart in a DEST since we
7137 always want a SUBREG (see below) and it would sometimes
7138 return a new hard register. */
7141 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7143 if (WORDS_BIG_ENDIAN
7144 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7145 final_word = ((GET_MODE_SIZE (inner_mode)
7146 - GET_MODE_SIZE (tmode))
7147 / UNITS_PER_WORD) - final_word;
7149 final_word *= UNITS_PER_WORD;
7150 if (BYTES_BIG_ENDIAN &&
7151 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7152 final_word += (GET_MODE_SIZE (inner_mode)
7153 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7155 /* Avoid creating invalid subregs, for example when
7156 simplifying (x>>32)&255. */
7157 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7160 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7163 new_rtx = gen_lowpart (tmode, inner);
7169 new_rtx = force_to_mode (inner, tmode,
7170 len >= HOST_BITS_PER_WIDE_INT
7171 ? ~(unsigned HOST_WIDE_INT) 0
7172 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7175 /* If this extraction is going into the destination of a SET,
7176 make a STRICT_LOW_PART unless we made a MEM. */
7179 return (MEM_P (new_rtx) ? new_rtx
7180 : (GET_CODE (new_rtx) != SUBREG
7181 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7182 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7187 if (CONST_INT_P (new_rtx)
7188 || GET_CODE (new_rtx) == CONST_DOUBLE)
7189 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7190 mode, new_rtx, tmode);
7192 /* If we know that no extraneous bits are set, and that the high
7193 bit is not set, convert the extraction to the cheaper of
7194 sign and zero extension, that are equivalent in these cases. */
7195 if (flag_expensive_optimizations
7196 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
7197 && ((nonzero_bits (new_rtx, tmode)
7198 & ~(((unsigned HOST_WIDE_INT)
7199 GET_MODE_MASK (tmode))
7203 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7204 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7206 /* Prefer ZERO_EXTENSION, since it gives more information to
7208 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
7209 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
7214 /* Otherwise, sign- or zero-extend unless we already are in the
7217 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7221 /* Unless this is a COMPARE or we have a funny memory reference,
7222 don't do anything with zero-extending field extracts starting at
7223 the low-order bit since they are simple AND operations. */
7224 if (pos_rtx == 0 && pos == 0 && ! in_dest
7225 && ! in_compare && unsignedp)
7228 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7229 if the position is not a constant and the length is not 1. In all
7230 other cases, we would only be going outside our object in cases when
7231 an original shift would have been undefined. */
7233 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
7234 || (pos_rtx != 0 && len != 1)))
7237 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7238 and the mode for the result. */
7239 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7241 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7242 pos_mode = mode_for_extraction (EP_insv, 2);
7243 extraction_mode = mode_for_extraction (EP_insv, 3);
7246 if (! in_dest && unsignedp
7247 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7249 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7250 pos_mode = mode_for_extraction (EP_extzv, 3);
7251 extraction_mode = mode_for_extraction (EP_extzv, 0);
7254 if (! in_dest && ! unsignedp
7255 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7257 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7258 pos_mode = mode_for_extraction (EP_extv, 3);
7259 extraction_mode = mode_for_extraction (EP_extv, 0);
7262 /* Never narrow an object, since that might not be safe. */
7264 if (mode != VOIDmode
7265 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7266 extraction_mode = mode;
7268 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7269 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7270 pos_mode = GET_MODE (pos_rtx);
7272 /* If this is not from memory, the desired mode is the preferred mode
7273 for an extraction pattern's first input operand, or word_mode if there
7276 wanted_inner_mode = wanted_inner_reg_mode;
7279 /* Be careful not to go beyond the extracted object and maintain the
7280 natural alignment of the memory. */
7281 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7282 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7283 > GET_MODE_BITSIZE (wanted_inner_mode))
7285 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7286 gcc_assert (wanted_inner_mode != VOIDmode);
7289 /* If we have to change the mode of memory and cannot, the desired mode
7290 is EXTRACTION_MODE. */
7291 if (inner_mode != wanted_inner_mode
7292 && (mode_dependent_address_p (XEXP (inner, 0))
7293 || MEM_VOLATILE_P (inner)
7295 wanted_inner_mode = extraction_mode;
7300 if (BITS_BIG_ENDIAN)
7302 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7303 BITS_BIG_ENDIAN style. If position is constant, compute new
7304 position. Otherwise, build subtraction.
7305 Note that POS is relative to the mode of the original argument.
7306 If it's a MEM we need to recompute POS relative to that.
7307 However, if we're extracting from (or inserting into) a register,
7308 we want to recompute POS relative to wanted_inner_mode. */
7309 int width = (MEM_P (inner)
7310 ? GET_MODE_BITSIZE (is_mode)
7311 : GET_MODE_BITSIZE (wanted_inner_mode));
7314 pos = width - len - pos;
7317 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7318 /* POS may be less than 0 now, but we check for that below.
7319 Note that it can only be less than 0 if !MEM_P (inner). */
7322 /* If INNER has a wider mode, and this is a constant extraction, try to
7323 make it smaller and adjust the byte to point to the byte containing
7325 if (wanted_inner_mode != VOIDmode
7326 && inner_mode != wanted_inner_mode
7328 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7330 && ! mode_dependent_address_p (XEXP (inner, 0))
7331 && ! MEM_VOLATILE_P (inner))
7335 /* The computations below will be correct if the machine is big
7336 endian in both bits and bytes or little endian in bits and bytes.
7337 If it is mixed, we must adjust. */
7339 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7340 adjust OFFSET to compensate. */
7341 if (BYTES_BIG_ENDIAN
7342 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7343 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7345 /* We can now move to the desired byte. */
7346 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7347 * GET_MODE_SIZE (wanted_inner_mode);
7348 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7350 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7351 && is_mode != wanted_inner_mode)
7352 offset = (GET_MODE_SIZE (is_mode)
7353 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7355 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7358 /* If INNER is not memory, get it into the proper mode. If we are changing
7359 its mode, POS must be a constant and smaller than the size of the new
7361 else if (!MEM_P (inner))
7363 /* On the LHS, don't create paradoxical subregs implicitely truncating
7364 the register unless TRULY_NOOP_TRUNCATION. */
7366 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (inner)),
7367 GET_MODE_BITSIZE (wanted_inner_mode)))
7370 if (GET_MODE (inner) != wanted_inner_mode
7372 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7378 inner = force_to_mode (inner, wanted_inner_mode,
7380 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7381 ? ~(unsigned HOST_WIDE_INT) 0
7382 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7387 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7388 have to zero extend. Otherwise, we can just use a SUBREG. */
7390 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7392 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7394 /* If we know that no extraneous bits are set, and that the high
7395 bit is not set, convert extraction to cheaper one - either
7396 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7398 if (flag_expensive_optimizations
7399 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
7400 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7401 & ~(((unsigned HOST_WIDE_INT)
7402 GET_MODE_MASK (GET_MODE (pos_rtx)))
7406 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7408 /* Prefer ZERO_EXTENSION, since it gives more information to
7410 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
7411 < rtx_cost (temp, SET, optimize_this_for_speed_p))
7416 else if (pos_rtx != 0
7417 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7418 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7420 /* Make POS_RTX unless we already have it and it is correct. If we don't
7421 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7423 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7424 pos_rtx = orig_pos_rtx;
7426 else if (pos_rtx == 0)
7427 pos_rtx = GEN_INT (pos);
7429 /* Make the required operation. See if we can use existing rtx. */
7430 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7431 extraction_mode, inner, GEN_INT (len), pos_rtx);
7433 new_rtx = gen_lowpart (mode, new_rtx);
7438 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7439 with any other operations in X. Return X without that shift if so. */
7442 extract_left_shift (rtx x, int count)
7444 enum rtx_code code = GET_CODE (x);
7445 enum machine_mode mode = GET_MODE (x);
7451 /* This is the shift itself. If it is wide enough, we will return
7452 either the value being shifted if the shift count is equal to
7453 COUNT or a shift for the difference. */
7454 if (CONST_INT_P (XEXP (x, 1))
7455 && INTVAL (XEXP (x, 1)) >= count)
7456 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7457 INTVAL (XEXP (x, 1)) - count);
7461 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7462 return simplify_gen_unary (code, mode, tem, mode);
7466 case PLUS: case IOR: case XOR: case AND:
7467 /* If we can safely shift this constant and we find the inner shift,
7468 make a new operation. */
7469 if (CONST_INT_P (XEXP (x, 1))
7470 && (UINTVAL (XEXP (x, 1))
7471 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7472 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7473 return simplify_gen_binary (code, mode, tem,
7474 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7485 /* Look at the expression rooted at X. Look for expressions
7486 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7487 Form these expressions.
7489 Return the new rtx, usually just X.
7491 Also, for machines like the VAX that don't have logical shift insns,
7492 try to convert logical to arithmetic shift operations in cases where
7493 they are equivalent. This undoes the canonicalizations to logical
7494 shifts done elsewhere.
7496 We try, as much as possible, to re-use rtl expressions to save memory.
7498 IN_CODE says what kind of expression we are processing. Normally, it is
7499 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7500 being kludges), it is MEM. When processing the arguments of a comparison
7501 or a COMPARE against zero, it is COMPARE. */
7504 make_compound_operation (rtx x, enum rtx_code in_code)
7506 enum rtx_code code = GET_CODE (x);
7507 enum machine_mode mode = GET_MODE (x);
7508 int mode_width = GET_MODE_BITSIZE (mode);
7510 enum rtx_code next_code;
7516 /* Select the code to be used in recursive calls. Once we are inside an
7517 address, we stay there. If we have a comparison, set to COMPARE,
7518 but once inside, go back to our default of SET. */
7520 next_code = (code == MEM ? MEM
7521 : ((code == PLUS || code == MINUS)
7522 && SCALAR_INT_MODE_P (mode)) ? MEM
7523 : ((code == COMPARE || COMPARISON_P (x))
7524 && XEXP (x, 1) == const0_rtx) ? COMPARE
7525 : in_code == COMPARE ? SET : in_code);
7527 /* Process depending on the code of this operation. If NEW is set
7528 nonzero, it will be returned. */
7533 /* Convert shifts by constants into multiplications if inside
7535 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7536 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7537 && INTVAL (XEXP (x, 1)) >= 0
7538 && SCALAR_INT_MODE_P (mode))
7540 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7541 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7543 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7544 if (GET_CODE (new_rtx) == NEG)
7546 new_rtx = XEXP (new_rtx, 0);
7549 multval = trunc_int_for_mode (multval, mode);
7550 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7557 lhs = make_compound_operation (lhs, next_code);
7558 rhs = make_compound_operation (rhs, next_code);
7559 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7560 && SCALAR_INT_MODE_P (mode))
7562 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7564 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7566 else if (GET_CODE (lhs) == MULT
7567 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7569 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7570 simplify_gen_unary (NEG, mode,
7573 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7577 SUBST (XEXP (x, 0), lhs);
7578 SUBST (XEXP (x, 1), rhs);
7581 x = gen_lowpart (mode, new_rtx);
7587 lhs = make_compound_operation (lhs, next_code);
7588 rhs = make_compound_operation (rhs, next_code);
7589 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7590 && SCALAR_INT_MODE_P (mode))
7592 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7594 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7596 else if (GET_CODE (rhs) == MULT
7597 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7599 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7600 simplify_gen_unary (NEG, mode,
7603 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7607 SUBST (XEXP (x, 0), lhs);
7608 SUBST (XEXP (x, 1), rhs);
7611 return gen_lowpart (mode, new_rtx);
7614 /* If the second operand is not a constant, we can't do anything
7616 if (!CONST_INT_P (XEXP (x, 1)))
7619 /* If the constant is a power of two minus one and the first operand
7620 is a logical right shift, make an extraction. */
7621 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7622 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7624 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7625 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7626 0, in_code == COMPARE);
7629 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7630 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7631 && subreg_lowpart_p (XEXP (x, 0))
7632 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7633 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7635 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7637 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7638 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7639 0, in_code == COMPARE);
7641 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7642 else if ((GET_CODE (XEXP (x, 0)) == XOR
7643 || GET_CODE (XEXP (x, 0)) == IOR)
7644 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7645 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7646 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7648 /* Apply the distributive law, and then try to make extractions. */
7649 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7650 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7652 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7654 new_rtx = make_compound_operation (new_rtx, in_code);
7657 /* If we are have (and (rotate X C) M) and C is larger than the number
7658 of bits in M, this is an extraction. */
7660 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7661 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7662 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7663 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7665 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7666 new_rtx = make_extraction (mode, new_rtx,
7667 (GET_MODE_BITSIZE (mode)
7668 - INTVAL (XEXP (XEXP (x, 0), 1))),
7669 NULL_RTX, i, 1, 0, in_code == COMPARE);
7672 /* On machines without logical shifts, if the operand of the AND is
7673 a logical shift and our mask turns off all the propagated sign
7674 bits, we can replace the logical shift with an arithmetic shift. */
7675 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7676 && !have_insn_for (LSHIFTRT, mode)
7677 && have_insn_for (ASHIFTRT, mode)
7678 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7679 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7680 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7681 && mode_width <= HOST_BITS_PER_WIDE_INT)
7683 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7685 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7686 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7688 gen_rtx_ASHIFTRT (mode,
7689 make_compound_operation
7690 (XEXP (XEXP (x, 0), 0), next_code),
7691 XEXP (XEXP (x, 0), 1)));
7694 /* If the constant is one less than a power of two, this might be
7695 representable by an extraction even if no shift is present.
7696 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7697 we are in a COMPARE. */
7698 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7699 new_rtx = make_extraction (mode,
7700 make_compound_operation (XEXP (x, 0),
7702 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7704 /* If we are in a comparison and this is an AND with a power of two,
7705 convert this into the appropriate bit extract. */
7706 else if (in_code == COMPARE
7707 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7708 new_rtx = make_extraction (mode,
7709 make_compound_operation (XEXP (x, 0),
7711 i, NULL_RTX, 1, 1, 0, 1);
7716 /* If the sign bit is known to be zero, replace this with an
7717 arithmetic shift. */
7718 if (have_insn_for (ASHIFTRT, mode)
7719 && ! have_insn_for (LSHIFTRT, mode)
7720 && mode_width <= HOST_BITS_PER_WIDE_INT
7721 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7723 new_rtx = gen_rtx_ASHIFTRT (mode,
7724 make_compound_operation (XEXP (x, 0),
7730 /* ... fall through ... */
7736 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7737 this is a SIGN_EXTRACT. */
7738 if (CONST_INT_P (rhs)
7739 && GET_CODE (lhs) == ASHIFT
7740 && CONST_INT_P (XEXP (lhs, 1))
7741 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7742 && INTVAL (XEXP (lhs, 1)) >= 0
7743 && INTVAL (rhs) < mode_width)
7745 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7746 new_rtx = make_extraction (mode, new_rtx,
7747 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7748 NULL_RTX, mode_width - INTVAL (rhs),
7749 code == LSHIFTRT, 0, in_code == COMPARE);
7753 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7754 If so, try to merge the shifts into a SIGN_EXTEND. We could
7755 also do this for some cases of SIGN_EXTRACT, but it doesn't
7756 seem worth the effort; the case checked for occurs on Alpha. */
7759 && ! (GET_CODE (lhs) == SUBREG
7760 && (OBJECT_P (SUBREG_REG (lhs))))
7761 && CONST_INT_P (rhs)
7762 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7763 && INTVAL (rhs) < mode_width
7764 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7765 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7766 0, NULL_RTX, mode_width - INTVAL (rhs),
7767 code == LSHIFTRT, 0, in_code == COMPARE);
7772 /* Call ourselves recursively on the inner expression. If we are
7773 narrowing the object and it has a different RTL code from
7774 what it originally did, do this SUBREG as a force_to_mode. */
7776 rtx inner = SUBREG_REG (x), simplified;
7778 tem = make_compound_operation (inner, in_code);
7781 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7785 if (GET_CODE (tem) != GET_CODE (inner)
7786 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7787 && subreg_lowpart_p (x))
7790 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7792 /* If we have something other than a SUBREG, we might have
7793 done an expansion, so rerun ourselves. */
7794 if (GET_CODE (newer) != SUBREG)
7795 newer = make_compound_operation (newer, in_code);
7797 /* force_to_mode can expand compounds. If it just re-expanded the
7798 compound, use gen_lowpart to convert to the desired mode. */
7799 if (rtx_equal_p (newer, x)
7800 /* Likewise if it re-expanded the compound only partially.
7801 This happens for SUBREG of ZERO_EXTRACT if they extract
7802 the same number of bits. */
7803 || (GET_CODE (newer) == SUBREG
7804 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7805 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7806 && GET_CODE (inner) == AND
7807 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7808 return gen_lowpart (GET_MODE (x), tem);
7824 x = gen_lowpart (mode, new_rtx);
7825 code = GET_CODE (x);
7828 /* Now recursively process each operand of this operation. */
7829 fmt = GET_RTX_FORMAT (code);
7830 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7833 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7834 SUBST (XEXP (x, i), new_rtx);
7836 else if (fmt[i] == 'E')
7837 for (j = 0; j < XVECLEN (x, i); j++)
7839 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7840 SUBST (XVECEXP (x, i, j), new_rtx);
7844 /* If this is a commutative operation, the changes to the operands
7845 may have made it noncanonical. */
7846 if (COMMUTATIVE_ARITH_P (x)
7847 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7850 SUBST (XEXP (x, 0), XEXP (x, 1));
7851 SUBST (XEXP (x, 1), tem);
7857 /* Given M see if it is a value that would select a field of bits
7858 within an item, but not the entire word. Return -1 if not.
7859 Otherwise, return the starting position of the field, where 0 is the
7862 *PLEN is set to the length of the field. */
7865 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7867 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7868 int pos = m ? ctz_hwi (m) : -1;
7872 /* Now shift off the low-order zero bits and see if we have a
7873 power of two minus 1. */
7874 len = exact_log2 ((m >> pos) + 1);
7883 /* If X refers to a register that equals REG in value, replace these
7884 references with REG. */
7886 canon_reg_for_combine (rtx x, rtx reg)
7893 enum rtx_code code = GET_CODE (x);
7894 switch (GET_RTX_CLASS (code))
7897 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7898 if (op0 != XEXP (x, 0))
7899 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7904 case RTX_COMM_ARITH:
7905 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7906 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7907 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7908 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7912 case RTX_COMM_COMPARE:
7913 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7914 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7915 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7916 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7917 GET_MODE (op0), op0, op1);
7921 case RTX_BITFIELD_OPS:
7922 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7923 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7924 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7925 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7926 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7927 GET_MODE (op0), op0, op1, op2);
7932 if (rtx_equal_p (get_last_value (reg), x)
7933 || rtx_equal_p (reg, get_last_value (x)))
7942 fmt = GET_RTX_FORMAT (code);
7944 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7947 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7948 if (op != XEXP (x, i))
7958 else if (fmt[i] == 'E')
7961 for (j = 0; j < XVECLEN (x, i); j++)
7963 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7964 if (op != XVECEXP (x, i, j))
7971 XVECEXP (x, i, j) = op;
7982 /* Return X converted to MODE. If the value is already truncated to
7983 MODE we can just return a subreg even though in the general case we
7984 would need an explicit truncation. */
7987 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7989 if (!CONST_INT_P (x)
7990 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
7991 && !TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7992 GET_MODE_BITSIZE (GET_MODE (x)))
7993 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
7995 /* Bit-cast X into an integer mode. */
7996 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
7997 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
7998 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8002 return gen_lowpart (mode, x);
8005 /* See if X can be simplified knowing that we will only refer to it in
8006 MODE and will only refer to those bits that are nonzero in MASK.
8007 If other bits are being computed or if masking operations are done
8008 that select a superset of the bits in MASK, they can sometimes be
8011 Return a possibly simplified expression, but always convert X to
8012 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8014 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8015 are all off in X. This is used when X will be complemented, by either
8016 NOT, NEG, or XOR. */
8019 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8022 enum rtx_code code = GET_CODE (x);
8023 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8024 enum machine_mode op_mode;
8025 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8028 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8029 code below will do the wrong thing since the mode of such an
8030 expression is VOIDmode.
8032 Also do nothing if X is a CLOBBER; this can happen if X was
8033 the return value from a call to gen_lowpart. */
8034 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8037 /* We want to perform the operation is its present mode unless we know
8038 that the operation is valid in MODE, in which case we do the operation
8040 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8041 && have_insn_for (code, mode))
8042 ? mode : GET_MODE (x));
8044 /* It is not valid to do a right-shift in a narrower mode
8045 than the one it came in with. */
8046 if ((code == LSHIFTRT || code == ASHIFTRT)
8047 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
8048 op_mode = GET_MODE (x);
8050 /* Truncate MASK to fit OP_MODE. */
8052 mask &= GET_MODE_MASK (op_mode);
8054 /* When we have an arithmetic operation, or a shift whose count we
8055 do not know, we need to assume that all bits up to the highest-order
8056 bit in MASK will be needed. This is how we form such a mask. */
8057 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8058 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8060 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8063 /* Determine what bits of X are guaranteed to be (non)zero. */
8064 nonzero = nonzero_bits (x, mode);
8066 /* If none of the bits in X are needed, return a zero. */
8067 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8070 /* If X is a CONST_INT, return a new one. Do this here since the
8071 test below will fail. */
8072 if (CONST_INT_P (x))
8074 if (SCALAR_INT_MODE_P (mode))
8075 return gen_int_mode (INTVAL (x) & mask, mode);
8078 x = GEN_INT (INTVAL (x) & mask);
8079 return gen_lowpart_common (mode, x);
8083 /* If X is narrower than MODE and we want all the bits in X's mode, just
8084 get X in the proper mode. */
8085 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8086 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8087 return gen_lowpart (mode, x);
8089 /* We can ignore the effect of a SUBREG if it narrows the mode or
8090 if the constant masks to zero all the bits the mode doesn't have. */
8091 if (GET_CODE (x) == SUBREG
8092 && subreg_lowpart_p (x)
8093 && ((GET_MODE_SIZE (GET_MODE (x))
8094 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8096 & GET_MODE_MASK (GET_MODE (x))
8097 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8098 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8100 /* The arithmetic simplifications here only work for scalar integer modes. */
8101 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8102 return gen_lowpart_or_truncate (mode, x);
8107 /* If X is a (clobber (const_int)), return it since we know we are
8108 generating something that won't match. */
8115 x = expand_compound_operation (x);
8116 if (GET_CODE (x) != code)
8117 return force_to_mode (x, mode, mask, next_select);
8121 /* Similarly for a truncate. */
8122 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8125 /* If this is an AND with a constant, convert it into an AND
8126 whose constant is the AND of that constant with MASK. If it
8127 remains an AND of MASK, delete it since it is redundant. */
8129 if (CONST_INT_P (XEXP (x, 1)))
8131 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8132 mask & INTVAL (XEXP (x, 1)));
8134 /* If X is still an AND, see if it is an AND with a mask that
8135 is just some low-order bits. If so, and it is MASK, we don't
8138 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8139 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8143 /* If it remains an AND, try making another AND with the bits
8144 in the mode mask that aren't in MASK turned on. If the
8145 constant in the AND is wide enough, this might make a
8146 cheaper constant. */
8148 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8149 && GET_MODE_MASK (GET_MODE (x)) != mask
8150 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
8152 unsigned HOST_WIDE_INT cval
8153 = UINTVAL (XEXP (x, 1))
8154 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8155 int width = GET_MODE_BITSIZE (GET_MODE (x));
8158 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8159 number, sign extend it. */
8160 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8161 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8162 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8164 y = simplify_gen_binary (AND, GET_MODE (x),
8165 XEXP (x, 0), GEN_INT (cval));
8166 if (rtx_cost (y, SET, optimize_this_for_speed_p)
8167 < rtx_cost (x, SET, optimize_this_for_speed_p))
8177 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8178 low-order bits (as in an alignment operation) and FOO is already
8179 aligned to that boundary, mask C1 to that boundary as well.
8180 This may eliminate that PLUS and, later, the AND. */
8183 unsigned int width = GET_MODE_BITSIZE (mode);
8184 unsigned HOST_WIDE_INT smask = mask;
8186 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8187 number, sign extend it. */
8189 if (width < HOST_BITS_PER_WIDE_INT
8190 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8191 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8193 if (CONST_INT_P (XEXP (x, 1))
8194 && exact_log2 (- smask) >= 0
8195 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8196 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8197 return force_to_mode (plus_constant (XEXP (x, 0),
8198 (INTVAL (XEXP (x, 1)) & smask)),
8199 mode, smask, next_select);
8202 /* ... fall through ... */
8205 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8206 most significant bit in MASK since carries from those bits will
8207 affect the bits we are interested in. */
8212 /* If X is (minus C Y) where C's least set bit is larger than any bit
8213 in the mask, then we may replace with (neg Y). */
8214 if (CONST_INT_P (XEXP (x, 0))
8215 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8216 & -INTVAL (XEXP (x, 0))))
8219 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8221 return force_to_mode (x, mode, mask, next_select);
8224 /* Similarly, if C contains every bit in the fuller_mask, then we may
8225 replace with (not Y). */
8226 if (CONST_INT_P (XEXP (x, 0))
8227 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8229 x = simplify_gen_unary (NOT, GET_MODE (x),
8230 XEXP (x, 1), GET_MODE (x));
8231 return force_to_mode (x, mode, mask, next_select);
8239 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8240 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8241 operation which may be a bitfield extraction. Ensure that the
8242 constant we form is not wider than the mode of X. */
8244 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8245 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8246 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8247 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8248 && CONST_INT_P (XEXP (x, 1))
8249 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8250 + floor_log2 (INTVAL (XEXP (x, 1))))
8251 < GET_MODE_BITSIZE (GET_MODE (x)))
8252 && (UINTVAL (XEXP (x, 1))
8253 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8255 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8256 << INTVAL (XEXP (XEXP (x, 0), 1)));
8257 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8258 XEXP (XEXP (x, 0), 0), temp);
8259 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8260 XEXP (XEXP (x, 0), 1));
8261 return force_to_mode (x, mode, mask, next_select);
8265 /* For most binary operations, just propagate into the operation and
8266 change the mode if we have an operation of that mode. */
8268 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8269 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8271 /* If we ended up truncating both operands, truncate the result of the
8272 operation instead. */
8273 if (GET_CODE (op0) == TRUNCATE
8274 && GET_CODE (op1) == TRUNCATE)
8276 op0 = XEXP (op0, 0);
8277 op1 = XEXP (op1, 0);
8280 op0 = gen_lowpart_or_truncate (op_mode, op0);
8281 op1 = gen_lowpart_or_truncate (op_mode, op1);
8283 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8284 x = simplify_gen_binary (code, op_mode, op0, op1);
8288 /* For left shifts, do the same, but just for the first operand.
8289 However, we cannot do anything with shifts where we cannot
8290 guarantee that the counts are smaller than the size of the mode
8291 because such a count will have a different meaning in a
8294 if (! (CONST_INT_P (XEXP (x, 1))
8295 && INTVAL (XEXP (x, 1)) >= 0
8296 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
8297 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8298 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8299 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
8302 /* If the shift count is a constant and we can do arithmetic in
8303 the mode of the shift, refine which bits we need. Otherwise, use the
8304 conservative form of the mask. */
8305 if (CONST_INT_P (XEXP (x, 1))
8306 && INTVAL (XEXP (x, 1)) >= 0
8307 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
8308 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8309 mask >>= INTVAL (XEXP (x, 1));
8313 op0 = gen_lowpart_or_truncate (op_mode,
8314 force_to_mode (XEXP (x, 0), op_mode,
8315 mask, next_select));
8317 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8318 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8322 /* Here we can only do something if the shift count is a constant,
8323 this shift constant is valid for the host, and we can do arithmetic
8326 if (CONST_INT_P (XEXP (x, 1))
8327 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8328 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
8330 rtx inner = XEXP (x, 0);
8331 unsigned HOST_WIDE_INT inner_mask;
8333 /* Select the mask of the bits we need for the shift operand. */
8334 inner_mask = mask << INTVAL (XEXP (x, 1));
8336 /* We can only change the mode of the shift if we can do arithmetic
8337 in the mode of the shift and INNER_MASK is no wider than the
8338 width of X's mode. */
8339 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8340 op_mode = GET_MODE (x);
8342 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8344 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8345 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8348 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8349 shift and AND produces only copies of the sign bit (C2 is one less
8350 than a power of two), we can do this with just a shift. */
8352 if (GET_CODE (x) == LSHIFTRT
8353 && CONST_INT_P (XEXP (x, 1))
8354 /* The shift puts one of the sign bit copies in the least significant
8356 && ((INTVAL (XEXP (x, 1))
8357 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8358 >= GET_MODE_BITSIZE (GET_MODE (x)))
8359 && exact_log2 (mask + 1) >= 0
8360 /* Number of bits left after the shift must be more than the mask
8362 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8363 <= GET_MODE_BITSIZE (GET_MODE (x)))
8364 /* Must be more sign bit copies than the mask needs. */
8365 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8366 >= exact_log2 (mask + 1)))
8367 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8368 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
8369 - exact_log2 (mask + 1)));
8374 /* If we are just looking for the sign bit, we don't need this shift at
8375 all, even if it has a variable count. */
8376 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8377 && (mask == ((unsigned HOST_WIDE_INT) 1
8378 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8379 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8381 /* If this is a shift by a constant, get a mask that contains those bits
8382 that are not copies of the sign bit. We then have two cases: If
8383 MASK only includes those bits, this can be a logical shift, which may
8384 allow simplifications. If MASK is a single-bit field not within
8385 those bits, we are requesting a copy of the sign bit and hence can
8386 shift the sign bit to the appropriate location. */
8388 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8389 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8393 /* If the considered data is wider than HOST_WIDE_INT, we can't
8394 represent a mask for all its bits in a single scalar.
8395 But we only care about the lower bits, so calculate these. */
8397 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8399 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8401 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8402 is the number of bits a full-width mask would have set.
8403 We need only shift if these are fewer than nonzero can
8404 hold. If not, we must keep all bits set in nonzero. */
8406 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8407 < HOST_BITS_PER_WIDE_INT)
8408 nonzero >>= INTVAL (XEXP (x, 1))
8409 + HOST_BITS_PER_WIDE_INT
8410 - GET_MODE_BITSIZE (GET_MODE (x)) ;
8414 nonzero = GET_MODE_MASK (GET_MODE (x));
8415 nonzero >>= INTVAL (XEXP (x, 1));
8418 if ((mask & ~nonzero) == 0)
8420 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8421 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8422 if (GET_CODE (x) != ASHIFTRT)
8423 return force_to_mode (x, mode, mask, next_select);
8426 else if ((i = exact_log2 (mask)) >= 0)
8428 x = simplify_shift_const
8429 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8430 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
8432 if (GET_CODE (x) != ASHIFTRT)
8433 return force_to_mode (x, mode, mask, next_select);
8437 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8438 even if the shift count isn't a constant. */
8440 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8441 XEXP (x, 0), XEXP (x, 1));
8445 /* If this is a zero- or sign-extension operation that just affects bits
8446 we don't care about, remove it. Be sure the call above returned
8447 something that is still a shift. */
8449 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8450 && CONST_INT_P (XEXP (x, 1))
8451 && INTVAL (XEXP (x, 1)) >= 0
8452 && (INTVAL (XEXP (x, 1))
8453 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
8454 && GET_CODE (XEXP (x, 0)) == ASHIFT
8455 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8456 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8463 /* If the shift count is constant and we can do computations
8464 in the mode of X, compute where the bits we care about are.
8465 Otherwise, we can't do anything. Don't change the mode of
8466 the shift or propagate MODE into the shift, though. */
8467 if (CONST_INT_P (XEXP (x, 1))
8468 && INTVAL (XEXP (x, 1)) >= 0)
8470 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8471 GET_MODE (x), GEN_INT (mask),
8473 if (temp && CONST_INT_P (temp))
8475 force_to_mode (XEXP (x, 0), GET_MODE (x),
8476 INTVAL (temp), next_select));
8481 /* If we just want the low-order bit, the NEG isn't needed since it
8482 won't change the low-order bit. */
8484 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8486 /* We need any bits less significant than the most significant bit in
8487 MASK since carries from those bits will affect the bits we are
8493 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8494 same as the XOR case above. Ensure that the constant we form is not
8495 wider than the mode of X. */
8497 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8498 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8499 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8500 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8501 < GET_MODE_BITSIZE (GET_MODE (x)))
8502 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8504 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8506 temp = simplify_gen_binary (XOR, GET_MODE (x),
8507 XEXP (XEXP (x, 0), 0), temp);
8508 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8509 temp, XEXP (XEXP (x, 0), 1));
8511 return force_to_mode (x, mode, mask, next_select);
8514 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8515 use the full mask inside the NOT. */
8519 op0 = gen_lowpart_or_truncate (op_mode,
8520 force_to_mode (XEXP (x, 0), mode, mask,
8522 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8523 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8527 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8528 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8529 which is equal to STORE_FLAG_VALUE. */
8530 if ((mask & ~STORE_FLAG_VALUE) == 0
8531 && XEXP (x, 1) == const0_rtx
8532 && GET_MODE (XEXP (x, 0)) == mode
8533 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8534 && (nonzero_bits (XEXP (x, 0), mode)
8535 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8536 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8541 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8542 written in a narrower mode. We play it safe and do not do so. */
8545 gen_lowpart_or_truncate (GET_MODE (x),
8546 force_to_mode (XEXP (x, 1), mode,
8547 mask, next_select)));
8549 gen_lowpart_or_truncate (GET_MODE (x),
8550 force_to_mode (XEXP (x, 2), mode,
8551 mask, next_select)));
8558 /* Ensure we return a value of the proper mode. */
8559 return gen_lowpart_or_truncate (mode, x);
8562 /* Return nonzero if X is an expression that has one of two values depending on
8563 whether some other value is zero or nonzero. In that case, we return the
8564 value that is being tested, *PTRUE is set to the value if the rtx being
8565 returned has a nonzero value, and *PFALSE is set to the other alternative.
8567 If we return zero, we set *PTRUE and *PFALSE to X. */
8570 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8572 enum machine_mode mode = GET_MODE (x);
8573 enum rtx_code code = GET_CODE (x);
8574 rtx cond0, cond1, true0, true1, false0, false1;
8575 unsigned HOST_WIDE_INT nz;
8577 /* If we are comparing a value against zero, we are done. */
8578 if ((code == NE || code == EQ)
8579 && XEXP (x, 1) == const0_rtx)
8581 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8582 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8586 /* If this is a unary operation whose operand has one of two values, apply
8587 our opcode to compute those values. */
8588 else if (UNARY_P (x)
8589 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8591 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8592 *pfalse = simplify_gen_unary (code, mode, false0,
8593 GET_MODE (XEXP (x, 0)));
8597 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8598 make can't possibly match and would suppress other optimizations. */
8599 else if (code == COMPARE)
8602 /* If this is a binary operation, see if either side has only one of two
8603 values. If either one does or if both do and they are conditional on
8604 the same value, compute the new true and false values. */
8605 else if (BINARY_P (x))
8607 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8608 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8610 if ((cond0 != 0 || cond1 != 0)
8611 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8613 /* If if_then_else_cond returned zero, then true/false are the
8614 same rtl. We must copy one of them to prevent invalid rtl
8617 true0 = copy_rtx (true0);
8618 else if (cond1 == 0)
8619 true1 = copy_rtx (true1);
8621 if (COMPARISON_P (x))
8623 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8625 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8630 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8631 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8634 return cond0 ? cond0 : cond1;
8637 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8638 operands is zero when the other is nonzero, and vice-versa,
8639 and STORE_FLAG_VALUE is 1 or -1. */
8641 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8642 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8644 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8646 rtx op0 = XEXP (XEXP (x, 0), 1);
8647 rtx op1 = XEXP (XEXP (x, 1), 1);
8649 cond0 = XEXP (XEXP (x, 0), 0);
8650 cond1 = XEXP (XEXP (x, 1), 0);
8652 if (COMPARISON_P (cond0)
8653 && COMPARISON_P (cond1)
8654 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8655 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8656 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8657 || ((swap_condition (GET_CODE (cond0))
8658 == reversed_comparison_code (cond1, NULL))
8659 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8660 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8661 && ! side_effects_p (x))
8663 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8664 *pfalse = simplify_gen_binary (MULT, mode,
8666 ? simplify_gen_unary (NEG, mode,
8674 /* Similarly for MULT, AND and UMIN, except that for these the result
8676 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8677 && (code == MULT || code == AND || code == UMIN)
8678 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8680 cond0 = XEXP (XEXP (x, 0), 0);
8681 cond1 = XEXP (XEXP (x, 1), 0);
8683 if (COMPARISON_P (cond0)
8684 && COMPARISON_P (cond1)
8685 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8686 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8687 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8688 || ((swap_condition (GET_CODE (cond0))
8689 == reversed_comparison_code (cond1, NULL))
8690 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8691 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8692 && ! side_effects_p (x))
8694 *ptrue = *pfalse = const0_rtx;
8700 else if (code == IF_THEN_ELSE)
8702 /* If we have IF_THEN_ELSE already, extract the condition and
8703 canonicalize it if it is NE or EQ. */
8704 cond0 = XEXP (x, 0);
8705 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8706 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8707 return XEXP (cond0, 0);
8708 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8710 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8711 return XEXP (cond0, 0);
8717 /* If X is a SUBREG, we can narrow both the true and false values
8718 if the inner expression, if there is a condition. */
8719 else if (code == SUBREG
8720 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8723 true0 = simplify_gen_subreg (mode, true0,
8724 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8725 false0 = simplify_gen_subreg (mode, false0,
8726 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8727 if (true0 && false0)
8735 /* If X is a constant, this isn't special and will cause confusions
8736 if we treat it as such. Likewise if it is equivalent to a constant. */
8737 else if (CONSTANT_P (x)
8738 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8741 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8742 will be least confusing to the rest of the compiler. */
8743 else if (mode == BImode)
8745 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8749 /* If X is known to be either 0 or -1, those are the true and
8750 false values when testing X. */
8751 else if (x == constm1_rtx || x == const0_rtx
8752 || (mode != VOIDmode
8753 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
8755 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8759 /* Likewise for 0 or a single bit. */
8760 else if (SCALAR_INT_MODE_P (mode)
8761 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8762 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8764 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8768 /* Otherwise fail; show no condition with true and false values the same. */
8769 *ptrue = *pfalse = x;
8773 /* Return the value of expression X given the fact that condition COND
8774 is known to be true when applied to REG as its first operand and VAL
8775 as its second. X is known to not be shared and so can be modified in
8778 We only handle the simplest cases, and specifically those cases that
8779 arise with IF_THEN_ELSE expressions. */
8782 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8784 enum rtx_code code = GET_CODE (x);
8789 if (side_effects_p (x))
8792 /* If either operand of the condition is a floating point value,
8793 then we have to avoid collapsing an EQ comparison. */
8795 && rtx_equal_p (x, reg)
8796 && ! FLOAT_MODE_P (GET_MODE (x))
8797 && ! FLOAT_MODE_P (GET_MODE (val)))
8800 if (cond == UNEQ && rtx_equal_p (x, reg))
8803 /* If X is (abs REG) and we know something about REG's relationship
8804 with zero, we may be able to simplify this. */
8806 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8809 case GE: case GT: case EQ:
8812 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8814 GET_MODE (XEXP (x, 0)));
8819 /* The only other cases we handle are MIN, MAX, and comparisons if the
8820 operands are the same as REG and VAL. */
8822 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8824 if (rtx_equal_p (XEXP (x, 0), val))
8825 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8827 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8829 if (COMPARISON_P (x))
8831 if (comparison_dominates_p (cond, code))
8832 return const_true_rtx;
8834 code = reversed_comparison_code (x, NULL);
8836 && comparison_dominates_p (cond, code))
8841 else if (code == SMAX || code == SMIN
8842 || code == UMIN || code == UMAX)
8844 int unsignedp = (code == UMIN || code == UMAX);
8846 /* Do not reverse the condition when it is NE or EQ.
8847 This is because we cannot conclude anything about
8848 the value of 'SMAX (x, y)' when x is not equal to y,
8849 but we can when x equals y. */
8850 if ((code == SMAX || code == UMAX)
8851 && ! (cond == EQ || cond == NE))
8852 cond = reverse_condition (cond);
8857 return unsignedp ? x : XEXP (x, 1);
8859 return unsignedp ? x : XEXP (x, 0);
8861 return unsignedp ? XEXP (x, 1) : x;
8863 return unsignedp ? XEXP (x, 0) : x;
8870 else if (code == SUBREG)
8872 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8873 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8875 if (SUBREG_REG (x) != r)
8877 /* We must simplify subreg here, before we lose track of the
8878 original inner_mode. */
8879 new_rtx = simplify_subreg (GET_MODE (x), r,
8880 inner_mode, SUBREG_BYTE (x));
8884 SUBST (SUBREG_REG (x), r);
8889 /* We don't have to handle SIGN_EXTEND here, because even in the
8890 case of replacing something with a modeless CONST_INT, a
8891 CONST_INT is already (supposed to be) a valid sign extension for
8892 its narrower mode, which implies it's already properly
8893 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8894 story is different. */
8895 else if (code == ZERO_EXTEND)
8897 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8898 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8900 if (XEXP (x, 0) != r)
8902 /* We must simplify the zero_extend here, before we lose
8903 track of the original inner_mode. */
8904 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8909 SUBST (XEXP (x, 0), r);
8915 fmt = GET_RTX_FORMAT (code);
8916 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8919 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8920 else if (fmt[i] == 'E')
8921 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8922 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8929 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8930 assignment as a field assignment. */
8933 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8935 if (x == y || rtx_equal_p (x, y))
8938 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8941 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8942 Note that all SUBREGs of MEM are paradoxical; otherwise they
8943 would have been rewritten. */
8944 if (MEM_P (x) && GET_CODE (y) == SUBREG
8945 && MEM_P (SUBREG_REG (y))
8946 && rtx_equal_p (SUBREG_REG (y),
8947 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8950 if (MEM_P (y) && GET_CODE (x) == SUBREG
8951 && MEM_P (SUBREG_REG (x))
8952 && rtx_equal_p (SUBREG_REG (x),
8953 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8956 /* We used to see if get_last_value of X and Y were the same but that's
8957 not correct. In one direction, we'll cause the assignment to have
8958 the wrong destination and in the case, we'll import a register into this
8959 insn that might have already have been dead. So fail if none of the
8960 above cases are true. */
8964 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8965 Return that assignment if so.
8967 We only handle the most common cases. */
8970 make_field_assignment (rtx x)
8972 rtx dest = SET_DEST (x);
8973 rtx src = SET_SRC (x);
8978 unsigned HOST_WIDE_INT len;
8980 enum machine_mode mode;
8982 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8983 a clear of a one-bit field. We will have changed it to
8984 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8987 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8988 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8989 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8990 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8992 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8995 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8999 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9000 && subreg_lowpart_p (XEXP (src, 0))
9001 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9002 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9003 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9004 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9005 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9006 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9008 assign = make_extraction (VOIDmode, dest, 0,
9009 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9012 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9016 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9018 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9019 && XEXP (XEXP (src, 0), 0) == const1_rtx
9020 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9022 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9025 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9029 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9030 SRC is an AND with all bits of that field set, then we can discard
9032 if (GET_CODE (dest) == ZERO_EXTRACT
9033 && CONST_INT_P (XEXP (dest, 1))
9034 && GET_CODE (src) == AND
9035 && CONST_INT_P (XEXP (src, 1)))
9037 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9038 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9039 unsigned HOST_WIDE_INT ze_mask;
9041 if (width >= HOST_BITS_PER_WIDE_INT)
9044 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9046 /* Complete overlap. We can remove the source AND. */
9047 if ((and_mask & ze_mask) == ze_mask)
9048 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9050 /* Partial overlap. We can reduce the source AND. */
9051 if ((and_mask & ze_mask) != and_mask)
9053 mode = GET_MODE (src);
9054 src = gen_rtx_AND (mode, XEXP (src, 0),
9055 gen_int_mode (and_mask & ze_mask, mode));
9056 return gen_rtx_SET (VOIDmode, dest, src);
9060 /* The other case we handle is assignments into a constant-position
9061 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9062 a mask that has all one bits except for a group of zero bits and
9063 OTHER is known to have zeros where C1 has ones, this is such an
9064 assignment. Compute the position and length from C1. Shift OTHER
9065 to the appropriate position, force it to the required mode, and
9066 make the extraction. Check for the AND in both operands. */
9068 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9071 rhs = expand_compound_operation (XEXP (src, 0));
9072 lhs = expand_compound_operation (XEXP (src, 1));
9074 if (GET_CODE (rhs) == AND
9075 && CONST_INT_P (XEXP (rhs, 1))
9076 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9077 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9078 else if (GET_CODE (lhs) == AND
9079 && CONST_INT_P (XEXP (lhs, 1))
9080 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9081 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9085 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9086 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
9087 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9088 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9091 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9095 /* The mode to use for the source is the mode of the assignment, or of
9096 what is inside a possible STRICT_LOW_PART. */
9097 mode = (GET_CODE (assign) == STRICT_LOW_PART
9098 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9100 /* Shift OTHER right POS places and make it the source, restricting it
9101 to the proper length and mode. */
9103 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9107 src = force_to_mode (src, mode,
9108 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
9109 ? ~(unsigned HOST_WIDE_INT) 0
9110 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9113 /* If SRC is masked by an AND that does not make a difference in
9114 the value being stored, strip it. */
9115 if (GET_CODE (assign) == ZERO_EXTRACT
9116 && CONST_INT_P (XEXP (assign, 1))
9117 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9118 && GET_CODE (src) == AND
9119 && CONST_INT_P (XEXP (src, 1))
9120 && UINTVAL (XEXP (src, 1))
9121 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9122 src = XEXP (src, 0);
9124 return gen_rtx_SET (VOIDmode, assign, src);
9127 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9131 apply_distributive_law (rtx x)
9133 enum rtx_code code = GET_CODE (x);
9134 enum rtx_code inner_code;
9135 rtx lhs, rhs, other;
9138 /* Distributivity is not true for floating point as it can change the
9139 value. So we don't do it unless -funsafe-math-optimizations. */
9140 if (FLOAT_MODE_P (GET_MODE (x))
9141 && ! flag_unsafe_math_optimizations)
9144 /* The outer operation can only be one of the following: */
9145 if (code != IOR && code != AND && code != XOR
9146 && code != PLUS && code != MINUS)
9152 /* If either operand is a primitive we can't do anything, so get out
9154 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9157 lhs = expand_compound_operation (lhs);
9158 rhs = expand_compound_operation (rhs);
9159 inner_code = GET_CODE (lhs);
9160 if (inner_code != GET_CODE (rhs))
9163 /* See if the inner and outer operations distribute. */
9170 /* These all distribute except over PLUS. */
9171 if (code == PLUS || code == MINUS)
9176 if (code != PLUS && code != MINUS)
9181 /* This is also a multiply, so it distributes over everything. */
9185 /* Non-paradoxical SUBREGs distributes over all operations,
9186 provided the inner modes and byte offsets are the same, this
9187 is an extraction of a low-order part, we don't convert an fp
9188 operation to int or vice versa, this is not a vector mode,
9189 and we would not be converting a single-word operation into a
9190 multi-word operation. The latter test is not required, but
9191 it prevents generating unneeded multi-word operations. Some
9192 of the previous tests are redundant given the latter test,
9193 but are retained because they are required for correctness.
9195 We produce the result slightly differently in this case. */
9197 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9198 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9199 || ! subreg_lowpart_p (lhs)
9200 || (GET_MODE_CLASS (GET_MODE (lhs))
9201 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9202 || (GET_MODE_SIZE (GET_MODE (lhs))
9203 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
9204 || VECTOR_MODE_P (GET_MODE (lhs))
9205 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9206 /* Result might need to be truncated. Don't change mode if
9207 explicit truncation is needed. */
9208 || !TRULY_NOOP_TRUNCATION
9209 (GET_MODE_BITSIZE (GET_MODE (x)),
9210 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
9213 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9214 SUBREG_REG (lhs), SUBREG_REG (rhs));
9215 return gen_lowpart (GET_MODE (x), tem);
9221 /* Set LHS and RHS to the inner operands (A and B in the example
9222 above) and set OTHER to the common operand (C in the example).
9223 There is only one way to do this unless the inner operation is
9225 if (COMMUTATIVE_ARITH_P (lhs)
9226 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9227 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9228 else if (COMMUTATIVE_ARITH_P (lhs)
9229 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9230 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9231 else if (COMMUTATIVE_ARITH_P (lhs)
9232 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9233 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9234 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9235 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9239 /* Form the new inner operation, seeing if it simplifies first. */
9240 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9242 /* There is one exception to the general way of distributing:
9243 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9244 if (code == XOR && inner_code == IOR)
9247 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9250 /* We may be able to continuing distributing the result, so call
9251 ourselves recursively on the inner operation before forming the
9252 outer operation, which we return. */
9253 return simplify_gen_binary (inner_code, GET_MODE (x),
9254 apply_distributive_law (tem), other);
9257 /* See if X is of the form (* (+ A B) C), and if so convert to
9258 (+ (* A C) (* B C)) and try to simplify.
9260 Most of the time, this results in no change. However, if some of
9261 the operands are the same or inverses of each other, simplifications
9264 For example, (and (ior A B) (not B)) can occur as the result of
9265 expanding a bit field assignment. When we apply the distributive
9266 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9267 which then simplifies to (and (A (not B))).
9269 Note that no checks happen on the validity of applying the inverse
9270 distributive law. This is pointless since we can do it in the
9271 few places where this routine is called.
9273 N is the index of the term that is decomposed (the arithmetic operation,
9274 i.e. (+ A B) in the first example above). !N is the index of the term that
9275 is distributed, i.e. of C in the first example above. */
9277 distribute_and_simplify_rtx (rtx x, int n)
9279 enum machine_mode mode;
9280 enum rtx_code outer_code, inner_code;
9281 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9283 /* Distributivity is not true for floating point as it can change the
9284 value. So we don't do it unless -funsafe-math-optimizations. */
9285 if (FLOAT_MODE_P (GET_MODE (x))
9286 && ! flag_unsafe_math_optimizations)
9289 decomposed = XEXP (x, n);
9290 if (!ARITHMETIC_P (decomposed))
9293 mode = GET_MODE (x);
9294 outer_code = GET_CODE (x);
9295 distributed = XEXP (x, !n);
9297 inner_code = GET_CODE (decomposed);
9298 inner_op0 = XEXP (decomposed, 0);
9299 inner_op1 = XEXP (decomposed, 1);
9301 /* Special case (and (xor B C) (not A)), which is equivalent to
9302 (xor (ior A B) (ior A C)) */
9303 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9305 distributed = XEXP (distributed, 0);
9311 /* Distribute the second term. */
9312 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9313 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9317 /* Distribute the first term. */
9318 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9319 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9322 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9324 if (GET_CODE (tmp) != outer_code
9325 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
9326 < rtx_cost (x, SET, optimize_this_for_speed_p))
9332 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9333 in MODE. Return an equivalent form, if different from (and VAROP
9334 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9337 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9338 unsigned HOST_WIDE_INT constop)
9340 unsigned HOST_WIDE_INT nonzero;
9341 unsigned HOST_WIDE_INT orig_constop;
9346 orig_constop = constop;
9347 if (GET_CODE (varop) == CLOBBER)
9350 /* Simplify VAROP knowing that we will be only looking at some of the
9353 Note by passing in CONSTOP, we guarantee that the bits not set in
9354 CONSTOP are not significant and will never be examined. We must
9355 ensure that is the case by explicitly masking out those bits
9356 before returning. */
9357 varop = force_to_mode (varop, mode, constop, 0);
9359 /* If VAROP is a CLOBBER, we will fail so return it. */
9360 if (GET_CODE (varop) == CLOBBER)
9363 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9364 to VAROP and return the new constant. */
9365 if (CONST_INT_P (varop))
9366 return gen_int_mode (INTVAL (varop) & constop, mode);
9368 /* See what bits may be nonzero in VAROP. Unlike the general case of
9369 a call to nonzero_bits, here we don't care about bits outside
9372 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9374 /* Turn off all bits in the constant that are known to already be zero.
9375 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9376 which is tested below. */
9380 /* If we don't have any bits left, return zero. */
9384 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9385 a power of two, we can replace this with an ASHIFT. */
9386 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9387 && (i = exact_log2 (constop)) >= 0)
9388 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9390 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9391 or XOR, then try to apply the distributive law. This may eliminate
9392 operations if either branch can be simplified because of the AND.
9393 It may also make some cases more complex, but those cases probably
9394 won't match a pattern either with or without this. */
9396 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9400 apply_distributive_law
9401 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9402 simplify_and_const_int (NULL_RTX,
9406 simplify_and_const_int (NULL_RTX,
9411 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9412 the AND and see if one of the operands simplifies to zero. If so, we
9413 may eliminate it. */
9415 if (GET_CODE (varop) == PLUS
9416 && exact_log2 (constop + 1) >= 0)
9420 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9421 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9422 if (o0 == const0_rtx)
9424 if (o1 == const0_rtx)
9428 /* Make a SUBREG if necessary. If we can't make it, fail. */
9429 varop = gen_lowpart (mode, varop);
9430 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9433 /* If we are only masking insignificant bits, return VAROP. */
9434 if (constop == nonzero)
9437 if (varop == orig_varop && constop == orig_constop)
9440 /* Otherwise, return an AND. */
9441 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9445 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9448 Return an equivalent form, if different from X. Otherwise, return X. If
9449 X is zero, we are to always construct the equivalent form. */
9452 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9453 unsigned HOST_WIDE_INT constop)
9455 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9460 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9461 gen_int_mode (constop, mode));
9462 if (GET_MODE (x) != mode)
9463 x = gen_lowpart (mode, x);
9467 /* Given a REG, X, compute which bits in X can be nonzero.
9468 We don't care about bits outside of those defined in MODE.
9470 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9471 a shift, AND, or zero_extract, we can do better. */
9474 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9475 const_rtx known_x ATTRIBUTE_UNUSED,
9476 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9477 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9478 unsigned HOST_WIDE_INT *nonzero)
9483 /* If X is a register whose nonzero bits value is current, use it.
9484 Otherwise, if X is a register whose value we can find, use that
9485 value. Otherwise, use the previously-computed global nonzero bits
9486 for this register. */
9488 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9489 if (rsp->last_set_value != 0
9490 && (rsp->last_set_mode == mode
9491 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9492 && GET_MODE_CLASS (mode) == MODE_INT))
9493 && ((rsp->last_set_label >= label_tick_ebb_start
9494 && rsp->last_set_label < label_tick)
9495 || (rsp->last_set_label == label_tick
9496 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9497 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9498 && REG_N_SETS (REGNO (x)) == 1
9500 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9502 *nonzero &= rsp->last_set_nonzero_bits;
9506 tem = get_last_value (x);
9510 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9511 /* If X is narrower than MODE and TEM is a non-negative
9512 constant that would appear negative in the mode of X,
9513 sign-extend it for use in reg_nonzero_bits because some
9514 machines (maybe most) will actually do the sign-extension
9515 and this is the conservative approach.
9517 ??? For 2.5, try to tighten up the MD files in this regard
9518 instead of this kludge. */
9520 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
9521 && CONST_INT_P (tem)
9523 && 0 != (UINTVAL (tem)
9524 & ((unsigned HOST_WIDE_INT) 1
9525 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
9526 tem = GEN_INT (UINTVAL (tem)
9527 | ((unsigned HOST_WIDE_INT) (-1)
9528 << GET_MODE_BITSIZE (GET_MODE (x))));
9532 else if (nonzero_sign_valid && rsp->nonzero_bits)
9534 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9536 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
9537 /* We don't know anything about the upper bits. */
9538 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9545 /* Return the number of bits at the high-order end of X that are known to
9546 be equal to the sign bit. X will be used in mode MODE; if MODE is
9547 VOIDmode, X will be used in its own mode. The returned value will always
9548 be between 1 and the number of bits in MODE. */
9551 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9552 const_rtx known_x ATTRIBUTE_UNUSED,
9553 enum machine_mode known_mode
9555 unsigned int known_ret ATTRIBUTE_UNUSED,
9556 unsigned int *result)
9561 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9562 if (rsp->last_set_value != 0
9563 && rsp->last_set_mode == mode
9564 && ((rsp->last_set_label >= label_tick_ebb_start
9565 && rsp->last_set_label < label_tick)
9566 || (rsp->last_set_label == label_tick
9567 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9568 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9569 && REG_N_SETS (REGNO (x)) == 1
9571 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9573 *result = rsp->last_set_sign_bit_copies;
9577 tem = get_last_value (x);
9581 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9582 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
9583 *result = rsp->sign_bit_copies;
9588 /* Return the number of "extended" bits there are in X, when interpreted
9589 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9590 unsigned quantities, this is the number of high-order zero bits.
9591 For signed quantities, this is the number of copies of the sign bit
9592 minus 1. In both case, this function returns the number of "spare"
9593 bits. For example, if two quantities for which this function returns
9594 at least 1 are added, the addition is known not to overflow.
9596 This function will always return 0 unless called during combine, which
9597 implies that it must be called from a define_split. */
9600 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9602 if (nonzero_sign_valid == 0)
9606 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9607 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
9608 - floor_log2 (nonzero_bits (x, mode)))
9610 : num_sign_bit_copies (x, mode) - 1);
9613 /* This function is called from `simplify_shift_const' to merge two
9614 outer operations. Specifically, we have already found that we need
9615 to perform operation *POP0 with constant *PCONST0 at the outermost
9616 position. We would now like to also perform OP1 with constant CONST1
9617 (with *POP0 being done last).
9619 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9620 the resulting operation. *PCOMP_P is set to 1 if we would need to
9621 complement the innermost operand, otherwise it is unchanged.
9623 MODE is the mode in which the operation will be done. No bits outside
9624 the width of this mode matter. It is assumed that the width of this mode
9625 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9627 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9628 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9629 result is simply *PCONST0.
9631 If the resulting operation cannot be expressed as one operation, we
9632 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9635 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9637 enum rtx_code op0 = *pop0;
9638 HOST_WIDE_INT const0 = *pconst0;
9640 const0 &= GET_MODE_MASK (mode);
9641 const1 &= GET_MODE_MASK (mode);
9643 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9647 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9650 if (op1 == UNKNOWN || op0 == SET)
9653 else if (op0 == UNKNOWN)
9654 op0 = op1, const0 = const1;
9656 else if (op0 == op1)
9680 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9681 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9684 /* If the two constants aren't the same, we can't do anything. The
9685 remaining six cases can all be done. */
9686 else if (const0 != const1)
9694 /* (a & b) | b == b */
9696 else /* op1 == XOR */
9697 /* (a ^ b) | b == a | b */
9703 /* (a & b) ^ b == (~a) & b */
9704 op0 = AND, *pcomp_p = 1;
9705 else /* op1 == IOR */
9706 /* (a | b) ^ b == a & ~b */
9707 op0 = AND, const0 = ~const0;
9712 /* (a | b) & b == b */
9714 else /* op1 == XOR */
9715 /* (a ^ b) & b) == (~a) & b */
9722 /* Check for NO-OP cases. */
9723 const0 &= GET_MODE_MASK (mode);
9725 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9727 else if (const0 == 0 && op0 == AND)
9729 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9735 /* ??? Slightly redundant with the above mask, but not entirely.
9736 Moving this above means we'd have to sign-extend the mode mask
9737 for the final test. */
9738 if (op0 != UNKNOWN && op0 != NEG)
9739 *pconst0 = trunc_int_for_mode (const0, mode);
9744 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9745 the shift in. The original shift operation CODE is performed on OP in
9746 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9747 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9748 result of the shift is subject to operation OUTER_CODE with operand
9751 static enum machine_mode
9752 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9753 enum machine_mode orig_mode, enum machine_mode mode,
9754 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9756 if (orig_mode == mode)
9758 gcc_assert (GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (orig_mode));
9760 /* In general we can't perform in wider mode for right shift and rotate. */
9764 /* We can still widen if the bits brought in from the left are identical
9765 to the sign bit of ORIG_MODE. */
9766 if (num_sign_bit_copies (op, mode)
9767 > (unsigned) (GET_MODE_BITSIZE (mode)
9768 - GET_MODE_BITSIZE (orig_mode)))
9773 /* Similarly here but with zero bits. */
9774 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9775 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9778 /* We can also widen if the bits brought in will be masked off. This
9779 operation is performed in ORIG_MODE. */
9780 if (outer_code == AND)
9782 int care_bits = low_bitmask_len (orig_mode, outer_const);
9785 && GET_MODE_BITSIZE (orig_mode) - care_bits >= count)
9801 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9802 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
9803 simplify it. Otherwise, return a simplified value.
9805 The shift is normally computed in the widest mode we find in VAROP, as
9806 long as it isn't a different number of words than RESULT_MODE. Exceptions
9807 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9810 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9811 rtx varop, int orig_count)
9813 enum rtx_code orig_code = code;
9814 rtx orig_varop = varop;
9816 enum machine_mode mode = result_mode;
9817 enum machine_mode shift_mode, tmode;
9818 unsigned int mode_words
9819 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9820 /* We form (outer_op (code varop count) (outer_const)). */
9821 enum rtx_code outer_op = UNKNOWN;
9822 HOST_WIDE_INT outer_const = 0;
9823 int complement_p = 0;
9826 /* Make sure and truncate the "natural" shift on the way in. We don't
9827 want to do this inside the loop as it makes it more difficult to
9829 if (SHIFT_COUNT_TRUNCATED)
9830 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9832 /* If we were given an invalid count, don't do anything except exactly
9833 what was requested. */
9835 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9840 /* Unless one of the branches of the `if' in this loop does a `continue',
9841 we will `break' the loop after the `if'. */
9845 /* If we have an operand of (clobber (const_int 0)), fail. */
9846 if (GET_CODE (varop) == CLOBBER)
9849 /* Convert ROTATERT to ROTATE. */
9850 if (code == ROTATERT)
9852 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9854 if (VECTOR_MODE_P (result_mode))
9855 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9857 count = bitsize - count;
9860 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9861 mode, outer_op, outer_const);
9863 /* Handle cases where the count is greater than the size of the mode
9864 minus 1. For ASHIFT, use the size minus one as the count (this can
9865 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9866 take the count modulo the size. For other shifts, the result is
9869 Since these shifts are being produced by the compiler by combining
9870 multiple operations, each of which are defined, we know what the
9871 result is supposed to be. */
9873 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9875 if (code == ASHIFTRT)
9876 count = GET_MODE_BITSIZE (shift_mode) - 1;
9877 else if (code == ROTATE || code == ROTATERT)
9878 count %= GET_MODE_BITSIZE (shift_mode);
9881 /* We can't simply return zero because there may be an
9889 /* If we discovered we had to complement VAROP, leave. Making a NOT
9890 here would cause an infinite loop. */
9894 /* An arithmetic right shift of a quantity known to be -1 or 0
9896 if (code == ASHIFTRT
9897 && (num_sign_bit_copies (varop, shift_mode)
9898 == GET_MODE_BITSIZE (shift_mode)))
9904 /* If we are doing an arithmetic right shift and discarding all but
9905 the sign bit copies, this is equivalent to doing a shift by the
9906 bitsize minus one. Convert it into that shift because it will often
9907 allow other simplifications. */
9909 if (code == ASHIFTRT
9910 && (count + num_sign_bit_copies (varop, shift_mode)
9911 >= GET_MODE_BITSIZE (shift_mode)))
9912 count = GET_MODE_BITSIZE (shift_mode) - 1;
9914 /* We simplify the tests below and elsewhere by converting
9915 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9916 `make_compound_operation' will convert it to an ASHIFTRT for
9917 those machines (such as VAX) that don't have an LSHIFTRT. */
9918 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9920 && ((nonzero_bits (varop, shift_mode)
9921 & ((unsigned HOST_WIDE_INT) 1
9922 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0))
9925 if (((code == LSHIFTRT
9926 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9927 && !(nonzero_bits (varop, shift_mode) >> count))
9929 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9930 && !((nonzero_bits (varop, shift_mode) << count)
9931 & GET_MODE_MASK (shift_mode))))
9932 && !side_effects_p (varop))
9935 switch (GET_CODE (varop))
9941 new_rtx = expand_compound_operation (varop);
9942 if (new_rtx != varop)
9950 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9951 minus the width of a smaller mode, we can do this with a
9952 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9953 if ((code == ASHIFTRT || code == LSHIFTRT)
9954 && ! mode_dependent_address_p (XEXP (varop, 0))
9955 && ! MEM_VOLATILE_P (varop)
9956 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9957 MODE_INT, 1)) != BLKmode)
9959 new_rtx = adjust_address_nv (varop, tmode,
9960 BYTES_BIG_ENDIAN ? 0
9961 : count / BITS_PER_UNIT);
9963 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9964 : ZERO_EXTEND, mode, new_rtx);
9971 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9972 the same number of words as what we've seen so far. Then store
9973 the widest mode in MODE. */
9974 if (subreg_lowpart_p (varop)
9975 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9976 > GET_MODE_SIZE (GET_MODE (varop)))
9977 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9978 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9980 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
9981 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
9983 varop = SUBREG_REG (varop);
9984 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9985 mode = GET_MODE (varop);
9991 /* Some machines use MULT instead of ASHIFT because MULT
9992 is cheaper. But it is still better on those machines to
9993 merge two shifts into one. */
9994 if (CONST_INT_P (XEXP (varop, 1))
9995 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
9998 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10000 GEN_INT (exact_log2 (
10001 UINTVAL (XEXP (varop, 1)))));
10007 /* Similar, for when divides are cheaper. */
10008 if (CONST_INT_P (XEXP (varop, 1))
10009 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10012 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10014 GEN_INT (exact_log2 (
10015 UINTVAL (XEXP (varop, 1)))));
10021 /* If we are extracting just the sign bit of an arithmetic
10022 right shift, that shift is not needed. However, the sign
10023 bit of a wider mode may be different from what would be
10024 interpreted as the sign bit in a narrower mode, so, if
10025 the result is narrower, don't discard the shift. */
10026 if (code == LSHIFTRT
10027 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10028 && (GET_MODE_BITSIZE (result_mode)
10029 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10031 varop = XEXP (varop, 0);
10035 /* ... fall through ... */
10040 /* Here we have two nested shifts. The result is usually the
10041 AND of a new shift with a mask. We compute the result below. */
10042 if (CONST_INT_P (XEXP (varop, 1))
10043 && INTVAL (XEXP (varop, 1)) >= 0
10044 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
10045 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10046 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10047 && !VECTOR_MODE_P (result_mode))
10049 enum rtx_code first_code = GET_CODE (varop);
10050 unsigned int first_count = INTVAL (XEXP (varop, 1));
10051 unsigned HOST_WIDE_INT mask;
10054 /* We have one common special case. We can't do any merging if
10055 the inner code is an ASHIFTRT of a smaller mode. However, if
10056 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10057 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10058 we can convert it to
10059 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
10060 This simplifies certain SIGN_EXTEND operations. */
10061 if (code == ASHIFT && first_code == ASHIFTRT
10062 && count == (GET_MODE_BITSIZE (result_mode)
10063 - GET_MODE_BITSIZE (GET_MODE (varop))))
10065 /* C3 has the low-order C1 bits zero. */
10067 mask = GET_MODE_MASK (mode)
10068 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10070 varop = simplify_and_const_int (NULL_RTX, result_mode,
10071 XEXP (varop, 0), mask);
10072 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10074 count = first_count;
10079 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10080 than C1 high-order bits equal to the sign bit, we can convert
10081 this to either an ASHIFT or an ASHIFTRT depending on the
10084 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10086 if (code == ASHIFTRT && first_code == ASHIFT
10087 && GET_MODE (varop) == shift_mode
10088 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10091 varop = XEXP (varop, 0);
10092 count -= first_count;
10102 /* There are some cases we can't do. If CODE is ASHIFTRT,
10103 we can only do this if FIRST_CODE is also ASHIFTRT.
10105 We can't do the case when CODE is ROTATE and FIRST_CODE is
10108 If the mode of this shift is not the mode of the outer shift,
10109 we can't do this if either shift is a right shift or ROTATE.
10111 Finally, we can't do any of these if the mode is too wide
10112 unless the codes are the same.
10114 Handle the case where the shift codes are the same
10117 if (code == first_code)
10119 if (GET_MODE (varop) != result_mode
10120 && (code == ASHIFTRT || code == LSHIFTRT
10121 || code == ROTATE))
10124 count += first_count;
10125 varop = XEXP (varop, 0);
10129 if (code == ASHIFTRT
10130 || (code == ROTATE && first_code == ASHIFTRT)
10131 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
10132 || (GET_MODE (varop) != result_mode
10133 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10134 || first_code == ROTATE
10135 || code == ROTATE)))
10138 /* To compute the mask to apply after the shift, shift the
10139 nonzero bits of the inner shift the same way the
10140 outer shift will. */
10142 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10145 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10148 /* Give up if we can't compute an outer operation to use. */
10150 || !CONST_INT_P (mask_rtx)
10151 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10153 result_mode, &complement_p))
10156 /* If the shifts are in the same direction, we add the
10157 counts. Otherwise, we subtract them. */
10158 if ((code == ASHIFTRT || code == LSHIFTRT)
10159 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10160 count += first_count;
10162 count -= first_count;
10164 /* If COUNT is positive, the new shift is usually CODE,
10165 except for the two exceptions below, in which case it is
10166 FIRST_CODE. If the count is negative, FIRST_CODE should
10169 && ((first_code == ROTATE && code == ASHIFT)
10170 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10172 else if (count < 0)
10173 code = first_code, count = -count;
10175 varop = XEXP (varop, 0);
10179 /* If we have (A << B << C) for any shift, we can convert this to
10180 (A << C << B). This wins if A is a constant. Only try this if
10181 B is not a constant. */
10183 else if (GET_CODE (varop) == code
10184 && CONST_INT_P (XEXP (varop, 0))
10185 && !CONST_INT_P (XEXP (varop, 1)))
10187 rtx new_rtx = simplify_const_binary_operation (code, mode,
10190 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10197 if (VECTOR_MODE_P (mode))
10200 /* Make this fit the case below. */
10201 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10202 GEN_INT (GET_MODE_MASK (mode)));
10208 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10209 with C the size of VAROP - 1 and the shift is logical if
10210 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10211 we have an (le X 0) operation. If we have an arithmetic shift
10212 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10213 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10215 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10216 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10217 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10218 && (code == LSHIFTRT || code == ASHIFTRT)
10219 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10220 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10223 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10226 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10227 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10232 /* If we have (shift (logical)), move the logical to the outside
10233 to allow it to possibly combine with another logical and the
10234 shift to combine with another shift. This also canonicalizes to
10235 what a ZERO_EXTRACT looks like. Also, some machines have
10236 (and (shift)) insns. */
10238 if (CONST_INT_P (XEXP (varop, 1))
10239 /* We can't do this if we have (ashiftrt (xor)) and the
10240 constant has its sign bit set in shift_mode. */
10241 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10242 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10244 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10246 GEN_INT (count))) != 0
10247 && CONST_INT_P (new_rtx)
10248 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10249 INTVAL (new_rtx), result_mode, &complement_p))
10251 varop = XEXP (varop, 0);
10255 /* If we can't do that, try to simplify the shift in each arm of the
10256 logical expression, make a new logical expression, and apply
10257 the inverse distributive law. This also can't be done
10258 for some (ashiftrt (xor)). */
10259 if (CONST_INT_P (XEXP (varop, 1))
10260 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10261 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10264 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10265 XEXP (varop, 0), count);
10266 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10267 XEXP (varop, 1), count);
10269 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10271 varop = apply_distributive_law (varop);
10279 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10280 says that the sign bit can be tested, FOO has mode MODE, C is
10281 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
10282 that may be nonzero. */
10283 if (code == LSHIFTRT
10284 && XEXP (varop, 1) == const0_rtx
10285 && GET_MODE (XEXP (varop, 0)) == result_mode
10286 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10287 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10288 && STORE_FLAG_VALUE == -1
10289 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10290 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10293 varop = XEXP (varop, 0);
10300 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10301 than the number of bits in the mode is equivalent to A. */
10302 if (code == LSHIFTRT
10303 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10304 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10306 varop = XEXP (varop, 0);
10311 /* NEG commutes with ASHIFT since it is multiplication. Move the
10312 NEG outside to allow shifts to combine. */
10314 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10317 varop = XEXP (varop, 0);
10323 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10324 is one less than the number of bits in the mode is
10325 equivalent to (xor A 1). */
10326 if (code == LSHIFTRT
10327 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10328 && XEXP (varop, 1) == constm1_rtx
10329 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10330 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10334 varop = XEXP (varop, 0);
10338 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10339 that might be nonzero in BAR are those being shifted out and those
10340 bits are known zero in FOO, we can replace the PLUS with FOO.
10341 Similarly in the other operand order. This code occurs when
10342 we are computing the size of a variable-size array. */
10344 if ((code == ASHIFTRT || code == LSHIFTRT)
10345 && count < HOST_BITS_PER_WIDE_INT
10346 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10347 && (nonzero_bits (XEXP (varop, 1), result_mode)
10348 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10350 varop = XEXP (varop, 0);
10353 else if ((code == ASHIFTRT || code == LSHIFTRT)
10354 && count < HOST_BITS_PER_WIDE_INT
10355 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
10356 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10358 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10359 & nonzero_bits (XEXP (varop, 1),
10362 varop = XEXP (varop, 1);
10366 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10368 && CONST_INT_P (XEXP (varop, 1))
10369 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10371 GEN_INT (count))) != 0
10372 && CONST_INT_P (new_rtx)
10373 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10374 INTVAL (new_rtx), result_mode, &complement_p))
10376 varop = XEXP (varop, 0);
10380 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10381 signbit', and attempt to change the PLUS to an XOR and move it to
10382 the outer operation as is done above in the AND/IOR/XOR case
10383 leg for shift(logical). See details in logical handling above
10384 for reasoning in doing so. */
10385 if (code == LSHIFTRT
10386 && CONST_INT_P (XEXP (varop, 1))
10387 && mode_signbit_p (result_mode, XEXP (varop, 1))
10388 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10390 GEN_INT (count))) != 0
10391 && CONST_INT_P (new_rtx)
10392 && merge_outer_ops (&outer_op, &outer_const, XOR,
10393 INTVAL (new_rtx), result_mode, &complement_p))
10395 varop = XEXP (varop, 0);
10402 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10403 with C the size of VAROP - 1 and the shift is logical if
10404 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10405 we have a (gt X 0) operation. If the shift is arithmetic with
10406 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10407 we have a (neg (gt X 0)) operation. */
10409 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10410 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10411 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
10412 && (code == LSHIFTRT || code == ASHIFTRT)
10413 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10414 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10415 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10418 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10421 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10422 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10429 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10430 if the truncate does not affect the value. */
10431 if (code == LSHIFTRT
10432 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10433 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10434 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10435 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
10436 - GET_MODE_BITSIZE (GET_MODE (varop)))))
10438 rtx varop_inner = XEXP (varop, 0);
10441 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10442 XEXP (varop_inner, 0),
10444 (count + INTVAL (XEXP (varop_inner, 1))));
10445 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10458 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10459 outer_op, outer_const);
10461 /* We have now finished analyzing the shift. The result should be
10462 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10463 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10464 to the result of the shift. OUTER_CONST is the relevant constant,
10465 but we must turn off all bits turned off in the shift. */
10467 if (outer_op == UNKNOWN
10468 && orig_code == code && orig_count == count
10469 && varop == orig_varop
10470 && shift_mode == GET_MODE (varop))
10473 /* Make a SUBREG if necessary. If we can't make it, fail. */
10474 varop = gen_lowpart (shift_mode, varop);
10475 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10478 /* If we have an outer operation and we just made a shift, it is
10479 possible that we could have simplified the shift were it not
10480 for the outer operation. So try to do the simplification
10483 if (outer_op != UNKNOWN)
10484 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10489 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10491 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10492 turn off all the bits that the shift would have turned off. */
10493 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10494 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10495 GET_MODE_MASK (result_mode) >> orig_count);
10497 /* Do the remainder of the processing in RESULT_MODE. */
10498 x = gen_lowpart_or_truncate (result_mode, x);
10500 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10503 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10505 if (outer_op != UNKNOWN)
10507 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10508 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
10509 outer_const = trunc_int_for_mode (outer_const, result_mode);
10511 if (outer_op == AND)
10512 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10513 else if (outer_op == SET)
10515 /* This means that we have determined that the result is
10516 equivalent to a constant. This should be rare. */
10517 if (!side_effects_p (x))
10518 x = GEN_INT (outer_const);
10520 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10521 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10523 x = simplify_gen_binary (outer_op, result_mode, x,
10524 GEN_INT (outer_const));
10530 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10531 The result of the shift is RESULT_MODE. If we cannot simplify it,
10532 return X or, if it is NULL, synthesize the expression with
10533 simplify_gen_binary. Otherwise, return a simplified value.
10535 The shift is normally computed in the widest mode we find in VAROP, as
10536 long as it isn't a different number of words than RESULT_MODE. Exceptions
10537 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10540 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10541 rtx varop, int count)
10543 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10548 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10549 if (GET_MODE (x) != result_mode)
10550 x = gen_lowpart (result_mode, x);
10555 /* Like recog, but we receive the address of a pointer to a new pattern.
10556 We try to match the rtx that the pointer points to.
10557 If that fails, we may try to modify or replace the pattern,
10558 storing the replacement into the same pointer object.
10560 Modifications include deletion or addition of CLOBBERs.
10562 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10563 the CLOBBERs are placed.
10565 The value is the final insn code from the pattern ultimately matched,
10569 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10571 rtx pat = *pnewpat;
10572 int insn_code_number;
10573 int num_clobbers_to_add = 0;
10576 rtx old_notes, old_pat;
10578 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10579 we use to indicate that something didn't match. If we find such a
10580 thing, force rejection. */
10581 if (GET_CODE (pat) == PARALLEL)
10582 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10583 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10584 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10587 old_pat = PATTERN (insn);
10588 old_notes = REG_NOTES (insn);
10589 PATTERN (insn) = pat;
10590 REG_NOTES (insn) = 0;
10592 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10593 if (dump_file && (dump_flags & TDF_DETAILS))
10595 if (insn_code_number < 0)
10596 fputs ("Failed to match this instruction:\n", dump_file);
10598 fputs ("Successfully matched this instruction:\n", dump_file);
10599 print_rtl_single (dump_file, pat);
10602 /* If it isn't, there is the possibility that we previously had an insn
10603 that clobbered some register as a side effect, but the combined
10604 insn doesn't need to do that. So try once more without the clobbers
10605 unless this represents an ASM insn. */
10607 if (insn_code_number < 0 && ! check_asm_operands (pat)
10608 && GET_CODE (pat) == PARALLEL)
10612 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10613 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10616 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10620 SUBST_INT (XVECLEN (pat, 0), pos);
10623 pat = XVECEXP (pat, 0, 0);
10625 PATTERN (insn) = pat;
10626 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10627 if (dump_file && (dump_flags & TDF_DETAILS))
10629 if (insn_code_number < 0)
10630 fputs ("Failed to match this instruction:\n", dump_file);
10632 fputs ("Successfully matched this instruction:\n", dump_file);
10633 print_rtl_single (dump_file, pat);
10636 PATTERN (insn) = old_pat;
10637 REG_NOTES (insn) = old_notes;
10639 /* Recognize all noop sets, these will be killed by followup pass. */
10640 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10641 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10643 /* If we had any clobbers to add, make a new pattern than contains
10644 them. Then check to make sure that all of them are dead. */
10645 if (num_clobbers_to_add)
10647 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10648 rtvec_alloc (GET_CODE (pat) == PARALLEL
10649 ? (XVECLEN (pat, 0)
10650 + num_clobbers_to_add)
10651 : num_clobbers_to_add + 1));
10653 if (GET_CODE (pat) == PARALLEL)
10654 for (i = 0; i < XVECLEN (pat, 0); i++)
10655 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10657 XVECEXP (newpat, 0, 0) = pat;
10659 add_clobbers (newpat, insn_code_number);
10661 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10662 i < XVECLEN (newpat, 0); i++)
10664 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10665 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10667 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10669 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10670 notes = alloc_reg_note (REG_UNUSED,
10671 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10680 return insn_code_number;
10683 /* Like gen_lowpart_general but for use by combine. In combine it
10684 is not possible to create any new pseudoregs. However, it is
10685 safe to create invalid memory addresses, because combine will
10686 try to recognize them and all they will do is make the combine
10689 If for some reason this cannot do its job, an rtx
10690 (clobber (const_int 0)) is returned.
10691 An insn containing that will not be recognized. */
10694 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10696 enum machine_mode imode = GET_MODE (x);
10697 unsigned int osize = GET_MODE_SIZE (omode);
10698 unsigned int isize = GET_MODE_SIZE (imode);
10701 if (omode == imode)
10704 /* Return identity if this is a CONST or symbolic reference. */
10706 && (GET_CODE (x) == CONST
10707 || GET_CODE (x) == SYMBOL_REF
10708 || GET_CODE (x) == LABEL_REF))
10711 /* We can only support MODE being wider than a word if X is a
10712 constant integer or has a mode the same size. */
10713 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10714 && ! ((imode == VOIDmode
10715 && (CONST_INT_P (x)
10716 || GET_CODE (x) == CONST_DOUBLE))
10717 || isize == osize))
10720 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10721 won't know what to do. So we will strip off the SUBREG here and
10722 process normally. */
10723 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10725 x = SUBREG_REG (x);
10727 /* For use in case we fall down into the address adjustments
10728 further below, we need to adjust the known mode and size of
10729 x; imode and isize, since we just adjusted x. */
10730 imode = GET_MODE (x);
10732 if (imode == omode)
10735 isize = GET_MODE_SIZE (imode);
10738 result = gen_lowpart_common (omode, x);
10747 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10749 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10752 /* If we want to refer to something bigger than the original memref,
10753 generate a paradoxical subreg instead. That will force a reload
10754 of the original memref X. */
10756 return gen_rtx_SUBREG (omode, x, 0);
10758 if (WORDS_BIG_ENDIAN)
10759 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10761 /* Adjust the address so that the address-after-the-data is
10763 if (BYTES_BIG_ENDIAN)
10764 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10766 return adjust_address_nv (x, omode, offset);
10769 /* If X is a comparison operator, rewrite it in a new mode. This
10770 probably won't match, but may allow further simplifications. */
10771 else if (COMPARISON_P (x))
10772 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10774 /* If we couldn't simplify X any other way, just enclose it in a
10775 SUBREG. Normally, this SUBREG won't match, but some patterns may
10776 include an explicit SUBREG or we may simplify it further in combine. */
10782 offset = subreg_lowpart_offset (omode, imode);
10783 if (imode == VOIDmode)
10785 imode = int_mode_for_mode (omode);
10786 x = gen_lowpart_common (imode, x);
10790 res = simplify_gen_subreg (omode, x, imode, offset);
10796 return gen_rtx_CLOBBER (omode, const0_rtx);
10799 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10800 comparison code that will be tested.
10802 The result is a possibly different comparison code to use. *POP0 and
10803 *POP1 may be updated.
10805 It is possible that we might detect that a comparison is either always
10806 true or always false. However, we do not perform general constant
10807 folding in combine, so this knowledge isn't useful. Such tautologies
10808 should have been detected earlier. Hence we ignore all such cases. */
10810 static enum rtx_code
10811 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
10817 enum machine_mode mode, tmode;
10819 /* Try a few ways of applying the same transformation to both operands. */
10822 #ifndef WORD_REGISTER_OPERATIONS
10823 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10824 so check specially. */
10825 if (code != GTU && code != GEU && code != LTU && code != LEU
10826 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10827 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10828 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10829 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10830 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10831 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10832 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10833 && CONST_INT_P (XEXP (op0, 1))
10834 && XEXP (op0, 1) == XEXP (op1, 1)
10835 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10836 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10837 && (INTVAL (XEXP (op0, 1))
10838 == (GET_MODE_BITSIZE (GET_MODE (op0))
10839 - (GET_MODE_BITSIZE
10840 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10842 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10843 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10847 /* If both operands are the same constant shift, see if we can ignore the
10848 shift. We can if the shift is a rotate or if the bits shifted out of
10849 this shift are known to be zero for both inputs and if the type of
10850 comparison is compatible with the shift. */
10851 if (GET_CODE (op0) == GET_CODE (op1)
10852 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10853 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10854 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10855 && (code != GT && code != LT && code != GE && code != LE))
10856 || (GET_CODE (op0) == ASHIFTRT
10857 && (code != GTU && code != LTU
10858 && code != GEU && code != LEU)))
10859 && CONST_INT_P (XEXP (op0, 1))
10860 && INTVAL (XEXP (op0, 1)) >= 0
10861 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10862 && XEXP (op0, 1) == XEXP (op1, 1))
10864 enum machine_mode mode = GET_MODE (op0);
10865 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10866 int shift_count = INTVAL (XEXP (op0, 1));
10868 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10869 mask &= (mask >> shift_count) << shift_count;
10870 else if (GET_CODE (op0) == ASHIFT)
10871 mask = (mask & (mask << shift_count)) >> shift_count;
10873 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10874 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10875 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10880 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10881 SUBREGs are of the same mode, and, in both cases, the AND would
10882 be redundant if the comparison was done in the narrower mode,
10883 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10884 and the operand's possibly nonzero bits are 0xffffff01; in that case
10885 if we only care about QImode, we don't need the AND). This case
10886 occurs if the output mode of an scc insn is not SImode and
10887 STORE_FLAG_VALUE == 1 (e.g., the 386).
10889 Similarly, check for a case where the AND's are ZERO_EXTEND
10890 operations from some narrower mode even though a SUBREG is not
10893 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10894 && CONST_INT_P (XEXP (op0, 1))
10895 && CONST_INT_P (XEXP (op1, 1)))
10897 rtx inner_op0 = XEXP (op0, 0);
10898 rtx inner_op1 = XEXP (op1, 0);
10899 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10900 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10903 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10904 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10905 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10906 && (GET_MODE (SUBREG_REG (inner_op0))
10907 == GET_MODE (SUBREG_REG (inner_op1)))
10908 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10909 <= HOST_BITS_PER_WIDE_INT)
10910 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10911 GET_MODE (SUBREG_REG (inner_op0)))))
10912 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10913 GET_MODE (SUBREG_REG (inner_op1))))))
10915 op0 = SUBREG_REG (inner_op0);
10916 op1 = SUBREG_REG (inner_op1);
10918 /* The resulting comparison is always unsigned since we masked
10919 off the original sign bit. */
10920 code = unsigned_condition (code);
10926 for (tmode = GET_CLASS_NARROWEST_MODE
10927 (GET_MODE_CLASS (GET_MODE (op0)));
10928 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10929 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10931 op0 = gen_lowpart (tmode, inner_op0);
10932 op1 = gen_lowpart (tmode, inner_op1);
10933 code = unsigned_condition (code);
10942 /* If both operands are NOT, we can strip off the outer operation
10943 and adjust the comparison code for swapped operands; similarly for
10944 NEG, except that this must be an equality comparison. */
10945 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10946 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10947 && (code == EQ || code == NE)))
10948 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10954 /* If the first operand is a constant, swap the operands and adjust the
10955 comparison code appropriately, but don't do this if the second operand
10956 is already a constant integer. */
10957 if (swap_commutative_operands_p (op0, op1))
10959 tem = op0, op0 = op1, op1 = tem;
10960 code = swap_condition (code);
10963 /* We now enter a loop during which we will try to simplify the comparison.
10964 For the most part, we only are concerned with comparisons with zero,
10965 but some things may really be comparisons with zero but not start
10966 out looking that way. */
10968 while (CONST_INT_P (op1))
10970 enum machine_mode mode = GET_MODE (op0);
10971 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10972 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10973 int equality_comparison_p;
10974 int sign_bit_comparison_p;
10975 int unsigned_comparison_p;
10976 HOST_WIDE_INT const_op;
10978 /* We only want to handle integral modes. This catches VOIDmode,
10979 CCmode, and the floating-point modes. An exception is that we
10980 can handle VOIDmode if OP0 is a COMPARE or a comparison
10983 if (GET_MODE_CLASS (mode) != MODE_INT
10984 && ! (mode == VOIDmode
10985 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10988 /* Get the constant we are comparing against and turn off all bits
10989 not on in our mode. */
10990 const_op = INTVAL (op1);
10991 if (mode != VOIDmode)
10992 const_op = trunc_int_for_mode (const_op, mode);
10993 op1 = GEN_INT (const_op);
10995 /* If we are comparing against a constant power of two and the value
10996 being compared can only have that single bit nonzero (e.g., it was
10997 `and'ed with that bit), we can replace this with a comparison
11000 && (code == EQ || code == NE || code == GE || code == GEU
11001 || code == LT || code == LTU)
11002 && mode_width <= HOST_BITS_PER_WIDE_INT
11003 && exact_log2 (const_op) >= 0
11004 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
11006 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11007 op1 = const0_rtx, const_op = 0;
11010 /* Similarly, if we are comparing a value known to be either -1 or
11011 0 with -1, change it to the opposite comparison against zero. */
11014 && (code == EQ || code == NE || code == GT || code == LE
11015 || code == GEU || code == LTU)
11016 && num_sign_bit_copies (op0, mode) == mode_width)
11018 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11019 op1 = const0_rtx, const_op = 0;
11022 /* Do some canonicalizations based on the comparison code. We prefer
11023 comparisons against zero and then prefer equality comparisons.
11024 If we can reduce the size of a constant, we will do that too. */
11029 /* < C is equivalent to <= (C - 1) */
11033 op1 = GEN_INT (const_op);
11035 /* ... fall through to LE case below. */
11041 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11045 op1 = GEN_INT (const_op);
11049 /* If we are doing a <= 0 comparison on a value known to have
11050 a zero sign bit, we can replace this with == 0. */
11051 else if (const_op == 0
11052 && mode_width <= HOST_BITS_PER_WIDE_INT
11053 && (nonzero_bits (op0, mode)
11054 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11060 /* >= C is equivalent to > (C - 1). */
11064 op1 = GEN_INT (const_op);
11066 /* ... fall through to GT below. */
11072 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11076 op1 = GEN_INT (const_op);
11080 /* If we are doing a > 0 comparison on a value known to have
11081 a zero sign bit, we can replace this with != 0. */
11082 else if (const_op == 0
11083 && mode_width <= HOST_BITS_PER_WIDE_INT
11084 && (nonzero_bits (op0, mode)
11085 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11091 /* < C is equivalent to <= (C - 1). */
11095 op1 = GEN_INT (const_op);
11097 /* ... fall through ... */
11100 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11101 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11102 && (unsigned HOST_WIDE_INT) const_op
11103 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11105 const_op = 0, op1 = const0_rtx;
11113 /* unsigned <= 0 is equivalent to == 0 */
11117 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11118 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11119 && (unsigned HOST_WIDE_INT) const_op
11120 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11122 const_op = 0, op1 = const0_rtx;
11128 /* >= C is equivalent to > (C - 1). */
11132 op1 = GEN_INT (const_op);
11134 /* ... fall through ... */
11137 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11138 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11139 && (unsigned HOST_WIDE_INT) const_op
11140 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11142 const_op = 0, op1 = const0_rtx;
11150 /* unsigned > 0 is equivalent to != 0 */
11154 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11155 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11156 && (unsigned HOST_WIDE_INT) const_op
11157 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11159 const_op = 0, op1 = const0_rtx;
11168 /* Compute some predicates to simplify code below. */
11170 equality_comparison_p = (code == EQ || code == NE);
11171 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11172 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11175 /* If this is a sign bit comparison and we can do arithmetic in
11176 MODE, say that we will only be needing the sign bit of OP0. */
11177 if (sign_bit_comparison_p
11178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11179 op0 = force_to_mode (op0, mode,
11180 (unsigned HOST_WIDE_INT) 1
11181 << (GET_MODE_BITSIZE (mode) - 1),
11184 /* Now try cases based on the opcode of OP0. If none of the cases
11185 does a "continue", we exit this loop immediately after the
11188 switch (GET_CODE (op0))
11191 /* If we are extracting a single bit from a variable position in
11192 a constant that has only a single bit set and are comparing it
11193 with zero, we can convert this into an equality comparison
11194 between the position and the location of the single bit. */
11195 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11196 have already reduced the shift count modulo the word size. */
11197 if (!SHIFT_COUNT_TRUNCATED
11198 && CONST_INT_P (XEXP (op0, 0))
11199 && XEXP (op0, 1) == const1_rtx
11200 && equality_comparison_p && const_op == 0
11201 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11203 if (BITS_BIG_ENDIAN)
11205 enum machine_mode new_mode
11206 = mode_for_extraction (EP_extzv, 1);
11207 if (new_mode == MAX_MACHINE_MODE)
11208 i = BITS_PER_WORD - 1 - i;
11212 i = (GET_MODE_BITSIZE (mode) - 1 - i);
11216 op0 = XEXP (op0, 2);
11220 /* Result is nonzero iff shift count is equal to I. */
11221 code = reverse_condition (code);
11225 /* ... fall through ... */
11228 tem = expand_compound_operation (op0);
11237 /* If testing for equality, we can take the NOT of the constant. */
11238 if (equality_comparison_p
11239 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11241 op0 = XEXP (op0, 0);
11246 /* If just looking at the sign bit, reverse the sense of the
11248 if (sign_bit_comparison_p)
11250 op0 = XEXP (op0, 0);
11251 code = (code == GE ? LT : GE);
11257 /* If testing for equality, we can take the NEG of the constant. */
11258 if (equality_comparison_p
11259 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11261 op0 = XEXP (op0, 0);
11266 /* The remaining cases only apply to comparisons with zero. */
11270 /* When X is ABS or is known positive,
11271 (neg X) is < 0 if and only if X != 0. */
11273 if (sign_bit_comparison_p
11274 && (GET_CODE (XEXP (op0, 0)) == ABS
11275 || (mode_width <= HOST_BITS_PER_WIDE_INT
11276 && (nonzero_bits (XEXP (op0, 0), mode)
11277 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11280 op0 = XEXP (op0, 0);
11281 code = (code == LT ? NE : EQ);
11285 /* If we have NEG of something whose two high-order bits are the
11286 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11287 if (num_sign_bit_copies (op0, mode) >= 2)
11289 op0 = XEXP (op0, 0);
11290 code = swap_condition (code);
11296 /* If we are testing equality and our count is a constant, we
11297 can perform the inverse operation on our RHS. */
11298 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11299 && (tem = simplify_binary_operation (ROTATERT, mode,
11300 op1, XEXP (op0, 1))) != 0)
11302 op0 = XEXP (op0, 0);
11307 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11308 a particular bit. Convert it to an AND of a constant of that
11309 bit. This will be converted into a ZERO_EXTRACT. */
11310 if (const_op == 0 && sign_bit_comparison_p
11311 && CONST_INT_P (XEXP (op0, 1))
11312 && mode_width <= HOST_BITS_PER_WIDE_INT)
11314 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11315 ((unsigned HOST_WIDE_INT) 1
11317 - INTVAL (XEXP (op0, 1)))));
11318 code = (code == LT ? NE : EQ);
11322 /* Fall through. */
11325 /* ABS is ignorable inside an equality comparison with zero. */
11326 if (const_op == 0 && equality_comparison_p)
11328 op0 = XEXP (op0, 0);
11334 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11335 (compare FOO CONST) if CONST fits in FOO's mode and we
11336 are either testing inequality or have an unsigned
11337 comparison with ZERO_EXTEND or a signed comparison with
11338 SIGN_EXTEND. But don't do it if we don't have a compare
11339 insn of the given mode, since we'd have to revert it
11340 later on, and then we wouldn't know whether to sign- or
11342 mode = GET_MODE (XEXP (op0, 0));
11343 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11344 && ! unsigned_comparison_p
11345 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11346 && ((unsigned HOST_WIDE_INT) const_op
11347 < (((unsigned HOST_WIDE_INT) 1
11348 << (GET_MODE_BITSIZE (mode) - 1))))
11349 && have_insn_for (COMPARE, mode))
11351 op0 = XEXP (op0, 0);
11357 /* Check for the case where we are comparing A - C1 with C2, that is
11359 (subreg:MODE (plus (A) (-C1))) op (C2)
11361 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11362 comparison in the wider mode. One of the following two conditions
11363 must be true in order for this to be valid:
11365 1. The mode extension results in the same bit pattern being added
11366 on both sides and the comparison is equality or unsigned. As
11367 C2 has been truncated to fit in MODE, the pattern can only be
11370 2. The mode extension results in the sign bit being copied on
11373 The difficulty here is that we have predicates for A but not for
11374 (A - C1) so we need to check that C1 is within proper bounds so
11375 as to perturbate A as little as possible. */
11377 if (mode_width <= HOST_BITS_PER_WIDE_INT
11378 && subreg_lowpart_p (op0)
11379 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
11380 && GET_CODE (SUBREG_REG (op0)) == PLUS
11381 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11383 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11384 rtx a = XEXP (SUBREG_REG (op0), 0);
11385 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11388 && (unsigned HOST_WIDE_INT) c1
11389 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11390 && (equality_comparison_p || unsigned_comparison_p)
11391 /* (A - C1) zero-extends if it is positive and sign-extends
11392 if it is negative, C2 both zero- and sign-extends. */
11393 && ((0 == (nonzero_bits (a, inner_mode)
11394 & ~GET_MODE_MASK (mode))
11396 /* (A - C1) sign-extends if it is positive and 1-extends
11397 if it is negative, C2 both sign- and 1-extends. */
11398 || (num_sign_bit_copies (a, inner_mode)
11399 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11402 || ((unsigned HOST_WIDE_INT) c1
11403 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11404 /* (A - C1) always sign-extends, like C2. */
11405 && num_sign_bit_copies (a, inner_mode)
11406 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
11407 - (mode_width - 1))))
11409 op0 = SUBREG_REG (op0);
11414 /* If the inner mode is narrower and we are extracting the low part,
11415 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11416 if (subreg_lowpart_p (op0)
11417 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
11418 /* Fall through */ ;
11422 /* ... fall through ... */
11425 mode = GET_MODE (XEXP (op0, 0));
11426 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11427 && (unsigned_comparison_p || equality_comparison_p)
11428 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11429 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
11430 && have_insn_for (COMPARE, mode))
11432 op0 = XEXP (op0, 0);
11438 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11439 this for equality comparisons due to pathological cases involving
11441 if (equality_comparison_p
11442 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11443 op1, XEXP (op0, 1))))
11445 op0 = XEXP (op0, 0);
11450 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11451 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11452 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11454 op0 = XEXP (XEXP (op0, 0), 0);
11455 code = (code == LT ? EQ : NE);
11461 /* We used to optimize signed comparisons against zero, but that
11462 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11463 arrive here as equality comparisons, or (GEU, LTU) are
11464 optimized away. No need to special-case them. */
11466 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11467 (eq B (minus A C)), whichever simplifies. We can only do
11468 this for equality comparisons due to pathological cases involving
11470 if (equality_comparison_p
11471 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11472 XEXP (op0, 1), op1)))
11474 op0 = XEXP (op0, 0);
11479 if (equality_comparison_p
11480 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11481 XEXP (op0, 0), op1)))
11483 op0 = XEXP (op0, 1);
11488 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11489 of bits in X minus 1, is one iff X > 0. */
11490 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11491 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11492 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11493 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11495 op0 = XEXP (op0, 1);
11496 code = (code == GE ? LE : GT);
11502 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11503 if C is zero or B is a constant. */
11504 if (equality_comparison_p
11505 && 0 != (tem = simplify_binary_operation (XOR, mode,
11506 XEXP (op0, 1), op1)))
11508 op0 = XEXP (op0, 0);
11515 case UNEQ: case LTGT:
11516 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11517 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11518 case UNORDERED: case ORDERED:
11519 /* We can't do anything if OP0 is a condition code value, rather
11520 than an actual data value. */
11522 || CC0_P (XEXP (op0, 0))
11523 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11526 /* Get the two operands being compared. */
11527 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11528 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11530 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11532 /* Check for the cases where we simply want the result of the
11533 earlier test or the opposite of that result. */
11534 if (code == NE || code == EQ
11535 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
11536 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11537 && (STORE_FLAG_VALUE
11538 & (((unsigned HOST_WIDE_INT) 1
11539 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
11540 && (code == LT || code == GE)))
11542 enum rtx_code new_code;
11543 if (code == LT || code == NE)
11544 new_code = GET_CODE (op0);
11546 new_code = reversed_comparison_code (op0, NULL);
11548 if (new_code != UNKNOWN)
11559 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11561 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11562 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11563 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11565 op0 = XEXP (op0, 1);
11566 code = (code == GE ? GT : LE);
11572 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11573 will be converted to a ZERO_EXTRACT later. */
11574 if (const_op == 0 && equality_comparison_p
11575 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11576 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11578 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11579 XEXP (XEXP (op0, 0), 1));
11580 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11584 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11585 zero and X is a comparison and C1 and C2 describe only bits set
11586 in STORE_FLAG_VALUE, we can compare with X. */
11587 if (const_op == 0 && equality_comparison_p
11588 && mode_width <= HOST_BITS_PER_WIDE_INT
11589 && CONST_INT_P (XEXP (op0, 1))
11590 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11591 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11592 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11593 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11595 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11596 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11597 if ((~STORE_FLAG_VALUE & mask) == 0
11598 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11599 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11600 && COMPARISON_P (tem))))
11602 op0 = XEXP (XEXP (op0, 0), 0);
11607 /* If we are doing an equality comparison of an AND of a bit equal
11608 to the sign bit, replace this with a LT or GE comparison of
11609 the underlying value. */
11610 if (equality_comparison_p
11612 && CONST_INT_P (XEXP (op0, 1))
11613 && mode_width <= HOST_BITS_PER_WIDE_INT
11614 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11615 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11617 op0 = XEXP (op0, 0);
11618 code = (code == EQ ? GE : LT);
11622 /* If this AND operation is really a ZERO_EXTEND from a narrower
11623 mode, the constant fits within that mode, and this is either an
11624 equality or unsigned comparison, try to do this comparison in
11629 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11630 -> (ne:DI (reg:SI 4) (const_int 0))
11632 unless TRULY_NOOP_TRUNCATION allows it or the register is
11633 known to hold a value of the required mode the
11634 transformation is invalid. */
11635 if ((equality_comparison_p || unsigned_comparison_p)
11636 && CONST_INT_P (XEXP (op0, 1))
11637 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11638 & GET_MODE_MASK (mode))
11640 && const_op >> i == 0
11641 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11642 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
11643 GET_MODE_BITSIZE (GET_MODE (op0)))
11644 || (REG_P (XEXP (op0, 0))
11645 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11647 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11651 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11652 fits in both M1 and M2 and the SUBREG is either paradoxical
11653 or represents the low part, permute the SUBREG and the AND
11655 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11657 unsigned HOST_WIDE_INT c1;
11658 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11659 /* Require an integral mode, to avoid creating something like
11661 if (SCALAR_INT_MODE_P (tmode)
11662 /* It is unsafe to commute the AND into the SUBREG if the
11663 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11664 not defined. As originally written the upper bits
11665 have a defined value due to the AND operation.
11666 However, if we commute the AND inside the SUBREG then
11667 they no longer have defined values and the meaning of
11668 the code has been changed. */
11670 #ifdef WORD_REGISTER_OPERATIONS
11671 || (mode_width > GET_MODE_BITSIZE (tmode)
11672 && mode_width <= BITS_PER_WORD)
11674 || (mode_width <= GET_MODE_BITSIZE (tmode)
11675 && subreg_lowpart_p (XEXP (op0, 0))))
11676 && CONST_INT_P (XEXP (op0, 1))
11677 && mode_width <= HOST_BITS_PER_WIDE_INT
11678 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
11679 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11680 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11682 && c1 != GET_MODE_MASK (tmode))
11684 op0 = simplify_gen_binary (AND, tmode,
11685 SUBREG_REG (XEXP (op0, 0)),
11686 gen_int_mode (c1, tmode));
11687 op0 = gen_lowpart (mode, op0);
11692 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11693 if (const_op == 0 && equality_comparison_p
11694 && XEXP (op0, 1) == const1_rtx
11695 && GET_CODE (XEXP (op0, 0)) == NOT)
11697 op0 = simplify_and_const_int (NULL_RTX, mode,
11698 XEXP (XEXP (op0, 0), 0), 1);
11699 code = (code == NE ? EQ : NE);
11703 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11704 (eq (and (lshiftrt X) 1) 0).
11705 Also handle the case where (not X) is expressed using xor. */
11706 if (const_op == 0 && equality_comparison_p
11707 && XEXP (op0, 1) == const1_rtx
11708 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11710 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11711 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11713 if (GET_CODE (shift_op) == NOT
11714 || (GET_CODE (shift_op) == XOR
11715 && CONST_INT_P (XEXP (shift_op, 1))
11716 && CONST_INT_P (shift_count)
11717 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
11718 && (UINTVAL (XEXP (shift_op, 1))
11719 == (unsigned HOST_WIDE_INT) 1
11720 << INTVAL (shift_count))))
11723 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11724 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11725 code = (code == NE ? EQ : NE);
11732 /* If we have (compare (ashift FOO N) (const_int C)) and
11733 the high order N bits of FOO (N+1 if an inequality comparison)
11734 are known to be zero, we can do this by comparing FOO with C
11735 shifted right N bits so long as the low-order N bits of C are
11737 if (CONST_INT_P (XEXP (op0, 1))
11738 && INTVAL (XEXP (op0, 1)) >= 0
11739 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11740 < HOST_BITS_PER_WIDE_INT)
11741 && (((unsigned HOST_WIDE_INT) const_op
11742 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11744 && mode_width <= HOST_BITS_PER_WIDE_INT
11745 && (nonzero_bits (XEXP (op0, 0), mode)
11746 & ~(mask >> (INTVAL (XEXP (op0, 1))
11747 + ! equality_comparison_p))) == 0)
11749 /* We must perform a logical shift, not an arithmetic one,
11750 as we want the top N bits of C to be zero. */
11751 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11753 temp >>= INTVAL (XEXP (op0, 1));
11754 op1 = gen_int_mode (temp, mode);
11755 op0 = XEXP (op0, 0);
11759 /* If we are doing a sign bit comparison, it means we are testing
11760 a particular bit. Convert it to the appropriate AND. */
11761 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11762 && mode_width <= HOST_BITS_PER_WIDE_INT)
11764 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11765 ((unsigned HOST_WIDE_INT) 1
11767 - INTVAL (XEXP (op0, 1)))));
11768 code = (code == LT ? NE : EQ);
11772 /* If this an equality comparison with zero and we are shifting
11773 the low bit to the sign bit, we can convert this to an AND of the
11775 if (const_op == 0 && equality_comparison_p
11776 && CONST_INT_P (XEXP (op0, 1))
11777 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11779 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11785 /* If this is an equality comparison with zero, we can do this
11786 as a logical shift, which might be much simpler. */
11787 if (equality_comparison_p && const_op == 0
11788 && CONST_INT_P (XEXP (op0, 1)))
11790 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11792 INTVAL (XEXP (op0, 1)));
11796 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11797 do the comparison in a narrower mode. */
11798 if (! unsigned_comparison_p
11799 && CONST_INT_P (XEXP (op0, 1))
11800 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11801 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11802 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11803 MODE_INT, 1)) != BLKmode
11804 && (((unsigned HOST_WIDE_INT) const_op
11805 + (GET_MODE_MASK (tmode) >> 1) + 1)
11806 <= GET_MODE_MASK (tmode)))
11808 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11812 /* Likewise if OP0 is a PLUS of a sign extension with a
11813 constant, which is usually represented with the PLUS
11814 between the shifts. */
11815 if (! unsigned_comparison_p
11816 && CONST_INT_P (XEXP (op0, 1))
11817 && GET_CODE (XEXP (op0, 0)) == PLUS
11818 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11819 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11820 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11821 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11822 MODE_INT, 1)) != BLKmode
11823 && (((unsigned HOST_WIDE_INT) const_op
11824 + (GET_MODE_MASK (tmode) >> 1) + 1)
11825 <= GET_MODE_MASK (tmode)))
11827 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11828 rtx add_const = XEXP (XEXP (op0, 0), 1);
11829 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11830 add_const, XEXP (op0, 1));
11832 op0 = simplify_gen_binary (PLUS, tmode,
11833 gen_lowpart (tmode, inner),
11838 /* ... fall through ... */
11840 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11841 the low order N bits of FOO are known to be zero, we can do this
11842 by comparing FOO with C shifted left N bits so long as no
11843 overflow occurs. Even if the low order N bits of FOO aren't known
11844 to be zero, if the comparison is >= or < we can use the same
11845 optimization and for > or <= by setting all the low
11846 order N bits in the comparison constant. */
11847 if (CONST_INT_P (XEXP (op0, 1))
11848 && INTVAL (XEXP (op0, 1)) > 0
11849 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11850 && mode_width <= HOST_BITS_PER_WIDE_INT
11851 && (((unsigned HOST_WIDE_INT) const_op
11852 + (GET_CODE (op0) != LSHIFTRT
11853 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11856 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11858 unsigned HOST_WIDE_INT low_bits
11859 = (nonzero_bits (XEXP (op0, 0), mode)
11860 & (((unsigned HOST_WIDE_INT) 1
11861 << INTVAL (XEXP (op0, 1))) - 1));
11862 if (low_bits == 0 || !equality_comparison_p)
11864 /* If the shift was logical, then we must make the condition
11866 if (GET_CODE (op0) == LSHIFTRT)
11867 code = unsigned_condition (code);
11869 const_op <<= INTVAL (XEXP (op0, 1));
11871 && (code == GT || code == GTU
11872 || code == LE || code == LEU))
11874 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11875 op1 = GEN_INT (const_op);
11876 op0 = XEXP (op0, 0);
11881 /* If we are using this shift to extract just the sign bit, we
11882 can replace this with an LT or GE comparison. */
11884 && (equality_comparison_p || sign_bit_comparison_p)
11885 && CONST_INT_P (XEXP (op0, 1))
11886 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11888 op0 = XEXP (op0, 0);
11889 code = (code == NE || code == GT ? LT : GE);
11901 /* Now make any compound operations involved in this comparison. Then,
11902 check for an outmost SUBREG on OP0 that is not doing anything or is
11903 paradoxical. The latter transformation must only be performed when
11904 it is known that the "extra" bits will be the same in op0 and op1 or
11905 that they don't matter. There are three cases to consider:
11907 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11908 care bits and we can assume they have any convenient value. So
11909 making the transformation is safe.
11911 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11912 In this case the upper bits of op0 are undefined. We should not make
11913 the simplification in that case as we do not know the contents of
11916 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11917 UNKNOWN. In that case we know those bits are zeros or ones. We must
11918 also be sure that they are the same as the upper bits of op1.
11920 We can never remove a SUBREG for a non-equality comparison because
11921 the sign bit is in a different place in the underlying object. */
11923 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11924 op1 = make_compound_operation (op1, SET);
11926 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11927 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11928 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11929 && (code == NE || code == EQ))
11931 if (GET_MODE_SIZE (GET_MODE (op0))
11932 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11934 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11936 if (REG_P (SUBREG_REG (op0)))
11938 op0 = SUBREG_REG (op0);
11939 op1 = gen_lowpart (GET_MODE (op0), op1);
11942 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11943 <= HOST_BITS_PER_WIDE_INT)
11944 && (nonzero_bits (SUBREG_REG (op0),
11945 GET_MODE (SUBREG_REG (op0)))
11946 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11948 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11950 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11951 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11952 op0 = SUBREG_REG (op0), op1 = tem;
11956 /* We now do the opposite procedure: Some machines don't have compare
11957 insns in all modes. If OP0's mode is an integer mode smaller than a
11958 word and we can't do a compare in that mode, see if there is a larger
11959 mode for which we can do the compare. There are a number of cases in
11960 which we can use the wider mode. */
11962 mode = GET_MODE (op0);
11963 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11964 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11965 && ! have_insn_for (COMPARE, mode))
11966 for (tmode = GET_MODE_WIDER_MODE (mode);
11968 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11969 tmode = GET_MODE_WIDER_MODE (tmode))
11970 if (have_insn_for (COMPARE, tmode))
11974 /* If this is a test for negative, we can make an explicit
11975 test of the sign bit. Test this first so we can use
11976 a paradoxical subreg to extend OP0. */
11978 if (op1 == const0_rtx && (code == LT || code == GE)
11979 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11981 op0 = simplify_gen_binary (AND, tmode,
11982 gen_lowpart (tmode, op0),
11983 GEN_INT ((unsigned HOST_WIDE_INT) 1
11984 << (GET_MODE_BITSIZE (mode)
11986 code = (code == LT) ? NE : EQ;
11990 /* If the only nonzero bits in OP0 and OP1 are those in the
11991 narrower mode and this is an equality or unsigned comparison,
11992 we can use the wider mode. Similarly for sign-extended
11993 values, in which case it is true for all comparisons. */
11994 zero_extended = ((code == EQ || code == NE
11995 || code == GEU || code == GTU
11996 || code == LEU || code == LTU)
11997 && (nonzero_bits (op0, tmode)
11998 & ~GET_MODE_MASK (mode)) == 0
11999 && ((CONST_INT_P (op1)
12000 || (nonzero_bits (op1, tmode)
12001 & ~GET_MODE_MASK (mode)) == 0)));
12004 || ((num_sign_bit_copies (op0, tmode)
12005 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12006 - GET_MODE_BITSIZE (mode)))
12007 && (num_sign_bit_copies (op1, tmode)
12008 > (unsigned int) (GET_MODE_BITSIZE (tmode)
12009 - GET_MODE_BITSIZE (mode)))))
12011 /* If OP0 is an AND and we don't have an AND in MODE either,
12012 make a new AND in the proper mode. */
12013 if (GET_CODE (op0) == AND
12014 && !have_insn_for (AND, mode))
12015 op0 = simplify_gen_binary (AND, tmode,
12016 gen_lowpart (tmode,
12018 gen_lowpart (tmode,
12024 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12025 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12029 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12030 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12037 #ifdef CANONICALIZE_COMPARISON
12038 /* If this machine only supports a subset of valid comparisons, see if we
12039 can convert an unsupported one into a supported one. */
12040 CANONICALIZE_COMPARISON (code, op0, op1);
12049 /* Utility function for record_value_for_reg. Count number of
12054 enum rtx_code code = GET_CODE (x);
12058 if (GET_RTX_CLASS (code) == '2'
12059 || GET_RTX_CLASS (code) == 'c')
12061 rtx x0 = XEXP (x, 0);
12062 rtx x1 = XEXP (x, 1);
12065 return 1 + 2 * count_rtxs (x0);
12067 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12068 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12069 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12070 return 2 + 2 * count_rtxs (x0)
12071 + count_rtxs (x == XEXP (x1, 0)
12072 ? XEXP (x1, 1) : XEXP (x1, 0));
12074 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12075 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12076 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12077 return 2 + 2 * count_rtxs (x1)
12078 + count_rtxs (x == XEXP (x0, 0)
12079 ? XEXP (x0, 1) : XEXP (x0, 0));
12082 fmt = GET_RTX_FORMAT (code);
12083 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12085 ret += count_rtxs (XEXP (x, i));
12086 else if (fmt[i] == 'E')
12087 for (j = 0; j < XVECLEN (x, i); j++)
12088 ret += count_rtxs (XVECEXP (x, i, j));
12093 /* Utility function for following routine. Called when X is part of a value
12094 being stored into last_set_value. Sets last_set_table_tick
12095 for each register mentioned. Similar to mention_regs in cse.c */
12098 update_table_tick (rtx x)
12100 enum rtx_code code = GET_CODE (x);
12101 const char *fmt = GET_RTX_FORMAT (code);
12106 unsigned int regno = REGNO (x);
12107 unsigned int endregno = END_REGNO (x);
12110 for (r = regno; r < endregno; r++)
12112 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12113 rsp->last_set_table_tick = label_tick;
12119 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12122 /* Check for identical subexpressions. If x contains
12123 identical subexpression we only have to traverse one of
12125 if (i == 0 && ARITHMETIC_P (x))
12127 /* Note that at this point x1 has already been
12129 rtx x0 = XEXP (x, 0);
12130 rtx x1 = XEXP (x, 1);
12132 /* If x0 and x1 are identical then there is no need to
12137 /* If x0 is identical to a subexpression of x1 then while
12138 processing x1, x0 has already been processed. Thus we
12139 are done with x. */
12140 if (ARITHMETIC_P (x1)
12141 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12144 /* If x1 is identical to a subexpression of x0 then we
12145 still have to process the rest of x0. */
12146 if (ARITHMETIC_P (x0)
12147 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12149 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12154 update_table_tick (XEXP (x, i));
12156 else if (fmt[i] == 'E')
12157 for (j = 0; j < XVECLEN (x, i); j++)
12158 update_table_tick (XVECEXP (x, i, j));
12161 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12162 are saying that the register is clobbered and we no longer know its
12163 value. If INSN is zero, don't update reg_stat[].last_set; this is
12164 only permitted with VALUE also zero and is used to invalidate the
12168 record_value_for_reg (rtx reg, rtx insn, rtx value)
12170 unsigned int regno = REGNO (reg);
12171 unsigned int endregno = END_REGNO (reg);
12173 reg_stat_type *rsp;
12175 /* If VALUE contains REG and we have a previous value for REG, substitute
12176 the previous value. */
12177 if (value && insn && reg_overlap_mentioned_p (reg, value))
12181 /* Set things up so get_last_value is allowed to see anything set up to
12183 subst_low_luid = DF_INSN_LUID (insn);
12184 tem = get_last_value (reg);
12186 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12187 it isn't going to be useful and will take a lot of time to process,
12188 so just use the CLOBBER. */
12192 if (ARITHMETIC_P (tem)
12193 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12194 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12195 tem = XEXP (tem, 0);
12196 else if (count_occurrences (value, reg, 1) >= 2)
12198 /* If there are two or more occurrences of REG in VALUE,
12199 prevent the value from growing too much. */
12200 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12201 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12204 value = replace_rtx (copy_rtx (value), reg, tem);
12208 /* For each register modified, show we don't know its value, that
12209 we don't know about its bitwise content, that its value has been
12210 updated, and that we don't know the location of the death of the
12212 for (i = regno; i < endregno; i++)
12214 rsp = VEC_index (reg_stat_type, reg_stat, i);
12217 rsp->last_set = insn;
12219 rsp->last_set_value = 0;
12220 rsp->last_set_mode = VOIDmode;
12221 rsp->last_set_nonzero_bits = 0;
12222 rsp->last_set_sign_bit_copies = 0;
12223 rsp->last_death = 0;
12224 rsp->truncated_to_mode = VOIDmode;
12227 /* Mark registers that are being referenced in this value. */
12229 update_table_tick (value);
12231 /* Now update the status of each register being set.
12232 If someone is using this register in this block, set this register
12233 to invalid since we will get confused between the two lives in this
12234 basic block. This makes using this register always invalid. In cse, we
12235 scan the table to invalidate all entries using this register, but this
12236 is too much work for us. */
12238 for (i = regno; i < endregno; i++)
12240 rsp = VEC_index (reg_stat_type, reg_stat, i);
12241 rsp->last_set_label = label_tick;
12243 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12244 rsp->last_set_invalid = 1;
12246 rsp->last_set_invalid = 0;
12249 /* The value being assigned might refer to X (like in "x++;"). In that
12250 case, we must replace it with (clobber (const_int 0)) to prevent
12252 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12253 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12255 value = copy_rtx (value);
12256 if (!get_last_value_validate (&value, insn, label_tick, 1))
12260 /* For the main register being modified, update the value, the mode, the
12261 nonzero bits, and the number of sign bit copies. */
12263 rsp->last_set_value = value;
12267 enum machine_mode mode = GET_MODE (reg);
12268 subst_low_luid = DF_INSN_LUID (insn);
12269 rsp->last_set_mode = mode;
12270 if (GET_MODE_CLASS (mode) == MODE_INT
12271 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
12272 mode = nonzero_bits_mode;
12273 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12274 rsp->last_set_sign_bit_copies
12275 = num_sign_bit_copies (value, GET_MODE (reg));
12279 /* Called via note_stores from record_dead_and_set_regs to handle one
12280 SET or CLOBBER in an insn. DATA is the instruction in which the
12281 set is occurring. */
12284 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12286 rtx record_dead_insn = (rtx) data;
12288 if (GET_CODE (dest) == SUBREG)
12289 dest = SUBREG_REG (dest);
12291 if (!record_dead_insn)
12294 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12300 /* If we are setting the whole register, we know its value. Otherwise
12301 show that we don't know the value. We can handle SUBREG in
12303 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12304 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12305 else if (GET_CODE (setter) == SET
12306 && GET_CODE (SET_DEST (setter)) == SUBREG
12307 && SUBREG_REG (SET_DEST (setter)) == dest
12308 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
12309 && subreg_lowpart_p (SET_DEST (setter)))
12310 record_value_for_reg (dest, record_dead_insn,
12311 gen_lowpart (GET_MODE (dest),
12312 SET_SRC (setter)));
12314 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12316 else if (MEM_P (dest)
12317 /* Ignore pushes, they clobber nothing. */
12318 && ! push_operand (dest, GET_MODE (dest)))
12319 mem_last_set = DF_INSN_LUID (record_dead_insn);
12322 /* Update the records of when each REG was most recently set or killed
12323 for the things done by INSN. This is the last thing done in processing
12324 INSN in the combiner loop.
12326 We update reg_stat[], in particular fields last_set, last_set_value,
12327 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12328 last_death, and also the similar information mem_last_set (which insn
12329 most recently modified memory) and last_call_luid (which insn was the
12330 most recent subroutine call). */
12333 record_dead_and_set_regs (rtx insn)
12338 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12340 if (REG_NOTE_KIND (link) == REG_DEAD
12341 && REG_P (XEXP (link, 0)))
12343 unsigned int regno = REGNO (XEXP (link, 0));
12344 unsigned int endregno = END_REGNO (XEXP (link, 0));
12346 for (i = regno; i < endregno; i++)
12348 reg_stat_type *rsp;
12350 rsp = VEC_index (reg_stat_type, reg_stat, i);
12351 rsp->last_death = insn;
12354 else if (REG_NOTE_KIND (link) == REG_INC)
12355 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12360 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12361 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12363 reg_stat_type *rsp;
12365 rsp = VEC_index (reg_stat_type, reg_stat, i);
12366 rsp->last_set_invalid = 1;
12367 rsp->last_set = insn;
12368 rsp->last_set_value = 0;
12369 rsp->last_set_mode = VOIDmode;
12370 rsp->last_set_nonzero_bits = 0;
12371 rsp->last_set_sign_bit_copies = 0;
12372 rsp->last_death = 0;
12373 rsp->truncated_to_mode = VOIDmode;
12376 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12378 /* We can't combine into a call pattern. Remember, though, that
12379 the return value register is set at this LUID. We could
12380 still replace a register with the return value from the
12381 wrong subroutine call! */
12382 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12385 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12388 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12389 register present in the SUBREG, so for each such SUBREG go back and
12390 adjust nonzero and sign bit information of the registers that are
12391 known to have some zero/sign bits set.
12393 This is needed because when combine blows the SUBREGs away, the
12394 information on zero/sign bits is lost and further combines can be
12395 missed because of that. */
12398 record_promoted_value (rtx insn, rtx subreg)
12401 unsigned int regno = REGNO (SUBREG_REG (subreg));
12402 enum machine_mode mode = GET_MODE (subreg);
12404 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
12407 for (links = LOG_LINKS (insn); links;)
12409 reg_stat_type *rsp;
12411 insn = XEXP (links, 0);
12412 set = single_set (insn);
12414 if (! set || !REG_P (SET_DEST (set))
12415 || REGNO (SET_DEST (set)) != regno
12416 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12418 links = XEXP (links, 1);
12422 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12423 if (rsp->last_set == insn)
12425 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12426 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12429 if (REG_P (SET_SRC (set)))
12431 regno = REGNO (SET_SRC (set));
12432 links = LOG_LINKS (insn);
12439 /* Check if X, a register, is known to contain a value already
12440 truncated to MODE. In this case we can use a subreg to refer to
12441 the truncated value even though in the generic case we would need
12442 an explicit truncation. */
12445 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12447 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12448 enum machine_mode truncated = rsp->truncated_to_mode;
12451 || rsp->truncation_label < label_tick_ebb_start)
12453 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12455 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
12456 GET_MODE_BITSIZE (truncated)))
12461 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12462 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12463 might be able to turn a truncate into a subreg using this information.
12464 Return -1 if traversing *P is complete or 0 otherwise. */
12467 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12470 enum machine_mode truncated_mode;
12471 reg_stat_type *rsp;
12473 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12475 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12476 truncated_mode = GET_MODE (x);
12478 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12481 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
12482 GET_MODE_BITSIZE (original_mode)))
12485 x = SUBREG_REG (x);
12487 /* ??? For hard-regs we now record everything. We might be able to
12488 optimize this using last_set_mode. */
12489 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12490 truncated_mode = GET_MODE (x);
12494 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12495 if (rsp->truncated_to_mode == 0
12496 || rsp->truncation_label < label_tick_ebb_start
12497 || (GET_MODE_SIZE (truncated_mode)
12498 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12500 rsp->truncated_to_mode = truncated_mode;
12501 rsp->truncation_label = label_tick;
12507 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12508 the modes they are used in. This can help truning TRUNCATEs into
12512 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12514 for_each_rtx (x, record_truncated_value, NULL);
12517 /* Scan X for promoted SUBREGs. For each one found,
12518 note what it implies to the registers used in it. */
12521 check_promoted_subreg (rtx insn, rtx x)
12523 if (GET_CODE (x) == SUBREG
12524 && SUBREG_PROMOTED_VAR_P (x)
12525 && REG_P (SUBREG_REG (x)))
12526 record_promoted_value (insn, x);
12529 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12532 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12536 check_promoted_subreg (insn, XEXP (x, i));
12540 if (XVEC (x, i) != 0)
12541 for (j = 0; j < XVECLEN (x, i); j++)
12542 check_promoted_subreg (insn, XVECEXP (x, i, j));
12548 /* Verify that all the registers and memory references mentioned in *LOC are
12549 still valid. *LOC was part of a value set in INSN when label_tick was
12550 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12551 the invalid references with (clobber (const_int 0)) and return 1. This
12552 replacement is useful because we often can get useful information about
12553 the form of a value (e.g., if it was produced by a shift that always
12554 produces -1 or 0) even though we don't know exactly what registers it
12555 was produced from. */
12558 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12561 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12562 int len = GET_RTX_LENGTH (GET_CODE (x));
12567 unsigned int regno = REGNO (x);
12568 unsigned int endregno = END_REGNO (x);
12571 for (j = regno; j < endregno; j++)
12573 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12574 if (rsp->last_set_invalid
12575 /* If this is a pseudo-register that was only set once and not
12576 live at the beginning of the function, it is always valid. */
12577 || (! (regno >= FIRST_PSEUDO_REGISTER
12578 && REG_N_SETS (regno) == 1
12579 && (!REGNO_REG_SET_P
12580 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12581 && rsp->last_set_label > tick))
12584 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12591 /* If this is a memory reference, make sure that there were no stores after
12592 it that might have clobbered the value. We don't have alias info, so we
12593 assume any store invalidates it. Moreover, we only have local UIDs, so
12594 we also assume that there were stores in the intervening basic blocks. */
12595 else if (MEM_P (x) && !MEM_READONLY_P (x)
12596 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12599 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12603 for (i = 0; i < len; i++)
12607 /* Check for identical subexpressions. If x contains
12608 identical subexpression we only have to traverse one of
12610 if (i == 1 && ARITHMETIC_P (x))
12612 /* Note that at this point x0 has already been checked
12613 and found valid. */
12614 rtx x0 = XEXP (x, 0);
12615 rtx x1 = XEXP (x, 1);
12617 /* If x0 and x1 are identical then x is also valid. */
12621 /* If x1 is identical to a subexpression of x0 then
12622 while checking x0, x1 has already been checked. Thus
12623 it is valid and so as x. */
12624 if (ARITHMETIC_P (x0)
12625 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12628 /* If x0 is identical to a subexpression of x1 then x is
12629 valid iff the rest of x1 is valid. */
12630 if (ARITHMETIC_P (x1)
12631 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12633 get_last_value_validate (&XEXP (x1,
12634 x0 == XEXP (x1, 0) ? 1 : 0),
12635 insn, tick, replace);
12638 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12642 else if (fmt[i] == 'E')
12643 for (j = 0; j < XVECLEN (x, i); j++)
12644 if (get_last_value_validate (&XVECEXP (x, i, j),
12645 insn, tick, replace) == 0)
12649 /* If we haven't found a reason for it to be invalid, it is valid. */
12653 /* Get the last value assigned to X, if known. Some registers
12654 in the value may be replaced with (clobber (const_int 0)) if their value
12655 is known longer known reliably. */
12658 get_last_value (const_rtx x)
12660 unsigned int regno;
12662 reg_stat_type *rsp;
12664 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12665 then convert it to the desired mode. If this is a paradoxical SUBREG,
12666 we cannot predict what values the "extra" bits might have. */
12667 if (GET_CODE (x) == SUBREG
12668 && subreg_lowpart_p (x)
12669 && (GET_MODE_SIZE (GET_MODE (x))
12670 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
12671 && (value = get_last_value (SUBREG_REG (x))) != 0)
12672 return gen_lowpart (GET_MODE (x), value);
12678 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12679 value = rsp->last_set_value;
12681 /* If we don't have a value, or if it isn't for this basic block and
12682 it's either a hard register, set more than once, or it's a live
12683 at the beginning of the function, return 0.
12685 Because if it's not live at the beginning of the function then the reg
12686 is always set before being used (is never used without being set).
12687 And, if it's set only once, and it's always set before use, then all
12688 uses must have the same last value, even if it's not from this basic
12692 || (rsp->last_set_label < label_tick_ebb_start
12693 && (regno < FIRST_PSEUDO_REGISTER
12694 || REG_N_SETS (regno) != 1
12696 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12699 /* If the value was set in a later insn than the ones we are processing,
12700 we can't use it even if the register was only set once. */
12701 if (rsp->last_set_label == label_tick
12702 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12705 /* If the value has all its registers valid, return it. */
12706 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12709 /* Otherwise, make a copy and replace any invalid register with
12710 (clobber (const_int 0)). If that fails for some reason, return 0. */
12712 value = copy_rtx (value);
12713 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12719 /* Return nonzero if expression X refers to a REG or to memory
12720 that is set in an instruction more recent than FROM_LUID. */
12723 use_crosses_set_p (const_rtx x, int from_luid)
12727 enum rtx_code code = GET_CODE (x);
12731 unsigned int regno = REGNO (x);
12732 unsigned endreg = END_REGNO (x);
12734 #ifdef PUSH_ROUNDING
12735 /* Don't allow uses of the stack pointer to be moved,
12736 because we don't know whether the move crosses a push insn. */
12737 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12740 for (; regno < endreg; regno++)
12742 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12744 && rsp->last_set_label == label_tick
12745 && DF_INSN_LUID (rsp->last_set) > from_luid)
12751 if (code == MEM && mem_last_set > from_luid)
12754 fmt = GET_RTX_FORMAT (code);
12756 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12761 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12762 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12765 else if (fmt[i] == 'e'
12766 && use_crosses_set_p (XEXP (x, i), from_luid))
12772 /* Define three variables used for communication between the following
12775 static unsigned int reg_dead_regno, reg_dead_endregno;
12776 static int reg_dead_flag;
12778 /* Function called via note_stores from reg_dead_at_p.
12780 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12781 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12784 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12786 unsigned int regno, endregno;
12791 regno = REGNO (dest);
12792 endregno = END_REGNO (dest);
12793 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12794 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12797 /* Return nonzero if REG is known to be dead at INSN.
12799 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12800 referencing REG, it is dead. If we hit a SET referencing REG, it is
12801 live. Otherwise, see if it is live or dead at the start of the basic
12802 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12803 must be assumed to be always live. */
12806 reg_dead_at_p (rtx reg, rtx insn)
12811 /* Set variables for reg_dead_at_p_1. */
12812 reg_dead_regno = REGNO (reg);
12813 reg_dead_endregno = END_REGNO (reg);
12817 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12818 we allow the machine description to decide whether use-and-clobber
12819 patterns are OK. */
12820 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12822 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12823 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12827 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12828 beginning of basic block. */
12829 block = BLOCK_FOR_INSN (insn);
12834 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12836 return reg_dead_flag == 1 ? 1 : 0;
12838 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12842 if (insn == BB_HEAD (block))
12845 insn = PREV_INSN (insn);
12848 /* Look at live-in sets for the basic block that we were in. */
12849 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12850 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12856 /* Note hard registers in X that are used. */
12859 mark_used_regs_combine (rtx x)
12861 RTX_CODE code = GET_CODE (x);
12862 unsigned int regno;
12875 case ADDR_DIFF_VEC:
12878 /* CC0 must die in the insn after it is set, so we don't need to take
12879 special note of it here. */
12885 /* If we are clobbering a MEM, mark any hard registers inside the
12886 address as used. */
12887 if (MEM_P (XEXP (x, 0)))
12888 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12893 /* A hard reg in a wide mode may really be multiple registers.
12894 If so, mark all of them just like the first. */
12895 if (regno < FIRST_PSEUDO_REGISTER)
12897 /* None of this applies to the stack, frame or arg pointers. */
12898 if (regno == STACK_POINTER_REGNUM
12899 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12900 || regno == HARD_FRAME_POINTER_REGNUM
12902 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12903 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12905 || regno == FRAME_POINTER_REGNUM)
12908 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12914 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12916 rtx testreg = SET_DEST (x);
12918 while (GET_CODE (testreg) == SUBREG
12919 || GET_CODE (testreg) == ZERO_EXTRACT
12920 || GET_CODE (testreg) == STRICT_LOW_PART)
12921 testreg = XEXP (testreg, 0);
12923 if (MEM_P (testreg))
12924 mark_used_regs_combine (XEXP (testreg, 0));
12926 mark_used_regs_combine (SET_SRC (x));
12934 /* Recursively scan the operands of this expression. */
12937 const char *fmt = GET_RTX_FORMAT (code);
12939 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12942 mark_used_regs_combine (XEXP (x, i));
12943 else if (fmt[i] == 'E')
12947 for (j = 0; j < XVECLEN (x, i); j++)
12948 mark_used_regs_combine (XVECEXP (x, i, j));
12954 /* Remove register number REGNO from the dead registers list of INSN.
12956 Return the note used to record the death, if there was one. */
12959 remove_death (unsigned int regno, rtx insn)
12961 rtx note = find_regno_note (insn, REG_DEAD, regno);
12964 remove_note (insn, note);
12969 /* For each register (hardware or pseudo) used within expression X, if its
12970 death is in an instruction with luid between FROM_LUID (inclusive) and
12971 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12972 list headed by PNOTES.
12974 That said, don't move registers killed by maybe_kill_insn.
12976 This is done when X is being merged by combination into TO_INSN. These
12977 notes will then be distributed as needed. */
12980 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12985 enum rtx_code code = GET_CODE (x);
12989 unsigned int regno = REGNO (x);
12990 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12992 /* Don't move the register if it gets killed in between from and to. */
12993 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12994 && ! reg_referenced_p (x, maybe_kill_insn))
12998 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12999 && DF_INSN_LUID (where_dead) >= from_luid
13000 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13002 rtx note = remove_death (regno, where_dead);
13004 /* It is possible for the call above to return 0. This can occur
13005 when last_death points to I2 or I1 that we combined with.
13006 In that case make a new note.
13008 We must also check for the case where X is a hard register
13009 and NOTE is a death note for a range of hard registers
13010 including X. In that case, we must put REG_DEAD notes for
13011 the remaining registers in place of NOTE. */
13013 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13014 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13015 > GET_MODE_SIZE (GET_MODE (x))))
13017 unsigned int deadregno = REGNO (XEXP (note, 0));
13018 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13019 unsigned int ourend = END_HARD_REGNO (x);
13022 for (i = deadregno; i < deadend; i++)
13023 if (i < regno || i >= ourend)
13024 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13027 /* If we didn't find any note, or if we found a REG_DEAD note that
13028 covers only part of the given reg, and we have a multi-reg hard
13029 register, then to be safe we must check for REG_DEAD notes
13030 for each register other than the first. They could have
13031 their own REG_DEAD notes lying around. */
13032 else if ((note == 0
13034 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13035 < GET_MODE_SIZE (GET_MODE (x)))))
13036 && regno < FIRST_PSEUDO_REGISTER
13037 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13039 unsigned int ourend = END_HARD_REGNO (x);
13040 unsigned int i, offset;
13044 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13048 for (i = regno + offset; i < ourend; i++)
13049 move_deaths (regno_reg_rtx[i],
13050 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13053 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13055 XEXP (note, 1) = *pnotes;
13059 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13065 else if (GET_CODE (x) == SET)
13067 rtx dest = SET_DEST (x);
13069 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13071 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13072 that accesses one word of a multi-word item, some
13073 piece of everything register in the expression is used by
13074 this insn, so remove any old death. */
13075 /* ??? So why do we test for equality of the sizes? */
13077 if (GET_CODE (dest) == ZERO_EXTRACT
13078 || GET_CODE (dest) == STRICT_LOW_PART
13079 || (GET_CODE (dest) == SUBREG
13080 && (((GET_MODE_SIZE (GET_MODE (dest))
13081 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13082 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13083 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13085 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13089 /* If this is some other SUBREG, we know it replaces the entire
13090 value, so use that as the destination. */
13091 if (GET_CODE (dest) == SUBREG)
13092 dest = SUBREG_REG (dest);
13094 /* If this is a MEM, adjust deaths of anything used in the address.
13095 For a REG (the only other possibility), the entire value is
13096 being replaced so the old value is not used in this insn. */
13099 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13104 else if (GET_CODE (x) == CLOBBER)
13107 len = GET_RTX_LENGTH (code);
13108 fmt = GET_RTX_FORMAT (code);
13110 for (i = 0; i < len; i++)
13115 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13116 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13119 else if (fmt[i] == 'e')
13120 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13124 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13125 pattern of an insn. X must be a REG. */
13128 reg_bitfield_target_p (rtx x, rtx body)
13132 if (GET_CODE (body) == SET)
13134 rtx dest = SET_DEST (body);
13136 unsigned int regno, tregno, endregno, endtregno;
13138 if (GET_CODE (dest) == ZERO_EXTRACT)
13139 target = XEXP (dest, 0);
13140 else if (GET_CODE (dest) == STRICT_LOW_PART)
13141 target = SUBREG_REG (XEXP (dest, 0));
13145 if (GET_CODE (target) == SUBREG)
13146 target = SUBREG_REG (target);
13148 if (!REG_P (target))
13151 tregno = REGNO (target), regno = REGNO (x);
13152 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13153 return target == x;
13155 endtregno = end_hard_regno (GET_MODE (target), tregno);
13156 endregno = end_hard_regno (GET_MODE (x), regno);
13158 return endregno > tregno && regno < endtregno;
13161 else if (GET_CODE (body) == PARALLEL)
13162 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13163 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13169 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13170 as appropriate. I3 and I2 are the insns resulting from the combination
13171 insns including FROM (I2 may be zero).
13173 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13174 not need REG_DEAD notes because they are being substituted for. This
13175 saves searching in the most common cases.
13177 Each note in the list is either ignored or placed on some insns, depending
13178 on the type of note. */
13181 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13182 rtx elim_i1, rtx elim_i0)
13184 rtx note, next_note;
13187 for (note = notes; note; note = next_note)
13189 rtx place = 0, place2 = 0;
13191 next_note = XEXP (note, 1);
13192 switch (REG_NOTE_KIND (note))
13196 /* Doesn't matter much where we put this, as long as it's somewhere.
13197 It is preferable to keep these notes on branches, which is most
13198 likely to be i3. */
13202 case REG_NON_LOCAL_GOTO:
13207 gcc_assert (i2 && JUMP_P (i2));
13212 case REG_EH_REGION:
13213 /* These notes must remain with the call or trapping instruction. */
13216 else if (i2 && CALL_P (i2))
13220 gcc_assert (cfun->can_throw_non_call_exceptions);
13221 if (may_trap_p (i3))
13223 else if (i2 && may_trap_p (i2))
13225 /* ??? Otherwise assume we've combined things such that we
13226 can now prove that the instructions can't trap. Drop the
13227 note in this case. */
13233 /* These notes must remain with the call. It should not be
13234 possible for both I2 and I3 to be a call. */
13239 gcc_assert (i2 && CALL_P (i2));
13245 /* Any clobbers for i3 may still exist, and so we must process
13246 REG_UNUSED notes from that insn.
13248 Any clobbers from i2 or i1 can only exist if they were added by
13249 recog_for_combine. In that case, recog_for_combine created the
13250 necessary REG_UNUSED notes. Trying to keep any original
13251 REG_UNUSED notes from these insns can cause incorrect output
13252 if it is for the same register as the original i3 dest.
13253 In that case, we will notice that the register is set in i3,
13254 and then add a REG_UNUSED note for the destination of i3, which
13255 is wrong. However, it is possible to have REG_UNUSED notes from
13256 i2 or i1 for register which were both used and clobbered, so
13257 we keep notes from i2 or i1 if they will turn into REG_DEAD
13260 /* If this register is set or clobbered in I3, put the note there
13261 unless there is one already. */
13262 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13264 if (from_insn != i3)
13267 if (! (REG_P (XEXP (note, 0))
13268 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13269 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13272 /* Otherwise, if this register is used by I3, then this register
13273 now dies here, so we must put a REG_DEAD note here unless there
13275 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13276 && ! (REG_P (XEXP (note, 0))
13277 ? find_regno_note (i3, REG_DEAD,
13278 REGNO (XEXP (note, 0)))
13279 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13281 PUT_REG_NOTE_KIND (note, REG_DEAD);
13289 /* These notes say something about results of an insn. We can
13290 only support them if they used to be on I3 in which case they
13291 remain on I3. Otherwise they are ignored.
13293 If the note refers to an expression that is not a constant, we
13294 must also ignore the note since we cannot tell whether the
13295 equivalence is still true. It might be possible to do
13296 slightly better than this (we only have a problem if I2DEST
13297 or I1DEST is present in the expression), but it doesn't
13298 seem worth the trouble. */
13300 if (from_insn == i3
13301 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13306 /* These notes say something about how a register is used. They must
13307 be present on any use of the register in I2 or I3. */
13308 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13311 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13320 case REG_LABEL_TARGET:
13321 case REG_LABEL_OPERAND:
13322 /* This can show up in several ways -- either directly in the
13323 pattern, or hidden off in the constant pool with (or without?)
13324 a REG_EQUAL note. */
13325 /* ??? Ignore the without-reg_equal-note problem for now. */
13326 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13327 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13328 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13329 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13333 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13334 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13335 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13336 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13344 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13345 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13347 if (place && JUMP_P (place)
13348 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13349 && (JUMP_LABEL (place) == NULL
13350 || JUMP_LABEL (place) == XEXP (note, 0)))
13352 rtx label = JUMP_LABEL (place);
13355 JUMP_LABEL (place) = XEXP (note, 0);
13356 else if (LABEL_P (label))
13357 LABEL_NUSES (label)--;
13360 if (place2 && JUMP_P (place2)
13361 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13362 && (JUMP_LABEL (place2) == NULL
13363 || JUMP_LABEL (place2) == XEXP (note, 0)))
13365 rtx label = JUMP_LABEL (place2);
13368 JUMP_LABEL (place2) = XEXP (note, 0);
13369 else if (LABEL_P (label))
13370 LABEL_NUSES (label)--;
13376 /* This note says something about the value of a register prior
13377 to the execution of an insn. It is too much trouble to see
13378 if the note is still correct in all situations. It is better
13379 to simply delete it. */
13383 /* If we replaced the right hand side of FROM_INSN with a
13384 REG_EQUAL note, the original use of the dying register
13385 will not have been combined into I3 and I2. In such cases,
13386 FROM_INSN is guaranteed to be the first of the combined
13387 instructions, so we simply need to search back before
13388 FROM_INSN for the previous use or set of this register,
13389 then alter the notes there appropriately.
13391 If the register is used as an input in I3, it dies there.
13392 Similarly for I2, if it is nonzero and adjacent to I3.
13394 If the register is not used as an input in either I3 or I2
13395 and it is not one of the registers we were supposed to eliminate,
13396 there are two possibilities. We might have a non-adjacent I2
13397 or we might have somehow eliminated an additional register
13398 from a computation. For example, we might have had A & B where
13399 we discover that B will always be zero. In this case we will
13400 eliminate the reference to A.
13402 In both cases, we must search to see if we can find a previous
13403 use of A and put the death note there. */
13406 && from_insn == i2mod
13407 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13412 && CALL_P (from_insn)
13413 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13415 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13417 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13418 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13420 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13422 && reg_overlap_mentioned_p (XEXP (note, 0),
13424 || rtx_equal_p (XEXP (note, 0), elim_i1)
13425 || rtx_equal_p (XEXP (note, 0), elim_i0))
13432 basic_block bb = this_basic_block;
13434 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13436 if (!NONDEBUG_INSN_P (tem))
13438 if (tem == BB_HEAD (bb))
13443 /* If the register is being set at TEM, see if that is all
13444 TEM is doing. If so, delete TEM. Otherwise, make this
13445 into a REG_UNUSED note instead. Don't delete sets to
13446 global register vars. */
13447 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13448 || !global_regs[REGNO (XEXP (note, 0))])
13449 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13451 rtx set = single_set (tem);
13452 rtx inner_dest = 0;
13454 rtx cc0_setter = NULL_RTX;
13458 for (inner_dest = SET_DEST (set);
13459 (GET_CODE (inner_dest) == STRICT_LOW_PART
13460 || GET_CODE (inner_dest) == SUBREG
13461 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13462 inner_dest = XEXP (inner_dest, 0))
13465 /* Verify that it was the set, and not a clobber that
13466 modified the register.
13468 CC0 targets must be careful to maintain setter/user
13469 pairs. If we cannot delete the setter due to side
13470 effects, mark the user with an UNUSED note instead
13473 if (set != 0 && ! side_effects_p (SET_SRC (set))
13474 && rtx_equal_p (XEXP (note, 0), inner_dest)
13476 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13477 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13478 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13482 /* Move the notes and links of TEM elsewhere.
13483 This might delete other dead insns recursively.
13484 First set the pattern to something that won't use
13486 rtx old_notes = REG_NOTES (tem);
13488 PATTERN (tem) = pc_rtx;
13489 REG_NOTES (tem) = NULL;
13491 distribute_notes (old_notes, tem, tem, NULL_RTX,
13492 NULL_RTX, NULL_RTX, NULL_RTX);
13493 distribute_links (LOG_LINKS (tem));
13495 SET_INSN_DELETED (tem);
13500 /* Delete the setter too. */
13503 PATTERN (cc0_setter) = pc_rtx;
13504 old_notes = REG_NOTES (cc0_setter);
13505 REG_NOTES (cc0_setter) = NULL;
13507 distribute_notes (old_notes, cc0_setter,
13508 cc0_setter, NULL_RTX,
13509 NULL_RTX, NULL_RTX, NULL_RTX);
13510 distribute_links (LOG_LINKS (cc0_setter));
13512 SET_INSN_DELETED (cc0_setter);
13513 if (cc0_setter == i2)
13520 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13522 /* If there isn't already a REG_UNUSED note, put one
13523 here. Do not place a REG_DEAD note, even if
13524 the register is also used here; that would not
13525 match the algorithm used in lifetime analysis
13526 and can cause the consistency check in the
13527 scheduler to fail. */
13528 if (! find_regno_note (tem, REG_UNUSED,
13529 REGNO (XEXP (note, 0))))
13534 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13536 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13540 /* If we are doing a 3->2 combination, and we have a
13541 register which formerly died in i3 and was not used
13542 by i2, which now no longer dies in i3 and is used in
13543 i2 but does not die in i2, and place is between i2
13544 and i3, then we may need to move a link from place to
13546 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13548 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13549 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13551 rtx links = LOG_LINKS (place);
13552 LOG_LINKS (place) = 0;
13553 distribute_links (links);
13558 if (tem == BB_HEAD (bb))
13564 /* If the register is set or already dead at PLACE, we needn't do
13565 anything with this note if it is still a REG_DEAD note.
13566 We check here if it is set at all, not if is it totally replaced,
13567 which is what `dead_or_set_p' checks, so also check for it being
13570 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13572 unsigned int regno = REGNO (XEXP (note, 0));
13573 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13575 if (dead_or_set_p (place, XEXP (note, 0))
13576 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13578 /* Unless the register previously died in PLACE, clear
13579 last_death. [I no longer understand why this is
13581 if (rsp->last_death != place)
13582 rsp->last_death = 0;
13586 rsp->last_death = place;
13588 /* If this is a death note for a hard reg that is occupying
13589 multiple registers, ensure that we are still using all
13590 parts of the object. If we find a piece of the object
13591 that is unused, we must arrange for an appropriate REG_DEAD
13592 note to be added for it. However, we can't just emit a USE
13593 and tag the note to it, since the register might actually
13594 be dead; so we recourse, and the recursive call then finds
13595 the previous insn that used this register. */
13597 if (place && regno < FIRST_PSEUDO_REGISTER
13598 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13600 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13604 for (i = regno; i < endregno; i++)
13605 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13606 && ! find_regno_fusage (place, USE, i))
13607 || dead_or_set_regno_p (place, i))
13612 /* Put only REG_DEAD notes for pieces that are
13613 not already dead or set. */
13615 for (i = regno; i < endregno;
13616 i += hard_regno_nregs[i][reg_raw_mode[i]])
13618 rtx piece = regno_reg_rtx[i];
13619 basic_block bb = this_basic_block;
13621 if (! dead_or_set_p (place, piece)
13622 && ! reg_bitfield_target_p (piece,
13625 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13628 distribute_notes (new_note, place, place,
13629 NULL_RTX, NULL_RTX, NULL_RTX,
13632 else if (! refers_to_regno_p (i, i + 1,
13633 PATTERN (place), 0)
13634 && ! find_regno_fusage (place, USE, i))
13635 for (tem = PREV_INSN (place); ;
13636 tem = PREV_INSN (tem))
13638 if (!NONDEBUG_INSN_P (tem))
13640 if (tem == BB_HEAD (bb))
13644 if (dead_or_set_p (tem, piece)
13645 || reg_bitfield_target_p (piece,
13648 add_reg_note (tem, REG_UNUSED, piece);
13662 /* Any other notes should not be present at this point in the
13664 gcc_unreachable ();
13669 XEXP (note, 1) = REG_NOTES (place);
13670 REG_NOTES (place) = note;
13674 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13678 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13679 I3, I2, and I1 to new locations. This is also called to add a link
13680 pointing at I3 when I3's destination is changed. */
13683 distribute_links (rtx links)
13685 rtx link, next_link;
13687 for (link = links; link; link = next_link)
13693 next_link = XEXP (link, 1);
13695 /* If the insn that this link points to is a NOTE or isn't a single
13696 set, ignore it. In the latter case, it isn't clear what we
13697 can do other than ignore the link, since we can't tell which
13698 register it was for. Such links wouldn't be used by combine
13701 It is not possible for the destination of the target of the link to
13702 have been changed by combine. The only potential of this is if we
13703 replace I3, I2, and I1 by I3 and I2. But in that case the
13704 destination of I2 also remains unchanged. */
13706 if (NOTE_P (XEXP (link, 0))
13707 || (set = single_set (XEXP (link, 0))) == 0)
13710 reg = SET_DEST (set);
13711 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13712 || GET_CODE (reg) == STRICT_LOW_PART)
13713 reg = XEXP (reg, 0);
13715 /* A LOG_LINK is defined as being placed on the first insn that uses
13716 a register and points to the insn that sets the register. Start
13717 searching at the next insn after the target of the link and stop
13718 when we reach a set of the register or the end of the basic block.
13720 Note that this correctly handles the link that used to point from
13721 I3 to I2. Also note that not much searching is typically done here
13722 since most links don't point very far away. */
13724 for (insn = NEXT_INSN (XEXP (link, 0));
13725 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13726 || BB_HEAD (this_basic_block->next_bb) != insn));
13727 insn = NEXT_INSN (insn))
13728 if (DEBUG_INSN_P (insn))
13730 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13732 if (reg_referenced_p (reg, PATTERN (insn)))
13736 else if (CALL_P (insn)
13737 && find_reg_fusage (insn, USE, reg))
13742 else if (INSN_P (insn) && reg_set_p (reg, insn))
13745 /* If we found a place to put the link, place it there unless there
13746 is already a link to the same insn as LINK at that point. */
13752 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
13753 if (XEXP (link2, 0) == XEXP (link, 0))
13758 XEXP (link, 1) = LOG_LINKS (place);
13759 LOG_LINKS (place) = link;
13761 /* Set added_links_insn to the earliest insn we added a
13763 if (added_links_insn == 0
13764 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13765 added_links_insn = place;
13771 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13772 Check whether the expression pointer to by LOC is a register or
13773 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13774 Otherwise return zero. */
13777 unmentioned_reg_p_1 (rtx *loc, void *expr)
13782 && (REG_P (x) || MEM_P (x))
13783 && ! reg_mentioned_p (x, (rtx) expr))
13788 /* Check for any register or memory mentioned in EQUIV that is not
13789 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13790 of EXPR where some registers may have been replaced by constants. */
13793 unmentioned_reg_p (rtx equiv, rtx expr)
13795 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13799 dump_combine_stats (FILE *file)
13803 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13804 combine_attempts, combine_merges, combine_extras, combine_successes);
13808 dump_combine_total_stats (FILE *file)
13812 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13813 total_attempts, total_merges, total_extras, total_successes);
13817 gate_handle_combine (void)
13819 return (optimize > 0);
13822 /* Try combining insns through substitution. */
13823 static unsigned int
13824 rest_of_handle_combine (void)
13826 int rebuild_jump_labels_after_combine;
13828 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13829 df_note_add_problem ();
13832 regstat_init_n_sets_and_refs ();
13834 rebuild_jump_labels_after_combine
13835 = combine_instructions (get_insns (), max_reg_num ());
13837 /* Combining insns may have turned an indirect jump into a
13838 direct jump. Rebuild the JUMP_LABEL fields of jumping
13840 if (rebuild_jump_labels_after_combine)
13842 timevar_push (TV_JUMP);
13843 rebuild_jump_labels (get_insns ());
13845 timevar_pop (TV_JUMP);
13848 regstat_free_n_sets_and_refs ();
13852 struct rtl_opt_pass pass_combine =
13856 "combine", /* name */
13857 gate_handle_combine, /* gate */
13858 rest_of_handle_combine, /* execute */
13861 0, /* static_pass_number */
13862 TV_COMBINE, /* tv_id */
13863 PROP_cfglayout, /* properties_required */
13864 0, /* properties_provided */
13865 0, /* properties_destroyed */
13866 0, /* todo_flags_start */
13868 TODO_df_finish | TODO_verify_rtl_sharing |
13869 TODO_ggc_collect, /* todo_flags_finish */