1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
81 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
85 #include "insn-flags.h"
86 #include "insn-codes.h"
87 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* If byte loads either zero- or sign- extend, define BYTE_LOADS_EXTEND
97 for cases when we don't care which is true. Define LOAD_EXTEND to
98 be ZERO_EXTEND or SIGN_EXTEND, depending on which was defined. */
100 #ifdef BYTE_LOADS_ZERO_EXTEND
101 #define BYTE_LOADS_EXTEND
102 #define LOAD_EXTEND ZERO_EXTEND
105 #ifdef BYTE_LOADS_SIGN_EXTEND
106 #define BYTE_LOADS_EXTEND
107 #define LOAD_EXTEND SIGN_EXTEND
110 /* Number of attempts to combine instructions in this function. */
112 static int combine_attempts;
114 /* Number of attempts that got as far as substitution in this function. */
116 static int combine_merges;
118 /* Number of instructions combined with added SETs in this function. */
120 static int combine_extras;
122 /* Number of instructions combined in this function. */
124 static int combine_successes;
126 /* Totals over entire compilation. */
128 static int total_attempts, total_merges, total_extras, total_successes;
130 /* Vector mapping INSN_UIDs to cuids.
131 The cuids are like uids but increase monotonically always.
132 Combine always uses cuids so that it can compare them.
133 But actually renumbering the uids, which we used to do,
134 proves to be a bad idea because it makes it hard to compare
135 the dumps produced by earlier passes with those from later passes. */
137 static int *uid_cuid;
139 /* Get the cuid of an insn. */
141 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
143 /* Maximum register number, which is the size of the tables below. */
145 static int combine_max_regno;
147 /* Record last point of death of (hard or pseudo) register n. */
149 static rtx *reg_last_death;
151 /* Record last point of modification of (hard or pseudo) register n. */
153 static rtx *reg_last_set;
155 /* Record the cuid of the last insn that invalidated memory
156 (anything that writes memory, and subroutine calls, but not pushes). */
158 static int mem_last_set;
160 /* Record the cuid of the last CALL_INSN
161 so we can tell whether a potential combination crosses any calls. */
163 static int last_call_cuid;
165 /* When `subst' is called, this is the insn that is being modified
166 (by combining in a previous insn). The PATTERN of this insn
167 is still the old pattern partially modified and it should not be
168 looked at, but this may be used to examine the successors of the insn
169 to judge whether a simplification is valid. */
171 static rtx subst_insn;
173 /* This is the lowest CUID that `subst' is currently dealing with.
174 get_last_value will not return a value if the register was set at or
175 after this CUID. If not for this mechanism, we could get confused if
176 I2 or I1 in try_combine were an insn that used the old value of a register
177 to obtain a new value. In that case, we might erroneously get the
178 new value of the register when we wanted the old one. */
180 static int subst_low_cuid;
182 /* This is the value of undobuf.num_undo when we started processing this
183 substitution. This will prevent gen_rtx_combine from re-used a piece
184 from the previous expression. Doing so can produce circular rtl
187 static int previous_num_undos;
189 /* The next group of arrays allows the recording of the last value assigned
190 to (hard or pseudo) register n. We use this information to see if a
191 operation being processed is redundant given a prior operation performed
192 on the register. For example, an `and' with a constant is redundant if
193 all the zero bits are already known to be turned off.
195 We use an approach similar to that used by cse, but change it in the
198 (1) We do not want to reinitialize at each label.
199 (2) It is useful, but not critical, to know the actual value assigned
200 to a register. Often just its form is helpful.
202 Therefore, we maintain the following arrays:
204 reg_last_set_value the last value assigned
205 reg_last_set_label records the value of label_tick when the
206 register was assigned
207 reg_last_set_table_tick records the value of label_tick when a
208 value using the register is assigned
209 reg_last_set_invalid set to non-zero when it is not valid
210 to use the value of this register in some
213 To understand the usage of these tables, it is important to understand
214 the distinction between the value in reg_last_set_value being valid
215 and the register being validly contained in some other expression in the
218 Entry I in reg_last_set_value is valid if it is non-zero, and either
219 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
221 Register I may validly appear in any expression returned for the value
222 of another register if reg_n_sets[i] is 1. It may also appear in the
223 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
224 reg_last_set_invalid[j] is zero.
226 If an expression is found in the table containing a register which may
227 not validly appear in an expression, the register is replaced by
228 something that won't match, (clobber (const_int 0)).
230 reg_last_set_invalid[i] is set non-zero when register I is being assigned
231 to and reg_last_set_table_tick[i] == label_tick. */
233 /* Record last value assigned to (hard or pseudo) register n. */
235 static rtx *reg_last_set_value;
237 /* Record the value of label_tick when the value for register n is placed in
238 reg_last_set_value[n]. */
240 static int *reg_last_set_label;
242 /* Record the value of label_tick when an expression involving register n
243 is placed in reg_last_set_value. */
245 static int *reg_last_set_table_tick;
247 /* Set non-zero if references to register n in expressions should not be
250 static char *reg_last_set_invalid;
252 /* Incremented for each label. */
254 static int label_tick;
256 /* Some registers that are set more than once and used in more than one
257 basic block are nevertheless always set in similar ways. For example,
258 a QImode register may be loaded from memory in two places on a machine
259 where byte loads zero extend.
261 We record in the following array what we know about the nonzero
262 bits of a register, specifically which bits are known to be zero.
264 If an entry is zero, it means that we don't know anything special. */
266 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
268 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
269 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
271 static enum machine_mode nonzero_bits_mode;
273 /* Nonzero if we know that a register has some leading bits that are always
274 equal to the sign bit. */
276 static char *reg_sign_bit_copies;
278 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
279 It is zero while computing them and after combine has completed. This
280 former test prevents propagating values based on previously set values,
281 which can be incorrect if a variable is modified in a loop. */
283 static int nonzero_sign_valid;
285 /* These arrays are maintained in parallel with reg_last_set_value
286 and are used to store the mode in which the register was last set,
287 the bits that were known to be zero when it was last set, and the
288 number of sign bits copies it was known to have when it was last set. */
290 static enum machine_mode *reg_last_set_mode;
291 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
292 static char *reg_last_set_sign_bit_copies;
294 /* Record one modification to rtl structure
295 to be undone by storing old_contents into *where.
296 is_int is 1 if the contents are an int. */
301 union {rtx rtx; int i;} old_contents;
302 union {rtx *rtx; int *i;} where;
305 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
306 num_undo says how many are currently recorded.
308 storage is nonzero if we must undo the allocation of new storage.
309 The value of storage is what to pass to obfree.
311 other_insn is nonzero if we have modified some other insn in the process
312 of working on subst_insn. It must be verified too. */
320 struct undo undo[MAX_UNDO];
324 static struct undobuf undobuf;
326 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
327 insn. The substitution can be undone by undo_all. If INTO is already
328 set to NEWVAL, do not record this change. Because computing NEWVAL might
329 also call SUBST, we have to compute it before we put anything into
332 #define SUBST(INTO, NEWVAL) \
333 do { rtx _new = (NEWVAL); \
334 if (undobuf.num_undo < MAX_UNDO) \
336 undobuf.undo[undobuf.num_undo].is_int = 0; \
337 undobuf.undo[undobuf.num_undo].where.rtx = &INTO; \
338 undobuf.undo[undobuf.num_undo].old_contents.rtx = INTO; \
340 if (undobuf.undo[undobuf.num_undo].old_contents.rtx != INTO) \
341 undobuf.num_undo++; \
345 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
347 Note that substitution for the value of a CONST_INT is not safe. */
349 #define SUBST_INT(INTO, NEWVAL) \
350 do { if (undobuf.num_undo < MAX_UNDO) \
352 undobuf.undo[undobuf.num_undo].is_int = 1; \
353 undobuf.undo[undobuf.num_undo].where.i = (int *) &INTO; \
354 undobuf.undo[undobuf.num_undo].old_contents.i = INTO; \
356 if (undobuf.undo[undobuf.num_undo].old_contents.i != INTO) \
357 undobuf.num_undo++; \
361 /* Number of times the pseudo being substituted for
362 was found and replaced. */
364 static int n_occurrences;
366 static void set_nonzero_bits_and_sign_copies ();
367 static void setup_incoming_promotions ();
368 static void move_deaths ();
370 static void record_value_for_reg ();
371 static void record_dead_and_set_regs ();
372 static int use_crosses_set_p ();
373 static rtx try_combine ();
374 static rtx *find_split_point ();
376 static void undo_all ();
377 static int reg_dead_at_p ();
378 static rtx expand_compound_operation ();
379 static rtx expand_field_assignment ();
380 static rtx make_extraction ();
381 static int get_pos_from_mask ();
382 static rtx force_to_mode ();
383 static rtx known_cond ();
384 static rtx make_field_assignment ();
385 static rtx make_compound_operation ();
386 static rtx apply_distributive_law ();
387 static rtx simplify_and_const_int ();
388 static unsigned HOST_WIDE_INT nonzero_bits ();
389 static int num_sign_bit_copies ();
390 static int merge_outer_ops ();
391 static rtx simplify_shift_const ();
392 static int recog_for_combine ();
393 static rtx gen_lowpart_for_combine ();
394 static rtx gen_rtx_combine ();
395 static rtx gen_binary ();
396 static rtx gen_unary ();
397 static enum rtx_code simplify_comparison ();
398 static int reversible_comparison_p ();
399 static int get_last_value_validate ();
400 static rtx get_last_value ();
401 static void distribute_notes ();
402 static void distribute_links ();
404 /* Main entry point for combiner. F is the first insn of the function.
405 NREGS is the first unused pseudo-reg number. */
408 combine_instructions (f, nregs)
412 register rtx insn, next, prev;
414 register rtx links, nextlinks;
416 combine_attempts = 0;
419 combine_successes = 0;
420 undobuf.num_undo = previous_num_undos = 0;
422 combine_max_regno = nregs;
424 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
425 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
426 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
427 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
428 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
429 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
431 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
432 reg_last_set_nonzero_bits
433 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
434 reg_last_set_sign_bit_copies
435 = (char *) alloca (nregs * sizeof (char));
438 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
439 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
441 bzero (reg_last_death, nregs * sizeof (rtx));
442 bzero (reg_last_set, nregs * sizeof (rtx));
443 bzero (reg_last_set_value, nregs * sizeof (rtx));
444 bzero (reg_last_set_table_tick, nregs * sizeof (int));
445 bzero (reg_last_set_label, nregs * sizeof (int));
446 bzero (reg_last_set_invalid, nregs * sizeof (char));
447 bzero (reg_last_set_mode, nregs * sizeof (enum machine_mode));
448 bzero (reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
449 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
450 bzero (reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
451 bzero (reg_sign_bit_copies, nregs * sizeof (char));
453 init_recog_no_volatile ();
455 /* Compute maximum uid value so uid_cuid can be allocated. */
457 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
458 if (INSN_UID (insn) > i)
461 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
463 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
465 /* Don't use reg_nonzero_bits when computing it. This can cause problems
466 when, for example, we have j <<= 1 in a loop. */
468 nonzero_sign_valid = 0;
470 /* Compute the mapping from uids to cuids.
471 Cuids are numbers assigned to insns, like uids,
472 except that cuids increase monotonically through the code.
474 Scan all SETs and see if we can deduce anything about what
475 bits are known to be zero for some registers and how many copies
476 of the sign bit are known to exist for those registers.
478 Also set any known values so that we can use it while searching
479 for what bits are known to be set. */
483 setup_incoming_promotions ();
485 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
487 INSN_CUID (insn) = ++i;
491 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
493 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
494 record_dead_and_set_regs (insn);
497 if (GET_CODE (insn) == CODE_LABEL)
501 nonzero_sign_valid = 1;
503 /* Now scan all the insns in forward order. */
508 bzero (reg_last_death, nregs * sizeof (rtx));
509 bzero (reg_last_set, nregs * sizeof (rtx));
510 bzero (reg_last_set_value, nregs * sizeof (rtx));
511 bzero (reg_last_set_table_tick, nregs * sizeof (int));
512 bzero (reg_last_set_label, nregs * sizeof (int));
513 bzero (reg_last_set_invalid, nregs * sizeof (char));
515 setup_incoming_promotions ();
517 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
521 if (GET_CODE (insn) == CODE_LABEL)
524 else if (GET_CODE (insn) == INSN
525 || GET_CODE (insn) == CALL_INSN
526 || GET_CODE (insn) == JUMP_INSN)
528 /* Try this insn with each insn it links back to. */
530 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
531 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
534 /* Try each sequence of three linked insns ending with this one. */
536 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
537 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
538 nextlinks = XEXP (nextlinks, 1))
539 if ((next = try_combine (insn, XEXP (links, 0),
540 XEXP (nextlinks, 0))) != 0)
544 /* Try to combine a jump insn that uses CC0
545 with a preceding insn that sets CC0, and maybe with its
546 logical predecessor as well.
547 This is how we make decrement-and-branch insns.
548 We need this special code because data flow connections
549 via CC0 do not get entered in LOG_LINKS. */
551 if (GET_CODE (insn) == JUMP_INSN
552 && (prev = prev_nonnote_insn (insn)) != 0
553 && GET_CODE (prev) == INSN
554 && sets_cc0_p (PATTERN (prev)))
556 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
559 for (nextlinks = LOG_LINKS (prev); nextlinks;
560 nextlinks = XEXP (nextlinks, 1))
561 if ((next = try_combine (insn, prev,
562 XEXP (nextlinks, 0))) != 0)
566 /* Do the same for an insn that explicitly references CC0. */
567 if (GET_CODE (insn) == INSN
568 && (prev = prev_nonnote_insn (insn)) != 0
569 && GET_CODE (prev) == INSN
570 && sets_cc0_p (PATTERN (prev))
571 && GET_CODE (PATTERN (insn)) == SET
572 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
574 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
577 for (nextlinks = LOG_LINKS (prev); nextlinks;
578 nextlinks = XEXP (nextlinks, 1))
579 if ((next = try_combine (insn, prev,
580 XEXP (nextlinks, 0))) != 0)
584 /* Finally, see if any of the insns that this insn links to
585 explicitly references CC0. If so, try this insn, that insn,
586 and its predecessor if it sets CC0. */
587 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
588 if (GET_CODE (XEXP (links, 0)) == INSN
589 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
590 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
591 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
592 && GET_CODE (prev) == INSN
593 && sets_cc0_p (PATTERN (prev))
594 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
598 /* Try combining an insn with two different insns whose results it
600 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
601 for (nextlinks = XEXP (links, 1); nextlinks;
602 nextlinks = XEXP (nextlinks, 1))
603 if ((next = try_combine (insn, XEXP (links, 0),
604 XEXP (nextlinks, 0))) != 0)
607 if (GET_CODE (insn) != NOTE)
608 record_dead_and_set_regs (insn);
615 total_attempts += combine_attempts;
616 total_merges += combine_merges;
617 total_extras += combine_extras;
618 total_successes += combine_successes;
620 nonzero_sign_valid = 0;
623 /* Set up any promoted values for incoming argument registers. */
626 setup_incoming_promotions ()
628 #ifdef PROMOTE_FUNCTION_ARGS
631 enum machine_mode mode;
633 rtx first = get_insns ();
635 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
636 if (FUNCTION_ARG_REGNO_P (regno)
637 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
638 record_value_for_reg (reg, first,
639 gen_rtx (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
641 gen_rtx (CLOBBER, mode, const0_rtx)));
645 /* Called via note_stores. If X is a pseudo that is used in more than
646 one basic block, is narrower that HOST_BITS_PER_WIDE_INT, and is being
647 set, record what bits are known zero. If we are clobbering X,
648 ignore this "set" because the clobbered value won't be used.
650 If we are setting only a portion of X and we can't figure out what
651 portion, assume all bits will be used since we don't know what will
654 Similarly, set how many bits of X are known to be copies of the sign bit
655 at all locations in the function. This is the smallest number implied
659 set_nonzero_bits_and_sign_copies (x, set)
665 if (GET_CODE (x) == REG
666 && REGNO (x) >= FIRST_PSEUDO_REGISTER
667 && reg_n_sets[REGNO (x)] > 1
668 && reg_basic_block[REGNO (x)] < 0
669 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
671 if (GET_CODE (set) == CLOBBER)
674 /* If this is a complex assignment, see if we can convert it into a
675 simple assignment. */
676 set = expand_field_assignment (set);
678 /* If this is a simple assignment, or we have a paradoxical SUBREG,
679 set what we know about X. */
681 if (SET_DEST (set) == x
682 || (GET_CODE (SET_DEST (set)) == SUBREG
683 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
684 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
685 && SUBREG_REG (SET_DEST (set)) == x))
687 reg_nonzero_bits[REGNO (x)]
688 |= nonzero_bits (SET_SRC (set), nonzero_bits_mode);
689 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
690 if (reg_sign_bit_copies[REGNO (x)] == 0
691 || reg_sign_bit_copies[REGNO (x)] > num)
692 reg_sign_bit_copies[REGNO (x)] = num;
696 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
697 reg_sign_bit_copies[REGNO (x)] = 0;
702 /* See if INSN can be combined into I3. PRED and SUCC are optionally
703 insns that were previously combined into I3 or that will be combined
704 into the merger of INSN and I3.
706 Return 0 if the combination is not allowed for any reason.
708 If the combination is allowed, *PDEST will be set to the single
709 destination of INSN and *PSRC to the single source, and this function
713 can_combine_p (insn, i3, pred, succ, pdest, psrc)
720 rtx set = 0, src, dest;
722 int all_adjacent = (succ ? (next_active_insn (insn) == succ
723 && next_active_insn (succ) == i3)
724 : next_active_insn (insn) == i3);
726 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
727 or a PARALLEL consisting of such a SET and CLOBBERs.
729 If INSN has CLOBBER parallel parts, ignore them for our processing.
730 By definition, these happen during the execution of the insn. When it
731 is merged with another insn, all bets are off. If they are, in fact,
732 needed and aren't also supplied in I3, they may be added by
733 recog_for_combine. Otherwise, it won't match.
735 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
738 Get the source and destination of INSN. If more than one, can't
741 if (GET_CODE (PATTERN (insn)) == SET)
742 set = PATTERN (insn);
743 else if (GET_CODE (PATTERN (insn)) == PARALLEL
744 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
746 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
748 rtx elt = XVECEXP (PATTERN (insn), 0, i);
750 switch (GET_CODE (elt))
752 /* We can ignore CLOBBERs. */
757 /* Ignore SETs whose result isn't used but not those that
758 have side-effects. */
759 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
760 && ! side_effects_p (elt))
763 /* If we have already found a SET, this is a second one and
764 so we cannot combine with this insn. */
772 /* Anything else means we can't combine. */
778 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
779 so don't do anything with it. */
780 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
789 set = expand_field_assignment (set);
790 src = SET_SRC (set), dest = SET_DEST (set);
792 /* Don't eliminate a store in the stack pointer. */
793 if (dest == stack_pointer_rtx
794 /* Don't install a subreg involving two modes not tieable.
795 It can worsen register allocation, and can even make invalid reload
796 insns, since the reg inside may need to be copied from in the
797 outside mode, and that may be invalid if it is an fp reg copied in
798 integer mode. As a special exception, we can allow this if
799 I3 is simply copying DEST, a REG, to CC0. */
800 || (GET_CODE (src) == SUBREG
801 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
803 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
804 && SET_DEST (PATTERN (i3)) == cc0_rtx
805 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
808 /* If we couldn't eliminate a field assignment, we can't combine. */
809 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
810 /* Don't combine with an insn that sets a register to itself if it has
811 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
812 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
813 /* Can't merge a function call. */
814 || GET_CODE (src) == CALL
815 /* Don't substitute into an incremented register. */
816 || FIND_REG_INC_NOTE (i3, dest)
817 || (succ && FIND_REG_INC_NOTE (succ, dest))
818 /* Don't combine the end of a libcall into anything. */
819 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
820 /* Make sure that DEST is not used after SUCC but before I3. */
821 || (succ && ! all_adjacent
822 && reg_used_between_p (dest, succ, i3))
823 /* Make sure that the value that is to be substituted for the register
824 does not use any registers whose values alter in between. However,
825 If the insns are adjacent, a use can't cross a set even though we
826 think it might (this can happen for a sequence of insns each setting
827 the same destination; reg_last_set of that register might point to
828 a NOTE). Also, don't move a volatile asm or UNSPEC_VOLATILE across
831 && (use_crosses_set_p (src, INSN_CUID (insn))
832 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
833 || GET_CODE (src) == UNSPEC_VOLATILE))
834 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
835 better register allocation by not doing the combine. */
836 || find_reg_note (i3, REG_NO_CONFLICT, dest)
837 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
838 /* Don't combine across a CALL_INSN, because that would possibly
839 change whether the life span of some REGs crosses calls or not,
840 and it is a pain to update that information.
841 Exception: if source is a constant, moving it later can't hurt.
842 Accept that special case, because it helps -fforce-addr a lot. */
843 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
846 /* DEST must either be a REG or CC0. */
847 if (GET_CODE (dest) == REG)
849 /* If register alignment is being enforced for multi-word items in all
850 cases except for parameters, it is possible to have a register copy
851 insn referencing a hard register that is not allowed to contain the
852 mode being copied and which would not be valid as an operand of most
853 insns. Eliminate this problem by not combining with such an insn.
855 Also, on some machines we don't want to extend the life of a hard
858 if (GET_CODE (src) == REG
859 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
860 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
861 #ifdef SMALL_REGISTER_CLASSES
862 /* Don't extend the life of a hard register. */
863 || REGNO (src) < FIRST_PSEUDO_REGISTER
865 || (REGNO (src) < FIRST_PSEUDO_REGISTER
866 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
871 else if (GET_CODE (dest) != CC0)
874 /* Don't substitute for a register intended as a clobberable operand.
875 Similarly, don't substitute an expression containing a register that
876 will be clobbered in I3. */
877 if (GET_CODE (PATTERN (i3)) == PARALLEL)
878 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
879 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
880 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
882 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
885 /* If INSN contains anything volatile, or is an `asm' (whether volatile
886 or not), reject, unless nothing volatile comes between it and I3,
887 with the exception of SUCC. */
889 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
890 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
891 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
892 && p != succ && volatile_refs_p (PATTERN (p)))
895 /* If INSN or I2 contains an autoincrement or autodecrement,
896 make sure that register is not used between there and I3,
897 and not already used in I3 either.
898 Also insist that I3 not be a jump; if it were one
899 and the incremented register were spilled, we would lose. */
902 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
903 if (REG_NOTE_KIND (link) == REG_INC
904 && (GET_CODE (i3) == JUMP_INSN
905 || reg_used_between_p (XEXP (link, 0), insn, i3)
906 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
911 /* Don't combine an insn that follows a CC0-setting insn.
912 An insn that uses CC0 must not be separated from the one that sets it.
913 We do, however, allow I2 to follow a CC0-setting insn if that insn
914 is passed as I1; in that case it will be deleted also.
915 We also allow combining in this case if all the insns are adjacent
916 because that would leave the two CC0 insns adjacent as well.
917 It would be more logical to test whether CC0 occurs inside I1 or I2,
918 but that would be much slower, and this ought to be equivalent. */
920 p = prev_nonnote_insn (insn);
921 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
926 /* If we get here, we have passed all the tests and the combination is
935 /* LOC is the location within I3 that contains its pattern or the component
936 of a PARALLEL of the pattern. We validate that it is valid for combining.
938 One problem is if I3 modifies its output, as opposed to replacing it
939 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
940 so would produce an insn that is not equivalent to the original insns.
944 (set (reg:DI 101) (reg:DI 100))
945 (set (subreg:SI (reg:DI 101) 0) <foo>)
947 This is NOT equivalent to:
949 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
950 (set (reg:DI 101) (reg:DI 100))])
952 Not only does this modify 100 (in which case it might still be valid
953 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
955 We can also run into a problem if I2 sets a register that I1
956 uses and I1 gets directly substituted into I3 (not via I2). In that
957 case, we would be getting the wrong value of I2DEST into I3, so we
958 must reject the combination. This case occurs when I2 and I1 both
959 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
960 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
961 of a SET must prevent combination from occurring.
963 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
964 if the destination of a SET is a hard register.
966 Before doing the above check, we first try to expand a field assignment
967 into a set of logical operations.
969 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
970 we place a register that is both set and used within I3. If more than one
971 such register is detected, we fail.
973 Return 1 if the combination is valid, zero otherwise. */
976 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
986 if (GET_CODE (x) == SET)
988 rtx set = expand_field_assignment (x);
989 rtx dest = SET_DEST (set);
990 rtx src = SET_SRC (set);
991 rtx inner_dest = dest, inner_src = src;
995 while (GET_CODE (inner_dest) == STRICT_LOW_PART
996 || GET_CODE (inner_dest) == SUBREG
997 || GET_CODE (inner_dest) == ZERO_EXTRACT)
998 inner_dest = XEXP (inner_dest, 0);
1000 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1003 while (GET_CODE (inner_src) == STRICT_LOW_PART
1004 || GET_CODE (inner_src) == SUBREG
1005 || GET_CODE (inner_src) == ZERO_EXTRACT)
1006 inner_src = XEXP (inner_src, 0);
1008 /* If it is better that two different modes keep two different pseudos,
1009 avoid combining them. This avoids producing the following pattern
1011 (set (subreg:SI (reg/v:QI 21) 0)
1012 (lshiftrt:SI (reg/v:SI 20)
1014 If that were made, reload could not handle the pair of
1015 reg 20/21, since it would try to get any GENERAL_REGS
1016 but some of them don't handle QImode. */
1018 if (rtx_equal_p (inner_src, i2dest)
1019 && GET_CODE (inner_dest) == REG
1020 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1024 /* Check for the case where I3 modifies its output, as
1026 if ((inner_dest != dest
1027 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1028 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1029 /* This is the same test done in can_combine_p except that we
1030 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1032 || (GET_CODE (inner_dest) == REG
1033 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1034 #ifdef SMALL_REGISTER_CLASSES
1035 && GET_CODE (src) != CALL
1037 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1038 GET_MODE (inner_dest))
1042 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1045 /* If DEST is used in I3, it is being killed in this insn,
1046 so record that for later. */
1047 if (pi3dest_killed && GET_CODE (dest) == REG
1048 && reg_referenced_p (dest, PATTERN (i3)))
1050 if (*pi3dest_killed)
1053 *pi3dest_killed = dest;
1057 else if (GET_CODE (x) == PARALLEL)
1061 for (i = 0; i < XVECLEN (x, 0); i++)
1062 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1063 i1_not_in_src, pi3dest_killed))
1070 /* Try to combine the insns I1 and I2 into I3.
1071 Here I1 and I2 appear earlier than I3.
1072 I1 can be zero; then we combine just I2 into I3.
1074 It we are combining three insns and the resulting insn is not recognized,
1075 try splitting it into two insns. If that happens, I2 and I3 are retained
1076 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1079 If we created two insns, return I2; otherwise return I3.
1080 Return 0 if the combination does not work. Then nothing is changed. */
1083 try_combine (i3, i2, i1)
1084 register rtx i3, i2, i1;
1086 /* New patterns for I3 and I3, respectively. */
1087 rtx newpat, newi2pat = 0;
1088 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1089 int added_sets_1, added_sets_2;
1090 /* Total number of SETs to put into I3. */
1092 /* Nonzero is I2's body now appears in I3. */
1094 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1095 int insn_code_number, i2_code_number, other_code_number;
1096 /* Contains I3 if the destination of I3 is used in its source, which means
1097 that the old life of I3 is being killed. If that usage is placed into
1098 I2 and not in I3, a REG_DEAD note must be made. */
1099 rtx i3dest_killed = 0;
1100 /* SET_DEST and SET_SRC of I2 and I1. */
1101 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1102 /* PATTERN (I2), or a copy of it in certain cases. */
1104 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1105 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1106 int i1_feeds_i3 = 0;
1107 /* Notes that must be added to REG_NOTES in I3 and I2. */
1108 rtx new_i3_notes, new_i2_notes;
1115 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1116 This can occur when flow deletes an insn that it has merged into an
1117 auto-increment address. We also can't do anything if I3 has a
1118 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1121 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1122 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1123 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1124 || find_reg_note (i3, REG_LIBCALL, NULL_RTX))
1129 undobuf.num_undo = previous_num_undos = 0;
1130 undobuf.other_insn = 0;
1132 /* Save the current high-water-mark so we can free storage if we didn't
1133 accept this combination. */
1134 undobuf.storage = (char *) oballoc (0);
1136 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1137 code below, set I1 to be the earlier of the two insns. */
1138 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1139 temp = i1, i1 = i2, i2 = temp;
1141 /* First check for one important special-case that the code below will
1142 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1143 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1144 we may be able to replace that destination with the destination of I3.
1145 This occurs in the common code where we compute both a quotient and
1146 remainder into a structure, in which case we want to do the computation
1147 directly into the structure to avoid register-register copies.
1149 We make very conservative checks below and only try to handle the
1150 most common cases of this. For example, we only handle the case
1151 where I2 and I3 are adjacent to avoid making difficult register
1154 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1155 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1156 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1157 #ifdef SMALL_REGISTER_CLASSES
1158 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1159 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1161 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1162 && GET_CODE (PATTERN (i2)) == PARALLEL
1163 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1164 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1165 below would need to check what is inside (and reg_overlap_mentioned_p
1166 doesn't support those codes anyway). Don't allow those destinations;
1167 the resulting insn isn't likely to be recognized anyway. */
1168 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1169 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1170 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1171 SET_DEST (PATTERN (i3)))
1172 && next_real_insn (i2) == i3)
1174 rtx p2 = PATTERN (i2);
1176 /* Make sure that the destination of I3,
1177 which we are going to substitute into one output of I2,
1178 is not used within another output of I2. We must avoid making this:
1179 (parallel [(set (mem (reg 69)) ...)
1180 (set (reg 69) ...)])
1181 which is not well-defined as to order of actions.
1182 (Besides, reload can't handle output reloads for this.)
1184 The problem can also happen if the dest of I3 is a memory ref,
1185 if another dest in I2 is an indirect memory ref. */
1186 for (i = 0; i < XVECLEN (p2, 0); i++)
1187 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1188 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1189 SET_DEST (XVECEXP (p2, 0, i))))
1192 if (i == XVECLEN (p2, 0))
1193 for (i = 0; i < XVECLEN (p2, 0); i++)
1194 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1199 subst_low_cuid = INSN_CUID (i2);
1202 i2dest = SET_SRC (PATTERN (i3));
1204 /* Replace the dest in I2 with our dest and make the resulting
1205 insn the new pattern for I3. Then skip to where we
1206 validate the pattern. Everything was set up above. */
1207 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1208 SET_DEST (PATTERN (i3)));
1211 goto validate_replacement;
1216 /* If we have no I1 and I2 looks like:
1217 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1219 make up a dummy I1 that is
1222 (set (reg:CC X) (compare:CC Y (const_int 0)))
1224 (We can ignore any trailing CLOBBERs.)
1226 This undoes a previous combination and allows us to match a branch-and-
1229 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1230 && XVECLEN (PATTERN (i2), 0) >= 2
1231 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1232 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1234 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1235 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1236 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1237 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1238 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1239 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1241 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1242 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1247 /* We make I1 with the same INSN_UID as I2. This gives it
1248 the same INSN_CUID for value tracking. Our fake I1 will
1249 never appear in the insn stream so giving it the same INSN_UID
1250 as I2 will not cause a problem. */
1252 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1253 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1255 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1256 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1257 SET_DEST (PATTERN (i1)));
1262 /* Verify that I2 and I1 are valid for combining. */
1263 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1264 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1270 /* Record whether I2DEST is used in I2SRC and similarly for the other
1271 cases. Knowing this will help in register status updating below. */
1272 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1273 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1274 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1276 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1278 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1280 /* Ensure that I3's pattern can be the destination of combines. */
1281 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1282 i1 && i2dest_in_i1src && i1_feeds_i3,
1289 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1290 We used to do this EXCEPT in one case: I3 has a post-inc in an
1291 output operand. However, that exception can give rise to insns like
1293 which is a famous insn on the PDP-11 where the value of r3 used as the
1294 source was model-dependent. Avoid this sort of thing. */
1297 if (!(GET_CODE (PATTERN (i3)) == SET
1298 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1299 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1300 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1301 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1302 /* It's not the exception. */
1305 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1306 if (REG_NOTE_KIND (link) == REG_INC
1307 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1309 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1316 /* See if the SETs in I1 or I2 need to be kept around in the merged
1317 instruction: whenever the value set there is still needed past I3.
1318 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1320 For the SET in I1, we have two cases: If I1 and I2 independently
1321 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1322 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1323 in I1 needs to be kept around unless I1DEST dies or is set in either
1324 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1325 I1DEST. If so, we know I1 feeds into I2. */
1327 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1330 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1331 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1333 /* If the set in I2 needs to be kept around, we must make a copy of
1334 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1335 PATTERN (I2), we are only substituting for the original I1DEST, not into
1336 an already-substituted copy. This also prevents making self-referential
1337 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1340 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1341 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1345 i2pat = copy_rtx (i2pat);
1349 /* Substitute in the latest insn for the regs set by the earlier ones. */
1351 maxreg = max_reg_num ();
1355 /* It is possible that the source of I2 or I1 may be performing an
1356 unneeded operation, such as a ZERO_EXTEND of something that is known
1357 to have the high part zero. Handle that case by letting subst look at
1358 the innermost one of them.
1360 Another way to do this would be to have a function that tries to
1361 simplify a single insn instead of merging two or more insns. We don't
1362 do this because of the potential of infinite loops and because
1363 of the potential extra memory required. However, doing it the way
1364 we are is a bit of a kludge and doesn't catch all cases.
1366 But only do this if -fexpensive-optimizations since it slows things down
1367 and doesn't usually win. */
1369 if (flag_expensive_optimizations)
1371 /* Pass pc_rtx so no substitutions are done, just simplifications.
1372 The cases that we are interested in here do not involve the few
1373 cases were is_replaced is checked. */
1376 subst_low_cuid = INSN_CUID (i1);
1377 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1381 subst_low_cuid = INSN_CUID (i2);
1382 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1385 previous_num_undos = undobuf.num_undo;
1389 /* Many machines that don't use CC0 have insns that can both perform an
1390 arithmetic operation and set the condition code. These operations will
1391 be represented as a PARALLEL with the first element of the vector
1392 being a COMPARE of an arithmetic operation with the constant zero.
1393 The second element of the vector will set some pseudo to the result
1394 of the same arithmetic operation. If we simplify the COMPARE, we won't
1395 match such a pattern and so will generate an extra insn. Here we test
1396 for this case, where both the comparison and the operation result are
1397 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1398 I2SRC. Later we will make the PARALLEL that contains I2. */
1400 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1401 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1402 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1403 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1406 enum machine_mode compare_mode;
1408 newpat = PATTERN (i3);
1409 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1413 #ifdef EXTRA_CC_MODES
1414 /* See if a COMPARE with the operand we substituted in should be done
1415 with the mode that is currently being used. If not, do the same
1416 processing we do in `subst' for a SET; namely, if the destination
1417 is used only once, try to replace it with a register of the proper
1418 mode and also replace the COMPARE. */
1419 if (undobuf.other_insn == 0
1420 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1421 &undobuf.other_insn))
1422 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1424 != GET_MODE (SET_DEST (newpat))))
1426 int regno = REGNO (SET_DEST (newpat));
1427 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1429 if (regno < FIRST_PSEUDO_REGISTER
1430 || (reg_n_sets[regno] == 1 && ! added_sets_2
1431 && ! REG_USERVAR_P (SET_DEST (newpat))))
1433 if (regno >= FIRST_PSEUDO_REGISTER)
1434 SUBST (regno_reg_rtx[regno], new_dest);
1436 SUBST (SET_DEST (newpat), new_dest);
1437 SUBST (XEXP (*cc_use, 0), new_dest);
1438 SUBST (SET_SRC (newpat),
1439 gen_rtx_combine (COMPARE, compare_mode,
1440 i2src, const0_rtx));
1443 undobuf.other_insn = 0;
1450 n_occurrences = 0; /* `subst' counts here */
1452 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1453 need to make a unique copy of I2SRC each time we substitute it
1454 to avoid self-referential rtl. */
1456 subst_low_cuid = INSN_CUID (i2);
1457 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1458 ! i1_feeds_i3 && i1dest_in_i1src);
1459 previous_num_undos = undobuf.num_undo;
1461 /* Record whether i2's body now appears within i3's body. */
1462 i2_is_used = n_occurrences;
1465 /* If we already got a failure, don't try to do more. Otherwise,
1466 try to substitute in I1 if we have it. */
1468 if (i1 && GET_CODE (newpat) != CLOBBER)
1470 /* Before we can do this substitution, we must redo the test done
1471 above (see detailed comments there) that ensures that I1DEST
1472 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1474 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1482 subst_low_cuid = INSN_CUID (i1);
1483 newpat = subst (newpat, i1dest, i1src, 0, 0);
1484 previous_num_undos = undobuf.num_undo;
1487 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1488 to count all the ways that I2SRC and I1SRC can be used. */
1489 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1490 && i2_is_used + added_sets_2 > 1)
1491 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1492 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1494 /* Fail if we tried to make a new register (we used to abort, but there's
1495 really no reason to). */
1496 || max_reg_num () != maxreg
1497 /* Fail if we couldn't do something and have a CLOBBER. */
1498 || GET_CODE (newpat) == CLOBBER)
1504 /* If the actions of the earlier insns must be kept
1505 in addition to substituting them into the latest one,
1506 we must make a new PARALLEL for the latest insn
1507 to hold additional the SETs. */
1509 if (added_sets_1 || added_sets_2)
1513 if (GET_CODE (newpat) == PARALLEL)
1515 rtvec old = XVEC (newpat, 0);
1516 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1517 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1518 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1519 sizeof (old->elem[0]) * old->num_elem);
1524 total_sets = 1 + added_sets_1 + added_sets_2;
1525 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1526 XVECEXP (newpat, 0, 0) = old;
1530 XVECEXP (newpat, 0, --total_sets)
1531 = (GET_CODE (PATTERN (i1)) == PARALLEL
1532 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1536 /* If there is no I1, use I2's body as is. We used to also not do
1537 the subst call below if I2 was substituted into I3,
1538 but that could lose a simplification. */
1540 XVECEXP (newpat, 0, --total_sets) = i2pat;
1542 /* See comment where i2pat is assigned. */
1543 XVECEXP (newpat, 0, --total_sets)
1544 = subst (i2pat, i1dest, i1src, 0, 0);
1548 /* We come here when we are replacing a destination in I2 with the
1549 destination of I3. */
1550 validate_replacement:
1552 /* Is the result of combination a valid instruction? */
1553 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1555 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1556 the second SET's destination is a register that is unused. In that case,
1557 we just need the first SET. This can occur when simplifying a divmod
1558 insn. We *must* test for this case here because the code below that
1559 splits two independent SETs doesn't handle this case correctly when it
1560 updates the register status. Also check the case where the first
1561 SET's destination is unused. That would not cause incorrect code, but
1562 does cause an unneeded insn to remain. */
1564 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1565 && XVECLEN (newpat, 0) == 2
1566 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1567 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1568 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1569 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1570 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1571 && asm_noperands (newpat) < 0)
1573 newpat = XVECEXP (newpat, 0, 0);
1574 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1577 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1578 && XVECLEN (newpat, 0) == 2
1579 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1580 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1581 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1582 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1583 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1584 && asm_noperands (newpat) < 0)
1586 newpat = XVECEXP (newpat, 0, 1);
1587 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1590 /* See if this is an XOR. If so, perhaps the problem is that the
1591 constant is out of range. Replace it with a complemented XOR with
1592 a complemented constant; it might be in range. */
1594 else if (insn_code_number < 0 && GET_CODE (newpat) == SET
1595 && GET_CODE (SET_SRC (newpat)) == XOR
1596 && GET_CODE (XEXP (SET_SRC (newpat), 1)) == CONST_INT
1597 && ((temp = simplify_unary_operation (NOT,
1598 GET_MODE (SET_SRC (newpat)),
1599 XEXP (SET_SRC (newpat), 1),
1600 GET_MODE (SET_SRC (newpat))))
1603 enum machine_mode i_mode = GET_MODE (SET_SRC (newpat));
1605 = gen_rtx_combine (SET, VOIDmode, SET_DEST (newpat),
1606 gen_unary (NOT, i_mode,
1607 gen_binary (XOR, i_mode,
1608 XEXP (SET_SRC (newpat), 0),
1611 insn_code_number = recog_for_combine (&pat, i3, &new_i3_notes);
1612 if (insn_code_number >= 0)
1616 /* If we were combining three insns and the result is a simple SET
1617 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1618 insns. There are two ways to do this. It can be split using a
1619 machine-specific method (like when you have an addition of a large
1620 constant) or by combine in the function find_split_point. */
1622 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1623 && asm_noperands (newpat) < 0)
1625 rtx m_split, *split;
1626 rtx ni2dest = i2dest;
1628 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1629 use I2DEST as a scratch register will help. In the latter case,
1630 convert I2DEST to the mode of the source of NEWPAT if we can. */
1632 m_split = split_insns (newpat, i3);
1634 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1635 inputs of NEWPAT. */
1637 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1638 possible to try that as a scratch reg. This would require adding
1639 more code to make it work though. */
1641 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1643 /* If I2DEST is a hard register or the only use of a pseudo,
1644 we can change its mode. */
1645 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1646 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1647 && GET_CODE (i2dest) == REG
1648 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1649 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1650 && ! REG_USERVAR_P (i2dest))))
1651 ni2dest = gen_rtx (REG, GET_MODE (SET_DEST (newpat)),
1654 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1655 gen_rtvec (2, newpat,
1662 if (m_split && GET_CODE (m_split) == SEQUENCE
1663 && XVECLEN (m_split, 0) == 2
1664 && (next_real_insn (i2) == i3
1665 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1669 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1670 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1672 i3set = single_set (XVECEXP (m_split, 0, 1));
1673 i2set = single_set (XVECEXP (m_split, 0, 0));
1675 /* In case we changed the mode of I2DEST, replace it in the
1676 pseudo-register table here. We can't do it above in case this
1677 code doesn't get executed and we do a split the other way. */
1679 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1680 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1682 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1684 /* If I2 or I3 has multiple SETs, we won't know how to track
1685 register status, so don't use these insns. */
1687 if (i2_code_number >= 0 && i2set && i3set)
1688 insn_code_number = recog_for_combine (&newi3pat, i3,
1691 if (insn_code_number >= 0)
1694 /* It is possible that both insns now set the destination of I3.
1695 If so, we must show an extra use of it. */
1697 if (insn_code_number >= 0 && GET_CODE (SET_DEST (i3set)) == REG
1698 && GET_CODE (SET_DEST (i2set)) == REG
1699 && REGNO (SET_DEST (i3set)) == REGNO (SET_DEST (i2set)))
1700 reg_n_sets[REGNO (SET_DEST (i2set))]++;
1703 /* If we can split it and use I2DEST, go ahead and see if that
1704 helps things be recognized. Verify that none of the registers
1705 are set between I2 and I3. */
1706 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1708 && GET_CODE (i2dest) == REG
1710 /* We need I2DEST in the proper mode. If it is a hard register
1711 or the only use of a pseudo, we can change its mode. */
1712 && (GET_MODE (*split) == GET_MODE (i2dest)
1713 || GET_MODE (*split) == VOIDmode
1714 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1715 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1716 && ! REG_USERVAR_P (i2dest)))
1717 && (next_real_insn (i2) == i3
1718 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1719 /* We can't overwrite I2DEST if its value is still used by
1721 && ! reg_referenced_p (i2dest, newpat))
1723 rtx newdest = i2dest;
1725 /* Get NEWDEST as a register in the proper mode. We have already
1726 validated that we can do this. */
1727 if (GET_MODE (i2dest) != GET_MODE (*split)
1728 && GET_MODE (*split) != VOIDmode)
1730 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1732 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1733 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1736 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1737 an ASHIFT. This can occur if it was inside a PLUS and hence
1738 appeared to be a memory address. This is a kludge. */
1739 if (GET_CODE (*split) == MULT
1740 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1741 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1742 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1743 XEXP (*split, 0), GEN_INT (i)));
1745 #ifdef INSN_SCHEDULING
1746 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1747 be written as a ZERO_EXTEND. */
1748 if (GET_CODE (*split) == SUBREG
1749 && GET_CODE (SUBREG_REG (*split)) == MEM)
1750 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1754 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1755 SUBST (*split, newdest);
1756 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1757 if (i2_code_number >= 0)
1758 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1762 /* Check for a case where we loaded from memory in a narrow mode and
1763 then sign extended it, but we need both registers. In that case,
1764 we have a PARALLEL with both loads from the same memory location.
1765 We can split this into a load from memory followed by a register-register
1766 copy. This saves at least one insn, more if register allocation can
1767 eliminate the copy. */
1769 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1770 && GET_CODE (newpat) == PARALLEL
1771 && XVECLEN (newpat, 0) == 2
1772 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1773 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1774 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1775 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1776 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1777 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1779 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1780 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1781 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1782 SET_SRC (XVECEXP (newpat, 0, 1)))
1783 && ! find_reg_note (i3, REG_UNUSED,
1784 SET_DEST (XVECEXP (newpat, 0, 0))))
1788 newi2pat = XVECEXP (newpat, 0, 0);
1789 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
1790 newpat = XVECEXP (newpat, 0, 1);
1791 SUBST (SET_SRC (newpat),
1792 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
1793 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1794 if (i2_code_number >= 0)
1795 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1797 if (insn_code_number >= 0)
1802 /* If we will be able to accept this, we have made a change to the
1803 destination of I3. This can invalidate a LOG_LINKS pointing
1804 to I3. No other part of combine.c makes such a transformation.
1806 The new I3 will have a destination that was previously the
1807 destination of I1 or I2 and which was used in i2 or I3. Call
1808 distribute_links to make a LOG_LINK from the next use of
1809 that destination. */
1811 PATTERN (i3) = newpat;
1812 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, NULL_RTX));
1814 /* I3 now uses what used to be its destination and which is
1815 now I2's destination. That means we need a LOG_LINK from
1816 I3 to I2. But we used to have one, so we still will.
1818 However, some later insn might be using I2's dest and have
1819 a LOG_LINK pointing at I3. We must remove this link.
1820 The simplest way to remove the link is to point it at I1,
1821 which we know will be a NOTE. */
1823 for (insn = NEXT_INSN (i3);
1824 insn && GET_CODE (insn) != CODE_LABEL
1825 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1826 insn = NEXT_INSN (insn))
1828 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1829 && reg_referenced_p (ni2dest, PATTERN (insn)))
1831 for (link = LOG_LINKS (insn); link;
1832 link = XEXP (link, 1))
1833 if (XEXP (link, 0) == i3)
1834 XEXP (link, 0) = i1;
1842 /* Similarly, check for a case where we have a PARALLEL of two independent
1843 SETs but we started with three insns. In this case, we can do the sets
1844 as two separate insns. This case occurs when some SET allows two
1845 other insns to combine, but the destination of that SET is still live. */
1847 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1848 && GET_CODE (newpat) == PARALLEL
1849 && XVECLEN (newpat, 0) == 2
1850 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1851 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1852 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1853 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1854 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1855 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1856 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1858 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1859 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1860 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1861 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1862 XVECEXP (newpat, 0, 0))
1863 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1864 XVECEXP (newpat, 0, 1)))
1866 newi2pat = XVECEXP (newpat, 0, 1);
1867 newpat = XVECEXP (newpat, 0, 0);
1869 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1870 if (i2_code_number >= 0)
1871 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1874 /* If it still isn't recognized, fail and change things back the way they
1876 if ((insn_code_number < 0
1877 /* Is the result a reasonable ASM_OPERANDS? */
1878 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1884 /* If we had to change another insn, make sure it is valid also. */
1885 if (undobuf.other_insn)
1887 rtx other_notes = REG_NOTES (undobuf.other_insn);
1888 rtx other_pat = PATTERN (undobuf.other_insn);
1889 rtx new_other_notes;
1892 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1895 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1901 PATTERN (undobuf.other_insn) = other_pat;
1903 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1904 are still valid. Then add any non-duplicate notes added by
1905 recog_for_combine. */
1906 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1908 next = XEXP (note, 1);
1910 if (REG_NOTE_KIND (note) == REG_UNUSED
1911 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1913 if (GET_CODE (XEXP (note, 0)) == REG)
1914 reg_n_deaths[REGNO (XEXP (note, 0))]--;
1916 remove_note (undobuf.other_insn, note);
1920 for (note = new_other_notes; note; note = XEXP (note, 1))
1921 if (GET_CODE (XEXP (note, 0)) == REG)
1922 reg_n_deaths[REGNO (XEXP (note, 0))]++;
1924 distribute_notes (new_other_notes, undobuf.other_insn,
1925 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
1928 /* We now know that we can do this combination. Merge the insns and
1929 update the status of registers and LOG_LINKS. */
1932 rtx i3notes, i2notes, i1notes = 0;
1933 rtx i3links, i2links, i1links = 0;
1935 int all_adjacent = (next_real_insn (i2) == i3
1936 && (i1 == 0 || next_real_insn (i1) == i2));
1938 /* Compute which registers we expect to eliminate. */
1939 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1941 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1943 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1945 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1946 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1948 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1950 /* Ensure that we do not have something that should not be shared but
1951 occurs multiple times in the new insns. Check this by first
1952 resetting all the `used' flags and then copying anything is shared. */
1954 reset_used_flags (i3notes);
1955 reset_used_flags (i2notes);
1956 reset_used_flags (i1notes);
1957 reset_used_flags (newpat);
1958 reset_used_flags (newi2pat);
1959 if (undobuf.other_insn)
1960 reset_used_flags (PATTERN (undobuf.other_insn));
1962 i3notes = copy_rtx_if_shared (i3notes);
1963 i2notes = copy_rtx_if_shared (i2notes);
1964 i1notes = copy_rtx_if_shared (i1notes);
1965 newpat = copy_rtx_if_shared (newpat);
1966 newi2pat = copy_rtx_if_shared (newi2pat);
1967 if (undobuf.other_insn)
1968 reset_used_flags (PATTERN (undobuf.other_insn));
1970 INSN_CODE (i3) = insn_code_number;
1971 PATTERN (i3) = newpat;
1972 if (undobuf.other_insn)
1973 INSN_CODE (undobuf.other_insn) = other_code_number;
1975 /* We had one special case above where I2 had more than one set and
1976 we replaced a destination of one of those sets with the destination
1977 of I3. In that case, we have to update LOG_LINKS of insns later
1978 in this basic block. Note that this (expensive) case is rare. */
1980 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1981 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1982 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1983 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1984 && ! find_reg_note (i2, REG_UNUSED,
1985 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1989 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1991 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1992 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1993 if (XEXP (link, 0) == i2)
1994 XEXP (link, 0) = i3;
1996 if (GET_CODE (insn) == CODE_LABEL
1997 || GET_CODE (insn) == JUMP_INSN)
2009 INSN_CODE (i2) = i2_code_number;
2010 PATTERN (i2) = newi2pat;
2014 PUT_CODE (i2, NOTE);
2015 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2016 NOTE_SOURCE_FILE (i2) = 0;
2023 PUT_CODE (i1, NOTE);
2024 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2025 NOTE_SOURCE_FILE (i1) = 0;
2028 /* Get death notes for everything that is now used in either I3 or
2029 I2 and used to die in a previous insn. */
2031 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
2033 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
2035 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2037 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2040 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2043 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2046 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2049 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2050 know these are REG_UNUSED and want them to go to the desired insn,
2051 so we always pass it as i3. We have not counted the notes in
2052 reg_n_deaths yet, so we need to do so now. */
2054 if (newi2pat && new_i2_notes)
2056 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2057 if (GET_CODE (XEXP (temp, 0)) == REG)
2058 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2060 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2065 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2066 if (GET_CODE (XEXP (temp, 0)) == REG)
2067 reg_n_deaths[REGNO (XEXP (temp, 0))]++;
2069 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2072 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2073 put a REG_DEAD note for it somewhere. Similarly for I2 and I1.
2074 Show an additional death due to the REG_DEAD note we make here. If
2075 we discard it in distribute_notes, we will decrement it again. */
2079 if (GET_CODE (i3dest_killed) == REG)
2080 reg_n_deaths[REGNO (i3dest_killed)]++;
2082 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed,
2084 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2085 NULL_RTX, NULL_RTX);
2088 /* For I2 and I1, we have to be careful. If NEWI2PAT exists and sets
2089 I2DEST or I1DEST, the death must be somewhere before I2, not I3. If
2090 we passed I3 in that case, it might delete I2. */
2092 if (i2dest_in_i2src)
2094 if (GET_CODE (i2dest) == REG)
2095 reg_n_deaths[REGNO (i2dest)]++;
2097 if (newi2pat && reg_set_p (i2dest, newi2pat))
2098 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2099 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2101 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, NULL_RTX),
2102 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2103 NULL_RTX, NULL_RTX);
2106 if (i1dest_in_i1src)
2108 if (GET_CODE (i1dest) == REG)
2109 reg_n_deaths[REGNO (i1dest)]++;
2111 if (newi2pat && reg_set_p (i1dest, newi2pat))
2112 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2113 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2115 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, NULL_RTX),
2116 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2117 NULL_RTX, NULL_RTX);
2120 distribute_links (i3links);
2121 distribute_links (i2links);
2122 distribute_links (i1links);
2124 if (GET_CODE (i2dest) == REG)
2127 rtx i2_insn = 0, i2_val = 0, set;
2129 /* The insn that used to set this register doesn't exist, and
2130 this life of the register may not exist either. See if one of
2131 I3's links points to an insn that sets I2DEST. If it does,
2132 that is now the last known value for I2DEST. If we don't update
2133 this and I2 set the register to a value that depended on its old
2134 contents, we will get confused. If this insn is used, thing
2135 will be set correctly in combine_instructions. */
2137 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2138 if ((set = single_set (XEXP (link, 0))) != 0
2139 && rtx_equal_p (i2dest, SET_DEST (set)))
2140 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2142 record_value_for_reg (i2dest, i2_insn, i2_val);
2144 /* If the reg formerly set in I2 died only once and that was in I3,
2145 zero its use count so it won't make `reload' do any work. */
2146 if (! added_sets_2 && newi2pat == 0)
2148 regno = REGNO (i2dest);
2149 reg_n_sets[regno]--;
2150 if (reg_n_sets[regno] == 0
2151 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2152 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2153 reg_n_refs[regno] = 0;
2157 if (i1 && GET_CODE (i1dest) == REG)
2160 rtx i1_insn = 0, i1_val = 0, set;
2162 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2163 if ((set = single_set (XEXP (link, 0))) != 0
2164 && rtx_equal_p (i1dest, SET_DEST (set)))
2165 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2167 record_value_for_reg (i1dest, i1_insn, i1_val);
2169 regno = REGNO (i1dest);
2172 reg_n_sets[regno]--;
2173 if (reg_n_sets[regno] == 0
2174 && ! (basic_block_live_at_start[0][regno / REGSET_ELT_BITS]
2175 & ((REGSET_ELT_TYPE) 1 << (regno % REGSET_ELT_BITS))))
2176 reg_n_refs[regno] = 0;
2180 /* Update reg_nonzero_bits et al for any changes that may have been made
2183 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2185 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2187 /* If I3 is now an unconditional jump, ensure that it has a
2188 BARRIER following it since it may have initially been a
2189 conditional jump. It may also be the last nonnote insn. */
2191 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2192 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2193 || GET_CODE (temp) != BARRIER))
2194 emit_barrier_after (i3);
2197 combine_successes++;
2199 return newi2pat ? i2 : i3;
2202 /* Undo all the modifications recorded in undobuf. */
2208 if (undobuf.num_undo > MAX_UNDO)
2209 undobuf.num_undo = MAX_UNDO;
2210 for (i = undobuf.num_undo - 1; i >= 0; i--)
2212 if (undobuf.undo[i].is_int)
2213 *undobuf.undo[i].where.i = undobuf.undo[i].old_contents.i;
2215 *undobuf.undo[i].where.rtx = undobuf.undo[i].old_contents.rtx;
2219 obfree (undobuf.storage);
2220 undobuf.num_undo = 0;
2223 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2224 where we have an arithmetic expression and return that point. LOC will
2227 try_combine will call this function to see if an insn can be split into
2231 find_split_point (loc, insn)
2236 enum rtx_code code = GET_CODE (x);
2238 int len = 0, pos, unsignedp;
2241 /* First special-case some codes. */
2245 #ifdef INSN_SCHEDULING
2246 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2248 if (GET_CODE (SUBREG_REG (x)) == MEM)
2251 return find_split_point (&SUBREG_REG (x), insn);
2255 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2256 using LO_SUM and HIGH. */
2257 if (GET_CODE (XEXP (x, 0)) == CONST
2258 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2261 gen_rtx_combine (LO_SUM, Pmode,
2262 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2264 return &XEXP (XEXP (x, 0), 0);
2268 /* If we have a PLUS whose second operand is a constant and the
2269 address is not valid, perhaps will can split it up using
2270 the machine-specific way to split large constants. We use
2271 the first psuedo-reg (one of the virtual regs) as a placeholder;
2272 it will not remain in the result. */
2273 if (GET_CODE (XEXP (x, 0)) == PLUS
2274 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2275 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2277 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2278 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
2281 /* This should have produced two insns, each of which sets our
2282 placeholder. If the source of the second is a valid address,
2283 we can make put both sources together and make a split point
2286 if (seq && XVECLEN (seq, 0) == 2
2287 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2288 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2289 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2290 && ! reg_mentioned_p (reg,
2291 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2292 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2293 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2294 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2295 && memory_address_p (GET_MODE (x),
2296 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2298 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2299 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2301 /* Replace the placeholder in SRC2 with SRC1. If we can
2302 find where in SRC2 it was placed, that can become our
2303 split point and we can replace this address with SRC2.
2304 Just try two obvious places. */
2306 src2 = replace_rtx (src2, reg, src1);
2308 if (XEXP (src2, 0) == src1)
2309 split = &XEXP (src2, 0);
2310 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2311 && XEXP (XEXP (src2, 0), 0) == src1)
2312 split = &XEXP (XEXP (src2, 0), 0);
2316 SUBST (XEXP (x, 0), src2);
2321 /* If that didn't work, perhaps the first operand is complex and
2322 needs to be computed separately, so make a split point there.
2323 This will occur on machines that just support REG + CONST
2324 and have a constant moved through some previous computation. */
2326 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2327 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2328 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2330 return &XEXP (XEXP (x, 0), 0);
2336 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2337 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2338 we need to put the operand into a register. So split at that
2341 if (SET_DEST (x) == cc0_rtx
2342 && GET_CODE (SET_SRC (x)) != COMPARE
2343 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2344 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2345 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2346 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2347 return &SET_SRC (x);
2350 /* See if we can split SET_SRC as it stands. */
2351 split = find_split_point (&SET_SRC (x), insn);
2352 if (split && split != &SET_SRC (x))
2355 /* See if this is a bitfield assignment with everything constant. If
2356 so, this is an IOR of an AND, so split it into that. */
2357 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2358 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2359 <= HOST_BITS_PER_WIDE_INT)
2360 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2361 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2362 && GET_CODE (SET_SRC (x)) == CONST_INT
2363 && ((INTVAL (XEXP (SET_DEST (x), 1))
2364 + INTVAL (XEXP (SET_DEST (x), 2)))
2365 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2366 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2368 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2369 int len = INTVAL (XEXP (SET_DEST (x), 1));
2370 int src = INTVAL (SET_SRC (x));
2371 rtx dest = XEXP (SET_DEST (x), 0);
2372 enum machine_mode mode = GET_MODE (dest);
2373 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2376 pos = GET_MODE_BITSIZE (mode) - len - pos;
2381 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2384 gen_binary (IOR, mode,
2385 gen_binary (AND, mode, dest,
2386 GEN_INT (~ (mask << pos)
2387 & GET_MODE_MASK (mode))),
2388 GEN_INT (src << pos)));
2390 SUBST (SET_DEST (x), dest);
2392 split = find_split_point (&SET_SRC (x), insn);
2393 if (split && split != &SET_SRC (x))
2397 /* Otherwise, see if this is an operation that we can split into two.
2398 If so, try to split that. */
2399 code = GET_CODE (SET_SRC (x));
2404 /* If we are AND'ing with a large constant that is only a single
2405 bit and the result is only being used in a context where we
2406 need to know if it is zero or non-zero, replace it with a bit
2407 extraction. This will avoid the large constant, which might
2408 have taken more than one insn to make. If the constant were
2409 not a valid argument to the AND but took only one insn to make,
2410 this is no worse, but if it took more than one insn, it will
2413 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2414 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2415 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2416 && GET_CODE (SET_DEST (x)) == REG
2417 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2418 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2419 && XEXP (*split, 0) == SET_DEST (x)
2420 && XEXP (*split, 1) == const0_rtx)
2423 make_extraction (GET_MODE (SET_DEST (x)),
2424 XEXP (SET_SRC (x), 0),
2425 pos, NULL_RTX, 1, 1, 0, 0));
2426 return find_split_point (loc, insn);
2431 inner = XEXP (SET_SRC (x), 0);
2433 len = GET_MODE_BITSIZE (GET_MODE (inner));
2439 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2440 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2442 inner = XEXP (SET_SRC (x), 0);
2443 len = INTVAL (XEXP (SET_SRC (x), 1));
2444 pos = INTVAL (XEXP (SET_SRC (x), 2));
2447 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2449 unsignedp = (code == ZERO_EXTRACT);
2454 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2456 enum machine_mode mode = GET_MODE (SET_SRC (x));
2458 /* For unsigned, we have a choice of a shift followed by an
2459 AND or two shifts. Use two shifts for field sizes where the
2460 constant might be too large. We assume here that we can
2461 always at least get 8-bit constants in an AND insn, which is
2462 true for every current RISC. */
2464 if (unsignedp && len <= 8)
2469 gen_rtx_combine (LSHIFTRT, mode,
2470 gen_lowpart_for_combine (mode, inner),
2472 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2474 split = find_split_point (&SET_SRC (x), insn);
2475 if (split && split != &SET_SRC (x))
2482 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2483 gen_rtx_combine (ASHIFT, mode,
2484 gen_lowpart_for_combine (mode, inner),
2485 GEN_INT (GET_MODE_BITSIZE (mode)
2487 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2489 split = find_split_point (&SET_SRC (x), insn);
2490 if (split && split != &SET_SRC (x))
2495 /* See if this is a simple operation with a constant as the second
2496 operand. It might be that this constant is out of range and hence
2497 could be used as a split point. */
2498 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2499 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2500 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2501 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2502 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2503 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2504 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2506 return &XEXP (SET_SRC (x), 1);
2508 /* Finally, see if this is a simple operation with its first operand
2509 not in a register. The operation might require this operand in a
2510 register, so return it as a split point. We can always do this
2511 because if the first operand were another operation, we would have
2512 already found it as a split point. */
2513 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2514 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2515 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2516 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2517 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2518 return &XEXP (SET_SRC (x), 0);
2524 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2525 it is better to write this as (not (ior A B)) so we can split it.
2526 Similarly for IOR. */
2527 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2530 gen_rtx_combine (NOT, GET_MODE (x),
2531 gen_rtx_combine (code == IOR ? AND : IOR,
2533 XEXP (XEXP (x, 0), 0),
2534 XEXP (XEXP (x, 1), 0))));
2535 return find_split_point (loc, insn);
2538 /* Many RISC machines have a large set of logical insns. If the
2539 second operand is a NOT, put it first so we will try to split the
2540 other operand first. */
2541 if (GET_CODE (XEXP (x, 1)) == NOT)
2543 rtx tem = XEXP (x, 0);
2544 SUBST (XEXP (x, 0), XEXP (x, 1));
2545 SUBST (XEXP (x, 1), tem);
2550 /* Otherwise, select our actions depending on our rtx class. */
2551 switch (GET_RTX_CLASS (code))
2553 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2555 split = find_split_point (&XEXP (x, 2), insn);
2558 /* ... fall through ... */
2562 split = find_split_point (&XEXP (x, 1), insn);
2565 /* ... fall through ... */
2567 /* Some machines have (and (shift ...) ...) insns. If X is not
2568 an AND, but XEXP (X, 0) is, use it as our split point. */
2569 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2570 return &XEXP (x, 0);
2572 split = find_split_point (&XEXP (x, 0), insn);
2578 /* Otherwise, we don't have a split point. */
2582 /* Throughout X, replace FROM with TO, and return the result.
2583 The result is TO if X is FROM;
2584 otherwise the result is X, but its contents may have been modified.
2585 If they were modified, a record was made in undobuf so that
2586 undo_all will (among other things) return X to its original state.
2588 If the number of changes necessary is too much to record to undo,
2589 the excess changes are not made, so the result is invalid.
2590 The changes already made can still be undone.
2591 undobuf.num_undo is incremented for such changes, so by testing that
2592 the caller can tell whether the result is valid.
2594 `n_occurrences' is incremented each time FROM is replaced.
2596 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2598 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2599 by copying if `n_occurrences' is non-zero. */
2602 subst (x, from, to, in_dest, unique_copy)
2603 register rtx x, from, to;
2608 register int len, i;
2609 register enum rtx_code code = GET_CODE (x), orig_code = code;
2611 enum machine_mode mode = GET_MODE (x);
2612 enum machine_mode op0_mode = VOIDmode;
2617 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2618 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2619 If it is 0, that cannot be done. We can now do this for any MEM
2620 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2621 If not for that, MEM's would very rarely be safe. */
2623 /* Reject MODEs bigger than a word, because we might not be able
2624 to reference a two-register group starting with an arbitrary register
2625 (and currently gen_lowpart might crash for a SUBREG). */
2627 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2628 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2630 /* Two expressions are equal if they are identical copies of a shared
2631 RTX or if they are both registers with the same register number
2634 #define COMBINE_RTX_EQUAL_P(X,Y) \
2636 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2637 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2639 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2642 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2645 /* If X and FROM are the same register but different modes, they will
2646 not have been seen as equal above. However, flow.c will make a
2647 LOG_LINKS entry for that case. If we do nothing, we will try to
2648 rerecognize our original insn and, when it succeeds, we will
2649 delete the feeding insn, which is incorrect.
2651 So force this insn not to match in this (rare) case. */
2652 if (! in_dest && code == REG && GET_CODE (from) == REG
2653 && REGNO (x) == REGNO (from))
2654 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2656 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2657 of which may contain things that can be combined. */
2658 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2661 /* It is possible to have a subexpression appear twice in the insn.
2662 Suppose that FROM is a register that appears within TO.
2663 Then, after that subexpression has been scanned once by `subst',
2664 the second time it is scanned, TO may be found. If we were
2665 to scan TO here, we would find FROM within it and create a
2666 self-referent rtl structure which is completely wrong. */
2667 if (COMBINE_RTX_EQUAL_P (x, to))
2670 len = GET_RTX_LENGTH (code);
2671 fmt = GET_RTX_FORMAT (code);
2673 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2674 set up to skip this common case. All other cases where we want to
2675 suppress replacing something inside a SET_SRC are handled via the
2678 && (GET_CODE (SET_DEST (x)) == REG
2679 || GET_CODE (SET_DEST (x)) == CC0
2680 || GET_CODE (SET_DEST (x)) == PC))
2683 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2685 op0_mode = GET_MODE (XEXP (x, 0));
2687 for (i = 0; i < len; i++)
2692 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2695 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2697 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2702 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2704 /* If this substitution failed, this whole thing fails. */
2705 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2709 SUBST (XVECEXP (x, i, j), new);
2712 else if (fmt[i] == 'e')
2716 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2718 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2722 /* If we are in a SET_DEST, suppress most cases unless we
2723 have gone inside a MEM, in which case we want to
2724 simplify the address. We assume here that things that
2725 are actually part of the destination have their inner
2726 parts in the first expression. This is true for SUBREG,
2727 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2728 things aside from REG and MEM that should appear in a
2730 new = subst (XEXP (x, i), from, to,
2732 && (code == SUBREG || code == STRICT_LOW_PART
2733 || code == ZERO_EXTRACT))
2735 && i == 0), unique_copy);
2737 /* If we found that we will have to reject this combination,
2738 indicate that by returning the CLOBBER ourselves, rather than
2739 an expression containing it. This will speed things up as
2740 well as prevent accidents where two CLOBBERs are considered
2741 to be equal, thus producing an incorrect simplification. */
2743 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2746 SUBST (XEXP (x, i), new);
2750 /* We come back to here if we have replaced the expression with one of
2751 a different code and it is likely that further simplification will be
2756 /* If we have restarted more than 4 times, we are probably looping, so
2758 if (++n_restarts > 4)
2761 /* If we are restarting at all, it means that we no longer know the
2762 original mode of operand 0 (since we have probably changed the
2766 op0_mode = VOIDmode;
2768 code = GET_CODE (x);
2770 /* If this is a commutative operation, put a constant last and a complex
2771 expression first. We don't need to do this for comparisons here. */
2772 if (GET_RTX_CLASS (code) == 'c'
2773 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2774 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2775 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2776 || (GET_CODE (XEXP (x, 0)) == SUBREG
2777 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2778 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2781 SUBST (XEXP (x, 0), XEXP (x, 1));
2782 SUBST (XEXP (x, 1), temp);
2785 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
2786 sign extension of a PLUS with a constant, reverse the order of the sign
2787 extension and the addition. Note that this not the same as the original
2788 code, but overflow is undefined for signed values. Also note that the
2789 PLUS will have been partially moved "inside" the sign-extension, so that
2790 the first operand of X will really look like:
2791 (ashiftrt (plus (ashift A C4) C5) C4).
2793 (plus (ashiftrt (ashift A C4) C2) C4)
2794 and replace the first operand of X with that expression. Later parts
2795 of this function may simplify the expression further.
2797 For example, if we start with (mult (sign_extend (plus A C1)) C2),
2798 we swap the SIGN_EXTEND and PLUS. Later code will apply the
2799 distributive law to produce (plus (mult (sign_extend X) C1) C3).
2801 We do this to simplify address expressions. */
2803 if ((code == PLUS || code == MINUS || code == MULT)
2804 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
2805 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
2806 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
2807 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
2808 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2809 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
2810 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2811 && (temp = simplify_binary_operation (ASHIFTRT, mode,
2812 XEXP (XEXP (XEXP (x, 0), 0), 1),
2813 XEXP (XEXP (x, 0), 1))) != 0)
2816 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
2817 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
2818 INTVAL (XEXP (XEXP (x, 0), 1)));
2820 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
2821 INTVAL (XEXP (XEXP (x, 0), 1)));
2823 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
2826 /* If this is a simple operation applied to an IF_THEN_ELSE, try
2827 applying it to the arms of the IF_THEN_ELSE. This often simplifies
2828 things. Don't deal with operations that change modes here. */
2830 if ((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c')
2831 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE)
2833 /* Don't do this by using SUBST inside X since we might be messing
2834 up a shared expression. */
2835 rtx cond = XEXP (XEXP (x, 0), 0);
2836 rtx t_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 1),
2838 pc_rtx, pc_rtx, 0, 0);
2839 rtx f_arm = subst (gen_binary (code, mode, XEXP (XEXP (x, 0), 2),
2841 pc_rtx, pc_rtx, 0, 0);
2844 x = gen_rtx (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2848 else if (GET_RTX_CLASS (code) == '1'
2849 && GET_CODE (XEXP (x, 0)) == IF_THEN_ELSE
2850 && GET_MODE (XEXP (x, 0)) == mode)
2852 rtx cond = XEXP (XEXP (x, 0), 0);
2853 rtx t_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 1)),
2854 pc_rtx, pc_rtx, 0, 0);
2855 rtx f_arm = subst (gen_unary (code, mode, XEXP (XEXP (x, 0), 2)),
2856 pc_rtx, pc_rtx, 0, 0);
2858 x = gen_rtx_combine (IF_THEN_ELSE, mode, cond, t_arm, f_arm);
2862 /* Try to fold this expression in case we have constants that weren't
2865 switch (GET_RTX_CLASS (code))
2868 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2871 temp = simplify_relational_operation (code, op0_mode,
2872 XEXP (x, 0), XEXP (x, 1));
2873 #ifdef FLOAT_STORE_FLAG_VALUE
2874 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2875 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
2876 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
2881 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2885 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2886 XEXP (x, 1), XEXP (x, 2));
2891 x = temp, code = GET_CODE (temp);
2893 /* First see if we can apply the inverse distributive law. */
2894 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2896 x = apply_distributive_law (x);
2897 code = GET_CODE (x);
2900 /* If CODE is an associative operation not otherwise handled, see if we
2901 can associate some operands. This can win if they are constants or
2902 if they are logically related (i.e. (a & b) & a. */
2903 if ((code == PLUS || code == MINUS
2904 || code == MULT || code == AND || code == IOR || code == XOR
2905 || code == DIV || code == UDIV
2906 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2907 && GET_MODE_CLASS (mode) == MODE_INT)
2909 if (GET_CODE (XEXP (x, 0)) == code)
2911 rtx other = XEXP (XEXP (x, 0), 0);
2912 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2913 rtx inner_op1 = XEXP (x, 1);
2916 /* Make sure we pass the constant operand if any as the second
2917 one if this is a commutative operation. */
2918 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2920 rtx tem = inner_op0;
2921 inner_op0 = inner_op1;
2924 inner = simplify_binary_operation (code == MINUS ? PLUS
2925 : code == DIV ? MULT
2926 : code == UDIV ? MULT
2928 mode, inner_op0, inner_op1);
2930 /* For commutative operations, try the other pair if that one
2932 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2934 other = XEXP (XEXP (x, 0), 1);
2935 inner = simplify_binary_operation (code, mode,
2936 XEXP (XEXP (x, 0), 0),
2942 x = gen_binary (code, mode, other, inner);
2949 /* A little bit of algebraic simplification here. */
2953 /* Ensure that our address has any ASHIFTs converted to MULT in case
2954 address-recognizing predicates are called later. */
2955 temp = make_compound_operation (XEXP (x, 0), MEM);
2956 SUBST (XEXP (x, 0), temp);
2960 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2961 is paradoxical. If we can't do that safely, then it becomes
2962 something nonsensical so that this combination won't take place. */
2964 if (GET_CODE (SUBREG_REG (x)) == MEM
2965 && (GET_MODE_SIZE (mode)
2966 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2968 rtx inner = SUBREG_REG (x);
2969 int endian_offset = 0;
2970 /* Don't change the mode of the MEM
2971 if that would change the meaning of the address. */
2972 if (MEM_VOLATILE_P (SUBREG_REG (x))
2973 || mode_dependent_address_p (XEXP (inner, 0)))
2974 return gen_rtx (CLOBBER, mode, const0_rtx);
2976 #if BYTES_BIG_ENDIAN
2977 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2978 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2979 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2980 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2982 /* Note if the plus_constant doesn't make a valid address
2983 then this combination won't be accepted. */
2984 x = gen_rtx (MEM, mode,
2985 plus_constant (XEXP (inner, 0),
2986 (SUBREG_WORD (x) * UNITS_PER_WORD
2988 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2989 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2990 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2994 /* If we are in a SET_DEST, these other cases can't apply. */
2998 /* Changing mode twice with SUBREG => just change it once,
2999 or not at all if changing back to starting mode. */
3000 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3002 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3003 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3004 return SUBREG_REG (SUBREG_REG (x));
3006 SUBST_INT (SUBREG_WORD (x),
3007 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3008 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3011 /* SUBREG of a hard register => just change the register number
3012 and/or mode. If the hard register is not valid in that mode,
3013 suppress this combination. If the hard register is the stack,
3014 frame, or argument pointer, leave this as a SUBREG. */
3016 if (GET_CODE (SUBREG_REG (x)) == REG
3017 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3018 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3019 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3020 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3022 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3024 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3026 return gen_rtx (REG, mode,
3027 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3029 return gen_rtx (CLOBBER, mode, const0_rtx);
3032 /* For a constant, try to pick up the part we want. Handle a full
3033 word and low-order part. Only do this if we are narrowing
3034 the constant; if it is being widened, we have no idea what
3035 the extra bits will have been set to. */
3037 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3038 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3039 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
3040 && GET_MODE_CLASS (mode) == MODE_INT)
3042 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3048 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
3049 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
3050 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3052 /* If we are narrowing the object, we need to see if we can simplify
3053 the expression for the object knowing that we only need the
3056 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
3057 && subreg_lowpart_p (x))
3058 return force_to_mode (SUBREG_REG (x), mode, GET_MODE_BITSIZE (mode),
3063 /* (not (plus X -1)) can become (neg X). */
3064 if (GET_CODE (XEXP (x, 0)) == PLUS
3065 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3067 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3071 /* Similarly, (not (neg X)) is (plus X -1). */
3072 if (GET_CODE (XEXP (x, 0)) == NEG)
3074 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3078 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3079 if (GET_CODE (XEXP (x, 0)) == XOR
3080 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3081 && (temp = simplify_unary_operation (NOT, mode,
3082 XEXP (XEXP (x, 0), 1),
3085 SUBST (XEXP (XEXP (x, 0), 1), temp);
3089 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3090 other than 1, but that is not valid. We could do a similar
3091 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3092 but this doesn't seem common enough to bother with. */
3093 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3094 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3096 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
3097 XEXP (XEXP (x, 0), 1));
3101 if (GET_CODE (XEXP (x, 0)) == SUBREG
3102 && subreg_lowpart_p (XEXP (x, 0))
3103 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3104 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3105 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3106 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3108 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3110 x = gen_rtx (ROTATE, inner_mode,
3111 gen_unary (NOT, inner_mode, const1_rtx),
3112 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3113 x = gen_lowpart_for_combine (mode, x);
3117 #if STORE_FLAG_VALUE == -1
3118 /* (not (comparison foo bar)) can be done by reversing the comparison
3120 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3121 && reversible_comparison_p (XEXP (x, 0)))
3122 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3123 mode, XEXP (XEXP (x, 0), 0),
3124 XEXP (XEXP (x, 0), 1));
3126 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3127 is (lt foo (const_int 0)), so we can perform the above
3130 if (XEXP (x, 1) == const1_rtx
3131 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3132 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3133 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3134 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3137 /* Apply De Morgan's laws to reduce number of patterns for machines
3138 with negating logical insns (and-not, nand, etc.). If result has
3139 only one NOT, put it first, since that is how the patterns are
3142 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3144 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3146 if (GET_CODE (in1) == NOT)
3147 in1 = XEXP (in1, 0);
3149 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3151 if (GET_CODE (in2) == NOT)
3152 in2 = XEXP (in2, 0);
3153 else if (GET_CODE (in2) == CONST_INT
3154 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3155 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3157 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3159 if (GET_CODE (in2) == NOT)
3162 in2 = in1; in1 = tem;
3165 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3172 /* (neg (plus X 1)) can become (not X). */
3173 if (GET_CODE (XEXP (x, 0)) == PLUS
3174 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3176 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3180 /* Similarly, (neg (not X)) is (plus X 1). */
3181 if (GET_CODE (XEXP (x, 0)) == NOT)
3183 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
3187 /* (neg (minus X Y)) can become (minus Y X). */
3188 if (GET_CODE (XEXP (x, 0)) == MINUS
3189 && (GET_MODE_CLASS (mode) != MODE_FLOAT
3190 /* x-y != -(y-x) with IEEE floating point. */
3191 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
3193 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3194 XEXP (XEXP (x, 0), 0));
3198 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3199 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3200 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3202 x = gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3206 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3207 if we can then eliminate the NEG (e.g.,
3208 if the operand is a constant). */
3210 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3212 temp = simplify_unary_operation (NEG, mode,
3213 XEXP (XEXP (x, 0), 0), mode);
3216 SUBST (XEXP (XEXP (x, 0), 0), temp);
3221 temp = expand_compound_operation (XEXP (x, 0));
3223 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3224 replaced by (lshiftrt X C). This will convert
3225 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3227 if (GET_CODE (temp) == ASHIFTRT
3228 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3229 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3231 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3232 INTVAL (XEXP (temp, 1)));
3236 /* If X has only a single bit that might be nonzero, say, bit I, convert
3237 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3238 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3239 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3240 or a SUBREG of one since we'd be making the expression more
3241 complex if it was just a register. */
3243 if (GET_CODE (temp) != REG
3244 && ! (GET_CODE (temp) == SUBREG
3245 && GET_CODE (SUBREG_REG (temp)) == REG)
3246 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3248 rtx temp1 = simplify_shift_const
3249 (NULL_RTX, ASHIFTRT, mode,
3250 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3251 GET_MODE_BITSIZE (mode) - 1 - i),
3252 GET_MODE_BITSIZE (mode) - 1 - i);
3254 /* If all we did was surround TEMP with the two shifts, we
3255 haven't improved anything, so don't use it. Otherwise,
3256 we are better off with TEMP1. */
3257 if (GET_CODE (temp1) != ASHIFTRT
3258 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3259 || XEXP (XEXP (temp1, 0), 0) != temp)
3267 case FLOAT_TRUNCATE:
3268 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3269 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3270 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3271 return XEXP (XEXP (x, 0), 0);
3276 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3277 using cc0, in which case we want to leave it as a COMPARE
3278 so we can distinguish it from a register-register-copy. */
3279 if (XEXP (x, 1) == const0_rtx)
3282 /* In IEEE floating point, x-0 is not the same as x. */
3283 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3284 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
3285 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3291 /* (const (const X)) can become (const X). Do it this way rather than
3292 returning the inner CONST since CONST can be shared with a
3294 if (GET_CODE (XEXP (x, 0)) == CONST)
3295 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3300 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3301 can add in an offset. find_split_point will split this address up
3302 again if it doesn't match. */
3303 if (GET_CODE (XEXP (x, 0)) == HIGH
3304 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3310 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3311 outermost. That's because that's the way indexed addresses are
3312 supposed to appear. This code used to check many more cases, but
3313 they are now checked elsewhere. */
3314 if (GET_CODE (XEXP (x, 0)) == PLUS
3315 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3316 return gen_binary (PLUS, mode,
3317 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3319 XEXP (XEXP (x, 0), 1));
3321 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3322 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3323 bit-field and can be replaced by either a sign_extend or a
3324 sign_extract. The `and' may be a zero_extend. */
3325 if (GET_CODE (XEXP (x, 0)) == XOR
3326 && GET_CODE (XEXP (x, 1)) == CONST_INT
3327 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3328 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3329 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3330 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3331 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3332 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3333 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3334 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3335 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3336 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3339 x = simplify_shift_const
3340 (NULL_RTX, ASHIFTRT, mode,
3341 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3342 XEXP (XEXP (XEXP (x, 0), 0), 0),
3343 GET_MODE_BITSIZE (mode) - (i + 1)),
3344 GET_MODE_BITSIZE (mode) - (i + 1));
3348 /* If only the low-order bit of X is possible nonzero, (plus x -1)
3349 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3350 the bitsize of the mode - 1. This allows simplification of
3351 "a = (b & 8) == 0;" */
3352 if (XEXP (x, 1) == constm1_rtx
3353 && GET_CODE (XEXP (x, 0)) != REG
3354 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3355 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3356 && nonzero_bits (XEXP (x, 0), mode) == 1)
3358 x = simplify_shift_const
3359 (NULL_RTX, ASHIFTRT, mode,
3360 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3361 gen_rtx_combine (XOR, mode,
3362 XEXP (x, 0), const1_rtx),
3363 GET_MODE_BITSIZE (mode) - 1),
3364 GET_MODE_BITSIZE (mode) - 1);
3368 /* If we are adding two things that have no bits in common, convert
3369 the addition into an IOR. This will often be further simplified,
3370 for example in cases like ((a & 1) + (a & 2)), which can
3373 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3374 && (nonzero_bits (XEXP (x, 0), mode)
3375 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3377 x = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3383 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3384 (and <foo> (const_int pow2-1)) */
3385 if (GET_CODE (XEXP (x, 1)) == AND
3386 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3387 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3388 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3390 x = simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3391 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3397 /* If we have (mult (plus A B) C), apply the distributive law and then
3398 the inverse distributive law to see if things simplify. This
3399 occurs mostly in addresses, often when unrolling loops. */
3401 if (GET_CODE (XEXP (x, 0)) == PLUS)
3403 x = apply_distributive_law
3404 (gen_binary (PLUS, mode,
3405 gen_binary (MULT, mode,
3406 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3407 gen_binary (MULT, mode,
3408 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3410 if (GET_CODE (x) != MULT)
3414 /* If this is multiplication by a power of two and its first operand is
3415 a shift, treat the multiply as a shift to allow the shifts to
3416 possibly combine. */
3417 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3418 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3419 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3420 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3421 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3422 || GET_CODE (XEXP (x, 0)) == ROTATE
3423 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3425 x = simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0), i);
3429 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
3430 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3431 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3432 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
3433 XEXP (XEXP (x, 0), 1));
3437 /* If this is a divide by a power of two, treat it as a shift if
3438 its first operand is a shift. */
3439 if (GET_CODE (XEXP (x, 1)) == CONST_INT
3440 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
3441 && (GET_CODE (XEXP (x, 0)) == ASHIFT
3442 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
3443 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
3444 || GET_CODE (XEXP (x, 0)) == ROTATE
3445 || GET_CODE (XEXP (x, 0)) == ROTATERT))
3447 x = simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
3453 case GT: case GTU: case GE: case GEU:
3454 case LT: case LTU: case LE: case LEU:
3455 /* If the first operand is a condition code, we can't do anything
3457 if (GET_CODE (XEXP (x, 0)) == COMPARE
3458 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3460 && XEXP (x, 0) != cc0_rtx
3464 rtx op0 = XEXP (x, 0);
3465 rtx op1 = XEXP (x, 1);
3466 enum rtx_code new_code;
3468 if (GET_CODE (op0) == COMPARE)
3469 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3471 /* Simplify our comparison, if possible. */
3472 new_code = simplify_comparison (code, &op0, &op1);
3474 #if STORE_FLAG_VALUE == 1
3475 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3476 if only the low-order bit is possibly nonzero in X (such as when
3477 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3478 EQ to (xor X 1). Remove any ZERO_EXTRACT we made when thinking
3479 this was a comparison. It may now be simpler to use, e.g., an
3480 AND. If a ZERO_EXTRACT is indeed appropriate, it will
3481 be placed back by the call to make_compound_operation in the
3483 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3484 && op1 == const0_rtx
3485 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3486 return gen_lowpart_for_combine (mode,
3487 expand_compound_operation (op0));
3488 else if (new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
3489 && op1 == const0_rtx
3490 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3492 op0 = expand_compound_operation (op0);
3494 x = gen_rtx_combine (XOR, mode,
3495 gen_lowpart_for_combine (mode, op0),
3501 #if STORE_FLAG_VALUE == -1
3502 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3503 to (neg x) if only the low-order bit of X can be nonzero.
3504 This converts (ne (zero_extract X 1 Y) 0) to
3505 (sign_extract X 1 Y). */
3506 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3507 && op1 == const0_rtx
3508 && nonzero_bits (op0, GET_MODE (op0)) == 1)
3510 op0 = expand_compound_operation (op0);
3511 x = gen_rtx_combine (NEG, mode,
3512 gen_lowpart_for_combine (mode, op0));
3517 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3518 one bit that might be nonzero, we can convert (ne x 0) to
3519 (ashift x c) where C puts the bit in the sign bit. Remove any
3520 AND with STORE_FLAG_VALUE when we are done, since we are only
3521 going to test the sign bit. */
3522 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
3523 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3524 && (STORE_FLAG_VALUE
3525 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
3526 && op1 == const0_rtx
3527 && mode == GET_MODE (op0)
3528 && (i = exact_log2 (nonzero_bits (op0, GET_MODE (op0)))) >= 0)
3530 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3531 expand_compound_operation (op0),
3532 GET_MODE_BITSIZE (mode) - 1 - i);
3533 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3539 /* If the code changed, return a whole new comparison. */
3540 if (new_code != code)
3541 return gen_rtx_combine (new_code, mode, op0, op1);
3543 /* Otherwise, keep this operation, but maybe change its operands.
3544 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3545 SUBST (XEXP (x, 0), op0);
3546 SUBST (XEXP (x, 1), op1);
3551 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register
3552 used in it is being compared against certain values. Get the
3553 true and false comparisons and see if that says anything about the
3554 value of each arm. */
3556 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3557 && reversible_comparison_p (XEXP (x, 0))
3558 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG)
3561 rtx from = XEXP (XEXP (x, 0), 0);
3562 enum rtx_code true_code = GET_CODE (XEXP (x, 0));
3563 enum rtx_code false_code = reverse_condition (true_code);
3564 rtx true_val = XEXP (XEXP (x, 0), 1);
3565 rtx false_val = true_val;
3566 rtx true_arm = XEXP (x, 1);
3567 rtx false_arm = XEXP (x, 2);
3570 /* If FALSE_CODE is EQ, swap the codes and arms. */
3572 if (false_code == EQ)
3574 swapped = 1, true_code = EQ, false_code = NE;
3575 true_arm = XEXP (x, 2), false_arm = XEXP (x, 1);
3578 /* If we are comparing against zero and the expression being tested
3579 has only a single bit that might be nonzero, that is its value
3580 when it is not equal to zero. Similarly if it is known to be
3583 if (true_code == EQ && true_val == const0_rtx
3584 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
3585 false_code = EQ, false_val = GEN_INT (nzb);
3586 else if (true_code == EQ && true_val == const0_rtx
3587 && (num_sign_bit_copies (from, GET_MODE (from))
3588 == GET_MODE_BITSIZE (GET_MODE (from))))
3589 false_code = EQ, false_val = constm1_rtx;
3591 /* Now simplify an arm if we know the value of the register
3592 in the branch and it is used in the arm. Be carefull due to
3593 the potential of locally-shared RTL. */
3595 if (reg_mentioned_p (from, true_arm))
3596 true_arm = subst (known_cond (copy_rtx (true_arm), true_code,
3598 pc_rtx, pc_rtx, 0, 0);
3599 if (reg_mentioned_p (from, false_arm))
3600 false_arm = subst (known_cond (copy_rtx (false_arm), false_code,
3602 pc_rtx, pc_rtx, 0, 0);
3604 SUBST (XEXP (x, 1), swapped ? false_arm : true_arm);
3605 SUBST (XEXP (x, 2), swapped ? true_arm : false_arm);
3608 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3609 reversed, do so to avoid needing two sets of patterns for
3610 subtract-and-branch insns. Similarly if we have a constant in that
3611 position or if the third operand is the same as the first operand
3612 of the comparison. */
3614 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3615 && reversible_comparison_p (XEXP (x, 0))
3616 && (XEXP (x, 1) == pc_rtx || GET_CODE (XEXP (x, 1)) == CONST_INT
3617 || rtx_equal_p (XEXP (x, 2), XEXP (XEXP (x, 0), 0))))
3620 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3621 GET_MODE (XEXP (x, 0)),
3622 XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 0), 1)));
3625 SUBST (XEXP (x, 1), XEXP (x, 2));
3626 SUBST (XEXP (x, 2), temp);
3629 /* If the two arms are identical, we don't need the comparison. */
3631 if (rtx_equal_p (XEXP (x, 1), XEXP (x, 2))
3632 && ! side_effects_p (XEXP (x, 0)))
3635 /* Look for cases where we have (abs x) or (neg (abs X)). */
3637 if (GET_MODE_CLASS (mode) == MODE_INT
3638 && GET_CODE (XEXP (x, 2)) == NEG
3639 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 2), 0))
3640 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3641 && rtx_equal_p (XEXP (x, 1), XEXP (XEXP (x, 0), 0))
3642 && ! side_effects_p (XEXP (x, 1)))
3643 switch (GET_CODE (XEXP (x, 0)))
3647 x = gen_unary (ABS, mode, XEXP (x, 1));
3651 x = gen_unary (NEG, mode, gen_unary (ABS, mode, XEXP (x, 1)));
3655 /* Look for MIN or MAX. */
3657 if (GET_MODE_CLASS (mode) == MODE_INT
3658 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3659 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3660 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 2))
3661 && ! side_effects_p (XEXP (x, 0)))
3662 switch (GET_CODE (XEXP (x, 0)))
3666 x = gen_binary (SMAX, mode, XEXP (x, 1), XEXP (x, 2));
3670 x = gen_binary (SMIN, mode, XEXP (x, 1), XEXP (x, 2));
3674 x = gen_binary (UMAX, mode, XEXP (x, 1), XEXP (x, 2));
3678 x = gen_binary (UMIN, mode, XEXP (x, 1), XEXP (x, 2));
3682 /* If we have something like (if_then_else (ne A 0) (OP X C) X),
3683 A is known to be either 0 or 1, and OP is an identity when its
3684 second operand is zero, this can be done as (OP X (mult A C)).
3685 Similarly if A is known to be 0 or -1 and also similarly if we have
3686 a ZERO_EXTEND or SIGN_EXTEND as long as X is already extended (so
3687 we don't destroy it). */
3689 if (mode != VOIDmode
3690 && (GET_CODE (XEXP (x, 0)) == EQ || GET_CODE (XEXP (x, 0)) == NE)
3691 && XEXP (XEXP (x, 0), 1) == const0_rtx
3692 && (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3693 || (num_sign_bit_copies (XEXP (XEXP (x, 0), 0), mode)
3694 == GET_MODE_BITSIZE (mode))))
3696 rtx nz = make_compound_operation (GET_CODE (XEXP (x, 0)) == NE
3697 ? XEXP (x, 1) : XEXP (x, 2));
3698 rtx z = GET_CODE (XEXP (x, 0)) == NE ? XEXP (x, 2) : XEXP (x, 1);
3699 rtx dir = (nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1
3700 ? const1_rtx : constm1_rtx);
3702 enum machine_mode m = mode;
3703 enum rtx_code op, extend_op = 0;
3705 if ((GET_CODE (nz) == PLUS || GET_CODE (nz) == MINUS
3706 || GET_CODE (nz) == IOR || GET_CODE (nz) == XOR
3707 || GET_CODE (nz) == ASHIFT
3708 || GET_CODE (nz) == LSHIFTRT || GET_CODE (nz) == ASHIFTRT)
3709 && rtx_equal_p (XEXP (nz, 0), z))
3710 c = XEXP (nz, 1), op = GET_CODE (nz);
3711 else if (GET_CODE (nz) == SIGN_EXTEND
3712 && (GET_CODE (XEXP (nz, 0)) == PLUS
3713 || GET_CODE (XEXP (nz, 0)) == MINUS
3714 || GET_CODE (XEXP (nz, 0)) == IOR
3715 || GET_CODE (XEXP (nz, 0)) == XOR
3716 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3717 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3718 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3719 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3720 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3721 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3722 && (num_sign_bit_copies (z, GET_MODE (z))
3723 >= (GET_MODE_BITSIZE (mode)
3724 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (nz, 0), 0))))))
3726 c = XEXP (XEXP (nz, 0), 1);
3727 op = GET_CODE (XEXP (nz, 0));
3728 extend_op = SIGN_EXTEND;
3729 m = GET_MODE (XEXP (nz, 0));
3731 else if (GET_CODE (nz) == ZERO_EXTEND
3732 && (GET_CODE (XEXP (nz, 0)) == PLUS
3733 || GET_CODE (XEXP (nz, 0)) == MINUS
3734 || GET_CODE (XEXP (nz, 0)) == IOR
3735 || GET_CODE (XEXP (nz, 0)) == XOR
3736 || GET_CODE (XEXP (nz, 0)) == ASHIFT
3737 || GET_CODE (XEXP (nz, 0)) == LSHIFTRT
3738 || GET_CODE (XEXP (nz, 0)) == ASHIFTRT)
3739 && GET_CODE (XEXP (XEXP (nz, 0), 0)) == SUBREG
3740 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3741 && subreg_lowpart_p (XEXP (XEXP (nz, 0), 0))
3742 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (nz, 0), 0)), z)
3743 && ((nonzero_bits (z, GET_MODE (z))
3744 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (nz, 0), 0))))
3747 c = XEXP (XEXP (nz, 0), 1);
3748 op = GET_CODE (XEXP (nz, 0));
3749 extend_op = ZERO_EXTEND;
3750 m = GET_MODE (XEXP (nz, 0));
3753 if (c && ! side_effects_p (c) && ! side_effects_p (z))
3756 = gen_binary (MULT, m,
3757 gen_lowpart_for_combine (m,
3758 XEXP (XEXP (x, 0), 0)),
3759 gen_binary (MULT, m, c, dir));
3761 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
3764 temp = gen_unary (extend_op, mode, temp);
3775 /* If we are processing SET_DEST, we are done. */
3779 x = expand_compound_operation (x);
3780 if (GET_CODE (x) != code)
3785 /* (set (pc) (return)) gets written as (return). */
3786 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3789 /* Convert this into a field assignment operation, if possible. */
3790 x = make_field_assignment (x);
3792 /* If we are setting CC0 or if the source is a COMPARE, look for the
3793 use of the comparison result and try to simplify it unless we already
3794 have used undobuf.other_insn. */
3795 if ((GET_CODE (SET_SRC (x)) == COMPARE
3797 || SET_DEST (x) == cc0_rtx
3800 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3802 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3803 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3804 && XEXP (*cc_use, 0) == SET_DEST (x))
3806 enum rtx_code old_code = GET_CODE (*cc_use);
3807 enum rtx_code new_code;
3809 int other_changed = 0;
3810 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3812 if (GET_CODE (SET_SRC (x)) == COMPARE)
3813 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3815 op0 = SET_SRC (x), op1 = const0_rtx;
3817 /* Simplify our comparison, if possible. */
3818 new_code = simplify_comparison (old_code, &op0, &op1);
3820 #ifdef EXTRA_CC_MODES
3821 /* If this machine has CC modes other than CCmode, check to see
3822 if we need to use a different CC mode here. */
3823 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
3824 #endif /* EXTRA_CC_MODES */
3826 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3827 /* If the mode changed, we have to change SET_DEST, the mode
3828 in the compare, and the mode in the place SET_DEST is used.
3829 If SET_DEST is a hard register, just build new versions with
3830 the proper mode. If it is a pseudo, we lose unless it is only
3831 time we set the pseudo, in which case we can safely change
3833 if (compare_mode != GET_MODE (SET_DEST (x)))
3835 int regno = REGNO (SET_DEST (x));
3836 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3838 if (regno < FIRST_PSEUDO_REGISTER
3839 || (reg_n_sets[regno] == 1
3840 && ! REG_USERVAR_P (SET_DEST (x))))
3842 if (regno >= FIRST_PSEUDO_REGISTER)
3843 SUBST (regno_reg_rtx[regno], new_dest);
3845 SUBST (SET_DEST (x), new_dest);
3846 SUBST (XEXP (*cc_use, 0), new_dest);
3852 /* If the code changed, we have to build a new comparison
3853 in undobuf.other_insn. */
3854 if (new_code != old_code)
3856 unsigned HOST_WIDE_INT mask;
3858 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3859 SET_DEST (x), const0_rtx));
3861 /* If the only change we made was to change an EQ into an
3862 NE or vice versa, OP0 has only one bit that might be nonzero,
3863 and OP1 is zero, check if changing the user of the condition
3864 code will produce a valid insn. If it won't, we can keep
3865 the original code in that insn by surrounding our operation
3868 if (((old_code == NE && new_code == EQ)
3869 || (old_code == EQ && new_code == NE))
3870 && ! other_changed && op1 == const0_rtx
3871 && (GET_MODE_BITSIZE (GET_MODE (op0))
3872 <= HOST_BITS_PER_WIDE_INT)
3873 && (exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0)))
3876 rtx pat = PATTERN (other_insn), note = 0;
3878 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
3879 && ! check_asm_operands (pat)))
3881 PUT_CODE (*cc_use, old_code);
3884 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3893 undobuf.other_insn = other_insn;
3896 /* If we are now comparing against zero, change our source if
3897 needed. If we do not use cc0, we always have a COMPARE. */
3898 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3899 SUBST (SET_SRC (x), op0);
3903 /* Otherwise, if we didn't previously have a COMPARE in the
3904 correct mode, we need one. */
3905 if (GET_CODE (SET_SRC (x)) != COMPARE
3906 || GET_MODE (SET_SRC (x)) != compare_mode)
3907 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3911 /* Otherwise, update the COMPARE if needed. */
3912 SUBST (XEXP (SET_SRC (x), 0), op0);
3913 SUBST (XEXP (SET_SRC (x), 1), op1);
3918 /* Get SET_SRC in a form where we have placed back any
3919 compound expressions. Then do the checks below. */
3920 temp = make_compound_operation (SET_SRC (x), SET);
3921 SUBST (SET_SRC (x), temp);
3924 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3925 operation, and X being a REG or (subreg (reg)), we may be able to
3926 convert this to (set (subreg:m2 x) (op)).
3928 We can always do this if M1 is narrower than M2 because that
3929 means that we only care about the low bits of the result.
3931 However, on most machines (those with neither BYTE_LOADS_ZERO_EXTEND
3932 nor BYTES_LOADS_SIGN_EXTEND defined), we cannot perform a
3933 narrower operation that requested since the high-order bits will
3934 be undefined. On machine where BYTE_LOADS_*_EXTEND is defined,
3935 however, this transformation is safe as long as M1 and M2 have
3936 the same number of words. */
3938 if (GET_CODE (SET_SRC (x)) == SUBREG
3939 && subreg_lowpart_p (SET_SRC (x))
3940 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3941 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3943 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3944 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3945 #ifndef BYTE_LOADS_EXTEND
3946 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3947 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3949 && (GET_CODE (SET_DEST (x)) == REG
3950 || (GET_CODE (SET_DEST (x)) == SUBREG
3951 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3953 SUBST (SET_DEST (x),
3954 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_SRC (x))),
3956 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3959 #ifdef BYTE_LOADS_EXTEND
3960 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3961 M wider than N, this would require a paradoxical subreg.
3962 Replace the subreg with a zero_extend to avoid the reload that
3963 would otherwise be required. */
3965 if (GET_CODE (SET_SRC (x)) == SUBREG
3966 && subreg_lowpart_p (SET_SRC (x))
3967 && SUBREG_WORD (SET_SRC (x)) == 0
3968 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3969 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3970 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3971 SUBST (SET_SRC (x), gen_rtx_combine (LOAD_EXTEND,
3972 GET_MODE (SET_SRC (x)),
3973 XEXP (SET_SRC (x), 0)));
3976 #ifndef HAVE_conditional_move
3978 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE,
3979 and we are comparing an item known to be 0 or -1 against 0, use a
3980 logical operation instead. Check for one of the arms being an IOR
3981 of the other arm with some value. We compute three terms to be
3982 IOR'ed together. In practice, at most two will be nonzero. Then
3985 if (GET_CODE (SET_DEST (x)) != PC
3986 && GET_CODE (SET_SRC (x)) == IF_THEN_ELSE
3987 && (GET_CODE (XEXP (SET_SRC (x), 0)) == EQ
3988 || GET_CODE (XEXP (SET_SRC (x), 0)) == NE)
3989 && XEXP (XEXP (SET_SRC (x), 0), 1) == const0_rtx
3990 && (num_sign_bit_copies (XEXP (XEXP (SET_SRC (x), 0), 0),
3991 GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0)))
3992 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (SET_SRC (x), 0), 0))))
3993 && ! side_effects_p (SET_SRC (x)))
3995 rtx true = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3996 ? XEXP (SET_SRC (x), 1) : XEXP (SET_SRC (x), 2));
3997 rtx false = (GET_CODE (XEXP (SET_SRC (x), 0)) == NE
3998 ? XEXP (SET_SRC (x), 2) : XEXP (SET_SRC (x), 1));
3999 rtx term1 = const0_rtx, term2, term3;
4001 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4002 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4003 else if (GET_CODE (true) == IOR
4004 && rtx_equal_p (XEXP (true, 1), false))
4005 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4006 else if (GET_CODE (false) == IOR
4007 && rtx_equal_p (XEXP (false, 0), true))
4008 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4009 else if (GET_CODE (false) == IOR
4010 && rtx_equal_p (XEXP (false, 1), true))
4011 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4013 term2 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4014 XEXP (XEXP (SET_SRC (x), 0), 0), true);
4015 term3 = gen_binary (AND, GET_MODE (SET_SRC (x)),
4016 gen_unary (NOT, GET_MODE (SET_SRC (x)),
4017 XEXP (XEXP (SET_SRC (x), 0), 0)),
4021 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4022 gen_binary (IOR, GET_MODE (SET_SRC (x)),
4030 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4032 x = simplify_and_const_int (x, mode, XEXP (x, 0),
4033 INTVAL (XEXP (x, 1)));
4035 /* If we have (ior (and (X C1) C2)) and the next restart would be
4036 the last, simplify this by making C1 as small as possible
4038 if (n_restarts >= 3 && GET_CODE (x) == IOR
4039 && GET_CODE (XEXP (x, 0)) == AND
4040 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4041 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4043 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
4044 GEN_INT (INTVAL (XEXP (XEXP (x, 0), 1))
4045 & ~ INTVAL (XEXP (x, 1))));
4046 return gen_binary (IOR, mode, temp, XEXP (x, 1));
4049 if (GET_CODE (x) != AND)
4053 /* Convert (A | B) & A to A. */
4054 if (GET_CODE (XEXP (x, 0)) == IOR
4055 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4056 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4057 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4058 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4061 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4062 insn (and may simplify more). */
4063 else if (GET_CODE (XEXP (x, 0)) == XOR
4064 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4065 && ! side_effects_p (XEXP (x, 1)))
4067 x = gen_binary (AND, mode,
4068 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4072 else if (GET_CODE (XEXP (x, 0)) == XOR
4073 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4074 && ! side_effects_p (XEXP (x, 1)))
4076 x = gen_binary (AND, mode,
4077 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4082 /* Similarly for (~ (A ^ B)) & A. */
4083 else if (GET_CODE (XEXP (x, 0)) == NOT
4084 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4085 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
4086 && ! side_effects_p (XEXP (x, 1)))
4088 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
4092 else if (GET_CODE (XEXP (x, 0)) == NOT
4093 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
4094 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
4095 && ! side_effects_p (XEXP (x, 1)))
4097 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
4102 /* If we have (and A B) with A not an object but that is known to
4103 be -1 or 0, this is equivalent to the expression
4104 (if_then_else (ne A (const_int 0)) B (const_int 0))
4105 We make this conversion because it may allow further
4106 simplifications and then allow use of conditional move insns.
4107 If the machine doesn't have condition moves, code in case SET
4108 will convert the IF_THEN_ELSE back to the logical operation.
4109 We build the IF_THEN_ELSE here in case further simplification
4110 is possible (e.g., we can convert it to ABS). */
4112 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
4113 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4114 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o')
4115 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4116 == GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4118 rtx op0 = XEXP (x, 0);
4119 rtx op1 = const0_rtx;
4120 enum rtx_code comp_code
4121 = simplify_comparison (NE, &op0, &op1);
4123 x = gen_rtx_combine (IF_THEN_ELSE, mode,
4124 gen_binary (comp_code, VOIDmode, op0, op1),
4125 XEXP (x, 1), const0_rtx);
4129 /* In the following group of tests (and those in case IOR below),
4130 we start with some combination of logical operations and apply
4131 the distributive law followed by the inverse distributive law.
4132 Most of the time, this results in no change. However, if some of
4133 the operands are the same or inverses of each other, simplifications
4136 For example, (and (ior A B) (not B)) can occur as the result of
4137 expanding a bit field assignment. When we apply the distributive
4138 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4139 which then simplifies to (and (A (not B))). */
4141 /* If we have (and (ior A B) C), apply the distributive law and then
4142 the inverse distributive law to see if things simplify. */
4144 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
4146 x = apply_distributive_law
4147 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
4148 gen_binary (AND, mode,
4149 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4150 gen_binary (AND, mode,
4151 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4152 if (GET_CODE (x) != AND)
4156 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
4158 x = apply_distributive_law
4159 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
4160 gen_binary (AND, mode,
4161 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4162 gen_binary (AND, mode,
4163 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4164 if (GET_CODE (x) != AND)
4168 /* Similarly, taking advantage of the fact that
4169 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4171 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
4173 x = apply_distributive_law
4174 (gen_binary (XOR, mode,
4175 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4176 XEXP (XEXP (x, 1), 0)),
4177 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
4178 XEXP (XEXP (x, 1), 1))));
4179 if (GET_CODE (x) != AND)
4183 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
4185 x = apply_distributive_law
4186 (gen_binary (XOR, mode,
4187 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4188 XEXP (XEXP (x, 0), 0)),
4189 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
4190 XEXP (XEXP (x, 0), 1))));
4191 if (GET_CODE (x) != AND)
4197 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4198 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4199 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4200 && (nonzero_bits (XEXP (x, 0), mode) & ~ INTVAL (XEXP (x, 1))) == 0)
4203 /* Convert (A & B) | A to A. */
4204 if (GET_CODE (XEXP (x, 0)) == AND
4205 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4206 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
4207 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
4208 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
4211 /* If we have (ior (and A B) C), apply the distributive law and then
4212 the inverse distributive law to see if things simplify. */
4214 if (GET_CODE (XEXP (x, 0)) == AND)
4216 x = apply_distributive_law
4217 (gen_binary (AND, mode,
4218 gen_binary (IOR, mode,
4219 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4220 gen_binary (IOR, mode,
4221 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4223 if (GET_CODE (x) != IOR)
4227 if (GET_CODE (XEXP (x, 1)) == AND)
4229 x = apply_distributive_law
4230 (gen_binary (AND, mode,
4231 gen_binary (IOR, mode,
4232 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
4233 gen_binary (IOR, mode,
4234 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
4236 if (GET_CODE (x) != IOR)
4240 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
4241 mode size to (rotate A CX). */
4243 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
4244 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
4245 || (GET_CODE (XEXP (x, 1)) == ASHIFT
4246 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
4247 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
4248 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4249 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4250 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
4251 == GET_MODE_BITSIZE (mode)))
4255 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4256 shift_count = XEXP (XEXP (x, 0), 1);
4258 shift_count = XEXP (XEXP (x, 1), 1);
4259 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
4265 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
4266 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
4269 int num_negated = 0;
4270 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
4272 if (GET_CODE (in1) == NOT)
4273 num_negated++, in1 = XEXP (in1, 0);
4274 if (GET_CODE (in2) == NOT)
4275 num_negated++, in2 = XEXP (in2, 0);
4277 if (num_negated == 2)
4279 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4280 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
4282 else if (num_negated == 1)
4284 x = gen_unary (NOT, mode,
4285 gen_binary (XOR, mode, in1, in2));
4290 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
4291 correspond to a machine insn or result in further simplifications
4292 if B is a constant. */
4294 if (GET_CODE (XEXP (x, 0)) == AND
4295 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
4296 && ! side_effects_p (XEXP (x, 1)))
4298 x = gen_binary (AND, mode,
4299 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
4303 else if (GET_CODE (XEXP (x, 0)) == AND
4304 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
4305 && ! side_effects_p (XEXP (x, 1)))
4307 x = gen_binary (AND, mode,
4308 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
4314 #if STORE_FLAG_VALUE == 1
4315 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
4317 if (XEXP (x, 1) == const1_rtx
4318 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4319 && reversible_comparison_p (XEXP (x, 0)))
4320 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4321 mode, XEXP (XEXP (x, 0), 0),
4322 XEXP (XEXP (x, 0), 1));
4324 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
4325 is (lt foo (const_int 0)), so we can perform the above
4328 if (XEXP (x, 1) == const1_rtx
4329 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4330 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4331 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
4332 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
4335 /* (xor (comparison foo bar) (const_int sign-bit))
4336 when STORE_FLAG_VALUE is the sign bit. */
4337 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4338 && (STORE_FLAG_VALUE
4339 == (HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4340 && XEXP (x, 1) == const_true_rtx
4341 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4342 && reversible_comparison_p (XEXP (x, 0)))
4343 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
4344 mode, XEXP (XEXP (x, 0), 0),
4345 XEXP (XEXP (x, 0), 1));
4349 /* (abs (neg <foo>)) -> (abs <foo>) */
4350 if (GET_CODE (XEXP (x, 0)) == NEG)
4351 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4353 /* If operand is something known to be positive, ignore the ABS. */
4354 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4355 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4356 <= HOST_BITS_PER_WIDE_INT)
4357 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4358 & ((HOST_WIDE_INT) 1
4359 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4364 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4365 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4367 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
4373 /* (ffs (*_extend <X>)) = (ffs <X>) */
4374 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4375 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4376 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4380 /* (float (sign_extend <X>)) = (float <X>). */
4381 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4382 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4391 /* If this is a shift by a constant amount, simplify it. */
4392 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4394 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
4395 INTVAL (XEXP (x, 1)));
4396 if (GET_CODE (x) != code)
4400 #ifdef SHIFT_COUNT_TRUNCATED
4401 else if (GET_CODE (XEXP (x, 1)) != REG)
4403 force_to_mode (XEXP (x, 1), GET_MODE (x),
4404 exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))),
4414 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
4415 operations" because they can be replaced with two more basic operations.
4416 ZERO_EXTEND is also considered "compound" because it can be replaced with
4417 an AND operation, which is simpler, though only one operation.
4419 The function expand_compound_operation is called with an rtx expression
4420 and will convert it to the appropriate shifts and AND operations,
4421 simplifying at each stage.
4423 The function make_compound_operation is called to convert an expression
4424 consisting of shifts and ANDs into the equivalent compound expression.
4425 It is the inverse of this function, loosely speaking. */
4428 expand_compound_operation (x)
4436 switch (GET_CODE (x))
4441 /* We can't necessarily use a const_int for a multiword mode;
4442 it depends on implicitly extending the value.
4443 Since we don't know the right way to extend it,
4444 we can't tell whether the implicit way is right.
4446 Even for a mode that is no wider than a const_int,
4447 we can't win, because we need to sign extend one of its bits through
4448 the rest of it, and we don't know which bit. */
4449 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
4452 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
4455 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
4456 /* If the inner object has VOIDmode (the only way this can happen
4457 is if it is a ASM_OPERANDS), we can't do anything since we don't
4458 know how much masking to do. */
4467 /* If the operand is a CLOBBER, just return it. */
4468 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
4471 if (GET_CODE (XEXP (x, 1)) != CONST_INT
4472 || GET_CODE (XEXP (x, 2)) != CONST_INT
4473 || GET_MODE (XEXP (x, 0)) == VOIDmode)
4476 len = INTVAL (XEXP (x, 1));
4477 pos = INTVAL (XEXP (x, 2));
4479 /* If this goes outside the object being extracted, replace the object
4480 with a (use (mem ...)) construct that only combine understands
4481 and is used only for this purpose. */
4482 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4483 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
4486 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
4494 /* If we reach here, we want to return a pair of shifts. The inner
4495 shift is a left shift of BITSIZE - POS - LEN bits. The outer
4496 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
4497 logical depending on the value of UNSIGNEDP.
4499 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
4500 converted into an AND of a shift.
4502 We must check for the case where the left shift would have a negative
4503 count. This can happen in a case like (x >> 31) & 255 on machines
4504 that can't shift by a constant. On those machines, we would first
4505 combine the shift with the AND to produce a variable-position
4506 extraction. Then the constant of 31 would be substituted in to produce
4507 a such a position. */
4509 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
4510 if (modewidth >= pos - len)
4511 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
4513 simplify_shift_const (NULL_RTX, ASHIFT,
4516 modewidth - pos - len),
4519 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
4520 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
4521 simplify_shift_const (NULL_RTX, LSHIFTRT,
4524 ((HOST_WIDE_INT) 1 << len) - 1);
4526 /* Any other cases we can't handle. */
4530 /* If we couldn't do this for some reason, return the original
4532 if (GET_CODE (tem) == CLOBBER)
4538 /* X is a SET which contains an assignment of one object into
4539 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
4540 or certain SUBREGS). If possible, convert it into a series of
4543 We half-heartedly support variable positions, but do not at all
4544 support variable lengths. */
4547 expand_field_assignment (x)
4551 rtx pos; /* Always counts from low bit. */
4554 enum machine_mode compute_mode;
4556 /* Loop until we find something we can't simplify. */
4559 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
4560 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
4562 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
4563 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
4566 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4567 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
4569 inner = XEXP (SET_DEST (x), 0);
4570 len = INTVAL (XEXP (SET_DEST (x), 1));
4571 pos = XEXP (SET_DEST (x), 2);
4573 /* If the position is constant and spans the width of INNER,
4574 surround INNER with a USE to indicate this. */
4575 if (GET_CODE (pos) == CONST_INT
4576 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
4577 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
4580 if (GET_CODE (pos) == CONST_INT)
4581 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
4583 else if (GET_CODE (pos) == MINUS
4584 && GET_CODE (XEXP (pos, 1)) == CONST_INT
4585 && (INTVAL (XEXP (pos, 1))
4586 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
4587 /* If position is ADJUST - X, new position is X. */
4588 pos = XEXP (pos, 0);
4590 pos = gen_binary (MINUS, GET_MODE (pos),
4591 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
4597 /* A SUBREG between two modes that occupy the same numbers of words
4598 can be done by moving the SUBREG to the source. */
4599 else if (GET_CODE (SET_DEST (x)) == SUBREG
4600 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
4601 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
4602 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
4603 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
4605 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
4606 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
4613 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4614 inner = SUBREG_REG (inner);
4616 compute_mode = GET_MODE (inner);
4618 /* Compute a mask of LEN bits, if we can do this on the host machine. */
4619 if (len < HOST_BITS_PER_WIDE_INT)
4620 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
4624 /* Now compute the equivalent expression. Make a copy of INNER
4625 for the SET_DEST in case it is a MEM into which we will substitute;
4626 we don't want shared RTL in that case. */
4627 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
4628 gen_binary (IOR, compute_mode,
4629 gen_binary (AND, compute_mode,
4630 gen_unary (NOT, compute_mode,
4635 gen_binary (ASHIFT, compute_mode,
4636 gen_binary (AND, compute_mode,
4637 gen_lowpart_for_combine
4647 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
4648 it is an RTX that represents a variable starting position; otherwise,
4649 POS is the (constant) starting bit position (counted from the LSB).
4651 INNER may be a USE. This will occur when we started with a bitfield
4652 that went outside the boundary of the object in memory, which is
4653 allowed on most machines. To isolate this case, we produce a USE
4654 whose mode is wide enough and surround the MEM with it. The only
4655 code that understands the USE is this routine. If it is not removed,
4656 it will cause the resulting insn not to match.
4658 UNSIGNEDP is non-zero for an unsigned reference and zero for a
4661 IN_DEST is non-zero if this is a reference in the destination of a
4662 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
4663 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
4666 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
4667 ZERO_EXTRACT should be built even for bits starting at bit 0.
4669 MODE is the desired mode of the result (if IN_DEST == 0). */
4672 make_extraction (mode, inner, pos, pos_rtx, len,
4673 unsignedp, in_dest, in_compare)
4674 enum machine_mode mode;
4680 int in_dest, in_compare;
4682 /* This mode describes the size of the storage area
4683 to fetch the overall value from. Within that, we
4684 ignore the POS lowest bits, etc. */
4685 enum machine_mode is_mode = GET_MODE (inner);
4686 enum machine_mode inner_mode;
4687 enum machine_mode wanted_mem_mode = byte_mode;
4688 enum machine_mode pos_mode = word_mode;
4689 enum machine_mode extraction_mode = word_mode;
4690 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
4693 rtx orig_pos_rtx = pos_rtx;
4695 /* Get some information about INNER and get the innermost object. */
4696 if (GET_CODE (inner) == USE)
4697 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
4698 /* We don't need to adjust the position because we set up the USE
4699 to pretend that it was a full-word object. */
4700 spans_byte = 1, inner = XEXP (inner, 0);
4701 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
4703 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
4704 consider just the QI as the memory to extract from.
4705 The subreg adds or removes high bits; its mode is
4706 irrelevant to the meaning of this extraction,
4707 since POS and LEN count from the lsb. */
4708 if (GET_CODE (SUBREG_REG (inner)) == MEM)
4709 is_mode = GET_MODE (SUBREG_REG (inner));
4710 inner = SUBREG_REG (inner);
4713 inner_mode = GET_MODE (inner);
4715 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
4716 pos = INTVAL (pos_rtx), pos_rtx = 0;
4718 /* See if this can be done without an extraction. We never can if the
4719 width of the field is not the same as that of some integer mode. For
4720 registers, we can only avoid the extraction if the position is at the
4721 low-order bit and this is either not in the destination or we have the
4722 appropriate STRICT_LOW_PART operation available.
4724 For MEM, we can avoid an extract if the field starts on an appropriate
4725 boundary and we can change the mode of the memory reference. However,
4726 we cannot directly access the MEM if we have a USE and the underlying
4727 MEM is not TMODE. This combination means that MEM was being used in a
4728 context where bits outside its mode were being referenced; that is only
4729 valid in bit-field insns. */
4731 if (tmode != BLKmode
4732 && ! (spans_byte && inner_mode != tmode)
4733 && ((pos_rtx == 0 && pos == 0 && GET_CODE (inner) != MEM
4735 || (GET_CODE (inner) == REG
4736 && (movstrict_optab->handlers[(int) tmode].insn_code
4737 != CODE_FOR_nothing))))
4738 || (GET_CODE (inner) == MEM && pos_rtx == 0
4740 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
4741 : BITS_PER_UNIT)) == 0
4742 /* We can't do this if we are widening INNER_MODE (it
4743 may not be aligned, for one thing). */
4744 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
4745 && (inner_mode == tmode
4746 || (! mode_dependent_address_p (XEXP (inner, 0))
4747 && ! MEM_VOLATILE_P (inner))))))
4749 /* If INNER is a MEM, make a new MEM that encompasses just the desired
4750 field. If the original and current mode are the same, we need not
4751 adjust the offset. Otherwise, we do if bytes big endian.
4753 If INNER is not a MEM, get a piece consisting of the just the field
4754 of interest (in this case POS must be 0). */
4756 if (GET_CODE (inner) == MEM)
4759 /* POS counts from lsb, but make OFFSET count in memory order. */
4760 if (BYTES_BIG_ENDIAN)
4761 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
4763 offset = pos / BITS_PER_UNIT;
4765 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4766 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4767 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4768 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4770 else if (GET_CODE (inner) == REG)
4771 /* We can't call gen_lowpart_for_combine here since we always want
4772 a SUBREG and it would sometimes return a new hard register. */
4773 new = gen_rtx (SUBREG, tmode, inner,
4775 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
4776 ? ((GET_MODE_SIZE (inner_mode) - GET_MODE_SIZE (tmode))
4780 new = force_to_mode (inner, tmode, len, NULL_RTX);
4782 /* If this extraction is going into the destination of a SET,
4783 make a STRICT_LOW_PART unless we made a MEM. */
4786 return (GET_CODE (new) == MEM ? new
4787 : (GET_CODE (new) != SUBREG
4788 ? gen_rtx (CLOBBER, tmode, const0_rtx)
4789 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
4791 /* Otherwise, sign- or zero-extend unless we already are in the
4794 return (mode == tmode ? new
4795 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4799 /* Unless this is a COMPARE or we have a funny memory reference,
4800 don't do anything with zero-extending field extracts starting at
4801 the low-order bit since they are simple AND operations. */
4802 if (pos_rtx == 0 && pos == 0 && ! in_dest
4803 && ! in_compare && ! spans_byte && unsignedp)
4806 /* Get the mode to use should INNER be a MEM, the mode for the position,
4807 and the mode for the result. */
4811 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4812 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4813 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4818 if (! in_dest && unsignedp)
4820 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4821 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4822 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4827 if (! in_dest && ! unsignedp)
4829 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4830 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4831 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4835 /* Never narrow an object, since that might not be safe. */
4837 if (mode != VOIDmode
4838 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4839 extraction_mode = mode;
4841 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4842 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4843 pos_mode = GET_MODE (pos_rtx);
4845 /* If this is not from memory or we have to change the mode of memory and
4846 cannot, the desired mode is EXTRACTION_MODE. */
4847 if (GET_CODE (inner) != MEM
4848 || (inner_mode != wanted_mem_mode
4849 && (mode_dependent_address_p (XEXP (inner, 0))
4850 || MEM_VOLATILE_P (inner))))
4851 wanted_mem_mode = extraction_mode;
4854 /* If position is constant, compute new position. Otherwise, build
4857 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4861 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4862 GEN_INT (MAX (GET_MODE_BITSIZE (is_mode),
4863 GET_MODE_BITSIZE (wanted_mem_mode))
4868 /* If INNER has a wider mode, make it smaller. If this is a constant
4869 extract, try to adjust the byte to point to the byte containing
4871 if (wanted_mem_mode != VOIDmode
4872 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4873 && ((GET_CODE (inner) == MEM
4874 && (inner_mode == wanted_mem_mode
4875 || (! mode_dependent_address_p (XEXP (inner, 0))
4876 && ! MEM_VOLATILE_P (inner))))))
4880 /* The computations below will be correct if the machine is big
4881 endian in both bits and bytes or little endian in bits and bytes.
4882 If it is mixed, we must adjust. */
4884 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4885 adjust OFFSET to compensate. */
4886 #if BYTES_BIG_ENDIAN
4888 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4889 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4892 /* If this is a constant position, we can move to the desired byte. */
4895 offset += pos / BITS_PER_UNIT;
4896 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4899 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4900 if (! spans_byte && is_mode != wanted_mem_mode)
4901 offset = (GET_MODE_SIZE (is_mode)
4902 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4905 if (offset != 0 || inner_mode != wanted_mem_mode)
4907 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4908 plus_constant (XEXP (inner, 0), offset));
4909 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4910 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4911 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4916 /* If INNER is not memory, we can always get it into the proper mode. */
4917 else if (GET_CODE (inner) != MEM)
4918 inner = force_to_mode (inner, extraction_mode,
4919 (pos < 0 ? GET_MODE_BITSIZE (extraction_mode)
4923 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4924 have to zero extend. Otherwise, we can just use a SUBREG. */
4926 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4927 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4928 else if (pos_rtx != 0
4929 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4930 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4932 /* Make POS_RTX unless we already have it and it is correct. If we don't
4933 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
4935 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
4936 pos_rtx = orig_pos_rtx;
4938 else if (pos_rtx == 0)
4939 pos_rtx = GEN_INT (pos);
4941 /* Make the required operation. See if we can use existing rtx. */
4942 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4943 extraction_mode, inner, GEN_INT (len), pos_rtx);
4945 new = gen_lowpart_for_combine (mode, new);
4950 /* Look at the expression rooted at X. Look for expressions
4951 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4952 Form these expressions.
4954 Return the new rtx, usually just X.
4956 Also, for machines like the Vax that don't have logical shift insns,
4957 try to convert logical to arithmetic shift operations in cases where
4958 they are equivalent. This undoes the canonicalizations to logical
4959 shifts done elsewhere.
4961 We try, as much as possible, to re-use rtl expressions to save memory.
4963 IN_CODE says what kind of expression we are processing. Normally, it is
4964 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
4965 being kludges), it is MEM. When processing the arguments of a comparison
4966 or a COMPARE against zero, it is COMPARE. */
4969 make_compound_operation (x, in_code)
4971 enum rtx_code in_code;
4973 enum rtx_code code = GET_CODE (x);
4974 enum machine_mode mode = GET_MODE (x);
4975 int mode_width = GET_MODE_BITSIZE (mode);
4976 enum rtx_code next_code;
4982 /* Select the code to be used in recursive calls. Once we are inside an
4983 address, we stay there. If we have a comparison, set to COMPARE,
4984 but once inside, go back to our default of SET. */
4986 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
4987 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4988 && XEXP (x, 1) == const0_rtx) ? COMPARE
4989 : in_code == COMPARE ? SET : in_code);
4991 /* Process depending on the code of this operation. If NEW is set
4992 non-zero, it will be returned. */
4998 /* Convert shifts by constants into multiplications if inside
5000 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5001 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5002 && INTVAL (XEXP (x, 1)) >= 0)
5004 new = make_compound_operation (XEXP (x, 0), next_code);
5005 new = gen_rtx_combine (MULT, mode, new,
5006 GEN_INT ((HOST_WIDE_INT) 1
5007 << INTVAL (XEXP (x, 1))));
5012 /* If the second operand is not a constant, we can't do anything
5014 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5017 /* If the constant is a power of two minus one and the first operand
5018 is a logical right shift, make an extraction. */
5019 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5020 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5022 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5023 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5024 0, in_code == COMPARE);
5027 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5028 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5029 && subreg_lowpart_p (XEXP (x, 0))
5030 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5031 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5033 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5035 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5036 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5037 0, in_code == COMPARE);
5040 /* If we are have (and (rotate X C) M) and C is larger than the number
5041 of bits in M, this is an extraction. */
5043 else if (GET_CODE (XEXP (x, 0)) == ROTATE
5044 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5045 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
5046 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
5048 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5049 new = make_extraction (mode, new,
5050 (GET_MODE_BITSIZE (mode)
5051 - INTVAL (XEXP (XEXP (x, 0), 1))),
5052 NULL_RTX, i, 1, 0, in_code == COMPARE);
5055 /* On machines without logical shifts, if the operand of the AND is
5056 a logical shift and our mask turns off all the propagated sign
5057 bits, we can replace the logical shift with an arithmetic shift. */
5058 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5059 && (lshr_optab->handlers[(int) mode].insn_code
5060 == CODE_FOR_nothing)
5061 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
5062 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5063 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
5064 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
5065 && mode_width <= HOST_BITS_PER_WIDE_INT)
5067 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
5069 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
5070 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
5072 gen_rtx_combine (ASHIFTRT, mode,
5073 make_compound_operation (XEXP (XEXP (x, 0), 0),
5075 XEXP (XEXP (x, 0), 1)));
5078 /* If the constant is one less than a power of two, this might be
5079 representable by an extraction even if no shift is present.
5080 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
5081 we are in a COMPARE. */
5082 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5083 new = make_extraction (mode,
5084 make_compound_operation (XEXP (x, 0),
5086 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
5088 /* If we are in a comparison and this is an AND with a power of two,
5089 convert this into the appropriate bit extract. */
5090 else if (in_code == COMPARE
5091 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
5092 new = make_extraction (mode,
5093 make_compound_operation (XEXP (x, 0),
5095 i, NULL_RTX, 1, 1, 0, 1);
5100 /* If the sign bit is known to be zero, replace this with an
5101 arithmetic shift. */
5102 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
5103 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
5104 && mode_width <= HOST_BITS_PER_WIDE_INT
5105 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
5107 new = gen_rtx_combine (ASHIFTRT, mode,
5108 make_compound_operation (XEXP (x, 0),
5114 /* ... fall through ... */
5117 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
5118 this is a SIGN_EXTRACT. */
5119 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5120 && GET_CODE (XEXP (x, 0)) == ASHIFT
5121 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5122 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
5124 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5125 new = make_extraction (mode, new,
5126 (INTVAL (XEXP (x, 1))
5127 - INTVAL (XEXP (XEXP (x, 0), 1))),
5128 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5129 code == LSHIFTRT, 0, in_code == COMPARE);
5132 /* Similarly if we have (ashifrt (OP (ashift foo C1) C3) C2). In these
5133 cases, we are better off returning a SIGN_EXTEND of the operation. */
5135 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5136 && (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND
5137 || GET_CODE (XEXP (x, 0)) == XOR
5138 || GET_CODE (XEXP (x, 0)) == PLUS)
5139 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5140 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5141 && INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)) < HOST_BITS_PER_WIDE_INT
5142 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5143 && 0 == (INTVAL (XEXP (XEXP (x, 0), 1))
5144 & (((HOST_WIDE_INT) 1
5145 << (MIN (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)),
5146 INTVAL (XEXP (x, 1)))
5149 rtx c1 = XEXP (XEXP (XEXP (x, 0), 0), 1);
5150 rtx c2 = XEXP (x, 1);
5151 rtx c3 = XEXP (XEXP (x, 0), 1);
5152 HOST_WIDE_INT newop1;
5153 rtx inner = XEXP (XEXP (XEXP (x, 0), 0), 0);
5155 /* If C1 > C2, INNER needs to have the shift performed on it
5157 if (INTVAL (c1) > INTVAL (c2))
5159 inner = gen_binary (ASHIFT, mode, inner,
5160 GEN_INT (INTVAL (c1) - INTVAL (c2)));
5164 newop1 = INTVAL (c3) >> INTVAL (c1);
5165 new = make_compound_operation (inner,
5166 GET_CODE (XEXP (x, 0)) == PLUS
5167 ? MEM : GET_CODE (XEXP (x, 0)));
5168 new = make_extraction (mode,
5169 gen_binary (GET_CODE (XEXP (x, 0)), mode, new,
5171 INTVAL (c2) - INTVAL (c1),
5172 NULL_RTX, mode_width - INTVAL (c1),
5173 code == LSHIFTRT, 0, in_code == COMPARE);
5176 /* Similarly for (ashiftrt (neg (ashift FOO C1)) C2). */
5177 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5178 && GET_CODE (XEXP (x, 0)) == NEG
5179 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
5180 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
5181 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
5183 new = make_compound_operation (XEXP (XEXP (XEXP (x, 0), 0), 0),
5185 new = make_extraction (mode,
5186 gen_unary (GET_CODE (XEXP (x, 0)), mode,
5188 (INTVAL (XEXP (x, 1))
5189 - INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))),
5190 NULL_RTX, mode_width - INTVAL (XEXP (x, 1)),
5191 code == LSHIFTRT, 0, in_code == COMPARE);
5196 /* Call ourselves recursively on the inner expression. If we are
5197 narrowing the object and it has a different RTL code from
5198 what it originally did, do this SUBREG as a force_to_mode. */
5200 tem = make_compound_operation (SUBREG_REG (x), in_code);
5201 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
5202 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
5203 && subreg_lowpart_p (x))
5205 rtx newer = force_to_mode (tem, mode,
5206 GET_MODE_BITSIZE (mode), NULL_RTX);
5208 /* If we have something other than a SUBREG, we might have
5209 done an expansion, so rerun outselves. */
5210 if (GET_CODE (newer) != SUBREG)
5211 newer = make_compound_operation (newer, in_code);
5219 x = gen_lowpart_for_combine (mode, new);
5220 code = GET_CODE (x);
5223 /* Now recursively process each operand of this operation. */
5224 fmt = GET_RTX_FORMAT (code);
5225 for (i = 0; i < GET_RTX_LENGTH (code); i++)
5228 new = make_compound_operation (XEXP (x, i), next_code);
5229 SUBST (XEXP (x, i), new);
5235 /* Given M see if it is a value that would select a field of bits
5236 within an item, but not the entire word. Return -1 if not.
5237 Otherwise, return the starting position of the field, where 0 is the
5240 *PLEN is set to the length of the field. */
5243 get_pos_from_mask (m, plen)
5244 unsigned HOST_WIDE_INT m;
5247 /* Get the bit number of the first 1 bit from the right, -1 if none. */
5248 int pos = exact_log2 (m & - m);
5253 /* Now shift off the low-order zero bits and see if we have a power of
5255 *plen = exact_log2 ((m >> pos) + 1);
5263 /* Rewrite X so that it is an expression in MODE. We only care about the
5264 low-order BITS bits so we can ignore AND operations that just clear
5267 Also, if REG is non-zero and X is a register equal in value to REG,
5268 replace X with REG. */
5271 force_to_mode (x, mode, bits, reg)
5273 enum machine_mode mode;
5277 enum rtx_code code = GET_CODE (x);
5278 enum machine_mode op_mode = mode;
5280 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
5281 just get X in the proper mode. */
5283 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
5284 || bits > GET_MODE_BITSIZE (mode))
5285 return gen_lowpart_for_combine (mode, x);
5293 x = expand_compound_operation (x);
5294 if (GET_CODE (x) != code)
5295 return force_to_mode (x, mode, bits, reg);
5299 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
5300 || rtx_equal_p (reg, get_last_value (x))))
5305 if (bits < HOST_BITS_PER_WIDE_INT)
5306 x = GEN_INT (INTVAL (x) & (((HOST_WIDE_INT) 1 << bits) - 1));
5310 /* Ignore low-order SUBREGs. */
5311 if (subreg_lowpart_p (x))
5312 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
5316 /* If this is an AND with a constant. Otherwise, we fall through to
5317 do the general binary case. */
5319 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5321 HOST_WIDE_INT mask = INTVAL (XEXP (x, 1));
5322 int len = exact_log2 (mask + 1);
5323 rtx op = XEXP (x, 0);
5325 /* If this is masking some low-order bits, we may be able to
5326 impose a stricter constraint on what bits of the operand are
5329 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
5332 if (bits < HOST_BITS_PER_WIDE_INT)
5333 mask &= ((HOST_WIDE_INT) 1 << bits) - 1;
5335 /* If we have no AND in MODE, use the original mode for the
5338 if (and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5339 op_mode = GET_MODE (x);
5341 x = simplify_and_const_int (x, op_mode, op, mask);
5343 /* If X is still an AND, see if it is an AND with a mask that
5344 is just some low-order bits. If so, and it is BITS wide (it
5345 can't be wider), we don't need it. */
5347 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
5348 && bits < HOST_BITS_PER_WIDE_INT
5349 && INTVAL (XEXP (x, 1)) == ((HOST_WIDE_INT) 1 << bits) - 1)
5355 /* ... fall through ... */
5362 /* For most binary operations, just propagate into the operation and
5363 change the mode if we have an operation of that mode. */
5366 && add_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5368 && sub_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5369 || (code == MULT && (smul_optab->handlers[(int) mode].insn_code
5370 == CODE_FOR_nothing))
5372 && and_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5374 && ior_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5375 || (code == XOR && (xor_optab->handlers[(int) mode].insn_code
5376 == CODE_FOR_nothing)))
5377 op_mode = GET_MODE (x);
5379 x = gen_binary (code, op_mode,
5380 gen_lowpart_for_combine (op_mode,
5381 force_to_mode (XEXP (x, 0),
5384 gen_lowpart_for_combine (op_mode,
5385 force_to_mode (XEXP (x, 1),
5392 /* For left shifts, do the same, but just for the first operand.
5393 However, we cannot do anything with shifts where we cannot
5394 guarantee that the counts are smaller than the size of the mode
5395 because such a count will have a different meaning in a
5398 If we can narrow the shift and know the count, we need even fewer
5399 bits of the first operand. */
5401 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
5402 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
5403 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
5404 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
5405 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
5408 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
5409 bits -= INTVAL (XEXP (x, 1));
5412 && ashl_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5413 || (code == LSHIFT && (lshl_optab->handlers[(int) mode].insn_code
5414 == CODE_FOR_nothing)))
5415 op_mode = GET_MODE (x);
5417 x = gen_binary (code, op_mode,
5418 gen_lowpart_for_combine (op_mode,
5419 force_to_mode (XEXP (x, 0),
5426 /* Here we can only do something if the shift count is a constant and
5427 the count plus BITS is no larger than the width of MODE. In that
5428 case, we can do the shift in MODE. */
5430 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5431 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
5433 rtx inner = force_to_mode (XEXP (x, 0), mode,
5434 bits + INTVAL (XEXP (x, 1)), reg);
5436 if (lshr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5437 op_mode = GET_MODE (x);
5439 x = gen_binary (LSHIFTRT, op_mode,
5440 gen_lowpart_for_combine (op_mode, inner),
5446 /* If this is a sign-extension operation that just affects bits
5447 we don't care about, remove it. */
5449 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5450 && INTVAL (XEXP (x, 1)) >= 0
5451 && INTVAL (XEXP (x, 1)) <= GET_MODE_BITSIZE (GET_MODE (x)) - bits
5452 && GET_CODE (XEXP (x, 0)) == ASHIFT
5453 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
5454 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
5455 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, bits, reg);
5461 && neg_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
5462 || (code == NOT && (one_cmpl_optab->handlers[(int) mode].insn_code
5463 == CODE_FOR_nothing)))
5464 op_mode = GET_MODE (x);
5466 /* Handle these similarly to the way we handle most binary operations. */
5467 x = gen_unary (code, op_mode,
5468 gen_lowpart_for_combine (op_mode,
5469 force_to_mode (XEXP (x, 0), mode,
5474 /* We have no way of knowing if the IF_THEN_ELSE can itself be
5475 written in a narrower mode. We play it safe and do not do so. */
5478 gen_lowpart_for_combine (GET_MODE (x),
5479 force_to_mode (XEXP (x, 1), mode,
5482 gen_lowpart_for_combine (GET_MODE (x),
5483 force_to_mode (XEXP (x, 2), mode,
5488 /* Ensure we return a value of the proper mode. */
5489 return gen_lowpart_for_combine (mode, x);
5492 /* Return the value of expression X given the fact that condition COND
5493 is known to be true when applied to REG as its first operand and VAL
5494 as its second. X is known to not be shared and so can be modified in
5497 We only handle the simplest cases, and specifically those cases that
5498 arise with IF_THEN_ELSE expressions. */
5501 known_cond (x, cond, reg, val)
5506 enum rtx_code code = GET_CODE (x);
5511 if (side_effects_p (x))
5514 if (cond == EQ && rtx_equal_p (x, reg))
5517 /* If X is (abs REG) and we know something about REG's relationship
5518 with zero, we may be able to simplify this. */
5520 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
5523 case GE: case GT: case EQ:
5526 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), XEXP (x, 0));
5529 /* The only other cases we handle are MIN, MAX, and comparisons if the
5530 operands are the same as REG and VAL. */
5532 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
5534 if (rtx_equal_p (XEXP (x, 0), val))
5535 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
5537 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
5539 if (GET_RTX_CLASS (code) == '<')
5540 return (comparison_dominates_p (cond, code) ? const_true_rtx
5541 : (comparison_dominates_p (cond,
5542 reverse_condition (code))
5545 else if (code == SMAX || code == SMIN
5546 || code == UMIN || code == UMAX)
5548 int unsignedp = (code == UMIN || code == UMAX);
5550 if (code == SMAX || code == UMAX)
5551 cond = reverse_condition (cond);
5556 return unsignedp ? x : XEXP (x, 1);
5558 return unsignedp ? x : XEXP (x, 0);
5560 return unsignedp ? XEXP (x, 1) : x;
5562 return unsignedp ? XEXP (x, 0) : x;
5568 fmt = GET_RTX_FORMAT (code);
5569 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5572 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
5573 else if (fmt[i] == 'E')
5574 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5575 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
5582 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
5583 Return that assignment if so.
5585 We only handle the most common cases. */
5588 make_field_assignment (x)
5591 rtx dest = SET_DEST (x);
5592 rtx src = SET_SRC (x);
5598 enum machine_mode mode;
5600 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
5601 a clear of a one-bit field. We will have changed it to
5602 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
5605 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
5606 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
5607 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
5608 && (rtx_equal_p (dest, XEXP (src, 1))
5609 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5610 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5612 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5614 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5617 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
5618 && subreg_lowpart_p (XEXP (src, 0))
5619 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
5620 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
5621 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
5622 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
5623 && (rtx_equal_p (dest, XEXP (src, 1))
5624 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5625 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5627 assign = make_extraction (VOIDmode, dest, 0,
5628 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
5630 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
5633 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
5635 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
5636 && XEXP (XEXP (src, 0), 0) == const1_rtx
5637 && (rtx_equal_p (dest, XEXP (src, 1))
5638 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
5639 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
5641 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
5643 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
5646 /* The other case we handle is assignments into a constant-position
5647 field. They look like (ior (and DEST C1) OTHER). If C1 represents
5648 a mask that has all one bits except for a group of zero bits and
5649 OTHER is known to have zeros where C1 has ones, this is such an
5650 assignment. Compute the position and length from C1. Shift OTHER
5651 to the appropriate position, force it to the required mode, and
5652 make the extraction. Check for the AND in both operands. */
5654 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
5655 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
5656 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
5657 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
5658 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
5659 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
5660 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
5661 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
5662 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
5663 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
5664 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
5666 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
5670 pos = get_pos_from_mask (~c1, &len);
5671 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
5672 || (GET_MODE_BITSIZE (GET_MODE (other)) <= HOST_BITS_PER_WIDE_INT
5673 && (c1 & nonzero_bits (other, GET_MODE (other))) != 0))
5676 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
5678 /* The mode to use for the source is the mode of the assignment, or of
5679 what is inside a possible STRICT_LOW_PART. */
5680 mode = (GET_CODE (assign) == STRICT_LOW_PART
5681 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
5683 /* Shift OTHER right POS places and make it the source, restricting it
5684 to the proper length and mode. */
5686 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
5687 GET_MODE (src), other, pos),
5690 return gen_rtx_combine (SET, VOIDmode, assign, src);
5693 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
5697 apply_distributive_law (x)
5700 enum rtx_code code = GET_CODE (x);
5701 rtx lhs, rhs, other;
5703 enum rtx_code inner_code;
5705 /* Distributivity is not true for floating point.
5706 It can change the value. So don't do it.
5707 -- rms and moshier@world.std.com. */
5708 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5711 /* The outer operation can only be one of the following: */
5712 if (code != IOR && code != AND && code != XOR
5713 && code != PLUS && code != MINUS)
5716 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
5718 /* If either operand is a primitive we can't do anything, so get out fast. */
5719 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
5720 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
5723 lhs = expand_compound_operation (lhs);
5724 rhs = expand_compound_operation (rhs);
5725 inner_code = GET_CODE (lhs);
5726 if (inner_code != GET_CODE (rhs))
5729 /* See if the inner and outer operations distribute. */
5736 /* These all distribute except over PLUS. */
5737 if (code == PLUS || code == MINUS)
5742 if (code != PLUS && code != MINUS)
5748 /* These are also multiplies, so they distribute over everything. */
5752 /* Non-paradoxical SUBREGs distributes over all operations, provided
5753 the inner modes and word numbers are the same, this is an extraction
5754 of a low-order part, we don't convert an fp operation to int or
5755 vice versa, and we would not be converting a single-word
5756 operation into a multi-word operation. The latter test is not
5757 required, but it prevents generating unneeded multi-word operations.
5758 Some of the previous tests are redundant given the latter test, but
5759 are retained because they are required for correctness.
5761 We produce the result slightly differently in this case. */
5763 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
5764 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
5765 || ! subreg_lowpart_p (lhs)
5766 || (GET_MODE_CLASS (GET_MODE (lhs))
5767 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
5768 || (GET_MODE_SIZE (GET_MODE (lhs))
5769 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
5770 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
5773 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
5774 SUBREG_REG (lhs), SUBREG_REG (rhs));
5775 return gen_lowpart_for_combine (GET_MODE (x), tem);
5781 /* Set LHS and RHS to the inner operands (A and B in the example
5782 above) and set OTHER to the common operand (C in the example).
5783 These is only one way to do this unless the inner operation is
5785 if (GET_RTX_CLASS (inner_code) == 'c'
5786 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
5787 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
5788 else if (GET_RTX_CLASS (inner_code) == 'c'
5789 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
5790 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
5791 else if (GET_RTX_CLASS (inner_code) == 'c'
5792 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
5793 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
5794 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
5795 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
5799 /* Form the new inner operation, seeing if it simplifies first. */
5800 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
5802 /* There is one exception to the general way of distributing:
5803 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
5804 if (code == XOR && inner_code == IOR)
5807 other = gen_unary (NOT, GET_MODE (x), other);
5810 /* We may be able to continuing distributing the result, so call
5811 ourselves recursively on the inner operation before forming the
5812 outer operation, which we return. */
5813 return gen_binary (inner_code, GET_MODE (x),
5814 apply_distributive_law (tem), other);
5817 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
5820 Return an equivalent form, if different from X. Otherwise, return X. If
5821 X is zero, we are to always construct the equivalent form. */
5824 simplify_and_const_int (x, mode, varop, constop)
5826 enum machine_mode mode;
5828 unsigned HOST_WIDE_INT constop;
5830 register enum machine_mode tmode;
5832 unsigned HOST_WIDE_INT nonzero;
5834 /* There is a large class of optimizations based on the principle that
5835 some operations produce results where certain bits are known to be zero,
5836 and hence are not significant to the AND. For example, if we have just
5837 done a left shift of one bit, the low-order bit is known to be zero and
5838 hence an AND with a mask of ~1 would not do anything.
5840 At the end of the following loop, we set:
5842 VAROP to be the item to be AND'ed with;
5843 CONSTOP to the constant value to AND it with. */
5847 /* If we ever encounter a mode wider than the host machine's widest
5848 integer size, we can't compute the masks accurately, so give up. */
5849 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_WIDE_INT)
5852 /* Unless one of the cases below does a `continue',
5853 a `break' will be executed to exit the loop. */
5855 switch (GET_CODE (varop))
5858 /* If VAROP is a (clobber (const_int)), return it since we know
5859 we are generating something that won't match. */
5862 #if ! BITS_BIG_ENDIAN
5864 /* VAROP is a (use (mem ..)) that was made from a bit-field
5865 extraction that spanned the boundary of the MEM. If we are
5866 now masking so it is within that boundary, we don't need the
5868 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
5870 varop = XEXP (varop, 0);
5877 if (subreg_lowpart_p (varop)
5878 /* We can ignore the effect this SUBREG if it narrows the mode
5879 or, on machines where byte operations extend, if the
5880 constant masks to zero all the bits the mode doesn't have. */
5881 && ((GET_MODE_SIZE (GET_MODE (varop))
5882 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
5883 #ifdef BYTE_LOADS_EXTEND
5885 & GET_MODE_MASK (GET_MODE (varop))
5886 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
5890 varop = SUBREG_REG (varop);
5899 /* Try to expand these into a series of shifts and then work
5900 with that result. If we can't, for example, if the extract
5901 isn't at a fixed position, give up. */
5902 temp = expand_compound_operation (varop);
5911 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
5913 constop &= INTVAL (XEXP (varop, 1));
5914 varop = XEXP (varop, 0);
5921 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
5922 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
5923 operation which may be a bitfield extraction. */
5925 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5926 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5927 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5928 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT
5929 && GET_CODE (XEXP (varop, 1)) == CONST_INT
5930 && (INTVAL (XEXP (varop, 1))
5931 & ~ nonzero_bits (XEXP (varop, 0), GET_MODE (varop)) == 0))
5933 temp = GEN_INT ((INTVAL (XEXP (varop, 1)) & constop)
5934 << INTVAL (XEXP (XEXP (varop, 0), 1)));
5935 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
5936 XEXP (XEXP (varop, 0), 0), temp);
5937 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5938 temp, XEXP (varop, 1));
5942 /* Apply the AND to both branches of the IOR or XOR, then try to
5943 apply the distributive law. This may eliminate operations
5944 if either branch can be simplified because of the AND.
5945 It may also make some cases more complex, but those cases
5946 probably won't match a pattern either with or without this. */
5948 gen_lowpart_for_combine
5949 (mode, apply_distributive_law
5951 (GET_CODE (varop), GET_MODE (varop),
5952 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5953 XEXP (varop, 0), constop),
5954 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
5955 XEXP (varop, 1), constop))));
5958 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
5959 LSHIFTRT we can do the same as above. */
5961 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
5962 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5963 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
5964 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_WIDE_INT)
5966 temp = GEN_INT (constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
5967 temp = gen_binary (XOR, GET_MODE (varop),
5968 XEXP (XEXP (varop, 0), 0), temp);
5969 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
5970 temp, XEXP (XEXP (varop, 0), 1));
5976 /* If we are just looking for the sign bit, we don't need this
5977 shift at all, even if it has a variable count. */
5978 if (constop == ((HOST_WIDE_INT) 1
5979 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)))
5981 varop = XEXP (varop, 0);
5985 /* If this is a shift by a constant, get a mask that contains
5986 those bits that are not copies of the sign bit. We then have
5987 two cases: If CONSTOP only includes those bits, this can be
5988 a logical shift, which may allow simplifications. If CONSTOP
5989 is a single-bit field not within those bits, we are requesting
5990 a copy of the sign bit and hence can shift the sign bit to
5991 the appropriate location. */
5992 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5993 && INTVAL (XEXP (varop, 1)) >= 0
5994 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_WIDE_INT)
5998 nonzero = GET_MODE_MASK (GET_MODE (varop));
5999 nonzero >>= INTVAL (XEXP (varop, 1));
6001 if ((constop & ~ nonzero) == 0
6002 || (i = exact_log2 (constop)) >= 0)
6004 varop = simplify_shift_const
6005 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6006 i < 0 ? INTVAL (XEXP (varop, 1))
6007 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
6008 if (GET_CODE (varop) != ASHIFTRT)
6013 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
6014 even if the shift count isn't a constant. */
6016 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
6017 XEXP (varop, 0), XEXP (varop, 1));
6021 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6022 shift and AND produces only copies of the sign bit (C2 is one less
6023 than a power of two), we can do this with just a shift. */
6025 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6026 && ((INTVAL (XEXP (varop, 1))
6027 + num_sign_bit_copies (XEXP (varop, 0),
6028 GET_MODE (XEXP (varop, 0))))
6029 >= GET_MODE_BITSIZE (GET_MODE (varop)))
6030 && exact_log2 (constop + 1) >= 0)
6032 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
6033 GEN_INT (GET_MODE_BITSIZE (GET_MODE (varop))
6034 - exact_log2 (constop + 1)));
6038 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
6039 included in STORE_FLAG_VALUE and FOO has no bits that might be
6040 nonzero not in CONST. */
6041 if ((constop & ~ STORE_FLAG_VALUE) == 0
6042 && XEXP (varop, 0) == const0_rtx
6043 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
6045 varop = XEXP (varop, 0);
6051 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6052 low-order bits (as in an alignment operation) and FOO is already
6053 aligned to that boundary, we can convert remove this AND
6054 and possibly the PLUS if it is now adding zero. */
6055 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
6056 && exact_log2 (-constop) >= 0
6057 && (nonzero_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
6059 varop = plus_constant (XEXP (varop, 0),
6060 INTVAL (XEXP (varop, 1)) & constop);
6065 /* ... fall through ... */
6068 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
6069 less than powers of two and M2 is narrower than M1, we can
6070 eliminate the inner AND. This occurs when incrementing
6073 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
6074 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
6075 SUBST (XEXP (varop, 0),
6076 expand_compound_operation (XEXP (varop, 0)));
6078 if (GET_CODE (XEXP (varop, 0)) == AND
6079 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6080 && exact_log2 (constop + 1) >= 0
6081 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
6082 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
6083 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
6090 /* If we have reached a constant, this whole thing is constant. */
6091 if (GET_CODE (varop) == CONST_INT)
6092 return GEN_INT (constop & INTVAL (varop));
6094 /* See what bits may be nonzero in VAROP. Unlike the general case of
6095 a call to nonzero_bits, here we don't care about bits outside
6098 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
6100 /* Turn off all bits in the constant that are known to already be zero.
6101 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
6102 which is tested below. */
6106 /* If we don't have any bits left, return zero. */
6110 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
6111 if we already had one (just check for the simplest cases). */
6112 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6113 && GET_MODE (XEXP (x, 0)) == mode
6114 && SUBREG_REG (XEXP (x, 0)) == varop)
6115 varop = XEXP (x, 0);
6117 varop = gen_lowpart_for_combine (mode, varop);
6119 /* If we can't make the SUBREG, try to return what we were given. */
6120 if (GET_CODE (varop) == CLOBBER)
6121 return x ? x : varop;
6123 /* If we are only masking insignificant bits, return VAROP. */
6124 if (constop == nonzero)
6127 /* Otherwise, return an AND. See how much, if any, of X we can use. */
6128 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
6129 x = gen_rtx_combine (AND, mode, varop, GEN_INT (constop));
6133 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6134 || INTVAL (XEXP (x, 1)) != constop)
6135 SUBST (XEXP (x, 1), GEN_INT (constop));
6137 SUBST (XEXP (x, 0), varop);
6143 /* Given an expression, X, compute which bits in X can be non-zero.
6144 We don't care about bits outside of those defined in MODE.
6146 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
6147 a shift, AND, or zero_extract, we can do better. */
6149 static unsigned HOST_WIDE_INT
6150 nonzero_bits (x, mode)
6152 enum machine_mode mode;
6154 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
6155 unsigned HOST_WIDE_INT inner_nz;
6157 int mode_width = GET_MODE_BITSIZE (mode);
6160 /* If X is wider than MODE, use its mode instead. */
6161 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
6163 mode = GET_MODE (x);
6164 nonzero = GET_MODE_MASK (mode);
6165 mode_width = GET_MODE_BITSIZE (mode);
6168 if (mode_width > HOST_BITS_PER_WIDE_INT)
6169 /* Our only callers in this case look for single bit values. So
6170 just return the mode mask. Those tests will then be false. */
6173 code = GET_CODE (x);
6177 #ifdef STACK_BOUNDARY
6178 /* If this is the stack pointer, we may know something about its
6179 alignment. If PUSH_ROUNDING is defined, it is possible for the
6180 stack to be momentarily aligned only to that amount, so we pick
6181 the least alignment. */
6183 if (x == stack_pointer_rtx)
6185 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6187 #ifdef PUSH_ROUNDING
6188 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
6191 return nonzero & ~ (sp_alignment - 1);
6195 /* If X is a register whose nonzero bits value is current, use it.
6196 Otherwise, if X is a register whose value we can find, use that
6197 value. Otherwise, use the previously-computed global nonzero bits
6198 for this register. */
6200 if (reg_last_set_value[REGNO (x)] != 0
6201 && reg_last_set_mode[REGNO (x)] == mode
6202 && (reg_n_sets[REGNO (x)] == 1
6203 || reg_last_set_label[REGNO (x)] == label_tick)
6204 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6205 return reg_last_set_nonzero_bits[REGNO (x)];
6207 tem = get_last_value (x);
6209 return nonzero_bits (tem, mode);
6210 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
6211 return reg_nonzero_bits[REGNO (x)] & nonzero;
6218 #ifdef BYTE_LOADS_ZERO_EXTEND
6220 /* In many, if not most, RISC machines, reading a byte from memory
6221 zeros the rest of the register. Noticing that fact saves a lot
6222 of extra zero-extends. */
6223 nonzero &= GET_MODE_MASK (GET_MODE (x));
6227 #if STORE_FLAG_VALUE == 1
6234 if (GET_MODE_CLASS (mode) == MODE_INT)
6237 /* A comparison operation only sets the bits given by its mode. The
6238 rest are set undefined. */
6239 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6240 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6245 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6246 == GET_MODE_BITSIZE (GET_MODE (x)))
6249 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
6250 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
6254 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
6255 == GET_MODE_BITSIZE (GET_MODE (x)))
6260 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
6264 nonzero &= nonzero_bits (XEXP (x, 0), mode);
6265 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6266 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6270 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
6271 Otherwise, show all the bits in the outer mode but not the inner
6273 inner_nz = nonzero_bits (XEXP (x, 0), mode);
6274 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
6276 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
6279 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
6280 inner_nz |= (GET_MODE_MASK (mode)
6281 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
6284 nonzero &= inner_nz;
6288 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6289 & nonzero_bits (XEXP (x, 1), mode));
6293 case UMIN: case UMAX: case SMIN: case SMAX:
6294 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
6295 | nonzero_bits (XEXP (x, 1), mode));
6298 case PLUS: case MINUS:
6300 case DIV: case UDIV:
6301 case MOD: case UMOD:
6302 /* We can apply the rules of arithmetic to compute the number of
6303 high- and low-order zero bits of these operations. We start by
6304 computing the width (position of the highest-order non-zero bit)
6305 and the number of low-order zero bits for each value. */
6307 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
6308 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
6309 int width0 = floor_log2 (nz0) + 1;
6310 int width1 = floor_log2 (nz1) + 1;
6311 int low0 = floor_log2 (nz0 & -nz0);
6312 int low1 = floor_log2 (nz1 & -nz1);
6313 int op0_maybe_minusp = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6314 int op1_maybe_minusp = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
6315 int result_width = mode_width;
6321 result_width = MAX (width0, width1) + 1;
6322 result_low = MIN (low0, low1);
6325 result_low = MIN (low0, low1);
6328 result_width = width0 + width1;
6329 result_low = low0 + low1;
6332 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6333 result_width = width0;
6336 result_width = width0;
6339 if (! op0_maybe_minusp && ! op1_maybe_minusp)
6340 result_width = MIN (width0, width1);
6341 result_low = MIN (low0, low1);
6344 result_width = MIN (width0, width1);
6345 result_low = MIN (low0, low1);
6349 if (result_width < mode_width)
6350 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
6353 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
6358 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6359 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6360 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
6364 /* If this is a SUBREG formed for a promoted variable that has
6365 been zero-extended, we know that at least the high-order bits
6366 are zero, though others might be too. */
6368 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
6369 nonzero = (GET_MODE_MASK (GET_MODE (x))
6370 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
6372 /* If the inner mode is a single word for both the host and target
6373 machines, we can compute this from which bits of the inner
6374 object might be nonzero. */
6375 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
6376 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6377 <= HOST_BITS_PER_WIDE_INT))
6379 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
6380 #ifndef BYTE_LOADS_EXTEND
6381 /* On many CISC machines, accessing an object in a wider mode
6382 causes the high-order bits to become undefined. So they are
6383 not known to be zero. */
6384 if (GET_MODE_SIZE (GET_MODE (x))
6385 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6386 nonzero |= (GET_MODE_MASK (GET_MODE (x))
6387 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
6397 /* The nonzero bits are in two classes: any bits within MODE
6398 that aren't in GET_MODE (x) are always significant. The rest of the
6399 nonzero bits are those that are significant in the operand of
6400 the shift when shifted the appropriate number of bits. This
6401 shows that high-order bits are cleared by the right shift and
6402 low-order bits by left shifts. */
6403 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6404 && INTVAL (XEXP (x, 1)) >= 0
6405 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6407 enum machine_mode inner_mode = GET_MODE (x);
6408 int width = GET_MODE_BITSIZE (inner_mode);
6409 int count = INTVAL (XEXP (x, 1));
6410 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
6411 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
6412 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
6413 unsigned HOST_WIDE_INT outer = 0;
6415 if (mode_width > width)
6416 outer = (op_nonzero & nonzero & ~ mode_mask);
6418 if (code == LSHIFTRT)
6420 else if (code == ASHIFTRT)
6424 /* If the sign bit may have been nonzero before the shift, we
6425 need to mark all the places it could have been copied to
6426 by the shift as possibly nonzero. */
6427 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
6428 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
6430 else if (code == LSHIFT || code == ASHIFT)
6433 inner = ((inner << (count % width)
6434 | (inner >> (width - (count % width)))) & mode_mask);
6436 nonzero &= (outer | inner);
6441 /* This is at most the number of bits in the mode. */
6442 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
6446 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
6447 | nonzero_bits (XEXP (x, 2), mode));
6454 /* Return the number of bits at the high-order end of X that are known to
6455 be equal to the sign bit. This number will always be between 1 and
6456 the number of bits in the mode of X. MODE is the mode to be used
6457 if X is VOIDmode. */
6460 num_sign_bit_copies (x, mode)
6462 enum machine_mode mode;
6464 enum rtx_code code = GET_CODE (x);
6466 int num0, num1, result;
6467 unsigned HOST_WIDE_INT nonzero;
6470 /* If we weren't given a mode, use the mode of X. If the mode is still
6471 VOIDmode, we don't know anything. */
6473 if (mode == VOIDmode)
6474 mode = GET_MODE (x);
6476 if (mode == VOIDmode)
6479 bitwidth = GET_MODE_BITSIZE (mode);
6485 if (reg_last_set_value[REGNO (x)] != 0
6486 && reg_last_set_mode[REGNO (x)] == mode
6487 && (reg_n_sets[REGNO (x)] == 1
6488 || reg_last_set_label[REGNO (x)] == label_tick)
6489 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
6490 return reg_last_set_sign_bit_copies[REGNO (x)];
6492 tem = get_last_value (x);
6494 return num_sign_bit_copies (tem, mode);
6496 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
6497 return reg_sign_bit_copies[REGNO (x)];
6500 #ifdef BYTE_LOADS_SIGN_EXTEND
6502 /* Some RISC machines sign-extend all loads of smaller than a word. */
6503 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
6507 /* If the constant is negative, take its 1's complement and remask.
6508 Then see how many zero bits we have. */
6509 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
6510 if (bitwidth <= HOST_BITS_PER_WIDE_INT
6511 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6512 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
6514 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
6517 /* If this is a SUBREG for a promoted object that is sign-extended
6518 and we are looking at it in a wider mode, we know that at least the
6519 high-order bits are known to be sign bit copies. */
6521 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
6522 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
6523 num_sign_bit_copies (SUBREG_REG (x), mode));
6525 /* For a smaller object, just ignore the high bits. */
6526 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
6528 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
6529 return MAX (1, (num0
6530 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
6534 #ifdef BYTE_LOADS_EXTEND
6535 /* For paradoxical SUBREGs, just look inside since, on machines with
6536 one of these defined, we assume that operations are actually
6537 performed on the full register. Note that we are passing MODE
6538 to the recursive call, so the number of sign bit copies will
6539 remain relative to that mode, not the inner mode. */
6541 if (GET_MODE_SIZE (GET_MODE (x))
6542 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6543 return num_sign_bit_copies (SUBREG_REG (x), mode);
6549 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6550 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
6554 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6555 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
6558 /* For a smaller object, just ignore the high bits. */
6559 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
6560 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6564 return num_sign_bit_copies (XEXP (x, 0), mode);
6566 case ROTATE: case ROTATERT:
6567 /* If we are rotating left by a number of bits less than the number
6568 of sign bit copies, we can just subtract that amount from the
6570 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6571 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
6573 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6574 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
6575 : bitwidth - INTVAL (XEXP (x, 1))));
6580 /* In general, this subtracts one sign bit copy. But if the value
6581 is known to be positive, the number of sign bit copies is the
6582 same as that of the input. Finally, if the input has just one bit
6583 that might be nonzero, all the bits are copies of the sign bit. */
6584 nonzero = nonzero_bits (XEXP (x, 0), mode);
6588 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6590 && bitwidth <= HOST_BITS_PER_WIDE_INT
6591 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
6596 case IOR: case AND: case XOR:
6597 case SMIN: case SMAX: case UMIN: case UMAX:
6598 /* Logical operations will preserve the number of sign-bit copies.
6599 MIN and MAX operations always return one of the operands. */
6600 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6601 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6602 return MIN (num0, num1);
6604 case PLUS: case MINUS:
6605 /* For addition and subtraction, we can have a 1-bit carry. However,
6606 if we are subtracting 1 from a positive number, there will not
6607 be such a carry. Furthermore, if the positive number is known to
6608 be 0 or 1, we know the result is either -1 or 0. */
6610 if (code == PLUS && XEXP (x, 1) == constm1_rtx
6611 && bitwidth <= HOST_BITS_PER_WIDE_INT)
6613 nonzero = nonzero_bits (XEXP (x, 0), mode);
6614 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
6615 return (nonzero == 1 || nonzero == 0 ? bitwidth
6616 : bitwidth - floor_log2 (nonzero) - 1);
6619 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6620 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6621 return MAX (1, MIN (num0, num1) - 1);
6624 /* The number of bits of the product is the sum of the number of
6625 bits of both terms. However, unless one of the terms if known
6626 to be positive, we must allow for an additional bit since negating
6627 a negative number can remove one sign bit copy. */
6629 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6630 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
6632 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
6634 && bitwidth <= HOST_BITS_PER_WIDE_INT
6635 && ((nonzero_bits (XEXP (x, 0), mode)
6636 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6637 && (nonzero_bits (XEXP (x, 1), mode)
6638 & ((HOST_WIDE_INT) 1 << (bitwidth - 1)) != 0))
6641 return MAX (1, result);
6644 /* The result must be <= the first operand. */
6645 return num_sign_bit_copies (XEXP (x, 0), mode);
6648 /* The result must be <= the scond operand. */
6649 return num_sign_bit_copies (XEXP (x, 1), mode);
6652 /* Similar to unsigned division, except that we have to worry about
6653 the case where the divisor is negative, in which case we have
6655 result = num_sign_bit_copies (XEXP (x, 0), mode);
6657 && bitwidth <= HOST_BITS_PER_WIDE_INT
6658 && (nonzero_bits (XEXP (x, 1), mode)
6659 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6665 result = num_sign_bit_copies (XEXP (x, 1), mode);
6667 && bitwidth <= HOST_BITS_PER_WIDE_INT
6668 && (nonzero_bits (XEXP (x, 1), mode)
6669 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
6675 /* Shifts by a constant add to the number of bits equal to the
6677 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6678 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6679 && INTVAL (XEXP (x, 1)) > 0)
6680 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
6686 /* Left shifts destroy copies. */
6687 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6688 || INTVAL (XEXP (x, 1)) < 0
6689 || INTVAL (XEXP (x, 1)) >= bitwidth)
6692 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
6693 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
6696 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
6697 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
6698 return MIN (num0, num1);
6700 #if STORE_FLAG_VALUE == -1
6701 case EQ: case NE: case GE: case GT: case LE: case LT:
6702 case GEU: case GTU: case LEU: case LTU:
6707 /* If we haven't been able to figure it out by one of the above rules,
6708 see if some of the high-order bits are known to be zero. If so,
6709 count those bits and return one less than that amount. If we can't
6710 safely compute the mask for this mode, always return BITWIDTH. */
6712 if (bitwidth > HOST_BITS_PER_WIDE_INT)
6715 nonzero = nonzero_bits (x, mode);
6716 return (nonzero == GET_MODE_MASK (mode)
6717 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
6720 /* Return the number of "extended" bits there are in X, when interpreted
6721 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
6722 unsigned quantities, this is the number of high-order zero bits.
6723 For signed quantities, this is the number of copies of the sign bit
6724 minus 1. In both case, this function returns the number of "spare"
6725 bits. For example, if two quantities for which this function returns
6726 at least 1 are added, the addition is known not to overflow.
6728 This function will always return 0 unless called during combine, which
6729 implies that it must be called from a define_split. */
6732 extended_count (x, mode, unsignedp)
6734 enum machine_mode mode;
6737 if (nonzero_sign_valid == 0)
6741 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
6742 && (GET_MODE_BITSIZE (mode) - 1
6743 - floor_log2 (nonzero_bits (x, mode))))
6744 : num_sign_bit_copies (x, mode) - 1);
6747 /* This function is called from `simplify_shift_const' to merge two
6748 outer operations. Specifically, we have already found that we need
6749 to perform operation *POP0 with constant *PCONST0 at the outermost
6750 position. We would now like to also perform OP1 with constant CONST1
6751 (with *POP0 being done last).
6753 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
6754 the resulting operation. *PCOMP_P is set to 1 if we would need to
6755 complement the innermost operand, otherwise it is unchanged.
6757 MODE is the mode in which the operation will be done. No bits outside
6758 the width of this mode matter. It is assumed that the width of this mode
6759 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
6761 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
6762 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
6763 result is simply *PCONST0.
6765 If the resulting operation cannot be expressed as one operation, we
6766 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
6769 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
6770 enum rtx_code *pop0;
6771 HOST_WIDE_INT *pconst0;
6773 HOST_WIDE_INT const1;
6774 enum machine_mode mode;
6777 enum rtx_code op0 = *pop0;
6778 HOST_WIDE_INT const0 = *pconst0;
6780 const0 &= GET_MODE_MASK (mode);
6781 const1 &= GET_MODE_MASK (mode);
6783 /* If OP0 is an AND, clear unimportant bits in CONST1. */
6787 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
6790 if (op1 == NIL || op0 == SET)
6793 else if (op0 == NIL)
6794 op0 = op1, const0 = const1;
6796 else if (op0 == op1)
6818 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
6819 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
6822 /* If the two constants aren't the same, we can't do anything. The
6823 remaining six cases can all be done. */
6824 else if (const0 != const1)
6832 /* (a & b) | b == b */
6834 else /* op1 == XOR */
6835 /* (a ^ b) | b == a | b */
6841 /* (a & b) ^ b == (~a) & b */
6842 op0 = AND, *pcomp_p = 1;
6843 else /* op1 == IOR */
6844 /* (a | b) ^ b == a & ~b */
6845 op0 = AND, *pconst0 = ~ const0;
6850 /* (a | b) & b == b */
6852 else /* op1 == XOR */
6853 /* (a ^ b) & b) == (~a) & b */
6858 /* Check for NO-OP cases. */
6859 const0 &= GET_MODE_MASK (mode);
6861 && (op0 == IOR || op0 == XOR || op0 == PLUS))
6863 else if (const0 == 0 && op0 == AND)
6865 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
6874 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
6875 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
6876 that we started with.
6878 The shift is normally computed in the widest mode we find in VAROP, as
6879 long as it isn't a different number of words than RESULT_MODE. Exceptions
6880 are ASHIFTRT and ROTATE, which are always done in their original mode, */
6883 simplify_shift_const (x, code, result_mode, varop, count)
6886 enum machine_mode result_mode;
6890 enum rtx_code orig_code = code;
6891 int orig_count = count;
6892 enum machine_mode mode = result_mode;
6893 enum machine_mode shift_mode, tmode;
6895 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
6896 /* We form (outer_op (code varop count) (outer_const)). */
6897 enum rtx_code outer_op = NIL;
6898 HOST_WIDE_INT outer_const;
6900 int complement_p = 0;
6903 /* If we were given an invalid count, don't do anything except exactly
6904 what was requested. */
6906 if (count < 0 || count > GET_MODE_BITSIZE (mode))
6911 return gen_rtx (code, mode, varop, GEN_INT (count));
6914 /* Unless one of the branches of the `if' in this loop does a `continue',
6915 we will `break' the loop after the `if'. */
6919 /* If we have an operand of (clobber (const_int 0)), just return that
6921 if (GET_CODE (varop) == CLOBBER)
6924 /* If we discovered we had to complement VAROP, leave. Making a NOT
6925 here would cause an infinite loop. */
6929 /* Convert ROTATETRT to ROTATE. */
6930 if (code == ROTATERT)
6931 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
6933 /* Canonicalize LSHIFT to ASHIFT. */
6937 /* We need to determine what mode we will do the shift in. If the
6938 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
6939 was originally done in. Otherwise, we can do it in MODE, the widest
6940 mode encountered. */
6941 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6943 /* Handle cases where the count is greater than the size of the mode
6944 minus 1. For ASHIFT, use the size minus one as the count (this can
6945 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
6946 take the count modulo the size. For other shifts, the result is
6949 Since these shifts are being produced by the compiler by combining
6950 multiple operations, each of which are defined, we know what the
6951 result is supposed to be. */
6953 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
6955 if (code == ASHIFTRT)
6956 count = GET_MODE_BITSIZE (shift_mode) - 1;
6957 else if (code == ROTATE || code == ROTATERT)
6958 count %= GET_MODE_BITSIZE (shift_mode);
6961 /* We can't simply return zero because there may be an
6969 /* Negative counts are invalid and should not have been made (a
6970 programmer-specified negative count should have been handled
6975 /* An arithmetic right shift of a quantity known to be -1 or 0
6977 if (code == ASHIFTRT
6978 && (num_sign_bit_copies (varop, shift_mode)
6979 == GET_MODE_BITSIZE (shift_mode)))
6985 /* If we are doing an arithmetic right shift and discarding all but
6986 the sign bit copies, this is equivalent to doing a shift by the
6987 bitsize minus one. Convert it into that shift because it will often
6988 allow other simplifications. */
6990 if (code == ASHIFTRT
6991 && (count + num_sign_bit_copies (varop, shift_mode)
6992 >= GET_MODE_BITSIZE (shift_mode)))
6993 count = GET_MODE_BITSIZE (shift_mode) - 1;
6995 /* We simplify the tests below and elsewhere by converting
6996 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
6997 `make_compound_operation' will convert it to a ASHIFTRT for
6998 those machines (such as Vax) that don't have a LSHIFTRT. */
6999 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
7001 && ((nonzero_bits (varop, shift_mode)
7002 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
7006 switch (GET_CODE (varop))
7012 new = expand_compound_operation (varop);
7021 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
7022 minus the width of a smaller mode, we can do this with a
7023 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
7024 if ((code == ASHIFTRT || code == LSHIFTRT)
7025 && ! mode_dependent_address_p (XEXP (varop, 0))
7026 && ! MEM_VOLATILE_P (varop)
7027 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7028 MODE_INT, 1)) != BLKmode)
7030 #if BYTES_BIG_ENDIAN
7031 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
7033 new = gen_rtx (MEM, tmode,
7034 plus_constant (XEXP (varop, 0),
7035 count / BITS_PER_UNIT));
7036 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
7037 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
7038 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
7040 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7041 : ZERO_EXTEND, mode, new);
7048 /* Similar to the case above, except that we can only do this if
7049 the resulting mode is the same as that of the underlying
7050 MEM and adjust the address depending on the *bits* endianness
7051 because of the way that bit-field extract insns are defined. */
7052 if ((code == ASHIFTRT || code == LSHIFTRT)
7053 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
7054 MODE_INT, 1)) != BLKmode
7055 && tmode == GET_MODE (XEXP (varop, 0)))
7058 new = XEXP (varop, 0);
7060 new = copy_rtx (XEXP (varop, 0));
7061 SUBST (XEXP (new, 0),
7062 plus_constant (XEXP (new, 0),
7063 count / BITS_PER_UNIT));
7066 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
7067 : ZERO_EXTEND, mode, new);
7074 /* If VAROP is a SUBREG, strip it as long as the inner operand has
7075 the same number of words as what we've seen so far. Then store
7076 the widest mode in MODE. */
7077 if (subreg_lowpart_p (varop)
7078 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7079 > GET_MODE_SIZE (GET_MODE (varop)))
7080 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
7081 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7084 varop = SUBREG_REG (varop);
7085 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
7086 mode = GET_MODE (varop);
7092 /* Some machines use MULT instead of ASHIFT because MULT
7093 is cheaper. But it is still better on those machines to
7094 merge two shifts into one. */
7095 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7096 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7098 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
7099 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
7105 /* Similar, for when divides are cheaper. */
7106 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7107 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
7109 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
7110 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
7116 /* If we are extracting just the sign bit of an arithmetic right
7117 shift, that shift is not needed. */
7118 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
7120 varop = XEXP (varop, 0);
7124 /* ... fall through ... */
7130 /* Here we have two nested shifts. The result is usually the
7131 AND of a new shift with a mask. We compute the result below. */
7132 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7133 && INTVAL (XEXP (varop, 1)) >= 0
7134 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
7135 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7136 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
7138 enum rtx_code first_code = GET_CODE (varop);
7139 int first_count = INTVAL (XEXP (varop, 1));
7140 unsigned HOST_WIDE_INT mask;
7144 if (first_code == LSHIFT)
7145 first_code = ASHIFT;
7147 /* We have one common special case. We can't do any merging if
7148 the inner code is an ASHIFTRT of a smaller mode. However, if
7149 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
7150 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
7151 we can convert it to
7152 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
7153 This simplifies certain SIGN_EXTEND operations. */
7154 if (code == ASHIFT && first_code == ASHIFTRT
7155 && (GET_MODE_BITSIZE (result_mode)
7156 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
7158 /* C3 has the low-order C1 bits zero. */
7160 mask = (GET_MODE_MASK (mode)
7161 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
7163 varop = simplify_and_const_int (NULL_RTX, result_mode,
7164 XEXP (varop, 0), mask);
7165 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
7167 count = first_count;
7172 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
7173 than C1 high-order bits equal to the sign bit, we can convert
7174 this to either an ASHIFT or a ASHIFTRT depending on the
7177 We cannot do this if VAROP's mode is not SHIFT_MODE. */
7179 if (code == ASHIFTRT && first_code == ASHIFT
7180 && GET_MODE (varop) == shift_mode
7181 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
7184 count -= first_count;
7186 count = - count, code = ASHIFT;
7187 varop = XEXP (varop, 0);
7191 /* There are some cases we can't do. If CODE is ASHIFTRT,
7192 we can only do this if FIRST_CODE is also ASHIFTRT.
7194 We can't do the case when CODE is ROTATE and FIRST_CODE is
7197 If the mode of this shift is not the mode of the outer shift,
7198 we can't do this if either shift is ASHIFTRT or ROTATE.
7200 Finally, we can't do any of these if the mode is too wide
7201 unless the codes are the same.
7203 Handle the case where the shift codes are the same
7206 if (code == first_code)
7208 if (GET_MODE (varop) != result_mode
7209 && (code == ASHIFTRT || code == ROTATE))
7212 count += first_count;
7213 varop = XEXP (varop, 0);
7217 if (code == ASHIFTRT
7218 || (code == ROTATE && first_code == ASHIFTRT)
7219 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
7220 || (GET_MODE (varop) != result_mode
7221 && (first_code == ASHIFTRT || first_code == ROTATE
7222 || code == ROTATE)))
7225 /* To compute the mask to apply after the shift, shift the
7226 nonzero bits of the inner shift the same way the
7227 outer shift will. */
7229 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
7232 = simplify_binary_operation (code, result_mode, mask_rtx,
7235 /* Give up if we can't compute an outer operation to use. */
7237 || GET_CODE (mask_rtx) != CONST_INT
7238 || ! merge_outer_ops (&outer_op, &outer_const, AND,
7240 result_mode, &complement_p))
7243 /* If the shifts are in the same direction, we add the
7244 counts. Otherwise, we subtract them. */
7245 if ((code == ASHIFTRT || code == LSHIFTRT)
7246 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
7247 count += first_count;
7249 count -= first_count;
7251 /* If COUNT is positive, the new shift is usually CODE,
7252 except for the two exceptions below, in which case it is
7253 FIRST_CODE. If the count is negative, FIRST_CODE should
7256 && ((first_code == ROTATE && code == ASHIFT)
7257 || (first_code == ASHIFTRT && code == LSHIFTRT)))
7260 code = first_code, count = - count;
7262 varop = XEXP (varop, 0);
7266 /* If we have (A << B << C) for any shift, we can convert this to
7267 (A << C << B). This wins if A is a constant. Only try this if
7268 B is not a constant. */
7270 else if (GET_CODE (varop) == code
7271 && GET_CODE (XEXP (varop, 1)) != CONST_INT
7273 = simplify_binary_operation (code, mode,
7277 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
7284 /* Make this fit the case below. */
7285 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
7286 GEN_INT (GET_MODE_MASK (mode)));
7292 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
7293 with C the size of VAROP - 1 and the shift is logical if
7294 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7295 we have an (le X 0) operation. If we have an arithmetic shift
7296 and STORE_FLAG_VALUE is 1 or we have a logical shift with
7297 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
7299 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
7300 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
7301 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7302 && (code == LSHIFTRT || code == ASHIFTRT)
7303 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7304 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7307 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
7310 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7311 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7316 /* If we have (shift (logical)), move the logical to the outside
7317 to allow it to possibly combine with another logical and the
7318 shift to combine with another shift. This also canonicalizes to
7319 what a ZERO_EXTRACT looks like. Also, some machines have
7320 (and (shift)) insns. */
7322 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
7323 && (new = simplify_binary_operation (code, result_mode,
7325 GEN_INT (count))) != 0
7326 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
7327 INTVAL (new), result_mode, &complement_p))
7329 varop = XEXP (varop, 0);
7333 /* If we can't do that, try to simplify the shift in each arm of the
7334 logical expression, make a new logical expression, and apply
7335 the inverse distributive law. */
7337 rtx lhs = simplify_shift_const (NULL_RTX, code, result_mode,
7338 XEXP (varop, 0), count);
7339 rtx rhs = simplify_shift_const (NULL_RTX, code, result_mode,
7340 XEXP (varop, 1), count);
7342 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
7343 varop = apply_distributive_law (varop);
7350 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
7351 says that the sign bit can be tested, FOO has mode MODE, C is
7352 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
7355 && XEXP (varop, 1) == const0_rtx
7356 && GET_MODE (XEXP (varop, 0)) == result_mode
7357 && count == GET_MODE_BITSIZE (result_mode) - 1
7358 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7359 && ((STORE_FLAG_VALUE
7360 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
7361 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7362 && merge_outer_ops (&outer_op, &outer_const, XOR,
7363 (HOST_WIDE_INT) 1, result_mode,
7366 varop = XEXP (varop, 0);
7373 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
7374 than the number of bits in the mode is equivalent to A. */
7375 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7376 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
7378 varop = XEXP (varop, 0);
7383 /* NEG commutes with ASHIFT since it is multiplication. Move the
7384 NEG outside to allow shifts to combine. */
7386 && merge_outer_ops (&outer_op, &outer_const, NEG,
7387 (HOST_WIDE_INT) 0, result_mode,
7390 varop = XEXP (varop, 0);
7396 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
7397 is one less than the number of bits in the mode is
7398 equivalent to (xor A 1). */
7399 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
7400 && XEXP (varop, 1) == constm1_rtx
7401 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
7402 && merge_outer_ops (&outer_op, &outer_const, XOR,
7403 (HOST_WIDE_INT) 1, result_mode,
7407 varop = XEXP (varop, 0);
7411 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
7412 that might be nonzero in BAR are those being shifted out and those
7413 bits are known zero in FOO, we can replace the PLUS with FOO.
7414 Similarly in the other operand order. This code occurs when
7415 we are computing the size of a variable-size array. */
7417 if ((code == ASHIFTRT || code == LSHIFTRT)
7418 && count < HOST_BITS_PER_WIDE_INT
7419 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
7420 && (nonzero_bits (XEXP (varop, 1), result_mode)
7421 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
7423 varop = XEXP (varop, 0);
7426 else if ((code == ASHIFTRT || code == LSHIFTRT)
7427 && count < HOST_BITS_PER_WIDE_INT
7428 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
7429 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7431 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
7432 & nonzero_bits (XEXP (varop, 1),
7435 varop = XEXP (varop, 1);
7439 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
7441 && GET_CODE (XEXP (varop, 1)) == CONST_INT
7442 && (new = simplify_binary_operation (ASHIFT, result_mode,
7444 GEN_INT (count))) != 0
7445 && merge_outer_ops (&outer_op, &outer_const, PLUS,
7446 INTVAL (new), result_mode, &complement_p))
7448 varop = XEXP (varop, 0);
7454 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
7455 with C the size of VAROP - 1 and the shift is logical if
7456 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
7457 we have a (gt X 0) operation. If the shift is arithmetic with
7458 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
7459 we have a (neg (gt X 0)) operation. */
7461 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
7462 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
7463 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7464 && (code == LSHIFTRT || code == ASHIFTRT)
7465 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
7466 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
7467 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
7470 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
7473 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
7474 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
7484 /* We need to determine what mode to do the shift in. If the shift is
7485 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
7486 done in. Otherwise, we can do it in MODE, the widest mode encountered.
7487 The code we care about is that of the shift that will actually be done,
7488 not the shift that was originally requested. */
7489 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
7491 /* We have now finished analyzing the shift. The result should be
7492 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
7493 OUTER_OP is non-NIL, it is an operation that needs to be applied
7494 to the result of the shift. OUTER_CONST is the relevant constant,
7495 but we must turn off all bits turned off in the shift.
7497 If we were passed a value for X, see if we can use any pieces of
7498 it. If not, make new rtx. */
7500 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
7501 && GET_CODE (XEXP (x, 1)) == CONST_INT
7502 && INTVAL (XEXP (x, 1)) == count)
7503 const_rtx = XEXP (x, 1);
7505 const_rtx = GEN_INT (count);
7507 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7508 && GET_MODE (XEXP (x, 0)) == shift_mode
7509 && SUBREG_REG (XEXP (x, 0)) == varop)
7510 varop = XEXP (x, 0);
7511 else if (GET_MODE (varop) != shift_mode)
7512 varop = gen_lowpart_for_combine (shift_mode, varop);
7514 /* If we can't make the SUBREG, try to return what we were given. */
7515 if (GET_CODE (varop) == CLOBBER)
7516 return x ? x : varop;
7518 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
7523 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
7524 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
7526 SUBST (XEXP (x, 0), varop);
7527 SUBST (XEXP (x, 1), const_rtx);
7530 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
7531 turn off all the bits that the shift would have turned off. */
7532 if (orig_code == LSHIFTRT && result_mode != shift_mode)
7533 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
7534 GET_MODE_MASK (result_mode) >> orig_count);
7536 /* Do the remainder of the processing in RESULT_MODE. */
7537 x = gen_lowpart_for_combine (result_mode, x);
7539 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
7542 x = gen_unary (NOT, result_mode, x);
7544 if (outer_op != NIL)
7546 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
7547 outer_const &= GET_MODE_MASK (result_mode);
7549 if (outer_op == AND)
7550 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
7551 else if (outer_op == SET)
7552 /* This means that we have determined that the result is
7553 equivalent to a constant. This should be rare. */
7554 x = GEN_INT (outer_const);
7555 else if (GET_RTX_CLASS (outer_op) == '1')
7556 x = gen_unary (outer_op, result_mode, x);
7558 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
7564 /* Like recog, but we receive the address of a pointer to a new pattern.
7565 We try to match the rtx that the pointer points to.
7566 If that fails, we may try to modify or replace the pattern,
7567 storing the replacement into the same pointer object.
7569 Modifications include deletion or addition of CLOBBERs.
7571 PNOTES is a pointer to a location where any REG_UNUSED notes added for
7572 the CLOBBERs are placed.
7574 The value is the final insn code from the pattern ultimately matched,
7578 recog_for_combine (pnewpat, insn, pnotes)
7583 register rtx pat = *pnewpat;
7584 int insn_code_number;
7585 int num_clobbers_to_add = 0;
7589 /* Is the result of combination a valid instruction? */
7590 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7592 /* If it isn't, there is the possibility that we previously had an insn
7593 that clobbered some register as a side effect, but the combined
7594 insn doesn't need to do that. So try once more without the clobbers
7595 unless this represents an ASM insn. */
7597 if (insn_code_number < 0 && ! check_asm_operands (pat)
7598 && GET_CODE (pat) == PARALLEL)
7602 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
7603 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
7606 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
7610 SUBST_INT (XVECLEN (pat, 0), pos);
7613 pat = XVECEXP (pat, 0, 0);
7615 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
7618 /* If we had any clobbers to add, make a new pattern than contains
7619 them. Then check to make sure that all of them are dead. */
7620 if (num_clobbers_to_add)
7622 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
7623 gen_rtvec (GET_CODE (pat) == PARALLEL
7624 ? XVECLEN (pat, 0) + num_clobbers_to_add
7625 : num_clobbers_to_add + 1));
7627 if (GET_CODE (pat) == PARALLEL)
7628 for (i = 0; i < XVECLEN (pat, 0); i++)
7629 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
7631 XVECEXP (newpat, 0, 0) = pat;
7633 add_clobbers (newpat, insn_code_number);
7635 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
7636 i < XVECLEN (newpat, 0); i++)
7638 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
7639 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
7641 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
7642 XEXP (XVECEXP (newpat, 0, i), 0), notes);
7650 return insn_code_number;
7653 /* Like gen_lowpart but for use by combine. In combine it is not possible
7654 to create any new pseudoregs. However, it is safe to create
7655 invalid memory addresses, because combine will try to recognize
7656 them and all they will do is make the combine attempt fail.
7658 If for some reason this cannot do its job, an rtx
7659 (clobber (const_int 0)) is returned.
7660 An insn containing that will not be recognized. */
7665 gen_lowpart_for_combine (mode, x)
7666 enum machine_mode mode;
7671 if (GET_MODE (x) == mode)
7674 /* We can only support MODE being wider than a word if X is a
7675 constant integer or has a mode the same size. */
7677 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
7678 && ! ((GET_MODE (x) == VOIDmode
7679 && (GET_CODE (x) == CONST_INT
7680 || GET_CODE (x) == CONST_DOUBLE))
7681 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
7682 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7684 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
7685 won't know what to do. So we will strip off the SUBREG here and
7686 process normally. */
7687 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
7690 if (GET_MODE (x) == mode)
7694 result = gen_lowpart_common (mode, x);
7698 if (GET_CODE (x) == MEM)
7700 register int offset = 0;
7703 /* Refuse to work on a volatile memory ref or one with a mode-dependent
7705 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
7706 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7708 /* If we want to refer to something bigger than the original memref,
7709 generate a perverse subreg instead. That will force a reload
7710 of the original memref X. */
7711 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
7712 return gen_rtx (SUBREG, mode, x, 0);
7714 #if WORDS_BIG_ENDIAN
7715 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
7716 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
7718 #if BYTES_BIG_ENDIAN
7719 /* Adjust the address so that the address-after-the-data
7721 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
7722 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
7724 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
7725 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
7726 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
7727 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
7731 /* If X is a comparison operator, rewrite it in a new mode. This
7732 probably won't match, but may allow further simplifications. */
7733 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
7734 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
7736 /* If we couldn't simplify X any other way, just enclose it in a
7737 SUBREG. Normally, this SUBREG won't match, but some patterns may
7738 include an explicit SUBREG or we may simplify it further in combine. */
7743 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
7744 word = ((GET_MODE_SIZE (GET_MODE (x))
7745 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
7747 return gen_rtx (SUBREG, mode, x, word);
7751 /* Make an rtx expression. This is a subset of gen_rtx and only supports
7752 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
7754 If the identical expression was previously in the insn (in the undobuf),
7755 it will be returned. Only if it is not found will a new expression
7760 gen_rtx_combine (va_alist)
7765 enum machine_mode mode;
7773 code = va_arg (p, enum rtx_code);
7774 mode = va_arg (p, enum machine_mode);
7775 n_args = GET_RTX_LENGTH (code);
7776 fmt = GET_RTX_FORMAT (code);
7778 if (n_args == 0 || n_args > 3)
7781 /* Get each arg and verify that it is supposed to be an expression. */
7782 for (j = 0; j < n_args; j++)
7787 args[j] = va_arg (p, rtx);
7790 /* See if this is in undobuf. Be sure we don't use objects that came
7791 from another insn; this could produce circular rtl structures. */
7793 for (i = previous_num_undos; i < undobuf.num_undo; i++)
7794 if (!undobuf.undo[i].is_int
7795 && GET_CODE (undobuf.undo[i].old_contents.rtx) == code
7796 && GET_MODE (undobuf.undo[i].old_contents.rtx) == mode)
7798 for (j = 0; j < n_args; j++)
7799 if (XEXP (undobuf.undo[i].old_contents.rtx, j) != args[j])
7803 return undobuf.undo[i].old_contents.rtx;
7806 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
7807 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
7808 rt = rtx_alloc (code);
7809 PUT_MODE (rt, mode);
7810 XEXP (rt, 0) = args[0];
7813 XEXP (rt, 1) = args[1];
7815 XEXP (rt, 2) = args[2];
7820 /* These routines make binary and unary operations by first seeing if they
7821 fold; if not, a new expression is allocated. */
7824 gen_binary (code, mode, op0, op1)
7826 enum machine_mode mode;
7832 if (GET_RTX_CLASS (code) == 'c'
7833 && (GET_CODE (op0) == CONST_INT
7834 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
7835 tem = op0, op0 = op1, op1 = tem;
7837 if (GET_RTX_CLASS (code) == '<')
7839 enum machine_mode op_mode = GET_MODE (op0);
7840 if (op_mode == VOIDmode)
7841 op_mode = GET_MODE (op1);
7842 result = simplify_relational_operation (code, op_mode, op0, op1);
7845 result = simplify_binary_operation (code, mode, op0, op1);
7850 /* Put complex operands first and constants second. */
7851 if (GET_RTX_CLASS (code) == 'c'
7852 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
7853 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
7854 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
7855 || (GET_CODE (op0) == SUBREG
7856 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
7857 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
7858 return gen_rtx_combine (code, mode, op1, op0);
7860 return gen_rtx_combine (code, mode, op0, op1);
7864 gen_unary (code, mode, op0)
7866 enum machine_mode mode;
7869 rtx result = simplify_unary_operation (code, mode, op0, mode);
7874 return gen_rtx_combine (code, mode, op0);
7877 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
7878 comparison code that will be tested.
7880 The result is a possibly different comparison code to use. *POP0 and
7881 *POP1 may be updated.
7883 It is possible that we might detect that a comparison is either always
7884 true or always false. However, we do not perform general constant
7885 folding in combine, so this knowledge isn't useful. Such tautologies
7886 should have been detected earlier. Hence we ignore all such cases. */
7888 static enum rtx_code
7889 simplify_comparison (code, pop0, pop1)
7898 enum machine_mode mode, tmode;
7900 /* Try a few ways of applying the same transformation to both operands. */
7903 /* If both operands are the same constant shift, see if we can ignore the
7904 shift. We can if the shift is a rotate or if the bits shifted out of
7905 this shift are known to be zero for both inputs and if the type of
7906 comparison is compatible with the shift. */
7907 if (GET_CODE (op0) == GET_CODE (op1)
7908 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
7909 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
7910 || ((GET_CODE (op0) == LSHIFTRT
7911 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7912 && (code != GT && code != LT && code != GE && code != LE))
7913 || (GET_CODE (op0) == ASHIFTRT
7914 && (code != GTU && code != LTU
7915 && code != GEU && code != GEU)))
7916 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7917 && INTVAL (XEXP (op0, 1)) >= 0
7918 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
7919 && XEXP (op0, 1) == XEXP (op1, 1))
7921 enum machine_mode mode = GET_MODE (op0);
7922 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7923 int shift_count = INTVAL (XEXP (op0, 1));
7925 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
7926 mask &= (mask >> shift_count) << shift_count;
7927 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
7928 mask = (mask & (mask << shift_count)) >> shift_count;
7930 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
7931 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
7932 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
7937 /* If both operands are AND's of a paradoxical SUBREG by constant, the
7938 SUBREGs are of the same mode, and, in both cases, the AND would
7939 be redundant if the comparison was done in the narrower mode,
7940 do the comparison in the narrower mode (e.g., we are AND'ing with 1
7941 and the operand's possibly nonzero bits are 0xffffff01; in that case
7942 if we only care about QImode, we don't need the AND). This case
7943 occurs if the output mode of an scc insn is not SImode and
7944 STORE_FLAG_VALUE == 1 (e.g., the 386). */
7946 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
7947 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7948 && GET_CODE (XEXP (op1, 1)) == CONST_INT
7949 && GET_CODE (XEXP (op0, 0)) == SUBREG
7950 && GET_CODE (XEXP (op1, 0)) == SUBREG
7951 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
7952 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
7953 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
7954 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7955 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7956 <= HOST_BITS_PER_WIDE_INT)
7957 && (nonzero_bits (SUBREG_REG (XEXP (op0, 0)),
7958 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
7959 & ~ INTVAL (XEXP (op0, 1))) == 0
7960 && (nonzero_bits (SUBREG_REG (XEXP (op1, 0)),
7961 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
7962 & ~ INTVAL (XEXP (op1, 1))) == 0)
7964 op0 = SUBREG_REG (XEXP (op0, 0));
7965 op1 = SUBREG_REG (XEXP (op1, 0));
7967 /* the resulting comparison is always unsigned since we masked off
7968 the original sign bit. */
7969 code = unsigned_condition (code);
7975 /* If the first operand is a constant, swap the operands and adjust the
7976 comparison code appropriately. */
7977 if (CONSTANT_P (op0))
7979 tem = op0, op0 = op1, op1 = tem;
7980 code = swap_condition (code);
7983 /* We now enter a loop during which we will try to simplify the comparison.
7984 For the most part, we only are concerned with comparisons with zero,
7985 but some things may really be comparisons with zero but not start
7986 out looking that way. */
7988 while (GET_CODE (op1) == CONST_INT)
7990 enum machine_mode mode = GET_MODE (op0);
7991 int mode_width = GET_MODE_BITSIZE (mode);
7992 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7993 int equality_comparison_p;
7994 int sign_bit_comparison_p;
7995 int unsigned_comparison_p;
7996 HOST_WIDE_INT const_op;
7998 /* We only want to handle integral modes. This catches VOIDmode,
7999 CCmode, and the floating-point modes. An exception is that we
8000 can handle VOIDmode if OP0 is a COMPARE or a comparison
8003 if (GET_MODE_CLASS (mode) != MODE_INT
8004 && ! (mode == VOIDmode
8005 && (GET_CODE (op0) == COMPARE
8006 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
8009 /* Get the constant we are comparing against and turn off all bits
8010 not on in our mode. */
8011 const_op = INTVAL (op1);
8012 if (mode_width <= HOST_BITS_PER_WIDE_INT)
8015 /* If we are comparing against a constant power of two and the value
8016 being compared can only have that single bit nonzero (e.g., it was
8017 `and'ed with that bit), we can replace this with a comparison
8020 && (code == EQ || code == NE || code == GE || code == GEU
8021 || code == LT || code == LTU)
8022 && mode_width <= HOST_BITS_PER_WIDE_INT
8023 && exact_log2 (const_op) >= 0
8024 && nonzero_bits (op0, mode) == const_op)
8026 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
8027 op1 = const0_rtx, const_op = 0;
8030 /* Similarly, if we are comparing a value known to be either -1 or
8031 0 with -1, change it to the opposite comparison against zero. */
8034 && (code == EQ || code == NE || code == GT || code == LE
8035 || code == GEU || code == LTU)
8036 && num_sign_bit_copies (op0, mode) == mode_width)
8038 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
8039 op1 = const0_rtx, const_op = 0;
8042 /* Do some canonicalizations based on the comparison code. We prefer
8043 comparisons against zero and then prefer equality comparisons.
8044 If we can reduce the size of a constant, we will do that too. */
8049 /* < C is equivalent to <= (C - 1) */
8053 op1 = GEN_INT (const_op);
8055 /* ... fall through to LE case below. */
8061 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
8065 op1 = GEN_INT (const_op);
8069 /* If we are doing a <= 0 comparison on a value known to have
8070 a zero sign bit, we can replace this with == 0. */
8071 else if (const_op == 0
8072 && mode_width <= HOST_BITS_PER_WIDE_INT
8073 && (nonzero_bits (op0, mode)
8074 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8079 /* >= C is equivalent to > (C - 1). */
8083 op1 = GEN_INT (const_op);
8085 /* ... fall through to GT below. */
8091 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
8095 op1 = GEN_INT (const_op);
8099 /* If we are doing a > 0 comparison on a value known to have
8100 a zero sign bit, we can replace this with != 0. */
8101 else if (const_op == 0
8102 && mode_width <= HOST_BITS_PER_WIDE_INT
8103 && (nonzero_bits (op0, mode)
8104 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
8109 /* < C is equivalent to <= (C - 1). */
8113 op1 = GEN_INT (const_op);
8115 /* ... fall through ... */
8118 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
8119 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8121 const_op = 0, op1 = const0_rtx;
8129 /* unsigned <= 0 is equivalent to == 0 */
8133 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
8134 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8136 const_op = 0, op1 = const0_rtx;
8142 /* >= C is equivalent to < (C - 1). */
8146 op1 = GEN_INT (const_op);
8148 /* ... fall through ... */
8151 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
8152 else if (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1))
8154 const_op = 0, op1 = const0_rtx;
8161 /* unsigned > 0 is equivalent to != 0 */
8165 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
8166 else if (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
8168 const_op = 0, op1 = const0_rtx;
8174 /* Compute some predicates to simplify code below. */
8176 equality_comparison_p = (code == EQ || code == NE);
8177 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
8178 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
8181 /* Now try cases based on the opcode of OP0. If none of the cases
8182 does a "continue", we exit this loop immediately after the
8185 switch (GET_CODE (op0))
8188 /* If we are extracting a single bit from a variable position in
8189 a constant that has only a single bit set and are comparing it
8190 with zero, we can convert this into an equality comparison
8191 between the position and the location of the single bit. We can't
8192 do this if bit endian and we don't have an extzv since we then
8193 can't know what mode to use for the endianness adjustment. */
8195 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
8196 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
8197 && XEXP (op0, 1) == const1_rtx
8198 && equality_comparison_p && const_op == 0
8199 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
8202 i = (GET_MODE_BITSIZE
8203 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
8206 op0 = XEXP (op0, 2);
8210 /* Result is nonzero iff shift count is equal to I. */
8211 code = reverse_condition (code);
8216 /* ... fall through ... */
8219 tem = expand_compound_operation (op0);
8228 /* If testing for equality, we can take the NOT of the constant. */
8229 if (equality_comparison_p
8230 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
8232 op0 = XEXP (op0, 0);
8237 /* If just looking at the sign bit, reverse the sense of the
8239 if (sign_bit_comparison_p)
8241 op0 = XEXP (op0, 0);
8242 code = (code == GE ? LT : GE);
8248 /* If testing for equality, we can take the NEG of the constant. */
8249 if (equality_comparison_p
8250 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
8252 op0 = XEXP (op0, 0);
8257 /* The remaining cases only apply to comparisons with zero. */
8261 /* When X is ABS or is known positive,
8262 (neg X) is < 0 if and only if X != 0. */
8264 if (sign_bit_comparison_p
8265 && (GET_CODE (XEXP (op0, 0)) == ABS
8266 || (mode_width <= HOST_BITS_PER_WIDE_INT
8267 && (nonzero_bits (XEXP (op0, 0), mode)
8268 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
8270 op0 = XEXP (op0, 0);
8271 code = (code == LT ? NE : EQ);
8275 /* If we have NEG of something whose two high-order bits are the
8276 same, we know that "(-a) < 0" is equivalent to "a > 0". */
8277 if (num_sign_bit_copies (op0, mode) >= 2)
8279 op0 = XEXP (op0, 0);
8280 code = swap_condition (code);
8286 /* If we are testing equality and our count is a constant, we
8287 can perform the inverse operation on our RHS. */
8288 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8289 && (tem = simplify_binary_operation (ROTATERT, mode,
8290 op1, XEXP (op0, 1))) != 0)
8292 op0 = XEXP (op0, 0);
8297 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
8298 a particular bit. Convert it to an AND of a constant of that
8299 bit. This will be converted into a ZERO_EXTRACT. */
8300 if (const_op == 0 && sign_bit_comparison_p
8301 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8302 && mode_width <= HOST_BITS_PER_WIDE_INT)
8304 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8307 - INTVAL (XEXP (op0, 1)))));
8308 code = (code == LT ? NE : EQ);
8312 /* ... fall through ... */
8315 /* ABS is ignorable inside an equality comparison with zero. */
8316 if (const_op == 0 && equality_comparison_p)
8318 op0 = XEXP (op0, 0);
8325 /* Can simplify (compare (zero/sign_extend FOO) CONST)
8326 to (compare FOO CONST) if CONST fits in FOO's mode and we
8327 are either testing inequality or have an unsigned comparison
8328 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
8329 if (! unsigned_comparison_p
8330 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8331 <= HOST_BITS_PER_WIDE_INT)
8332 && ((unsigned HOST_WIDE_INT) const_op
8333 < (((HOST_WIDE_INT) 1
8334 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
8336 op0 = XEXP (op0, 0);
8342 /* Check for the case where we are comparing A - C1 with C2,
8343 both constants are smaller than 1/2 the maxium positive
8344 value in MODE, and the comparison is equality or unsigned.
8345 In that case, if A is either zero-extended to MODE or has
8346 sufficient sign bits so that the high-order bit in MODE
8347 is a copy of the sign in the inner mode, we can prove that it is
8348 safe to do the operation in the wider mode. This simplifies
8349 many range checks. */
8351 if (mode_width <= HOST_BITS_PER_WIDE_INT
8352 && subreg_lowpart_p (op0)
8353 && GET_CODE (SUBREG_REG (op0)) == PLUS
8354 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
8355 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
8356 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
8357 < GET_MODE_MASK (mode) / 2)
8358 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
8359 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
8360 GET_MODE (SUBREG_REG (op0)))
8361 & ~ GET_MODE_MASK (mode))
8362 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
8363 GET_MODE (SUBREG_REG (op0)))
8364 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8365 - GET_MODE_BITSIZE (mode)))))
8367 op0 = SUBREG_REG (op0);
8371 /* If the inner mode is narrower and we are extracting the low part,
8372 we can treat the SUBREG as if it were a ZERO_EXTEND. */
8373 if (subreg_lowpart_p (op0)
8374 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
8375 /* Fall through */ ;
8379 /* ... fall through ... */
8382 if ((unsigned_comparison_p || equality_comparison_p)
8383 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
8384 <= HOST_BITS_PER_WIDE_INT)
8385 && ((unsigned HOST_WIDE_INT) const_op
8386 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
8388 op0 = XEXP (op0, 0);
8394 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
8395 this for equality comparisons due to pathological cases involving
8397 if (equality_comparison_p
8398 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8399 op1, XEXP (op0, 1))))
8401 op0 = XEXP (op0, 0);
8406 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
8407 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
8408 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
8410 op0 = XEXP (XEXP (op0, 0), 0);
8411 code = (code == LT ? EQ : NE);
8417 /* (eq (minus A B) C) -> (eq A (plus B C)) or
8418 (eq B (minus A C)), whichever simplifies. We can only do
8419 this for equality comparisons due to pathological cases involving
8421 if (equality_comparison_p
8422 && 0 != (tem = simplify_binary_operation (PLUS, mode,
8423 XEXP (op0, 1), op1)))
8425 op0 = XEXP (op0, 0);
8430 if (equality_comparison_p
8431 && 0 != (tem = simplify_binary_operation (MINUS, mode,
8432 XEXP (op0, 0), op1)))
8434 op0 = XEXP (op0, 1);
8439 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
8440 of bits in X minus 1, is one iff X > 0. */
8441 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
8442 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8443 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
8444 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8446 op0 = XEXP (op0, 1);
8447 code = (code == GE ? LE : GT);
8453 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
8454 if C is zero or B is a constant. */
8455 if (equality_comparison_p
8456 && 0 != (tem = simplify_binary_operation (XOR, mode,
8457 XEXP (op0, 1), op1)))
8459 op0 = XEXP (op0, 0);
8466 case LT: case LTU: case LE: case LEU:
8467 case GT: case GTU: case GE: case GEU:
8468 /* We can't do anything if OP0 is a condition code value, rather
8469 than an actual data value. */
8472 || XEXP (op0, 0) == cc0_rtx
8474 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
8477 /* Get the two operands being compared. */
8478 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
8479 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
8481 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
8483 /* Check for the cases where we simply want the result of the
8484 earlier test or the opposite of that result. */
8486 || (code == EQ && reversible_comparison_p (op0))
8487 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
8488 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8489 && (STORE_FLAG_VALUE
8490 & (((HOST_WIDE_INT) 1
8491 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
8493 || (code == GE && reversible_comparison_p (op0)))))
8495 code = (code == LT || code == NE
8496 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
8497 op0 = tem, op1 = tem1;
8503 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
8505 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
8506 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
8507 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
8509 op0 = XEXP (op0, 1);
8510 code = (code == GE ? GT : LE);
8516 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
8517 will be converted to a ZERO_EXTRACT later. */
8518 if (const_op == 0 && equality_comparison_p
8519 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
8520 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
8521 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
8523 op0 = simplify_and_const_int
8524 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
8526 XEXP (XEXP (op0, 0), 1)),
8531 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
8532 zero and X is a comparison and C1 and C2 describe only bits set
8533 in STORE_FLAG_VALUE, we can compare with X. */
8534 if (const_op == 0 && equality_comparison_p
8535 && mode_width <= HOST_BITS_PER_WIDE_INT
8536 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8537 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
8538 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
8539 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
8540 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8542 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8543 << INTVAL (XEXP (XEXP (op0, 0), 1)));
8544 if ((~ STORE_FLAG_VALUE & mask) == 0
8545 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
8546 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
8547 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
8549 op0 = XEXP (XEXP (op0, 0), 0);
8554 /* If we are doing an equality comparison of an AND of a bit equal
8555 to the sign bit, replace this with a LT or GE comparison of
8556 the underlying value. */
8557 if (equality_comparison_p
8559 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8560 && mode_width <= HOST_BITS_PER_WIDE_INT
8561 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
8562 == (HOST_WIDE_INT) 1 << (mode_width - 1)))
8564 op0 = XEXP (op0, 0);
8565 code = (code == EQ ? GE : LT);
8569 /* If this AND operation is really a ZERO_EXTEND from a narrower
8570 mode, the constant fits within that mode, and this is either an
8571 equality or unsigned comparison, try to do this comparison in
8572 the narrower mode. */
8573 if ((equality_comparison_p || unsigned_comparison_p)
8574 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8575 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
8576 & GET_MODE_MASK (mode))
8578 && const_op >> i == 0
8579 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
8581 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
8588 /* If we have (compare (xshift FOO N) (const_int C)) and
8589 the high order N bits of FOO (N+1 if an inequality comparison)
8590 are known to be zero, we can do this by comparing FOO with C
8591 shifted right N bits so long as the low-order N bits of C are
8593 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8594 && INTVAL (XEXP (op0, 1)) >= 0
8595 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
8596 < HOST_BITS_PER_WIDE_INT)
8598 & ((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1) == 0)
8599 && mode_width <= HOST_BITS_PER_WIDE_INT
8600 && (nonzero_bits (XEXP (op0, 0), mode)
8601 & ~ (mask >> (INTVAL (XEXP (op0, 1))
8602 + ! equality_comparison_p))) == 0)
8604 const_op >>= INTVAL (XEXP (op0, 1));
8605 op1 = GEN_INT (const_op);
8606 op0 = XEXP (op0, 0);
8610 /* If we are doing a sign bit comparison, it means we are testing
8611 a particular bit. Convert it to the appropriate AND. */
8612 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
8613 && mode_width <= HOST_BITS_PER_WIDE_INT)
8615 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8618 - INTVAL (XEXP (op0, 1)))));
8619 code = (code == LT ? NE : EQ);
8623 /* If this an equality comparison with zero and we are shifting
8624 the low bit to the sign bit, we can convert this to an AND of the
8626 if (const_op == 0 && equality_comparison_p
8627 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8628 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8630 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
8637 /* If this is an equality comparison with zero, we can do this
8638 as a logical shift, which might be much simpler. */
8639 if (equality_comparison_p && const_op == 0
8640 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
8642 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
8644 INTVAL (XEXP (op0, 1)));
8648 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
8649 do the comparison in a narrower mode. */
8650 if (! unsigned_comparison_p
8651 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8652 && GET_CODE (XEXP (op0, 0)) == ASHIFT
8653 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
8654 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
8655 MODE_INT, 1)) != BLKmode
8656 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
8657 || ((unsigned HOST_WIDE_INT) - const_op
8658 <= GET_MODE_MASK (tmode))))
8660 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
8664 /* ... fall through ... */
8666 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
8667 the low order N bits of FOO are known to be zero, we can do this
8668 by comparing FOO with C shifted left N bits so long as no
8670 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
8671 && INTVAL (XEXP (op0, 1)) >= 0
8672 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
8673 && mode_width <= HOST_BITS_PER_WIDE_INT
8674 && (nonzero_bits (XEXP (op0, 0), mode)
8675 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
8677 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
8680 const_op <<= INTVAL (XEXP (op0, 1));
8681 op1 = GEN_INT (const_op);
8682 op0 = XEXP (op0, 0);
8686 /* If we are using this shift to extract just the sign bit, we
8687 can replace this with an LT or GE comparison. */
8689 && (equality_comparison_p || sign_bit_comparison_p)
8690 && GET_CODE (XEXP (op0, 1)) == CONST_INT
8691 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
8693 op0 = XEXP (op0, 0);
8694 code = (code == NE || code == GT ? LT : GE);
8703 /* Now make any compound operations involved in this comparison. Then,
8704 check for an outmost SUBREG on OP0 that isn't doing anything or is
8705 paradoxical. The latter case can only occur when it is known that the
8706 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
8707 We can never remove a SUBREG for a non-equality comparison because the
8708 sign bit is in a different place in the underlying object. */
8710 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
8711 op1 = make_compound_operation (op1, SET);
8713 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8714 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8715 && (code == NE || code == EQ)
8716 && ((GET_MODE_SIZE (GET_MODE (op0))
8717 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
8719 op0 = SUBREG_REG (op0);
8720 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
8723 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
8724 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
8725 && (code == NE || code == EQ)
8726 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
8727 <= HOST_BITS_PER_WIDE_INT)
8728 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
8729 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
8730 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
8732 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
8733 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
8734 op0 = SUBREG_REG (op0), op1 = tem;
8736 /* We now do the opposite procedure: Some machines don't have compare
8737 insns in all modes. If OP0's mode is an integer mode smaller than a
8738 word and we can't do a compare in that mode, see if there is a larger
8739 mode for which we can do the compare. There are a number of cases in
8740 which we can use the wider mode. */
8742 mode = GET_MODE (op0);
8743 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
8744 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
8745 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
8746 for (tmode = GET_MODE_WIDER_MODE (mode);
8748 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
8749 tmode = GET_MODE_WIDER_MODE (tmode))
8750 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
8752 /* If the only nonzero bits in OP0 and OP1 are those in the
8753 narrower mode and this is an equality or unsigned comparison,
8754 we can use the wider mode. Similarly for sign-extended
8755 values and equality or signed comparisons. */
8756 if (((code == EQ || code == NE
8757 || code == GEU || code == GTU || code == LEU || code == LTU)
8758 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
8759 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
8760 || ((code == EQ || code == NE
8761 || code == GE || code == GT || code == LE || code == LT)
8762 && (num_sign_bit_copies (op0, tmode)
8763 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
8764 && (num_sign_bit_copies (op1, tmode)
8765 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
8767 op0 = gen_lowpart_for_combine (tmode, op0);
8768 op1 = gen_lowpart_for_combine (tmode, op1);
8772 /* If this is a test for negative, we can make an explicit
8773 test of the sign bit. */
8775 if (op1 == const0_rtx && (code == LT || code == GE)
8776 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8778 op0 = gen_binary (AND, tmode,
8779 gen_lowpart_for_combine (tmode, op0),
8780 GEN_INT ((HOST_WIDE_INT) 1
8781 << (GET_MODE_BITSIZE (mode) - 1)));
8782 code = (code == LT) ? NE : EQ;
8793 /* Return 1 if we know that X, a comparison operation, is not operating
8794 on a floating-point value or is EQ or NE, meaning that we can safely
8798 reversible_comparison_p (x)
8801 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
8802 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
8805 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
8811 x = get_last_value (XEXP (x, 0));
8812 return (x && GET_CODE (x) == COMPARE
8813 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
8819 /* Utility function for following routine. Called when X is part of a value
8820 being stored into reg_last_set_value. Sets reg_last_set_table_tick
8821 for each register mentioned. Similar to mention_regs in cse.c */
8824 update_table_tick (x)
8827 register enum rtx_code code = GET_CODE (x);
8828 register char *fmt = GET_RTX_FORMAT (code);
8833 int regno = REGNO (x);
8834 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8835 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
8837 for (i = regno; i < endregno; i++)
8838 reg_last_set_table_tick[i] = label_tick;
8843 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8844 /* Note that we can't have an "E" in values stored; see
8845 get_last_value_validate. */
8847 update_table_tick (XEXP (x, i));
8850 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
8851 are saying that the register is clobbered and we no longer know its
8852 value. If INSN is zero, don't update reg_last_set; this is only permitted
8853 with VALUE also zero and is used to invalidate the register. */
8856 record_value_for_reg (reg, insn, value)
8861 int regno = REGNO (reg);
8862 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
8863 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
8866 /* If VALUE contains REG and we have a previous value for REG, substitute
8867 the previous value. */
8868 if (value && insn && reg_overlap_mentioned_p (reg, value))
8872 /* Set things up so get_last_value is allowed to see anything set up to
8874 subst_low_cuid = INSN_CUID (insn);
8875 tem = get_last_value (reg);
8878 value = replace_rtx (copy_rtx (value), reg, tem);
8881 /* For each register modified, show we don't know its value, that
8882 its value has been updated, and that we don't know the location of
8883 the death of the register. */
8884 for (i = regno; i < endregno; i ++)
8887 reg_last_set[i] = insn;
8888 reg_last_set_value[i] = 0;
8889 reg_last_death[i] = 0;
8892 /* Mark registers that are being referenced in this value. */
8894 update_table_tick (value);
8896 /* Now update the status of each register being set.
8897 If someone is using this register in this block, set this register
8898 to invalid since we will get confused between the two lives in this
8899 basic block. This makes using this register always invalid. In cse, we
8900 scan the table to invalidate all entries using this register, but this
8901 is too much work for us. */
8903 for (i = regno; i < endregno; i++)
8905 reg_last_set_label[i] = label_tick;
8906 if (value && reg_last_set_table_tick[i] == label_tick)
8907 reg_last_set_invalid[i] = 1;
8909 reg_last_set_invalid[i] = 0;
8912 /* The value being assigned might refer to X (like in "x++;"). In that
8913 case, we must replace it with (clobber (const_int 0)) to prevent
8915 if (value && ! get_last_value_validate (&value,
8916 reg_last_set_label[regno], 0))
8918 value = copy_rtx (value);
8919 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
8923 /* For the main register being modified, update the value, the mode, the
8924 nonzero bits, and the number of sign bit copies. */
8926 reg_last_set_value[regno] = value;
8930 subst_low_cuid = INSN_CUID (insn);
8931 reg_last_set_mode[regno] = GET_MODE (reg);
8932 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
8933 reg_last_set_sign_bit_copies[regno]
8934 = num_sign_bit_copies (value, GET_MODE (reg));
8938 /* Used for communication between the following two routines. */
8939 static rtx record_dead_insn;
8941 /* Called via note_stores from record_dead_and_set_regs to handle one
8942 SET or CLOBBER in an insn. */
8945 record_dead_and_set_regs_1 (dest, setter)
8948 if (GET_CODE (dest) == REG)
8950 /* If we are setting the whole register, we know its value. Otherwise
8951 show that we don't know the value. We can handle SUBREG in
8953 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
8954 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
8955 else if (GET_CODE (setter) == SET
8956 && GET_CODE (SET_DEST (setter)) == SUBREG
8957 && SUBREG_REG (SET_DEST (setter)) == dest
8958 && subreg_lowpart_p (SET_DEST (setter)))
8959 record_value_for_reg (dest, record_dead_insn,
8960 gen_lowpart_for_combine (GET_MODE (dest),
8963 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
8965 else if (GET_CODE (dest) == MEM
8966 /* Ignore pushes, they clobber nothing. */
8967 && ! push_operand (dest, GET_MODE (dest)))
8968 mem_last_set = INSN_CUID (record_dead_insn);
8971 /* Update the records of when each REG was most recently set or killed
8972 for the things done by INSN. This is the last thing done in processing
8973 INSN in the combiner loop.
8975 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
8976 similar information mem_last_set (which insn most recently modified memory)
8977 and last_call_cuid (which insn was the most recent subroutine call). */
8980 record_dead_and_set_regs (insn)
8986 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
8988 if (REG_NOTE_KIND (link) == REG_DEAD
8989 && GET_CODE (XEXP (link, 0)) == REG)
8991 int regno = REGNO (XEXP (link, 0));
8993 = regno + (regno < FIRST_PSEUDO_REGISTER
8994 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
8997 for (i = regno; i < endregno; i++)
8998 reg_last_death[i] = insn;
9000 else if (REG_NOTE_KIND (link) == REG_INC)
9001 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
9004 if (GET_CODE (insn) == CALL_INSN)
9006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
9007 if (call_used_regs[i])
9009 reg_last_set_value[i] = 0;
9010 reg_last_death[i] = 0;
9013 last_call_cuid = mem_last_set = INSN_CUID (insn);
9016 record_dead_insn = insn;
9017 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
9020 /* Utility routine for the following function. Verify that all the registers
9021 mentioned in *LOC are valid when *LOC was part of a value set when
9022 label_tick == TICK. Return 0 if some are not.
9024 If REPLACE is non-zero, replace the invalid reference with
9025 (clobber (const_int 0)) and return 1. This replacement is useful because
9026 we often can get useful information about the form of a value (e.g., if
9027 it was produced by a shift that always produces -1 or 0) even though
9028 we don't know exactly what registers it was produced from. */
9031 get_last_value_validate (loc, tick, replace)
9037 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
9038 int len = GET_RTX_LENGTH (GET_CODE (x));
9041 if (GET_CODE (x) == REG)
9043 int regno = REGNO (x);
9044 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9045 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
9048 for (j = regno; j < endregno; j++)
9049 if (reg_last_set_invalid[j]
9050 /* If this is a pseudo-register that was only set once, it is
9052 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
9053 && reg_last_set_label[j] > tick))
9056 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
9063 for (i = 0; i < len; i++)
9065 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
9066 /* Don't bother with these. They shouldn't occur anyway. */
9070 /* If we haven't found a reason for it to be invalid, it is valid. */
9074 /* Get the last value assigned to X, if known. Some registers
9075 in the value may be replaced with (clobber (const_int 0)) if their value
9076 is known longer known reliably. */
9085 /* If this is a non-paradoxical SUBREG, get the value of its operand and
9086 then convert it to the desired mode. If this is a paradoxical SUBREG,
9087 we cannot predict what values the "extra" bits might have. */
9088 if (GET_CODE (x) == SUBREG
9089 && subreg_lowpart_p (x)
9090 && (GET_MODE_SIZE (GET_MODE (x))
9091 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
9092 && (value = get_last_value (SUBREG_REG (x))) != 0)
9093 return gen_lowpart_for_combine (GET_MODE (x), value);
9095 if (GET_CODE (x) != REG)
9099 value = reg_last_set_value[regno];
9101 /* If we don't have a value or if it isn't for this basic block, return 0. */
9104 || (reg_n_sets[regno] != 1
9105 && reg_last_set_label[regno] != label_tick))
9108 /* If the value was set in a later insn that the ones we are processing,
9109 we can't use it even if the register was only set once, but make a quick
9110 check to see if the previous insn set it to something. This is commonly
9111 the case when the same pseudo is used by repeated insns. */
9113 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
9117 for (insn = prev_nonnote_insn (subst_insn);
9118 insn && INSN_CUID (insn) >= subst_low_cuid;
9119 insn = prev_nonnote_insn (insn))
9123 && (set = single_set (insn)) != 0
9124 && rtx_equal_p (SET_DEST (set), x))
9126 value = SET_SRC (set);
9128 /* Make sure that VALUE doesn't reference X. Replace any
9129 expliit references with a CLOBBER. If there are any remaining
9130 references (rare), don't use the value. */
9132 if (reg_mentioned_p (x, value))
9133 value = replace_rtx (copy_rtx (value), x,
9134 gen_rtx (CLOBBER, GET_MODE (x), const0_rtx));
9136 if (reg_overlap_mentioned_p (x, value))
9143 /* If the value has all its registers valid, return it. */
9144 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
9147 /* Otherwise, make a copy and replace any invalid register with
9148 (clobber (const_int 0)). If that fails for some reason, return 0. */
9150 value = copy_rtx (value);
9151 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
9157 /* Return nonzero if expression X refers to a REG or to memory
9158 that is set in an instruction more recent than FROM_CUID. */
9161 use_crosses_set_p (x, from_cuid)
9167 register enum rtx_code code = GET_CODE (x);
9171 register int regno = REGNO (x);
9172 #ifdef PUSH_ROUNDING
9173 /* Don't allow uses of the stack pointer to be moved,
9174 because we don't know whether the move crosses a push insn. */
9175 if (regno == STACK_POINTER_REGNUM)
9178 return (reg_last_set[regno]
9179 && INSN_CUID (reg_last_set[regno]) > from_cuid);
9182 if (code == MEM && mem_last_set > from_cuid)
9185 fmt = GET_RTX_FORMAT (code);
9187 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9192 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9193 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
9196 else if (fmt[i] == 'e'
9197 && use_crosses_set_p (XEXP (x, i), from_cuid))
9203 /* Define three variables used for communication between the following
9206 static int reg_dead_regno, reg_dead_endregno;
9207 static int reg_dead_flag;
9209 /* Function called via note_stores from reg_dead_at_p.
9211 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
9212 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
9215 reg_dead_at_p_1 (dest, x)
9219 int regno, endregno;
9221 if (GET_CODE (dest) != REG)
9224 regno = REGNO (dest);
9225 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
9226 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
9228 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
9229 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
9232 /* Return non-zero if REG is known to be dead at INSN.
9234 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
9235 referencing REG, it is dead. If we hit a SET referencing REG, it is
9236 live. Otherwise, see if it is live or dead at the start of the basic
9240 reg_dead_at_p (reg, insn)
9246 /* Set variables for reg_dead_at_p_1. */
9247 reg_dead_regno = REGNO (reg);
9248 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
9249 ? HARD_REGNO_NREGS (reg_dead_regno,
9255 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
9256 beginning of function. */
9257 for (; insn && GET_CODE (insn) != CODE_LABEL;
9258 insn = prev_nonnote_insn (insn))
9260 note_stores (PATTERN (insn), reg_dead_at_p_1);
9262 return reg_dead_flag == 1 ? 1 : 0;
9264 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
9268 /* Get the basic block number that we were in. */
9273 for (block = 0; block < n_basic_blocks; block++)
9274 if (insn == basic_block_head[block])
9277 if (block == n_basic_blocks)
9281 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
9282 if (basic_block_live_at_start[block][i / REGSET_ELT_BITS]
9283 & ((REGSET_ELT_TYPE) 1 << (i % REGSET_ELT_BITS)))
9289 /* Remove register number REGNO from the dead registers list of INSN.
9291 Return the note used to record the death, if there was one. */
9294 remove_death (regno, insn)
9298 register rtx note = find_regno_note (insn, REG_DEAD, regno);
9302 reg_n_deaths[regno]--;
9303 remove_note (insn, note);
9309 /* For each register (hardware or pseudo) used within expression X, if its
9310 death is in an instruction with cuid between FROM_CUID (inclusive) and
9311 TO_INSN (exclusive), put a REG_DEAD note for that register in the
9312 list headed by PNOTES.
9314 This is done when X is being merged by combination into TO_INSN. These
9315 notes will then be distributed as needed. */
9318 move_deaths (x, from_cuid, to_insn, pnotes)
9325 register int len, i;
9326 register enum rtx_code code = GET_CODE (x);
9330 register int regno = REGNO (x);
9331 register rtx where_dead = reg_last_death[regno];
9333 if (where_dead && INSN_CUID (where_dead) >= from_cuid
9334 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
9336 rtx note = remove_death (regno, where_dead);
9338 /* It is possible for the call above to return 0. This can occur
9339 when reg_last_death points to I2 or I1 that we combined with.
9340 In that case make a new note.
9342 We must also check for the case where X is a hard register
9343 and NOTE is a death note for a range of hard registers
9344 including X. In that case, we must put REG_DEAD notes for
9345 the remaining registers in place of NOTE. */
9347 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
9348 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
9349 != GET_MODE_SIZE (GET_MODE (x))))
9351 int deadregno = REGNO (XEXP (note, 0));
9353 = (deadregno + HARD_REGNO_NREGS (deadregno,
9354 GET_MODE (XEXP (note, 0))));
9355 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9358 for (i = deadregno; i < deadend; i++)
9359 if (i < regno || i >= ourend)
9360 REG_NOTES (where_dead)
9361 = gen_rtx (EXPR_LIST, REG_DEAD,
9362 gen_rtx (REG, word_mode, i),
9363 REG_NOTES (where_dead));
9366 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
9368 XEXP (note, 1) = *pnotes;
9372 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
9374 reg_n_deaths[regno]++;
9380 else if (GET_CODE (x) == SET)
9382 rtx dest = SET_DEST (x);
9384 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
9386 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
9387 that accesses one word of a multi-word item, some
9388 piece of everything register in the expression is used by
9389 this insn, so remove any old death. */
9391 if (GET_CODE (dest) == ZERO_EXTRACT
9392 || GET_CODE (dest) == STRICT_LOW_PART
9393 || (GET_CODE (dest) == SUBREG
9394 && (((GET_MODE_SIZE (GET_MODE (dest))
9395 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9396 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
9397 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
9399 move_deaths (dest, from_cuid, to_insn, pnotes);
9403 /* If this is some other SUBREG, we know it replaces the entire
9404 value, so use that as the destination. */
9405 if (GET_CODE (dest) == SUBREG)
9406 dest = SUBREG_REG (dest);
9408 /* If this is a MEM, adjust deaths of anything used in the address.
9409 For a REG (the only other possibility), the entire value is
9410 being replaced so the old value is not used in this insn. */
9412 if (GET_CODE (dest) == MEM)
9413 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
9417 else if (GET_CODE (x) == CLOBBER)
9420 len = GET_RTX_LENGTH (code);
9421 fmt = GET_RTX_FORMAT (code);
9423 for (i = 0; i < len; i++)
9428 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9429 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
9431 else if (fmt[i] == 'e')
9432 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
9436 /* Return 1 if X is the target of a bit-field assignment in BODY, the
9437 pattern of an insn. X must be a REG. */
9440 reg_bitfield_target_p (x, body)
9446 if (GET_CODE (body) == SET)
9448 rtx dest = SET_DEST (body);
9450 int regno, tregno, endregno, endtregno;
9452 if (GET_CODE (dest) == ZERO_EXTRACT)
9453 target = XEXP (dest, 0);
9454 else if (GET_CODE (dest) == STRICT_LOW_PART)
9455 target = SUBREG_REG (XEXP (dest, 0));
9459 if (GET_CODE (target) == SUBREG)
9460 target = SUBREG_REG (target);
9462 if (GET_CODE (target) != REG)
9465 tregno = REGNO (target), regno = REGNO (x);
9466 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
9469 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
9470 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
9472 return endregno > tregno && regno < endtregno;
9475 else if (GET_CODE (body) == PARALLEL)
9476 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
9477 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
9483 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
9484 as appropriate. I3 and I2 are the insns resulting from the combination
9485 insns including FROM (I2 may be zero).
9487 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
9488 not need REG_DEAD notes because they are being substituted for. This
9489 saves searching in the most common cases.
9491 Each note in the list is either ignored or placed on some insns, depending
9492 on the type of note. */
9495 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
9499 rtx elim_i2, elim_i1;
9501 rtx note, next_note;
9504 for (note = notes; note; note = next_note)
9506 rtx place = 0, place2 = 0;
9508 /* If this NOTE references a pseudo register, ensure it references
9509 the latest copy of that register. */
9510 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
9511 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
9512 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
9514 next_note = XEXP (note, 1);
9515 switch (REG_NOTE_KIND (note))
9518 /* If this register is set or clobbered in I3, put the note there
9519 unless there is one already. */
9520 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
9522 if (! (GET_CODE (XEXP (note, 0)) == REG
9523 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
9524 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
9527 /* Otherwise, if this register is used by I3, then this register
9528 now dies here, so we must put a REG_DEAD note here unless there
9530 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
9531 && ! (GET_CODE (XEXP (note, 0)) == REG
9532 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
9533 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
9535 PUT_REG_NOTE_KIND (note, REG_DEAD);
9543 /* These notes say something about results of an insn. We can
9544 only support them if they used to be on I3 in which case they
9545 remain on I3. Otherwise they are ignored.
9547 If the note refers to an expression that is not a constant, we
9548 must also ignore the note since we cannot tell whether the
9549 equivalence is still true. It might be possible to do
9550 slightly better than this (we only have a problem if I2DEST
9551 or I1DEST is present in the expression), but it doesn't
9552 seem worth the trouble. */
9555 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
9560 case REG_NO_CONFLICT:
9562 /* These notes say something about how a register is used. They must
9563 be present on any use of the register in I2 or I3. */
9564 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
9567 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
9577 /* It is too much trouble to try to see if this note is still
9578 correct in all situations. It is better to simply delete it. */
9582 /* If the insn previously containing this note still exists,
9583 put it back where it was. Otherwise move it to the previous
9584 insn. Adjust the corresponding REG_LIBCALL note. */
9585 if (GET_CODE (from_insn) != NOTE)
9589 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
9590 place = prev_real_insn (from_insn);
9592 XEXP (tem, 0) = place;
9597 /* This is handled similarly to REG_RETVAL. */
9598 if (GET_CODE (from_insn) != NOTE)
9602 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
9603 place = next_real_insn (from_insn);
9605 XEXP (tem, 0) = place;
9610 /* If the register is used as an input in I3, it dies there.
9611 Similarly for I2, if it is non-zero and adjacent to I3.
9613 If the register is not used as an input in either I3 or I2
9614 and it is not one of the registers we were supposed to eliminate,
9615 there are two possibilities. We might have a non-adjacent I2
9616 or we might have somehow eliminated an additional register
9617 from a computation. For example, we might have had A & B where
9618 we discover that B will always be zero. In this case we will
9619 eliminate the reference to A.
9621 In both cases, we must search to see if we can find a previous
9622 use of A and put the death note there. */
9624 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
9626 else if (i2 != 0 && next_nonnote_insn (i2) == i3
9627 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9630 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
9633 /* If the register is used in both I2 and I3 and it dies in I3,
9634 we might have added another reference to it. If reg_n_refs
9635 was 2, bump it to 3. This has to be correct since the
9636 register must have been set somewhere. The reason this is
9637 done is because local-alloc.c treats 2 references as a
9640 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
9641 && reg_n_refs[REGNO (XEXP (note, 0))]== 2
9642 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
9643 reg_n_refs[REGNO (XEXP (note, 0))] = 3;
9646 for (tem = prev_nonnote_insn (i3);
9647 tem && (GET_CODE (tem) == INSN
9648 || GET_CODE (tem) == CALL_INSN);
9649 tem = prev_nonnote_insn (tem))
9651 /* If the register is being set at TEM, see if that is all
9652 TEM is doing. If so, delete TEM. Otherwise, make this
9653 into a REG_UNUSED note instead. */
9654 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
9656 rtx set = single_set (tem);
9658 /* Verify that it was the set, and not a clobber that
9659 modified the register. */
9661 if (set != 0 && ! side_effects_p (SET_SRC (set))
9662 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
9664 /* Move the notes and links of TEM elsewhere.
9665 This might delete other dead insns recursively.
9666 First set the pattern to something that won't use
9669 PATTERN (tem) = pc_rtx;
9671 distribute_notes (REG_NOTES (tem), tem, tem,
9672 NULL_RTX, NULL_RTX, NULL_RTX);
9673 distribute_links (LOG_LINKS (tem));
9675 PUT_CODE (tem, NOTE);
9676 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
9677 NOTE_SOURCE_FILE (tem) = 0;
9681 PUT_REG_NOTE_KIND (note, REG_UNUSED);
9683 /* If there isn't already a REG_UNUSED note, put one
9685 if (! find_regno_note (tem, REG_UNUSED,
9686 REGNO (XEXP (note, 0))))
9691 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
9698 /* If the register is set or already dead at PLACE, we needn't do
9699 anything with this note if it is still a REG_DEAD note.
9701 Note that we cannot use just `dead_or_set_p' here since we can
9702 convert an assignment to a register into a bit-field assignment.
9703 Therefore, we must also omit the note if the register is the
9704 target of a bitfield assignment. */
9706 if (place && REG_NOTE_KIND (note) == REG_DEAD)
9708 int regno = REGNO (XEXP (note, 0));
9710 if (dead_or_set_p (place, XEXP (note, 0))
9711 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
9713 /* Unless the register previously died in PLACE, clear
9714 reg_last_death. [I no longer understand why this is
9716 if (reg_last_death[regno] != place)
9717 reg_last_death[regno] = 0;
9721 reg_last_death[regno] = place;
9723 /* If this is a death note for a hard reg that is occupying
9724 multiple registers, ensure that we are still using all
9725 parts of the object. If we find a piece of the object
9726 that is unused, we must add a USE for that piece before
9727 PLACE and put the appropriate REG_DEAD note on it.
9729 An alternative would be to put a REG_UNUSED for the pieces
9730 on the insn that set the register, but that can't be done if
9731 it is not in the same block. It is simpler, though less
9732 efficient, to add the USE insns. */
9734 if (place && regno < FIRST_PSEUDO_REGISTER
9735 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
9738 = regno + HARD_REGNO_NREGS (regno,
9739 GET_MODE (XEXP (note, 0)));
9743 for (i = regno; i < endregno; i++)
9744 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
9746 rtx piece = gen_rtx (REG, word_mode, i);
9749 /* See if we already placed a USE note for this
9750 register in front of PLACE. */
9752 GET_CODE (PREV_INSN (p)) == INSN
9753 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
9755 if (rtx_equal_p (piece,
9756 XEXP (PATTERN (PREV_INSN (p)), 0)))
9765 = emit_insn_before (gen_rtx (USE, VOIDmode,
9768 REG_NOTES (use_insn)
9769 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
9770 REG_NOTES (use_insn));
9776 /* Check for the case where the register dying partially
9777 overlaps the register set by this insn. */
9779 for (i = regno; i < endregno; i++)
9780 if (dead_or_set_regno_p (place, i))
9788 /* Put only REG_DEAD notes for pieces that are
9789 still used and that are not already dead or set. */
9791 for (i = regno; i < endregno; i++)
9793 rtx piece = gen_rtx (REG, word_mode, i);
9795 if (reg_referenced_p (piece, PATTERN (place))
9796 && ! dead_or_set_p (place, piece)
9797 && ! reg_bitfield_target_p (piece,
9799 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
9811 /* Any other notes should not be present at this point in the
9818 XEXP (note, 1) = REG_NOTES (place);
9819 REG_NOTES (place) = note;
9821 else if ((REG_NOTE_KIND (note) == REG_DEAD
9822 || REG_NOTE_KIND (note) == REG_UNUSED)
9823 && GET_CODE (XEXP (note, 0)) == REG)
9824 reg_n_deaths[REGNO (XEXP (note, 0))]--;
9828 if ((REG_NOTE_KIND (note) == REG_DEAD
9829 || REG_NOTE_KIND (note) == REG_UNUSED)
9830 && GET_CODE (XEXP (note, 0)) == REG)
9831 reg_n_deaths[REGNO (XEXP (note, 0))]++;
9833 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
9834 XEXP (note, 0), REG_NOTES (place2));
9839 /* Similarly to above, distribute the LOG_LINKS that used to be present on
9840 I3, I2, and I1 to new locations. This is also called in one case to
9841 add a link pointing at I3 when I3's destination is changed. */
9844 distribute_links (links)
9847 rtx link, next_link;
9849 for (link = links; link; link = next_link)
9855 next_link = XEXP (link, 1);
9857 /* If the insn that this link points to is a NOTE or isn't a single
9858 set, ignore it. In the latter case, it isn't clear what we
9859 can do other than ignore the link, since we can't tell which
9860 register it was for. Such links wouldn't be used by combine
9863 It is not possible for the destination of the target of the link to
9864 have been changed by combine. The only potential of this is if we
9865 replace I3, I2, and I1 by I3 and I2. But in that case the
9866 destination of I2 also remains unchanged. */
9868 if (GET_CODE (XEXP (link, 0)) == NOTE
9869 || (set = single_set (XEXP (link, 0))) == 0)
9872 reg = SET_DEST (set);
9873 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
9874 || GET_CODE (reg) == SIGN_EXTRACT
9875 || GET_CODE (reg) == STRICT_LOW_PART)
9876 reg = XEXP (reg, 0);
9878 /* A LOG_LINK is defined as being placed on the first insn that uses
9879 a register and points to the insn that sets the register. Start
9880 searching at the next insn after the target of the link and stop
9881 when we reach a set of the register or the end of the basic block.
9883 Note that this correctly handles the link that used to point from
9884 I3 to I2. Also note that not much searching is typically done here
9885 since most links don't point very far away. */
9887 for (insn = NEXT_INSN (XEXP (link, 0));
9888 (insn && GET_CODE (insn) != CODE_LABEL
9889 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
9890 insn = NEXT_INSN (insn))
9891 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
9892 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
9894 if (reg_referenced_p (reg, PATTERN (insn)))
9899 /* If we found a place to put the link, place it there unless there
9900 is already a link to the same insn as LINK at that point. */
9906 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
9907 if (XEXP (link2, 0) == XEXP (link, 0))
9912 XEXP (link, 1) = LOG_LINKS (place);
9913 LOG_LINKS (place) = link;
9920 dump_combine_stats (file)
9925 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
9926 combine_attempts, combine_merges, combine_extras, combine_successes);
9930 dump_combine_total_stats (file)
9935 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
9936 total_attempts, total_merges, total_extras, total_successes);