1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
83 #include "hard-reg-set.h"
84 #include "basic-block.h"
85 #include "insn-config.h"
87 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
89 #include "insn-flags.h"
90 #include "insn-codes.h"
91 #include "insn-attr.h"
96 #ifndef ACCUMULATE_OUTGOING_ARGS
97 #define ACCUMULATE_OUTGOING_ARGS 0
100 /* Supply a default definition for PUSH_ARGS. */
103 #define PUSH_ARGS !ACCUMULATE_OUTGOING_ARGS
109 /* It is not safe to use ordinary gen_lowpart in combine.
110 Use gen_lowpart_for_combine instead. See comments there. */
111 #define gen_lowpart dont_use_gen_lowpart_you_dummy
113 /* Number of attempts to combine instructions in this function. */
115 static int combine_attempts;
117 /* Number of attempts that got as far as substitution in this function. */
119 static int combine_merges;
121 /* Number of instructions combined with added SETs in this function. */
123 static int combine_extras;
125 /* Number of instructions combined in this function. */
127 static int combine_successes;
129 /* Totals over entire compilation. */
131 static int total_attempts, total_merges, total_extras, total_successes;
134 /* Vector mapping INSN_UIDs to cuids.
135 The cuids are like uids but increase monotonically always.
136 Combine always uses cuids so that it can compare them.
137 But actually renumbering the uids, which we used to do,
138 proves to be a bad idea because it makes it hard to compare
139 the dumps produced by earlier passes with those from later passes. */
141 static int *uid_cuid;
142 static int max_uid_cuid;
144 /* Get the cuid of an insn. */
146 #define INSN_CUID(INSN) \
147 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
149 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
150 BITS_PER_WORD would invoke undefined behavior. Work around it. */
152 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
153 (((unsigned HOST_WIDE_INT)(val) << (BITS_PER_WORD - 1)) << 1)
155 /* Maximum register number, which is the size of the tables below. */
157 static unsigned int combine_max_regno;
159 /* Record last point of death of (hard or pseudo) register n. */
161 static rtx *reg_last_death;
163 /* Record last point of modification of (hard or pseudo) register n. */
165 static rtx *reg_last_set;
167 /* Record the cuid of the last insn that invalidated memory
168 (anything that writes memory, and subroutine calls, but not pushes). */
170 static int mem_last_set;
172 /* Record the cuid of the last CALL_INSN
173 so we can tell whether a potential combination crosses any calls. */
175 static int last_call_cuid;
177 /* When `subst' is called, this is the insn that is being modified
178 (by combining in a previous insn). The PATTERN of this insn
179 is still the old pattern partially modified and it should not be
180 looked at, but this may be used to examine the successors of the insn
181 to judge whether a simplification is valid. */
183 static rtx subst_insn;
185 /* This is an insn that belongs before subst_insn, but is not currently
186 on the insn chain. */
188 static rtx subst_prev_insn;
190 /* This is the lowest CUID that `subst' is currently dealing with.
191 get_last_value will not return a value if the register was set at or
192 after this CUID. If not for this mechanism, we could get confused if
193 I2 or I1 in try_combine were an insn that used the old value of a register
194 to obtain a new value. In that case, we might erroneously get the
195 new value of the register when we wanted the old one. */
197 static int subst_low_cuid;
199 /* This contains any hard registers that are used in newpat; reg_dead_at_p
200 must consider all these registers to be always live. */
202 static HARD_REG_SET newpat_used_regs;
204 /* This is an insn to which a LOG_LINKS entry has been added. If this
205 insn is the earlier than I2 or I3, combine should rescan starting at
208 static rtx added_links_insn;
210 /* Basic block number of the block in which we are performing combines. */
211 static int this_basic_block;
213 /* A bitmap indicating which blocks had registers go dead at entry.
214 After combine, we'll need to re-do global life analysis with
215 those blocks as starting points. */
216 static sbitmap refresh_blocks;
217 static int need_refresh;
219 /* The next group of arrays allows the recording of the last value assigned
220 to (hard or pseudo) register n. We use this information to see if a
221 operation being processed is redundant given a prior operation performed
222 on the register. For example, an `and' with a constant is redundant if
223 all the zero bits are already known to be turned off.
225 We use an approach similar to that used by cse, but change it in the
228 (1) We do not want to reinitialize at each label.
229 (2) It is useful, but not critical, to know the actual value assigned
230 to a register. Often just its form is helpful.
232 Therefore, we maintain the following arrays:
234 reg_last_set_value the last value assigned
235 reg_last_set_label records the value of label_tick when the
236 register was assigned
237 reg_last_set_table_tick records the value of label_tick when a
238 value using the register is assigned
239 reg_last_set_invalid set to non-zero when it is not valid
240 to use the value of this register in some
243 To understand the usage of these tables, it is important to understand
244 the distinction between the value in reg_last_set_value being valid
245 and the register being validly contained in some other expression in the
248 Entry I in reg_last_set_value is valid if it is non-zero, and either
249 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
251 Register I may validly appear in any expression returned for the value
252 of another register if reg_n_sets[i] is 1. It may also appear in the
253 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
254 reg_last_set_invalid[j] is zero.
256 If an expression is found in the table containing a register which may
257 not validly appear in an expression, the register is replaced by
258 something that won't match, (clobber (const_int 0)).
260 reg_last_set_invalid[i] is set non-zero when register I is being assigned
261 to and reg_last_set_table_tick[i] == label_tick. */
263 /* Record last value assigned to (hard or pseudo) register n. */
265 static rtx *reg_last_set_value;
267 /* Record the value of label_tick when the value for register n is placed in
268 reg_last_set_value[n]. */
270 static int *reg_last_set_label;
272 /* Record the value of label_tick when an expression involving register n
273 is placed in reg_last_set_value. */
275 static int *reg_last_set_table_tick;
277 /* Set non-zero if references to register n in expressions should not be
280 static char *reg_last_set_invalid;
282 /* Incremented for each label. */
284 static int label_tick;
286 /* Some registers that are set more than once and used in more than one
287 basic block are nevertheless always set in similar ways. For example,
288 a QImode register may be loaded from memory in two places on a machine
289 where byte loads zero extend.
291 We record in the following array what we know about the nonzero
292 bits of a register, specifically which bits are known to be zero.
294 If an entry is zero, it means that we don't know anything special. */
296 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
298 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
299 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
301 static enum machine_mode nonzero_bits_mode;
303 /* Nonzero if we know that a register has some leading bits that are always
304 equal to the sign bit. */
306 static unsigned char *reg_sign_bit_copies;
308 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
309 It is zero while computing them and after combine has completed. This
310 former test prevents propagating values based on previously set values,
311 which can be incorrect if a variable is modified in a loop. */
313 static int nonzero_sign_valid;
315 /* These arrays are maintained in parallel with reg_last_set_value
316 and are used to store the mode in which the register was last set,
317 the bits that were known to be zero when it was last set, and the
318 number of sign bits copies it was known to have when it was last set. */
320 static enum machine_mode *reg_last_set_mode;
321 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
322 static char *reg_last_set_sign_bit_copies;
324 /* Record one modification to rtl structure
325 to be undone by storing old_contents into *where.
326 is_int is 1 if the contents are an int. */
332 union {rtx r; unsigned int i;} old_contents;
333 union {rtx *r; unsigned int *i;} where;
336 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
337 num_undo says how many are currently recorded.
339 other_insn is nonzero if we have modified some other insn in the process
340 of working on subst_insn. It must be verified too.
342 previous_undos is the value of undobuf.undos when we started processing
343 this substitution. This will prevent gen_rtx_combine from re-used a piece
344 from the previous expression. Doing so can produce circular rtl
351 struct undo *previous_undos;
355 static struct undobuf undobuf;
357 /* Number of times the pseudo being substituted for
358 was found and replaced. */
360 static int n_occurrences;
362 static void do_SUBST PARAMS ((rtx *, rtx));
363 static void do_SUBST_INT PARAMS ((unsigned int *,
365 static void init_reg_last_arrays PARAMS ((void));
366 static void setup_incoming_promotions PARAMS ((void));
367 static void set_nonzero_bits_and_sign_copies PARAMS ((rtx, rtx, void *));
368 static int cant_combine_insn_p PARAMS ((rtx));
369 static int can_combine_p PARAMS ((rtx, rtx, rtx, rtx, rtx *, rtx *));
370 static int sets_function_arg_p PARAMS ((rtx));
371 static int combinable_i3pat PARAMS ((rtx, rtx *, rtx, rtx, int, rtx *));
372 static int contains_muldiv PARAMS ((rtx));
373 static rtx try_combine PARAMS ((rtx, rtx, rtx, int *));
374 static void undo_all PARAMS ((void));
375 static void undo_commit PARAMS ((void));
376 static rtx *find_split_point PARAMS ((rtx *, rtx));
377 static rtx subst PARAMS ((rtx, rtx, rtx, int, int));
378 static rtx combine_simplify_rtx PARAMS ((rtx, enum machine_mode, int, int));
379 static rtx simplify_if_then_else PARAMS ((rtx));
380 static rtx simplify_set PARAMS ((rtx));
381 static rtx simplify_logical PARAMS ((rtx, int));
382 static rtx expand_compound_operation PARAMS ((rtx));
383 static rtx expand_field_assignment PARAMS ((rtx));
384 static rtx make_extraction PARAMS ((enum machine_mode, rtx, HOST_WIDE_INT,
385 rtx, unsigned HOST_WIDE_INT, int,
387 static rtx extract_left_shift PARAMS ((rtx, int));
388 static rtx make_compound_operation PARAMS ((rtx, enum rtx_code));
389 static int get_pos_from_mask PARAMS ((unsigned HOST_WIDE_INT,
390 unsigned HOST_WIDE_INT *));
391 static rtx force_to_mode PARAMS ((rtx, enum machine_mode,
392 unsigned HOST_WIDE_INT, rtx, int));
393 static rtx if_then_else_cond PARAMS ((rtx, rtx *, rtx *));
394 static rtx known_cond PARAMS ((rtx, enum rtx_code, rtx, rtx));
395 static int rtx_equal_for_field_assignment_p PARAMS ((rtx, rtx));
396 static rtx make_field_assignment PARAMS ((rtx));
397 static rtx apply_distributive_law PARAMS ((rtx));
398 static rtx simplify_and_const_int PARAMS ((rtx, enum machine_mode, rtx,
399 unsigned HOST_WIDE_INT));
400 static unsigned HOST_WIDE_INT nonzero_bits PARAMS ((rtx, enum machine_mode));
401 static unsigned int num_sign_bit_copies PARAMS ((rtx, enum machine_mode));
402 static int merge_outer_ops PARAMS ((enum rtx_code *, HOST_WIDE_INT *,
403 enum rtx_code, HOST_WIDE_INT,
404 enum machine_mode, int *));
405 static rtx simplify_shift_const PARAMS ((rtx, enum rtx_code, enum machine_mode,
407 static int recog_for_combine PARAMS ((rtx *, rtx, rtx *));
408 static rtx gen_lowpart_for_combine PARAMS ((enum machine_mode, rtx));
409 static rtx gen_rtx_combine PARAMS ((enum rtx_code code, enum machine_mode mode,
411 static rtx gen_binary PARAMS ((enum rtx_code, enum machine_mode,
413 static rtx gen_unary PARAMS ((enum rtx_code, enum machine_mode,
414 enum machine_mode, rtx));
415 static enum rtx_code simplify_comparison PARAMS ((enum rtx_code, rtx *, rtx *));
416 static void update_table_tick PARAMS ((rtx));
417 static void record_value_for_reg PARAMS ((rtx, rtx, rtx));
418 static void check_promoted_subreg PARAMS ((rtx, rtx));
419 static void record_dead_and_set_regs_1 PARAMS ((rtx, rtx, void *));
420 static void record_dead_and_set_regs PARAMS ((rtx));
421 static int get_last_value_validate PARAMS ((rtx *, rtx, int, int));
422 static rtx get_last_value PARAMS ((rtx));
423 static int use_crosses_set_p PARAMS ((rtx, int));
424 static void reg_dead_at_p_1 PARAMS ((rtx, rtx, void *));
425 static int reg_dead_at_p PARAMS ((rtx, rtx));
426 static void move_deaths PARAMS ((rtx, rtx, int, rtx, rtx *));
427 static int reg_bitfield_target_p PARAMS ((rtx, rtx));
428 static void distribute_notes PARAMS ((rtx, rtx, rtx, rtx, rtx, rtx));
429 static void distribute_links PARAMS ((rtx));
430 static void mark_used_regs_combine PARAMS ((rtx));
431 static int insn_cuid PARAMS ((rtx));
432 static void record_promoted_value PARAMS ((rtx, rtx));
433 static rtx reversed_comparison PARAMS ((rtx, enum machine_mode, rtx, rtx));
434 static enum rtx_code combine_reversed_comparison_code PARAMS ((rtx));
436 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
437 insn. The substitution can be undone by undo_all. If INTO is already
438 set to NEWVAL, do not record this change. Because computing NEWVAL might
439 also call SUBST, we have to compute it before we put anything into
443 do_SUBST (into, newval)
449 if (oldval == newval)
453 buf = undobuf.frees, undobuf.frees = buf->next;
455 buf = (struct undo *) xmalloc (sizeof (struct undo));
459 buf->old_contents.r = oldval;
462 buf->next = undobuf.undos, undobuf.undos = buf;
465 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
467 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
468 for the value of a HOST_WIDE_INT value (including CONST_INT) is
472 do_SUBST_INT (into, newval)
473 unsigned int *into, newval;
476 unsigned int oldval = *into;
478 if (oldval == newval)
482 buf = undobuf.frees, undobuf.frees = buf->next;
484 buf = (struct undo *) xmalloc (sizeof (struct undo));
488 buf->old_contents.i = oldval;
491 buf->next = undobuf.undos, undobuf.undos = buf;
494 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
496 /* Main entry point for combiner. F is the first insn of the function.
497 NREGS is the first unused pseudo-reg number.
499 Return non-zero if the combiner has turned an indirect jump
500 instruction into a direct jump. */
502 combine_instructions (f, nregs)
506 register rtx insn, next;
511 register rtx links, nextlinks;
513 int new_direct_jump_p = 0;
515 combine_attempts = 0;
518 combine_successes = 0;
520 combine_max_regno = nregs;
522 reg_nonzero_bits = ((unsigned HOST_WIDE_INT *)
523 xcalloc (nregs, sizeof (unsigned HOST_WIDE_INT)));
525 = (unsigned char *) xcalloc (nregs, sizeof (unsigned char));
527 reg_last_death = (rtx *) xmalloc (nregs * sizeof (rtx));
528 reg_last_set = (rtx *) xmalloc (nregs * sizeof (rtx));
529 reg_last_set_value = (rtx *) xmalloc (nregs * sizeof (rtx));
530 reg_last_set_table_tick = (int *) xmalloc (nregs * sizeof (int));
531 reg_last_set_label = (int *) xmalloc (nregs * sizeof (int));
532 reg_last_set_invalid = (char *) xmalloc (nregs * sizeof (char));
534 = (enum machine_mode *) xmalloc (nregs * sizeof (enum machine_mode));
535 reg_last_set_nonzero_bits
536 = (unsigned HOST_WIDE_INT *) xmalloc (nregs * sizeof (HOST_WIDE_INT));
537 reg_last_set_sign_bit_copies
538 = (char *) xmalloc (nregs * sizeof (char));
540 init_reg_last_arrays ();
542 init_recog_no_volatile ();
544 /* Compute maximum uid value so uid_cuid can be allocated. */
546 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
547 if (INSN_UID (insn) > i)
550 uid_cuid = (int *) xmalloc ((i + 1) * sizeof (int));
553 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
555 /* Don't use reg_nonzero_bits when computing it. This can cause problems
556 when, for example, we have j <<= 1 in a loop. */
558 nonzero_sign_valid = 0;
560 /* Compute the mapping from uids to cuids.
561 Cuids are numbers assigned to insns, like uids,
562 except that cuids increase monotonically through the code.
564 Scan all SETs and see if we can deduce anything about what
565 bits are known to be zero for some registers and how many copies
566 of the sign bit are known to exist for those registers.
568 Also set any known values so that we can use it while searching
569 for what bits are known to be set. */
573 /* We need to initialize it here, because record_dead_and_set_regs may call
575 subst_prev_insn = NULL_RTX;
577 setup_incoming_promotions ();
579 refresh_blocks = sbitmap_alloc (n_basic_blocks);
580 sbitmap_zero (refresh_blocks);
583 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
585 uid_cuid[INSN_UID (insn)] = ++i;
591 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
593 record_dead_and_set_regs (insn);
596 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
597 if (REG_NOTE_KIND (links) == REG_INC)
598 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
603 if (GET_CODE (insn) == CODE_LABEL)
607 nonzero_sign_valid = 1;
609 /* Now scan all the insns in forward order. */
611 this_basic_block = -1;
615 init_reg_last_arrays ();
616 setup_incoming_promotions ();
618 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
622 /* If INSN starts a new basic block, update our basic block number. */
623 if (this_basic_block + 1 < n_basic_blocks
624 && BLOCK_HEAD (this_basic_block + 1) == insn)
627 if (GET_CODE (insn) == CODE_LABEL)
630 else if (INSN_P (insn))
632 /* See if we know about function return values before this
633 insn based upon SUBREG flags. */
634 check_promoted_subreg (insn, PATTERN (insn));
636 /* Try this insn with each insn it links back to. */
638 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
639 if ((next = try_combine (insn, XEXP (links, 0),
640 NULL_RTX, &new_direct_jump_p)) != 0)
643 /* Try each sequence of three linked insns ending with this one. */
645 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
647 rtx link = XEXP (links, 0);
649 /* If the linked insn has been replaced by a note, then there
650 is no point in persuing this chain any further. */
651 if (GET_CODE (link) == NOTE)
654 for (nextlinks = LOG_LINKS (link);
656 nextlinks = XEXP (nextlinks, 1))
657 if ((next = try_combine (insn, XEXP (links, 0),
659 &new_direct_jump_p)) != 0)
664 /* Try to combine a jump insn that uses CC0
665 with a preceding insn that sets CC0, and maybe with its
666 logical predecessor as well.
667 This is how we make decrement-and-branch insns.
668 We need this special code because data flow connections
669 via CC0 do not get entered in LOG_LINKS. */
671 if (GET_CODE (insn) == JUMP_INSN
672 && (prev = prev_nonnote_insn (insn)) != 0
673 && GET_CODE (prev) == INSN
674 && sets_cc0_p (PATTERN (prev)))
676 if ((next = try_combine (insn, prev,
677 NULL_RTX, &new_direct_jump_p)) != 0)
680 for (nextlinks = LOG_LINKS (prev); nextlinks;
681 nextlinks = XEXP (nextlinks, 1))
682 if ((next = try_combine (insn, prev,
684 &new_direct_jump_p)) != 0)
688 /* Do the same for an insn that explicitly references CC0. */
689 if (GET_CODE (insn) == INSN
690 && (prev = prev_nonnote_insn (insn)) != 0
691 && GET_CODE (prev) == INSN
692 && sets_cc0_p (PATTERN (prev))
693 && GET_CODE (PATTERN (insn)) == SET
694 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
696 if ((next = try_combine (insn, prev,
697 NULL_RTX, &new_direct_jump_p)) != 0)
700 for (nextlinks = LOG_LINKS (prev); nextlinks;
701 nextlinks = XEXP (nextlinks, 1))
702 if ((next = try_combine (insn, prev,
704 &new_direct_jump_p)) != 0)
708 /* Finally, see if any of the insns that this insn links to
709 explicitly references CC0. If so, try this insn, that insn,
710 and its predecessor if it sets CC0. */
711 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
712 if (GET_CODE (XEXP (links, 0)) == INSN
713 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
714 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
715 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
716 && GET_CODE (prev) == INSN
717 && sets_cc0_p (PATTERN (prev))
718 && (next = try_combine (insn, XEXP (links, 0),
719 prev, &new_direct_jump_p)) != 0)
723 /* Try combining an insn with two different insns whose results it
725 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
726 for (nextlinks = XEXP (links, 1); nextlinks;
727 nextlinks = XEXP (nextlinks, 1))
728 if ((next = try_combine (insn, XEXP (links, 0),
730 &new_direct_jump_p)) != 0)
733 if (GET_CODE (insn) != NOTE)
734 record_dead_and_set_regs (insn);
743 compute_bb_for_insn (get_max_uid ());
744 update_life_info (refresh_blocks, UPDATE_LIFE_GLOBAL_RM_NOTES,
749 sbitmap_free (refresh_blocks);
750 free (reg_nonzero_bits);
751 free (reg_sign_bit_copies);
752 free (reg_last_death);
754 free (reg_last_set_value);
755 free (reg_last_set_table_tick);
756 free (reg_last_set_label);
757 free (reg_last_set_invalid);
758 free (reg_last_set_mode);
759 free (reg_last_set_nonzero_bits);
760 free (reg_last_set_sign_bit_copies);
764 struct undo *undo, *next;
765 for (undo = undobuf.frees; undo; undo = next)
773 total_attempts += combine_attempts;
774 total_merges += combine_merges;
775 total_extras += combine_extras;
776 total_successes += combine_successes;
778 nonzero_sign_valid = 0;
780 /* Make recognizer allow volatile MEMs again. */
783 return new_direct_jump_p;
786 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
789 init_reg_last_arrays ()
791 unsigned int nregs = combine_max_regno;
793 memset ((char *) reg_last_death, 0, nregs * sizeof (rtx));
794 memset ((char *) reg_last_set, 0, nregs * sizeof (rtx));
795 memset ((char *) reg_last_set_value, 0, nregs * sizeof (rtx));
796 memset ((char *) reg_last_set_table_tick, 0, nregs * sizeof (int));
797 memset ((char *) reg_last_set_label, 0, nregs * sizeof (int));
798 memset (reg_last_set_invalid, 0, nregs * sizeof (char));
799 memset ((char *) reg_last_set_mode, 0, nregs * sizeof (enum machine_mode));
800 memset ((char *) reg_last_set_nonzero_bits, 0, nregs * sizeof (HOST_WIDE_INT));
801 memset (reg_last_set_sign_bit_copies, 0, nregs * sizeof (char));
804 /* Set up any promoted values for incoming argument registers. */
807 setup_incoming_promotions ()
809 #ifdef PROMOTE_FUNCTION_ARGS
812 enum machine_mode mode;
814 rtx first = get_insns ();
816 #ifndef OUTGOING_REGNO
817 #define OUTGOING_REGNO(N) N
819 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
820 /* Check whether this register can hold an incoming pointer
821 argument. FUNCTION_ARG_REGNO_P tests outgoing register
822 numbers, so translate if necessary due to register windows. */
823 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
824 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
827 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
830 gen_rtx_CLOBBER (mode, const0_rtx)));
835 /* Called via note_stores. If X is a pseudo that is narrower than
836 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
838 If we are setting only a portion of X and we can't figure out what
839 portion, assume all bits will be used since we don't know what will
842 Similarly, set how many bits of X are known to be copies of the sign bit
843 at all locations in the function. This is the smallest number implied
847 set_nonzero_bits_and_sign_copies (x, set, data)
850 void *data ATTRIBUTE_UNUSED;
854 if (GET_CODE (x) == REG
855 && REGNO (x) >= FIRST_PSEUDO_REGISTER
856 /* If this register is undefined at the start of the file, we can't
857 say what its contents were. */
858 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
859 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
861 if (set == 0 || GET_CODE (set) == CLOBBER)
863 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
864 reg_sign_bit_copies[REGNO (x)] = 1;
868 /* If this is a complex assignment, see if we can convert it into a
869 simple assignment. */
870 set = expand_field_assignment (set);
872 /* If this is a simple assignment, or we have a paradoxical SUBREG,
873 set what we know about X. */
875 if (SET_DEST (set) == x
876 || (GET_CODE (SET_DEST (set)) == SUBREG
877 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
878 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
879 && SUBREG_REG (SET_DEST (set)) == x))
881 rtx src = SET_SRC (set);
883 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
884 /* If X is narrower than a word and SRC is a non-negative
885 constant that would appear negative in the mode of X,
886 sign-extend it for use in reg_nonzero_bits because some
887 machines (maybe most) will actually do the sign-extension
888 and this is the conservative approach.
890 ??? For 2.5, try to tighten up the MD files in this regard
891 instead of this kludge. */
893 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
894 && GET_CODE (src) == CONST_INT
896 && 0 != (INTVAL (src)
898 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
899 src = GEN_INT (INTVAL (src)
900 | ((HOST_WIDE_INT) (-1)
901 << GET_MODE_BITSIZE (GET_MODE (x))));
904 reg_nonzero_bits[REGNO (x)]
905 |= nonzero_bits (src, nonzero_bits_mode);
906 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
907 if (reg_sign_bit_copies[REGNO (x)] == 0
908 || reg_sign_bit_copies[REGNO (x)] > num)
909 reg_sign_bit_copies[REGNO (x)] = num;
913 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
914 reg_sign_bit_copies[REGNO (x)] = 1;
919 /* See if INSN can be combined into I3. PRED and SUCC are optionally
920 insns that were previously combined into I3 or that will be combined
921 into the merger of INSN and I3.
923 Return 0 if the combination is not allowed for any reason.
925 If the combination is allowed, *PDEST will be set to the single
926 destination of INSN and *PSRC to the single source, and this function
930 can_combine_p (insn, i3, pred, succ, pdest, psrc)
933 rtx pred ATTRIBUTE_UNUSED;
938 rtx set = 0, src, dest;
943 int all_adjacent = (succ ? (next_active_insn (insn) == succ
944 && next_active_insn (succ) == i3)
945 : next_active_insn (insn) == i3);
947 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
948 or a PARALLEL consisting of such a SET and CLOBBERs.
950 If INSN has CLOBBER parallel parts, ignore them for our processing.
951 By definition, these happen during the execution of the insn. When it
952 is merged with another insn, all bets are off. If they are, in fact,
953 needed and aren't also supplied in I3, they may be added by
954 recog_for_combine. Otherwise, it won't match.
956 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
959 Get the source and destination of INSN. If more than one, can't
962 if (GET_CODE (PATTERN (insn)) == SET)
963 set = PATTERN (insn);
964 else if (GET_CODE (PATTERN (insn)) == PARALLEL
965 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
967 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
969 rtx elt = XVECEXP (PATTERN (insn), 0, i);
971 switch (GET_CODE (elt))
973 /* This is important to combine floating point insns
976 /* Combining an isolated USE doesn't make sense.
977 We depend here on combinable_i3_pat to reject them. */
978 /* The code below this loop only verifies that the inputs of
979 the SET in INSN do not change. We call reg_set_between_p
980 to verify that the REG in the USE does not change betweeen
982 If the USE in INSN was for a pseudo register, the matching
983 insn pattern will likely match any register; combining this
984 with any other USE would only be safe if we knew that the
985 used registers have identical values, or if there was
986 something to tell them apart, e.g. different modes. For
987 now, we forgo such compilcated tests and simply disallow
988 combining of USES of pseudo registers with any other USE. */
989 if (GET_CODE (XEXP (elt, 0)) == REG
990 && GET_CODE (PATTERN (i3)) == PARALLEL)
992 rtx i3pat = PATTERN (i3);
993 int i = XVECLEN (i3pat, 0) - 1;
994 unsigned int regno = REGNO (XEXP (elt, 0));
998 rtx i3elt = XVECEXP (i3pat, 0, i);
1000 if (GET_CODE (i3elt) == USE
1001 && GET_CODE (XEXP (i3elt, 0)) == REG
1002 && (REGNO (XEXP (i3elt, 0)) == regno
1003 ? reg_set_between_p (XEXP (elt, 0),
1004 PREV_INSN (insn), i3)
1005 : regno >= FIRST_PSEUDO_REGISTER))
1012 /* We can ignore CLOBBERs. */
1017 /* Ignore SETs whose result isn't used but not those that
1018 have side-effects. */
1019 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1020 && ! side_effects_p (elt))
1023 /* If we have already found a SET, this is a second one and
1024 so we cannot combine with this insn. */
1032 /* Anything else means we can't combine. */
1038 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1039 so don't do anything with it. */
1040 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1049 set = expand_field_assignment (set);
1050 src = SET_SRC (set), dest = SET_DEST (set);
1052 /* Don't eliminate a store in the stack pointer. */
1053 if (dest == stack_pointer_rtx
1054 /* If we couldn't eliminate a field assignment, we can't combine. */
1055 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
1056 /* Don't combine with an insn that sets a register to itself if it has
1057 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1058 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1059 /* Can't merge an ASM_OPERANDS. */
1060 || GET_CODE (src) == ASM_OPERANDS
1061 /* Can't merge a function call. */
1062 || GET_CODE (src) == CALL
1063 /* Don't eliminate a function call argument. */
1064 || (GET_CODE (i3) == CALL_INSN
1065 && (find_reg_fusage (i3, USE, dest)
1066 || (GET_CODE (dest) == REG
1067 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1068 && global_regs[REGNO (dest)])))
1069 /* Don't substitute into an incremented register. */
1070 || FIND_REG_INC_NOTE (i3, dest)
1071 || (succ && FIND_REG_INC_NOTE (succ, dest))
1073 /* Don't combine the end of a libcall into anything. */
1074 /* ??? This gives worse code, and appears to be unnecessary, since no
1075 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1076 use REG_RETVAL notes for noconflict blocks, but other code here
1077 makes sure that those insns don't disappear. */
1078 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1080 /* Make sure that DEST is not used after SUCC but before I3. */
1081 || (succ && ! all_adjacent
1082 && reg_used_between_p (dest, succ, i3))
1083 /* Make sure that the value that is to be substituted for the register
1084 does not use any registers whose values alter in between. However,
1085 If the insns are adjacent, a use can't cross a set even though we
1086 think it might (this can happen for a sequence of insns each setting
1087 the same destination; reg_last_set of that register might point to
1088 a NOTE). If INSN has a REG_EQUIV note, the register is always
1089 equivalent to the memory so the substitution is valid even if there
1090 are intervening stores. Also, don't move a volatile asm or
1091 UNSPEC_VOLATILE across any other insns. */
1093 && (((GET_CODE (src) != MEM
1094 || ! find_reg_note (insn, REG_EQUIV, src))
1095 && use_crosses_set_p (src, INSN_CUID (insn)))
1096 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1097 || GET_CODE (src) == UNSPEC_VOLATILE))
1098 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1099 better register allocation by not doing the combine. */
1100 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1101 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1102 /* Don't combine across a CALL_INSN, because that would possibly
1103 change whether the life span of some REGs crosses calls or not,
1104 and it is a pain to update that information.
1105 Exception: if source is a constant, moving it later can't hurt.
1106 Accept that special case, because it helps -fforce-addr a lot. */
1107 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1110 /* DEST must either be a REG or CC0. */
1111 if (GET_CODE (dest) == REG)
1113 /* If register alignment is being enforced for multi-word items in all
1114 cases except for parameters, it is possible to have a register copy
1115 insn referencing a hard register that is not allowed to contain the
1116 mode being copied and which would not be valid as an operand of most
1117 insns. Eliminate this problem by not combining with such an insn.
1119 Also, on some machines we don't want to extend the life of a hard
1122 if (GET_CODE (src) == REG
1123 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1124 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1125 /* Don't extend the life of a hard register unless it is
1126 user variable (if we have few registers) or it can't
1127 fit into the desired register (meaning something special
1129 Also avoid substituting a return register into I3, because
1130 reload can't handle a conflict with constraints of other
1132 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1133 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1136 else if (GET_CODE (dest) != CC0)
1139 /* Don't substitute for a register intended as a clobberable operand.
1140 Similarly, don't substitute an expression containing a register that
1141 will be clobbered in I3. */
1142 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1143 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1144 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1145 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1147 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1150 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1151 or not), reject, unless nothing volatile comes between it and I3 */
1153 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1155 /* Make sure succ doesn't contain a volatile reference. */
1156 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1159 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1160 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1164 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1165 to be an explicit register variable, and was chosen for a reason. */
1167 if (GET_CODE (src) == ASM_OPERANDS
1168 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1171 /* If there are any volatile insns between INSN and I3, reject, because
1172 they might affect machine state. */
1174 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1175 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1178 /* If INSN or I2 contains an autoincrement or autodecrement,
1179 make sure that register is not used between there and I3,
1180 and not already used in I3 either.
1181 Also insist that I3 not be a jump; if it were one
1182 and the incremented register were spilled, we would lose. */
1185 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1186 if (REG_NOTE_KIND (link) == REG_INC
1187 && (GET_CODE (i3) == JUMP_INSN
1188 || reg_used_between_p (XEXP (link, 0), insn, i3)
1189 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1194 /* Don't combine an insn that follows a CC0-setting insn.
1195 An insn that uses CC0 must not be separated from the one that sets it.
1196 We do, however, allow I2 to follow a CC0-setting insn if that insn
1197 is passed as I1; in that case it will be deleted also.
1198 We also allow combining in this case if all the insns are adjacent
1199 because that would leave the two CC0 insns adjacent as well.
1200 It would be more logical to test whether CC0 occurs inside I1 or I2,
1201 but that would be much slower, and this ought to be equivalent. */
1203 p = prev_nonnote_insn (insn);
1204 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1209 /* If we get here, we have passed all the tests and the combination is
1218 /* Check if PAT is an insn - or a part of it - used to set up an
1219 argument for a function in a hard register. */
1222 sets_function_arg_p (pat)
1228 switch (GET_CODE (pat))
1231 return sets_function_arg_p (PATTERN (pat));
1234 for (i = XVECLEN (pat, 0); --i >= 0;)
1235 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1241 inner_dest = SET_DEST (pat);
1242 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1243 || GET_CODE (inner_dest) == SUBREG
1244 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1245 inner_dest = XEXP (inner_dest, 0);
1247 return (GET_CODE (inner_dest) == REG
1248 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1249 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1258 /* LOC is the location within I3 that contains its pattern or the component
1259 of a PARALLEL of the pattern. We validate that it is valid for combining.
1261 One problem is if I3 modifies its output, as opposed to replacing it
1262 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1263 so would produce an insn that is not equivalent to the original insns.
1267 (set (reg:DI 101) (reg:DI 100))
1268 (set (subreg:SI (reg:DI 101) 0) <foo>)
1270 This is NOT equivalent to:
1272 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1273 (set (reg:DI 101) (reg:DI 100))])
1275 Not only does this modify 100 (in which case it might still be valid
1276 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1278 We can also run into a problem if I2 sets a register that I1
1279 uses and I1 gets directly substituted into I3 (not via I2). In that
1280 case, we would be getting the wrong value of I2DEST into I3, so we
1281 must reject the combination. This case occurs when I2 and I1 both
1282 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1283 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1284 of a SET must prevent combination from occurring.
1286 Before doing the above check, we first try to expand a field assignment
1287 into a set of logical operations.
1289 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1290 we place a register that is both set and used within I3. If more than one
1291 such register is detected, we fail.
1293 Return 1 if the combination is valid, zero otherwise. */
1296 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1302 rtx *pi3dest_killed;
1306 if (GET_CODE (x) == SET)
1308 rtx set = expand_field_assignment (x);
1309 rtx dest = SET_DEST (set);
1310 rtx src = SET_SRC (set);
1311 rtx inner_dest = dest;
1314 rtx inner_src = src;
1319 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1320 || GET_CODE (inner_dest) == SUBREG
1321 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1322 inner_dest = XEXP (inner_dest, 0);
1324 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1327 while (GET_CODE (inner_src) == STRICT_LOW_PART
1328 || GET_CODE (inner_src) == SUBREG
1329 || GET_CODE (inner_src) == ZERO_EXTRACT)
1330 inner_src = XEXP (inner_src, 0);
1332 /* If it is better that two different modes keep two different pseudos,
1333 avoid combining them. This avoids producing the following pattern
1335 (set (subreg:SI (reg/v:QI 21) 0)
1336 (lshiftrt:SI (reg/v:SI 20)
1338 If that were made, reload could not handle the pair of
1339 reg 20/21, since it would try to get any GENERAL_REGS
1340 but some of them don't handle QImode. */
1342 if (rtx_equal_p (inner_src, i2dest)
1343 && GET_CODE (inner_dest) == REG
1344 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1348 /* Check for the case where I3 modifies its output, as
1350 if ((inner_dest != dest
1351 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1352 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1354 /* This is the same test done in can_combine_p except we can't test
1355 all_adjacent; we don't have to, since this instruction will stay
1356 in place, thus we are not considering increasing the lifetime of
1359 Also, if this insn sets a function argument, combining it with
1360 something that might need a spill could clobber a previous
1361 function argument; the all_adjacent test in can_combine_p also
1362 checks this; here, we do a more specific test for this case. */
1364 || (GET_CODE (inner_dest) == REG
1365 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1366 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1367 GET_MODE (inner_dest))))
1368 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1371 /* If DEST is used in I3, it is being killed in this insn,
1372 so record that for later.
1373 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1374 STACK_POINTER_REGNUM, since these are always considered to be
1375 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1376 if (pi3dest_killed && GET_CODE (dest) == REG
1377 && reg_referenced_p (dest, PATTERN (i3))
1378 && REGNO (dest) != FRAME_POINTER_REGNUM
1379 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1380 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1382 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1383 && (REGNO (dest) != ARG_POINTER_REGNUM
1384 || ! fixed_regs [REGNO (dest)])
1386 && REGNO (dest) != STACK_POINTER_REGNUM)
1388 if (*pi3dest_killed)
1391 *pi3dest_killed = dest;
1395 else if (GET_CODE (x) == PARALLEL)
1399 for (i = 0; i < XVECLEN (x, 0); i++)
1400 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1401 i1_not_in_src, pi3dest_killed))
1408 /* Return 1 if X is an arithmetic expression that contains a multiplication
1409 and division. We don't count multiplications by powers of two here. */
1415 switch (GET_CODE (x))
1417 case MOD: case DIV: case UMOD: case UDIV:
1421 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1422 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1424 switch (GET_RTX_CLASS (GET_CODE (x)))
1426 case 'c': case '<': case '2':
1427 return contains_muldiv (XEXP (x, 0))
1428 || contains_muldiv (XEXP (x, 1));
1431 return contains_muldiv (XEXP (x, 0));
1439 /* Determine whether INSN can be used in a combination. Return nonzero if
1440 not. This is used in try_combine to detect early some cases where we
1441 can't perform combinations. */
1444 cant_combine_insn_p (insn)
1450 /* If this isn't really an insn, we can't do anything.
1451 This can occur when flow deletes an insn that it has merged into an
1452 auto-increment address. */
1453 if (! INSN_P (insn))
1456 /* Never combine loads and stores involving hard regs. The register
1457 allocator can usually handle such reg-reg moves by tying. If we allow
1458 the combiner to make substitutions of hard regs, we risk aborting in
1459 reload on machines that have SMALL_REGISTER_CLASSES.
1460 As an exception, we allow combinations involving fixed regs; these are
1461 not available to the register allocator so there's no risk involved. */
1463 set = single_set (insn);
1466 src = SET_SRC (set);
1467 dest = SET_DEST (set);
1468 if (GET_CODE (src) == SUBREG)
1469 src = SUBREG_REG (src);
1470 if (GET_CODE (dest) == SUBREG)
1471 dest = SUBREG_REG (dest);
1472 if (REG_P (src) && REG_P (dest)
1473 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1474 && ! fixed_regs[REGNO (src)])
1475 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1476 && ! fixed_regs[REGNO (dest)])))
1482 /* Try to combine the insns I1 and I2 into I3.
1483 Here I1 and I2 appear earlier than I3.
1484 I1 can be zero; then we combine just I2 into I3.
1486 It we are combining three insns and the resulting insn is not recognized,
1487 try splitting it into two insns. If that happens, I2 and I3 are retained
1488 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1491 Return 0 if the combination does not work. Then nothing is changed.
1492 If we did the combination, return the insn at which combine should
1495 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1496 new direct jump instruction. */
1499 try_combine (i3, i2, i1, new_direct_jump_p)
1500 register rtx i3, i2, i1;
1501 register int *new_direct_jump_p;
1503 /* New patterns for I3 and I2, respectively. */
1504 rtx newpat, newi2pat = 0;
1505 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1506 int added_sets_1, added_sets_2;
1507 /* Total number of SETs to put into I3. */
1509 /* Nonzero is I2's body now appears in I3. */
1511 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1512 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1513 /* Contains I3 if the destination of I3 is used in its source, which means
1514 that the old life of I3 is being killed. If that usage is placed into
1515 I2 and not in I3, a REG_DEAD note must be made. */
1516 rtx i3dest_killed = 0;
1517 /* SET_DEST and SET_SRC of I2 and I1. */
1518 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1519 /* PATTERN (I2), or a copy of it in certain cases. */
1521 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1522 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1523 int i1_feeds_i3 = 0;
1524 /* Notes that must be added to REG_NOTES in I3 and I2. */
1525 rtx new_i3_notes, new_i2_notes;
1526 /* Notes that we substituted I3 into I2 instead of the normal case. */
1527 int i3_subst_into_i2 = 0;
1528 /* Notes that I1, I2 or I3 is a MULT operation. */
1536 /* Exit early if one of the insns involved can't be used for
1538 if (cant_combine_insn_p (i3)
1539 || cant_combine_insn_p (i2)
1540 || (i1 && cant_combine_insn_p (i1))
1541 /* We also can't do anything if I3 has a
1542 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1545 /* ??? This gives worse code, and appears to be unnecessary, since no
1546 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1547 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1553 undobuf.other_insn = 0;
1555 /* Reset the hard register usage information. */
1556 CLEAR_HARD_REG_SET (newpat_used_regs);
1558 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1559 code below, set I1 to be the earlier of the two insns. */
1560 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1561 temp = i1, i1 = i2, i2 = temp;
1563 added_links_insn = 0;
1565 /* First check for one important special-case that the code below will
1566 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1567 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1568 we may be able to replace that destination with the destination of I3.
1569 This occurs in the common code where we compute both a quotient and
1570 remainder into a structure, in which case we want to do the computation
1571 directly into the structure to avoid register-register copies.
1573 Note that this case handles both multiple sets in I2 and also
1574 cases where I2 has a number of CLOBBER or PARALLELs.
1576 We make very conservative checks below and only try to handle the
1577 most common cases of this. For example, we only handle the case
1578 where I2 and I3 are adjacent to avoid making difficult register
1581 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1582 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1583 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1584 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1585 && GET_CODE (PATTERN (i2)) == PARALLEL
1586 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1587 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1588 below would need to check what is inside (and reg_overlap_mentioned_p
1589 doesn't support those codes anyway). Don't allow those destinations;
1590 the resulting insn isn't likely to be recognized anyway. */
1591 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1592 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1593 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1594 SET_DEST (PATTERN (i3)))
1595 && next_real_insn (i2) == i3)
1597 rtx p2 = PATTERN (i2);
1599 /* Make sure that the destination of I3,
1600 which we are going to substitute into one output of I2,
1601 is not used within another output of I2. We must avoid making this:
1602 (parallel [(set (mem (reg 69)) ...)
1603 (set (reg 69) ...)])
1604 which is not well-defined as to order of actions.
1605 (Besides, reload can't handle output reloads for this.)
1607 The problem can also happen if the dest of I3 is a memory ref,
1608 if another dest in I2 is an indirect memory ref. */
1609 for (i = 0; i < XVECLEN (p2, 0); i++)
1610 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1611 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1612 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1613 SET_DEST (XVECEXP (p2, 0, i))))
1616 if (i == XVECLEN (p2, 0))
1617 for (i = 0; i < XVECLEN (p2, 0); i++)
1618 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1619 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1620 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1625 subst_low_cuid = INSN_CUID (i2);
1627 added_sets_2 = added_sets_1 = 0;
1628 i2dest = SET_SRC (PATTERN (i3));
1630 /* Replace the dest in I2 with our dest and make the resulting
1631 insn the new pattern for I3. Then skip to where we
1632 validate the pattern. Everything was set up above. */
1633 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1634 SET_DEST (PATTERN (i3)));
1637 i3_subst_into_i2 = 1;
1638 goto validate_replacement;
1642 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1643 one of those words to another constant, merge them by making a new
1646 && (temp = single_set (i2)) != 0
1647 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1648 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1649 && GET_CODE (SET_DEST (temp)) == REG
1650 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1651 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1652 && GET_CODE (PATTERN (i3)) == SET
1653 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1654 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1655 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1656 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1657 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1659 HOST_WIDE_INT lo, hi;
1661 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1662 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1665 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1666 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1669 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1671 /* We don't handle the case of the target word being wider
1672 than a host wide int. */
1673 if (HOST_BITS_PER_WIDE_INT < BITS_PER_WORD)
1676 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1677 lo |= INTVAL (SET_SRC (PATTERN (i3)));
1679 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1680 hi = INTVAL (SET_SRC (PATTERN (i3)));
1681 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1683 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1684 >> (HOST_BITS_PER_WIDE_INT - 1));
1686 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1687 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1688 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1689 (INTVAL (SET_SRC (PATTERN (i3)))));
1691 hi = lo < 0 ? -1 : 0;
1694 /* We don't handle the case of the higher word not fitting
1695 entirely in either hi or lo. */
1700 subst_low_cuid = INSN_CUID (i2);
1701 added_sets_2 = added_sets_1 = 0;
1702 i2dest = SET_DEST (temp);
1704 SUBST (SET_SRC (temp),
1705 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1707 newpat = PATTERN (i2);
1708 goto validate_replacement;
1712 /* If we have no I1 and I2 looks like:
1713 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1715 make up a dummy I1 that is
1718 (set (reg:CC X) (compare:CC Y (const_int 0)))
1720 (We can ignore any trailing CLOBBERs.)
1722 This undoes a previous combination and allows us to match a branch-and-
1725 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1726 && XVECLEN (PATTERN (i2), 0) >= 2
1727 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1728 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1730 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1731 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1732 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1733 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1734 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1735 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1737 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1738 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1743 /* We make I1 with the same INSN_UID as I2. This gives it
1744 the same INSN_CUID for value tracking. Our fake I1 will
1745 never appear in the insn stream so giving it the same INSN_UID
1746 as I2 will not cause a problem. */
1748 subst_prev_insn = i1
1749 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1750 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1753 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1754 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1755 SET_DEST (PATTERN (i1)));
1760 /* Verify that I2 and I1 are valid for combining. */
1761 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1762 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1768 /* Record whether I2DEST is used in I2SRC and similarly for the other
1769 cases. Knowing this will help in register status updating below. */
1770 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1771 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1772 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1774 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1776 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1778 /* Ensure that I3's pattern can be the destination of combines. */
1779 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1780 i1 && i2dest_in_i1src && i1_feeds_i3,
1787 /* See if any of the insns is a MULT operation. Unless one is, we will
1788 reject a combination that is, since it must be slower. Be conservative
1790 if (GET_CODE (i2src) == MULT
1791 || (i1 != 0 && GET_CODE (i1src) == MULT)
1792 || (GET_CODE (PATTERN (i3)) == SET
1793 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1796 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1797 We used to do this EXCEPT in one case: I3 has a post-inc in an
1798 output operand. However, that exception can give rise to insns like
1800 which is a famous insn on the PDP-11 where the value of r3 used as the
1801 source was model-dependent. Avoid this sort of thing. */
1804 if (!(GET_CODE (PATTERN (i3)) == SET
1805 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1806 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1807 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1808 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1809 /* It's not the exception. */
1812 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1813 if (REG_NOTE_KIND (link) == REG_INC
1814 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1816 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1823 /* See if the SETs in I1 or I2 need to be kept around in the merged
1824 instruction: whenever the value set there is still needed past I3.
1825 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1827 For the SET in I1, we have two cases: If I1 and I2 independently
1828 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1829 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1830 in I1 needs to be kept around unless I1DEST dies or is set in either
1831 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1832 I1DEST. If so, we know I1 feeds into I2. */
1834 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1837 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1838 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1840 /* If the set in I2 needs to be kept around, we must make a copy of
1841 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1842 PATTERN (I2), we are only substituting for the original I1DEST, not into
1843 an already-substituted copy. This also prevents making self-referential
1844 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1847 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1848 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1852 i2pat = copy_rtx (i2pat);
1856 /* Substitute in the latest insn for the regs set by the earlier ones. */
1858 maxreg = max_reg_num ();
1862 /* It is possible that the source of I2 or I1 may be performing an
1863 unneeded operation, such as a ZERO_EXTEND of something that is known
1864 to have the high part zero. Handle that case by letting subst look at
1865 the innermost one of them.
1867 Another way to do this would be to have a function that tries to
1868 simplify a single insn instead of merging two or more insns. We don't
1869 do this because of the potential of infinite loops and because
1870 of the potential extra memory required. However, doing it the way
1871 we are is a bit of a kludge and doesn't catch all cases.
1873 But only do this if -fexpensive-optimizations since it slows things down
1874 and doesn't usually win. */
1876 if (flag_expensive_optimizations)
1878 /* Pass pc_rtx so no substitutions are done, just simplifications.
1879 The cases that we are interested in here do not involve the few
1880 cases were is_replaced is checked. */
1883 subst_low_cuid = INSN_CUID (i1);
1884 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1888 subst_low_cuid = INSN_CUID (i2);
1889 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1892 undobuf.previous_undos = undobuf.undos;
1896 /* Many machines that don't use CC0 have insns that can both perform an
1897 arithmetic operation and set the condition code. These operations will
1898 be represented as a PARALLEL with the first element of the vector
1899 being a COMPARE of an arithmetic operation with the constant zero.
1900 The second element of the vector will set some pseudo to the result
1901 of the same arithmetic operation. If we simplify the COMPARE, we won't
1902 match such a pattern and so will generate an extra insn. Here we test
1903 for this case, where both the comparison and the operation result are
1904 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1905 I2SRC. Later we will make the PARALLEL that contains I2. */
1907 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1908 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1909 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1910 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1912 #ifdef EXTRA_CC_MODES
1914 enum machine_mode compare_mode;
1917 newpat = PATTERN (i3);
1918 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1922 #ifdef EXTRA_CC_MODES
1923 /* See if a COMPARE with the operand we substituted in should be done
1924 with the mode that is currently being used. If not, do the same
1925 processing we do in `subst' for a SET; namely, if the destination
1926 is used only once, try to replace it with a register of the proper
1927 mode and also replace the COMPARE. */
1928 if (undobuf.other_insn == 0
1929 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1930 &undobuf.other_insn))
1931 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1933 != GET_MODE (SET_DEST (newpat))))
1935 unsigned int regno = REGNO (SET_DEST (newpat));
1936 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1938 if (regno < FIRST_PSEUDO_REGISTER
1939 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1940 && ! REG_USERVAR_P (SET_DEST (newpat))))
1942 if (regno >= FIRST_PSEUDO_REGISTER)
1943 SUBST (regno_reg_rtx[regno], new_dest);
1945 SUBST (SET_DEST (newpat), new_dest);
1946 SUBST (XEXP (*cc_use, 0), new_dest);
1947 SUBST (SET_SRC (newpat),
1948 gen_rtx_combine (COMPARE, compare_mode,
1949 i2src, const0_rtx));
1952 undobuf.other_insn = 0;
1959 n_occurrences = 0; /* `subst' counts here */
1961 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1962 need to make a unique copy of I2SRC each time we substitute it
1963 to avoid self-referential rtl. */
1965 subst_low_cuid = INSN_CUID (i2);
1966 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1967 ! i1_feeds_i3 && i1dest_in_i1src);
1968 undobuf.previous_undos = undobuf.undos;
1970 /* Record whether i2's body now appears within i3's body. */
1971 i2_is_used = n_occurrences;
1974 /* If we already got a failure, don't try to do more. Otherwise,
1975 try to substitute in I1 if we have it. */
1977 if (i1 && GET_CODE (newpat) != CLOBBER)
1979 /* Before we can do this substitution, we must redo the test done
1980 above (see detailed comments there) that ensures that I1DEST
1981 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1983 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1991 subst_low_cuid = INSN_CUID (i1);
1992 newpat = subst (newpat, i1dest, i1src, 0, 0);
1993 undobuf.previous_undos = undobuf.undos;
1996 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1997 to count all the ways that I2SRC and I1SRC can be used. */
1998 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1999 && i2_is_used + added_sets_2 > 1)
2000 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2001 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2003 /* Fail if we tried to make a new register (we used to abort, but there's
2004 really no reason to). */
2005 || max_reg_num () != maxreg
2006 /* Fail if we couldn't do something and have a CLOBBER. */
2007 || GET_CODE (newpat) == CLOBBER
2008 /* Fail if this new pattern is a MULT and we didn't have one before
2009 at the outer level. */
2010 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2017 /* If the actions of the earlier insns must be kept
2018 in addition to substituting them into the latest one,
2019 we must make a new PARALLEL for the latest insn
2020 to hold additional the SETs. */
2022 if (added_sets_1 || added_sets_2)
2026 if (GET_CODE (newpat) == PARALLEL)
2028 rtvec old = XVEC (newpat, 0);
2029 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2030 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2031 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
2032 sizeof (old->elem[0]) * old->num_elem);
2037 total_sets = 1 + added_sets_1 + added_sets_2;
2038 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2039 XVECEXP (newpat, 0, 0) = old;
2043 XVECEXP (newpat, 0, --total_sets)
2044 = (GET_CODE (PATTERN (i1)) == PARALLEL
2045 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2049 /* If there is no I1, use I2's body as is. We used to also not do
2050 the subst call below if I2 was substituted into I3,
2051 but that could lose a simplification. */
2053 XVECEXP (newpat, 0, --total_sets) = i2pat;
2055 /* See comment where i2pat is assigned. */
2056 XVECEXP (newpat, 0, --total_sets)
2057 = subst (i2pat, i1dest, i1src, 0, 0);
2061 /* We come here when we are replacing a destination in I2 with the
2062 destination of I3. */
2063 validate_replacement:
2065 /* Note which hard regs this insn has as inputs. */
2066 mark_used_regs_combine (newpat);
2068 /* Is the result of combination a valid instruction? */
2069 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2071 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2072 the second SET's destination is a register that is unused. In that case,
2073 we just need the first SET. This can occur when simplifying a divmod
2074 insn. We *must* test for this case here because the code below that
2075 splits two independent SETs doesn't handle this case correctly when it
2076 updates the register status. Also check the case where the first
2077 SET's destination is unused. That would not cause incorrect code, but
2078 does cause an unneeded insn to remain. */
2080 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2081 && XVECLEN (newpat, 0) == 2
2082 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2083 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2084 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
2085 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
2086 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
2087 && asm_noperands (newpat) < 0)
2089 newpat = XVECEXP (newpat, 0, 0);
2090 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2093 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
2094 && XVECLEN (newpat, 0) == 2
2095 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2096 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2097 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
2098 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
2099 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
2100 && asm_noperands (newpat) < 0)
2102 newpat = XVECEXP (newpat, 0, 1);
2103 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2106 /* If we were combining three insns and the result is a simple SET
2107 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2108 insns. There are two ways to do this. It can be split using a
2109 machine-specific method (like when you have an addition of a large
2110 constant) or by combine in the function find_split_point. */
2112 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2113 && asm_noperands (newpat) < 0)
2115 rtx m_split, *split;
2116 rtx ni2dest = i2dest;
2118 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2119 use I2DEST as a scratch register will help. In the latter case,
2120 convert I2DEST to the mode of the source of NEWPAT if we can. */
2122 m_split = split_insns (newpat, i3);
2124 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2125 inputs of NEWPAT. */
2127 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2128 possible to try that as a scratch reg. This would require adding
2129 more code to make it work though. */
2131 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2133 /* If I2DEST is a hard register or the only use of a pseudo,
2134 we can change its mode. */
2135 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2136 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2137 && GET_CODE (i2dest) == REG
2138 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2139 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2140 && ! REG_USERVAR_P (i2dest))))
2141 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2144 m_split = split_insns (gen_rtx_PARALLEL
2146 gen_rtvec (2, newpat,
2147 gen_rtx_CLOBBER (VOIDmode,
2150 /* If the split with the mode-changed register didn't work, try
2151 the original register. */
2152 if (! m_split && ni2dest != i2dest)
2153 m_split = split_insns (gen_rtx_PARALLEL
2155 gen_rtvec (2, newpat,
2156 gen_rtx_CLOBBER (VOIDmode,
2161 if (m_split && GET_CODE (m_split) != SEQUENCE)
2163 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2164 if (insn_code_number >= 0)
2167 else if (m_split && GET_CODE (m_split) == SEQUENCE
2168 && XVECLEN (m_split, 0) == 2
2169 && (next_real_insn (i2) == i3
2170 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
2174 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
2175 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
2177 i3set = single_set (XVECEXP (m_split, 0, 1));
2178 i2set = single_set (XVECEXP (m_split, 0, 0));
2180 /* In case we changed the mode of I2DEST, replace it in the
2181 pseudo-register table here. We can't do it above in case this
2182 code doesn't get executed and we do a split the other way. */
2184 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2185 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2187 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2189 /* If I2 or I3 has multiple SETs, we won't know how to track
2190 register status, so don't use these insns. If I2's destination
2191 is used between I2 and I3, we also can't use these insns. */
2193 if (i2_code_number >= 0 && i2set && i3set
2194 && (next_real_insn (i2) == i3
2195 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2196 insn_code_number = recog_for_combine (&newi3pat, i3,
2198 if (insn_code_number >= 0)
2201 /* It is possible that both insns now set the destination of I3.
2202 If so, we must show an extra use of it. */
2204 if (insn_code_number >= 0)
2206 rtx new_i3_dest = SET_DEST (i3set);
2207 rtx new_i2_dest = SET_DEST (i2set);
2209 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2210 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2211 || GET_CODE (new_i3_dest) == SUBREG)
2212 new_i3_dest = XEXP (new_i3_dest, 0);
2214 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2215 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2216 || GET_CODE (new_i2_dest) == SUBREG)
2217 new_i2_dest = XEXP (new_i2_dest, 0);
2219 if (GET_CODE (new_i3_dest) == REG
2220 && GET_CODE (new_i2_dest) == REG
2221 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2222 REG_N_SETS (REGNO (new_i2_dest))++;
2226 /* If we can split it and use I2DEST, go ahead and see if that
2227 helps things be recognized. Verify that none of the registers
2228 are set between I2 and I3. */
2229 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2231 && GET_CODE (i2dest) == REG
2233 /* We need I2DEST in the proper mode. If it is a hard register
2234 or the only use of a pseudo, we can change its mode. */
2235 && (GET_MODE (*split) == GET_MODE (i2dest)
2236 || GET_MODE (*split) == VOIDmode
2237 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2238 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2239 && ! REG_USERVAR_P (i2dest)))
2240 && (next_real_insn (i2) == i3
2241 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2242 /* We can't overwrite I2DEST if its value is still used by
2244 && ! reg_referenced_p (i2dest, newpat))
2246 rtx newdest = i2dest;
2247 enum rtx_code split_code = GET_CODE (*split);
2248 enum machine_mode split_mode = GET_MODE (*split);
2250 /* Get NEWDEST as a register in the proper mode. We have already
2251 validated that we can do this. */
2252 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2254 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2256 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2257 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2260 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2261 an ASHIFT. This can occur if it was inside a PLUS and hence
2262 appeared to be a memory address. This is a kludge. */
2263 if (split_code == MULT
2264 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2265 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2267 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2268 XEXP (*split, 0), GEN_INT (i)));
2269 /* Update split_code because we may not have a multiply
2271 split_code = GET_CODE (*split);
2274 #ifdef INSN_SCHEDULING
2275 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2276 be written as a ZERO_EXTEND. */
2277 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2278 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2282 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2283 SUBST (*split, newdest);
2284 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2286 /* If the split point was a MULT and we didn't have one before,
2287 don't use one now. */
2288 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2289 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2293 /* Check for a case where we loaded from memory in a narrow mode and
2294 then sign extended it, but we need both registers. In that case,
2295 we have a PARALLEL with both loads from the same memory location.
2296 We can split this into a load from memory followed by a register-register
2297 copy. This saves at least one insn, more if register allocation can
2300 We cannot do this if the destination of the second assignment is
2301 a register that we have already assumed is zero-extended. Similarly
2302 for a SUBREG of such a register. */
2304 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2305 && GET_CODE (newpat) == PARALLEL
2306 && XVECLEN (newpat, 0) == 2
2307 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2308 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2309 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2310 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2311 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2312 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2314 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2315 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2316 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2317 (GET_CODE (temp) == REG
2318 && reg_nonzero_bits[REGNO (temp)] != 0
2319 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2320 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2321 && (reg_nonzero_bits[REGNO (temp)]
2322 != GET_MODE_MASK (word_mode))))
2323 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2324 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2325 (GET_CODE (temp) == REG
2326 && reg_nonzero_bits[REGNO (temp)] != 0
2327 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2328 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2329 && (reg_nonzero_bits[REGNO (temp)]
2330 != GET_MODE_MASK (word_mode)))))
2331 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2332 SET_SRC (XVECEXP (newpat, 0, 1)))
2333 && ! find_reg_note (i3, REG_UNUSED,
2334 SET_DEST (XVECEXP (newpat, 0, 0))))
2338 newi2pat = XVECEXP (newpat, 0, 0);
2339 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2340 newpat = XVECEXP (newpat, 0, 1);
2341 SUBST (SET_SRC (newpat),
2342 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2343 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2345 if (i2_code_number >= 0)
2346 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2348 if (insn_code_number >= 0)
2353 /* If we will be able to accept this, we have made a change to the
2354 destination of I3. This can invalidate a LOG_LINKS pointing
2355 to I3. No other part of combine.c makes such a transformation.
2357 The new I3 will have a destination that was previously the
2358 destination of I1 or I2 and which was used in i2 or I3. Call
2359 distribute_links to make a LOG_LINK from the next use of
2360 that destination. */
2362 PATTERN (i3) = newpat;
2363 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2365 /* I3 now uses what used to be its destination and which is
2366 now I2's destination. That means we need a LOG_LINK from
2367 I3 to I2. But we used to have one, so we still will.
2369 However, some later insn might be using I2's dest and have
2370 a LOG_LINK pointing at I3. We must remove this link.
2371 The simplest way to remove the link is to point it at I1,
2372 which we know will be a NOTE. */
2374 for (insn = NEXT_INSN (i3);
2375 insn && (this_basic_block == n_basic_blocks - 1
2376 || insn != BLOCK_HEAD (this_basic_block + 1));
2377 insn = NEXT_INSN (insn))
2379 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2381 for (link = LOG_LINKS (insn); link;
2382 link = XEXP (link, 1))
2383 if (XEXP (link, 0) == i3)
2384 XEXP (link, 0) = i1;
2392 /* Similarly, check for a case where we have a PARALLEL of two independent
2393 SETs but we started with three insns. In this case, we can do the sets
2394 as two separate insns. This case occurs when some SET allows two
2395 other insns to combine, but the destination of that SET is still live. */
2397 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2398 && GET_CODE (newpat) == PARALLEL
2399 && XVECLEN (newpat, 0) == 2
2400 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2401 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2402 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2403 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2404 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2405 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2406 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2408 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2409 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2410 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2411 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2412 XVECEXP (newpat, 0, 0))
2413 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2414 XVECEXP (newpat, 0, 1))
2415 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2416 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2418 /* Normally, it doesn't matter which of the two is done first,
2419 but it does if one references cc0. In that case, it has to
2422 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2424 newi2pat = XVECEXP (newpat, 0, 0);
2425 newpat = XVECEXP (newpat, 0, 1);
2430 newi2pat = XVECEXP (newpat, 0, 1);
2431 newpat = XVECEXP (newpat, 0, 0);
2434 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2436 if (i2_code_number >= 0)
2437 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2440 /* If it still isn't recognized, fail and change things back the way they
2442 if ((insn_code_number < 0
2443 /* Is the result a reasonable ASM_OPERANDS? */
2444 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2450 /* If we had to change another insn, make sure it is valid also. */
2451 if (undobuf.other_insn)
2453 rtx other_pat = PATTERN (undobuf.other_insn);
2454 rtx new_other_notes;
2457 CLEAR_HARD_REG_SET (newpat_used_regs);
2459 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2462 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2468 PATTERN (undobuf.other_insn) = other_pat;
2470 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2471 are still valid. Then add any non-duplicate notes added by
2472 recog_for_combine. */
2473 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2475 next = XEXP (note, 1);
2477 if (REG_NOTE_KIND (note) == REG_UNUSED
2478 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2480 if (GET_CODE (XEXP (note, 0)) == REG)
2481 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2483 remove_note (undobuf.other_insn, note);
2487 for (note = new_other_notes; note; note = XEXP (note, 1))
2488 if (GET_CODE (XEXP (note, 0)) == REG)
2489 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2491 distribute_notes (new_other_notes, undobuf.other_insn,
2492 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2495 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2496 they are adjacent to each other or not. */
2498 rtx p = prev_nonnote_insn (i3);
2499 if (p && p != i2 && GET_CODE (p) == INSN && newi2pat
2500 && sets_cc0_p (newi2pat))
2508 /* We now know that we can do this combination. Merge the insns and
2509 update the status of registers and LOG_LINKS. */
2512 rtx i3notes, i2notes, i1notes = 0;
2513 rtx i3links, i2links, i1links = 0;
2516 /* Compute which registers we expect to eliminate. newi2pat may be setting
2517 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2518 same as i3dest, in which case newi2pat may be setting i1dest. */
2519 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2520 || i2dest_in_i2src || i2dest_in_i1src
2522 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2523 || (newi2pat && reg_set_p (i1dest, newi2pat))
2526 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2528 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2529 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2531 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2533 /* Ensure that we do not have something that should not be shared but
2534 occurs multiple times in the new insns. Check this by first
2535 resetting all the `used' flags and then copying anything is shared. */
2537 reset_used_flags (i3notes);
2538 reset_used_flags (i2notes);
2539 reset_used_flags (i1notes);
2540 reset_used_flags (newpat);
2541 reset_used_flags (newi2pat);
2542 if (undobuf.other_insn)
2543 reset_used_flags (PATTERN (undobuf.other_insn));
2545 i3notes = copy_rtx_if_shared (i3notes);
2546 i2notes = copy_rtx_if_shared (i2notes);
2547 i1notes = copy_rtx_if_shared (i1notes);
2548 newpat = copy_rtx_if_shared (newpat);
2549 newi2pat = copy_rtx_if_shared (newi2pat);
2550 if (undobuf.other_insn)
2551 reset_used_flags (PATTERN (undobuf.other_insn));
2553 INSN_CODE (i3) = insn_code_number;
2554 PATTERN (i3) = newpat;
2555 if (undobuf.other_insn)
2556 INSN_CODE (undobuf.other_insn) = other_code_number;
2558 /* We had one special case above where I2 had more than one set and
2559 we replaced a destination of one of those sets with the destination
2560 of I3. In that case, we have to update LOG_LINKS of insns later
2561 in this basic block. Note that this (expensive) case is rare.
2563 Also, in this case, we must pretend that all REG_NOTEs for I2
2564 actually came from I3, so that REG_UNUSED notes from I2 will be
2565 properly handled. */
2567 if (i3_subst_into_i2)
2569 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2570 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2571 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2572 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2573 && ! find_reg_note (i2, REG_UNUSED,
2574 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2575 for (temp = NEXT_INSN (i2);
2576 temp && (this_basic_block == n_basic_blocks - 1
2577 || BLOCK_HEAD (this_basic_block) != temp);
2578 temp = NEXT_INSN (temp))
2579 if (temp != i3 && INSN_P (temp))
2580 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2581 if (XEXP (link, 0) == i2)
2582 XEXP (link, 0) = i3;
2587 while (XEXP (link, 1))
2588 link = XEXP (link, 1);
2589 XEXP (link, 1) = i2notes;
2603 INSN_CODE (i2) = i2_code_number;
2604 PATTERN (i2) = newi2pat;
2608 PUT_CODE (i2, NOTE);
2609 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2610 NOTE_SOURCE_FILE (i2) = 0;
2617 PUT_CODE (i1, NOTE);
2618 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2619 NOTE_SOURCE_FILE (i1) = 0;
2622 /* Get death notes for everything that is now used in either I3 or
2623 I2 and used to die in a previous insn. If we built two new
2624 patterns, move from I1 to I2 then I2 to I3 so that we get the
2625 proper movement on registers that I2 modifies. */
2629 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2630 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2633 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2636 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2638 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2641 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2644 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2647 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2650 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2651 know these are REG_UNUSED and want them to go to the desired insn,
2652 so we always pass it as i3. We have not counted the notes in
2653 reg_n_deaths yet, so we need to do so now. */
2655 if (newi2pat && new_i2_notes)
2657 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2658 if (GET_CODE (XEXP (temp, 0)) == REG)
2659 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2661 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2666 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2667 if (GET_CODE (XEXP (temp, 0)) == REG)
2668 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2670 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2673 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2674 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2675 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2676 in that case, it might delete I2. Similarly for I2 and I1.
2677 Show an additional death due to the REG_DEAD note we make here. If
2678 we discard it in distribute_notes, we will decrement it again. */
2682 if (GET_CODE (i3dest_killed) == REG)
2683 REG_N_DEATHS (REGNO (i3dest_killed))++;
2685 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2686 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2688 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2690 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2692 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2696 if (i2dest_in_i2src)
2698 if (GET_CODE (i2dest) == REG)
2699 REG_N_DEATHS (REGNO (i2dest))++;
2701 if (newi2pat && reg_set_p (i2dest, newi2pat))
2702 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2703 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2705 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2706 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2707 NULL_RTX, NULL_RTX);
2710 if (i1dest_in_i1src)
2712 if (GET_CODE (i1dest) == REG)
2713 REG_N_DEATHS (REGNO (i1dest))++;
2715 if (newi2pat && reg_set_p (i1dest, newi2pat))
2716 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2717 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2719 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2720 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2721 NULL_RTX, NULL_RTX);
2724 distribute_links (i3links);
2725 distribute_links (i2links);
2726 distribute_links (i1links);
2728 if (GET_CODE (i2dest) == REG)
2731 rtx i2_insn = 0, i2_val = 0, set;
2733 /* The insn that used to set this register doesn't exist, and
2734 this life of the register may not exist either. See if one of
2735 I3's links points to an insn that sets I2DEST. If it does,
2736 that is now the last known value for I2DEST. If we don't update
2737 this and I2 set the register to a value that depended on its old
2738 contents, we will get confused. If this insn is used, thing
2739 will be set correctly in combine_instructions. */
2741 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2742 if ((set = single_set (XEXP (link, 0))) != 0
2743 && rtx_equal_p (i2dest, SET_DEST (set)))
2744 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2746 record_value_for_reg (i2dest, i2_insn, i2_val);
2748 /* If the reg formerly set in I2 died only once and that was in I3,
2749 zero its use count so it won't make `reload' do any work. */
2751 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2752 && ! i2dest_in_i2src)
2754 regno = REGNO (i2dest);
2755 REG_N_SETS (regno)--;
2759 if (i1 && GET_CODE (i1dest) == REG)
2762 rtx i1_insn = 0, i1_val = 0, set;
2764 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2765 if ((set = single_set (XEXP (link, 0))) != 0
2766 && rtx_equal_p (i1dest, SET_DEST (set)))
2767 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2769 record_value_for_reg (i1dest, i1_insn, i1_val);
2771 regno = REGNO (i1dest);
2772 if (! added_sets_1 && ! i1dest_in_i1src)
2773 REG_N_SETS (regno)--;
2776 /* Update reg_nonzero_bits et al for any changes that may have been made
2777 to this insn. The order of set_nonzero_bits_and_sign_copies() is
2778 important. Because newi2pat can affect nonzero_bits of newpat */
2780 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2781 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2783 /* Set new_direct_jump_p if a new return or simple jump instruction
2786 If I3 is now an unconditional jump, ensure that it has a
2787 BARRIER following it since it may have initially been a
2788 conditional jump. It may also be the last nonnote insn. */
2790 if (GET_CODE (newpat) == RETURN || any_uncondjump_p (i3))
2792 *new_direct_jump_p = 1;
2794 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2795 || GET_CODE (temp) != BARRIER)
2796 emit_barrier_after (i3);
2800 combine_successes++;
2803 /* Clear this here, so that subsequent get_last_value calls are not
2805 subst_prev_insn = NULL_RTX;
2807 if (added_links_insn
2808 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2809 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2810 return added_links_insn;
2812 return newi2pat ? i2 : i3;
2815 /* Undo all the modifications recorded in undobuf. */
2820 struct undo *undo, *next;
2822 for (undo = undobuf.undos; undo; undo = next)
2826 *undo->where.i = undo->old_contents.i;
2828 *undo->where.r = undo->old_contents.r;
2830 undo->next = undobuf.frees;
2831 undobuf.frees = undo;
2834 undobuf.undos = undobuf.previous_undos = 0;
2836 /* Clear this here, so that subsequent get_last_value calls are not
2838 subst_prev_insn = NULL_RTX;
2841 /* We've committed to accepting the changes we made. Move all
2842 of the undos to the free list. */
2847 struct undo *undo, *next;
2849 for (undo = undobuf.undos; undo; undo = next)
2852 undo->next = undobuf.frees;
2853 undobuf.frees = undo;
2855 undobuf.undos = undobuf.previous_undos = 0;
2859 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2860 where we have an arithmetic expression and return that point. LOC will
2863 try_combine will call this function to see if an insn can be split into
2867 find_split_point (loc, insn)
2872 enum rtx_code code = GET_CODE (x);
2874 unsigned HOST_WIDE_INT len = 0;
2875 HOST_WIDE_INT pos = 0;
2877 rtx inner = NULL_RTX;
2879 /* First special-case some codes. */
2883 #ifdef INSN_SCHEDULING
2884 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2886 if (GET_CODE (SUBREG_REG (x)) == MEM)
2889 return find_split_point (&SUBREG_REG (x), insn);
2893 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2894 using LO_SUM and HIGH. */
2895 if (GET_CODE (XEXP (x, 0)) == CONST
2896 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2899 gen_rtx_combine (LO_SUM, Pmode,
2900 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2902 return &XEXP (XEXP (x, 0), 0);
2906 /* If we have a PLUS whose second operand is a constant and the
2907 address is not valid, perhaps will can split it up using
2908 the machine-specific way to split large constants. We use
2909 the first pseudo-reg (one of the virtual regs) as a placeholder;
2910 it will not remain in the result. */
2911 if (GET_CODE (XEXP (x, 0)) == PLUS
2912 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2913 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2915 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2916 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2919 /* This should have produced two insns, each of which sets our
2920 placeholder. If the source of the second is a valid address,
2921 we can make put both sources together and make a split point
2924 if (seq && XVECLEN (seq, 0) == 2
2925 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2926 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2927 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2928 && ! reg_mentioned_p (reg,
2929 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2930 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2931 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2932 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2933 && memory_address_p (GET_MODE (x),
2934 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2936 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2937 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2939 /* Replace the placeholder in SRC2 with SRC1. If we can
2940 find where in SRC2 it was placed, that can become our
2941 split point and we can replace this address with SRC2.
2942 Just try two obvious places. */
2944 src2 = replace_rtx (src2, reg, src1);
2946 if (XEXP (src2, 0) == src1)
2947 split = &XEXP (src2, 0);
2948 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2949 && XEXP (XEXP (src2, 0), 0) == src1)
2950 split = &XEXP (XEXP (src2, 0), 0);
2954 SUBST (XEXP (x, 0), src2);
2959 /* If that didn't work, perhaps the first operand is complex and
2960 needs to be computed separately, so make a split point there.
2961 This will occur on machines that just support REG + CONST
2962 and have a constant moved through some previous computation. */
2964 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2965 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2966 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2968 return &XEXP (XEXP (x, 0), 0);
2974 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2975 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2976 we need to put the operand into a register. So split at that
2979 if (SET_DEST (x) == cc0_rtx
2980 && GET_CODE (SET_SRC (x)) != COMPARE
2981 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2982 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2983 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2984 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2985 return &SET_SRC (x);
2988 /* See if we can split SET_SRC as it stands. */
2989 split = find_split_point (&SET_SRC (x), insn);
2990 if (split && split != &SET_SRC (x))
2993 /* See if we can split SET_DEST as it stands. */
2994 split = find_split_point (&SET_DEST (x), insn);
2995 if (split && split != &SET_DEST (x))
2998 /* See if this is a bitfield assignment with everything constant. If
2999 so, this is an IOR of an AND, so split it into that. */
3000 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3001 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3002 <= HOST_BITS_PER_WIDE_INT)
3003 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3004 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3005 && GET_CODE (SET_SRC (x)) == CONST_INT
3006 && ((INTVAL (XEXP (SET_DEST (x), 1))
3007 + INTVAL (XEXP (SET_DEST (x), 2)))
3008 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3009 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3011 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3012 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3013 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3014 rtx dest = XEXP (SET_DEST (x), 0);
3015 enum machine_mode mode = GET_MODE (dest);
3016 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3018 if (BITS_BIG_ENDIAN)
3019 pos = GET_MODE_BITSIZE (mode) - len - pos;
3023 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3026 gen_binary (IOR, mode,
3027 gen_binary (AND, mode, dest,
3028 GEN_INT (~(mask << pos)
3029 & GET_MODE_MASK (mode))),
3030 GEN_INT (src << pos)));
3032 SUBST (SET_DEST (x), dest);
3034 split = find_split_point (&SET_SRC (x), insn);
3035 if (split && split != &SET_SRC (x))
3039 /* Otherwise, see if this is an operation that we can split into two.
3040 If so, try to split that. */
3041 code = GET_CODE (SET_SRC (x));
3046 /* If we are AND'ing with a large constant that is only a single
3047 bit and the result is only being used in a context where we
3048 need to know if it is zero or non-zero, replace it with a bit
3049 extraction. This will avoid the large constant, which might
3050 have taken more than one insn to make. If the constant were
3051 not a valid argument to the AND but took only one insn to make,
3052 this is no worse, but if it took more than one insn, it will
3055 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3056 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
3057 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3058 && GET_CODE (SET_DEST (x)) == REG
3059 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
3060 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3061 && XEXP (*split, 0) == SET_DEST (x)
3062 && XEXP (*split, 1) == const0_rtx)
3064 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3065 XEXP (SET_SRC (x), 0),
3066 pos, NULL_RTX, 1, 1, 0, 0);
3067 if (extraction != 0)
3069 SUBST (SET_SRC (x), extraction);
3070 return find_split_point (loc, insn);
3076 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3077 is known to be on, this can be converted into a NEG of a shift. */
3078 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3079 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3080 && 1 <= (pos = exact_log2
3081 (nonzero_bits (XEXP (SET_SRC (x), 0),
3082 GET_MODE (XEXP (SET_SRC (x), 0))))))
3084 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3087 gen_rtx_combine (NEG, mode,
3088 gen_rtx_combine (LSHIFTRT, mode,
3089 XEXP (SET_SRC (x), 0),
3092 split = find_split_point (&SET_SRC (x), insn);
3093 if (split && split != &SET_SRC (x))
3099 inner = XEXP (SET_SRC (x), 0);
3101 /* We can't optimize if either mode is a partial integer
3102 mode as we don't know how many bits are significant
3104 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3105 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3109 len = GET_MODE_BITSIZE (GET_MODE (inner));
3115 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3116 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3118 inner = XEXP (SET_SRC (x), 0);
3119 len = INTVAL (XEXP (SET_SRC (x), 1));
3120 pos = INTVAL (XEXP (SET_SRC (x), 2));
3122 if (BITS_BIG_ENDIAN)
3123 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3124 unsignedp = (code == ZERO_EXTRACT);
3132 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3134 enum machine_mode mode = GET_MODE (SET_SRC (x));
3136 /* For unsigned, we have a choice of a shift followed by an
3137 AND or two shifts. Use two shifts for field sizes where the
3138 constant might be too large. We assume here that we can
3139 always at least get 8-bit constants in an AND insn, which is
3140 true for every current RISC. */
3142 if (unsignedp && len <= 8)
3147 gen_rtx_combine (LSHIFTRT, mode,
3148 gen_lowpart_for_combine (mode, inner),
3150 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3152 split = find_split_point (&SET_SRC (x), insn);
3153 if (split && split != &SET_SRC (x))
3160 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3161 gen_rtx_combine (ASHIFT, mode,
3162 gen_lowpart_for_combine (mode, inner),
3163 GEN_INT (GET_MODE_BITSIZE (mode)
3165 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3167 split = find_split_point (&SET_SRC (x), insn);
3168 if (split && split != &SET_SRC (x))
3173 /* See if this is a simple operation with a constant as the second
3174 operand. It might be that this constant is out of range and hence
3175 could be used as a split point. */
3176 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3177 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3178 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
3179 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3180 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
3181 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3182 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
3184 return &XEXP (SET_SRC (x), 1);
3186 /* Finally, see if this is a simple operation with its first operand
3187 not in a register. The operation might require this operand in a
3188 register, so return it as a split point. We can always do this
3189 because if the first operand were another operation, we would have
3190 already found it as a split point. */
3191 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
3192 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
3193 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
3194 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
3195 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3196 return &XEXP (SET_SRC (x), 0);
3202 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3203 it is better to write this as (not (ior A B)) so we can split it.
3204 Similarly for IOR. */
3205 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3208 gen_rtx_combine (NOT, GET_MODE (x),
3209 gen_rtx_combine (code == IOR ? AND : IOR,
3211 XEXP (XEXP (x, 0), 0),
3212 XEXP (XEXP (x, 1), 0))));
3213 return find_split_point (loc, insn);
3216 /* Many RISC machines have a large set of logical insns. If the
3217 second operand is a NOT, put it first so we will try to split the
3218 other operand first. */
3219 if (GET_CODE (XEXP (x, 1)) == NOT)
3221 rtx tem = XEXP (x, 0);
3222 SUBST (XEXP (x, 0), XEXP (x, 1));
3223 SUBST (XEXP (x, 1), tem);
3231 /* Otherwise, select our actions depending on our rtx class. */
3232 switch (GET_RTX_CLASS (code))
3234 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3236 split = find_split_point (&XEXP (x, 2), insn);
3239 /* ... fall through ... */
3243 split = find_split_point (&XEXP (x, 1), insn);
3246 /* ... fall through ... */
3248 /* Some machines have (and (shift ...) ...) insns. If X is not
3249 an AND, but XEXP (X, 0) is, use it as our split point. */
3250 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3251 return &XEXP (x, 0);
3253 split = find_split_point (&XEXP (x, 0), insn);
3259 /* Otherwise, we don't have a split point. */
3263 /* Throughout X, replace FROM with TO, and return the result.
3264 The result is TO if X is FROM;
3265 otherwise the result is X, but its contents may have been modified.
3266 If they were modified, a record was made in undobuf so that
3267 undo_all will (among other things) return X to its original state.
3269 If the number of changes necessary is too much to record to undo,
3270 the excess changes are not made, so the result is invalid.
3271 The changes already made can still be undone.
3272 undobuf.num_undo is incremented for such changes, so by testing that
3273 the caller can tell whether the result is valid.
3275 `n_occurrences' is incremented each time FROM is replaced.
3277 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3279 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3280 by copying if `n_occurrences' is non-zero. */
3283 subst (x, from, to, in_dest, unique_copy)
3284 register rtx x, from, to;
3288 register enum rtx_code code = GET_CODE (x);
3289 enum machine_mode op0_mode = VOIDmode;
3290 register const char *fmt;
3291 register int len, i;
3294 /* Two expressions are equal if they are identical copies of a shared
3295 RTX or if they are both registers with the same register number
3298 #define COMBINE_RTX_EQUAL_P(X,Y) \
3300 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3301 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3303 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3306 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3309 /* If X and FROM are the same register but different modes, they will
3310 not have been seen as equal above. However, flow.c will make a
3311 LOG_LINKS entry for that case. If we do nothing, we will try to
3312 rerecognize our original insn and, when it succeeds, we will
3313 delete the feeding insn, which is incorrect.
3315 So force this insn not to match in this (rare) case. */
3316 if (! in_dest && code == REG && GET_CODE (from) == REG
3317 && REGNO (x) == REGNO (from))
3318 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3320 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3321 of which may contain things that can be combined. */
3322 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3325 /* It is possible to have a subexpression appear twice in the insn.
3326 Suppose that FROM is a register that appears within TO.
3327 Then, after that subexpression has been scanned once by `subst',
3328 the second time it is scanned, TO may be found. If we were
3329 to scan TO here, we would find FROM within it and create a
3330 self-referent rtl structure which is completely wrong. */
3331 if (COMBINE_RTX_EQUAL_P (x, to))
3334 /* Parallel asm_operands need special attention because all of the
3335 inputs are shared across the arms. Furthermore, unsharing the
3336 rtl results in recognition failures. Failure to handle this case
3337 specially can result in circular rtl.
3339 Solve this by doing a normal pass across the first entry of the
3340 parallel, and only processing the SET_DESTs of the subsequent
3343 if (code == PARALLEL
3344 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3345 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3347 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3349 /* If this substitution failed, this whole thing fails. */
3350 if (GET_CODE (new) == CLOBBER
3351 && XEXP (new, 0) == const0_rtx)
3354 SUBST (XVECEXP (x, 0, 0), new);
3356 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3358 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3360 if (GET_CODE (dest) != REG
3361 && GET_CODE (dest) != CC0
3362 && GET_CODE (dest) != PC)
3364 new = subst (dest, from, to, 0, unique_copy);
3366 /* If this substitution failed, this whole thing fails. */
3367 if (GET_CODE (new) == CLOBBER
3368 && XEXP (new, 0) == const0_rtx)
3371 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3377 len = GET_RTX_LENGTH (code);
3378 fmt = GET_RTX_FORMAT (code);
3380 /* We don't need to process a SET_DEST that is a register, CC0,
3381 or PC, so set up to skip this common case. All other cases
3382 where we want to suppress replacing something inside a
3383 SET_SRC are handled via the IN_DEST operand. */
3385 && (GET_CODE (SET_DEST (x)) == REG
3386 || GET_CODE (SET_DEST (x)) == CC0
3387 || GET_CODE (SET_DEST (x)) == PC))
3390 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3393 op0_mode = GET_MODE (XEXP (x, 0));
3395 for (i = 0; i < len; i++)
3400 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3402 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3404 new = (unique_copy && n_occurrences
3405 ? copy_rtx (to) : to);
3410 new = subst (XVECEXP (x, i, j), from, to, 0,
3413 /* If this substitution failed, this whole thing
3415 if (GET_CODE (new) == CLOBBER
3416 && XEXP (new, 0) == const0_rtx)
3420 SUBST (XVECEXP (x, i, j), new);
3423 else if (fmt[i] == 'e')
3425 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3427 /* In general, don't install a subreg involving two
3428 modes not tieable. It can worsen register
3429 allocation, and can even make invalid reload
3430 insns, since the reg inside may need to be copied
3431 from in the outside mode, and that may be invalid
3432 if it is an fp reg copied in integer mode.
3434 We allow two exceptions to this: It is valid if
3435 it is inside another SUBREG and the mode of that
3436 SUBREG and the mode of the inside of TO is
3437 tieable and it is valid if X is a SET that copies
3440 if (GET_CODE (to) == SUBREG
3441 && ! MODES_TIEABLE_P (GET_MODE (to),
3442 GET_MODE (SUBREG_REG (to)))
3443 && ! (code == SUBREG
3444 && MODES_TIEABLE_P (GET_MODE (x),
3445 GET_MODE (SUBREG_REG (to))))
3447 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3450 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3452 #ifdef CLASS_CANNOT_CHANGE_MODE
3454 && GET_CODE (to) == REG
3455 && REGNO (to) < FIRST_PSEUDO_REGISTER
3456 && (TEST_HARD_REG_BIT
3457 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
3459 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (to),
3461 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3464 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3468 /* If we are in a SET_DEST, suppress most cases unless we
3469 have gone inside a MEM, in which case we want to
3470 simplify the address. We assume here that things that
3471 are actually part of the destination have their inner
3472 parts in the first expression. This is true for SUBREG,
3473 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3474 things aside from REG and MEM that should appear in a
3476 new = subst (XEXP (x, i), from, to,
3478 && (code == SUBREG || code == STRICT_LOW_PART
3479 || code == ZERO_EXTRACT))
3481 && i == 0), unique_copy);
3483 /* If we found that we will have to reject this combination,
3484 indicate that by returning the CLOBBER ourselves, rather than
3485 an expression containing it. This will speed things up as
3486 well as prevent accidents where two CLOBBERs are considered
3487 to be equal, thus producing an incorrect simplification. */
3489 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3492 SUBST (XEXP (x, i), new);
3497 /* Try to simplify X. If the simplification changed the code, it is likely
3498 that further simplification will help, so loop, but limit the number
3499 of repetitions that will be performed. */
3501 for (i = 0; i < 4; i++)
3503 /* If X is sufficiently simple, don't bother trying to do anything
3505 if (code != CONST_INT && code != REG && code != CLOBBER)
3506 x = combine_simplify_rtx (x, op0_mode, i == 3, in_dest);
3508 if (GET_CODE (x) == code)
3511 code = GET_CODE (x);
3513 /* We no longer know the original mode of operand 0 since we
3514 have changed the form of X) */
3515 op0_mode = VOIDmode;
3521 /* Simplify X, a piece of RTL. We just operate on the expression at the
3522 outer level; call `subst' to simplify recursively. Return the new
3525 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3526 will be the iteration even if an expression with a code different from
3527 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3530 combine_simplify_rtx (x, op0_mode, last, in_dest)
3532 enum machine_mode op0_mode;
3536 enum rtx_code code = GET_CODE (x);
3537 enum machine_mode mode = GET_MODE (x);
3542 /* If this is a commutative operation, put a constant last and a complex
3543 expression first. We don't need to do this for comparisons here. */
3544 if (GET_RTX_CLASS (code) == 'c'
3545 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3546 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3547 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3548 || (GET_CODE (XEXP (x, 0)) == SUBREG
3549 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3550 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3553 SUBST (XEXP (x, 0), XEXP (x, 1));
3554 SUBST (XEXP (x, 1), temp);
3557 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3558 sign extension of a PLUS with a constant, reverse the order of the sign
3559 extension and the addition. Note that this not the same as the original
3560 code, but overflow is undefined for signed values. Also note that the
3561 PLUS will have been partially moved "inside" the sign-extension, so that
3562 the first operand of X will really look like:
3563 (ashiftrt (plus (ashift A C4) C5) C4).
3565 (plus (ashiftrt (ashift A C4) C2) C4)
3566 and replace the first operand of X with that expression. Later parts
3567 of this function may simplify the expression further.
3569 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3570 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3571 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3573 We do this to simplify address expressions. */
3575 if ((code == PLUS || code == MINUS || code == MULT)
3576 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3577 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3578 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3579 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3580 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3581 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3582 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3583 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3584 XEXP (XEXP (XEXP (x, 0), 0), 1),
3585 XEXP (XEXP (x, 0), 1))) != 0)
3588 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3589 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3590 INTVAL (XEXP (XEXP (x, 0), 1)));
3592 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3593 INTVAL (XEXP (XEXP (x, 0), 1)));
3595 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3598 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3599 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3600 things. Check for cases where both arms are testing the same
3603 Don't do anything if all operands are very simple. */
3605 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3606 || GET_RTX_CLASS (code) == '<')
3607 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3608 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3609 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3611 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3612 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3613 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3615 || (GET_RTX_CLASS (code) == '1'
3616 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3617 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3618 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3621 rtx cond, true_rtx, false_rtx;
3623 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3625 /* If everything is a comparison, what we have is highly unlikely
3626 to be simpler, so don't use it. */
3627 && ! (GET_RTX_CLASS (code) == '<'
3628 && (GET_RTX_CLASS (GET_CODE (true_rtx)) == '<'
3629 || GET_RTX_CLASS (GET_CODE (false_rtx)) == '<')))
3631 rtx cop1 = const0_rtx;
3632 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3634 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3637 /* Simplify the alternative arms; this may collapse the true and
3638 false arms to store-flag values. */
3639 true_rtx = subst (true_rtx, pc_rtx, pc_rtx, 0, 0);
3640 false_rtx = subst (false_rtx, pc_rtx, pc_rtx, 0, 0);
3642 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3643 is unlikely to be simpler. */
3644 if (general_operand (true_rtx, VOIDmode)
3645 && general_operand (false_rtx, VOIDmode))
3647 /* Restarting if we generate a store-flag expression will cause
3648 us to loop. Just drop through in this case. */
3650 /* If the result values are STORE_FLAG_VALUE and zero, we can
3651 just make the comparison operation. */
3652 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3653 x = gen_binary (cond_code, mode, cond, cop1);
3654 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx)
3655 x = gen_binary (reverse_condition (cond_code),
3658 /* Likewise, we can make the negate of a comparison operation
3659 if the result values are - STORE_FLAG_VALUE and zero. */
3660 else if (GET_CODE (true_rtx) == CONST_INT
3661 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3662 && false_rtx == const0_rtx)
3663 x = gen_unary (NEG, mode, mode,
3664 gen_binary (cond_code, mode, cond, cop1));
3665 else if (GET_CODE (false_rtx) == CONST_INT
3666 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3667 && true_rtx == const0_rtx)
3668 x = gen_unary (NEG, mode, mode,
3669 gen_binary (reverse_condition (cond_code),
3672 return gen_rtx_IF_THEN_ELSE (mode,
3673 gen_binary (cond_code, VOIDmode,
3675 true_rtx, false_rtx);
3677 code = GET_CODE (x);
3678 op0_mode = VOIDmode;
3683 /* Try to fold this expression in case we have constants that weren't
3686 switch (GET_RTX_CLASS (code))
3689 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3693 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3694 if (cmp_mode == VOIDmode)
3696 cmp_mode = GET_MODE (XEXP (x, 1));
3697 if (cmp_mode == VOIDmode)
3698 cmp_mode = op0_mode;
3700 temp = simplify_relational_operation (code, cmp_mode,
3701 XEXP (x, 0), XEXP (x, 1));
3703 #ifdef FLOAT_STORE_FLAG_VALUE
3704 if (temp != 0 && GET_MODE_CLASS (mode) == MODE_FLOAT)
3706 if (temp == const0_rtx)
3707 temp = CONST0_RTX (mode);
3709 temp = immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode), mode);
3715 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3719 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3720 XEXP (x, 1), XEXP (x, 2));
3725 x = temp, code = GET_CODE (temp);
3727 /* First see if we can apply the inverse distributive law. */
3728 if (code == PLUS || code == MINUS
3729 || code == AND || code == IOR || code == XOR)
3731 x = apply_distributive_law (x);
3732 code = GET_CODE (x);
3735 /* If CODE is an associative operation not otherwise handled, see if we
3736 can associate some operands. This can win if they are constants or
3737 if they are logically related (i.e. (a & b) & a. */
3738 if ((code == PLUS || code == MINUS
3739 || code == MULT || code == AND || code == IOR || code == XOR
3740 || code == DIV || code == UDIV
3741 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3742 && INTEGRAL_MODE_P (mode))
3744 if (GET_CODE (XEXP (x, 0)) == code)
3746 rtx other = XEXP (XEXP (x, 0), 0);
3747 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3748 rtx inner_op1 = XEXP (x, 1);
3751 /* Make sure we pass the constant operand if any as the second
3752 one if this is a commutative operation. */
3753 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3755 rtx tem = inner_op0;
3756 inner_op0 = inner_op1;
3759 inner = simplify_binary_operation (code == MINUS ? PLUS
3760 : code == DIV ? MULT
3761 : code == UDIV ? MULT
3763 mode, inner_op0, inner_op1);
3765 /* For commutative operations, try the other pair if that one
3767 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3769 other = XEXP (XEXP (x, 0), 1);
3770 inner = simplify_binary_operation (code, mode,
3771 XEXP (XEXP (x, 0), 0),
3776 return gen_binary (code, mode, other, inner);
3780 /* A little bit of algebraic simplification here. */
3784 /* Ensure that our address has any ASHIFTs converted to MULT in case
3785 address-recognizing predicates are called later. */
3786 temp = make_compound_operation (XEXP (x, 0), MEM);
3787 SUBST (XEXP (x, 0), temp);
3791 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3792 is paradoxical. If we can't do that safely, then it becomes
3793 something nonsensical so that this combination won't take place. */
3795 if (GET_CODE (SUBREG_REG (x)) == MEM
3796 && (GET_MODE_SIZE (mode)
3797 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3799 rtx inner = SUBREG_REG (x);
3800 int endian_offset = 0;
3801 /* Don't change the mode of the MEM
3802 if that would change the meaning of the address. */
3803 if (MEM_VOLATILE_P (SUBREG_REG (x))
3804 || mode_dependent_address_p (XEXP (inner, 0)))
3805 return gen_rtx_CLOBBER (mode, const0_rtx);
3807 if (BYTES_BIG_ENDIAN)
3809 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3810 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3811 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3812 endian_offset -= (UNITS_PER_WORD
3813 - GET_MODE_SIZE (GET_MODE (inner)));
3815 /* Note if the plus_constant doesn't make a valid address
3816 then this combination won't be accepted. */
3817 x = gen_rtx_MEM (mode,
3818 plus_constant (XEXP (inner, 0),
3819 (SUBREG_WORD (x) * UNITS_PER_WORD
3821 MEM_COPY_ATTRIBUTES (x, inner);
3825 /* If we are in a SET_DEST, these other cases can't apply. */
3829 /* Changing mode twice with SUBREG => just change it once,
3830 or not at all if changing back to starting mode. */
3831 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3833 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3834 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3835 return SUBREG_REG (SUBREG_REG (x));
3837 SUBST_INT (SUBREG_WORD (x),
3838 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3839 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3842 /* SUBREG of a hard register => just change the register number
3843 and/or mode. If the hard register is not valid in that mode,
3844 suppress this combination. If the hard register is the stack,
3845 frame, or argument pointer, leave this as a SUBREG. */
3847 if (GET_CODE (SUBREG_REG (x)) == REG
3848 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3849 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3850 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3851 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3853 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3854 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3856 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3858 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3860 return gen_rtx_REG (mode,
3861 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3863 return gen_rtx_CLOBBER (mode, const0_rtx);
3866 /* For a constant, try to pick up the part we want. Handle a full
3867 word and low-order part. Only do this if we are narrowing
3868 the constant; if it is being widened, we have no idea what
3869 the extra bits will have been set to. */
3871 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3872 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3873 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3874 && GET_MODE_CLASS (mode) == MODE_INT)
3876 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3882 /* If we want a subreg of a constant, at offset 0,
3883 take the low bits. On a little-endian machine, that's
3884 always valid. On a big-endian machine, it's valid
3885 only if the constant's mode fits in one word. Note that we
3886 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3887 if (CONSTANT_P (SUBREG_REG (x))
3888 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3889 || ! WORDS_BIG_ENDIAN)
3890 ? SUBREG_WORD (x) == 0
3892 == ((GET_MODE_SIZE (op0_mode)
3893 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3895 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3896 && (! WORDS_BIG_ENDIAN
3897 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3898 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3900 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3901 since we are saying that the high bits don't matter. */
3902 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3903 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3905 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
3906 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
3907 return operand_subword (SUBREG_REG (x), SUBREG_WORD (x), 0, mode);
3908 return SUBREG_REG (x);
3911 /* Note that we cannot do any narrowing for non-constants since
3912 we might have been counting on using the fact that some bits were
3913 zero. We now do this in the SET. */
3918 /* (not (plus X -1)) can become (neg X). */
3919 if (GET_CODE (XEXP (x, 0)) == PLUS
3920 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3921 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3923 /* Similarly, (not (neg X)) is (plus X -1). */
3924 if (GET_CODE (XEXP (x, 0)) == NEG)
3925 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3928 /* (not (xor X C)) for C constant is (xor X D) with D = ~C. */
3929 if (GET_CODE (XEXP (x, 0)) == XOR
3930 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3931 && (temp = simplify_unary_operation (NOT, mode,
3932 XEXP (XEXP (x, 0), 1),
3934 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3936 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3937 other than 1, but that is not valid. We could do a similar
3938 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3939 but this doesn't seem common enough to bother with. */
3940 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3941 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3942 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3943 XEXP (XEXP (x, 0), 1));
3945 if (GET_CODE (XEXP (x, 0)) == SUBREG
3946 && subreg_lowpart_p (XEXP (x, 0))
3947 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3948 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3949 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3950 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3952 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3954 x = gen_rtx_ROTATE (inner_mode,
3955 gen_unary (NOT, inner_mode, inner_mode,
3957 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3958 return gen_lowpart_for_combine (mode, x);
3961 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3962 reversing the comparison code if valid. */
3963 if (STORE_FLAG_VALUE == -1
3964 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3965 && (reversed = reversed_comparison (x, mode, XEXP (XEXP (x, 0), 0),
3966 XEXP (XEXP (x, 0), 1))))
3969 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3970 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3971 perform the above simplification. */
3973 if (STORE_FLAG_VALUE == -1
3974 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3975 && XEXP (x, 1) == const1_rtx
3976 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3977 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3978 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3980 /* Apply De Morgan's laws to reduce number of patterns for machines
3981 with negating logical insns (and-not, nand, etc.). If result has
3982 only one NOT, put it first, since that is how the patterns are
3985 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3987 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3988 enum machine_mode op_mode;
3990 op_mode = GET_MODE (in1);
3991 in1 = gen_unary (NOT, op_mode, op_mode, in1);
3993 op_mode = GET_MODE (in2);
3994 if (op_mode == VOIDmode)
3996 in2 = gen_unary (NOT, op_mode, op_mode, in2);
3998 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4001 in2 = in1; in1 = tem;
4004 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4010 /* (neg (plus X 1)) can become (not X). */
4011 if (GET_CODE (XEXP (x, 0)) == PLUS
4012 && XEXP (XEXP (x, 0), 1) == const1_rtx)
4013 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
4015 /* Similarly, (neg (not X)) is (plus X 1). */
4016 if (GET_CODE (XEXP (x, 0)) == NOT)
4017 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
4019 /* (neg (minus X Y)) can become (minus Y X). */
4020 if (GET_CODE (XEXP (x, 0)) == MINUS
4021 && (! FLOAT_MODE_P (mode)
4022 /* x-y != -(y-x) with IEEE floating point. */
4023 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4024 || flag_unsafe_math_optimizations))
4025 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
4026 XEXP (XEXP (x, 0), 0));
4028 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4029 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
4030 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4031 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4033 /* NEG commutes with ASHIFT since it is multiplication. Only do this
4034 if we can then eliminate the NEG (e.g.,
4035 if the operand is a constant). */
4037 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
4039 temp = simplify_unary_operation (NEG, mode,
4040 XEXP (XEXP (x, 0), 0), mode);
4043 SUBST (XEXP (XEXP (x, 0), 0), temp);
4048 temp = expand_compound_operation (XEXP (x, 0));
4050 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4051 replaced by (lshiftrt X C). This will convert
4052 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4054 if (GET_CODE (temp) == ASHIFTRT
4055 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4056 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4057 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4058 INTVAL (XEXP (temp, 1)));
4060 /* If X has only a single bit that might be nonzero, say, bit I, convert
4061 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4062 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4063 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4064 or a SUBREG of one since we'd be making the expression more
4065 complex if it was just a register. */
4067 if (GET_CODE (temp) != REG
4068 && ! (GET_CODE (temp) == SUBREG
4069 && GET_CODE (SUBREG_REG (temp)) == REG)
4070 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4072 rtx temp1 = simplify_shift_const
4073 (NULL_RTX, ASHIFTRT, mode,
4074 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4075 GET_MODE_BITSIZE (mode) - 1 - i),
4076 GET_MODE_BITSIZE (mode) - 1 - i);
4078 /* If all we did was surround TEMP with the two shifts, we
4079 haven't improved anything, so don't use it. Otherwise,
4080 we are better off with TEMP1. */
4081 if (GET_CODE (temp1) != ASHIFTRT
4082 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4083 || XEXP (XEXP (temp1, 0), 0) != temp)
4089 /* We can't handle truncation to a partial integer mode here
4090 because we don't know the real bitsize of the partial
4092 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4095 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4096 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4097 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4099 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4100 GET_MODE_MASK (mode), NULL_RTX, 0));
4102 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4103 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4104 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4105 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4106 return XEXP (XEXP (x, 0), 0);
4108 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4109 (OP:SI foo:SI) if OP is NEG or ABS. */
4110 if ((GET_CODE (XEXP (x, 0)) == ABS
4111 || GET_CODE (XEXP (x, 0)) == NEG)
4112 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4113 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4114 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4115 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4116 XEXP (XEXP (XEXP (x, 0), 0), 0));
4118 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4120 if (GET_CODE (XEXP (x, 0)) == SUBREG
4121 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4122 && subreg_lowpart_p (XEXP (x, 0)))
4123 return SUBREG_REG (XEXP (x, 0));
4125 /* If we know that the value is already truncated, we can
4126 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4127 is nonzero for the corresponding modes. But don't do this
4128 for an (LSHIFTRT (MULT ...)) since this will cause problems
4129 with the umulXi3_highpart patterns. */
4130 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4131 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4132 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4133 >= GET_MODE_BITSIZE (mode) + 1
4134 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4135 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4136 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4138 /* A truncate of a comparison can be replaced with a subreg if
4139 STORE_FLAG_VALUE permits. This is like the previous test,
4140 but it works even if the comparison is done in a mode larger
4141 than HOST_BITS_PER_WIDE_INT. */
4142 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4143 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4144 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4145 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4147 /* Similarly, a truncate of a register whose value is a
4148 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4150 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4151 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4152 && (temp = get_last_value (XEXP (x, 0)))
4153 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
4154 return gen_lowpart_for_combine (mode, XEXP (x, 0));
4158 case FLOAT_TRUNCATE:
4159 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4160 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4161 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4162 return XEXP (XEXP (x, 0), 0);
4164 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4165 (OP:SF foo:SF) if OP is NEG or ABS. */
4166 if ((GET_CODE (XEXP (x, 0)) == ABS
4167 || GET_CODE (XEXP (x, 0)) == NEG)
4168 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4169 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4170 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
4171 XEXP (XEXP (XEXP (x, 0), 0), 0));
4173 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4174 is (float_truncate:SF x). */
4175 if (GET_CODE (XEXP (x, 0)) == SUBREG
4176 && subreg_lowpart_p (XEXP (x, 0))
4177 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4178 return SUBREG_REG (XEXP (x, 0));
4183 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4184 using cc0, in which case we want to leave it as a COMPARE
4185 so we can distinguish it from a register-register-copy. */
4186 if (XEXP (x, 1) == const0_rtx)
4189 /* In IEEE floating point, x-0 is not the same as x. */
4190 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
4191 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
4192 || flag_unsafe_math_optimizations)
4193 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4199 /* (const (const X)) can become (const X). Do it this way rather than
4200 returning the inner CONST since CONST can be shared with a
4202 if (GET_CODE (XEXP (x, 0)) == CONST)
4203 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4208 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4209 can add in an offset. find_split_point will split this address up
4210 again if it doesn't match. */
4211 if (GET_CODE (XEXP (x, 0)) == HIGH
4212 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4218 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4219 outermost. That's because that's the way indexed addresses are
4220 supposed to appear. This code used to check many more cases, but
4221 they are now checked elsewhere. */
4222 if (GET_CODE (XEXP (x, 0)) == PLUS
4223 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4224 return gen_binary (PLUS, mode,
4225 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4227 XEXP (XEXP (x, 0), 1));
4229 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4230 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4231 bit-field and can be replaced by either a sign_extend or a
4232 sign_extract. The `and' may be a zero_extend and the two
4233 <c>, -<c> constants may be reversed. */
4234 if (GET_CODE (XEXP (x, 0)) == XOR
4235 && GET_CODE (XEXP (x, 1)) == CONST_INT
4236 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4237 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4238 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4239 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4240 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4241 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4242 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4243 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4244 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4245 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4246 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4247 == (unsigned int) i + 1))))
4248 return simplify_shift_const
4249 (NULL_RTX, ASHIFTRT, mode,
4250 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4251 XEXP (XEXP (XEXP (x, 0), 0), 0),
4252 GET_MODE_BITSIZE (mode) - (i + 1)),
4253 GET_MODE_BITSIZE (mode) - (i + 1));
4255 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4256 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4257 is 1. This produces better code than the alternative immediately
4259 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
4260 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4261 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4262 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4263 XEXP (XEXP (x, 0), 0),
4264 XEXP (XEXP (x, 0), 1))))
4266 gen_unary (NEG, mode, mode, reversed);
4268 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4269 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4270 the bitsize of the mode - 1. This allows simplification of
4271 "a = (b & 8) == 0;" */
4272 if (XEXP (x, 1) == constm1_rtx
4273 && GET_CODE (XEXP (x, 0)) != REG
4274 && ! (GET_CODE (XEXP (x,0)) == SUBREG
4275 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
4276 && nonzero_bits (XEXP (x, 0), mode) == 1)
4277 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4278 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4279 gen_rtx_combine (XOR, mode,
4280 XEXP (x, 0), const1_rtx),
4281 GET_MODE_BITSIZE (mode) - 1),
4282 GET_MODE_BITSIZE (mode) - 1);
4284 /* If we are adding two things that have no bits in common, convert
4285 the addition into an IOR. This will often be further simplified,
4286 for example in cases like ((a & 1) + (a & 2)), which can
4289 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4290 && (nonzero_bits (XEXP (x, 0), mode)
4291 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4293 /* Try to simplify the expression further. */
4294 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4295 temp = combine_simplify_rtx (tor, mode, last, in_dest);
4297 /* If we could, great. If not, do not go ahead with the IOR
4298 replacement, since PLUS appears in many special purpose
4299 address arithmetic instructions. */
4300 if (GET_CODE (temp) != CLOBBER && temp != tor)
4306 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4307 by reversing the comparison code if valid. */
4308 if (STORE_FLAG_VALUE == 1
4309 && XEXP (x, 0) == const1_rtx
4310 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
4311 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4312 XEXP (XEXP (x, 1), 0),
4313 XEXP (XEXP (x, 1), 1))))
4316 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4317 (and <foo> (const_int pow2-1)) */
4318 if (GET_CODE (XEXP (x, 1)) == AND
4319 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4320 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4321 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4322 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4323 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4325 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4327 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4328 return gen_binary (MINUS, mode,
4329 gen_binary (MINUS, mode, XEXP (x, 0),
4330 XEXP (XEXP (x, 1), 0)),
4331 XEXP (XEXP (x, 1), 1));
4335 /* If we have (mult (plus A B) C), apply the distributive law and then
4336 the inverse distributive law to see if things simplify. This
4337 occurs mostly in addresses, often when unrolling loops. */
4339 if (GET_CODE (XEXP (x, 0)) == PLUS)
4341 x = apply_distributive_law
4342 (gen_binary (PLUS, mode,
4343 gen_binary (MULT, mode,
4344 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4345 gen_binary (MULT, mode,
4346 XEXP (XEXP (x, 0), 1),
4347 copy_rtx (XEXP (x, 1)))));
4349 if (GET_CODE (x) != MULT)
4355 /* If this is a divide by a power of two, treat it as a shift if
4356 its first operand is a shift. */
4357 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4358 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4359 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4360 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4361 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4362 || GET_CODE (XEXP (x, 0)) == ROTATE
4363 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4364 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4368 case GT: case GTU: case GE: case GEU:
4369 case LT: case LTU: case LE: case LEU:
4370 case UNEQ: case LTGT:
4371 case UNGT: case UNGE:
4372 case UNLT: case UNLE:
4373 case UNORDERED: case ORDERED:
4374 /* If the first operand is a condition code, we can't do anything
4376 if (GET_CODE (XEXP (x, 0)) == COMPARE
4377 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4379 && XEXP (x, 0) != cc0_rtx
4383 rtx op0 = XEXP (x, 0);
4384 rtx op1 = XEXP (x, 1);
4385 enum rtx_code new_code;
4387 if (GET_CODE (op0) == COMPARE)
4388 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4390 /* Simplify our comparison, if possible. */
4391 new_code = simplify_comparison (code, &op0, &op1);
4393 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4394 if only the low-order bit is possibly nonzero in X (such as when
4395 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4396 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4397 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4400 Remove any ZERO_EXTRACT we made when thinking this was a
4401 comparison. It may now be simpler to use, e.g., an AND. If a
4402 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4403 the call to make_compound_operation in the SET case. */
4405 if (STORE_FLAG_VALUE == 1
4406 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4407 && op1 == const0_rtx
4408 && mode == GET_MODE (op0)
4409 && nonzero_bits (op0, mode) == 1)
4410 return gen_lowpart_for_combine (mode,
4411 expand_compound_operation (op0));
4413 else if (STORE_FLAG_VALUE == 1
4414 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4415 && op1 == const0_rtx
4416 && mode == GET_MODE (op0)
4417 && (num_sign_bit_copies (op0, mode)
4418 == GET_MODE_BITSIZE (mode)))
4420 op0 = expand_compound_operation (op0);
4421 return gen_unary (NEG, mode, mode,
4422 gen_lowpart_for_combine (mode, op0));
4425 else if (STORE_FLAG_VALUE == 1
4426 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4427 && op1 == const0_rtx
4428 && mode == GET_MODE (op0)
4429 && nonzero_bits (op0, mode) == 1)
4431 op0 = expand_compound_operation (op0);
4432 return gen_binary (XOR, mode,
4433 gen_lowpart_for_combine (mode, op0),
4437 else if (STORE_FLAG_VALUE == 1
4438 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4439 && op1 == const0_rtx
4440 && mode == GET_MODE (op0)
4441 && (num_sign_bit_copies (op0, mode)
4442 == GET_MODE_BITSIZE (mode)))
4444 op0 = expand_compound_operation (op0);
4445 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4448 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4450 if (STORE_FLAG_VALUE == -1
4451 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4452 && op1 == const0_rtx
4453 && (num_sign_bit_copies (op0, mode)
4454 == GET_MODE_BITSIZE (mode)))
4455 return gen_lowpart_for_combine (mode,
4456 expand_compound_operation (op0));
4458 else if (STORE_FLAG_VALUE == -1
4459 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4460 && op1 == const0_rtx
4461 && mode == GET_MODE (op0)
4462 && nonzero_bits (op0, mode) == 1)
4464 op0 = expand_compound_operation (op0);
4465 return gen_unary (NEG, mode, mode,
4466 gen_lowpart_for_combine (mode, op0));
4469 else if (STORE_FLAG_VALUE == -1
4470 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4471 && op1 == const0_rtx
4472 && mode == GET_MODE (op0)
4473 && (num_sign_bit_copies (op0, mode)
4474 == GET_MODE_BITSIZE (mode)))
4476 op0 = expand_compound_operation (op0);
4477 return gen_unary (NOT, mode, mode,
4478 gen_lowpart_for_combine (mode, op0));
4481 /* If X is 0/1, (eq X 0) is X-1. */
4482 else if (STORE_FLAG_VALUE == -1
4483 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4484 && op1 == const0_rtx
4485 && mode == GET_MODE (op0)
4486 && nonzero_bits (op0, mode) == 1)
4488 op0 = expand_compound_operation (op0);
4489 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4492 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4493 one bit that might be nonzero, we can convert (ne x 0) to
4494 (ashift x c) where C puts the bit in the sign bit. Remove any
4495 AND with STORE_FLAG_VALUE when we are done, since we are only
4496 going to test the sign bit. */
4497 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4498 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4499 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4500 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4501 && op1 == const0_rtx
4502 && mode == GET_MODE (op0)
4503 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4505 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4506 expand_compound_operation (op0),
4507 GET_MODE_BITSIZE (mode) - 1 - i);
4508 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4514 /* If the code changed, return a whole new comparison. */
4515 if (new_code != code)
4516 return gen_rtx_combine (new_code, mode, op0, op1);
4518 /* Otherwise, keep this operation, but maybe change its operands.
4519 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4520 SUBST (XEXP (x, 0), op0);
4521 SUBST (XEXP (x, 1), op1);
4526 return simplify_if_then_else (x);
4532 /* If we are processing SET_DEST, we are done. */
4536 return expand_compound_operation (x);
4539 return simplify_set (x);
4544 return simplify_logical (x, last);
4547 /* (abs (neg <foo>)) -> (abs <foo>) */
4548 if (GET_CODE (XEXP (x, 0)) == NEG)
4549 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4551 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4553 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4556 /* If operand is something known to be positive, ignore the ABS. */
4557 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4558 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4559 <= HOST_BITS_PER_WIDE_INT)
4560 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4561 & ((HOST_WIDE_INT) 1
4562 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4566 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4567 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4568 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4573 /* (ffs (*_extend <X>)) = (ffs <X>) */
4574 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4575 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4576 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4580 /* (float (sign_extend <X>)) = (float <X>). */
4581 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4582 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4590 /* If this is a shift by a constant amount, simplify it. */
4591 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4592 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4593 INTVAL (XEXP (x, 1)));
4595 #ifdef SHIFT_COUNT_TRUNCATED
4596 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4598 force_to_mode (XEXP (x, 1), GET_MODE (x),
4600 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4609 rtx op0 = XEXP (x, 0);
4610 rtx op1 = XEXP (x, 1);
4613 if (GET_CODE (op1) != PARALLEL)
4615 len = XVECLEN (op1, 0);
4617 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4618 && GET_CODE (op0) == VEC_CONCAT)
4620 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4622 /* Try to find the element in the VEC_CONCAT. */
4625 if (GET_MODE (op0) == GET_MODE (x))
4627 if (GET_CODE (op0) == VEC_CONCAT)
4629 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4630 if (op0_size < offset)
4631 op0 = XEXP (op0, 0);
4635 op0 = XEXP (op0, 1);
4653 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4656 simplify_if_then_else (x)
4659 enum machine_mode mode = GET_MODE (x);
4660 rtx cond = XEXP (x, 0);
4661 rtx true_rtx = XEXP (x, 1);
4662 rtx false_rtx = XEXP (x, 2);
4663 enum rtx_code true_code = GET_CODE (cond);
4664 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4667 enum rtx_code false_code;
4670 /* Simplify storing of the truth value. */
4671 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4672 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4674 /* Also when the truth value has to be reversed. */
4676 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4677 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4681 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4682 in it is being compared against certain values. Get the true and false
4683 comparisons and see if that says anything about the value of each arm. */
4686 && ((false_code = combine_reversed_comparison_code (cond))
4688 && GET_CODE (XEXP (cond, 0)) == REG)
4691 rtx from = XEXP (cond, 0);
4692 rtx true_val = XEXP (cond, 1);
4693 rtx false_val = true_val;
4696 /* If FALSE_CODE is EQ, swap the codes and arms. */
4698 if (false_code == EQ)
4700 swapped = 1, true_code = EQ, false_code = NE;
4701 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4704 /* If we are comparing against zero and the expression being tested has
4705 only a single bit that might be nonzero, that is its value when it is
4706 not equal to zero. Similarly if it is known to be -1 or 0. */
4708 if (true_code == EQ && true_val == const0_rtx
4709 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4710 false_code = EQ, false_val = GEN_INT (nzb);
4711 else if (true_code == EQ && true_val == const0_rtx
4712 && (num_sign_bit_copies (from, GET_MODE (from))
4713 == GET_MODE_BITSIZE (GET_MODE (from))))
4714 false_code = EQ, false_val = constm1_rtx;
4716 /* Now simplify an arm if we know the value of the register in the
4717 branch and it is used in the arm. Be careful due to the potential
4718 of locally-shared RTL. */
4720 if (reg_mentioned_p (from, true_rtx))
4721 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4723 pc_rtx, pc_rtx, 0, 0);
4724 if (reg_mentioned_p (from, false_rtx))
4725 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4727 pc_rtx, pc_rtx, 0, 0);
4729 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4730 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4732 true_rtx = XEXP (x, 1);
4733 false_rtx = XEXP (x, 2);
4734 true_code = GET_CODE (cond);
4737 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4738 reversed, do so to avoid needing two sets of patterns for
4739 subtract-and-branch insns. Similarly if we have a constant in the true
4740 arm, the false arm is the same as the first operand of the comparison, or
4741 the false arm is more complicated than the true arm. */
4744 && combine_reversed_comparison_code (cond) != UNKNOWN
4745 && (true_rtx == pc_rtx
4746 || (CONSTANT_P (true_rtx)
4747 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4748 || true_rtx == const0_rtx
4749 || (GET_RTX_CLASS (GET_CODE (true_rtx)) == 'o'
4750 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4751 || (GET_CODE (true_rtx) == SUBREG
4752 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true_rtx))) == 'o'
4753 && GET_RTX_CLASS (GET_CODE (false_rtx)) != 'o')
4754 || reg_mentioned_p (true_rtx, false_rtx)
4755 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4757 true_code = reversed_comparison_code (cond, NULL);
4759 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4762 SUBST (XEXP (x, 1), false_rtx);
4763 SUBST (XEXP (x, 2), true_rtx);
4765 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4768 /* It is possible that the conditional has been simplified out. */
4769 true_code = GET_CODE (cond);
4770 comparison_p = GET_RTX_CLASS (true_code) == '<';
4773 /* If the two arms are identical, we don't need the comparison. */
4775 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4778 /* Convert a == b ? b : a to "a". */
4779 if (true_code == EQ && ! side_effects_p (cond)
4780 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4781 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4782 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4784 else if (true_code == NE && ! side_effects_p (cond)
4785 && (! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4786 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4787 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4790 /* Look for cases where we have (abs x) or (neg (abs X)). */
4792 if (GET_MODE_CLASS (mode) == MODE_INT
4793 && GET_CODE (false_rtx) == NEG
4794 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4796 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4797 && ! side_effects_p (true_rtx))
4802 return gen_unary (ABS, mode, mode, true_rtx);
4805 return gen_unary (NEG, mode, mode,
4806 gen_unary (ABS, mode, mode, true_rtx));
4811 /* Look for MIN or MAX. */
4813 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4815 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4816 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4817 && ! side_effects_p (cond))
4822 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4825 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4828 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4831 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4836 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4837 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4838 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4839 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4840 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4841 neither 1 or -1, but it isn't worth checking for. */
4843 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4844 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4846 rtx t = make_compound_operation (true_rtx, SET);
4847 rtx f = make_compound_operation (false_rtx, SET);
4848 rtx cond_op0 = XEXP (cond, 0);
4849 rtx cond_op1 = XEXP (cond, 1);
4850 enum rtx_code op = NIL, extend_op = NIL;
4851 enum machine_mode m = mode;
4852 rtx z = 0, c1 = NULL_RTX;
4854 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4855 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4856 || GET_CODE (t) == ASHIFT
4857 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4858 && rtx_equal_p (XEXP (t, 0), f))
4859 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4861 /* If an identity-zero op is commutative, check whether there
4862 would be a match if we swapped the operands. */
4863 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4864 || GET_CODE (t) == XOR)
4865 && rtx_equal_p (XEXP (t, 1), f))
4866 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4867 else if (GET_CODE (t) == SIGN_EXTEND
4868 && (GET_CODE (XEXP (t, 0)) == PLUS
4869 || GET_CODE (XEXP (t, 0)) == MINUS
4870 || GET_CODE (XEXP (t, 0)) == IOR
4871 || GET_CODE (XEXP (t, 0)) == XOR
4872 || GET_CODE (XEXP (t, 0)) == ASHIFT
4873 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4874 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4875 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4876 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4877 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4878 && (num_sign_bit_copies (f, GET_MODE (f))
4879 > (GET_MODE_BITSIZE (mode)
4880 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4882 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4883 extend_op = SIGN_EXTEND;
4884 m = GET_MODE (XEXP (t, 0));
4886 else if (GET_CODE (t) == SIGN_EXTEND
4887 && (GET_CODE (XEXP (t, 0)) == PLUS
4888 || GET_CODE (XEXP (t, 0)) == IOR
4889 || GET_CODE (XEXP (t, 0)) == XOR)
4890 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4891 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4892 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4893 && (num_sign_bit_copies (f, GET_MODE (f))
4894 > (GET_MODE_BITSIZE (mode)
4895 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4897 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4898 extend_op = SIGN_EXTEND;
4899 m = GET_MODE (XEXP (t, 0));
4901 else if (GET_CODE (t) == ZERO_EXTEND
4902 && (GET_CODE (XEXP (t, 0)) == PLUS
4903 || GET_CODE (XEXP (t, 0)) == MINUS
4904 || GET_CODE (XEXP (t, 0)) == IOR
4905 || GET_CODE (XEXP (t, 0)) == XOR
4906 || GET_CODE (XEXP (t, 0)) == ASHIFT
4907 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4908 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4909 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4910 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4911 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4912 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4913 && ((nonzero_bits (f, GET_MODE (f))
4914 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4917 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4918 extend_op = ZERO_EXTEND;
4919 m = GET_MODE (XEXP (t, 0));
4921 else if (GET_CODE (t) == ZERO_EXTEND
4922 && (GET_CODE (XEXP (t, 0)) == PLUS
4923 || GET_CODE (XEXP (t, 0)) == IOR
4924 || GET_CODE (XEXP (t, 0)) == XOR)
4925 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4926 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4927 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4928 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4929 && ((nonzero_bits (f, GET_MODE (f))
4930 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4933 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4934 extend_op = ZERO_EXTEND;
4935 m = GET_MODE (XEXP (t, 0));
4940 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4941 pc_rtx, pc_rtx, 0, 0);
4942 temp = gen_binary (MULT, m, temp,
4943 gen_binary (MULT, m, c1, const_true_rtx));
4944 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4945 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4947 if (extend_op != NIL)
4948 temp = gen_unary (extend_op, mode, m, temp);
4954 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4955 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4956 negation of a single bit, we can convert this operation to a shift. We
4957 can actually do this more generally, but it doesn't seem worth it. */
4959 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4960 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4961 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4962 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4963 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4964 == GET_MODE_BITSIZE (mode))
4965 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4967 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4968 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4973 /* Simplify X, a SET expression. Return the new expression. */
4979 rtx src = SET_SRC (x);
4980 rtx dest = SET_DEST (x);
4981 enum machine_mode mode
4982 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4986 /* (set (pc) (return)) gets written as (return). */
4987 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4990 /* Now that we know for sure which bits of SRC we are using, see if we can
4991 simplify the expression for the object knowing that we only need the
4994 if (GET_MODE_CLASS (mode) == MODE_INT)
4996 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
4997 SUBST (SET_SRC (x), src);
5000 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5001 the comparison result and try to simplify it unless we already have used
5002 undobuf.other_insn. */
5003 if ((GET_CODE (src) == COMPARE
5008 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5009 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5010 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
5011 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5013 enum rtx_code old_code = GET_CODE (*cc_use);
5014 enum rtx_code new_code;
5016 int other_changed = 0;
5017 enum machine_mode compare_mode = GET_MODE (dest);
5019 if (GET_CODE (src) == COMPARE)
5020 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5022 op0 = src, op1 = const0_rtx;
5024 /* Simplify our comparison, if possible. */
5025 new_code = simplify_comparison (old_code, &op0, &op1);
5027 #ifdef EXTRA_CC_MODES
5028 /* If this machine has CC modes other than CCmode, check to see if we
5029 need to use a different CC mode here. */
5030 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5031 #endif /* EXTRA_CC_MODES */
5033 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
5034 /* If the mode changed, we have to change SET_DEST, the mode in the
5035 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5036 a hard register, just build new versions with the proper mode. If it
5037 is a pseudo, we lose unless it is only time we set the pseudo, in
5038 which case we can safely change its mode. */
5039 if (compare_mode != GET_MODE (dest))
5041 unsigned int regno = REGNO (dest);
5042 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5044 if (regno < FIRST_PSEUDO_REGISTER
5045 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5047 if (regno >= FIRST_PSEUDO_REGISTER)
5048 SUBST (regno_reg_rtx[regno], new_dest);
5050 SUBST (SET_DEST (x), new_dest);
5051 SUBST (XEXP (*cc_use, 0), new_dest);
5059 /* If the code changed, we have to build a new comparison in
5060 undobuf.other_insn. */
5061 if (new_code != old_code)
5063 unsigned HOST_WIDE_INT mask;
5065 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
5068 /* If the only change we made was to change an EQ into an NE or
5069 vice versa, OP0 has only one bit that might be nonzero, and OP1
5070 is zero, check if changing the user of the condition code will
5071 produce a valid insn. If it won't, we can keep the original code
5072 in that insn by surrounding our operation with an XOR. */
5074 if (((old_code == NE && new_code == EQ)
5075 || (old_code == EQ && new_code == NE))
5076 && ! other_changed && op1 == const0_rtx
5077 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5078 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5080 rtx pat = PATTERN (other_insn), note = 0;
5082 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5083 && ! check_asm_operands (pat)))
5085 PUT_CODE (*cc_use, old_code);
5088 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5096 undobuf.other_insn = other_insn;
5099 /* If we are now comparing against zero, change our source if
5100 needed. If we do not use cc0, we always have a COMPARE. */
5101 if (op1 == const0_rtx && dest == cc0_rtx)
5103 SUBST (SET_SRC (x), op0);
5109 /* Otherwise, if we didn't previously have a COMPARE in the
5110 correct mode, we need one. */
5111 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5114 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
5119 /* Otherwise, update the COMPARE if needed. */
5120 SUBST (XEXP (src, 0), op0);
5121 SUBST (XEXP (src, 1), op1);
5126 /* Get SET_SRC in a form where we have placed back any
5127 compound expressions. Then do the checks below. */
5128 src = make_compound_operation (src, SET);
5129 SUBST (SET_SRC (x), src);
5132 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5133 and X being a REG or (subreg (reg)), we may be able to convert this to
5134 (set (subreg:m2 x) (op)).
5136 We can always do this if M1 is narrower than M2 because that means that
5137 we only care about the low bits of the result.
5139 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5140 perform a narrower operation than requested since the high-order bits will
5141 be undefined. On machine where it is defined, this transformation is safe
5142 as long as M1 and M2 have the same number of words. */
5144 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5145 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
5146 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5148 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5149 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5150 #ifndef WORD_REGISTER_OPERATIONS
5151 && (GET_MODE_SIZE (GET_MODE (src))
5152 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5154 #ifdef CLASS_CANNOT_CHANGE_MODE
5155 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
5156 && (TEST_HARD_REG_BIT
5157 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE],
5159 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (src),
5160 GET_MODE (SUBREG_REG (src))))
5162 && (GET_CODE (dest) == REG
5163 || (GET_CODE (dest) == SUBREG
5164 && GET_CODE (SUBREG_REG (dest)) == REG)))
5166 SUBST (SET_DEST (x),
5167 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
5169 SUBST (SET_SRC (x), SUBREG_REG (src));
5171 src = SET_SRC (x), dest = SET_DEST (x);
5174 #ifdef LOAD_EXTEND_OP
5175 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5176 would require a paradoxical subreg. Replace the subreg with a
5177 zero_extend to avoid the reload that would otherwise be required. */
5179 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5180 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
5181 && SUBREG_WORD (src) == 0
5182 && (GET_MODE_SIZE (GET_MODE (src))
5183 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5184 && GET_CODE (SUBREG_REG (src)) == MEM)
5187 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5188 GET_MODE (src), XEXP (src, 0)));
5194 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5195 are comparing an item known to be 0 or -1 against 0, use a logical
5196 operation instead. Check for one of the arms being an IOR of the other
5197 arm with some value. We compute three terms to be IOR'ed together. In
5198 practice, at most two will be nonzero. Then we do the IOR's. */
5200 if (GET_CODE (dest) != PC
5201 && GET_CODE (src) == IF_THEN_ELSE
5202 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5203 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5204 && XEXP (XEXP (src, 0), 1) == const0_rtx
5205 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5206 #ifdef HAVE_conditional_move
5207 && ! can_conditionally_move_p (GET_MODE (src))
5209 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5210 GET_MODE (XEXP (XEXP (src, 0), 0)))
5211 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5212 && ! side_effects_p (src))
5214 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5215 ? XEXP (src, 1) : XEXP (src, 2));
5216 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5217 ? XEXP (src, 2) : XEXP (src, 1));
5218 rtx term1 = const0_rtx, term2, term3;
5220 if (GET_CODE (true_rtx) == IOR
5221 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5222 term1 = false_rtx, true_rtx = XEXP(true_rtx, 1), false_rtx = const0_rtx;
5223 else if (GET_CODE (true_rtx) == IOR
5224 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5225 term1 = false_rtx, true_rtx = XEXP(true_rtx, 0), false_rtx = const0_rtx;
5226 else if (GET_CODE (false_rtx) == IOR
5227 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5228 term1 = true_rtx, false_rtx = XEXP(false_rtx, 1), true_rtx = const0_rtx;
5229 else if (GET_CODE (false_rtx) == IOR
5230 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5231 term1 = true_rtx, false_rtx = XEXP(false_rtx, 0), true_rtx = const0_rtx;
5233 term2 = gen_binary (AND, GET_MODE (src),
5234 XEXP (XEXP (src, 0), 0), true_rtx);
5235 term3 = gen_binary (AND, GET_MODE (src),
5236 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
5237 XEXP (XEXP (src, 0), 0)),
5241 gen_binary (IOR, GET_MODE (src),
5242 gen_binary (IOR, GET_MODE (src), term1, term2),
5248 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5249 whole thing fail. */
5250 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5252 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5255 /* Convert this into a field assignment operation, if possible. */
5256 return make_field_assignment (x);
5259 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5260 result. LAST is nonzero if this is the last retry. */
5263 simplify_logical (x, last)
5267 enum machine_mode mode = GET_MODE (x);
5268 rtx op0 = XEXP (x, 0);
5269 rtx op1 = XEXP (x, 1);
5272 switch (GET_CODE (x))
5275 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5276 insn (and may simplify more). */
5277 if (GET_CODE (op0) == XOR
5278 && rtx_equal_p (XEXP (op0, 0), op1)
5279 && ! side_effects_p (op1))
5280 x = gen_binary (AND, mode,
5281 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
5283 if (GET_CODE (op0) == XOR
5284 && rtx_equal_p (XEXP (op0, 1), op1)
5285 && ! side_effects_p (op1))
5286 x = gen_binary (AND, mode,
5287 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
5289 /* Similarly for (~(A ^ B)) & A. */
5290 if (GET_CODE (op0) == NOT
5291 && GET_CODE (XEXP (op0, 0)) == XOR
5292 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5293 && ! side_effects_p (op1))
5294 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5296 if (GET_CODE (op0) == NOT
5297 && GET_CODE (XEXP (op0, 0)) == XOR
5298 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5299 && ! side_effects_p (op1))
5300 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5302 /* We can call simplify_and_const_int only if we don't lose
5303 any (sign) bits when converting INTVAL (op1) to
5304 "unsigned HOST_WIDE_INT". */
5305 if (GET_CODE (op1) == CONST_INT
5306 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5307 || INTVAL (op1) > 0))
5309 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5311 /* If we have (ior (and (X C1) C2)) and the next restart would be
5312 the last, simplify this by making C1 as small as possible
5315 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
5316 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5317 && GET_CODE (op1) == CONST_INT)
5318 return gen_binary (IOR, mode,
5319 gen_binary (AND, mode, XEXP (op0, 0),
5320 GEN_INT (INTVAL (XEXP (op0, 1))
5321 & ~INTVAL (op1))), op1);
5323 if (GET_CODE (x) != AND)
5326 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
5327 || GET_RTX_CLASS (GET_CODE (x)) == '2')
5328 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5331 /* Convert (A | B) & A to A. */
5332 if (GET_CODE (op0) == IOR
5333 && (rtx_equal_p (XEXP (op0, 0), op1)
5334 || rtx_equal_p (XEXP (op0, 1), op1))
5335 && ! side_effects_p (XEXP (op0, 0))
5336 && ! side_effects_p (XEXP (op0, 1)))
5339 /* In the following group of tests (and those in case IOR below),
5340 we start with some combination of logical operations and apply
5341 the distributive law followed by the inverse distributive law.
5342 Most of the time, this results in no change. However, if some of
5343 the operands are the same or inverses of each other, simplifications
5346 For example, (and (ior A B) (not B)) can occur as the result of
5347 expanding a bit field assignment. When we apply the distributive
5348 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5349 which then simplifies to (and (A (not B))).
5351 If we have (and (ior A B) C), apply the distributive law and then
5352 the inverse distributive law to see if things simplify. */
5354 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5356 x = apply_distributive_law
5357 (gen_binary (GET_CODE (op0), mode,
5358 gen_binary (AND, mode, XEXP (op0, 0), op1),
5359 gen_binary (AND, mode, XEXP (op0, 1),
5361 if (GET_CODE (x) != AND)
5365 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5366 return apply_distributive_law
5367 (gen_binary (GET_CODE (op1), mode,
5368 gen_binary (AND, mode, XEXP (op1, 0), op0),
5369 gen_binary (AND, mode, XEXP (op1, 1),
5372 /* Similarly, taking advantage of the fact that
5373 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5375 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5376 return apply_distributive_law
5377 (gen_binary (XOR, mode,
5378 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5379 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5382 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5383 return apply_distributive_law
5384 (gen_binary (XOR, mode,
5385 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5386 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5390 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5391 if (GET_CODE (op1) == CONST_INT
5392 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5393 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5396 /* Convert (A & B) | A to A. */
5397 if (GET_CODE (op0) == AND
5398 && (rtx_equal_p (XEXP (op0, 0), op1)
5399 || rtx_equal_p (XEXP (op0, 1), op1))
5400 && ! side_effects_p (XEXP (op0, 0))
5401 && ! side_effects_p (XEXP (op0, 1)))
5404 /* If we have (ior (and A B) C), apply the distributive law and then
5405 the inverse distributive law to see if things simplify. */
5407 if (GET_CODE (op0) == AND)
5409 x = apply_distributive_law
5410 (gen_binary (AND, mode,
5411 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5412 gen_binary (IOR, mode, XEXP (op0, 1),
5415 if (GET_CODE (x) != IOR)
5419 if (GET_CODE (op1) == AND)
5421 x = apply_distributive_law
5422 (gen_binary (AND, mode,
5423 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5424 gen_binary (IOR, mode, XEXP (op1, 1),
5427 if (GET_CODE (x) != IOR)
5431 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5432 mode size to (rotate A CX). */
5434 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5435 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5436 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5437 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5438 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5439 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5440 == GET_MODE_BITSIZE (mode)))
5441 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5442 (GET_CODE (op0) == ASHIFT
5443 ? XEXP (op0, 1) : XEXP (op1, 1)));
5445 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5446 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5447 does not affect any of the bits in OP1, it can really be done
5448 as a PLUS and we can associate. We do this by seeing if OP1
5449 can be safely shifted left C bits. */
5450 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5451 && GET_CODE (XEXP (op0, 0)) == PLUS
5452 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5453 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5454 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5456 int count = INTVAL (XEXP (op0, 1));
5457 HOST_WIDE_INT mask = INTVAL (op1) << count;
5459 if (mask >> count == INTVAL (op1)
5460 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5462 SUBST (XEXP (XEXP (op0, 0), 1),
5463 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5470 /* If we are XORing two things that have no bits in common,
5471 convert them into an IOR. This helps to detect rotation encoded
5472 using those methods and possibly other simplifications. */
5474 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5475 && (nonzero_bits (op0, mode)
5476 & nonzero_bits (op1, mode)) == 0)
5477 return (gen_binary (IOR, mode, op0, op1));
5479 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5480 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5483 int num_negated = 0;
5485 if (GET_CODE (op0) == NOT)
5486 num_negated++, op0 = XEXP (op0, 0);
5487 if (GET_CODE (op1) == NOT)
5488 num_negated++, op1 = XEXP (op1, 0);
5490 if (num_negated == 2)
5492 SUBST (XEXP (x, 0), op0);
5493 SUBST (XEXP (x, 1), op1);
5495 else if (num_negated == 1)
5496 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5499 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5500 correspond to a machine insn or result in further simplifications
5501 if B is a constant. */
5503 if (GET_CODE (op0) == AND
5504 && rtx_equal_p (XEXP (op0, 1), op1)
5505 && ! side_effects_p (op1))
5506 return gen_binary (AND, mode,
5507 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5510 else if (GET_CODE (op0) == AND
5511 && rtx_equal_p (XEXP (op0, 0), op1)
5512 && ! side_effects_p (op1))
5513 return gen_binary (AND, mode,
5514 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5517 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5518 comparison if STORE_FLAG_VALUE is 1. */
5519 if (STORE_FLAG_VALUE == 1
5520 && op1 == const1_rtx
5521 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5522 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5526 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5527 is (lt foo (const_int 0)), so we can perform the above
5528 simplification if STORE_FLAG_VALUE is 1. */
5530 if (STORE_FLAG_VALUE == 1
5531 && op1 == const1_rtx
5532 && GET_CODE (op0) == LSHIFTRT
5533 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5534 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5535 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5537 /* (xor (comparison foo bar) (const_int sign-bit))
5538 when STORE_FLAG_VALUE is the sign bit. */
5539 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5540 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5541 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5542 && op1 == const_true_rtx
5543 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5544 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5557 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5558 operations" because they can be replaced with two more basic operations.
5559 ZERO_EXTEND is also considered "compound" because it can be replaced with
5560 an AND operation, which is simpler, though only one operation.
5562 The function expand_compound_operation is called with an rtx expression
5563 and will convert it to the appropriate shifts and AND operations,
5564 simplifying at each stage.
5566 The function make_compound_operation is called to convert an expression
5567 consisting of shifts and ANDs into the equivalent compound expression.
5568 It is the inverse of this function, loosely speaking. */
5571 expand_compound_operation (x)
5574 unsigned HOST_WIDE_INT pos = 0, len;
5576 unsigned int modewidth;
5579 switch (GET_CODE (x))
5584 /* We can't necessarily use a const_int for a multiword mode;
5585 it depends on implicitly extending the value.
5586 Since we don't know the right way to extend it,
5587 we can't tell whether the implicit way is right.
5589 Even for a mode that is no wider than a const_int,
5590 we can't win, because we need to sign extend one of its bits through
5591 the rest of it, and we don't know which bit. */
5592 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5595 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5596 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5597 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5598 reloaded. If not for that, MEM's would very rarely be safe.
5600 Reject MODEs bigger than a word, because we might not be able
5601 to reference a two-register group starting with an arbitrary register
5602 (and currently gen_lowpart might crash for a SUBREG). */
5604 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5607 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5608 /* If the inner object has VOIDmode (the only way this can happen
5609 is if it is a ASM_OPERANDS), we can't do anything since we don't
5610 know how much masking to do. */
5619 /* If the operand is a CLOBBER, just return it. */
5620 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5623 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5624 || GET_CODE (XEXP (x, 2)) != CONST_INT
5625 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5628 len = INTVAL (XEXP (x, 1));
5629 pos = INTVAL (XEXP (x, 2));
5631 /* If this goes outside the object being extracted, replace the object
5632 with a (use (mem ...)) construct that only combine understands
5633 and is used only for this purpose. */
5634 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5635 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5637 if (BITS_BIG_ENDIAN)
5638 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5645 /* Convert sign extension to zero extension, if we know that the high
5646 bit is not set, as this is easier to optimize. It will be converted
5647 back to cheaper alternative in make_extraction. */
5648 if (GET_CODE (x) == SIGN_EXTEND
5649 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5650 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5651 & ~(((unsigned HOST_WIDE_INT)
5652 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5656 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5657 return expand_compound_operation (temp);
5660 /* We can optimize some special cases of ZERO_EXTEND. */
5661 if (GET_CODE (x) == ZERO_EXTEND)
5663 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5664 know that the last value didn't have any inappropriate bits
5666 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5667 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5668 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5669 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5670 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5671 return XEXP (XEXP (x, 0), 0);
5673 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5674 if (GET_CODE (XEXP (x, 0)) == SUBREG
5675 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5676 && subreg_lowpart_p (XEXP (x, 0))
5677 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5678 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5679 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5680 return SUBREG_REG (XEXP (x, 0));
5682 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5683 is a comparison and STORE_FLAG_VALUE permits. This is like
5684 the first case, but it works even when GET_MODE (x) is larger
5685 than HOST_WIDE_INT. */
5686 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5687 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5688 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5689 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5690 <= HOST_BITS_PER_WIDE_INT)
5691 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5692 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5693 return XEXP (XEXP (x, 0), 0);
5695 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5696 if (GET_CODE (XEXP (x, 0)) == SUBREG
5697 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5698 && subreg_lowpart_p (XEXP (x, 0))
5699 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5700 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5701 <= HOST_BITS_PER_WIDE_INT)
5702 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5703 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5704 return SUBREG_REG (XEXP (x, 0));
5708 /* If we reach here, we want to return a pair of shifts. The inner
5709 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5710 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5711 logical depending on the value of UNSIGNEDP.
5713 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5714 converted into an AND of a shift.
5716 We must check for the case where the left shift would have a negative
5717 count. This can happen in a case like (x >> 31) & 255 on machines
5718 that can't shift by a constant. On those machines, we would first
5719 combine the shift with the AND to produce a variable-position
5720 extraction. Then the constant of 31 would be substituted in to produce
5721 a such a position. */
5723 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5724 if (modewidth + len >= pos)
5725 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5727 simplify_shift_const (NULL_RTX, ASHIFT,
5730 modewidth - pos - len),
5733 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5734 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5735 simplify_shift_const (NULL_RTX, LSHIFTRT,
5738 ((HOST_WIDE_INT) 1 << len) - 1);
5740 /* Any other cases we can't handle. */
5743 /* If we couldn't do this for some reason, return the original
5745 if (GET_CODE (tem) == CLOBBER)
5751 /* X is a SET which contains an assignment of one object into
5752 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5753 or certain SUBREGS). If possible, convert it into a series of
5756 We half-heartedly support variable positions, but do not at all
5757 support variable lengths. */
5760 expand_field_assignment (x)
5764 rtx pos; /* Always counts from low bit. */
5767 enum machine_mode compute_mode;
5769 /* Loop until we find something we can't simplify. */
5772 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5773 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5775 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5776 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5777 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5779 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5780 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5782 inner = XEXP (SET_DEST (x), 0);
5783 len = INTVAL (XEXP (SET_DEST (x), 1));
5784 pos = XEXP (SET_DEST (x), 2);
5786 /* If the position is constant and spans the width of INNER,
5787 surround INNER with a USE to indicate this. */
5788 if (GET_CODE (pos) == CONST_INT
5789 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5790 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5792 if (BITS_BIG_ENDIAN)
5794 if (GET_CODE (pos) == CONST_INT)
5795 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5797 else if (GET_CODE (pos) == MINUS
5798 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5799 && (INTVAL (XEXP (pos, 1))
5800 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5801 /* If position is ADJUST - X, new position is X. */
5802 pos = XEXP (pos, 0);
5804 pos = gen_binary (MINUS, GET_MODE (pos),
5805 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5811 /* A SUBREG between two modes that occupy the same numbers of words
5812 can be done by moving the SUBREG to the source. */
5813 else if (GET_CODE (SET_DEST (x)) == SUBREG
5814 /* We need SUBREGs to compute nonzero_bits properly. */
5815 && nonzero_sign_valid
5816 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5817 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5818 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5819 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5821 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5822 gen_lowpart_for_combine
5823 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5830 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5831 inner = SUBREG_REG (inner);
5833 compute_mode = GET_MODE (inner);
5835 /* Don't attempt bitwise arithmetic on non-integral modes. */
5836 if (! INTEGRAL_MODE_P (compute_mode))
5838 enum machine_mode imode;
5840 /* Something is probably seriously wrong if this matches. */
5841 if (! FLOAT_MODE_P (compute_mode))
5844 /* Try to find an integral mode to pun with. */
5845 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5846 if (imode == BLKmode)
5849 compute_mode = imode;
5850 inner = gen_lowpart_for_combine (imode, inner);
5853 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5854 if (len < HOST_BITS_PER_WIDE_INT)
5855 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5859 /* Now compute the equivalent expression. Make a copy of INNER
5860 for the SET_DEST in case it is a MEM into which we will substitute;
5861 we don't want shared RTL in that case. */
5863 (VOIDmode, copy_rtx (inner),
5864 gen_binary (IOR, compute_mode,
5865 gen_binary (AND, compute_mode,
5866 gen_unary (NOT, compute_mode,
5872 gen_binary (ASHIFT, compute_mode,
5873 gen_binary (AND, compute_mode,
5874 gen_lowpart_for_combine
5875 (compute_mode, SET_SRC (x)),
5883 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5884 it is an RTX that represents a variable starting position; otherwise,
5885 POS is the (constant) starting bit position (counted from the LSB).
5887 INNER may be a USE. This will occur when we started with a bitfield
5888 that went outside the boundary of the object in memory, which is
5889 allowed on most machines. To isolate this case, we produce a USE
5890 whose mode is wide enough and surround the MEM with it. The only
5891 code that understands the USE is this routine. If it is not removed,
5892 it will cause the resulting insn not to match.
5894 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5897 IN_DEST is non-zero if this is a reference in the destination of a
5898 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5899 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5902 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5903 ZERO_EXTRACT should be built even for bits starting at bit 0.
5905 MODE is the desired mode of the result (if IN_DEST == 0).
5907 The result is an RTX for the extraction or NULL_RTX if the target
5911 make_extraction (mode, inner, pos, pos_rtx, len,
5912 unsignedp, in_dest, in_compare)
5913 enum machine_mode mode;
5917 unsigned HOST_WIDE_INT len;
5919 int in_dest, in_compare;
5921 /* This mode describes the size of the storage area
5922 to fetch the overall value from. Within that, we
5923 ignore the POS lowest bits, etc. */
5924 enum machine_mode is_mode = GET_MODE (inner);
5925 enum machine_mode inner_mode;
5926 enum machine_mode wanted_inner_mode = byte_mode;
5927 enum machine_mode wanted_inner_reg_mode = word_mode;
5928 enum machine_mode pos_mode = word_mode;
5929 enum machine_mode extraction_mode = word_mode;
5930 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5933 rtx orig_pos_rtx = pos_rtx;
5934 HOST_WIDE_INT orig_pos;
5936 /* Get some information about INNER and get the innermost object. */
5937 if (GET_CODE (inner) == USE)
5938 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5939 /* We don't need to adjust the position because we set up the USE
5940 to pretend that it was a full-word object. */
5941 spans_byte = 1, inner = XEXP (inner, 0);
5942 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5944 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5945 consider just the QI as the memory to extract from.
5946 The subreg adds or removes high bits; its mode is
5947 irrelevant to the meaning of this extraction,
5948 since POS and LEN count from the lsb. */
5949 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5950 is_mode = GET_MODE (SUBREG_REG (inner));
5951 inner = SUBREG_REG (inner);
5954 inner_mode = GET_MODE (inner);
5956 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5957 pos = INTVAL (pos_rtx), pos_rtx = 0;
5959 /* See if this can be done without an extraction. We never can if the
5960 width of the field is not the same as that of some integer mode. For
5961 registers, we can only avoid the extraction if the position is at the
5962 low-order bit and this is either not in the destination or we have the
5963 appropriate STRICT_LOW_PART operation available.
5965 For MEM, we can avoid an extract if the field starts on an appropriate
5966 boundary and we can change the mode of the memory reference. However,
5967 we cannot directly access the MEM if we have a USE and the underlying
5968 MEM is not TMODE. This combination means that MEM was being used in a
5969 context where bits outside its mode were being referenced; that is only
5970 valid in bit-field insns. */
5972 if (tmode != BLKmode
5973 && ! (spans_byte && inner_mode != tmode)
5974 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5975 && GET_CODE (inner) != MEM
5977 || (GET_CODE (inner) == REG
5978 && (movstrict_optab->handlers[(int) tmode].insn_code
5979 != CODE_FOR_nothing))))
5980 || (GET_CODE (inner) == MEM && pos_rtx == 0
5982 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5983 : BITS_PER_UNIT)) == 0
5984 /* We can't do this if we are widening INNER_MODE (it
5985 may not be aligned, for one thing). */
5986 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5987 && (inner_mode == tmode
5988 || (! mode_dependent_address_p (XEXP (inner, 0))
5989 && ! MEM_VOLATILE_P (inner))))))
5991 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5992 field. If the original and current mode are the same, we need not
5993 adjust the offset. Otherwise, we do if bytes big endian.
5995 If INNER is not a MEM, get a piece consisting of just the field
5996 of interest (in this case POS % BITS_PER_WORD must be 0). */
5998 if (GET_CODE (inner) == MEM)
6001 /* POS counts from lsb, but make OFFSET count in memory order. */
6002 if (BYTES_BIG_ENDIAN)
6003 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6005 offset = pos / BITS_PER_UNIT;
6007 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
6008 MEM_COPY_ATTRIBUTES (new, inner);
6010 else if (GET_CODE (inner) == REG)
6012 /* We can't call gen_lowpart_for_combine here since we always want
6013 a SUBREG and it would sometimes return a new hard register. */
6014 if (tmode != inner_mode)
6015 new = gen_rtx_SUBREG (tmode, inner,
6017 && (GET_MODE_SIZE (inner_mode)
6019 ? (((GET_MODE_SIZE (inner_mode)
6020 - GET_MODE_SIZE (tmode))
6022 - pos / BITS_PER_WORD)
6023 : pos / BITS_PER_WORD));
6028 new = force_to_mode (inner, tmode,
6029 len >= HOST_BITS_PER_WIDE_INT
6030 ? ~(unsigned HOST_WIDE_INT) 0
6031 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6034 /* If this extraction is going into the destination of a SET,
6035 make a STRICT_LOW_PART unless we made a MEM. */
6038 return (GET_CODE (new) == MEM ? new
6039 : (GET_CODE (new) != SUBREG
6040 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6041 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
6046 /* If we know that no extraneous bits are set, and that the high
6047 bit is not set, convert the extraction to the cheaper of
6048 sign and zero extension, that are equivalent in these cases. */
6049 if (flag_expensive_optimizations
6050 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6051 && ((nonzero_bits (new, tmode)
6052 & ~(((unsigned HOST_WIDE_INT)
6053 GET_MODE_MASK (tmode))
6057 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6058 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6060 /* Prefer ZERO_EXTENSION, since it gives more information to
6062 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6067 /* Otherwise, sign- or zero-extend unless we already are in the
6070 return (gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6074 /* Unless this is a COMPARE or we have a funny memory reference,
6075 don't do anything with zero-extending field extracts starting at
6076 the low-order bit since they are simple AND operations. */
6077 if (pos_rtx == 0 && pos == 0 && ! in_dest
6078 && ! in_compare && ! spans_byte && unsignedp)
6081 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6082 we would be spanning bytes or if the position is not a constant and the
6083 length is not 1. In all other cases, we would only be going outside
6084 our object in cases when an original shift would have been
6086 if (! spans_byte && GET_CODE (inner) == MEM
6087 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6088 || (pos_rtx != 0 && len != 1)))
6091 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6092 and the mode for the result. */
6096 wanted_inner_reg_mode
6097 = insn_data[(int) CODE_FOR_insv].operand[0].mode;
6098 if (wanted_inner_reg_mode == VOIDmode)
6099 wanted_inner_reg_mode = word_mode;
6101 pos_mode = insn_data[(int) CODE_FOR_insv].operand[2].mode;
6102 if (pos_mode == VOIDmode)
6103 pos_mode = word_mode;
6105 extraction_mode = insn_data[(int) CODE_FOR_insv].operand[3].mode;
6106 if (extraction_mode == VOIDmode)
6107 extraction_mode = word_mode;
6112 if (! in_dest && unsignedp)
6114 wanted_inner_reg_mode
6115 = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
6116 if (wanted_inner_reg_mode == VOIDmode)
6117 wanted_inner_reg_mode = word_mode;
6119 pos_mode = insn_data[(int) CODE_FOR_extzv].operand[3].mode;
6120 if (pos_mode == VOIDmode)
6121 pos_mode = word_mode;
6123 extraction_mode = insn_data[(int) CODE_FOR_extzv].operand[0].mode;
6124 if (extraction_mode == VOIDmode)
6125 extraction_mode = word_mode;
6130 if (! in_dest && ! unsignedp)
6132 wanted_inner_reg_mode
6133 = insn_data[(int) CODE_FOR_extv].operand[1].mode;
6134 if (wanted_inner_reg_mode == VOIDmode)
6135 wanted_inner_reg_mode = word_mode;
6137 pos_mode = insn_data[(int) CODE_FOR_extv].operand[3].mode;
6138 if (pos_mode == VOIDmode)
6139 pos_mode = word_mode;
6141 extraction_mode = insn_data[(int) CODE_FOR_extv].operand[0].mode;
6142 if (extraction_mode == VOIDmode)
6143 extraction_mode = word_mode;
6147 /* Never narrow an object, since that might not be safe. */
6149 if (mode != VOIDmode
6150 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6151 extraction_mode = mode;
6153 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6154 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6155 pos_mode = GET_MODE (pos_rtx);
6157 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6158 if we have to change the mode of memory and cannot, the desired mode is
6160 if (GET_CODE (inner) != MEM)
6161 wanted_inner_mode = wanted_inner_reg_mode;
6162 else if (inner_mode != wanted_inner_mode
6163 && (mode_dependent_address_p (XEXP (inner, 0))
6164 || MEM_VOLATILE_P (inner)))
6165 wanted_inner_mode = extraction_mode;
6169 if (BITS_BIG_ENDIAN)
6171 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6172 BITS_BIG_ENDIAN style. If position is constant, compute new
6173 position. Otherwise, build subtraction.
6174 Note that POS is relative to the mode of the original argument.
6175 If it's a MEM we need to recompute POS relative to that.
6176 However, if we're extracting from (or inserting into) a register,
6177 we want to recompute POS relative to wanted_inner_mode. */
6178 int width = (GET_CODE (inner) == MEM
6179 ? GET_MODE_BITSIZE (is_mode)
6180 : GET_MODE_BITSIZE (wanted_inner_mode));
6183 pos = width - len - pos;
6186 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
6187 GEN_INT (width - len), pos_rtx);
6188 /* POS may be less than 0 now, but we check for that below.
6189 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6192 /* If INNER has a wider mode, make it smaller. If this is a constant
6193 extract, try to adjust the byte to point to the byte containing
6195 if (wanted_inner_mode != VOIDmode
6196 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6197 && ((GET_CODE (inner) == MEM
6198 && (inner_mode == wanted_inner_mode
6199 || (! mode_dependent_address_p (XEXP (inner, 0))
6200 && ! MEM_VOLATILE_P (inner))))))
6204 /* The computations below will be correct if the machine is big
6205 endian in both bits and bytes or little endian in bits and bytes.
6206 If it is mixed, we must adjust. */
6208 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6209 adjust OFFSET to compensate. */
6210 if (BYTES_BIG_ENDIAN
6212 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6213 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6215 /* If this is a constant position, we can move to the desired byte. */
6218 offset += pos / BITS_PER_UNIT;
6219 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6222 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6224 && is_mode != wanted_inner_mode)
6225 offset = (GET_MODE_SIZE (is_mode)
6226 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6228 if (offset != 0 || inner_mode != wanted_inner_mode)
6230 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
6231 plus_constant (XEXP (inner, 0), offset));
6233 MEM_COPY_ATTRIBUTES (newmem, inner);
6238 /* If INNER is not memory, we can always get it into the proper mode. If we
6239 are changing its mode, POS must be a constant and smaller than the size
6241 else if (GET_CODE (inner) != MEM)
6243 if (GET_MODE (inner) != wanted_inner_mode
6245 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6248 inner = force_to_mode (inner, wanted_inner_mode,
6250 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6251 ? ~(unsigned HOST_WIDE_INT) 0
6252 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6257 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6258 have to zero extend. Otherwise, we can just use a SUBREG. */
6260 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6262 rtx temp = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
6264 /* If we know that no extraneous bits are set, and that the high
6265 bit is not set, convert extraction to cheaper one - eighter
6266 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6268 if (flag_expensive_optimizations
6269 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6270 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6271 & ~(((unsigned HOST_WIDE_INT)
6272 GET_MODE_MASK (GET_MODE (pos_rtx)))
6276 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6278 /* Prefer ZERO_EXTENSION, since it gives more information to
6280 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6285 else if (pos_rtx != 0
6286 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6287 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
6289 /* Make POS_RTX unless we already have it and it is correct. If we don't
6290 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6292 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6293 pos_rtx = orig_pos_rtx;
6295 else if (pos_rtx == 0)
6296 pos_rtx = GEN_INT (pos);
6298 /* Make the required operation. See if we can use existing rtx. */
6299 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6300 extraction_mode, inner, GEN_INT (len), pos_rtx);
6302 new = gen_lowpart_for_combine (mode, new);
6307 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6308 with any other operations in X. Return X without that shift if so. */
6311 extract_left_shift (x, count)
6315 enum rtx_code code = GET_CODE (x);
6316 enum machine_mode mode = GET_MODE (x);
6322 /* This is the shift itself. If it is wide enough, we will return
6323 either the value being shifted if the shift count is equal to
6324 COUNT or a shift for the difference. */
6325 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6326 && INTVAL (XEXP (x, 1)) >= count)
6327 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6328 INTVAL (XEXP (x, 1)) - count);
6332 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6333 return gen_unary (code, mode, mode, tem);
6337 case PLUS: case IOR: case XOR: case AND:
6338 /* If we can safely shift this constant and we find the inner shift,
6339 make a new operation. */
6340 if (GET_CODE (XEXP (x,1)) == CONST_INT
6341 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6342 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6343 return gen_binary (code, mode, tem,
6344 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6355 /* Look at the expression rooted at X. Look for expressions
6356 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6357 Form these expressions.
6359 Return the new rtx, usually just X.
6361 Also, for machines like the Vax that don't have logical shift insns,
6362 try to convert logical to arithmetic shift operations in cases where
6363 they are equivalent. This undoes the canonicalizations to logical
6364 shifts done elsewhere.
6366 We try, as much as possible, to re-use rtl expressions to save memory.
6368 IN_CODE says what kind of expression we are processing. Normally, it is
6369 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6370 being kludges), it is MEM. When processing the arguments of a comparison
6371 or a COMPARE against zero, it is COMPARE. */
6374 make_compound_operation (x, in_code)
6376 enum rtx_code in_code;
6378 enum rtx_code code = GET_CODE (x);
6379 enum machine_mode mode = GET_MODE (x);
6380 int mode_width = GET_MODE_BITSIZE (mode);
6382 enum rtx_code next_code;
6388 /* Select the code to be used in recursive calls. Once we are inside an
6389 address, we stay there. If we have a comparison, set to COMPARE,
6390 but once inside, go back to our default of SET. */
6392 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6393 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
6394 && XEXP (x, 1) == const0_rtx) ? COMPARE
6395 : in_code == COMPARE ? SET : in_code);
6397 /* Process depending on the code of this operation. If NEW is set
6398 non-zero, it will be returned. */
6403 /* Convert shifts by constants into multiplications if inside
6405 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6406 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6407 && INTVAL (XEXP (x, 1)) >= 0)
6409 new = make_compound_operation (XEXP (x, 0), next_code);
6410 new = gen_rtx_combine (MULT, mode, new,
6411 GEN_INT ((HOST_WIDE_INT) 1
6412 << INTVAL (XEXP (x, 1))));
6417 /* If the second operand is not a constant, we can't do anything
6419 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6422 /* If the constant is a power of two minus one and the first operand
6423 is a logical right shift, make an extraction. */
6424 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6425 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6427 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6428 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6429 0, in_code == COMPARE);
6432 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6433 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6434 && subreg_lowpart_p (XEXP (x, 0))
6435 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6436 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6438 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6440 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6441 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6442 0, in_code == COMPARE);
6444 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6445 else if ((GET_CODE (XEXP (x, 0)) == XOR
6446 || GET_CODE (XEXP (x, 0)) == IOR)
6447 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6448 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6449 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6451 /* Apply the distributive law, and then try to make extractions. */
6452 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
6453 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6455 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6457 new = make_compound_operation (new, in_code);
6460 /* If we are have (and (rotate X C) M) and C is larger than the number
6461 of bits in M, this is an extraction. */
6463 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6464 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6465 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6466 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6468 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6469 new = make_extraction (mode, new,
6470 (GET_MODE_BITSIZE (mode)
6471 - INTVAL (XEXP (XEXP (x, 0), 1))),
6472 NULL_RTX, i, 1, 0, in_code == COMPARE);
6475 /* On machines without logical shifts, if the operand of the AND is
6476 a logical shift and our mask turns off all the propagated sign
6477 bits, we can replace the logical shift with an arithmetic shift. */
6478 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6479 && (lshr_optab->handlers[(int) mode].insn_code
6480 == CODE_FOR_nothing)
6481 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6482 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6483 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6484 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6485 && mode_width <= HOST_BITS_PER_WIDE_INT)
6487 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6489 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6490 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6492 gen_rtx_combine (ASHIFTRT, mode,
6493 make_compound_operation (XEXP (XEXP (x, 0), 0),
6495 XEXP (XEXP (x, 0), 1)));
6498 /* If the constant is one less than a power of two, this might be
6499 representable by an extraction even if no shift is present.
6500 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6501 we are in a COMPARE. */
6502 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6503 new = make_extraction (mode,
6504 make_compound_operation (XEXP (x, 0),
6506 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6508 /* If we are in a comparison and this is an AND with a power of two,
6509 convert this into the appropriate bit extract. */
6510 else if (in_code == COMPARE
6511 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6512 new = make_extraction (mode,
6513 make_compound_operation (XEXP (x, 0),
6515 i, NULL_RTX, 1, 1, 0, 1);
6520 /* If the sign bit is known to be zero, replace this with an
6521 arithmetic shift. */
6522 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6523 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6524 && mode_width <= HOST_BITS_PER_WIDE_INT
6525 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6527 new = gen_rtx_combine (ASHIFTRT, mode,
6528 make_compound_operation (XEXP (x, 0),
6534 /* ... fall through ... */
6540 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6541 this is a SIGN_EXTRACT. */
6542 if (GET_CODE (rhs) == CONST_INT
6543 && GET_CODE (lhs) == ASHIFT
6544 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6545 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6547 new = make_compound_operation (XEXP (lhs, 0), next_code);
6548 new = make_extraction (mode, new,
6549 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6550 NULL_RTX, mode_width - INTVAL (rhs),
6551 code == LSHIFTRT, 0, in_code == COMPARE);
6555 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6556 If so, try to merge the shifts into a SIGN_EXTEND. We could
6557 also do this for some cases of SIGN_EXTRACT, but it doesn't
6558 seem worth the effort; the case checked for occurs on Alpha. */
6560 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6561 && ! (GET_CODE (lhs) == SUBREG
6562 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6563 && GET_CODE (rhs) == CONST_INT
6564 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6565 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6566 new = make_extraction (mode, make_compound_operation (new, next_code),
6567 0, NULL_RTX, mode_width - INTVAL (rhs),
6568 code == LSHIFTRT, 0, in_code == COMPARE);
6573 /* Call ourselves recursively on the inner expression. If we are
6574 narrowing the object and it has a different RTL code from
6575 what it originally did, do this SUBREG as a force_to_mode. */
6577 tem = make_compound_operation (SUBREG_REG (x), in_code);
6578 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6579 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6580 && subreg_lowpart_p (x))
6582 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6585 /* If we have something other than a SUBREG, we might have
6586 done an expansion, so rerun outselves. */
6587 if (GET_CODE (newer) != SUBREG)
6588 newer = make_compound_operation (newer, in_code);
6593 /* If this is a paradoxical subreg, and the new code is a sign or
6594 zero extension, omit the subreg and widen the extension. If it
6595 is a regular subreg, we can still get rid of the subreg by not
6596 widening so much, or in fact removing the extension entirely. */
6597 if ((GET_CODE (tem) == SIGN_EXTEND
6598 || GET_CODE (tem) == ZERO_EXTEND)
6599 && subreg_lowpart_p (x))
6601 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6602 || (GET_MODE_SIZE (mode) >
6603 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6604 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6606 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6617 x = gen_lowpart_for_combine (mode, new);
6618 code = GET_CODE (x);
6621 /* Now recursively process each operand of this operation. */
6622 fmt = GET_RTX_FORMAT (code);
6623 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6626 new = make_compound_operation (XEXP (x, i), next_code);
6627 SUBST (XEXP (x, i), new);
6633 /* Given M see if it is a value that would select a field of bits
6634 within an item, but not the entire word. Return -1 if not.
6635 Otherwise, return the starting position of the field, where 0 is the
6638 *PLEN is set to the length of the field. */
6641 get_pos_from_mask (m, plen)
6642 unsigned HOST_WIDE_INT m;
6643 unsigned HOST_WIDE_INT *plen;
6645 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6646 int pos = exact_log2 (m & -m);
6652 /* Now shift off the low-order zero bits and see if we have a power of
6654 len = exact_log2 ((m >> pos) + 1);
6663 /* See if X can be simplified knowing that we will only refer to it in
6664 MODE and will only refer to those bits that are nonzero in MASK.
6665 If other bits are being computed or if masking operations are done
6666 that select a superset of the bits in MASK, they can sometimes be
6669 Return a possibly simplified expression, but always convert X to
6670 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6672 Also, if REG is non-zero and X is a register equal in value to REG,
6675 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6676 are all off in X. This is used when X will be complemented, by either
6677 NOT, NEG, or XOR. */
6680 force_to_mode (x, mode, mask, reg, just_select)
6682 enum machine_mode mode;
6683 unsigned HOST_WIDE_INT mask;
6687 enum rtx_code code = GET_CODE (x);
6688 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6689 enum machine_mode op_mode;
6690 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6693 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6694 code below will do the wrong thing since the mode of such an
6695 expression is VOIDmode.
6697 Also do nothing if X is a CLOBBER; this can happen if X was
6698 the return value from a call to gen_lowpart_for_combine. */
6699 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6702 /* We want to perform the operation is its present mode unless we know
6703 that the operation is valid in MODE, in which case we do the operation
6705 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6706 && code_to_optab[(int) code] != 0
6707 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6708 != CODE_FOR_nothing))
6709 ? mode : GET_MODE (x));
6711 /* It is not valid to do a right-shift in a narrower mode
6712 than the one it came in with. */
6713 if ((code == LSHIFTRT || code == ASHIFTRT)
6714 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6715 op_mode = GET_MODE (x);
6717 /* Truncate MASK to fit OP_MODE. */
6719 mask &= GET_MODE_MASK (op_mode);
6721 /* When we have an arithmetic operation, or a shift whose count we
6722 do not know, we need to assume that all bit the up to the highest-order
6723 bit in MASK will be needed. This is how we form such a mask. */
6725 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6726 ? GET_MODE_MASK (op_mode)
6727 : (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6730 fuller_mask = ~(HOST_WIDE_INT) 0;
6732 /* Determine what bits of X are guaranteed to be (non)zero. */
6733 nonzero = nonzero_bits (x, mode);
6735 /* If none of the bits in X are needed, return a zero. */
6736 if (! just_select && (nonzero & mask) == 0)
6739 /* If X is a CONST_INT, return a new one. Do this here since the
6740 test below will fail. */
6741 if (GET_CODE (x) == CONST_INT)
6743 HOST_WIDE_INT cval = INTVAL (x) & mask;
6744 int width = GET_MODE_BITSIZE (mode);
6746 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6747 number, sign extend it. */
6748 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6749 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6750 cval |= (HOST_WIDE_INT) -1 << width;
6752 return GEN_INT (cval);
6755 /* If X is narrower than MODE and we want all the bits in X's mode, just
6756 get X in the proper mode. */
6757 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6758 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6759 return gen_lowpart_for_combine (mode, x);
6761 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6762 MASK are already known to be zero in X, we need not do anything. */
6763 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6769 /* If X is a (clobber (const_int)), return it since we know we are
6770 generating something that won't match. */
6774 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6775 spanned the boundary of the MEM. If we are now masking so it is
6776 within that boundary, we don't need the USE any more. */
6777 if (! BITS_BIG_ENDIAN
6778 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6779 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6786 x = expand_compound_operation (x);
6787 if (GET_CODE (x) != code)
6788 return force_to_mode (x, mode, mask, reg, next_select);
6792 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6793 || rtx_equal_p (reg, get_last_value (x))))
6798 if (subreg_lowpart_p (x)
6799 /* We can ignore the effect of this SUBREG if it narrows the mode or
6800 if the constant masks to zero all the bits the mode doesn't
6802 && ((GET_MODE_SIZE (GET_MODE (x))
6803 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6805 & GET_MODE_MASK (GET_MODE (x))
6806 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6807 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6811 /* If this is an AND with a constant, convert it into an AND
6812 whose constant is the AND of that constant with MASK. If it
6813 remains an AND of MASK, delete it since it is redundant. */
6815 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6817 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6818 mask & INTVAL (XEXP (x, 1)));
6820 /* If X is still an AND, see if it is an AND with a mask that
6821 is just some low-order bits. If so, and it is MASK, we don't
6824 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6825 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6828 /* If it remains an AND, try making another AND with the bits
6829 in the mode mask that aren't in MASK turned on. If the
6830 constant in the AND is wide enough, this might make a
6831 cheaper constant. */
6833 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6834 && GET_MODE_MASK (GET_MODE (x)) != mask
6835 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6837 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6838 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6839 int width = GET_MODE_BITSIZE (GET_MODE (x));
6842 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6843 number, sign extend it. */
6844 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6845 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6846 cval |= (HOST_WIDE_INT) -1 << width;
6848 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6849 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6859 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6860 low-order bits (as in an alignment operation) and FOO is already
6861 aligned to that boundary, mask C1 to that boundary as well.
6862 This may eliminate that PLUS and, later, the AND. */
6865 unsigned int width = GET_MODE_BITSIZE (mode);
6866 unsigned HOST_WIDE_INT smask = mask;
6868 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6869 number, sign extend it. */
6871 if (width < HOST_BITS_PER_WIDE_INT
6872 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6873 smask |= (HOST_WIDE_INT) -1 << width;
6875 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6876 && exact_log2 (- smask) >= 0)
6880 && (XEXP (x, 0) == stack_pointer_rtx
6881 || XEXP (x, 0) == frame_pointer_rtx))
6883 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6884 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6886 sp_mask &= ~(sp_alignment - 1);
6887 if ((sp_mask & ~smask) == 0
6888 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~smask) != 0)
6889 return force_to_mode (plus_constant (XEXP (x, 0),
6890 ((INTVAL (XEXP (x, 1)) -
6891 STACK_BIAS) & smask)
6893 mode, smask, reg, next_select);
6896 if ((nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6897 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6898 return force_to_mode (plus_constant (XEXP (x, 0),
6899 (INTVAL (XEXP (x, 1))
6901 mode, smask, reg, next_select);
6905 /* ... fall through ... */
6908 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6909 most significant bit in MASK since carries from those bits will
6910 affect the bits we are interested in. */
6915 /* If X is (minus C Y) where C's least set bit is larger than any bit
6916 in the mask, then we may replace with (neg Y). */
6917 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6918 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6919 & -INTVAL (XEXP (x, 0))))
6922 x = gen_unary (NEG, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6923 return force_to_mode (x, mode, mask, reg, next_select);
6926 /* Similarly, if C contains every bit in the mask, then we may
6927 replace with (not Y). */
6928 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6929 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) mask)
6930 == INTVAL (XEXP (x, 0))))
6932 x = gen_unary (NOT, GET_MODE (x), GET_MODE (x), XEXP (x, 1));
6933 return force_to_mode (x, mode, mask, reg, next_select);
6941 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6942 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6943 operation which may be a bitfield extraction. Ensure that the
6944 constant we form is not wider than the mode of X. */
6946 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6947 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6948 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6949 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6950 && GET_CODE (XEXP (x, 1)) == CONST_INT
6951 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6952 + floor_log2 (INTVAL (XEXP (x, 1))))
6953 < GET_MODE_BITSIZE (GET_MODE (x)))
6954 && (INTVAL (XEXP (x, 1))
6955 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6957 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6958 << INTVAL (XEXP (XEXP (x, 0), 1)));
6959 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6960 XEXP (XEXP (x, 0), 0), temp);
6961 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6962 XEXP (XEXP (x, 0), 1));
6963 return force_to_mode (x, mode, mask, reg, next_select);
6967 /* For most binary operations, just propagate into the operation and
6968 change the mode if we have an operation of that mode. */
6970 op0 = gen_lowpart_for_combine (op_mode,
6971 force_to_mode (XEXP (x, 0), mode, mask,
6973 op1 = gen_lowpart_for_combine (op_mode,
6974 force_to_mode (XEXP (x, 1), mode, mask,
6977 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6978 MASK since OP1 might have been sign-extended but we never want
6979 to turn on extra bits, since combine might have previously relied
6980 on them being off. */
6981 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6982 && (INTVAL (op1) & mask) != 0)
6983 op1 = GEN_INT (INTVAL (op1) & mask);
6985 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6986 x = gen_binary (code, op_mode, op0, op1);
6990 /* For left shifts, do the same, but just for the first operand.
6991 However, we cannot do anything with shifts where we cannot
6992 guarantee that the counts are smaller than the size of the mode
6993 because such a count will have a different meaning in a
6996 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6997 && INTVAL (XEXP (x, 1)) >= 0
6998 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6999 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7000 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7001 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7004 /* If the shift count is a constant and we can do arithmetic in
7005 the mode of the shift, refine which bits we need. Otherwise, use the
7006 conservative form of the mask. */
7007 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7008 && INTVAL (XEXP (x, 1)) >= 0
7009 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7010 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7011 mask >>= INTVAL (XEXP (x, 1));
7015 op0 = gen_lowpart_for_combine (op_mode,
7016 force_to_mode (XEXP (x, 0), op_mode,
7017 mask, reg, next_select));
7019 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7020 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7024 /* Here we can only do something if the shift count is a constant,
7025 this shift constant is valid for the host, and we can do arithmetic
7028 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7029 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7030 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7032 rtx inner = XEXP (x, 0);
7033 unsigned HOST_WIDE_INT inner_mask;
7035 /* Select the mask of the bits we need for the shift operand. */
7036 inner_mask = mask << INTVAL (XEXP (x, 1));
7038 /* We can only change the mode of the shift if we can do arithmetic
7039 in the mode of the shift and INNER_MASK is no wider than the
7040 width of OP_MODE. */
7041 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
7042 || (inner_mask & ~GET_MODE_MASK (op_mode)) != 0)
7043 op_mode = GET_MODE (x);
7045 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7047 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7048 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7051 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7052 shift and AND produces only copies of the sign bit (C2 is one less
7053 than a power of two), we can do this with just a shift. */
7055 if (GET_CODE (x) == LSHIFTRT
7056 && GET_CODE (XEXP (x, 1)) == CONST_INT
7057 /* The shift puts one of the sign bit copies in the least significant
7059 && ((INTVAL (XEXP (x, 1))
7060 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7061 >= GET_MODE_BITSIZE (GET_MODE (x)))
7062 && exact_log2 (mask + 1) >= 0
7063 /* Number of bits left after the shift must be more than the mask
7065 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7066 <= GET_MODE_BITSIZE (GET_MODE (x)))
7067 /* Must be more sign bit copies than the mask needs. */
7068 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7069 >= exact_log2 (mask + 1)))
7070 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7071 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7072 - exact_log2 (mask + 1)));
7077 /* If we are just looking for the sign bit, we don't need this shift at
7078 all, even if it has a variable count. */
7079 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7080 && (mask == ((unsigned HOST_WIDE_INT) 1
7081 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7082 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7084 /* If this is a shift by a constant, get a mask that contains those bits
7085 that are not copies of the sign bit. We then have two cases: If
7086 MASK only includes those bits, this can be a logical shift, which may
7087 allow simplifications. If MASK is a single-bit field not within
7088 those bits, we are requesting a copy of the sign bit and hence can
7089 shift the sign bit to the appropriate location. */
7091 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7092 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7096 /* If the considered data is wider then HOST_WIDE_INT, we can't
7097 represent a mask for all its bits in a single scalar.
7098 But we only care about the lower bits, so calculate these. */
7100 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7102 nonzero = ~(HOST_WIDE_INT) 0;
7104 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7105 is the number of bits a full-width mask would have set.
7106 We need only shift if these are fewer than nonzero can
7107 hold. If not, we must keep all bits set in nonzero. */
7109 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7110 < HOST_BITS_PER_WIDE_INT)
7111 nonzero >>= INTVAL (XEXP (x, 1))
7112 + HOST_BITS_PER_WIDE_INT
7113 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7117 nonzero = GET_MODE_MASK (GET_MODE (x));
7118 nonzero >>= INTVAL (XEXP (x, 1));
7121 if ((mask & ~nonzero) == 0
7122 || (i = exact_log2 (mask)) >= 0)
7124 x = simplify_shift_const
7125 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7126 i < 0 ? INTVAL (XEXP (x, 1))
7127 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7129 if (GET_CODE (x) != ASHIFTRT)
7130 return force_to_mode (x, mode, mask, reg, next_select);
7134 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
7135 even if the shift count isn't a constant. */
7137 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7141 /* If this is a zero- or sign-extension operation that just affects bits
7142 we don't care about, remove it. Be sure the call above returned
7143 something that is still a shift. */
7145 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7146 && GET_CODE (XEXP (x, 1)) == CONST_INT
7147 && INTVAL (XEXP (x, 1)) >= 0
7148 && (INTVAL (XEXP (x, 1))
7149 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7150 && GET_CODE (XEXP (x, 0)) == ASHIFT
7151 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7152 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
7153 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7160 /* If the shift count is constant and we can do computations
7161 in the mode of X, compute where the bits we care about are.
7162 Otherwise, we can't do anything. Don't change the mode of
7163 the shift or propagate MODE into the shift, though. */
7164 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7165 && INTVAL (XEXP (x, 1)) >= 0)
7167 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7168 GET_MODE (x), GEN_INT (mask),
7170 if (temp && GET_CODE(temp) == CONST_INT)
7172 force_to_mode (XEXP (x, 0), GET_MODE (x),
7173 INTVAL (temp), reg, next_select));
7178 /* If we just want the low-order bit, the NEG isn't needed since it
7179 won't change the low-order bit. */
7181 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7183 /* We need any bits less significant than the most significant bit in
7184 MASK since carries from those bits will affect the bits we are
7190 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7191 same as the XOR case above. Ensure that the constant we form is not
7192 wider than the mode of X. */
7194 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7195 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7196 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7197 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7198 < GET_MODE_BITSIZE (GET_MODE (x)))
7199 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7201 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
7202 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7203 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7205 return force_to_mode (x, mode, mask, reg, next_select);
7208 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7209 use the full mask inside the NOT. */
7213 op0 = gen_lowpart_for_combine (op_mode,
7214 force_to_mode (XEXP (x, 0), mode, mask,
7216 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7217 x = gen_unary (code, op_mode, op_mode, op0);
7221 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7222 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7223 which is equal to STORE_FLAG_VALUE. */
7224 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7225 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7226 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
7227 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7232 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7233 written in a narrower mode. We play it safe and do not do so. */
7236 gen_lowpart_for_combine (GET_MODE (x),
7237 force_to_mode (XEXP (x, 1), mode,
7238 mask, reg, next_select)));
7240 gen_lowpart_for_combine (GET_MODE (x),
7241 force_to_mode (XEXP (x, 2), mode,
7242 mask, reg,next_select)));
7249 /* Ensure we return a value of the proper mode. */
7250 return gen_lowpart_for_combine (mode, x);
7253 /* Return nonzero if X is an expression that has one of two values depending on
7254 whether some other value is zero or nonzero. In that case, we return the
7255 value that is being tested, *PTRUE is set to the value if the rtx being
7256 returned has a nonzero value, and *PFALSE is set to the other alternative.
7258 If we return zero, we set *PTRUE and *PFALSE to X. */
7261 if_then_else_cond (x, ptrue, pfalse)
7263 rtx *ptrue, *pfalse;
7265 enum machine_mode mode = GET_MODE (x);
7266 enum rtx_code code = GET_CODE (x);
7267 rtx cond0, cond1, true0, true1, false0, false1;
7268 unsigned HOST_WIDE_INT nz;
7270 /* If we are comparing a value against zero, we are done. */
7271 if ((code == NE || code == EQ)
7272 && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 0)
7274 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7275 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7279 /* If this is a unary operation whose operand has one of two values, apply
7280 our opcode to compute those values. */
7281 else if (GET_RTX_CLASS (code) == '1'
7282 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7284 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
7285 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
7289 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7290 make can't possibly match and would suppress other optimizations. */
7291 else if (code == COMPARE)
7294 /* If this is a binary operation, see if either side has only one of two
7295 values. If either one does or if both do and they are conditional on
7296 the same value, compute the new true and false values. */
7297 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
7298 || GET_RTX_CLASS (code) == '<')
7300 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7301 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7303 if ((cond0 != 0 || cond1 != 0)
7304 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7306 /* If if_then_else_cond returned zero, then true/false are the
7307 same rtl. We must copy one of them to prevent invalid rtl
7310 true0 = copy_rtx (true0);
7311 else if (cond1 == 0)
7312 true1 = copy_rtx (true1);
7314 *ptrue = gen_binary (code, mode, true0, true1);
7315 *pfalse = gen_binary (code, mode, false0, false1);
7316 return cond0 ? cond0 : cond1;
7319 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7320 operands is zero when the other is non-zero, and vice-versa,
7321 and STORE_FLAG_VALUE is 1 or -1. */
7323 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7324 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7326 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7328 rtx op0 = XEXP (XEXP (x, 0), 1);
7329 rtx op1 = XEXP (XEXP (x, 1), 1);
7331 cond0 = XEXP (XEXP (x, 0), 0);
7332 cond1 = XEXP (XEXP (x, 1), 0);
7334 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7335 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7336 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7337 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7338 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7339 || ((swap_condition (GET_CODE (cond0))
7340 == combine_reversed_comparison_code (cond1))
7341 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7342 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7343 && ! side_effects_p (x))
7345 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7346 *pfalse = gen_binary (MULT, mode,
7348 ? gen_unary (NEG, mode, mode, op1) : op1),
7354 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7356 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7357 && (code == MULT || code == AND || code == UMIN)
7358 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7360 cond0 = XEXP (XEXP (x, 0), 0);
7361 cond1 = XEXP (XEXP (x, 1), 0);
7363 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
7364 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
7365 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7366 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7367 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7368 || ((swap_condition (GET_CODE (cond0))
7369 == combine_reversed_comparison_code (cond1))
7370 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7371 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7372 && ! side_effects_p (x))
7374 *ptrue = *pfalse = const0_rtx;
7380 else if (code == IF_THEN_ELSE)
7382 /* If we have IF_THEN_ELSE already, extract the condition and
7383 canonicalize it if it is NE or EQ. */
7384 cond0 = XEXP (x, 0);
7385 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7386 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7387 return XEXP (cond0, 0);
7388 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7390 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7391 return XEXP (cond0, 0);
7397 /* If X is a normal SUBREG with both inner and outer modes integral,
7398 we can narrow both the true and false values of the inner expression,
7399 if there is a condition. */
7400 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
7401 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
7402 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
7403 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7406 if ((GET_CODE (SUBREG_REG (x)) == REG
7407 || GET_CODE (SUBREG_REG (x)) == MEM
7408 || CONSTANT_P (SUBREG_REG (x)))
7409 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))) > UNITS_PER_WORD
7410 && (WORDS_BIG_ENDIAN || SUBREG_WORD (x) != 0))
7412 true0 = operand_subword (true0, SUBREG_WORD (x), 0,
7413 GET_MODE (SUBREG_REG (x)));
7414 false0 = operand_subword (false0, SUBREG_WORD (x), 0,
7415 GET_MODE (SUBREG_REG (x)));
7417 *ptrue = force_to_mode (true0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7419 = force_to_mode (false0, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
7424 /* If X is a constant, this isn't special and will cause confusions
7425 if we treat it as such. Likewise if it is equivalent to a constant. */
7426 else if (CONSTANT_P (x)
7427 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7430 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7431 will be least confusing to the rest of the compiler. */
7432 else if (mode == BImode)
7434 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7438 /* If X is known to be either 0 or -1, those are the true and
7439 false values when testing X. */
7440 else if (x == constm1_rtx || x == const0_rtx
7441 || (mode != VOIDmode
7442 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7444 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7448 /* Likewise for 0 or a single bit. */
7449 else if (mode != VOIDmode
7450 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7451 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7453 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
7457 /* Otherwise fail; show no condition with true and false values the same. */
7458 *ptrue = *pfalse = x;
7462 /* Return the value of expression X given the fact that condition COND
7463 is known to be true when applied to REG as its first operand and VAL
7464 as its second. X is known to not be shared and so can be modified in
7467 We only handle the simplest cases, and specifically those cases that
7468 arise with IF_THEN_ELSE expressions. */
7471 known_cond (x, cond, reg, val)
7476 enum rtx_code code = GET_CODE (x);
7481 if (side_effects_p (x))
7484 if (cond == EQ && rtx_equal_p (x, reg) && !FLOAT_MODE_P (cond))
7486 if (cond == UNEQ && rtx_equal_p (x, reg))
7489 /* If X is (abs REG) and we know something about REG's relationship
7490 with zero, we may be able to simplify this. */
7492 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7495 case GE: case GT: case EQ:
7498 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
7504 /* The only other cases we handle are MIN, MAX, and comparisons if the
7505 operands are the same as REG and VAL. */
7507 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
7509 if (rtx_equal_p (XEXP (x, 0), val))
7510 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7512 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7514 if (GET_RTX_CLASS (code) == '<')
7516 if (comparison_dominates_p (cond, code))
7517 return const_true_rtx;
7519 code = combine_reversed_comparison_code (x);
7521 && comparison_dominates_p (cond, code))
7526 else if (code == SMAX || code == SMIN
7527 || code == UMIN || code == UMAX)
7529 int unsignedp = (code == UMIN || code == UMAX);
7531 /* Do not reverse the condition when it is NE or EQ.
7532 This is because we cannot conclude anything about
7533 the value of 'SMAX (x, y)' when x is not equal to y,
7534 but we can when x equals y. */
7535 if ((code == SMAX || code == UMAX)
7536 && ! (cond == EQ || cond == NE))
7537 cond = reverse_condition (cond);
7542 return unsignedp ? x : XEXP (x, 1);
7544 return unsignedp ? x : XEXP (x, 0);
7546 return unsignedp ? XEXP (x, 1) : x;
7548 return unsignedp ? XEXP (x, 0) : x;
7556 fmt = GET_RTX_FORMAT (code);
7557 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7560 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7561 else if (fmt[i] == 'E')
7562 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7563 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7570 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7571 assignment as a field assignment. */
7574 rtx_equal_for_field_assignment_p (x, y)
7578 if (x == y || rtx_equal_p (x, y))
7581 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7584 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7585 Note that all SUBREGs of MEM are paradoxical; otherwise they
7586 would have been rewritten. */
7587 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7588 && GET_CODE (SUBREG_REG (y)) == MEM
7589 && rtx_equal_p (SUBREG_REG (y),
7590 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7593 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7594 && GET_CODE (SUBREG_REG (x)) == MEM
7595 && rtx_equal_p (SUBREG_REG (x),
7596 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7599 /* We used to see if get_last_value of X and Y were the same but that's
7600 not correct. In one direction, we'll cause the assignment to have
7601 the wrong destination and in the case, we'll import a register into this
7602 insn that might have already have been dead. So fail if none of the
7603 above cases are true. */
7607 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7608 Return that assignment if so.
7610 We only handle the most common cases. */
7613 make_field_assignment (x)
7616 rtx dest = SET_DEST (x);
7617 rtx src = SET_SRC (x);
7622 unsigned HOST_WIDE_INT len;
7624 enum machine_mode mode;
7626 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7627 a clear of a one-bit field. We will have changed it to
7628 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7631 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7632 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7633 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7634 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7636 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7639 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7643 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7644 && subreg_lowpart_p (XEXP (src, 0))
7645 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7646 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7647 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7648 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7649 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7651 assign = make_extraction (VOIDmode, dest, 0,
7652 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7655 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7659 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7661 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7662 && XEXP (XEXP (src, 0), 0) == const1_rtx
7663 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7665 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7668 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7672 /* The other case we handle is assignments into a constant-position
7673 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7674 a mask that has all one bits except for a group of zero bits and
7675 OTHER is known to have zeros where C1 has ones, this is such an
7676 assignment. Compute the position and length from C1. Shift OTHER
7677 to the appropriate position, force it to the required mode, and
7678 make the extraction. Check for the AND in both operands. */
7680 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7683 rhs = expand_compound_operation (XEXP (src, 0));
7684 lhs = expand_compound_operation (XEXP (src, 1));
7686 if (GET_CODE (rhs) == AND
7687 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7688 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7689 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7690 else if (GET_CODE (lhs) == AND
7691 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7692 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7693 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7697 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7698 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7699 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7700 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7703 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7707 /* The mode to use for the source is the mode of the assignment, or of
7708 what is inside a possible STRICT_LOW_PART. */
7709 mode = (GET_CODE (assign) == STRICT_LOW_PART
7710 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7712 /* Shift OTHER right POS places and make it the source, restricting it
7713 to the proper length and mode. */
7715 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7716 GET_MODE (src), other, pos),
7718 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7719 ? ~(unsigned HOST_WIDE_INT) 0
7720 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7723 return gen_rtx_combine (SET, VOIDmode, assign, src);
7726 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7730 apply_distributive_law (x)
7733 enum rtx_code code = GET_CODE (x);
7734 rtx lhs, rhs, other;
7736 enum rtx_code inner_code;
7738 /* Distributivity is not true for floating point.
7739 It can change the value. So don't do it.
7740 -- rms and moshier@world.std.com. */
7741 if (FLOAT_MODE_P (GET_MODE (x)))
7744 /* The outer operation can only be one of the following: */
7745 if (code != IOR && code != AND && code != XOR
7746 && code != PLUS && code != MINUS)
7749 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7751 /* If either operand is a primitive we can't do anything, so get out
7753 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7754 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7757 lhs = expand_compound_operation (lhs);
7758 rhs = expand_compound_operation (rhs);
7759 inner_code = GET_CODE (lhs);
7760 if (inner_code != GET_CODE (rhs))
7763 /* See if the inner and outer operations distribute. */
7770 /* These all distribute except over PLUS. */
7771 if (code == PLUS || code == MINUS)
7776 if (code != PLUS && code != MINUS)
7781 /* This is also a multiply, so it distributes over everything. */
7785 /* Non-paradoxical SUBREGs distributes over all operations, provided
7786 the inner modes and word numbers are the same, this is an extraction
7787 of a low-order part, we don't convert an fp operation to int or
7788 vice versa, and we would not be converting a single-word
7789 operation into a multi-word operation. The latter test is not
7790 required, but it prevents generating unneeded multi-word operations.
7791 Some of the previous tests are redundant given the latter test, but
7792 are retained because they are required for correctness.
7794 We produce the result slightly differently in this case. */
7796 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7797 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7798 || ! subreg_lowpart_p (lhs)
7799 || (GET_MODE_CLASS (GET_MODE (lhs))
7800 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7801 || (GET_MODE_SIZE (GET_MODE (lhs))
7802 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7803 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7806 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7807 SUBREG_REG (lhs), SUBREG_REG (rhs));
7808 return gen_lowpart_for_combine (GET_MODE (x), tem);
7814 /* Set LHS and RHS to the inner operands (A and B in the example
7815 above) and set OTHER to the common operand (C in the example).
7816 These is only one way to do this unless the inner operation is
7818 if (GET_RTX_CLASS (inner_code) == 'c'
7819 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7820 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7821 else if (GET_RTX_CLASS (inner_code) == 'c'
7822 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7823 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7824 else if (GET_RTX_CLASS (inner_code) == 'c'
7825 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7826 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7827 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7828 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7832 /* Form the new inner operation, seeing if it simplifies first. */
7833 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7835 /* There is one exception to the general way of distributing:
7836 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7837 if (code == XOR && inner_code == IOR)
7840 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7843 /* We may be able to continuing distributing the result, so call
7844 ourselves recursively on the inner operation before forming the
7845 outer operation, which we return. */
7846 return gen_binary (inner_code, GET_MODE (x),
7847 apply_distributive_law (tem), other);
7850 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7853 Return an equivalent form, if different from X. Otherwise, return X. If
7854 X is zero, we are to always construct the equivalent form. */
7857 simplify_and_const_int (x, mode, varop, constop)
7859 enum machine_mode mode;
7861 unsigned HOST_WIDE_INT constop;
7863 unsigned HOST_WIDE_INT nonzero;
7866 /* Simplify VAROP knowing that we will be only looking at some of the
7868 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7870 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7871 CONST_INT, we are done. */
7872 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7875 /* See what bits may be nonzero in VAROP. Unlike the general case of
7876 a call to nonzero_bits, here we don't care about bits outside
7879 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7880 nonzero = trunc_int_for_mode (nonzero, mode);
7882 /* Turn off all bits in the constant that are known to already be zero.
7883 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7884 which is tested below. */
7888 /* If we don't have any bits left, return zero. */
7892 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7893 a power of two, we can replace this with a ASHIFT. */
7894 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7895 && (i = exact_log2 (constop)) >= 0)
7896 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7898 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7899 or XOR, then try to apply the distributive law. This may eliminate
7900 operations if either branch can be simplified because of the AND.
7901 It may also make some cases more complex, but those cases probably
7902 won't match a pattern either with or without this. */
7904 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7906 gen_lowpart_for_combine
7908 apply_distributive_law
7909 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7910 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7911 XEXP (varop, 0), constop),
7912 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7913 XEXP (varop, 1), constop))));
7915 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7916 if we already had one (just check for the simplest cases). */
7917 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7918 && GET_MODE (XEXP (x, 0)) == mode
7919 && SUBREG_REG (XEXP (x, 0)) == varop)
7920 varop = XEXP (x, 0);
7922 varop = gen_lowpart_for_combine (mode, varop);
7924 /* If we can't make the SUBREG, try to return what we were given. */
7925 if (GET_CODE (varop) == CLOBBER)
7926 return x ? x : varop;
7928 /* If we are only masking insignificant bits, return VAROP. */
7929 if (constop == nonzero)
7932 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7933 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7934 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7938 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7939 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7940 SUBST (XEXP (x, 1), GEN_INT (constop));
7942 SUBST (XEXP (x, 0), varop);
7948 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7949 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7950 is less useful. We can't allow both, because that results in exponential
7951 run time recursion. There is a nullstone testcase that triggered
7952 this. This macro avoids accidental uses of num_sign_bit_copies. */
7953 #define num_sign_bit_copies()
7955 /* Given an expression, X, compute which bits in X can be non-zero.
7956 We don't care about bits outside of those defined in MODE.
7958 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7959 a shift, AND, or zero_extract, we can do better. */
7961 static unsigned HOST_WIDE_INT
7962 nonzero_bits (x, mode)
7964 enum machine_mode mode;
7966 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7967 unsigned HOST_WIDE_INT inner_nz;
7969 unsigned int mode_width = GET_MODE_BITSIZE (mode);
7972 /* For floating-point values, assume all bits are needed. */
7973 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7976 /* If X is wider than MODE, use its mode instead. */
7977 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7979 mode = GET_MODE (x);
7980 nonzero = GET_MODE_MASK (mode);
7981 mode_width = GET_MODE_BITSIZE (mode);
7984 if (mode_width > HOST_BITS_PER_WIDE_INT)
7985 /* Our only callers in this case look for single bit values. So
7986 just return the mode mask. Those tests will then be false. */
7989 #ifndef WORD_REGISTER_OPERATIONS
7990 /* If MODE is wider than X, but both are a single word for both the host
7991 and target machines, we can compute this from which bits of the
7992 object might be nonzero in its own mode, taking into account the fact
7993 that on many CISC machines, accessing an object in a wider mode
7994 causes the high-order bits to become undefined. So they are
7995 not known to be zero. */
7997 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7998 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7999 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
8000 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
8002 nonzero &= nonzero_bits (x, GET_MODE (x));
8003 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x));
8008 code = GET_CODE (x);
8012 #ifdef POINTERS_EXTEND_UNSIGNED
8013 /* If pointers extend unsigned and this is a pointer in Pmode, say that
8014 all the bits above ptr_mode are known to be zero. */
8015 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8017 nonzero &= GET_MODE_MASK (ptr_mode);
8020 #ifdef STACK_BOUNDARY
8021 /* If this is the stack pointer, we may know something about its
8022 alignment. If PUSH_ROUNDING is defined, it is possible for the
8023 stack to be momentarily aligned only to that amount, so we pick
8024 the least alignment. */
8026 /* We can't check for arg_pointer_rtx here, because it is not
8027 guaranteed to have as much alignment as the stack pointer.
8028 In particular, in the Irix6 n64 ABI, the stack has 128 bit
8029 alignment but the argument pointer has only 64 bit alignment. */
8031 if ((x == frame_pointer_rtx
8032 || x == stack_pointer_rtx
8033 || x == hard_frame_pointer_rtx
8034 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
8035 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
8041 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8043 #ifdef PUSH_ROUNDING
8044 if (REGNO (x) == STACK_POINTER_REGNUM && PUSH_ARGS)
8045 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
8048 /* We must return here, otherwise we may get a worse result from
8049 one of the choices below. There is nothing useful below as
8050 far as the stack pointer is concerned. */
8051 return nonzero &= ~(sp_alignment - 1);
8055 /* If X is a register whose nonzero bits value is current, use it.
8056 Otherwise, if X is a register whose value we can find, use that
8057 value. Otherwise, use the previously-computed global nonzero bits
8058 for this register. */
8060 if (reg_last_set_value[REGNO (x)] != 0
8061 && reg_last_set_mode[REGNO (x)] == mode
8062 && (reg_last_set_label[REGNO (x)] == label_tick
8063 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8064 && REG_N_SETS (REGNO (x)) == 1
8065 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8067 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8068 return reg_last_set_nonzero_bits[REGNO (x)];
8070 tem = get_last_value (x);
8074 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8075 /* If X is narrower than MODE and TEM is a non-negative
8076 constant that would appear negative in the mode of X,
8077 sign-extend it for use in reg_nonzero_bits because some
8078 machines (maybe most) will actually do the sign-extension
8079 and this is the conservative approach.
8081 ??? For 2.5, try to tighten up the MD files in this regard
8082 instead of this kludge. */
8084 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
8085 && GET_CODE (tem) == CONST_INT
8087 && 0 != (INTVAL (tem)
8088 & ((HOST_WIDE_INT) 1
8089 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8090 tem = GEN_INT (INTVAL (tem)
8091 | ((HOST_WIDE_INT) (-1)
8092 << GET_MODE_BITSIZE (GET_MODE (x))));
8094 return nonzero_bits (tem, mode);
8096 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
8097 return reg_nonzero_bits[REGNO (x)] & nonzero;
8102 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8103 /* If X is negative in MODE, sign-extend the value. */
8104 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
8105 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
8106 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
8112 #ifdef LOAD_EXTEND_OP
8113 /* In many, if not most, RISC machines, reading a byte from memory
8114 zeros the rest of the register. Noticing that fact saves a lot
8115 of extra zero-extends. */
8116 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
8117 nonzero &= GET_MODE_MASK (GET_MODE (x));
8122 case UNEQ: case LTGT:
8123 case GT: case GTU: case UNGT:
8124 case LT: case LTU: case UNLT:
8125 case GE: case GEU: case UNGE:
8126 case LE: case LEU: case UNLE:
8127 case UNORDERED: case ORDERED:
8129 /* If this produces an integer result, we know which bits are set.
8130 Code here used to clear bits outside the mode of X, but that is
8133 if (GET_MODE_CLASS (mode) == MODE_INT
8134 && mode_width <= HOST_BITS_PER_WIDE_INT)
8135 nonzero = STORE_FLAG_VALUE;
8140 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8141 and num_sign_bit_copies. */
8142 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8143 == GET_MODE_BITSIZE (GET_MODE (x)))
8147 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
8148 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)));
8153 /* Disabled to avoid exponential mutual recursion between nonzero_bits
8154 and num_sign_bit_copies. */
8155 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
8156 == GET_MODE_BITSIZE (GET_MODE (x)))
8162 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
8166 nonzero &= nonzero_bits (XEXP (x, 0), mode);
8167 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8168 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8172 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8173 Otherwise, show all the bits in the outer mode but not the inner
8175 inner_nz = nonzero_bits (XEXP (x, 0), mode);
8176 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
8178 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
8180 & (((HOST_WIDE_INT) 1
8181 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
8182 inner_nz |= (GET_MODE_MASK (mode)
8183 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
8186 nonzero &= inner_nz;
8190 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8191 & nonzero_bits (XEXP (x, 1), mode));
8195 case UMIN: case UMAX: case SMIN: case SMAX:
8196 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
8197 | nonzero_bits (XEXP (x, 1), mode));
8200 case PLUS: case MINUS:
8202 case DIV: case UDIV:
8203 case MOD: case UMOD:
8204 /* We can apply the rules of arithmetic to compute the number of
8205 high- and low-order zero bits of these operations. We start by
8206 computing the width (position of the highest-order non-zero bit)
8207 and the number of low-order zero bits for each value. */
8209 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
8210 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
8211 int width0 = floor_log2 (nz0) + 1;
8212 int width1 = floor_log2 (nz1) + 1;
8213 int low0 = floor_log2 (nz0 & -nz0);
8214 int low1 = floor_log2 (nz1 & -nz1);
8215 HOST_WIDE_INT op0_maybe_minusp
8216 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8217 HOST_WIDE_INT op1_maybe_minusp
8218 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
8219 unsigned int result_width = mode_width;
8227 && (XEXP (x, 0) == stack_pointer_rtx
8228 || XEXP (x, 0) == frame_pointer_rtx)
8229 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8231 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
8233 nz0 = (GET_MODE_MASK (mode) & ~(sp_alignment - 1));
8234 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
8235 width0 = floor_log2 (nz0) + 1;
8236 width1 = floor_log2 (nz1) + 1;
8237 low0 = floor_log2 (nz0 & -nz0);
8238 low1 = floor_log2 (nz1 & -nz1);
8241 result_width = MAX (width0, width1) + 1;
8242 result_low = MIN (low0, low1);
8245 result_low = MIN (low0, low1);
8248 result_width = width0 + width1;
8249 result_low = low0 + low1;
8252 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8253 result_width = width0;
8256 result_width = width0;
8259 if (! op0_maybe_minusp && ! op1_maybe_minusp)
8260 result_width = MIN (width0, width1);
8261 result_low = MIN (low0, low1);
8264 result_width = MIN (width0, width1);
8265 result_low = MIN (low0, low1);
8271 if (result_width < mode_width)
8272 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
8275 nonzero &= ~(((HOST_WIDE_INT) 1 << result_low) - 1);
8277 #ifdef POINTERS_EXTEND_UNSIGNED
8278 /* If pointers extend unsigned and this is an addition or subtraction
8279 to a pointer in Pmode, all the bits above ptr_mode are known to be
8281 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8282 && (code == PLUS || code == MINUS)
8283 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8284 nonzero &= GET_MODE_MASK (ptr_mode);
8290 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8291 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8292 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
8296 /* If this is a SUBREG formed for a promoted variable that has
8297 been zero-extended, we know that at least the high-order bits
8298 are zero, though others might be too. */
8300 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
8301 nonzero = (GET_MODE_MASK (GET_MODE (x))
8302 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
8304 /* If the inner mode is a single word for both the host and target
8305 machines, we can compute this from which bits of the inner
8306 object might be nonzero. */
8307 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
8308 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8309 <= HOST_BITS_PER_WIDE_INT))
8311 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
8313 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8314 /* If this is a typical RISC machine, we only have to worry
8315 about the way loads are extended. */
8316 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
8318 & (((unsigned HOST_WIDE_INT) 1
8319 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1))))
8321 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
8324 /* On many CISC machines, accessing an object in a wider mode
8325 causes the high-order bits to become undefined. So they are
8326 not known to be zero. */
8327 if (GET_MODE_SIZE (GET_MODE (x))
8328 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8329 nonzero |= (GET_MODE_MASK (GET_MODE (x))
8330 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
8339 /* The nonzero bits are in two classes: any bits within MODE
8340 that aren't in GET_MODE (x) are always significant. The rest of the
8341 nonzero bits are those that are significant in the operand of
8342 the shift when shifted the appropriate number of bits. This
8343 shows that high-order bits are cleared by the right shift and
8344 low-order bits by left shifts. */
8345 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8346 && INTVAL (XEXP (x, 1)) >= 0
8347 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8349 enum machine_mode inner_mode = GET_MODE (x);
8350 unsigned int width = GET_MODE_BITSIZE (inner_mode);
8351 int count = INTVAL (XEXP (x, 1));
8352 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
8353 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
8354 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
8355 unsigned HOST_WIDE_INT outer = 0;
8357 if (mode_width > width)
8358 outer = (op_nonzero & nonzero & ~mode_mask);
8360 if (code == LSHIFTRT)
8362 else if (code == ASHIFTRT)
8366 /* If the sign bit may have been nonzero before the shift, we
8367 need to mark all the places it could have been copied to
8368 by the shift as possibly nonzero. */
8369 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
8370 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
8372 else if (code == ASHIFT)
8375 inner = ((inner << (count % width)
8376 | (inner >> (width - (count % width)))) & mode_mask);
8378 nonzero &= (outer | inner);
8383 /* This is at most the number of bits in the mode. */
8384 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
8388 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
8389 | nonzero_bits (XEXP (x, 2), mode));
8399 /* See the macro definition above. */
8400 #undef num_sign_bit_copies
8402 /* Return the number of bits at the high-order end of X that are known to
8403 be equal to the sign bit. X will be used in mode MODE; if MODE is
8404 VOIDmode, X will be used in its own mode. The returned value will always
8405 be between 1 and the number of bits in MODE. */
8408 num_sign_bit_copies (x, mode)
8410 enum machine_mode mode;
8412 enum rtx_code code = GET_CODE (x);
8413 unsigned int bitwidth;
8414 int num0, num1, result;
8415 unsigned HOST_WIDE_INT nonzero;
8418 /* If we weren't given a mode, use the mode of X. If the mode is still
8419 VOIDmode, we don't know anything. Likewise if one of the modes is
8422 if (mode == VOIDmode)
8423 mode = GET_MODE (x);
8425 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
8428 bitwidth = GET_MODE_BITSIZE (mode);
8430 /* For a smaller object, just ignore the high bits. */
8431 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
8433 num0 = num_sign_bit_copies (x, GET_MODE (x));
8435 num0 - (int) (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth));
8438 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
8440 #ifndef WORD_REGISTER_OPERATIONS
8441 /* If this machine does not do all register operations on the entire
8442 register and MODE is wider than the mode of X, we can say nothing
8443 at all about the high-order bits. */
8446 /* Likewise on machines that do, if the mode of the object is smaller
8447 than a word and loads of that size don't sign extend, we can say
8448 nothing about the high order bits. */
8449 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
8450 #ifdef LOAD_EXTEND_OP
8451 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
8462 #ifdef POINTERS_EXTEND_UNSIGNED
8463 /* If pointers extend signed and this is a pointer in Pmode, say that
8464 all the bits above ptr_mode are known to be sign bit copies. */
8465 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
8467 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
8470 if (reg_last_set_value[REGNO (x)] != 0
8471 && reg_last_set_mode[REGNO (x)] == mode
8472 && (reg_last_set_label[REGNO (x)] == label_tick
8473 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8474 && REG_N_SETS (REGNO (x)) == 1
8475 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
8477 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
8478 return reg_last_set_sign_bit_copies[REGNO (x)];
8480 tem = get_last_value (x);
8482 return num_sign_bit_copies (tem, mode);
8484 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
8485 return reg_sign_bit_copies[REGNO (x)];
8489 #ifdef LOAD_EXTEND_OP
8490 /* Some RISC machines sign-extend all loads of smaller than a word. */
8491 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
8492 return MAX (1, ((int) bitwidth
8493 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1));
8498 /* If the constant is negative, take its 1's complement and remask.
8499 Then see how many zero bits we have. */
8500 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
8501 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8502 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8503 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8505 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8508 /* If this is a SUBREG for a promoted object that is sign-extended
8509 and we are looking at it in a wider mode, we know that at least the
8510 high-order bits are known to be sign bit copies. */
8512 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
8514 num0 = num_sign_bit_copies (SUBREG_REG (x), mode);
8515 return MAX ((int) bitwidth
8516 - (int) GET_MODE_BITSIZE (GET_MODE (x)) + 1,
8520 /* For a smaller object, just ignore the high bits. */
8521 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
8523 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
8524 return MAX (1, (num0
8525 - (int) (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
8529 #ifdef WORD_REGISTER_OPERATIONS
8530 #ifdef LOAD_EXTEND_OP
8531 /* For paradoxical SUBREGs on machines where all register operations
8532 affect the entire register, just look inside. Note that we are
8533 passing MODE to the recursive call, so the number of sign bit copies
8534 will remain relative to that mode, not the inner mode. */
8536 /* This works only if loads sign extend. Otherwise, if we get a
8537 reload for the inner part, it may be loaded from the stack, and
8538 then we lose all sign bit copies that existed before the store
8541 if ((GET_MODE_SIZE (GET_MODE (x))
8542 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8543 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
8544 return num_sign_bit_copies (SUBREG_REG (x), mode);
8550 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
8551 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
8555 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8556 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
8559 /* For a smaller object, just ignore the high bits. */
8560 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
8561 return MAX (1, (num0 - (int) (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
8565 return num_sign_bit_copies (XEXP (x, 0), mode);
8567 case ROTATE: case ROTATERT:
8568 /* If we are rotating left by a number of bits less than the number
8569 of sign bit copies, we can just subtract that amount from the
8571 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8572 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8574 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8575 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8576 : (int) bitwidth - INTVAL (XEXP (x, 1))));
8581 /* In general, this subtracts one sign bit copy. But if the value
8582 is known to be positive, the number of sign bit copies is the
8583 same as that of the input. Finally, if the input has just one bit
8584 that might be nonzero, all the bits are copies of the sign bit. */
8585 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8586 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8587 return num0 > 1 ? num0 - 1 : 1;
8589 nonzero = nonzero_bits (XEXP (x, 0), mode);
8594 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8599 case IOR: case AND: case XOR:
8600 case SMIN: case SMAX: case UMIN: case UMAX:
8601 /* Logical operations will preserve the number of sign-bit copies.
8602 MIN and MAX operations always return one of the operands. */
8603 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8604 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8605 return MIN (num0, num1);
8607 case PLUS: case MINUS:
8608 /* For addition and subtraction, we can have a 1-bit carry. However,
8609 if we are subtracting 1 from a positive number, there will not
8610 be such a carry. Furthermore, if the positive number is known to
8611 be 0 or 1, we know the result is either -1 or 0. */
8613 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8614 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8616 nonzero = nonzero_bits (XEXP (x, 0), mode);
8617 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8618 return (nonzero == 1 || nonzero == 0 ? bitwidth
8619 : bitwidth - floor_log2 (nonzero) - 1);
8622 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8623 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8624 result = MAX (1, MIN (num0, num1) - 1);
8626 #ifdef POINTERS_EXTEND_UNSIGNED
8627 /* If pointers extend signed and this is an addition or subtraction
8628 to a pointer in Pmode, all the bits above ptr_mode are known to be
8630 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
8631 && (code == PLUS || code == MINUS)
8632 && GET_CODE (XEXP (x, 0)) == REG && REG_POINTER (XEXP (x, 0)))
8633 result = MAX ((GET_MODE_BITSIZE (Pmode)
8634 - GET_MODE_BITSIZE (ptr_mode) + 1),
8640 /* The number of bits of the product is the sum of the number of
8641 bits of both terms. However, unless one of the terms if known
8642 to be positive, we must allow for an additional bit since negating
8643 a negative number can remove one sign bit copy. */
8645 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8646 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8648 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8650 && (bitwidth > HOST_BITS_PER_WIDE_INT
8651 || (((nonzero_bits (XEXP (x, 0), mode)
8652 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8653 && ((nonzero_bits (XEXP (x, 1), mode)
8654 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8657 return MAX (1, result);
8660 /* The result must be <= the first operand. If the first operand
8661 has the high bit set, we know nothing about the number of sign
8663 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8665 else if ((nonzero_bits (XEXP (x, 0), mode)
8666 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8669 return num_sign_bit_copies (XEXP (x, 0), mode);
8672 /* The result must be <= the scond operand. */
8673 return num_sign_bit_copies (XEXP (x, 1), mode);
8676 /* Similar to unsigned division, except that we have to worry about
8677 the case where the divisor is negative, in which case we have
8679 result = num_sign_bit_copies (XEXP (x, 0), mode);
8681 && (bitwidth > HOST_BITS_PER_WIDE_INT
8682 || (nonzero_bits (XEXP (x, 1), mode)
8683 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8689 result = num_sign_bit_copies (XEXP (x, 1), mode);
8691 && (bitwidth > HOST_BITS_PER_WIDE_INT
8692 || (nonzero_bits (XEXP (x, 1), mode)
8693 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8699 /* Shifts by a constant add to the number of bits equal to the
8701 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8702 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8703 && INTVAL (XEXP (x, 1)) > 0)
8704 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8709 /* Left shifts destroy copies. */
8710 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8711 || INTVAL (XEXP (x, 1)) < 0
8712 || INTVAL (XEXP (x, 1)) >= bitwidth)
8715 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8716 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8719 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8720 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8721 return MIN (num0, num1);
8723 case EQ: case NE: case GE: case GT: case LE: case LT:
8724 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
8725 case GEU: case GTU: case LEU: case LTU:
8726 case UNORDERED: case ORDERED:
8727 /* If the constant is negative, take its 1's complement and remask.
8728 Then see how many zero bits we have. */
8729 nonzero = STORE_FLAG_VALUE;
8730 if (bitwidth <= HOST_BITS_PER_WIDE_INT
8731 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8732 nonzero = (~nonzero) & GET_MODE_MASK (mode);
8734 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
8741 /* If we haven't been able to figure it out by one of the above rules,
8742 see if some of the high-order bits are known to be zero. If so,
8743 count those bits and return one less than that amount. If we can't
8744 safely compute the mask for this mode, always return BITWIDTH. */
8746 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8749 nonzero = nonzero_bits (x, mode);
8750 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8751 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8754 /* Return the number of "extended" bits there are in X, when interpreted
8755 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8756 unsigned quantities, this is the number of high-order zero bits.
8757 For signed quantities, this is the number of copies of the sign bit
8758 minus 1. In both case, this function returns the number of "spare"
8759 bits. For example, if two quantities for which this function returns
8760 at least 1 are added, the addition is known not to overflow.
8762 This function will always return 0 unless called during combine, which
8763 implies that it must be called from a define_split. */
8766 extended_count (x, mode, unsignedp)
8768 enum machine_mode mode;
8771 if (nonzero_sign_valid == 0)
8775 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8776 ? (GET_MODE_BITSIZE (mode) - 1
8777 - floor_log2 (nonzero_bits (x, mode)))
8779 : num_sign_bit_copies (x, mode) - 1);
8782 /* This function is called from `simplify_shift_const' to merge two
8783 outer operations. Specifically, we have already found that we need
8784 to perform operation *POP0 with constant *PCONST0 at the outermost
8785 position. We would now like to also perform OP1 with constant CONST1
8786 (with *POP0 being done last).
8788 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8789 the resulting operation. *PCOMP_P is set to 1 if we would need to
8790 complement the innermost operand, otherwise it is unchanged.
8792 MODE is the mode in which the operation will be done. No bits outside
8793 the width of this mode matter. It is assumed that the width of this mode
8794 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8796 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8797 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8798 result is simply *PCONST0.
8800 If the resulting operation cannot be expressed as one operation, we
8801 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8804 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8805 enum rtx_code *pop0;
8806 HOST_WIDE_INT *pconst0;
8808 HOST_WIDE_INT const1;
8809 enum machine_mode mode;
8812 enum rtx_code op0 = *pop0;
8813 HOST_WIDE_INT const0 = *pconst0;
8815 const0 &= GET_MODE_MASK (mode);
8816 const1 &= GET_MODE_MASK (mode);
8818 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8822 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8825 if (op1 == NIL || op0 == SET)
8828 else if (op0 == NIL)
8829 op0 = op1, const0 = const1;
8831 else if (op0 == op1)
8855 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8856 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8859 /* If the two constants aren't the same, we can't do anything. The
8860 remaining six cases can all be done. */
8861 else if (const0 != const1)
8869 /* (a & b) | b == b */
8871 else /* op1 == XOR */
8872 /* (a ^ b) | b == a | b */
8878 /* (a & b) ^ b == (~a) & b */
8879 op0 = AND, *pcomp_p = 1;
8880 else /* op1 == IOR */
8881 /* (a | b) ^ b == a & ~b */
8882 op0 = AND, *pconst0 = ~const0;
8887 /* (a | b) & b == b */
8889 else /* op1 == XOR */
8890 /* (a ^ b) & b) == (~a) & b */
8897 /* Check for NO-OP cases. */
8898 const0 &= GET_MODE_MASK (mode);
8900 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8902 else if (const0 == 0 && op0 == AND)
8904 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8908 /* ??? Slightly redundant with the above mask, but not entirely.
8909 Moving this above means we'd have to sign-extend the mode mask
8910 for the final test. */
8911 const0 = trunc_int_for_mode (const0, mode);
8919 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8920 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8921 that we started with.
8923 The shift is normally computed in the widest mode we find in VAROP, as
8924 long as it isn't a different number of words than RESULT_MODE. Exceptions
8925 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8928 simplify_shift_const (x, code, result_mode, varop, input_count)
8931 enum machine_mode result_mode;
8935 enum rtx_code orig_code = code;
8936 int orig_count = input_count;
8939 enum machine_mode mode = result_mode;
8940 enum machine_mode shift_mode, tmode;
8941 unsigned int mode_words
8942 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8943 /* We form (outer_op (code varop count) (outer_const)). */
8944 enum rtx_code outer_op = NIL;
8945 HOST_WIDE_INT outer_const = 0;
8947 int complement_p = 0;
8950 /* If we were given an invalid count, don't do anything except exactly
8951 what was requested. */
8953 if (input_count < 0 || input_count > (int) GET_MODE_BITSIZE (mode))
8958 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (input_count));
8961 count = input_count;
8963 /* Make sure and truncate the "natural" shift on the way in. We don't
8964 want to do this inside the loop as it makes it more difficult to
8966 #ifdef SHIFT_COUNT_TRUNCATED
8967 if (SHIFT_COUNT_TRUNCATED)
8968 count %= GET_MODE_BITSIZE (mode);
8971 /* Unless one of the branches of the `if' in this loop does a `continue',
8972 we will `break' the loop after the `if'. */
8976 /* If we have an operand of (clobber (const_int 0)), just return that
8978 if (GET_CODE (varop) == CLOBBER)
8981 /* If we discovered we had to complement VAROP, leave. Making a NOT
8982 here would cause an infinite loop. */
8986 /* Convert ROTATERT to ROTATE. */
8987 if (code == ROTATERT)
8988 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8990 /* We need to determine what mode we will do the shift in. If the
8991 shift is a right shift or a ROTATE, we must always do it in the mode
8992 it was originally done in. Otherwise, we can do it in MODE, the
8993 widest mode encountered. */
8995 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8996 ? result_mode : mode);
8998 /* Handle cases where the count is greater than the size of the mode
8999 minus 1. For ASHIFT, use the size minus one as the count (this can
9000 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9001 take the count modulo the size. For other shifts, the result is
9004 Since these shifts are being produced by the compiler by combining
9005 multiple operations, each of which are defined, we know what the
9006 result is supposed to be. */
9008 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
9010 if (code == ASHIFTRT)
9011 count = GET_MODE_BITSIZE (shift_mode) - 1;
9012 else if (code == ROTATE || code == ROTATERT)
9013 count %= GET_MODE_BITSIZE (shift_mode);
9016 /* We can't simply return zero because there may be an
9024 /* An arithmetic right shift of a quantity known to be -1 or 0
9026 if (code == ASHIFTRT
9027 && (num_sign_bit_copies (varop, shift_mode)
9028 == GET_MODE_BITSIZE (shift_mode)))
9034 /* If we are doing an arithmetic right shift and discarding all but
9035 the sign bit copies, this is equivalent to doing a shift by the
9036 bitsize minus one. Convert it into that shift because it will often
9037 allow other simplifications. */
9039 if (code == ASHIFTRT
9040 && (count + num_sign_bit_copies (varop, shift_mode)
9041 >= GET_MODE_BITSIZE (shift_mode)))
9042 count = GET_MODE_BITSIZE (shift_mode) - 1;
9044 /* We simplify the tests below and elsewhere by converting
9045 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9046 `make_compound_operation' will convert it to a ASHIFTRT for
9047 those machines (such as Vax) that don't have a LSHIFTRT. */
9048 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9050 && ((nonzero_bits (varop, shift_mode)
9051 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9055 switch (GET_CODE (varop))
9061 new = expand_compound_operation (varop);
9070 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9071 minus the width of a smaller mode, we can do this with a
9072 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9073 if ((code == ASHIFTRT || code == LSHIFTRT)
9074 && ! mode_dependent_address_p (XEXP (varop, 0))
9075 && ! MEM_VOLATILE_P (varop)
9076 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9077 MODE_INT, 1)) != BLKmode)
9079 if (BYTES_BIG_ENDIAN)
9080 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
9082 new = gen_rtx_MEM (tmode,
9083 plus_constant (XEXP (varop, 0),
9084 count / BITS_PER_UNIT));
9086 MEM_COPY_ATTRIBUTES (new, varop);
9087 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9088 : ZERO_EXTEND, mode, new);
9095 /* Similar to the case above, except that we can only do this if
9096 the resulting mode is the same as that of the underlying
9097 MEM and adjust the address depending on the *bits* endianness
9098 because of the way that bit-field extract insns are defined. */
9099 if ((code == ASHIFTRT || code == LSHIFTRT)
9100 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9101 MODE_INT, 1)) != BLKmode
9102 && tmode == GET_MODE (XEXP (varop, 0)))
9104 if (BITS_BIG_ENDIAN)
9105 new = XEXP (varop, 0);
9108 new = copy_rtx (XEXP (varop, 0));
9109 SUBST (XEXP (new, 0),
9110 plus_constant (XEXP (new, 0),
9111 count / BITS_PER_UNIT));
9114 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
9115 : ZERO_EXTEND, mode, new);
9122 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9123 the same number of words as what we've seen so far. Then store
9124 the widest mode in MODE. */
9125 if (subreg_lowpart_p (varop)
9126 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9127 > GET_MODE_SIZE (GET_MODE (varop)))
9128 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9129 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9132 varop = SUBREG_REG (varop);
9133 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9134 mode = GET_MODE (varop);
9140 /* Some machines use MULT instead of ASHIFT because MULT
9141 is cheaper. But it is still better on those machines to
9142 merge two shifts into one. */
9143 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9144 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9147 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
9148 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9154 /* Similar, for when divides are cheaper. */
9155 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9156 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9159 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
9160 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
9166 /* If we are extracting just the sign bit of an arithmetic
9167 right shift, that shift is not needed. However, the sign
9168 bit of a wider mode may be different from what would be
9169 interpreted as the sign bit in a narrower mode, so, if
9170 the result is narrower, don't discard the shift. */
9171 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9172 && (GET_MODE_BITSIZE (result_mode)
9173 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9175 varop = XEXP (varop, 0);
9179 /* ... fall through ... */
9184 /* Here we have two nested shifts. The result is usually the
9185 AND of a new shift with a mask. We compute the result below. */
9186 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9187 && INTVAL (XEXP (varop, 1)) >= 0
9188 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9189 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9190 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9192 enum rtx_code first_code = GET_CODE (varop);
9193 unsigned int first_count = INTVAL (XEXP (varop, 1));
9194 unsigned HOST_WIDE_INT mask;
9197 /* We have one common special case. We can't do any merging if
9198 the inner code is an ASHIFTRT of a smaller mode. However, if
9199 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9200 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9201 we can convert it to
9202 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9203 This simplifies certain SIGN_EXTEND operations. */
9204 if (code == ASHIFT && first_code == ASHIFTRT
9205 && (GET_MODE_BITSIZE (result_mode)
9206 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
9208 /* C3 has the low-order C1 bits zero. */
9210 mask = (GET_MODE_MASK (mode)
9211 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9213 varop = simplify_and_const_int (NULL_RTX, result_mode,
9214 XEXP (varop, 0), mask);
9215 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9217 count = first_count;
9222 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9223 than C1 high-order bits equal to the sign bit, we can convert
9224 this to either an ASHIFT or a ASHIFTRT depending on the
9227 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9229 if (code == ASHIFTRT && first_code == ASHIFT
9230 && GET_MODE (varop) == shift_mode
9231 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9234 varop = XEXP (varop, 0);
9236 signed_count = count - first_count;
9237 if (signed_count < 0)
9238 count = -signed_count, code = ASHIFT;
9240 count = signed_count;
9245 /* There are some cases we can't do. If CODE is ASHIFTRT,
9246 we can only do this if FIRST_CODE is also ASHIFTRT.
9248 We can't do the case when CODE is ROTATE and FIRST_CODE is
9251 If the mode of this shift is not the mode of the outer shift,
9252 we can't do this if either shift is a right shift or ROTATE.
9254 Finally, we can't do any of these if the mode is too wide
9255 unless the codes are the same.
9257 Handle the case where the shift codes are the same
9260 if (code == first_code)
9262 if (GET_MODE (varop) != result_mode
9263 && (code == ASHIFTRT || code == LSHIFTRT
9267 count += first_count;
9268 varop = XEXP (varop, 0);
9272 if (code == ASHIFTRT
9273 || (code == ROTATE && first_code == ASHIFTRT)
9274 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9275 || (GET_MODE (varop) != result_mode
9276 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9277 || first_code == ROTATE
9278 || code == ROTATE)))
9281 /* To compute the mask to apply after the shift, shift the
9282 nonzero bits of the inner shift the same way the
9283 outer shift will. */
9285 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9288 = simplify_binary_operation (code, result_mode, mask_rtx,
9291 /* Give up if we can't compute an outer operation to use. */
9293 || GET_CODE (mask_rtx) != CONST_INT
9294 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9296 result_mode, &complement_p))
9299 /* If the shifts are in the same direction, we add the
9300 counts. Otherwise, we subtract them. */
9301 signed_count = count;
9302 if ((code == ASHIFTRT || code == LSHIFTRT)
9303 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9304 signed_count += first_count;
9306 signed_count -= first_count;
9308 /* If COUNT is positive, the new shift is usually CODE,
9309 except for the two exceptions below, in which case it is
9310 FIRST_CODE. If the count is negative, FIRST_CODE should
9312 if (signed_count > 0
9313 && ((first_code == ROTATE && code == ASHIFT)
9314 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9315 code = first_code, count = signed_count;
9316 else if (signed_count < 0)
9317 code = first_code, count = -signed_count;
9319 count = signed_count;
9321 varop = XEXP (varop, 0);
9325 /* If we have (A << B << C) for any shift, we can convert this to
9326 (A << C << B). This wins if A is a constant. Only try this if
9327 B is not a constant. */
9329 else if (GET_CODE (varop) == code
9330 && GET_CODE (XEXP (varop, 1)) != CONST_INT
9332 = simplify_binary_operation (code, mode,
9336 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
9343 /* Make this fit the case below. */
9344 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
9345 GEN_INT (GET_MODE_MASK (mode)));
9351 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9352 with C the size of VAROP - 1 and the shift is logical if
9353 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9354 we have an (le X 0) operation. If we have an arithmetic shift
9355 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9356 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9358 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9359 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9360 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9361 && (code == LSHIFTRT || code == ASHIFTRT)
9362 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9363 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9366 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
9369 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9370 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9375 /* If we have (shift (logical)), move the logical to the outside
9376 to allow it to possibly combine with another logical and the
9377 shift to combine with another shift. This also canonicalizes to
9378 what a ZERO_EXTRACT looks like. Also, some machines have
9379 (and (shift)) insns. */
9381 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9382 && (new = simplify_binary_operation (code, result_mode,
9384 GEN_INT (count))) != 0
9385 && GET_CODE (new) == CONST_INT
9386 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9387 INTVAL (new), result_mode, &complement_p))
9389 varop = XEXP (varop, 0);
9393 /* If we can't do that, try to simplify the shift in each arm of the
9394 logical expression, make a new logical expression, and apply
9395 the inverse distributive law. */
9397 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9398 XEXP (varop, 0), count);
9399 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9400 XEXP (varop, 1), count);
9402 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
9403 varop = apply_distributive_law (varop);
9410 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9411 says that the sign bit can be tested, FOO has mode MODE, C is
9412 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9413 that may be nonzero. */
9414 if (code == LSHIFTRT
9415 && XEXP (varop, 1) == const0_rtx
9416 && GET_MODE (XEXP (varop, 0)) == result_mode
9417 && count == GET_MODE_BITSIZE (result_mode) - 1
9418 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9419 && ((STORE_FLAG_VALUE
9420 & ((HOST_WIDE_INT) 1
9421 < (GET_MODE_BITSIZE (result_mode) - 1))))
9422 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9423 && merge_outer_ops (&outer_op, &outer_const, XOR,
9424 (HOST_WIDE_INT) 1, result_mode,
9427 varop = XEXP (varop, 0);
9434 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9435 than the number of bits in the mode is equivalent to A. */
9436 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9437 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9439 varop = XEXP (varop, 0);
9444 /* NEG commutes with ASHIFT since it is multiplication. Move the
9445 NEG outside to allow shifts to combine. */
9447 && merge_outer_ops (&outer_op, &outer_const, NEG,
9448 (HOST_WIDE_INT) 0, result_mode,
9451 varop = XEXP (varop, 0);
9457 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9458 is one less than the number of bits in the mode is
9459 equivalent to (xor A 1). */
9460 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
9461 && XEXP (varop, 1) == constm1_rtx
9462 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9463 && merge_outer_ops (&outer_op, &outer_const, XOR,
9464 (HOST_WIDE_INT) 1, result_mode,
9468 varop = XEXP (varop, 0);
9472 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9473 that might be nonzero in BAR are those being shifted out and those
9474 bits are known zero in FOO, we can replace the PLUS with FOO.
9475 Similarly in the other operand order. This code occurs when
9476 we are computing the size of a variable-size array. */
9478 if ((code == ASHIFTRT || code == LSHIFTRT)
9479 && count < HOST_BITS_PER_WIDE_INT
9480 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9481 && (nonzero_bits (XEXP (varop, 1), result_mode)
9482 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9484 varop = XEXP (varop, 0);
9487 else if ((code == ASHIFTRT || code == LSHIFTRT)
9488 && count < HOST_BITS_PER_WIDE_INT
9489 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9490 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9492 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9493 & nonzero_bits (XEXP (varop, 1),
9496 varop = XEXP (varop, 1);
9500 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9502 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9503 && (new = simplify_binary_operation (ASHIFT, result_mode,
9505 GEN_INT (count))) != 0
9506 && GET_CODE (new) == CONST_INT
9507 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9508 INTVAL (new), result_mode, &complement_p))
9510 varop = XEXP (varop, 0);
9516 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9517 with C the size of VAROP - 1 and the shift is logical if
9518 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9519 we have a (gt X 0) operation. If the shift is arithmetic with
9520 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9521 we have a (neg (gt X 0)) operation. */
9523 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9524 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9525 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
9526 && (code == LSHIFTRT || code == ASHIFTRT)
9527 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9528 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9529 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9532 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
9535 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9536 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
9543 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9544 if the truncate does not affect the value. */
9545 if (code == LSHIFTRT
9546 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9547 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9548 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9549 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9550 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9552 rtx varop_inner = XEXP (varop, 0);
9555 = gen_rtx_combine (LSHIFTRT, GET_MODE (varop_inner),
9556 XEXP (varop_inner, 0),
9558 + INTVAL (XEXP (varop_inner, 1))));
9559 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
9573 /* We need to determine what mode to do the shift in. If the shift is
9574 a right shift or ROTATE, we must always do it in the mode it was
9575 originally done in. Otherwise, we can do it in MODE, the widest mode
9576 encountered. The code we care about is that of the shift that will
9577 actually be done, not the shift that was originally requested. */
9579 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9580 ? result_mode : mode);
9582 /* We have now finished analyzing the shift. The result should be
9583 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9584 OUTER_OP is non-NIL, it is an operation that needs to be applied
9585 to the result of the shift. OUTER_CONST is the relevant constant,
9586 but we must turn off all bits turned off in the shift.
9588 If we were passed a value for X, see if we can use any pieces of
9589 it. If not, make new rtx. */
9591 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
9592 && GET_CODE (XEXP (x, 1)) == CONST_INT
9593 && INTVAL (XEXP (x, 1)) == count)
9594 const_rtx = XEXP (x, 1);
9596 const_rtx = GEN_INT (count);
9598 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9599 && GET_MODE (XEXP (x, 0)) == shift_mode
9600 && SUBREG_REG (XEXP (x, 0)) == varop)
9601 varop = XEXP (x, 0);
9602 else if (GET_MODE (varop) != shift_mode)
9603 varop = gen_lowpart_for_combine (shift_mode, varop);
9605 /* If we can't make the SUBREG, try to return what we were given. */
9606 if (GET_CODE (varop) == CLOBBER)
9607 return x ? x : varop;
9609 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9614 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9615 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9617 SUBST (XEXP (x, 0), varop);
9618 SUBST (XEXP (x, 1), const_rtx);
9621 /* If we have an outer operation and we just made a shift, it is
9622 possible that we could have simplified the shift were it not
9623 for the outer operation. So try to do the simplification
9626 if (outer_op != NIL && GET_CODE (x) == code
9627 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9628 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9629 INTVAL (XEXP (x, 1)));
9631 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9632 turn off all the bits that the shift would have turned off. */
9633 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9634 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9635 GET_MODE_MASK (result_mode) >> orig_count);
9637 /* Do the remainder of the processing in RESULT_MODE. */
9638 x = gen_lowpart_for_combine (result_mode, x);
9640 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9643 x = gen_unary (NOT, result_mode, result_mode, x);
9645 if (outer_op != NIL)
9647 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9648 outer_const = trunc_int_for_mode (outer_const, result_mode);
9650 if (outer_op == AND)
9651 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9652 else if (outer_op == SET)
9653 /* This means that we have determined that the result is
9654 equivalent to a constant. This should be rare. */
9655 x = GEN_INT (outer_const);
9656 else if (GET_RTX_CLASS (outer_op) == '1')
9657 x = gen_unary (outer_op, result_mode, result_mode, x);
9659 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9665 /* Like recog, but we receive the address of a pointer to a new pattern.
9666 We try to match the rtx that the pointer points to.
9667 If that fails, we may try to modify or replace the pattern,
9668 storing the replacement into the same pointer object.
9670 Modifications include deletion or addition of CLOBBERs.
9672 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9673 the CLOBBERs are placed.
9675 The value is the final insn code from the pattern ultimately matched,
9679 recog_for_combine (pnewpat, insn, pnotes)
9684 register rtx pat = *pnewpat;
9685 int insn_code_number;
9686 int num_clobbers_to_add = 0;
9691 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9692 we use to indicate that something didn't match. If we find such a
9693 thing, force rejection. */
9694 if (GET_CODE (pat) == PARALLEL)
9695 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9696 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9697 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9700 /* Remove the old notes prior to trying to recognize the new pattern. */
9701 old_notes = REG_NOTES (insn);
9702 REG_NOTES (insn) = 0;
9704 /* Is the result of combination a valid instruction? */
9705 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9707 /* If it isn't, there is the possibility that we previously had an insn
9708 that clobbered some register as a side effect, but the combined
9709 insn doesn't need to do that. So try once more without the clobbers
9710 unless this represents an ASM insn. */
9712 if (insn_code_number < 0 && ! check_asm_operands (pat)
9713 && GET_CODE (pat) == PARALLEL)
9717 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9718 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9721 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9725 SUBST_INT (XVECLEN (pat, 0), pos);
9728 pat = XVECEXP (pat, 0, 0);
9730 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9733 REG_NOTES (insn) = old_notes;
9735 /* If we had any clobbers to add, make a new pattern than contains
9736 them. Then check to make sure that all of them are dead. */
9737 if (num_clobbers_to_add)
9739 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9740 rtvec_alloc (GET_CODE (pat) == PARALLEL
9742 + num_clobbers_to_add)
9743 : num_clobbers_to_add + 1));
9745 if (GET_CODE (pat) == PARALLEL)
9746 for (i = 0; i < XVECLEN (pat, 0); i++)
9747 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9749 XVECEXP (newpat, 0, 0) = pat;
9751 add_clobbers (newpat, insn_code_number);
9753 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9754 i < XVECLEN (newpat, 0); i++)
9756 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9757 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9759 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9760 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9768 return insn_code_number;
9771 /* Like gen_lowpart but for use by combine. In combine it is not possible
9772 to create any new pseudoregs. However, it is safe to create
9773 invalid memory addresses, because combine will try to recognize
9774 them and all they will do is make the combine attempt fail.
9776 If for some reason this cannot do its job, an rtx
9777 (clobber (const_int 0)) is returned.
9778 An insn containing that will not be recognized. */
9783 gen_lowpart_for_combine (mode, x)
9784 enum machine_mode mode;
9789 if (GET_MODE (x) == mode)
9792 /* We can only support MODE being wider than a word if X is a
9793 constant integer or has a mode the same size. */
9795 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9796 && ! ((GET_MODE (x) == VOIDmode
9797 && (GET_CODE (x) == CONST_INT
9798 || GET_CODE (x) == CONST_DOUBLE))
9799 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9800 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9802 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9803 won't know what to do. So we will strip off the SUBREG here and
9804 process normally. */
9805 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9808 if (GET_MODE (x) == mode)
9812 result = gen_lowpart_common (mode, x);
9813 #ifdef CLASS_CANNOT_CHANGE_MODE
9815 && GET_CODE (result) == SUBREG
9816 && GET_CODE (SUBREG_REG (result)) == REG
9817 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9818 && CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (result),
9819 GET_MODE (SUBREG_REG (result))))
9820 REG_CHANGES_MODE (REGNO (SUBREG_REG (result))) = 1;
9826 if (GET_CODE (x) == MEM)
9828 register int offset = 0;
9831 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9833 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9834 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9836 /* If we want to refer to something bigger than the original memref,
9837 generate a perverse subreg instead. That will force a reload
9838 of the original memref X. */
9839 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9840 return gen_rtx_SUBREG (mode, x, 0);
9842 if (WORDS_BIG_ENDIAN)
9843 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9844 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9846 if (BYTES_BIG_ENDIAN)
9848 /* Adjust the address so that the address-after-the-data is
9850 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9851 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9853 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9854 MEM_COPY_ATTRIBUTES (new, x);
9858 /* If X is a comparison operator, rewrite it in a new mode. This
9859 probably won't match, but may allow further simplifications. */
9860 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9861 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9863 /* If we couldn't simplify X any other way, just enclose it in a
9864 SUBREG. Normally, this SUBREG won't match, but some patterns may
9865 include an explicit SUBREG or we may simplify it further in combine. */
9870 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9871 word = ((GET_MODE_SIZE (GET_MODE (x))
9872 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9874 return gen_rtx_SUBREG (mode, x, word);
9878 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9879 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9881 If the identical expression was previously in the insn (in the undobuf),
9882 it will be returned. Only if it is not found will a new expression
9887 gen_rtx_combine VPARAMS ((enum rtx_code code, enum machine_mode mode, ...))
9889 #ifndef ANSI_PROTOTYPES
9891 enum machine_mode mode;
9903 #ifndef ANSI_PROTOTYPES
9904 code = va_arg (p, enum rtx_code);
9905 mode = va_arg (p, enum machine_mode);
9908 n_args = GET_RTX_LENGTH (code);
9909 fmt = GET_RTX_FORMAT (code);
9911 if (n_args == 0 || n_args > 3)
9914 /* Get each arg and verify that it is supposed to be an expression. */
9915 for (j = 0; j < n_args; j++)
9920 args[j] = va_arg (p, rtx);
9925 /* See if this is in undobuf. Be sure we don't use objects that came
9926 from another insn; this could produce circular rtl structures. */
9928 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9930 && GET_CODE (undo->old_contents.r) == code
9931 && GET_MODE (undo->old_contents.r) == mode)
9933 for (j = 0; j < n_args; j++)
9934 if (XEXP (undo->old_contents.r, j) != args[j])
9938 return undo->old_contents.r;
9941 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9942 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9943 rt = rtx_alloc (code);
9944 PUT_MODE (rt, mode);
9945 XEXP (rt, 0) = args[0];
9948 XEXP (rt, 1) = args[1];
9950 XEXP (rt, 2) = args[2];
9955 /* These routines make binary and unary operations by first seeing if they
9956 fold; if not, a new expression is allocated. */
9959 gen_binary (code, mode, op0, op1)
9961 enum machine_mode mode;
9967 if (GET_RTX_CLASS (code) == 'c'
9968 && (GET_CODE (op0) == CONST_INT
9969 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9970 tem = op0, op0 = op1, op1 = tem;
9972 if (GET_RTX_CLASS (code) == '<')
9974 enum machine_mode op_mode = GET_MODE (op0);
9976 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9977 just (REL_OP X Y). */
9978 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9980 op1 = XEXP (op0, 1);
9981 op0 = XEXP (op0, 0);
9982 op_mode = GET_MODE (op0);
9985 if (op_mode == VOIDmode)
9986 op_mode = GET_MODE (op1);
9987 result = simplify_relational_operation (code, op_mode, op0, op1);
9990 result = simplify_binary_operation (code, mode, op0, op1);
9995 /* Put complex operands first and constants second. */
9996 if (GET_RTX_CLASS (code) == 'c'
9997 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9998 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9999 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
10000 || (GET_CODE (op0) == SUBREG
10001 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
10002 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
10003 return gen_rtx_combine (code, mode, op1, op0);
10005 /* If we are turning off bits already known off in OP0, we need not do
10007 else if (code == AND && GET_CODE (op1) == CONST_INT
10008 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10009 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
10012 return gen_rtx_combine (code, mode, op0, op1);
10016 gen_unary (code, mode, op0_mode, op0)
10017 enum rtx_code code;
10018 enum machine_mode mode, op0_mode;
10021 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
10026 return gen_rtx_combine (code, mode, op0);
10029 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
10030 comparison code that will be tested.
10032 The result is a possibly different comparison code to use. *POP0 and
10033 *POP1 may be updated.
10035 It is possible that we might detect that a comparison is either always
10036 true or always false. However, we do not perform general constant
10037 folding in combine, so this knowledge isn't useful. Such tautologies
10038 should have been detected earlier. Hence we ignore all such cases. */
10040 static enum rtx_code
10041 simplify_comparison (code, pop0, pop1)
10042 enum rtx_code code;
10050 enum machine_mode mode, tmode;
10052 /* Try a few ways of applying the same transformation to both operands. */
10055 #ifndef WORD_REGISTER_OPERATIONS
10056 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10057 so check specially. */
10058 if (code != GTU && code != GEU && code != LTU && code != LEU
10059 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10060 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10061 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10062 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10063 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10064 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10065 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10066 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10067 && GET_CODE (XEXP (op1, 1)) == CONST_INT
10068 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10069 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
10070 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
10071 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
10072 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
10073 && (INTVAL (XEXP (op0, 1))
10074 == (GET_MODE_BITSIZE (GET_MODE (op0))
10075 - (GET_MODE_BITSIZE
10076 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10078 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10079 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10083 /* If both operands are the same constant shift, see if we can ignore the
10084 shift. We can if the shift is a rotate or if the bits shifted out of
10085 this shift are known to be zero for both inputs and if the type of
10086 comparison is compatible with the shift. */
10087 if (GET_CODE (op0) == GET_CODE (op1)
10088 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10089 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10090 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10091 && (code != GT && code != LT && code != GE && code != LE))
10092 || (GET_CODE (op0) == ASHIFTRT
10093 && (code != GTU && code != LTU
10094 && code != GEU && code != GEU)))
10095 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10096 && INTVAL (XEXP (op0, 1)) >= 0
10097 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10098 && XEXP (op0, 1) == XEXP (op1, 1))
10100 enum machine_mode mode = GET_MODE (op0);
10101 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10102 int shift_count = INTVAL (XEXP (op0, 1));
10104 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10105 mask &= (mask >> shift_count) << shift_count;
10106 else if (GET_CODE (op0) == ASHIFT)
10107 mask = (mask & (mask << shift_count)) >> shift_count;
10109 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10110 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10111 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10116 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10117 SUBREGs are of the same mode, and, in both cases, the AND would
10118 be redundant if the comparison was done in the narrower mode,
10119 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10120 and the operand's possibly nonzero bits are 0xffffff01; in that case
10121 if we only care about QImode, we don't need the AND). This case
10122 occurs if the output mode of an scc insn is not SImode and
10123 STORE_FLAG_VALUE == 1 (e.g., the 386).
10125 Similarly, check for a case where the AND's are ZERO_EXTEND
10126 operations from some narrower mode even though a SUBREG is not
10129 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10130 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10131 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10133 rtx inner_op0 = XEXP (op0, 0);
10134 rtx inner_op1 = XEXP (op1, 0);
10135 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10136 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10139 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10140 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10141 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10142 && (GET_MODE (SUBREG_REG (inner_op0))
10143 == GET_MODE (SUBREG_REG (inner_op1)))
10144 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10145 <= HOST_BITS_PER_WIDE_INT)
10146 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10147 GET_MODE (SUBREG_REG (inner_op0)))))
10148 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10149 GET_MODE (SUBREG_REG (inner_op1))))))
10151 op0 = SUBREG_REG (inner_op0);
10152 op1 = SUBREG_REG (inner_op1);
10154 /* The resulting comparison is always unsigned since we masked
10155 off the original sign bit. */
10156 code = unsigned_condition (code);
10162 for (tmode = GET_CLASS_NARROWEST_MODE
10163 (GET_MODE_CLASS (GET_MODE (op0)));
10164 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10165 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10167 op0 = gen_lowpart_for_combine (tmode, inner_op0);
10168 op1 = gen_lowpart_for_combine (tmode, inner_op1);
10169 code = unsigned_condition (code);
10178 /* If both operands are NOT, we can strip off the outer operation
10179 and adjust the comparison code for swapped operands; similarly for
10180 NEG, except that this must be an equality comparison. */
10181 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10182 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10183 && (code == EQ || code == NE)))
10184 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10190 /* If the first operand is a constant, swap the operands and adjust the
10191 comparison code appropriately, but don't do this if the second operand
10192 is already a constant integer. */
10193 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
10195 tem = op0, op0 = op1, op1 = tem;
10196 code = swap_condition (code);
10199 /* We now enter a loop during which we will try to simplify the comparison.
10200 For the most part, we only are concerned with comparisons with zero,
10201 but some things may really be comparisons with zero but not start
10202 out looking that way. */
10204 while (GET_CODE (op1) == CONST_INT)
10206 enum machine_mode mode = GET_MODE (op0);
10207 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10208 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10209 int equality_comparison_p;
10210 int sign_bit_comparison_p;
10211 int unsigned_comparison_p;
10212 HOST_WIDE_INT const_op;
10214 /* We only want to handle integral modes. This catches VOIDmode,
10215 CCmode, and the floating-point modes. An exception is that we
10216 can handle VOIDmode if OP0 is a COMPARE or a comparison
10219 if (GET_MODE_CLASS (mode) != MODE_INT
10220 && ! (mode == VOIDmode
10221 && (GET_CODE (op0) == COMPARE
10222 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
10225 /* Get the constant we are comparing against and turn off all bits
10226 not on in our mode. */
10227 const_op = trunc_int_for_mode (INTVAL (op1), mode);
10229 /* If we are comparing against a constant power of two and the value
10230 being compared can only have that single bit nonzero (e.g., it was
10231 `and'ed with that bit), we can replace this with a comparison
10234 && (code == EQ || code == NE || code == GE || code == GEU
10235 || code == LT || code == LTU)
10236 && mode_width <= HOST_BITS_PER_WIDE_INT
10237 && exact_log2 (const_op) >= 0
10238 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10240 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10241 op1 = const0_rtx, const_op = 0;
10244 /* Similarly, if we are comparing a value known to be either -1 or
10245 0 with -1, change it to the opposite comparison against zero. */
10248 && (code == EQ || code == NE || code == GT || code == LE
10249 || code == GEU || code == LTU)
10250 && num_sign_bit_copies (op0, mode) == mode_width)
10252 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10253 op1 = const0_rtx, const_op = 0;
10256 /* Do some canonicalizations based on the comparison code. We prefer
10257 comparisons against zero and then prefer equality comparisons.
10258 If we can reduce the size of a constant, we will do that too. */
10263 /* < C is equivalent to <= (C - 1) */
10267 op1 = GEN_INT (const_op);
10269 /* ... fall through to LE case below. */
10275 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10279 op1 = GEN_INT (const_op);
10283 /* If we are doing a <= 0 comparison on a value known to have
10284 a zero sign bit, we can replace this with == 0. */
10285 else if (const_op == 0
10286 && mode_width <= HOST_BITS_PER_WIDE_INT
10287 && (nonzero_bits (op0, mode)
10288 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10293 /* >= C is equivalent to > (C - 1). */
10297 op1 = GEN_INT (const_op);
10299 /* ... fall through to GT below. */
10305 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10309 op1 = GEN_INT (const_op);
10313 /* If we are doing a > 0 comparison on a value known to have
10314 a zero sign bit, we can replace this with != 0. */
10315 else if (const_op == 0
10316 && mode_width <= HOST_BITS_PER_WIDE_INT
10317 && (nonzero_bits (op0, mode)
10318 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10323 /* < C is equivalent to <= (C - 1). */
10327 op1 = GEN_INT (const_op);
10329 /* ... fall through ... */
10332 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10333 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10334 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10336 const_op = 0, op1 = const0_rtx;
10344 /* unsigned <= 0 is equivalent to == 0 */
10348 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10349 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10350 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10352 const_op = 0, op1 = const0_rtx;
10358 /* >= C is equivalent to < (C - 1). */
10362 op1 = GEN_INT (const_op);
10364 /* ... fall through ... */
10367 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10368 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10369 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10371 const_op = 0, op1 = const0_rtx;
10379 /* unsigned > 0 is equivalent to != 0 */
10383 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10384 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10385 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10387 const_op = 0, op1 = const0_rtx;
10396 /* Compute some predicates to simplify code below. */
10398 equality_comparison_p = (code == EQ || code == NE);
10399 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10400 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10403 /* If this is a sign bit comparison and we can do arithmetic in
10404 MODE, say that we will only be needing the sign bit of OP0. */
10405 if (sign_bit_comparison_p
10406 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10407 op0 = force_to_mode (op0, mode,
10409 << (GET_MODE_BITSIZE (mode) - 1)),
10412 /* Now try cases based on the opcode of OP0. If none of the cases
10413 does a "continue", we exit this loop immediately after the
10416 switch (GET_CODE (op0))
10419 /* If we are extracting a single bit from a variable position in
10420 a constant that has only a single bit set and are comparing it
10421 with zero, we can convert this into an equality comparison
10422 between the position and the location of the single bit. */
10424 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
10425 && XEXP (op0, 1) == const1_rtx
10426 && equality_comparison_p && const_op == 0
10427 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10429 if (BITS_BIG_ENDIAN)
10432 mode = insn_data[(int) CODE_FOR_extzv].operand[1].mode;
10433 if (mode == VOIDmode)
10435 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10437 i = BITS_PER_WORD - 1 - i;
10441 op0 = XEXP (op0, 2);
10445 /* Result is nonzero iff shift count is equal to I. */
10446 code = reverse_condition (code);
10450 /* ... fall through ... */
10453 tem = expand_compound_operation (op0);
10462 /* If testing for equality, we can take the NOT of the constant. */
10463 if (equality_comparison_p
10464 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10466 op0 = XEXP (op0, 0);
10471 /* If just looking at the sign bit, reverse the sense of the
10473 if (sign_bit_comparison_p)
10475 op0 = XEXP (op0, 0);
10476 code = (code == GE ? LT : GE);
10482 /* If testing for equality, we can take the NEG of the constant. */
10483 if (equality_comparison_p
10484 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10486 op0 = XEXP (op0, 0);
10491 /* The remaining cases only apply to comparisons with zero. */
10495 /* When X is ABS or is known positive,
10496 (neg X) is < 0 if and only if X != 0. */
10498 if (sign_bit_comparison_p
10499 && (GET_CODE (XEXP (op0, 0)) == ABS
10500 || (mode_width <= HOST_BITS_PER_WIDE_INT
10501 && (nonzero_bits (XEXP (op0, 0), mode)
10502 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10504 op0 = XEXP (op0, 0);
10505 code = (code == LT ? NE : EQ);
10509 /* If we have NEG of something whose two high-order bits are the
10510 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10511 if (num_sign_bit_copies (op0, mode) >= 2)
10513 op0 = XEXP (op0, 0);
10514 code = swap_condition (code);
10520 /* If we are testing equality and our count is a constant, we
10521 can perform the inverse operation on our RHS. */
10522 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10523 && (tem = simplify_binary_operation (ROTATERT, mode,
10524 op1, XEXP (op0, 1))) != 0)
10526 op0 = XEXP (op0, 0);
10531 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10532 a particular bit. Convert it to an AND of a constant of that
10533 bit. This will be converted into a ZERO_EXTRACT. */
10534 if (const_op == 0 && sign_bit_comparison_p
10535 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10536 && mode_width <= HOST_BITS_PER_WIDE_INT)
10538 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10541 - INTVAL (XEXP (op0, 1)))));
10542 code = (code == LT ? NE : EQ);
10546 /* Fall through. */
10549 /* ABS is ignorable inside an equality comparison with zero. */
10550 if (const_op == 0 && equality_comparison_p)
10552 op0 = XEXP (op0, 0);
10558 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10559 to (compare FOO CONST) if CONST fits in FOO's mode and we
10560 are either testing inequality or have an unsigned comparison
10561 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10562 if (! unsigned_comparison_p
10563 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10564 <= HOST_BITS_PER_WIDE_INT)
10565 && ((unsigned HOST_WIDE_INT) const_op
10566 < (((unsigned HOST_WIDE_INT) 1
10567 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
10569 op0 = XEXP (op0, 0);
10575 /* Check for the case where we are comparing A - C1 with C2,
10576 both constants are smaller than 1/2 the maximum positive
10577 value in MODE, and the comparison is equality or unsigned.
10578 In that case, if A is either zero-extended to MODE or has
10579 sufficient sign bits so that the high-order bit in MODE
10580 is a copy of the sign in the inner mode, we can prove that it is
10581 safe to do the operation in the wider mode. This simplifies
10582 many range checks. */
10584 if (mode_width <= HOST_BITS_PER_WIDE_INT
10585 && subreg_lowpart_p (op0)
10586 && GET_CODE (SUBREG_REG (op0)) == PLUS
10587 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10588 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10589 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10590 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10591 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10592 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10593 GET_MODE (SUBREG_REG (op0)))
10594 & ~GET_MODE_MASK (mode))
10595 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10596 GET_MODE (SUBREG_REG (op0)))
10597 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10598 - GET_MODE_BITSIZE (mode)))))
10600 op0 = SUBREG_REG (op0);
10604 /* If the inner mode is narrower and we are extracting the low part,
10605 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10606 if (subreg_lowpart_p (op0)
10607 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10608 /* Fall through */ ;
10612 /* ... fall through ... */
10615 if ((unsigned_comparison_p || equality_comparison_p)
10616 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10617 <= HOST_BITS_PER_WIDE_INT)
10618 && ((unsigned HOST_WIDE_INT) const_op
10619 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10621 op0 = XEXP (op0, 0);
10627 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10628 this for equality comparisons due to pathological cases involving
10630 if (equality_comparison_p
10631 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10632 op1, XEXP (op0, 1))))
10634 op0 = XEXP (op0, 0);
10639 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10640 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10641 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10643 op0 = XEXP (XEXP (op0, 0), 0);
10644 code = (code == LT ? EQ : NE);
10650 /* We used to optimize signed comparisons against zero, but that
10651 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10652 arrive here as equality comparisons, or (GEU, LTU) are
10653 optimized away. No need to special-case them. */
10655 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10656 (eq B (minus A C)), whichever simplifies. We can only do
10657 this for equality comparisons due to pathological cases involving
10659 if (equality_comparison_p
10660 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10661 XEXP (op0, 1), op1)))
10663 op0 = XEXP (op0, 0);
10668 if (equality_comparison_p
10669 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10670 XEXP (op0, 0), op1)))
10672 op0 = XEXP (op0, 1);
10677 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10678 of bits in X minus 1, is one iff X > 0. */
10679 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10680 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10681 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10682 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10684 op0 = XEXP (op0, 1);
10685 code = (code == GE ? LE : GT);
10691 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10692 if C is zero or B is a constant. */
10693 if (equality_comparison_p
10694 && 0 != (tem = simplify_binary_operation (XOR, mode,
10695 XEXP (op0, 1), op1)))
10697 op0 = XEXP (op0, 0);
10704 case UNEQ: case LTGT:
10705 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10706 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10707 case UNORDERED: case ORDERED:
10708 /* We can't do anything if OP0 is a condition code value, rather
10709 than an actual data value. */
10712 || XEXP (op0, 0) == cc0_rtx
10714 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10717 /* Get the two operands being compared. */
10718 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10719 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10721 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10723 /* Check for the cases where we simply want the result of the
10724 earlier test or the opposite of that result. */
10725 if (code == NE || code == EQ
10726 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10727 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10728 && (STORE_FLAG_VALUE
10729 & (((HOST_WIDE_INT) 1
10730 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10731 && (code == LT || code == GE)))
10733 enum rtx_code new_code;
10734 if (code == LT || code == NE)
10735 new_code = GET_CODE (op0);
10737 new_code = combine_reversed_comparison_code (op0);
10739 if (new_code != UNKNOWN)
10750 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10752 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10753 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10754 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10756 op0 = XEXP (op0, 1);
10757 code = (code == GE ? GT : LE);
10763 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10764 will be converted to a ZERO_EXTRACT later. */
10765 if (const_op == 0 && equality_comparison_p
10766 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10767 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10769 op0 = simplify_and_const_int
10770 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10772 XEXP (XEXP (op0, 0), 1)),
10773 (HOST_WIDE_INT) 1);
10777 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10778 zero and X is a comparison and C1 and C2 describe only bits set
10779 in STORE_FLAG_VALUE, we can compare with X. */
10780 if (const_op == 0 && equality_comparison_p
10781 && mode_width <= HOST_BITS_PER_WIDE_INT
10782 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10783 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10784 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10785 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10786 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10788 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10789 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10790 if ((~STORE_FLAG_VALUE & mask) == 0
10791 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10792 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10793 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10795 op0 = XEXP (XEXP (op0, 0), 0);
10800 /* If we are doing an equality comparison of an AND of a bit equal
10801 to the sign bit, replace this with a LT or GE comparison of
10802 the underlying value. */
10803 if (equality_comparison_p
10805 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10806 && mode_width <= HOST_BITS_PER_WIDE_INT
10807 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10808 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10810 op0 = XEXP (op0, 0);
10811 code = (code == EQ ? GE : LT);
10815 /* If this AND operation is really a ZERO_EXTEND from a narrower
10816 mode, the constant fits within that mode, and this is either an
10817 equality or unsigned comparison, try to do this comparison in
10818 the narrower mode. */
10819 if ((equality_comparison_p || unsigned_comparison_p)
10820 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10821 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10822 & GET_MODE_MASK (mode))
10824 && const_op >> i == 0
10825 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10827 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10831 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10832 in both M1 and M2 and the SUBREG is either paradoxical or
10833 represents the low part, permute the SUBREG and the AND and
10835 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10837 #ifdef WORD_REGISTER_OPERATIONS
10839 > (GET_MODE_BITSIZE
10840 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10841 && mode_width <= BITS_PER_WORD)
10844 <= (GET_MODE_BITSIZE
10845 (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10846 && subreg_lowpart_p (XEXP (op0, 0))))
10847 #ifndef WORD_REGISTER_OPERATIONS
10848 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10849 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10850 As originally written the upper bits have a defined value
10851 due to the AND operation. However, if we commute the AND
10852 inside the SUBREG then they no longer have defined values
10853 and the meaning of the code has been changed. */
10854 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10855 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10857 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10858 && mode_width <= HOST_BITS_PER_WIDE_INT
10859 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10860 <= HOST_BITS_PER_WIDE_INT)
10861 && (INTVAL (XEXP (op0, 1)) & ~mask) == 0
10862 && 0 == (~GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10863 & INTVAL (XEXP (op0, 1)))
10864 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10865 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10866 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10870 = gen_lowpart_for_combine
10872 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10873 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10877 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10878 (eq (and (lshiftrt X) 1) 0). */
10879 if (const_op == 0 && equality_comparison_p
10880 && XEXP (op0, 1) == const1_rtx
10881 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10882 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == NOT)
10884 op0 = simplify_and_const_int
10885 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10886 XEXP (XEXP (XEXP (op0, 0), 0), 0),
10887 XEXP (XEXP (op0, 0), 1)),
10888 (HOST_WIDE_INT) 1);
10889 code = (code == NE ? EQ : NE);
10895 /* If we have (compare (ashift FOO N) (const_int C)) and
10896 the high order N bits of FOO (N+1 if an inequality comparison)
10897 are known to be zero, we can do this by comparing FOO with C
10898 shifted right N bits so long as the low-order N bits of C are
10900 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10901 && INTVAL (XEXP (op0, 1)) >= 0
10902 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10903 < HOST_BITS_PER_WIDE_INT)
10905 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10906 && mode_width <= HOST_BITS_PER_WIDE_INT
10907 && (nonzero_bits (XEXP (op0, 0), mode)
10908 & ~(mask >> (INTVAL (XEXP (op0, 1))
10909 + ! equality_comparison_p))) == 0)
10911 /* We must perform a logical shift, not an arithmetic one,
10912 as we want the top N bits of C to be zero. */
10913 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10915 temp >>= INTVAL (XEXP (op0, 1));
10916 op1 = GEN_INT (trunc_int_for_mode (temp, mode));
10917 op0 = XEXP (op0, 0);
10921 /* If we are doing a sign bit comparison, it means we are testing
10922 a particular bit. Convert it to the appropriate AND. */
10923 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10924 && mode_width <= HOST_BITS_PER_WIDE_INT)
10926 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10929 - INTVAL (XEXP (op0, 1)))));
10930 code = (code == LT ? NE : EQ);
10934 /* If this an equality comparison with zero and we are shifting
10935 the low bit to the sign bit, we can convert this to an AND of the
10937 if (const_op == 0 && equality_comparison_p
10938 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10939 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10941 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10942 (HOST_WIDE_INT) 1);
10948 /* If this is an equality comparison with zero, we can do this
10949 as a logical shift, which might be much simpler. */
10950 if (equality_comparison_p && const_op == 0
10951 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10953 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10955 INTVAL (XEXP (op0, 1)));
10959 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10960 do the comparison in a narrower mode. */
10961 if (! unsigned_comparison_p
10962 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10963 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10964 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10965 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10966 MODE_INT, 1)) != BLKmode
10967 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10968 || ((unsigned HOST_WIDE_INT) -const_op
10969 <= GET_MODE_MASK (tmode))))
10971 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10975 /* Likewise if OP0 is a PLUS of a sign extension with a
10976 constant, which is usually represented with the PLUS
10977 between the shifts. */
10978 if (! unsigned_comparison_p
10979 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10980 && GET_CODE (XEXP (op0, 0)) == PLUS
10981 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10982 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10983 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10984 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10985 MODE_INT, 1)) != BLKmode
10986 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10987 || ((unsigned HOST_WIDE_INT) -const_op
10988 <= GET_MODE_MASK (tmode))))
10990 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10991 rtx add_const = XEXP (XEXP (op0, 0), 1);
10992 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10995 op0 = gen_binary (PLUS, tmode,
10996 gen_lowpart_for_combine (tmode, inner),
11001 /* ... fall through ... */
11003 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11004 the low order N bits of FOO are known to be zero, we can do this
11005 by comparing FOO with C shifted left N bits so long as no
11006 overflow occurs. */
11007 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
11008 && INTVAL (XEXP (op0, 1)) >= 0
11009 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11010 && mode_width <= HOST_BITS_PER_WIDE_INT
11011 && (nonzero_bits (XEXP (op0, 0), mode)
11012 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11014 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
11017 const_op <<= INTVAL (XEXP (op0, 1));
11018 op1 = GEN_INT (const_op);
11019 op0 = XEXP (op0, 0);
11023 /* If we are using this shift to extract just the sign bit, we
11024 can replace this with an LT or GE comparison. */
11026 && (equality_comparison_p || sign_bit_comparison_p)
11027 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11028 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
11030 op0 = XEXP (op0, 0);
11031 code = (code == NE || code == GT ? LT : GE);
11043 /* Now make any compound operations involved in this comparison. Then,
11044 check for an outmost SUBREG on OP0 that is not doing anything or is
11045 paradoxical. The latter case can only occur when it is known that the
11046 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
11047 We can never remove a SUBREG for a non-equality comparison because the
11048 sign bit is in a different place in the underlying object. */
11050 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11051 op1 = make_compound_operation (op1, SET);
11053 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11054 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11055 && (code == NE || code == EQ)
11056 && ((GET_MODE_SIZE (GET_MODE (op0))
11057 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
11059 op0 = SUBREG_REG (op0);
11060 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
11063 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11064 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11065 && (code == NE || code == EQ)
11066 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11067 <= HOST_BITS_PER_WIDE_INT)
11068 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
11069 & ~GET_MODE_MASK (GET_MODE (op0))) == 0
11070 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
11072 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11073 & ~GET_MODE_MASK (GET_MODE (op0))) == 0))
11074 op0 = SUBREG_REG (op0), op1 = tem;
11076 /* We now do the opposite procedure: Some machines don't have compare
11077 insns in all modes. If OP0's mode is an integer mode smaller than a
11078 word and we can't do a compare in that mode, see if there is a larger
11079 mode for which we can do the compare. There are a number of cases in
11080 which we can use the wider mode. */
11082 mode = GET_MODE (op0);
11083 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11084 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11085 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
11086 for (tmode = GET_MODE_WIDER_MODE (mode);
11088 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11089 tmode = GET_MODE_WIDER_MODE (tmode))
11090 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
11092 /* If the only nonzero bits in OP0 and OP1 are those in the
11093 narrower mode and this is an equality or unsigned comparison,
11094 we can use the wider mode. Similarly for sign-extended
11095 values, in which case it is true for all comparisons. */
11096 if (((code == EQ || code == NE
11097 || code == GEU || code == GTU || code == LEU || code == LTU)
11098 && (nonzero_bits (op0, tmode) & ~GET_MODE_MASK (mode)) == 0
11099 && (nonzero_bits (op1, tmode) & ~GET_MODE_MASK (mode)) == 0)
11100 || ((num_sign_bit_copies (op0, tmode)
11101 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
11102 && (num_sign_bit_copies (op1, tmode)
11103 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
11105 /* If OP0 is an AND and we don't have an AND in MODE either,
11106 make a new AND in the proper mode. */
11107 if (GET_CODE (op0) == AND
11108 && (add_optab->handlers[(int) mode].insn_code
11109 == CODE_FOR_nothing))
11110 op0 = gen_binary (AND, tmode,
11111 gen_lowpart_for_combine (tmode,
11113 gen_lowpart_for_combine (tmode,
11116 op0 = gen_lowpart_for_combine (tmode, op0);
11117 op1 = gen_lowpart_for_combine (tmode, op1);
11121 /* If this is a test for negative, we can make an explicit
11122 test of the sign bit. */
11124 if (op1 == const0_rtx && (code == LT || code == GE)
11125 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11127 op0 = gen_binary (AND, tmode,
11128 gen_lowpart_for_combine (tmode, op0),
11129 GEN_INT ((HOST_WIDE_INT) 1
11130 << (GET_MODE_BITSIZE (mode) - 1)));
11131 code = (code == LT) ? NE : EQ;
11136 #ifdef CANONICALIZE_COMPARISON
11137 /* If this machine only supports a subset of valid comparisons, see if we
11138 can convert an unsupported one into a supported one. */
11139 CANONICALIZE_COMPARISON (code, op0, op1);
11148 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
11149 searching backward. */
11150 static enum rtx_code
11151 combine_reversed_comparison_code (exp)
11154 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
11157 if (code1 != UNKNOWN
11158 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
11160 /* Otherwise try and find where the condition codes were last set and
11162 x = get_last_value (XEXP (exp, 0));
11163 if (!x || GET_CODE (x) != COMPARE)
11165 return reversed_comparison_code_parts (GET_CODE (exp),
11166 XEXP (x, 0), XEXP (x, 1), NULL);
11168 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
11169 Return NULL_RTX in case we fail to do the reversal. */
11171 reversed_comparison (exp, mode, op0, op1)
11173 enum machine_mode mode;
11175 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
11176 if (reversed_code == UNKNOWN)
11179 return gen_binary (reversed_code, mode, op0, op1);
11182 /* Utility function for following routine. Called when X is part of a value
11183 being stored into reg_last_set_value. Sets reg_last_set_table_tick
11184 for each register mentioned. Similar to mention_regs in cse.c */
11187 update_table_tick (x)
11190 register enum rtx_code code = GET_CODE (x);
11191 register const char *fmt = GET_RTX_FORMAT (code);
11196 unsigned int regno = REGNO (x);
11197 unsigned int endregno
11198 = regno + (regno < FIRST_PSEUDO_REGISTER
11199 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11202 for (r = regno; r < endregno; r++)
11203 reg_last_set_table_tick[r] = label_tick;
11208 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11209 /* Note that we can't have an "E" in values stored; see
11210 get_last_value_validate. */
11212 update_table_tick (XEXP (x, i));
11215 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11216 are saying that the register is clobbered and we no longer know its
11217 value. If INSN is zero, don't update reg_last_set; this is only permitted
11218 with VALUE also zero and is used to invalidate the register. */
11221 record_value_for_reg (reg, insn, value)
11226 unsigned int regno = REGNO (reg);
11227 unsigned int endregno
11228 = regno + (regno < FIRST_PSEUDO_REGISTER
11229 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
11232 /* If VALUE contains REG and we have a previous value for REG, substitute
11233 the previous value. */
11234 if (value && insn && reg_overlap_mentioned_p (reg, value))
11238 /* Set things up so get_last_value is allowed to see anything set up to
11240 subst_low_cuid = INSN_CUID (insn);
11241 tem = get_last_value (reg);
11243 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11244 it isn't going to be useful and will take a lot of time to process,
11245 so just use the CLOBBER. */
11249 if ((GET_RTX_CLASS (GET_CODE (tem)) == '2'
11250 || GET_RTX_CLASS (GET_CODE (tem)) == 'c')
11251 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11252 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11253 tem = XEXP (tem, 0);
11255 value = replace_rtx (copy_rtx (value), reg, tem);
11259 /* For each register modified, show we don't know its value, that
11260 we don't know about its bitwise content, that its value has been
11261 updated, and that we don't know the location of the death of the
11263 for (i = regno; i < endregno; i++)
11266 reg_last_set[i] = insn;
11268 reg_last_set_value[i] = 0;
11269 reg_last_set_mode[i] = 0;
11270 reg_last_set_nonzero_bits[i] = 0;
11271 reg_last_set_sign_bit_copies[i] = 0;
11272 reg_last_death[i] = 0;
11275 /* Mark registers that are being referenced in this value. */
11277 update_table_tick (value);
11279 /* Now update the status of each register being set.
11280 If someone is using this register in this block, set this register
11281 to invalid since we will get confused between the two lives in this
11282 basic block. This makes using this register always invalid. In cse, we
11283 scan the table to invalidate all entries using this register, but this
11284 is too much work for us. */
11286 for (i = regno; i < endregno; i++)
11288 reg_last_set_label[i] = label_tick;
11289 if (value && reg_last_set_table_tick[i] == label_tick)
11290 reg_last_set_invalid[i] = 1;
11292 reg_last_set_invalid[i] = 0;
11295 /* The value being assigned might refer to X (like in "x++;"). In that
11296 case, we must replace it with (clobber (const_int 0)) to prevent
11298 if (value && ! get_last_value_validate (&value, insn,
11299 reg_last_set_label[regno], 0))
11301 value = copy_rtx (value);
11302 if (! get_last_value_validate (&value, insn,
11303 reg_last_set_label[regno], 1))
11307 /* For the main register being modified, update the value, the mode, the
11308 nonzero bits, and the number of sign bit copies. */
11310 reg_last_set_value[regno] = value;
11314 subst_low_cuid = INSN_CUID (insn);
11315 reg_last_set_mode[regno] = GET_MODE (reg);
11316 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
11317 reg_last_set_sign_bit_copies[regno]
11318 = num_sign_bit_copies (value, GET_MODE (reg));
11322 /* Called via note_stores from record_dead_and_set_regs to handle one
11323 SET or CLOBBER in an insn. DATA is the instruction in which the
11324 set is occurring. */
11327 record_dead_and_set_regs_1 (dest, setter, data)
11331 rtx record_dead_insn = (rtx) data;
11333 if (GET_CODE (dest) == SUBREG)
11334 dest = SUBREG_REG (dest);
11336 if (GET_CODE (dest) == REG)
11338 /* If we are setting the whole register, we know its value. Otherwise
11339 show that we don't know the value. We can handle SUBREG in
11341 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11342 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11343 else if (GET_CODE (setter) == SET
11344 && GET_CODE (SET_DEST (setter)) == SUBREG
11345 && SUBREG_REG (SET_DEST (setter)) == dest
11346 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11347 && subreg_lowpart_p (SET_DEST (setter)))
11348 record_value_for_reg (dest, record_dead_insn,
11349 gen_lowpart_for_combine (GET_MODE (dest),
11350 SET_SRC (setter)));
11352 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11354 else if (GET_CODE (dest) == MEM
11355 /* Ignore pushes, they clobber nothing. */
11356 && ! push_operand (dest, GET_MODE (dest)))
11357 mem_last_set = INSN_CUID (record_dead_insn);
11360 /* Update the records of when each REG was most recently set or killed
11361 for the things done by INSN. This is the last thing done in processing
11362 INSN in the combiner loop.
11364 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11365 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11366 and also the similar information mem_last_set (which insn most recently
11367 modified memory) and last_call_cuid (which insn was the most recent
11368 subroutine call). */
11371 record_dead_and_set_regs (insn)
11377 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11379 if (REG_NOTE_KIND (link) == REG_DEAD
11380 && GET_CODE (XEXP (link, 0)) == REG)
11382 unsigned int regno = REGNO (XEXP (link, 0));
11383 unsigned int endregno
11384 = regno + (regno < FIRST_PSEUDO_REGISTER
11385 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
11388 for (i = regno; i < endregno; i++)
11389 reg_last_death[i] = insn;
11391 else if (REG_NOTE_KIND (link) == REG_INC)
11392 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11395 if (GET_CODE (insn) == CALL_INSN)
11397 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11398 if (call_used_regs[i])
11400 reg_last_set_value[i] = 0;
11401 reg_last_set_mode[i] = 0;
11402 reg_last_set_nonzero_bits[i] = 0;
11403 reg_last_set_sign_bit_copies[i] = 0;
11404 reg_last_death[i] = 0;
11407 last_call_cuid = mem_last_set = INSN_CUID (insn);
11410 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11413 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11414 register present in the SUBREG, so for each such SUBREG go back and
11415 adjust nonzero and sign bit information of the registers that are
11416 known to have some zero/sign bits set.
11418 This is needed because when combine blows the SUBREGs away, the
11419 information on zero/sign bits is lost and further combines can be
11420 missed because of that. */
11423 record_promoted_value (insn, subreg)
11428 unsigned int regno = REGNO (SUBREG_REG (subreg));
11429 enum machine_mode mode = GET_MODE (subreg);
11431 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11434 for (links = LOG_LINKS (insn); links;)
11436 insn = XEXP (links, 0);
11437 set = single_set (insn);
11439 if (! set || GET_CODE (SET_DEST (set)) != REG
11440 || REGNO (SET_DEST (set)) != regno
11441 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11443 links = XEXP (links, 1);
11447 if (reg_last_set[regno] == insn)
11449 if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
11450 reg_last_set_nonzero_bits[regno] &= GET_MODE_MASK (mode);
11453 if (GET_CODE (SET_SRC (set)) == REG)
11455 regno = REGNO (SET_SRC (set));
11456 links = LOG_LINKS (insn);
11463 /* Scan X for promoted SUBREGs. For each one found,
11464 note what it implies to the registers used in it. */
11467 check_promoted_subreg (insn, x)
11471 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11472 && GET_CODE (SUBREG_REG (x)) == REG)
11473 record_promoted_value (insn, x);
11476 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11479 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11483 check_promoted_subreg (insn, XEXP (x, i));
11487 if (XVEC (x, i) != 0)
11488 for (j = 0; j < XVECLEN (x, i); j++)
11489 check_promoted_subreg (insn, XVECEXP (x, i, j));
11495 /* Utility routine for the following function. Verify that all the registers
11496 mentioned in *LOC are valid when *LOC was part of a value set when
11497 label_tick == TICK. Return 0 if some are not.
11499 If REPLACE is non-zero, replace the invalid reference with
11500 (clobber (const_int 0)) and return 1. This replacement is useful because
11501 we often can get useful information about the form of a value (e.g., if
11502 it was produced by a shift that always produces -1 or 0) even though
11503 we don't know exactly what registers it was produced from. */
11506 get_last_value_validate (loc, insn, tick, replace)
11513 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11514 int len = GET_RTX_LENGTH (GET_CODE (x));
11517 if (GET_CODE (x) == REG)
11519 unsigned int regno = REGNO (x);
11520 unsigned int endregno
11521 = regno + (regno < FIRST_PSEUDO_REGISTER
11522 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11525 for (j = regno; j < endregno; j++)
11526 if (reg_last_set_invalid[j]
11527 /* If this is a pseudo-register that was only set once and not
11528 live at the beginning of the function, it is always valid. */
11529 || (! (regno >= FIRST_PSEUDO_REGISTER
11530 && REG_N_SETS (regno) == 1
11531 && (! REGNO_REG_SET_P
11532 (BASIC_BLOCK (0)->global_live_at_start, regno)))
11533 && reg_last_set_label[j] > tick))
11536 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11542 /* If this is a memory reference, make sure that there were
11543 no stores after it that might have clobbered the value. We don't
11544 have alias info, so we assume any store invalidates it. */
11545 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
11546 && INSN_CUID (insn) <= mem_last_set)
11549 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11553 for (i = 0; i < len; i++)
11555 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
11556 /* Don't bother with these. They shouldn't occur anyway. */
11560 /* If we haven't found a reason for it to be invalid, it is valid. */
11564 /* Get the last value assigned to X, if known. Some registers
11565 in the value may be replaced with (clobber (const_int 0)) if their value
11566 is known longer known reliably. */
11572 unsigned int regno;
11575 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11576 then convert it to the desired mode. If this is a paradoxical SUBREG,
11577 we cannot predict what values the "extra" bits might have. */
11578 if (GET_CODE (x) == SUBREG
11579 && subreg_lowpart_p (x)
11580 && (GET_MODE_SIZE (GET_MODE (x))
11581 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11582 && (value = get_last_value (SUBREG_REG (x))) != 0)
11583 return gen_lowpart_for_combine (GET_MODE (x), value);
11585 if (GET_CODE (x) != REG)
11589 value = reg_last_set_value[regno];
11591 /* If we don't have a value, or if it isn't for this basic block and
11592 it's either a hard register, set more than once, or it's a live
11593 at the beginning of the function, return 0.
11595 Because if it's not live at the beginnning of the function then the reg
11596 is always set before being used (is never used without being set).
11597 And, if it's set only once, and it's always set before use, then all
11598 uses must have the same last value, even if it's not from this basic
11602 || (reg_last_set_label[regno] != label_tick
11603 && (regno < FIRST_PSEUDO_REGISTER
11604 || REG_N_SETS (regno) != 1
11605 || (REGNO_REG_SET_P
11606 (BASIC_BLOCK (0)->global_live_at_start, regno)))))
11609 /* If the value was set in a later insn than the ones we are processing,
11610 we can't use it even if the register was only set once. */
11611 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
11614 /* If the value has all its registers valid, return it. */
11615 if (get_last_value_validate (&value, reg_last_set[regno],
11616 reg_last_set_label[regno], 0))
11619 /* Otherwise, make a copy and replace any invalid register with
11620 (clobber (const_int 0)). If that fails for some reason, return 0. */
11622 value = copy_rtx (value);
11623 if (get_last_value_validate (&value, reg_last_set[regno],
11624 reg_last_set_label[regno], 1))
11630 /* Return nonzero if expression X refers to a REG or to memory
11631 that is set in an instruction more recent than FROM_CUID. */
11634 use_crosses_set_p (x, from_cuid)
11638 register const char *fmt;
11640 register enum rtx_code code = GET_CODE (x);
11644 unsigned int regno = REGNO (x);
11645 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11646 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
11648 #ifdef PUSH_ROUNDING
11649 /* Don't allow uses of the stack pointer to be moved,
11650 because we don't know whether the move crosses a push insn. */
11651 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11654 for (; regno < endreg; regno++)
11655 if (reg_last_set[regno]
11656 && INSN_CUID (reg_last_set[regno]) > from_cuid)
11661 if (code == MEM && mem_last_set > from_cuid)
11664 fmt = GET_RTX_FORMAT (code);
11666 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11671 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11672 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11675 else if (fmt[i] == 'e'
11676 && use_crosses_set_p (XEXP (x, i), from_cuid))
11682 /* Define three variables used for communication between the following
11685 static unsigned int reg_dead_regno, reg_dead_endregno;
11686 static int reg_dead_flag;
11688 /* Function called via note_stores from reg_dead_at_p.
11690 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11691 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11694 reg_dead_at_p_1 (dest, x, data)
11697 void *data ATTRIBUTE_UNUSED;
11699 unsigned int regno, endregno;
11701 if (GET_CODE (dest) != REG)
11704 regno = REGNO (dest);
11705 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11706 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
11708 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11709 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11712 /* Return non-zero if REG is known to be dead at INSN.
11714 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11715 referencing REG, it is dead. If we hit a SET referencing REG, it is
11716 live. Otherwise, see if it is live or dead at the start of the basic
11717 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11718 must be assumed to be always live. */
11721 reg_dead_at_p (reg, insn)
11728 /* Set variables for reg_dead_at_p_1. */
11729 reg_dead_regno = REGNO (reg);
11730 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11731 ? HARD_REGNO_NREGS (reg_dead_regno,
11737 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11738 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11740 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11741 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
11745 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11746 beginning of function. */
11747 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
11748 insn = prev_nonnote_insn (insn))
11750 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11752 return reg_dead_flag == 1 ? 1 : 0;
11754 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11758 /* Get the basic block number that we were in. */
11763 for (block = 0; block < n_basic_blocks; block++)
11764 if (insn == BLOCK_HEAD (block))
11767 if (block == n_basic_blocks)
11771 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11772 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11778 /* Note hard registers in X that are used. This code is similar to
11779 that in flow.c, but much simpler since we don't care about pseudos. */
11782 mark_used_regs_combine (x)
11785 RTX_CODE code = GET_CODE (x);
11786 unsigned int regno;
11798 case ADDR_DIFF_VEC:
11801 /* CC0 must die in the insn after it is set, so we don't need to take
11802 special note of it here. */
11808 /* If we are clobbering a MEM, mark any hard registers inside the
11809 address as used. */
11810 if (GET_CODE (XEXP (x, 0)) == MEM)
11811 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11816 /* A hard reg in a wide mode may really be multiple registers.
11817 If so, mark all of them just like the first. */
11818 if (regno < FIRST_PSEUDO_REGISTER)
11820 unsigned int endregno, r;
11822 /* None of this applies to the stack, frame or arg pointers */
11823 if (regno == STACK_POINTER_REGNUM
11824 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11825 || regno == HARD_FRAME_POINTER_REGNUM
11827 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11828 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11830 || regno == FRAME_POINTER_REGNUM)
11833 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11834 for (r = regno; r < endregno; r++)
11835 SET_HARD_REG_BIT (newpat_used_regs, r);
11841 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11843 register rtx testreg = SET_DEST (x);
11845 while (GET_CODE (testreg) == SUBREG
11846 || GET_CODE (testreg) == ZERO_EXTRACT
11847 || GET_CODE (testreg) == SIGN_EXTRACT
11848 || GET_CODE (testreg) == STRICT_LOW_PART)
11849 testreg = XEXP (testreg, 0);
11851 if (GET_CODE (testreg) == MEM)
11852 mark_used_regs_combine (XEXP (testreg, 0));
11854 mark_used_regs_combine (SET_SRC (x));
11862 /* Recursively scan the operands of this expression. */
11865 register const char *fmt = GET_RTX_FORMAT (code);
11867 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11870 mark_used_regs_combine (XEXP (x, i));
11871 else if (fmt[i] == 'E')
11875 for (j = 0; j < XVECLEN (x, i); j++)
11876 mark_used_regs_combine (XVECEXP (x, i, j));
11882 /* Remove register number REGNO from the dead registers list of INSN.
11884 Return the note used to record the death, if there was one. */
11887 remove_death (regno, insn)
11888 unsigned int regno;
11891 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11895 REG_N_DEATHS (regno)--;
11896 remove_note (insn, note);
11902 /* For each register (hardware or pseudo) used within expression X, if its
11903 death is in an instruction with cuid between FROM_CUID (inclusive) and
11904 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11905 list headed by PNOTES.
11907 That said, don't move registers killed by maybe_kill_insn.
11909 This is done when X is being merged by combination into TO_INSN. These
11910 notes will then be distributed as needed. */
11913 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11915 rtx maybe_kill_insn;
11920 register const char *fmt;
11921 register int len, i;
11922 register enum rtx_code code = GET_CODE (x);
11926 unsigned int regno = REGNO (x);
11927 register rtx where_dead = reg_last_death[regno];
11928 register rtx before_dead, after_dead;
11930 /* Don't move the register if it gets killed in between from and to */
11931 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11932 && ! reg_referenced_p (x, maybe_kill_insn))
11935 /* WHERE_DEAD could be a USE insn made by combine, so first we
11936 make sure that we have insns with valid INSN_CUID values. */
11937 before_dead = where_dead;
11938 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11939 before_dead = PREV_INSN (before_dead);
11941 after_dead = where_dead;
11942 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11943 after_dead = NEXT_INSN (after_dead);
11945 if (before_dead && after_dead
11946 && INSN_CUID (before_dead) >= from_cuid
11947 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11948 || (where_dead != after_dead
11949 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11951 rtx note = remove_death (regno, where_dead);
11953 /* It is possible for the call above to return 0. This can occur
11954 when reg_last_death points to I2 or I1 that we combined with.
11955 In that case make a new note.
11957 We must also check for the case where X is a hard register
11958 and NOTE is a death note for a range of hard registers
11959 including X. In that case, we must put REG_DEAD notes for
11960 the remaining registers in place of NOTE. */
11962 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11963 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11964 > GET_MODE_SIZE (GET_MODE (x))))
11966 unsigned int deadregno = REGNO (XEXP (note, 0));
11967 unsigned int deadend
11968 = (deadregno + HARD_REGNO_NREGS (deadregno,
11969 GET_MODE (XEXP (note, 0))));
11970 unsigned int ourend
11971 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11974 for (i = deadregno; i < deadend; i++)
11975 if (i < regno || i >= ourend)
11976 REG_NOTES (where_dead)
11977 = gen_rtx_EXPR_LIST (REG_DEAD,
11978 gen_rtx_REG (reg_raw_mode[i], i),
11979 REG_NOTES (where_dead));
11982 /* If we didn't find any note, or if we found a REG_DEAD note that
11983 covers only part of the given reg, and we have a multi-reg hard
11984 register, then to be safe we must check for REG_DEAD notes
11985 for each register other than the first. They could have
11986 their own REG_DEAD notes lying around. */
11987 else if ((note == 0
11989 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11990 < GET_MODE_SIZE (GET_MODE (x)))))
11991 && regno < FIRST_PSEUDO_REGISTER
11992 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11994 unsigned int ourend
11995 = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11996 unsigned int i, offset;
12000 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
12004 for (i = regno + offset; i < ourend; i++)
12005 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
12006 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
12009 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12011 XEXP (note, 1) = *pnotes;
12015 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12017 REG_N_DEATHS (regno)++;
12023 else if (GET_CODE (x) == SET)
12025 rtx dest = SET_DEST (x);
12027 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
12029 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12030 that accesses one word of a multi-word item, some
12031 piece of everything register in the expression is used by
12032 this insn, so remove any old death. */
12034 if (GET_CODE (dest) == ZERO_EXTRACT
12035 || GET_CODE (dest) == STRICT_LOW_PART
12036 || (GET_CODE (dest) == SUBREG
12037 && (((GET_MODE_SIZE (GET_MODE (dest))
12038 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12039 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12040 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12042 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
12046 /* If this is some other SUBREG, we know it replaces the entire
12047 value, so use that as the destination. */
12048 if (GET_CODE (dest) == SUBREG)
12049 dest = SUBREG_REG (dest);
12051 /* If this is a MEM, adjust deaths of anything used in the address.
12052 For a REG (the only other possibility), the entire value is
12053 being replaced so the old value is not used in this insn. */
12055 if (GET_CODE (dest) == MEM)
12056 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
12061 else if (GET_CODE (x) == CLOBBER)
12064 len = GET_RTX_LENGTH (code);
12065 fmt = GET_RTX_FORMAT (code);
12067 for (i = 0; i < len; i++)
12072 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12073 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
12076 else if (fmt[i] == 'e')
12077 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
12081 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12082 pattern of an insn. X must be a REG. */
12085 reg_bitfield_target_p (x, body)
12091 if (GET_CODE (body) == SET)
12093 rtx dest = SET_DEST (body);
12095 unsigned int regno, tregno, endregno, endtregno;
12097 if (GET_CODE (dest) == ZERO_EXTRACT)
12098 target = XEXP (dest, 0);
12099 else if (GET_CODE (dest) == STRICT_LOW_PART)
12100 target = SUBREG_REG (XEXP (dest, 0));
12104 if (GET_CODE (target) == SUBREG)
12105 target = SUBREG_REG (target);
12107 if (GET_CODE (target) != REG)
12110 tregno = REGNO (target), regno = REGNO (x);
12111 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12112 return target == x;
12114 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
12115 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
12117 return endregno > tregno && regno < endtregno;
12120 else if (GET_CODE (body) == PARALLEL)
12121 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12122 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12128 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12129 as appropriate. I3 and I2 are the insns resulting from the combination
12130 insns including FROM (I2 may be zero).
12132 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12133 not need REG_DEAD notes because they are being substituted for. This
12134 saves searching in the most common cases.
12136 Each note in the list is either ignored or placed on some insns, depending
12137 on the type of note. */
12140 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
12144 rtx elim_i2, elim_i1;
12146 rtx note, next_note;
12149 for (note = notes; note; note = next_note)
12151 rtx place = 0, place2 = 0;
12153 /* If this NOTE references a pseudo register, ensure it references
12154 the latest copy of that register. */
12155 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
12156 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
12157 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
12159 next_note = XEXP (note, 1);
12160 switch (REG_NOTE_KIND (note))
12163 case REG_EXEC_COUNT:
12164 /* Doesn't matter much where we put this, as long as it's somewhere.
12165 It is preferable to keep these notes on branches, which is most
12166 likely to be i3. */
12170 case REG_NON_LOCAL_GOTO:
12171 if (GET_CODE (i3) == JUMP_INSN)
12173 else if (i2 && GET_CODE (i2) == JUMP_INSN)
12179 case REG_EH_REGION:
12180 case REG_EH_RETHROW:
12182 /* These notes must remain with the call. It should not be
12183 possible for both I2 and I3 to be a call. */
12184 if (GET_CODE (i3) == CALL_INSN)
12186 else if (i2 && GET_CODE (i2) == CALL_INSN)
12193 /* Any clobbers for i3 may still exist, and so we must process
12194 REG_UNUSED notes from that insn.
12196 Any clobbers from i2 or i1 can only exist if they were added by
12197 recog_for_combine. In that case, recog_for_combine created the
12198 necessary REG_UNUSED notes. Trying to keep any original
12199 REG_UNUSED notes from these insns can cause incorrect output
12200 if it is for the same register as the original i3 dest.
12201 In that case, we will notice that the register is set in i3,
12202 and then add a REG_UNUSED note for the destination of i3, which
12203 is wrong. However, it is possible to have REG_UNUSED notes from
12204 i2 or i1 for register which were both used and clobbered, so
12205 we keep notes from i2 or i1 if they will turn into REG_DEAD
12208 /* If this register is set or clobbered in I3, put the note there
12209 unless there is one already. */
12210 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12212 if (from_insn != i3)
12215 if (! (GET_CODE (XEXP (note, 0)) == REG
12216 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12217 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12220 /* Otherwise, if this register is used by I3, then this register
12221 now dies here, so we must put a REG_DEAD note here unless there
12223 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12224 && ! (GET_CODE (XEXP (note, 0)) == REG
12225 ? find_regno_note (i3, REG_DEAD,
12226 REGNO (XEXP (note, 0)))
12227 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12229 PUT_REG_NOTE_KIND (note, REG_DEAD);
12237 /* These notes say something about results of an insn. We can
12238 only support them if they used to be on I3 in which case they
12239 remain on I3. Otherwise they are ignored.
12241 If the note refers to an expression that is not a constant, we
12242 must also ignore the note since we cannot tell whether the
12243 equivalence is still true. It might be possible to do
12244 slightly better than this (we only have a problem if I2DEST
12245 or I1DEST is present in the expression), but it doesn't
12246 seem worth the trouble. */
12248 if (from_insn == i3
12249 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12254 case REG_NO_CONFLICT:
12255 /* These notes say something about how a register is used. They must
12256 be present on any use of the register in I2 or I3. */
12257 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12260 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12270 /* This can show up in several ways -- either directly in the
12271 pattern, or hidden off in the constant pool with (or without?)
12272 a REG_EQUAL note. */
12273 /* ??? Ignore the without-reg_equal-note problem for now. */
12274 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12275 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12276 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12277 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12281 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12282 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12283 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12284 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12295 /* These notes say something about the value of a register prior
12296 to the execution of an insn. It is too much trouble to see
12297 if the note is still correct in all situations. It is better
12298 to simply delete it. */
12302 /* If the insn previously containing this note still exists,
12303 put it back where it was. Otherwise move it to the previous
12304 insn. Adjust the corresponding REG_LIBCALL note. */
12305 if (GET_CODE (from_insn) != NOTE)
12309 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12310 place = prev_real_insn (from_insn);
12312 XEXP (tem, 0) = place;
12313 /* If we're deleting the last remaining instruction of a
12314 libcall sequence, don't add the notes. */
12315 else if (XEXP (note, 0) == from_insn)
12321 /* This is handled similarly to REG_RETVAL. */
12322 if (GET_CODE (from_insn) != NOTE)
12326 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12327 place = next_real_insn (from_insn);
12329 XEXP (tem, 0) = place;
12330 /* If we're deleting the last remaining instruction of a
12331 libcall sequence, don't add the notes. */
12332 else if (XEXP (note, 0) == from_insn)
12338 /* If the register is used as an input in I3, it dies there.
12339 Similarly for I2, if it is non-zero and adjacent to I3.
12341 If the register is not used as an input in either I3 or I2
12342 and it is not one of the registers we were supposed to eliminate,
12343 there are two possibilities. We might have a non-adjacent I2
12344 or we might have somehow eliminated an additional register
12345 from a computation. For example, we might have had A & B where
12346 we discover that B will always be zero. In this case we will
12347 eliminate the reference to A.
12349 In both cases, we must search to see if we can find a previous
12350 use of A and put the death note there. */
12353 && GET_CODE (from_insn) == CALL_INSN
12354 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12356 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12358 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12359 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12362 if (rtx_equal_p (XEXP (note, 0), elim_i2)
12363 || rtx_equal_p (XEXP (note, 0), elim_i1))
12368 basic_block bb = BASIC_BLOCK (this_basic_block);
12370 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12372 if (! INSN_P (tem))
12374 if (tem == bb->head)
12379 /* If the register is being set at TEM, see if that is all
12380 TEM is doing. If so, delete TEM. Otherwise, make this
12381 into a REG_UNUSED note instead. */
12382 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
12384 rtx set = single_set (tem);
12385 rtx inner_dest = 0;
12387 rtx cc0_setter = NULL_RTX;
12391 for (inner_dest = SET_DEST (set);
12392 (GET_CODE (inner_dest) == STRICT_LOW_PART
12393 || GET_CODE (inner_dest) == SUBREG
12394 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12395 inner_dest = XEXP (inner_dest, 0))
12398 /* Verify that it was the set, and not a clobber that
12399 modified the register.
12401 CC0 targets must be careful to maintain setter/user
12402 pairs. If we cannot delete the setter due to side
12403 effects, mark the user with an UNUSED note instead
12406 if (set != 0 && ! side_effects_p (SET_SRC (set))
12407 && rtx_equal_p (XEXP (note, 0), inner_dest)
12409 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12410 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12411 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12415 /* Move the notes and links of TEM elsewhere.
12416 This might delete other dead insns recursively.
12417 First set the pattern to something that won't use
12420 PATTERN (tem) = pc_rtx;
12422 distribute_notes (REG_NOTES (tem), tem, tem,
12423 NULL_RTX, NULL_RTX, NULL_RTX);
12424 distribute_links (LOG_LINKS (tem));
12426 PUT_CODE (tem, NOTE);
12427 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
12428 NOTE_SOURCE_FILE (tem) = 0;
12431 /* Delete the setter too. */
12434 PATTERN (cc0_setter) = pc_rtx;
12436 distribute_notes (REG_NOTES (cc0_setter),
12437 cc0_setter, cc0_setter,
12438 NULL_RTX, NULL_RTX, NULL_RTX);
12439 distribute_links (LOG_LINKS (cc0_setter));
12441 PUT_CODE (cc0_setter, NOTE);
12442 NOTE_LINE_NUMBER (cc0_setter)
12443 = NOTE_INSN_DELETED;
12444 NOTE_SOURCE_FILE (cc0_setter) = 0;
12448 /* If the register is both set and used here, put the
12449 REG_DEAD note here, but place a REG_UNUSED note
12450 here too unless there already is one. */
12451 else if (reg_referenced_p (XEXP (note, 0),
12456 if (! find_regno_note (tem, REG_UNUSED,
12457 REGNO (XEXP (note, 0))))
12459 = gen_rtx_EXPR_LIST (REG_UNUSED, XEXP (note, 0),
12464 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12466 /* If there isn't already a REG_UNUSED note, put one
12468 if (! find_regno_note (tem, REG_UNUSED,
12469 REGNO (XEXP (note, 0))))
12474 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12475 || (GET_CODE (tem) == CALL_INSN
12476 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12480 /* If we are doing a 3->2 combination, and we have a
12481 register which formerly died in i3 and was not used
12482 by i2, which now no longer dies in i3 and is used in
12483 i2 but does not die in i2, and place is between i2
12484 and i3, then we may need to move a link from place to
12486 if (i2 && INSN_UID (place) <= max_uid_cuid
12487 && INSN_CUID (place) > INSN_CUID (i2)
12489 && INSN_CUID (from_insn) > INSN_CUID (i2)
12490 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12492 rtx links = LOG_LINKS (place);
12493 LOG_LINKS (place) = 0;
12494 distribute_links (links);
12499 if (tem == bb->head)
12503 /* We haven't found an insn for the death note and it
12504 is still a REG_DEAD note, but we have hit the beginning
12505 of the block. If the existing life info says the reg
12506 was dead, there's nothing left to do. Otherwise, we'll
12507 need to do a global life update after combine. */
12508 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12509 && REGNO_REG_SET_P (bb->global_live_at_start,
12510 REGNO (XEXP (note, 0))))
12512 SET_BIT (refresh_blocks, this_basic_block);
12517 /* If the register is set or already dead at PLACE, we needn't do
12518 anything with this note if it is still a REG_DEAD note.
12519 We can here if it is set at all, not if is it totally replace,
12520 which is what `dead_or_set_p' checks, so also check for it being
12523 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12525 unsigned int regno = REGNO (XEXP (note, 0));
12527 if (dead_or_set_p (place, XEXP (note, 0))
12528 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12530 /* Unless the register previously died in PLACE, clear
12531 reg_last_death. [I no longer understand why this is
12533 if (reg_last_death[regno] != place)
12534 reg_last_death[regno] = 0;
12538 reg_last_death[regno] = place;
12540 /* If this is a death note for a hard reg that is occupying
12541 multiple registers, ensure that we are still using all
12542 parts of the object. If we find a piece of the object
12543 that is unused, we must arrange for an appropriate REG_DEAD
12544 note to be added for it. However, we can't just emit a USE
12545 and tag the note to it, since the register might actually
12546 be dead; so we recourse, and the recursive call then finds
12547 the previous insn that used this register. */
12549 if (place && regno < FIRST_PSEUDO_REGISTER
12550 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
12552 unsigned int endregno
12553 = regno + HARD_REGNO_NREGS (regno,
12554 GET_MODE (XEXP (note, 0)));
12558 for (i = regno; i < endregno; i++)
12559 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12560 && ! find_regno_fusage (place, USE, i))
12561 || dead_or_set_regno_p (place, i))
12566 /* Put only REG_DEAD notes for pieces that are
12567 not already dead or set. */
12569 for (i = regno; i < endregno;
12570 i += HARD_REGNO_NREGS (i, reg_raw_mode[i]))
12572 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
12573 basic_block bb = BASIC_BLOCK (this_basic_block);
12575 if (! dead_or_set_p (place, piece)
12576 && ! reg_bitfield_target_p (piece,
12580 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12582 distribute_notes (new_note, place, place,
12583 NULL_RTX, NULL_RTX, NULL_RTX);
12585 else if (! refers_to_regno_p (i, i + 1,
12586 PATTERN (place), 0)
12587 && ! find_regno_fusage (place, USE, i))
12588 for (tem = PREV_INSN (place); ;
12589 tem = PREV_INSN (tem))
12591 if (! INSN_P (tem))
12593 if (tem == bb->head)
12595 SET_BIT (refresh_blocks,
12602 if (dead_or_set_p (tem, piece)
12603 || reg_bitfield_target_p (piece,
12607 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12622 /* Any other notes should not be present at this point in the
12629 XEXP (note, 1) = REG_NOTES (place);
12630 REG_NOTES (place) = note;
12632 else if ((REG_NOTE_KIND (note) == REG_DEAD
12633 || REG_NOTE_KIND (note) == REG_UNUSED)
12634 && GET_CODE (XEXP (note, 0)) == REG)
12635 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12639 if ((REG_NOTE_KIND (note) == REG_DEAD
12640 || REG_NOTE_KIND (note) == REG_UNUSED)
12641 && GET_CODE (XEXP (note, 0)) == REG)
12642 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12644 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12645 REG_NOTE_KIND (note),
12647 REG_NOTES (place2));
12652 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12653 I3, I2, and I1 to new locations. This is also called in one case to
12654 add a link pointing at I3 when I3's destination is changed. */
12657 distribute_links (links)
12660 rtx link, next_link;
12662 for (link = links; link; link = next_link)
12668 next_link = XEXP (link, 1);
12670 /* If the insn that this link points to is a NOTE or isn't a single
12671 set, ignore it. In the latter case, it isn't clear what we
12672 can do other than ignore the link, since we can't tell which
12673 register it was for. Such links wouldn't be used by combine
12676 It is not possible for the destination of the target of the link to
12677 have been changed by combine. The only potential of this is if we
12678 replace I3, I2, and I1 by I3 and I2. But in that case the
12679 destination of I2 also remains unchanged. */
12681 if (GET_CODE (XEXP (link, 0)) == NOTE
12682 || (set = single_set (XEXP (link, 0))) == 0)
12685 reg = SET_DEST (set);
12686 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12687 || GET_CODE (reg) == SIGN_EXTRACT
12688 || GET_CODE (reg) == STRICT_LOW_PART)
12689 reg = XEXP (reg, 0);
12691 /* A LOG_LINK is defined as being placed on the first insn that uses
12692 a register and points to the insn that sets the register. Start
12693 searching at the next insn after the target of the link and stop
12694 when we reach a set of the register or the end of the basic block.
12696 Note that this correctly handles the link that used to point from
12697 I3 to I2. Also note that not much searching is typically done here
12698 since most links don't point very far away. */
12700 for (insn = NEXT_INSN (XEXP (link, 0));
12701 (insn && (this_basic_block == n_basic_blocks - 1
12702 || BLOCK_HEAD (this_basic_block + 1) != insn));
12703 insn = NEXT_INSN (insn))
12704 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12706 if (reg_referenced_p (reg, PATTERN (insn)))
12710 else if (GET_CODE (insn) == CALL_INSN
12711 && find_reg_fusage (insn, USE, reg))
12717 /* If we found a place to put the link, place it there unless there
12718 is already a link to the same insn as LINK at that point. */
12724 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12725 if (XEXP (link2, 0) == XEXP (link, 0))
12730 XEXP (link, 1) = LOG_LINKS (place);
12731 LOG_LINKS (place) = link;
12733 /* Set added_links_insn to the earliest insn we added a
12735 if (added_links_insn == 0
12736 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12737 added_links_insn = place;
12743 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12749 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12750 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
12751 insn = NEXT_INSN (insn);
12753 if (INSN_UID (insn) > max_uid_cuid)
12756 return INSN_CUID (insn);
12760 dump_combine_stats (file)
12765 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12766 combine_attempts, combine_merges, combine_extras, combine_successes);
12770 dump_combine_total_stats (file)
12775 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12776 total_attempts, total_merges, total_extras, total_successes);