1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 88, 92-98, 1999 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "rtl.h" /* stdio.h must precede rtl.h for FFS. */
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
85 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
87 #include "insn-flags.h"
88 #include "insn-codes.h"
89 #include "insn-attr.h"
94 /* It is not safe to use ordinary gen_lowpart in combine.
95 Use gen_lowpart_for_combine instead. See comments there. */
96 #define gen_lowpart dont_use_gen_lowpart_you_dummy
98 /* Number of attempts to combine instructions in this function. */
100 static int combine_attempts;
102 /* Number of attempts that got as far as substitution in this function. */
104 static int combine_merges;
106 /* Number of instructions combined with added SETs in this function. */
108 static int combine_extras;
110 /* Number of instructions combined in this function. */
112 static int combine_successes;
114 /* Totals over entire compilation. */
116 static int total_attempts, total_merges, total_extras, total_successes;
118 /* Define a default value for REVERSIBLE_CC_MODE.
119 We can never assume that a condition code mode is safe to reverse unless
120 the md tells us so. */
121 #ifndef REVERSIBLE_CC_MODE
122 #define REVERSIBLE_CC_MODE(MODE) 0
125 /* Vector mapping INSN_UIDs to cuids.
126 The cuids are like uids but increase monotonically always.
127 Combine always uses cuids so that it can compare them.
128 But actually renumbering the uids, which we used to do,
129 proves to be a bad idea because it makes it hard to compare
130 the dumps produced by earlier passes with those from later passes. */
132 static int *uid_cuid;
133 static int max_uid_cuid;
135 /* Get the cuid of an insn. */
137 #define INSN_CUID(INSN) \
138 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
140 /* Maximum register number, which is the size of the tables below. */
142 static int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
146 static rtx *reg_last_death;
148 /* Record last point of modification of (hard or pseudo) register n. */
150 static rtx *reg_last_set;
152 /* Record the cuid of the last insn that invalidated memory
153 (anything that writes memory, and subroutine calls, but not pushes). */
155 static int mem_last_set;
157 /* Record the cuid of the last CALL_INSN
158 so we can tell whether a potential combination crosses any calls. */
160 static int last_call_cuid;
162 /* When `subst' is called, this is the insn that is being modified
163 (by combining in a previous insn). The PATTERN of this insn
164 is still the old pattern partially modified and it should not be
165 looked at, but this may be used to examine the successors of the insn
166 to judge whether a simplification is valid. */
168 static rtx subst_insn;
170 /* This is an insn that belongs before subst_insn, but is not currently
171 on the insn chain. */
173 static rtx subst_prev_insn;
175 /* This is the lowest CUID that `subst' is currently dealing with.
176 get_last_value will not return a value if the register was set at or
177 after this CUID. If not for this mechanism, we could get confused if
178 I2 or I1 in try_combine were an insn that used the old value of a register
179 to obtain a new value. In that case, we might erroneously get the
180 new value of the register when we wanted the old one. */
182 static int subst_low_cuid;
184 /* This contains any hard registers that are used in newpat; reg_dead_at_p
185 must consider all these registers to be always live. */
187 static HARD_REG_SET newpat_used_regs;
189 /* This is an insn to which a LOG_LINKS entry has been added. If this
190 insn is the earlier than I2 or I3, combine should rescan starting at
193 static rtx added_links_insn;
195 /* Basic block number of the block in which we are performing combines. */
196 static int this_basic_block;
198 /* The next group of arrays allows the recording of the last value assigned
199 to (hard or pseudo) register n. We use this information to see if a
200 operation being processed is redundant given a prior operation performed
201 on the register. For example, an `and' with a constant is redundant if
202 all the zero bits are already known to be turned off.
204 We use an approach similar to that used by cse, but change it in the
207 (1) We do not want to reinitialize at each label.
208 (2) It is useful, but not critical, to know the actual value assigned
209 to a register. Often just its form is helpful.
211 Therefore, we maintain the following arrays:
213 reg_last_set_value the last value assigned
214 reg_last_set_label records the value of label_tick when the
215 register was assigned
216 reg_last_set_table_tick records the value of label_tick when a
217 value using the register is assigned
218 reg_last_set_invalid set to non-zero when it is not valid
219 to use the value of this register in some
222 To understand the usage of these tables, it is important to understand
223 the distinction between the value in reg_last_set_value being valid
224 and the register being validly contained in some other expression in the
227 Entry I in reg_last_set_value is valid if it is non-zero, and either
228 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
230 Register I may validly appear in any expression returned for the value
231 of another register if reg_n_sets[i] is 1. It may also appear in the
232 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
233 reg_last_set_invalid[j] is zero.
235 If an expression is found in the table containing a register which may
236 not validly appear in an expression, the register is replaced by
237 something that won't match, (clobber (const_int 0)).
239 reg_last_set_invalid[i] is set non-zero when register I is being assigned
240 to and reg_last_set_table_tick[i] == label_tick. */
242 /* Record last value assigned to (hard or pseudo) register n. */
244 static rtx *reg_last_set_value;
246 /* Record the value of label_tick when the value for register n is placed in
247 reg_last_set_value[n]. */
249 static int *reg_last_set_label;
251 /* Record the value of label_tick when an expression involving register n
252 is placed in reg_last_set_value. */
254 static int *reg_last_set_table_tick;
256 /* Set non-zero if references to register n in expressions should not be
259 static char *reg_last_set_invalid;
261 /* Incremented for each label. */
263 static int label_tick;
265 /* Some registers that are set more than once and used in more than one
266 basic block are nevertheless always set in similar ways. For example,
267 a QImode register may be loaded from memory in two places on a machine
268 where byte loads zero extend.
270 We record in the following array what we know about the nonzero
271 bits of a register, specifically which bits are known to be zero.
273 If an entry is zero, it means that we don't know anything special. */
275 static unsigned HOST_WIDE_INT *reg_nonzero_bits;
277 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
278 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
280 static enum machine_mode nonzero_bits_mode;
282 /* Nonzero if we know that a register has some leading bits that are always
283 equal to the sign bit. */
285 static char *reg_sign_bit_copies;
287 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
288 It is zero while computing them and after combine has completed. This
289 former test prevents propagating values based on previously set values,
290 which can be incorrect if a variable is modified in a loop. */
292 static int nonzero_sign_valid;
294 /* These arrays are maintained in parallel with reg_last_set_value
295 and are used to store the mode in which the register was last set,
296 the bits that were known to be zero when it was last set, and the
297 number of sign bits copies it was known to have when it was last set. */
299 static enum machine_mode *reg_last_set_mode;
300 static unsigned HOST_WIDE_INT *reg_last_set_nonzero_bits;
301 static char *reg_last_set_sign_bit_copies;
303 /* Record one modification to rtl structure
304 to be undone by storing old_contents into *where.
305 is_int is 1 if the contents are an int. */
311 union {rtx r; int i;} old_contents;
312 union {rtx *r; int *i;} where;
315 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
316 num_undo says how many are currently recorded.
318 storage is nonzero if we must undo the allocation of new storage.
319 The value of storage is what to pass to obfree.
321 other_insn is nonzero if we have modified some other insn in the process
322 of working on subst_insn. It must be verified too.
324 previous_undos is the value of undobuf.undos when we started processing
325 this substitution. This will prevent gen_rtx_combine from re-used a piece
326 from the previous expression. Doing so can produce circular rtl
334 struct undo *previous_undos;
338 static struct undobuf undobuf;
340 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
341 insn. The substitution can be undone by undo_all. If INTO is already
342 set to NEWVAL, do not record this change. Because computing NEWVAL might
343 also call SUBST, we have to compute it before we put anything into
346 #define SUBST(INTO, NEWVAL) \
347 do { rtx _new = (NEWVAL); \
351 _buf = undobuf.frees, undobuf.frees = _buf->next; \
353 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
356 _buf->where.r = &INTO; \
357 _buf->old_contents.r = INTO; \
359 if (_buf->old_contents.r == INTO) \
360 _buf->next = undobuf.frees, undobuf.frees = _buf; \
362 _buf->next = undobuf.undos, undobuf.undos = _buf; \
365 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
366 for the value of a HOST_WIDE_INT value (including CONST_INT) is
369 #define SUBST_INT(INTO, NEWVAL) \
370 do { struct undo *_buf; \
373 _buf = undobuf.frees, undobuf.frees = _buf->next; \
375 _buf = (struct undo *) xmalloc (sizeof (struct undo)); \
378 _buf->where.i = (int *) &INTO; \
379 _buf->old_contents.i = INTO; \
381 if (_buf->old_contents.i == INTO) \
382 _buf->next = undobuf.frees, undobuf.frees = _buf; \
384 _buf->next = undobuf.undos, undobuf.undos = _buf; \
387 /* Number of times the pseudo being substituted for
388 was found and replaced. */
390 static int n_occurrences;
392 static void init_reg_last_arrays PROTO((void));
393 static void setup_incoming_promotions PROTO((void));
394 static void set_nonzero_bits_and_sign_copies PROTO((rtx, rtx));
395 static int can_combine_p PROTO((rtx, rtx, rtx, rtx, rtx *, rtx *));
396 static int sets_function_arg_p PROTO((rtx));
397 static int combinable_i3pat PROTO((rtx, rtx *, rtx, rtx, int, rtx *));
398 static rtx try_combine PROTO((rtx, rtx, rtx));
399 static void undo_all PROTO((void));
400 static rtx *find_split_point PROTO((rtx *, rtx));
401 static rtx subst PROTO((rtx, rtx, rtx, int, int));
402 static rtx simplify_rtx PROTO((rtx, enum machine_mode, int, int));
403 static rtx simplify_if_then_else PROTO((rtx));
404 static rtx simplify_set PROTO((rtx));
405 static rtx simplify_logical PROTO((rtx, int));
406 static rtx expand_compound_operation PROTO((rtx));
407 static rtx expand_field_assignment PROTO((rtx));
408 static rtx make_extraction PROTO((enum machine_mode, rtx, int, rtx, int,
410 static rtx extract_left_shift PROTO((rtx, int));
411 static rtx make_compound_operation PROTO((rtx, enum rtx_code));
412 static int get_pos_from_mask PROTO((unsigned HOST_WIDE_INT, int *));
413 static rtx force_to_mode PROTO((rtx, enum machine_mode,
414 unsigned HOST_WIDE_INT, rtx, int));
415 static rtx if_then_else_cond PROTO((rtx, rtx *, rtx *));
416 static rtx known_cond PROTO((rtx, enum rtx_code, rtx, rtx));
417 static int rtx_equal_for_field_assignment_p PROTO((rtx, rtx));
418 static rtx make_field_assignment PROTO((rtx));
419 static rtx apply_distributive_law PROTO((rtx));
420 static rtx simplify_and_const_int PROTO((rtx, enum machine_mode, rtx,
421 unsigned HOST_WIDE_INT));
422 static unsigned HOST_WIDE_INT nonzero_bits PROTO((rtx, enum machine_mode));
423 static int num_sign_bit_copies PROTO((rtx, enum machine_mode));
424 static int merge_outer_ops PROTO((enum rtx_code *, HOST_WIDE_INT *,
425 enum rtx_code, HOST_WIDE_INT,
426 enum machine_mode, int *));
427 static rtx simplify_shift_const PROTO((rtx, enum rtx_code, enum machine_mode,
429 static int recog_for_combine PROTO((rtx *, rtx, rtx *));
430 static rtx gen_lowpart_for_combine PROTO((enum machine_mode, rtx));
431 static rtx gen_rtx_combine PVPROTO((enum rtx_code code, enum machine_mode mode,
433 static rtx gen_binary PROTO((enum rtx_code, enum machine_mode,
435 static rtx gen_unary PROTO((enum rtx_code, enum machine_mode,
436 enum machine_mode, rtx));
437 static enum rtx_code simplify_comparison PROTO((enum rtx_code, rtx *, rtx *));
438 static int reversible_comparison_p PROTO((rtx));
439 static void update_table_tick PROTO((rtx));
440 static void record_value_for_reg PROTO((rtx, rtx, rtx));
441 static void record_dead_and_set_regs_1 PROTO((rtx, rtx));
442 static void record_dead_and_set_regs PROTO((rtx));
443 static int get_last_value_validate PROTO((rtx *, rtx, int, int));
444 static rtx get_last_value PROTO((rtx));
445 static int use_crosses_set_p PROTO((rtx, int));
446 static void reg_dead_at_p_1 PROTO((rtx, rtx));
447 static int reg_dead_at_p PROTO((rtx, rtx));
448 static void move_deaths PROTO((rtx, rtx, int, rtx, rtx *));
449 static int reg_bitfield_target_p PROTO((rtx, rtx));
450 static void distribute_notes PROTO((rtx, rtx, rtx, rtx, rtx, rtx));
451 static void distribute_links PROTO((rtx));
452 static void mark_used_regs_combine PROTO((rtx));
453 static int insn_cuid PROTO((rtx));
455 /* Main entry point for combiner. F is the first insn of the function.
456 NREGS is the first unused pseudo-reg number. */
459 combine_instructions (f, nregs)
463 register rtx insn, next;
468 register rtx links, nextlinks;
470 combine_attempts = 0;
473 combine_successes = 0;
474 undobuf.undos = undobuf.previous_undos = 0;
476 combine_max_regno = nregs;
479 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
480 reg_sign_bit_copies = (char *) alloca (nregs * sizeof (char));
482 bzero ((char *) reg_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
483 bzero (reg_sign_bit_copies, nregs * sizeof (char));
485 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
486 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
487 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
488 reg_last_set_table_tick = (int *) alloca (nregs * sizeof (int));
489 reg_last_set_label = (int *) alloca (nregs * sizeof (int));
490 reg_last_set_invalid = (char *) alloca (nregs * sizeof (char));
492 = (enum machine_mode *) alloca (nregs * sizeof (enum machine_mode));
493 reg_last_set_nonzero_bits
494 = (unsigned HOST_WIDE_INT *) alloca (nregs * sizeof (HOST_WIDE_INT));
495 reg_last_set_sign_bit_copies
496 = (char *) alloca (nregs * sizeof (char));
498 init_reg_last_arrays ();
500 init_recog_no_volatile ();
502 /* Compute maximum uid value so uid_cuid can be allocated. */
504 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
505 if (INSN_UID (insn) > i)
508 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
511 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
513 /* Don't use reg_nonzero_bits when computing it. This can cause problems
514 when, for example, we have j <<= 1 in a loop. */
516 nonzero_sign_valid = 0;
518 /* Compute the mapping from uids to cuids.
519 Cuids are numbers assigned to insns, like uids,
520 except that cuids increase monotonically through the code.
522 Scan all SETs and see if we can deduce anything about what
523 bits are known to be zero for some registers and how many copies
524 of the sign bit are known to exist for those registers.
526 Also set any known values so that we can use it while searching
527 for what bits are known to be set. */
531 /* We need to initialize it here, because record_dead_and_set_regs may call
533 subst_prev_insn = NULL_RTX;
535 setup_incoming_promotions ();
537 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
539 uid_cuid[INSN_UID (insn)] = ++i;
543 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
545 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies);
546 record_dead_and_set_regs (insn);
549 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
550 if (REG_NOTE_KIND (links) == REG_INC)
551 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX);
555 if (GET_CODE (insn) == CODE_LABEL)
559 nonzero_sign_valid = 1;
561 /* Now scan all the insns in forward order. */
563 this_basic_block = -1;
567 init_reg_last_arrays ();
568 setup_incoming_promotions ();
570 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
574 /* If INSN starts a new basic block, update our basic block number. */
575 if (this_basic_block + 1 < n_basic_blocks
576 && BLOCK_HEAD (this_basic_block + 1) == insn)
579 if (GET_CODE (insn) == CODE_LABEL)
582 else if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
584 /* Try this insn with each insn it links back to. */
586 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
587 if ((next = try_combine (insn, XEXP (links, 0), NULL_RTX)) != 0)
590 /* Try each sequence of three linked insns ending with this one. */
592 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
593 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
594 nextlinks = XEXP (nextlinks, 1))
595 if ((next = try_combine (insn, XEXP (links, 0),
596 XEXP (nextlinks, 0))) != 0)
600 /* Try to combine a jump insn that uses CC0
601 with a preceding insn that sets CC0, and maybe with its
602 logical predecessor as well.
603 This is how we make decrement-and-branch insns.
604 We need this special code because data flow connections
605 via CC0 do not get entered in LOG_LINKS. */
607 if (GET_CODE (insn) == JUMP_INSN
608 && (prev = prev_nonnote_insn (insn)) != 0
609 && GET_CODE (prev) == INSN
610 && sets_cc0_p (PATTERN (prev)))
612 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
615 for (nextlinks = LOG_LINKS (prev); nextlinks;
616 nextlinks = XEXP (nextlinks, 1))
617 if ((next = try_combine (insn, prev,
618 XEXP (nextlinks, 0))) != 0)
622 /* Do the same for an insn that explicitly references CC0. */
623 if (GET_CODE (insn) == INSN
624 && (prev = prev_nonnote_insn (insn)) != 0
625 && GET_CODE (prev) == INSN
626 && sets_cc0_p (PATTERN (prev))
627 && GET_CODE (PATTERN (insn)) == SET
628 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
630 if ((next = try_combine (insn, prev, NULL_RTX)) != 0)
633 for (nextlinks = LOG_LINKS (prev); nextlinks;
634 nextlinks = XEXP (nextlinks, 1))
635 if ((next = try_combine (insn, prev,
636 XEXP (nextlinks, 0))) != 0)
640 /* Finally, see if any of the insns that this insn links to
641 explicitly references CC0. If so, try this insn, that insn,
642 and its predecessor if it sets CC0. */
643 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
644 if (GET_CODE (XEXP (links, 0)) == INSN
645 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
646 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
647 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
648 && GET_CODE (prev) == INSN
649 && sets_cc0_p (PATTERN (prev))
650 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
654 /* Try combining an insn with two different insns whose results it
656 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
657 for (nextlinks = XEXP (links, 1); nextlinks;
658 nextlinks = XEXP (nextlinks, 1))
659 if ((next = try_combine (insn, XEXP (links, 0),
660 XEXP (nextlinks, 0))) != 0)
663 if (GET_CODE (insn) != NOTE)
664 record_dead_and_set_regs (insn);
671 total_attempts += combine_attempts;
672 total_merges += combine_merges;
673 total_extras += combine_extras;
674 total_successes += combine_successes;
676 nonzero_sign_valid = 0;
678 /* Make recognizer allow volatile MEMs again. */
682 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
685 init_reg_last_arrays ()
687 int nregs = combine_max_regno;
689 bzero ((char *) reg_last_death, nregs * sizeof (rtx));
690 bzero ((char *) reg_last_set, nregs * sizeof (rtx));
691 bzero ((char *) reg_last_set_value, nregs * sizeof (rtx));
692 bzero ((char *) reg_last_set_table_tick, nregs * sizeof (int));
693 bzero ((char *) reg_last_set_label, nregs * sizeof (int));
694 bzero (reg_last_set_invalid, nregs * sizeof (char));
695 bzero ((char *) reg_last_set_mode, nregs * sizeof (enum machine_mode));
696 bzero ((char *) reg_last_set_nonzero_bits, nregs * sizeof (HOST_WIDE_INT));
697 bzero (reg_last_set_sign_bit_copies, nregs * sizeof (char));
700 /* Set up any promoted values for incoming argument registers. */
703 setup_incoming_promotions ()
705 #ifdef PROMOTE_FUNCTION_ARGS
708 enum machine_mode mode;
710 rtx first = get_insns ();
712 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
713 if (FUNCTION_ARG_REGNO_P (regno)
714 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
717 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
720 gen_rtx_CLOBBER (mode, const0_rtx)));
725 /* Called via note_stores. If X is a pseudo that is narrower than
726 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
728 If we are setting only a portion of X and we can't figure out what
729 portion, assume all bits will be used since we don't know what will
732 Similarly, set how many bits of X are known to be copies of the sign bit
733 at all locations in the function. This is the smallest number implied
737 set_nonzero_bits_and_sign_copies (x, set)
743 if (GET_CODE (x) == REG
744 && REGNO (x) >= FIRST_PSEUDO_REGISTER
745 /* If this register is undefined at the start of the file, we can't
746 say what its contents were. */
747 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start, REGNO (x))
748 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
750 if (set == 0 || GET_CODE (set) == CLOBBER)
752 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
753 reg_sign_bit_copies[REGNO (x)] = 1;
757 /* If this is a complex assignment, see if we can convert it into a
758 simple assignment. */
759 set = expand_field_assignment (set);
761 /* If this is a simple assignment, or we have a paradoxical SUBREG,
762 set what we know about X. */
764 if (SET_DEST (set) == x
765 || (GET_CODE (SET_DEST (set)) == SUBREG
766 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
767 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
768 && SUBREG_REG (SET_DEST (set)) == x))
770 rtx src = SET_SRC (set);
772 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
773 /* If X is narrower than a word and SRC is a non-negative
774 constant that would appear negative in the mode of X,
775 sign-extend it for use in reg_nonzero_bits because some
776 machines (maybe most) will actually do the sign-extension
777 and this is the conservative approach.
779 ??? For 2.5, try to tighten up the MD files in this regard
780 instead of this kludge. */
782 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
783 && GET_CODE (src) == CONST_INT
785 && 0 != (INTVAL (src)
787 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
788 src = GEN_INT (INTVAL (src)
789 | ((HOST_WIDE_INT) (-1)
790 << GET_MODE_BITSIZE (GET_MODE (x))));
793 reg_nonzero_bits[REGNO (x)]
794 |= nonzero_bits (src, nonzero_bits_mode);
795 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
796 if (reg_sign_bit_copies[REGNO (x)] == 0
797 || reg_sign_bit_copies[REGNO (x)] > num)
798 reg_sign_bit_copies[REGNO (x)] = num;
802 reg_nonzero_bits[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
803 reg_sign_bit_copies[REGNO (x)] = 1;
808 /* See if INSN can be combined into I3. PRED and SUCC are optionally
809 insns that were previously combined into I3 or that will be combined
810 into the merger of INSN and I3.
812 Return 0 if the combination is not allowed for any reason.
814 If the combination is allowed, *PDEST will be set to the single
815 destination of INSN and *PSRC to the single source, and this function
819 can_combine_p (insn, i3, pred, succ, pdest, psrc)
822 rtx pred ATTRIBUTE_UNUSED;
827 rtx set = 0, src, dest;
832 int all_adjacent = (succ ? (next_active_insn (insn) == succ
833 && next_active_insn (succ) == i3)
834 : next_active_insn (insn) == i3);
836 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
837 or a PARALLEL consisting of such a SET and CLOBBERs.
839 If INSN has CLOBBER parallel parts, ignore them for our processing.
840 By definition, these happen during the execution of the insn. When it
841 is merged with another insn, all bets are off. If they are, in fact,
842 needed and aren't also supplied in I3, they may be added by
843 recog_for_combine. Otherwise, it won't match.
845 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
848 Get the source and destination of INSN. If more than one, can't
851 if (GET_CODE (PATTERN (insn)) == SET)
852 set = PATTERN (insn);
853 else if (GET_CODE (PATTERN (insn)) == PARALLEL
854 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
856 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
858 rtx elt = XVECEXP (PATTERN (insn), 0, i);
860 switch (GET_CODE (elt))
862 /* This is important to combine floating point insns
865 /* Combining an isolated USE doesn't make sense.
866 We depend here on combinable_i3_pat to reject them. */
867 /* The code below this loop only verifies that the inputs of
868 the SET in INSN do not change. We call reg_set_between_p
869 to verify that the REG in the USE does not change betweeen
871 If the USE in INSN was for a pseudo register, the matching
872 insn pattern will likely match any register; combining this
873 with any other USE would only be safe if we knew that the
874 used registers have identical values, or if there was
875 something to tell them apart, e.g. different modes. For
876 now, we forgo such compilcated tests and simply disallow
877 combining of USES of pseudo registers with any other USE. */
878 if (GET_CODE (XEXP (elt, 0)) == REG
879 && GET_CODE (PATTERN (i3)) == PARALLEL)
881 rtx i3pat = PATTERN (i3);
882 int i = XVECLEN (i3pat, 0) - 1;
883 int regno = REGNO (XEXP (elt, 0));
886 rtx i3elt = XVECEXP (i3pat, 0, i);
887 if (GET_CODE (i3elt) == USE
888 && GET_CODE (XEXP (i3elt, 0)) == REG
889 && (REGNO (XEXP (i3elt, 0)) == regno
890 ? reg_set_between_p (XEXP (elt, 0),
891 PREV_INSN (insn), i3)
892 : regno >= FIRST_PSEUDO_REGISTER))
899 /* We can ignore CLOBBERs. */
904 /* Ignore SETs whose result isn't used but not those that
905 have side-effects. */
906 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
907 && ! side_effects_p (elt))
910 /* If we have already found a SET, this is a second one and
911 so we cannot combine with this insn. */
919 /* Anything else means we can't combine. */
925 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
926 so don't do anything with it. */
927 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
936 set = expand_field_assignment (set);
937 src = SET_SRC (set), dest = SET_DEST (set);
939 /* Don't eliminate a store in the stack pointer. */
940 if (dest == stack_pointer_rtx
941 /* If we couldn't eliminate a field assignment, we can't combine. */
942 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
943 /* Don't combine with an insn that sets a register to itself if it has
944 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
945 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
946 /* Can't merge a function call. */
947 || GET_CODE (src) == CALL
948 /* Don't eliminate a function call argument. */
949 || (GET_CODE (i3) == CALL_INSN
950 && (find_reg_fusage (i3, USE, dest)
951 || (GET_CODE (dest) == REG
952 && REGNO (dest) < FIRST_PSEUDO_REGISTER
953 && global_regs[REGNO (dest)])))
954 /* Don't substitute into an incremented register. */
955 || FIND_REG_INC_NOTE (i3, dest)
956 || (succ && FIND_REG_INC_NOTE (succ, dest))
958 /* Don't combine the end of a libcall into anything. */
959 /* ??? This gives worse code, and appears to be unnecessary, since no
960 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
961 use REG_RETVAL notes for noconflict blocks, but other code here
962 makes sure that those insns don't disappear. */
963 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
965 /* Make sure that DEST is not used after SUCC but before I3. */
966 || (succ && ! all_adjacent
967 && reg_used_between_p (dest, succ, i3))
968 /* Make sure that the value that is to be substituted for the register
969 does not use any registers whose values alter in between. However,
970 If the insns are adjacent, a use can't cross a set even though we
971 think it might (this can happen for a sequence of insns each setting
972 the same destination; reg_last_set of that register might point to
973 a NOTE). If INSN has a REG_EQUIV note, the register is always
974 equivalent to the memory so the substitution is valid even if there
975 are intervening stores. Also, don't move a volatile asm or
976 UNSPEC_VOLATILE across any other insns. */
978 && (((GET_CODE (src) != MEM
979 || ! find_reg_note (insn, REG_EQUIV, src))
980 && use_crosses_set_p (src, INSN_CUID (insn)))
981 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
982 || GET_CODE (src) == UNSPEC_VOLATILE))
983 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
984 better register allocation by not doing the combine. */
985 || find_reg_note (i3, REG_NO_CONFLICT, dest)
986 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
987 /* Don't combine across a CALL_INSN, because that would possibly
988 change whether the life span of some REGs crosses calls or not,
989 and it is a pain to update that information.
990 Exception: if source is a constant, moving it later can't hurt.
991 Accept that special case, because it helps -fforce-addr a lot. */
992 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
995 /* DEST must either be a REG or CC0. */
996 if (GET_CODE (dest) == REG)
998 /* If register alignment is being enforced for multi-word items in all
999 cases except for parameters, it is possible to have a register copy
1000 insn referencing a hard register that is not allowed to contain the
1001 mode being copied and which would not be valid as an operand of most
1002 insns. Eliminate this problem by not combining with such an insn.
1004 Also, on some machines we don't want to extend the life of a hard
1007 This is the same test done in can_combine except that we don't test
1008 if SRC is a CALL operation to permit a hard register with
1009 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1012 if (GET_CODE (src) == REG
1013 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1014 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1015 /* Don't extend the life of a hard register unless it is
1016 user variable (if we have few registers) or it can't
1017 fit into the desired register (meaning something special
1019 Also avoid substituting a return register into I3, because
1020 reload can't handle a conflict with constraints of other
1022 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1023 && (! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src))
1024 || (SMALL_REGISTER_CLASSES
1025 && ((! all_adjacent && ! REG_USERVAR_P (src))
1026 || (FUNCTION_VALUE_REGNO_P (REGNO (src))
1027 && ! REG_USERVAR_P (src))))))))
1030 else if (GET_CODE (dest) != CC0)
1033 /* Don't substitute for a register intended as a clobberable operand.
1034 Similarly, don't substitute an expression containing a register that
1035 will be clobbered in I3. */
1036 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1037 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1038 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
1039 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0),
1041 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest)))
1044 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1045 or not), reject, unless nothing volatile comes between it and I3 */
1047 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1049 /* Make sure succ doesn't contain a volatile reference. */
1050 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1053 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1054 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1055 && p != succ && volatile_refs_p (PATTERN (p)))
1059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1060 to be an explicit register variable, and was chosen for a reason. */
1062 if (GET_CODE (src) == ASM_OPERANDS
1063 && GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1066 /* If there are any volatile insns between INSN and I3, reject, because
1067 they might affect machine state. */
1069 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1070 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
1071 && p != succ && volatile_insn_p (PATTERN (p)))
1074 /* If INSN or I2 contains an autoincrement or autodecrement,
1075 make sure that register is not used between there and I3,
1076 and not already used in I3 either.
1077 Also insist that I3 not be a jump; if it were one
1078 and the incremented register were spilled, we would lose. */
1081 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1082 if (REG_NOTE_KIND (link) == REG_INC
1083 && (GET_CODE (i3) == JUMP_INSN
1084 || reg_used_between_p (XEXP (link, 0), insn, i3)
1085 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1090 /* Don't combine an insn that follows a CC0-setting insn.
1091 An insn that uses CC0 must not be separated from the one that sets it.
1092 We do, however, allow I2 to follow a CC0-setting insn if that insn
1093 is passed as I1; in that case it will be deleted also.
1094 We also allow combining in this case if all the insns are adjacent
1095 because that would leave the two CC0 insns adjacent as well.
1096 It would be more logical to test whether CC0 occurs inside I1 or I2,
1097 but that would be much slower, and this ought to be equivalent. */
1099 p = prev_nonnote_insn (insn);
1100 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
1105 /* If we get here, we have passed all the tests and the combination is
1114 /* Check if PAT is an insn - or a part of it - used to set up an
1115 argument for a function in a hard register. */
1118 sets_function_arg_p (pat)
1124 switch (GET_CODE (pat))
1127 return sets_function_arg_p (PATTERN (pat));
1130 for (i = XVECLEN (pat, 0); --i >= 0;)
1131 if (sets_function_arg_p (XVECEXP (pat, 0, i)))
1137 inner_dest = SET_DEST (pat);
1138 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1139 || GET_CODE (inner_dest) == SUBREG
1140 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1141 inner_dest = XEXP (inner_dest, 0);
1143 return (GET_CODE (inner_dest) == REG
1144 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1145 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest)));
1154 /* LOC is the location within I3 that contains its pattern or the component
1155 of a PARALLEL of the pattern. We validate that it is valid for combining.
1157 One problem is if I3 modifies its output, as opposed to replacing it
1158 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1159 so would produce an insn that is not equivalent to the original insns.
1163 (set (reg:DI 101) (reg:DI 100))
1164 (set (subreg:SI (reg:DI 101) 0) <foo>)
1166 This is NOT equivalent to:
1168 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1169 (set (reg:DI 101) (reg:DI 100))])
1171 Not only does this modify 100 (in which case it might still be valid
1172 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1174 We can also run into a problem if I2 sets a register that I1
1175 uses and I1 gets directly substituted into I3 (not via I2). In that
1176 case, we would be getting the wrong value of I2DEST into I3, so we
1177 must reject the combination. This case occurs when I2 and I1 both
1178 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1179 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1180 of a SET must prevent combination from occurring.
1182 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1183 if the destination of a SET is a hard register that isn't a user
1186 Before doing the above check, we first try to expand a field assignment
1187 into a set of logical operations.
1189 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1190 we place a register that is both set and used within I3. If more than one
1191 such register is detected, we fail.
1193 Return 1 if the combination is valid, zero otherwise. */
1196 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
1202 rtx *pi3dest_killed;
1206 if (GET_CODE (x) == SET)
1208 rtx set = expand_field_assignment (x);
1209 rtx dest = SET_DEST (set);
1210 rtx src = SET_SRC (set);
1211 rtx inner_dest = dest;
1214 rtx inner_src = src;
1219 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1220 || GET_CODE (inner_dest) == SUBREG
1221 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1222 inner_dest = XEXP (inner_dest, 0);
1224 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1227 while (GET_CODE (inner_src) == STRICT_LOW_PART
1228 || GET_CODE (inner_src) == SUBREG
1229 || GET_CODE (inner_src) == ZERO_EXTRACT)
1230 inner_src = XEXP (inner_src, 0);
1232 /* If it is better that two different modes keep two different pseudos,
1233 avoid combining them. This avoids producing the following pattern
1235 (set (subreg:SI (reg/v:QI 21) 0)
1236 (lshiftrt:SI (reg/v:SI 20)
1238 If that were made, reload could not handle the pair of
1239 reg 20/21, since it would try to get any GENERAL_REGS
1240 but some of them don't handle QImode. */
1242 if (rtx_equal_p (inner_src, i2dest)
1243 && GET_CODE (inner_dest) == REG
1244 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
1248 /* Check for the case where I3 modifies its output, as
1250 if ((inner_dest != dest
1251 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1252 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1254 /* This is the same test done in can_combine_p except that we
1255 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1256 CALL operation. Moreover, we can't test all_adjacent; we don't
1257 have to, since this instruction will stay in place, thus we are
1258 not considering increasing the lifetime of INNER_DEST.
1260 Also, if this insn sets a function argument, combining it with
1261 something that might need a spill could clobber a previous
1262 function argument; the all_adjacent test in can_combine_p also
1263 checks this; here, we do a more specific test for this case. */
1265 || (GET_CODE (inner_dest) == REG
1266 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1267 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1268 GET_MODE (inner_dest))
1269 || (SMALL_REGISTER_CLASSES && GET_CODE (src) != CALL
1270 && ! REG_USERVAR_P (inner_dest)
1271 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest))
1272 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest))
1274 && sets_function_arg_p (prev_nonnote_insn (i3)))))))
1275 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1278 /* If DEST is used in I3, it is being killed in this insn,
1279 so record that for later.
1280 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1281 STACK_POINTER_REGNUM, since these are always considered to be
1282 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1283 if (pi3dest_killed && GET_CODE (dest) == REG
1284 && reg_referenced_p (dest, PATTERN (i3))
1285 && REGNO (dest) != FRAME_POINTER_REGNUM
1286 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1287 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1289 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1290 && (REGNO (dest) != ARG_POINTER_REGNUM
1291 || ! fixed_regs [REGNO (dest)])
1293 && REGNO (dest) != STACK_POINTER_REGNUM)
1295 if (*pi3dest_killed)
1298 *pi3dest_killed = dest;
1302 else if (GET_CODE (x) == PARALLEL)
1306 for (i = 0; i < XVECLEN (x, 0); i++)
1307 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1308 i1_not_in_src, pi3dest_killed))
1315 /* Try to combine the insns I1 and I2 into I3.
1316 Here I1 and I2 appear earlier than I3.
1317 I1 can be zero; then we combine just I2 into I3.
1319 It we are combining three insns and the resulting insn is not recognized,
1320 try splitting it into two insns. If that happens, I2 and I3 are retained
1321 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1324 Return 0 if the combination does not work. Then nothing is changed.
1325 If we did the combination, return the insn at which combine should
1329 try_combine (i3, i2, i1)
1330 register rtx i3, i2, i1;
1332 /* New patterns for I3 and I3, respectively. */
1333 rtx newpat, newi2pat = 0;
1334 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1335 int added_sets_1, added_sets_2;
1336 /* Total number of SETs to put into I3. */
1338 /* Nonzero is I2's body now appears in I3. */
1340 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1341 int insn_code_number, i2_code_number, other_code_number;
1342 /* Contains I3 if the destination of I3 is used in its source, which means
1343 that the old life of I3 is being killed. If that usage is placed into
1344 I2 and not in I3, a REG_DEAD note must be made. */
1345 rtx i3dest_killed = 0;
1346 /* SET_DEST and SET_SRC of I2 and I1. */
1347 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1348 /* PATTERN (I2), or a copy of it in certain cases. */
1350 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1351 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1352 int i1_feeds_i3 = 0;
1353 /* Notes that must be added to REG_NOTES in I3 and I2. */
1354 rtx new_i3_notes, new_i2_notes;
1355 /* Notes that we substituted I3 into I2 instead of the normal case. */
1356 int i3_subst_into_i2 = 0;
1357 /* Notes that I1, I2 or I3 is a MULT operation. */
1365 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1366 This can occur when flow deletes an insn that it has merged into an
1367 auto-increment address. We also can't do anything if I3 has a
1368 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1371 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
1372 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1373 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1375 /* ??? This gives worse code, and appears to be unnecessary, since no
1376 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1377 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1384 undobuf.undos = undobuf.previous_undos = 0;
1385 undobuf.other_insn = 0;
1387 /* Save the current high-water-mark so we can free storage if we didn't
1388 accept this combination. */
1389 undobuf.storage = (char *) oballoc (0);
1391 /* Reset the hard register usage information. */
1392 CLEAR_HARD_REG_SET (newpat_used_regs);
1394 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1395 code below, set I1 to be the earlier of the two insns. */
1396 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1397 temp = i1, i1 = i2, i2 = temp;
1399 added_links_insn = 0;
1401 /* First check for one important special-case that the code below will
1402 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1403 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1404 we may be able to replace that destination with the destination of I3.
1405 This occurs in the common code where we compute both a quotient and
1406 remainder into a structure, in which case we want to do the computation
1407 directly into the structure to avoid register-register copies.
1409 We make very conservative checks below and only try to handle the
1410 most common cases of this. For example, we only handle the case
1411 where I2 and I3 are adjacent to avoid making difficult register
1414 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1415 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1416 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1417 && (! SMALL_REGISTER_CLASSES
1418 || (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1419 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1420 || REG_USERVAR_P (SET_DEST (PATTERN (i3)))))
1421 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1422 && GET_CODE (PATTERN (i2)) == PARALLEL
1423 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1424 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1425 below would need to check what is inside (and reg_overlap_mentioned_p
1426 doesn't support those codes anyway). Don't allow those destinations;
1427 the resulting insn isn't likely to be recognized anyway. */
1428 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1429 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1430 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1431 SET_DEST (PATTERN (i3)))
1432 && next_real_insn (i2) == i3)
1434 rtx p2 = PATTERN (i2);
1436 /* Make sure that the destination of I3,
1437 which we are going to substitute into one output of I2,
1438 is not used within another output of I2. We must avoid making this:
1439 (parallel [(set (mem (reg 69)) ...)
1440 (set (reg 69) ...)])
1441 which is not well-defined as to order of actions.
1442 (Besides, reload can't handle output reloads for this.)
1444 The problem can also happen if the dest of I3 is a memory ref,
1445 if another dest in I2 is an indirect memory ref. */
1446 for (i = 0; i < XVECLEN (p2, 0); i++)
1447 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1448 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1449 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1450 SET_DEST (XVECEXP (p2, 0, i))))
1453 if (i == XVECLEN (p2, 0))
1454 for (i = 0; i < XVECLEN (p2, 0); i++)
1455 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1460 subst_low_cuid = INSN_CUID (i2);
1462 added_sets_2 = added_sets_1 = 0;
1463 i2dest = SET_SRC (PATTERN (i3));
1465 /* Replace the dest in I2 with our dest and make the resulting
1466 insn the new pattern for I3. Then skip to where we
1467 validate the pattern. Everything was set up above. */
1468 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1469 SET_DEST (PATTERN (i3)));
1472 i3_subst_into_i2 = 1;
1473 goto validate_replacement;
1478 /* If we have no I1 and I2 looks like:
1479 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1481 make up a dummy I1 that is
1484 (set (reg:CC X) (compare:CC Y (const_int 0)))
1486 (We can ignore any trailing CLOBBERs.)
1488 This undoes a previous combination and allows us to match a branch-and-
1491 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1492 && XVECLEN (PATTERN (i2), 0) >= 2
1493 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1494 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1496 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1497 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1498 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1499 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1500 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1501 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1503 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1504 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1509 /* We make I1 with the same INSN_UID as I2. This gives it
1510 the same INSN_CUID for value tracking. Our fake I1 will
1511 never appear in the insn stream so giving it the same INSN_UID
1512 as I2 will not cause a problem. */
1514 subst_prev_insn = i1
1515 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1516 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1519 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1520 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1521 SET_DEST (PATTERN (i1)));
1526 /* Verify that I2 and I1 are valid for combining. */
1527 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1528 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1534 /* Record whether I2DEST is used in I2SRC and similarly for the other
1535 cases. Knowing this will help in register status updating below. */
1536 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1537 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1538 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1540 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1542 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1544 /* Ensure that I3's pattern can be the destination of combines. */
1545 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1546 i1 && i2dest_in_i1src && i1_feeds_i3,
1553 /* See if any of the insns is a MULT operation. Unless one is, we will
1554 reject a combination that is, since it must be slower. Be conservative
1556 if (GET_CODE (i2src) == MULT
1557 || (i1 != 0 && GET_CODE (i1src) == MULT)
1558 || (GET_CODE (PATTERN (i3)) == SET
1559 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1562 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1563 We used to do this EXCEPT in one case: I3 has a post-inc in an
1564 output operand. However, that exception can give rise to insns like
1566 which is a famous insn on the PDP-11 where the value of r3 used as the
1567 source was model-dependent. Avoid this sort of thing. */
1570 if (!(GET_CODE (PATTERN (i3)) == SET
1571 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1572 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1573 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1574 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1575 /* It's not the exception. */
1578 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1579 if (REG_NOTE_KIND (link) == REG_INC
1580 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1582 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1589 /* See if the SETs in I1 or I2 need to be kept around in the merged
1590 instruction: whenever the value set there is still needed past I3.
1591 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1593 For the SET in I1, we have two cases: If I1 and I2 independently
1594 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1595 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1596 in I1 needs to be kept around unless I1DEST dies or is set in either
1597 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1598 I1DEST. If so, we know I1 feeds into I2. */
1600 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1603 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1604 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1606 /* If the set in I2 needs to be kept around, we must make a copy of
1607 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1608 PATTERN (I2), we are only substituting for the original I1DEST, not into
1609 an already-substituted copy. This also prevents making self-referential
1610 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1613 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1614 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1618 i2pat = copy_rtx (i2pat);
1622 /* Substitute in the latest insn for the regs set by the earlier ones. */
1624 maxreg = max_reg_num ();
1628 /* It is possible that the source of I2 or I1 may be performing an
1629 unneeded operation, such as a ZERO_EXTEND of something that is known
1630 to have the high part zero. Handle that case by letting subst look at
1631 the innermost one of them.
1633 Another way to do this would be to have a function that tries to
1634 simplify a single insn instead of merging two or more insns. We don't
1635 do this because of the potential of infinite loops and because
1636 of the potential extra memory required. However, doing it the way
1637 we are is a bit of a kludge and doesn't catch all cases.
1639 But only do this if -fexpensive-optimizations since it slows things down
1640 and doesn't usually win. */
1642 if (flag_expensive_optimizations)
1644 /* Pass pc_rtx so no substitutions are done, just simplifications.
1645 The cases that we are interested in here do not involve the few
1646 cases were is_replaced is checked. */
1649 subst_low_cuid = INSN_CUID (i1);
1650 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1654 subst_low_cuid = INSN_CUID (i2);
1655 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1658 undobuf.previous_undos = undobuf.undos;
1662 /* Many machines that don't use CC0 have insns that can both perform an
1663 arithmetic operation and set the condition code. These operations will
1664 be represented as a PARALLEL with the first element of the vector
1665 being a COMPARE of an arithmetic operation with the constant zero.
1666 The second element of the vector will set some pseudo to the result
1667 of the same arithmetic operation. If we simplify the COMPARE, we won't
1668 match such a pattern and so will generate an extra insn. Here we test
1669 for this case, where both the comparison and the operation result are
1670 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1671 I2SRC. Later we will make the PARALLEL that contains I2. */
1673 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1674 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1675 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1676 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1678 #ifdef EXTRA_CC_MODES
1680 enum machine_mode compare_mode;
1683 newpat = PATTERN (i3);
1684 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1688 #ifdef EXTRA_CC_MODES
1689 /* See if a COMPARE with the operand we substituted in should be done
1690 with the mode that is currently being used. If not, do the same
1691 processing we do in `subst' for a SET; namely, if the destination
1692 is used only once, try to replace it with a register of the proper
1693 mode and also replace the COMPARE. */
1694 if (undobuf.other_insn == 0
1695 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1696 &undobuf.other_insn))
1697 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
1699 != GET_MODE (SET_DEST (newpat))))
1701 int regno = REGNO (SET_DEST (newpat));
1702 rtx new_dest = gen_rtx_REG (compare_mode, regno);
1704 if (regno < FIRST_PSEUDO_REGISTER
1705 || (REG_N_SETS (regno) == 1 && ! added_sets_2
1706 && ! REG_USERVAR_P (SET_DEST (newpat))))
1708 if (regno >= FIRST_PSEUDO_REGISTER)
1709 SUBST (regno_reg_rtx[regno], new_dest);
1711 SUBST (SET_DEST (newpat), new_dest);
1712 SUBST (XEXP (*cc_use, 0), new_dest);
1713 SUBST (SET_SRC (newpat),
1714 gen_rtx_combine (COMPARE, compare_mode,
1715 i2src, const0_rtx));
1718 undobuf.other_insn = 0;
1725 n_occurrences = 0; /* `subst' counts here */
1727 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1728 need to make a unique copy of I2SRC each time we substitute it
1729 to avoid self-referential rtl. */
1731 subst_low_cuid = INSN_CUID (i2);
1732 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1733 ! i1_feeds_i3 && i1dest_in_i1src);
1734 undobuf.previous_undos = undobuf.undos;
1736 /* Record whether i2's body now appears within i3's body. */
1737 i2_is_used = n_occurrences;
1740 /* If we already got a failure, don't try to do more. Otherwise,
1741 try to substitute in I1 if we have it. */
1743 if (i1 && GET_CODE (newpat) != CLOBBER)
1745 /* Before we can do this substitution, we must redo the test done
1746 above (see detailed comments there) that ensures that I1DEST
1747 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1749 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
1757 subst_low_cuid = INSN_CUID (i1);
1758 newpat = subst (newpat, i1dest, i1src, 0, 0);
1759 undobuf.previous_undos = undobuf.undos;
1762 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1763 to count all the ways that I2SRC and I1SRC can be used. */
1764 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
1765 && i2_is_used + added_sets_2 > 1)
1766 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
1767 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1769 /* Fail if we tried to make a new register (we used to abort, but there's
1770 really no reason to). */
1771 || max_reg_num () != maxreg
1772 /* Fail if we couldn't do something and have a CLOBBER. */
1773 || GET_CODE (newpat) == CLOBBER
1774 /* Fail if this new pattern is a MULT and we didn't have one before
1775 at the outer level. */
1776 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
1783 /* If the actions of the earlier insns must be kept
1784 in addition to substituting them into the latest one,
1785 we must make a new PARALLEL for the latest insn
1786 to hold additional the SETs. */
1788 if (added_sets_1 || added_sets_2)
1792 if (GET_CODE (newpat) == PARALLEL)
1794 rtvec old = XVEC (newpat, 0);
1795 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1796 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1797 bcopy ((char *) &old->elem[0], (char *) XVEC (newpat, 0)->elem,
1798 sizeof (old->elem[0]) * old->num_elem);
1803 total_sets = 1 + added_sets_1 + added_sets_2;
1804 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
1805 XVECEXP (newpat, 0, 0) = old;
1809 XVECEXP (newpat, 0, --total_sets)
1810 = (GET_CODE (PATTERN (i1)) == PARALLEL
1811 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
1815 /* If there is no I1, use I2's body as is. We used to also not do
1816 the subst call below if I2 was substituted into I3,
1817 but that could lose a simplification. */
1819 XVECEXP (newpat, 0, --total_sets) = i2pat;
1821 /* See comment where i2pat is assigned. */
1822 XVECEXP (newpat, 0, --total_sets)
1823 = subst (i2pat, i1dest, i1src, 0, 0);
1827 /* We come here when we are replacing a destination in I2 with the
1828 destination of I3. */
1829 validate_replacement:
1831 /* Note which hard regs this insn has as inputs. */
1832 mark_used_regs_combine (newpat);
1834 /* Is the result of combination a valid instruction? */
1835 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1837 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1838 the second SET's destination is a register that is unused. In that case,
1839 we just need the first SET. This can occur when simplifying a divmod
1840 insn. We *must* test for this case here because the code below that
1841 splits two independent SETs doesn't handle this case correctly when it
1842 updates the register status. Also check the case where the first
1843 SET's destination is unused. That would not cause incorrect code, but
1844 does cause an unneeded insn to remain. */
1846 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1847 && XVECLEN (newpat, 0) == 2
1848 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1849 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1850 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1851 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1852 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1853 && asm_noperands (newpat) < 0)
1855 newpat = XVECEXP (newpat, 0, 0);
1856 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1859 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1860 && XVECLEN (newpat, 0) == 2
1861 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1862 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1863 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1864 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1865 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1866 && asm_noperands (newpat) < 0)
1868 newpat = XVECEXP (newpat, 0, 1);
1869 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1872 /* If we were combining three insns and the result is a simple SET
1873 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1874 insns. There are two ways to do this. It can be split using a
1875 machine-specific method (like when you have an addition of a large
1876 constant) or by combine in the function find_split_point. */
1878 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1879 && asm_noperands (newpat) < 0)
1881 rtx m_split, *split;
1882 rtx ni2dest = i2dest;
1884 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1885 use I2DEST as a scratch register will help. In the latter case,
1886 convert I2DEST to the mode of the source of NEWPAT if we can. */
1888 m_split = split_insns (newpat, i3);
1890 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
1891 inputs of NEWPAT. */
1893 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
1894 possible to try that as a scratch reg. This would require adding
1895 more code to make it work though. */
1897 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
1899 /* If I2DEST is a hard register or the only use of a pseudo,
1900 we can change its mode. */
1901 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
1902 && GET_MODE (SET_DEST (newpat)) != VOIDmode
1903 && GET_CODE (i2dest) == REG
1904 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1905 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1906 && ! REG_USERVAR_P (i2dest))))
1907 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
1910 m_split = split_insns
1911 (gen_rtx_PARALLEL (VOIDmode,
1912 gen_rtvec (2, newpat,
1913 gen_rtx_CLOBBER (VOIDmode,
1918 if (m_split && GET_CODE (m_split) == SEQUENCE
1919 && XVECLEN (m_split, 0) == 2
1920 && (next_real_insn (i2) == i3
1921 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split, 0, 0)),
1925 rtx newi3pat = PATTERN (XVECEXP (m_split, 0, 1));
1926 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1928 i3set = single_set (XVECEXP (m_split, 0, 1));
1929 i2set = single_set (XVECEXP (m_split, 0, 0));
1931 /* In case we changed the mode of I2DEST, replace it in the
1932 pseudo-register table here. We can't do it above in case this
1933 code doesn't get executed and we do a split the other way. */
1935 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1936 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
1938 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1940 /* If I2 or I3 has multiple SETs, we won't know how to track
1941 register status, so don't use these insns. If I2's destination
1942 is used between I2 and I3, we also can't use these insns. */
1944 if (i2_code_number >= 0 && i2set && i3set
1945 && (next_real_insn (i2) == i3
1946 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
1947 insn_code_number = recog_for_combine (&newi3pat, i3,
1949 if (insn_code_number >= 0)
1952 /* It is possible that both insns now set the destination of I3.
1953 If so, we must show an extra use of it. */
1955 if (insn_code_number >= 0)
1957 rtx new_i3_dest = SET_DEST (i3set);
1958 rtx new_i2_dest = SET_DEST (i2set);
1960 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
1961 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
1962 || GET_CODE (new_i3_dest) == SUBREG)
1963 new_i3_dest = XEXP (new_i3_dest, 0);
1965 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
1966 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
1967 || GET_CODE (new_i2_dest) == SUBREG)
1968 new_i2_dest = XEXP (new_i2_dest, 0);
1970 if (GET_CODE (new_i3_dest) == REG
1971 && GET_CODE (new_i2_dest) == REG
1972 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
1973 REG_N_SETS (REGNO (new_i2_dest))++;
1977 /* If we can split it and use I2DEST, go ahead and see if that
1978 helps things be recognized. Verify that none of the registers
1979 are set between I2 and I3. */
1980 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
1982 && GET_CODE (i2dest) == REG
1984 /* We need I2DEST in the proper mode. If it is a hard register
1985 or the only use of a pseudo, we can change its mode. */
1986 && (GET_MODE (*split) == GET_MODE (i2dest)
1987 || GET_MODE (*split) == VOIDmode
1988 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1989 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
1990 && ! REG_USERVAR_P (i2dest)))
1991 && (next_real_insn (i2) == i3
1992 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1993 /* We can't overwrite I2DEST if its value is still used by
1995 && ! reg_referenced_p (i2dest, newpat))
1997 rtx newdest = i2dest;
1998 enum rtx_code split_code = GET_CODE (*split);
1999 enum machine_mode split_mode = GET_MODE (*split);
2001 /* Get NEWDEST as a register in the proper mode. We have already
2002 validated that we can do this. */
2003 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2005 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2007 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2008 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2011 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2012 an ASHIFT. This can occur if it was inside a PLUS and hence
2013 appeared to be a memory address. This is a kludge. */
2014 if (split_code == MULT
2015 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2016 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2018 SUBST (*split, gen_rtx_combine (ASHIFT, split_mode,
2019 XEXP (*split, 0), GEN_INT (i)));
2020 /* Update split_code because we may not have a multiply
2022 split_code = GET_CODE (*split);
2025 #ifdef INSN_SCHEDULING
2026 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2027 be written as a ZERO_EXTEND. */
2028 if (split_code == SUBREG && GET_CODE (SUBREG_REG (*split)) == MEM)
2029 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, split_mode,
2033 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
2034 SUBST (*split, newdest);
2035 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2037 /* If the split point was a MULT and we didn't have one before,
2038 don't use one now. */
2039 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2040 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2044 /* Check for a case where we loaded from memory in a narrow mode and
2045 then sign extended it, but we need both registers. In that case,
2046 we have a PARALLEL with both loads from the same memory location.
2047 We can split this into a load from memory followed by a register-register
2048 copy. This saves at least one insn, more if register allocation can
2051 We cannot do this if the destination of the second assignment is
2052 a register that we have already assumed is zero-extended. Similarly
2053 for a SUBREG of such a register. */
2055 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2056 && GET_CODE (newpat) == PARALLEL
2057 && XVECLEN (newpat, 0) == 2
2058 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2059 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2060 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2061 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2062 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2063 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2065 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2066 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2067 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2068 (GET_CODE (temp) == REG
2069 && reg_nonzero_bits[REGNO (temp)] != 0
2070 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2071 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2072 && (reg_nonzero_bits[REGNO (temp)]
2073 != GET_MODE_MASK (word_mode))))
2074 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2075 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2076 (GET_CODE (temp) == REG
2077 && reg_nonzero_bits[REGNO (temp)] != 0
2078 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2079 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2080 && (reg_nonzero_bits[REGNO (temp)]
2081 != GET_MODE_MASK (word_mode)))))
2082 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2083 SET_SRC (XVECEXP (newpat, 0, 1)))
2084 && ! find_reg_note (i3, REG_UNUSED,
2085 SET_DEST (XVECEXP (newpat, 0, 0))))
2089 newi2pat = XVECEXP (newpat, 0, 0);
2090 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2091 newpat = XVECEXP (newpat, 0, 1);
2092 SUBST (SET_SRC (newpat),
2093 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)), ni2dest));
2094 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2096 if (i2_code_number >= 0)
2097 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2099 if (insn_code_number >= 0)
2104 /* If we will be able to accept this, we have made a change to the
2105 destination of I3. This can invalidate a LOG_LINKS pointing
2106 to I3. No other part of combine.c makes such a transformation.
2108 The new I3 will have a destination that was previously the
2109 destination of I1 or I2 and which was used in i2 or I3. Call
2110 distribute_links to make a LOG_LINK from the next use of
2111 that destination. */
2113 PATTERN (i3) = newpat;
2114 distribute_links (gen_rtx_INSN_LIST (VOIDmode, i3, NULL_RTX));
2116 /* I3 now uses what used to be its destination and which is
2117 now I2's destination. That means we need a LOG_LINK from
2118 I3 to I2. But we used to have one, so we still will.
2120 However, some later insn might be using I2's dest and have
2121 a LOG_LINK pointing at I3. We must remove this link.
2122 The simplest way to remove the link is to point it at I1,
2123 which we know will be a NOTE. */
2125 for (insn = NEXT_INSN (i3);
2126 insn && (this_basic_block == n_basic_blocks - 1
2127 || insn != BLOCK_HEAD (this_basic_block + 1));
2128 insn = NEXT_INSN (insn))
2130 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
2131 && reg_referenced_p (ni2dest, PATTERN (insn)))
2133 for (link = LOG_LINKS (insn); link;
2134 link = XEXP (link, 1))
2135 if (XEXP (link, 0) == i3)
2136 XEXP (link, 0) = i1;
2144 /* Similarly, check for a case where we have a PARALLEL of two independent
2145 SETs but we started with three insns. In this case, we can do the sets
2146 as two separate insns. This case occurs when some SET allows two
2147 other insns to combine, but the destination of that SET is still live. */
2149 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2150 && GET_CODE (newpat) == PARALLEL
2151 && XVECLEN (newpat, 0) == 2
2152 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2153 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2154 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2155 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2156 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2157 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2158 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2160 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2161 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2162 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2163 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2164 XVECEXP (newpat, 0, 0))
2165 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2166 XVECEXP (newpat, 0, 1)))
2168 /* Normally, it doesn't matter which of the two is done first,
2169 but it does if one references cc0. In that case, it has to
2172 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2174 newi2pat = XVECEXP (newpat, 0, 0);
2175 newpat = XVECEXP (newpat, 0, 1);
2180 newi2pat = XVECEXP (newpat, 0, 1);
2181 newpat = XVECEXP (newpat, 0, 0);
2184 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2186 if (i2_code_number >= 0)
2187 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2190 /* If it still isn't recognized, fail and change things back the way they
2192 if ((insn_code_number < 0
2193 /* Is the result a reasonable ASM_OPERANDS? */
2194 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2200 /* If we had to change another insn, make sure it is valid also. */
2201 if (undobuf.other_insn)
2203 rtx other_pat = PATTERN (undobuf.other_insn);
2204 rtx new_other_notes;
2207 CLEAR_HARD_REG_SET (newpat_used_regs);
2209 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2212 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2218 PATTERN (undobuf.other_insn) = other_pat;
2220 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2221 are still valid. Then add any non-duplicate notes added by
2222 recog_for_combine. */
2223 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2225 next = XEXP (note, 1);
2227 if (REG_NOTE_KIND (note) == REG_UNUSED
2228 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2230 if (GET_CODE (XEXP (note, 0)) == REG)
2231 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2233 remove_note (undobuf.other_insn, note);
2237 for (note = new_other_notes; note; note = XEXP (note, 1))
2238 if (GET_CODE (XEXP (note, 0)) == REG)
2239 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2241 distribute_notes (new_other_notes, undobuf.other_insn,
2242 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2245 /* We now know that we can do this combination. Merge the insns and
2246 update the status of registers and LOG_LINKS. */
2249 rtx i3notes, i2notes, i1notes = 0;
2250 rtx i3links, i2links, i1links = 0;
2253 /* Compute which registers we expect to eliminate. newi2pat may be setting
2254 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2255 same as i3dest, in which case newi2pat may be setting i1dest. */
2256 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2257 || i2dest_in_i2src || i2dest_in_i1src
2259 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2260 || (newi2pat && reg_set_p (i1dest, newi2pat))
2263 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2265 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2266 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2268 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2270 /* Ensure that we do not have something that should not be shared but
2271 occurs multiple times in the new insns. Check this by first
2272 resetting all the `used' flags and then copying anything is shared. */
2274 reset_used_flags (i3notes);
2275 reset_used_flags (i2notes);
2276 reset_used_flags (i1notes);
2277 reset_used_flags (newpat);
2278 reset_used_flags (newi2pat);
2279 if (undobuf.other_insn)
2280 reset_used_flags (PATTERN (undobuf.other_insn));
2282 i3notes = copy_rtx_if_shared (i3notes);
2283 i2notes = copy_rtx_if_shared (i2notes);
2284 i1notes = copy_rtx_if_shared (i1notes);
2285 newpat = copy_rtx_if_shared (newpat);
2286 newi2pat = copy_rtx_if_shared (newi2pat);
2287 if (undobuf.other_insn)
2288 reset_used_flags (PATTERN (undobuf.other_insn));
2290 INSN_CODE (i3) = insn_code_number;
2291 PATTERN (i3) = newpat;
2292 if (undobuf.other_insn)
2293 INSN_CODE (undobuf.other_insn) = other_code_number;
2295 /* We had one special case above where I2 had more than one set and
2296 we replaced a destination of one of those sets with the destination
2297 of I3. In that case, we have to update LOG_LINKS of insns later
2298 in this basic block. Note that this (expensive) case is rare.
2300 Also, in this case, we must pretend that all REG_NOTEs for I2
2301 actually came from I3, so that REG_UNUSED notes from I2 will be
2302 properly handled. */
2304 if (i3_subst_into_i2)
2306 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2307 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
2308 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2309 && ! find_reg_note (i2, REG_UNUSED,
2310 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2311 for (temp = NEXT_INSN (i2);
2312 temp && (this_basic_block == n_basic_blocks - 1
2313 || BLOCK_HEAD (this_basic_block) != temp);
2314 temp = NEXT_INSN (temp))
2315 if (temp != i3 && GET_RTX_CLASS (GET_CODE (temp)) == 'i')
2316 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2317 if (XEXP (link, 0) == i2)
2318 XEXP (link, 0) = i3;
2323 while (XEXP (link, 1))
2324 link = XEXP (link, 1);
2325 XEXP (link, 1) = i2notes;
2339 INSN_CODE (i2) = i2_code_number;
2340 PATTERN (i2) = newi2pat;
2344 PUT_CODE (i2, NOTE);
2345 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
2346 NOTE_SOURCE_FILE (i2) = 0;
2353 PUT_CODE (i1, NOTE);
2354 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
2355 NOTE_SOURCE_FILE (i1) = 0;
2358 /* Get death notes for everything that is now used in either I3 or
2359 I2 and used to die in a previous insn. If we built two new
2360 patterns, move from I1 to I2 then I2 to I3 so that we get the
2361 proper movement on registers that I2 modifies. */
2365 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2366 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2369 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2372 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2374 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2377 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2380 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2383 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2386 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2387 know these are REG_UNUSED and want them to go to the desired insn,
2388 so we always pass it as i3. We have not counted the notes in
2389 reg_n_deaths yet, so we need to do so now. */
2391 if (newi2pat && new_i2_notes)
2393 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2394 if (GET_CODE (XEXP (temp, 0)) == REG)
2395 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2397 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2402 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2403 if (GET_CODE (XEXP (temp, 0)) == REG)
2404 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2406 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
2409 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2410 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2411 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2412 in that case, it might delete I2. Similarly for I2 and I1.
2413 Show an additional death due to the REG_DEAD note we make here. If
2414 we discard it in distribute_notes, we will decrement it again. */
2418 if (GET_CODE (i3dest_killed) == REG)
2419 REG_N_DEATHS (REGNO (i3dest_killed))++;
2421 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2422 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2424 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
2426 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2428 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2432 if (i2dest_in_i2src)
2434 if (GET_CODE (i2dest) == REG)
2435 REG_N_DEATHS (REGNO (i2dest))++;
2437 if (newi2pat && reg_set_p (i2dest, newi2pat))
2438 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2439 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2441 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2442 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2443 NULL_RTX, NULL_RTX);
2446 if (i1dest_in_i1src)
2448 if (GET_CODE (i1dest) == REG)
2449 REG_N_DEATHS (REGNO (i1dest))++;
2451 if (newi2pat && reg_set_p (i1dest, newi2pat))
2452 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2453 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
2455 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2456 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2457 NULL_RTX, NULL_RTX);
2460 distribute_links (i3links);
2461 distribute_links (i2links);
2462 distribute_links (i1links);
2464 if (GET_CODE (i2dest) == REG)
2467 rtx i2_insn = 0, i2_val = 0, set;
2469 /* The insn that used to set this register doesn't exist, and
2470 this life of the register may not exist either. See if one of
2471 I3's links points to an insn that sets I2DEST. If it does,
2472 that is now the last known value for I2DEST. If we don't update
2473 this and I2 set the register to a value that depended on its old
2474 contents, we will get confused. If this insn is used, thing
2475 will be set correctly in combine_instructions. */
2477 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2478 if ((set = single_set (XEXP (link, 0))) != 0
2479 && rtx_equal_p (i2dest, SET_DEST (set)))
2480 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2482 record_value_for_reg (i2dest, i2_insn, i2_val);
2484 /* If the reg formerly set in I2 died only once and that was in I3,
2485 zero its use count so it won't make `reload' do any work. */
2487 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2488 && ! i2dest_in_i2src)
2490 regno = REGNO (i2dest);
2491 REG_N_SETS (regno)--;
2492 if (REG_N_SETS (regno) == 0
2493 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2495 REG_N_REFS (regno) = 0;
2499 if (i1 && GET_CODE (i1dest) == REG)
2502 rtx i1_insn = 0, i1_val = 0, set;
2504 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2505 if ((set = single_set (XEXP (link, 0))) != 0
2506 && rtx_equal_p (i1dest, SET_DEST (set)))
2507 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2509 record_value_for_reg (i1dest, i1_insn, i1_val);
2511 regno = REGNO (i1dest);
2512 if (! added_sets_1 && ! i1dest_in_i1src)
2514 REG_N_SETS (regno)--;
2515 if (REG_N_SETS (regno) == 0
2516 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start,
2518 REG_N_REFS (regno) = 0;
2522 /* Update reg_nonzero_bits et al for any changes that may have been made
2525 note_stores (newpat, set_nonzero_bits_and_sign_copies);
2527 note_stores (newi2pat, set_nonzero_bits_and_sign_copies);
2529 /* If I3 is now an unconditional jump, ensure that it has a
2530 BARRIER following it since it may have initially been a
2531 conditional jump. It may also be the last nonnote insn. */
2533 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
2534 && ((temp = next_nonnote_insn (i3)) == NULL_RTX
2535 || GET_CODE (temp) != BARRIER))
2536 emit_barrier_after (i3);
2539 combine_successes++;
2541 /* Clear this here, so that subsequent get_last_value calls are not
2543 subst_prev_insn = NULL_RTX;
2545 if (added_links_insn
2546 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2547 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2548 return added_links_insn;
2550 return newi2pat ? i2 : i3;
2553 /* Undo all the modifications recorded in undobuf. */
2558 struct undo *undo, *next;
2560 for (undo = undobuf.undos; undo; undo = next)
2564 *undo->where.i = undo->old_contents.i;
2566 *undo->where.r = undo->old_contents.r;
2568 undo->next = undobuf.frees;
2569 undobuf.frees = undo;
2572 obfree (undobuf.storage);
2573 undobuf.undos = undobuf.previous_undos = 0;
2575 /* Clear this here, so that subsequent get_last_value calls are not
2577 subst_prev_insn = NULL_RTX;
2580 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2581 where we have an arithmetic expression and return that point. LOC will
2584 try_combine will call this function to see if an insn can be split into
2588 find_split_point (loc, insn)
2593 enum rtx_code code = GET_CODE (x);
2595 int len = 0, pos, unsignedp;
2598 /* First special-case some codes. */
2602 #ifdef INSN_SCHEDULING
2603 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2605 if (GET_CODE (SUBREG_REG (x)) == MEM)
2608 return find_split_point (&SUBREG_REG (x), insn);
2612 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2613 using LO_SUM and HIGH. */
2614 if (GET_CODE (XEXP (x, 0)) == CONST
2615 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
2618 gen_rtx_combine (LO_SUM, Pmode,
2619 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
2621 return &XEXP (XEXP (x, 0), 0);
2625 /* If we have a PLUS whose second operand is a constant and the
2626 address is not valid, perhaps will can split it up using
2627 the machine-specific way to split large constants. We use
2628 the first pseudo-reg (one of the virtual regs) as a placeholder;
2629 it will not remain in the result. */
2630 if (GET_CODE (XEXP (x, 0)) == PLUS
2631 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2632 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
2634 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
2635 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
2638 /* This should have produced two insns, each of which sets our
2639 placeholder. If the source of the second is a valid address,
2640 we can make put both sources together and make a split point
2643 if (seq && XVECLEN (seq, 0) == 2
2644 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
2645 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
2646 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
2647 && ! reg_mentioned_p (reg,
2648 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
2649 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
2650 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
2651 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
2652 && memory_address_p (GET_MODE (x),
2653 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
2655 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
2656 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
2658 /* Replace the placeholder in SRC2 with SRC1. If we can
2659 find where in SRC2 it was placed, that can become our
2660 split point and we can replace this address with SRC2.
2661 Just try two obvious places. */
2663 src2 = replace_rtx (src2, reg, src1);
2665 if (XEXP (src2, 0) == src1)
2666 split = &XEXP (src2, 0);
2667 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
2668 && XEXP (XEXP (src2, 0), 0) == src1)
2669 split = &XEXP (XEXP (src2, 0), 0);
2673 SUBST (XEXP (x, 0), src2);
2678 /* If that didn't work, perhaps the first operand is complex and
2679 needs to be computed separately, so make a split point there.
2680 This will occur on machines that just support REG + CONST
2681 and have a constant moved through some previous computation. */
2683 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) != 'o'
2684 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
2685 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x, 0), 0))))
2687 return &XEXP (XEXP (x, 0), 0);
2693 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2694 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2695 we need to put the operand into a register. So split at that
2698 if (SET_DEST (x) == cc0_rtx
2699 && GET_CODE (SET_SRC (x)) != COMPARE
2700 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2701 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2702 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2703 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2704 return &SET_SRC (x);
2707 /* See if we can split SET_SRC as it stands. */
2708 split = find_split_point (&SET_SRC (x), insn);
2709 if (split && split != &SET_SRC (x))
2712 /* See if we can split SET_DEST as it stands. */
2713 split = find_split_point (&SET_DEST (x), insn);
2714 if (split && split != &SET_DEST (x))
2717 /* See if this is a bitfield assignment with everything constant. If
2718 so, this is an IOR of an AND, so split it into that. */
2719 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2720 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2721 <= HOST_BITS_PER_WIDE_INT)
2722 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2723 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2724 && GET_CODE (SET_SRC (x)) == CONST_INT
2725 && ((INTVAL (XEXP (SET_DEST (x), 1))
2726 + INTVAL (XEXP (SET_DEST (x), 2)))
2727 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2728 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2730 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2731 int len = INTVAL (XEXP (SET_DEST (x), 1));
2732 int src = INTVAL (SET_SRC (x));
2733 rtx dest = XEXP (SET_DEST (x), 0);
2734 enum machine_mode mode = GET_MODE (dest);
2735 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
2737 if (BITS_BIG_ENDIAN)
2738 pos = GET_MODE_BITSIZE (mode) - len - pos;
2740 if ((unsigned HOST_WIDE_INT) src == mask)
2742 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
2745 gen_binary (IOR, mode,
2746 gen_binary (AND, mode, dest,
2747 GEN_INT (~ (mask << pos)
2748 & GET_MODE_MASK (mode))),
2749 GEN_INT (src << pos)));
2751 SUBST (SET_DEST (x), dest);
2753 split = find_split_point (&SET_SRC (x), insn);
2754 if (split && split != &SET_SRC (x))
2758 /* Otherwise, see if this is an operation that we can split into two.
2759 If so, try to split that. */
2760 code = GET_CODE (SET_SRC (x));
2765 /* If we are AND'ing with a large constant that is only a single
2766 bit and the result is only being used in a context where we
2767 need to know if it is zero or non-zero, replace it with a bit
2768 extraction. This will avoid the large constant, which might
2769 have taken more than one insn to make. If the constant were
2770 not a valid argument to the AND but took only one insn to make,
2771 this is no worse, but if it took more than one insn, it will
2774 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2775 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2776 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
2777 && GET_CODE (SET_DEST (x)) == REG
2778 && (split = find_single_use (SET_DEST (x), insn, NULL_PTR)) != 0
2779 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
2780 && XEXP (*split, 0) == SET_DEST (x)
2781 && XEXP (*split, 1) == const0_rtx)
2783 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
2784 XEXP (SET_SRC (x), 0),
2785 pos, NULL_RTX, 1, 1, 0, 0);
2786 if (extraction != 0)
2788 SUBST (SET_SRC (x), extraction);
2789 return find_split_point (loc, insn);
2795 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2796 is known to be on, this can be converted into a NEG of a shift. */
2797 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
2798 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
2799 && 1 <= (pos = exact_log2
2800 (nonzero_bits (XEXP (SET_SRC (x), 0),
2801 GET_MODE (XEXP (SET_SRC (x), 0))))))
2803 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
2806 gen_rtx_combine (NEG, mode,
2807 gen_rtx_combine (LSHIFTRT, mode,
2808 XEXP (SET_SRC (x), 0),
2811 split = find_split_point (&SET_SRC (x), insn);
2812 if (split && split != &SET_SRC (x))
2818 inner = XEXP (SET_SRC (x), 0);
2820 /* We can't optimize if either mode is a partial integer
2821 mode as we don't know how many bits are significant
2823 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
2824 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
2828 len = GET_MODE_BITSIZE (GET_MODE (inner));
2834 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2835 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2837 inner = XEXP (SET_SRC (x), 0);
2838 len = INTVAL (XEXP (SET_SRC (x), 1));
2839 pos = INTVAL (XEXP (SET_SRC (x), 2));
2841 if (BITS_BIG_ENDIAN)
2842 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2843 unsignedp = (code == ZERO_EXTRACT);
2851 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2853 enum machine_mode mode = GET_MODE (SET_SRC (x));
2855 /* For unsigned, we have a choice of a shift followed by an
2856 AND or two shifts. Use two shifts for field sizes where the
2857 constant might be too large. We assume here that we can
2858 always at least get 8-bit constants in an AND insn, which is
2859 true for every current RISC. */
2861 if (unsignedp && len <= 8)
2866 gen_rtx_combine (LSHIFTRT, mode,
2867 gen_lowpart_for_combine (mode, inner),
2869 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
2871 split = find_split_point (&SET_SRC (x), insn);
2872 if (split && split != &SET_SRC (x))
2879 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
2880 gen_rtx_combine (ASHIFT, mode,
2881 gen_lowpart_for_combine (mode, inner),
2882 GEN_INT (GET_MODE_BITSIZE (mode)
2884 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
2886 split = find_split_point (&SET_SRC (x), insn);
2887 if (split && split != &SET_SRC (x))
2892 /* See if this is a simple operation with a constant as the second
2893 operand. It might be that this constant is out of range and hence
2894 could be used as a split point. */
2895 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2896 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2897 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2898 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2899 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2900 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2901 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2903 return &XEXP (SET_SRC (x), 1);
2905 /* Finally, see if this is a simple operation with its first operand
2906 not in a register. The operation might require this operand in a
2907 register, so return it as a split point. We can always do this
2908 because if the first operand were another operation, we would have
2909 already found it as a split point. */
2910 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2911 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2912 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2913 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2914 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2915 return &XEXP (SET_SRC (x), 0);
2921 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2922 it is better to write this as (not (ior A B)) so we can split it.
2923 Similarly for IOR. */
2924 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2927 gen_rtx_combine (NOT, GET_MODE (x),
2928 gen_rtx_combine (code == IOR ? AND : IOR,
2930 XEXP (XEXP (x, 0), 0),
2931 XEXP (XEXP (x, 1), 0))));
2932 return find_split_point (loc, insn);
2935 /* Many RISC machines have a large set of logical insns. If the
2936 second operand is a NOT, put it first so we will try to split the
2937 other operand first. */
2938 if (GET_CODE (XEXP (x, 1)) == NOT)
2940 rtx tem = XEXP (x, 0);
2941 SUBST (XEXP (x, 0), XEXP (x, 1));
2942 SUBST (XEXP (x, 1), tem);
2950 /* Otherwise, select our actions depending on our rtx class. */
2951 switch (GET_RTX_CLASS (code))
2953 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2955 split = find_split_point (&XEXP (x, 2), insn);
2958 /* ... fall through ... */
2962 split = find_split_point (&XEXP (x, 1), insn);
2965 /* ... fall through ... */
2967 /* Some machines have (and (shift ...) ...) insns. If X is not
2968 an AND, but XEXP (X, 0) is, use it as our split point. */
2969 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2970 return &XEXP (x, 0);
2972 split = find_split_point (&XEXP (x, 0), insn);
2978 /* Otherwise, we don't have a split point. */
2982 /* Throughout X, replace FROM with TO, and return the result.
2983 The result is TO if X is FROM;
2984 otherwise the result is X, but its contents may have been modified.
2985 If they were modified, a record was made in undobuf so that
2986 undo_all will (among other things) return X to its original state.
2988 If the number of changes necessary is too much to record to undo,
2989 the excess changes are not made, so the result is invalid.
2990 The changes already made can still be undone.
2991 undobuf.num_undo is incremented for such changes, so by testing that
2992 the caller can tell whether the result is valid.
2994 `n_occurrences' is incremented each time FROM is replaced.
2996 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2998 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2999 by copying if `n_occurrences' is non-zero. */
3002 subst (x, from, to, in_dest, unique_copy)
3003 register rtx x, from, to;
3007 register enum rtx_code code = GET_CODE (x);
3008 enum machine_mode op0_mode = VOIDmode;
3010 register int len, i;
3013 /* Two expressions are equal if they are identical copies of a shared
3014 RTX or if they are both registers with the same register number
3017 #define COMBINE_RTX_EQUAL_P(X,Y) \
3019 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3020 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3022 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3025 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3028 /* If X and FROM are the same register but different modes, they will
3029 not have been seen as equal above. However, flow.c will make a
3030 LOG_LINKS entry for that case. If we do nothing, we will try to
3031 rerecognize our original insn and, when it succeeds, we will
3032 delete the feeding insn, which is incorrect.
3034 So force this insn not to match in this (rare) case. */
3035 if (! in_dest && code == REG && GET_CODE (from) == REG
3036 && REGNO (x) == REGNO (from))
3037 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3039 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3040 of which may contain things that can be combined. */
3041 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
3044 /* It is possible to have a subexpression appear twice in the insn.
3045 Suppose that FROM is a register that appears within TO.
3046 Then, after that subexpression has been scanned once by `subst',
3047 the second time it is scanned, TO may be found. If we were
3048 to scan TO here, we would find FROM within it and create a
3049 self-referent rtl structure which is completely wrong. */
3050 if (COMBINE_RTX_EQUAL_P (x, to))
3053 /* Parallel asm_operands need special attention because all of the
3054 inputs are shared across the arms. Furthermore, unsharing the
3055 rtl results in recognition failures. Failure to handle this case
3056 specially can result in circular rtl.
3058 Solve this by doing a normal pass across the first entry of the
3059 parallel, and only processing the SET_DESTs of the subsequent
3062 if (code == PARALLEL
3063 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3064 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3066 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3068 /* If this substitution failed, this whole thing fails. */
3069 if (GET_CODE (new) == CLOBBER
3070 && XEXP (new, 0) == const0_rtx)
3073 SUBST (XVECEXP (x, 0, 0), new);
3075 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3077 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3079 if (GET_CODE (dest) != REG
3080 && GET_CODE (dest) != CC0
3081 && GET_CODE (dest) != PC)
3083 new = subst (dest, from, to, 0, unique_copy);
3085 /* If this substitution failed, this whole thing fails. */
3086 if (GET_CODE (new) == CLOBBER
3087 && XEXP (new, 0) == const0_rtx)
3090 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3096 len = GET_RTX_LENGTH (code);
3097 fmt = GET_RTX_FORMAT (code);
3099 /* We don't need to process a SET_DEST that is a register, CC0,
3100 or PC, so set up to skip this common case. All other cases
3101 where we want to suppress replacing something inside a
3102 SET_SRC are handled via the IN_DEST operand. */
3104 && (GET_CODE (SET_DEST (x)) == REG
3105 || GET_CODE (SET_DEST (x)) == CC0
3106 || GET_CODE (SET_DEST (x)) == PC))
3109 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3112 op0_mode = GET_MODE (XEXP (x, 0));
3114 for (i = 0; i < len; i++)
3119 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3121 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3123 new = (unique_copy && n_occurrences
3124 ? copy_rtx (to) : to);
3129 new = subst (XVECEXP (x, i, j), from, to, 0,
3132 /* If this substitution failed, this whole thing
3134 if (GET_CODE (new) == CLOBBER
3135 && XEXP (new, 0) == const0_rtx)
3139 SUBST (XVECEXP (x, i, j), new);
3142 else if (fmt[i] == 'e')
3144 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3146 /* In general, don't install a subreg involving two
3147 modes not tieable. It can worsen register
3148 allocation, and can even make invalid reload
3149 insns, since the reg inside may need to be copied
3150 from in the outside mode, and that may be invalid
3151 if it is an fp reg copied in integer mode.
3153 We allow two exceptions to this: It is valid if
3154 it is inside another SUBREG and the mode of that
3155 SUBREG and the mode of the inside of TO is
3156 tieable and it is valid if X is a SET that copies
3159 if (GET_CODE (to) == SUBREG
3160 && ! MODES_TIEABLE_P (GET_MODE (to),
3161 GET_MODE (SUBREG_REG (to)))
3162 && ! (code == SUBREG
3163 && MODES_TIEABLE_P (GET_MODE (x),
3164 GET_MODE (SUBREG_REG (to))))
3166 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3169 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3171 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3175 /* If we are in a SET_DEST, suppress most cases unless we
3176 have gone inside a MEM, in which case we want to
3177 simplify the address. We assume here that things that
3178 are actually part of the destination have their inner
3179 parts in the first expression. This is true for SUBREG,
3180 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3181 things aside from REG and MEM that should appear in a
3183 new = subst (XEXP (x, i), from, to,
3185 && (code == SUBREG || code == STRICT_LOW_PART
3186 || code == ZERO_EXTRACT))
3188 && i == 0), unique_copy);
3190 /* If we found that we will have to reject this combination,
3191 indicate that by returning the CLOBBER ourselves, rather than
3192 an expression containing it. This will speed things up as
3193 well as prevent accidents where two CLOBBERs are considered
3194 to be equal, thus producing an incorrect simplification. */
3196 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3199 SUBST (XEXP (x, i), new);
3204 /* Try to simplify X. If the simplification changed the code, it is likely
3205 that further simplification will help, so loop, but limit the number
3206 of repetitions that will be performed. */
3208 for (i = 0; i < 4; i++)
3210 /* If X is sufficiently simple, don't bother trying to do anything
3212 if (code != CONST_INT && code != REG && code != CLOBBER)
3213 x = simplify_rtx (x, op0_mode, i == 3, in_dest);
3215 if (GET_CODE (x) == code)
3218 code = GET_CODE (x);
3220 /* We no longer know the original mode of operand 0 since we
3221 have changed the form of X) */
3222 op0_mode = VOIDmode;
3228 /* Simplify X, a piece of RTL. We just operate on the expression at the
3229 outer level; call `subst' to simplify recursively. Return the new
3232 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3233 will be the iteration even if an expression with a code different from
3234 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3237 simplify_rtx (x, op0_mode, last, in_dest)
3239 enum machine_mode op0_mode;
3243 enum rtx_code code = GET_CODE (x);
3244 enum machine_mode mode = GET_MODE (x);
3248 /* If this is a commutative operation, put a constant last and a complex
3249 expression first. We don't need to do this for comparisons here. */
3250 if (GET_RTX_CLASS (code) == 'c'
3251 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
3252 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
3253 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
3254 || (GET_CODE (XEXP (x, 0)) == SUBREG
3255 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
3256 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
3259 SUBST (XEXP (x, 0), XEXP (x, 1));
3260 SUBST (XEXP (x, 1), temp);
3263 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3264 sign extension of a PLUS with a constant, reverse the order of the sign
3265 extension and the addition. Note that this not the same as the original
3266 code, but overflow is undefined for signed values. Also note that the
3267 PLUS will have been partially moved "inside" the sign-extension, so that
3268 the first operand of X will really look like:
3269 (ashiftrt (plus (ashift A C4) C5) C4).
3271 (plus (ashiftrt (ashift A C4) C2) C4)
3272 and replace the first operand of X with that expression. Later parts
3273 of this function may simplify the expression further.
3275 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3276 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3277 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3279 We do this to simplify address expressions. */
3281 if ((code == PLUS || code == MINUS || code == MULT)
3282 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3283 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3284 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3285 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3286 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3287 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3288 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3289 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3290 XEXP (XEXP (XEXP (x, 0), 0), 1),
3291 XEXP (XEXP (x, 0), 1))) != 0)
3294 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3295 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3296 INTVAL (XEXP (XEXP (x, 0), 1)));
3298 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3299 INTVAL (XEXP (XEXP (x, 0), 1)));
3301 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3304 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3305 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3306 things. Check for cases where both arms are testing the same
3309 Don't do anything if all operands are very simple. */
3311 if (((GET_RTX_CLASS (code) == '2' || GET_RTX_CLASS (code) == 'c'
3312 || GET_RTX_CLASS (code) == '<')
3313 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3314 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3315 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3317 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o'
3318 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3319 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 1))))
3321 || (GET_RTX_CLASS (code) == '1'
3322 && ((GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) != 'o'
3323 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3324 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0))))
3327 rtx cond, true, false;
3329 cond = if_then_else_cond (x, &true, &false);
3331 /* If everything is a comparison, what we have is highly unlikely
3332 to be simpler, so don't use it. */
3333 && ! (GET_RTX_CLASS (code) == '<'
3334 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3335 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3337 rtx cop1 = const0_rtx;
3338 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3340 if (cond_code == NE && GET_RTX_CLASS (GET_CODE (cond)) == '<')
3343 /* Simplify the alternative arms; this may collapse the true and
3344 false arms to store-flag values. */
3345 true = subst (true, pc_rtx, pc_rtx, 0, 0);
3346 false = subst (false, pc_rtx, pc_rtx, 0, 0);
3348 /* Restarting if we generate a store-flag expression will cause
3349 us to loop. Just drop through in this case. */
3351 /* If the result values are STORE_FLAG_VALUE and zero, we can
3352 just make the comparison operation. */
3353 if (true == const_true_rtx && false == const0_rtx)
3354 x = gen_binary (cond_code, mode, cond, cop1);
3355 else if (true == const0_rtx && false == const_true_rtx)
3356 x = gen_binary (reverse_condition (cond_code), mode, cond, cop1);
3358 /* Likewise, we can make the negate of a comparison operation
3359 if the result values are - STORE_FLAG_VALUE and zero. */
3360 else if (GET_CODE (true) == CONST_INT
3361 && INTVAL (true) == - STORE_FLAG_VALUE
3362 && false == const0_rtx)
3363 x = gen_unary (NEG, mode, mode,
3364 gen_binary (cond_code, mode, cond, cop1));
3365 else if (GET_CODE (false) == CONST_INT
3366 && INTVAL (false) == - STORE_FLAG_VALUE
3367 && true == const0_rtx)
3368 x = gen_unary (NEG, mode, mode,
3369 gen_binary (reverse_condition (cond_code),
3372 return gen_rtx_IF_THEN_ELSE (mode,
3373 gen_binary (cond_code, VOIDmode,
3377 code = GET_CODE (x);
3378 op0_mode = VOIDmode;
3382 /* Try to fold this expression in case we have constants that weren't
3385 switch (GET_RTX_CLASS (code))
3388 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3391 temp = simplify_relational_operation (code, op0_mode,
3392 XEXP (x, 0), XEXP (x, 1));
3393 #ifdef FLOAT_STORE_FLAG_VALUE
3394 if (temp != 0 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
3395 temp = ((temp == const0_rtx) ? CONST0_RTX (GET_MODE (x))
3396 : immed_real_const_1 (FLOAT_STORE_FLAG_VALUE, GET_MODE (x)));
3401 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3405 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3406 XEXP (x, 1), XEXP (x, 2));
3411 x = temp, code = GET_CODE (temp);
3413 /* First see if we can apply the inverse distributive law. */
3414 if (code == PLUS || code == MINUS
3415 || code == AND || code == IOR || code == XOR)
3417 x = apply_distributive_law (x);
3418 code = GET_CODE (x);
3421 /* If CODE is an associative operation not otherwise handled, see if we
3422 can associate some operands. This can win if they are constants or
3423 if they are logically related (i.e. (a & b) & a. */
3424 if ((code == PLUS || code == MINUS
3425 || code == MULT || code == AND || code == IOR || code == XOR
3426 || code == DIV || code == UDIV
3427 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3428 && INTEGRAL_MODE_P (mode))
3430 if (GET_CODE (XEXP (x, 0)) == code)
3432 rtx other = XEXP (XEXP (x, 0), 0);
3433 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3434 rtx inner_op1 = XEXP (x, 1);
3437 /* Make sure we pass the constant operand if any as the second
3438 one if this is a commutative operation. */
3439 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
3441 rtx tem = inner_op0;
3442 inner_op0 = inner_op1;
3445 inner = simplify_binary_operation (code == MINUS ? PLUS
3446 : code == DIV ? MULT
3447 : code == UDIV ? MULT
3449 mode, inner_op0, inner_op1);
3451 /* For commutative operations, try the other pair if that one
3453 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
3455 other = XEXP (XEXP (x, 0), 1);
3456 inner = simplify_binary_operation (code, mode,
3457 XEXP (XEXP (x, 0), 0),
3462 return gen_binary (code, mode, other, inner);
3466 /* A little bit of algebraic simplification here. */
3470 /* Ensure that our address has any ASHIFTs converted to MULT in case
3471 address-recognizing predicates are called later. */
3472 temp = make_compound_operation (XEXP (x, 0), MEM);
3473 SUBST (XEXP (x, 0), temp);
3477 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3478 is paradoxical. If we can't do that safely, then it becomes
3479 something nonsensical so that this combination won't take place. */
3481 if (GET_CODE (SUBREG_REG (x)) == MEM
3482 && (GET_MODE_SIZE (mode)
3483 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
3485 rtx inner = SUBREG_REG (x);
3486 int endian_offset = 0;
3487 /* Don't change the mode of the MEM
3488 if that would change the meaning of the address. */
3489 if (MEM_VOLATILE_P (SUBREG_REG (x))
3490 || mode_dependent_address_p (XEXP (inner, 0)))
3491 return gen_rtx_CLOBBER (mode, const0_rtx);
3493 if (BYTES_BIG_ENDIAN)
3495 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
3496 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
3497 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
3498 endian_offset -= (UNITS_PER_WORD
3499 - GET_MODE_SIZE (GET_MODE (inner)));
3501 /* Note if the plus_constant doesn't make a valid address
3502 then this combination won't be accepted. */
3503 x = gen_rtx_MEM (mode,
3504 plus_constant (XEXP (inner, 0),
3505 (SUBREG_WORD (x) * UNITS_PER_WORD
3507 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
3508 MEM_COPY_ATTRIBUTES (x, inner);
3512 /* If we are in a SET_DEST, these other cases can't apply. */
3516 /* Changing mode twice with SUBREG => just change it once,
3517 or not at all if changing back to starting mode. */
3518 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
3520 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
3521 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
3522 return SUBREG_REG (SUBREG_REG (x));
3524 SUBST_INT (SUBREG_WORD (x),
3525 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
3526 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
3529 /* SUBREG of a hard register => just change the register number
3530 and/or mode. If the hard register is not valid in that mode,
3531 suppress this combination. If the hard register is the stack,
3532 frame, or argument pointer, leave this as a SUBREG. */
3534 if (GET_CODE (SUBREG_REG (x)) == REG
3535 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER
3536 && REGNO (SUBREG_REG (x)) != FRAME_POINTER_REGNUM
3537 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3538 && REGNO (SUBREG_REG (x)) != HARD_FRAME_POINTER_REGNUM
3540 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3541 && REGNO (SUBREG_REG (x)) != ARG_POINTER_REGNUM
3543 && REGNO (SUBREG_REG (x)) != STACK_POINTER_REGNUM)
3545 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
3547 return gen_rtx_REG (mode,
3548 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
3550 return gen_rtx_CLOBBER (mode, const0_rtx);
3553 /* For a constant, try to pick up the part we want. Handle a full
3554 word and low-order part. Only do this if we are narrowing
3555 the constant; if it is being widened, we have no idea what
3556 the extra bits will have been set to. */
3558 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
3559 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
3560 && GET_MODE_SIZE (op0_mode) > UNITS_PER_WORD
3561 && GET_MODE_CLASS (mode) == MODE_INT)
3563 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
3569 /* If we want a subreg of a constant, at offset 0,
3570 take the low bits. On a little-endian machine, that's
3571 always valid. On a big-endian machine, it's valid
3572 only if the constant's mode fits in one word. Note that we
3573 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3574 if (CONSTANT_P (SUBREG_REG (x))
3575 && ((GET_MODE_SIZE (op0_mode) <= UNITS_PER_WORD
3576 || ! WORDS_BIG_ENDIAN)
3577 ? SUBREG_WORD (x) == 0
3579 == ((GET_MODE_SIZE (op0_mode)
3580 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
3582 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (op0_mode)
3583 && (! WORDS_BIG_ENDIAN
3584 || GET_MODE_BITSIZE (op0_mode) <= BITS_PER_WORD))
3585 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
3587 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3588 since we are saying that the high bits don't matter. */
3589 if (CONSTANT_P (SUBREG_REG (x)) && GET_MODE (SUBREG_REG (x)) == VOIDmode
3590 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (op0_mode))
3591 return SUBREG_REG (x);
3593 /* Note that we cannot do any narrowing for non-constants since
3594 we might have been counting on using the fact that some bits were
3595 zero. We now do this in the SET. */
3600 /* (not (plus X -1)) can become (neg X). */
3601 if (GET_CODE (XEXP (x, 0)) == PLUS
3602 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
3603 return gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
3605 /* Similarly, (not (neg X)) is (plus X -1). */
3606 if (GET_CODE (XEXP (x, 0)) == NEG)
3607 return gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0),
3610 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3611 if (GET_CODE (XEXP (x, 0)) == XOR
3612 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3613 && (temp = simplify_unary_operation (NOT, mode,
3614 XEXP (XEXP (x, 0), 1),
3616 return gen_binary (XOR, mode, XEXP (XEXP (x, 0), 0), temp);
3618 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3619 other than 1, but that is not valid. We could do a similar
3620 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3621 but this doesn't seem common enough to bother with. */
3622 if (GET_CODE (XEXP (x, 0)) == ASHIFT
3623 && XEXP (XEXP (x, 0), 0) == const1_rtx)
3624 return gen_rtx_ROTATE (mode, gen_unary (NOT, mode, mode, const1_rtx),
3625 XEXP (XEXP (x, 0), 1));
3627 if (GET_CODE (XEXP (x, 0)) == SUBREG
3628 && subreg_lowpart_p (XEXP (x, 0))
3629 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3630 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3631 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3632 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3634 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3636 x = gen_rtx_ROTATE (inner_mode,
3637 gen_unary (NOT, inner_mode, inner_mode,
3639 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3640 return gen_lowpart_for_combine (mode, x);
3643 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3644 reversing the comparison code if valid. */
3645 if (STORE_FLAG_VALUE == -1
3646 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3647 && reversible_comparison_p (XEXP (x, 0)))
3648 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3649 mode, XEXP (XEXP (x, 0), 0),
3650 XEXP (XEXP (x, 0), 1));
3652 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3653 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3654 perform the above simplification. */
3656 if (STORE_FLAG_VALUE == -1
3657 && XEXP (x, 1) == const1_rtx
3658 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3659 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3660 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3661 return gen_rtx_combine (GE, mode, XEXP (XEXP (x, 0), 0), const0_rtx);
3663 /* Apply De Morgan's laws to reduce number of patterns for machines
3664 with negating logical insns (and-not, nand, etc.). If result has
3665 only one NOT, put it first, since that is how the patterns are
3668 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3670 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
3672 if (GET_CODE (in1) == NOT)
3673 in1 = XEXP (in1, 0);
3675 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
3677 if (GET_CODE (in2) == NOT)
3678 in2 = XEXP (in2, 0);
3679 else if (GET_CODE (in2) == CONST_INT
3680 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3681 in2 = GEN_INT (GET_MODE_MASK (mode) & ~ INTVAL (in2));
3683 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
3685 if (GET_CODE (in2) == NOT)
3688 in2 = in1; in1 = tem;
3691 return gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
3697 /* (neg (plus X 1)) can become (not X). */
3698 if (GET_CODE (XEXP (x, 0)) == PLUS
3699 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3700 return gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
3702 /* Similarly, (neg (not X)) is (plus X 1). */
3703 if (GET_CODE (XEXP (x, 0)) == NOT)
3704 return plus_constant (XEXP (XEXP (x, 0), 0), 1);
3706 /* (neg (minus X Y)) can become (minus Y X). */
3707 if (GET_CODE (XEXP (x, 0)) == MINUS
3708 && (! FLOAT_MODE_P (mode)
3709 /* x-y != -(y-x) with IEEE floating point. */
3710 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3712 return gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
3713 XEXP (XEXP (x, 0), 0));
3715 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3716 if (GET_CODE (XEXP (x, 0)) == XOR && XEXP (XEXP (x, 0), 1) == const1_rtx
3717 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
3718 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
3720 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3721 if we can then eliminate the NEG (e.g.,
3722 if the operand is a constant). */
3724 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3726 temp = simplify_unary_operation (NEG, mode,
3727 XEXP (XEXP (x, 0), 0), mode);
3730 SUBST (XEXP (XEXP (x, 0), 0), temp);
3735 temp = expand_compound_operation (XEXP (x, 0));
3737 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3738 replaced by (lshiftrt X C). This will convert
3739 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3741 if (GET_CODE (temp) == ASHIFTRT
3742 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3743 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
3744 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
3745 INTVAL (XEXP (temp, 1)));
3747 /* If X has only a single bit that might be nonzero, say, bit I, convert
3748 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3749 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3750 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3751 or a SUBREG of one since we'd be making the expression more
3752 complex if it was just a register. */
3754 if (GET_CODE (temp) != REG
3755 && ! (GET_CODE (temp) == SUBREG
3756 && GET_CODE (SUBREG_REG (temp)) == REG)
3757 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
3759 rtx temp1 = simplify_shift_const
3760 (NULL_RTX, ASHIFTRT, mode,
3761 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
3762 GET_MODE_BITSIZE (mode) - 1 - i),
3763 GET_MODE_BITSIZE (mode) - 1 - i);
3765 /* If all we did was surround TEMP with the two shifts, we
3766 haven't improved anything, so don't use it. Otherwise,
3767 we are better off with TEMP1. */
3768 if (GET_CODE (temp1) != ASHIFTRT
3769 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
3770 || XEXP (XEXP (temp1, 0), 0) != temp)
3776 /* We can't handle truncation to a partial integer mode here
3777 because we don't know the real bitsize of the partial
3779 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
3782 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3783 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3784 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
3786 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
3787 GET_MODE_MASK (mode), NULL_RTX, 0));
3789 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
3790 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3791 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3792 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3793 return XEXP (XEXP (x, 0), 0);
3795 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
3796 (OP:SI foo:SI) if OP is NEG or ABS. */
3797 if ((GET_CODE (XEXP (x, 0)) == ABS
3798 || GET_CODE (XEXP (x, 0)) == NEG)
3799 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
3800 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
3801 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3802 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3803 XEXP (XEXP (XEXP (x, 0), 0), 0));
3805 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
3807 if (GET_CODE (XEXP (x, 0)) == SUBREG
3808 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
3809 && subreg_lowpart_p (XEXP (x, 0)))
3810 return SUBREG_REG (XEXP (x, 0));
3812 /* If we know that the value is already truncated, we can
3813 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION is
3814 nonzero for the corresponding modes. */
3815 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
3816 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3817 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3818 >= GET_MODE_BITSIZE (mode) + 1)
3819 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3821 /* A truncate of a comparison can be replaced with a subreg if
3822 STORE_FLAG_VALUE permits. This is like the previous test,
3823 but it works even if the comparison is done in a mode larger
3824 than HOST_BITS_PER_WIDE_INT. */
3825 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3826 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3827 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0)
3828 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3830 /* Similarly, a truncate of a register whose value is a
3831 comparison can be replaced with a subreg if STORE_FLAG_VALUE
3833 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3834 && ((HOST_WIDE_INT) STORE_FLAG_VALUE &~ GET_MODE_MASK (mode)) == 0
3835 && (temp = get_last_value (XEXP (x, 0)))
3836 && GET_RTX_CLASS (GET_CODE (temp)) == '<')
3837 return gen_lowpart_for_combine (mode, XEXP (x, 0));
3841 case FLOAT_TRUNCATE:
3842 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
3843 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
3844 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
3845 return XEXP (XEXP (x, 0), 0);
3847 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
3848 (OP:SF foo:SF) if OP is NEG or ABS. */
3849 if ((GET_CODE (XEXP (x, 0)) == ABS
3850 || GET_CODE (XEXP (x, 0)) == NEG)
3851 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
3852 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
3853 return gen_unary (GET_CODE (XEXP (x, 0)), mode, mode,
3854 XEXP (XEXP (XEXP (x, 0), 0), 0));
3856 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
3857 is (float_truncate:SF x). */
3858 if (GET_CODE (XEXP (x, 0)) == SUBREG
3859 && subreg_lowpart_p (XEXP (x, 0))
3860 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
3861 return SUBREG_REG (XEXP (x, 0));
3866 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
3867 using cc0, in which case we want to leave it as a COMPARE
3868 so we can distinguish it from a register-register-copy. */
3869 if (XEXP (x, 1) == const0_rtx)
3872 /* In IEEE floating point, x-0 is not the same as x. */
3873 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
3874 || ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0)))
3876 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
3882 /* (const (const X)) can become (const X). Do it this way rather than
3883 returning the inner CONST since CONST can be shared with a
3885 if (GET_CODE (XEXP (x, 0)) == CONST)
3886 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3891 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
3892 can add in an offset. find_split_point will split this address up
3893 again if it doesn't match. */
3894 if (GET_CODE (XEXP (x, 0)) == HIGH
3895 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
3901 /* If we have (plus (plus (A const) B)), associate it so that CONST is
3902 outermost. That's because that's the way indexed addresses are
3903 supposed to appear. This code used to check many more cases, but
3904 they are now checked elsewhere. */
3905 if (GET_CODE (XEXP (x, 0)) == PLUS
3906 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
3907 return gen_binary (PLUS, mode,
3908 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
3910 XEXP (XEXP (x, 0), 1));
3912 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
3913 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
3914 bit-field and can be replaced by either a sign_extend or a
3915 sign_extract. The `and' may be a zero_extend. */
3916 if (GET_CODE (XEXP (x, 0)) == XOR
3917 && GET_CODE (XEXP (x, 1)) == CONST_INT
3918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3919 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
3920 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
3921 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3922 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
3923 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3924 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
3925 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
3926 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
3927 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
3929 return simplify_shift_const
3930 (NULL_RTX, ASHIFTRT, mode,
3931 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3932 XEXP (XEXP (XEXP (x, 0), 0), 0),
3933 GET_MODE_BITSIZE (mode) - (i + 1)),
3934 GET_MODE_BITSIZE (mode) - (i + 1));
3936 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
3937 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
3938 is 1. This produces better code than the alternative immediately
3940 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3941 && reversible_comparison_p (XEXP (x, 0))
3942 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
3943 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx)))
3945 gen_unary (NEG, mode, mode,
3946 gen_binary (reverse_condition (GET_CODE (XEXP (x, 0))),
3947 mode, XEXP (XEXP (x, 0), 0),
3948 XEXP (XEXP (x, 0), 1)));
3950 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
3951 can become (ashiftrt (ashift (xor x 1) C) C) where C is
3952 the bitsize of the mode - 1. This allows simplification of
3953 "a = (b & 8) == 0;" */
3954 if (XEXP (x, 1) == constm1_rtx
3955 && GET_CODE (XEXP (x, 0)) != REG
3956 && ! (GET_CODE (XEXP (x,0)) == SUBREG
3957 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
3958 && nonzero_bits (XEXP (x, 0), mode) == 1)
3959 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
3960 simplify_shift_const (NULL_RTX, ASHIFT, mode,
3961 gen_rtx_combine (XOR, mode,
3962 XEXP (x, 0), const1_rtx),
3963 GET_MODE_BITSIZE (mode) - 1),
3964 GET_MODE_BITSIZE (mode) - 1);
3966 /* If we are adding two things that have no bits in common, convert
3967 the addition into an IOR. This will often be further simplified,
3968 for example in cases like ((a & 1) + (a & 2)), which can
3971 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
3972 && (nonzero_bits (XEXP (x, 0), mode)
3973 & nonzero_bits (XEXP (x, 1), mode)) == 0)
3974 return gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
3978 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
3979 by reversing the comparison code if valid. */
3980 if (STORE_FLAG_VALUE == 1
3981 && XEXP (x, 0) == const1_rtx
3982 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<'
3983 && reversible_comparison_p (XEXP (x, 1)))
3984 return gen_binary (reverse_condition (GET_CODE (XEXP (x, 1))),
3985 mode, XEXP (XEXP (x, 1), 0),
3986 XEXP (XEXP (x, 1), 1));
3988 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
3989 (and <foo> (const_int pow2-1)) */
3990 if (GET_CODE (XEXP (x, 1)) == AND
3991 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3992 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
3993 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3994 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
3995 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
3997 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
3999 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4000 return gen_binary (MINUS, mode,
4001 gen_binary (MINUS, mode, XEXP (x, 0),
4002 XEXP (XEXP (x, 1), 0)),
4003 XEXP (XEXP (x, 1), 1));
4007 /* If we have (mult (plus A B) C), apply the distributive law and then
4008 the inverse distributive law to see if things simplify. This
4009 occurs mostly in addresses, often when unrolling loops. */
4011 if (GET_CODE (XEXP (x, 0)) == PLUS)
4013 x = apply_distributive_law
4014 (gen_binary (PLUS, mode,
4015 gen_binary (MULT, mode,
4016 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4017 gen_binary (MULT, mode,
4018 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
4020 if (GET_CODE (x) != MULT)
4026 /* If this is a divide by a power of two, treat it as a shift if
4027 its first operand is a shift. */
4028 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4029 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4030 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4031 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4032 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4033 || GET_CODE (XEXP (x, 0)) == ROTATE
4034 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4035 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4039 case GT: case GTU: case GE: case GEU:
4040 case LT: case LTU: case LE: case LEU:
4041 /* If the first operand is a condition code, we can't do anything
4043 if (GET_CODE (XEXP (x, 0)) == COMPARE
4044 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4046 && XEXP (x, 0) != cc0_rtx
4050 rtx op0 = XEXP (x, 0);
4051 rtx op1 = XEXP (x, 1);
4052 enum rtx_code new_code;
4054 if (GET_CODE (op0) == COMPARE)
4055 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4057 /* Simplify our comparison, if possible. */
4058 new_code = simplify_comparison (code, &op0, &op1);
4060 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4061 if only the low-order bit is possibly nonzero in X (such as when
4062 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4063 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4064 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4067 Remove any ZERO_EXTRACT we made when thinking this was a
4068 comparison. It may now be simpler to use, e.g., an AND. If a
4069 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4070 the call to make_compound_operation in the SET case. */
4072 if (STORE_FLAG_VALUE == 1
4073 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4074 && op1 == const0_rtx && nonzero_bits (op0, mode) == 1)
4075 return gen_lowpart_for_combine (mode,
4076 expand_compound_operation (op0));
4078 else if (STORE_FLAG_VALUE == 1
4079 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4080 && op1 == const0_rtx
4081 && (num_sign_bit_copies (op0, mode)
4082 == GET_MODE_BITSIZE (mode)))
4084 op0 = expand_compound_operation (op0);
4085 return gen_unary (NEG, mode, mode,
4086 gen_lowpart_for_combine (mode, op0));
4089 else if (STORE_FLAG_VALUE == 1
4090 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4091 && op1 == const0_rtx
4092 && nonzero_bits (op0, mode) == 1)
4094 op0 = expand_compound_operation (op0);
4095 return gen_binary (XOR, mode,
4096 gen_lowpart_for_combine (mode, op0),
4100 else if (STORE_FLAG_VALUE == 1
4101 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4102 && op1 == const0_rtx
4103 && (num_sign_bit_copies (op0, mode)
4104 == GET_MODE_BITSIZE (mode)))
4106 op0 = expand_compound_operation (op0);
4107 return plus_constant (gen_lowpart_for_combine (mode, op0), 1);
4110 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4112 if (STORE_FLAG_VALUE == -1
4113 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4114 && op1 == const0_rtx
4115 && (num_sign_bit_copies (op0, mode)
4116 == GET_MODE_BITSIZE (mode)))
4117 return gen_lowpart_for_combine (mode,
4118 expand_compound_operation (op0));
4120 else if (STORE_FLAG_VALUE == -1
4121 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4122 && op1 == const0_rtx
4123 && nonzero_bits (op0, mode) == 1)
4125 op0 = expand_compound_operation (op0);
4126 return gen_unary (NEG, mode, mode,
4127 gen_lowpart_for_combine (mode, op0));
4130 else if (STORE_FLAG_VALUE == -1
4131 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4132 && op1 == const0_rtx
4133 && (num_sign_bit_copies (op0, mode)
4134 == GET_MODE_BITSIZE (mode)))
4136 op0 = expand_compound_operation (op0);
4137 return gen_unary (NOT, mode, mode,
4138 gen_lowpart_for_combine (mode, op0));
4141 /* If X is 0/1, (eq X 0) is X-1. */
4142 else if (STORE_FLAG_VALUE == -1
4143 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4144 && op1 == const0_rtx
4145 && nonzero_bits (op0, mode) == 1)
4147 op0 = expand_compound_operation (op0);
4148 return plus_constant (gen_lowpart_for_combine (mode, op0), -1);
4151 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4152 one bit that might be nonzero, we can convert (ne x 0) to
4153 (ashift x c) where C puts the bit in the sign bit. Remove any
4154 AND with STORE_FLAG_VALUE when we are done, since we are only
4155 going to test the sign bit. */
4156 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4157 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4158 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4159 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE(mode)-1))
4160 && op1 == const0_rtx
4161 && mode == GET_MODE (op0)
4162 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4164 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4165 expand_compound_operation (op0),
4166 GET_MODE_BITSIZE (mode) - 1 - i);
4167 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4173 /* If the code changed, return a whole new comparison. */
4174 if (new_code != code)
4175 return gen_rtx_combine (new_code, mode, op0, op1);
4177 /* Otherwise, keep this operation, but maybe change its operands.
4178 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4179 SUBST (XEXP (x, 0), op0);
4180 SUBST (XEXP (x, 1), op1);
4185 return simplify_if_then_else (x);
4191 /* If we are processing SET_DEST, we are done. */
4195 return expand_compound_operation (x);
4198 return simplify_set (x);
4203 return simplify_logical (x, last);
4206 /* (abs (neg <foo>)) -> (abs <foo>) */
4207 if (GET_CODE (XEXP (x, 0)) == NEG)
4208 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4210 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4212 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4215 /* If operand is something known to be positive, ignore the ABS. */
4216 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4217 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4218 <= HOST_BITS_PER_WIDE_INT)
4219 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4220 & ((HOST_WIDE_INT) 1
4221 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4226 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4227 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4228 return gen_rtx_combine (NEG, mode, XEXP (x, 0));
4233 /* (ffs (*_extend <X>)) = (ffs <X>) */
4234 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4235 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4236 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4240 /* (float (sign_extend <X>)) = (float <X>). */
4241 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4242 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4250 /* If this is a shift by a constant amount, simplify it. */
4251 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4252 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4253 INTVAL (XEXP (x, 1)));
4255 #ifdef SHIFT_COUNT_TRUNCATED
4256 else if (SHIFT_COUNT_TRUNCATED && GET_CODE (XEXP (x, 1)) != REG)
4258 force_to_mode (XEXP (x, 1), GET_MODE (x),
4260 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4274 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4277 simplify_if_then_else (x)
4280 enum machine_mode mode = GET_MODE (x);
4281 rtx cond = XEXP (x, 0);
4282 rtx true = XEXP (x, 1);
4283 rtx false = XEXP (x, 2);
4284 enum rtx_code true_code = GET_CODE (cond);
4285 int comparison_p = GET_RTX_CLASS (true_code) == '<';
4289 /* Simplify storing of the truth value. */
4290 if (comparison_p && true == const_true_rtx && false == const0_rtx)
4291 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4293 /* Also when the truth value has to be reversed. */
4294 if (comparison_p && reversible_comparison_p (cond)
4295 && true == const0_rtx && false == const_true_rtx)
4296 return gen_binary (reverse_condition (true_code),
4297 mode, XEXP (cond, 0), XEXP (cond, 1));
4299 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4300 in it is being compared against certain values. Get the true and false
4301 comparisons and see if that says anything about the value of each arm. */
4303 if (comparison_p && reversible_comparison_p (cond)
4304 && GET_CODE (XEXP (cond, 0)) == REG)
4307 rtx from = XEXP (cond, 0);
4308 enum rtx_code false_code = reverse_condition (true_code);
4309 rtx true_val = XEXP (cond, 1);
4310 rtx false_val = true_val;
4313 /* If FALSE_CODE is EQ, swap the codes and arms. */
4315 if (false_code == EQ)
4317 swapped = 1, true_code = EQ, false_code = NE;
4318 temp = true, true = false, false = temp;
4321 /* If we are comparing against zero and the expression being tested has
4322 only a single bit that might be nonzero, that is its value when it is
4323 not equal to zero. Similarly if it is known to be -1 or 0. */
4325 if (true_code == EQ && true_val == const0_rtx
4326 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4327 false_code = EQ, false_val = GEN_INT (nzb);
4328 else if (true_code == EQ && true_val == const0_rtx
4329 && (num_sign_bit_copies (from, GET_MODE (from))
4330 == GET_MODE_BITSIZE (GET_MODE (from))))
4331 false_code = EQ, false_val = constm1_rtx;
4333 /* Now simplify an arm if we know the value of the register in the
4334 branch and it is used in the arm. Be careful due to the potential
4335 of locally-shared RTL. */
4337 if (reg_mentioned_p (from, true))
4338 true = subst (known_cond (copy_rtx (true), true_code, from, true_val),
4339 pc_rtx, pc_rtx, 0, 0);
4340 if (reg_mentioned_p (from, false))
4341 false = subst (known_cond (copy_rtx (false), false_code,
4343 pc_rtx, pc_rtx, 0, 0);
4345 SUBST (XEXP (x, 1), swapped ? false : true);
4346 SUBST (XEXP (x, 2), swapped ? true : false);
4348 true = XEXP (x, 1), false = XEXP (x, 2), true_code = GET_CODE (cond);
4351 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4352 reversed, do so to avoid needing two sets of patterns for
4353 subtract-and-branch insns. Similarly if we have a constant in the true
4354 arm, the false arm is the same as the first operand of the comparison, or
4355 the false arm is more complicated than the true arm. */
4357 if (comparison_p && reversible_comparison_p (cond)
4359 || (CONSTANT_P (true)
4360 && GET_CODE (false) != CONST_INT && false != pc_rtx)
4361 || true == const0_rtx
4362 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4363 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4364 || (GET_CODE (true) == SUBREG
4365 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4366 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4367 || reg_mentioned_p (true, false)
4368 || rtx_equal_p (false, XEXP (cond, 0))))
4370 true_code = reverse_condition (true_code);
4372 gen_binary (true_code, GET_MODE (cond), XEXP (cond, 0),
4375 SUBST (XEXP (x, 1), false);
4376 SUBST (XEXP (x, 2), true);
4378 temp = true, true = false, false = temp, cond = XEXP (x, 0);
4380 /* It is possible that the conditional has been simplified out. */
4381 true_code = GET_CODE (cond);
4382 comparison_p = GET_RTX_CLASS (true_code) == '<';
4385 /* If the two arms are identical, we don't need the comparison. */
4387 if (rtx_equal_p (true, false) && ! side_effects_p (cond))
4390 /* Convert a == b ? b : a to "a". */
4391 if (true_code == EQ && ! side_effects_p (cond)
4392 && rtx_equal_p (XEXP (cond, 0), false)
4393 && rtx_equal_p (XEXP (cond, 1), true))
4395 else if (true_code == NE && ! side_effects_p (cond)
4396 && rtx_equal_p (XEXP (cond, 0), true)
4397 && rtx_equal_p (XEXP (cond, 1), false))
4400 /* Look for cases where we have (abs x) or (neg (abs X)). */
4402 if (GET_MODE_CLASS (mode) == MODE_INT
4403 && GET_CODE (false) == NEG
4404 && rtx_equal_p (true, XEXP (false, 0))
4406 && rtx_equal_p (true, XEXP (cond, 0))
4407 && ! side_effects_p (true))
4412 return gen_unary (ABS, mode, mode, true);
4415 return gen_unary (NEG, mode, mode, gen_unary (ABS, mode, mode, true));
4420 /* Look for MIN or MAX. */
4422 if ((! FLOAT_MODE_P (mode) || flag_fast_math)
4424 && rtx_equal_p (XEXP (cond, 0), true)
4425 && rtx_equal_p (XEXP (cond, 1), false)
4426 && ! side_effects_p (cond))
4431 return gen_binary (SMAX, mode, true, false);
4434 return gen_binary (SMIN, mode, true, false);
4437 return gen_binary (UMAX, mode, true, false);
4440 return gen_binary (UMIN, mode, true, false);
4445 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4446 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4447 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4448 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4449 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4450 neither 1 or -1, but it isn't worth checking for. */
4452 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4453 && comparison_p && mode != VOIDmode && ! side_effects_p (x))
4455 rtx t = make_compound_operation (true, SET);
4456 rtx f = make_compound_operation (false, SET);
4457 rtx cond_op0 = XEXP (cond, 0);
4458 rtx cond_op1 = XEXP (cond, 1);
4459 enum rtx_code op, extend_op = NIL;
4460 enum machine_mode m = mode;
4463 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4464 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4465 || GET_CODE (t) == ASHIFT
4466 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4467 && rtx_equal_p (XEXP (t, 0), f))
4468 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4470 /* If an identity-zero op is commutative, check whether there
4471 would be a match if we swapped the operands. */
4472 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4473 || GET_CODE (t) == XOR)
4474 && rtx_equal_p (XEXP (t, 1), f))
4475 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4476 else if (GET_CODE (t) == SIGN_EXTEND
4477 && (GET_CODE (XEXP (t, 0)) == PLUS
4478 || GET_CODE (XEXP (t, 0)) == MINUS
4479 || GET_CODE (XEXP (t, 0)) == IOR
4480 || GET_CODE (XEXP (t, 0)) == XOR
4481 || GET_CODE (XEXP (t, 0)) == ASHIFT
4482 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4483 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4484 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4485 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4486 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4487 && (num_sign_bit_copies (f, GET_MODE (f))
4488 > (GET_MODE_BITSIZE (mode)
4489 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4491 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4492 extend_op = SIGN_EXTEND;
4493 m = GET_MODE (XEXP (t, 0));
4495 else if (GET_CODE (t) == SIGN_EXTEND
4496 && (GET_CODE (XEXP (t, 0)) == PLUS
4497 || GET_CODE (XEXP (t, 0)) == IOR
4498 || GET_CODE (XEXP (t, 0)) == XOR)
4499 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4500 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4501 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4502 && (num_sign_bit_copies (f, GET_MODE (f))
4503 > (GET_MODE_BITSIZE (mode)
4504 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4506 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4507 extend_op = SIGN_EXTEND;
4508 m = GET_MODE (XEXP (t, 0));
4510 else if (GET_CODE (t) == ZERO_EXTEND
4511 && (GET_CODE (XEXP (t, 0)) == PLUS
4512 || GET_CODE (XEXP (t, 0)) == MINUS
4513 || GET_CODE (XEXP (t, 0)) == IOR
4514 || GET_CODE (XEXP (t, 0)) == XOR
4515 || GET_CODE (XEXP (t, 0)) == ASHIFT
4516 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4517 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4518 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4519 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4520 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4521 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4522 && ((nonzero_bits (f, GET_MODE (f))
4523 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4526 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4527 extend_op = ZERO_EXTEND;
4528 m = GET_MODE (XEXP (t, 0));
4530 else if (GET_CODE (t) == ZERO_EXTEND
4531 && (GET_CODE (XEXP (t, 0)) == PLUS
4532 || GET_CODE (XEXP (t, 0)) == IOR
4533 || GET_CODE (XEXP (t, 0)) == XOR)
4534 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4535 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4536 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4537 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4538 && ((nonzero_bits (f, GET_MODE (f))
4539 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4542 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4543 extend_op = ZERO_EXTEND;
4544 m = GET_MODE (XEXP (t, 0));
4549 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
4550 pc_rtx, pc_rtx, 0, 0);
4551 temp = gen_binary (MULT, m, temp,
4552 gen_binary (MULT, m, c1, const_true_rtx));
4553 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4554 temp = gen_binary (op, m, gen_lowpart_for_combine (m, z), temp);
4556 if (extend_op != NIL)
4557 temp = gen_unary (extend_op, mode, m, temp);
4563 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4564 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4565 negation of a single bit, we can convert this operation to a shift. We
4566 can actually do this more generally, but it doesn't seem worth it. */
4568 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4569 && false == const0_rtx && GET_CODE (true) == CONST_INT
4570 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4571 && (i = exact_log2 (INTVAL (true))) >= 0)
4572 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4573 == GET_MODE_BITSIZE (mode))
4574 && (i = exact_log2 (- INTVAL (true))) >= 0)))
4576 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4577 gen_lowpart_for_combine (mode, XEXP (cond, 0)), i);
4582 /* Simplify X, a SET expression. Return the new expression. */
4588 rtx src = SET_SRC (x);
4589 rtx dest = SET_DEST (x);
4590 enum machine_mode mode
4591 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4595 /* (set (pc) (return)) gets written as (return). */
4596 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4599 /* Now that we know for sure which bits of SRC we are using, see if we can
4600 simplify the expression for the object knowing that we only need the
4603 if (GET_MODE_CLASS (mode) == MODE_INT)
4604 src = force_to_mode (src, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
4606 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4607 the comparison result and try to simplify it unless we already have used
4608 undobuf.other_insn. */
4609 if ((GET_CODE (src) == COMPARE
4614 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4615 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4616 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
4617 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4619 enum rtx_code old_code = GET_CODE (*cc_use);
4620 enum rtx_code new_code;
4622 int other_changed = 0;
4623 enum machine_mode compare_mode = GET_MODE (dest);
4625 if (GET_CODE (src) == COMPARE)
4626 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4628 op0 = src, op1 = const0_rtx;
4630 /* Simplify our comparison, if possible. */
4631 new_code = simplify_comparison (old_code, &op0, &op1);
4633 #ifdef EXTRA_CC_MODES
4634 /* If this machine has CC modes other than CCmode, check to see if we
4635 need to use a different CC mode here. */
4636 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
4637 #endif /* EXTRA_CC_MODES */
4639 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4640 /* If the mode changed, we have to change SET_DEST, the mode in the
4641 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4642 a hard register, just build new versions with the proper mode. If it
4643 is a pseudo, we lose unless it is only time we set the pseudo, in
4644 which case we can safely change its mode. */
4645 if (compare_mode != GET_MODE (dest))
4647 int regno = REGNO (dest);
4648 rtx new_dest = gen_rtx_REG (compare_mode, regno);
4650 if (regno < FIRST_PSEUDO_REGISTER
4651 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
4653 if (regno >= FIRST_PSEUDO_REGISTER)
4654 SUBST (regno_reg_rtx[regno], new_dest);
4656 SUBST (SET_DEST (x), new_dest);
4657 SUBST (XEXP (*cc_use, 0), new_dest);
4665 /* If the code changed, we have to build a new comparison in
4666 undobuf.other_insn. */
4667 if (new_code != old_code)
4669 unsigned HOST_WIDE_INT mask;
4671 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
4674 /* If the only change we made was to change an EQ into an NE or
4675 vice versa, OP0 has only one bit that might be nonzero, and OP1
4676 is zero, check if changing the user of the condition code will
4677 produce a valid insn. If it won't, we can keep the original code
4678 in that insn by surrounding our operation with an XOR. */
4680 if (((old_code == NE && new_code == EQ)
4681 || (old_code == EQ && new_code == NE))
4682 && ! other_changed && op1 == const0_rtx
4683 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
4684 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
4686 rtx pat = PATTERN (other_insn), note = 0;
4688 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
4689 && ! check_asm_operands (pat)))
4691 PUT_CODE (*cc_use, old_code);
4694 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
4702 undobuf.other_insn = other_insn;
4705 /* If we are now comparing against zero, change our source if
4706 needed. If we do not use cc0, we always have a COMPARE. */
4707 if (op1 == const0_rtx && dest == cc0_rtx)
4709 SUBST (SET_SRC (x), op0);
4715 /* Otherwise, if we didn't previously have a COMPARE in the
4716 correct mode, we need one. */
4717 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
4720 gen_rtx_combine (COMPARE, compare_mode, op0, op1));
4725 /* Otherwise, update the COMPARE if needed. */
4726 SUBST (XEXP (src, 0), op0);
4727 SUBST (XEXP (src, 1), op1);
4732 /* Get SET_SRC in a form where we have placed back any
4733 compound expressions. Then do the checks below. */
4734 src = make_compound_operation (src, SET);
4735 SUBST (SET_SRC (x), src);
4738 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4739 and X being a REG or (subreg (reg)), we may be able to convert this to
4740 (set (subreg:m2 x) (op)).
4742 We can always do this if M1 is narrower than M2 because that means that
4743 we only care about the low bits of the result.
4745 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4746 perform a narrower operation than requested since the high-order bits will
4747 be undefined. On machine where it is defined, this transformation is safe
4748 as long as M1 and M2 have the same number of words. */
4750 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4751 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src))) != 'o'
4752 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
4754 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
4755 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
4756 #ifndef WORD_REGISTER_OPERATIONS
4757 && (GET_MODE_SIZE (GET_MODE (src))
4758 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4760 #ifdef CLASS_CANNOT_CHANGE_SIZE
4761 && ! (GET_CODE (dest) == REG && REGNO (dest) < FIRST_PSEUDO_REGISTER
4762 && (TEST_HARD_REG_BIT
4763 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_SIZE],
4765 && (GET_MODE_SIZE (GET_MODE (src))
4766 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
4768 && (GET_CODE (dest) == REG
4769 || (GET_CODE (dest) == SUBREG
4770 && GET_CODE (SUBREG_REG (dest)) == REG)))
4772 SUBST (SET_DEST (x),
4773 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src)),
4775 SUBST (SET_SRC (x), SUBREG_REG (src));
4777 src = SET_SRC (x), dest = SET_DEST (x);
4780 #ifdef LOAD_EXTEND_OP
4781 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
4782 would require a paradoxical subreg. Replace the subreg with a
4783 zero_extend to avoid the reload that would otherwise be required. */
4785 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
4786 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != NIL
4787 && SUBREG_WORD (src) == 0
4788 && (GET_MODE_SIZE (GET_MODE (src))
4789 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
4790 && GET_CODE (SUBREG_REG (src)) == MEM)
4793 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
4794 GET_MODE (src), XEXP (src, 0)));
4800 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
4801 are comparing an item known to be 0 or -1 against 0, use a logical
4802 operation instead. Check for one of the arms being an IOR of the other
4803 arm with some value. We compute three terms to be IOR'ed together. In
4804 practice, at most two will be nonzero. Then we do the IOR's. */
4806 if (GET_CODE (dest) != PC
4807 && GET_CODE (src) == IF_THEN_ELSE
4808 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
4809 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
4810 && XEXP (XEXP (src, 0), 1) == const0_rtx
4811 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
4812 #ifdef HAVE_conditional_move
4813 && ! can_conditionally_move_p (GET_MODE (src))
4815 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
4816 GET_MODE (XEXP (XEXP (src, 0), 0)))
4817 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
4818 && ! side_effects_p (src))
4820 rtx true = (GET_CODE (XEXP (src, 0)) == NE
4821 ? XEXP (src, 1) : XEXP (src, 2));
4822 rtx false = (GET_CODE (XEXP (src, 0)) == NE
4823 ? XEXP (src, 2) : XEXP (src, 1));
4824 rtx term1 = const0_rtx, term2, term3;
4826 if (GET_CODE (true) == IOR && rtx_equal_p (XEXP (true, 0), false))
4827 term1 = false, true = XEXP (true, 1), false = const0_rtx;
4828 else if (GET_CODE (true) == IOR
4829 && rtx_equal_p (XEXP (true, 1), false))
4830 term1 = false, true = XEXP (true, 0), false = const0_rtx;
4831 else if (GET_CODE (false) == IOR
4832 && rtx_equal_p (XEXP (false, 0), true))
4833 term1 = true, false = XEXP (false, 1), true = const0_rtx;
4834 else if (GET_CODE (false) == IOR
4835 && rtx_equal_p (XEXP (false, 1), true))
4836 term1 = true, false = XEXP (false, 0), true = const0_rtx;
4838 term2 = gen_binary (AND, GET_MODE (src), XEXP (XEXP (src, 0), 0), true);
4839 term3 = gen_binary (AND, GET_MODE (src),
4840 gen_unary (NOT, GET_MODE (src), GET_MODE (src),
4841 XEXP (XEXP (src, 0), 0)),
4845 gen_binary (IOR, GET_MODE (src),
4846 gen_binary (IOR, GET_MODE (src), term1, term2),
4852 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
4853 whole thing fail. */
4854 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
4856 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
4859 /* Convert this into a field assignment operation, if possible. */
4860 return make_field_assignment (x);
4863 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
4864 result. LAST is nonzero if this is the last retry. */
4867 simplify_logical (x, last)
4871 enum machine_mode mode = GET_MODE (x);
4872 rtx op0 = XEXP (x, 0);
4873 rtx op1 = XEXP (x, 1);
4875 switch (GET_CODE (x))
4878 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
4879 insn (and may simplify more). */
4880 if (GET_CODE (op0) == XOR
4881 && rtx_equal_p (XEXP (op0, 0), op1)
4882 && ! side_effects_p (op1))
4883 x = gen_binary (AND, mode,
4884 gen_unary (NOT, mode, mode, XEXP (op0, 1)), op1);
4886 if (GET_CODE (op0) == XOR
4887 && rtx_equal_p (XEXP (op0, 1), op1)
4888 && ! side_effects_p (op1))
4889 x = gen_binary (AND, mode,
4890 gen_unary (NOT, mode, mode, XEXP (op0, 0)), op1);
4892 /* Similarly for (~ (A ^ B)) & A. */
4893 if (GET_CODE (op0) == NOT
4894 && GET_CODE (XEXP (op0, 0)) == XOR
4895 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
4896 && ! side_effects_p (op1))
4897 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
4899 if (GET_CODE (op0) == NOT
4900 && GET_CODE (XEXP (op0, 0)) == XOR
4901 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
4902 && ! side_effects_p (op1))
4903 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
4905 /* We can call simplify_and_const_int only if we don't lose
4906 any (sign) bits when converting INTVAL (op1) to
4907 "unsigned HOST_WIDE_INT". */
4908 if (GET_CODE (op1) == CONST_INT
4909 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4910 || INTVAL (op1) > 0))
4912 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
4914 /* If we have (ior (and (X C1) C2)) and the next restart would be
4915 the last, simplify this by making C1 as small as possible
4918 && GET_CODE (x) == IOR && GET_CODE (op0) == AND
4919 && GET_CODE (XEXP (op0, 1)) == CONST_INT
4920 && GET_CODE (op1) == CONST_INT)
4921 return gen_binary (IOR, mode,
4922 gen_binary (AND, mode, XEXP (op0, 0),
4923 GEN_INT (INTVAL (XEXP (op0, 1))
4924 & ~ INTVAL (op1))), op1);
4926 if (GET_CODE (x) != AND)
4929 if (GET_RTX_CLASS (GET_CODE (x)) == 'c'
4930 || GET_RTX_CLASS (GET_CODE (x)) == '2')
4931 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
4934 /* Convert (A | B) & A to A. */
4935 if (GET_CODE (op0) == IOR
4936 && (rtx_equal_p (XEXP (op0, 0), op1)
4937 || rtx_equal_p (XEXP (op0, 1), op1))
4938 && ! side_effects_p (XEXP (op0, 0))
4939 && ! side_effects_p (XEXP (op0, 1)))
4942 /* In the following group of tests (and those in case IOR below),
4943 we start with some combination of logical operations and apply
4944 the distributive law followed by the inverse distributive law.
4945 Most of the time, this results in no change. However, if some of
4946 the operands are the same or inverses of each other, simplifications
4949 For example, (and (ior A B) (not B)) can occur as the result of
4950 expanding a bit field assignment. When we apply the distributive
4951 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
4952 which then simplifies to (and (A (not B))).
4954 If we have (and (ior A B) C), apply the distributive law and then
4955 the inverse distributive law to see if things simplify. */
4957 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
4959 x = apply_distributive_law
4960 (gen_binary (GET_CODE (op0), mode,
4961 gen_binary (AND, mode, XEXP (op0, 0), op1),
4962 gen_binary (AND, mode, XEXP (op0, 1), op1)));
4963 if (GET_CODE (x) != AND)
4967 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
4968 return apply_distributive_law
4969 (gen_binary (GET_CODE (op1), mode,
4970 gen_binary (AND, mode, XEXP (op1, 0), op0),
4971 gen_binary (AND, mode, XEXP (op1, 1), op0)));
4973 /* Similarly, taking advantage of the fact that
4974 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
4976 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
4977 return apply_distributive_law
4978 (gen_binary (XOR, mode,
4979 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
4980 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 1))));
4982 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
4983 return apply_distributive_law
4984 (gen_binary (XOR, mode,
4985 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
4986 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 1))));
4990 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
4991 if (GET_CODE (op1) == CONST_INT
4992 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4993 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
4996 /* Convert (A & B) | A to A. */
4997 if (GET_CODE (op0) == AND
4998 && (rtx_equal_p (XEXP (op0, 0), op1)
4999 || rtx_equal_p (XEXP (op0, 1), op1))
5000 && ! side_effects_p (XEXP (op0, 0))
5001 && ! side_effects_p (XEXP (op0, 1)))
5004 /* If we have (ior (and A B) C), apply the distributive law and then
5005 the inverse distributive law to see if things simplify. */
5007 if (GET_CODE (op0) == AND)
5009 x = apply_distributive_law
5010 (gen_binary (AND, mode,
5011 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5012 gen_binary (IOR, mode, XEXP (op0, 1), op1)));
5014 if (GET_CODE (x) != IOR)
5018 if (GET_CODE (op1) == AND)
5020 x = apply_distributive_law
5021 (gen_binary (AND, mode,
5022 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5023 gen_binary (IOR, mode, XEXP (op1, 1), op0)));
5025 if (GET_CODE (x) != IOR)
5029 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5030 mode size to (rotate A CX). */
5032 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5033 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5034 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5035 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5036 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5037 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5038 == GET_MODE_BITSIZE (mode)))
5039 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5040 (GET_CODE (op0) == ASHIFT
5041 ? XEXP (op0, 1) : XEXP (op1, 1)));
5043 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5044 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5045 does not affect any of the bits in OP1, it can really be done
5046 as a PLUS and we can associate. We do this by seeing if OP1
5047 can be safely shifted left C bits. */
5048 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5049 && GET_CODE (XEXP (op0, 0)) == PLUS
5050 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5051 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5052 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5054 int count = INTVAL (XEXP (op0, 1));
5055 HOST_WIDE_INT mask = INTVAL (op1) << count;
5057 if (mask >> count == INTVAL (op1)
5058 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5060 SUBST (XEXP (XEXP (op0, 0), 1),
5061 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5068 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5069 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5072 int num_negated = 0;
5074 if (GET_CODE (op0) == NOT)
5075 num_negated++, op0 = XEXP (op0, 0);
5076 if (GET_CODE (op1) == NOT)
5077 num_negated++, op1 = XEXP (op1, 0);
5079 if (num_negated == 2)
5081 SUBST (XEXP (x, 0), op0);
5082 SUBST (XEXP (x, 1), op1);
5084 else if (num_negated == 1)
5085 return gen_unary (NOT, mode, mode, gen_binary (XOR, mode, op0, op1));
5088 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5089 correspond to a machine insn or result in further simplifications
5090 if B is a constant. */
5092 if (GET_CODE (op0) == AND
5093 && rtx_equal_p (XEXP (op0, 1), op1)
5094 && ! side_effects_p (op1))
5095 return gen_binary (AND, mode,
5096 gen_unary (NOT, mode, mode, XEXP (op0, 0)),
5099 else if (GET_CODE (op0) == AND
5100 && rtx_equal_p (XEXP (op0, 0), op1)
5101 && ! side_effects_p (op1))
5102 return gen_binary (AND, mode,
5103 gen_unary (NOT, mode, mode, XEXP (op0, 1)),
5106 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5107 comparison if STORE_FLAG_VALUE is 1. */
5108 if (STORE_FLAG_VALUE == 1
5109 && op1 == const1_rtx
5110 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5111 && reversible_comparison_p (op0))
5112 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5113 mode, XEXP (op0, 0), XEXP (op0, 1));
5115 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5116 is (lt foo (const_int 0)), so we can perform the above
5117 simplification if STORE_FLAG_VALUE is 1. */
5119 if (STORE_FLAG_VALUE == 1
5120 && op1 == const1_rtx
5121 && GET_CODE (op0) == LSHIFTRT
5122 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5123 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5124 return gen_rtx_combine (GE, mode, XEXP (op0, 0), const0_rtx);
5126 /* (xor (comparison foo bar) (const_int sign-bit))
5127 when STORE_FLAG_VALUE is the sign bit. */
5128 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5129 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5130 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5131 && op1 == const_true_rtx
5132 && GET_RTX_CLASS (GET_CODE (op0)) == '<'
5133 && reversible_comparison_p (op0))
5134 return gen_rtx_combine (reverse_condition (GET_CODE (op0)),
5135 mode, XEXP (op0, 0), XEXP (op0, 1));
5145 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5146 operations" because they can be replaced with two more basic operations.
5147 ZERO_EXTEND is also considered "compound" because it can be replaced with
5148 an AND operation, which is simpler, though only one operation.
5150 The function expand_compound_operation is called with an rtx expression
5151 and will convert it to the appropriate shifts and AND operations,
5152 simplifying at each stage.
5154 The function make_compound_operation is called to convert an expression
5155 consisting of shifts and ANDs into the equivalent compound expression.
5156 It is the inverse of this function, loosely speaking. */
5159 expand_compound_operation (x)
5167 switch (GET_CODE (x))
5172 /* We can't necessarily use a const_int for a multiword mode;
5173 it depends on implicitly extending the value.
5174 Since we don't know the right way to extend it,
5175 we can't tell whether the implicit way is right.
5177 Even for a mode that is no wider than a const_int,
5178 we can't win, because we need to sign extend one of its bits through
5179 the rest of it, and we don't know which bit. */
5180 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5183 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5184 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5185 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5186 reloaded. If not for that, MEM's would very rarely be safe.
5188 Reject MODEs bigger than a word, because we might not be able
5189 to reference a two-register group starting with an arbitrary register
5190 (and currently gen_lowpart might crash for a SUBREG). */
5192 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5195 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5196 /* If the inner object has VOIDmode (the only way this can happen
5197 is if it is a ASM_OPERANDS), we can't do anything since we don't
5198 know how much masking to do. */
5207 /* If the operand is a CLOBBER, just return it. */
5208 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5211 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5212 || GET_CODE (XEXP (x, 2)) != CONST_INT
5213 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5216 len = INTVAL (XEXP (x, 1));
5217 pos = INTVAL (XEXP (x, 2));
5219 /* If this goes outside the object being extracted, replace the object
5220 with a (use (mem ...)) construct that only combine understands
5221 and is used only for this purpose. */
5222 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5223 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5225 if (BITS_BIG_ENDIAN)
5226 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5234 /* We can optimize some special cases of ZERO_EXTEND. */
5235 if (GET_CODE (x) == ZERO_EXTEND)
5237 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5238 know that the last value didn't have any inappropriate bits
5240 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5241 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5242 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5243 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5244 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5245 return XEXP (XEXP (x, 0), 0);
5247 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5248 if (GET_CODE (XEXP (x, 0)) == SUBREG
5249 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5250 && subreg_lowpart_p (XEXP (x, 0))
5251 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5252 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5253 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5254 return SUBREG_REG (XEXP (x, 0));
5256 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5257 is a comparison and STORE_FLAG_VALUE permits. This is like
5258 the first case, but it works even when GET_MODE (x) is larger
5259 than HOST_WIDE_INT. */
5260 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5261 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5262 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x, 0), 0))) == '<'
5263 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5264 <= HOST_BITS_PER_WIDE_INT)
5265 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5266 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5267 return XEXP (XEXP (x, 0), 0);
5269 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5270 if (GET_CODE (XEXP (x, 0)) == SUBREG
5271 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5272 && subreg_lowpart_p (XEXP (x, 0))
5273 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == '<'
5274 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5275 <= HOST_BITS_PER_WIDE_INT)
5276 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5277 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5278 return SUBREG_REG (XEXP (x, 0));
5280 /* If sign extension is cheaper than zero extension, then use it
5281 if we know that no extraneous bits are set, and that the high
5283 if (flag_expensive_optimizations
5284 && ((GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5285 && ((nonzero_bits (XEXP (x, 0), GET_MODE (x))
5286 & ~ (((unsigned HOST_WIDE_INT)
5287 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5290 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5291 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5292 <= HOST_BITS_PER_WIDE_INT)
5293 && (((HOST_WIDE_INT) STORE_FLAG_VALUE
5294 & ~ (((unsigned HOST_WIDE_INT)
5295 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5299 rtx temp = gen_rtx_SIGN_EXTEND (GET_MODE (x), XEXP (x, 0));
5301 if (rtx_cost (temp, SET) < rtx_cost (x, SET))
5302 return expand_compound_operation (temp);
5306 /* If we reach here, we want to return a pair of shifts. The inner
5307 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5308 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5309 logical depending on the value of UNSIGNEDP.
5311 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5312 converted into an AND of a shift.
5314 We must check for the case where the left shift would have a negative
5315 count. This can happen in a case like (x >> 31) & 255 on machines
5316 that can't shift by a constant. On those machines, we would first
5317 combine the shift with the AND to produce a variable-position
5318 extraction. Then the constant of 31 would be substituted in to produce
5319 a such a position. */
5321 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5322 if (modewidth >= pos - len)
5323 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5325 simplify_shift_const (NULL_RTX, ASHIFT,
5328 modewidth - pos - len),
5331 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5332 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5333 simplify_shift_const (NULL_RTX, LSHIFTRT,
5336 ((HOST_WIDE_INT) 1 << len) - 1);
5338 /* Any other cases we can't handle. */
5342 /* If we couldn't do this for some reason, return the original
5344 if (GET_CODE (tem) == CLOBBER)
5350 /* X is a SET which contains an assignment of one object into
5351 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5352 or certain SUBREGS). If possible, convert it into a series of
5355 We half-heartedly support variable positions, but do not at all
5356 support variable lengths. */
5359 expand_field_assignment (x)
5363 rtx pos; /* Always counts from low bit. */
5366 enum machine_mode compute_mode;
5368 /* Loop until we find something we can't simplify. */
5371 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5372 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5374 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5375 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5376 pos = GEN_INT (BITS_PER_WORD * SUBREG_WORD (XEXP (SET_DEST (x), 0)));
5378 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5379 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5381 inner = XEXP (SET_DEST (x), 0);
5382 len = INTVAL (XEXP (SET_DEST (x), 1));
5383 pos = XEXP (SET_DEST (x), 2);
5385 /* If the position is constant and spans the width of INNER,
5386 surround INNER with a USE to indicate this. */
5387 if (GET_CODE (pos) == CONST_INT
5388 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5389 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5391 if (BITS_BIG_ENDIAN)
5393 if (GET_CODE (pos) == CONST_INT)
5394 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5396 else if (GET_CODE (pos) == MINUS
5397 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5398 && (INTVAL (XEXP (pos, 1))
5399 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5400 /* If position is ADJUST - X, new position is X. */
5401 pos = XEXP (pos, 0);
5403 pos = gen_binary (MINUS, GET_MODE (pos),
5404 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5410 /* A SUBREG between two modes that occupy the same numbers of words
5411 can be done by moving the SUBREG to the source. */
5412 else if (GET_CODE (SET_DEST (x)) == SUBREG
5413 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5414 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5415 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5416 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5418 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5419 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
5426 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5427 inner = SUBREG_REG (inner);
5429 compute_mode = GET_MODE (inner);
5431 /* Don't attempt bitwise arithmetic on non-integral modes. */
5432 if (! INTEGRAL_MODE_P (compute_mode))
5434 enum machine_mode imode;
5436 /* Something is probably seriously wrong if this matches. */
5437 if (! FLOAT_MODE_P (compute_mode))
5440 /* Try to find an integral mode to pun with. */
5441 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5442 if (imode == BLKmode)
5445 compute_mode = imode;
5446 inner = gen_lowpart_for_combine (imode, inner);
5449 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5450 if (len < HOST_BITS_PER_WIDE_INT)
5451 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5455 /* Now compute the equivalent expression. Make a copy of INNER
5456 for the SET_DEST in case it is a MEM into which we will substitute;
5457 we don't want shared RTL in that case. */
5458 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5459 gen_binary (IOR, compute_mode,
5460 gen_binary (AND, compute_mode,
5461 gen_unary (NOT, compute_mode,
5467 gen_binary (ASHIFT, compute_mode,
5468 gen_binary (AND, compute_mode,
5469 gen_lowpart_for_combine
5479 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5480 it is an RTX that represents a variable starting position; otherwise,
5481 POS is the (constant) starting bit position (counted from the LSB).
5483 INNER may be a USE. This will occur when we started with a bitfield
5484 that went outside the boundary of the object in memory, which is
5485 allowed on most machines. To isolate this case, we produce a USE
5486 whose mode is wide enough and surround the MEM with it. The only
5487 code that understands the USE is this routine. If it is not removed,
5488 it will cause the resulting insn not to match.
5490 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5493 IN_DEST is non-zero if this is a reference in the destination of a
5494 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5495 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5498 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5499 ZERO_EXTRACT should be built even for bits starting at bit 0.
5501 MODE is the desired mode of the result (if IN_DEST == 0).
5503 The result is an RTX for the extraction or NULL_RTX if the target
5507 make_extraction (mode, inner, pos, pos_rtx, len,
5508 unsignedp, in_dest, in_compare)
5509 enum machine_mode mode;
5515 int in_dest, in_compare;
5517 /* This mode describes the size of the storage area
5518 to fetch the overall value from. Within that, we
5519 ignore the POS lowest bits, etc. */
5520 enum machine_mode is_mode = GET_MODE (inner);
5521 enum machine_mode inner_mode;
5522 enum machine_mode wanted_inner_mode = byte_mode;
5523 enum machine_mode wanted_inner_reg_mode = word_mode;
5524 enum machine_mode pos_mode = word_mode;
5525 enum machine_mode extraction_mode = word_mode;
5526 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5529 rtx orig_pos_rtx = pos_rtx;
5532 /* Get some information about INNER and get the innermost object. */
5533 if (GET_CODE (inner) == USE)
5534 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5535 /* We don't need to adjust the position because we set up the USE
5536 to pretend that it was a full-word object. */
5537 spans_byte = 1, inner = XEXP (inner, 0);
5538 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5540 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5541 consider just the QI as the memory to extract from.
5542 The subreg adds or removes high bits; its mode is
5543 irrelevant to the meaning of this extraction,
5544 since POS and LEN count from the lsb. */
5545 if (GET_CODE (SUBREG_REG (inner)) == MEM)
5546 is_mode = GET_MODE (SUBREG_REG (inner));
5547 inner = SUBREG_REG (inner);
5550 inner_mode = GET_MODE (inner);
5552 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5553 pos = INTVAL (pos_rtx), pos_rtx = 0;
5555 /* See if this can be done without an extraction. We never can if the
5556 width of the field is not the same as that of some integer mode. For
5557 registers, we can only avoid the extraction if the position is at the
5558 low-order bit and this is either not in the destination or we have the
5559 appropriate STRICT_LOW_PART operation available.
5561 For MEM, we can avoid an extract if the field starts on an appropriate
5562 boundary and we can change the mode of the memory reference. However,
5563 we cannot directly access the MEM if we have a USE and the underlying
5564 MEM is not TMODE. This combination means that MEM was being used in a
5565 context where bits outside its mode were being referenced; that is only
5566 valid in bit-field insns. */
5568 if (tmode != BLKmode
5569 && ! (spans_byte && inner_mode != tmode)
5570 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5571 && GET_CODE (inner) != MEM
5573 || (GET_CODE (inner) == REG
5574 && (movstrict_optab->handlers[(int) tmode].insn_code
5575 != CODE_FOR_nothing))))
5576 || (GET_CODE (inner) == MEM && pos_rtx == 0
5578 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5579 : BITS_PER_UNIT)) == 0
5580 /* We can't do this if we are widening INNER_MODE (it
5581 may not be aligned, for one thing). */
5582 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5583 && (inner_mode == tmode
5584 || (! mode_dependent_address_p (XEXP (inner, 0))
5585 && ! MEM_VOLATILE_P (inner))))))
5587 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5588 field. If the original and current mode are the same, we need not
5589 adjust the offset. Otherwise, we do if bytes big endian.
5591 If INNER is not a MEM, get a piece consisting of just the field
5592 of interest (in this case POS % BITS_PER_WORD must be 0). */
5594 if (GET_CODE (inner) == MEM)
5597 /* POS counts from lsb, but make OFFSET count in memory order. */
5598 if (BYTES_BIG_ENDIAN)
5599 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5601 offset = pos / BITS_PER_UNIT;
5603 new = gen_rtx_MEM (tmode, plus_constant (XEXP (inner, 0), offset));
5604 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
5605 MEM_COPY_ATTRIBUTES (new, inner);
5607 else if (GET_CODE (inner) == REG)
5609 /* We can't call gen_lowpart_for_combine here since we always want
5610 a SUBREG and it would sometimes return a new hard register. */
5611 if (tmode != inner_mode)
5612 new = gen_rtx_SUBREG (tmode, inner,
5614 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD
5615 ? (((GET_MODE_SIZE (inner_mode)
5616 - GET_MODE_SIZE (tmode))
5618 - pos / BITS_PER_WORD)
5619 : pos / BITS_PER_WORD));
5624 new = force_to_mode (inner, tmode,
5625 len >= HOST_BITS_PER_WIDE_INT
5626 ? GET_MODE_MASK (tmode)
5627 : ((HOST_WIDE_INT) 1 << len) - 1,
5630 /* If this extraction is going into the destination of a SET,
5631 make a STRICT_LOW_PART unless we made a MEM. */
5634 return (GET_CODE (new) == MEM ? new
5635 : (GET_CODE (new) != SUBREG
5636 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5637 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new)));
5639 /* Otherwise, sign- or zero-extend unless we already are in the
5642 return (mode == tmode ? new
5643 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5647 /* Unless this is a COMPARE or we have a funny memory reference,
5648 don't do anything with zero-extending field extracts starting at
5649 the low-order bit since they are simple AND operations. */
5650 if (pos_rtx == 0 && pos == 0 && ! in_dest
5651 && ! in_compare && ! spans_byte && unsignedp)
5654 /* Unless we are allowed to span bytes, reject this if we would be
5655 spanning bytes or if the position is not a constant and the length
5656 is not 1. In all other cases, we would only be going outside
5657 out object in cases when an original shift would have been
5660 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5661 || (pos_rtx != 0 && len != 1)))
5664 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5665 and the mode for the result. */
5669 wanted_inner_reg_mode
5670 = (insn_operand_mode[(int) CODE_FOR_insv][0] == VOIDmode
5672 : insn_operand_mode[(int) CODE_FOR_insv][0]);
5673 pos_mode = (insn_operand_mode[(int) CODE_FOR_insv][2] == VOIDmode
5674 ? word_mode : insn_operand_mode[(int) CODE_FOR_insv][2]);
5675 extraction_mode = (insn_operand_mode[(int) CODE_FOR_insv][3] == VOIDmode
5677 : insn_operand_mode[(int) CODE_FOR_insv][3]);
5682 if (! in_dest && unsignedp)
5684 wanted_inner_reg_mode
5685 = (insn_operand_mode[(int) CODE_FOR_extzv][1] == VOIDmode
5687 : insn_operand_mode[(int) CODE_FOR_extzv][1]);
5688 pos_mode = (insn_operand_mode[(int) CODE_FOR_extzv][3] == VOIDmode
5689 ? word_mode : insn_operand_mode[(int) CODE_FOR_extzv][3]);
5690 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extzv][0] == VOIDmode
5692 : insn_operand_mode[(int) CODE_FOR_extzv][0]);
5697 if (! in_dest && ! unsignedp)
5699 wanted_inner_reg_mode
5700 = (insn_operand_mode[(int) CODE_FOR_extv][1] == VOIDmode
5702 : insn_operand_mode[(int) CODE_FOR_extv][1]);
5703 pos_mode = (insn_operand_mode[(int) CODE_FOR_extv][3] == VOIDmode
5704 ? word_mode : insn_operand_mode[(int) CODE_FOR_extv][3]);
5705 extraction_mode = (insn_operand_mode[(int) CODE_FOR_extv][0] == VOIDmode
5707 : insn_operand_mode[(int) CODE_FOR_extv][0]);
5711 /* Never narrow an object, since that might not be safe. */
5713 if (mode != VOIDmode
5714 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5715 extraction_mode = mode;
5717 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5718 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5719 pos_mode = GET_MODE (pos_rtx);
5721 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5722 if we have to change the mode of memory and cannot, the desired mode is
5724 if (GET_CODE (inner) != MEM)
5725 wanted_inner_mode = wanted_inner_reg_mode;
5726 else if (inner_mode != wanted_inner_mode
5727 && (mode_dependent_address_p (XEXP (inner, 0))
5728 || MEM_VOLATILE_P (inner)))
5729 wanted_inner_mode = extraction_mode;
5733 if (BITS_BIG_ENDIAN)
5735 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5736 BITS_BIG_ENDIAN style. If position is constant, compute new
5737 position. Otherwise, build subtraction.
5738 Note that POS is relative to the mode of the original argument.
5739 If it's a MEM we need to recompute POS relative to that.
5740 However, if we're extracting from (or inserting into) a register,
5741 we want to recompute POS relative to wanted_inner_mode. */
5742 int width = (GET_CODE (inner) == MEM
5743 ? GET_MODE_BITSIZE (is_mode)
5744 : GET_MODE_BITSIZE (wanted_inner_mode));
5747 pos = width - len - pos;
5750 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
5751 GEN_INT (width - len), pos_rtx);
5752 /* POS may be less than 0 now, but we check for that below.
5753 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
5756 /* If INNER has a wider mode, make it smaller. If this is a constant
5757 extract, try to adjust the byte to point to the byte containing
5759 if (wanted_inner_mode != VOIDmode
5760 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5761 && ((GET_CODE (inner) == MEM
5762 && (inner_mode == wanted_inner_mode
5763 || (! mode_dependent_address_p (XEXP (inner, 0))
5764 && ! MEM_VOLATILE_P (inner))))))
5768 /* The computations below will be correct if the machine is big
5769 endian in both bits and bytes or little endian in bits and bytes.
5770 If it is mixed, we must adjust. */
5772 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5773 adjust OFFSET to compensate. */
5774 if (BYTES_BIG_ENDIAN
5776 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
5777 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
5779 /* If this is a constant position, we can move to the desired byte. */
5782 offset += pos / BITS_PER_UNIT;
5783 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
5786 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
5788 && is_mode != wanted_inner_mode)
5789 offset = (GET_MODE_SIZE (is_mode)
5790 - GET_MODE_SIZE (wanted_inner_mode) - offset);
5792 if (offset != 0 || inner_mode != wanted_inner_mode)
5794 rtx newmem = gen_rtx_MEM (wanted_inner_mode,
5795 plus_constant (XEXP (inner, 0), offset));
5796 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
5797 MEM_COPY_ATTRIBUTES (newmem, inner);
5802 /* If INNER is not memory, we can always get it into the proper mode. If we
5803 are changing its mode, POS must be a constant and smaller than the size
5805 else if (GET_CODE (inner) != MEM)
5807 if (GET_MODE (inner) != wanted_inner_mode
5809 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
5812 inner = force_to_mode (inner, wanted_inner_mode,
5814 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
5815 ? GET_MODE_MASK (wanted_inner_mode)
5816 : (((HOST_WIDE_INT) 1 << len) - 1) << orig_pos,
5820 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
5821 have to zero extend. Otherwise, we can just use a SUBREG. */
5823 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
5824 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
5825 else if (pos_rtx != 0
5826 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5827 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
5829 /* Make POS_RTX unless we already have it and it is correct. If we don't
5830 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
5832 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
5833 pos_rtx = orig_pos_rtx;
5835 else if (pos_rtx == 0)
5836 pos_rtx = GEN_INT (pos);
5838 /* Make the required operation. See if we can use existing rtx. */
5839 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
5840 extraction_mode, inner, GEN_INT (len), pos_rtx);
5842 new = gen_lowpart_for_combine (mode, new);
5847 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
5848 with any other operations in X. Return X without that shift if so. */
5851 extract_left_shift (x, count)
5855 enum rtx_code code = GET_CODE (x);
5856 enum machine_mode mode = GET_MODE (x);
5862 /* This is the shift itself. If it is wide enough, we will return
5863 either the value being shifted if the shift count is equal to
5864 COUNT or a shift for the difference. */
5865 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5866 && INTVAL (XEXP (x, 1)) >= count)
5867 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
5868 INTVAL (XEXP (x, 1)) - count);
5872 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5873 return gen_unary (code, mode, mode, tem);
5877 case PLUS: case IOR: case XOR: case AND:
5878 /* If we can safely shift this constant and we find the inner shift,
5879 make a new operation. */
5880 if (GET_CODE (XEXP (x,1)) == CONST_INT
5881 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
5882 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
5883 return gen_binary (code, mode, tem,
5884 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
5895 /* Look at the expression rooted at X. Look for expressions
5896 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
5897 Form these expressions.
5899 Return the new rtx, usually just X.
5901 Also, for machines like the Vax that don't have logical shift insns,
5902 try to convert logical to arithmetic shift operations in cases where
5903 they are equivalent. This undoes the canonicalizations to logical
5904 shifts done elsewhere.
5906 We try, as much as possible, to re-use rtl expressions to save memory.
5908 IN_CODE says what kind of expression we are processing. Normally, it is
5909 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
5910 being kludges), it is MEM. When processing the arguments of a comparison
5911 or a COMPARE against zero, it is COMPARE. */
5914 make_compound_operation (x, in_code)
5916 enum rtx_code in_code;
5918 enum rtx_code code = GET_CODE (x);
5919 enum machine_mode mode = GET_MODE (x);
5920 int mode_width = GET_MODE_BITSIZE (mode);
5922 enum rtx_code next_code;
5928 /* Select the code to be used in recursive calls. Once we are inside an
5929 address, we stay there. If we have a comparison, set to COMPARE,
5930 but once inside, go back to our default of SET. */
5932 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
5933 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
5934 && XEXP (x, 1) == const0_rtx) ? COMPARE
5935 : in_code == COMPARE ? SET : in_code);
5937 /* Process depending on the code of this operation. If NEW is set
5938 non-zero, it will be returned. */
5943 /* Convert shifts by constants into multiplications if inside
5945 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
5946 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5947 && INTVAL (XEXP (x, 1)) >= 0)
5949 new = make_compound_operation (XEXP (x, 0), next_code);
5950 new = gen_rtx_combine (MULT, mode, new,
5951 GEN_INT ((HOST_WIDE_INT) 1
5952 << INTVAL (XEXP (x, 1))));
5957 /* If the second operand is not a constant, we can't do anything
5959 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
5962 /* If the constant is a power of two minus one and the first operand
5963 is a logical right shift, make an extraction. */
5964 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
5965 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5967 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
5968 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
5969 0, in_code == COMPARE);
5972 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
5973 else if (GET_CODE (XEXP (x, 0)) == SUBREG
5974 && subreg_lowpart_p (XEXP (x, 0))
5975 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
5976 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5978 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
5980 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
5981 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
5982 0, in_code == COMPARE);
5984 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
5985 else if ((GET_CODE (XEXP (x, 0)) == XOR
5986 || GET_CODE (XEXP (x, 0)) == IOR)
5987 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
5988 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
5989 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
5991 /* Apply the distributive law, and then try to make extractions. */
5992 new = gen_rtx_combine (GET_CODE (XEXP (x, 0)), mode,
5993 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
5995 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
5997 new = make_compound_operation (new, in_code);
6000 /* If we are have (and (rotate X C) M) and C is larger than the number
6001 of bits in M, this is an extraction. */
6003 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6004 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6005 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6006 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6008 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6009 new = make_extraction (mode, new,
6010 (GET_MODE_BITSIZE (mode)
6011 - INTVAL (XEXP (XEXP (x, 0), 1))),
6012 NULL_RTX, i, 1, 0, in_code == COMPARE);
6015 /* On machines without logical shifts, if the operand of the AND is
6016 a logical shift and our mask turns off all the propagated sign
6017 bits, we can replace the logical shift with an arithmetic shift. */
6018 else if (ashr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6019 && (lshr_optab->handlers[(int) mode].insn_code
6020 == CODE_FOR_nothing)
6021 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
6022 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6023 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6024 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6025 && mode_width <= HOST_BITS_PER_WIDE_INT)
6027 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6029 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6030 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6032 gen_rtx_combine (ASHIFTRT, mode,
6033 make_compound_operation (XEXP (XEXP (x, 0), 0),
6035 XEXP (XEXP (x, 0), 1)));
6038 /* If the constant is one less than a power of two, this might be
6039 representable by an extraction even if no shift is present.
6040 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6041 we are in a COMPARE. */
6042 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6043 new = make_extraction (mode,
6044 make_compound_operation (XEXP (x, 0),
6046 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6048 /* If we are in a comparison and this is an AND with a power of two,
6049 convert this into the appropriate bit extract. */
6050 else if (in_code == COMPARE
6051 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6052 new = make_extraction (mode,
6053 make_compound_operation (XEXP (x, 0),
6055 i, NULL_RTX, 1, 1, 0, 1);
6060 /* If the sign bit is known to be zero, replace this with an
6061 arithmetic shift. */
6062 if (ashr_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing
6063 && lshr_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing
6064 && mode_width <= HOST_BITS_PER_WIDE_INT
6065 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6067 new = gen_rtx_combine (ASHIFTRT, mode,
6068 make_compound_operation (XEXP (x, 0),
6074 /* ... fall through ... */
6080 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6081 this is a SIGN_EXTRACT. */
6082 if (GET_CODE (rhs) == CONST_INT
6083 && GET_CODE (lhs) == ASHIFT
6084 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6085 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6087 new = make_compound_operation (XEXP (lhs, 0), next_code);
6088 new = make_extraction (mode, new,
6089 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6090 NULL_RTX, mode_width - INTVAL (rhs),
6091 code == LSHIFTRT, 0, in_code == COMPARE);
6094 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6095 If so, try to merge the shifts into a SIGN_EXTEND. We could
6096 also do this for some cases of SIGN_EXTRACT, but it doesn't
6097 seem worth the effort; the case checked for occurs on Alpha. */
6099 if (GET_RTX_CLASS (GET_CODE (lhs)) != 'o'
6100 && ! (GET_CODE (lhs) == SUBREG
6101 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs))) == 'o'))
6102 && GET_CODE (rhs) == CONST_INT
6103 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6104 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6105 new = make_extraction (mode, make_compound_operation (new, next_code),
6106 0, NULL_RTX, mode_width - INTVAL (rhs),
6107 code == LSHIFTRT, 0, in_code == COMPARE);
6112 /* Call ourselves recursively on the inner expression. If we are
6113 narrowing the object and it has a different RTL code from
6114 what it originally did, do this SUBREG as a force_to_mode. */
6116 tem = make_compound_operation (SUBREG_REG (x), in_code);
6117 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6118 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6119 && subreg_lowpart_p (x))
6121 rtx newer = force_to_mode (tem, mode,
6122 GET_MODE_MASK (mode), NULL_RTX, 0);
6124 /* If we have something other than a SUBREG, we might have
6125 done an expansion, so rerun outselves. */
6126 if (GET_CODE (newer) != SUBREG)
6127 newer = make_compound_operation (newer, in_code);
6132 /* If this is a paradoxical subreg, and the new code is a sign or
6133 zero extension, omit the subreg and widen the extension. If it
6134 is a regular subreg, we can still get rid of the subreg by not
6135 widening so much, or in fact removing the extension entirely. */
6136 if ((GET_CODE (tem) == SIGN_EXTEND
6137 || GET_CODE (tem) == ZERO_EXTEND)
6138 && subreg_lowpart_p (x))
6140 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6141 || (GET_MODE_SIZE (mode) >
6142 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6143 tem = gen_rtx_combine (GET_CODE (tem), mode, XEXP (tem, 0));
6145 tem = gen_lowpart_for_combine (mode, XEXP (tem, 0));
6156 x = gen_lowpart_for_combine (mode, new);
6157 code = GET_CODE (x);
6160 /* Now recursively process each operand of this operation. */
6161 fmt = GET_RTX_FORMAT (code);
6162 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6165 new = make_compound_operation (XEXP (x, i), next_code);
6166 SUBST (XEXP (x, i), new);
6172 /* Given M see if it is a value that would select a field of bits
6173 within an item, but not the entire word. Return -1 if not.
6174 Otherwise, return the starting position of the field, where 0 is the
6177 *PLEN is set to the length of the field. */
6180 get_pos_from_mask (m, plen)
6181 unsigned HOST_WIDE_INT m;
6184 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6185 int pos = exact_log2 (m & - m);
6190 /* Now shift off the low-order zero bits and see if we have a power of
6192 *plen = exact_log2 ((m >> pos) + 1);
6200 /* See if X can be simplified knowing that we will only refer to it in
6201 MODE and will only refer to those bits that are nonzero in MASK.
6202 If other bits are being computed or if masking operations are done
6203 that select a superset of the bits in MASK, they can sometimes be
6206 Return a possibly simplified expression, but always convert X to
6207 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6209 Also, if REG is non-zero and X is a register equal in value to REG,
6212 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6213 are all off in X. This is used when X will be complemented, by either
6214 NOT, NEG, or XOR. */
6217 force_to_mode (x, mode, mask, reg, just_select)
6219 enum machine_mode mode;
6220 unsigned HOST_WIDE_INT mask;
6224 enum rtx_code code = GET_CODE (x);
6225 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6226 enum machine_mode op_mode;
6227 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6230 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6231 code below will do the wrong thing since the mode of such an
6232 expression is VOIDmode.
6234 Also do nothing if X is a CLOBBER; this can happen if X was
6235 the return value from a call to gen_lowpart_for_combine. */
6236 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6239 /* We want to perform the operation is its present mode unless we know
6240 that the operation is valid in MODE, in which case we do the operation
6242 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6243 && code_to_optab[(int) code] != 0
6244 && (code_to_optab[(int) code]->handlers[(int) mode].insn_code
6245 != CODE_FOR_nothing))
6246 ? mode : GET_MODE (x));
6248 /* It is not valid to do a right-shift in a narrower mode
6249 than the one it came in with. */
6250 if ((code == LSHIFTRT || code == ASHIFTRT)
6251 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6252 op_mode = GET_MODE (x);
6254 /* Truncate MASK to fit OP_MODE. */
6256 mask &= GET_MODE_MASK (op_mode);
6258 /* When we have an arithmetic operation, or a shift whose count we
6259 do not know, we need to assume that all bit the up to the highest-order
6260 bit in MASK will be needed. This is how we form such a mask. */
6262 fuller_mask = (GET_MODE_BITSIZE (op_mode) >= HOST_BITS_PER_WIDE_INT
6263 ? GET_MODE_MASK (op_mode)
6264 : ((HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1)) - 1);
6266 fuller_mask = ~ (HOST_WIDE_INT) 0;
6268 /* Determine what bits of X are guaranteed to be (non)zero. */
6269 nonzero = nonzero_bits (x, mode);
6271 /* If none of the bits in X are needed, return a zero. */
6272 if (! just_select && (nonzero & mask) == 0)
6275 /* If X is a CONST_INT, return a new one. Do this here since the
6276 test below will fail. */
6277 if (GET_CODE (x) == CONST_INT)
6279 HOST_WIDE_INT cval = INTVAL (x) & mask;
6280 int width = GET_MODE_BITSIZE (mode);
6282 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6283 number, sign extend it. */
6284 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6285 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6286 cval |= (HOST_WIDE_INT) -1 << width;
6288 return GEN_INT (cval);
6291 /* If X is narrower than MODE and we want all the bits in X's mode, just
6292 get X in the proper mode. */
6293 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6294 && (GET_MODE_MASK (GET_MODE (x)) & ~ mask) == 0)
6295 return gen_lowpart_for_combine (mode, x);
6297 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6298 MASK are already known to be zero in X, we need not do anything. */
6299 if (GET_MODE (x) == mode && code != SUBREG && (~ mask & nonzero) == 0)
6305 /* If X is a (clobber (const_int)), return it since we know we are
6306 generating something that won't match. */
6310 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6311 spanned the boundary of the MEM. If we are now masking so it is
6312 within that boundary, we don't need the USE any more. */
6313 if (! BITS_BIG_ENDIAN
6314 && (mask & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6315 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6322 x = expand_compound_operation (x);
6323 if (GET_CODE (x) != code)
6324 return force_to_mode (x, mode, mask, reg, next_select);
6328 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6329 || rtx_equal_p (reg, get_last_value (x))))
6334 if (subreg_lowpart_p (x)
6335 /* We can ignore the effect of this SUBREG if it narrows the mode or
6336 if the constant masks to zero all the bits the mode doesn't
6338 && ((GET_MODE_SIZE (GET_MODE (x))
6339 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6341 & GET_MODE_MASK (GET_MODE (x))
6342 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6343 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6347 /* If this is an AND with a constant, convert it into an AND
6348 whose constant is the AND of that constant with MASK. If it
6349 remains an AND of MASK, delete it since it is redundant. */
6351 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6353 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6354 mask & INTVAL (XEXP (x, 1)));
6356 /* If X is still an AND, see if it is an AND with a mask that
6357 is just some low-order bits. If so, and it is MASK, we don't
6360 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6361 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == mask)
6364 /* If it remains an AND, try making another AND with the bits
6365 in the mode mask that aren't in MASK turned on. If the
6366 constant in the AND is wide enough, this might make a
6367 cheaper constant. */
6369 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6370 && GET_MODE_MASK (GET_MODE (x)) != mask
6371 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6373 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6374 | (GET_MODE_MASK (GET_MODE (x)) & ~ mask));
6375 int width = GET_MODE_BITSIZE (GET_MODE (x));
6378 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6379 number, sign extend it. */
6380 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6381 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6382 cval |= (HOST_WIDE_INT) -1 << width;
6384 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6385 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6395 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6396 low-order bits (as in an alignment operation) and FOO is already
6397 aligned to that boundary, mask C1 to that boundary as well.
6398 This may eliminate that PLUS and, later, the AND. */
6401 int width = GET_MODE_BITSIZE (mode);
6402 unsigned HOST_WIDE_INT smask = mask;
6404 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6405 number, sign extend it. */
6407 if (width < HOST_BITS_PER_WIDE_INT
6408 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6409 smask |= (HOST_WIDE_INT) -1 << width;
6411 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6412 && exact_log2 (- smask) >= 0)
6416 && (XEXP (x, 0) == stack_pointer_rtx
6417 || XEXP (x, 0) == frame_pointer_rtx))
6419 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
6420 unsigned HOST_WIDE_INT sp_mask = GET_MODE_MASK (mode);
6422 sp_mask &= ~ (sp_alignment - 1);
6423 if ((sp_mask & ~ smask) == 0
6424 && ((INTVAL (XEXP (x, 1)) - STACK_BIAS) & ~ smask) != 0)
6425 return force_to_mode (plus_constant (XEXP (x, 0),
6426 ((INTVAL (XEXP (x, 1)) -
6427 STACK_BIAS) & smask)
6429 mode, smask, reg, next_select);
6432 if ((nonzero_bits (XEXP (x, 0), mode) & ~ smask) == 0
6433 && (INTVAL (XEXP (x, 1)) & ~ smask) != 0)
6434 return force_to_mode (plus_constant (XEXP (x, 0),
6435 (INTVAL (XEXP (x, 1))
6437 mode, smask, reg, next_select);
6441 /* ... fall through ... */
6445 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6446 most significant bit in MASK since carries from those bits will
6447 affect the bits we are interested in. */
6453 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6454 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6455 operation which may be a bitfield extraction. Ensure that the
6456 constant we form is not wider than the mode of X. */
6458 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6459 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6460 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6461 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6462 && GET_CODE (XEXP (x, 1)) == CONST_INT
6463 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6464 + floor_log2 (INTVAL (XEXP (x, 1))))
6465 < GET_MODE_BITSIZE (GET_MODE (x)))
6466 && (INTVAL (XEXP (x, 1))
6467 & ~ nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6469 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6470 << INTVAL (XEXP (XEXP (x, 0), 1)));
6471 temp = gen_binary (GET_CODE (x), GET_MODE (x),
6472 XEXP (XEXP (x, 0), 0), temp);
6473 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
6474 XEXP (XEXP (x, 0), 1));
6475 return force_to_mode (x, mode, mask, reg, next_select);
6479 /* For most binary operations, just propagate into the operation and
6480 change the mode if we have an operation of that mode. */
6482 op0 = gen_lowpart_for_combine (op_mode,
6483 force_to_mode (XEXP (x, 0), mode, mask,
6485 op1 = gen_lowpart_for_combine (op_mode,
6486 force_to_mode (XEXP (x, 1), mode, mask,
6489 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6490 MASK since OP1 might have been sign-extended but we never want
6491 to turn on extra bits, since combine might have previously relied
6492 on them being off. */
6493 if (GET_CODE (op1) == CONST_INT && (code == IOR || code == XOR)
6494 && (INTVAL (op1) & mask) != 0)
6495 op1 = GEN_INT (INTVAL (op1) & mask);
6497 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6498 x = gen_binary (code, op_mode, op0, op1);
6502 /* For left shifts, do the same, but just for the first operand.
6503 However, we cannot do anything with shifts where we cannot
6504 guarantee that the counts are smaller than the size of the mode
6505 because such a count will have a different meaning in a
6508 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6509 && INTVAL (XEXP (x, 1)) >= 0
6510 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6511 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6512 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6513 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6516 /* If the shift count is a constant and we can do arithmetic in
6517 the mode of the shift, refine which bits we need. Otherwise, use the
6518 conservative form of the mask. */
6519 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6520 && INTVAL (XEXP (x, 1)) >= 0
6521 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6522 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6523 mask >>= INTVAL (XEXP (x, 1));
6527 op0 = gen_lowpart_for_combine (op_mode,
6528 force_to_mode (XEXP (x, 0), op_mode,
6529 mask, reg, next_select));
6531 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6532 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
6536 /* Here we can only do something if the shift count is a constant,
6537 this shift constant is valid for the host, and we can do arithmetic
6540 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6541 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6542 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6544 rtx inner = XEXP (x, 0);
6546 /* Select the mask of the bits we need for the shift operand. */
6547 mask <<= INTVAL (XEXP (x, 1));
6549 /* We can only change the mode of the shift if we can do arithmetic
6550 in the mode of the shift and MASK is no wider than the width of
6552 if (GET_MODE_BITSIZE (op_mode) > HOST_BITS_PER_WIDE_INT
6553 || (mask & ~ GET_MODE_MASK (op_mode)) != 0)
6554 op_mode = GET_MODE (x);
6556 inner = force_to_mode (inner, op_mode, mask, reg, next_select);
6558 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6559 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6562 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6563 shift and AND produces only copies of the sign bit (C2 is one less
6564 than a power of two), we can do this with just a shift. */
6566 if (GET_CODE (x) == LSHIFTRT
6567 && GET_CODE (XEXP (x, 1)) == CONST_INT
6568 && ((INTVAL (XEXP (x, 1))
6569 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6570 >= GET_MODE_BITSIZE (GET_MODE (x)))
6571 && exact_log2 (mask + 1) >= 0
6572 && (num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6573 >= exact_log2 (mask + 1)))
6574 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6575 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6576 - exact_log2 (mask + 1)));
6581 /* If we are just looking for the sign bit, we don't need this shift at
6582 all, even if it has a variable count. */
6583 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6584 && (mask == ((unsigned HOST_WIDE_INT) 1
6585 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6586 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6588 /* If this is a shift by a constant, get a mask that contains those bits
6589 that are not copies of the sign bit. We then have two cases: If
6590 MASK only includes those bits, this can be a logical shift, which may
6591 allow simplifications. If MASK is a single-bit field not within
6592 those bits, we are requesting a copy of the sign bit and hence can
6593 shift the sign bit to the appropriate location. */
6595 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6596 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6600 /* If the considered data is wider then HOST_WIDE_INT, we can't
6601 represent a mask for all its bits in a single scalar.
6602 But we only care about the lower bits, so calculate these. */
6604 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6606 nonzero = ~ (HOST_WIDE_INT) 0;
6608 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6609 is the number of bits a full-width mask would have set.
6610 We need only shift if these are fewer than nonzero can
6611 hold. If not, we must keep all bits set in nonzero. */
6613 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6614 < HOST_BITS_PER_WIDE_INT)
6615 nonzero >>= INTVAL (XEXP (x, 1))
6616 + HOST_BITS_PER_WIDE_INT
6617 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6621 nonzero = GET_MODE_MASK (GET_MODE (x));
6622 nonzero >>= INTVAL (XEXP (x, 1));
6625 if ((mask & ~ nonzero) == 0
6626 || (i = exact_log2 (mask)) >= 0)
6628 x = simplify_shift_const
6629 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6630 i < 0 ? INTVAL (XEXP (x, 1))
6631 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6633 if (GET_CODE (x) != ASHIFTRT)
6634 return force_to_mode (x, mode, mask, reg, next_select);
6638 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6639 even if the shift count isn't a constant. */
6641 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
6645 /* If this is a zero- or sign-extension operation that just affects bits
6646 we don't care about, remove it. Be sure the call above returned
6647 something that is still a shift. */
6649 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6650 && GET_CODE (XEXP (x, 1)) == CONST_INT
6651 && INTVAL (XEXP (x, 1)) >= 0
6652 && (INTVAL (XEXP (x, 1))
6653 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6654 && GET_CODE (XEXP (x, 0)) == ASHIFT
6655 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6656 && INTVAL (XEXP (XEXP (x, 0), 1)) == INTVAL (XEXP (x, 1)))
6657 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6664 /* If the shift count is constant and we can do computations
6665 in the mode of X, compute where the bits we care about are.
6666 Otherwise, we can't do anything. Don't change the mode of
6667 the shift or propagate MODE into the shift, though. */
6668 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6669 && INTVAL (XEXP (x, 1)) >= 0)
6671 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6672 GET_MODE (x), GEN_INT (mask),
6674 if (temp && GET_CODE(temp) == CONST_INT)
6676 force_to_mode (XEXP (x, 0), GET_MODE (x),
6677 INTVAL (temp), reg, next_select));
6682 /* If we just want the low-order bit, the NEG isn't needed since it
6683 won't change the low-order bit. */
6685 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
6687 /* We need any bits less significant than the most significant bit in
6688 MASK since carries from those bits will affect the bits we are
6694 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
6695 same as the XOR case above. Ensure that the constant we form is not
6696 wider than the mode of X. */
6698 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6699 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6700 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6701 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
6702 < GET_MODE_BITSIZE (GET_MODE (x)))
6703 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
6705 temp = GEN_INT (mask << INTVAL (XEXP (XEXP (x, 0), 1)));
6706 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
6707 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
6709 return force_to_mode (x, mode, mask, reg, next_select);
6712 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
6713 use the full mask inside the NOT. */
6717 op0 = gen_lowpart_for_combine (op_mode,
6718 force_to_mode (XEXP (x, 0), mode, mask,
6720 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6721 x = gen_unary (code, op_mode, op_mode, op0);
6725 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
6726 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
6727 which is equal to STORE_FLAG_VALUE. */
6728 if ((mask & ~ STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
6729 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
6730 && nonzero_bits (XEXP (x, 0), mode) == STORE_FLAG_VALUE)
6731 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6736 /* We have no way of knowing if the IF_THEN_ELSE can itself be
6737 written in a narrower mode. We play it safe and do not do so. */
6740 gen_lowpart_for_combine (GET_MODE (x),
6741 force_to_mode (XEXP (x, 1), mode,
6742 mask, reg, next_select)));
6744 gen_lowpart_for_combine (GET_MODE (x),
6745 force_to_mode (XEXP (x, 2), mode,
6746 mask, reg,next_select)));
6753 /* Ensure we return a value of the proper mode. */
6754 return gen_lowpart_for_combine (mode, x);
6757 /* Return nonzero if X is an expression that has one of two values depending on
6758 whether some other value is zero or nonzero. In that case, we return the
6759 value that is being tested, *PTRUE is set to the value if the rtx being
6760 returned has a nonzero value, and *PFALSE is set to the other alternative.
6762 If we return zero, we set *PTRUE and *PFALSE to X. */
6765 if_then_else_cond (x, ptrue, pfalse)
6767 rtx *ptrue, *pfalse;
6769 enum machine_mode mode = GET_MODE (x);
6770 enum rtx_code code = GET_CODE (x);
6771 int size = GET_MODE_BITSIZE (mode);
6772 rtx cond0, cond1, true0, true1, false0, false1;
6773 unsigned HOST_WIDE_INT nz;
6775 /* If this is a unary operation whose operand has one of two values, apply
6776 our opcode to compute those values. */
6777 if (GET_RTX_CLASS (code) == '1'
6778 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
6780 *ptrue = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), true0);
6781 *pfalse = gen_unary (code, mode, GET_MODE (XEXP (x, 0)), false0);
6785 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
6786 make can't possibly match and would suppress other optimizations. */
6787 else if (code == COMPARE)
6790 /* If this is a binary operation, see if either side has only one of two
6791 values. If either one does or if both do and they are conditional on
6792 the same value, compute the new true and false values. */
6793 else if (GET_RTX_CLASS (code) == 'c' || GET_RTX_CLASS (code) == '2'
6794 || GET_RTX_CLASS (code) == '<')
6796 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
6797 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
6799 if ((cond0 != 0 || cond1 != 0)
6800 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
6802 /* If if_then_else_cond returned zero, then true/false are the
6803 same rtl. We must copy one of them to prevent invalid rtl
6806 true0 = copy_rtx (true0);
6807 else if (cond1 == 0)
6808 true1 = copy_rtx (true1);
6810 *ptrue = gen_binary (code, mode, true0, true1);
6811 *pfalse = gen_binary (code, mode, false0, false1);
6812 return cond0 ? cond0 : cond1;
6815 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
6816 operands is zero when the other is non-zero, and vice-versa,
6817 and STORE_FLAG_VALUE is 1 or -1. */
6819 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6820 && (code == PLUS || code == IOR || code == XOR || code == MINUS
6822 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6824 rtx op0 = XEXP (XEXP (x, 0), 1);
6825 rtx op1 = XEXP (XEXP (x, 1), 1);
6827 cond0 = XEXP (XEXP (x, 0), 0);
6828 cond1 = XEXP (XEXP (x, 1), 0);
6830 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6831 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6832 && reversible_comparison_p (cond1)
6833 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6834 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6835 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6836 || ((swap_condition (GET_CODE (cond0))
6837 == reverse_condition (GET_CODE (cond1)))
6838 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6839 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6840 && ! side_effects_p (x))
6842 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
6843 *pfalse = gen_binary (MULT, mode,
6845 ? gen_unary (NEG, mode, mode, op1) : op1),
6851 /* Similarly for MULT, AND and UMIN, execpt that for these the result
6853 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6854 && (code == MULT || code == AND || code == UMIN)
6855 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
6857 cond0 = XEXP (XEXP (x, 0), 0);
6858 cond1 = XEXP (XEXP (x, 1), 0);
6860 if (GET_RTX_CLASS (GET_CODE (cond0)) == '<'
6861 && GET_RTX_CLASS (GET_CODE (cond1)) == '<'
6862 && reversible_comparison_p (cond1)
6863 && ((GET_CODE (cond0) == reverse_condition (GET_CODE (cond1))
6864 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
6865 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
6866 || ((swap_condition (GET_CODE (cond0))
6867 == reverse_condition (GET_CODE (cond1)))
6868 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
6869 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
6870 && ! side_effects_p (x))
6872 *ptrue = *pfalse = const0_rtx;
6878 else if (code == IF_THEN_ELSE)
6880 /* If we have IF_THEN_ELSE already, extract the condition and
6881 canonicalize it if it is NE or EQ. */
6882 cond0 = XEXP (x, 0);
6883 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
6884 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
6885 return XEXP (cond0, 0);
6886 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
6888 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
6889 return XEXP (cond0, 0);
6895 /* If X is a normal SUBREG with both inner and outer modes integral,
6896 we can narrow both the true and false values of the inner expression,
6897 if there is a condition. */
6898 else if (code == SUBREG && GET_MODE_CLASS (mode) == MODE_INT
6899 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_INT
6900 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
6901 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
6904 *ptrue = force_to_mode (true0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6906 = force_to_mode (false0, mode, GET_MODE_MASK (mode), NULL_RTX, 0);
6911 /* If X is a constant, this isn't special and will cause confusions
6912 if we treat it as such. Likewise if it is equivalent to a constant. */
6913 else if (CONSTANT_P (x)
6914 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
6917 /* If X is known to be either 0 or -1, those are the true and
6918 false values when testing X. */
6919 else if (num_sign_bit_copies (x, mode) == size)
6921 *ptrue = constm1_rtx, *pfalse = const0_rtx;
6925 /* Likewise for 0 or a single bit. */
6926 else if (exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
6928 *ptrue = GEN_INT (nz), *pfalse = const0_rtx;
6932 /* Otherwise fail; show no condition with true and false values the same. */
6933 *ptrue = *pfalse = x;
6937 /* Return the value of expression X given the fact that condition COND
6938 is known to be true when applied to REG as its first operand and VAL
6939 as its second. X is known to not be shared and so can be modified in
6942 We only handle the simplest cases, and specifically those cases that
6943 arise with IF_THEN_ELSE expressions. */
6946 known_cond (x, cond, reg, val)
6951 enum rtx_code code = GET_CODE (x);
6956 if (side_effects_p (x))
6959 if (cond == EQ && rtx_equal_p (x, reg))
6962 /* If X is (abs REG) and we know something about REG's relationship
6963 with zero, we may be able to simplify this. */
6965 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
6968 case GE: case GT: case EQ:
6971 return gen_unary (NEG, GET_MODE (XEXP (x, 0)), GET_MODE (XEXP (x, 0)),
6977 /* The only other cases we handle are MIN, MAX, and comparisons if the
6978 operands are the same as REG and VAL. */
6980 else if (GET_RTX_CLASS (code) == '<' || GET_RTX_CLASS (code) == 'c')
6982 if (rtx_equal_p (XEXP (x, 0), val))
6983 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
6985 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
6987 if (GET_RTX_CLASS (code) == '<')
6988 return (comparison_dominates_p (cond, code) ? const_true_rtx
6989 : (comparison_dominates_p (cond,
6990 reverse_condition (code))
6993 else if (code == SMAX || code == SMIN
6994 || code == UMIN || code == UMAX)
6996 int unsignedp = (code == UMIN || code == UMAX);
6998 if (code == SMAX || code == UMAX)
6999 cond = reverse_condition (cond);
7004 return unsignedp ? x : XEXP (x, 1);
7006 return unsignedp ? x : XEXP (x, 0);
7008 return unsignedp ? XEXP (x, 1) : x;
7010 return unsignedp ? XEXP (x, 0) : x;
7018 fmt = GET_RTX_FORMAT (code);
7019 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7022 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7023 else if (fmt[i] == 'E')
7024 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7025 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7032 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7033 assignment as a field assignment. */
7036 rtx_equal_for_field_assignment_p (x, y)
7040 if (x == y || rtx_equal_p (x, y))
7043 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7046 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7047 Note that all SUBREGs of MEM are paradoxical; otherwise they
7048 would have been rewritten. */
7049 if (GET_CODE (x) == MEM && GET_CODE (y) == SUBREG
7050 && GET_CODE (SUBREG_REG (y)) == MEM
7051 && rtx_equal_p (SUBREG_REG (y),
7052 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y)), x)))
7055 if (GET_CODE (y) == MEM && GET_CODE (x) == SUBREG
7056 && GET_CODE (SUBREG_REG (x)) == MEM
7057 && rtx_equal_p (SUBREG_REG (x),
7058 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x)), y)))
7061 /* We used to see if get_last_value of X and Y were the same but that's
7062 not correct. In one direction, we'll cause the assignment to have
7063 the wrong destination and in the case, we'll import a register into this
7064 insn that might have already have been dead. So fail if none of the
7065 above cases are true. */
7069 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7070 Return that assignment if so.
7072 We only handle the most common cases. */
7075 make_field_assignment (x)
7078 rtx dest = SET_DEST (x);
7079 rtx src = SET_SRC (x);
7085 enum machine_mode mode;
7087 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7088 a clear of a one-bit field. We will have changed it to
7089 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7092 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7093 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7094 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7095 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7097 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7100 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7104 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7105 && subreg_lowpart_p (XEXP (src, 0))
7106 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7107 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7108 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7109 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7110 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7112 assign = make_extraction (VOIDmode, dest, 0,
7113 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7116 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7120 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7122 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7123 && XEXP (XEXP (src, 0), 0) == const1_rtx
7124 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7126 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7129 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7133 /* The other case we handle is assignments into a constant-position
7134 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7135 a mask that has all one bits except for a group of zero bits and
7136 OTHER is known to have zeros where C1 has ones, this is such an
7137 assignment. Compute the position and length from C1. Shift OTHER
7138 to the appropriate position, force it to the required mode, and
7139 make the extraction. Check for the AND in both operands. */
7141 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7144 rhs = expand_compound_operation (XEXP (src, 0));
7145 lhs = expand_compound_operation (XEXP (src, 1));
7147 if (GET_CODE (rhs) == AND
7148 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7149 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7150 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7151 else if (GET_CODE (lhs) == AND
7152 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7153 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7154 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7158 pos = get_pos_from_mask ((~ c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7159 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7160 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7161 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7164 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7168 /* The mode to use for the source is the mode of the assignment, or of
7169 what is inside a possible STRICT_LOW_PART. */
7170 mode = (GET_CODE (assign) == STRICT_LOW_PART
7171 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7173 /* Shift OTHER right POS places and make it the source, restricting it
7174 to the proper length and mode. */
7176 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7177 GET_MODE (src), other, pos),
7179 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7180 ? GET_MODE_MASK (mode)
7181 : ((HOST_WIDE_INT) 1 << len) - 1,
7184 return gen_rtx_combine (SET, VOIDmode, assign, src);
7187 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7191 apply_distributive_law (x)
7194 enum rtx_code code = GET_CODE (x);
7195 rtx lhs, rhs, other;
7197 enum rtx_code inner_code;
7199 /* Distributivity is not true for floating point.
7200 It can change the value. So don't do it.
7201 -- rms and moshier@world.std.com. */
7202 if (FLOAT_MODE_P (GET_MODE (x)))
7205 /* The outer operation can only be one of the following: */
7206 if (code != IOR && code != AND && code != XOR
7207 && code != PLUS && code != MINUS)
7210 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
7212 /* If either operand is a primitive we can't do anything, so get out
7214 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
7215 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
7218 lhs = expand_compound_operation (lhs);
7219 rhs = expand_compound_operation (rhs);
7220 inner_code = GET_CODE (lhs);
7221 if (inner_code != GET_CODE (rhs))
7224 /* See if the inner and outer operations distribute. */
7231 /* These all distribute except over PLUS. */
7232 if (code == PLUS || code == MINUS)
7237 if (code != PLUS && code != MINUS)
7242 /* This is also a multiply, so it distributes over everything. */
7246 /* Non-paradoxical SUBREGs distributes over all operations, provided
7247 the inner modes and word numbers are the same, this is an extraction
7248 of a low-order part, we don't convert an fp operation to int or
7249 vice versa, and we would not be converting a single-word
7250 operation into a multi-word operation. The latter test is not
7251 required, but it prevents generating unneeded multi-word operations.
7252 Some of the previous tests are redundant given the latter test, but
7253 are retained because they are required for correctness.
7255 We produce the result slightly differently in this case. */
7257 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7258 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
7259 || ! subreg_lowpart_p (lhs)
7260 || (GET_MODE_CLASS (GET_MODE (lhs))
7261 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7262 || (GET_MODE_SIZE (GET_MODE (lhs))
7263 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7264 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7267 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7268 SUBREG_REG (lhs), SUBREG_REG (rhs));
7269 return gen_lowpart_for_combine (GET_MODE (x), tem);
7275 /* Set LHS and RHS to the inner operands (A and B in the example
7276 above) and set OTHER to the common operand (C in the example).
7277 These is only one way to do this unless the inner operation is
7279 if (GET_RTX_CLASS (inner_code) == 'c'
7280 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7281 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7282 else if (GET_RTX_CLASS (inner_code) == 'c'
7283 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7284 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7285 else if (GET_RTX_CLASS (inner_code) == 'c'
7286 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7287 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7288 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7289 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7293 /* Form the new inner operation, seeing if it simplifies first. */
7294 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7296 /* There is one exception to the general way of distributing:
7297 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7298 if (code == XOR && inner_code == IOR)
7301 other = gen_unary (NOT, GET_MODE (x), GET_MODE (x), other);
7304 /* We may be able to continuing distributing the result, so call
7305 ourselves recursively on the inner operation before forming the
7306 outer operation, which we return. */
7307 return gen_binary (inner_code, GET_MODE (x),
7308 apply_distributive_law (tem), other);
7311 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7314 Return an equivalent form, if different from X. Otherwise, return X. If
7315 X is zero, we are to always construct the equivalent form. */
7318 simplify_and_const_int (x, mode, varop, constop)
7320 enum machine_mode mode;
7322 unsigned HOST_WIDE_INT constop;
7324 unsigned HOST_WIDE_INT nonzero;
7325 int width = GET_MODE_BITSIZE (mode);
7328 /* Simplify VAROP knowing that we will be only looking at some of the
7330 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
7332 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7333 CONST_INT, we are done. */
7334 if (GET_CODE (varop) == CLOBBER || GET_CODE (varop) == CONST_INT)
7337 /* See what bits may be nonzero in VAROP. Unlike the general case of
7338 a call to nonzero_bits, here we don't care about bits outside
7341 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7342 nonzero = trunc_int_for_mode (nonzero, mode);
7344 /* Turn off all bits in the constant that are known to already be zero.
7345 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7346 which is tested below. */
7350 /* If we don't have any bits left, return zero. */
7354 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7355 a power of two, we can replace this with a ASHIFT. */
7356 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7357 && (i = exact_log2 (constop)) >= 0)
7358 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7360 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7361 or XOR, then try to apply the distributive law. This may eliminate
7362 operations if either branch can be simplified because of the AND.
7363 It may also make some cases more complex, but those cases probably
7364 won't match a pattern either with or without this. */
7366 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7368 gen_lowpart_for_combine
7370 apply_distributive_law
7371 (gen_binary (GET_CODE (varop), GET_MODE (varop),
7372 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7373 XEXP (varop, 0), constop),
7374 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
7375 XEXP (varop, 1), constop))));
7377 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7378 if we already had one (just check for the simplest cases). */
7379 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7380 && GET_MODE (XEXP (x, 0)) == mode
7381 && SUBREG_REG (XEXP (x, 0)) == varop)
7382 varop = XEXP (x, 0);
7384 varop = gen_lowpart_for_combine (mode, varop);
7386 /* If we can't make the SUBREG, try to return what we were given. */
7387 if (GET_CODE (varop) == CLOBBER)
7388 return x ? x : varop;
7390 /* If we are only masking insignificant bits, return VAROP. */
7391 if (constop == nonzero)
7394 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7395 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7396 x = gen_binary (AND, mode, varop, GEN_INT (constop));
7400 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7401 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7402 SUBST (XEXP (x, 1), GEN_INT (constop));
7404 SUBST (XEXP (x, 0), varop);
7410 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7411 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7412 is less useful. We can't allow both, because that results in exponential
7413 run time recursion. There is a nullstone testcase that triggered
7414 this. This macro avoids accidental uses of num_sign_bit_copies. */
7415 #define num_sign_bit_copies()
7417 /* Given an expression, X, compute which bits in X can be non-zero.
7418 We don't care about bits outside of those defined in MODE.
7420 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7421 a shift, AND, or zero_extract, we can do better. */
7423 static unsigned HOST_WIDE_INT
7424 nonzero_bits (x, mode)
7426 enum machine_mode mode;
7428 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
7429 unsigned HOST_WIDE_INT inner_nz;
7431 int mode_width = GET_MODE_BITSIZE (mode);
7434 /* For floating-point values, assume all bits are needed. */
7435 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode))
7438 /* If X is wider than MODE, use its mode instead. */
7439 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
7441 mode = GET_MODE (x);
7442 nonzero = GET_MODE_MASK (mode);
7443 mode_width = GET_MODE_BITSIZE (mode);
7446 if (mode_width > HOST_BITS_PER_WIDE_INT)
7447 /* Our only callers in this case look for single bit values. So
7448 just return the mode mask. Those tests will then be false. */
7451 #ifndef WORD_REGISTER_OPERATIONS
7452 /* If MODE is wider than X, but both are a single word for both the host
7453 and target machines, we can compute this from which bits of the
7454 object might be nonzero in its own mode, taking into account the fact
7455 that on many CISC machines, accessing an object in a wider mode
7456 causes the high-order bits to become undefined. So they are
7457 not known to be zero. */
7459 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode
7460 && GET_MODE_BITSIZE (GET_MODE (x)) <= BITS_PER_WORD
7461 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7462 && GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (GET_MODE (x)))
7464 nonzero &= nonzero_bits (x, GET_MODE (x));
7465 nonzero |= GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x));
7470 code = GET_CODE (x);
7474 #ifdef POINTERS_EXTEND_UNSIGNED
7475 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7476 all the bits above ptr_mode are known to be zero. */
7477 if (POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode
7478 && REGNO_POINTER_FLAG (REGNO (x)))
7479 nonzero &= GET_MODE_MASK (ptr_mode);
7482 #ifdef STACK_BOUNDARY
7483 /* If this is the stack pointer, we may know something about its
7484 alignment. If PUSH_ROUNDING is defined, it is possible for the
7485 stack to be momentarily aligned only to that amount, so we pick
7486 the least alignment. */
7488 /* We can't check for arg_pointer_rtx here, because it is not
7489 guaranteed to have as much alignment as the stack pointer.
7490 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7491 alignment but the argument pointer has only 64 bit alignment. */
7493 if ((x == frame_pointer_rtx
7494 || x == stack_pointer_rtx
7495 || x == hard_frame_pointer_rtx
7496 || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
7497 && REGNO (x) <= LAST_VIRTUAL_REGISTER))
7503 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7505 #ifdef PUSH_ROUNDING
7506 if (REGNO (x) == STACK_POINTER_REGNUM)
7507 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
7510 /* We must return here, otherwise we may get a worse result from
7511 one of the choices below. There is nothing useful below as
7512 far as the stack pointer is concerned. */
7513 return nonzero &= ~ (sp_alignment - 1);
7517 /* If X is a register whose nonzero bits value is current, use it.
7518 Otherwise, if X is a register whose value we can find, use that
7519 value. Otherwise, use the previously-computed global nonzero bits
7520 for this register. */
7522 if (reg_last_set_value[REGNO (x)] != 0
7523 && reg_last_set_mode[REGNO (x)] == mode
7524 && (REG_N_SETS (REGNO (x)) == 1
7525 || reg_last_set_label[REGNO (x)] == label_tick)
7526 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7527 return reg_last_set_nonzero_bits[REGNO (x)];
7529 tem = get_last_value (x);
7533 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7534 /* If X is narrower than MODE and TEM is a non-negative
7535 constant that would appear negative in the mode of X,
7536 sign-extend it for use in reg_nonzero_bits because some
7537 machines (maybe most) will actually do the sign-extension
7538 and this is the conservative approach.
7540 ??? For 2.5, try to tighten up the MD files in this regard
7541 instead of this kludge. */
7543 if (GET_MODE_BITSIZE (GET_MODE (x)) < mode_width
7544 && GET_CODE (tem) == CONST_INT
7546 && 0 != (INTVAL (tem)
7547 & ((HOST_WIDE_INT) 1
7548 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7549 tem = GEN_INT (INTVAL (tem)
7550 | ((HOST_WIDE_INT) (-1)
7551 << GET_MODE_BITSIZE (GET_MODE (x))));
7553 return nonzero_bits (tem, mode);
7555 else if (nonzero_sign_valid && reg_nonzero_bits[REGNO (x)])
7556 return reg_nonzero_bits[REGNO (x)] & nonzero;
7561 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7562 /* If X is negative in MODE, sign-extend the value. */
7563 if (INTVAL (x) > 0 && mode_width < BITS_PER_WORD
7564 && 0 != (INTVAL (x) & ((HOST_WIDE_INT) 1 << (mode_width - 1))))
7565 return (INTVAL (x) | ((HOST_WIDE_INT) (-1) << mode_width));
7571 #ifdef LOAD_EXTEND_OP
7572 /* In many, if not most, RISC machines, reading a byte from memory
7573 zeros the rest of the register. Noticing that fact saves a lot
7574 of extra zero-extends. */
7575 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND)
7576 nonzero &= GET_MODE_MASK (GET_MODE (x));
7586 /* If this produces an integer result, we know which bits are set.
7587 Code here used to clear bits outside the mode of X, but that is
7590 if (GET_MODE_CLASS (mode) == MODE_INT
7591 && mode_width <= HOST_BITS_PER_WIDE_INT)
7592 nonzero = STORE_FLAG_VALUE;
7597 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7598 and num_sign_bit_copies. */
7599 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7600 == GET_MODE_BITSIZE (GET_MODE (x)))
7604 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
7605 nonzero |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
7610 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7611 and num_sign_bit_copies. */
7612 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x))
7613 == GET_MODE_BITSIZE (GET_MODE (x)))
7619 nonzero &= (nonzero_bits (XEXP (x, 0), mode) & GET_MODE_MASK (mode));
7623 nonzero &= nonzero_bits (XEXP (x, 0), mode);
7624 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7625 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7629 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
7630 Otherwise, show all the bits in the outer mode but not the inner
7632 inner_nz = nonzero_bits (XEXP (x, 0), mode);
7633 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
7635 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
7637 & (((HOST_WIDE_INT) 1
7638 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1))))
7639 inner_nz |= (GET_MODE_MASK (mode)
7640 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
7643 nonzero &= inner_nz;
7647 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7648 & nonzero_bits (XEXP (x, 1), mode));
7652 case UMIN: case UMAX: case SMIN: case SMAX:
7653 nonzero &= (nonzero_bits (XEXP (x, 0), mode)
7654 | nonzero_bits (XEXP (x, 1), mode));
7657 case PLUS: case MINUS:
7659 case DIV: case UDIV:
7660 case MOD: case UMOD:
7661 /* We can apply the rules of arithmetic to compute the number of
7662 high- and low-order zero bits of these operations. We start by
7663 computing the width (position of the highest-order non-zero bit)
7664 and the number of low-order zero bits for each value. */
7666 unsigned HOST_WIDE_INT nz0 = nonzero_bits (XEXP (x, 0), mode);
7667 unsigned HOST_WIDE_INT nz1 = nonzero_bits (XEXP (x, 1), mode);
7668 int width0 = floor_log2 (nz0) + 1;
7669 int width1 = floor_log2 (nz1) + 1;
7670 int low0 = floor_log2 (nz0 & -nz0);
7671 int low1 = floor_log2 (nz1 & -nz1);
7672 HOST_WIDE_INT op0_maybe_minusp
7673 = (nz0 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7674 HOST_WIDE_INT op1_maybe_minusp
7675 = (nz1 & ((HOST_WIDE_INT) 1 << (mode_width - 1)));
7676 int result_width = mode_width;
7684 && (XEXP (x, 0) == stack_pointer_rtx
7685 || XEXP (x, 0) == frame_pointer_rtx)
7686 && GET_CODE (XEXP (x, 1)) == CONST_INT)
7688 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
7690 nz0 = (GET_MODE_MASK (mode) & ~ (sp_alignment - 1));
7691 nz1 = INTVAL (XEXP (x, 1)) - STACK_BIAS;
7692 width0 = floor_log2 (nz0) + 1;
7693 width1 = floor_log2 (nz1) + 1;
7694 low0 = floor_log2 (nz0 & -nz0);
7695 low1 = floor_log2 (nz1 & -nz1);
7698 result_width = MAX (width0, width1) + 1;
7699 result_low = MIN (low0, low1);
7702 result_low = MIN (low0, low1);
7705 result_width = width0 + width1;
7706 result_low = low0 + low1;
7709 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7710 result_width = width0;
7713 result_width = width0;
7716 if (! op0_maybe_minusp && ! op1_maybe_minusp)
7717 result_width = MIN (width0, width1);
7718 result_low = MIN (low0, low1);
7721 result_width = MIN (width0, width1);
7722 result_low = MIN (low0, low1);
7728 if (result_width < mode_width)
7729 nonzero &= ((HOST_WIDE_INT) 1 << result_width) - 1;
7732 nonzero &= ~ (((HOST_WIDE_INT) 1 << result_low) - 1);
7737 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7738 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7739 nonzero &= ((HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1;
7743 /* If this is a SUBREG formed for a promoted variable that has
7744 been zero-extended, we know that at least the high-order bits
7745 are zero, though others might be too. */
7747 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
7748 nonzero = (GET_MODE_MASK (GET_MODE (x))
7749 & nonzero_bits (SUBREG_REG (x), GET_MODE (x)));
7751 /* If the inner mode is a single word for both the host and target
7752 machines, we can compute this from which bits of the inner
7753 object might be nonzero. */
7754 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
7755 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7756 <= HOST_BITS_PER_WIDE_INT))
7758 nonzero &= nonzero_bits (SUBREG_REG (x), mode);
7760 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
7761 /* If this is a typical RISC machine, we only have to worry
7762 about the way loads are extended. */
7763 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND
7765 & (1L << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) - 1)))
7766 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) != ZERO_EXTEND)
7769 /* On many CISC machines, accessing an object in a wider mode
7770 causes the high-order bits to become undefined. So they are
7771 not known to be zero. */
7772 if (GET_MODE_SIZE (GET_MODE (x))
7773 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7774 nonzero |= (GET_MODE_MASK (GET_MODE (x))
7775 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
7784 /* The nonzero bits are in two classes: any bits within MODE
7785 that aren't in GET_MODE (x) are always significant. The rest of the
7786 nonzero bits are those that are significant in the operand of
7787 the shift when shifted the appropriate number of bits. This
7788 shows that high-order bits are cleared by the right shift and
7789 low-order bits by left shifts. */
7790 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7791 && INTVAL (XEXP (x, 1)) >= 0
7792 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7794 enum machine_mode inner_mode = GET_MODE (x);
7795 int width = GET_MODE_BITSIZE (inner_mode);
7796 int count = INTVAL (XEXP (x, 1));
7797 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode);
7798 unsigned HOST_WIDE_INT op_nonzero = nonzero_bits (XEXP (x, 0), mode);
7799 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
7800 unsigned HOST_WIDE_INT outer = 0;
7802 if (mode_width > width)
7803 outer = (op_nonzero & nonzero & ~ mode_mask);
7805 if (code == LSHIFTRT)
7807 else if (code == ASHIFTRT)
7811 /* If the sign bit may have been nonzero before the shift, we
7812 need to mark all the places it could have been copied to
7813 by the shift as possibly nonzero. */
7814 if (inner & ((HOST_WIDE_INT) 1 << (width - 1 - count)))
7815 inner |= (((HOST_WIDE_INT) 1 << count) - 1) << (width - count);
7817 else if (code == ASHIFT)
7820 inner = ((inner << (count % width)
7821 | (inner >> (width - (count % width)))) & mode_mask);
7823 nonzero &= (outer | inner);
7828 /* This is at most the number of bits in the mode. */
7829 nonzero = ((HOST_WIDE_INT) 1 << (floor_log2 (mode_width) + 1)) - 1;
7833 nonzero &= (nonzero_bits (XEXP (x, 1), mode)
7834 | nonzero_bits (XEXP (x, 2), mode));
7844 /* See the macro definition above. */
7845 #undef num_sign_bit_copies
7847 /* Return the number of bits at the high-order end of X that are known to
7848 be equal to the sign bit. X will be used in mode MODE; if MODE is
7849 VOIDmode, X will be used in its own mode. The returned value will always
7850 be between 1 and the number of bits in MODE. */
7853 num_sign_bit_copies (x, mode)
7855 enum machine_mode mode;
7857 enum rtx_code code = GET_CODE (x);
7859 int num0, num1, result;
7860 unsigned HOST_WIDE_INT nonzero;
7863 /* If we weren't given a mode, use the mode of X. If the mode is still
7864 VOIDmode, we don't know anything. Likewise if one of the modes is
7867 if (mode == VOIDmode)
7868 mode = GET_MODE (x);
7870 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)))
7873 bitwidth = GET_MODE_BITSIZE (mode);
7875 /* For a smaller object, just ignore the high bits. */
7876 if (bitwidth < GET_MODE_BITSIZE (GET_MODE (x)))
7877 return MAX (1, (num_sign_bit_copies (x, GET_MODE (x))
7878 - (GET_MODE_BITSIZE (GET_MODE (x)) - bitwidth)));
7880 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_BITSIZE (GET_MODE (x)))
7882 #ifndef WORD_REGISTER_OPERATIONS
7883 /* If this machine does not do all register operations on the entire
7884 register and MODE is wider than the mode of X, we can say nothing
7885 at all about the high-order bits. */
7888 /* Likewise on machines that do, if the mode of the object is smaller
7889 than a word and loads of that size don't sign extend, we can say
7890 nothing about the high order bits. */
7891 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
7892 #ifdef LOAD_EXTEND_OP
7893 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND
7904 #ifdef POINTERS_EXTEND_UNSIGNED
7905 /* If pointers extend signed and this is a pointer in Pmode, say that
7906 all the bits above ptr_mode are known to be sign bit copies. */
7907 if (! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode && mode == Pmode
7908 && REGNO_POINTER_FLAG (REGNO (x)))
7909 return GET_MODE_BITSIZE (Pmode) - GET_MODE_BITSIZE (ptr_mode) + 1;
7912 if (reg_last_set_value[REGNO (x)] != 0
7913 && reg_last_set_mode[REGNO (x)] == mode
7914 && (REG_N_SETS (REGNO (x)) == 1
7915 || reg_last_set_label[REGNO (x)] == label_tick)
7916 && INSN_CUID (reg_last_set[REGNO (x)]) < subst_low_cuid)
7917 return reg_last_set_sign_bit_copies[REGNO (x)];
7919 tem = get_last_value (x);
7921 return num_sign_bit_copies (tem, mode);
7923 if (nonzero_sign_valid && reg_sign_bit_copies[REGNO (x)] != 0)
7924 return reg_sign_bit_copies[REGNO (x)];
7928 #ifdef LOAD_EXTEND_OP
7929 /* Some RISC machines sign-extend all loads of smaller than a word. */
7930 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND)
7931 return MAX (1, bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1);
7936 /* If the constant is negative, take its 1's complement and remask.
7937 Then see how many zero bits we have. */
7938 nonzero = INTVAL (x) & GET_MODE_MASK (mode);
7939 if (bitwidth <= HOST_BITS_PER_WIDE_INT
7940 && (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
7941 nonzero = (~ nonzero) & GET_MODE_MASK (mode);
7943 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1);
7946 /* If this is a SUBREG for a promoted object that is sign-extended
7947 and we are looking at it in a wider mode, we know that at least the
7948 high-order bits are known to be sign bit copies. */
7950 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x))
7951 return MAX (bitwidth - GET_MODE_BITSIZE (GET_MODE (x)) + 1,
7952 num_sign_bit_copies (SUBREG_REG (x), mode));
7954 /* For a smaller object, just ignore the high bits. */
7955 if (bitwidth <= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))))
7957 num0 = num_sign_bit_copies (SUBREG_REG (x), VOIDmode);
7958 return MAX (1, (num0
7959 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x)))
7963 #ifdef WORD_REGISTER_OPERATIONS
7964 #ifdef LOAD_EXTEND_OP
7965 /* For paradoxical SUBREGs on machines where all register operations
7966 affect the entire register, just look inside. Note that we are
7967 passing MODE to the recursive call, so the number of sign bit copies
7968 will remain relative to that mode, not the inner mode. */
7970 /* This works only if loads sign extend. Otherwise, if we get a
7971 reload for the inner part, it may be loaded from the stack, and
7972 then we lose all sign bit copies that existed before the store
7975 if ((GET_MODE_SIZE (GET_MODE (x))
7976 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7977 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND)
7978 return num_sign_bit_copies (SUBREG_REG (x), mode);
7984 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7985 return MAX (1, bitwidth - INTVAL (XEXP (x, 1)));
7989 return (bitwidth - GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7990 + num_sign_bit_copies (XEXP (x, 0), VOIDmode));
7993 /* For a smaller object, just ignore the high bits. */
7994 num0 = num_sign_bit_copies (XEXP (x, 0), VOIDmode);
7995 return MAX (1, (num0 - (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
7999 return num_sign_bit_copies (XEXP (x, 0), mode);
8001 case ROTATE: case ROTATERT:
8002 /* If we are rotating left by a number of bits less than the number
8003 of sign bit copies, we can just subtract that amount from the
8005 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8006 && INTVAL (XEXP (x, 1)) >= 0 && INTVAL (XEXP (x, 1)) < bitwidth)
8008 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8009 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
8010 : bitwidth - INTVAL (XEXP (x, 1))));
8015 /* In general, this subtracts one sign bit copy. But if the value
8016 is known to be positive, the number of sign bit copies is the
8017 same as that of the input. Finally, if the input has just one bit
8018 that might be nonzero, all the bits are copies of the sign bit. */
8019 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8020 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8021 return num0 > 1 ? num0 - 1 : 1;
8023 nonzero = nonzero_bits (XEXP (x, 0), mode);
8028 && (((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero))
8033 case IOR: case AND: case XOR:
8034 case SMIN: case SMAX: case UMIN: case UMAX:
8035 /* Logical operations will preserve the number of sign-bit copies.
8036 MIN and MAX operations always return one of the operands. */
8037 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8038 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8039 return MIN (num0, num1);
8041 case PLUS: case MINUS:
8042 /* For addition and subtraction, we can have a 1-bit carry. However,
8043 if we are subtracting 1 from a positive number, there will not
8044 be such a carry. Furthermore, if the positive number is known to
8045 be 0 or 1, we know the result is either -1 or 0. */
8047 if (code == PLUS && XEXP (x, 1) == constm1_rtx
8048 && bitwidth <= HOST_BITS_PER_WIDE_INT)
8050 nonzero = nonzero_bits (XEXP (x, 0), mode);
8051 if ((((HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0)
8052 return (nonzero == 1 || nonzero == 0 ? bitwidth
8053 : bitwidth - floor_log2 (nonzero) - 1);
8056 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8057 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8058 return MAX (1, MIN (num0, num1) - 1);
8061 /* The number of bits of the product is the sum of the number of
8062 bits of both terms. However, unless one of the terms if known
8063 to be positive, we must allow for an additional bit since negating
8064 a negative number can remove one sign bit copy. */
8066 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8067 num1 = num_sign_bit_copies (XEXP (x, 1), mode);
8069 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
8071 && (bitwidth > HOST_BITS_PER_WIDE_INT
8072 || (((nonzero_bits (XEXP (x, 0), mode)
8073 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8074 && ((nonzero_bits (XEXP (x, 1), mode)
8075 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))))
8078 return MAX (1, result);
8081 /* The result must be <= the first operand. If the first operand
8082 has the high bit set, we know nothing about the number of sign
8084 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8086 else if ((nonzero_bits (XEXP (x, 0), mode)
8087 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)
8090 return num_sign_bit_copies (XEXP (x, 0), mode);
8093 /* The result must be <= the scond operand. */
8094 return num_sign_bit_copies (XEXP (x, 1), mode);
8097 /* Similar to unsigned division, except that we have to worry about
8098 the case where the divisor is negative, in which case we have
8100 result = num_sign_bit_copies (XEXP (x, 0), mode);
8102 && (bitwidth > HOST_BITS_PER_WIDE_INT
8103 || (nonzero_bits (XEXP (x, 1), mode)
8104 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8110 result = num_sign_bit_copies (XEXP (x, 1), mode);
8112 && (bitwidth > HOST_BITS_PER_WIDE_INT
8113 || (nonzero_bits (XEXP (x, 1), mode)
8114 & ((HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0))
8120 /* Shifts by a constant add to the number of bits equal to the
8122 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8123 if (GET_CODE (XEXP (x, 1)) == CONST_INT
8124 && INTVAL (XEXP (x, 1)) > 0)
8125 num0 = MIN (bitwidth, num0 + INTVAL (XEXP (x, 1)));
8130 /* Left shifts destroy copies. */
8131 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8132 || INTVAL (XEXP (x, 1)) < 0
8133 || INTVAL (XEXP (x, 1)) >= bitwidth)
8136 num0 = num_sign_bit_copies (XEXP (x, 0), mode);
8137 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
8140 num0 = num_sign_bit_copies (XEXP (x, 1), mode);
8141 num1 = num_sign_bit_copies (XEXP (x, 2), mode);
8142 return MIN (num0, num1);
8144 case EQ: case NE: case GE: case GT: case LE: case LT:
8145 case GEU: case GTU: case LEU: case LTU:
8146 if (STORE_FLAG_VALUE == -1)
8154 /* If we haven't been able to figure it out by one of the above rules,
8155 see if some of the high-order bits are known to be zero. If so,
8156 count those bits and return one less than that amount. If we can't
8157 safely compute the mask for this mode, always return BITWIDTH. */
8159 if (bitwidth > HOST_BITS_PER_WIDE_INT)
8162 nonzero = nonzero_bits (x, mode);
8163 return (nonzero & ((HOST_WIDE_INT) 1 << (bitwidth - 1))
8164 ? 1 : bitwidth - floor_log2 (nonzero) - 1);
8167 /* Return the number of "extended" bits there are in X, when interpreted
8168 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8169 unsigned quantities, this is the number of high-order zero bits.
8170 For signed quantities, this is the number of copies of the sign bit
8171 minus 1. In both case, this function returns the number of "spare"
8172 bits. For example, if two quantities for which this function returns
8173 at least 1 are added, the addition is known not to overflow.
8175 This function will always return 0 unless called during combine, which
8176 implies that it must be called from a define_split. */
8179 extended_count (x, mode, unsignedp)
8181 enum machine_mode mode;
8184 if (nonzero_sign_valid == 0)
8188 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8189 && (GET_MODE_BITSIZE (mode) - 1
8190 - floor_log2 (nonzero_bits (x, mode))))
8191 : num_sign_bit_copies (x, mode) - 1);
8194 /* This function is called from `simplify_shift_const' to merge two
8195 outer operations. Specifically, we have already found that we need
8196 to perform operation *POP0 with constant *PCONST0 at the outermost
8197 position. We would now like to also perform OP1 with constant CONST1
8198 (with *POP0 being done last).
8200 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8201 the resulting operation. *PCOMP_P is set to 1 if we would need to
8202 complement the innermost operand, otherwise it is unchanged.
8204 MODE is the mode in which the operation will be done. No bits outside
8205 the width of this mode matter. It is assumed that the width of this mode
8206 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8208 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8209 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8210 result is simply *PCONST0.
8212 If the resulting operation cannot be expressed as one operation, we
8213 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8216 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
8217 enum rtx_code *pop0;
8218 HOST_WIDE_INT *pconst0;
8220 HOST_WIDE_INT const1;
8221 enum machine_mode mode;
8224 enum rtx_code op0 = *pop0;
8225 HOST_WIDE_INT const0 = *pconst0;
8226 int width = GET_MODE_BITSIZE (mode);
8228 const0 &= GET_MODE_MASK (mode);
8229 const1 &= GET_MODE_MASK (mode);
8231 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8235 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8238 if (op1 == NIL || op0 == SET)
8241 else if (op0 == NIL)
8242 op0 = op1, const0 = const1;
8244 else if (op0 == op1)
8268 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8269 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8272 /* If the two constants aren't the same, we can't do anything. The
8273 remaining six cases can all be done. */
8274 else if (const0 != const1)
8282 /* (a & b) | b == b */
8284 else /* op1 == XOR */
8285 /* (a ^ b) | b == a | b */
8291 /* (a & b) ^ b == (~a) & b */
8292 op0 = AND, *pcomp_p = 1;
8293 else /* op1 == IOR */
8294 /* (a | b) ^ b == a & ~b */
8295 op0 = AND, *pconst0 = ~ const0;
8300 /* (a | b) & b == b */
8302 else /* op1 == XOR */
8303 /* (a ^ b) & b) == (~a) & b */
8310 /* Check for NO-OP cases. */
8311 const0 &= GET_MODE_MASK (mode);
8313 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8315 else if (const0 == 0 && op0 == AND)
8317 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8321 /* ??? Slightly redundant with the above mask, but not entirely.
8322 Moving this above means we'd have to sign-extend the mode mask
8323 for the final test. */
8324 const0 = trunc_int_for_mode (const0, mode);
8332 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8333 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8334 that we started with.
8336 The shift is normally computed in the widest mode we find in VAROP, as
8337 long as it isn't a different number of words than RESULT_MODE. Exceptions
8338 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8341 simplify_shift_const (x, code, result_mode, varop, count)
8344 enum machine_mode result_mode;
8348 enum rtx_code orig_code = code;
8349 int orig_count = count;
8350 enum machine_mode mode = result_mode;
8351 enum machine_mode shift_mode, tmode;
8353 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8354 /* We form (outer_op (code varop count) (outer_const)). */
8355 enum rtx_code outer_op = NIL;
8356 HOST_WIDE_INT outer_const = 0;
8358 int complement_p = 0;
8361 /* If we were given an invalid count, don't do anything except exactly
8362 what was requested. */
8364 if (count < 0 || count > GET_MODE_BITSIZE (mode))
8369 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (count));
8372 /* Unless one of the branches of the `if' in this loop does a `continue',
8373 we will `break' the loop after the `if'. */
8377 /* If we have an operand of (clobber (const_int 0)), just return that
8379 if (GET_CODE (varop) == CLOBBER)
8382 /* If we discovered we had to complement VAROP, leave. Making a NOT
8383 here would cause an infinite loop. */
8387 /* Convert ROTATERT to ROTATE. */
8388 if (code == ROTATERT)
8389 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
8391 /* We need to determine what mode we will do the shift in. If the
8392 shift is a right shift or a ROTATE, we must always do it in the mode
8393 it was originally done in. Otherwise, we can do it in MODE, the
8394 widest mode encountered. */
8396 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8397 ? result_mode : mode);
8399 /* Handle cases where the count is greater than the size of the mode
8400 minus 1. For ASHIFT, use the size minus one as the count (this can
8401 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8402 take the count modulo the size. For other shifts, the result is
8405 Since these shifts are being produced by the compiler by combining
8406 multiple operations, each of which are defined, we know what the
8407 result is supposed to be. */
8409 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
8411 if (code == ASHIFTRT)
8412 count = GET_MODE_BITSIZE (shift_mode) - 1;
8413 else if (code == ROTATE || code == ROTATERT)
8414 count %= GET_MODE_BITSIZE (shift_mode);
8417 /* We can't simply return zero because there may be an
8425 /* Negative counts are invalid and should not have been made (a
8426 programmer-specified negative count should have been handled
8431 /* An arithmetic right shift of a quantity known to be -1 or 0
8433 if (code == ASHIFTRT
8434 && (num_sign_bit_copies (varop, shift_mode)
8435 == GET_MODE_BITSIZE (shift_mode)))
8441 /* If we are doing an arithmetic right shift and discarding all but
8442 the sign bit copies, this is equivalent to doing a shift by the
8443 bitsize minus one. Convert it into that shift because it will often
8444 allow other simplifications. */
8446 if (code == ASHIFTRT
8447 && (count + num_sign_bit_copies (varop, shift_mode)
8448 >= GET_MODE_BITSIZE (shift_mode)))
8449 count = GET_MODE_BITSIZE (shift_mode) - 1;
8451 /* We simplify the tests below and elsewhere by converting
8452 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8453 `make_compound_operation' will convert it to a ASHIFTRT for
8454 those machines (such as Vax) that don't have a LSHIFTRT. */
8455 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8457 && ((nonzero_bits (varop, shift_mode)
8458 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8462 switch (GET_CODE (varop))
8468 new = expand_compound_operation (varop);
8477 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8478 minus the width of a smaller mode, we can do this with a
8479 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8480 if ((code == ASHIFTRT || code == LSHIFTRT)
8481 && ! mode_dependent_address_p (XEXP (varop, 0))
8482 && ! MEM_VOLATILE_P (varop)
8483 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8484 MODE_INT, 1)) != BLKmode)
8486 if (BYTES_BIG_ENDIAN)
8487 new = gen_rtx_MEM (tmode, XEXP (varop, 0));
8489 new = gen_rtx_MEM (tmode,
8490 plus_constant (XEXP (varop, 0),
8491 count / BITS_PER_UNIT));
8492 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
8493 MEM_COPY_ATTRIBUTES (new, varop);
8494 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8495 : ZERO_EXTEND, mode, new);
8502 /* Similar to the case above, except that we can only do this if
8503 the resulting mode is the same as that of the underlying
8504 MEM and adjust the address depending on the *bits* endianness
8505 because of the way that bit-field extract insns are defined. */
8506 if ((code == ASHIFTRT || code == LSHIFTRT)
8507 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8508 MODE_INT, 1)) != BLKmode
8509 && tmode == GET_MODE (XEXP (varop, 0)))
8511 if (BITS_BIG_ENDIAN)
8512 new = XEXP (varop, 0);
8515 new = copy_rtx (XEXP (varop, 0));
8516 SUBST (XEXP (new, 0),
8517 plus_constant (XEXP (new, 0),
8518 count / BITS_PER_UNIT));
8521 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
8522 : ZERO_EXTEND, mode, new);
8529 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8530 the same number of words as what we've seen so far. Then store
8531 the widest mode in MODE. */
8532 if (subreg_lowpart_p (varop)
8533 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8534 > GET_MODE_SIZE (GET_MODE (varop)))
8535 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8536 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8539 varop = SUBREG_REG (varop);
8540 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8541 mode = GET_MODE (varop);
8547 /* Some machines use MULT instead of ASHIFT because MULT
8548 is cheaper. But it is still better on those machines to
8549 merge two shifts into one. */
8550 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8551 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8553 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8554 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));;
8560 /* Similar, for when divides are cheaper. */
8561 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8562 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8564 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8565 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8571 /* If we are extracting just the sign bit of an arithmetic right
8572 shift, that shift is not needed. */
8573 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
8575 varop = XEXP (varop, 0);
8579 /* ... fall through ... */
8584 /* Here we have two nested shifts. The result is usually the
8585 AND of a new shift with a mask. We compute the result below. */
8586 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8587 && INTVAL (XEXP (varop, 1)) >= 0
8588 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8589 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8590 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8592 enum rtx_code first_code = GET_CODE (varop);
8593 int first_count = INTVAL (XEXP (varop, 1));
8594 unsigned HOST_WIDE_INT mask;
8597 /* We have one common special case. We can't do any merging if
8598 the inner code is an ASHIFTRT of a smaller mode. However, if
8599 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8600 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8601 we can convert it to
8602 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8603 This simplifies certain SIGN_EXTEND operations. */
8604 if (code == ASHIFT && first_code == ASHIFTRT
8605 && (GET_MODE_BITSIZE (result_mode)
8606 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
8608 /* C3 has the low-order C1 bits zero. */
8610 mask = (GET_MODE_MASK (mode)
8611 & ~ (((HOST_WIDE_INT) 1 << first_count) - 1));
8613 varop = simplify_and_const_int (NULL_RTX, result_mode,
8614 XEXP (varop, 0), mask);
8615 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8617 count = first_count;
8622 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8623 than C1 high-order bits equal to the sign bit, we can convert
8624 this to either an ASHIFT or a ASHIFTRT depending on the
8627 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8629 if (code == ASHIFTRT && first_code == ASHIFT
8630 && GET_MODE (varop) == shift_mode
8631 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8634 count -= first_count;
8636 count = - count, code = ASHIFT;
8637 varop = XEXP (varop, 0);
8641 /* There are some cases we can't do. If CODE is ASHIFTRT,
8642 we can only do this if FIRST_CODE is also ASHIFTRT.
8644 We can't do the case when CODE is ROTATE and FIRST_CODE is
8647 If the mode of this shift is not the mode of the outer shift,
8648 we can't do this if either shift is a right shift or ROTATE.
8650 Finally, we can't do any of these if the mode is too wide
8651 unless the codes are the same.
8653 Handle the case where the shift codes are the same
8656 if (code == first_code)
8658 if (GET_MODE (varop) != result_mode
8659 && (code == ASHIFTRT || code == LSHIFTRT
8663 count += first_count;
8664 varop = XEXP (varop, 0);
8668 if (code == ASHIFTRT
8669 || (code == ROTATE && first_code == ASHIFTRT)
8670 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8671 || (GET_MODE (varop) != result_mode
8672 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8673 || first_code == ROTATE
8674 || code == ROTATE)))
8677 /* To compute the mask to apply after the shift, shift the
8678 nonzero bits of the inner shift the same way the
8679 outer shift will. */
8681 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8684 = simplify_binary_operation (code, result_mode, mask_rtx,
8687 /* Give up if we can't compute an outer operation to use. */
8689 || GET_CODE (mask_rtx) != CONST_INT
8690 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8692 result_mode, &complement_p))
8695 /* If the shifts are in the same direction, we add the
8696 counts. Otherwise, we subtract them. */
8697 if ((code == ASHIFTRT || code == LSHIFTRT)
8698 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8699 count += first_count;
8701 count -= first_count;
8703 /* If COUNT is positive, the new shift is usually CODE,
8704 except for the two exceptions below, in which case it is
8705 FIRST_CODE. If the count is negative, FIRST_CODE should
8708 && ((first_code == ROTATE && code == ASHIFT)
8709 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8712 code = first_code, count = - count;
8714 varop = XEXP (varop, 0);
8718 /* If we have (A << B << C) for any shift, we can convert this to
8719 (A << C << B). This wins if A is a constant. Only try this if
8720 B is not a constant. */
8722 else if (GET_CODE (varop) == code
8723 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8725 = simplify_binary_operation (code, mode,
8729 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
8736 /* Make this fit the case below. */
8737 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
8738 GEN_INT (GET_MODE_MASK (mode)));
8744 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8745 with C the size of VAROP - 1 and the shift is logical if
8746 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8747 we have an (le X 0) operation. If we have an arithmetic shift
8748 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8749 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8751 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8752 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8753 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8754 && (code == LSHIFTRT || code == ASHIFTRT)
8755 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8756 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8759 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
8762 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8763 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8768 /* If we have (shift (logical)), move the logical to the outside
8769 to allow it to possibly combine with another logical and the
8770 shift to combine with another shift. This also canonicalizes to
8771 what a ZERO_EXTRACT looks like. Also, some machines have
8772 (and (shift)) insns. */
8774 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8775 && (new = simplify_binary_operation (code, result_mode,
8777 GEN_INT (count))) != 0
8778 && GET_CODE(new) == CONST_INT
8779 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8780 INTVAL (new), result_mode, &complement_p))
8782 varop = XEXP (varop, 0);
8786 /* If we can't do that, try to simplify the shift in each arm of the
8787 logical expression, make a new logical expression, and apply
8788 the inverse distributive law. */
8790 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8791 XEXP (varop, 0), count);
8792 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8793 XEXP (varop, 1), count);
8795 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8796 varop = apply_distributive_law (varop);
8803 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8804 says that the sign bit can be tested, FOO has mode MODE, C is
8805 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8806 that may be nonzero. */
8807 if (code == LSHIFTRT
8808 && XEXP (varop, 1) == const0_rtx
8809 && GET_MODE (XEXP (varop, 0)) == result_mode
8810 && count == GET_MODE_BITSIZE (result_mode) - 1
8811 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8812 && ((STORE_FLAG_VALUE
8813 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (result_mode) - 1))))
8814 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8815 && merge_outer_ops (&outer_op, &outer_const, XOR,
8816 (HOST_WIDE_INT) 1, result_mode,
8819 varop = XEXP (varop, 0);
8826 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8827 than the number of bits in the mode is equivalent to A. */
8828 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8829 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8831 varop = XEXP (varop, 0);
8836 /* NEG commutes with ASHIFT since it is multiplication. Move the
8837 NEG outside to allow shifts to combine. */
8839 && merge_outer_ops (&outer_op, &outer_const, NEG,
8840 (HOST_WIDE_INT) 0, result_mode,
8843 varop = XEXP (varop, 0);
8849 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8850 is one less than the number of bits in the mode is
8851 equivalent to (xor A 1). */
8852 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
8853 && XEXP (varop, 1) == constm1_rtx
8854 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8855 && merge_outer_ops (&outer_op, &outer_const, XOR,
8856 (HOST_WIDE_INT) 1, result_mode,
8860 varop = XEXP (varop, 0);
8864 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8865 that might be nonzero in BAR are those being shifted out and those
8866 bits are known zero in FOO, we can replace the PLUS with FOO.
8867 Similarly in the other operand order. This code occurs when
8868 we are computing the size of a variable-size array. */
8870 if ((code == ASHIFTRT || code == LSHIFTRT)
8871 && count < HOST_BITS_PER_WIDE_INT
8872 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8873 && (nonzero_bits (XEXP (varop, 1), result_mode)
8874 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8876 varop = XEXP (varop, 0);
8879 else if ((code == ASHIFTRT || code == LSHIFTRT)
8880 && count < HOST_BITS_PER_WIDE_INT
8881 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8882 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8884 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8885 & nonzero_bits (XEXP (varop, 1),
8888 varop = XEXP (varop, 1);
8892 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8894 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8895 && (new = simplify_binary_operation (ASHIFT, result_mode,
8897 GEN_INT (count))) != 0
8898 && GET_CODE(new) == CONST_INT
8899 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8900 INTVAL (new), result_mode, &complement_p))
8902 varop = XEXP (varop, 0);
8908 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8909 with C the size of VAROP - 1 and the shift is logical if
8910 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8911 we have a (gt X 0) operation. If the shift is arithmetic with
8912 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8913 we have a (neg (gt X 0)) operation. */
8915 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8916 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8917 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
8918 && (code == LSHIFTRT || code == ASHIFTRT)
8919 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8920 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
8921 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8924 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
8927 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8928 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
8935 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8936 if the truncate does not affect the value. */
8937 if (code == LSHIFTRT
8938 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8939 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8940 && (INTVAL (XEXP (XEXP (varop, 0), 1))
8941 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8942 - GET_MODE_BITSIZE (GET_MODE (varop)))))
8944 rtx varop_inner = XEXP (varop, 0);
8946 varop_inner = gen_rtx_combine (LSHIFTRT,
8947 GET_MODE (varop_inner),
8948 XEXP (varop_inner, 0),
8949 GEN_INT (count + INTVAL (XEXP (varop_inner, 1))));
8950 varop = gen_rtx_combine (TRUNCATE, GET_MODE (varop),
8964 /* We need to determine what mode to do the shift in. If the shift is
8965 a right shift or ROTATE, we must always do it in the mode it was
8966 originally done in. Otherwise, we can do it in MODE, the widest mode
8967 encountered. The code we care about is that of the shift that will
8968 actually be done, not the shift that was originally requested. */
8970 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8971 ? result_mode : mode);
8973 /* We have now finished analyzing the shift. The result should be
8974 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8975 OUTER_OP is non-NIL, it is an operation that needs to be applied
8976 to the result of the shift. OUTER_CONST is the relevant constant,
8977 but we must turn off all bits turned off in the shift.
8979 If we were passed a value for X, see if we can use any pieces of
8980 it. If not, make new rtx. */
8982 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
8983 && GET_CODE (XEXP (x, 1)) == CONST_INT
8984 && INTVAL (XEXP (x, 1)) == count)
8985 const_rtx = XEXP (x, 1);
8987 const_rtx = GEN_INT (count);
8989 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8990 && GET_MODE (XEXP (x, 0)) == shift_mode
8991 && SUBREG_REG (XEXP (x, 0)) == varop)
8992 varop = XEXP (x, 0);
8993 else if (GET_MODE (varop) != shift_mode)
8994 varop = gen_lowpart_for_combine (shift_mode, varop);
8996 /* If we can't make the SUBREG, try to return what we were given. */
8997 if (GET_CODE (varop) == CLOBBER)
8998 return x ? x : varop;
9000 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9005 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
9006 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
9008 SUBST (XEXP (x, 0), varop);
9009 SUBST (XEXP (x, 1), const_rtx);
9012 /* If we have an outer operation and we just made a shift, it is
9013 possible that we could have simplified the shift were it not
9014 for the outer operation. So try to do the simplification
9017 if (outer_op != NIL && GET_CODE (x) == code
9018 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9019 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9020 INTVAL (XEXP (x, 1)));
9022 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9023 turn off all the bits that the shift would have turned off. */
9024 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9025 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9026 GET_MODE_MASK (result_mode) >> orig_count);
9028 /* Do the remainder of the processing in RESULT_MODE. */
9029 x = gen_lowpart_for_combine (result_mode, x);
9031 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9034 x = gen_unary (NOT, result_mode, result_mode, x);
9036 if (outer_op != NIL)
9038 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9039 outer_const = trunc_int_for_mode (outer_const, result_mode);
9041 if (outer_op == AND)
9042 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9043 else if (outer_op == SET)
9044 /* This means that we have determined that the result is
9045 equivalent to a constant. This should be rare. */
9046 x = GEN_INT (outer_const);
9047 else if (GET_RTX_CLASS (outer_op) == '1')
9048 x = gen_unary (outer_op, result_mode, result_mode, x);
9050 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9056 /* Like recog, but we receive the address of a pointer to a new pattern.
9057 We try to match the rtx that the pointer points to.
9058 If that fails, we may try to modify or replace the pattern,
9059 storing the replacement into the same pointer object.
9061 Modifications include deletion or addition of CLOBBERs.
9063 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9064 the CLOBBERs are placed.
9066 The value is the final insn code from the pattern ultimately matched,
9070 recog_for_combine (pnewpat, insn, pnotes)
9075 register rtx pat = *pnewpat;
9076 int insn_code_number;
9077 int num_clobbers_to_add = 0;
9081 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9082 we use to indicate that something didn't match. If we find such a
9083 thing, force rejection. */
9084 if (GET_CODE (pat) == PARALLEL)
9085 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9086 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9087 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9090 /* Is the result of combination a valid instruction? */
9091 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9093 /* If it isn't, there is the possibility that we previously had an insn
9094 that clobbered some register as a side effect, but the combined
9095 insn doesn't need to do that. So try once more without the clobbers
9096 unless this represents an ASM insn. */
9098 if (insn_code_number < 0 && ! check_asm_operands (pat)
9099 && GET_CODE (pat) == PARALLEL)
9103 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9104 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9107 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9111 SUBST_INT (XVECLEN (pat, 0), pos);
9114 pat = XVECEXP (pat, 0, 0);
9116 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9119 /* If we had any clobbers to add, make a new pattern than contains
9120 them. Then check to make sure that all of them are dead. */
9121 if (num_clobbers_to_add)
9123 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9124 gen_rtvec (GET_CODE (pat) == PARALLEL
9125 ? XVECLEN (pat, 0) + num_clobbers_to_add
9126 : num_clobbers_to_add + 1));
9128 if (GET_CODE (pat) == PARALLEL)
9129 for (i = 0; i < XVECLEN (pat, 0); i++)
9130 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9132 XVECEXP (newpat, 0, 0) = pat;
9134 add_clobbers (newpat, insn_code_number);
9136 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9137 i < XVECLEN (newpat, 0); i++)
9139 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
9140 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9142 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9143 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9151 return insn_code_number;
9154 /* Like gen_lowpart but for use by combine. In combine it is not possible
9155 to create any new pseudoregs. However, it is safe to create
9156 invalid memory addresses, because combine will try to recognize
9157 them and all they will do is make the combine attempt fail.
9159 If for some reason this cannot do its job, an rtx
9160 (clobber (const_int 0)) is returned.
9161 An insn containing that will not be recognized. */
9166 gen_lowpart_for_combine (mode, x)
9167 enum machine_mode mode;
9172 if (GET_MODE (x) == mode)
9175 /* We can only support MODE being wider than a word if X is a
9176 constant integer or has a mode the same size. */
9178 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9179 && ! ((GET_MODE (x) == VOIDmode
9180 && (GET_CODE (x) == CONST_INT
9181 || GET_CODE (x) == CONST_DOUBLE))
9182 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9183 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9185 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9186 won't know what to do. So we will strip off the SUBREG here and
9187 process normally. */
9188 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
9191 if (GET_MODE (x) == mode)
9195 result = gen_lowpart_common (mode, x);
9197 && GET_CODE (result) == SUBREG
9198 && GET_CODE (SUBREG_REG (result)) == REG
9199 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER
9200 && (GET_MODE_SIZE (GET_MODE (result))
9201 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result)))))
9202 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result))) = 1;
9207 if (GET_CODE (x) == MEM)
9209 register int offset = 0;
9212 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9214 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9215 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9217 /* If we want to refer to something bigger than the original memref,
9218 generate a perverse subreg instead. That will force a reload
9219 of the original memref X. */
9220 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9221 return gen_rtx_SUBREG (mode, x, 0);
9223 if (WORDS_BIG_ENDIAN)
9224 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9225 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9226 if (BYTES_BIG_ENDIAN)
9228 /* Adjust the address so that the address-after-the-data is
9230 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9231 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9233 new = gen_rtx_MEM (mode, plus_constant (XEXP (x, 0), offset));
9234 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
9235 MEM_COPY_ATTRIBUTES (new, x);
9239 /* If X is a comparison operator, rewrite it in a new mode. This
9240 probably won't match, but may allow further simplifications. */
9241 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
9242 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9244 /* If we couldn't simplify X any other way, just enclose it in a
9245 SUBREG. Normally, this SUBREG won't match, but some patterns may
9246 include an explicit SUBREG or we may simplify it further in combine. */
9251 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
9252 word = ((GET_MODE_SIZE (GET_MODE (x))
9253 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
9255 return gen_rtx_SUBREG (mode, x, word);
9259 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9260 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9262 If the identical expression was previously in the insn (in the undobuf),
9263 it will be returned. Only if it is not found will a new expression
9268 gen_rtx_combine VPROTO((enum rtx_code code, enum machine_mode mode, ...))
9270 #ifndef ANSI_PROTOTYPES
9272 enum machine_mode mode;
9284 #ifndef ANSI_PROTOTYPES
9285 code = va_arg (p, enum rtx_code);
9286 mode = va_arg (p, enum machine_mode);
9289 n_args = GET_RTX_LENGTH (code);
9290 fmt = GET_RTX_FORMAT (code);
9292 if (n_args == 0 || n_args > 3)
9295 /* Get each arg and verify that it is supposed to be an expression. */
9296 for (j = 0; j < n_args; j++)
9301 args[j] = va_arg (p, rtx);
9304 /* See if this is in undobuf. Be sure we don't use objects that came
9305 from another insn; this could produce circular rtl structures. */
9307 for (undo = undobuf.undos; undo != undobuf.previous_undos; undo = undo->next)
9309 && GET_CODE (undo->old_contents.r) == code
9310 && GET_MODE (undo->old_contents.r) == mode)
9312 for (j = 0; j < n_args; j++)
9313 if (XEXP (undo->old_contents.r, j) != args[j])
9317 return undo->old_contents.r;
9320 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9321 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9322 rt = rtx_alloc (code);
9323 PUT_MODE (rt, mode);
9324 XEXP (rt, 0) = args[0];
9327 XEXP (rt, 1) = args[1];
9329 XEXP (rt, 2) = args[2];
9334 /* These routines make binary and unary operations by first seeing if they
9335 fold; if not, a new expression is allocated. */
9338 gen_binary (code, mode, op0, op1)
9340 enum machine_mode mode;
9346 if (GET_RTX_CLASS (code) == 'c'
9347 && (GET_CODE (op0) == CONST_INT
9348 || (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)))
9349 tem = op0, op0 = op1, op1 = tem;
9351 if (GET_RTX_CLASS (code) == '<')
9353 enum machine_mode op_mode = GET_MODE (op0);
9355 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9356 just (REL_OP X Y). */
9357 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9359 op1 = XEXP (op0, 1);
9360 op0 = XEXP (op0, 0);
9361 op_mode = GET_MODE (op0);
9364 if (op_mode == VOIDmode)
9365 op_mode = GET_MODE (op1);
9366 result = simplify_relational_operation (code, op_mode, op0, op1);
9369 result = simplify_binary_operation (code, mode, op0, op1);
9374 /* Put complex operands first and constants second. */
9375 if (GET_RTX_CLASS (code) == 'c'
9376 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9377 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
9378 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
9379 || (GET_CODE (op0) == SUBREG
9380 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
9381 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
9382 return gen_rtx_combine (code, mode, op1, op0);
9384 /* If we are turning off bits already known off in OP0, we need not do
9386 else if (code == AND && GET_CODE (op1) == CONST_INT
9387 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9388 && (nonzero_bits (op0, mode) & ~ INTVAL (op1)) == 0)
9391 return gen_rtx_combine (code, mode, op0, op1);
9395 gen_unary (code, mode, op0_mode, op0)
9397 enum machine_mode mode, op0_mode;
9400 rtx result = simplify_unary_operation (code, mode, op0, op0_mode);
9405 return gen_rtx_combine (code, mode, op0);
9408 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9409 comparison code that will be tested.
9411 The result is a possibly different comparison code to use. *POP0 and
9412 *POP1 may be updated.
9414 It is possible that we might detect that a comparison is either always
9415 true or always false. However, we do not perform general constant
9416 folding in combine, so this knowledge isn't useful. Such tautologies
9417 should have been detected earlier. Hence we ignore all such cases. */
9419 static enum rtx_code
9420 simplify_comparison (code, pop0, pop1)
9429 enum machine_mode mode, tmode;
9431 /* Try a few ways of applying the same transformation to both operands. */
9434 #ifndef WORD_REGISTER_OPERATIONS
9435 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9436 so check specially. */
9437 if (code != GTU && code != GEU && code != LTU && code != LEU
9438 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9439 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9440 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9441 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9442 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9443 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9444 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9445 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9446 && GET_CODE (XEXP (op1, 1)) == CONST_INT
9447 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9448 && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT
9449 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (op1, 1))
9450 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op0, 0), 1))
9451 && INTVAL (XEXP (op0, 1)) == INTVAL (XEXP (XEXP (op1, 0), 1))
9452 && (INTVAL (XEXP (op0, 1))
9453 == (GET_MODE_BITSIZE (GET_MODE (op0))
9455 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9457 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9458 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9462 /* If both operands are the same constant shift, see if we can ignore the
9463 shift. We can if the shift is a rotate or if the bits shifted out of
9464 this shift are known to be zero for both inputs and if the type of
9465 comparison is compatible with the shift. */
9466 if (GET_CODE (op0) == GET_CODE (op1)
9467 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9468 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9469 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9470 && (code != GT && code != LT && code != GE && code != LE))
9471 || (GET_CODE (op0) == ASHIFTRT
9472 && (code != GTU && code != LTU
9473 && code != GEU && code != GEU)))
9474 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9475 && INTVAL (XEXP (op0, 1)) >= 0
9476 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9477 && XEXP (op0, 1) == XEXP (op1, 1))
9479 enum machine_mode mode = GET_MODE (op0);
9480 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9481 int shift_count = INTVAL (XEXP (op0, 1));
9483 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9484 mask &= (mask >> shift_count) << shift_count;
9485 else if (GET_CODE (op0) == ASHIFT)
9486 mask = (mask & (mask << shift_count)) >> shift_count;
9488 if ((nonzero_bits (XEXP (op0, 0), mode) & ~ mask) == 0
9489 && (nonzero_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
9490 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9495 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9496 SUBREGs are of the same mode, and, in both cases, the AND would
9497 be redundant if the comparison was done in the narrower mode,
9498 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9499 and the operand's possibly nonzero bits are 0xffffff01; in that case
9500 if we only care about QImode, we don't need the AND). This case
9501 occurs if the output mode of an scc insn is not SImode and
9502 STORE_FLAG_VALUE == 1 (e.g., the 386).
9504 Similarly, check for a case where the AND's are ZERO_EXTEND
9505 operations from some narrower mode even though a SUBREG is not
9508 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9509 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9510 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9512 rtx inner_op0 = XEXP (op0, 0);
9513 rtx inner_op1 = XEXP (op1, 0);
9514 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9515 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9518 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9519 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9520 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9521 && (GET_MODE (SUBREG_REG (inner_op0))
9522 == GET_MODE (SUBREG_REG (inner_op1)))
9523 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9524 <= HOST_BITS_PER_WIDE_INT)
9525 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9526 GET_MODE (SUBREG_REG (inner_op0)))))
9527 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9528 GET_MODE (SUBREG_REG (inner_op1))))))
9530 op0 = SUBREG_REG (inner_op0);
9531 op1 = SUBREG_REG (inner_op1);
9533 /* The resulting comparison is always unsigned since we masked
9534 off the original sign bit. */
9535 code = unsigned_condition (code);
9541 for (tmode = GET_CLASS_NARROWEST_MODE
9542 (GET_MODE_CLASS (GET_MODE (op0)));
9543 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9544 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9546 op0 = gen_lowpart_for_combine (tmode, inner_op0);
9547 op1 = gen_lowpart_for_combine (tmode, inner_op1);
9548 code = unsigned_condition (code);
9557 /* If both operands are NOT, we can strip off the outer operation
9558 and adjust the comparison code for swapped operands; similarly for
9559 NEG, except that this must be an equality comparison. */
9560 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9561 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9562 && (code == EQ || code == NE)))
9563 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9569 /* If the first operand is a constant, swap the operands and adjust the
9570 comparison code appropriately, but don't do this if the second operand
9571 is already a constant integer. */
9572 if (CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
9574 tem = op0, op0 = op1, op1 = tem;
9575 code = swap_condition (code);
9578 /* We now enter a loop during which we will try to simplify the comparison.
9579 For the most part, we only are concerned with comparisons with zero,
9580 but some things may really be comparisons with zero but not start
9581 out looking that way. */
9583 while (GET_CODE (op1) == CONST_INT)
9585 enum machine_mode mode = GET_MODE (op0);
9586 int mode_width = GET_MODE_BITSIZE (mode);
9587 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9588 int equality_comparison_p;
9589 int sign_bit_comparison_p;
9590 int unsigned_comparison_p;
9591 HOST_WIDE_INT const_op;
9593 /* We only want to handle integral modes. This catches VOIDmode,
9594 CCmode, and the floating-point modes. An exception is that we
9595 can handle VOIDmode if OP0 is a COMPARE or a comparison
9598 if (GET_MODE_CLASS (mode) != MODE_INT
9599 && ! (mode == VOIDmode
9600 && (GET_CODE (op0) == COMPARE
9601 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
9604 /* Get the constant we are comparing against and turn off all bits
9605 not on in our mode. */
9606 const_op = INTVAL (op1);
9607 if (mode_width <= HOST_BITS_PER_WIDE_INT)
9610 /* If we are comparing against a constant power of two and the value
9611 being compared can only have that single bit nonzero (e.g., it was
9612 `and'ed with that bit), we can replace this with a comparison
9615 && (code == EQ || code == NE || code == GE || code == GEU
9616 || code == LT || code == LTU)
9617 && mode_width <= HOST_BITS_PER_WIDE_INT
9618 && exact_log2 (const_op) >= 0
9619 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9621 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9622 op1 = const0_rtx, const_op = 0;
9625 /* Similarly, if we are comparing a value known to be either -1 or
9626 0 with -1, change it to the opposite comparison against zero. */
9629 && (code == EQ || code == NE || code == GT || code == LE
9630 || code == GEU || code == LTU)
9631 && num_sign_bit_copies (op0, mode) == mode_width)
9633 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9634 op1 = const0_rtx, const_op = 0;
9637 /* Do some canonicalizations based on the comparison code. We prefer
9638 comparisons against zero and then prefer equality comparisons.
9639 If we can reduce the size of a constant, we will do that too. */
9644 /* < C is equivalent to <= (C - 1) */
9648 op1 = GEN_INT (const_op);
9650 /* ... fall through to LE case below. */
9656 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9660 op1 = GEN_INT (const_op);
9664 /* If we are doing a <= 0 comparison on a value known to have
9665 a zero sign bit, we can replace this with == 0. */
9666 else if (const_op == 0
9667 && mode_width <= HOST_BITS_PER_WIDE_INT
9668 && (nonzero_bits (op0, mode)
9669 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9674 /* >= C is equivalent to > (C - 1). */
9678 op1 = GEN_INT (const_op);
9680 /* ... fall through to GT below. */
9686 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
9690 op1 = GEN_INT (const_op);
9694 /* If we are doing a > 0 comparison on a value known to have
9695 a zero sign bit, we can replace this with != 0. */
9696 else if (const_op == 0
9697 && mode_width <= HOST_BITS_PER_WIDE_INT
9698 && (nonzero_bits (op0, mode)
9699 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9704 /* < C is equivalent to <= (C - 1). */
9708 op1 = GEN_INT (const_op);
9710 /* ... fall through ... */
9713 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9714 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9715 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9717 const_op = 0, op1 = const0_rtx;
9725 /* unsigned <= 0 is equivalent to == 0 */
9729 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9730 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9731 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9733 const_op = 0, op1 = const0_rtx;
9739 /* >= C is equivalent to < (C - 1). */
9743 op1 = GEN_INT (const_op);
9745 /* ... fall through ... */
9748 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9749 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9750 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9752 const_op = 0, op1 = const0_rtx;
9760 /* unsigned > 0 is equivalent to != 0 */
9764 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9765 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9766 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9768 const_op = 0, op1 = const0_rtx;
9777 /* Compute some predicates to simplify code below. */
9779 equality_comparison_p = (code == EQ || code == NE);
9780 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9781 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9784 /* If this is a sign bit comparison and we can do arithmetic in
9785 MODE, say that we will only be needing the sign bit of OP0. */
9786 if (sign_bit_comparison_p
9787 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9788 op0 = force_to_mode (op0, mode,
9790 << (GET_MODE_BITSIZE (mode) - 1)),
9793 /* Now try cases based on the opcode of OP0. If none of the cases
9794 does a "continue", we exit this loop immediately after the
9797 switch (GET_CODE (op0))
9800 /* If we are extracting a single bit from a variable position in
9801 a constant that has only a single bit set and are comparing it
9802 with zero, we can convert this into an equality comparison
9803 between the position and the location of the single bit. */
9805 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
9806 && XEXP (op0, 1) == const1_rtx
9807 && equality_comparison_p && const_op == 0
9808 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9810 if (BITS_BIG_ENDIAN)
9813 mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
9814 if (mode == VOIDmode)
9816 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9818 i = BITS_PER_WORD - 1 - i;
9822 op0 = XEXP (op0, 2);
9826 /* Result is nonzero iff shift count is equal to I. */
9827 code = reverse_condition (code);
9831 /* ... fall through ... */
9834 tem = expand_compound_operation (op0);
9843 /* If testing for equality, we can take the NOT of the constant. */
9844 if (equality_comparison_p
9845 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9847 op0 = XEXP (op0, 0);
9852 /* If just looking at the sign bit, reverse the sense of the
9854 if (sign_bit_comparison_p)
9856 op0 = XEXP (op0, 0);
9857 code = (code == GE ? LT : GE);
9863 /* If testing for equality, we can take the NEG of the constant. */
9864 if (equality_comparison_p
9865 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9867 op0 = XEXP (op0, 0);
9872 /* The remaining cases only apply to comparisons with zero. */
9876 /* When X is ABS or is known positive,
9877 (neg X) is < 0 if and only if X != 0. */
9879 if (sign_bit_comparison_p
9880 && (GET_CODE (XEXP (op0, 0)) == ABS
9881 || (mode_width <= HOST_BITS_PER_WIDE_INT
9882 && (nonzero_bits (XEXP (op0, 0), mode)
9883 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9885 op0 = XEXP (op0, 0);
9886 code = (code == LT ? NE : EQ);
9890 /* If we have NEG of something whose two high-order bits are the
9891 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9892 if (num_sign_bit_copies (op0, mode) >= 2)
9894 op0 = XEXP (op0, 0);
9895 code = swap_condition (code);
9901 /* If we are testing equality and our count is a constant, we
9902 can perform the inverse operation on our RHS. */
9903 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9904 && (tem = simplify_binary_operation (ROTATERT, mode,
9905 op1, XEXP (op0, 1))) != 0)
9907 op0 = XEXP (op0, 0);
9912 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9913 a particular bit. Convert it to an AND of a constant of that
9914 bit. This will be converted into a ZERO_EXTRACT. */
9915 if (const_op == 0 && sign_bit_comparison_p
9916 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9917 && mode_width <= HOST_BITS_PER_WIDE_INT)
9919 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9922 - INTVAL (XEXP (op0, 1)))));
9923 code = (code == LT ? NE : EQ);
9927 /* ... fall through ... */
9930 /* ABS is ignorable inside an equality comparison with zero. */
9931 if (const_op == 0 && equality_comparison_p)
9933 op0 = XEXP (op0, 0);
9940 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9941 to (compare FOO CONST) if CONST fits in FOO's mode and we
9942 are either testing inequality or have an unsigned comparison
9943 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9944 if (! unsigned_comparison_p
9945 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9946 <= HOST_BITS_PER_WIDE_INT)
9947 && ((unsigned HOST_WIDE_INT) const_op
9948 < (((unsigned HOST_WIDE_INT) 1
9949 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9951 op0 = XEXP (op0, 0);
9957 /* Check for the case where we are comparing A - C1 with C2,
9958 both constants are smaller than 1/2 the maximum positive
9959 value in MODE, and the comparison is equality or unsigned.
9960 In that case, if A is either zero-extended to MODE or has
9961 sufficient sign bits so that the high-order bit in MODE
9962 is a copy of the sign in the inner mode, we can prove that it is
9963 safe to do the operation in the wider mode. This simplifies
9964 many range checks. */
9966 if (mode_width <= HOST_BITS_PER_WIDE_INT
9967 && subreg_lowpart_p (op0)
9968 && GET_CODE (SUBREG_REG (op0)) == PLUS
9969 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
9970 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
9971 && (- INTVAL (XEXP (SUBREG_REG (op0), 1))
9972 < (HOST_WIDE_INT)(GET_MODE_MASK (mode) / 2))
9973 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
9974 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
9975 GET_MODE (SUBREG_REG (op0)))
9976 & ~ GET_MODE_MASK (mode))
9977 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
9978 GET_MODE (SUBREG_REG (op0)))
9979 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
9980 - GET_MODE_BITSIZE (mode)))))
9982 op0 = SUBREG_REG (op0);
9986 /* If the inner mode is narrower and we are extracting the low part,
9987 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9988 if (subreg_lowpart_p (op0)
9989 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9990 /* Fall through */ ;
9994 /* ... fall through ... */
9997 if ((unsigned_comparison_p || equality_comparison_p)
9998 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9999 <= HOST_BITS_PER_WIDE_INT)
10000 && ((unsigned HOST_WIDE_INT) const_op
10001 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10003 op0 = XEXP (op0, 0);
10009 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10010 this for equality comparisons due to pathological cases involving
10012 if (equality_comparison_p
10013 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10014 op1, XEXP (op0, 1))))
10016 op0 = XEXP (op0, 0);
10021 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10022 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10023 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10025 op0 = XEXP (XEXP (op0, 0), 0);
10026 code = (code == LT ? EQ : NE);
10032 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10033 (eq B (minus A C)), whichever simplifies. We can only do
10034 this for equality comparisons due to pathological cases involving
10036 if (equality_comparison_p
10037 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10038 XEXP (op0, 1), op1)))
10040 op0 = XEXP (op0, 0);
10045 if (equality_comparison_p
10046 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10047 XEXP (op0, 0), op1)))
10049 op0 = XEXP (op0, 1);
10054 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10055 of bits in X minus 1, is one iff X > 0. */
10056 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10057 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10058 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
10059 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10061 op0 = XEXP (op0, 1);
10062 code = (code == GE ? LE : GT);
10068 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10069 if C is zero or B is a constant. */
10070 if (equality_comparison_p
10071 && 0 != (tem = simplify_binary_operation (XOR, mode,
10072 XEXP (op0, 1), op1)))
10074 op0 = XEXP (op0, 0);
10081 case LT: case LTU: case LE: case LEU:
10082 case GT: case GTU: case GE: case GEU:
10083 /* We can't do anything if OP0 is a condition code value, rather
10084 than an actual data value. */
10087 || XEXP (op0, 0) == cc0_rtx
10089 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10092 /* Get the two operands being compared. */
10093 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10094 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10096 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10098 /* Check for the cases where we simply want the result of the
10099 earlier test or the opposite of that result. */
10101 || (code == EQ && reversible_comparison_p (op0))
10102 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10103 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10104 && (STORE_FLAG_VALUE
10105 & (((HOST_WIDE_INT) 1
10106 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10108 || (code == GE && reversible_comparison_p (op0)))))
10110 code = (code == LT || code == NE
10111 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
10112 op0 = tem, op1 = tem1;
10118 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10120 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10121 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10122 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10124 op0 = XEXP (op0, 1);
10125 code = (code == GE ? GT : LE);
10131 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10132 will be converted to a ZERO_EXTRACT later. */
10133 if (const_op == 0 && equality_comparison_p
10134 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10135 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10137 op0 = simplify_and_const_int
10138 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
10140 XEXP (XEXP (op0, 0), 1)),
10141 (HOST_WIDE_INT) 1);
10145 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10146 zero and X is a comparison and C1 and C2 describe only bits set
10147 in STORE_FLAG_VALUE, we can compare with X. */
10148 if (const_op == 0 && equality_comparison_p
10149 && mode_width <= HOST_BITS_PER_WIDE_INT
10150 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10151 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10152 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10153 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10154 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10156 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10157 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10158 if ((~ STORE_FLAG_VALUE & mask) == 0
10159 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
10160 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10161 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
10163 op0 = XEXP (XEXP (op0, 0), 0);
10168 /* If we are doing an equality comparison of an AND of a bit equal
10169 to the sign bit, replace this with a LT or GE comparison of
10170 the underlying value. */
10171 if (equality_comparison_p
10173 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10174 && mode_width <= HOST_BITS_PER_WIDE_INT
10175 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10176 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10178 op0 = XEXP (op0, 0);
10179 code = (code == EQ ? GE : LT);
10183 /* If this AND operation is really a ZERO_EXTEND from a narrower
10184 mode, the constant fits within that mode, and this is either an
10185 equality or unsigned comparison, try to do this comparison in
10186 the narrower mode. */
10187 if ((equality_comparison_p || unsigned_comparison_p)
10188 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10189 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10190 & GET_MODE_MASK (mode))
10192 && const_op >> i == 0
10193 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10195 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
10199 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10200 in both M1 and M2 and the SUBREG is either paradoxical or
10201 represents the low part, permute the SUBREG and the AND and
10203 if (GET_CODE (XEXP (op0, 0)) == SUBREG
10205 >= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10206 #ifdef WORD_REGISTER_OPERATIONS
10207 || subreg_lowpart_p (XEXP (op0, 0))
10210 #ifndef WORD_REGISTER_OPERATIONS
10211 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10212 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10213 As originally written the upper bits have a defined value
10214 due to the AND operation. However, if we commute the AND
10215 inside the SUBREG then they no longer have defined values
10216 and the meaning of the code has been changed. */
10217 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
10218 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
10220 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10221 && mode_width <= HOST_BITS_PER_WIDE_INT
10222 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10223 <= HOST_BITS_PER_WIDE_INT)
10224 && (INTVAL (XEXP (op0, 1)) & ~ mask) == 0
10225 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))
10226 & INTVAL (XEXP (op0, 1)))
10227 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1)) != mask
10228 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10229 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0, 0))))))
10233 = gen_lowpart_for_combine
10235 gen_binary (AND, GET_MODE (SUBREG_REG (XEXP (op0, 0))),
10236 SUBREG_REG (XEXP (op0, 0)), XEXP (op0, 1)));
10243 /* If we have (compare (ashift FOO N) (const_int C)) and
10244 the high order N bits of FOO (N+1 if an inequality comparison)
10245 are known to be zero, we can do this by comparing FOO with C
10246 shifted right N bits so long as the low-order N bits of C are
10248 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10249 && INTVAL (XEXP (op0, 1)) >= 0
10250 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10251 < HOST_BITS_PER_WIDE_INT)
10253 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10254 && mode_width <= HOST_BITS_PER_WIDE_INT
10255 && (nonzero_bits (XEXP (op0, 0), mode)
10256 & ~ (mask >> (INTVAL (XEXP (op0, 1))
10257 + ! equality_comparison_p))) == 0)
10259 const_op >>= INTVAL (XEXP (op0, 1));
10260 op1 = GEN_INT (const_op);
10261 op0 = XEXP (op0, 0);
10265 /* If we are doing a sign bit comparison, it means we are testing
10266 a particular bit. Convert it to the appropriate AND. */
10267 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10268 && mode_width <= HOST_BITS_PER_WIDE_INT)
10270 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10273 - INTVAL (XEXP (op0, 1)))));
10274 code = (code == LT ? NE : EQ);
10278 /* If this an equality comparison with zero and we are shifting
10279 the low bit to the sign bit, we can convert this to an AND of the
10281 if (const_op == 0 && equality_comparison_p
10282 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10283 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10285 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10286 (HOST_WIDE_INT) 1);
10292 /* If this is an equality comparison with zero, we can do this
10293 as a logical shift, which might be much simpler. */
10294 if (equality_comparison_p && const_op == 0
10295 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10297 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10299 INTVAL (XEXP (op0, 1)));
10303 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10304 do the comparison in a narrower mode. */
10305 if (! unsigned_comparison_p
10306 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10307 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10308 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10309 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10310 MODE_INT, 1)) != BLKmode
10311 && ((unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (tmode)
10312 || ((unsigned HOST_WIDE_INT) - const_op
10313 <= GET_MODE_MASK (tmode))))
10315 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
10319 /* ... fall through ... */
10321 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10322 the low order N bits of FOO are known to be zero, we can do this
10323 by comparing FOO with C shifted left N bits so long as no
10324 overflow occurs. */
10325 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10326 && INTVAL (XEXP (op0, 1)) >= 0
10327 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10328 && mode_width <= HOST_BITS_PER_WIDE_INT
10329 && (nonzero_bits (XEXP (op0, 0), mode)
10330 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10332 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
10335 const_op <<= INTVAL (XEXP (op0, 1));
10336 op1 = GEN_INT (const_op);
10337 op0 = XEXP (op0, 0);
10341 /* If we are using this shift to extract just the sign bit, we
10342 can replace this with an LT or GE comparison. */
10344 && (equality_comparison_p || sign_bit_comparison_p)
10345 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10346 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
10348 op0 = XEXP (op0, 0);
10349 code = (code == NE || code == GT ? LT : GE);
10361 /* Now make any compound operations involved in this comparison. Then,
10362 check for an outmost SUBREG on OP0 that is not doing anything or is
10363 paradoxical. The latter case can only occur when it is known that the
10364 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10365 We can never remove a SUBREG for a non-equality comparison because the
10366 sign bit is in a different place in the underlying object. */
10368 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10369 op1 = make_compound_operation (op1, SET);
10371 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10372 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10373 && (code == NE || code == EQ)
10374 && ((GET_MODE_SIZE (GET_MODE (op0))
10375 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
10377 op0 = SUBREG_REG (op0);
10378 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
10381 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10382 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10383 && (code == NE || code == EQ)
10384 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10385 <= HOST_BITS_PER_WIDE_INT)
10386 && (nonzero_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
10387 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
10388 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
10390 (nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10391 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
10392 op0 = SUBREG_REG (op0), op1 = tem;
10394 /* We now do the opposite procedure: Some machines don't have compare
10395 insns in all modes. If OP0's mode is an integer mode smaller than a
10396 word and we can't do a compare in that mode, see if there is a larger
10397 mode for which we can do the compare. There are a number of cases in
10398 which we can use the wider mode. */
10400 mode = GET_MODE (op0);
10401 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10402 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10403 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
10404 for (tmode = GET_MODE_WIDER_MODE (mode);
10406 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10407 tmode = GET_MODE_WIDER_MODE (tmode))
10408 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing)
10410 /* If the only nonzero bits in OP0 and OP1 are those in the
10411 narrower mode and this is an equality or unsigned comparison,
10412 we can use the wider mode. Similarly for sign-extended
10413 values, in which case it is true for all comparisons. */
10414 if (((code == EQ || code == NE
10415 || code == GEU || code == GTU || code == LEU || code == LTU)
10416 && (nonzero_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
10417 && (nonzero_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0)
10418 || ((num_sign_bit_copies (op0, tmode)
10419 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))
10420 && (num_sign_bit_copies (op1, tmode)
10421 > GET_MODE_BITSIZE (tmode) - GET_MODE_BITSIZE (mode))))
10423 op0 = gen_lowpart_for_combine (tmode, op0);
10424 op1 = gen_lowpart_for_combine (tmode, op1);
10428 /* If this is a test for negative, we can make an explicit
10429 test of the sign bit. */
10431 if (op1 == const0_rtx && (code == LT || code == GE)
10432 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10434 op0 = gen_binary (AND, tmode,
10435 gen_lowpart_for_combine (tmode, op0),
10436 GEN_INT ((HOST_WIDE_INT) 1
10437 << (GET_MODE_BITSIZE (mode) - 1)));
10438 code = (code == LT) ? NE : EQ;
10443 #ifdef CANONICALIZE_COMPARISON
10444 /* If this machine only supports a subset of valid comparisons, see if we
10445 can convert an unsupported one into a supported one. */
10446 CANONICALIZE_COMPARISON (code, op0, op1);
10455 /* Return 1 if we know that X, a comparison operation, is not operating
10456 on a floating-point value or is EQ or NE, meaning that we can safely
10460 reversible_comparison_p (x)
10463 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
10465 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
10468 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
10471 case MODE_PARTIAL_INT:
10472 case MODE_COMPLEX_INT:
10476 /* If the mode of the condition codes tells us that this is safe,
10477 we need look no further. */
10478 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x, 0))))
10481 /* Otherwise try and find where the condition codes were last set and
10483 x = get_last_value (XEXP (x, 0));
10484 return (x && GET_CODE (x) == COMPARE
10485 && ! FLOAT_MODE_P (GET_MODE (XEXP (x, 0))));
10492 /* Utility function for following routine. Called when X is part of a value
10493 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10494 for each register mentioned. Similar to mention_regs in cse.c */
10497 update_table_tick (x)
10500 register enum rtx_code code = GET_CODE (x);
10501 register char *fmt = GET_RTX_FORMAT (code);
10506 int regno = REGNO (x);
10507 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10508 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10510 for (i = regno; i < endregno; i++)
10511 reg_last_set_table_tick[i] = label_tick;
10516 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10517 /* Note that we can't have an "E" in values stored; see
10518 get_last_value_validate. */
10520 update_table_tick (XEXP (x, i));
10523 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10524 are saying that the register is clobbered and we no longer know its
10525 value. If INSN is zero, don't update reg_last_set; this is only permitted
10526 with VALUE also zero and is used to invalidate the register. */
10529 record_value_for_reg (reg, insn, value)
10534 int regno = REGNO (reg);
10535 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10536 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
10539 /* If VALUE contains REG and we have a previous value for REG, substitute
10540 the previous value. */
10541 if (value && insn && reg_overlap_mentioned_p (reg, value))
10545 /* Set things up so get_last_value is allowed to see anything set up to
10547 subst_low_cuid = INSN_CUID (insn);
10548 tem = get_last_value (reg);
10551 value = replace_rtx (copy_rtx (value), reg, tem);
10554 /* For each register modified, show we don't know its value, that
10555 we don't know about its bitwise content, that its value has been
10556 updated, and that we don't know the location of the death of the
10558 for (i = regno; i < endregno; i ++)
10561 reg_last_set[i] = insn;
10562 reg_last_set_value[i] = 0;
10563 reg_last_set_mode[i] = 0;
10564 reg_last_set_nonzero_bits[i] = 0;
10565 reg_last_set_sign_bit_copies[i] = 0;
10566 reg_last_death[i] = 0;
10569 /* Mark registers that are being referenced in this value. */
10571 update_table_tick (value);
10573 /* Now update the status of each register being set.
10574 If someone is using this register in this block, set this register
10575 to invalid since we will get confused between the two lives in this
10576 basic block. This makes using this register always invalid. In cse, we
10577 scan the table to invalidate all entries using this register, but this
10578 is too much work for us. */
10580 for (i = regno; i < endregno; i++)
10582 reg_last_set_label[i] = label_tick;
10583 if (value && reg_last_set_table_tick[i] == label_tick)
10584 reg_last_set_invalid[i] = 1;
10586 reg_last_set_invalid[i] = 0;
10589 /* The value being assigned might refer to X (like in "x++;"). In that
10590 case, we must replace it with (clobber (const_int 0)) to prevent
10592 if (value && ! get_last_value_validate (&value, insn,
10593 reg_last_set_label[regno], 0))
10595 value = copy_rtx (value);
10596 if (! get_last_value_validate (&value, insn,
10597 reg_last_set_label[regno], 1))
10601 /* For the main register being modified, update the value, the mode, the
10602 nonzero bits, and the number of sign bit copies. */
10604 reg_last_set_value[regno] = value;
10608 subst_low_cuid = INSN_CUID (insn);
10609 reg_last_set_mode[regno] = GET_MODE (reg);
10610 reg_last_set_nonzero_bits[regno] = nonzero_bits (value, GET_MODE (reg));
10611 reg_last_set_sign_bit_copies[regno]
10612 = num_sign_bit_copies (value, GET_MODE (reg));
10616 /* Used for communication between the following two routines. */
10617 static rtx record_dead_insn;
10619 /* Called via note_stores from record_dead_and_set_regs to handle one
10620 SET or CLOBBER in an insn. */
10623 record_dead_and_set_regs_1 (dest, setter)
10626 if (GET_CODE (dest) == SUBREG)
10627 dest = SUBREG_REG (dest);
10629 if (GET_CODE (dest) == REG)
10631 /* If we are setting the whole register, we know its value. Otherwise
10632 show that we don't know the value. We can handle SUBREG in
10634 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10635 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10636 else if (GET_CODE (setter) == SET
10637 && GET_CODE (SET_DEST (setter)) == SUBREG
10638 && SUBREG_REG (SET_DEST (setter)) == dest
10639 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10640 && subreg_lowpart_p (SET_DEST (setter)))
10641 record_value_for_reg (dest, record_dead_insn,
10642 gen_lowpart_for_combine (GET_MODE (dest),
10643 SET_SRC (setter)));
10645 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10647 else if (GET_CODE (dest) == MEM
10648 /* Ignore pushes, they clobber nothing. */
10649 && ! push_operand (dest, GET_MODE (dest)))
10650 mem_last_set = INSN_CUID (record_dead_insn);
10653 /* Update the records of when each REG was most recently set or killed
10654 for the things done by INSN. This is the last thing done in processing
10655 INSN in the combiner loop.
10657 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
10658 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
10659 and also the similar information mem_last_set (which insn most recently
10660 modified memory) and last_call_cuid (which insn was the most recent
10661 subroutine call). */
10664 record_dead_and_set_regs (insn)
10670 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10672 if (REG_NOTE_KIND (link) == REG_DEAD
10673 && GET_CODE (XEXP (link, 0)) == REG)
10675 int regno = REGNO (XEXP (link, 0));
10677 = regno + (regno < FIRST_PSEUDO_REGISTER
10678 ? HARD_REGNO_NREGS (regno, GET_MODE (XEXP (link, 0)))
10681 for (i = regno; i < endregno; i++)
10682 reg_last_death[i] = insn;
10684 else if (REG_NOTE_KIND (link) == REG_INC)
10685 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10688 if (GET_CODE (insn) == CALL_INSN)
10690 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10691 if (call_used_regs[i])
10693 reg_last_set_value[i] = 0;
10694 reg_last_set_mode[i] = 0;
10695 reg_last_set_nonzero_bits[i] = 0;
10696 reg_last_set_sign_bit_copies[i] = 0;
10697 reg_last_death[i] = 0;
10700 last_call_cuid = mem_last_set = INSN_CUID (insn);
10703 record_dead_insn = insn;
10704 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
10707 /* Utility routine for the following function. Verify that all the registers
10708 mentioned in *LOC are valid when *LOC was part of a value set when
10709 label_tick == TICK. Return 0 if some are not.
10711 If REPLACE is non-zero, replace the invalid reference with
10712 (clobber (const_int 0)) and return 1. This replacement is useful because
10713 we often can get useful information about the form of a value (e.g., if
10714 it was produced by a shift that always produces -1 or 0) even though
10715 we don't know exactly what registers it was produced from. */
10718 get_last_value_validate (loc, insn, tick, replace)
10725 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10726 int len = GET_RTX_LENGTH (GET_CODE (x));
10729 if (GET_CODE (x) == REG)
10731 int regno = REGNO (x);
10732 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10733 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10736 for (j = regno; j < endregno; j++)
10737 if (reg_last_set_invalid[j]
10738 /* If this is a pseudo-register that was only set once, it is
10740 || (! (regno >= FIRST_PSEUDO_REGISTER && REG_N_SETS (regno) == 1)
10741 && reg_last_set_label[j] > tick))
10744 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10750 /* If this is a memory reference, make sure that there were
10751 no stores after it that might have clobbered the value. We don't
10752 have alias info, so we assume any store invalidates it. */
10753 else if (GET_CODE (x) == MEM && ! RTX_UNCHANGING_P (x)
10754 && INSN_CUID (insn) <= mem_last_set)
10757 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10761 for (i = 0; i < len; i++)
10763 && get_last_value_validate (&XEXP (x, i), insn, tick, replace) == 0)
10764 /* Don't bother with these. They shouldn't occur anyway. */
10768 /* If we haven't found a reason for it to be invalid, it is valid. */
10772 /* Get the last value assigned to X, if known. Some registers
10773 in the value may be replaced with (clobber (const_int 0)) if their value
10774 is known longer known reliably. */
10783 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10784 then convert it to the desired mode. If this is a paradoxical SUBREG,
10785 we cannot predict what values the "extra" bits might have. */
10786 if (GET_CODE (x) == SUBREG
10787 && subreg_lowpart_p (x)
10788 && (GET_MODE_SIZE (GET_MODE (x))
10789 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10790 && (value = get_last_value (SUBREG_REG (x))) != 0)
10791 return gen_lowpart_for_combine (GET_MODE (x), value);
10793 if (GET_CODE (x) != REG)
10797 value = reg_last_set_value[regno];
10799 /* If we don't have a value or if it isn't for this basic block,
10803 || (REG_N_SETS (regno) != 1
10804 && reg_last_set_label[regno] != label_tick))
10807 /* If the value was set in a later insn than the ones we are processing,
10808 we can't use it even if the register was only set once, but make a quick
10809 check to see if the previous insn set it to something. This is commonly
10810 the case when the same pseudo is used by repeated insns.
10812 This does not work if there exists an instruction which is temporarily
10813 not on the insn chain. */
10815 if (INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)
10819 /* We can not do anything useful in this case, because there is
10820 an instruction which is not on the insn chain. */
10821 if (subst_prev_insn)
10824 /* Skip over USE insns. They are not useful here, and they may have
10825 been made by combine, in which case they do not have a INSN_CUID
10826 value. We can't use prev_real_insn, because that would incorrectly
10827 take us backwards across labels. Skip over BARRIERs also, since
10828 they could have been made by combine. If we see one, we must be
10829 optimizing dead code, so it doesn't matter what we do. */
10830 for (insn = prev_nonnote_insn (subst_insn);
10831 insn && ((GET_CODE (insn) == INSN
10832 && GET_CODE (PATTERN (insn)) == USE)
10833 || GET_CODE (insn) == BARRIER
10834 || INSN_CUID (insn) >= subst_low_cuid);
10835 insn = prev_nonnote_insn (insn))
10839 && (set = single_set (insn)) != 0
10840 && rtx_equal_p (SET_DEST (set), x))
10842 value = SET_SRC (set);
10844 /* Make sure that VALUE doesn't reference X. Replace any
10845 explicit references with a CLOBBER. If there are any remaining
10846 references (rare), don't use the value. */
10848 if (reg_mentioned_p (x, value))
10849 value = replace_rtx (copy_rtx (value), x,
10850 gen_rtx_CLOBBER (GET_MODE (x), const0_rtx));
10852 if (reg_overlap_mentioned_p (x, value))
10859 /* If the value has all its registers valid, return it. */
10860 if (get_last_value_validate (&value, reg_last_set[regno],
10861 reg_last_set_label[regno], 0))
10864 /* Otherwise, make a copy and replace any invalid register with
10865 (clobber (const_int 0)). If that fails for some reason, return 0. */
10867 value = copy_rtx (value);
10868 if (get_last_value_validate (&value, reg_last_set[regno],
10869 reg_last_set_label[regno], 1))
10875 /* Return nonzero if expression X refers to a REG or to memory
10876 that is set in an instruction more recent than FROM_CUID. */
10879 use_crosses_set_p (x, from_cuid)
10883 register char *fmt;
10885 register enum rtx_code code = GET_CODE (x);
10889 register int regno = REGNO (x);
10890 int endreg = regno + (regno < FIRST_PSEUDO_REGISTER
10891 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
10893 #ifdef PUSH_ROUNDING
10894 /* Don't allow uses of the stack pointer to be moved,
10895 because we don't know whether the move crosses a push insn. */
10896 if (regno == STACK_POINTER_REGNUM)
10899 for (;regno < endreg; regno++)
10900 if (reg_last_set[regno]
10901 && INSN_CUID (reg_last_set[regno]) > from_cuid)
10906 if (code == MEM && mem_last_set > from_cuid)
10909 fmt = GET_RTX_FORMAT (code);
10911 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10916 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
10917 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
10920 else if (fmt[i] == 'e'
10921 && use_crosses_set_p (XEXP (x, i), from_cuid))
10927 /* Define three variables used for communication between the following
10930 static int reg_dead_regno, reg_dead_endregno;
10931 static int reg_dead_flag;
10933 /* Function called via note_stores from reg_dead_at_p.
10935 If DEST is within [reg_dead_regno, reg_dead_endregno), set
10936 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
10939 reg_dead_at_p_1 (dest, x)
10943 int regno, endregno;
10945 if (GET_CODE (dest) != REG)
10948 regno = REGNO (dest);
10949 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
10950 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
10952 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
10953 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
10956 /* Return non-zero if REG is known to be dead at INSN.
10958 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
10959 referencing REG, it is dead. If we hit a SET referencing REG, it is
10960 live. Otherwise, see if it is live or dead at the start of the basic
10961 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
10962 must be assumed to be always live. */
10965 reg_dead_at_p (reg, insn)
10971 /* Set variables for reg_dead_at_p_1. */
10972 reg_dead_regno = REGNO (reg);
10973 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
10974 ? HARD_REGNO_NREGS (reg_dead_regno,
10980 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
10981 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
10983 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
10984 if (TEST_HARD_REG_BIT (newpat_used_regs, i))
10988 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
10989 beginning of function. */
10990 for (; insn && GET_CODE (insn) != CODE_LABEL && GET_CODE (insn) != BARRIER;
10991 insn = prev_nonnote_insn (insn))
10993 note_stores (PATTERN (insn), reg_dead_at_p_1);
10995 return reg_dead_flag == 1 ? 1 : 0;
10997 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11001 /* Get the basic block number that we were in. */
11006 for (block = 0; block < n_basic_blocks; block++)
11007 if (insn == BLOCK_HEAD (block))
11010 if (block == n_basic_blocks)
11014 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11015 if (REGNO_REG_SET_P (BASIC_BLOCK (block)->global_live_at_start, i))
11021 /* Note hard registers in X that are used. This code is similar to
11022 that in flow.c, but much simpler since we don't care about pseudos. */
11025 mark_used_regs_combine (x)
11028 register RTX_CODE code = GET_CODE (x);
11029 register int regno;
11041 case ADDR_DIFF_VEC:
11044 /* CC0 must die in the insn after it is set, so we don't need to take
11045 special note of it here. */
11051 /* If we are clobbering a MEM, mark any hard registers inside the
11052 address as used. */
11053 if (GET_CODE (XEXP (x, 0)) == MEM)
11054 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11059 /* A hard reg in a wide mode may really be multiple registers.
11060 If so, mark all of them just like the first. */
11061 if (regno < FIRST_PSEUDO_REGISTER)
11063 /* None of this applies to the stack, frame or arg pointers */
11064 if (regno == STACK_POINTER_REGNUM
11065 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11066 || regno == HARD_FRAME_POINTER_REGNUM
11068 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11069 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11071 || regno == FRAME_POINTER_REGNUM)
11074 i = HARD_REGNO_NREGS (regno, GET_MODE (x));
11076 SET_HARD_REG_BIT (newpat_used_regs, regno + i);
11082 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11084 register rtx testreg = SET_DEST (x);
11086 while (GET_CODE (testreg) == SUBREG
11087 || GET_CODE (testreg) == ZERO_EXTRACT
11088 || GET_CODE (testreg) == SIGN_EXTRACT
11089 || GET_CODE (testreg) == STRICT_LOW_PART)
11090 testreg = XEXP (testreg, 0);
11092 if (GET_CODE (testreg) == MEM)
11093 mark_used_regs_combine (XEXP (testreg, 0));
11095 mark_used_regs_combine (SET_SRC (x));
11103 /* Recursively scan the operands of this expression. */
11106 register char *fmt = GET_RTX_FORMAT (code);
11108 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11111 mark_used_regs_combine (XEXP (x, i));
11112 else if (fmt[i] == 'E')
11116 for (j = 0; j < XVECLEN (x, i); j++)
11117 mark_used_regs_combine (XVECEXP (x, i, j));
11124 /* Remove register number REGNO from the dead registers list of INSN.
11126 Return the note used to record the death, if there was one. */
11129 remove_death (regno, insn)
11133 register rtx note = find_regno_note (insn, REG_DEAD, regno);
11137 REG_N_DEATHS (regno)--;
11138 remove_note (insn, note);
11144 /* For each register (hardware or pseudo) used within expression X, if its
11145 death is in an instruction with cuid between FROM_CUID (inclusive) and
11146 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11147 list headed by PNOTES.
11149 That said, don't move registers killed by maybe_kill_insn.
11151 This is done when X is being merged by combination into TO_INSN. These
11152 notes will then be distributed as needed. */
11155 move_deaths (x, maybe_kill_insn, from_cuid, to_insn, pnotes)
11157 rtx maybe_kill_insn;
11162 register char *fmt;
11163 register int len, i;
11164 register enum rtx_code code = GET_CODE (x);
11168 register int regno = REGNO (x);
11169 register rtx where_dead = reg_last_death[regno];
11170 register rtx before_dead, after_dead;
11172 /* Don't move the register if it gets killed in between from and to */
11173 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11174 && !reg_referenced_p (x, maybe_kill_insn))
11177 /* WHERE_DEAD could be a USE insn made by combine, so first we
11178 make sure that we have insns with valid INSN_CUID values. */
11179 before_dead = where_dead;
11180 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11181 before_dead = PREV_INSN (before_dead);
11182 after_dead = where_dead;
11183 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11184 after_dead = NEXT_INSN (after_dead);
11186 if (before_dead && after_dead
11187 && INSN_CUID (before_dead) >= from_cuid
11188 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11189 || (where_dead != after_dead
11190 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11192 rtx note = remove_death (regno, where_dead);
11194 /* It is possible for the call above to return 0. This can occur
11195 when reg_last_death points to I2 or I1 that we combined with.
11196 In that case make a new note.
11198 We must also check for the case where X is a hard register
11199 and NOTE is a death note for a range of hard registers
11200 including X. In that case, we must put REG_DEAD notes for
11201 the remaining registers in place of NOTE. */
11203 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11204 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11205 > GET_MODE_SIZE (GET_MODE (x))))
11207 int deadregno = REGNO (XEXP (note, 0));
11209 = (deadregno + HARD_REGNO_NREGS (deadregno,
11210 GET_MODE (XEXP (note, 0))));
11211 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11214 for (i = deadregno; i < deadend; i++)
11215 if (i < regno || i >= ourend)
11216 REG_NOTES (where_dead)
11217 = gen_rtx_EXPR_LIST (REG_DEAD,
11218 gen_rtx_REG (reg_raw_mode[i], i),
11219 REG_NOTES (where_dead));
11221 /* If we didn't find any note, or if we found a REG_DEAD note that
11222 covers only part of the given reg, and we have a multi-reg hard
11223 register, then to be safe we must check for REG_DEAD notes
11224 for each register other than the first. They could have
11225 their own REG_DEAD notes lying around. */
11226 else if ((note == 0
11228 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11229 < GET_MODE_SIZE (GET_MODE (x)))))
11230 && regno < FIRST_PSEUDO_REGISTER
11231 && HARD_REGNO_NREGS (regno, GET_MODE (x)) > 1)
11233 int ourend = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11238 offset = HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0)));
11242 for (i = regno + offset; i < ourend; i++)
11243 move_deaths (gen_rtx_REG (reg_raw_mode[i], i),
11244 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11247 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11249 XEXP (note, 1) = *pnotes;
11253 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11255 REG_N_DEATHS (regno)++;
11261 else if (GET_CODE (x) == SET)
11263 rtx dest = SET_DEST (x);
11265 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11267 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11268 that accesses one word of a multi-word item, some
11269 piece of everything register in the expression is used by
11270 this insn, so remove any old death. */
11272 if (GET_CODE (dest) == ZERO_EXTRACT
11273 || GET_CODE (dest) == STRICT_LOW_PART
11274 || (GET_CODE (dest) == SUBREG
11275 && (((GET_MODE_SIZE (GET_MODE (dest))
11276 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11277 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11278 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11280 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11284 /* If this is some other SUBREG, we know it replaces the entire
11285 value, so use that as the destination. */
11286 if (GET_CODE (dest) == SUBREG)
11287 dest = SUBREG_REG (dest);
11289 /* If this is a MEM, adjust deaths of anything used in the address.
11290 For a REG (the only other possibility), the entire value is
11291 being replaced so the old value is not used in this insn. */
11293 if (GET_CODE (dest) == MEM)
11294 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11299 else if (GET_CODE (x) == CLOBBER)
11302 len = GET_RTX_LENGTH (code);
11303 fmt = GET_RTX_FORMAT (code);
11305 for (i = 0; i < len; i++)
11310 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11311 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11314 else if (fmt[i] == 'e')
11315 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11319 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11320 pattern of an insn. X must be a REG. */
11323 reg_bitfield_target_p (x, body)
11329 if (GET_CODE (body) == SET)
11331 rtx dest = SET_DEST (body);
11333 int regno, tregno, endregno, endtregno;
11335 if (GET_CODE (dest) == ZERO_EXTRACT)
11336 target = XEXP (dest, 0);
11337 else if (GET_CODE (dest) == STRICT_LOW_PART)
11338 target = SUBREG_REG (XEXP (dest, 0));
11342 if (GET_CODE (target) == SUBREG)
11343 target = SUBREG_REG (target);
11345 if (GET_CODE (target) != REG)
11348 tregno = REGNO (target), regno = REGNO (x);
11349 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11350 return target == x;
11352 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
11353 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
11355 return endregno > tregno && regno < endtregno;
11358 else if (GET_CODE (body) == PARALLEL)
11359 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11360 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11366 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11367 as appropriate. I3 and I2 are the insns resulting from the combination
11368 insns including FROM (I2 may be zero).
11370 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11371 not need REG_DEAD notes because they are being substituted for. This
11372 saves searching in the most common cases.
11374 Each note in the list is either ignored or placed on some insns, depending
11375 on the type of note. */
11378 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
11382 rtx elim_i2, elim_i1;
11384 rtx note, next_note;
11387 for (note = notes; note; note = next_note)
11389 rtx place = 0, place2 = 0;
11391 /* If this NOTE references a pseudo register, ensure it references
11392 the latest copy of that register. */
11393 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
11394 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11395 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11397 next_note = XEXP (note, 1);
11398 switch (REG_NOTE_KIND (note))
11401 case REG_EXEC_COUNT:
11402 /* Doesn't matter much where we put this, as long as it's somewhere.
11403 It is preferable to keep these notes on branches, which is most
11404 likely to be i3. */
11408 case REG_EH_REGION:
11409 /* This note must remain with the call. It should not be possible
11410 for both I2 and I3 to be a call. */
11411 if (GET_CODE (i3) == CALL_INSN)
11413 else if (i2 && GET_CODE (i2) == CALL_INSN)
11420 /* Any clobbers for i3 may still exist, and so we must process
11421 REG_UNUSED notes from that insn.
11423 Any clobbers from i2 or i1 can only exist if they were added by
11424 recog_for_combine. In that case, recog_for_combine created the
11425 necessary REG_UNUSED notes. Trying to keep any original
11426 REG_UNUSED notes from these insns can cause incorrect output
11427 if it is for the same register as the original i3 dest.
11428 In that case, we will notice that the register is set in i3,
11429 and then add a REG_UNUSED note for the destination of i3, which
11430 is wrong. However, it is possible to have REG_UNUSED notes from
11431 i2 or i1 for register which were both used and clobbered, so
11432 we keep notes from i2 or i1 if they will turn into REG_DEAD
11435 /* If this register is set or clobbered in I3, put the note there
11436 unless there is one already. */
11437 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11439 if (from_insn != i3)
11442 if (! (GET_CODE (XEXP (note, 0)) == REG
11443 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11444 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11447 /* Otherwise, if this register is used by I3, then this register
11448 now dies here, so we must put a REG_DEAD note here unless there
11450 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11451 && ! (GET_CODE (XEXP (note, 0)) == REG
11452 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
11453 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11455 PUT_REG_NOTE_KIND (note, REG_DEAD);
11464 /* These notes say something about results of an insn. We can
11465 only support them if they used to be on I3 in which case they
11466 remain on I3. Otherwise they are ignored.
11468 If the note refers to an expression that is not a constant, we
11469 must also ignore the note since we cannot tell whether the
11470 equivalence is still true. It might be possible to do
11471 slightly better than this (we only have a problem if I2DEST
11472 or I1DEST is present in the expression), but it doesn't
11473 seem worth the trouble. */
11475 if (from_insn == i3
11476 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11481 case REG_NO_CONFLICT:
11482 /* These notes say something about how a register is used. They must
11483 be present on any use of the register in I2 or I3. */
11484 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11487 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11497 /* This can show up in several ways -- either directly in the
11498 pattern, or hidden off in the constant pool with (or without?)
11499 a REG_EQUAL note. */
11500 /* ??? Ignore the without-reg_equal-note problem for now. */
11501 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11502 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11503 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11504 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11508 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11509 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11510 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11511 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11521 /* It is too much trouble to try to see if this note is still
11522 correct in all situations. It is better to simply delete it. */
11526 /* If the insn previously containing this note still exists,
11527 put it back where it was. Otherwise move it to the previous
11528 insn. Adjust the corresponding REG_LIBCALL note. */
11529 if (GET_CODE (from_insn) != NOTE)
11533 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11534 place = prev_real_insn (from_insn);
11536 XEXP (tem, 0) = place;
11541 /* This is handled similarly to REG_RETVAL. */
11542 if (GET_CODE (from_insn) != NOTE)
11546 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11547 place = next_real_insn (from_insn);
11549 XEXP (tem, 0) = place;
11554 /* If the register is used as an input in I3, it dies there.
11555 Similarly for I2, if it is non-zero and adjacent to I3.
11557 If the register is not used as an input in either I3 or I2
11558 and it is not one of the registers we were supposed to eliminate,
11559 there are two possibilities. We might have a non-adjacent I2
11560 or we might have somehow eliminated an additional register
11561 from a computation. For example, we might have had A & B where
11562 we discover that B will always be zero. In this case we will
11563 eliminate the reference to A.
11565 In both cases, we must search to see if we can find a previous
11566 use of A and put the death note there. */
11569 && GET_CODE (from_insn) == CALL_INSN
11570 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11572 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11574 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11575 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11578 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
11581 /* If the register is used in both I2 and I3 and it dies in I3,
11582 we might have added another reference to it. If reg_n_refs
11583 was 2, bump it to 3. This has to be correct since the
11584 register must have been set somewhere. The reason this is
11585 done is because local-alloc.c treats 2 references as a
11588 if (place == i3 && i2 != 0 && GET_CODE (XEXP (note, 0)) == REG
11589 && REG_N_REFS (REGNO (XEXP (note, 0)))== 2
11590 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11591 REG_N_REFS (REGNO (XEXP (note, 0))) = 3;
11595 for (tem = prev_nonnote_insn (i3);
11597 && (GET_CODE (tem) == INSN || GET_CODE (tem) == CALL_INSN);
11598 tem = prev_nonnote_insn (tem))
11600 /* If the register is being set at TEM, see if that is all
11601 TEM is doing. If so, delete TEM. Otherwise, make this
11602 into a REG_UNUSED note instead. */
11603 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
11605 rtx set = single_set (tem);
11606 rtx inner_dest = 0;
11608 rtx cc0_setter = NULL_RTX;
11612 for (inner_dest = SET_DEST (set);
11613 GET_CODE (inner_dest) == STRICT_LOW_PART
11614 || GET_CODE (inner_dest) == SUBREG
11615 || GET_CODE (inner_dest) == ZERO_EXTRACT;
11616 inner_dest = XEXP (inner_dest, 0))
11619 /* Verify that it was the set, and not a clobber that
11620 modified the register.
11622 CC0 targets must be careful to maintain setter/user
11623 pairs. If we cannot delete the setter due to side
11624 effects, mark the user with an UNUSED note instead
11627 if (set != 0 && ! side_effects_p (SET_SRC (set))
11628 && rtx_equal_p (XEXP (note, 0), inner_dest)
11630 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11631 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11632 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11636 /* Move the notes and links of TEM elsewhere.
11637 This might delete other dead insns recursively.
11638 First set the pattern to something that won't use
11641 PATTERN (tem) = pc_rtx;
11643 distribute_notes (REG_NOTES (tem), tem, tem,
11644 NULL_RTX, NULL_RTX, NULL_RTX);
11645 distribute_links (LOG_LINKS (tem));
11647 PUT_CODE (tem, NOTE);
11648 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
11649 NOTE_SOURCE_FILE (tem) = 0;
11652 /* Delete the setter too. */
11655 PATTERN (cc0_setter) = pc_rtx;
11657 distribute_notes (REG_NOTES (cc0_setter),
11658 cc0_setter, cc0_setter,
11659 NULL_RTX, NULL_RTX, NULL_RTX);
11660 distribute_links (LOG_LINKS (cc0_setter));
11662 PUT_CODE (cc0_setter, NOTE);
11663 NOTE_LINE_NUMBER (cc0_setter) = NOTE_INSN_DELETED;
11664 NOTE_SOURCE_FILE (cc0_setter) = 0;
11668 /* If the register is both set and used here, put the
11669 REG_DEAD note here, but place a REG_UNUSED note
11670 here too unless there already is one. */
11671 else if (reg_referenced_p (XEXP (note, 0),
11676 if (! find_regno_note (tem, REG_UNUSED,
11677 REGNO (XEXP (note, 0))))
11679 = gen_rtx_EXPR_LIST (REG_UNUSED,
11685 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11687 /* If there isn't already a REG_UNUSED note, put one
11689 if (! find_regno_note (tem, REG_UNUSED,
11690 REGNO (XEXP (note, 0))))
11695 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11696 || (GET_CODE (tem) == CALL_INSN
11697 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11701 /* If we are doing a 3->2 combination, and we have a
11702 register which formerly died in i3 and was not used
11703 by i2, which now no longer dies in i3 and is used in
11704 i2 but does not die in i2, and place is between i2
11705 and i3, then we may need to move a link from place to
11707 if (i2 && INSN_UID (place) <= max_uid_cuid
11708 && INSN_CUID (place) > INSN_CUID (i2)
11709 && from_insn && INSN_CUID (from_insn) > INSN_CUID (i2)
11710 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11712 rtx links = LOG_LINKS (place);
11713 LOG_LINKS (place) = 0;
11714 distribute_links (links);
11720 /* If we haven't found an insn for the death note and it
11721 is still a REG_DEAD note, but we have hit a CODE_LABEL,
11722 insert a USE insn for the register at that label and
11723 put the death node there. This prevents problems with
11724 call-state tracking in caller-save.c. */
11725 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0 && tem != 0)
11728 = emit_insn_after (gen_rtx_USE (VOIDmode, XEXP (note, 0)),
11731 /* If this insn was emitted between blocks, then update
11732 BLOCK_HEAD of the current block to include it. */
11733 if (BLOCK_END (this_basic_block - 1) == tem)
11734 BLOCK_HEAD (this_basic_block) = place;
11738 /* If the register is set or already dead at PLACE, we needn't do
11739 anything with this note if it is still a REG_DEAD note.
11740 We can here if it is set at all, not if is it totally replace,
11741 which is what `dead_or_set_p' checks, so also check for it being
11745 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11747 int regno = REGNO (XEXP (note, 0));
11749 if (dead_or_set_p (place, XEXP (note, 0))
11750 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11752 /* Unless the register previously died in PLACE, clear
11753 reg_last_death. [I no longer understand why this is
11755 if (reg_last_death[regno] != place)
11756 reg_last_death[regno] = 0;
11760 reg_last_death[regno] = place;
11762 /* If this is a death note for a hard reg that is occupying
11763 multiple registers, ensure that we are still using all
11764 parts of the object. If we find a piece of the object
11765 that is unused, we must add a USE for that piece before
11766 PLACE and put the appropriate REG_DEAD note on it.
11768 An alternative would be to put a REG_UNUSED for the pieces
11769 on the insn that set the register, but that can't be done if
11770 it is not in the same block. It is simpler, though less
11771 efficient, to add the USE insns. */
11773 if (place && regno < FIRST_PSEUDO_REGISTER
11774 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
11777 = regno + HARD_REGNO_NREGS (regno,
11778 GET_MODE (XEXP (note, 0)));
11782 for (i = regno; i < endregno; i++)
11783 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
11784 && ! find_regno_fusage (place, USE, i))
11786 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11789 /* See if we already placed a USE note for this
11790 register in front of PLACE. */
11792 GET_CODE (PREV_INSN (p)) == INSN
11793 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
11795 if (rtx_equal_p (piece,
11796 XEXP (PATTERN (PREV_INSN (p)), 0)))
11805 = emit_insn_before (gen_rtx_USE (VOIDmode,
11808 REG_NOTES (use_insn)
11809 = gen_rtx_EXPR_LIST (REG_DEAD, piece,
11810 REG_NOTES (use_insn));
11816 /* Check for the case where the register dying partially
11817 overlaps the register set by this insn. */
11819 for (i = regno; i < endregno; i++)
11820 if (dead_or_set_regno_p (place, i))
11828 /* Put only REG_DEAD notes for pieces that are
11829 still used and that are not already dead or set. */
11831 for (i = regno; i < endregno; i++)
11833 rtx piece = gen_rtx_REG (reg_raw_mode[i], i);
11835 if ((reg_referenced_p (piece, PATTERN (place))
11836 || (GET_CODE (place) == CALL_INSN
11837 && find_reg_fusage (place, USE, piece)))
11838 && ! dead_or_set_p (place, piece)
11839 && ! reg_bitfield_target_p (piece,
11842 = gen_rtx_EXPR_LIST (REG_DEAD,
11843 piece, REG_NOTES (place));
11853 /* Any other notes should not be present at this point in the
11860 XEXP (note, 1) = REG_NOTES (place);
11861 REG_NOTES (place) = note;
11863 else if ((REG_NOTE_KIND (note) == REG_DEAD
11864 || REG_NOTE_KIND (note) == REG_UNUSED)
11865 && GET_CODE (XEXP (note, 0)) == REG)
11866 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
11870 if ((REG_NOTE_KIND (note) == REG_DEAD
11871 || REG_NOTE_KIND (note) == REG_UNUSED)
11872 && GET_CODE (XEXP (note, 0)) == REG)
11873 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
11875 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
11876 REG_NOTE_KIND (note),
11878 REG_NOTES (place2));
11883 /* Similarly to above, distribute the LOG_LINKS that used to be present on
11884 I3, I2, and I1 to new locations. This is also called in one case to
11885 add a link pointing at I3 when I3's destination is changed. */
11888 distribute_links (links)
11891 rtx link, next_link;
11893 for (link = links; link; link = next_link)
11899 next_link = XEXP (link, 1);
11901 /* If the insn that this link points to is a NOTE or isn't a single
11902 set, ignore it. In the latter case, it isn't clear what we
11903 can do other than ignore the link, since we can't tell which
11904 register it was for. Such links wouldn't be used by combine
11907 It is not possible for the destination of the target of the link to
11908 have been changed by combine. The only potential of this is if we
11909 replace I3, I2, and I1 by I3 and I2. But in that case the
11910 destination of I2 also remains unchanged. */
11912 if (GET_CODE (XEXP (link, 0)) == NOTE
11913 || (set = single_set (XEXP (link, 0))) == 0)
11916 reg = SET_DEST (set);
11917 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
11918 || GET_CODE (reg) == SIGN_EXTRACT
11919 || GET_CODE (reg) == STRICT_LOW_PART)
11920 reg = XEXP (reg, 0);
11922 /* A LOG_LINK is defined as being placed on the first insn that uses
11923 a register and points to the insn that sets the register. Start
11924 searching at the next insn after the target of the link and stop
11925 when we reach a set of the register or the end of the basic block.
11927 Note that this correctly handles the link that used to point from
11928 I3 to I2. Also note that not much searching is typically done here
11929 since most links don't point very far away. */
11931 for (insn = NEXT_INSN (XEXP (link, 0));
11932 (insn && (this_basic_block == n_basic_blocks - 1
11933 || BLOCK_HEAD (this_basic_block + 1) != insn));
11934 insn = NEXT_INSN (insn))
11935 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
11936 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
11938 if (reg_referenced_p (reg, PATTERN (insn)))
11942 else if (GET_CODE (insn) == CALL_INSN
11943 && find_reg_fusage (insn, USE, reg))
11949 /* If we found a place to put the link, place it there unless there
11950 is already a link to the same insn as LINK at that point. */
11956 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
11957 if (XEXP (link2, 0) == XEXP (link, 0))
11962 XEXP (link, 1) = LOG_LINKS (place);
11963 LOG_LINKS (place) = link;
11965 /* Set added_links_insn to the earliest insn we added a
11967 if (added_links_insn == 0
11968 || INSN_CUID (added_links_insn) > INSN_CUID (place))
11969 added_links_insn = place;
11975 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
11981 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
11982 && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == USE)
11983 insn = NEXT_INSN (insn);
11985 if (INSN_UID (insn) > max_uid_cuid)
11988 return INSN_CUID (insn);
11992 dump_combine_stats (file)
11997 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
11998 combine_attempts, combine_merges, combine_extras, combine_successes);
12002 dump_combine_total_stats (file)
12007 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12008 total_attempts, total_merges, total_extras, total_successes);