1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
4 2011, 2012 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
95 #include "diagnostic-core.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as struct insn_link pointers. */
317 struct insn_link *next;
320 static struct insn_link **uid_log_links;
322 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
323 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
325 #define FOR_EACH_LOG_LINK(L, INSN) \
326 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
328 /* Links for LOG_LINKS are allocated from this obstack. */
330 static struct obstack insn_link_obstack;
332 /* Allocate a link. */
334 static inline struct insn_link *
335 alloc_insn_link (rtx insn, struct insn_link *next)
338 = (struct insn_link *) obstack_alloc (&insn_link_obstack,
339 sizeof (struct insn_link));
345 /* Incremented for each basic block. */
347 static int label_tick;
349 /* Reset to label_tick for each extended basic block in scanning order. */
351 static int label_tick_ebb_start;
353 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
354 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
356 static enum machine_mode nonzero_bits_mode;
358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
359 be safely used. It is zero while computing them and after combine has
360 completed. This former test prevents propagating values based on
361 previously set values, which can be incorrect if a variable is modified
364 static int nonzero_sign_valid;
367 /* Record one modification to rtl structure
368 to be undone by storing old_contents into *where. */
370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
376 union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
377 union { rtx *r; int *i; struct insn_link **l; } where;
380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
381 num_undo says how many are currently recorded.
383 other_insn is nonzero if we have modified some other insn in the process
384 of working on subst_insn. It must be verified too. */
393 static struct undobuf undobuf;
395 /* Number of times the pseudo being substituted for
396 was found and replaced. */
398 static int n_occurrences;
400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
402 unsigned HOST_WIDE_INT,
403 unsigned HOST_WIDE_INT *);
404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
406 unsigned int, unsigned int *);
407 static void do_SUBST (rtx *, rtx);
408 static void do_SUBST_INT (int *, int);
409 static void init_reg_last (void);
410 static void setup_incoming_promotions (rtx);
411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
412 static int cant_combine_insn_p (rtx);
413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
415 static int contains_muldiv (rtx);
416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
417 static void undo_all (void);
418 static void undo_commit (void);
419 static rtx *find_split_point (rtx *, rtx, bool);
420 static rtx subst (rtx, rtx, rtx, int, int, int);
421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
422 static rtx simplify_if_then_else (rtx);
423 static rtx simplify_set (rtx);
424 static rtx simplify_logical (rtx);
425 static rtx expand_compound_operation (rtx);
426 static const_rtx expand_field_assignment (const_rtx);
427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
428 rtx, unsigned HOST_WIDE_INT, int, int, int);
429 static rtx extract_left_shift (rtx, int);
430 static rtx make_compound_operation (rtx, enum rtx_code);
431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
432 unsigned HOST_WIDE_INT *);
433 static rtx canon_reg_for_combine (rtx, rtx);
434 static rtx force_to_mode (rtx, enum machine_mode,
435 unsigned HOST_WIDE_INT, int);
436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
439 static rtx make_field_assignment (rtx);
440 static rtx apply_distributive_law (rtx);
441 static rtx distribute_and_simplify_rtx (rtx, int);
442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
443 unsigned HOST_WIDE_INT);
444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
445 unsigned HOST_WIDE_INT);
446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
447 HOST_WIDE_INT, enum machine_mode, int *);
448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
451 static int recog_for_combine (rtx *, rtx, rtx *);
452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
453 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
454 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
455 static void update_table_tick (rtx);
456 static void record_value_for_reg (rtx, rtx, rtx);
457 static void check_promoted_subreg (rtx, rtx);
458 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
459 static void record_dead_and_set_regs (rtx);
460 static int get_last_value_validate (rtx *, rtx, int, int);
461 static rtx get_last_value (const_rtx);
462 static int use_crosses_set_p (const_rtx, int);
463 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
464 static int reg_dead_at_p (rtx, rtx);
465 static void move_deaths (rtx, rtx, int, rtx, rtx *);
466 static int reg_bitfield_target_p (rtx, rtx);
467 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
468 static void distribute_links (struct insn_link *);
469 static void mark_used_regs_combine (rtx);
470 static void record_promoted_value (rtx, rtx);
471 static int unmentioned_reg_p_1 (rtx *, void *);
472 static bool unmentioned_reg_p (rtx, rtx);
473 static int record_truncated_value (rtx *, void *);
474 static void record_truncated_values (rtx *, void *);
475 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
476 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
479 /* It is not safe to use ordinary gen_lowpart in combine.
480 See comments in gen_lowpart_for_combine. */
481 #undef RTL_HOOKS_GEN_LOWPART
482 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
484 /* Our implementation of gen_lowpart never emits a new pseudo. */
485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
489 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
497 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
500 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
501 PATTERN can not be split. Otherwise, it returns an insn sequence.
502 This is a wrapper around split_insns which ensures that the
503 reg_stat vector is made larger if the splitter creates a new
507 combine_split_insns (rtx pattern, rtx insn)
512 ret = split_insns (pattern, insn);
513 nregs = max_reg_num ();
514 if (nregs > VEC_length (reg_stat_type, reg_stat))
515 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
519 /* This is used by find_single_use to locate an rtx in LOC that
520 contains exactly one use of DEST, which is typically either a REG
521 or CC0. It returns a pointer to the innermost rtx expression
522 containing DEST. Appearances of DEST that are being used to
523 totally replace it are not counted. */
526 find_single_use_1 (rtx dest, rtx *loc)
529 enum rtx_code code = GET_CODE (x);
547 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
548 of a REG that occupies all of the REG, the insn uses DEST if
549 it is mentioned in the destination or the source. Otherwise, we
550 need just check the source. */
551 if (GET_CODE (SET_DEST (x)) != CC0
552 && GET_CODE (SET_DEST (x)) != PC
553 && !REG_P (SET_DEST (x))
554 && ! (GET_CODE (SET_DEST (x)) == SUBREG
555 && REG_P (SUBREG_REG (SET_DEST (x)))
556 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
557 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
558 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
559 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
562 return find_single_use_1 (dest, &SET_SRC (x));
566 return find_single_use_1 (dest, &XEXP (x, 0));
572 /* If it wasn't one of the common cases above, check each expression and
573 vector of this code. Look for a unique usage of DEST. */
575 fmt = GET_RTX_FORMAT (code);
576 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
580 if (dest == XEXP (x, i)
581 || (REG_P (dest) && REG_P (XEXP (x, i))
582 && REGNO (dest) == REGNO (XEXP (x, i))))
585 this_result = find_single_use_1 (dest, &XEXP (x, i));
588 result = this_result;
589 else if (this_result)
590 /* Duplicate usage. */
593 else if (fmt[i] == 'E')
597 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
599 if (XVECEXP (x, i, j) == dest
601 && REG_P (XVECEXP (x, i, j))
602 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
605 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
608 result = this_result;
609 else if (this_result)
619 /* See if DEST, produced in INSN, is used only a single time in the
620 sequel. If so, return a pointer to the innermost rtx expression in which
623 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
625 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
626 care about REG_DEAD notes or LOG_LINKS.
628 Otherwise, we find the single use by finding an insn that has a
629 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
630 only referenced once in that insn, we know that it must be the first
631 and last insn referencing DEST. */
634 find_single_use (rtx dest, rtx insn, rtx *ploc)
639 struct insn_link *link;
644 next = NEXT_INSN (insn);
646 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
649 result = find_single_use_1 (dest, &PATTERN (next));
659 bb = BLOCK_FOR_INSN (insn);
660 for (next = NEXT_INSN (insn);
661 next && BLOCK_FOR_INSN (next) == bb;
662 next = NEXT_INSN (next))
663 if (INSN_P (next) && dead_or_set_p (next, dest))
665 FOR_EACH_LOG_LINK (link, next)
666 if (link->insn == insn)
671 result = find_single_use_1 (dest, &PATTERN (next));
681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
682 insn. The substitution can be undone by undo_all. If INTO is already
683 set to NEWVAL, do not record this change. Because computing NEWVAL might
684 also call SUBST, we have to compute it before we put anything into
688 do_SUBST (rtx *into, rtx newval)
693 if (oldval == newval)
696 /* We'd like to catch as many invalid transformations here as
697 possible. Unfortunately, there are way too many mode changes
698 that are perfectly valid, so we'd waste too much effort for
699 little gain doing the checks here. Focus on catching invalid
700 transformations involving integer constants. */
701 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
702 && CONST_INT_P (newval))
704 /* Sanity check that we're replacing oldval with a CONST_INT
705 that is a valid sign-extension for the original mode. */
706 gcc_assert (INTVAL (newval)
707 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
709 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
710 CONST_INT is not valid, because after the replacement, the
711 original mode would be gone. Unfortunately, we can't tell
712 when do_SUBST is called to replace the operand thereof, so we
713 perform this test on oldval instead, checking whether an
714 invalid replacement took place before we got here. */
715 gcc_assert (!(GET_CODE (oldval) == SUBREG
716 && CONST_INT_P (SUBREG_REG (oldval))));
717 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
718 && CONST_INT_P (XEXP (oldval, 0))));
722 buf = undobuf.frees, undobuf.frees = buf->next;
724 buf = XNEW (struct undo);
726 buf->kind = UNDO_RTX;
728 buf->old_contents.r = oldval;
731 buf->next = undobuf.undos, undobuf.undos = buf;
734 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
736 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
737 for the value of a HOST_WIDE_INT value (including CONST_INT) is
741 do_SUBST_INT (int *into, int newval)
746 if (oldval == newval)
750 buf = undobuf.frees, undobuf.frees = buf->next;
752 buf = XNEW (struct undo);
754 buf->kind = UNDO_INT;
756 buf->old_contents.i = oldval;
759 buf->next = undobuf.undos, undobuf.undos = buf;
762 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
764 /* Similar to SUBST, but just substitute the mode. This is used when
765 changing the mode of a pseudo-register, so that any other
766 references to the entry in the regno_reg_rtx array will change as
770 do_SUBST_MODE (rtx *into, enum machine_mode newval)
773 enum machine_mode oldval = GET_MODE (*into);
775 if (oldval == newval)
779 buf = undobuf.frees, undobuf.frees = buf->next;
781 buf = XNEW (struct undo);
783 buf->kind = UNDO_MODE;
785 buf->old_contents.m = oldval;
786 adjust_reg_mode (*into, newval);
788 buf->next = undobuf.undos, undobuf.undos = buf;
791 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
794 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
797 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
800 struct insn_link * oldval = *into;
802 if (oldval == newval)
806 buf = undobuf.frees, undobuf.frees = buf->next;
808 buf = XNEW (struct undo);
810 buf->kind = UNDO_LINKS;
812 buf->old_contents.l = oldval;
815 buf->next = undobuf.undos, undobuf.undos = buf;
818 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
821 /* Subroutine of try_combine. Determine whether the replacement patterns
822 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
823 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
824 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
825 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
826 of all the instructions can be estimated and the replacements are more
827 expensive than the original sequence. */
830 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
831 rtx newi2pat, rtx newotherpat)
833 int i0_cost, i1_cost, i2_cost, i3_cost;
834 int new_i2_cost, new_i3_cost;
835 int old_cost, new_cost;
837 /* Lookup the original insn_rtx_costs. */
838 i2_cost = INSN_COST (i2);
839 i3_cost = INSN_COST (i3);
843 i1_cost = INSN_COST (i1);
846 i0_cost = INSN_COST (i0);
847 old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
848 ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
852 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
853 ? i1_cost + i2_cost + i3_cost : 0);
859 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
860 i1_cost = i0_cost = 0;
863 /* Calculate the replacement insn_rtx_costs. */
864 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
867 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
868 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
869 ? new_i2_cost + new_i3_cost : 0;
873 new_cost = new_i3_cost;
877 if (undobuf.other_insn)
879 int old_other_cost, new_other_cost;
881 old_other_cost = INSN_COST (undobuf.other_insn);
882 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
883 if (old_other_cost > 0 && new_other_cost > 0)
885 old_cost += old_other_cost;
886 new_cost += new_other_cost;
892 /* Disallow this combination if both new_cost and old_cost are greater than
893 zero, and new_cost is greater than old cost. */
894 if (old_cost > 0 && new_cost > old_cost)
901 "rejecting combination of insns %d, %d, %d and %d\n",
902 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
904 fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
905 i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
910 "rejecting combination of insns %d, %d and %d\n",
911 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
912 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
913 i1_cost, i2_cost, i3_cost, old_cost);
918 "rejecting combination of insns %d and %d\n",
919 INSN_UID (i2), INSN_UID (i3));
920 fprintf (dump_file, "original costs %d + %d = %d\n",
921 i2_cost, i3_cost, old_cost);
926 fprintf (dump_file, "replacement costs %d + %d = %d\n",
927 new_i2_cost, new_i3_cost, new_cost);
930 fprintf (dump_file, "replacement cost %d\n", new_cost);
936 /* Update the uid_insn_cost array with the replacement costs. */
937 INSN_COST (i2) = new_i2_cost;
938 INSN_COST (i3) = new_i3_cost;
950 /* Delete any insns that copy a register to itself. */
953 delete_noop_moves (void)
960 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
962 next = NEXT_INSN (insn);
963 if (INSN_P (insn) && noop_move_p (insn))
966 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
968 delete_insn_and_edges (insn);
975 /* Fill in log links field for all insns. */
978 create_log_links (void)
982 df_ref *def_vec, *use_vec;
984 next_use = XCNEWVEC (rtx, max_reg_num ());
986 /* Pass through each block from the end, recording the uses of each
987 register and establishing log links when def is encountered.
988 Note that we do not clear next_use array in order to save time,
989 so we have to test whether the use is in the same basic block as def.
991 There are a few cases below when we do not consider the definition or
992 usage -- these are taken from original flow.c did. Don't ask me why it is
993 done this way; I don't know and if it works, I don't want to know. */
997 FOR_BB_INSNS_REVERSE (bb, insn)
999 if (!NONDEBUG_INSN_P (insn))
1002 /* Log links are created only once. */
1003 gcc_assert (!LOG_LINKS (insn));
1005 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1007 df_ref def = *def_vec;
1008 int regno = DF_REF_REGNO (def);
1011 if (!next_use[regno])
1014 /* Do not consider if it is pre/post modification in MEM. */
1015 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1018 /* Do not make the log link for frame pointer. */
1019 if ((regno == FRAME_POINTER_REGNUM
1020 && (! reload_completed || frame_pointer_needed))
1021 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1022 || (regno == HARD_FRAME_POINTER_REGNUM
1023 && (! reload_completed || frame_pointer_needed))
1025 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1026 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1031 use_insn = next_use[regno];
1032 if (BLOCK_FOR_INSN (use_insn) == bb)
1036 We don't build a LOG_LINK for hard registers contained
1037 in ASM_OPERANDs. If these registers get replaced,
1038 we might wind up changing the semantics of the insn,
1039 even if reload can make what appear to be valid
1040 assignments later. */
1041 if (regno >= FIRST_PSEUDO_REGISTER
1042 || asm_noperands (PATTERN (use_insn)) < 0)
1044 /* Don't add duplicate links between instructions. */
1045 struct insn_link *links;
1046 FOR_EACH_LOG_LINK (links, use_insn)
1047 if (insn == links->insn)
1051 LOG_LINKS (use_insn)
1052 = alloc_insn_link (insn, LOG_LINKS (use_insn));
1055 next_use[regno] = NULL_RTX;
1058 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1060 df_ref use = *use_vec;
1061 int regno = DF_REF_REGNO (use);
1063 /* Do not consider the usage of the stack pointer
1064 by function call. */
1065 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1068 next_use[regno] = insn;
1076 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1077 true if we found a LOG_LINK that proves that A feeds B. This only works
1078 if there are no instructions between A and B which could have a link
1079 depending on A, since in that case we would not record a link for B.
1080 We also check the implicit dependency created by a cc0 setter/user
1084 insn_a_feeds_b (rtx a, rtx b)
1086 struct insn_link *links;
1087 FOR_EACH_LOG_LINK (links, b)
1088 if (links->insn == a)
1097 /* Main entry point for combiner. F is the first insn of the function.
1098 NREGS is the first unused pseudo-reg number.
1100 Return nonzero if the combiner has turned an indirect jump
1101 instruction into a direct jump. */
1103 combine_instructions (rtx f, unsigned int nregs)
1109 struct insn_link *links, *nextlinks;
1111 basic_block last_bb;
1113 int new_direct_jump_p = 0;
1115 for (first = f; first && !INSN_P (first); )
1116 first = NEXT_INSN (first);
1120 combine_attempts = 0;
1123 combine_successes = 0;
1125 rtl_hooks = combine_rtl_hooks;
1127 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1129 init_recog_no_volatile ();
1131 /* Allocate array for insn info. */
1132 max_uid_known = get_max_uid ();
1133 uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1134 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1135 gcc_obstack_init (&insn_link_obstack);
1137 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1139 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1140 problems when, for example, we have j <<= 1 in a loop. */
1142 nonzero_sign_valid = 0;
1143 label_tick = label_tick_ebb_start = 1;
1145 /* Scan all SETs and see if we can deduce anything about what
1146 bits are known to be zero for some registers and how many copies
1147 of the sign bit are known to exist for those registers.
1149 Also set any known values so that we can use it while searching
1150 for what bits are known to be set. */
1152 setup_incoming_promotions (first);
1153 /* Allow the entry block and the first block to fall into the same EBB.
1154 Conceptually the incoming promotions are assigned to the entry block. */
1155 last_bb = ENTRY_BLOCK_PTR;
1157 create_log_links ();
1158 FOR_EACH_BB (this_basic_block)
1160 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1165 if (!single_pred_p (this_basic_block)
1166 || single_pred (this_basic_block) != last_bb)
1167 label_tick_ebb_start = label_tick;
1168 last_bb = this_basic_block;
1170 FOR_BB_INSNS (this_basic_block, insn)
1171 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1177 subst_low_luid = DF_INSN_LUID (insn);
1180 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1182 record_dead_and_set_regs (insn);
1185 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1186 if (REG_NOTE_KIND (links) == REG_INC)
1187 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1191 /* Record the current insn_rtx_cost of this instruction. */
1192 if (NONJUMP_INSN_P (insn))
1193 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1194 optimize_this_for_speed_p);
1196 fprintf(dump_file, "insn_cost %d: %d\n",
1197 INSN_UID (insn), INSN_COST (insn));
1201 nonzero_sign_valid = 1;
1203 /* Now scan all the insns in forward order. */
1204 label_tick = label_tick_ebb_start = 1;
1206 setup_incoming_promotions (first);
1207 last_bb = ENTRY_BLOCK_PTR;
1209 FOR_EACH_BB (this_basic_block)
1211 rtx last_combined_insn = NULL_RTX;
1212 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1217 if (!single_pred_p (this_basic_block)
1218 || single_pred (this_basic_block) != last_bb)
1219 label_tick_ebb_start = label_tick;
1220 last_bb = this_basic_block;
1222 rtl_profile_for_bb (this_basic_block);
1223 for (insn = BB_HEAD (this_basic_block);
1224 insn != NEXT_INSN (BB_END (this_basic_block));
1225 insn = next ? next : NEXT_INSN (insn))
1228 if (NONDEBUG_INSN_P (insn))
1230 while (last_combined_insn
1231 && INSN_DELETED_P (last_combined_insn))
1232 last_combined_insn = PREV_INSN (last_combined_insn);
1233 if (last_combined_insn == NULL_RTX
1234 || BARRIER_P (last_combined_insn)
1235 || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1236 || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1237 last_combined_insn = insn;
1239 /* See if we know about function return values before this
1240 insn based upon SUBREG flags. */
1241 check_promoted_subreg (insn, PATTERN (insn));
1243 /* See if we can find hardregs and subreg of pseudos in
1244 narrower modes. This could help turning TRUNCATEs
1246 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1248 /* Try this insn with each insn it links back to. */
1250 FOR_EACH_LOG_LINK (links, insn)
1251 if ((next = try_combine (insn, links->insn, NULL_RTX,
1252 NULL_RTX, &new_direct_jump_p,
1253 last_combined_insn)) != 0)
1256 /* Try each sequence of three linked insns ending with this one. */
1258 FOR_EACH_LOG_LINK (links, insn)
1260 rtx link = links->insn;
1262 /* If the linked insn has been replaced by a note, then there
1263 is no point in pursuing this chain any further. */
1267 FOR_EACH_LOG_LINK (nextlinks, link)
1268 if ((next = try_combine (insn, link, nextlinks->insn,
1269 NULL_RTX, &new_direct_jump_p,
1270 last_combined_insn)) != 0)
1275 /* Try to combine a jump insn that uses CC0
1276 with a preceding insn that sets CC0, and maybe with its
1277 logical predecessor as well.
1278 This is how we make decrement-and-branch insns.
1279 We need this special code because data flow connections
1280 via CC0 do not get entered in LOG_LINKS. */
1283 && (prev = prev_nonnote_insn (insn)) != 0
1284 && NONJUMP_INSN_P (prev)
1285 && sets_cc0_p (PATTERN (prev)))
1287 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1289 last_combined_insn)) != 0)
1292 FOR_EACH_LOG_LINK (nextlinks, prev)
1293 if ((next = try_combine (insn, prev, nextlinks->insn,
1294 NULL_RTX, &new_direct_jump_p,
1295 last_combined_insn)) != 0)
1299 /* Do the same for an insn that explicitly references CC0. */
1300 if (NONJUMP_INSN_P (insn)
1301 && (prev = prev_nonnote_insn (insn)) != 0
1302 && NONJUMP_INSN_P (prev)
1303 && sets_cc0_p (PATTERN (prev))
1304 && GET_CODE (PATTERN (insn)) == SET
1305 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1307 if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1309 last_combined_insn)) != 0)
1312 FOR_EACH_LOG_LINK (nextlinks, prev)
1313 if ((next = try_combine (insn, prev, nextlinks->insn,
1314 NULL_RTX, &new_direct_jump_p,
1315 last_combined_insn)) != 0)
1319 /* Finally, see if any of the insns that this insn links to
1320 explicitly references CC0. If so, try this insn, that insn,
1321 and its predecessor if it sets CC0. */
1322 FOR_EACH_LOG_LINK (links, insn)
1323 if (NONJUMP_INSN_P (links->insn)
1324 && GET_CODE (PATTERN (links->insn)) == SET
1325 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1326 && (prev = prev_nonnote_insn (links->insn)) != 0
1327 && NONJUMP_INSN_P (prev)
1328 && sets_cc0_p (PATTERN (prev))
1329 && (next = try_combine (insn, links->insn,
1330 prev, NULL_RTX, &new_direct_jump_p,
1331 last_combined_insn)) != 0)
1335 /* Try combining an insn with two different insns whose results it
1337 FOR_EACH_LOG_LINK (links, insn)
1338 for (nextlinks = links->next; nextlinks;
1339 nextlinks = nextlinks->next)
1340 if ((next = try_combine (insn, links->insn,
1341 nextlinks->insn, NULL_RTX,
1343 last_combined_insn)) != 0)
1346 /* Try four-instruction combinations. */
1347 FOR_EACH_LOG_LINK (links, insn)
1349 struct insn_link *next1;
1350 rtx link = links->insn;
1352 /* If the linked insn has been replaced by a note, then there
1353 is no point in pursuing this chain any further. */
1357 FOR_EACH_LOG_LINK (next1, link)
1359 rtx link1 = next1->insn;
1362 /* I0 -> I1 -> I2 -> I3. */
1363 FOR_EACH_LOG_LINK (nextlinks, link1)
1364 if ((next = try_combine (insn, link, link1,
1367 last_combined_insn)) != 0)
1369 /* I0, I1 -> I2, I2 -> I3. */
1370 for (nextlinks = next1->next; nextlinks;
1371 nextlinks = nextlinks->next)
1372 if ((next = try_combine (insn, link, link1,
1375 last_combined_insn)) != 0)
1379 for (next1 = links->next; next1; next1 = next1->next)
1381 rtx link1 = next1->insn;
1384 /* I0 -> I2; I1, I2 -> I3. */
1385 FOR_EACH_LOG_LINK (nextlinks, link)
1386 if ((next = try_combine (insn, link, link1,
1389 last_combined_insn)) != 0)
1391 /* I0 -> I1; I1, I2 -> I3. */
1392 FOR_EACH_LOG_LINK (nextlinks, link1)
1393 if ((next = try_combine (insn, link, link1,
1396 last_combined_insn)) != 0)
1401 /* Try this insn with each REG_EQUAL note it links back to. */
1402 FOR_EACH_LOG_LINK (links, insn)
1405 rtx temp = links->insn;
1406 if ((set = single_set (temp)) != 0
1407 && (note = find_reg_equal_equiv_note (temp)) != 0
1408 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1409 /* Avoid using a register that may already been marked
1410 dead by an earlier instruction. */
1411 && ! unmentioned_reg_p (note, SET_SRC (set))
1412 && (GET_MODE (note) == VOIDmode
1413 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1414 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1416 /* Temporarily replace the set's source with the
1417 contents of the REG_EQUAL note. The insn will
1418 be deleted or recognized by try_combine. */
1419 rtx orig = SET_SRC (set);
1420 SET_SRC (set) = note;
1422 i2mod_old_rhs = copy_rtx (orig);
1423 i2mod_new_rhs = copy_rtx (note);
1424 next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1426 last_combined_insn);
1430 SET_SRC (set) = orig;
1435 record_dead_and_set_regs (insn);
1443 default_rtl_profile ();
1445 new_direct_jump_p |= purge_all_dead_edges ();
1446 delete_noop_moves ();
1449 obstack_free (&insn_link_obstack, NULL);
1450 free (uid_log_links);
1451 free (uid_insn_cost);
1452 VEC_free (reg_stat_type, heap, reg_stat);
1455 struct undo *undo, *next;
1456 for (undo = undobuf.frees; undo; undo = next)
1464 total_attempts += combine_attempts;
1465 total_merges += combine_merges;
1466 total_extras += combine_extras;
1467 total_successes += combine_successes;
1469 nonzero_sign_valid = 0;
1470 rtl_hooks = general_rtl_hooks;
1472 /* Make recognizer allow volatile MEMs again. */
1475 return new_direct_jump_p;
1478 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1481 init_reg_last (void)
1486 FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1487 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1490 /* Set up any promoted values for incoming argument registers. */
1493 setup_incoming_promotions (rtx first)
1496 bool strictly_local = false;
1498 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1499 arg = DECL_CHAIN (arg))
1501 rtx x, reg = DECL_INCOMING_RTL (arg);
1503 enum machine_mode mode1, mode2, mode3, mode4;
1505 /* Only continue if the incoming argument is in a register. */
1509 /* Determine, if possible, whether all call sites of the current
1510 function lie within the current compilation unit. (This does
1511 take into account the exporting of a function via taking its
1512 address, and so forth.) */
1513 strictly_local = cgraph_local_info (current_function_decl)->local;
1515 /* The mode and signedness of the argument before any promotions happen
1516 (equal to the mode of the pseudo holding it at that stage). */
1517 mode1 = TYPE_MODE (TREE_TYPE (arg));
1518 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1520 /* The mode and signedness of the argument after any source language and
1521 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1522 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1523 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1525 /* The mode and signedness of the argument as it is actually passed,
1526 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1527 mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1528 TREE_TYPE (cfun->decl), 0);
1530 /* The mode of the register in which the argument is being passed. */
1531 mode4 = GET_MODE (reg);
1533 /* Eliminate sign extensions in the callee when:
1534 (a) A mode promotion has occurred; */
1537 /* (b) The mode of the register is the same as the mode of
1538 the argument as it is passed; */
1541 /* (c) There's no language level extension; */
1544 /* (c.1) All callers are from the current compilation unit. If that's
1545 the case we don't have to rely on an ABI, we only have to know
1546 what we're generating right now, and we know that we will do the
1547 mode1 to mode2 promotion with the given sign. */
1548 else if (!strictly_local)
1550 /* (c.2) The combination of the two promotions is useful. This is
1551 true when the signs match, or if the first promotion is unsigned.
1552 In the later case, (sign_extend (zero_extend x)) is the same as
1553 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1559 /* Record that the value was promoted from mode1 to mode3,
1560 so that any sign extension at the head of the current
1561 function may be eliminated. */
1562 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1563 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1564 record_value_for_reg (reg, first, x);
1568 /* Called via note_stores. If X is a pseudo that is narrower than
1569 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1571 If we are setting only a portion of X and we can't figure out what
1572 portion, assume all bits will be used since we don't know what will
1575 Similarly, set how many bits of X are known to be copies of the sign bit
1576 at all locations in the function. This is the smallest number implied
1580 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1582 rtx insn = (rtx) data;
1586 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1587 /* If this register is undefined at the start of the file, we can't
1588 say what its contents were. */
1589 && ! REGNO_REG_SET_P
1590 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1591 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1593 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1595 if (set == 0 || GET_CODE (set) == CLOBBER)
1597 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1598 rsp->sign_bit_copies = 1;
1602 /* If this register is being initialized using itself, and the
1603 register is uninitialized in this basic block, and there are
1604 no LOG_LINKS which set the register, then part of the
1605 register is uninitialized. In that case we can't assume
1606 anything about the number of nonzero bits.
1608 ??? We could do better if we checked this in
1609 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1610 could avoid making assumptions about the insn which initially
1611 sets the register, while still using the information in other
1612 insns. We would have to be careful to check every insn
1613 involved in the combination. */
1616 && reg_referenced_p (x, PATTERN (insn))
1617 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1620 struct insn_link *link;
1622 FOR_EACH_LOG_LINK (link, insn)
1623 if (dead_or_set_p (link->insn, x))
1627 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1628 rsp->sign_bit_copies = 1;
1633 /* If this is a complex assignment, see if we can convert it into a
1634 simple assignment. */
1635 set = expand_field_assignment (set);
1637 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1638 set what we know about X. */
1640 if (SET_DEST (set) == x
1641 || (paradoxical_subreg_p (SET_DEST (set))
1642 && SUBREG_REG (SET_DEST (set)) == x))
1644 rtx src = SET_SRC (set);
1646 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1647 /* If X is narrower than a word and SRC is a non-negative
1648 constant that would appear negative in the mode of X,
1649 sign-extend it for use in reg_stat[].nonzero_bits because some
1650 machines (maybe most) will actually do the sign-extension
1651 and this is the conservative approach.
1653 ??? For 2.5, try to tighten up the MD files in this regard
1654 instead of this kludge. */
1656 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1657 && CONST_INT_P (src)
1659 && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1660 src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1663 /* Don't call nonzero_bits if it cannot change anything. */
1664 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1665 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1666 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1667 if (rsp->sign_bit_copies == 0
1668 || rsp->sign_bit_copies > num)
1669 rsp->sign_bit_copies = num;
1673 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1674 rsp->sign_bit_copies = 1;
1679 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1680 optionally insns that were previously combined into I3 or that will be
1681 combined into the merger of INSN and I3. The order is PRED, PRED2,
1682 INSN, SUCC, SUCC2, I3.
1684 Return 0 if the combination is not allowed for any reason.
1686 If the combination is allowed, *PDEST will be set to the single
1687 destination of INSN and *PSRC to the single source, and this function
1691 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1692 rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1693 rtx *pdest, rtx *psrc)
1702 bool all_adjacent = true;
1708 if (next_active_insn (succ2) != i3)
1709 all_adjacent = false;
1710 if (next_active_insn (succ) != succ2)
1711 all_adjacent = false;
1713 else if (next_active_insn (succ) != i3)
1714 all_adjacent = false;
1715 if (next_active_insn (insn) != succ)
1716 all_adjacent = false;
1718 else if (next_active_insn (insn) != i3)
1719 all_adjacent = false;
1721 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1722 or a PARALLEL consisting of such a SET and CLOBBERs.
1724 If INSN has CLOBBER parallel parts, ignore them for our processing.
1725 By definition, these happen during the execution of the insn. When it
1726 is merged with another insn, all bets are off. If they are, in fact,
1727 needed and aren't also supplied in I3, they may be added by
1728 recog_for_combine. Otherwise, it won't match.
1730 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1733 Get the source and destination of INSN. If more than one, can't
1736 if (GET_CODE (PATTERN (insn)) == SET)
1737 set = PATTERN (insn);
1738 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1739 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1741 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1743 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1745 switch (GET_CODE (elt))
1747 /* This is important to combine floating point insns
1748 for the SH4 port. */
1750 /* Combining an isolated USE doesn't make sense.
1751 We depend here on combinable_i3pat to reject them. */
1752 /* The code below this loop only verifies that the inputs of
1753 the SET in INSN do not change. We call reg_set_between_p
1754 to verify that the REG in the USE does not change between
1756 If the USE in INSN was for a pseudo register, the matching
1757 insn pattern will likely match any register; combining this
1758 with any other USE would only be safe if we knew that the
1759 used registers have identical values, or if there was
1760 something to tell them apart, e.g. different modes. For
1761 now, we forgo such complicated tests and simply disallow
1762 combining of USES of pseudo registers with any other USE. */
1763 if (REG_P (XEXP (elt, 0))
1764 && GET_CODE (PATTERN (i3)) == PARALLEL)
1766 rtx i3pat = PATTERN (i3);
1767 int i = XVECLEN (i3pat, 0) - 1;
1768 unsigned int regno = REGNO (XEXP (elt, 0));
1772 rtx i3elt = XVECEXP (i3pat, 0, i);
1774 if (GET_CODE (i3elt) == USE
1775 && REG_P (XEXP (i3elt, 0))
1776 && (REGNO (XEXP (i3elt, 0)) == regno
1777 ? reg_set_between_p (XEXP (elt, 0),
1778 PREV_INSN (insn), i3)
1779 : regno >= FIRST_PSEUDO_REGISTER))
1786 /* We can ignore CLOBBERs. */
1791 /* Ignore SETs whose result isn't used but not those that
1792 have side-effects. */
1793 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1794 && insn_nothrow_p (insn)
1795 && !side_effects_p (elt))
1798 /* If we have already found a SET, this is a second one and
1799 so we cannot combine with this insn. */
1807 /* Anything else means we can't combine. */
1813 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1814 so don't do anything with it. */
1815 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1824 set = expand_field_assignment (set);
1825 src = SET_SRC (set), dest = SET_DEST (set);
1827 /* Don't eliminate a store in the stack pointer. */
1828 if (dest == stack_pointer_rtx
1829 /* Don't combine with an insn that sets a register to itself if it has
1830 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1831 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1832 /* Can't merge an ASM_OPERANDS. */
1833 || GET_CODE (src) == ASM_OPERANDS
1834 /* Can't merge a function call. */
1835 || GET_CODE (src) == CALL
1836 /* Don't eliminate a function call argument. */
1838 && (find_reg_fusage (i3, USE, dest)
1840 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1841 && global_regs[REGNO (dest)])))
1842 /* Don't substitute into an incremented register. */
1843 || FIND_REG_INC_NOTE (i3, dest)
1844 || (succ && FIND_REG_INC_NOTE (succ, dest))
1845 || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1846 /* Don't substitute into a non-local goto, this confuses CFG. */
1847 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1848 /* Make sure that DEST is not used after SUCC but before I3. */
1851 && (reg_used_between_p (dest, succ2, i3)
1852 || reg_used_between_p (dest, succ, succ2)))
1853 || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1854 /* Make sure that the value that is to be substituted for the register
1855 does not use any registers whose values alter in between. However,
1856 If the insns are adjacent, a use can't cross a set even though we
1857 think it might (this can happen for a sequence of insns each setting
1858 the same destination; last_set of that register might point to
1859 a NOTE). If INSN has a REG_EQUIV note, the register is always
1860 equivalent to the memory so the substitution is valid even if there
1861 are intervening stores. Also, don't move a volatile asm or
1862 UNSPEC_VOLATILE across any other insns. */
1865 || ! find_reg_note (insn, REG_EQUIV, src))
1866 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1867 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1868 || GET_CODE (src) == UNSPEC_VOLATILE))
1869 /* Don't combine across a CALL_INSN, because that would possibly
1870 change whether the life span of some REGs crosses calls or not,
1871 and it is a pain to update that information.
1872 Exception: if source is a constant, moving it later can't hurt.
1873 Accept that as a special case. */
1874 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1877 /* DEST must either be a REG or CC0. */
1880 /* If register alignment is being enforced for multi-word items in all
1881 cases except for parameters, it is possible to have a register copy
1882 insn referencing a hard register that is not allowed to contain the
1883 mode being copied and which would not be valid as an operand of most
1884 insns. Eliminate this problem by not combining with such an insn.
1886 Also, on some machines we don't want to extend the life of a hard
1890 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1891 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1892 /* Don't extend the life of a hard register unless it is
1893 user variable (if we have few registers) or it can't
1894 fit into the desired register (meaning something special
1896 Also avoid substituting a return register into I3, because
1897 reload can't handle a conflict with constraints of other
1899 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1900 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1903 else if (GET_CODE (dest) != CC0)
1907 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1908 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1909 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1911 /* Don't substitute for a register intended as a clobberable
1913 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1914 if (rtx_equal_p (reg, dest))
1917 /* If the clobber represents an earlyclobber operand, we must not
1918 substitute an expression containing the clobbered register.
1919 As we do not analyze the constraint strings here, we have to
1920 make the conservative assumption. However, if the register is
1921 a fixed hard reg, the clobber cannot represent any operand;
1922 we leave it up to the machine description to either accept or
1923 reject use-and-clobber patterns. */
1925 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1926 || !fixed_regs[REGNO (reg)])
1927 if (reg_overlap_mentioned_p (reg, src))
1931 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1932 or not), reject, unless nothing volatile comes between it and I3 */
1934 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1936 /* Make sure neither succ nor succ2 contains a volatile reference. */
1937 if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1939 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1941 /* We'll check insns between INSN and I3 below. */
1944 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1945 to be an explicit register variable, and was chosen for a reason. */
1947 if (GET_CODE (src) == ASM_OPERANDS
1948 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1951 /* If there are any volatile insns between INSN and I3, reject, because
1952 they might affect machine state. */
1954 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1955 if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1958 /* If INSN contains an autoincrement or autodecrement, make sure that
1959 register is not used between there and I3, and not already used in
1960 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1961 Also insist that I3 not be a jump; if it were one
1962 and the incremented register were spilled, we would lose. */
1965 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1966 if (REG_NOTE_KIND (link) == REG_INC
1968 || reg_used_between_p (XEXP (link, 0), insn, i3)
1969 || (pred != NULL_RTX
1970 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1971 || (pred2 != NULL_RTX
1972 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1973 || (succ != NULL_RTX
1974 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1975 || (succ2 != NULL_RTX
1976 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1977 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1982 /* Don't combine an insn that follows a CC0-setting insn.
1983 An insn that uses CC0 must not be separated from the one that sets it.
1984 We do, however, allow I2 to follow a CC0-setting insn if that insn
1985 is passed as I1; in that case it will be deleted also.
1986 We also allow combining in this case if all the insns are adjacent
1987 because that would leave the two CC0 insns adjacent as well.
1988 It would be more logical to test whether CC0 occurs inside I1 or I2,
1989 but that would be much slower, and this ought to be equivalent. */
1991 p = prev_nonnote_insn (insn);
1992 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1997 /* If we get here, we have passed all the tests and the combination is
2006 /* LOC is the location within I3 that contains its pattern or the component
2007 of a PARALLEL of the pattern. We validate that it is valid for combining.
2009 One problem is if I3 modifies its output, as opposed to replacing it
2010 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2011 doing so would produce an insn that is not equivalent to the original insns.
2015 (set (reg:DI 101) (reg:DI 100))
2016 (set (subreg:SI (reg:DI 101) 0) <foo>)
2018 This is NOT equivalent to:
2020 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2021 (set (reg:DI 101) (reg:DI 100))])
2023 Not only does this modify 100 (in which case it might still be valid
2024 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2026 We can also run into a problem if I2 sets a register that I1
2027 uses and I1 gets directly substituted into I3 (not via I2). In that
2028 case, we would be getting the wrong value of I2DEST into I3, so we
2029 must reject the combination. This case occurs when I2 and I1 both
2030 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2031 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2032 of a SET must prevent combination from occurring. The same situation
2033 can occur for I0, in which case I0_NOT_IN_SRC is set.
2035 Before doing the above check, we first try to expand a field assignment
2036 into a set of logical operations.
2038 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2039 we place a register that is both set and used within I3. If more than one
2040 such register is detected, we fail.
2042 Return 1 if the combination is valid, zero otherwise. */
2045 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2046 int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2050 if (GET_CODE (x) == SET)
2053 rtx dest = SET_DEST (set);
2054 rtx src = SET_SRC (set);
2055 rtx inner_dest = dest;
2058 while (GET_CODE (inner_dest) == STRICT_LOW_PART
2059 || GET_CODE (inner_dest) == SUBREG
2060 || GET_CODE (inner_dest) == ZERO_EXTRACT)
2061 inner_dest = XEXP (inner_dest, 0);
2063 /* Check for the case where I3 modifies its output, as discussed
2064 above. We don't want to prevent pseudos from being combined
2065 into the address of a MEM, so only prevent the combination if
2066 i1 or i2 set the same MEM. */
2067 if ((inner_dest != dest &&
2068 (!MEM_P (inner_dest)
2069 || rtx_equal_p (i2dest, inner_dest)
2070 || (i1dest && rtx_equal_p (i1dest, inner_dest))
2071 || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2072 && (reg_overlap_mentioned_p (i2dest, inner_dest)
2073 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2074 || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2076 /* This is the same test done in can_combine_p except we can't test
2077 all_adjacent; we don't have to, since this instruction will stay
2078 in place, thus we are not considering increasing the lifetime of
2081 Also, if this insn sets a function argument, combining it with
2082 something that might need a spill could clobber a previous
2083 function argument; the all_adjacent test in can_combine_p also
2084 checks this; here, we do a more specific test for this case. */
2086 || (REG_P (inner_dest)
2087 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2088 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2089 GET_MODE (inner_dest))))
2090 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2091 || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2094 /* If DEST is used in I3, it is being killed in this insn, so
2095 record that for later. We have to consider paradoxical
2096 subregs here, since they kill the whole register, but we
2097 ignore partial subregs, STRICT_LOW_PART, etc.
2098 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2099 STACK_POINTER_REGNUM, since these are always considered to be
2100 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2102 if (GET_CODE (subdest) == SUBREG
2103 && (GET_MODE_SIZE (GET_MODE (subdest))
2104 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2105 subdest = SUBREG_REG (subdest);
2108 && reg_referenced_p (subdest, PATTERN (i3))
2109 && REGNO (subdest) != FRAME_POINTER_REGNUM
2110 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2111 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2113 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2114 && (REGNO (subdest) != ARG_POINTER_REGNUM
2115 || ! fixed_regs [REGNO (subdest)])
2117 && REGNO (subdest) != STACK_POINTER_REGNUM)
2119 if (*pi3dest_killed)
2122 *pi3dest_killed = subdest;
2126 else if (GET_CODE (x) == PARALLEL)
2130 for (i = 0; i < XVECLEN (x, 0); i++)
2131 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2132 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2139 /* Return 1 if X is an arithmetic expression that contains a multiplication
2140 and division. We don't count multiplications by powers of two here. */
2143 contains_muldiv (rtx x)
2145 switch (GET_CODE (x))
2147 case MOD: case DIV: case UMOD: case UDIV:
2151 return ! (CONST_INT_P (XEXP (x, 1))
2152 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2155 return contains_muldiv (XEXP (x, 0))
2156 || contains_muldiv (XEXP (x, 1));
2159 return contains_muldiv (XEXP (x, 0));
2165 /* Determine whether INSN can be used in a combination. Return nonzero if
2166 not. This is used in try_combine to detect early some cases where we
2167 can't perform combinations. */
2170 cant_combine_insn_p (rtx insn)
2175 /* If this isn't really an insn, we can't do anything.
2176 This can occur when flow deletes an insn that it has merged into an
2177 auto-increment address. */
2178 if (! INSN_P (insn))
2181 /* Never combine loads and stores involving hard regs that are likely
2182 to be spilled. The register allocator can usually handle such
2183 reg-reg moves by tying. If we allow the combiner to make
2184 substitutions of likely-spilled regs, reload might die.
2185 As an exception, we allow combinations involving fixed regs; these are
2186 not available to the register allocator so there's no risk involved. */
2188 set = single_set (insn);
2191 src = SET_SRC (set);
2192 dest = SET_DEST (set);
2193 if (GET_CODE (src) == SUBREG)
2194 src = SUBREG_REG (src);
2195 if (GET_CODE (dest) == SUBREG)
2196 dest = SUBREG_REG (dest);
2197 if (REG_P (src) && REG_P (dest)
2198 && ((HARD_REGISTER_P (src)
2199 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2200 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2201 || (HARD_REGISTER_P (dest)
2202 && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2203 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2209 struct likely_spilled_retval_info
2211 unsigned regno, nregs;
2215 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2216 hard registers that are known to be written to / clobbered in full. */
2218 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2220 struct likely_spilled_retval_info *const info =
2221 (struct likely_spilled_retval_info *) data;
2222 unsigned regno, nregs;
2225 if (!REG_P (XEXP (set, 0)))
2228 if (regno >= info->regno + info->nregs)
2230 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2231 if (regno + nregs <= info->regno)
2233 new_mask = (2U << (nregs - 1)) - 1;
2234 if (regno < info->regno)
2235 new_mask >>= info->regno - regno;
2237 new_mask <<= regno - info->regno;
2238 info->mask &= ~new_mask;
2241 /* Return nonzero iff part of the return value is live during INSN, and
2242 it is likely spilled. This can happen when more than one insn is needed
2243 to copy the return value, e.g. when we consider to combine into the
2244 second copy insn for a complex value. */
2247 likely_spilled_retval_p (rtx insn)
2249 rtx use = BB_END (this_basic_block);
2251 unsigned regno, nregs;
2252 /* We assume here that no machine mode needs more than
2253 32 hard registers when the value overlaps with a register
2254 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2256 struct likely_spilled_retval_info info;
2258 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2260 reg = XEXP (PATTERN (use), 0);
2261 if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2263 regno = REGNO (reg);
2264 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2267 mask = (2U << (nregs - 1)) - 1;
2269 /* Disregard parts of the return value that are set later. */
2273 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2275 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2278 /* Check if any of the (probably) live return value registers is
2283 if ((mask & 1 << nregs)
2284 && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2290 /* Adjust INSN after we made a change to its destination.
2292 Changing the destination can invalidate notes that say something about
2293 the results of the insn and a LOG_LINK pointing to the insn. */
2296 adjust_for_new_dest (rtx insn)
2298 /* For notes, be conservative and simply remove them. */
2299 remove_reg_equal_equiv_notes (insn);
2301 /* The new insn will have a destination that was previously the destination
2302 of an insn just above it. Call distribute_links to make a LOG_LINK from
2303 the next use of that destination. */
2304 distribute_links (alloc_insn_link (insn, NULL));
2306 df_insn_rescan (insn);
2309 /* Return TRUE if combine can reuse reg X in mode MODE.
2310 ADDED_SETS is nonzero if the original set is still required. */
2312 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2320 /* Allow hard registers if the new mode is legal, and occupies no more
2321 registers than the old mode. */
2322 if (regno < FIRST_PSEUDO_REGISTER)
2323 return (HARD_REGNO_MODE_OK (regno, mode)
2324 && (hard_regno_nregs[regno][GET_MODE (x)]
2325 >= hard_regno_nregs[regno][mode]));
2327 /* Or a pseudo that is only used once. */
2328 return (REG_N_SETS (regno) == 1 && !added_sets
2329 && !REG_USERVAR_P (x));
2333 /* Check whether X, the destination of a set, refers to part of
2334 the register specified by REG. */
2337 reg_subword_p (rtx x, rtx reg)
2339 /* Check that reg is an integer mode register. */
2340 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2343 if (GET_CODE (x) == STRICT_LOW_PART
2344 || GET_CODE (x) == ZERO_EXTRACT)
2347 return GET_CODE (x) == SUBREG
2348 && SUBREG_REG (x) == reg
2349 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2353 /* Replace auto-increment addressing modes with explicit operations to access
2354 the same addresses without modifying the corresponding registers. */
2357 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2360 const RTX_CODE code = GET_CODE (x);
2376 /* SCRATCH must be shared because they represent distinct values. */
2379 if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2384 if (shared_const_p (x))
2389 mem_mode = GET_MODE (x);
2394 gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2395 return gen_rtx_PLUS (GET_MODE (x),
2396 cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2397 GEN_INT (code == PRE_INC
2398 ? GET_MODE_SIZE (mem_mode)
2399 : -GET_MODE_SIZE (mem_mode)));
2405 return cleanup_auto_inc_dec (code == PRE_MODIFY
2406 ? XEXP (x, 1) : XEXP (x, 0),
2413 /* Copy the various flags, fields, and other information. We assume
2414 that all fields need copying, and then clear the fields that should
2415 not be copied. That is the sensible default behavior, and forces
2416 us to explicitly document why we are *not* copying a flag. */
2417 x = shallow_copy_rtx (x);
2419 /* We do not copy the USED flag, which is used as a mark bit during
2420 walks over the RTL. */
2421 RTX_FLAG (x, used) = 0;
2423 /* We do not copy FRAME_RELATED for INSNs. */
2425 RTX_FLAG (x, frame_related) = 0;
2427 fmt = GET_RTX_FORMAT (code);
2428 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2430 XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2431 else if (fmt[i] == 'E' || fmt[i] == 'V')
2434 XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2435 for (j = 0; j < XVECLEN (x, i); j++)
2437 = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2444 /* Auxiliary data structure for propagate_for_debug_stmt. */
2446 struct rtx_subst_pair
2452 /* DATA points to an rtx_subst_pair. Return the value that should be
2456 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2458 struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2460 if (!rtx_equal_p (from, old_rtx))
2462 if (!pair->adjusted)
2464 pair->adjusted = true;
2466 pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2468 pair->to = copy_rtx (pair->to);
2470 pair->to = make_compound_operation (pair->to, SET);
2473 return copy_rtx (pair->to);
2476 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2477 and LAST, not including INSN, but including LAST. Also stop at the end
2478 of THIS_BASIC_BLOCK. */
2481 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2483 rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2485 struct rtx_subst_pair p;
2489 next = NEXT_INSN (insn);
2490 last = NEXT_INSN (last);
2491 while (next != last && next != end)
2494 next = NEXT_INSN (insn);
2495 if (DEBUG_INSN_P (insn))
2497 loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2498 dest, propagate_for_debug_subst, &p);
2499 if (loc == INSN_VAR_LOCATION_LOC (insn))
2501 INSN_VAR_LOCATION_LOC (insn) = loc;
2502 df_insn_rescan (insn);
2507 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2508 Note that the INSN should be deleted *after* removing dead edges, so
2509 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2510 but not for a (set (pc) (label_ref FOO)). */
2513 update_cfg_for_uncondjump (rtx insn)
2515 basic_block bb = BLOCK_FOR_INSN (insn);
2516 gcc_assert (BB_END (bb) == insn);
2518 purge_dead_edges (bb);
2521 if (EDGE_COUNT (bb->succs) == 1)
2525 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2527 /* Remove barriers from the footer if there are any. */
2528 for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2529 if (BARRIER_P (insn))
2531 if (PREV_INSN (insn))
2532 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2534 bb->il.rtl->footer = NEXT_INSN (insn);
2535 if (NEXT_INSN (insn))
2536 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2538 else if (LABEL_P (insn))
2543 /* Try to combine the insns I0, I1 and I2 into I3.
2544 Here I0, I1 and I2 appear earlier than I3.
2545 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2548 If we are combining more than two insns and the resulting insn is not
2549 recognized, try splitting it into two insns. If that happens, I2 and I3
2550 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2551 Otherwise, I0, I1 and I2 are pseudo-deleted.
2553 Return 0 if the combination does not work. Then nothing is changed.
2554 If we did the combination, return the insn at which combine should
2557 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2558 new direct jump instruction.
2560 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2561 been I3 passed to an earlier try_combine within the same basic
2565 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2566 rtx last_combined_insn)
2568 /* New patterns for I3 and I2, respectively. */
2569 rtx newpat, newi2pat = 0;
2570 rtvec newpat_vec_with_clobbers = 0;
2571 int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2572 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2574 int added_sets_0, added_sets_1, added_sets_2;
2575 /* Total number of SETs to put into I3. */
2577 /* Nonzero if I2's or I1's body now appears in I3. */
2578 int i2_is_used = 0, i1_is_used = 0;
2579 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2580 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2581 /* Contains I3 if the destination of I3 is used in its source, which means
2582 that the old life of I3 is being killed. If that usage is placed into
2583 I2 and not in I3, a REG_DEAD note must be made. */
2584 rtx i3dest_killed = 0;
2585 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2586 rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2587 /* Copy of SET_SRC of I1, if needed. */
2589 /* Set if I2DEST was reused as a scratch register. */
2590 bool i2scratch = false;
2591 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2592 rtx i0pat = 0, i1pat = 0, i2pat = 0;
2593 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2594 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2595 int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2596 int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2597 int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2598 /* Notes that must be added to REG_NOTES in I3 and I2. */
2599 rtx new_i3_notes, new_i2_notes;
2600 /* Notes that we substituted I3 into I2 instead of the normal case. */
2601 int i3_subst_into_i2 = 0;
2602 /* Notes that I1, I2 or I3 is a MULT operation. */
2605 int changed_i3_dest = 0;
2609 struct insn_link *link;
2611 rtx new_other_notes;
2614 /* Only try four-insn combinations when there's high likelihood of
2615 success. Look for simple insns, such as loads of constants or
2616 binary operations involving a constant. */
2623 if (!flag_expensive_optimizations)
2626 for (i = 0; i < 4; i++)
2628 rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2629 rtx set = single_set (insn);
2633 src = SET_SRC (set);
2634 if (CONSTANT_P (src))
2639 else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2641 else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2642 || GET_CODE (src) == LSHIFTRT)
2645 if (ngood < 2 && nshift < 2)
2649 /* Exit early if one of the insns involved can't be used for
2651 if (cant_combine_insn_p (i3)
2652 || cant_combine_insn_p (i2)
2653 || (i1 && cant_combine_insn_p (i1))
2654 || (i0 && cant_combine_insn_p (i0))
2655 || likely_spilled_retval_p (i3))
2659 undobuf.other_insn = 0;
2661 /* Reset the hard register usage information. */
2662 CLEAR_HARD_REG_SET (newpat_used_regs);
2664 if (dump_file && (dump_flags & TDF_DETAILS))
2667 fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2668 INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2670 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2671 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2673 fprintf (dump_file, "\nTrying %d -> %d:\n",
2674 INSN_UID (i2), INSN_UID (i3));
2677 /* If multiple insns feed into one of I2 or I3, they can be in any
2678 order. To simplify the code below, reorder them in sequence. */
2679 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2680 temp = i2, i2 = i0, i0 = temp;
2681 if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2682 temp = i1, i1 = i0, i0 = temp;
2683 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2684 temp = i1, i1 = i2, i2 = temp;
2686 added_links_insn = 0;
2688 /* First check for one important special case that the code below will
2689 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2690 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2691 we may be able to replace that destination with the destination of I3.
2692 This occurs in the common code where we compute both a quotient and
2693 remainder into a structure, in which case we want to do the computation
2694 directly into the structure to avoid register-register copies.
2696 Note that this case handles both multiple sets in I2 and also cases
2697 where I2 has a number of CLOBBERs inside the PARALLEL.
2699 We make very conservative checks below and only try to handle the
2700 most common cases of this. For example, we only handle the case
2701 where I2 and I3 are adjacent to avoid making difficult register
2704 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2705 && REG_P (SET_SRC (PATTERN (i3)))
2706 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2707 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2708 && GET_CODE (PATTERN (i2)) == PARALLEL
2709 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2710 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2711 below would need to check what is inside (and reg_overlap_mentioned_p
2712 doesn't support those codes anyway). Don't allow those destinations;
2713 the resulting insn isn't likely to be recognized anyway. */
2714 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2715 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2716 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2717 SET_DEST (PATTERN (i3)))
2718 && next_active_insn (i2) == i3)
2720 rtx p2 = PATTERN (i2);
2722 /* Make sure that the destination of I3,
2723 which we are going to substitute into one output of I2,
2724 is not used within another output of I2. We must avoid making this:
2725 (parallel [(set (mem (reg 69)) ...)
2726 (set (reg 69) ...)])
2727 which is not well-defined as to order of actions.
2728 (Besides, reload can't handle output reloads for this.)
2730 The problem can also happen if the dest of I3 is a memory ref,
2731 if another dest in I2 is an indirect memory ref. */
2732 for (i = 0; i < XVECLEN (p2, 0); i++)
2733 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2734 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2735 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2736 SET_DEST (XVECEXP (p2, 0, i))))
2739 if (i == XVECLEN (p2, 0))
2740 for (i = 0; i < XVECLEN (p2, 0); i++)
2741 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2742 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2747 subst_low_luid = DF_INSN_LUID (i2);
2749 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2750 i2src = SET_SRC (XVECEXP (p2, 0, i));
2751 i2dest = SET_DEST (XVECEXP (p2, 0, i));
2752 i2dest_killed = dead_or_set_p (i2, i2dest);
2754 /* Replace the dest in I2 with our dest and make the resulting
2755 insn the new pattern for I3. Then skip to where we validate
2756 the pattern. Everything was set up above. */
2757 SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2759 i3_subst_into_i2 = 1;
2760 goto validate_replacement;
2764 /* If I2 is setting a pseudo to a constant and I3 is setting some
2765 sub-part of it to another constant, merge them by making a new
2768 && (temp = single_set (i2)) != 0
2769 && (CONST_INT_P (SET_SRC (temp))
2770 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2771 && GET_CODE (PATTERN (i3)) == SET
2772 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2773 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2774 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2776 rtx dest = SET_DEST (PATTERN (i3));
2780 if (GET_CODE (dest) == ZERO_EXTRACT)
2782 if (CONST_INT_P (XEXP (dest, 1))
2783 && CONST_INT_P (XEXP (dest, 2)))
2785 width = INTVAL (XEXP (dest, 1));
2786 offset = INTVAL (XEXP (dest, 2));
2787 dest = XEXP (dest, 0);
2788 if (BITS_BIG_ENDIAN)
2789 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2794 if (GET_CODE (dest) == STRICT_LOW_PART)
2795 dest = XEXP (dest, 0);
2796 width = GET_MODE_PRECISION (GET_MODE (dest));
2802 /* If this is the low part, we're done. */
2803 if (subreg_lowpart_p (dest))
2805 /* Handle the case where inner is twice the size of outer. */
2806 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2807 == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2808 offset += GET_MODE_PRECISION (GET_MODE (dest));
2809 /* Otherwise give up for now. */
2815 && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2816 <= HOST_BITS_PER_DOUBLE_INT))
2819 rtx inner = SET_SRC (PATTERN (i3));
2820 rtx outer = SET_SRC (temp);
2822 o = rtx_to_double_int (outer);
2823 i = rtx_to_double_int (inner);
2825 m = double_int_mask (width);
2826 i = double_int_and (i, m);
2827 m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2828 i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2829 o = double_int_ior (double_int_and_not (o, m), i);
2833 subst_low_luid = DF_INSN_LUID (i2);
2834 added_sets_2 = added_sets_1 = added_sets_0 = 0;
2835 i2dest = SET_DEST (temp);
2836 i2dest_killed = dead_or_set_p (i2, i2dest);
2838 /* Replace the source in I2 with the new constant and make the
2839 resulting insn the new pattern for I3. Then skip to where we
2840 validate the pattern. Everything was set up above. */
2841 SUBST (SET_SRC (temp),
2842 immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2844 newpat = PATTERN (i2);
2846 /* The dest of I3 has been replaced with the dest of I2. */
2847 changed_i3_dest = 1;
2848 goto validate_replacement;
2853 /* If we have no I1 and I2 looks like:
2854 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2856 make up a dummy I1 that is
2859 (set (reg:CC X) (compare:CC Y (const_int 0)))
2861 (We can ignore any trailing CLOBBERs.)
2863 This undoes a previous combination and allows us to match a branch-and-
2866 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2867 && XVECLEN (PATTERN (i2), 0) >= 2
2868 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2869 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2871 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2872 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2873 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2874 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2875 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2876 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2878 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2879 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2884 /* We make I1 with the same INSN_UID as I2. This gives it
2885 the same DF_INSN_LUID for value tracking. Our fake I1 will
2886 never appear in the insn stream so giving it the same INSN_UID
2887 as I2 will not cause a problem. */
2889 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2890 BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2891 INSN_LOCATOR (i2), -1, NULL_RTX);
2893 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2894 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2895 SET_DEST (PATTERN (i1)));
2896 SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2901 /* Verify that I2 and I1 are valid for combining. */
2902 if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2903 || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2905 || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2912 /* Record whether I2DEST is used in I2SRC and similarly for the other
2913 cases. Knowing this will help in register status updating below. */
2914 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2915 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2916 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2917 i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2918 i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2919 i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2920 i2dest_killed = dead_or_set_p (i2, i2dest);
2921 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2922 i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2924 /* For the earlier insns, determine which of the subsequent ones they
2926 i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2927 i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2928 i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2929 : (!reg_overlap_mentioned_p (i1dest, i0dest)
2930 && reg_overlap_mentioned_p (i0dest, i2src))));
2932 /* Ensure that I3's pattern can be the destination of combines. */
2933 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2934 i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2935 i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2936 || (i1dest_in_i0src && !i0_feeds_i1_n)),
2943 /* See if any of the insns is a MULT operation. Unless one is, we will
2944 reject a combination that is, since it must be slower. Be conservative
2946 if (GET_CODE (i2src) == MULT
2947 || (i1 != 0 && GET_CODE (i1src) == MULT)
2948 || (i0 != 0 && GET_CODE (i0src) == MULT)
2949 || (GET_CODE (PATTERN (i3)) == SET
2950 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2953 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2954 We used to do this EXCEPT in one case: I3 has a post-inc in an
2955 output operand. However, that exception can give rise to insns like
2957 which is a famous insn on the PDP-11 where the value of r3 used as the
2958 source was model-dependent. Avoid this sort of thing. */
2961 if (!(GET_CODE (PATTERN (i3)) == SET
2962 && REG_P (SET_SRC (PATTERN (i3)))
2963 && MEM_P (SET_DEST (PATTERN (i3)))
2964 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2965 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2966 /* It's not the exception. */
2971 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2972 if (REG_NOTE_KIND (link) == REG_INC
2973 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2975 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2983 /* See if the SETs in I1 or I2 need to be kept around in the merged
2984 instruction: whenever the value set there is still needed past I3.
2985 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2987 For the SET in I1, we have two cases: If I1 and I2 independently
2988 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2989 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2990 in I1 needs to be kept around unless I1DEST dies or is set in either
2991 I2 or I3. The same consideration applies to I0. */
2993 added_sets_2 = !dead_or_set_p (i3, i2dest);
2996 added_sets_1 = !(dead_or_set_p (i3, i1dest)
2997 || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3002 added_sets_0 = !(dead_or_set_p (i3, i0dest)
3003 || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3004 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
3008 /* We are about to copy insns for the case where they need to be kept
3009 around. Check that they can be copied in the merged instruction. */
3011 if (targetm.cannot_copy_insn_p
3012 && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3013 || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3014 || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3020 /* If the set in I2 needs to be kept around, we must make a copy of
3021 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3022 PATTERN (I2), we are only substituting for the original I1DEST, not into
3023 an already-substituted copy. This also prevents making self-referential
3024 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3029 if (GET_CODE (PATTERN (i2)) == PARALLEL)
3030 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3032 i2pat = copy_rtx (PATTERN (i2));
3037 if (GET_CODE (PATTERN (i1)) == PARALLEL)
3038 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3040 i1pat = copy_rtx (PATTERN (i1));
3045 if (GET_CODE (PATTERN (i0)) == PARALLEL)
3046 i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3048 i0pat = copy_rtx (PATTERN (i0));
3053 /* Substitute in the latest insn for the regs set by the earlier ones. */
3055 maxreg = max_reg_num ();
3060 /* Many machines that don't use CC0 have insns that can both perform an
3061 arithmetic operation and set the condition code. These operations will
3062 be represented as a PARALLEL with the first element of the vector
3063 being a COMPARE of an arithmetic operation with the constant zero.
3064 The second element of the vector will set some pseudo to the result
3065 of the same arithmetic operation. If we simplify the COMPARE, we won't
3066 match such a pattern and so will generate an extra insn. Here we test
3067 for this case, where both the comparison and the operation result are
3068 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3069 I2SRC. Later we will make the PARALLEL that contains I2. */
3071 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3072 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3073 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3074 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3077 rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
3078 rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3079 enum machine_mode compare_mode, orig_compare_mode;
3080 enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3082 newpat = PATTERN (i3);
3083 newpat_dest = SET_DEST (newpat);
3084 compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3086 if (undobuf.other_insn == 0
3087 && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3090 compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3091 compare_code = simplify_compare_const (compare_code,
3093 #ifdef CANONICALIZE_COMPARISON
3094 CANONICALIZE_COMPARISON (compare_code, op0, op1);
3098 /* Do the rest only if op1 is const0_rtx, which may be the
3099 result of simplification. */
3100 if (op1 == const0_rtx)
3102 /* If a single use of the CC is found, prepare to modify it
3103 when SELECT_CC_MODE returns a new CC-class mode, or when
3104 the above simplify_compare_const() returned a new comparison
3105 operator. undobuf.other_insn is assigned the CC use insn
3106 when modifying it. */
3109 #ifdef SELECT_CC_MODE
3110 enum machine_mode new_mode
3111 = SELECT_CC_MODE (compare_code, op0, op1);
3112 if (new_mode != orig_compare_mode
3113 && can_change_dest_mode (SET_DEST (newpat),
3114 added_sets_2, new_mode))
3116 unsigned int regno = REGNO (newpat_dest);
3117 compare_mode = new_mode;
3118 if (regno < FIRST_PSEUDO_REGISTER)
3119 newpat_dest = gen_rtx_REG (compare_mode, regno);
3122 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3123 newpat_dest = regno_reg_rtx[regno];
3127 /* Cases for modifying the CC-using comparison. */
3128 if (compare_code != orig_compare_code
3129 /* ??? Do we need to verify the zero rtx? */
3130 && XEXP (*cc_use_loc, 1) == const0_rtx)
3132 /* Replace cc_use_loc with entire new RTX. */
3134 gen_rtx_fmt_ee (compare_code, compare_mode,
3135 newpat_dest, const0_rtx));
3136 undobuf.other_insn = cc_use_insn;
3138 else if (compare_mode != orig_compare_mode)
3140 /* Just replace the CC reg with a new mode. */
3141 SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3142 undobuf.other_insn = cc_use_insn;
3146 /* Now we modify the current newpat:
3147 First, SET_DEST(newpat) is updated if the CC mode has been
3148 altered. For targets without SELECT_CC_MODE, this should be
3150 if (compare_mode != orig_compare_mode)
3151 SUBST (SET_DEST (newpat), newpat_dest);
3152 /* This is always done to propagate i2src into newpat. */
3153 SUBST (SET_SRC (newpat),
3154 gen_rtx_COMPARE (compare_mode, op0, op1));
3155 /* Create new version of i2pat if needed; the below PARALLEL
3156 creation needs this to work correctly. */
3157 if (! rtx_equal_p (i2src, op0))
3158 i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3164 if (i2_is_used == 0)
3166 /* It is possible that the source of I2 or I1 may be performing
3167 an unneeded operation, such as a ZERO_EXTEND of something
3168 that is known to have the high part zero. Handle that case
3169 by letting subst look at the inner insns.
3171 Another way to do this would be to have a function that tries
3172 to simplify a single insn instead of merging two or more
3173 insns. We don't do this because of the potential of infinite
3174 loops and because of the potential extra memory required.
3175 However, doing it the way we are is a bit of a kludge and
3176 doesn't catch all cases.
3178 But only do this if -fexpensive-optimizations since it slows
3179 things down and doesn't usually win.
3181 This is not done in the COMPARE case above because the
3182 unmodified I2PAT is used in the PARALLEL and so a pattern
3183 with a modified I2SRC would not match. */
3185 if (flag_expensive_optimizations)
3187 /* Pass pc_rtx so no substitutions are done, just
3191 subst_low_luid = DF_INSN_LUID (i1);
3192 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3195 subst_low_luid = DF_INSN_LUID (i2);
3196 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3199 n_occurrences = 0; /* `subst' counts here */
3200 subst_low_luid = DF_INSN_LUID (i2);
3202 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3203 copy of I2SRC each time we substitute it, in order to avoid creating
3204 self-referential RTL when we will be substituting I1SRC for I1DEST
3205 later. Likewise if I0 feeds into I2, either directly or indirectly
3206 through I1, and I0DEST is in I0SRC. */
3207 newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3208 (i1_feeds_i2_n && i1dest_in_i1src)
3209 || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3210 && i0dest_in_i0src));
3213 /* Record whether I2's body now appears within I3's body. */
3214 i2_is_used = n_occurrences;
3217 /* If we already got a failure, don't try to do more. Otherwise, try to
3218 substitute I1 if we have it. */
3220 if (i1 && GET_CODE (newpat) != CLOBBER)
3222 /* Check that an autoincrement side-effect on I1 has not been lost.
3223 This happens if I1DEST is mentioned in I2 and dies there, and
3224 has disappeared from the new pattern. */
3225 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3227 && dead_or_set_p (i2, i1dest)
3228 && !reg_overlap_mentioned_p (i1dest, newpat))
3229 /* Before we can do this substitution, we must redo the test done
3230 above (see detailed comments there) that ensures I1DEST isn't
3231 mentioned in any SETs in NEWPAT that are field assignments. */
3232 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3240 subst_low_luid = DF_INSN_LUID (i1);
3242 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3243 copy of I1SRC each time we substitute it, in order to avoid creating
3244 self-referential RTL when we will be substituting I0SRC for I0DEST
3246 newpat = subst (newpat, i1dest, i1src, 0, 0,
3247 i0_feeds_i1_n && i0dest_in_i0src);
3250 /* Record whether I1's body now appears within I3's body. */
3251 i1_is_used = n_occurrences;
3254 /* Likewise for I0 if we have it. */
3256 if (i0 && GET_CODE (newpat) != CLOBBER)
3258 if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3259 && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3260 || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3261 && !reg_overlap_mentioned_p (i0dest, newpat))
3262 || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3269 /* If the following substitution will modify I1SRC, make a copy of it
3270 for the case where it is substituted for I1DEST in I2PAT later. */
3271 if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3272 i1src_copy = copy_rtx (i1src);
3275 subst_low_luid = DF_INSN_LUID (i0);
3276 newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3280 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3281 to count all the ways that I2SRC and I1SRC can be used. */
3282 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3283 && i2_is_used + added_sets_2 > 1)
3284 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3285 && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3287 || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3288 && (n_occurrences + added_sets_0
3289 + (added_sets_1 && i0_feeds_i1_n)
3290 + (added_sets_2 && i0_feeds_i2_n)
3292 /* Fail if we tried to make a new register. */
3293 || max_reg_num () != maxreg
3294 /* Fail if we couldn't do something and have a CLOBBER. */
3295 || GET_CODE (newpat) == CLOBBER
3296 /* Fail if this new pattern is a MULT and we didn't have one before
3297 at the outer level. */
3298 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3305 /* If the actions of the earlier insns must be kept
3306 in addition to substituting them into the latest one,
3307 we must make a new PARALLEL for the latest insn
3308 to hold additional the SETs. */
3310 if (added_sets_0 || added_sets_1 || added_sets_2)
3312 int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3315 if (GET_CODE (newpat) == PARALLEL)
3317 rtvec old = XVEC (newpat, 0);
3318 total_sets = XVECLEN (newpat, 0) + extra_sets;
3319 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3320 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3321 sizeof (old->elem[0]) * old->num_elem);
3326 total_sets = 1 + extra_sets;
3327 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3328 XVECEXP (newpat, 0, 0) = old;
3332 XVECEXP (newpat, 0, --total_sets) = i0pat;
3338 t = subst (t, i0dest, i0src, 0, 0, 0);
3340 XVECEXP (newpat, 0, --total_sets) = t;
3346 t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3347 i0_feeds_i1_n && i0dest_in_i0src);
3348 if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3349 t = subst (t, i0dest, i0src, 0, 0, 0);
3351 XVECEXP (newpat, 0, --total_sets) = t;
3355 validate_replacement:
3357 /* Note which hard regs this insn has as inputs. */
3358 mark_used_regs_combine (newpat);
3360 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3361 consider splitting this pattern, we might need these clobbers. */
3362 if (i1 && GET_CODE (newpat) == PARALLEL
3363 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3365 int len = XVECLEN (newpat, 0);
3367 newpat_vec_with_clobbers = rtvec_alloc (len);
3368 for (i = 0; i < len; i++)
3369 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3372 /* Is the result of combination a valid instruction? */
3373 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3375 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3376 the second SET's destination is a register that is unused and isn't
3377 marked as an instruction that might trap in an EH region. In that case,
3378 we just need the first SET. This can occur when simplifying a divmod
3379 insn. We *must* test for this case here because the code below that
3380 splits two independent SETs doesn't handle this case correctly when it
3381 updates the register status.
3383 It's pointless doing this if we originally had two sets, one from
3384 i3, and one from i2. Combining then splitting the parallel results
3385 in the original i2 again plus an invalid insn (which we delete).
3386 The net effect is only to move instructions around, which makes
3387 debug info less accurate.
3389 Also check the case where the first SET's destination is unused.
3390 That would not cause incorrect code, but does cause an unneeded
3393 if (insn_code_number < 0
3394 && !(added_sets_2 && i1 == 0)
3395 && GET_CODE (newpat) == PARALLEL
3396 && XVECLEN (newpat, 0) == 2
3397 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3398 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3399 && asm_noperands (newpat) < 0)
3401 rtx set0 = XVECEXP (newpat, 0, 0);
3402 rtx set1 = XVECEXP (newpat, 0, 1);
3404 if (((REG_P (SET_DEST (set1))
3405 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3406 || (GET_CODE (SET_DEST (set1)) == SUBREG
3407 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3408 && insn_nothrow_p (i3)
3409 && !side_effects_p (SET_SRC (set1)))
3412 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3415 else if (((REG_P (SET_DEST (set0))
3416 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3417 || (GET_CODE (SET_DEST (set0)) == SUBREG
3418 && find_reg_note (i3, REG_UNUSED,
3419 SUBREG_REG (SET_DEST (set0)))))
3420 && insn_nothrow_p (i3)
3421 && !side_effects_p (SET_SRC (set0)))
3424 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3426 if (insn_code_number >= 0)
3427 changed_i3_dest = 1;
3431 /* If we were combining three insns and the result is a simple SET
3432 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3433 insns. There are two ways to do this. It can be split using a
3434 machine-specific method (like when you have an addition of a large
3435 constant) or by combine in the function find_split_point. */
3437 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3438 && asm_noperands (newpat) < 0)
3440 rtx parallel, m_split, *split;
3442 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3443 use I2DEST as a scratch register will help. In the latter case,
3444 convert I2DEST to the mode of the source of NEWPAT if we can. */
3446 m_split = combine_split_insns (newpat, i3);
3448 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3449 inputs of NEWPAT. */
3451 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3452 possible to try that as a scratch reg. This would require adding
3453 more code to make it work though. */
3455 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3457 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3459 /* First try to split using the original register as a
3460 scratch register. */
3461 parallel = gen_rtx_PARALLEL (VOIDmode,
3462 gen_rtvec (2, newpat,
3463 gen_rtx_CLOBBER (VOIDmode,
3465 m_split = combine_split_insns (parallel, i3);
3467 /* If that didn't work, try changing the mode of I2DEST if
3470 && new_mode != GET_MODE (i2dest)
3471 && new_mode != VOIDmode
3472 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3474 enum machine_mode old_mode = GET_MODE (i2dest);
3477 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3478 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3481 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3482 ni2dest = regno_reg_rtx[REGNO (i2dest)];
3485 parallel = (gen_rtx_PARALLEL
3487 gen_rtvec (2, newpat,
3488 gen_rtx_CLOBBER (VOIDmode,
3490 m_split = combine_split_insns (parallel, i3);
3493 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3497 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3498 buf = undobuf.undos;
3499 undobuf.undos = buf->next;
3500 buf->next = undobuf.frees;
3501 undobuf.frees = buf;
3505 i2scratch = m_split != 0;
3508 /* If recog_for_combine has discarded clobbers, try to use them
3509 again for the split. */
3510 if (m_split == 0 && newpat_vec_with_clobbers)
3512 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3513 m_split = combine_split_insns (parallel, i3);
3516 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3518 m_split = PATTERN (m_split);
3519 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3520 if (insn_code_number >= 0)
3523 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3524 && (next_nonnote_nondebug_insn (i2) == i3
3525 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3528 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3529 newi2pat = PATTERN (m_split);
3531 i3set = single_set (NEXT_INSN (m_split));
3532 i2set = single_set (m_split);
3534 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3536 /* If I2 or I3 has multiple SETs, we won't know how to track
3537 register status, so don't use these insns. If I2's destination
3538 is used between I2 and I3, we also can't use these insns. */
3540 if (i2_code_number >= 0 && i2set && i3set
3541 && (next_nonnote_nondebug_insn (i2) == i3
3542 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3543 insn_code_number = recog_for_combine (&newi3pat, i3,
3545 if (insn_code_number >= 0)
3548 /* It is possible that both insns now set the destination of I3.
3549 If so, we must show an extra use of it. */
3551 if (insn_code_number >= 0)
3553 rtx new_i3_dest = SET_DEST (i3set);
3554 rtx new_i2_dest = SET_DEST (i2set);
3556 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3557 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3558 || GET_CODE (new_i3_dest) == SUBREG)
3559 new_i3_dest = XEXP (new_i3_dest, 0);
3561 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3562 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3563 || GET_CODE (new_i2_dest) == SUBREG)
3564 new_i2_dest = XEXP (new_i2_dest, 0);
3566 if (REG_P (new_i3_dest)
3567 && REG_P (new_i2_dest)
3568 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3569 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3573 /* If we can split it and use I2DEST, go ahead and see if that
3574 helps things be recognized. Verify that none of the registers
3575 are set between I2 and I3. */
3576 if (insn_code_number < 0
3577 && (split = find_split_point (&newpat, i3, false)) != 0
3581 /* We need I2DEST in the proper mode. If it is a hard register
3582 or the only use of a pseudo, we can change its mode.
3583 Make sure we don't change a hard register to have a mode that
3584 isn't valid for it, or change the number of registers. */
3585 && (GET_MODE (*split) == GET_MODE (i2dest)
3586 || GET_MODE (*split) == VOIDmode
3587 || can_change_dest_mode (i2dest, added_sets_2,
3589 && (next_nonnote_nondebug_insn (i2) == i3
3590 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3591 /* We can't overwrite I2DEST if its value is still used by
3593 && ! reg_referenced_p (i2dest, newpat))
3595 rtx newdest = i2dest;
3596 enum rtx_code split_code = GET_CODE (*split);
3597 enum machine_mode split_mode = GET_MODE (*split);
3598 bool subst_done = false;
3599 newi2pat = NULL_RTX;
3603 /* *SPLIT may be part of I2SRC, so make sure we have the
3604 original expression around for later debug processing.
3605 We should not need I2SRC any more in other cases. */
3606 if (MAY_HAVE_DEBUG_INSNS)
3607 i2src = copy_rtx (i2src);
3611 /* Get NEWDEST as a register in the proper mode. We have already
3612 validated that we can do this. */
3613 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3615 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3616 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3619 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3620 newdest = regno_reg_rtx[REGNO (i2dest)];
3624 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3625 an ASHIFT. This can occur if it was inside a PLUS and hence
3626 appeared to be a memory address. This is a kludge. */
3627 if (split_code == MULT
3628 && CONST_INT_P (XEXP (*split, 1))
3629 && INTVAL (XEXP (*split, 1)) > 0
3630 && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3632 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3633 XEXP (*split, 0), GEN_INT (i)));
3634 /* Update split_code because we may not have a multiply
3636 split_code = GET_CODE (*split);
3639 #ifdef INSN_SCHEDULING
3640 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3641 be written as a ZERO_EXTEND. */
3642 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3644 #ifdef LOAD_EXTEND_OP
3645 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3646 what it really is. */
3647 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3649 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3650 SUBREG_REG (*split)));
3653 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3654 SUBREG_REG (*split)));
3658 /* Attempt to split binary operators using arithmetic identities. */
3659 if (BINARY_P (SET_SRC (newpat))
3660 && split_mode == GET_MODE (SET_SRC (newpat))
3661 && ! side_effects_p (SET_SRC (newpat)))
3663 rtx setsrc = SET_SRC (newpat);
3664 enum machine_mode mode = GET_MODE (setsrc);
3665 enum rtx_code code = GET_CODE (setsrc);
3666 rtx src_op0 = XEXP (setsrc, 0);
3667 rtx src_op1 = XEXP (setsrc, 1);
3669 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3670 if (rtx_equal_p (src_op0, src_op1))
3672 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3673 SUBST (XEXP (setsrc, 0), newdest);
3674 SUBST (XEXP (setsrc, 1), newdest);
3677 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3678 else if ((code == PLUS || code == MULT)
3679 && GET_CODE (src_op0) == code
3680 && GET_CODE (XEXP (src_op0, 0)) == code
3681 && (INTEGRAL_MODE_P (mode)
3682 || (FLOAT_MODE_P (mode)
3683 && flag_unsafe_math_optimizations)))
3685 rtx p = XEXP (XEXP (src_op0, 0), 0);
3686 rtx q = XEXP (XEXP (src_op0, 0), 1);
3687 rtx r = XEXP (src_op0, 1);
3690 /* Split both "((X op Y) op X) op Y" and
3691 "((X op Y) op Y) op X" as "T op T" where T is
3693 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3694 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3696 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3698 SUBST (XEXP (setsrc, 0), newdest);
3699 SUBST (XEXP (setsrc, 1), newdest);
3702 /* Split "((X op X) op Y) op Y)" as "T op T" where
3704 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3706 rtx tmp = simplify_gen_binary (code, mode, p, r);
3707 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3708 SUBST (XEXP (setsrc, 0), newdest);
3709 SUBST (XEXP (setsrc, 1), newdest);
3717 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3718 SUBST (*split, newdest);
3721 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3723 /* recog_for_combine might have added CLOBBERs to newi2pat.
3724 Make sure NEWPAT does not depend on the clobbered regs. */
3725 if (GET_CODE (newi2pat) == PARALLEL)
3726 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3727 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3729 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3730 if (reg_overlap_mentioned_p (reg, newpat))
3737 /* If the split point was a MULT and we didn't have one before,
3738 don't use one now. */
3739 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3740 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3744 /* Check for a case where we loaded from memory in a narrow mode and
3745 then sign extended it, but we need both registers. In that case,
3746 we have a PARALLEL with both loads from the same memory location.
3747 We can split this into a load from memory followed by a register-register
3748 copy. This saves at least one insn, more if register allocation can
3751 We cannot do this if the destination of the first assignment is a
3752 condition code register or cc0. We eliminate this case by making sure
3753 the SET_DEST and SET_SRC have the same mode.
3755 We cannot do this if the destination of the second assignment is
3756 a register that we have already assumed is zero-extended. Similarly
3757 for a SUBREG of such a register. */
3759 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3760 && GET_CODE (newpat) == PARALLEL
3761 && XVECLEN (newpat, 0) == 2
3762 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3763 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3764 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3765 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3766 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3767 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3768 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3769 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3771 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3772 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3773 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3775 && VEC_index (reg_stat_type, reg_stat,
3776 REGNO (temp))->nonzero_bits != 0
3777 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3778 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3779 && (VEC_index (reg_stat_type, reg_stat,
3780 REGNO (temp))->nonzero_bits
3781 != GET_MODE_MASK (word_mode))))
3782 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3783 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3785 && VEC_index (reg_stat_type, reg_stat,
3786 REGNO (temp))->nonzero_bits != 0
3787 && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3788 && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3789 && (VEC_index (reg_stat_type, reg_stat,
3790 REGNO (temp))->nonzero_bits
3791 != GET_MODE_MASK (word_mode)))))
3792 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3793 SET_SRC (XVECEXP (newpat, 0, 1)))
3794 && ! find_reg_note (i3, REG_UNUSED,
3795 SET_DEST (XVECEXP (newpat, 0, 0))))
3799 newi2pat = XVECEXP (newpat, 0, 0);
3800 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3801 newpat = XVECEXP (newpat, 0, 1);
3802 SUBST (SET_SRC (newpat),
3803 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3804 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3806 if (i2_code_number >= 0)
3807 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3809 if (insn_code_number >= 0)
3813 /* Similarly, check for a case where we have a PARALLEL of two independent
3814 SETs but we started with three insns. In this case, we can do the sets
3815 as two separate insns. This case occurs when some SET allows two
3816 other insns to combine, but the destination of that SET is still live. */
3818 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3819 && GET_CODE (newpat) == PARALLEL
3820 && XVECLEN (newpat, 0) == 2
3821 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3822 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3823 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3824 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3825 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3826 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3827 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3828 XVECEXP (newpat, 0, 0))
3829 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3830 XVECEXP (newpat, 0, 1))
3831 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3832 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3834 /* Normally, it doesn't matter which of the two is done first,
3835 but the one that references cc0 can't be the second, and
3836 one which uses any regs/memory set in between i2 and i3 can't
3838 if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3841 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3845 newi2pat = XVECEXP (newpat, 0, 1);
3846 newpat = XVECEXP (newpat, 0, 0);
3848 else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3851 && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3855 newi2pat = XVECEXP (newpat, 0, 0);
3856 newpat = XVECEXP (newpat, 0, 1);
3864 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3866 if (i2_code_number >= 0)
3868 /* recog_for_combine might have added CLOBBERs to newi2pat.
3869 Make sure NEWPAT does not depend on the clobbered regs. */
3870 if (GET_CODE (newi2pat) == PARALLEL)
3872 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3873 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3875 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3876 if (reg_overlap_mentioned_p (reg, newpat))
3884 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3888 /* If it still isn't recognized, fail and change things back the way they
3890 if ((insn_code_number < 0
3891 /* Is the result a reasonable ASM_OPERANDS? */
3892 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3898 /* If we had to change another insn, make sure it is valid also. */
3899 if (undobuf.other_insn)
3901 CLEAR_HARD_REG_SET (newpat_used_regs);
3903 other_pat = PATTERN (undobuf.other_insn);
3904 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3907 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3915 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3916 they are adjacent to each other or not. */
3918 rtx p = prev_nonnote_insn (i3);
3919 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3920 && sets_cc0_p (newi2pat))
3928 /* Only allow this combination if insn_rtx_costs reports that the
3929 replacement instructions are cheaper than the originals. */
3930 if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3936 if (MAY_HAVE_DEBUG_INSNS)
3940 for (undo = undobuf.undos; undo; undo = undo->next)
3941 if (undo->kind == UNDO_MODE)
3943 rtx reg = *undo->where.r;
3944 enum machine_mode new_mode = GET_MODE (reg);
3945 enum machine_mode old_mode = undo->old_contents.m;
3947 /* Temporarily revert mode back. */
3948 adjust_reg_mode (reg, old_mode);
3950 if (reg == i2dest && i2scratch)
3952 /* If we used i2dest as a scratch register with a
3953 different mode, substitute it for the original
3954 i2src while its original mode is temporarily
3955 restored, and then clear i2scratch so that we don't
3956 do it again later. */
3957 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3959 /* Put back the new mode. */
3960 adjust_reg_mode (reg, new_mode);
3964 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3970 last = last_combined_insn;
3975 last = undobuf.other_insn;
3977 if (DF_INSN_LUID (last)
3978 < DF_INSN_LUID (last_combined_insn))
3979 last = last_combined_insn;
3982 /* We're dealing with a reg that changed mode but not
3983 meaning, so we want to turn it into a subreg for
3984 the new mode. However, because of REG sharing and
3985 because its mode had already changed, we have to do
3986 it in two steps. First, replace any debug uses of
3987 reg, with its original mode temporarily restored,
3988 with this copy we have created; then, replace the
3989 copy with the SUBREG of the original shared reg,
3990 once again changed to the new mode. */
3991 propagate_for_debug (first, last, reg, tempreg);
3992 adjust_reg_mode (reg, new_mode);
3993 propagate_for_debug (first, last, tempreg,
3994 lowpart_subreg (old_mode, reg, new_mode));
3999 /* If we will be able to accept this, we have made a
4000 change to the destination of I3. This requires us to
4001 do a few adjustments. */
4003 if (changed_i3_dest)
4005 PATTERN (i3) = newpat;
4006 adjust_for_new_dest (i3);
4009 /* We now know that we can do this combination. Merge the insns and
4010 update the status of registers and LOG_LINKS. */
4012 if (undobuf.other_insn)
4016 PATTERN (undobuf.other_insn) = other_pat;
4018 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4019 are still valid. Then add any non-duplicate notes added by
4020 recog_for_combine. */
4021 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4023 next = XEXP (note, 1);
4025 if (REG_NOTE_KIND (note) == REG_UNUSED
4026 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4027 remove_note (undobuf.other_insn, note);
4030 distribute_notes (new_other_notes, undobuf.other_insn,
4031 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4038 struct insn_link *link;
4041 /* I3 now uses what used to be its destination and which is now
4042 I2's destination. This requires us to do a few adjustments. */
4043 PATTERN (i3) = newpat;
4044 adjust_for_new_dest (i3);
4046 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4049 However, some later insn might be using I2's dest and have
4050 a LOG_LINK pointing at I3. We must remove this link.
4051 The simplest way to remove the link is to point it at I1,
4052 which we know will be a NOTE. */
4054 /* newi2pat is usually a SET here; however, recog_for_combine might
4055 have added some clobbers. */
4056 if (GET_CODE (newi2pat) == PARALLEL)
4057 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4059 ni2dest = SET_DEST (newi2pat);
4061 for (insn = NEXT_INSN (i3);
4062 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4063 || insn != BB_HEAD (this_basic_block->next_bb));
4064 insn = NEXT_INSN (insn))
4066 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4068 FOR_EACH_LOG_LINK (link, insn)
4069 if (link->insn == i3)
4078 rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4079 struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4082 /* Compute which registers we expect to eliminate. newi2pat may be setting
4083 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4084 same as i3dest, in which case newi2pat may be setting i1dest. */
4085 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4086 || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4089 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4090 || (newi2pat && reg_set_p (i1dest, newi2pat))
4093 rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4094 || (newi2pat && reg_set_p (i0dest, newi2pat))
4098 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4100 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4101 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4103 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4105 i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4107 /* Ensure that we do not have something that should not be shared but
4108 occurs multiple times in the new insns. Check this by first
4109 resetting all the `used' flags and then copying anything is shared. */
4111 reset_used_flags (i3notes);
4112 reset_used_flags (i2notes);
4113 reset_used_flags (i1notes);
4114 reset_used_flags (i0notes);
4115 reset_used_flags (newpat);
4116 reset_used_flags (newi2pat);
4117 if (undobuf.other_insn)
4118 reset_used_flags (PATTERN (undobuf.other_insn));
4120 i3notes = copy_rtx_if_shared (i3notes);
4121 i2notes = copy_rtx_if_shared (i2notes);
4122 i1notes = copy_rtx_if_shared (i1notes);
4123 i0notes = copy_rtx_if_shared (i0notes);
4124 newpat = copy_rtx_if_shared (newpat);
4125 newi2pat = copy_rtx_if_shared (newi2pat);
4126 if (undobuf.other_insn)
4127 reset_used_flags (PATTERN (undobuf.other_insn));
4129 INSN_CODE (i3) = insn_code_number;
4130 PATTERN (i3) = newpat;
4132 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4134 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4136 reset_used_flags (call_usage);
4137 call_usage = copy_rtx (call_usage);
4141 /* I2SRC must still be meaningful at this point. Some splitting
4142 operations can invalidate I2SRC, but those operations do not
4145 replace_rtx (call_usage, i2dest, i2src);
4149 replace_rtx (call_usage, i1dest, i1src);
4151 replace_rtx (call_usage, i0dest, i0src);
4153 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4156 if (undobuf.other_insn)
4157 INSN_CODE (undobuf.other_insn) = other_code_number;
4159 /* We had one special case above where I2 had more than one set and
4160 we replaced a destination of one of those sets with the destination
4161 of I3. In that case, we have to update LOG_LINKS of insns later
4162 in this basic block. Note that this (expensive) case is rare.
4164 Also, in this case, we must pretend that all REG_NOTEs for I2
4165 actually came from I3, so that REG_UNUSED notes from I2 will be
4166 properly handled. */
4168 if (i3_subst_into_i2)
4170 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4171 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4172 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4173 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4174 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4175 && ! find_reg_note (i2, REG_UNUSED,
4176 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4177 for (temp = NEXT_INSN (i2);
4178 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4179 || BB_HEAD (this_basic_block) != temp);
4180 temp = NEXT_INSN (temp))
4181 if (temp != i3 && INSN_P (temp))
4182 FOR_EACH_LOG_LINK (link, temp)
4183 if (link->insn == i2)
4189 while (XEXP (link, 1))
4190 link = XEXP (link, 1);
4191 XEXP (link, 1) = i2notes;
4198 LOG_LINKS (i3) = NULL;
4200 LOG_LINKS (i2) = NULL;
4205 if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4206 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4207 INSN_CODE (i2) = i2_code_number;
4208 PATTERN (i2) = newi2pat;
4212 if (MAY_HAVE_DEBUG_INSNS && i2src)
4213 propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4214 SET_INSN_DELETED (i2);
4219 LOG_LINKS (i1) = NULL;
4221 if (MAY_HAVE_DEBUG_INSNS)
4222 propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4223 SET_INSN_DELETED (i1);
4228 LOG_LINKS (i0) = NULL;
4230 if (MAY_HAVE_DEBUG_INSNS)
4231 propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4232 SET_INSN_DELETED (i0);
4235 /* Get death notes for everything that is now used in either I3 or
4236 I2 and used to die in a previous insn. If we built two new
4237 patterns, move from I1 to I2 then I2 to I3 so that we get the
4238 proper movement on registers that I2 modifies. */
4241 from_luid = DF_INSN_LUID (i0);
4243 from_luid = DF_INSN_LUID (i1);
4245 from_luid = DF_INSN_LUID (i2);
4247 move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4248 move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4250 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4252 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4253 elim_i2, elim_i1, elim_i0);
4255 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4256 elim_i2, elim_i1, elim_i0);
4258 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4259 elim_i2, elim_i1, elim_i0);
4261 distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4262 elim_i2, elim_i1, elim_i0);
4264 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4265 elim_i2, elim_i1, elim_i0);
4267 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4268 know these are REG_UNUSED and want them to go to the desired insn,
4269 so we always pass it as i3. */
4271 if (newi2pat && new_i2_notes)
4272 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4276 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4279 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4280 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4281 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4282 in that case, it might delete I2. Similarly for I2 and I1.
4283 Show an additional death due to the REG_DEAD note we make here. If
4284 we discard it in distribute_notes, we will decrement it again. */
4288 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4289 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4291 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4293 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4295 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4296 elim_i2, elim_i1, elim_i0);
4299 if (i2dest_in_i2src)
4301 rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4302 if (newi2pat && reg_set_p (i2dest, newi2pat))
4303 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4304 NULL_RTX, NULL_RTX);
4306 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4307 NULL_RTX, NULL_RTX, NULL_RTX);
4310 if (i1dest_in_i1src)
4312 rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4313 if (newi2pat && reg_set_p (i1dest, newi2pat))
4314 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4315 NULL_RTX, NULL_RTX);
4317 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4318 NULL_RTX, NULL_RTX, NULL_RTX);
4321 if (i0dest_in_i0src)
4323 rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4324 if (newi2pat && reg_set_p (i0dest, newi2pat))
4325 distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4326 NULL_RTX, NULL_RTX);
4328 distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4329 NULL_RTX, NULL_RTX, NULL_RTX);
4332 distribute_links (i3links);
4333 distribute_links (i2links);
4334 distribute_links (i1links);
4335 distribute_links (i0links);
4339 struct insn_link *link;
4340 rtx i2_insn = 0, i2_val = 0, set;
4342 /* The insn that used to set this register doesn't exist, and
4343 this life of the register may not exist either. See if one of
4344 I3's links points to an insn that sets I2DEST. If it does,
4345 that is now the last known value for I2DEST. If we don't update
4346 this and I2 set the register to a value that depended on its old
4347 contents, we will get confused. If this insn is used, thing
4348 will be set correctly in combine_instructions. */
4349 FOR_EACH_LOG_LINK (link, i3)
4350 if ((set = single_set (link->insn)) != 0
4351 && rtx_equal_p (i2dest, SET_DEST (set)))
4352 i2_insn = link->insn, i2_val = SET_SRC (set);
4354 record_value_for_reg (i2dest, i2_insn, i2_val);
4356 /* If the reg formerly set in I2 died only once and that was in I3,
4357 zero its use count so it won't make `reload' do any work. */
4359 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4360 && ! i2dest_in_i2src)
4361 INC_REG_N_SETS (REGNO (i2dest), -1);
4364 if (i1 && REG_P (i1dest))
4366 struct insn_link *link;
4367 rtx i1_insn = 0, i1_val = 0, set;
4369 FOR_EACH_LOG_LINK (link, i3)
4370 if ((set = single_set (link->insn)) != 0
4371 && rtx_equal_p (i1dest, SET_DEST (set)))
4372 i1_insn = link->insn, i1_val = SET_SRC (set);
4374 record_value_for_reg (i1dest, i1_insn, i1_val);
4376 if (! added_sets_1 && ! i1dest_in_i1src)
4377 INC_REG_N_SETS (REGNO (i1dest), -1);
4380 if (i0 && REG_P (i0dest))
4382 struct insn_link *link;
4383 rtx i0_insn = 0, i0_val = 0, set;
4385 FOR_EACH_LOG_LINK (link, i3)
4386 if ((set = single_set (link->insn)) != 0
4387 && rtx_equal_p (i0dest, SET_DEST (set)))
4388 i0_insn = link->insn, i0_val = SET_SRC (set);
4390 record_value_for_reg (i0dest, i0_insn, i0_val);
4392 if (! added_sets_0 && ! i0dest_in_i0src)
4393 INC_REG_N_SETS (REGNO (i0dest), -1);
4396 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4397 been made to this insn. The order of
4398 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
4399 can affect nonzero_bits of newpat */
4401 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4402 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4405 if (undobuf.other_insn != NULL_RTX)
4409 fprintf (dump_file, "modifying other_insn ");
4410 dump_insn_slim (dump_file, undobuf.other_insn);
4412 df_insn_rescan (undobuf.other_insn);
4415 if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4419 fprintf (dump_file, "modifying insn i1 ");
4420 dump_insn_slim (dump_file, i0);
4422 df_insn_rescan (i0);
4425 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4429 fprintf (dump_file, "modifying insn i1 ");
4430 dump_insn_slim (dump_file, i1);
4432 df_insn_rescan (i1);
4435 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4439 fprintf (dump_file, "modifying insn i2 ");
4440 dump_insn_slim (dump_file, i2);
4442 df_insn_rescan (i2);
4445 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4449 fprintf (dump_file, "modifying insn i3 ");
4450 dump_insn_slim (dump_file, i3);
4452 df_insn_rescan (i3);
4455 /* Set new_direct_jump_p if a new return or simple jump instruction
4456 has been created. Adjust the CFG accordingly. */
4458 if (returnjump_p (i3) || any_uncondjump_p (i3))
4460 *new_direct_jump_p = 1;
4461 mark_jump_label (PATTERN (i3), i3, 0);
4462 update_cfg_for_uncondjump (i3);
4465 if (undobuf.other_insn != NULL_RTX
4466 && (returnjump_p (undobuf.other_insn)
4467 || any_uncondjump_p (undobuf.other_insn)))
4469 *new_direct_jump_p = 1;
4470 update_cfg_for_uncondjump (undobuf.other_insn);
4473 /* A noop might also need cleaning up of CFG, if it comes from the
4474 simplification of a jump. */
4476 && GET_CODE (newpat) == SET
4477 && SET_SRC (newpat) == pc_rtx
4478 && SET_DEST (newpat) == pc_rtx)
4480 *new_direct_jump_p = 1;
4481 update_cfg_for_uncondjump (i3);
4484 if (undobuf.other_insn != NULL_RTX
4485 && JUMP_P (undobuf.other_insn)
4486 && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4487 && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4488 && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4490 *new_direct_jump_p = 1;
4491 update_cfg_for_uncondjump (undobuf.other_insn);
4494 combine_successes++;
4497 if (added_links_insn
4498 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4499 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4500 return added_links_insn;
4502 return newi2pat ? i2 : i3;
4505 /* Undo all the modifications recorded in undobuf. */
4510 struct undo *undo, *next;
4512 for (undo = undobuf.undos; undo; undo = next)
4518 *undo->where.r = undo->old_contents.r;
4521 *undo->where.i = undo->old_contents.i;
4524 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4527 *undo->where.l = undo->old_contents.l;
4533 undo->next = undobuf.frees;
4534 undobuf.frees = undo;
4540 /* We've committed to accepting the changes we made. Move all
4541 of the undos to the free list. */
4546 struct undo *undo, *next;
4548 for (undo = undobuf.undos; undo; undo = next)
4551 undo->next = undobuf.frees;
4552 undobuf.frees = undo;
4557 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4558 where we have an arithmetic expression and return that point. LOC will
4561 try_combine will call this function to see if an insn can be split into
4565 find_split_point (rtx *loc, rtx insn, bool set_src)
4568 enum rtx_code code = GET_CODE (x);
4570 unsigned HOST_WIDE_INT len = 0;
4571 HOST_WIDE_INT pos = 0;
4573 rtx inner = NULL_RTX;
4575 /* First special-case some codes. */
4579 #ifdef INSN_SCHEDULING
4580 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4582 if (MEM_P (SUBREG_REG (x)))
4585 return find_split_point (&SUBREG_REG (x), insn, false);
4589 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4590 using LO_SUM and HIGH. */
4591 if (GET_CODE (XEXP (x, 0)) == CONST
4592 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4594 enum machine_mode address_mode
4595 = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4598 gen_rtx_LO_SUM (address_mode,
4599 gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4601 return &XEXP (XEXP (x, 0), 0);
4605 /* If we have a PLUS whose second operand is a constant and the
4606 address is not valid, perhaps will can split it up using
4607 the machine-specific way to split large constants. We use
4608 the first pseudo-reg (one of the virtual regs) as a placeholder;
4609 it will not remain in the result. */
4610 if (GET_CODE (XEXP (x, 0)) == PLUS
4611 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4612 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4613 MEM_ADDR_SPACE (x)))
4615 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4616 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4620 /* This should have produced two insns, each of which sets our
4621 placeholder. If the source of the second is a valid address,
4622 we can make put both sources together and make a split point
4626 && NEXT_INSN (seq) != NULL_RTX
4627 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4628 && NONJUMP_INSN_P (seq)
4629 && GET_CODE (PATTERN (seq)) == SET
4630 && SET_DEST (PATTERN (seq)) == reg
4631 && ! reg_mentioned_p (reg,
4632 SET_SRC (PATTERN (seq)))
4633 && NONJUMP_INSN_P (NEXT_INSN (seq))
4634 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4635 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4636 && memory_address_addr_space_p
4637 (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4638 MEM_ADDR_SPACE (x)))
4640 rtx src1 = SET_SRC (PATTERN (seq));
4641 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4643 /* Replace the placeholder in SRC2 with SRC1. If we can
4644 find where in SRC2 it was placed, that can become our
4645 split point and we can replace this address with SRC2.
4646 Just try two obvious places. */
4648 src2 = replace_rtx (src2, reg, src1);
4650 if (XEXP (src2, 0) == src1)
4651 split = &XEXP (src2, 0);
4652 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4653 && XEXP (XEXP (src2, 0), 0) == src1)
4654 split = &XEXP (XEXP (src2, 0), 0);
4658 SUBST (XEXP (x, 0), src2);
4663 /* If that didn't work, perhaps the first operand is complex and
4664 needs to be computed separately, so make a split point there.
4665 This will occur on machines that just support REG + CONST
4666 and have a constant moved through some previous computation. */
4668 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4669 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4670 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4671 return &XEXP (XEXP (x, 0), 0);
4674 /* If we have a PLUS whose first operand is complex, try computing it
4675 separately by making a split there. */
4676 if (GET_CODE (XEXP (x, 0)) == PLUS
4677 && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4679 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4680 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4681 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4682 return &XEXP (XEXP (x, 0), 0);
4687 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4688 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4689 we need to put the operand into a register. So split at that
4692 if (SET_DEST (x) == cc0_rtx
4693 && GET_CODE (SET_SRC (x)) != COMPARE
4694 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4695 && !OBJECT_P (SET_SRC (x))
4696 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4697 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4698 return &SET_SRC (x);
4701 /* See if we can split SET_SRC as it stands. */
4702 split = find_split_point (&SET_SRC (x), insn, true);
4703 if (split && split != &SET_SRC (x))
4706 /* See if we can split SET_DEST as it stands. */
4707 split = find_split_point (&SET_DEST (x), insn, false);
4708 if (split && split != &SET_DEST (x))
4711 /* See if this is a bitfield assignment with everything constant. If
4712 so, this is an IOR of an AND, so split it into that. */
4713 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4714 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4715 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4716 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4717 && CONST_INT_P (SET_SRC (x))
4718 && ((INTVAL (XEXP (SET_DEST (x), 1))
4719 + INTVAL (XEXP (SET_DEST (x), 2)))
4720 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4721 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4723 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4724 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4725 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4726 rtx dest = XEXP (SET_DEST (x), 0);
4727 enum machine_mode mode = GET_MODE (dest);
4728 unsigned HOST_WIDE_INT mask
4729 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4732 if (BITS_BIG_ENDIAN)
4733 pos = GET_MODE_PRECISION (mode) - len - pos;
4735 or_mask = gen_int_mode (src << pos, mode);
4738 simplify_gen_binary (IOR, mode, dest, or_mask));
4741 rtx negmask = gen_int_mode (~(mask << pos), mode);
4743 simplify_gen_binary (IOR, mode,
4744 simplify_gen_binary (AND, mode,
4749 SUBST (SET_DEST (x), dest);
4751 split = find_split_point (&SET_SRC (x), insn, true);
4752 if (split && split != &SET_SRC (x))
4756 /* Otherwise, see if this is an operation that we can split into two.
4757 If so, try to split that. */
4758 code = GET_CODE (SET_SRC (x));
4763 /* If we are AND'ing with a large constant that is only a single
4764 bit and the result is only being used in a context where we
4765 need to know if it is zero or nonzero, replace it with a bit
4766 extraction. This will avoid the large constant, which might
4767 have taken more than one insn to make. If the constant were
4768 not a valid argument to the AND but took only one insn to make,
4769 this is no worse, but if it took more than one insn, it will
4772 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4773 && REG_P (XEXP (SET_SRC (x), 0))
4774 && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4775 && REG_P (SET_DEST (x))
4776 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4777 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4778 && XEXP (*split, 0) == SET_DEST (x)
4779 && XEXP (*split, 1) == const0_rtx)
4781 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4782 XEXP (SET_SRC (x), 0),
4783 pos, NULL_RTX, 1, 1, 0, 0);
4784 if (extraction != 0)
4786 SUBST (SET_SRC (x), extraction);
4787 return find_split_point (loc, insn, false);
4793 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4794 is known to be on, this can be converted into a NEG of a shift. */
4795 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4796 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4797 && 1 <= (pos = exact_log2
4798 (nonzero_bits (XEXP (SET_SRC (x), 0),
4799 GET_MODE (XEXP (SET_SRC (x), 0))))))
4801 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4805 gen_rtx_LSHIFTRT (mode,
4806 XEXP (SET_SRC (x), 0),
4809 split = find_split_point (&SET_SRC (x), insn, true);
4810 if (split && split != &SET_SRC (x))
4816 inner = XEXP (SET_SRC (x), 0);
4818 /* We can't optimize if either mode is a partial integer
4819 mode as we don't know how many bits are significant
4821 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4822 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4826 len = GET_MODE_PRECISION (GET_MODE (inner));
4832 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4833 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4835 inner = XEXP (SET_SRC (x), 0);
4836 len = INTVAL (XEXP (SET_SRC (x), 1));
4837 pos = INTVAL (XEXP (SET_SRC (x), 2));
4839 if (BITS_BIG_ENDIAN)
4840 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4841 unsignedp = (code == ZERO_EXTRACT);
4850 && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4852 enum machine_mode mode = GET_MODE (SET_SRC (x));
4854 /* For unsigned, we have a choice of a shift followed by an
4855 AND or two shifts. Use two shifts for field sizes where the
4856 constant might be too large. We assume here that we can
4857 always at least get 8-bit constants in an AND insn, which is
4858 true for every current RISC. */
4860 if (unsignedp && len <= 8)
4865 (mode, gen_lowpart (mode, inner),
4867 GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4870 split = find_split_point (&SET_SRC (x), insn, true);
4871 if (split && split != &SET_SRC (x))
4878 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4879 gen_rtx_ASHIFT (mode,
4880 gen_lowpart (mode, inner),
4881 GEN_INT (GET_MODE_PRECISION (mode)
4883 GEN_INT (GET_MODE_PRECISION (mode) - len)));
4885 split = find_split_point (&SET_SRC (x), insn, true);
4886 if (split && split != &SET_SRC (x))
4891 /* See if this is a simple operation with a constant as the second
4892 operand. It might be that this constant is out of range and hence
4893 could be used as a split point. */
4894 if (BINARY_P (SET_SRC (x))
4895 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4896 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4897 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4898 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4899 return &XEXP (SET_SRC (x), 1);
4901 /* Finally, see if this is a simple operation with its first operand
4902 not in a register. The operation might require this operand in a
4903 register, so return it as a split point. We can always do this
4904 because if the first operand were another operation, we would have
4905 already found it as a split point. */
4906 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4907 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4908 return &XEXP (SET_SRC (x), 0);
4914 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4915 it is better to write this as (not (ior A B)) so we can split it.
4916 Similarly for IOR. */
4917 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4920 gen_rtx_NOT (GET_MODE (x),
4921 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4923 XEXP (XEXP (x, 0), 0),
4924 XEXP (XEXP (x, 1), 0))));
4925 return find_split_point (loc, insn, set_src);
4928 /* Many RISC machines have a large set of logical insns. If the
4929 second operand is a NOT, put it first so we will try to split the
4930 other operand first. */
4931 if (GET_CODE (XEXP (x, 1)) == NOT)
4933 rtx tem = XEXP (x, 0);
4934 SUBST (XEXP (x, 0), XEXP (x, 1));
4935 SUBST (XEXP (x, 1), tem);
4941 /* Canonicalization can produce (minus A (mult B C)), where C is a
4942 constant. It may be better to try splitting (plus (mult B -C) A)
4943 instead if this isn't a multiply by a power of two. */
4944 if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4945 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4946 && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4948 enum machine_mode mode = GET_MODE (x);
4949 unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4950 HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4951 SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4952 XEXP (XEXP (x, 1), 0),
4953 GEN_INT (other_int)),
4955 return find_split_point (loc, insn, set_src);
4958 /* Split at a multiply-accumulate instruction. However if this is
4959 the SET_SRC, we likely do not have such an instruction and it's
4960 worthless to try this split. */
4961 if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4968 /* Otherwise, select our actions depending on our rtx class. */
4969 switch (GET_RTX_CLASS (code))
4971 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4973 split = find_split_point (&XEXP (x, 2), insn, false);
4976 /* ... fall through ... */
4978 case RTX_COMM_ARITH:
4980 case RTX_COMM_COMPARE:
4981 split = find_split_point (&XEXP (x, 1), insn, false);
4984 /* ... fall through ... */
4986 /* Some machines have (and (shift ...) ...) insns. If X is not
4987 an AND, but XEXP (X, 0) is, use it as our split point. */
4988 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4989 return &XEXP (x, 0);
4991 split = find_split_point (&XEXP (x, 0), insn, false);
4997 /* Otherwise, we don't have a split point. */
5002 /* Throughout X, replace FROM with TO, and return the result.
5003 The result is TO if X is FROM;
5004 otherwise the result is X, but its contents may have been modified.
5005 If they were modified, a record was made in undobuf so that
5006 undo_all will (among other things) return X to its original state.
5008 If the number of changes necessary is too much to record to undo,
5009 the excess changes are not made, so the result is invalid.
5010 The changes already made can still be undone.
5011 undobuf.num_undo is incremented for such changes, so by testing that
5012 the caller can tell whether the result is valid.
5014 `n_occurrences' is incremented each time FROM is replaced.
5016 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5018 IN_COND is nonzero if we are at the top level of a condition.
5020 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5021 by copying if `n_occurrences' is nonzero. */
5024 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5026 enum rtx_code code = GET_CODE (x);
5027 enum machine_mode op0_mode = VOIDmode;
5032 /* Two expressions are equal if they are identical copies of a shared
5033 RTX or if they are both registers with the same register number
5036 #define COMBINE_RTX_EQUAL_P(X,Y) \
5038 || (REG_P (X) && REG_P (Y) \
5039 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5041 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5044 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5047 /* If X and FROM are the same register but different modes, they
5048 will not have been seen as equal above. However, the log links code
5049 will make a LOG_LINKS entry for that case. If we do nothing, we
5050 will try to rerecognize our original insn and, when it succeeds,
5051 we will delete the feeding insn, which is incorrect.
5053 So force this insn not to match in this (rare) case. */
5054 if (! in_dest && code == REG && REG_P (from)
5055 && reg_overlap_mentioned_p (x, from))
5056 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5058 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5059 of which may contain things that can be combined. */
5060 if (code != MEM && code != LO_SUM && OBJECT_P (x))
5063 /* It is possible to have a subexpression appear twice in the insn.
5064 Suppose that FROM is a register that appears within TO.
5065 Then, after that subexpression has been scanned once by `subst',
5066 the second time it is scanned, TO may be found. If we were
5067 to scan TO here, we would find FROM within it and create a
5068 self-referent rtl structure which is completely wrong. */
5069 if (COMBINE_RTX_EQUAL_P (x, to))
5072 /* Parallel asm_operands need special attention because all of the
5073 inputs are shared across the arms. Furthermore, unsharing the
5074 rtl results in recognition failures. Failure to handle this case
5075 specially can result in circular rtl.
5077 Solve this by doing a normal pass across the first entry of the
5078 parallel, and only processing the SET_DESTs of the subsequent
5081 if (code == PARALLEL
5082 && GET_CODE (XVECEXP (x, 0, 0)) == SET
5083 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5085 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5087 /* If this substitution failed, this whole thing fails. */
5088 if (GET_CODE (new_rtx) == CLOBBER
5089 && XEXP (new_rtx, 0) == const0_rtx)
5092 SUBST (XVECEXP (x, 0, 0), new_rtx);
5094 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5096 rtx dest = SET_DEST (XVECEXP (x, 0, i));
5099 && GET_CODE (dest) != CC0
5100 && GET_CODE (dest) != PC)
5102 new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5104 /* If this substitution failed, this whole thing fails. */
5105 if (GET_CODE (new_rtx) == CLOBBER
5106 && XEXP (new_rtx, 0) == const0_rtx)
5109 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5115 len = GET_RTX_LENGTH (code);
5116 fmt = GET_RTX_FORMAT (code);
5118 /* We don't need to process a SET_DEST that is a register, CC0,
5119 or PC, so set up to skip this common case. All other cases
5120 where we want to suppress replacing something inside a
5121 SET_SRC are handled via the IN_DEST operand. */
5123 && (REG_P (SET_DEST (x))
5124 || GET_CODE (SET_DEST (x)) == CC0
5125 || GET_CODE (SET_DEST (x)) == PC))
5128 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5131 op0_mode = GET_MODE (XEXP (x, 0));
5133 for (i = 0; i < len; i++)
5138 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5140 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5142 new_rtx = (unique_copy && n_occurrences
5143 ? copy_rtx (to) : to);
5148 new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5151 /* If this substitution failed, this whole thing
5153 if (GET_CODE (new_rtx) == CLOBBER
5154 && XEXP (new_rtx, 0) == const0_rtx)
5158 SUBST (XVECEXP (x, i, j), new_rtx);
5161 else if (fmt[i] == 'e')
5163 /* If this is a register being set, ignore it. */
5164 new_rtx = XEXP (x, i);
5167 && (((code == SUBREG || code == ZERO_EXTRACT)
5169 || code == STRICT_LOW_PART))
5172 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5174 /* In general, don't install a subreg involving two
5175 modes not tieable. It can worsen register
5176 allocation, and can even make invalid reload
5177 insns, since the reg inside may need to be copied
5178 from in the outside mode, and that may be invalid
5179 if it is an fp reg copied in integer mode.
5181 We allow two exceptions to this: It is valid if
5182 it is inside another SUBREG and the mode of that
5183 SUBREG and the mode of the inside of TO is
5184 tieable and it is valid if X is a SET that copies
5187 if (GET_CODE (to) == SUBREG
5188 && ! MODES_TIEABLE_P (GET_MODE (to),
5189 GET_MODE (SUBREG_REG (to)))
5190 && ! (code == SUBREG
5191 && MODES_TIEABLE_P (GET_MODE (x),
5192 GET_MODE (SUBREG_REG (to))))
5194 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5197 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5199 #ifdef CANNOT_CHANGE_MODE_CLASS
5202 && REGNO (to) < FIRST_PSEUDO_REGISTER
5203 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5206 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5209 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5213 /* If we are in a SET_DEST, suppress most cases unless we
5214 have gone inside a MEM, in which case we want to
5215 simplify the address. We assume here that things that
5216 are actually part of the destination have their inner
5217 parts in the first expression. This is true for SUBREG,
5218 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5219 things aside from REG and MEM that should appear in a
5221 new_rtx = subst (XEXP (x, i), from, to,
5223 && (code == SUBREG || code == STRICT_LOW_PART
5224 || code == ZERO_EXTRACT))
5227 code == IF_THEN_ELSE && i == 0,
5230 /* If we found that we will have to reject this combination,
5231 indicate that by returning the CLOBBER ourselves, rather than
5232 an expression containing it. This will speed things up as
5233 well as prevent accidents where two CLOBBERs are considered
5234 to be equal, thus producing an incorrect simplification. */
5236 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5239 if (GET_CODE (x) == SUBREG
5240 && (CONST_INT_P (new_rtx)
5241 || GET_CODE (new_rtx) == CONST_DOUBLE))
5243 enum machine_mode mode = GET_MODE (x);
5245 x = simplify_subreg (GET_MODE (x), new_rtx,
5246 GET_MODE (SUBREG_REG (x)),
5249 x = gen_rtx_CLOBBER (mode, const0_rtx);
5251 else if (CONST_INT_P (new_rtx)
5252 && GET_CODE (x) == ZERO_EXTEND)
5254 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5255 new_rtx, GET_MODE (XEXP (x, 0)));
5259 SUBST (XEXP (x, i), new_rtx);
5264 /* Check if we are loading something from the constant pool via float
5265 extension; in this case we would undo compress_float_constant
5266 optimization and degenerate constant load to an immediate value. */
5267 if (GET_CODE (x) == FLOAT_EXTEND
5268 && MEM_P (XEXP (x, 0))
5269 && MEM_READONLY_P (XEXP (x, 0)))
5271 rtx tmp = avoid_constant_pool_reference (x);
5276 /* Try to simplify X. If the simplification changed the code, it is likely
5277 that further simplification will help, so loop, but limit the number
5278 of repetitions that will be performed. */
5280 for (i = 0; i < 4; i++)
5282 /* If X is sufficiently simple, don't bother trying to do anything
5284 if (code != CONST_INT && code != REG && code != CLOBBER)
5285 x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5287 if (GET_CODE (x) == code)
5290 code = GET_CODE (x);
5292 /* We no longer know the original mode of operand 0 since we
5293 have changed the form of X) */
5294 op0_mode = VOIDmode;
5300 /* Simplify X, a piece of RTL. We just operate on the expression at the
5301 outer level; call `subst' to simplify recursively. Return the new
5304 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5305 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5309 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5312 enum rtx_code code = GET_CODE (x);
5313 enum machine_mode mode = GET_MODE (x);
5317 /* If this is a commutative operation, put a constant last and a complex
5318 expression first. We don't need to do this for comparisons here. */
5319 if (COMMUTATIVE_ARITH_P (x)
5320 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5323 SUBST (XEXP (x, 0), XEXP (x, 1));
5324 SUBST (XEXP (x, 1), temp);
5327 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5328 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5329 things. Check for cases where both arms are testing the same
5332 Don't do anything if all operands are very simple. */
5335 && ((!OBJECT_P (XEXP (x, 0))
5336 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5337 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5338 || (!OBJECT_P (XEXP (x, 1))
5339 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5340 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5342 && (!OBJECT_P (XEXP (x, 0))
5343 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5344 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5346 rtx cond, true_rtx, false_rtx;
5348 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5350 /* If everything is a comparison, what we have is highly unlikely
5351 to be simpler, so don't use it. */
5352 && ! (COMPARISON_P (x)
5353 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5355 rtx cop1 = const0_rtx;
5356 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5358 if (cond_code == NE && COMPARISON_P (cond))
5361 /* Simplify the alternative arms; this may collapse the true and
5362 false arms to store-flag values. Be careful to use copy_rtx
5363 here since true_rtx or false_rtx might share RTL with x as a
5364 result of the if_then_else_cond call above. */
5365 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5366 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5368 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5369 is unlikely to be simpler. */
5370 if (general_operand (true_rtx, VOIDmode)
5371 && general_operand (false_rtx, VOIDmode))
5373 enum rtx_code reversed;
5375 /* Restarting if we generate a store-flag expression will cause
5376 us to loop. Just drop through in this case. */
5378 /* If the result values are STORE_FLAG_VALUE and zero, we can
5379 just make the comparison operation. */
5380 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5381 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5383 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5384 && ((reversed = reversed_comparison_code_parts
5385 (cond_code, cond, cop1, NULL))
5387 x = simplify_gen_relational (reversed, mode, VOIDmode,
5390 /* Likewise, we can make the negate of a comparison operation
5391 if the result values are - STORE_FLAG_VALUE and zero. */
5392 else if (CONST_INT_P (true_rtx)
5393 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5394 && false_rtx == const0_rtx)
5395 x = simplify_gen_unary (NEG, mode,
5396 simplify_gen_relational (cond_code,
5400 else if (CONST_INT_P (false_rtx)
5401 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5402 && true_rtx == const0_rtx
5403 && ((reversed = reversed_comparison_code_parts
5404 (cond_code, cond, cop1, NULL))
5406 x = simplify_gen_unary (NEG, mode,
5407 simplify_gen_relational (reversed,
5412 return gen_rtx_IF_THEN_ELSE (mode,
5413 simplify_gen_relational (cond_code,
5418 true_rtx, false_rtx);
5420 code = GET_CODE (x);
5421 op0_mode = VOIDmode;
5426 /* Try to fold this expression in case we have constants that weren't
5429 switch (GET_RTX_CLASS (code))
5432 if (op0_mode == VOIDmode)
5433 op0_mode = GET_MODE (XEXP (x, 0));
5434 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5437 case RTX_COMM_COMPARE:
5439 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5440 if (cmp_mode == VOIDmode)
5442 cmp_mode = GET_MODE (XEXP (x, 1));
5443 if (cmp_mode == VOIDmode)
5444 cmp_mode = op0_mode;
5446 temp = simplify_relational_operation (code, mode, cmp_mode,
5447 XEXP (x, 0), XEXP (x, 1));
5450 case RTX_COMM_ARITH:
5452 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5454 case RTX_BITFIELD_OPS:
5456 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5457 XEXP (x, 1), XEXP (x, 2));
5466 code = GET_CODE (temp);
5467 op0_mode = VOIDmode;
5468 mode = GET_MODE (temp);
5471 /* First see if we can apply the inverse distributive law. */
5472 if (code == PLUS || code == MINUS
5473 || code == AND || code == IOR || code == XOR)
5475 x = apply_distributive_law (x);
5476 code = GET_CODE (x);
5477 op0_mode = VOIDmode;
5480 /* If CODE is an associative operation not otherwise handled, see if we
5481 can associate some operands. This can win if they are constants or
5482 if they are logically related (i.e. (a & b) & a). */
5483 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5484 || code == AND || code == IOR || code == XOR
5485 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5486 && ((INTEGRAL_MODE_P (mode) && code != DIV)
5487 || (flag_associative_math && FLOAT_MODE_P (mode))))
5489 if (GET_CODE (XEXP (x, 0)) == code)
5491 rtx other = XEXP (XEXP (x, 0), 0);
5492 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5493 rtx inner_op1 = XEXP (x, 1);
5496 /* Make sure we pass the constant operand if any as the second
5497 one if this is a commutative operation. */
5498 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5500 rtx tem = inner_op0;
5501 inner_op0 = inner_op1;
5504 inner = simplify_binary_operation (code == MINUS ? PLUS
5505 : code == DIV ? MULT
5507 mode, inner_op0, inner_op1);
5509 /* For commutative operations, try the other pair if that one
5511 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5513 other = XEXP (XEXP (x, 0), 1);
5514 inner = simplify_binary_operation (code, mode,
5515 XEXP (XEXP (x, 0), 0),
5520 return simplify_gen_binary (code, mode, other, inner);
5524 /* A little bit of algebraic simplification here. */
5528 /* Ensure that our address has any ASHIFTs converted to MULT in case
5529 address-recognizing predicates are called later. */
5530 temp = make_compound_operation (XEXP (x, 0), MEM);
5531 SUBST (XEXP (x, 0), temp);
5535 if (op0_mode == VOIDmode)
5536 op0_mode = GET_MODE (SUBREG_REG (x));
5538 /* See if this can be moved to simplify_subreg. */
5539 if (CONSTANT_P (SUBREG_REG (x))
5540 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5541 /* Don't call gen_lowpart if the inner mode
5542 is VOIDmode and we cannot simplify it, as SUBREG without
5543 inner mode is invalid. */
5544 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5545 || gen_lowpart_common (mode, SUBREG_REG (x))))
5546 return gen_lowpart (mode, SUBREG_REG (x));
5548 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5552 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5558 /* Don't change the mode of the MEM if that would change the meaning
5560 if (MEM_P (SUBREG_REG (x))
5561 && (MEM_VOLATILE_P (SUBREG_REG (x))
5562 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5563 return gen_rtx_CLOBBER (mode, const0_rtx);
5565 /* Note that we cannot do any narrowing for non-constants since
5566 we might have been counting on using the fact that some bits were
5567 zero. We now do this in the SET. */
5572 temp = expand_compound_operation (XEXP (x, 0));
5574 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5575 replaced by (lshiftrt X C). This will convert
5576 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5578 if (GET_CODE (temp) == ASHIFTRT
5579 && CONST_INT_P (XEXP (temp, 1))
5580 && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5581 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5582 INTVAL (XEXP (temp, 1)));
5584 /* If X has only a single bit that might be nonzero, say, bit I, convert
5585 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5586 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5587 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5588 or a SUBREG of one since we'd be making the expression more
5589 complex if it was just a register. */
5592 && ! (GET_CODE (temp) == SUBREG
5593 && REG_P (SUBREG_REG (temp)))
5594 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5596 rtx temp1 = simplify_shift_const
5597 (NULL_RTX, ASHIFTRT, mode,
5598 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5599 GET_MODE_PRECISION (mode) - 1 - i),
5600 GET_MODE_PRECISION (mode) - 1 - i);
5602 /* If all we did was surround TEMP with the two shifts, we
5603 haven't improved anything, so don't use it. Otherwise,
5604 we are better off with TEMP1. */
5605 if (GET_CODE (temp1) != ASHIFTRT
5606 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5607 || XEXP (XEXP (temp1, 0), 0) != temp)
5613 /* We can't handle truncation to a partial integer mode here
5614 because we don't know the real bitsize of the partial
5616 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5619 if (HWI_COMPUTABLE_MODE_P (mode))
5621 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5622 GET_MODE_MASK (mode), 0));
5624 /* We can truncate a constant value and return it. */
5625 if (CONST_INT_P (XEXP (x, 0)))
5626 return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5628 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5629 whose value is a comparison can be replaced with a subreg if
5630 STORE_FLAG_VALUE permits. */
5631 if (HWI_COMPUTABLE_MODE_P (mode)
5632 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5633 && (temp = get_last_value (XEXP (x, 0)))
5634 && COMPARISON_P (temp))
5635 return gen_lowpart (mode, XEXP (x, 0));
5639 /* (const (const X)) can become (const X). Do it this way rather than
5640 returning the inner CONST since CONST can be shared with a
5642 if (GET_CODE (XEXP (x, 0)) == CONST)
5643 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5648 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5649 can add in an offset. find_split_point will split this address up
5650 again if it doesn't match. */
5651 if (GET_CODE (XEXP (x, 0)) == HIGH
5652 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5658 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5659 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5660 bit-field and can be replaced by either a sign_extend or a
5661 sign_extract. The `and' may be a zero_extend and the two
5662 <c>, -<c> constants may be reversed. */
5663 if (GET_CODE (XEXP (x, 0)) == XOR
5664 && CONST_INT_P (XEXP (x, 1))
5665 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5666 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5667 && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5668 || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5669 && HWI_COMPUTABLE_MODE_P (mode)
5670 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5671 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5672 && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5673 == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5674 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5675 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5676 == (unsigned int) i + 1))))
5677 return simplify_shift_const
5678 (NULL_RTX, ASHIFTRT, mode,
5679 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5680 XEXP (XEXP (XEXP (x, 0), 0), 0),
5681 GET_MODE_PRECISION (mode) - (i + 1)),
5682 GET_MODE_PRECISION (mode) - (i + 1));
5684 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5685 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5686 the bitsize of the mode - 1. This allows simplification of
5687 "a = (b & 8) == 0;" */
5688 if (XEXP (x, 1) == constm1_rtx
5689 && !REG_P (XEXP (x, 0))
5690 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5691 && REG_P (SUBREG_REG (XEXP (x, 0))))
5692 && nonzero_bits (XEXP (x, 0), mode) == 1)
5693 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5694 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5695 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5696 GET_MODE_PRECISION (mode) - 1),
5697 GET_MODE_PRECISION (mode) - 1);
5699 /* If we are adding two things that have no bits in common, convert
5700 the addition into an IOR. This will often be further simplified,
5701 for example in cases like ((a & 1) + (a & 2)), which can
5704 if (HWI_COMPUTABLE_MODE_P (mode)
5705 && (nonzero_bits (XEXP (x, 0), mode)
5706 & nonzero_bits (XEXP (x, 1), mode)) == 0)
5708 /* Try to simplify the expression further. */
5709 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5710 temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5712 /* If we could, great. If not, do not go ahead with the IOR
5713 replacement, since PLUS appears in many special purpose
5714 address arithmetic instructions. */
5715 if (GET_CODE (temp) != CLOBBER
5716 && (GET_CODE (temp) != IOR
5717 || ((XEXP (temp, 0) != XEXP (x, 0)
5718 || XEXP (temp, 1) != XEXP (x, 1))
5719 && (XEXP (temp, 0) != XEXP (x, 1)
5720 || XEXP (temp, 1) != XEXP (x, 0)))))
5726 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5727 (and <foo> (const_int pow2-1)) */
5728 if (GET_CODE (XEXP (x, 1)) == AND
5729 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5730 && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5731 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5732 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5733 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5737 /* If we have (mult (plus A B) C), apply the distributive law and then
5738 the inverse distributive law to see if things simplify. This
5739 occurs mostly in addresses, often when unrolling loops. */
5741 if (GET_CODE (XEXP (x, 0)) == PLUS)
5743 rtx result = distribute_and_simplify_rtx (x, 0);
5748 /* Try simplify a*(b/c) as (a*b)/c. */
5749 if (FLOAT_MODE_P (mode) && flag_associative_math
5750 && GET_CODE (XEXP (x, 0)) == DIV)
5752 rtx tem = simplify_binary_operation (MULT, mode,
5753 XEXP (XEXP (x, 0), 0),
5756 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5761 /* If this is a divide by a power of two, treat it as a shift if
5762 its first operand is a shift. */
5763 if (CONST_INT_P (XEXP (x, 1))
5764 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5765 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5766 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5767 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5768 || GET_CODE (XEXP (x, 0)) == ROTATE
5769 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5770 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5774 case GT: case GTU: case GE: case GEU:
5775 case LT: case LTU: case LE: case LEU:
5776 case UNEQ: case LTGT:
5777 case UNGT: case UNGE:
5778 case UNLT: case UNLE:
5779 case UNORDERED: case ORDERED:
5780 /* If the first operand is a condition code, we can't do anything
5782 if (GET_CODE (XEXP (x, 0)) == COMPARE
5783 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5784 && ! CC0_P (XEXP (x, 0))))
5786 rtx op0 = XEXP (x, 0);
5787 rtx op1 = XEXP (x, 1);
5788 enum rtx_code new_code;
5790 if (GET_CODE (op0) == COMPARE)
5791 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5793 /* Simplify our comparison, if possible. */
5794 new_code = simplify_comparison (code, &op0, &op1);
5796 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5797 if only the low-order bit is possibly nonzero in X (such as when
5798 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5799 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5800 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5803 Remove any ZERO_EXTRACT we made when thinking this was a
5804 comparison. It may now be simpler to use, e.g., an AND. If a
5805 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5806 the call to make_compound_operation in the SET case.
5808 Don't apply these optimizations if the caller would
5809 prefer a comparison rather than a value.
5810 E.g., for the condition in an IF_THEN_ELSE most targets need
5811 an explicit comparison. */
5816 else if (STORE_FLAG_VALUE == 1
5817 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5818 && op1 == const0_rtx
5819 && mode == GET_MODE (op0)
5820 && nonzero_bits (op0, mode) == 1)
5821 return gen_lowpart (mode,
5822 expand_compound_operation (op0));
5824 else if (STORE_FLAG_VALUE == 1
5825 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5826 && op1 == const0_rtx
5827 && mode == GET_MODE (op0)
5828 && (num_sign_bit_copies (op0, mode)
5829 == GET_MODE_PRECISION (mode)))
5831 op0 = expand_compound_operation (op0);
5832 return simplify_gen_unary (NEG, mode,
5833 gen_lowpart (mode, op0),
5837 else if (STORE_FLAG_VALUE == 1
5838 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5839 && op1 == const0_rtx
5840 && mode == GET_MODE (op0)
5841 && nonzero_bits (op0, mode) == 1)
5843 op0 = expand_compound_operation (op0);
5844 return simplify_gen_binary (XOR, mode,
5845 gen_lowpart (mode, op0),
5849 else if (STORE_FLAG_VALUE == 1
5850 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5851 && op1 == const0_rtx
5852 && mode == GET_MODE (op0)
5853 && (num_sign_bit_copies (op0, mode)
5854 == GET_MODE_PRECISION (mode)))
5856 op0 = expand_compound_operation (op0);
5857 return plus_constant (gen_lowpart (mode, op0), 1);
5860 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5865 else if (STORE_FLAG_VALUE == -1
5866 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5867 && op1 == const0_rtx
5868 && (num_sign_bit_copies (op0, mode)
5869 == GET_MODE_PRECISION (mode)))
5870 return gen_lowpart (mode,
5871 expand_compound_operation (op0));
5873 else if (STORE_FLAG_VALUE == -1
5874 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5875 && op1 == const0_rtx
5876 && mode == GET_MODE (op0)
5877 && nonzero_bits (op0, mode) == 1)
5879 op0 = expand_compound_operation (op0);
5880 return simplify_gen_unary (NEG, mode,
5881 gen_lowpart (mode, op0),
5885 else if (STORE_FLAG_VALUE == -1
5886 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5887 && op1 == const0_rtx
5888 && mode == GET_MODE (op0)
5889 && (num_sign_bit_copies (op0, mode)
5890 == GET_MODE_PRECISION (mode)))
5892 op0 = expand_compound_operation (op0);
5893 return simplify_gen_unary (NOT, mode,
5894 gen_lowpart (mode, op0),
5898 /* If X is 0/1, (eq X 0) is X-1. */
5899 else if (STORE_FLAG_VALUE == -1
5900 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5901 && op1 == const0_rtx
5902 && mode == GET_MODE (op0)
5903 && nonzero_bits (op0, mode) == 1)
5905 op0 = expand_compound_operation (op0);
5906 return plus_constant (gen_lowpart (mode, op0), -1);
5909 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5910 one bit that might be nonzero, we can convert (ne x 0) to
5911 (ashift x c) where C puts the bit in the sign bit. Remove any
5912 AND with STORE_FLAG_VALUE when we are done, since we are only
5913 going to test the sign bit. */
5914 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5915 && HWI_COMPUTABLE_MODE_P (mode)
5916 && val_signbit_p (mode, STORE_FLAG_VALUE)
5917 && op1 == const0_rtx
5918 && mode == GET_MODE (op0)
5919 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5921 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5922 expand_compound_operation (op0),
5923 GET_MODE_PRECISION (mode) - 1 - i);
5924 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5930 /* If the code changed, return a whole new comparison. */
5931 if (new_code != code)
5932 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5934 /* Otherwise, keep this operation, but maybe change its operands.
5935 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5936 SUBST (XEXP (x, 0), op0);
5937 SUBST (XEXP (x, 1), op1);
5942 return simplify_if_then_else (x);
5948 /* If we are processing SET_DEST, we are done. */
5952 return expand_compound_operation (x);
5955 return simplify_set (x);
5959 return simplify_logical (x);
5966 /* If this is a shift by a constant amount, simplify it. */
5967 if (CONST_INT_P (XEXP (x, 1)))
5968 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5969 INTVAL (XEXP (x, 1)));
5971 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5973 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5974 ((unsigned HOST_WIDE_INT) 1
5975 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5987 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5990 simplify_if_then_else (rtx x)
5992 enum machine_mode mode = GET_MODE (x);
5993 rtx cond = XEXP (x, 0);
5994 rtx true_rtx = XEXP (x, 1);
5995 rtx false_rtx = XEXP (x, 2);
5996 enum rtx_code true_code = GET_CODE (cond);
5997 int comparison_p = COMPARISON_P (cond);
6000 enum rtx_code false_code;
6003 /* Simplify storing of the truth value. */
6004 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6005 return simplify_gen_relational (true_code, mode, VOIDmode,
6006 XEXP (cond, 0), XEXP (cond, 1));
6008 /* Also when the truth value has to be reversed. */
6010 && true_rtx == const0_rtx && false_rtx == const_true_rtx
6011 && (reversed = reversed_comparison (cond, mode)))
6014 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6015 in it is being compared against certain values. Get the true and false
6016 comparisons and see if that says anything about the value of each arm. */
6019 && ((false_code = reversed_comparison_code (cond, NULL))
6021 && REG_P (XEXP (cond, 0)))
6024 rtx from = XEXP (cond, 0);
6025 rtx true_val = XEXP (cond, 1);
6026 rtx false_val = true_val;
6029 /* If FALSE_CODE is EQ, swap the codes and arms. */
6031 if (false_code == EQ)
6033 swapped = 1, true_code = EQ, false_code = NE;
6034 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6037 /* If we are comparing against zero and the expression being tested has
6038 only a single bit that might be nonzero, that is its value when it is
6039 not equal to zero. Similarly if it is known to be -1 or 0. */
6041 if (true_code == EQ && true_val == const0_rtx
6042 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6045 false_val = gen_int_mode (nzb, GET_MODE (from));
6047 else if (true_code == EQ && true_val == const0_rtx
6048 && (num_sign_bit_copies (from, GET_MODE (from))
6049 == GET_MODE_PRECISION (GET_MODE (from))))
6052 false_val = constm1_rtx;
6055 /* Now simplify an arm if we know the value of the register in the
6056 branch and it is used in the arm. Be careful due to the potential
6057 of locally-shared RTL. */
6059 if (reg_mentioned_p (from, true_rtx))
6060 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6062 pc_rtx, pc_rtx, 0, 0, 0);
6063 if (reg_mentioned_p (from, false_rtx))
6064 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6066 pc_rtx, pc_rtx, 0, 0, 0);
6068 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6069 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6071 true_rtx = XEXP (x, 1);
6072 false_rtx = XEXP (x, 2);
6073 true_code = GET_CODE (cond);
6076 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6077 reversed, do so to avoid needing two sets of patterns for
6078 subtract-and-branch insns. Similarly if we have a constant in the true
6079 arm, the false arm is the same as the first operand of the comparison, or
6080 the false arm is more complicated than the true arm. */
6083 && reversed_comparison_code (cond, NULL) != UNKNOWN
6084 && (true_rtx == pc_rtx
6085 || (CONSTANT_P (true_rtx)
6086 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6087 || true_rtx == const0_rtx
6088 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6089 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6090 && !OBJECT_P (false_rtx))
6091 || reg_mentioned_p (true_rtx, false_rtx)
6092 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6094 true_code = reversed_comparison_code (cond, NULL);
6095 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6096 SUBST (XEXP (x, 1), false_rtx);
6097 SUBST (XEXP (x, 2), true_rtx);
6099 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6102 /* It is possible that the conditional has been simplified out. */
6103 true_code = GET_CODE (cond);
6104 comparison_p = COMPARISON_P (cond);
6107 /* If the two arms are identical, we don't need the comparison. */
6109 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6112 /* Convert a == b ? b : a to "a". */
6113 if (true_code == EQ && ! side_effects_p (cond)
6114 && !HONOR_NANS (mode)
6115 && rtx_equal_p (XEXP (cond, 0), false_rtx)
6116 && rtx_equal_p (XEXP (cond, 1), true_rtx))
6118 else if (true_code == NE && ! side_effects_p (cond)
6119 && !HONOR_NANS (mode)
6120 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6121 && rtx_equal_p (XEXP (cond, 1), false_rtx))
6124 /* Look for cases where we have (abs x) or (neg (abs X)). */
6126 if (GET_MODE_CLASS (mode) == MODE_INT
6128 && XEXP (cond, 1) == const0_rtx
6129 && GET_CODE (false_rtx) == NEG
6130 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6131 && rtx_equal_p (true_rtx, XEXP (cond, 0))
6132 && ! side_effects_p (true_rtx))
6137 return simplify_gen_unary (ABS, mode, true_rtx, mode);
6141 simplify_gen_unary (NEG, mode,
6142 simplify_gen_unary (ABS, mode, true_rtx, mode),
6148 /* Look for MIN or MAX. */
6150 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6152 && rtx_equal_p (XEXP (cond, 0), true_rtx)
6153 && rtx_equal_p (XEXP (cond, 1), false_rtx)
6154 && ! side_effects_p (cond))
6159 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6162 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6165 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6168 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6173 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6174 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6175 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6176 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6177 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6178 neither 1 or -1, but it isn't worth checking for. */
6180 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6182 && GET_MODE_CLASS (mode) == MODE_INT
6183 && ! side_effects_p (x))
6185 rtx t = make_compound_operation (true_rtx, SET);
6186 rtx f = make_compound_operation (false_rtx, SET);
6187 rtx cond_op0 = XEXP (cond, 0);
6188 rtx cond_op1 = XEXP (cond, 1);
6189 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6190 enum machine_mode m = mode;
6191 rtx z = 0, c1 = NULL_RTX;
6193 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6194 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6195 || GET_CODE (t) == ASHIFT
6196 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6197 && rtx_equal_p (XEXP (t, 0), f))
6198 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6200 /* If an identity-zero op is commutative, check whether there
6201 would be a match if we swapped the operands. */
6202 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6203 || GET_CODE (t) == XOR)
6204 && rtx_equal_p (XEXP (t, 1), f))
6205 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6206 else if (GET_CODE (t) == SIGN_EXTEND
6207 && (GET_CODE (XEXP (t, 0)) == PLUS
6208 || GET_CODE (XEXP (t, 0)) == MINUS
6209 || GET_CODE (XEXP (t, 0)) == IOR
6210 || GET_CODE (XEXP (t, 0)) == XOR
6211 || GET_CODE (XEXP (t, 0)) == ASHIFT
6212 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6213 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6214 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6215 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6216 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6217 && (num_sign_bit_copies (f, GET_MODE (f))
6219 (GET_MODE_PRECISION (mode)
6220 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6222 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6223 extend_op = SIGN_EXTEND;
6224 m = GET_MODE (XEXP (t, 0));
6226 else if (GET_CODE (t) == SIGN_EXTEND
6227 && (GET_CODE (XEXP (t, 0)) == PLUS
6228 || GET_CODE (XEXP (t, 0)) == IOR
6229 || GET_CODE (XEXP (t, 0)) == XOR)
6230 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6231 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6232 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6233 && (num_sign_bit_copies (f, GET_MODE (f))
6235 (GET_MODE_PRECISION (mode)
6236 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6238 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6239 extend_op = SIGN_EXTEND;
6240 m = GET_MODE (XEXP (t, 0));
6242 else if (GET_CODE (t) == ZERO_EXTEND
6243 && (GET_CODE (XEXP (t, 0)) == PLUS
6244 || GET_CODE (XEXP (t, 0)) == MINUS
6245 || GET_CODE (XEXP (t, 0)) == IOR
6246 || GET_CODE (XEXP (t, 0)) == XOR
6247 || GET_CODE (XEXP (t, 0)) == ASHIFT
6248 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6249 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6250 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6251 && HWI_COMPUTABLE_MODE_P (mode)
6252 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6253 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6254 && ((nonzero_bits (f, GET_MODE (f))
6255 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6258 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6259 extend_op = ZERO_EXTEND;
6260 m = GET_MODE (XEXP (t, 0));
6262 else if (GET_CODE (t) == ZERO_EXTEND
6263 && (GET_CODE (XEXP (t, 0)) == PLUS
6264 || GET_CODE (XEXP (t, 0)) == IOR
6265 || GET_CODE (XEXP (t, 0)) == XOR)
6266 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6267 && HWI_COMPUTABLE_MODE_P (mode)
6268 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6269 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6270 && ((nonzero_bits (f, GET_MODE (f))
6271 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6274 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6275 extend_op = ZERO_EXTEND;
6276 m = GET_MODE (XEXP (t, 0));
6281 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6282 cond_op0, cond_op1),
6283 pc_rtx, pc_rtx, 0, 0, 0);
6284 temp = simplify_gen_binary (MULT, m, temp,
6285 simplify_gen_binary (MULT, m, c1,
6287 temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6288 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6290 if (extend_op != UNKNOWN)
6291 temp = simplify_gen_unary (extend_op, mode, temp, m);
6297 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6298 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6299 negation of a single bit, we can convert this operation to a shift. We
6300 can actually do this more generally, but it doesn't seem worth it. */
6302 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6303 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6304 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6305 && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6306 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6307 == GET_MODE_PRECISION (mode))
6308 && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6310 simplify_shift_const (NULL_RTX, ASHIFT, mode,
6311 gen_lowpart (mode, XEXP (cond, 0)), i);
6313 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6314 if (true_code == NE && XEXP (cond, 1) == const0_rtx
6315 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6316 && GET_MODE (XEXP (cond, 0)) == mode
6317 && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6318 == nonzero_bits (XEXP (cond, 0), mode)
6319 && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6320 return XEXP (cond, 0);
6325 /* Simplify X, a SET expression. Return the new expression. */
6328 simplify_set (rtx x)
6330 rtx src = SET_SRC (x);
6331 rtx dest = SET_DEST (x);
6332 enum machine_mode mode
6333 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6337 /* (set (pc) (return)) gets written as (return). */
6338 if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6341 /* Now that we know for sure which bits of SRC we are using, see if we can
6342 simplify the expression for the object knowing that we only need the
6345 if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6347 src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6348 SUBST (SET_SRC (x), src);
6351 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6352 the comparison result and try to simplify it unless we already have used
6353 undobuf.other_insn. */
6354 if ((GET_MODE_CLASS (mode) == MODE_CC
6355 || GET_CODE (src) == COMPARE
6357 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6358 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6359 && COMPARISON_P (*cc_use)
6360 && rtx_equal_p (XEXP (*cc_use, 0), dest))
6362 enum rtx_code old_code = GET_CODE (*cc_use);
6363 enum rtx_code new_code;
6365 int other_changed = 0;
6366 rtx inner_compare = NULL_RTX;
6367 enum machine_mode compare_mode = GET_MODE (dest);
6369 if (GET_CODE (src) == COMPARE)
6371 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6372 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6374 inner_compare = op0;
6375 op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6379 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6381 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6384 new_code = old_code;
6385 else if (!CONSTANT_P (tmp))
6387 new_code = GET_CODE (tmp);
6388 op0 = XEXP (tmp, 0);
6389 op1 = XEXP (tmp, 1);
6393 rtx pat = PATTERN (other_insn);
6394 undobuf.other_insn = other_insn;
6395 SUBST (*cc_use, tmp);
6397 /* Attempt to simplify CC user. */
6398 if (GET_CODE (pat) == SET)
6400 rtx new_rtx = simplify_rtx (SET_SRC (pat));
6401 if (new_rtx != NULL_RTX)
6402 SUBST (SET_SRC (pat), new_rtx);
6405 /* Convert X into a no-op move. */
6406 SUBST (SET_DEST (x), pc_rtx);
6407 SUBST (SET_SRC (x), pc_rtx);
6411 /* Simplify our comparison, if possible. */
6412 new_code = simplify_comparison (new_code, &op0, &op1);
6414 #ifdef SELECT_CC_MODE
6415 /* If this machine has CC modes other than CCmode, check to see if we
6416 need to use a different CC mode here. */
6417 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6418 compare_mode = GET_MODE (op0);
6419 else if (inner_compare
6420 && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6421 && new_code == old_code
6422 && op0 == XEXP (inner_compare, 0)
6423 && op1 == XEXP (inner_compare, 1))
6424 compare_mode = GET_MODE (inner_compare);
6426 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6429 /* If the mode changed, we have to change SET_DEST, the mode in the
6430 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6431 a hard register, just build new versions with the proper mode. If it
6432 is a pseudo, we lose unless it is only time we set the pseudo, in
6433 which case we can safely change its mode. */
6434 if (compare_mode != GET_MODE (dest))
6436 if (can_change_dest_mode (dest, 0, compare_mode))
6438 unsigned int regno = REGNO (dest);
6441 if (regno < FIRST_PSEUDO_REGISTER)
6442 new_dest = gen_rtx_REG (compare_mode, regno);
6445 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6446 new_dest = regno_reg_rtx[regno];
6449 SUBST (SET_DEST (x), new_dest);
6450 SUBST (XEXP (*cc_use, 0), new_dest);
6457 #endif /* SELECT_CC_MODE */
6459 /* If the code changed, we have to build a new comparison in
6460 undobuf.other_insn. */
6461 if (new_code != old_code)
6463 int other_changed_previously = other_changed;
6464 unsigned HOST_WIDE_INT mask;
6465 rtx old_cc_use = *cc_use;
6467 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6471 /* If the only change we made was to change an EQ into an NE or
6472 vice versa, OP0 has only one bit that might be nonzero, and OP1
6473 is zero, check if changing the user of the condition code will
6474 produce a valid insn. If it won't, we can keep the original code
6475 in that insn by surrounding our operation with an XOR. */
6477 if (((old_code == NE && new_code == EQ)
6478 || (old_code == EQ && new_code == NE))
6479 && ! other_changed_previously && op1 == const0_rtx
6480 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6481 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6483 rtx pat = PATTERN (other_insn), note = 0;
6485 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
6486 && ! check_asm_operands (pat)))
6488 *cc_use = old_cc_use;
6491 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6492 op0, GEN_INT (mask));
6498 undobuf.other_insn = other_insn;
6500 /* Otherwise, if we didn't previously have a COMPARE in the
6501 correct mode, we need one. */
6502 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6504 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6507 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6509 SUBST (SET_SRC (x), op0);
6512 /* Otherwise, update the COMPARE if needed. */
6513 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6515 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6521 /* Get SET_SRC in a form where we have placed back any
6522 compound expressions. Then do the checks below. */
6523 src = make_compound_operation (src, SET);
6524 SUBST (SET_SRC (x), src);
6527 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6528 and X being a REG or (subreg (reg)), we may be able to convert this to
6529 (set (subreg:m2 x) (op)).
6531 We can always do this if M1 is narrower than M2 because that means that
6532 we only care about the low bits of the result.
6534 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6535 perform a narrower operation than requested since the high-order bits will
6536 be undefined. On machine where it is defined, this transformation is safe
6537 as long as M1 and M2 have the same number of words. */
6539 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6540 && !OBJECT_P (SUBREG_REG (src))
6541 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6543 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6544 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6545 #ifndef WORD_REGISTER_OPERATIONS
6546 && (GET_MODE_SIZE (GET_MODE (src))
6547 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6549 #ifdef CANNOT_CHANGE_MODE_CLASS
6550 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6551 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6552 GET_MODE (SUBREG_REG (src)),
6556 || (GET_CODE (dest) == SUBREG
6557 && REG_P (SUBREG_REG (dest)))))
6559 SUBST (SET_DEST (x),
6560 gen_lowpart (GET_MODE (SUBREG_REG (src)),
6562 SUBST (SET_SRC (x), SUBREG_REG (src));
6564 src = SET_SRC (x), dest = SET_DEST (x);
6568 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6571 && GET_CODE (src) == SUBREG
6572 && subreg_lowpart_p (src)
6573 && (GET_MODE_PRECISION (GET_MODE (src))
6574 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6576 rtx inner = SUBREG_REG (src);
6577 enum machine_mode inner_mode = GET_MODE (inner);
6579 /* Here we make sure that we don't have a sign bit on. */
6580 if (val_signbit_known_clear_p (GET_MODE (src),
6581 nonzero_bits (inner, inner_mode)))
6583 SUBST (SET_SRC (x), inner);
6589 #ifdef LOAD_EXTEND_OP
6590 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6591 would require a paradoxical subreg. Replace the subreg with a
6592 zero_extend to avoid the reload that would otherwise be required. */
6594 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6595 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6596 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6597 && SUBREG_BYTE (src) == 0
6598 && paradoxical_subreg_p (src)
6599 && MEM_P (SUBREG_REG (src)))
6602 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6603 GET_MODE (src), SUBREG_REG (src)));
6609 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6610 are comparing an item known to be 0 or -1 against 0, use a logical
6611 operation instead. Check for one of the arms being an IOR of the other
6612 arm with some value. We compute three terms to be IOR'ed together. In
6613 practice, at most two will be nonzero. Then we do the IOR's. */
6615 if (GET_CODE (dest) != PC
6616 && GET_CODE (src) == IF_THEN_ELSE
6617 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6618 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6619 && XEXP (XEXP (src, 0), 1) == const0_rtx
6620 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6621 #ifdef HAVE_conditional_move
6622 && ! can_conditionally_move_p (GET_MODE (src))
6624 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6625 GET_MODE (XEXP (XEXP (src, 0), 0)))
6626 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6627 && ! side_effects_p (src))
6629 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6630 ? XEXP (src, 1) : XEXP (src, 2));
6631 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6632 ? XEXP (src, 2) : XEXP (src, 1));
6633 rtx term1 = const0_rtx, term2, term3;
6635 if (GET_CODE (true_rtx) == IOR
6636 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6637 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6638 else if (GET_CODE (true_rtx) == IOR
6639 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6640 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6641 else if (GET_CODE (false_rtx) == IOR
6642 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6643 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6644 else if (GET_CODE (false_rtx) == IOR
6645 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6646 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6648 term2 = simplify_gen_binary (AND, GET_MODE (src),
6649 XEXP (XEXP (src, 0), 0), true_rtx);
6650 term3 = simplify_gen_binary (AND, GET_MODE (src),
6651 simplify_gen_unary (NOT, GET_MODE (src),
6652 XEXP (XEXP (src, 0), 0),
6657 simplify_gen_binary (IOR, GET_MODE (src),
6658 simplify_gen_binary (IOR, GET_MODE (src),
6665 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6666 whole thing fail. */
6667 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6669 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6672 /* Convert this into a field assignment operation, if possible. */
6673 return make_field_assignment (x);
6676 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6680 simplify_logical (rtx x)
6682 enum machine_mode mode = GET_MODE (x);
6683 rtx op0 = XEXP (x, 0);
6684 rtx op1 = XEXP (x, 1);
6686 switch (GET_CODE (x))
6689 /* We can call simplify_and_const_int only if we don't lose
6690 any (sign) bits when converting INTVAL (op1) to
6691 "unsigned HOST_WIDE_INT". */
6692 if (CONST_INT_P (op1)
6693 && (HWI_COMPUTABLE_MODE_P (mode)
6694 || INTVAL (op1) > 0))
6696 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6697 if (GET_CODE (x) != AND)
6704 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6705 apply the distributive law and then the inverse distributive
6706 law to see if things simplify. */
6707 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6709 rtx result = distribute_and_simplify_rtx (x, 0);
6713 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6715 rtx result = distribute_and_simplify_rtx (x, 1);
6722 /* If we have (ior (and A B) C), apply the distributive law and then
6723 the inverse distributive law to see if things simplify. */
6725 if (GET_CODE (op0) == AND)
6727 rtx result = distribute_and_simplify_rtx (x, 0);
6732 if (GET_CODE (op1) == AND)
6734 rtx result = distribute_and_simplify_rtx (x, 1);
6747 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6748 operations" because they can be replaced with two more basic operations.
6749 ZERO_EXTEND is also considered "compound" because it can be replaced with
6750 an AND operation, which is simpler, though only one operation.
6752 The function expand_compound_operation is called with an rtx expression
6753 and will convert it to the appropriate shifts and AND operations,
6754 simplifying at each stage.
6756 The function make_compound_operation is called to convert an expression
6757 consisting of shifts and ANDs into the equivalent compound expression.
6758 It is the inverse of this function, loosely speaking. */
6761 expand_compound_operation (rtx x)
6763 unsigned HOST_WIDE_INT pos = 0, len;
6765 unsigned int modewidth;
6768 switch (GET_CODE (x))
6773 /* We can't necessarily use a const_int for a multiword mode;
6774 it depends on implicitly extending the value.
6775 Since we don't know the right way to extend it,
6776 we can't tell whether the implicit way is right.
6778 Even for a mode that is no wider than a const_int,
6779 we can't win, because we need to sign extend one of its bits through
6780 the rest of it, and we don't know which bit. */
6781 if (CONST_INT_P (XEXP (x, 0)))
6784 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6785 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6786 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6787 reloaded. If not for that, MEM's would very rarely be safe.
6789 Reject MODEs bigger than a word, because we might not be able
6790 to reference a two-register group starting with an arbitrary register
6791 (and currently gen_lowpart might crash for a SUBREG). */
6793 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6796 /* Reject MODEs that aren't scalar integers because turning vector
6797 or complex modes into shifts causes problems. */
6799 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6802 len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6803 /* If the inner object has VOIDmode (the only way this can happen
6804 is if it is an ASM_OPERANDS), we can't do anything since we don't
6805 know how much masking to do. */
6814 /* ... fall through ... */
6817 /* If the operand is a CLOBBER, just return it. */
6818 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6821 if (!CONST_INT_P (XEXP (x, 1))
6822 || !CONST_INT_P (XEXP (x, 2))
6823 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6826 /* Reject MODEs that aren't scalar integers because turning vector
6827 or complex modes into shifts causes problems. */
6829 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6832 len = INTVAL (XEXP (x, 1));
6833 pos = INTVAL (XEXP (x, 2));
6835 /* This should stay within the object being extracted, fail otherwise. */
6836 if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6839 if (BITS_BIG_ENDIAN)
6840 pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6847 /* Convert sign extension to zero extension, if we know that the high
6848 bit is not set, as this is easier to optimize. It will be converted
6849 back to cheaper alternative in make_extraction. */
6850 if (GET_CODE (x) == SIGN_EXTEND
6851 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6852 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6853 & ~(((unsigned HOST_WIDE_INT)
6854 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6858 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6859 rtx temp2 = expand_compound_operation (temp);
6861 /* Make sure this is a profitable operation. */
6862 if (set_src_cost (x, optimize_this_for_speed_p)
6863 > set_src_cost (temp2, optimize_this_for_speed_p))
6865 else if (set_src_cost (x, optimize_this_for_speed_p)
6866 > set_src_cost (temp, optimize_this_for_speed_p))
6872 /* We can optimize some special cases of ZERO_EXTEND. */
6873 if (GET_CODE (x) == ZERO_EXTEND)
6875 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6876 know that the last value didn't have any inappropriate bits
6878 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6879 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6880 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6881 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6882 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6883 return XEXP (XEXP (x, 0), 0);
6885 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6886 if (GET_CODE (XEXP (x, 0)) == SUBREG
6887 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6888 && subreg_lowpart_p (XEXP (x, 0))
6889 && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6890 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6891 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6892 return SUBREG_REG (XEXP (x, 0));
6894 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6895 is a comparison and STORE_FLAG_VALUE permits. This is like
6896 the first case, but it works even when GET_MODE (x) is larger
6897 than HOST_WIDE_INT. */
6898 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6899 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6900 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6901 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6902 <= HOST_BITS_PER_WIDE_INT)
6903 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6904 return XEXP (XEXP (x, 0), 0);
6906 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6907 if (GET_CODE (XEXP (x, 0)) == SUBREG
6908 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6909 && subreg_lowpart_p (XEXP (x, 0))
6910 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6911 && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6912 <= HOST_BITS_PER_WIDE_INT)
6913 && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6914 return SUBREG_REG (XEXP (x, 0));
6918 /* If we reach here, we want to return a pair of shifts. The inner
6919 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6920 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6921 logical depending on the value of UNSIGNEDP.
6923 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6924 converted into an AND of a shift.
6926 We must check for the case where the left shift would have a negative
6927 count. This can happen in a case like (x >> 31) & 255 on machines
6928 that can't shift by a constant. On those machines, we would first
6929 combine the shift with the AND to produce a variable-position
6930 extraction. Then the constant of 31 would be substituted in
6931 to produce such a position. */
6933 modewidth = GET_MODE_PRECISION (GET_MODE (x));
6934 if (modewidth >= pos + len)
6936 enum machine_mode mode = GET_MODE (x);
6937 tem = gen_lowpart (mode, XEXP (x, 0));
6938 if (!tem || GET_CODE (tem) == CLOBBER)
6940 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6941 tem, modewidth - pos - len);
6942 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6943 mode, tem, modewidth - len);
6945 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6946 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6947 simplify_shift_const (NULL_RTX, LSHIFTRT,
6950 ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6952 /* Any other cases we can't handle. */
6955 /* If we couldn't do this for some reason, return the original
6957 if (GET_CODE (tem) == CLOBBER)
6963 /* X is a SET which contains an assignment of one object into
6964 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6965 or certain SUBREGS). If possible, convert it into a series of
6968 We half-heartedly support variable positions, but do not at all
6969 support variable lengths. */
6972 expand_field_assignment (const_rtx x)
6975 rtx pos; /* Always counts from low bit. */
6977 rtx mask, cleared, masked;
6978 enum machine_mode compute_mode;
6980 /* Loop until we find something we can't simplify. */
6983 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6984 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6986 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6987 len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6988 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6990 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6991 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6993 inner = XEXP (SET_DEST (x), 0);
6994 len = INTVAL (XEXP (SET_DEST (x), 1));
6995 pos = XEXP (SET_DEST (x), 2);
6997 /* A constant position should stay within the width of INNER. */
6998 if (CONST_INT_P (pos)
6999 && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
7002 if (BITS_BIG_ENDIAN)
7004 if (CONST_INT_P (pos))
7005 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
7007 else if (GET_CODE (pos) == MINUS
7008 && CONST_INT_P (XEXP (pos, 1))
7009 && (INTVAL (XEXP (pos, 1))
7010 == GET_MODE_PRECISION (GET_MODE (inner)) - len))
7011 /* If position is ADJUST - X, new position is X. */
7012 pos = XEXP (pos, 0);
7014 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7015 GEN_INT (GET_MODE_PRECISION (
7022 /* A SUBREG between two modes that occupy the same numbers of words
7023 can be done by moving the SUBREG to the source. */
7024 else if (GET_CODE (SET_DEST (x)) == SUBREG
7025 /* We need SUBREGs to compute nonzero_bits properly. */
7026 && nonzero_sign_valid
7027 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
7028 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7029 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7030 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7032 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
7034 (GET_MODE (SUBREG_REG (SET_DEST (x))),
7041 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7042 inner = SUBREG_REG (inner);
7044 compute_mode = GET_MODE (inner);
7046 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7047 if (! SCALAR_INT_MODE_P (compute_mode))
7049 enum machine_mode imode;
7051 /* Don't do anything for vector or complex integral types. */
7052 if (! FLOAT_MODE_P (compute_mode))
7055 /* Try to find an integral mode to pun with. */
7056 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7057 if (imode == BLKmode)
7060 compute_mode = imode;
7061 inner = gen_lowpart (imode, inner);
7064 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7065 if (len >= HOST_BITS_PER_WIDE_INT)
7068 /* Now compute the equivalent expression. Make a copy of INNER
7069 for the SET_DEST in case it is a MEM into which we will substitute;
7070 we don't want shared RTL in that case. */
7071 mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7072 cleared = simplify_gen_binary (AND, compute_mode,
7073 simplify_gen_unary (NOT, compute_mode,
7074 simplify_gen_binary (ASHIFT,
7079 masked = simplify_gen_binary (ASHIFT, compute_mode,
7080 simplify_gen_binary (
7082 gen_lowpart (compute_mode, SET_SRC (x)),
7086 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7087 simplify_gen_binary (IOR, compute_mode,
7094 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7095 it is an RTX that represents a variable starting position; otherwise,
7096 POS is the (constant) starting bit position (counted from the LSB).
7098 UNSIGNEDP is nonzero for an unsigned reference and zero for a
7101 IN_DEST is nonzero if this is a reference in the destination of a
7102 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7103 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7106 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7107 ZERO_EXTRACT should be built even for bits starting at bit 0.
7109 MODE is the desired mode of the result (if IN_DEST == 0).
7111 The result is an RTX for the extraction or NULL_RTX if the target
7115 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7116 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7117 int in_dest, int in_compare)
7119 /* This mode describes the size of the storage area
7120 to fetch the overall value from. Within that, we
7121 ignore the POS lowest bits, etc. */
7122 enum machine_mode is_mode = GET_MODE (inner);
7123 enum machine_mode inner_mode;
7124 enum machine_mode wanted_inner_mode;
7125 enum machine_mode wanted_inner_reg_mode = word_mode;
7126 enum machine_mode pos_mode = word_mode;
7127 enum machine_mode extraction_mode = word_mode;
7128 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7130 rtx orig_pos_rtx = pos_rtx;
7131 HOST_WIDE_INT orig_pos;
7133 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7135 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7136 consider just the QI as the memory to extract from.
7137 The subreg adds or removes high bits; its mode is
7138 irrelevant to the meaning of this extraction,
7139 since POS and LEN count from the lsb. */
7140 if (MEM_P (SUBREG_REG (inner)))
7141 is_mode = GET_MODE (SUBREG_REG (inner));
7142 inner = SUBREG_REG (inner);
7144 else if (GET_CODE (inner) == ASHIFT
7145 && CONST_INT_P (XEXP (inner, 1))
7146 && pos_rtx == 0 && pos == 0
7147 && len > UINTVAL (XEXP (inner, 1)))
7149 /* We're extracting the least significant bits of an rtx
7150 (ashift X (const_int C)), where LEN > C. Extract the
7151 least significant (LEN - C) bits of X, giving an rtx
7152 whose mode is MODE, then shift it left C times. */
7153 new_rtx = make_extraction (mode, XEXP (inner, 0),
7154 0, 0, len - INTVAL (XEXP (inner, 1)),
7155 unsignedp, in_dest, in_compare);
7157 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7160 inner_mode = GET_MODE (inner);
7162 if (pos_rtx && CONST_INT_P (pos_rtx))
7163 pos = INTVAL (pos_rtx), pos_rtx = 0;
7165 /* See if this can be done without an extraction. We never can if the
7166 width of the field is not the same as that of some integer mode. For
7167 registers, we can only avoid the extraction if the position is at the
7168 low-order bit and this is either not in the destination or we have the
7169 appropriate STRICT_LOW_PART operation available.
7171 For MEM, we can avoid an extract if the field starts on an appropriate
7172 boundary and we can change the mode of the memory reference. */
7174 if (tmode != BLKmode
7175 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7177 && (inner_mode == tmode
7179 || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7180 || reg_truncated_to_mode (tmode, inner))
7183 && have_insn_for (STRICT_LOW_PART, tmode))))
7184 || (MEM_P (inner) && pos_rtx == 0
7186 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7187 : BITS_PER_UNIT)) == 0
7188 /* We can't do this if we are widening INNER_MODE (it
7189 may not be aligned, for one thing). */
7190 && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7191 && (inner_mode == tmode
7192 || (! mode_dependent_address_p (XEXP (inner, 0))
7193 && ! MEM_VOLATILE_P (inner))))))
7195 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7196 field. If the original and current mode are the same, we need not
7197 adjust the offset. Otherwise, we do if bytes big endian.
7199 If INNER is not a MEM, get a piece consisting of just the field
7200 of interest (in this case POS % BITS_PER_WORD must be 0). */
7204 HOST_WIDE_INT offset;
7206 /* POS counts from lsb, but make OFFSET count in memory order. */
7207 if (BYTES_BIG_ENDIAN)
7208 offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7210 offset = pos / BITS_PER_UNIT;
7212 new_rtx = adjust_address_nv (inner, tmode, offset);
7214 else if (REG_P (inner))
7216 if (tmode != inner_mode)
7218 /* We can't call gen_lowpart in a DEST since we
7219 always want a SUBREG (see below) and it would sometimes
7220 return a new hard register. */
7223 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7225 if (WORDS_BIG_ENDIAN
7226 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7227 final_word = ((GET_MODE_SIZE (inner_mode)
7228 - GET_MODE_SIZE (tmode))
7229 / UNITS_PER_WORD) - final_word;
7231 final_word *= UNITS_PER_WORD;
7232 if (BYTES_BIG_ENDIAN &&
7233 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7234 final_word += (GET_MODE_SIZE (inner_mode)
7235 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7237 /* Avoid creating invalid subregs, for example when
7238 simplifying (x>>32)&255. */
7239 if (!validate_subreg (tmode, inner_mode, inner, final_word))
7242 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7245 new_rtx = gen_lowpart (tmode, inner);
7251 new_rtx = force_to_mode (inner, tmode,
7252 len >= HOST_BITS_PER_WIDE_INT
7253 ? ~(unsigned HOST_WIDE_INT) 0
7254 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7257 /* If this extraction is going into the destination of a SET,
7258 make a STRICT_LOW_PART unless we made a MEM. */
7261 return (MEM_P (new_rtx) ? new_rtx
7262 : (GET_CODE (new_rtx) != SUBREG
7263 ? gen_rtx_CLOBBER (tmode, const0_rtx)
7264 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7269 if (CONST_INT_P (new_rtx)
7270 || GET_CODE (new_rtx) == CONST_DOUBLE)
7271 return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7272 mode, new_rtx, tmode);
7274 /* If we know that no extraneous bits are set, and that the high
7275 bit is not set, convert the extraction to the cheaper of
7276 sign and zero extension, that are equivalent in these cases. */
7277 if (flag_expensive_optimizations
7278 && (HWI_COMPUTABLE_MODE_P (tmode)
7279 && ((nonzero_bits (new_rtx, tmode)
7280 & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7283 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7284 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7286 /* Prefer ZERO_EXTENSION, since it gives more information to
7288 if (set_src_cost (temp, optimize_this_for_speed_p)
7289 <= set_src_cost (temp1, optimize_this_for_speed_p))
7294 /* Otherwise, sign- or zero-extend unless we already are in the
7297 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7301 /* Unless this is a COMPARE or we have a funny memory reference,
7302 don't do anything with zero-extending field extracts starting at
7303 the low-order bit since they are simple AND operations. */
7304 if (pos_rtx == 0 && pos == 0 && ! in_dest
7305 && ! in_compare && unsignedp)
7308 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7309 if the position is not a constant and the length is not 1. In all
7310 other cases, we would only be going outside our object in cases when
7311 an original shift would have been undefined. */
7313 && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7314 || (pos_rtx != 0 && len != 1)))
7317 /* Get the mode to use should INNER not be a MEM, the mode for the position,
7318 and the mode for the result. */
7319 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7321 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7322 pos_mode = mode_for_extraction (EP_insv, 2);
7323 extraction_mode = mode_for_extraction (EP_insv, 3);
7326 if (! in_dest && unsignedp
7327 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7329 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7330 pos_mode = mode_for_extraction (EP_extzv, 3);
7331 extraction_mode = mode_for_extraction (EP_extzv, 0);
7334 if (! in_dest && ! unsignedp
7335 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7337 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7338 pos_mode = mode_for_extraction (EP_extv, 3);
7339 extraction_mode = mode_for_extraction (EP_extv, 0);
7342 /* Never narrow an object, since that might not be safe. */
7344 if (mode != VOIDmode
7345 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7346 extraction_mode = mode;
7348 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7349 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7350 pos_mode = GET_MODE (pos_rtx);
7352 /* If this is not from memory, the desired mode is the preferred mode
7353 for an extraction pattern's first input operand, or word_mode if there
7356 wanted_inner_mode = wanted_inner_reg_mode;
7359 /* Be careful not to go beyond the extracted object and maintain the
7360 natural alignment of the memory. */
7361 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7362 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7363 > GET_MODE_BITSIZE (wanted_inner_mode))
7365 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7366 gcc_assert (wanted_inner_mode != VOIDmode);
7369 /* If we have to change the mode of memory and cannot, the desired mode
7370 is EXTRACTION_MODE. */
7371 if (inner_mode != wanted_inner_mode
7372 && (mode_dependent_address_p (XEXP (inner, 0))
7373 || MEM_VOLATILE_P (inner)
7375 wanted_inner_mode = extraction_mode;
7380 if (BITS_BIG_ENDIAN)
7382 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7383 BITS_BIG_ENDIAN style. If position is constant, compute new
7384 position. Otherwise, build subtraction.
7385 Note that POS is relative to the mode of the original argument.
7386 If it's a MEM we need to recompute POS relative to that.
7387 However, if we're extracting from (or inserting into) a register,
7388 we want to recompute POS relative to wanted_inner_mode. */
7389 int width = (MEM_P (inner)
7390 ? GET_MODE_BITSIZE (is_mode)
7391 : GET_MODE_BITSIZE (wanted_inner_mode));
7394 pos = width - len - pos;
7397 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7398 /* POS may be less than 0 now, but we check for that below.
7399 Note that it can only be less than 0 if !MEM_P (inner). */
7402 /* If INNER has a wider mode, and this is a constant extraction, try to
7403 make it smaller and adjust the byte to point to the byte containing
7405 if (wanted_inner_mode != VOIDmode
7406 && inner_mode != wanted_inner_mode
7408 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7410 && ! mode_dependent_address_p (XEXP (inner, 0))
7411 && ! MEM_VOLATILE_P (inner))
7415 /* The computations below will be correct if the machine is big
7416 endian in both bits and bytes or little endian in bits and bytes.
7417 If it is mixed, we must adjust. */
7419 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7420 adjust OFFSET to compensate. */
7421 if (BYTES_BIG_ENDIAN
7422 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7423 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7425 /* We can now move to the desired byte. */
7426 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7427 * GET_MODE_SIZE (wanted_inner_mode);
7428 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7430 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7431 && is_mode != wanted_inner_mode)
7432 offset = (GET_MODE_SIZE (is_mode)
7433 - GET_MODE_SIZE (wanted_inner_mode) - offset);
7435 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7438 /* If INNER is not memory, get it into the proper mode. If we are changing
7439 its mode, POS must be a constant and smaller than the size of the new
7441 else if (!MEM_P (inner))
7443 /* On the LHS, don't create paradoxical subregs implicitely truncating
7444 the register unless TRULY_NOOP_TRUNCATION. */
7446 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7450 if (GET_MODE (inner) != wanted_inner_mode
7452 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7458 inner = force_to_mode (inner, wanted_inner_mode,
7460 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7461 ? ~(unsigned HOST_WIDE_INT) 0
7462 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7467 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7468 have to zero extend. Otherwise, we can just use a SUBREG. */
7470 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7472 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7474 /* If we know that no extraneous bits are set, and that the high
7475 bit is not set, convert extraction to cheaper one - either
7476 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7478 if (flag_expensive_optimizations
7479 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7480 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7481 & ~(((unsigned HOST_WIDE_INT)
7482 GET_MODE_MASK (GET_MODE (pos_rtx)))
7486 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7488 /* Prefer ZERO_EXTENSION, since it gives more information to
7490 if (set_src_cost (temp1, optimize_this_for_speed_p)
7491 < set_src_cost (temp, optimize_this_for_speed_p))
7496 else if (pos_rtx != 0
7497 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7498 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7500 /* Make POS_RTX unless we already have it and it is correct. If we don't
7501 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7503 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7504 pos_rtx = orig_pos_rtx;
7506 else if (pos_rtx == 0)
7507 pos_rtx = GEN_INT (pos);
7509 /* Make the required operation. See if we can use existing rtx. */
7510 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7511 extraction_mode, inner, GEN_INT (len), pos_rtx);
7513 new_rtx = gen_lowpart (mode, new_rtx);
7518 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7519 with any other operations in X. Return X without that shift if so. */
7522 extract_left_shift (rtx x, int count)
7524 enum rtx_code code = GET_CODE (x);
7525 enum machine_mode mode = GET_MODE (x);
7531 /* This is the shift itself. If it is wide enough, we will return
7532 either the value being shifted if the shift count is equal to
7533 COUNT or a shift for the difference. */
7534 if (CONST_INT_P (XEXP (x, 1))
7535 && INTVAL (XEXP (x, 1)) >= count)
7536 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7537 INTVAL (XEXP (x, 1)) - count);
7541 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7542 return simplify_gen_unary (code, mode, tem, mode);
7546 case PLUS: case IOR: case XOR: case AND:
7547 /* If we can safely shift this constant and we find the inner shift,
7548 make a new operation. */
7549 if (CONST_INT_P (XEXP (x, 1))
7550 && (UINTVAL (XEXP (x, 1))
7551 & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7552 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7553 return simplify_gen_binary (code, mode, tem,
7554 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7565 /* Look at the expression rooted at X. Look for expressions
7566 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7567 Form these expressions.
7569 Return the new rtx, usually just X.
7571 Also, for machines like the VAX that don't have logical shift insns,
7572 try to convert logical to arithmetic shift operations in cases where
7573 they are equivalent. This undoes the canonicalizations to logical
7574 shifts done elsewhere.
7576 We try, as much as possible, to re-use rtl expressions to save memory.
7578 IN_CODE says what kind of expression we are processing. Normally, it is
7579 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7580 being kludges), it is MEM. When processing the arguments of a comparison
7581 or a COMPARE against zero, it is COMPARE. */
7584 make_compound_operation (rtx x, enum rtx_code in_code)
7586 enum rtx_code code = GET_CODE (x);
7587 enum machine_mode mode = GET_MODE (x);
7588 int mode_width = GET_MODE_PRECISION (mode);
7590 enum rtx_code next_code;
7596 /* Select the code to be used in recursive calls. Once we are inside an
7597 address, we stay there. If we have a comparison, set to COMPARE,
7598 but once inside, go back to our default of SET. */
7600 next_code = (code == MEM ? MEM
7601 : ((code == PLUS || code == MINUS)
7602 && SCALAR_INT_MODE_P (mode)) ? MEM
7603 : ((code == COMPARE || COMPARISON_P (x))
7604 && XEXP (x, 1) == const0_rtx) ? COMPARE
7605 : in_code == COMPARE ? SET : in_code);
7607 /* Process depending on the code of this operation. If NEW is set
7608 nonzero, it will be returned. */
7613 /* Convert shifts by constants into multiplications if inside
7615 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7616 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7617 && INTVAL (XEXP (x, 1)) >= 0
7618 && SCALAR_INT_MODE_P (mode))
7620 HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7621 HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7623 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7624 if (GET_CODE (new_rtx) == NEG)
7626 new_rtx = XEXP (new_rtx, 0);
7629 multval = trunc_int_for_mode (multval, mode);
7630 new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7637 lhs = make_compound_operation (lhs, next_code);
7638 rhs = make_compound_operation (rhs, next_code);
7639 if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7640 && SCALAR_INT_MODE_P (mode))
7642 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7644 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7646 else if (GET_CODE (lhs) == MULT
7647 && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7649 tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7650 simplify_gen_unary (NEG, mode,
7653 new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7657 SUBST (XEXP (x, 0), lhs);
7658 SUBST (XEXP (x, 1), rhs);
7661 x = gen_lowpart (mode, new_rtx);
7667 lhs = make_compound_operation (lhs, next_code);
7668 rhs = make_compound_operation (rhs, next_code);
7669 if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7670 && SCALAR_INT_MODE_P (mode))
7672 tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7674 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7676 else if (GET_CODE (rhs) == MULT
7677 && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7679 tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7680 simplify_gen_unary (NEG, mode,
7683 new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7687 SUBST (XEXP (x, 0), lhs);
7688 SUBST (XEXP (x, 1), rhs);
7691 return gen_lowpart (mode, new_rtx);
7694 /* If the second operand is not a constant, we can't do anything
7696 if (!CONST_INT_P (XEXP (x, 1)))
7699 /* If the constant is a power of two minus one and the first operand
7700 is a logical right shift, make an extraction. */
7701 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7702 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7704 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7705 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7706 0, in_code == COMPARE);
7709 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7710 else if (GET_CODE (XEXP (x, 0)) == SUBREG
7711 && subreg_lowpart_p (XEXP (x, 0))
7712 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7713 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7715 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7717 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7718 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7719 0, in_code == COMPARE);
7721 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7722 else if ((GET_CODE (XEXP (x, 0)) == XOR
7723 || GET_CODE (XEXP (x, 0)) == IOR)
7724 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7725 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7726 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7728 /* Apply the distributive law, and then try to make extractions. */
7729 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7730 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7732 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7734 new_rtx = make_compound_operation (new_rtx, in_code);
7737 /* If we are have (and (rotate X C) M) and C is larger than the number
7738 of bits in M, this is an extraction. */
7740 else if (GET_CODE (XEXP (x, 0)) == ROTATE
7741 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7742 && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7743 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7745 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7746 new_rtx = make_extraction (mode, new_rtx,
7747 (GET_MODE_PRECISION (mode)
7748 - INTVAL (XEXP (XEXP (x, 0), 1))),
7749 NULL_RTX, i, 1, 0, in_code == COMPARE);
7752 /* On machines without logical shifts, if the operand of the AND is
7753 a logical shift and our mask turns off all the propagated sign
7754 bits, we can replace the logical shift with an arithmetic shift. */
7755 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7756 && !have_insn_for (LSHIFTRT, mode)
7757 && have_insn_for (ASHIFTRT, mode)
7758 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7759 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7760 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7761 && mode_width <= HOST_BITS_PER_WIDE_INT)
7763 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7765 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7766 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7768 gen_rtx_ASHIFTRT (mode,
7769 make_compound_operation
7770 (XEXP (XEXP (x, 0), 0), next_code),
7771 XEXP (XEXP (x, 0), 1)));
7774 /* If the constant is one less than a power of two, this might be
7775 representable by an extraction even if no shift is present.
7776 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7777 we are in a COMPARE. */
7778 else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7779 new_rtx = make_extraction (mode,
7780 make_compound_operation (XEXP (x, 0),
7782 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7784 /* If we are in a comparison and this is an AND with a power of two,
7785 convert this into the appropriate bit extract. */
7786 else if (in_code == COMPARE
7787 && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7788 new_rtx = make_extraction (mode,
7789 make_compound_operation (XEXP (x, 0),
7791 i, NULL_RTX, 1, 1, 0, 1);
7796 /* If the sign bit is known to be zero, replace this with an
7797 arithmetic shift. */
7798 if (have_insn_for (ASHIFTRT, mode)
7799 && ! have_insn_for (LSHIFTRT, mode)
7800 && mode_width <= HOST_BITS_PER_WIDE_INT
7801 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7803 new_rtx = gen_rtx_ASHIFTRT (mode,
7804 make_compound_operation (XEXP (x, 0),
7810 /* ... fall through ... */
7816 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7817 this is a SIGN_EXTRACT. */
7818 if (CONST_INT_P (rhs)
7819 && GET_CODE (lhs) == ASHIFT
7820 && CONST_INT_P (XEXP (lhs, 1))
7821 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7822 && INTVAL (XEXP (lhs, 1)) >= 0
7823 && INTVAL (rhs) < mode_width)
7825 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7826 new_rtx = make_extraction (mode, new_rtx,
7827 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7828 NULL_RTX, mode_width - INTVAL (rhs),
7829 code == LSHIFTRT, 0, in_code == COMPARE);
7833 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7834 If so, try to merge the shifts into a SIGN_EXTEND. We could
7835 also do this for some cases of SIGN_EXTRACT, but it doesn't
7836 seem worth the effort; the case checked for occurs on Alpha. */
7839 && ! (GET_CODE (lhs) == SUBREG
7840 && (OBJECT_P (SUBREG_REG (lhs))))
7841 && CONST_INT_P (rhs)
7842 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7843 && INTVAL (rhs) < mode_width
7844 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7845 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7846 0, NULL_RTX, mode_width - INTVAL (rhs),
7847 code == LSHIFTRT, 0, in_code == COMPARE);
7852 /* Call ourselves recursively on the inner expression. If we are
7853 narrowing the object and it has a different RTL code from
7854 what it originally did, do this SUBREG as a force_to_mode. */
7856 rtx inner = SUBREG_REG (x), simplified;
7858 tem = make_compound_operation (inner, in_code);
7861 = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7865 if (GET_CODE (tem) != GET_CODE (inner)
7866 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7867 && subreg_lowpart_p (x))
7870 = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7872 /* If we have something other than a SUBREG, we might have
7873 done an expansion, so rerun ourselves. */
7874 if (GET_CODE (newer) != SUBREG)
7875 newer = make_compound_operation (newer, in_code);
7877 /* force_to_mode can expand compounds. If it just re-expanded the
7878 compound, use gen_lowpart to convert to the desired mode. */
7879 if (rtx_equal_p (newer, x)
7880 /* Likewise if it re-expanded the compound only partially.
7881 This happens for SUBREG of ZERO_EXTRACT if they extract
7882 the same number of bits. */
7883 || (GET_CODE (newer) == SUBREG
7884 && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7885 || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7886 && GET_CODE (inner) == AND
7887 && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7888 return gen_lowpart (GET_MODE (x), tem);
7904 x = gen_lowpart (mode, new_rtx);
7905 code = GET_CODE (x);
7908 /* Now recursively process each operand of this operation. We need to
7909 handle ZERO_EXTEND specially so that we don't lose track of the
7911 if (GET_CODE (x) == ZERO_EXTEND)
7913 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7914 tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7915 new_rtx, GET_MODE (XEXP (x, 0)));
7918 SUBST (XEXP (x, 0), new_rtx);
7922 fmt = GET_RTX_FORMAT (code);
7923 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7926 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7927 SUBST (XEXP (x, i), new_rtx);
7929 else if (fmt[i] == 'E')
7930 for (j = 0; j < XVECLEN (x, i); j++)
7932 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7933 SUBST (XVECEXP (x, i, j), new_rtx);
7937 /* If this is a commutative operation, the changes to the operands
7938 may have made it noncanonical. */
7939 if (COMMUTATIVE_ARITH_P (x)
7940 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7943 SUBST (XEXP (x, 0), XEXP (x, 1));
7944 SUBST (XEXP (x, 1), tem);
7950 /* Given M see if it is a value that would select a field of bits
7951 within an item, but not the entire word. Return -1 if not.
7952 Otherwise, return the starting position of the field, where 0 is the
7955 *PLEN is set to the length of the field. */
7958 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7960 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7961 int pos = m ? ctz_hwi (m) : -1;
7965 /* Now shift off the low-order zero bits and see if we have a
7966 power of two minus 1. */
7967 len = exact_log2 ((m >> pos) + 1);
7976 /* If X refers to a register that equals REG in value, replace these
7977 references with REG. */
7979 canon_reg_for_combine (rtx x, rtx reg)
7986 enum rtx_code code = GET_CODE (x);
7987 switch (GET_RTX_CLASS (code))
7990 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7991 if (op0 != XEXP (x, 0))
7992 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7997 case RTX_COMM_ARITH:
7998 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7999 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8000 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8001 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8005 case RTX_COMM_COMPARE:
8006 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8007 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8008 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8009 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8010 GET_MODE (op0), op0, op1);
8014 case RTX_BITFIELD_OPS:
8015 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8016 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8017 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8018 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8019 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8020 GET_MODE (op0), op0, op1, op2);
8025 if (rtx_equal_p (get_last_value (reg), x)
8026 || rtx_equal_p (reg, get_last_value (x)))
8035 fmt = GET_RTX_FORMAT (code);
8037 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8040 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8041 if (op != XEXP (x, i))
8051 else if (fmt[i] == 'E')
8054 for (j = 0; j < XVECLEN (x, i); j++)
8056 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8057 if (op != XVECEXP (x, i, j))
8064 XVECEXP (x, i, j) = op;
8075 /* Return X converted to MODE. If the value is already truncated to
8076 MODE we can just return a subreg even though in the general case we
8077 would need an explicit truncation. */
8080 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8082 if (!CONST_INT_P (x)
8083 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8084 && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8085 && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8087 /* Bit-cast X into an integer mode. */
8088 if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8089 x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8090 x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8094 return gen_lowpart (mode, x);
8097 /* See if X can be simplified knowing that we will only refer to it in
8098 MODE and will only refer to those bits that are nonzero in MASK.
8099 If other bits are being computed or if masking operations are done
8100 that select a superset of the bits in MASK, they can sometimes be
8103 Return a possibly simplified expression, but always convert X to
8104 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8106 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8107 are all off in X. This is used when X will be complemented, by either
8108 NOT, NEG, or XOR. */
8111 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8114 enum rtx_code code = GET_CODE (x);
8115 int next_select = just_select || code == XOR || code == NOT || code == NEG;
8116 enum machine_mode op_mode;
8117 unsigned HOST_WIDE_INT fuller_mask, nonzero;
8120 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8121 code below will do the wrong thing since the mode of such an
8122 expression is VOIDmode.
8124 Also do nothing if X is a CLOBBER; this can happen if X was
8125 the return value from a call to gen_lowpart. */
8126 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8129 /* We want to perform the operation is its present mode unless we know
8130 that the operation is valid in MODE, in which case we do the operation
8132 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8133 && have_insn_for (code, mode))
8134 ? mode : GET_MODE (x));
8136 /* It is not valid to do a right-shift in a narrower mode
8137 than the one it came in with. */
8138 if ((code == LSHIFTRT || code == ASHIFTRT)
8139 && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8140 op_mode = GET_MODE (x);
8142 /* Truncate MASK to fit OP_MODE. */
8144 mask &= GET_MODE_MASK (op_mode);
8146 /* When we have an arithmetic operation, or a shift whose count we
8147 do not know, we need to assume that all bits up to the highest-order
8148 bit in MASK will be needed. This is how we form such a mask. */
8149 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8150 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8152 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8155 /* Determine what bits of X are guaranteed to be (non)zero. */
8156 nonzero = nonzero_bits (x, mode);
8158 /* If none of the bits in X are needed, return a zero. */
8159 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8162 /* If X is a CONST_INT, return a new one. Do this here since the
8163 test below will fail. */
8164 if (CONST_INT_P (x))
8166 if (SCALAR_INT_MODE_P (mode))
8167 return gen_int_mode (INTVAL (x) & mask, mode);
8170 x = GEN_INT (INTVAL (x) & mask);
8171 return gen_lowpart_common (mode, x);
8175 /* If X is narrower than MODE and we want all the bits in X's mode, just
8176 get X in the proper mode. */
8177 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8178 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8179 return gen_lowpart (mode, x);
8181 /* We can ignore the effect of a SUBREG if it narrows the mode or
8182 if the constant masks to zero all the bits the mode doesn't have. */
8183 if (GET_CODE (x) == SUBREG
8184 && subreg_lowpart_p (x)
8185 && ((GET_MODE_SIZE (GET_MODE (x))
8186 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8188 & GET_MODE_MASK (GET_MODE (x))
8189 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8190 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8192 /* The arithmetic simplifications here only work for scalar integer modes. */
8193 if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8194 return gen_lowpart_or_truncate (mode, x);
8199 /* If X is a (clobber (const_int)), return it since we know we are
8200 generating something that won't match. */
8207 x = expand_compound_operation (x);
8208 if (GET_CODE (x) != code)
8209 return force_to_mode (x, mode, mask, next_select);
8213 /* Similarly for a truncate. */
8214 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8217 /* If this is an AND with a constant, convert it into an AND
8218 whose constant is the AND of that constant with MASK. If it
8219 remains an AND of MASK, delete it since it is redundant. */
8221 if (CONST_INT_P (XEXP (x, 1)))
8223 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8224 mask & INTVAL (XEXP (x, 1)));
8226 /* If X is still an AND, see if it is an AND with a mask that
8227 is just some low-order bits. If so, and it is MASK, we don't
8230 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8231 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8235 /* If it remains an AND, try making another AND with the bits
8236 in the mode mask that aren't in MASK turned on. If the
8237 constant in the AND is wide enough, this might make a
8238 cheaper constant. */
8240 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8241 && GET_MODE_MASK (GET_MODE (x)) != mask
8242 && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8244 unsigned HOST_WIDE_INT cval
8245 = UINTVAL (XEXP (x, 1))
8246 | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8247 int width = GET_MODE_PRECISION (GET_MODE (x));
8250 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8251 number, sign extend it. */
8252 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8253 && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8254 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8256 y = simplify_gen_binary (AND, GET_MODE (x),
8257 XEXP (x, 0), GEN_INT (cval));
8258 if (set_src_cost (y, optimize_this_for_speed_p)
8259 < set_src_cost (x, optimize_this_for_speed_p))
8269 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8270 low-order bits (as in an alignment operation) and FOO is already
8271 aligned to that boundary, mask C1 to that boundary as well.
8272 This may eliminate that PLUS and, later, the AND. */
8275 unsigned int width = GET_MODE_PRECISION (mode);
8276 unsigned HOST_WIDE_INT smask = mask;
8278 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8279 number, sign extend it. */
8281 if (width < HOST_BITS_PER_WIDE_INT
8282 && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8283 smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8285 if (CONST_INT_P (XEXP (x, 1))
8286 && exact_log2 (- smask) >= 0
8287 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8288 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8289 return force_to_mode (plus_constant (XEXP (x, 0),
8290 (INTVAL (XEXP (x, 1)) & smask)),
8291 mode, smask, next_select);
8294 /* ... fall through ... */
8297 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8298 most significant bit in MASK since carries from those bits will
8299 affect the bits we are interested in. */
8304 /* If X is (minus C Y) where C's least set bit is larger than any bit
8305 in the mask, then we may replace with (neg Y). */
8306 if (CONST_INT_P (XEXP (x, 0))
8307 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8308 & -INTVAL (XEXP (x, 0))))
8311 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8313 return force_to_mode (x, mode, mask, next_select);
8316 /* Similarly, if C contains every bit in the fuller_mask, then we may
8317 replace with (not Y). */
8318 if (CONST_INT_P (XEXP (x, 0))
8319 && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8321 x = simplify_gen_unary (NOT, GET_MODE (x),
8322 XEXP (x, 1), GET_MODE (x));
8323 return force_to_mode (x, mode, mask, next_select);
8331 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8332 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8333 operation which may be a bitfield extraction. Ensure that the
8334 constant we form is not wider than the mode of X. */
8336 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8337 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8338 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8339 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8340 && CONST_INT_P (XEXP (x, 1))
8341 && ((INTVAL (XEXP (XEXP (x, 0), 1))
8342 + floor_log2 (INTVAL (XEXP (x, 1))))
8343 < GET_MODE_PRECISION (GET_MODE (x)))
8344 && (UINTVAL (XEXP (x, 1))
8345 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8347 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8348 << INTVAL (XEXP (XEXP (x, 0), 1)));
8349 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8350 XEXP (XEXP (x, 0), 0), temp);
8351 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8352 XEXP (XEXP (x, 0), 1));
8353 return force_to_mode (x, mode, mask, next_select);
8357 /* For most binary operations, just propagate into the operation and
8358 change the mode if we have an operation of that mode. */
8360 op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8361 op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8363 /* If we ended up truncating both operands, truncate the result of the
8364 operation instead. */
8365 if (GET_CODE (op0) == TRUNCATE
8366 && GET_CODE (op1) == TRUNCATE)
8368 op0 = XEXP (op0, 0);
8369 op1 = XEXP (op1, 0);
8372 op0 = gen_lowpart_or_truncate (op_mode, op0);
8373 op1 = gen_lowpart_or_truncate (op_mode, op1);
8375 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8376 x = simplify_gen_binary (code, op_mode, op0, op1);
8380 /* For left shifts, do the same, but just for the first operand.
8381 However, we cannot do anything with shifts where we cannot
8382 guarantee that the counts are smaller than the size of the mode
8383 because such a count will have a different meaning in a
8386 if (! (CONST_INT_P (XEXP (x, 1))
8387 && INTVAL (XEXP (x, 1)) >= 0
8388 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8389 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8390 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8391 < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8394 /* If the shift count is a constant and we can do arithmetic in
8395 the mode of the shift, refine which bits we need. Otherwise, use the
8396 conservative form of the mask. */
8397 if (CONST_INT_P (XEXP (x, 1))
8398 && INTVAL (XEXP (x, 1)) >= 0
8399 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8400 && HWI_COMPUTABLE_MODE_P (op_mode))
8401 mask >>= INTVAL (XEXP (x, 1));
8405 op0 = gen_lowpart_or_truncate (op_mode,
8406 force_to_mode (XEXP (x, 0), op_mode,
8407 mask, next_select));
8409 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8410 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8414 /* Here we can only do something if the shift count is a constant,
8415 this shift constant is valid for the host, and we can do arithmetic
8418 if (CONST_INT_P (XEXP (x, 1))
8419 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8420 && HWI_COMPUTABLE_MODE_P (op_mode))
8422 rtx inner = XEXP (x, 0);
8423 unsigned HOST_WIDE_INT inner_mask;
8425 /* Select the mask of the bits we need for the shift operand. */
8426 inner_mask = mask << INTVAL (XEXP (x, 1));
8428 /* We can only change the mode of the shift if we can do arithmetic
8429 in the mode of the shift and INNER_MASK is no wider than the
8430 width of X's mode. */
8431 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8432 op_mode = GET_MODE (x);
8434 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8436 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8437 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8440 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8441 shift and AND produces only copies of the sign bit (C2 is one less
8442 than a power of two), we can do this with just a shift. */
8444 if (GET_CODE (x) == LSHIFTRT
8445 && CONST_INT_P (XEXP (x, 1))
8446 /* The shift puts one of the sign bit copies in the least significant
8448 && ((INTVAL (XEXP (x, 1))
8449 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8450 >= GET_MODE_PRECISION (GET_MODE (x)))
8451 && exact_log2 (mask + 1) >= 0
8452 /* Number of bits left after the shift must be more than the mask
8454 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8455 <= GET_MODE_PRECISION (GET_MODE (x)))
8456 /* Must be more sign bit copies than the mask needs. */
8457 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8458 >= exact_log2 (mask + 1)))
8459 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8460 GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8461 - exact_log2 (mask + 1)));
8466 /* If we are just looking for the sign bit, we don't need this shift at
8467 all, even if it has a variable count. */
8468 if (val_signbit_p (GET_MODE (x), mask))
8469 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8471 /* If this is a shift by a constant, get a mask that contains those bits
8472 that are not copies of the sign bit. We then have two cases: If
8473 MASK only includes those bits, this can be a logical shift, which may
8474 allow simplifications. If MASK is a single-bit field not within
8475 those bits, we are requesting a copy of the sign bit and hence can
8476 shift the sign bit to the appropriate location. */
8478 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8479 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8483 /* If the considered data is wider than HOST_WIDE_INT, we can't
8484 represent a mask for all its bits in a single scalar.
8485 But we only care about the lower bits, so calculate these. */
8487 if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8489 nonzero = ~(unsigned HOST_WIDE_INT) 0;
8491 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8492 is the number of bits a full-width mask would have set.
8493 We need only shift if these are fewer than nonzero can
8494 hold. If not, we must keep all bits set in nonzero. */
8496 if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8497 < HOST_BITS_PER_WIDE_INT)
8498 nonzero >>= INTVAL (XEXP (x, 1))
8499 + HOST_BITS_PER_WIDE_INT
8500 - GET_MODE_PRECISION (GET_MODE (x)) ;
8504 nonzero = GET_MODE_MASK (GET_MODE (x));
8505 nonzero >>= INTVAL (XEXP (x, 1));
8508 if ((mask & ~nonzero) == 0)
8510 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8511 XEXP (x, 0), INTVAL (XEXP (x, 1)));
8512 if (GET_CODE (x) != ASHIFTRT)
8513 return force_to_mode (x, mode, mask, next_select);
8516 else if ((i = exact_log2 (mask)) >= 0)
8518 x = simplify_shift_const
8519 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8520 GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8522 if (GET_CODE (x) != ASHIFTRT)
8523 return force_to_mode (x, mode, mask, next_select);
8527 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8528 even if the shift count isn't a constant. */
8530 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8531 XEXP (x, 0), XEXP (x, 1));
8535 /* If this is a zero- or sign-extension operation that just affects bits
8536 we don't care about, remove it. Be sure the call above returned
8537 something that is still a shift. */
8539 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8540 && CONST_INT_P (XEXP (x, 1))
8541 && INTVAL (XEXP (x, 1)) >= 0
8542 && (INTVAL (XEXP (x, 1))
8543 <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8544 && GET_CODE (XEXP (x, 0)) == ASHIFT
8545 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8546 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8553 /* If the shift count is constant and we can do computations
8554 in the mode of X, compute where the bits we care about are.
8555 Otherwise, we can't do anything. Don't change the mode of
8556 the shift or propagate MODE into the shift, though. */
8557 if (CONST_INT_P (XEXP (x, 1))
8558 && INTVAL (XEXP (x, 1)) >= 0)
8560 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8561 GET_MODE (x), GEN_INT (mask),
8563 if (temp && CONST_INT_P (temp))
8565 force_to_mode (XEXP (x, 0), GET_MODE (x),
8566 INTVAL (temp), next_select));
8571 /* If we just want the low-order bit, the NEG isn't needed since it
8572 won't change the low-order bit. */
8574 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8576 /* We need any bits less significant than the most significant bit in
8577 MASK since carries from those bits will affect the bits we are
8583 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8584 same as the XOR case above. Ensure that the constant we form is not
8585 wider than the mode of X. */
8587 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8588 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8589 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8590 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8591 < GET_MODE_PRECISION (GET_MODE (x)))
8592 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8594 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8596 temp = simplify_gen_binary (XOR, GET_MODE (x),
8597 XEXP (XEXP (x, 0), 0), temp);
8598 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8599 temp, XEXP (XEXP (x, 0), 1));
8601 return force_to_mode (x, mode, mask, next_select);
8604 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8605 use the full mask inside the NOT. */
8609 op0 = gen_lowpart_or_truncate (op_mode,
8610 force_to_mode (XEXP (x, 0), mode, mask,
8612 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8613 x = simplify_gen_unary (code, op_mode, op0, op_mode);
8617 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8618 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8619 which is equal to STORE_FLAG_VALUE. */
8620 if ((mask & ~STORE_FLAG_VALUE) == 0
8621 && XEXP (x, 1) == const0_rtx
8622 && GET_MODE (XEXP (x, 0)) == mode
8623 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8624 && (nonzero_bits (XEXP (x, 0), mode)
8625 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8626 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8631 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8632 written in a narrower mode. We play it safe and do not do so. */
8635 gen_lowpart_or_truncate (GET_MODE (x),
8636 force_to_mode (XEXP (x, 1), mode,
8637 mask, next_select)));
8639 gen_lowpart_or_truncate (GET_MODE (x),
8640 force_to_mode (XEXP (x, 2), mode,
8641 mask, next_select)));
8648 /* Ensure we return a value of the proper mode. */
8649 return gen_lowpart_or_truncate (mode, x);
8652 /* Return nonzero if X is an expression that has one of two values depending on
8653 whether some other value is zero or nonzero. In that case, we return the
8654 value that is being tested, *PTRUE is set to the value if the rtx being
8655 returned has a nonzero value, and *PFALSE is set to the other alternative.
8657 If we return zero, we set *PTRUE and *PFALSE to X. */
8660 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8662 enum machine_mode mode = GET_MODE (x);
8663 enum rtx_code code = GET_CODE (x);
8664 rtx cond0, cond1, true0, true1, false0, false1;
8665 unsigned HOST_WIDE_INT nz;
8667 /* If we are comparing a value against zero, we are done. */
8668 if ((code == NE || code == EQ)
8669 && XEXP (x, 1) == const0_rtx)
8671 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8672 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8676 /* If this is a unary operation whose operand has one of two values, apply
8677 our opcode to compute those values. */
8678 else if (UNARY_P (x)
8679 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8681 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8682 *pfalse = simplify_gen_unary (code, mode, false0,
8683 GET_MODE (XEXP (x, 0)));
8687 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8688 make can't possibly match and would suppress other optimizations. */
8689 else if (code == COMPARE)
8692 /* If this is a binary operation, see if either side has only one of two
8693 values. If either one does or if both do and they are conditional on
8694 the same value, compute the new true and false values. */
8695 else if (BINARY_P (x))
8697 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8698 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8700 if ((cond0 != 0 || cond1 != 0)
8701 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8703 /* If if_then_else_cond returned zero, then true/false are the
8704 same rtl. We must copy one of them to prevent invalid rtl
8707 true0 = copy_rtx (true0);
8708 else if (cond1 == 0)
8709 true1 = copy_rtx (true1);
8711 if (COMPARISON_P (x))
8713 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8715 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8720 *ptrue = simplify_gen_binary (code, mode, true0, true1);
8721 *pfalse = simplify_gen_binary (code, mode, false0, false1);
8724 return cond0 ? cond0 : cond1;
8727 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8728 operands is zero when the other is nonzero, and vice-versa,
8729 and STORE_FLAG_VALUE is 1 or -1. */
8731 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8732 && (code == PLUS || code == IOR || code == XOR || code == MINUS
8734 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8736 rtx op0 = XEXP (XEXP (x, 0), 1);
8737 rtx op1 = XEXP (XEXP (x, 1), 1);
8739 cond0 = XEXP (XEXP (x, 0), 0);
8740 cond1 = XEXP (XEXP (x, 1), 0);
8742 if (COMPARISON_P (cond0)
8743 && COMPARISON_P (cond1)
8744 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8745 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8746 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8747 || ((swap_condition (GET_CODE (cond0))
8748 == reversed_comparison_code (cond1, NULL))
8749 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8750 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8751 && ! side_effects_p (x))
8753 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8754 *pfalse = simplify_gen_binary (MULT, mode,
8756 ? simplify_gen_unary (NEG, mode,
8764 /* Similarly for MULT, AND and UMIN, except that for these the result
8766 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8767 && (code == MULT || code == AND || code == UMIN)
8768 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8770 cond0 = XEXP (XEXP (x, 0), 0);
8771 cond1 = XEXP (XEXP (x, 1), 0);
8773 if (COMPARISON_P (cond0)
8774 && COMPARISON_P (cond1)
8775 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8776 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8777 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8778 || ((swap_condition (GET_CODE (cond0))
8779 == reversed_comparison_code (cond1, NULL))
8780 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8781 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8782 && ! side_effects_p (x))
8784 *ptrue = *pfalse = const0_rtx;
8790 else if (code == IF_THEN_ELSE)
8792 /* If we have IF_THEN_ELSE already, extract the condition and
8793 canonicalize it if it is NE or EQ. */
8794 cond0 = XEXP (x, 0);
8795 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8796 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8797 return XEXP (cond0, 0);
8798 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8800 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8801 return XEXP (cond0, 0);
8807 /* If X is a SUBREG, we can narrow both the true and false values
8808 if the inner expression, if there is a condition. */
8809 else if (code == SUBREG
8810 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8813 true0 = simplify_gen_subreg (mode, true0,
8814 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8815 false0 = simplify_gen_subreg (mode, false0,
8816 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8817 if (true0 && false0)
8825 /* If X is a constant, this isn't special and will cause confusions
8826 if we treat it as such. Likewise if it is equivalent to a constant. */
8827 else if (CONSTANT_P (x)
8828 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8831 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8832 will be least confusing to the rest of the compiler. */
8833 else if (mode == BImode)
8835 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8839 /* If X is known to be either 0 or -1, those are the true and
8840 false values when testing X. */
8841 else if (x == constm1_rtx || x == const0_rtx
8842 || (mode != VOIDmode
8843 && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8845 *ptrue = constm1_rtx, *pfalse = const0_rtx;
8849 /* Likewise for 0 or a single bit. */
8850 else if (HWI_COMPUTABLE_MODE_P (mode)
8851 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8853 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8857 /* Otherwise fail; show no condition with true and false values the same. */
8858 *ptrue = *pfalse = x;
8862 /* Return the value of expression X given the fact that condition COND
8863 is known to be true when applied to REG as its first operand and VAL
8864 as its second. X is known to not be shared and so can be modified in
8867 We only handle the simplest cases, and specifically those cases that
8868 arise with IF_THEN_ELSE expressions. */
8871 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8873 enum rtx_code code = GET_CODE (x);
8878 if (side_effects_p (x))
8881 /* If either operand of the condition is a floating point value,
8882 then we have to avoid collapsing an EQ comparison. */
8884 && rtx_equal_p (x, reg)
8885 && ! FLOAT_MODE_P (GET_MODE (x))
8886 && ! FLOAT_MODE_P (GET_MODE (val)))
8889 if (cond == UNEQ && rtx_equal_p (x, reg))
8892 /* If X is (abs REG) and we know something about REG's relationship
8893 with zero, we may be able to simplify this. */
8895 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8898 case GE: case GT: case EQ:
8901 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8903 GET_MODE (XEXP (x, 0)));
8908 /* The only other cases we handle are MIN, MAX, and comparisons if the
8909 operands are the same as REG and VAL. */
8911 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8913 if (rtx_equal_p (XEXP (x, 0), val))
8914 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8916 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8918 if (COMPARISON_P (x))
8920 if (comparison_dominates_p (cond, code))
8921 return const_true_rtx;
8923 code = reversed_comparison_code (x, NULL);
8925 && comparison_dominates_p (cond, code))
8930 else if (code == SMAX || code == SMIN
8931 || code == UMIN || code == UMAX)
8933 int unsignedp = (code == UMIN || code == UMAX);
8935 /* Do not reverse the condition when it is NE or EQ.
8936 This is because we cannot conclude anything about
8937 the value of 'SMAX (x, y)' when x is not equal to y,
8938 but we can when x equals y. */
8939 if ((code == SMAX || code == UMAX)
8940 && ! (cond == EQ || cond == NE))
8941 cond = reverse_condition (cond);
8946 return unsignedp ? x : XEXP (x, 1);
8948 return unsignedp ? x : XEXP (x, 0);
8950 return unsignedp ? XEXP (x, 1) : x;
8952 return unsignedp ? XEXP (x, 0) : x;
8959 else if (code == SUBREG)
8961 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8962 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8964 if (SUBREG_REG (x) != r)
8966 /* We must simplify subreg here, before we lose track of the
8967 original inner_mode. */
8968 new_rtx = simplify_subreg (GET_MODE (x), r,
8969 inner_mode, SUBREG_BYTE (x));
8973 SUBST (SUBREG_REG (x), r);
8978 /* We don't have to handle SIGN_EXTEND here, because even in the
8979 case of replacing something with a modeless CONST_INT, a
8980 CONST_INT is already (supposed to be) a valid sign extension for
8981 its narrower mode, which implies it's already properly
8982 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8983 story is different. */
8984 else if (code == ZERO_EXTEND)
8986 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8987 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8989 if (XEXP (x, 0) != r)
8991 /* We must simplify the zero_extend here, before we lose
8992 track of the original inner_mode. */
8993 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8998 SUBST (XEXP (x, 0), r);
9004 fmt = GET_RTX_FORMAT (code);
9005 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9008 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9009 else if (fmt[i] == 'E')
9010 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9011 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9018 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9019 assignment as a field assignment. */
9022 rtx_equal_for_field_assignment_p (rtx x, rtx y)
9024 if (x == y || rtx_equal_p (x, y))
9027 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9030 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9031 Note that all SUBREGs of MEM are paradoxical; otherwise they
9032 would have been rewritten. */
9033 if (MEM_P (x) && GET_CODE (y) == SUBREG
9034 && MEM_P (SUBREG_REG (y))
9035 && rtx_equal_p (SUBREG_REG (y),
9036 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9039 if (MEM_P (y) && GET_CODE (x) == SUBREG
9040 && MEM_P (SUBREG_REG (x))
9041 && rtx_equal_p (SUBREG_REG (x),
9042 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9045 /* We used to see if get_last_value of X and Y were the same but that's
9046 not correct. In one direction, we'll cause the assignment to have
9047 the wrong destination and in the case, we'll import a register into this
9048 insn that might have already have been dead. So fail if none of the
9049 above cases are true. */
9053 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9054 Return that assignment if so.
9056 We only handle the most common cases. */
9059 make_field_assignment (rtx x)
9061 rtx dest = SET_DEST (x);
9062 rtx src = SET_SRC (x);
9067 unsigned HOST_WIDE_INT len;
9069 enum machine_mode mode;
9071 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9072 a clear of a one-bit field. We will have changed it to
9073 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9076 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9077 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9078 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9079 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9081 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9084 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9088 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9089 && subreg_lowpart_p (XEXP (src, 0))
9090 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9091 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9092 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9093 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9094 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9095 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9097 assign = make_extraction (VOIDmode, dest, 0,
9098 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9101 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9105 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9107 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9108 && XEXP (XEXP (src, 0), 0) == const1_rtx
9109 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9111 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9114 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9118 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9119 SRC is an AND with all bits of that field set, then we can discard
9121 if (GET_CODE (dest) == ZERO_EXTRACT
9122 && CONST_INT_P (XEXP (dest, 1))
9123 && GET_CODE (src) == AND
9124 && CONST_INT_P (XEXP (src, 1)))
9126 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9127 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9128 unsigned HOST_WIDE_INT ze_mask;
9130 if (width >= HOST_BITS_PER_WIDE_INT)
9133 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9135 /* Complete overlap. We can remove the source AND. */
9136 if ((and_mask & ze_mask) == ze_mask)
9137 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9139 /* Partial overlap. We can reduce the source AND. */
9140 if ((and_mask & ze_mask) != and_mask)
9142 mode = GET_MODE (src);
9143 src = gen_rtx_AND (mode, XEXP (src, 0),
9144 gen_int_mode (and_mask & ze_mask, mode));
9145 return gen_rtx_SET (VOIDmode, dest, src);
9149 /* The other case we handle is assignments into a constant-position
9150 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9151 a mask that has all one bits except for a group of zero bits and
9152 OTHER is known to have zeros where C1 has ones, this is such an
9153 assignment. Compute the position and length from C1. Shift OTHER
9154 to the appropriate position, force it to the required mode, and
9155 make the extraction. Check for the AND in both operands. */
9157 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9160 rhs = expand_compound_operation (XEXP (src, 0));
9161 lhs = expand_compound_operation (XEXP (src, 1));
9163 if (GET_CODE (rhs) == AND
9164 && CONST_INT_P (XEXP (rhs, 1))
9165 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9166 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9167 else if (GET_CODE (lhs) == AND
9168 && CONST_INT_P (XEXP (lhs, 1))
9169 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9170 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9174 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9175 if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9176 || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9177 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9180 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9184 /* The mode to use for the source is the mode of the assignment, or of
9185 what is inside a possible STRICT_LOW_PART. */
9186 mode = (GET_CODE (assign) == STRICT_LOW_PART
9187 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9189 /* Shift OTHER right POS places and make it the source, restricting it
9190 to the proper length and mode. */
9192 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9196 src = force_to_mode (src, mode,
9197 GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9198 ? ~(unsigned HOST_WIDE_INT) 0
9199 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9202 /* If SRC is masked by an AND that does not make a difference in
9203 the value being stored, strip it. */
9204 if (GET_CODE (assign) == ZERO_EXTRACT
9205 && CONST_INT_P (XEXP (assign, 1))
9206 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9207 && GET_CODE (src) == AND
9208 && CONST_INT_P (XEXP (src, 1))
9209 && UINTVAL (XEXP (src, 1))
9210 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9211 src = XEXP (src, 0);
9213 return gen_rtx_SET (VOIDmode, assign, src);
9216 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9220 apply_distributive_law (rtx x)
9222 enum rtx_code code = GET_CODE (x);
9223 enum rtx_code inner_code;
9224 rtx lhs, rhs, other;
9227 /* Distributivity is not true for floating point as it can change the
9228 value. So we don't do it unless -funsafe-math-optimizations. */
9229 if (FLOAT_MODE_P (GET_MODE (x))
9230 && ! flag_unsafe_math_optimizations)
9233 /* The outer operation can only be one of the following: */
9234 if (code != IOR && code != AND && code != XOR
9235 && code != PLUS && code != MINUS)
9241 /* If either operand is a primitive we can't do anything, so get out
9243 if (OBJECT_P (lhs) || OBJECT_P (rhs))
9246 lhs = expand_compound_operation (lhs);
9247 rhs = expand_compound_operation (rhs);
9248 inner_code = GET_CODE (lhs);
9249 if (inner_code != GET_CODE (rhs))
9252 /* See if the inner and outer operations distribute. */
9259 /* These all distribute except over PLUS. */
9260 if (code == PLUS || code == MINUS)
9265 if (code != PLUS && code != MINUS)
9270 /* This is also a multiply, so it distributes over everything. */
9274 /* Non-paradoxical SUBREGs distributes over all operations,
9275 provided the inner modes and byte offsets are the same, this
9276 is an extraction of a low-order part, we don't convert an fp
9277 operation to int or vice versa, this is not a vector mode,
9278 and we would not be converting a single-word operation into a
9279 multi-word operation. The latter test is not required, but
9280 it prevents generating unneeded multi-word operations. Some
9281 of the previous tests are redundant given the latter test,
9282 but are retained because they are required for correctness.
9284 We produce the result slightly differently in this case. */
9286 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9287 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9288 || ! subreg_lowpart_p (lhs)
9289 || (GET_MODE_CLASS (GET_MODE (lhs))
9290 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9291 || paradoxical_subreg_p (lhs)
9292 || VECTOR_MODE_P (GET_MODE (lhs))
9293 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9294 /* Result might need to be truncated. Don't change mode if
9295 explicit truncation is needed. */
9296 || !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x),
9297 GET_MODE (SUBREG_REG (lhs))))
9300 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9301 SUBREG_REG (lhs), SUBREG_REG (rhs));
9302 return gen_lowpart (GET_MODE (x), tem);
9308 /* Set LHS and RHS to the inner operands (A and B in the example
9309 above) and set OTHER to the common operand (C in the example).
9310 There is only one way to do this unless the inner operation is
9312 if (COMMUTATIVE_ARITH_P (lhs)
9313 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9314 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9315 else if (COMMUTATIVE_ARITH_P (lhs)
9316 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9317 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9318 else if (COMMUTATIVE_ARITH_P (lhs)
9319 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9320 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9321 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9322 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9326 /* Form the new inner operation, seeing if it simplifies first. */
9327 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9329 /* There is one exception to the general way of distributing:
9330 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9331 if (code == XOR && inner_code == IOR)
9334 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9337 /* We may be able to continuing distributing the result, so call
9338 ourselves recursively on the inner operation before forming the
9339 outer operation, which we return. */
9340 return simplify_gen_binary (inner_code, GET_MODE (x),
9341 apply_distributive_law (tem), other);
9344 /* See if X is of the form (* (+ A B) C), and if so convert to
9345 (+ (* A C) (* B C)) and try to simplify.
9347 Most of the time, this results in no change. However, if some of
9348 the operands are the same or inverses of each other, simplifications
9351 For example, (and (ior A B) (not B)) can occur as the result of
9352 expanding a bit field assignment. When we apply the distributive
9353 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9354 which then simplifies to (and (A (not B))).
9356 Note that no checks happen on the validity of applying the inverse
9357 distributive law. This is pointless since we can do it in the
9358 few places where this routine is called.
9360 N is the index of the term that is decomposed (the arithmetic operation,
9361 i.e. (+ A B) in the first example above). !N is the index of the term that
9362 is distributed, i.e. of C in the first example above. */
9364 distribute_and_simplify_rtx (rtx x, int n)
9366 enum machine_mode mode;
9367 enum rtx_code outer_code, inner_code;
9368 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9370 /* Distributivity is not true for floating point as it can change the
9371 value. So we don't do it unless -funsafe-math-optimizations. */
9372 if (FLOAT_MODE_P (GET_MODE (x))
9373 && ! flag_unsafe_math_optimizations)
9376 decomposed = XEXP (x, n);
9377 if (!ARITHMETIC_P (decomposed))
9380 mode = GET_MODE (x);
9381 outer_code = GET_CODE (x);
9382 distributed = XEXP (x, !n);
9384 inner_code = GET_CODE (decomposed);
9385 inner_op0 = XEXP (decomposed, 0);
9386 inner_op1 = XEXP (decomposed, 1);
9388 /* Special case (and (xor B C) (not A)), which is equivalent to
9389 (xor (ior A B) (ior A C)) */
9390 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9392 distributed = XEXP (distributed, 0);
9398 /* Distribute the second term. */
9399 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9400 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9404 /* Distribute the first term. */
9405 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9406 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9409 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9411 if (GET_CODE (tmp) != outer_code
9412 && (set_src_cost (tmp, optimize_this_for_speed_p)
9413 < set_src_cost (x, optimize_this_for_speed_p)))
9419 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9420 in MODE. Return an equivalent form, if different from (and VAROP
9421 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9424 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9425 unsigned HOST_WIDE_INT constop)
9427 unsigned HOST_WIDE_INT nonzero;
9428 unsigned HOST_WIDE_INT orig_constop;
9433 orig_constop = constop;
9434 if (GET_CODE (varop) == CLOBBER)
9437 /* Simplify VAROP knowing that we will be only looking at some of the
9440 Note by passing in CONSTOP, we guarantee that the bits not set in
9441 CONSTOP are not significant and will never be examined. We must
9442 ensure that is the case by explicitly masking out those bits
9443 before returning. */
9444 varop = force_to_mode (varop, mode, constop, 0);
9446 /* If VAROP is a CLOBBER, we will fail so return it. */
9447 if (GET_CODE (varop) == CLOBBER)
9450 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9451 to VAROP and return the new constant. */
9452 if (CONST_INT_P (varop))
9453 return gen_int_mode (INTVAL (varop) & constop, mode);
9455 /* See what bits may be nonzero in VAROP. Unlike the general case of
9456 a call to nonzero_bits, here we don't care about bits outside
9459 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9461 /* Turn off all bits in the constant that are known to already be zero.
9462 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9463 which is tested below. */
9467 /* If we don't have any bits left, return zero. */
9471 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9472 a power of two, we can replace this with an ASHIFT. */
9473 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9474 && (i = exact_log2 (constop)) >= 0)
9475 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9477 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9478 or XOR, then try to apply the distributive law. This may eliminate
9479 operations if either branch can be simplified because of the AND.
9480 It may also make some cases more complex, but those cases probably
9481 won't match a pattern either with or without this. */
9483 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9487 apply_distributive_law
9488 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9489 simplify_and_const_int (NULL_RTX,
9493 simplify_and_const_int (NULL_RTX,
9498 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9499 the AND and see if one of the operands simplifies to zero. If so, we
9500 may eliminate it. */
9502 if (GET_CODE (varop) == PLUS
9503 && exact_log2 (constop + 1) >= 0)
9507 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9508 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9509 if (o0 == const0_rtx)
9511 if (o1 == const0_rtx)
9515 /* Make a SUBREG if necessary. If we can't make it, fail. */
9516 varop = gen_lowpart (mode, varop);
9517 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9520 /* If we are only masking insignificant bits, return VAROP. */
9521 if (constop == nonzero)
9524 if (varop == orig_varop && constop == orig_constop)
9527 /* Otherwise, return an AND. */
9528 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9532 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9535 Return an equivalent form, if different from X. Otherwise, return X. If
9536 X is zero, we are to always construct the equivalent form. */
9539 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9540 unsigned HOST_WIDE_INT constop)
9542 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9547 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9548 gen_int_mode (constop, mode));
9549 if (GET_MODE (x) != mode)
9550 x = gen_lowpart (mode, x);
9554 /* Given a REG, X, compute which bits in X can be nonzero.
9555 We don't care about bits outside of those defined in MODE.
9557 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9558 a shift, AND, or zero_extract, we can do better. */
9561 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9562 const_rtx known_x ATTRIBUTE_UNUSED,
9563 enum machine_mode known_mode ATTRIBUTE_UNUSED,
9564 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9565 unsigned HOST_WIDE_INT *nonzero)
9570 /* If X is a register whose nonzero bits value is current, use it.
9571 Otherwise, if X is a register whose value we can find, use that
9572 value. Otherwise, use the previously-computed global nonzero bits
9573 for this register. */
9575 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9576 if (rsp->last_set_value != 0
9577 && (rsp->last_set_mode == mode
9578 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9579 && GET_MODE_CLASS (mode) == MODE_INT))
9580 && ((rsp->last_set_label >= label_tick_ebb_start
9581 && rsp->last_set_label < label_tick)
9582 || (rsp->last_set_label == label_tick
9583 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9584 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9585 && REG_N_SETS (REGNO (x)) == 1
9587 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9589 *nonzero &= rsp->last_set_nonzero_bits;
9593 tem = get_last_value (x);
9597 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9598 /* If X is narrower than MODE and TEM is a non-negative
9599 constant that would appear negative in the mode of X,
9600 sign-extend it for use in reg_nonzero_bits because some
9601 machines (maybe most) will actually do the sign-extension
9602 and this is the conservative approach.
9604 ??? For 2.5, try to tighten up the MD files in this regard
9605 instead of this kludge. */
9607 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9608 && CONST_INT_P (tem)
9610 && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9611 tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9615 else if (nonzero_sign_valid && rsp->nonzero_bits)
9617 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9619 if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9620 /* We don't know anything about the upper bits. */
9621 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9628 /* Return the number of bits at the high-order end of X that are known to
9629 be equal to the sign bit. X will be used in mode MODE; if MODE is
9630 VOIDmode, X will be used in its own mode. The returned value will always
9631 be between 1 and the number of bits in MODE. */
9634 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9635 const_rtx known_x ATTRIBUTE_UNUSED,
9636 enum machine_mode known_mode
9638 unsigned int known_ret ATTRIBUTE_UNUSED,
9639 unsigned int *result)
9644 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9645 if (rsp->last_set_value != 0
9646 && rsp->last_set_mode == mode
9647 && ((rsp->last_set_label >= label_tick_ebb_start
9648 && rsp->last_set_label < label_tick)
9649 || (rsp->last_set_label == label_tick
9650 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9651 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9652 && REG_N_SETS (REGNO (x)) == 1
9654 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9656 *result = rsp->last_set_sign_bit_copies;
9660 tem = get_last_value (x);
9664 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9665 && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9666 *result = rsp->sign_bit_copies;
9671 /* Return the number of "extended" bits there are in X, when interpreted
9672 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9673 unsigned quantities, this is the number of high-order zero bits.
9674 For signed quantities, this is the number of copies of the sign bit
9675 minus 1. In both case, this function returns the number of "spare"
9676 bits. For example, if two quantities for which this function returns
9677 at least 1 are added, the addition is known not to overflow.
9679 This function will always return 0 unless called during combine, which
9680 implies that it must be called from a define_split. */
9683 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9685 if (nonzero_sign_valid == 0)
9689 ? (HWI_COMPUTABLE_MODE_P (mode)
9690 ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9691 - floor_log2 (nonzero_bits (x, mode)))
9693 : num_sign_bit_copies (x, mode) - 1);
9696 /* This function is called from `simplify_shift_const' to merge two
9697 outer operations. Specifically, we have already found that we need
9698 to perform operation *POP0 with constant *PCONST0 at the outermost
9699 position. We would now like to also perform OP1 with constant CONST1
9700 (with *POP0 being done last).
9702 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9703 the resulting operation. *PCOMP_P is set to 1 if we would need to
9704 complement the innermost operand, otherwise it is unchanged.
9706 MODE is the mode in which the operation will be done. No bits outside
9707 the width of this mode matter. It is assumed that the width of this mode
9708 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9710 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9711 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9712 result is simply *PCONST0.
9714 If the resulting operation cannot be expressed as one operation, we
9715 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9718 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9720 enum rtx_code op0 = *pop0;
9721 HOST_WIDE_INT const0 = *pconst0;
9723 const0 &= GET_MODE_MASK (mode);
9724 const1 &= GET_MODE_MASK (mode);
9726 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9730 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9733 if (op1 == UNKNOWN || op0 == SET)
9736 else if (op0 == UNKNOWN)
9737 op0 = op1, const0 = const1;
9739 else if (op0 == op1)
9763 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9764 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9767 /* If the two constants aren't the same, we can't do anything. The
9768 remaining six cases can all be done. */
9769 else if (const0 != const1)
9777 /* (a & b) | b == b */
9779 else /* op1 == XOR */
9780 /* (a ^ b) | b == a | b */
9786 /* (a & b) ^ b == (~a) & b */
9787 op0 = AND, *pcomp_p = 1;
9788 else /* op1 == IOR */
9789 /* (a | b) ^ b == a & ~b */
9790 op0 = AND, const0 = ~const0;
9795 /* (a | b) & b == b */
9797 else /* op1 == XOR */
9798 /* (a ^ b) & b) == (~a) & b */
9805 /* Check for NO-OP cases. */
9806 const0 &= GET_MODE_MASK (mode);
9808 && (op0 == IOR || op0 == XOR || op0 == PLUS))
9810 else if (const0 == 0 && op0 == AND)
9812 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9818 /* ??? Slightly redundant with the above mask, but not entirely.
9819 Moving this above means we'd have to sign-extend the mode mask
9820 for the final test. */
9821 if (op0 != UNKNOWN && op0 != NEG)
9822 *pconst0 = trunc_int_for_mode (const0, mode);
9827 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9828 the shift in. The original shift operation CODE is performed on OP in
9829 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9830 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9831 result of the shift is subject to operation OUTER_CODE with operand
9834 static enum machine_mode
9835 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9836 enum machine_mode orig_mode, enum machine_mode mode,
9837 enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9839 if (orig_mode == mode)
9841 gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9843 /* In general we can't perform in wider mode for right shift and rotate. */
9847 /* We can still widen if the bits brought in from the left are identical
9848 to the sign bit of ORIG_MODE. */
9849 if (num_sign_bit_copies (op, mode)
9850 > (unsigned) (GET_MODE_PRECISION (mode)
9851 - GET_MODE_PRECISION (orig_mode)))
9856 /* Similarly here but with zero bits. */
9857 if (HWI_COMPUTABLE_MODE_P (mode)
9858 && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9861 /* We can also widen if the bits brought in will be masked off. This
9862 operation is performed in ORIG_MODE. */
9863 if (outer_code == AND)
9865 int care_bits = low_bitmask_len (orig_mode, outer_const);
9868 && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9884 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9885 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9886 if we cannot simplify it. Otherwise, return a simplified value.
9888 The shift is normally computed in the widest mode we find in VAROP, as
9889 long as it isn't a different number of words than RESULT_MODE. Exceptions
9890 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9893 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9894 rtx varop, int orig_count)
9896 enum rtx_code orig_code = code;
9897 rtx orig_varop = varop;
9899 enum machine_mode mode = result_mode;
9900 enum machine_mode shift_mode, tmode;
9901 unsigned int mode_words
9902 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9903 /* We form (outer_op (code varop count) (outer_const)). */
9904 enum rtx_code outer_op = UNKNOWN;
9905 HOST_WIDE_INT outer_const = 0;
9906 int complement_p = 0;
9909 /* Make sure and truncate the "natural" shift on the way in. We don't
9910 want to do this inside the loop as it makes it more difficult to
9912 if (SHIFT_COUNT_TRUNCATED)
9913 orig_count &= GET_MODE_BITSIZE (mode) - 1;
9915 /* If we were given an invalid count, don't do anything except exactly
9916 what was requested. */
9918 if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9923 /* Unless one of the branches of the `if' in this loop does a `continue',
9924 we will `break' the loop after the `if'. */
9928 /* If we have an operand of (clobber (const_int 0)), fail. */
9929 if (GET_CODE (varop) == CLOBBER)
9932 /* Convert ROTATERT to ROTATE. */
9933 if (code == ROTATERT)
9935 unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9937 if (VECTOR_MODE_P (result_mode))
9938 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9940 count = bitsize - count;
9943 shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9944 mode, outer_op, outer_const);
9946 /* Handle cases where the count is greater than the size of the mode
9947 minus 1. For ASHIFT, use the size minus one as the count (this can
9948 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9949 take the count modulo the size. For other shifts, the result is
9952 Since these shifts are being produced by the compiler by combining
9953 multiple operations, each of which are defined, we know what the
9954 result is supposed to be. */
9956 if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9958 if (code == ASHIFTRT)
9959 count = GET_MODE_PRECISION (shift_mode) - 1;
9960 else if (code == ROTATE || code == ROTATERT)
9961 count %= GET_MODE_PRECISION (shift_mode);
9964 /* We can't simply return zero because there may be an
9972 /* If we discovered we had to complement VAROP, leave. Making a NOT
9973 here would cause an infinite loop. */
9977 /* An arithmetic right shift of a quantity known to be -1 or 0
9979 if (code == ASHIFTRT
9980 && (num_sign_bit_copies (varop, shift_mode)
9981 == GET_MODE_PRECISION (shift_mode)))
9987 /* If we are doing an arithmetic right shift and discarding all but
9988 the sign bit copies, this is equivalent to doing a shift by the
9989 bitsize minus one. Convert it into that shift because it will often
9990 allow other simplifications. */
9992 if (code == ASHIFTRT
9993 && (count + num_sign_bit_copies (varop, shift_mode)
9994 >= GET_MODE_PRECISION (shift_mode)))
9995 count = GET_MODE_PRECISION (shift_mode) - 1;
9997 /* We simplify the tests below and elsewhere by converting
9998 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9999 `make_compound_operation' will convert it to an ASHIFTRT for
10000 those machines (such as VAX) that don't have an LSHIFTRT. */
10001 if (code == ASHIFTRT
10002 && val_signbit_known_clear_p (shift_mode,
10003 nonzero_bits (varop, shift_mode)))
10006 if (((code == LSHIFTRT
10007 && HWI_COMPUTABLE_MODE_P (shift_mode)
10008 && !(nonzero_bits (varop, shift_mode) >> count))
10010 && HWI_COMPUTABLE_MODE_P (shift_mode)
10011 && !((nonzero_bits (varop, shift_mode) << count)
10012 & GET_MODE_MASK (shift_mode))))
10013 && !side_effects_p (varop))
10014 varop = const0_rtx;
10016 switch (GET_CODE (varop))
10022 new_rtx = expand_compound_operation (varop);
10023 if (new_rtx != varop)
10031 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10032 minus the width of a smaller mode, we can do this with a
10033 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10034 if ((code == ASHIFTRT || code == LSHIFTRT)
10035 && ! mode_dependent_address_p (XEXP (varop, 0))
10036 && ! MEM_VOLATILE_P (varop)
10037 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10038 MODE_INT, 1)) != BLKmode)
10040 new_rtx = adjust_address_nv (varop, tmode,
10041 BYTES_BIG_ENDIAN ? 0
10042 : count / BITS_PER_UNIT);
10044 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10045 : ZERO_EXTEND, mode, new_rtx);
10052 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10053 the same number of words as what we've seen so far. Then store
10054 the widest mode in MODE. */
10055 if (subreg_lowpart_p (varop)
10056 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10057 > GET_MODE_SIZE (GET_MODE (varop)))
10058 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10059 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10061 && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10062 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10064 varop = SUBREG_REG (varop);
10065 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10066 mode = GET_MODE (varop);
10072 /* Some machines use MULT instead of ASHIFT because MULT
10073 is cheaper. But it is still better on those machines to
10074 merge two shifts into one. */
10075 if (CONST_INT_P (XEXP (varop, 1))
10076 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10079 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10081 GEN_INT (exact_log2 (
10082 UINTVAL (XEXP (varop, 1)))));
10088 /* Similar, for when divides are cheaper. */
10089 if (CONST_INT_P (XEXP (varop, 1))
10090 && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10093 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10095 GEN_INT (exact_log2 (
10096 UINTVAL (XEXP (varop, 1)))));
10102 /* If we are extracting just the sign bit of an arithmetic
10103 right shift, that shift is not needed. However, the sign
10104 bit of a wider mode may be different from what would be
10105 interpreted as the sign bit in a narrower mode, so, if
10106 the result is narrower, don't discard the shift. */
10107 if (code == LSHIFTRT
10108 && count == (GET_MODE_BITSIZE (result_mode) - 1)
10109 && (GET_MODE_BITSIZE (result_mode)
10110 >= GET_MODE_BITSIZE (GET_MODE (varop))))
10112 varop = XEXP (varop, 0);
10116 /* ... fall through ... */
10121 /* Here we have two nested shifts. The result is usually the
10122 AND of a new shift with a mask. We compute the result below. */
10123 if (CONST_INT_P (XEXP (varop, 1))
10124 && INTVAL (XEXP (varop, 1)) >= 0
10125 && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10126 && HWI_COMPUTABLE_MODE_P (result_mode)
10127 && HWI_COMPUTABLE_MODE_P (mode)
10128 && !VECTOR_MODE_P (result_mode))
10130 enum rtx_code first_code = GET_CODE (varop);
10131 unsigned int first_count = INTVAL (XEXP (varop, 1));
10132 unsigned HOST_WIDE_INT mask;
10135 /* We have one common special case. We can't do any merging if
10136 the inner code is an ASHIFTRT of a smaller mode. However, if
10137 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10138 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10139 we can convert it to
10140 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10141 This simplifies certain SIGN_EXTEND operations. */
10142 if (code == ASHIFT && first_code == ASHIFTRT
10143 && count == (GET_MODE_PRECISION (result_mode)
10144 - GET_MODE_PRECISION (GET_MODE (varop))))
10146 /* C3 has the low-order C1 bits zero. */
10148 mask = GET_MODE_MASK (mode)
10149 & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10151 varop = simplify_and_const_int (NULL_RTX, result_mode,
10152 XEXP (varop, 0), mask);
10153 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10155 count = first_count;
10160 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10161 than C1 high-order bits equal to the sign bit, we can convert
10162 this to either an ASHIFT or an ASHIFTRT depending on the
10165 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10167 if (code == ASHIFTRT && first_code == ASHIFT
10168 && GET_MODE (varop) == shift_mode
10169 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10172 varop = XEXP (varop, 0);
10173 count -= first_count;
10183 /* There are some cases we can't do. If CODE is ASHIFTRT,
10184 we can only do this if FIRST_CODE is also ASHIFTRT.
10186 We can't do the case when CODE is ROTATE and FIRST_CODE is
10189 If the mode of this shift is not the mode of the outer shift,
10190 we can't do this if either shift is a right shift or ROTATE.
10192 Finally, we can't do any of these if the mode is too wide
10193 unless the codes are the same.
10195 Handle the case where the shift codes are the same
10198 if (code == first_code)
10200 if (GET_MODE (varop) != result_mode
10201 && (code == ASHIFTRT || code == LSHIFTRT
10202 || code == ROTATE))
10205 count += first_count;
10206 varop = XEXP (varop, 0);
10210 if (code == ASHIFTRT
10211 || (code == ROTATE && first_code == ASHIFTRT)
10212 || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10213 || (GET_MODE (varop) != result_mode
10214 && (first_code == ASHIFTRT || first_code == LSHIFTRT
10215 || first_code == ROTATE
10216 || code == ROTATE)))
10219 /* To compute the mask to apply after the shift, shift the
10220 nonzero bits of the inner shift the same way the
10221 outer shift will. */
10223 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10226 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10229 /* Give up if we can't compute an outer operation to use. */
10231 || !CONST_INT_P (mask_rtx)
10232 || ! merge_outer_ops (&outer_op, &outer_const, AND,
10234 result_mode, &complement_p))
10237 /* If the shifts are in the same direction, we add the
10238 counts. Otherwise, we subtract them. */
10239 if ((code == ASHIFTRT || code == LSHIFTRT)
10240 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10241 count += first_count;
10243 count -= first_count;
10245 /* If COUNT is positive, the new shift is usually CODE,
10246 except for the two exceptions below, in which case it is
10247 FIRST_CODE. If the count is negative, FIRST_CODE should
10250 && ((first_code == ROTATE && code == ASHIFT)
10251 || (first_code == ASHIFTRT && code == LSHIFTRT)))
10253 else if (count < 0)
10254 code = first_code, count = -count;
10256 varop = XEXP (varop, 0);
10260 /* If we have (A << B << C) for any shift, we can convert this to
10261 (A << C << B). This wins if A is a constant. Only try this if
10262 B is not a constant. */
10264 else if (GET_CODE (varop) == code
10265 && CONST_INT_P (XEXP (varop, 0))
10266 && !CONST_INT_P (XEXP (varop, 1)))
10268 rtx new_rtx = simplify_const_binary_operation (code, mode,
10271 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10278 if (VECTOR_MODE_P (mode))
10281 /* Make this fit the case below. */
10282 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10283 GEN_INT (GET_MODE_MASK (mode)));
10289 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10290 with C the size of VAROP - 1 and the shift is logical if
10291 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10292 we have an (le X 0) operation. If we have an arithmetic shift
10293 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10294 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10296 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10297 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10298 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10299 && (code == LSHIFTRT || code == ASHIFTRT)
10300 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10301 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10304 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10307 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10308 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10313 /* If we have (shift (logical)), move the logical to the outside
10314 to allow it to possibly combine with another logical and the
10315 shift to combine with another shift. This also canonicalizes to
10316 what a ZERO_EXTRACT looks like. Also, some machines have
10317 (and (shift)) insns. */
10319 if (CONST_INT_P (XEXP (varop, 1))
10320 /* We can't do this if we have (ashiftrt (xor)) and the
10321 constant has its sign bit set in shift_mode. */
10322 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10323 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10325 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10327 GEN_INT (count))) != 0
10328 && CONST_INT_P (new_rtx)
10329 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10330 INTVAL (new_rtx), result_mode, &complement_p))
10332 varop = XEXP (varop, 0);
10336 /* If we can't do that, try to simplify the shift in each arm of the
10337 logical expression, make a new logical expression, and apply
10338 the inverse distributive law. This also can't be done
10339 for some (ashiftrt (xor)). */
10340 if (CONST_INT_P (XEXP (varop, 1))
10341 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10342 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10345 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10346 XEXP (varop, 0), count);
10347 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10348 XEXP (varop, 1), count);
10350 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10352 varop = apply_distributive_law (varop);
10360 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10361 says that the sign bit can be tested, FOO has mode MODE, C is
10362 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10363 that may be nonzero. */
10364 if (code == LSHIFTRT
10365 && XEXP (varop, 1) == const0_rtx
10366 && GET_MODE (XEXP (varop, 0)) == result_mode
10367 && count == (GET_MODE_PRECISION (result_mode) - 1)
10368 && HWI_COMPUTABLE_MODE_P (result_mode)
10369 && STORE_FLAG_VALUE == -1
10370 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10371 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10374 varop = XEXP (varop, 0);
10381 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10382 than the number of bits in the mode is equivalent to A. */
10383 if (code == LSHIFTRT
10384 && count == (GET_MODE_PRECISION (result_mode) - 1)
10385 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10387 varop = XEXP (varop, 0);
10392 /* NEG commutes with ASHIFT since it is multiplication. Move the
10393 NEG outside to allow shifts to combine. */
10395 && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10398 varop = XEXP (varop, 0);
10404 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10405 is one less than the number of bits in the mode is
10406 equivalent to (xor A 1). */
10407 if (code == LSHIFTRT
10408 && count == (GET_MODE_PRECISION (result_mode) - 1)
10409 && XEXP (varop, 1) == constm1_rtx
10410 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10411 && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10415 varop = XEXP (varop, 0);
10419 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10420 that might be nonzero in BAR are those being shifted out and those
10421 bits are known zero in FOO, we can replace the PLUS with FOO.
10422 Similarly in the other operand order. This code occurs when
10423 we are computing the size of a variable-size array. */
10425 if ((code == ASHIFTRT || code == LSHIFTRT)
10426 && count < HOST_BITS_PER_WIDE_INT
10427 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10428 && (nonzero_bits (XEXP (varop, 1), result_mode)
10429 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10431 varop = XEXP (varop, 0);
10434 else if ((code == ASHIFTRT || code == LSHIFTRT)
10435 && count < HOST_BITS_PER_WIDE_INT
10436 && HWI_COMPUTABLE_MODE_P (result_mode)
10437 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10439 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10440 & nonzero_bits (XEXP (varop, 1),
10443 varop = XEXP (varop, 1);
10447 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10449 && CONST_INT_P (XEXP (varop, 1))
10450 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10452 GEN_INT (count))) != 0
10453 && CONST_INT_P (new_rtx)
10454 && merge_outer_ops (&outer_op, &outer_const, PLUS,
10455 INTVAL (new_rtx), result_mode, &complement_p))
10457 varop = XEXP (varop, 0);
10461 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10462 signbit', and attempt to change the PLUS to an XOR and move it to
10463 the outer operation as is done above in the AND/IOR/XOR case
10464 leg for shift(logical). See details in logical handling above
10465 for reasoning in doing so. */
10466 if (code == LSHIFTRT
10467 && CONST_INT_P (XEXP (varop, 1))
10468 && mode_signbit_p (result_mode, XEXP (varop, 1))
10469 && (new_rtx = simplify_const_binary_operation (code, result_mode,
10471 GEN_INT (count))) != 0
10472 && CONST_INT_P (new_rtx)
10473 && merge_outer_ops (&outer_op, &outer_const, XOR,
10474 INTVAL (new_rtx), result_mode, &complement_p))
10476 varop = XEXP (varop, 0);
10483 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10484 with C the size of VAROP - 1 and the shift is logical if
10485 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10486 we have a (gt X 0) operation. If the shift is arithmetic with
10487 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10488 we have a (neg (gt X 0)) operation. */
10490 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10491 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10492 && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10493 && (code == LSHIFTRT || code == ASHIFTRT)
10494 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10495 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10496 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10499 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10502 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10503 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10510 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10511 if the truncate does not affect the value. */
10512 if (code == LSHIFTRT
10513 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10514 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10515 && (INTVAL (XEXP (XEXP (varop, 0), 1))
10516 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10517 - GET_MODE_PRECISION (GET_MODE (varop)))))
10519 rtx varop_inner = XEXP (varop, 0);
10522 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10523 XEXP (varop_inner, 0),
10525 (count + INTVAL (XEXP (varop_inner, 1))));
10526 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10539 shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10540 outer_op, outer_const);
10542 /* We have now finished analyzing the shift. The result should be
10543 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10544 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10545 to the result of the shift. OUTER_CONST is the relevant constant,
10546 but we must turn off all bits turned off in the shift. */
10548 if (outer_op == UNKNOWN
10549 && orig_code == code && orig_count == count
10550 && varop == orig_varop
10551 && shift_mode == GET_MODE (varop))
10554 /* Make a SUBREG if necessary. If we can't make it, fail. */
10555 varop = gen_lowpart (shift_mode, varop);
10556 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10559 /* If we have an outer operation and we just made a shift, it is
10560 possible that we could have simplified the shift were it not
10561 for the outer operation. So try to do the simplification
10564 if (outer_op != UNKNOWN)
10565 x = simplify_shift_const_1 (code, shift_mode, varop, count);
10570 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10572 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10573 turn off all the bits that the shift would have turned off. */
10574 if (orig_code == LSHIFTRT && result_mode != shift_mode)
10575 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10576 GET_MODE_MASK (result_mode) >> orig_count);
10578 /* Do the remainder of the processing in RESULT_MODE. */
10579 x = gen_lowpart_or_truncate (result_mode, x);
10581 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10584 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10586 if (outer_op != UNKNOWN)
10588 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10589 && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10590 outer_const = trunc_int_for_mode (outer_const, result_mode);
10592 if (outer_op == AND)
10593 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10594 else if (outer_op == SET)
10596 /* This means that we have determined that the result is
10597 equivalent to a constant. This should be rare. */
10598 if (!side_effects_p (x))
10599 x = GEN_INT (outer_const);
10601 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10602 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10604 x = simplify_gen_binary (outer_op, result_mode, x,
10605 GEN_INT (outer_const));
10611 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10612 The result of the shift is RESULT_MODE. If we cannot simplify it,
10613 return X or, if it is NULL, synthesize the expression with
10614 simplify_gen_binary. Otherwise, return a simplified value.
10616 The shift is normally computed in the widest mode we find in VAROP, as
10617 long as it isn't a different number of words than RESULT_MODE. Exceptions
10618 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10621 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10622 rtx varop, int count)
10624 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10629 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10630 if (GET_MODE (x) != result_mode)
10631 x = gen_lowpart (result_mode, x);
10636 /* Like recog, but we receive the address of a pointer to a new pattern.
10637 We try to match the rtx that the pointer points to.
10638 If that fails, we may try to modify or replace the pattern,
10639 storing the replacement into the same pointer object.
10641 Modifications include deletion or addition of CLOBBERs.
10643 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10644 the CLOBBERs are placed.
10646 The value is the final insn code from the pattern ultimately matched,
10650 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10652 rtx pat = *pnewpat;
10653 int insn_code_number;
10654 int num_clobbers_to_add = 0;
10657 rtx old_notes, old_pat;
10659 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10660 we use to indicate that something didn't match. If we find such a
10661 thing, force rejection. */
10662 if (GET_CODE (pat) == PARALLEL)
10663 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10664 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10665 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10668 old_pat = PATTERN (insn);
10669 old_notes = REG_NOTES (insn);
10670 PATTERN (insn) = pat;
10671 REG_NOTES (insn) = 0;
10673 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10674 if (dump_file && (dump_flags & TDF_DETAILS))
10676 if (insn_code_number < 0)
10677 fputs ("Failed to match this instruction:\n", dump_file);
10679 fputs ("Successfully matched this instruction:\n", dump_file);
10680 print_rtl_single (dump_file, pat);
10683 /* If it isn't, there is the possibility that we previously had an insn
10684 that clobbered some register as a side effect, but the combined
10685 insn doesn't need to do that. So try once more without the clobbers
10686 unless this represents an ASM insn. */
10688 if (insn_code_number < 0 && ! check_asm_operands (pat)
10689 && GET_CODE (pat) == PARALLEL)
10693 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10694 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10697 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10701 SUBST_INT (XVECLEN (pat, 0), pos);
10704 pat = XVECEXP (pat, 0, 0);
10706 PATTERN (insn) = pat;
10707 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10708 if (dump_file && (dump_flags & TDF_DETAILS))
10710 if (insn_code_number < 0)
10711 fputs ("Failed to match this instruction:\n", dump_file);
10713 fputs ("Successfully matched this instruction:\n", dump_file);
10714 print_rtl_single (dump_file, pat);
10717 PATTERN (insn) = old_pat;
10718 REG_NOTES (insn) = old_notes;
10720 /* Recognize all noop sets, these will be killed by followup pass. */
10721 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10722 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10724 /* If we had any clobbers to add, make a new pattern than contains
10725 them. Then check to make sure that all of them are dead. */
10726 if (num_clobbers_to_add)
10728 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10729 rtvec_alloc (GET_CODE (pat) == PARALLEL
10730 ? (XVECLEN (pat, 0)
10731 + num_clobbers_to_add)
10732 : num_clobbers_to_add + 1));
10734 if (GET_CODE (pat) == PARALLEL)
10735 for (i = 0; i < XVECLEN (pat, 0); i++)
10736 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10738 XVECEXP (newpat, 0, 0) = pat;
10740 add_clobbers (newpat, insn_code_number);
10742 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10743 i < XVECLEN (newpat, 0); i++)
10745 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10746 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10748 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10750 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10751 notes = alloc_reg_note (REG_UNUSED,
10752 XEXP (XVECEXP (newpat, 0, i), 0), notes);
10761 return insn_code_number;
10764 /* Like gen_lowpart_general but for use by combine. In combine it
10765 is not possible to create any new pseudoregs. However, it is
10766 safe to create invalid memory addresses, because combine will
10767 try to recognize them and all they will do is make the combine
10770 If for some reason this cannot do its job, an rtx
10771 (clobber (const_int 0)) is returned.
10772 An insn containing that will not be recognized. */
10775 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10777 enum machine_mode imode = GET_MODE (x);
10778 unsigned int osize = GET_MODE_SIZE (omode);
10779 unsigned int isize = GET_MODE_SIZE (imode);
10782 if (omode == imode)
10785 /* Return identity if this is a CONST or symbolic reference. */
10787 && (GET_CODE (x) == CONST
10788 || GET_CODE (x) == SYMBOL_REF
10789 || GET_CODE (x) == LABEL_REF))
10792 /* We can only support MODE being wider than a word if X is a
10793 constant integer or has a mode the same size. */
10794 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10795 && ! ((imode == VOIDmode
10796 && (CONST_INT_P (x)
10797 || GET_CODE (x) == CONST_DOUBLE))
10798 || isize == osize))
10801 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10802 won't know what to do. So we will strip off the SUBREG here and
10803 process normally. */
10804 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10806 x = SUBREG_REG (x);
10808 /* For use in case we fall down into the address adjustments
10809 further below, we need to adjust the known mode and size of
10810 x; imode and isize, since we just adjusted x. */
10811 imode = GET_MODE (x);
10813 if (imode == omode)
10816 isize = GET_MODE_SIZE (imode);
10819 result = gen_lowpart_common (omode, x);
10828 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10830 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10833 /* If we want to refer to something bigger than the original memref,
10834 generate a paradoxical subreg instead. That will force a reload
10835 of the original memref X. */
10837 return gen_rtx_SUBREG (omode, x, 0);
10839 if (WORDS_BIG_ENDIAN)
10840 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10842 /* Adjust the address so that the address-after-the-data is
10844 if (BYTES_BIG_ENDIAN)
10845 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10847 return adjust_address_nv (x, omode, offset);
10850 /* If X is a comparison operator, rewrite it in a new mode. This
10851 probably won't match, but may allow further simplifications. */
10852 else if (COMPARISON_P (x))
10853 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10855 /* If we couldn't simplify X any other way, just enclose it in a
10856 SUBREG. Normally, this SUBREG won't match, but some patterns may
10857 include an explicit SUBREG or we may simplify it further in combine. */
10863 offset = subreg_lowpart_offset (omode, imode);
10864 if (imode == VOIDmode)
10866 imode = int_mode_for_mode (omode);
10867 x = gen_lowpart_common (imode, x);
10871 res = simplify_gen_subreg (omode, x, imode, offset);
10877 return gen_rtx_CLOBBER (omode, const0_rtx);
10880 /* Try to simplify a comparison between OP0 and a constant OP1,
10881 where CODE is the comparison code that will be tested, into a
10882 (CODE OP0 const0_rtx) form.
10884 The result is a possibly different comparison code to use.
10885 *POP1 may be updated. */
10887 static enum rtx_code
10888 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10890 enum machine_mode mode = GET_MODE (op0);
10891 unsigned int mode_width = GET_MODE_PRECISION (mode);
10892 HOST_WIDE_INT const_op = INTVAL (*pop1);
10894 /* Get the constant we are comparing against and turn off all bits
10895 not on in our mode. */
10896 if (mode != VOIDmode)
10897 const_op = trunc_int_for_mode (const_op, mode);
10899 /* If we are comparing against a constant power of two and the value
10900 being compared can only have that single bit nonzero (e.g., it was
10901 `and'ed with that bit), we can replace this with a comparison
10904 && (code == EQ || code == NE || code == GE || code == GEU
10905 || code == LT || code == LTU)
10906 && mode_width <= HOST_BITS_PER_WIDE_INT
10907 && exact_log2 (const_op) >= 0
10908 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10910 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10914 /* Similarly, if we are comparing a value known to be either -1 or
10915 0 with -1, change it to the opposite comparison against zero. */
10917 && (code == EQ || code == NE || code == GT || code == LE
10918 || code == GEU || code == LTU)
10919 && num_sign_bit_copies (op0, mode) == mode_width)
10921 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10925 /* Do some canonicalizations based on the comparison code. We prefer
10926 comparisons against zero and then prefer equality comparisons.
10927 If we can reduce the size of a constant, we will do that too. */
10931 /* < C is equivalent to <= (C - 1) */
10936 /* ... fall through to LE case below. */
10942 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10949 /* If we are doing a <= 0 comparison on a value known to have
10950 a zero sign bit, we can replace this with == 0. */
10951 else if (const_op == 0
10952 && mode_width <= HOST_BITS_PER_WIDE_INT
10953 && (nonzero_bits (op0, mode)
10954 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10960 /* >= C is equivalent to > (C - 1). */
10965 /* ... fall through to GT below. */
10971 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10978 /* If we are doing a > 0 comparison on a value known to have
10979 a zero sign bit, we can replace this with != 0. */
10980 else if (const_op == 0
10981 && mode_width <= HOST_BITS_PER_WIDE_INT
10982 && (nonzero_bits (op0, mode)
10983 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10989 /* < C is equivalent to <= (C - 1). */
10994 /* ... fall through ... */
10996 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10997 else if (mode_width <= HOST_BITS_PER_WIDE_INT
10998 && (unsigned HOST_WIDE_INT) const_op
10999 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11009 /* unsigned <= 0 is equivalent to == 0 */
11012 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11013 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11014 && (unsigned HOST_WIDE_INT) const_op
11015 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11023 /* >= C is equivalent to > (C - 1). */
11028 /* ... fall through ... */
11031 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11032 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11033 && (unsigned HOST_WIDE_INT) const_op
11034 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11044 /* unsigned > 0 is equivalent to != 0 */
11047 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11048 else if (mode_width <= HOST_BITS_PER_WIDE_INT
11049 && (unsigned HOST_WIDE_INT) const_op
11050 == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11061 *pop1 = GEN_INT (const_op);
11065 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11066 comparison code that will be tested.
11068 The result is a possibly different comparison code to use. *POP0 and
11069 *POP1 may be updated.
11071 It is possible that we might detect that a comparison is either always
11072 true or always false. However, we do not perform general constant
11073 folding in combine, so this knowledge isn't useful. Such tautologies
11074 should have been detected earlier. Hence we ignore all such cases. */
11076 static enum rtx_code
11077 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11083 enum machine_mode mode, tmode;
11085 /* Try a few ways of applying the same transformation to both operands. */
11088 #ifndef WORD_REGISTER_OPERATIONS
11089 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11090 so check specially. */
11091 if (code != GTU && code != GEU && code != LTU && code != LEU
11092 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11093 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11094 && GET_CODE (XEXP (op1, 0)) == ASHIFT
11095 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11096 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11097 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11098 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11099 && CONST_INT_P (XEXP (op0, 1))
11100 && XEXP (op0, 1) == XEXP (op1, 1)
11101 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11102 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11103 && (INTVAL (XEXP (op0, 1))
11104 == (GET_MODE_PRECISION (GET_MODE (op0))
11105 - (GET_MODE_PRECISION
11106 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11108 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11109 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11113 /* If both operands are the same constant shift, see if we can ignore the
11114 shift. We can if the shift is a rotate or if the bits shifted out of
11115 this shift are known to be zero for both inputs and if the type of
11116 comparison is compatible with the shift. */
11117 if (GET_CODE (op0) == GET_CODE (op1)
11118 && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11119 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11120 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11121 && (code != GT && code != LT && code != GE && code != LE))
11122 || (GET_CODE (op0) == ASHIFTRT
11123 && (code != GTU && code != LTU
11124 && code != GEU && code != LEU)))
11125 && CONST_INT_P (XEXP (op0, 1))
11126 && INTVAL (XEXP (op0, 1)) >= 0
11127 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11128 && XEXP (op0, 1) == XEXP (op1, 1))
11130 enum machine_mode mode = GET_MODE (op0);
11131 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11132 int shift_count = INTVAL (XEXP (op0, 1));
11134 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11135 mask &= (mask >> shift_count) << shift_count;
11136 else if (GET_CODE (op0) == ASHIFT)
11137 mask = (mask & (mask << shift_count)) >> shift_count;
11139 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11140 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11141 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11146 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11147 SUBREGs are of the same mode, and, in both cases, the AND would
11148 be redundant if the comparison was done in the narrower mode,
11149 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11150 and the operand's possibly nonzero bits are 0xffffff01; in that case
11151 if we only care about QImode, we don't need the AND). This case
11152 occurs if the output mode of an scc insn is not SImode and
11153 STORE_FLAG_VALUE == 1 (e.g., the 386).
11155 Similarly, check for a case where the AND's are ZERO_EXTEND
11156 operations from some narrower mode even though a SUBREG is not
11159 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11160 && CONST_INT_P (XEXP (op0, 1))
11161 && CONST_INT_P (XEXP (op1, 1)))
11163 rtx inner_op0 = XEXP (op0, 0);
11164 rtx inner_op1 = XEXP (op1, 0);
11165 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11166 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11169 if (paradoxical_subreg_p (inner_op0)
11170 && GET_CODE (inner_op1) == SUBREG
11171 && (GET_MODE (SUBREG_REG (inner_op0))
11172 == GET_MODE (SUBREG_REG (inner_op1)))
11173 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11174 <= HOST_BITS_PER_WIDE_INT)
11175 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11176 GET_MODE (SUBREG_REG (inner_op0)))))
11177 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11178 GET_MODE (SUBREG_REG (inner_op1))))))
11180 op0 = SUBREG_REG (inner_op0);
11181 op1 = SUBREG_REG (inner_op1);
11183 /* The resulting comparison is always unsigned since we masked
11184 off the original sign bit. */
11185 code = unsigned_condition (code);
11191 for (tmode = GET_CLASS_NARROWEST_MODE
11192 (GET_MODE_CLASS (GET_MODE (op0)));
11193 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11194 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11196 op0 = gen_lowpart (tmode, inner_op0);
11197 op1 = gen_lowpart (tmode, inner_op1);
11198 code = unsigned_condition (code);
11207 /* If both operands are NOT, we can strip off the outer operation
11208 and adjust the comparison code for swapped operands; similarly for
11209 NEG, except that this must be an equality comparison. */
11210 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11211 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11212 && (code == EQ || code == NE)))
11213 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11219 /* If the first operand is a constant, swap the operands and adjust the
11220 comparison code appropriately, but don't do this if the second operand
11221 is already a constant integer. */
11222 if (swap_commutative_operands_p (op0, op1))
11224 tem = op0, op0 = op1, op1 = tem;
11225 code = swap_condition (code);
11228 /* We now enter a loop during which we will try to simplify the comparison.
11229 For the most part, we only are concerned with comparisons with zero,
11230 but some things may really be comparisons with zero but not start
11231 out looking that way. */
11233 while (CONST_INT_P (op1))
11235 enum machine_mode mode = GET_MODE (op0);
11236 unsigned int mode_width = GET_MODE_PRECISION (mode);
11237 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11238 int equality_comparison_p;
11239 int sign_bit_comparison_p;
11240 int unsigned_comparison_p;
11241 HOST_WIDE_INT const_op;
11243 /* We only want to handle integral modes. This catches VOIDmode,
11244 CCmode, and the floating-point modes. An exception is that we
11245 can handle VOIDmode if OP0 is a COMPARE or a comparison
11248 if (GET_MODE_CLASS (mode) != MODE_INT
11249 && ! (mode == VOIDmode
11250 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11253 /* Try to simplify the compare to constant, possibly changing the
11254 comparison op, and/or changing op1 to zero. */
11255 code = simplify_compare_const (code, op0, &op1);
11256 const_op = INTVAL (op1);
11258 /* Compute some predicates to simplify code below. */
11260 equality_comparison_p = (code == EQ || code == NE);
11261 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11262 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11265 /* If this is a sign bit comparison and we can do arithmetic in
11266 MODE, say that we will only be needing the sign bit of OP0. */
11267 if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11268 op0 = force_to_mode (op0, mode,
11269 (unsigned HOST_WIDE_INT) 1
11270 << (GET_MODE_PRECISION (mode) - 1),
11273 /* Now try cases based on the opcode of OP0. If none of the cases
11274 does a "continue", we exit this loop immediately after the
11277 switch (GET_CODE (op0))
11280 /* If we are extracting a single bit from a variable position in
11281 a constant that has only a single bit set and are comparing it
11282 with zero, we can convert this into an equality comparison
11283 between the position and the location of the single bit. */
11284 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11285 have already reduced the shift count modulo the word size. */
11286 if (!SHIFT_COUNT_TRUNCATED
11287 && CONST_INT_P (XEXP (op0, 0))
11288 && XEXP (op0, 1) == const1_rtx
11289 && equality_comparison_p && const_op == 0
11290 && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11292 if (BITS_BIG_ENDIAN)
11294 enum machine_mode new_mode
11295 = mode_for_extraction (EP_extzv, 1);
11296 if (new_mode == MAX_MACHINE_MODE)
11297 i = BITS_PER_WORD - 1 - i;
11301 i = (GET_MODE_PRECISION (mode) - 1 - i);
11305 op0 = XEXP (op0, 2);
11309 /* Result is nonzero iff shift count is equal to I. */
11310 code = reverse_condition (code);
11314 /* ... fall through ... */
11317 tem = expand_compound_operation (op0);
11326 /* If testing for equality, we can take the NOT of the constant. */
11327 if (equality_comparison_p
11328 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11330 op0 = XEXP (op0, 0);
11335 /* If just looking at the sign bit, reverse the sense of the
11337 if (sign_bit_comparison_p)
11339 op0 = XEXP (op0, 0);
11340 code = (code == GE ? LT : GE);
11346 /* If testing for equality, we can take the NEG of the constant. */
11347 if (equality_comparison_p
11348 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11350 op0 = XEXP (op0, 0);
11355 /* The remaining cases only apply to comparisons with zero. */
11359 /* When X is ABS or is known positive,
11360 (neg X) is < 0 if and only if X != 0. */
11362 if (sign_bit_comparison_p
11363 && (GET_CODE (XEXP (op0, 0)) == ABS
11364 || (mode_width <= HOST_BITS_PER_WIDE_INT
11365 && (nonzero_bits (XEXP (op0, 0), mode)
11366 & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11369 op0 = XEXP (op0, 0);
11370 code = (code == LT ? NE : EQ);
11374 /* If we have NEG of something whose two high-order bits are the
11375 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11376 if (num_sign_bit_copies (op0, mode) >= 2)
11378 op0 = XEXP (op0, 0);
11379 code = swap_condition (code);
11385 /* If we are testing equality and our count is a constant, we
11386 can perform the inverse operation on our RHS. */
11387 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11388 && (tem = simplify_binary_operation (ROTATERT, mode,
11389 op1, XEXP (op0, 1))) != 0)
11391 op0 = XEXP (op0, 0);
11396 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11397 a particular bit. Convert it to an AND of a constant of that
11398 bit. This will be converted into a ZERO_EXTRACT. */
11399 if (const_op == 0 && sign_bit_comparison_p
11400 && CONST_INT_P (XEXP (op0, 1))
11401 && mode_width <= HOST_BITS_PER_WIDE_INT)
11403 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11404 ((unsigned HOST_WIDE_INT) 1
11406 - INTVAL (XEXP (op0, 1)))));
11407 code = (code == LT ? NE : EQ);
11411 /* Fall through. */
11414 /* ABS is ignorable inside an equality comparison with zero. */
11415 if (const_op == 0 && equality_comparison_p)
11417 op0 = XEXP (op0, 0);
11423 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11424 (compare FOO CONST) if CONST fits in FOO's mode and we
11425 are either testing inequality or have an unsigned
11426 comparison with ZERO_EXTEND or a signed comparison with
11427 SIGN_EXTEND. But don't do it if we don't have a compare
11428 insn of the given mode, since we'd have to revert it
11429 later on, and then we wouldn't know whether to sign- or
11431 mode = GET_MODE (XEXP (op0, 0));
11432 if (GET_MODE_CLASS (mode) == MODE_INT
11433 && ! unsigned_comparison_p
11434 && HWI_COMPUTABLE_MODE_P (mode)
11435 && trunc_int_for_mode (const_op, mode) == const_op
11436 && have_insn_for (COMPARE, mode))
11438 op0 = XEXP (op0, 0);
11444 /* Check for the case where we are comparing A - C1 with C2, that is
11446 (subreg:MODE (plus (A) (-C1))) op (C2)
11448 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11449 comparison in the wider mode. One of the following two conditions
11450 must be true in order for this to be valid:
11452 1. The mode extension results in the same bit pattern being added
11453 on both sides and the comparison is equality or unsigned. As
11454 C2 has been truncated to fit in MODE, the pattern can only be
11457 2. The mode extension results in the sign bit being copied on
11460 The difficulty here is that we have predicates for A but not for
11461 (A - C1) so we need to check that C1 is within proper bounds so
11462 as to perturbate A as little as possible. */
11464 if (mode_width <= HOST_BITS_PER_WIDE_INT
11465 && subreg_lowpart_p (op0)
11466 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11467 && GET_CODE (SUBREG_REG (op0)) == PLUS
11468 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11470 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11471 rtx a = XEXP (SUBREG_REG (op0), 0);
11472 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11475 && (unsigned HOST_WIDE_INT) c1
11476 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11477 && (equality_comparison_p || unsigned_comparison_p)
11478 /* (A - C1) zero-extends if it is positive and sign-extends
11479 if it is negative, C2 both zero- and sign-extends. */
11480 && ((0 == (nonzero_bits (a, inner_mode)
11481 & ~GET_MODE_MASK (mode))
11483 /* (A - C1) sign-extends if it is positive and 1-extends
11484 if it is negative, C2 both sign- and 1-extends. */
11485 || (num_sign_bit_copies (a, inner_mode)
11486 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11489 || ((unsigned HOST_WIDE_INT) c1
11490 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11491 /* (A - C1) always sign-extends, like C2. */
11492 && num_sign_bit_copies (a, inner_mode)
11493 > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11494 - (mode_width - 1))))
11496 op0 = SUBREG_REG (op0);
11501 /* If the inner mode is narrower and we are extracting the low part,
11502 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11503 if (subreg_lowpart_p (op0)
11504 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11505 /* Fall through */ ;
11509 /* ... fall through ... */
11512 mode = GET_MODE (XEXP (op0, 0));
11513 if (GET_MODE_CLASS (mode) == MODE_INT
11514 && (unsigned_comparison_p || equality_comparison_p)
11515 && HWI_COMPUTABLE_MODE_P (mode)
11516 && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11518 && have_insn_for (COMPARE, mode))
11520 op0 = XEXP (op0, 0);
11526 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11527 this for equality comparisons due to pathological cases involving
11529 if (equality_comparison_p
11530 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11531 op1, XEXP (op0, 1))))
11533 op0 = XEXP (op0, 0);
11538 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11539 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11540 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11542 op0 = XEXP (XEXP (op0, 0), 0);
11543 code = (code == LT ? EQ : NE);
11549 /* We used to optimize signed comparisons against zero, but that
11550 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11551 arrive here as equality comparisons, or (GEU, LTU) are
11552 optimized away. No need to special-case them. */
11554 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11555 (eq B (minus A C)), whichever simplifies. We can only do
11556 this for equality comparisons due to pathological cases involving
11558 if (equality_comparison_p
11559 && 0 != (tem = simplify_binary_operation (PLUS, mode,
11560 XEXP (op0, 1), op1)))
11562 op0 = XEXP (op0, 0);
11567 if (equality_comparison_p
11568 && 0 != (tem = simplify_binary_operation (MINUS, mode,
11569 XEXP (op0, 0), op1)))
11571 op0 = XEXP (op0, 1);
11576 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11577 of bits in X minus 1, is one iff X > 0. */
11578 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11579 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11580 && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11581 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11583 op0 = XEXP (op0, 1);
11584 code = (code == GE ? LE : GT);
11590 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11591 if C is zero or B is a constant. */
11592 if (equality_comparison_p
11593 && 0 != (tem = simplify_binary_operation (XOR, mode,
11594 XEXP (op0, 1), op1)))
11596 op0 = XEXP (op0, 0);
11603 case UNEQ: case LTGT:
11604 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
11605 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
11606 case UNORDERED: case ORDERED:
11607 /* We can't do anything if OP0 is a condition code value, rather
11608 than an actual data value. */
11610 || CC0_P (XEXP (op0, 0))
11611 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11614 /* Get the two operands being compared. */
11615 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11616 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11618 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11620 /* Check for the cases where we simply want the result of the
11621 earlier test or the opposite of that result. */
11622 if (code == NE || code == EQ
11623 || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11624 && (code == LT || code == GE)))
11626 enum rtx_code new_code;
11627 if (code == LT || code == NE)
11628 new_code = GET_CODE (op0);
11630 new_code = reversed_comparison_code (op0, NULL);
11632 if (new_code != UNKNOWN)
11643 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11645 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11646 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11647 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11649 op0 = XEXP (op0, 1);
11650 code = (code == GE ? GT : LE);
11656 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11657 will be converted to a ZERO_EXTRACT later. */
11658 if (const_op == 0 && equality_comparison_p
11659 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11660 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11662 op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11663 XEXP (XEXP (op0, 0), 1));
11664 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11668 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11669 zero and X is a comparison and C1 and C2 describe only bits set
11670 in STORE_FLAG_VALUE, we can compare with X. */
11671 if (const_op == 0 && equality_comparison_p
11672 && mode_width <= HOST_BITS_PER_WIDE_INT
11673 && CONST_INT_P (XEXP (op0, 1))
11674 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11675 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11676 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11677 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11679 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11680 << INTVAL (XEXP (XEXP (op0, 0), 1)));
11681 if ((~STORE_FLAG_VALUE & mask) == 0
11682 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11683 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11684 && COMPARISON_P (tem))))
11686 op0 = XEXP (XEXP (op0, 0), 0);
11691 /* If we are doing an equality comparison of an AND of a bit equal
11692 to the sign bit, replace this with a LT or GE comparison of
11693 the underlying value. */
11694 if (equality_comparison_p
11696 && CONST_INT_P (XEXP (op0, 1))
11697 && mode_width <= HOST_BITS_PER_WIDE_INT
11698 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11699 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11701 op0 = XEXP (op0, 0);
11702 code = (code == EQ ? GE : LT);
11706 /* If this AND operation is really a ZERO_EXTEND from a narrower
11707 mode, the constant fits within that mode, and this is either an
11708 equality or unsigned comparison, try to do this comparison in
11713 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11714 -> (ne:DI (reg:SI 4) (const_int 0))
11716 unless TRULY_NOOP_TRUNCATION allows it or the register is
11717 known to hold a value of the required mode the
11718 transformation is invalid. */
11719 if ((equality_comparison_p || unsigned_comparison_p)
11720 && CONST_INT_P (XEXP (op0, 1))
11721 && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11722 & GET_MODE_MASK (mode))
11724 && const_op >> i == 0
11725 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11726 && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11727 || (REG_P (XEXP (op0, 0))
11728 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11730 op0 = gen_lowpart (tmode, XEXP (op0, 0));
11734 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11735 fits in both M1 and M2 and the SUBREG is either paradoxical
11736 or represents the low part, permute the SUBREG and the AND
11738 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11740 unsigned HOST_WIDE_INT c1;
11741 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11742 /* Require an integral mode, to avoid creating something like
11744 if (SCALAR_INT_MODE_P (tmode)
11745 /* It is unsafe to commute the AND into the SUBREG if the
11746 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11747 not defined. As originally written the upper bits
11748 have a defined value due to the AND operation.
11749 However, if we commute the AND inside the SUBREG then
11750 they no longer have defined values and the meaning of
11751 the code has been changed. */
11753 #ifdef WORD_REGISTER_OPERATIONS
11754 || (mode_width > GET_MODE_PRECISION (tmode)
11755 && mode_width <= BITS_PER_WORD)
11757 || (mode_width <= GET_MODE_PRECISION (tmode)
11758 && subreg_lowpart_p (XEXP (op0, 0))))
11759 && CONST_INT_P (XEXP (op0, 1))
11760 && mode_width <= HOST_BITS_PER_WIDE_INT
11761 && HWI_COMPUTABLE_MODE_P (tmode)
11762 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11763 && (c1 & ~GET_MODE_MASK (tmode)) == 0
11765 && c1 != GET_MODE_MASK (tmode))
11767 op0 = simplify_gen_binary (AND, tmode,
11768 SUBREG_REG (XEXP (op0, 0)),
11769 gen_int_mode (c1, tmode));
11770 op0 = gen_lowpart (mode, op0);
11775 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11776 if (const_op == 0 && equality_comparison_p
11777 && XEXP (op0, 1) == const1_rtx
11778 && GET_CODE (XEXP (op0, 0)) == NOT)
11780 op0 = simplify_and_const_int (NULL_RTX, mode,
11781 XEXP (XEXP (op0, 0), 0), 1);
11782 code = (code == NE ? EQ : NE);
11786 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11787 (eq (and (lshiftrt X) 1) 0).
11788 Also handle the case where (not X) is expressed using xor. */
11789 if (const_op == 0 && equality_comparison_p
11790 && XEXP (op0, 1) == const1_rtx
11791 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11793 rtx shift_op = XEXP (XEXP (op0, 0), 0);
11794 rtx shift_count = XEXP (XEXP (op0, 0), 1);
11796 if (GET_CODE (shift_op) == NOT
11797 || (GET_CODE (shift_op) == XOR
11798 && CONST_INT_P (XEXP (shift_op, 1))
11799 && CONST_INT_P (shift_count)
11800 && HWI_COMPUTABLE_MODE_P (mode)
11801 && (UINTVAL (XEXP (shift_op, 1))
11802 == (unsigned HOST_WIDE_INT) 1
11803 << INTVAL (shift_count))))
11806 = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11807 op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11808 code = (code == NE ? EQ : NE);
11815 /* If we have (compare (ashift FOO N) (const_int C)) and
11816 the high order N bits of FOO (N+1 if an inequality comparison)
11817 are known to be zero, we can do this by comparing FOO with C
11818 shifted right N bits so long as the low-order N bits of C are
11820 if (CONST_INT_P (XEXP (op0, 1))
11821 && INTVAL (XEXP (op0, 1)) >= 0
11822 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11823 < HOST_BITS_PER_WIDE_INT)
11824 && (((unsigned HOST_WIDE_INT) const_op
11825 & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11827 && mode_width <= HOST_BITS_PER_WIDE_INT
11828 && (nonzero_bits (XEXP (op0, 0), mode)
11829 & ~(mask >> (INTVAL (XEXP (op0, 1))
11830 + ! equality_comparison_p))) == 0)
11832 /* We must perform a logical shift, not an arithmetic one,
11833 as we want the top N bits of C to be zero. */
11834 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11836 temp >>= INTVAL (XEXP (op0, 1));
11837 op1 = gen_int_mode (temp, mode);
11838 op0 = XEXP (op0, 0);
11842 /* If we are doing a sign bit comparison, it means we are testing
11843 a particular bit. Convert it to the appropriate AND. */
11844 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11845 && mode_width <= HOST_BITS_PER_WIDE_INT)
11847 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11848 ((unsigned HOST_WIDE_INT) 1
11850 - INTVAL (XEXP (op0, 1)))));
11851 code = (code == LT ? NE : EQ);
11855 /* If this an equality comparison with zero and we are shifting
11856 the low bit to the sign bit, we can convert this to an AND of the
11858 if (const_op == 0 && equality_comparison_p
11859 && CONST_INT_P (XEXP (op0, 1))
11860 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11862 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11868 /* If this is an equality comparison with zero, we can do this
11869 as a logical shift, which might be much simpler. */
11870 if (equality_comparison_p && const_op == 0
11871 && CONST_INT_P (XEXP (op0, 1)))
11873 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11875 INTVAL (XEXP (op0, 1)));
11879 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11880 do the comparison in a narrower mode. */
11881 if (! unsigned_comparison_p
11882 && CONST_INT_P (XEXP (op0, 1))
11883 && GET_CODE (XEXP (op0, 0)) == ASHIFT
11884 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11885 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11886 MODE_INT, 1)) != BLKmode
11887 && (((unsigned HOST_WIDE_INT) const_op
11888 + (GET_MODE_MASK (tmode) >> 1) + 1)
11889 <= GET_MODE_MASK (tmode)))
11891 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11895 /* Likewise if OP0 is a PLUS of a sign extension with a
11896 constant, which is usually represented with the PLUS
11897 between the shifts. */
11898 if (! unsigned_comparison_p
11899 && CONST_INT_P (XEXP (op0, 1))
11900 && GET_CODE (XEXP (op0, 0)) == PLUS
11901 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11902 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11903 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11904 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11905 MODE_INT, 1)) != BLKmode
11906 && (((unsigned HOST_WIDE_INT) const_op
11907 + (GET_MODE_MASK (tmode) >> 1) + 1)
11908 <= GET_MODE_MASK (tmode)))
11910 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11911 rtx add_const = XEXP (XEXP (op0, 0), 1);
11912 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11913 add_const, XEXP (op0, 1));
11915 op0 = simplify_gen_binary (PLUS, tmode,
11916 gen_lowpart (tmode, inner),
11921 /* ... fall through ... */
11923 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11924 the low order N bits of FOO are known to be zero, we can do this
11925 by comparing FOO with C shifted left N bits so long as no
11926 overflow occurs. Even if the low order N bits of FOO aren't known
11927 to be zero, if the comparison is >= or < we can use the same
11928 optimization and for > or <= by setting all the low
11929 order N bits in the comparison constant. */
11930 if (CONST_INT_P (XEXP (op0, 1))
11931 && INTVAL (XEXP (op0, 1)) > 0
11932 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11933 && mode_width <= HOST_BITS_PER_WIDE_INT
11934 && (((unsigned HOST_WIDE_INT) const_op
11935 + (GET_CODE (op0) != LSHIFTRT
11936 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11939 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11941 unsigned HOST_WIDE_INT low_bits
11942 = (nonzero_bits (XEXP (op0, 0), mode)
11943 & (((unsigned HOST_WIDE_INT) 1
11944 << INTVAL (XEXP (op0, 1))) - 1));
11945 if (low_bits == 0 || !equality_comparison_p)
11947 /* If the shift was logical, then we must make the condition
11949 if (GET_CODE (op0) == LSHIFTRT)
11950 code = unsigned_condition (code);
11952 const_op <<= INTVAL (XEXP (op0, 1));
11954 && (code == GT || code == GTU
11955 || code == LE || code == LEU))
11957 |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11958 op1 = GEN_INT (const_op);
11959 op0 = XEXP (op0, 0);
11964 /* If we are using this shift to extract just the sign bit, we
11965 can replace this with an LT or GE comparison. */
11967 && (equality_comparison_p || sign_bit_comparison_p)
11968 && CONST_INT_P (XEXP (op0, 1))
11969 && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11971 op0 = XEXP (op0, 0);
11972 code = (code == NE || code == GT ? LT : GE);
11984 /* Now make any compound operations involved in this comparison. Then,
11985 check for an outmost SUBREG on OP0 that is not doing anything or is
11986 paradoxical. The latter transformation must only be performed when
11987 it is known that the "extra" bits will be the same in op0 and op1 or
11988 that they don't matter. There are three cases to consider:
11990 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11991 care bits and we can assume they have any convenient value. So
11992 making the transformation is safe.
11994 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11995 In this case the upper bits of op0 are undefined. We should not make
11996 the simplification in that case as we do not know the contents of
11999 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12000 UNKNOWN. In that case we know those bits are zeros or ones. We must
12001 also be sure that they are the same as the upper bits of op1.
12003 We can never remove a SUBREG for a non-equality comparison because
12004 the sign bit is in a different place in the underlying object. */
12006 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
12007 op1 = make_compound_operation (op1, SET);
12009 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12010 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
12011 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
12012 && (code == NE || code == EQ))
12014 if (paradoxical_subreg_p (op0))
12016 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12018 if (REG_P (SUBREG_REG (op0)))
12020 op0 = SUBREG_REG (op0);
12021 op1 = gen_lowpart (GET_MODE (op0), op1);
12024 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12025 <= HOST_BITS_PER_WIDE_INT)
12026 && (nonzero_bits (SUBREG_REG (op0),
12027 GET_MODE (SUBREG_REG (op0)))
12028 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12030 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12032 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12033 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12034 op0 = SUBREG_REG (op0), op1 = tem;
12038 /* We now do the opposite procedure: Some machines don't have compare
12039 insns in all modes. If OP0's mode is an integer mode smaller than a
12040 word and we can't do a compare in that mode, see if there is a larger
12041 mode for which we can do the compare. There are a number of cases in
12042 which we can use the wider mode. */
12044 mode = GET_MODE (op0);
12045 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12046 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12047 && ! have_insn_for (COMPARE, mode))
12048 for (tmode = GET_MODE_WIDER_MODE (mode);
12049 (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12050 tmode = GET_MODE_WIDER_MODE (tmode))
12051 if (have_insn_for (COMPARE, tmode))
12055 /* If this is a test for negative, we can make an explicit
12056 test of the sign bit. Test this first so we can use
12057 a paradoxical subreg to extend OP0. */
12059 if (op1 == const0_rtx && (code == LT || code == GE)
12060 && HWI_COMPUTABLE_MODE_P (mode))
12062 op0 = simplify_gen_binary (AND, tmode,
12063 gen_lowpart (tmode, op0),
12064 GEN_INT ((unsigned HOST_WIDE_INT) 1
12065 << (GET_MODE_BITSIZE (mode)
12067 code = (code == LT) ? NE : EQ;
12071 /* If the only nonzero bits in OP0 and OP1 are those in the
12072 narrower mode and this is an equality or unsigned comparison,
12073 we can use the wider mode. Similarly for sign-extended
12074 values, in which case it is true for all comparisons. */
12075 zero_extended = ((code == EQ || code == NE
12076 || code == GEU || code == GTU
12077 || code == LEU || code == LTU)
12078 && (nonzero_bits (op0, tmode)
12079 & ~GET_MODE_MASK (mode)) == 0
12080 && ((CONST_INT_P (op1)
12081 || (nonzero_bits (op1, tmode)
12082 & ~GET_MODE_MASK (mode)) == 0)));
12085 || ((num_sign_bit_copies (op0, tmode)
12086 > (unsigned int) (GET_MODE_PRECISION (tmode)
12087 - GET_MODE_PRECISION (mode)))
12088 && (num_sign_bit_copies (op1, tmode)
12089 > (unsigned int) (GET_MODE_PRECISION (tmode)
12090 - GET_MODE_PRECISION (mode)))))
12092 /* If OP0 is an AND and we don't have an AND in MODE either,
12093 make a new AND in the proper mode. */
12094 if (GET_CODE (op0) == AND
12095 && !have_insn_for (AND, mode))
12096 op0 = simplify_gen_binary (AND, tmode,
12097 gen_lowpart (tmode,
12099 gen_lowpart (tmode,
12105 op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12106 op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12110 op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12111 op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12118 #ifdef CANONICALIZE_COMPARISON
12119 /* If this machine only supports a subset of valid comparisons, see if we
12120 can convert an unsupported one into a supported one. */
12121 CANONICALIZE_COMPARISON (code, op0, op1);
12130 /* Utility function for record_value_for_reg. Count number of
12135 enum rtx_code code = GET_CODE (x);
12139 if (GET_RTX_CLASS (code) == '2'
12140 || GET_RTX_CLASS (code) == 'c')
12142 rtx x0 = XEXP (x, 0);
12143 rtx x1 = XEXP (x, 1);
12146 return 1 + 2 * count_rtxs (x0);
12148 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12149 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12150 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12151 return 2 + 2 * count_rtxs (x0)
12152 + count_rtxs (x == XEXP (x1, 0)
12153 ? XEXP (x1, 1) : XEXP (x1, 0));
12155 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12156 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12157 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12158 return 2 + 2 * count_rtxs (x1)
12159 + count_rtxs (x == XEXP (x0, 0)
12160 ? XEXP (x0, 1) : XEXP (x0, 0));
12163 fmt = GET_RTX_FORMAT (code);
12164 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12166 ret += count_rtxs (XEXP (x, i));
12167 else if (fmt[i] == 'E')
12168 for (j = 0; j < XVECLEN (x, i); j++)
12169 ret += count_rtxs (XVECEXP (x, i, j));
12174 /* Utility function for following routine. Called when X is part of a value
12175 being stored into last_set_value. Sets last_set_table_tick
12176 for each register mentioned. Similar to mention_regs in cse.c */
12179 update_table_tick (rtx x)
12181 enum rtx_code code = GET_CODE (x);
12182 const char *fmt = GET_RTX_FORMAT (code);
12187 unsigned int regno = REGNO (x);
12188 unsigned int endregno = END_REGNO (x);
12191 for (r = regno; r < endregno; r++)
12193 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12194 rsp->last_set_table_tick = label_tick;
12200 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12203 /* Check for identical subexpressions. If x contains
12204 identical subexpression we only have to traverse one of
12206 if (i == 0 && ARITHMETIC_P (x))
12208 /* Note that at this point x1 has already been
12210 rtx x0 = XEXP (x, 0);
12211 rtx x1 = XEXP (x, 1);
12213 /* If x0 and x1 are identical then there is no need to
12218 /* If x0 is identical to a subexpression of x1 then while
12219 processing x1, x0 has already been processed. Thus we
12220 are done with x. */
12221 if (ARITHMETIC_P (x1)
12222 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12225 /* If x1 is identical to a subexpression of x0 then we
12226 still have to process the rest of x0. */
12227 if (ARITHMETIC_P (x0)
12228 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12230 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12235 update_table_tick (XEXP (x, i));
12237 else if (fmt[i] == 'E')
12238 for (j = 0; j < XVECLEN (x, i); j++)
12239 update_table_tick (XVECEXP (x, i, j));
12242 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12243 are saying that the register is clobbered and we no longer know its
12244 value. If INSN is zero, don't update reg_stat[].last_set; this is
12245 only permitted with VALUE also zero and is used to invalidate the
12249 record_value_for_reg (rtx reg, rtx insn, rtx value)
12251 unsigned int regno = REGNO (reg);
12252 unsigned int endregno = END_REGNO (reg);
12254 reg_stat_type *rsp;
12256 /* If VALUE contains REG and we have a previous value for REG, substitute
12257 the previous value. */
12258 if (value && insn && reg_overlap_mentioned_p (reg, value))
12262 /* Set things up so get_last_value is allowed to see anything set up to
12264 subst_low_luid = DF_INSN_LUID (insn);
12265 tem = get_last_value (reg);
12267 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12268 it isn't going to be useful and will take a lot of time to process,
12269 so just use the CLOBBER. */
12273 if (ARITHMETIC_P (tem)
12274 && GET_CODE (XEXP (tem, 0)) == CLOBBER
12275 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12276 tem = XEXP (tem, 0);
12277 else if (count_occurrences (value, reg, 1) >= 2)
12279 /* If there are two or more occurrences of REG in VALUE,
12280 prevent the value from growing too much. */
12281 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12282 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12285 value = replace_rtx (copy_rtx (value), reg, tem);
12289 /* For each register modified, show we don't know its value, that
12290 we don't know about its bitwise content, that its value has been
12291 updated, and that we don't know the location of the death of the
12293 for (i = regno; i < endregno; i++)
12295 rsp = VEC_index (reg_stat_type, reg_stat, i);
12298 rsp->last_set = insn;
12300 rsp->last_set_value = 0;
12301 rsp->last_set_mode = VOIDmode;
12302 rsp->last_set_nonzero_bits = 0;
12303 rsp->last_set_sign_bit_copies = 0;
12304 rsp->last_death = 0;
12305 rsp->truncated_to_mode = VOIDmode;
12308 /* Mark registers that are being referenced in this value. */
12310 update_table_tick (value);
12312 /* Now update the status of each register being set.
12313 If someone is using this register in this block, set this register
12314 to invalid since we will get confused between the two lives in this
12315 basic block. This makes using this register always invalid. In cse, we
12316 scan the table to invalidate all entries using this register, but this
12317 is too much work for us. */
12319 for (i = regno; i < endregno; i++)
12321 rsp = VEC_index (reg_stat_type, reg_stat, i);
12322 rsp->last_set_label = label_tick;
12324 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12325 rsp->last_set_invalid = 1;
12327 rsp->last_set_invalid = 0;
12330 /* The value being assigned might refer to X (like in "x++;"). In that
12331 case, we must replace it with (clobber (const_int 0)) to prevent
12333 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12334 if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12336 value = copy_rtx (value);
12337 if (!get_last_value_validate (&value, insn, label_tick, 1))
12341 /* For the main register being modified, update the value, the mode, the
12342 nonzero bits, and the number of sign bit copies. */
12344 rsp->last_set_value = value;
12348 enum machine_mode mode = GET_MODE (reg);
12349 subst_low_luid = DF_INSN_LUID (insn);
12350 rsp->last_set_mode = mode;
12351 if (GET_MODE_CLASS (mode) == MODE_INT
12352 && HWI_COMPUTABLE_MODE_P (mode))
12353 mode = nonzero_bits_mode;
12354 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12355 rsp->last_set_sign_bit_copies
12356 = num_sign_bit_copies (value, GET_MODE (reg));
12360 /* Called via note_stores from record_dead_and_set_regs to handle one
12361 SET or CLOBBER in an insn. DATA is the instruction in which the
12362 set is occurring. */
12365 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12367 rtx record_dead_insn = (rtx) data;
12369 if (GET_CODE (dest) == SUBREG)
12370 dest = SUBREG_REG (dest);
12372 if (!record_dead_insn)
12375 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12381 /* If we are setting the whole register, we know its value. Otherwise
12382 show that we don't know the value. We can handle SUBREG in
12384 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12385 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12386 else if (GET_CODE (setter) == SET
12387 && GET_CODE (SET_DEST (setter)) == SUBREG
12388 && SUBREG_REG (SET_DEST (setter)) == dest
12389 && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12390 && subreg_lowpart_p (SET_DEST (setter)))
12391 record_value_for_reg (dest, record_dead_insn,
12392 gen_lowpart (GET_MODE (dest),
12393 SET_SRC (setter)));
12395 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12397 else if (MEM_P (dest)
12398 /* Ignore pushes, they clobber nothing. */
12399 && ! push_operand (dest, GET_MODE (dest)))
12400 mem_last_set = DF_INSN_LUID (record_dead_insn);
12403 /* Update the records of when each REG was most recently set or killed
12404 for the things done by INSN. This is the last thing done in processing
12405 INSN in the combiner loop.
12407 We update reg_stat[], in particular fields last_set, last_set_value,
12408 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12409 last_death, and also the similar information mem_last_set (which insn
12410 most recently modified memory) and last_call_luid (which insn was the
12411 most recent subroutine call). */
12414 record_dead_and_set_regs (rtx insn)
12419 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12421 if (REG_NOTE_KIND (link) == REG_DEAD
12422 && REG_P (XEXP (link, 0)))
12424 unsigned int regno = REGNO (XEXP (link, 0));
12425 unsigned int endregno = END_REGNO (XEXP (link, 0));
12427 for (i = regno; i < endregno; i++)
12429 reg_stat_type *rsp;
12431 rsp = VEC_index (reg_stat_type, reg_stat, i);
12432 rsp->last_death = insn;
12435 else if (REG_NOTE_KIND (link) == REG_INC)
12436 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12441 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12442 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12444 reg_stat_type *rsp;
12446 rsp = VEC_index (reg_stat_type, reg_stat, i);
12447 rsp->last_set_invalid = 1;
12448 rsp->last_set = insn;
12449 rsp->last_set_value = 0;
12450 rsp->last_set_mode = VOIDmode;
12451 rsp->last_set_nonzero_bits = 0;
12452 rsp->last_set_sign_bit_copies = 0;
12453 rsp->last_death = 0;
12454 rsp->truncated_to_mode = VOIDmode;
12457 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12459 /* We can't combine into a call pattern. Remember, though, that
12460 the return value register is set at this LUID. We could
12461 still replace a register with the return value from the
12462 wrong subroutine call! */
12463 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12466 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12469 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12470 register present in the SUBREG, so for each such SUBREG go back and
12471 adjust nonzero and sign bit information of the registers that are
12472 known to have some zero/sign bits set.
12474 This is needed because when combine blows the SUBREGs away, the
12475 information on zero/sign bits is lost and further combines can be
12476 missed because of that. */
12479 record_promoted_value (rtx insn, rtx subreg)
12481 struct insn_link *links;
12483 unsigned int regno = REGNO (SUBREG_REG (subreg));
12484 enum machine_mode mode = GET_MODE (subreg);
12486 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12489 for (links = LOG_LINKS (insn); links;)
12491 reg_stat_type *rsp;
12493 insn = links->insn;
12494 set = single_set (insn);
12496 if (! set || !REG_P (SET_DEST (set))
12497 || REGNO (SET_DEST (set)) != regno
12498 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12500 links = links->next;
12504 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12505 if (rsp->last_set == insn)
12507 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12508 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12511 if (REG_P (SET_SRC (set)))
12513 regno = REGNO (SET_SRC (set));
12514 links = LOG_LINKS (insn);
12521 /* Check if X, a register, is known to contain a value already
12522 truncated to MODE. In this case we can use a subreg to refer to
12523 the truncated value even though in the generic case we would need
12524 an explicit truncation. */
12527 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12529 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12530 enum machine_mode truncated = rsp->truncated_to_mode;
12533 || rsp->truncation_label < label_tick_ebb_start)
12535 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12537 if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12542 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
12543 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
12544 might be able to turn a truncate into a subreg using this information.
12545 Return -1 if traversing *P is complete or 0 otherwise. */
12548 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12551 enum machine_mode truncated_mode;
12552 reg_stat_type *rsp;
12554 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12556 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12557 truncated_mode = GET_MODE (x);
12559 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12562 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12565 x = SUBREG_REG (x);
12567 /* ??? For hard-regs we now record everything. We might be able to
12568 optimize this using last_set_mode. */
12569 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12570 truncated_mode = GET_MODE (x);
12574 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12575 if (rsp->truncated_to_mode == 0
12576 || rsp->truncation_label < label_tick_ebb_start
12577 || (GET_MODE_SIZE (truncated_mode)
12578 < GET_MODE_SIZE (rsp->truncated_to_mode)))
12580 rsp->truncated_to_mode = truncated_mode;
12581 rsp->truncation_label = label_tick;
12587 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12588 the modes they are used in. This can help truning TRUNCATEs into
12592 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12594 for_each_rtx (x, record_truncated_value, NULL);
12597 /* Scan X for promoted SUBREGs. For each one found,
12598 note what it implies to the registers used in it. */
12601 check_promoted_subreg (rtx insn, rtx x)
12603 if (GET_CODE (x) == SUBREG
12604 && SUBREG_PROMOTED_VAR_P (x)
12605 && REG_P (SUBREG_REG (x)))
12606 record_promoted_value (insn, x);
12609 const char *format = GET_RTX_FORMAT (GET_CODE (x));
12612 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12616 check_promoted_subreg (insn, XEXP (x, i));
12620 if (XVEC (x, i) != 0)
12621 for (j = 0; j < XVECLEN (x, i); j++)
12622 check_promoted_subreg (insn, XVECEXP (x, i, j));
12628 /* Verify that all the registers and memory references mentioned in *LOC are
12629 still valid. *LOC was part of a value set in INSN when label_tick was
12630 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12631 the invalid references with (clobber (const_int 0)) and return 1. This
12632 replacement is useful because we often can get useful information about
12633 the form of a value (e.g., if it was produced by a shift that always
12634 produces -1 or 0) even though we don't know exactly what registers it
12635 was produced from. */
12638 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12641 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12642 int len = GET_RTX_LENGTH (GET_CODE (x));
12647 unsigned int regno = REGNO (x);
12648 unsigned int endregno = END_REGNO (x);
12651 for (j = regno; j < endregno; j++)
12653 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12654 if (rsp->last_set_invalid
12655 /* If this is a pseudo-register that was only set once and not
12656 live at the beginning of the function, it is always valid. */
12657 || (! (regno >= FIRST_PSEUDO_REGISTER
12658 && REG_N_SETS (regno) == 1
12659 && (!REGNO_REG_SET_P
12660 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12661 && rsp->last_set_label > tick))
12664 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12671 /* If this is a memory reference, make sure that there were no stores after
12672 it that might have clobbered the value. We don't have alias info, so we
12673 assume any store invalidates it. Moreover, we only have local UIDs, so
12674 we also assume that there were stores in the intervening basic blocks. */
12675 else if (MEM_P (x) && !MEM_READONLY_P (x)
12676 && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12679 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12683 for (i = 0; i < len; i++)
12687 /* Check for identical subexpressions. If x contains
12688 identical subexpression we only have to traverse one of
12690 if (i == 1 && ARITHMETIC_P (x))
12692 /* Note that at this point x0 has already been checked
12693 and found valid. */
12694 rtx x0 = XEXP (x, 0);
12695 rtx x1 = XEXP (x, 1);
12697 /* If x0 and x1 are identical then x is also valid. */
12701 /* If x1 is identical to a subexpression of x0 then
12702 while checking x0, x1 has already been checked. Thus
12703 it is valid and so as x. */
12704 if (ARITHMETIC_P (x0)
12705 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12708 /* If x0 is identical to a subexpression of x1 then x is
12709 valid iff the rest of x1 is valid. */
12710 if (ARITHMETIC_P (x1)
12711 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12713 get_last_value_validate (&XEXP (x1,
12714 x0 == XEXP (x1, 0) ? 1 : 0),
12715 insn, tick, replace);
12718 if (get_last_value_validate (&XEXP (x, i), insn, tick,
12722 else if (fmt[i] == 'E')
12723 for (j = 0; j < XVECLEN (x, i); j++)
12724 if (get_last_value_validate (&XVECEXP (x, i, j),
12725 insn, tick, replace) == 0)
12729 /* If we haven't found a reason for it to be invalid, it is valid. */
12733 /* Get the last value assigned to X, if known. Some registers
12734 in the value may be replaced with (clobber (const_int 0)) if their value
12735 is known longer known reliably. */
12738 get_last_value (const_rtx x)
12740 unsigned int regno;
12742 reg_stat_type *rsp;
12744 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12745 then convert it to the desired mode. If this is a paradoxical SUBREG,
12746 we cannot predict what values the "extra" bits might have. */
12747 if (GET_CODE (x) == SUBREG
12748 && subreg_lowpart_p (x)
12749 && !paradoxical_subreg_p (x)
12750 && (value = get_last_value (SUBREG_REG (x))) != 0)
12751 return gen_lowpart (GET_MODE (x), value);
12757 rsp = VEC_index (reg_stat_type, reg_stat, regno);
12758 value = rsp->last_set_value;
12760 /* If we don't have a value, or if it isn't for this basic block and
12761 it's either a hard register, set more than once, or it's a live
12762 at the beginning of the function, return 0.
12764 Because if it's not live at the beginning of the function then the reg
12765 is always set before being used (is never used without being set).
12766 And, if it's set only once, and it's always set before use, then all
12767 uses must have the same last value, even if it's not from this basic
12771 || (rsp->last_set_label < label_tick_ebb_start
12772 && (regno < FIRST_PSEUDO_REGISTER
12773 || REG_N_SETS (regno) != 1
12775 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12778 /* If the value was set in a later insn than the ones we are processing,
12779 we can't use it even if the register was only set once. */
12780 if (rsp->last_set_label == label_tick
12781 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12784 /* If the value has all its registers valid, return it. */
12785 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12788 /* Otherwise, make a copy and replace any invalid register with
12789 (clobber (const_int 0)). If that fails for some reason, return 0. */
12791 value = copy_rtx (value);
12792 if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12798 /* Return nonzero if expression X refers to a REG or to memory
12799 that is set in an instruction more recent than FROM_LUID. */
12802 use_crosses_set_p (const_rtx x, int from_luid)
12806 enum rtx_code code = GET_CODE (x);
12810 unsigned int regno = REGNO (x);
12811 unsigned endreg = END_REGNO (x);
12813 #ifdef PUSH_ROUNDING
12814 /* Don't allow uses of the stack pointer to be moved,
12815 because we don't know whether the move crosses a push insn. */
12816 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12819 for (; regno < endreg; regno++)
12821 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12823 && rsp->last_set_label == label_tick
12824 && DF_INSN_LUID (rsp->last_set) > from_luid)
12830 if (code == MEM && mem_last_set > from_luid)
12833 fmt = GET_RTX_FORMAT (code);
12835 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12840 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12841 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12844 else if (fmt[i] == 'e'
12845 && use_crosses_set_p (XEXP (x, i), from_luid))
12851 /* Define three variables used for communication between the following
12854 static unsigned int reg_dead_regno, reg_dead_endregno;
12855 static int reg_dead_flag;
12857 /* Function called via note_stores from reg_dead_at_p.
12859 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12860 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12863 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12865 unsigned int regno, endregno;
12870 regno = REGNO (dest);
12871 endregno = END_REGNO (dest);
12872 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12873 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12876 /* Return nonzero if REG is known to be dead at INSN.
12878 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12879 referencing REG, it is dead. If we hit a SET referencing REG, it is
12880 live. Otherwise, see if it is live or dead at the start of the basic
12881 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12882 must be assumed to be always live. */
12885 reg_dead_at_p (rtx reg, rtx insn)
12890 /* Set variables for reg_dead_at_p_1. */
12891 reg_dead_regno = REGNO (reg);
12892 reg_dead_endregno = END_REGNO (reg);
12896 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12897 we allow the machine description to decide whether use-and-clobber
12898 patterns are OK. */
12899 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12901 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12902 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12906 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12907 beginning of basic block. */
12908 block = BLOCK_FOR_INSN (insn);
12913 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12915 return reg_dead_flag == 1 ? 1 : 0;
12917 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12921 if (insn == BB_HEAD (block))
12924 insn = PREV_INSN (insn);
12927 /* Look at live-in sets for the basic block that we were in. */
12928 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12929 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12935 /* Note hard registers in X that are used. */
12938 mark_used_regs_combine (rtx x)
12940 RTX_CODE code = GET_CODE (x);
12941 unsigned int regno;
12954 case ADDR_DIFF_VEC:
12957 /* CC0 must die in the insn after it is set, so we don't need to take
12958 special note of it here. */
12964 /* If we are clobbering a MEM, mark any hard registers inside the
12965 address as used. */
12966 if (MEM_P (XEXP (x, 0)))
12967 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12972 /* A hard reg in a wide mode may really be multiple registers.
12973 If so, mark all of them just like the first. */
12974 if (regno < FIRST_PSEUDO_REGISTER)
12976 /* None of this applies to the stack, frame or arg pointers. */
12977 if (regno == STACK_POINTER_REGNUM
12978 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12979 || regno == HARD_FRAME_POINTER_REGNUM
12981 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12982 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12984 || regno == FRAME_POINTER_REGNUM)
12987 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12993 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12995 rtx testreg = SET_DEST (x);
12997 while (GET_CODE (testreg) == SUBREG
12998 || GET_CODE (testreg) == ZERO_EXTRACT
12999 || GET_CODE (testreg) == STRICT_LOW_PART)
13000 testreg = XEXP (testreg, 0);
13002 if (MEM_P (testreg))
13003 mark_used_regs_combine (XEXP (testreg, 0));
13005 mark_used_regs_combine (SET_SRC (x));
13013 /* Recursively scan the operands of this expression. */
13016 const char *fmt = GET_RTX_FORMAT (code);
13018 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13021 mark_used_regs_combine (XEXP (x, i));
13022 else if (fmt[i] == 'E')
13026 for (j = 0; j < XVECLEN (x, i); j++)
13027 mark_used_regs_combine (XVECEXP (x, i, j));
13033 /* Remove register number REGNO from the dead registers list of INSN.
13035 Return the note used to record the death, if there was one. */
13038 remove_death (unsigned int regno, rtx insn)
13040 rtx note = find_regno_note (insn, REG_DEAD, regno);
13043 remove_note (insn, note);
13048 /* For each register (hardware or pseudo) used within expression X, if its
13049 death is in an instruction with luid between FROM_LUID (inclusive) and
13050 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13051 list headed by PNOTES.
13053 That said, don't move registers killed by maybe_kill_insn.
13055 This is done when X is being merged by combination into TO_INSN. These
13056 notes will then be distributed as needed. */
13059 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13064 enum rtx_code code = GET_CODE (x);
13068 unsigned int regno = REGNO (x);
13069 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13071 /* Don't move the register if it gets killed in between from and to. */
13072 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13073 && ! reg_referenced_p (x, maybe_kill_insn))
13077 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13078 && DF_INSN_LUID (where_dead) >= from_luid
13079 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13081 rtx note = remove_death (regno, where_dead);
13083 /* It is possible for the call above to return 0. This can occur
13084 when last_death points to I2 or I1 that we combined with.
13085 In that case make a new note.
13087 We must also check for the case where X is a hard register
13088 and NOTE is a death note for a range of hard registers
13089 including X. In that case, we must put REG_DEAD notes for
13090 the remaining registers in place of NOTE. */
13092 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13093 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13094 > GET_MODE_SIZE (GET_MODE (x))))
13096 unsigned int deadregno = REGNO (XEXP (note, 0));
13097 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13098 unsigned int ourend = END_HARD_REGNO (x);
13101 for (i = deadregno; i < deadend; i++)
13102 if (i < regno || i >= ourend)
13103 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13106 /* If we didn't find any note, or if we found a REG_DEAD note that
13107 covers only part of the given reg, and we have a multi-reg hard
13108 register, then to be safe we must check for REG_DEAD notes
13109 for each register other than the first. They could have
13110 their own REG_DEAD notes lying around. */
13111 else if ((note == 0
13113 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13114 < GET_MODE_SIZE (GET_MODE (x)))))
13115 && regno < FIRST_PSEUDO_REGISTER
13116 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13118 unsigned int ourend = END_HARD_REGNO (x);
13119 unsigned int i, offset;
13123 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13127 for (i = regno + offset; i < ourend; i++)
13128 move_deaths (regno_reg_rtx[i],
13129 maybe_kill_insn, from_luid, to_insn, &oldnotes);
13132 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13134 XEXP (note, 1) = *pnotes;
13138 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13144 else if (GET_CODE (x) == SET)
13146 rtx dest = SET_DEST (x);
13148 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13150 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13151 that accesses one word of a multi-word item, some
13152 piece of everything register in the expression is used by
13153 this insn, so remove any old death. */
13154 /* ??? So why do we test for equality of the sizes? */
13156 if (GET_CODE (dest) == ZERO_EXTRACT
13157 || GET_CODE (dest) == STRICT_LOW_PART
13158 || (GET_CODE (dest) == SUBREG
13159 && (((GET_MODE_SIZE (GET_MODE (dest))
13160 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13161 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13162 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13164 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13168 /* If this is some other SUBREG, we know it replaces the entire
13169 value, so use that as the destination. */
13170 if (GET_CODE (dest) == SUBREG)
13171 dest = SUBREG_REG (dest);
13173 /* If this is a MEM, adjust deaths of anything used in the address.
13174 For a REG (the only other possibility), the entire value is
13175 being replaced so the old value is not used in this insn. */
13178 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13183 else if (GET_CODE (x) == CLOBBER)
13186 len = GET_RTX_LENGTH (code);
13187 fmt = GET_RTX_FORMAT (code);
13189 for (i = 0; i < len; i++)
13194 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13195 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13198 else if (fmt[i] == 'e')
13199 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13203 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13204 pattern of an insn. X must be a REG. */
13207 reg_bitfield_target_p (rtx x, rtx body)
13211 if (GET_CODE (body) == SET)
13213 rtx dest = SET_DEST (body);
13215 unsigned int regno, tregno, endregno, endtregno;
13217 if (GET_CODE (dest) == ZERO_EXTRACT)
13218 target = XEXP (dest, 0);
13219 else if (GET_CODE (dest) == STRICT_LOW_PART)
13220 target = SUBREG_REG (XEXP (dest, 0));
13224 if (GET_CODE (target) == SUBREG)
13225 target = SUBREG_REG (target);
13227 if (!REG_P (target))
13230 tregno = REGNO (target), regno = REGNO (x);
13231 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13232 return target == x;
13234 endtregno = end_hard_regno (GET_MODE (target), tregno);
13235 endregno = end_hard_regno (GET_MODE (x), regno);
13237 return endregno > tregno && regno < endtregno;
13240 else if (GET_CODE (body) == PARALLEL)
13241 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13242 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13248 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13249 as appropriate. I3 and I2 are the insns resulting from the combination
13250 insns including FROM (I2 may be zero).
13252 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13253 not need REG_DEAD notes because they are being substituted for. This
13254 saves searching in the most common cases.
13256 Each note in the list is either ignored or placed on some insns, depending
13257 on the type of note. */
13260 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13261 rtx elim_i1, rtx elim_i0)
13263 rtx note, next_note;
13266 for (note = notes; note; note = next_note)
13268 rtx place = 0, place2 = 0;
13270 next_note = XEXP (note, 1);
13271 switch (REG_NOTE_KIND (note))
13275 /* Doesn't matter much where we put this, as long as it's somewhere.
13276 It is preferable to keep these notes on branches, which is most
13277 likely to be i3. */
13281 case REG_NON_LOCAL_GOTO:
13286 gcc_assert (i2 && JUMP_P (i2));
13291 case REG_EH_REGION:
13292 /* These notes must remain with the call or trapping instruction. */
13295 else if (i2 && CALL_P (i2))
13299 gcc_assert (cfun->can_throw_non_call_exceptions);
13300 if (may_trap_p (i3))
13302 else if (i2 && may_trap_p (i2))
13304 /* ??? Otherwise assume we've combined things such that we
13305 can now prove that the instructions can't trap. Drop the
13306 note in this case. */
13310 case REG_ARGS_SIZE:
13311 /* ??? How to distribute between i3-i1. Assume i3 contains the
13312 entire adjustment. Assert i3 contains at least some adjust. */
13313 if (!noop_move_p (i3))
13315 int old_size, args_size = INTVAL (XEXP (note, 0));
13316 /* fixup_args_size_notes looks at REG_NORETURN note,
13317 so ensure the note is placed there first. */
13321 for (np = &next_note; *np; np = &XEXP (*np, 1))
13322 if (REG_NOTE_KIND (*np) == REG_NORETURN)
13326 XEXP (n, 1) = REG_NOTES (i3);
13327 REG_NOTES (i3) = n;
13331 old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13332 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13333 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13334 gcc_assert (old_size != args_size
13336 && !ACCUMULATE_OUTGOING_ARGS
13337 && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13344 /* These notes must remain with the call. It should not be
13345 possible for both I2 and I3 to be a call. */
13350 gcc_assert (i2 && CALL_P (i2));
13356 /* Any clobbers for i3 may still exist, and so we must process
13357 REG_UNUSED notes from that insn.
13359 Any clobbers from i2 or i1 can only exist if they were added by
13360 recog_for_combine. In that case, recog_for_combine created the
13361 necessary REG_UNUSED notes. Trying to keep any original
13362 REG_UNUSED notes from these insns can cause incorrect output
13363 if it is for the same register as the original i3 dest.
13364 In that case, we will notice that the register is set in i3,
13365 and then add a REG_UNUSED note for the destination of i3, which
13366 is wrong. However, it is possible to have REG_UNUSED notes from
13367 i2 or i1 for register which were both used and clobbered, so
13368 we keep notes from i2 or i1 if they will turn into REG_DEAD
13371 /* If this register is set or clobbered in I3, put the note there
13372 unless there is one already. */
13373 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13375 if (from_insn != i3)
13378 if (! (REG_P (XEXP (note, 0))
13379 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13380 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13383 /* Otherwise, if this register is used by I3, then this register
13384 now dies here, so we must put a REG_DEAD note here unless there
13386 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13387 && ! (REG_P (XEXP (note, 0))
13388 ? find_regno_note (i3, REG_DEAD,
13389 REGNO (XEXP (note, 0)))
13390 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13392 PUT_REG_NOTE_KIND (note, REG_DEAD);
13400 /* These notes say something about results of an insn. We can
13401 only support them if they used to be on I3 in which case they
13402 remain on I3. Otherwise they are ignored.
13404 If the note refers to an expression that is not a constant, we
13405 must also ignore the note since we cannot tell whether the
13406 equivalence is still true. It might be possible to do
13407 slightly better than this (we only have a problem if I2DEST
13408 or I1DEST is present in the expression), but it doesn't
13409 seem worth the trouble. */
13411 if (from_insn == i3
13412 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13417 /* These notes say something about how a register is used. They must
13418 be present on any use of the register in I2 or I3. */
13419 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13422 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13431 case REG_LABEL_TARGET:
13432 case REG_LABEL_OPERAND:
13433 /* This can show up in several ways -- either directly in the
13434 pattern, or hidden off in the constant pool with (or without?)
13435 a REG_EQUAL note. */
13436 /* ??? Ignore the without-reg_equal-note problem for now. */
13437 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13438 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13439 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13440 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13444 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13445 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13446 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13447 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13455 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13456 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13458 if (place && JUMP_P (place)
13459 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13460 && (JUMP_LABEL (place) == NULL
13461 || JUMP_LABEL (place) == XEXP (note, 0)))
13463 rtx label = JUMP_LABEL (place);
13466 JUMP_LABEL (place) = XEXP (note, 0);
13467 else if (LABEL_P (label))
13468 LABEL_NUSES (label)--;
13471 if (place2 && JUMP_P (place2)
13472 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13473 && (JUMP_LABEL (place2) == NULL
13474 || JUMP_LABEL (place2) == XEXP (note, 0)))
13476 rtx label = JUMP_LABEL (place2);
13479 JUMP_LABEL (place2) = XEXP (note, 0);
13480 else if (LABEL_P (label))
13481 LABEL_NUSES (label)--;
13487 /* This note says something about the value of a register prior
13488 to the execution of an insn. It is too much trouble to see
13489 if the note is still correct in all situations. It is better
13490 to simply delete it. */
13494 /* If we replaced the right hand side of FROM_INSN with a
13495 REG_EQUAL note, the original use of the dying register
13496 will not have been combined into I3 and I2. In such cases,
13497 FROM_INSN is guaranteed to be the first of the combined
13498 instructions, so we simply need to search back before
13499 FROM_INSN for the previous use or set of this register,
13500 then alter the notes there appropriately.
13502 If the register is used as an input in I3, it dies there.
13503 Similarly for I2, if it is nonzero and adjacent to I3.
13505 If the register is not used as an input in either I3 or I2
13506 and it is not one of the registers we were supposed to eliminate,
13507 there are two possibilities. We might have a non-adjacent I2
13508 or we might have somehow eliminated an additional register
13509 from a computation. For example, we might have had A & B where
13510 we discover that B will always be zero. In this case we will
13511 eliminate the reference to A.
13513 In both cases, we must search to see if we can find a previous
13514 use of A and put the death note there. */
13517 && from_insn == i2mod
13518 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13523 && CALL_P (from_insn)
13524 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13526 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13528 else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13529 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13531 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13533 && reg_overlap_mentioned_p (XEXP (note, 0),
13535 || rtx_equal_p (XEXP (note, 0), elim_i1)
13536 || rtx_equal_p (XEXP (note, 0), elim_i0))
13543 basic_block bb = this_basic_block;
13545 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13547 if (!NONDEBUG_INSN_P (tem))
13549 if (tem == BB_HEAD (bb))
13554 /* If the register is being set at TEM, see if that is all
13555 TEM is doing. If so, delete TEM. Otherwise, make this
13556 into a REG_UNUSED note instead. Don't delete sets to
13557 global register vars. */
13558 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13559 || !global_regs[REGNO (XEXP (note, 0))])
13560 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13562 rtx set = single_set (tem);
13563 rtx inner_dest = 0;
13565 rtx cc0_setter = NULL_RTX;
13569 for (inner_dest = SET_DEST (set);
13570 (GET_CODE (inner_dest) == STRICT_LOW_PART
13571 || GET_CODE (inner_dest) == SUBREG
13572 || GET_CODE (inner_dest) == ZERO_EXTRACT);
13573 inner_dest = XEXP (inner_dest, 0))
13576 /* Verify that it was the set, and not a clobber that
13577 modified the register.
13579 CC0 targets must be careful to maintain setter/user
13580 pairs. If we cannot delete the setter due to side
13581 effects, mark the user with an UNUSED note instead
13584 if (set != 0 && ! side_effects_p (SET_SRC (set))
13585 && rtx_equal_p (XEXP (note, 0), inner_dest)
13587 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13588 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13589 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13593 /* Move the notes and links of TEM elsewhere.
13594 This might delete other dead insns recursively.
13595 First set the pattern to something that won't use
13597 rtx old_notes = REG_NOTES (tem);
13599 PATTERN (tem) = pc_rtx;
13600 REG_NOTES (tem) = NULL;
13602 distribute_notes (old_notes, tem, tem, NULL_RTX,
13603 NULL_RTX, NULL_RTX, NULL_RTX);
13604 distribute_links (LOG_LINKS (tem));
13606 SET_INSN_DELETED (tem);
13611 /* Delete the setter too. */
13614 PATTERN (cc0_setter) = pc_rtx;
13615 old_notes = REG_NOTES (cc0_setter);
13616 REG_NOTES (cc0_setter) = NULL;
13618 distribute_notes (old_notes, cc0_setter,
13619 cc0_setter, NULL_RTX,
13620 NULL_RTX, NULL_RTX, NULL_RTX);
13621 distribute_links (LOG_LINKS (cc0_setter));
13623 SET_INSN_DELETED (cc0_setter);
13624 if (cc0_setter == i2)
13631 PUT_REG_NOTE_KIND (note, REG_UNUSED);
13633 /* If there isn't already a REG_UNUSED note, put one
13634 here. Do not place a REG_DEAD note, even if
13635 the register is also used here; that would not
13636 match the algorithm used in lifetime analysis
13637 and can cause the consistency check in the
13638 scheduler to fail. */
13639 if (! find_regno_note (tem, REG_UNUSED,
13640 REGNO (XEXP (note, 0))))
13645 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13647 && find_reg_fusage (tem, USE, XEXP (note, 0))))
13651 /* If we are doing a 3->2 combination, and we have a
13652 register which formerly died in i3 and was not used
13653 by i2, which now no longer dies in i3 and is used in
13654 i2 but does not die in i2, and place is between i2
13655 and i3, then we may need to move a link from place to
13657 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13659 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13660 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13662 struct insn_link *links = LOG_LINKS (place);
13663 LOG_LINKS (place) = NULL;
13664 distribute_links (links);
13669 if (tem == BB_HEAD (bb))
13675 /* If the register is set or already dead at PLACE, we needn't do
13676 anything with this note if it is still a REG_DEAD note.
13677 We check here if it is set at all, not if is it totally replaced,
13678 which is what `dead_or_set_p' checks, so also check for it being
13681 if (place && REG_NOTE_KIND (note) == REG_DEAD)
13683 unsigned int regno = REGNO (XEXP (note, 0));
13684 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13686 if (dead_or_set_p (place, XEXP (note, 0))
13687 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13689 /* Unless the register previously died in PLACE, clear
13690 last_death. [I no longer understand why this is
13692 if (rsp->last_death != place)
13693 rsp->last_death = 0;
13697 rsp->last_death = place;
13699 /* If this is a death note for a hard reg that is occupying
13700 multiple registers, ensure that we are still using all
13701 parts of the object. If we find a piece of the object
13702 that is unused, we must arrange for an appropriate REG_DEAD
13703 note to be added for it. However, we can't just emit a USE
13704 and tag the note to it, since the register might actually
13705 be dead; so we recourse, and the recursive call then finds
13706 the previous insn that used this register. */
13708 if (place && regno < FIRST_PSEUDO_REGISTER
13709 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13711 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13715 for (i = regno; i < endregno; i++)
13716 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13717 && ! find_regno_fusage (place, USE, i))
13718 || dead_or_set_regno_p (place, i))
13723 /* Put only REG_DEAD notes for pieces that are
13724 not already dead or set. */
13726 for (i = regno; i < endregno;
13727 i += hard_regno_nregs[i][reg_raw_mode[i]])
13729 rtx piece = regno_reg_rtx[i];
13730 basic_block bb = this_basic_block;
13732 if (! dead_or_set_p (place, piece)
13733 && ! reg_bitfield_target_p (piece,
13736 rtx new_note = alloc_reg_note (REG_DEAD, piece,
13739 distribute_notes (new_note, place, place,
13740 NULL_RTX, NULL_RTX, NULL_RTX,
13743 else if (! refers_to_regno_p (i, i + 1,
13744 PATTERN (place), 0)
13745 && ! find_regno_fusage (place, USE, i))
13746 for (tem = PREV_INSN (place); ;
13747 tem = PREV_INSN (tem))
13749 if (!NONDEBUG_INSN_P (tem))
13751 if (tem == BB_HEAD (bb))
13755 if (dead_or_set_p (tem, piece)
13756 || reg_bitfield_target_p (piece,
13759 add_reg_note (tem, REG_UNUSED, piece);
13773 /* Any other notes should not be present at this point in the
13775 gcc_unreachable ();
13780 XEXP (note, 1) = REG_NOTES (place);
13781 REG_NOTES (place) = note;
13785 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13789 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13790 I3, I2, and I1 to new locations. This is also called to add a link
13791 pointing at I3 when I3's destination is changed. */
13794 distribute_links (struct insn_link *links)
13796 struct insn_link *link, *next_link;
13798 for (link = links; link; link = next_link)
13804 next_link = link->next;
13806 /* If the insn that this link points to is a NOTE or isn't a single
13807 set, ignore it. In the latter case, it isn't clear what we
13808 can do other than ignore the link, since we can't tell which
13809 register it was for. Such links wouldn't be used by combine
13812 It is not possible for the destination of the target of the link to
13813 have been changed by combine. The only potential of this is if we
13814 replace I3, I2, and I1 by I3 and I2. But in that case the
13815 destination of I2 also remains unchanged. */
13817 if (NOTE_P (link->insn)
13818 || (set = single_set (link->insn)) == 0)
13821 reg = SET_DEST (set);
13822 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13823 || GET_CODE (reg) == STRICT_LOW_PART)
13824 reg = XEXP (reg, 0);
13826 /* A LOG_LINK is defined as being placed on the first insn that uses
13827 a register and points to the insn that sets the register. Start
13828 searching at the next insn after the target of the link and stop
13829 when we reach a set of the register or the end of the basic block.
13831 Note that this correctly handles the link that used to point from
13832 I3 to I2. Also note that not much searching is typically done here
13833 since most links don't point very far away. */
13835 for (insn = NEXT_INSN (link->insn);
13836 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13837 || BB_HEAD (this_basic_block->next_bb) != insn));
13838 insn = NEXT_INSN (insn))
13839 if (DEBUG_INSN_P (insn))
13841 else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13843 if (reg_referenced_p (reg, PATTERN (insn)))
13847 else if (CALL_P (insn)
13848 && find_reg_fusage (insn, USE, reg))
13853 else if (INSN_P (insn) && reg_set_p (reg, insn))
13856 /* If we found a place to put the link, place it there unless there
13857 is already a link to the same insn as LINK at that point. */
13861 struct insn_link *link2;
13863 FOR_EACH_LOG_LINK (link2, place)
13864 if (link2->insn == link->insn)
13869 link->next = LOG_LINKS (place);
13870 LOG_LINKS (place) = link;
13872 /* Set added_links_insn to the earliest insn we added a
13874 if (added_links_insn == 0
13875 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13876 added_links_insn = place;
13882 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13883 Check whether the expression pointer to by LOC is a register or
13884 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13885 Otherwise return zero. */
13888 unmentioned_reg_p_1 (rtx *loc, void *expr)
13893 && (REG_P (x) || MEM_P (x))
13894 && ! reg_mentioned_p (x, (rtx) expr))
13899 /* Check for any register or memory mentioned in EQUIV that is not
13900 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13901 of EXPR where some registers may have been replaced by constants. */
13904 unmentioned_reg_p (rtx equiv, rtx expr)
13906 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13910 dump_combine_stats (FILE *file)
13914 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13915 combine_attempts, combine_merges, combine_extras, combine_successes);
13919 dump_combine_total_stats (FILE *file)
13923 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13924 total_attempts, total_merges, total_extras, total_successes);
13928 gate_handle_combine (void)
13930 return (optimize > 0);
13933 /* Try combining insns through substitution. */
13934 static unsigned int
13935 rest_of_handle_combine (void)
13937 int rebuild_jump_labels_after_combine;
13939 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13940 df_note_add_problem ();
13943 regstat_init_n_sets_and_refs ();
13945 rebuild_jump_labels_after_combine
13946 = combine_instructions (get_insns (), max_reg_num ());
13948 /* Combining insns may have turned an indirect jump into a
13949 direct jump. Rebuild the JUMP_LABEL fields of jumping
13951 if (rebuild_jump_labels_after_combine)
13953 timevar_push (TV_JUMP);
13954 rebuild_jump_labels (get_insns ());
13956 timevar_pop (TV_JUMP);
13959 regstat_free_n_sets_and_refs ();
13963 struct rtl_opt_pass pass_combine =
13967 "combine", /* name */
13968 gate_handle_combine, /* gate */
13969 rest_of_handle_combine, /* execute */
13972 0, /* static_pass_number */
13973 TV_COMBINE, /* tv_id */
13974 PROP_cfglayout, /* properties_required */
13975 0, /* properties_provided */
13976 0, /* properties_destroyed */
13977 0, /* todo_flags_start */
13978 TODO_df_finish | TODO_verify_rtl_sharing |
13979 TODO_ggc_collect, /* todo_flags_finish */