1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
300 static bool optimize_this_for_speed_p;
303 /* Length of the currently allocated uid_insn_cost array. */
305 static int max_uid_known;
307 /* The following array records the insn_rtx_cost for every insn
308 in the instruction stream. */
310 static int *uid_insn_cost;
312 /* The following array records the LOG_LINKS for every insn in the
313 instruction stream as an INSN_LIST rtx. */
315 static rtx *uid_log_links;
317 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
318 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
320 /* Incremented for each basic block. */
322 static int label_tick;
324 /* Reset to label_tick for each label. */
326 static int label_tick_ebb_start;
328 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
329 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
331 static enum machine_mode nonzero_bits_mode;
333 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
334 be safely used. It is zero while computing them and after combine has
335 completed. This former test prevents propagating values based on
336 previously set values, which can be incorrect if a variable is modified
339 static int nonzero_sign_valid;
342 /* Record one modification to rtl structure
343 to be undone by storing old_contents into *where. */
345 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE };
351 union { rtx r; int i; enum machine_mode m; } old_contents;
352 union { rtx *r; int *i; } where;
355 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
356 num_undo says how many are currently recorded.
358 other_insn is nonzero if we have modified some other insn in the process
359 of working on subst_insn. It must be verified too. */
368 static struct undobuf undobuf;
370 /* Number of times the pseudo being substituted for
371 was found and replaced. */
373 static int n_occurrences;
375 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
377 unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
381 unsigned int, unsigned int *);
382 static void do_SUBST (rtx *, rtx);
383 static void do_SUBST_INT (int *, int);
384 static void init_reg_last (void);
385 static void setup_incoming_promotions (rtx);
386 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
387 static int cant_combine_insn_p (rtx);
388 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
389 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
390 static int contains_muldiv (rtx);
391 static rtx try_combine (rtx, rtx, rtx, int *);
392 static void undo_all (void);
393 static void undo_commit (void);
394 static rtx *find_split_point (rtx *, rtx);
395 static rtx subst (rtx, rtx, rtx, int, int);
396 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
397 static rtx simplify_if_then_else (rtx);
398 static rtx simplify_set (rtx);
399 static rtx simplify_logical (rtx);
400 static rtx expand_compound_operation (rtx);
401 static const_rtx expand_field_assignment (const_rtx);
402 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
403 rtx, unsigned HOST_WIDE_INT, int, int, int);
404 static rtx extract_left_shift (rtx, int);
405 static rtx make_compound_operation (rtx, enum rtx_code);
406 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
407 unsigned HOST_WIDE_INT *);
408 static rtx canon_reg_for_combine (rtx, rtx);
409 static rtx force_to_mode (rtx, enum machine_mode,
410 unsigned HOST_WIDE_INT, int);
411 static rtx if_then_else_cond (rtx, rtx *, rtx *);
412 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
413 static int rtx_equal_for_field_assignment_p (rtx, rtx);
414 static rtx make_field_assignment (rtx);
415 static rtx apply_distributive_law (rtx);
416 static rtx distribute_and_simplify_rtx (rtx, int);
417 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
418 unsigned HOST_WIDE_INT);
419 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
420 unsigned HOST_WIDE_INT);
421 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
422 HOST_WIDE_INT, enum machine_mode, int *);
423 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
424 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
426 static int recog_for_combine (rtx *, rtx, rtx *);
427 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
428 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
429 static void update_table_tick (rtx);
430 static void record_value_for_reg (rtx, rtx, rtx);
431 static void check_promoted_subreg (rtx, rtx);
432 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
433 static void record_dead_and_set_regs (rtx);
434 static int get_last_value_validate (rtx *, rtx, int, int);
435 static rtx get_last_value (const_rtx);
436 static int use_crosses_set_p (const_rtx, int);
437 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
438 static int reg_dead_at_p (rtx, rtx);
439 static void move_deaths (rtx, rtx, int, rtx, rtx *);
440 static int reg_bitfield_target_p (rtx, rtx);
441 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
442 static void distribute_links (rtx);
443 static void mark_used_regs_combine (rtx);
444 static void record_promoted_value (rtx, rtx);
445 static int unmentioned_reg_p_1 (rtx *, void *);
446 static bool unmentioned_reg_p (rtx, rtx);
447 static int record_truncated_value (rtx *, void *);
448 static void record_truncated_values (rtx *, void *);
449 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
450 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
453 /* It is not safe to use ordinary gen_lowpart in combine.
454 See comments in gen_lowpart_for_combine. */
455 #undef RTL_HOOKS_GEN_LOWPART
456 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
458 /* Our implementation of gen_lowpart never emits a new pseudo. */
459 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
460 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
462 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
463 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
465 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
466 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
468 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
469 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
471 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
474 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
475 PATTERN can not be split. Otherwise, it returns an insn sequence.
476 This is a wrapper around split_insns which ensures that the
477 reg_stat vector is made larger if the splitter creates a new
481 combine_split_insns (rtx pattern, rtx insn)
486 ret = split_insns (pattern, insn);
487 nregs = max_reg_num ();
488 if (nregs > VEC_length (reg_stat_type, reg_stat))
489 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
493 /* This is used by find_single_use to locate an rtx in LOC that
494 contains exactly one use of DEST, which is typically either a REG
495 or CC0. It returns a pointer to the innermost rtx expression
496 containing DEST. Appearances of DEST that are being used to
497 totally replace it are not counted. */
500 find_single_use_1 (rtx dest, rtx *loc)
503 enum rtx_code code = GET_CODE (x);
521 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
522 of a REG that occupies all of the REG, the insn uses DEST if
523 it is mentioned in the destination or the source. Otherwise, we
524 need just check the source. */
525 if (GET_CODE (SET_DEST (x)) != CC0
526 && GET_CODE (SET_DEST (x)) != PC
527 && !REG_P (SET_DEST (x))
528 && ! (GET_CODE (SET_DEST (x)) == SUBREG
529 && REG_P (SUBREG_REG (SET_DEST (x)))
530 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
531 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
532 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
533 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
536 return find_single_use_1 (dest, &SET_SRC (x));
540 return find_single_use_1 (dest, &XEXP (x, 0));
546 /* If it wasn't one of the common cases above, check each expression and
547 vector of this code. Look for a unique usage of DEST. */
549 fmt = GET_RTX_FORMAT (code);
550 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
554 if (dest == XEXP (x, i)
555 || (REG_P (dest) && REG_P (XEXP (x, i))
556 && REGNO (dest) == REGNO (XEXP (x, i))))
559 this_result = find_single_use_1 (dest, &XEXP (x, i));
562 result = this_result;
563 else if (this_result)
564 /* Duplicate usage. */
567 else if (fmt[i] == 'E')
571 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
573 if (XVECEXP (x, i, j) == dest
575 && REG_P (XVECEXP (x, i, j))
576 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
579 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
582 result = this_result;
583 else if (this_result)
593 /* See if DEST, produced in INSN, is used only a single time in the
594 sequel. If so, return a pointer to the innermost rtx expression in which
597 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
599 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
600 care about REG_DEAD notes or LOG_LINKS.
602 Otherwise, we find the single use by finding an insn that has a
603 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
604 only referenced once in that insn, we know that it must be the first
605 and last insn referencing DEST. */
608 find_single_use (rtx dest, rtx insn, rtx *ploc)
618 next = NEXT_INSN (insn);
620 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
623 result = find_single_use_1 (dest, &PATTERN (next));
633 bb = BLOCK_FOR_INSN (insn);
634 for (next = NEXT_INSN (insn);
635 next && BLOCK_FOR_INSN (next) == bb;
636 next = NEXT_INSN (next))
637 if (INSN_P (next) && dead_or_set_p (next, dest))
639 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
640 if (XEXP (link, 0) == insn)
645 result = find_single_use_1 (dest, &PATTERN (next));
655 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
656 insn. The substitution can be undone by undo_all. If INTO is already
657 set to NEWVAL, do not record this change. Because computing NEWVAL might
658 also call SUBST, we have to compute it before we put anything into
662 do_SUBST (rtx *into, rtx newval)
667 if (oldval == newval)
670 /* We'd like to catch as many invalid transformations here as
671 possible. Unfortunately, there are way too many mode changes
672 that are perfectly valid, so we'd waste too much effort for
673 little gain doing the checks here. Focus on catching invalid
674 transformations involving integer constants. */
675 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
676 && CONST_INT_P (newval))
678 /* Sanity check that we're replacing oldval with a CONST_INT
679 that is a valid sign-extension for the original mode. */
680 gcc_assert (INTVAL (newval)
681 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
683 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
684 CONST_INT is not valid, because after the replacement, the
685 original mode would be gone. Unfortunately, we can't tell
686 when do_SUBST is called to replace the operand thereof, so we
687 perform this test on oldval instead, checking whether an
688 invalid replacement took place before we got here. */
689 gcc_assert (!(GET_CODE (oldval) == SUBREG
690 && CONST_INT_P (SUBREG_REG (oldval))));
691 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
692 && CONST_INT_P (XEXP (oldval, 0))));
696 buf = undobuf.frees, undobuf.frees = buf->next;
698 buf = XNEW (struct undo);
700 buf->kind = UNDO_RTX;
702 buf->old_contents.r = oldval;
705 buf->next = undobuf.undos, undobuf.undos = buf;
708 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
710 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
711 for the value of a HOST_WIDE_INT value (including CONST_INT) is
715 do_SUBST_INT (int *into, int newval)
720 if (oldval == newval)
724 buf = undobuf.frees, undobuf.frees = buf->next;
726 buf = XNEW (struct undo);
728 buf->kind = UNDO_INT;
730 buf->old_contents.i = oldval;
733 buf->next = undobuf.undos, undobuf.undos = buf;
736 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
738 /* Similar to SUBST, but just substitute the mode. This is used when
739 changing the mode of a pseudo-register, so that any other
740 references to the entry in the regno_reg_rtx array will change as
744 do_SUBST_MODE (rtx *into, enum machine_mode newval)
747 enum machine_mode oldval = GET_MODE (*into);
749 if (oldval == newval)
753 buf = undobuf.frees, undobuf.frees = buf->next;
755 buf = XNEW (struct undo);
757 buf->kind = UNDO_MODE;
759 buf->old_contents.m = oldval;
760 adjust_reg_mode (*into, newval);
762 buf->next = undobuf.undos, undobuf.undos = buf;
765 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
767 /* Subroutine of try_combine. Determine whether the combine replacement
768 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
769 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
770 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
771 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
772 function returns false, if the costs of all instructions can be
773 estimated, and the replacements are more expensive than the original
777 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
780 int i1_cost, i2_cost, i3_cost;
781 int new_i2_cost, new_i3_cost;
782 int old_cost, new_cost;
784 /* Lookup the original insn_rtx_costs. */
785 i2_cost = INSN_COST (i2);
786 i3_cost = INSN_COST (i3);
790 i1_cost = INSN_COST (i1);
791 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
792 ? i1_cost + i2_cost + i3_cost : 0;
796 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
800 /* Calculate the replacement insn_rtx_costs. */
801 new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
804 new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
805 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
806 ? new_i2_cost + new_i3_cost : 0;
810 new_cost = new_i3_cost;
814 if (undobuf.other_insn)
816 int old_other_cost, new_other_cost;
818 old_other_cost = INSN_COST (undobuf.other_insn);
819 new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
820 if (old_other_cost > 0 && new_other_cost > 0)
822 old_cost += old_other_cost;
823 new_cost += new_other_cost;
829 /* Disallow this recombination if both new_cost and old_cost are
830 greater than zero, and new_cost is greater than old cost. */
832 && new_cost > old_cost)
839 "rejecting combination of insns %d, %d and %d\n",
840 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
841 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
842 i1_cost, i2_cost, i3_cost, old_cost);
847 "rejecting combination of insns %d and %d\n",
848 INSN_UID (i2), INSN_UID (i3));
849 fprintf (dump_file, "original costs %d + %d = %d\n",
850 i2_cost, i3_cost, old_cost);
855 fprintf (dump_file, "replacement costs %d + %d = %d\n",
856 new_i2_cost, new_i3_cost, new_cost);
859 fprintf (dump_file, "replacement cost %d\n", new_cost);
865 /* Update the uid_insn_cost array with the replacement costs. */
866 INSN_COST (i2) = new_i2_cost;
867 INSN_COST (i3) = new_i3_cost;
875 /* Delete any insns that copy a register to itself. */
878 delete_noop_moves (void)
885 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
887 next = NEXT_INSN (insn);
888 if (INSN_P (insn) && noop_move_p (insn))
891 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
893 delete_insn_and_edges (insn);
900 /* Fill in log links field for all insns. */
903 create_log_links (void)
907 df_ref *def_vec, *use_vec;
909 next_use = XCNEWVEC (rtx, max_reg_num ());
911 /* Pass through each block from the end, recording the uses of each
912 register and establishing log links when def is encountered.
913 Note that we do not clear next_use array in order to save time,
914 so we have to test whether the use is in the same basic block as def.
916 There are a few cases below when we do not consider the definition or
917 usage -- these are taken from original flow.c did. Don't ask me why it is
918 done this way; I don't know and if it works, I don't want to know. */
922 FOR_BB_INSNS_REVERSE (bb, insn)
927 /* Log links are created only once. */
928 gcc_assert (!LOG_LINKS (insn));
930 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
932 df_ref def = *def_vec;
933 int regno = DF_REF_REGNO (def);
936 if (!next_use[regno])
939 /* Do not consider if it is pre/post modification in MEM. */
940 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
943 /* Do not make the log link for frame pointer. */
944 if ((regno == FRAME_POINTER_REGNUM
945 && (! reload_completed || frame_pointer_needed))
946 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
947 || (regno == HARD_FRAME_POINTER_REGNUM
948 && (! reload_completed || frame_pointer_needed))
950 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
951 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
956 use_insn = next_use[regno];
957 if (BLOCK_FOR_INSN (use_insn) == bb)
961 We don't build a LOG_LINK for hard registers contained
962 in ASM_OPERANDs. If these registers get replaced,
963 we might wind up changing the semantics of the insn,
964 even if reload can make what appear to be valid
965 assignments later. */
966 if (regno >= FIRST_PSEUDO_REGISTER
967 || asm_noperands (PATTERN (use_insn)) < 0)
969 /* Don't add duplicate links between instructions. */
971 for (links = LOG_LINKS (use_insn); links;
972 links = XEXP (links, 1))
973 if (insn == XEXP (links, 0))
977 LOG_LINKS (use_insn) =
978 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
981 next_use[regno] = NULL_RTX;
984 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
986 df_ref use = *use_vec;
987 int regno = DF_REF_REGNO (use);
989 /* Do not consider the usage of the stack pointer
991 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
994 next_use[regno] = insn;
1002 /* Clear LOG_LINKS fields of insns. */
1005 clear_log_links (void)
1009 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1011 free_INSN_LIST_list (&LOG_LINKS (insn));
1017 /* Main entry point for combiner. F is the first insn of the function.
1018 NREGS is the first unused pseudo-reg number.
1020 Return nonzero if the combiner has turned an indirect jump
1021 instruction into a direct jump. */
1023 combine_instructions (rtx f, unsigned int nregs)
1029 rtx links, nextlinks;
1032 int new_direct_jump_p = 0;
1034 for (first = f; first && !INSN_P (first); )
1035 first = NEXT_INSN (first);
1039 combine_attempts = 0;
1042 combine_successes = 0;
1044 rtl_hooks = combine_rtl_hooks;
1046 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1048 init_recog_no_volatile ();
1050 /* Allocate array for insn info. */
1051 max_uid_known = get_max_uid ();
1052 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1053 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1055 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1057 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1058 problems when, for example, we have j <<= 1 in a loop. */
1060 nonzero_sign_valid = 0;
1062 /* Scan all SETs and see if we can deduce anything about what
1063 bits are known to be zero for some registers and how many copies
1064 of the sign bit are known to exist for those registers.
1066 Also set any known values so that we can use it while searching
1067 for what bits are known to be set. */
1069 setup_incoming_promotions (first);
1071 create_log_links ();
1072 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1073 FOR_EACH_BB (this_basic_block)
1075 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1078 label_tick = this_basic_block->index;
1079 if (!single_pred_p (this_basic_block)
1080 || single_pred (this_basic_block)->index != label_tick - 1)
1081 label_tick_ebb_start = label_tick;
1082 FOR_BB_INSNS (this_basic_block, insn)
1083 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1085 subst_low_luid = DF_INSN_LUID (insn);
1088 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1090 record_dead_and_set_regs (insn);
1093 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1094 if (REG_NOTE_KIND (links) == REG_INC)
1095 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1099 /* Record the current insn_rtx_cost of this instruction. */
1100 if (NONJUMP_INSN_P (insn))
1101 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1102 optimize_this_for_speed_p);
1104 fprintf(dump_file, "insn_cost %d: %d\n",
1105 INSN_UID (insn), INSN_COST (insn));
1109 nonzero_sign_valid = 1;
1111 /* Now scan all the insns in forward order. */
1113 label_tick_ebb_start = ENTRY_BLOCK_PTR->index;
1115 setup_incoming_promotions (first);
1117 FOR_EACH_BB (this_basic_block)
1119 optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1122 label_tick = this_basic_block->index;
1123 if (!single_pred_p (this_basic_block)
1124 || single_pred (this_basic_block)->index != label_tick - 1)
1125 label_tick_ebb_start = label_tick;
1126 rtl_profile_for_bb (this_basic_block);
1127 for (insn = BB_HEAD (this_basic_block);
1128 insn != NEXT_INSN (BB_END (this_basic_block));
1129 insn = next ? next : NEXT_INSN (insn))
1134 /* See if we know about function return values before this
1135 insn based upon SUBREG flags. */
1136 check_promoted_subreg (insn, PATTERN (insn));
1138 /* See if we can find hardregs and subreg of pseudos in
1139 narrower modes. This could help turning TRUNCATEs
1141 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1143 /* Try this insn with each insn it links back to. */
1145 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1146 if ((next = try_combine (insn, XEXP (links, 0),
1147 NULL_RTX, &new_direct_jump_p)) != 0)
1150 /* Try each sequence of three linked insns ending with this one. */
1152 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1154 rtx link = XEXP (links, 0);
1156 /* If the linked insn has been replaced by a note, then there
1157 is no point in pursuing this chain any further. */
1161 for (nextlinks = LOG_LINKS (link);
1163 nextlinks = XEXP (nextlinks, 1))
1164 if ((next = try_combine (insn, link,
1165 XEXP (nextlinks, 0),
1166 &new_direct_jump_p)) != 0)
1171 /* Try to combine a jump insn that uses CC0
1172 with a preceding insn that sets CC0, and maybe with its
1173 logical predecessor as well.
1174 This is how we make decrement-and-branch insns.
1175 We need this special code because data flow connections
1176 via CC0 do not get entered in LOG_LINKS. */
1179 && (prev = prev_nonnote_insn (insn)) != 0
1180 && NONJUMP_INSN_P (prev)
1181 && sets_cc0_p (PATTERN (prev)))
1183 if ((next = try_combine (insn, prev,
1184 NULL_RTX, &new_direct_jump_p)) != 0)
1187 for (nextlinks = LOG_LINKS (prev); nextlinks;
1188 nextlinks = XEXP (nextlinks, 1))
1189 if ((next = try_combine (insn, prev,
1190 XEXP (nextlinks, 0),
1191 &new_direct_jump_p)) != 0)
1195 /* Do the same for an insn that explicitly references CC0. */
1196 if (NONJUMP_INSN_P (insn)
1197 && (prev = prev_nonnote_insn (insn)) != 0
1198 && NONJUMP_INSN_P (prev)
1199 && sets_cc0_p (PATTERN (prev))
1200 && GET_CODE (PATTERN (insn)) == SET
1201 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1203 if ((next = try_combine (insn, prev,
1204 NULL_RTX, &new_direct_jump_p)) != 0)
1207 for (nextlinks = LOG_LINKS (prev); nextlinks;
1208 nextlinks = XEXP (nextlinks, 1))
1209 if ((next = try_combine (insn, prev,
1210 XEXP (nextlinks, 0),
1211 &new_direct_jump_p)) != 0)
1215 /* Finally, see if any of the insns that this insn links to
1216 explicitly references CC0. If so, try this insn, that insn,
1217 and its predecessor if it sets CC0. */
1218 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1219 if (NONJUMP_INSN_P (XEXP (links, 0))
1220 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1221 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1222 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1223 && NONJUMP_INSN_P (prev)
1224 && sets_cc0_p (PATTERN (prev))
1225 && (next = try_combine (insn, XEXP (links, 0),
1226 prev, &new_direct_jump_p)) != 0)
1230 /* Try combining an insn with two different insns whose results it
1232 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1233 for (nextlinks = XEXP (links, 1); nextlinks;
1234 nextlinks = XEXP (nextlinks, 1))
1235 if ((next = try_combine (insn, XEXP (links, 0),
1236 XEXP (nextlinks, 0),
1237 &new_direct_jump_p)) != 0)
1240 /* Try this insn with each REG_EQUAL note it links back to. */
1241 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1244 rtx temp = XEXP (links, 0);
1245 if ((set = single_set (temp)) != 0
1246 && (note = find_reg_equal_equiv_note (temp)) != 0
1247 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1248 /* Avoid using a register that may already been marked
1249 dead by an earlier instruction. */
1250 && ! unmentioned_reg_p (note, SET_SRC (set))
1251 && (GET_MODE (note) == VOIDmode
1252 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1253 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1255 /* Temporarily replace the set's source with the
1256 contents of the REG_EQUAL note. The insn will
1257 be deleted or recognized by try_combine. */
1258 rtx orig = SET_SRC (set);
1259 SET_SRC (set) = note;
1261 i2mod_old_rhs = copy_rtx (orig);
1262 i2mod_new_rhs = copy_rtx (note);
1263 next = try_combine (insn, i2mod, NULL_RTX,
1264 &new_direct_jump_p);
1268 SET_SRC (set) = orig;
1273 record_dead_and_set_regs (insn);
1281 default_rtl_profile ();
1284 new_direct_jump_p |= purge_all_dead_edges ();
1285 delete_noop_moves ();
1288 free (uid_log_links);
1289 free (uid_insn_cost);
1290 VEC_free (reg_stat_type, heap, reg_stat);
1293 struct undo *undo, *next;
1294 for (undo = undobuf.frees; undo; undo = next)
1302 total_attempts += combine_attempts;
1303 total_merges += combine_merges;
1304 total_extras += combine_extras;
1305 total_successes += combine_successes;
1307 nonzero_sign_valid = 0;
1308 rtl_hooks = general_rtl_hooks;
1310 /* Make recognizer allow volatile MEMs again. */
1313 return new_direct_jump_p;
1316 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1319 init_reg_last (void)
1324 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1325 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1328 /* Set up any promoted values for incoming argument registers. */
1331 setup_incoming_promotions (rtx first)
1334 bool strictly_local = false;
1336 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1339 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1340 arg = TREE_CHAIN (arg))
1342 rtx reg = DECL_INCOMING_RTL (arg);
1344 enum machine_mode mode1, mode2, mode3, mode4;
1346 /* Only continue if the incoming argument is in a register. */
1350 /* Determine, if possible, whether all call sites of the current
1351 function lie within the current compilation unit. (This does
1352 take into account the exporting of a function via taking its
1353 address, and so forth.) */
1354 strictly_local = cgraph_local_info (current_function_decl)->local;
1356 /* The mode and signedness of the argument before any promotions happen
1357 (equal to the mode of the pseudo holding it at that stage). */
1358 mode1 = TYPE_MODE (TREE_TYPE (arg));
1359 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1361 /* The mode and signedness of the argument after any source language and
1362 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1363 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1364 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1366 /* The mode and signedness of the argument as it is actually passed,
1367 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1368 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1370 /* The mode of the register in which the argument is being passed. */
1371 mode4 = GET_MODE (reg);
1373 /* Eliminate sign extensions in the callee when possible. Only
1375 (a) a mode promotion has occurred;
1376 (b) the mode of the register is the same as the mode of
1377 the argument as it is passed; and
1378 (c) the signedness does not change across any of the promotions; and
1379 (d) when no language-level promotions (which we cannot guarantee
1380 will have been done by an external caller) are necessary,
1381 unless we know that this function is only ever called from
1382 the current compilation unit -- all of whose call sites will
1383 do the mode1 --> mode2 promotion. */
1387 && (mode1 == mode2 || strictly_local))
1389 /* Record that the value was promoted from mode1 to mode3,
1390 so that any sign extension at the head of the current
1391 function may be eliminated. */
1393 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1394 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1395 record_value_for_reg (reg, first, x);
1400 /* Called via note_stores. If X is a pseudo that is narrower than
1401 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1403 If we are setting only a portion of X and we can't figure out what
1404 portion, assume all bits will be used since we don't know what will
1407 Similarly, set how many bits of X are known to be copies of the sign bit
1408 at all locations in the function. This is the smallest number implied
1412 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1414 rtx insn = (rtx) data;
1418 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1419 /* If this register is undefined at the start of the file, we can't
1420 say what its contents were. */
1421 && ! REGNO_REG_SET_P
1422 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1423 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1425 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1427 if (set == 0 || GET_CODE (set) == CLOBBER)
1429 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1430 rsp->sign_bit_copies = 1;
1434 /* If this register is being initialized using itself, and the
1435 register is uninitialized in this basic block, and there are
1436 no LOG_LINKS which set the register, then part of the
1437 register is uninitialized. In that case we can't assume
1438 anything about the number of nonzero bits.
1440 ??? We could do better if we checked this in
1441 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1442 could avoid making assumptions about the insn which initially
1443 sets the register, while still using the information in other
1444 insns. We would have to be careful to check every insn
1445 involved in the combination. */
1448 && reg_referenced_p (x, PATTERN (insn))
1449 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1454 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1456 if (dead_or_set_p (XEXP (link, 0), x))
1461 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1462 rsp->sign_bit_copies = 1;
1467 /* If this is a complex assignment, see if we can convert it into a
1468 simple assignment. */
1469 set = expand_field_assignment (set);
1471 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1472 set what we know about X. */
1474 if (SET_DEST (set) == x
1475 || (GET_CODE (SET_DEST (set)) == SUBREG
1476 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1477 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1478 && SUBREG_REG (SET_DEST (set)) == x))
1480 rtx src = SET_SRC (set);
1482 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1483 /* If X is narrower than a word and SRC is a non-negative
1484 constant that would appear negative in the mode of X,
1485 sign-extend it for use in reg_stat[].nonzero_bits because some
1486 machines (maybe most) will actually do the sign-extension
1487 and this is the conservative approach.
1489 ??? For 2.5, try to tighten up the MD files in this regard
1490 instead of this kludge. */
1492 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1493 && CONST_INT_P (src)
1495 && 0 != (INTVAL (src)
1496 & ((HOST_WIDE_INT) 1
1497 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1498 src = GEN_INT (INTVAL (src)
1499 | ((HOST_WIDE_INT) (-1)
1500 << GET_MODE_BITSIZE (GET_MODE (x))));
1503 /* Don't call nonzero_bits if it cannot change anything. */
1504 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1505 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1506 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1507 if (rsp->sign_bit_copies == 0
1508 || rsp->sign_bit_copies > num)
1509 rsp->sign_bit_copies = num;
1513 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1514 rsp->sign_bit_copies = 1;
1519 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1520 insns that were previously combined into I3 or that will be combined
1521 into the merger of INSN and I3.
1523 Return 0 if the combination is not allowed for any reason.
1525 If the combination is allowed, *PDEST will be set to the single
1526 destination of INSN and *PSRC to the single source, and this function
1530 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1531 rtx *pdest, rtx *psrc)
1540 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1541 && next_active_insn (succ) == i3)
1542 : next_active_insn (insn) == i3);
1544 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1545 or a PARALLEL consisting of such a SET and CLOBBERs.
1547 If INSN has CLOBBER parallel parts, ignore them for our processing.
1548 By definition, these happen during the execution of the insn. When it
1549 is merged with another insn, all bets are off. If they are, in fact,
1550 needed and aren't also supplied in I3, they may be added by
1551 recog_for_combine. Otherwise, it won't match.
1553 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1556 Get the source and destination of INSN. If more than one, can't
1559 if (GET_CODE (PATTERN (insn)) == SET)
1560 set = PATTERN (insn);
1561 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1562 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1564 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1566 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1569 switch (GET_CODE (elt))
1571 /* This is important to combine floating point insns
1572 for the SH4 port. */
1574 /* Combining an isolated USE doesn't make sense.
1575 We depend here on combinable_i3pat to reject them. */
1576 /* The code below this loop only verifies that the inputs of
1577 the SET in INSN do not change. We call reg_set_between_p
1578 to verify that the REG in the USE does not change between
1580 If the USE in INSN was for a pseudo register, the matching
1581 insn pattern will likely match any register; combining this
1582 with any other USE would only be safe if we knew that the
1583 used registers have identical values, or if there was
1584 something to tell them apart, e.g. different modes. For
1585 now, we forgo such complicated tests and simply disallow
1586 combining of USES of pseudo registers with any other USE. */
1587 if (REG_P (XEXP (elt, 0))
1588 && GET_CODE (PATTERN (i3)) == PARALLEL)
1590 rtx i3pat = PATTERN (i3);
1591 int i = XVECLEN (i3pat, 0) - 1;
1592 unsigned int regno = REGNO (XEXP (elt, 0));
1596 rtx i3elt = XVECEXP (i3pat, 0, i);
1598 if (GET_CODE (i3elt) == USE
1599 && REG_P (XEXP (i3elt, 0))
1600 && (REGNO (XEXP (i3elt, 0)) == regno
1601 ? reg_set_between_p (XEXP (elt, 0),
1602 PREV_INSN (insn), i3)
1603 : regno >= FIRST_PSEUDO_REGISTER))
1610 /* We can ignore CLOBBERs. */
1615 /* Ignore SETs whose result isn't used but not those that
1616 have side-effects. */
1617 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1618 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1619 || INTVAL (XEXP (note, 0)) <= 0)
1620 && ! side_effects_p (elt))
1623 /* If we have already found a SET, this is a second one and
1624 so we cannot combine with this insn. */
1632 /* Anything else means we can't combine. */
1638 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1639 so don't do anything with it. */
1640 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1649 set = expand_field_assignment (set);
1650 src = SET_SRC (set), dest = SET_DEST (set);
1652 /* Don't eliminate a store in the stack pointer. */
1653 if (dest == stack_pointer_rtx
1654 /* Don't combine with an insn that sets a register to itself if it has
1655 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1656 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1657 /* Can't merge an ASM_OPERANDS. */
1658 || GET_CODE (src) == ASM_OPERANDS
1659 /* Can't merge a function call. */
1660 || GET_CODE (src) == CALL
1661 /* Don't eliminate a function call argument. */
1663 && (find_reg_fusage (i3, USE, dest)
1665 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1666 && global_regs[REGNO (dest)])))
1667 /* Don't substitute into an incremented register. */
1668 || FIND_REG_INC_NOTE (i3, dest)
1669 || (succ && FIND_REG_INC_NOTE (succ, dest))
1670 /* Don't substitute into a non-local goto, this confuses CFG. */
1671 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1672 /* Make sure that DEST is not used after SUCC but before I3. */
1673 || (succ && ! all_adjacent
1674 && reg_used_between_p (dest, succ, i3))
1675 /* Make sure that the value that is to be substituted for the register
1676 does not use any registers whose values alter in between. However,
1677 If the insns are adjacent, a use can't cross a set even though we
1678 think it might (this can happen for a sequence of insns each setting
1679 the same destination; last_set of that register might point to
1680 a NOTE). If INSN has a REG_EQUIV note, the register is always
1681 equivalent to the memory so the substitution is valid even if there
1682 are intervening stores. Also, don't move a volatile asm or
1683 UNSPEC_VOLATILE across any other insns. */
1686 || ! find_reg_note (insn, REG_EQUIV, src))
1687 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1688 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1689 || GET_CODE (src) == UNSPEC_VOLATILE))
1690 /* Don't combine across a CALL_INSN, because that would possibly
1691 change whether the life span of some REGs crosses calls or not,
1692 and it is a pain to update that information.
1693 Exception: if source is a constant, moving it later can't hurt.
1694 Accept that as a special case. */
1695 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1698 /* DEST must either be a REG or CC0. */
1701 /* If register alignment is being enforced for multi-word items in all
1702 cases except for parameters, it is possible to have a register copy
1703 insn referencing a hard register that is not allowed to contain the
1704 mode being copied and which would not be valid as an operand of most
1705 insns. Eliminate this problem by not combining with such an insn.
1707 Also, on some machines we don't want to extend the life of a hard
1711 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1712 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1713 /* Don't extend the life of a hard register unless it is
1714 user variable (if we have few registers) or it can't
1715 fit into the desired register (meaning something special
1717 Also avoid substituting a return register into I3, because
1718 reload can't handle a conflict with constraints of other
1720 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1721 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1724 else if (GET_CODE (dest) != CC0)
1728 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1729 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1730 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1732 /* Don't substitute for a register intended as a clobberable
1734 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1735 if (rtx_equal_p (reg, dest))
1738 /* If the clobber represents an earlyclobber operand, we must not
1739 substitute an expression containing the clobbered register.
1740 As we do not analyze the constraint strings here, we have to
1741 make the conservative assumption. However, if the register is
1742 a fixed hard reg, the clobber cannot represent any operand;
1743 we leave it up to the machine description to either accept or
1744 reject use-and-clobber patterns. */
1746 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1747 || !fixed_regs[REGNO (reg)])
1748 if (reg_overlap_mentioned_p (reg, src))
1752 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1753 or not), reject, unless nothing volatile comes between it and I3 */
1755 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1757 /* Make sure succ doesn't contain a volatile reference. */
1758 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1761 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1762 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1766 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1767 to be an explicit register variable, and was chosen for a reason. */
1769 if (GET_CODE (src) == ASM_OPERANDS
1770 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1773 /* If there are any volatile insns between INSN and I3, reject, because
1774 they might affect machine state. */
1776 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1777 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1780 /* If INSN contains an autoincrement or autodecrement, make sure that
1781 register is not used between there and I3, and not already used in
1782 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1783 Also insist that I3 not be a jump; if it were one
1784 and the incremented register were spilled, we would lose. */
1787 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1788 if (REG_NOTE_KIND (link) == REG_INC
1790 || reg_used_between_p (XEXP (link, 0), insn, i3)
1791 || (pred != NULL_RTX
1792 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1793 || (succ != NULL_RTX
1794 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1795 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1800 /* Don't combine an insn that follows a CC0-setting insn.
1801 An insn that uses CC0 must not be separated from the one that sets it.
1802 We do, however, allow I2 to follow a CC0-setting insn if that insn
1803 is passed as I1; in that case it will be deleted also.
1804 We also allow combining in this case if all the insns are adjacent
1805 because that would leave the two CC0 insns adjacent as well.
1806 It would be more logical to test whether CC0 occurs inside I1 or I2,
1807 but that would be much slower, and this ought to be equivalent. */
1809 p = prev_nonnote_insn (insn);
1810 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1815 /* If we get here, we have passed all the tests and the combination is
1824 /* LOC is the location within I3 that contains its pattern or the component
1825 of a PARALLEL of the pattern. We validate that it is valid for combining.
1827 One problem is if I3 modifies its output, as opposed to replacing it
1828 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1829 so would produce an insn that is not equivalent to the original insns.
1833 (set (reg:DI 101) (reg:DI 100))
1834 (set (subreg:SI (reg:DI 101) 0) <foo>)
1836 This is NOT equivalent to:
1838 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1839 (set (reg:DI 101) (reg:DI 100))])
1841 Not only does this modify 100 (in which case it might still be valid
1842 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1844 We can also run into a problem if I2 sets a register that I1
1845 uses and I1 gets directly substituted into I3 (not via I2). In that
1846 case, we would be getting the wrong value of I2DEST into I3, so we
1847 must reject the combination. This case occurs when I2 and I1 both
1848 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1849 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1850 of a SET must prevent combination from occurring.
1852 Before doing the above check, we first try to expand a field assignment
1853 into a set of logical operations.
1855 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1856 we place a register that is both set and used within I3. If more than one
1857 such register is detected, we fail.
1859 Return 1 if the combination is valid, zero otherwise. */
1862 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1863 int i1_not_in_src, rtx *pi3dest_killed)
1867 if (GET_CODE (x) == SET)
1870 rtx dest = SET_DEST (set);
1871 rtx src = SET_SRC (set);
1872 rtx inner_dest = dest;
1875 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1876 || GET_CODE (inner_dest) == SUBREG
1877 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1878 inner_dest = XEXP (inner_dest, 0);
1880 /* Check for the case where I3 modifies its output, as discussed
1881 above. We don't want to prevent pseudos from being combined
1882 into the address of a MEM, so only prevent the combination if
1883 i1 or i2 set the same MEM. */
1884 if ((inner_dest != dest &&
1885 (!MEM_P (inner_dest)
1886 || rtx_equal_p (i2dest, inner_dest)
1887 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1888 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1889 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1891 /* This is the same test done in can_combine_p except we can't test
1892 all_adjacent; we don't have to, since this instruction will stay
1893 in place, thus we are not considering increasing the lifetime of
1896 Also, if this insn sets a function argument, combining it with
1897 something that might need a spill could clobber a previous
1898 function argument; the all_adjacent test in can_combine_p also
1899 checks this; here, we do a more specific test for this case. */
1901 || (REG_P (inner_dest)
1902 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1903 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1904 GET_MODE (inner_dest))))
1905 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1908 /* If DEST is used in I3, it is being killed in this insn, so
1909 record that for later. We have to consider paradoxical
1910 subregs here, since they kill the whole register, but we
1911 ignore partial subregs, STRICT_LOW_PART, etc.
1912 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1913 STACK_POINTER_REGNUM, since these are always considered to be
1914 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1916 if (GET_CODE (subdest) == SUBREG
1917 && (GET_MODE_SIZE (GET_MODE (subdest))
1918 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1919 subdest = SUBREG_REG (subdest);
1922 && reg_referenced_p (subdest, PATTERN (i3))
1923 && REGNO (subdest) != FRAME_POINTER_REGNUM
1924 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1925 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1927 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1928 && (REGNO (subdest) != ARG_POINTER_REGNUM
1929 || ! fixed_regs [REGNO (subdest)])
1931 && REGNO (subdest) != STACK_POINTER_REGNUM)
1933 if (*pi3dest_killed)
1936 *pi3dest_killed = subdest;
1940 else if (GET_CODE (x) == PARALLEL)
1944 for (i = 0; i < XVECLEN (x, 0); i++)
1945 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1946 i1_not_in_src, pi3dest_killed))
1953 /* Return 1 if X is an arithmetic expression that contains a multiplication
1954 and division. We don't count multiplications by powers of two here. */
1957 contains_muldiv (rtx x)
1959 switch (GET_CODE (x))
1961 case MOD: case DIV: case UMOD: case UDIV:
1965 return ! (CONST_INT_P (XEXP (x, 1))
1966 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1969 return contains_muldiv (XEXP (x, 0))
1970 || contains_muldiv (XEXP (x, 1));
1973 return contains_muldiv (XEXP (x, 0));
1979 /* Determine whether INSN can be used in a combination. Return nonzero if
1980 not. This is used in try_combine to detect early some cases where we
1981 can't perform combinations. */
1984 cant_combine_insn_p (rtx insn)
1989 /* If this isn't really an insn, we can't do anything.
1990 This can occur when flow deletes an insn that it has merged into an
1991 auto-increment address. */
1992 if (! INSN_P (insn))
1995 /* Never combine loads and stores involving hard regs that are likely
1996 to be spilled. The register allocator can usually handle such
1997 reg-reg moves by tying. If we allow the combiner to make
1998 substitutions of likely-spilled regs, reload might die.
1999 As an exception, we allow combinations involving fixed regs; these are
2000 not available to the register allocator so there's no risk involved. */
2002 set = single_set (insn);
2005 src = SET_SRC (set);
2006 dest = SET_DEST (set);
2007 if (GET_CODE (src) == SUBREG)
2008 src = SUBREG_REG (src);
2009 if (GET_CODE (dest) == SUBREG)
2010 dest = SUBREG_REG (dest);
2011 if (REG_P (src) && REG_P (dest)
2012 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2013 && ! fixed_regs[REGNO (src)]
2014 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2015 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2016 && ! fixed_regs[REGNO (dest)]
2017 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2023 struct likely_spilled_retval_info
2025 unsigned regno, nregs;
2029 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2030 hard registers that are known to be written to / clobbered in full. */
2032 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2034 struct likely_spilled_retval_info *const info =
2035 (struct likely_spilled_retval_info *) data;
2036 unsigned regno, nregs;
2039 if (!REG_P (XEXP (set, 0)))
2042 if (regno >= info->regno + info->nregs)
2044 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2045 if (regno + nregs <= info->regno)
2047 new_mask = (2U << (nregs - 1)) - 1;
2048 if (regno < info->regno)
2049 new_mask >>= info->regno - regno;
2051 new_mask <<= regno - info->regno;
2052 info->mask &= ~new_mask;
2055 /* Return nonzero iff part of the return value is live during INSN, and
2056 it is likely spilled. This can happen when more than one insn is needed
2057 to copy the return value, e.g. when we consider to combine into the
2058 second copy insn for a complex value. */
2061 likely_spilled_retval_p (rtx insn)
2063 rtx use = BB_END (this_basic_block);
2065 unsigned regno, nregs;
2066 /* We assume here that no machine mode needs more than
2067 32 hard registers when the value overlaps with a register
2068 for which FUNCTION_VALUE_REGNO_P is true. */
2070 struct likely_spilled_retval_info info;
2072 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2074 reg = XEXP (PATTERN (use), 0);
2075 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2077 regno = REGNO (reg);
2078 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2081 mask = (2U << (nregs - 1)) - 1;
2083 /* Disregard parts of the return value that are set later. */
2087 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2089 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2092 /* Check if any of the (probably) live return value registers is
2097 if ((mask & 1 << nregs)
2098 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2104 /* Adjust INSN after we made a change to its destination.
2106 Changing the destination can invalidate notes that say something about
2107 the results of the insn and a LOG_LINK pointing to the insn. */
2110 adjust_for_new_dest (rtx insn)
2112 /* For notes, be conservative and simply remove them. */
2113 remove_reg_equal_equiv_notes (insn);
2115 /* The new insn will have a destination that was previously the destination
2116 of an insn just above it. Call distribute_links to make a LOG_LINK from
2117 the next use of that destination. */
2118 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2120 df_insn_rescan (insn);
2123 /* Return TRUE if combine can reuse reg X in mode MODE.
2124 ADDED_SETS is nonzero if the original set is still required. */
2126 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2134 /* Allow hard registers if the new mode is legal, and occupies no more
2135 registers than the old mode. */
2136 if (regno < FIRST_PSEUDO_REGISTER)
2137 return (HARD_REGNO_MODE_OK (regno, mode)
2138 && (hard_regno_nregs[regno][GET_MODE (x)]
2139 >= hard_regno_nregs[regno][mode]));
2141 /* Or a pseudo that is only used once. */
2142 return (REG_N_SETS (regno) == 1 && !added_sets
2143 && !REG_USERVAR_P (x));
2147 /* Check whether X, the destination of a set, refers to part of
2148 the register specified by REG. */
2151 reg_subword_p (rtx x, rtx reg)
2153 /* Check that reg is an integer mode register. */
2154 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2157 if (GET_CODE (x) == STRICT_LOW_PART
2158 || GET_CODE (x) == ZERO_EXTRACT)
2161 return GET_CODE (x) == SUBREG
2162 && SUBREG_REG (x) == reg
2163 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2167 /* Delete the conditional jump INSN and adjust the CFG correspondingly.
2168 Note that the INSN should be deleted *after* removing dead edges, so
2169 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2170 but not for a (set (pc) (label_ref FOO)). */
2173 update_cfg_for_uncondjump (rtx insn)
2175 basic_block bb = BLOCK_FOR_INSN (insn);
2177 if (BB_END (bb) == insn)
2178 purge_dead_edges (bb);
2181 if (EDGE_COUNT (bb->succs) == 1)
2182 single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2186 /* Try to combine the insns I1 and I2 into I3.
2187 Here I1 and I2 appear earlier than I3.
2188 I1 can be zero; then we combine just I2 into I3.
2190 If we are combining three insns and the resulting insn is not recognized,
2191 try splitting it into two insns. If that happens, I2 and I3 are retained
2192 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2195 Return 0 if the combination does not work. Then nothing is changed.
2196 If we did the combination, return the insn at which combine should
2199 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2200 new direct jump instruction. */
2203 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2205 /* New patterns for I3 and I2, respectively. */
2206 rtx newpat, newi2pat = 0;
2207 rtvec newpat_vec_with_clobbers = 0;
2208 int substed_i2 = 0, substed_i1 = 0;
2209 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2210 int added_sets_1, added_sets_2;
2211 /* Total number of SETs to put into I3. */
2213 /* Nonzero if I2's body now appears in I3. */
2215 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2216 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2217 /* Contains I3 if the destination of I3 is used in its source, which means
2218 that the old life of I3 is being killed. If that usage is placed into
2219 I2 and not in I3, a REG_DEAD note must be made. */
2220 rtx i3dest_killed = 0;
2221 /* SET_DEST and SET_SRC of I2 and I1. */
2222 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2223 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2224 rtx i1pat = 0, i2pat = 0;
2225 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2226 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2227 int i2dest_killed = 0, i1dest_killed = 0;
2228 int i1_feeds_i3 = 0;
2229 /* Notes that must be added to REG_NOTES in I3 and I2. */
2230 rtx new_i3_notes, new_i2_notes;
2231 /* Notes that we substituted I3 into I2 instead of the normal case. */
2232 int i3_subst_into_i2 = 0;
2233 /* Notes that I1, I2 or I3 is a MULT operation. */
2236 int changed_i3_dest = 0;
2242 rtx new_other_notes;
2245 /* Exit early if one of the insns involved can't be used for
2247 if (cant_combine_insn_p (i3)
2248 || cant_combine_insn_p (i2)
2249 || (i1 && cant_combine_insn_p (i1))
2250 || likely_spilled_retval_p (i3))
2254 undobuf.other_insn = 0;
2256 /* Reset the hard register usage information. */
2257 CLEAR_HARD_REG_SET (newpat_used_regs);
2259 if (dump_file && (dump_flags & TDF_DETAILS))
2262 fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2263 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2265 fprintf (dump_file, "\nTrying %d -> %d:\n",
2266 INSN_UID (i2), INSN_UID (i3));
2269 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2270 code below, set I1 to be the earlier of the two insns. */
2271 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2272 temp = i1, i1 = i2, i2 = temp;
2274 added_links_insn = 0;
2276 /* First check for one important special-case that the code below will
2277 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2278 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2279 we may be able to replace that destination with the destination of I3.
2280 This occurs in the common code where we compute both a quotient and
2281 remainder into a structure, in which case we want to do the computation
2282 directly into the structure to avoid register-register copies.
2284 Note that this case handles both multiple sets in I2 and also
2285 cases where I2 has a number of CLOBBER or PARALLELs.
2287 We make very conservative checks below and only try to handle the
2288 most common cases of this. For example, we only handle the case
2289 where I2 and I3 are adjacent to avoid making difficult register
2292 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2293 && REG_P (SET_SRC (PATTERN (i3)))
2294 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2295 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2296 && GET_CODE (PATTERN (i2)) == PARALLEL
2297 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2298 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2299 below would need to check what is inside (and reg_overlap_mentioned_p
2300 doesn't support those codes anyway). Don't allow those destinations;
2301 the resulting insn isn't likely to be recognized anyway. */
2302 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2303 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2304 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2305 SET_DEST (PATTERN (i3)))
2306 && next_real_insn (i2) == i3)
2308 rtx p2 = PATTERN (i2);
2310 /* Make sure that the destination of I3,
2311 which we are going to substitute into one output of I2,
2312 is not used within another output of I2. We must avoid making this:
2313 (parallel [(set (mem (reg 69)) ...)
2314 (set (reg 69) ...)])
2315 which is not well-defined as to order of actions.
2316 (Besides, reload can't handle output reloads for this.)
2318 The problem can also happen if the dest of I3 is a memory ref,
2319 if another dest in I2 is an indirect memory ref. */
2320 for (i = 0; i < XVECLEN (p2, 0); i++)
2321 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2322 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2323 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2324 SET_DEST (XVECEXP (p2, 0, i))))
2327 if (i == XVECLEN (p2, 0))
2328 for (i = 0; i < XVECLEN (p2, 0); i++)
2329 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2330 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2331 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2336 subst_low_luid = DF_INSN_LUID (i2);
2338 added_sets_2 = added_sets_1 = 0;
2339 i2dest = SET_SRC (PATTERN (i3));
2340 i2dest_killed = dead_or_set_p (i2, i2dest);
2342 /* Replace the dest in I2 with our dest and make the resulting
2343 insn the new pattern for I3. Then skip to where we
2344 validate the pattern. Everything was set up above. */
2345 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2346 SET_DEST (PATTERN (i3)));
2349 i3_subst_into_i2 = 1;
2350 goto validate_replacement;
2354 /* If I2 is setting a pseudo to a constant and I3 is setting some
2355 sub-part of it to another constant, merge them by making a new
2358 && (temp = single_set (i2)) != 0
2359 && (CONST_INT_P (SET_SRC (temp))
2360 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2361 && GET_CODE (PATTERN (i3)) == SET
2362 && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2363 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2364 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2366 rtx dest = SET_DEST (PATTERN (i3));
2370 if (GET_CODE (dest) == ZERO_EXTRACT)
2372 if (CONST_INT_P (XEXP (dest, 1))
2373 && CONST_INT_P (XEXP (dest, 2)))
2375 width = INTVAL (XEXP (dest, 1));
2376 offset = INTVAL (XEXP (dest, 2));
2377 dest = XEXP (dest, 0);
2378 if (BITS_BIG_ENDIAN)
2379 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2384 if (GET_CODE (dest) == STRICT_LOW_PART)
2385 dest = XEXP (dest, 0);
2386 width = GET_MODE_BITSIZE (GET_MODE (dest));
2392 /* If this is the low part, we're done. */
2393 if (subreg_lowpart_p (dest))
2395 /* Handle the case where inner is twice the size of outer. */
2396 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2397 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2398 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2399 /* Otherwise give up for now. */
2405 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2406 <= HOST_BITS_PER_WIDE_INT * 2))
2408 HOST_WIDE_INT mhi, ohi, ihi;
2409 HOST_WIDE_INT mlo, olo, ilo;
2410 rtx inner = SET_SRC (PATTERN (i3));
2411 rtx outer = SET_SRC (temp);
2413 if (CONST_INT_P (outer))
2415 olo = INTVAL (outer);
2416 ohi = olo < 0 ? -1 : 0;
2420 olo = CONST_DOUBLE_LOW (outer);
2421 ohi = CONST_DOUBLE_HIGH (outer);
2424 if (CONST_INT_P (inner))
2426 ilo = INTVAL (inner);
2427 ihi = ilo < 0 ? -1 : 0;
2431 ilo = CONST_DOUBLE_LOW (inner);
2432 ihi = CONST_DOUBLE_HIGH (inner);
2435 if (width < HOST_BITS_PER_WIDE_INT)
2437 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2440 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2442 mhi = ((unsigned HOST_WIDE_INT) 1
2443 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2455 if (offset >= HOST_BITS_PER_WIDE_INT)
2457 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2459 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2462 else if (offset > 0)
2464 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2465 >> (HOST_BITS_PER_WIDE_INT - offset));
2466 mlo = mlo << offset;
2467 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2468 >> (HOST_BITS_PER_WIDE_INT - offset));
2469 ilo = ilo << offset;
2472 olo = (olo & ~mlo) | ilo;
2473 ohi = (ohi & ~mhi) | ihi;
2477 subst_low_luid = DF_INSN_LUID (i2);
2478 added_sets_2 = added_sets_1 = 0;
2479 i2dest = SET_DEST (temp);
2480 i2dest_killed = dead_or_set_p (i2, i2dest);
2482 SUBST (SET_SRC (temp),
2483 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2485 newpat = PATTERN (i2);
2486 goto validate_replacement;
2491 /* If we have no I1 and I2 looks like:
2492 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2494 make up a dummy I1 that is
2497 (set (reg:CC X) (compare:CC Y (const_int 0)))
2499 (We can ignore any trailing CLOBBERs.)
2501 This undoes a previous combination and allows us to match a branch-and-
2504 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2505 && XVECLEN (PATTERN (i2), 0) >= 2
2506 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2507 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2509 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2510 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2511 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2512 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2513 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2514 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2516 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2517 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2522 /* We make I1 with the same INSN_UID as I2. This gives it
2523 the same DF_INSN_LUID for value tracking. Our fake I1 will
2524 never appear in the insn stream so giving it the same INSN_UID
2525 as I2 will not cause a problem. */
2527 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2528 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2529 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2531 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2532 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2533 SET_DEST (PATTERN (i1)));
2538 /* Verify that I2 and I1 are valid for combining. */
2539 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2540 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2546 /* Record whether I2DEST is used in I2SRC and similarly for the other
2547 cases. Knowing this will help in register status updating below. */
2548 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2549 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2550 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2551 i2dest_killed = dead_or_set_p (i2, i2dest);
2552 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2554 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2556 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2558 /* Ensure that I3's pattern can be the destination of combines. */
2559 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2560 i1 && i2dest_in_i1src && i1_feeds_i3,
2567 /* See if any of the insns is a MULT operation. Unless one is, we will
2568 reject a combination that is, since it must be slower. Be conservative
2570 if (GET_CODE (i2src) == MULT
2571 || (i1 != 0 && GET_CODE (i1src) == MULT)
2572 || (GET_CODE (PATTERN (i3)) == SET
2573 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2576 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2577 We used to do this EXCEPT in one case: I3 has a post-inc in an
2578 output operand. However, that exception can give rise to insns like
2580 which is a famous insn on the PDP-11 where the value of r3 used as the
2581 source was model-dependent. Avoid this sort of thing. */
2584 if (!(GET_CODE (PATTERN (i3)) == SET
2585 && REG_P (SET_SRC (PATTERN (i3)))
2586 && MEM_P (SET_DEST (PATTERN (i3)))
2587 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2588 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2589 /* It's not the exception. */
2592 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2593 if (REG_NOTE_KIND (link) == REG_INC
2594 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2596 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2603 /* See if the SETs in I1 or I2 need to be kept around in the merged
2604 instruction: whenever the value set there is still needed past I3.
2605 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2607 For the SET in I1, we have two cases: If I1 and I2 independently
2608 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2609 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2610 in I1 needs to be kept around unless I1DEST dies or is set in either
2611 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2612 I1DEST. If so, we know I1 feeds into I2. */
2614 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2617 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2618 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2620 /* If the set in I2 needs to be kept around, we must make a copy of
2621 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2622 PATTERN (I2), we are only substituting for the original I1DEST, not into
2623 an already-substituted copy. This also prevents making self-referential
2624 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2629 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2630 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2632 i2pat = copy_rtx (PATTERN (i2));
2637 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2638 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2640 i1pat = copy_rtx (PATTERN (i1));
2645 /* Substitute in the latest insn for the regs set by the earlier ones. */
2647 maxreg = max_reg_num ();
2652 /* Many machines that don't use CC0 have insns that can both perform an
2653 arithmetic operation and set the condition code. These operations will
2654 be represented as a PARALLEL with the first element of the vector
2655 being a COMPARE of an arithmetic operation with the constant zero.
2656 The second element of the vector will set some pseudo to the result
2657 of the same arithmetic operation. If we simplify the COMPARE, we won't
2658 match such a pattern and so will generate an extra insn. Here we test
2659 for this case, where both the comparison and the operation result are
2660 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2661 I2SRC. Later we will make the PARALLEL that contains I2. */
2663 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2664 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2665 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2666 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2668 #ifdef SELECT_CC_MODE
2670 enum machine_mode compare_mode;
2673 newpat = PATTERN (i3);
2674 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2678 #ifdef SELECT_CC_MODE
2679 /* See if a COMPARE with the operand we substituted in should be done
2680 with the mode that is currently being used. If not, do the same
2681 processing we do in `subst' for a SET; namely, if the destination
2682 is used only once, try to replace it with a register of the proper
2683 mode and also replace the COMPARE. */
2684 if (undobuf.other_insn == 0
2685 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2686 &undobuf.other_insn))
2687 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2689 != GET_MODE (SET_DEST (newpat))))
2691 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2694 unsigned int regno = REGNO (SET_DEST (newpat));
2697 if (regno < FIRST_PSEUDO_REGISTER)
2698 new_dest = gen_rtx_REG (compare_mode, regno);
2701 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2702 new_dest = regno_reg_rtx[regno];
2705 SUBST (SET_DEST (newpat), new_dest);
2706 SUBST (XEXP (*cc_use, 0), new_dest);
2707 SUBST (SET_SRC (newpat),
2708 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2711 undobuf.other_insn = 0;
2718 /* It is possible that the source of I2 or I1 may be performing
2719 an unneeded operation, such as a ZERO_EXTEND of something
2720 that is known to have the high part zero. Handle that case
2721 by letting subst look at the innermost one of them.
2723 Another way to do this would be to have a function that tries
2724 to simplify a single insn instead of merging two or more
2725 insns. We don't do this because of the potential of infinite
2726 loops and because of the potential extra memory required.
2727 However, doing it the way we are is a bit of a kludge and
2728 doesn't catch all cases.
2730 But only do this if -fexpensive-optimizations since it slows
2731 things down and doesn't usually win.
2733 This is not done in the COMPARE case above because the
2734 unmodified I2PAT is used in the PARALLEL and so a pattern
2735 with a modified I2SRC would not match. */
2737 if (flag_expensive_optimizations)
2739 /* Pass pc_rtx so no substitutions are done, just
2743 subst_low_luid = DF_INSN_LUID (i1);
2744 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2748 subst_low_luid = DF_INSN_LUID (i2);
2749 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2753 n_occurrences = 0; /* `subst' counts here */
2755 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2756 need to make a unique copy of I2SRC each time we substitute it
2757 to avoid self-referential rtl. */
2759 subst_low_luid = DF_INSN_LUID (i2);
2760 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2761 ! i1_feeds_i3 && i1dest_in_i1src);
2764 /* Record whether i2's body now appears within i3's body. */
2765 i2_is_used = n_occurrences;
2768 /* If we already got a failure, don't try to do more. Otherwise,
2769 try to substitute in I1 if we have it. */
2771 if (i1 && GET_CODE (newpat) != CLOBBER)
2773 /* Check that an autoincrement side-effect on I1 has not been lost.
2774 This happens if I1DEST is mentioned in I2 and dies there, and
2775 has disappeared from the new pattern. */
2776 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2778 && dead_or_set_p (i2, i1dest)
2779 && !reg_overlap_mentioned_p (i1dest, newpat))
2780 /* Before we can do this substitution, we must redo the test done
2781 above (see detailed comments there) that ensures that I1DEST
2782 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2783 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2790 subst_low_luid = DF_INSN_LUID (i1);
2791 newpat = subst (newpat, i1dest, i1src, 0, 0);
2795 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2796 to count all the ways that I2SRC and I1SRC can be used. */
2797 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2798 && i2_is_used + added_sets_2 > 1)
2799 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2800 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2802 /* Fail if we tried to make a new register. */
2803 || max_reg_num () != maxreg
2804 /* Fail if we couldn't do something and have a CLOBBER. */
2805 || GET_CODE (newpat) == CLOBBER
2806 /* Fail if this new pattern is a MULT and we didn't have one before
2807 at the outer level. */
2808 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2815 /* If the actions of the earlier insns must be kept
2816 in addition to substituting them into the latest one,
2817 we must make a new PARALLEL for the latest insn
2818 to hold additional the SETs. */
2820 if (added_sets_1 || added_sets_2)
2824 if (GET_CODE (newpat) == PARALLEL)
2826 rtvec old = XVEC (newpat, 0);
2827 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2828 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2829 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2830 sizeof (old->elem[0]) * old->num_elem);
2835 total_sets = 1 + added_sets_1 + added_sets_2;
2836 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2837 XVECEXP (newpat, 0, 0) = old;
2841 XVECEXP (newpat, 0, --total_sets) = i1pat;
2845 /* If there is no I1, use I2's body as is. We used to also not do
2846 the subst call below if I2 was substituted into I3,
2847 but that could lose a simplification. */
2849 XVECEXP (newpat, 0, --total_sets) = i2pat;
2851 /* See comment where i2pat is assigned. */
2852 XVECEXP (newpat, 0, --total_sets)
2853 = subst (i2pat, i1dest, i1src, 0, 0);
2857 /* We come here when we are replacing a destination in I2 with the
2858 destination of I3. */
2859 validate_replacement:
2861 /* Note which hard regs this insn has as inputs. */
2862 mark_used_regs_combine (newpat);
2864 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2865 consider splitting this pattern, we might need these clobbers. */
2866 if (i1 && GET_CODE (newpat) == PARALLEL
2867 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2869 int len = XVECLEN (newpat, 0);
2871 newpat_vec_with_clobbers = rtvec_alloc (len);
2872 for (i = 0; i < len; i++)
2873 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2876 /* Is the result of combination a valid instruction? */
2877 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2879 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2880 the second SET's destination is a register that is unused and isn't
2881 marked as an instruction that might trap in an EH region. In that case,
2882 we just need the first SET. This can occur when simplifying a divmod
2883 insn. We *must* test for this case here because the code below that
2884 splits two independent SETs doesn't handle this case correctly when it
2885 updates the register status.
2887 It's pointless doing this if we originally had two sets, one from
2888 i3, and one from i2. Combining then splitting the parallel results
2889 in the original i2 again plus an invalid insn (which we delete).
2890 The net effect is only to move instructions around, which makes
2891 debug info less accurate.
2893 Also check the case where the first SET's destination is unused.
2894 That would not cause incorrect code, but does cause an unneeded
2897 if (insn_code_number < 0
2898 && !(added_sets_2 && i1 == 0)
2899 && GET_CODE (newpat) == PARALLEL
2900 && XVECLEN (newpat, 0) == 2
2901 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2902 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2903 && asm_noperands (newpat) < 0)
2905 rtx set0 = XVECEXP (newpat, 0, 0);
2906 rtx set1 = XVECEXP (newpat, 0, 1);
2909 if (((REG_P (SET_DEST (set1))
2910 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2911 || (GET_CODE (SET_DEST (set1)) == SUBREG
2912 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2913 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2914 || INTVAL (XEXP (note, 0)) <= 0)
2915 && ! side_effects_p (SET_SRC (set1)))
2918 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2921 else if (((REG_P (SET_DEST (set0))
2922 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2923 || (GET_CODE (SET_DEST (set0)) == SUBREG
2924 && find_reg_note (i3, REG_UNUSED,
2925 SUBREG_REG (SET_DEST (set0)))))
2926 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2927 || INTVAL (XEXP (note, 0)) <= 0)
2928 && ! side_effects_p (SET_SRC (set0)))
2931 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2933 if (insn_code_number >= 0)
2934 changed_i3_dest = 1;
2938 /* If we were combining three insns and the result is a simple SET
2939 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2940 insns. There are two ways to do this. It can be split using a
2941 machine-specific method (like when you have an addition of a large
2942 constant) or by combine in the function find_split_point. */
2944 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2945 && asm_noperands (newpat) < 0)
2947 rtx parallel, m_split, *split;
2949 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2950 use I2DEST as a scratch register will help. In the latter case,
2951 convert I2DEST to the mode of the source of NEWPAT if we can. */
2953 m_split = combine_split_insns (newpat, i3);
2955 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2956 inputs of NEWPAT. */
2958 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2959 possible to try that as a scratch reg. This would require adding
2960 more code to make it work though. */
2962 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2964 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2966 /* First try to split using the original register as a
2967 scratch register. */
2968 parallel = gen_rtx_PARALLEL (VOIDmode,
2969 gen_rtvec (2, newpat,
2970 gen_rtx_CLOBBER (VOIDmode,
2972 m_split = combine_split_insns (parallel, i3);
2974 /* If that didn't work, try changing the mode of I2DEST if
2977 && new_mode != GET_MODE (i2dest)
2978 && new_mode != VOIDmode
2979 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2981 enum machine_mode old_mode = GET_MODE (i2dest);
2984 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2985 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2988 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2989 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2992 parallel = (gen_rtx_PARALLEL
2994 gen_rtvec (2, newpat,
2995 gen_rtx_CLOBBER (VOIDmode,
2997 m_split = combine_split_insns (parallel, i3);
3000 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3004 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3005 buf = undobuf.undos;
3006 undobuf.undos = buf->next;
3007 buf->next = undobuf.frees;
3008 undobuf.frees = buf;
3013 /* If recog_for_combine has discarded clobbers, try to use them
3014 again for the split. */
3015 if (m_split == 0 && newpat_vec_with_clobbers)
3017 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3018 m_split = combine_split_insns (parallel, i3);
3021 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3023 m_split = PATTERN (m_split);
3024 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3025 if (insn_code_number >= 0)
3028 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3029 && (next_real_insn (i2) == i3
3030 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3033 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3034 newi2pat = PATTERN (m_split);
3036 i3set = single_set (NEXT_INSN (m_split));
3037 i2set = single_set (m_split);
3039 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3041 /* If I2 or I3 has multiple SETs, we won't know how to track
3042 register status, so don't use these insns. If I2's destination
3043 is used between I2 and I3, we also can't use these insns. */
3045 if (i2_code_number >= 0 && i2set && i3set
3046 && (next_real_insn (i2) == i3
3047 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3048 insn_code_number = recog_for_combine (&newi3pat, i3,
3050 if (insn_code_number >= 0)
3053 /* It is possible that both insns now set the destination of I3.
3054 If so, we must show an extra use of it. */
3056 if (insn_code_number >= 0)
3058 rtx new_i3_dest = SET_DEST (i3set);
3059 rtx new_i2_dest = SET_DEST (i2set);
3061 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3062 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3063 || GET_CODE (new_i3_dest) == SUBREG)
3064 new_i3_dest = XEXP (new_i3_dest, 0);
3066 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3067 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3068 || GET_CODE (new_i2_dest) == SUBREG)
3069 new_i2_dest = XEXP (new_i2_dest, 0);
3071 if (REG_P (new_i3_dest)
3072 && REG_P (new_i2_dest)
3073 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3074 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3078 /* If we can split it and use I2DEST, go ahead and see if that
3079 helps things be recognized. Verify that none of the registers
3080 are set between I2 and I3. */
3081 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3085 /* We need I2DEST in the proper mode. If it is a hard register
3086 or the only use of a pseudo, we can change its mode.
3087 Make sure we don't change a hard register to have a mode that
3088 isn't valid for it, or change the number of registers. */
3089 && (GET_MODE (*split) == GET_MODE (i2dest)
3090 || GET_MODE (*split) == VOIDmode
3091 || can_change_dest_mode (i2dest, added_sets_2,
3093 && (next_real_insn (i2) == i3
3094 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3095 /* We can't overwrite I2DEST if its value is still used by
3097 && ! reg_referenced_p (i2dest, newpat))
3099 rtx newdest = i2dest;
3100 enum rtx_code split_code = GET_CODE (*split);
3101 enum machine_mode split_mode = GET_MODE (*split);
3102 bool subst_done = false;
3103 newi2pat = NULL_RTX;
3105 /* Get NEWDEST as a register in the proper mode. We have already
3106 validated that we can do this. */
3107 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3109 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3110 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3113 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3114 newdest = regno_reg_rtx[REGNO (i2dest)];
3118 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3119 an ASHIFT. This can occur if it was inside a PLUS and hence
3120 appeared to be a memory address. This is a kludge. */
3121 if (split_code == MULT
3122 && CONST_INT_P (XEXP (*split, 1))
3123 && INTVAL (XEXP (*split, 1)) > 0
3124 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3126 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3127 XEXP (*split, 0), GEN_INT (i)));
3128 /* Update split_code because we may not have a multiply
3130 split_code = GET_CODE (*split);
3133 #ifdef INSN_SCHEDULING
3134 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3135 be written as a ZERO_EXTEND. */
3136 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3138 #ifdef LOAD_EXTEND_OP
3139 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3140 what it really is. */
3141 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3143 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3144 SUBREG_REG (*split)));
3147 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3148 SUBREG_REG (*split)));
3152 /* Attempt to split binary operators using arithmetic identities. */
3153 if (BINARY_P (SET_SRC (newpat))
3154 && split_mode == GET_MODE (SET_SRC (newpat))
3155 && ! side_effects_p (SET_SRC (newpat)))
3157 rtx setsrc = SET_SRC (newpat);
3158 enum machine_mode mode = GET_MODE (setsrc);
3159 enum rtx_code code = GET_CODE (setsrc);
3160 rtx src_op0 = XEXP (setsrc, 0);
3161 rtx src_op1 = XEXP (setsrc, 1);
3163 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3164 if (rtx_equal_p (src_op0, src_op1))
3166 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3167 SUBST (XEXP (setsrc, 0), newdest);
3168 SUBST (XEXP (setsrc, 1), newdest);
3171 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3172 else if ((code == PLUS || code == MULT)
3173 && GET_CODE (src_op0) == code
3174 && GET_CODE (XEXP (src_op0, 0)) == code
3175 && (INTEGRAL_MODE_P (mode)
3176 || (FLOAT_MODE_P (mode)
3177 && flag_unsafe_math_optimizations)))
3179 rtx p = XEXP (XEXP (src_op0, 0), 0);
3180 rtx q = XEXP (XEXP (src_op0, 0), 1);
3181 rtx r = XEXP (src_op0, 1);
3184 /* Split both "((X op Y) op X) op Y" and
3185 "((X op Y) op Y) op X" as "T op T" where T is
3187 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3188 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3190 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3192 SUBST (XEXP (setsrc, 0), newdest);
3193 SUBST (XEXP (setsrc, 1), newdest);
3196 /* Split "((X op X) op Y) op Y)" as "T op T" where
3198 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3200 rtx tmp = simplify_gen_binary (code, mode, p, r);
3201 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3202 SUBST (XEXP (setsrc, 0), newdest);
3203 SUBST (XEXP (setsrc, 1), newdest);
3211 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3212 SUBST (*split, newdest);
3215 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3217 /* recog_for_combine might have added CLOBBERs to newi2pat.
3218 Make sure NEWPAT does not depend on the clobbered regs. */
3219 if (GET_CODE (newi2pat) == PARALLEL)
3220 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3221 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3223 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3224 if (reg_overlap_mentioned_p (reg, newpat))
3231 /* If the split point was a MULT and we didn't have one before,
3232 don't use one now. */
3233 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3234 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3238 /* Check for a case where we loaded from memory in a narrow mode and
3239 then sign extended it, but we need both registers. In that case,
3240 we have a PARALLEL with both loads from the same memory location.
3241 We can split this into a load from memory followed by a register-register
3242 copy. This saves at least one insn, more if register allocation can
3245 We cannot do this if the destination of the first assignment is a
3246 condition code register or cc0. We eliminate this case by making sure
3247 the SET_DEST and SET_SRC have the same mode.
3249 We cannot do this if the destination of the second assignment is
3250 a register that we have already assumed is zero-extended. Similarly
3251 for a SUBREG of such a register. */
3253 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3254 && GET_CODE (newpat) == PARALLEL
3255 && XVECLEN (newpat, 0) == 2
3256 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3257 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3258 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3259 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3260 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3261 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3262 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3263 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3265 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3266 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3267 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3269 && VEC_index (reg_stat_type, reg_stat,
3270 REGNO (temp))->nonzero_bits != 0
3271 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3272 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3273 && (VEC_index (reg_stat_type, reg_stat,
3274 REGNO (temp))->nonzero_bits
3275 != GET_MODE_MASK (word_mode))))
3276 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3277 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3279 && VEC_index (reg_stat_type, reg_stat,
3280 REGNO (temp))->nonzero_bits != 0
3281 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3282 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3283 && (VEC_index (reg_stat_type, reg_stat,
3284 REGNO (temp))->nonzero_bits
3285 != GET_MODE_MASK (word_mode)))))
3286 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3287 SET_SRC (XVECEXP (newpat, 0, 1)))
3288 && ! find_reg_note (i3, REG_UNUSED,
3289 SET_DEST (XVECEXP (newpat, 0, 0))))
3293 newi2pat = XVECEXP (newpat, 0, 0);
3294 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3295 newpat = XVECEXP (newpat, 0, 1);
3296 SUBST (SET_SRC (newpat),
3297 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3298 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3300 if (i2_code_number >= 0)
3301 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3303 if (insn_code_number >= 0)
3307 /* Similarly, check for a case where we have a PARALLEL of two independent
3308 SETs but we started with three insns. In this case, we can do the sets
3309 as two separate insns. This case occurs when some SET allows two
3310 other insns to combine, but the destination of that SET is still live. */
3312 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3313 && GET_CODE (newpat) == PARALLEL
3314 && XVECLEN (newpat, 0) == 2
3315 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3316 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3317 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3318 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3319 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3320 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3321 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3323 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3324 XVECEXP (newpat, 0, 0))
3325 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3326 XVECEXP (newpat, 0, 1))
3327 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3328 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3330 /* We cannot split the parallel into two sets if both sets
3332 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3333 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3337 /* Normally, it doesn't matter which of the two is done first,
3338 but it does if one references cc0. In that case, it has to
3341 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3343 newi2pat = XVECEXP (newpat, 0, 0);
3344 newpat = XVECEXP (newpat, 0, 1);
3349 newi2pat = XVECEXP (newpat, 0, 1);
3350 newpat = XVECEXP (newpat, 0, 0);
3353 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3355 if (i2_code_number >= 0)
3356 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3359 /* If it still isn't recognized, fail and change things back the way they
3361 if ((insn_code_number < 0
3362 /* Is the result a reasonable ASM_OPERANDS? */
3363 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3369 /* If we had to change another insn, make sure it is valid also. */
3370 if (undobuf.other_insn)
3372 CLEAR_HARD_REG_SET (newpat_used_regs);
3374 other_pat = PATTERN (undobuf.other_insn);
3375 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3378 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3386 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3387 they are adjacent to each other or not. */
3389 rtx p = prev_nonnote_insn (i3);
3390 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3391 && sets_cc0_p (newi2pat))
3399 /* Only allow this combination if insn_rtx_costs reports that the
3400 replacement instructions are cheaper than the originals. */
3401 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3407 /* If we will be able to accept this, we have made a
3408 change to the destination of I3. This requires us to
3409 do a few adjustments. */
3411 if (changed_i3_dest)
3413 PATTERN (i3) = newpat;
3414 adjust_for_new_dest (i3);
3417 /* We now know that we can do this combination. Merge the insns and
3418 update the status of registers and LOG_LINKS. */
3420 if (undobuf.other_insn)
3424 PATTERN (undobuf.other_insn) = other_pat;
3426 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3427 are still valid. Then add any non-duplicate notes added by
3428 recog_for_combine. */
3429 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3431 next = XEXP (note, 1);
3433 if (REG_NOTE_KIND (note) == REG_UNUSED
3434 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3435 remove_note (undobuf.other_insn, note);
3438 distribute_notes (new_other_notes, undobuf.other_insn,
3439 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3448 /* I3 now uses what used to be its destination and which is now
3449 I2's destination. This requires us to do a few adjustments. */
3450 PATTERN (i3) = newpat;
3451 adjust_for_new_dest (i3);
3453 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3456 However, some later insn might be using I2's dest and have
3457 a LOG_LINK pointing at I3. We must remove this link.
3458 The simplest way to remove the link is to point it at I1,
3459 which we know will be a NOTE. */
3461 /* newi2pat is usually a SET here; however, recog_for_combine might
3462 have added some clobbers. */
3463 if (GET_CODE (newi2pat) == PARALLEL)
3464 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3466 ni2dest = SET_DEST (newi2pat);
3468 for (insn = NEXT_INSN (i3);
3469 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3470 || insn != BB_HEAD (this_basic_block->next_bb));
3471 insn = NEXT_INSN (insn))
3473 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3475 for (link = LOG_LINKS (insn); link;
3476 link = XEXP (link, 1))
3477 if (XEXP (link, 0) == i3)
3478 XEXP (link, 0) = i1;
3486 rtx i3notes, i2notes, i1notes = 0;
3487 rtx i3links, i2links, i1links = 0;
3490 /* Compute which registers we expect to eliminate. newi2pat may be setting
3491 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3492 same as i3dest, in which case newi2pat may be setting i1dest. */
3493 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3494 || i2dest_in_i2src || i2dest_in_i1src
3497 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3498 || (newi2pat && reg_set_p (i1dest, newi2pat))
3502 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3504 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3505 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3507 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3509 /* Ensure that we do not have something that should not be shared but
3510 occurs multiple times in the new insns. Check this by first
3511 resetting all the `used' flags and then copying anything is shared. */
3513 reset_used_flags (i3notes);
3514 reset_used_flags (i2notes);
3515 reset_used_flags (i1notes);
3516 reset_used_flags (newpat);
3517 reset_used_flags (newi2pat);
3518 if (undobuf.other_insn)
3519 reset_used_flags (PATTERN (undobuf.other_insn));
3521 i3notes = copy_rtx_if_shared (i3notes);
3522 i2notes = copy_rtx_if_shared (i2notes);
3523 i1notes = copy_rtx_if_shared (i1notes);
3524 newpat = copy_rtx_if_shared (newpat);
3525 newi2pat = copy_rtx_if_shared (newi2pat);
3526 if (undobuf.other_insn)
3527 reset_used_flags (PATTERN (undobuf.other_insn));
3529 INSN_CODE (i3) = insn_code_number;
3530 PATTERN (i3) = newpat;
3532 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3534 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3536 reset_used_flags (call_usage);
3537 call_usage = copy_rtx (call_usage);
3540 replace_rtx (call_usage, i2dest, i2src);
3543 replace_rtx (call_usage, i1dest, i1src);
3545 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3548 if (undobuf.other_insn)
3549 INSN_CODE (undobuf.other_insn) = other_code_number;
3551 /* We had one special case above where I2 had more than one set and
3552 we replaced a destination of one of those sets with the destination
3553 of I3. In that case, we have to update LOG_LINKS of insns later
3554 in this basic block. Note that this (expensive) case is rare.
3556 Also, in this case, we must pretend that all REG_NOTEs for I2
3557 actually came from I3, so that REG_UNUSED notes from I2 will be
3558 properly handled. */
3560 if (i3_subst_into_i2)
3562 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3563 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3564 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3565 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3566 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3567 && ! find_reg_note (i2, REG_UNUSED,
3568 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3569 for (temp = NEXT_INSN (i2);
3570 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3571 || BB_HEAD (this_basic_block) != temp);
3572 temp = NEXT_INSN (temp))
3573 if (temp != i3 && INSN_P (temp))
3574 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3575 if (XEXP (link, 0) == i2)
3576 XEXP (link, 0) = i3;
3581 while (XEXP (link, 1))
3582 link = XEXP (link, 1);
3583 XEXP (link, 1) = i2notes;
3597 INSN_CODE (i2) = i2_code_number;
3598 PATTERN (i2) = newi2pat;
3601 SET_INSN_DELETED (i2);
3607 SET_INSN_DELETED (i1);
3610 /* Get death notes for everything that is now used in either I3 or
3611 I2 and used to die in a previous insn. If we built two new
3612 patterns, move from I1 to I2 then I2 to I3 so that we get the
3613 proper movement on registers that I2 modifies. */
3617 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3618 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3621 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3624 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3626 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3629 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3632 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3635 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3638 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3639 know these are REG_UNUSED and want them to go to the desired insn,
3640 so we always pass it as i3. */
3642 if (newi2pat && new_i2_notes)
3643 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3646 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3648 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3649 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3650 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3651 in that case, it might delete I2. Similarly for I2 and I1.
3652 Show an additional death due to the REG_DEAD note we make here. If
3653 we discard it in distribute_notes, we will decrement it again. */
3657 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3658 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3660 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3662 distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
3664 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3668 if (i2dest_in_i2src)
3670 if (newi2pat && reg_set_p (i2dest, newi2pat))
3671 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3672 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3674 distribute_notes (alloc_reg_note (REG_DEAD, i2dest, NULL_RTX),
3675 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3676 NULL_RTX, NULL_RTX);
3679 if (i1dest_in_i1src)
3681 if (newi2pat && reg_set_p (i1dest, newi2pat))
3682 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3683 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3685 distribute_notes (alloc_reg_note (REG_DEAD, i1dest, NULL_RTX),
3686 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3687 NULL_RTX, NULL_RTX);
3690 distribute_links (i3links);
3691 distribute_links (i2links);
3692 distribute_links (i1links);
3697 rtx i2_insn = 0, i2_val = 0, set;
3699 /* The insn that used to set this register doesn't exist, and
3700 this life of the register may not exist either. See if one of
3701 I3's links points to an insn that sets I2DEST. If it does,
3702 that is now the last known value for I2DEST. If we don't update
3703 this and I2 set the register to a value that depended on its old
3704 contents, we will get confused. If this insn is used, thing
3705 will be set correctly in combine_instructions. */
3707 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3708 if ((set = single_set (XEXP (link, 0))) != 0
3709 && rtx_equal_p (i2dest, SET_DEST (set)))
3710 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3712 record_value_for_reg (i2dest, i2_insn, i2_val);
3714 /* If the reg formerly set in I2 died only once and that was in I3,
3715 zero its use count so it won't make `reload' do any work. */
3717 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3718 && ! i2dest_in_i2src)
3720 regno = REGNO (i2dest);
3721 INC_REG_N_SETS (regno, -1);
3725 if (i1 && REG_P (i1dest))
3728 rtx i1_insn = 0, i1_val = 0, set;
3730 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3731 if ((set = single_set (XEXP (link, 0))) != 0
3732 && rtx_equal_p (i1dest, SET_DEST (set)))
3733 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3735 record_value_for_reg (i1dest, i1_insn, i1_val);
3737 regno = REGNO (i1dest);
3738 if (! added_sets_1 && ! i1dest_in_i1src)
3739 INC_REG_N_SETS (regno, -1);
3742 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3743 been made to this insn. The order of
3744 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3745 can affect nonzero_bits of newpat */
3747 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3748 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3751 if (undobuf.other_insn != NULL_RTX)
3755 fprintf (dump_file, "modifying other_insn ");
3756 dump_insn_slim (dump_file, undobuf.other_insn);
3758 df_insn_rescan (undobuf.other_insn);
3761 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3765 fprintf (dump_file, "modifying insn i1 ");
3766 dump_insn_slim (dump_file, i1);
3768 df_insn_rescan (i1);
3771 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3775 fprintf (dump_file, "modifying insn i2 ");
3776 dump_insn_slim (dump_file, i2);
3778 df_insn_rescan (i2);
3781 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3785 fprintf (dump_file, "modifying insn i3 ");
3786 dump_insn_slim (dump_file, i3);
3788 df_insn_rescan (i3);
3791 /* Set new_direct_jump_p if a new return or simple jump instruction
3792 has been created. Adjust the CFG accordingly. */
3794 if (returnjump_p (i3) || any_uncondjump_p (i3))
3796 *new_direct_jump_p = 1;
3797 mark_jump_label (PATTERN (i3), i3, 0);
3798 update_cfg_for_uncondjump (i3);
3801 if (undobuf.other_insn != NULL_RTX
3802 && (returnjump_p (undobuf.other_insn)
3803 || any_uncondjump_p (undobuf.other_insn)))
3805 *new_direct_jump_p = 1;
3806 update_cfg_for_uncondjump (undobuf.other_insn);
3809 /* A noop might also need cleaning up of CFG, if it comes from the
3810 simplification of a jump. */
3811 if (GET_CODE (newpat) == SET
3812 && SET_SRC (newpat) == pc_rtx
3813 && SET_DEST (newpat) == pc_rtx)
3815 *new_direct_jump_p = 1;
3816 update_cfg_for_uncondjump (i3);
3819 combine_successes++;
3822 if (added_links_insn
3823 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3824 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3825 return added_links_insn;
3827 return newi2pat ? i2 : i3;
3830 /* Undo all the modifications recorded in undobuf. */
3835 struct undo *undo, *next;
3837 for (undo = undobuf.undos; undo; undo = next)
3843 *undo->where.r = undo->old_contents.r;
3846 *undo->where.i = undo->old_contents.i;
3849 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3855 undo->next = undobuf.frees;
3856 undobuf.frees = undo;
3862 /* We've committed to accepting the changes we made. Move all
3863 of the undos to the free list. */
3868 struct undo *undo, *next;
3870 for (undo = undobuf.undos; undo; undo = next)
3873 undo->next = undobuf.frees;
3874 undobuf.frees = undo;
3879 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3880 where we have an arithmetic expression and return that point. LOC will
3883 try_combine will call this function to see if an insn can be split into
3887 find_split_point (rtx *loc, rtx insn)
3890 enum rtx_code code = GET_CODE (x);
3892 unsigned HOST_WIDE_INT len = 0;
3893 HOST_WIDE_INT pos = 0;
3895 rtx inner = NULL_RTX;
3897 /* First special-case some codes. */
3901 #ifdef INSN_SCHEDULING
3902 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3904 if (MEM_P (SUBREG_REG (x)))
3907 return find_split_point (&SUBREG_REG (x), insn);
3911 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3912 using LO_SUM and HIGH. */
3913 if (GET_CODE (XEXP (x, 0)) == CONST
3914 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3917 gen_rtx_LO_SUM (Pmode,
3918 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3920 return &XEXP (XEXP (x, 0), 0);
3924 /* If we have a PLUS whose second operand is a constant and the
3925 address is not valid, perhaps will can split it up using
3926 the machine-specific way to split large constants. We use
3927 the first pseudo-reg (one of the virtual regs) as a placeholder;
3928 it will not remain in the result. */
3929 if (GET_CODE (XEXP (x, 0)) == PLUS
3930 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3931 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3933 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3934 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3938 /* This should have produced two insns, each of which sets our
3939 placeholder. If the source of the second is a valid address,
3940 we can make put both sources together and make a split point
3944 && NEXT_INSN (seq) != NULL_RTX
3945 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3946 && NONJUMP_INSN_P (seq)
3947 && GET_CODE (PATTERN (seq)) == SET
3948 && SET_DEST (PATTERN (seq)) == reg
3949 && ! reg_mentioned_p (reg,
3950 SET_SRC (PATTERN (seq)))
3951 && NONJUMP_INSN_P (NEXT_INSN (seq))
3952 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3953 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3954 && memory_address_p (GET_MODE (x),
3955 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3957 rtx src1 = SET_SRC (PATTERN (seq));
3958 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3960 /* Replace the placeholder in SRC2 with SRC1. If we can
3961 find where in SRC2 it was placed, that can become our
3962 split point and we can replace this address with SRC2.
3963 Just try two obvious places. */
3965 src2 = replace_rtx (src2, reg, src1);
3967 if (XEXP (src2, 0) == src1)
3968 split = &XEXP (src2, 0);
3969 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3970 && XEXP (XEXP (src2, 0), 0) == src1)
3971 split = &XEXP (XEXP (src2, 0), 0);
3975 SUBST (XEXP (x, 0), src2);
3980 /* If that didn't work, perhaps the first operand is complex and
3981 needs to be computed separately, so make a split point there.
3982 This will occur on machines that just support REG + CONST
3983 and have a constant moved through some previous computation. */
3985 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3986 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3987 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3988 return &XEXP (XEXP (x, 0), 0);
3991 /* If we have a PLUS whose first operand is complex, try computing it
3992 separately by making a split there. */
3993 if (GET_CODE (XEXP (x, 0)) == PLUS
3994 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3995 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3996 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3997 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3998 return &XEXP (XEXP (x, 0), 0);
4003 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4004 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4005 we need to put the operand into a register. So split at that
4008 if (SET_DEST (x) == cc0_rtx
4009 && GET_CODE (SET_SRC (x)) != COMPARE
4010 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4011 && !OBJECT_P (SET_SRC (x))
4012 && ! (GET_CODE (SET_SRC (x)) == SUBREG
4013 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4014 return &SET_SRC (x);
4017 /* See if we can split SET_SRC as it stands. */
4018 split = find_split_point (&SET_SRC (x), insn);
4019 if (split && split != &SET_SRC (x))
4022 /* See if we can split SET_DEST as it stands. */
4023 split = find_split_point (&SET_DEST (x), insn);
4024 if (split && split != &SET_DEST (x))
4027 /* See if this is a bitfield assignment with everything constant. If
4028 so, this is an IOR of an AND, so split it into that. */
4029 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4030 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
4031 <= HOST_BITS_PER_WIDE_INT)
4032 && CONST_INT_P (XEXP (SET_DEST (x), 1))
4033 && CONST_INT_P (XEXP (SET_DEST (x), 2))
4034 && CONST_INT_P (SET_SRC (x))
4035 && ((INTVAL (XEXP (SET_DEST (x), 1))
4036 + INTVAL (XEXP (SET_DEST (x), 2)))
4037 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4038 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4040 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4041 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4042 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4043 rtx dest = XEXP (SET_DEST (x), 0);
4044 enum machine_mode mode = GET_MODE (dest);
4045 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4048 if (BITS_BIG_ENDIAN)
4049 pos = GET_MODE_BITSIZE (mode) - len - pos;
4051 or_mask = gen_int_mode (src << pos, mode);
4054 simplify_gen_binary (IOR, mode, dest, or_mask));
4057 rtx negmask = gen_int_mode (~(mask << pos), mode);
4059 simplify_gen_binary (IOR, mode,
4060 simplify_gen_binary (AND, mode,
4065 SUBST (SET_DEST (x), dest);
4067 split = find_split_point (&SET_SRC (x), insn);
4068 if (split && split != &SET_SRC (x))
4072 /* Otherwise, see if this is an operation that we can split into two.
4073 If so, try to split that. */
4074 code = GET_CODE (SET_SRC (x));
4079 /* If we are AND'ing with a large constant that is only a single
4080 bit and the result is only being used in a context where we
4081 need to know if it is zero or nonzero, replace it with a bit
4082 extraction. This will avoid the large constant, which might
4083 have taken more than one insn to make. If the constant were
4084 not a valid argument to the AND but took only one insn to make,
4085 this is no worse, but if it took more than one insn, it will
4088 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4089 && REG_P (XEXP (SET_SRC (x), 0))
4090 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4091 && REG_P (SET_DEST (x))
4092 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4093 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4094 && XEXP (*split, 0) == SET_DEST (x)
4095 && XEXP (*split, 1) == const0_rtx)
4097 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4098 XEXP (SET_SRC (x), 0),
4099 pos, NULL_RTX, 1, 1, 0, 0);
4100 if (extraction != 0)
4102 SUBST (SET_SRC (x), extraction);
4103 return find_split_point (loc, insn);
4109 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4110 is known to be on, this can be converted into a NEG of a shift. */
4111 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4112 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4113 && 1 <= (pos = exact_log2
4114 (nonzero_bits (XEXP (SET_SRC (x), 0),
4115 GET_MODE (XEXP (SET_SRC (x), 0))))))
4117 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4121 gen_rtx_LSHIFTRT (mode,
4122 XEXP (SET_SRC (x), 0),
4125 split = find_split_point (&SET_SRC (x), insn);
4126 if (split && split != &SET_SRC (x))
4132 inner = XEXP (SET_SRC (x), 0);
4134 /* We can't optimize if either mode is a partial integer
4135 mode as we don't know how many bits are significant
4137 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4138 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4142 len = GET_MODE_BITSIZE (GET_MODE (inner));
4148 if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4149 && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4151 inner = XEXP (SET_SRC (x), 0);
4152 len = INTVAL (XEXP (SET_SRC (x), 1));
4153 pos = INTVAL (XEXP (SET_SRC (x), 2));
4155 if (BITS_BIG_ENDIAN)
4156 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4157 unsignedp = (code == ZERO_EXTRACT);
4165 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4167 enum machine_mode mode = GET_MODE (SET_SRC (x));
4169 /* For unsigned, we have a choice of a shift followed by an
4170 AND or two shifts. Use two shifts for field sizes where the
4171 constant might be too large. We assume here that we can
4172 always at least get 8-bit constants in an AND insn, which is
4173 true for every current RISC. */
4175 if (unsignedp && len <= 8)
4180 (mode, gen_lowpart (mode, inner),
4182 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4184 split = find_split_point (&SET_SRC (x), insn);
4185 if (split && split != &SET_SRC (x))
4192 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4193 gen_rtx_ASHIFT (mode,
4194 gen_lowpart (mode, inner),
4195 GEN_INT (GET_MODE_BITSIZE (mode)
4197 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4199 split = find_split_point (&SET_SRC (x), insn);
4200 if (split && split != &SET_SRC (x))
4205 /* See if this is a simple operation with a constant as the second
4206 operand. It might be that this constant is out of range and hence
4207 could be used as a split point. */
4208 if (BINARY_P (SET_SRC (x))
4209 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4210 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4211 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4212 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4213 return &XEXP (SET_SRC (x), 1);
4215 /* Finally, see if this is a simple operation with its first operand
4216 not in a register. The operation might require this operand in a
4217 register, so return it as a split point. We can always do this
4218 because if the first operand were another operation, we would have
4219 already found it as a split point. */
4220 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4221 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4222 return &XEXP (SET_SRC (x), 0);
4228 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4229 it is better to write this as (not (ior A B)) so we can split it.
4230 Similarly for IOR. */
4231 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4234 gen_rtx_NOT (GET_MODE (x),
4235 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4237 XEXP (XEXP (x, 0), 0),
4238 XEXP (XEXP (x, 1), 0))));
4239 return find_split_point (loc, insn);
4242 /* Many RISC machines have a large set of logical insns. If the
4243 second operand is a NOT, put it first so we will try to split the
4244 other operand first. */
4245 if (GET_CODE (XEXP (x, 1)) == NOT)
4247 rtx tem = XEXP (x, 0);
4248 SUBST (XEXP (x, 0), XEXP (x, 1));
4249 SUBST (XEXP (x, 1), tem);
4257 /* Otherwise, select our actions depending on our rtx class. */
4258 switch (GET_RTX_CLASS (code))
4260 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4262 split = find_split_point (&XEXP (x, 2), insn);
4265 /* ... fall through ... */
4267 case RTX_COMM_ARITH:
4269 case RTX_COMM_COMPARE:
4270 split = find_split_point (&XEXP (x, 1), insn);
4273 /* ... fall through ... */
4275 /* Some machines have (and (shift ...) ...) insns. If X is not
4276 an AND, but XEXP (X, 0) is, use it as our split point. */
4277 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4278 return &XEXP (x, 0);
4280 split = find_split_point (&XEXP (x, 0), insn);
4286 /* Otherwise, we don't have a split point. */
4291 /* Throughout X, replace FROM with TO, and return the result.
4292 The result is TO if X is FROM;
4293 otherwise the result is X, but its contents may have been modified.
4294 If they were modified, a record was made in undobuf so that
4295 undo_all will (among other things) return X to its original state.
4297 If the number of changes necessary is too much to record to undo,
4298 the excess changes are not made, so the result is invalid.
4299 The changes already made can still be undone.
4300 undobuf.num_undo is incremented for such changes, so by testing that
4301 the caller can tell whether the result is valid.
4303 `n_occurrences' is incremented each time FROM is replaced.
4305 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4307 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4308 by copying if `n_occurrences' is nonzero. */
4311 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4313 enum rtx_code code = GET_CODE (x);
4314 enum machine_mode op0_mode = VOIDmode;
4319 /* Two expressions are equal if they are identical copies of a shared
4320 RTX or if they are both registers with the same register number
4323 #define COMBINE_RTX_EQUAL_P(X,Y) \
4325 || (REG_P (X) && REG_P (Y) \
4326 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4328 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4331 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4334 /* If X and FROM are the same register but different modes, they
4335 will not have been seen as equal above. However, the log links code
4336 will make a LOG_LINKS entry for that case. If we do nothing, we
4337 will try to rerecognize our original insn and, when it succeeds,
4338 we will delete the feeding insn, which is incorrect.
4340 So force this insn not to match in this (rare) case. */
4341 if (! in_dest && code == REG && REG_P (from)
4342 && reg_overlap_mentioned_p (x, from))
4343 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4345 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4346 of which may contain things that can be combined. */
4347 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4350 /* It is possible to have a subexpression appear twice in the insn.
4351 Suppose that FROM is a register that appears within TO.
4352 Then, after that subexpression has been scanned once by `subst',
4353 the second time it is scanned, TO may be found. If we were
4354 to scan TO here, we would find FROM within it and create a
4355 self-referent rtl structure which is completely wrong. */
4356 if (COMBINE_RTX_EQUAL_P (x, to))
4359 /* Parallel asm_operands need special attention because all of the
4360 inputs are shared across the arms. Furthermore, unsharing the
4361 rtl results in recognition failures. Failure to handle this case
4362 specially can result in circular rtl.
4364 Solve this by doing a normal pass across the first entry of the
4365 parallel, and only processing the SET_DESTs of the subsequent
4368 if (code == PARALLEL
4369 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4370 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4372 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4374 /* If this substitution failed, this whole thing fails. */
4375 if (GET_CODE (new_rtx) == CLOBBER
4376 && XEXP (new_rtx, 0) == const0_rtx)
4379 SUBST (XVECEXP (x, 0, 0), new_rtx);
4381 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4383 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4386 && GET_CODE (dest) != CC0
4387 && GET_CODE (dest) != PC)
4389 new_rtx = subst (dest, from, to, 0, unique_copy);
4391 /* If this substitution failed, this whole thing fails. */
4392 if (GET_CODE (new_rtx) == CLOBBER
4393 && XEXP (new_rtx, 0) == const0_rtx)
4396 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4402 len = GET_RTX_LENGTH (code);
4403 fmt = GET_RTX_FORMAT (code);
4405 /* We don't need to process a SET_DEST that is a register, CC0,
4406 or PC, so set up to skip this common case. All other cases
4407 where we want to suppress replacing something inside a
4408 SET_SRC are handled via the IN_DEST operand. */
4410 && (REG_P (SET_DEST (x))
4411 || GET_CODE (SET_DEST (x)) == CC0
4412 || GET_CODE (SET_DEST (x)) == PC))
4415 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4418 op0_mode = GET_MODE (XEXP (x, 0));
4420 for (i = 0; i < len; i++)
4425 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4427 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4429 new_rtx = (unique_copy && n_occurrences
4430 ? copy_rtx (to) : to);
4435 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4438 /* If this substitution failed, this whole thing
4440 if (GET_CODE (new_rtx) == CLOBBER
4441 && XEXP (new_rtx, 0) == const0_rtx)
4445 SUBST (XVECEXP (x, i, j), new_rtx);
4448 else if (fmt[i] == 'e')
4450 /* If this is a register being set, ignore it. */
4451 new_rtx = XEXP (x, i);
4454 && (((code == SUBREG || code == ZERO_EXTRACT)
4456 || code == STRICT_LOW_PART))
4459 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4461 /* In general, don't install a subreg involving two
4462 modes not tieable. It can worsen register
4463 allocation, and can even make invalid reload
4464 insns, since the reg inside may need to be copied
4465 from in the outside mode, and that may be invalid
4466 if it is an fp reg copied in integer mode.
4468 We allow two exceptions to this: It is valid if
4469 it is inside another SUBREG and the mode of that
4470 SUBREG and the mode of the inside of TO is
4471 tieable and it is valid if X is a SET that copies
4474 if (GET_CODE (to) == SUBREG
4475 && ! MODES_TIEABLE_P (GET_MODE (to),
4476 GET_MODE (SUBREG_REG (to)))
4477 && ! (code == SUBREG
4478 && MODES_TIEABLE_P (GET_MODE (x),
4479 GET_MODE (SUBREG_REG (to))))
4481 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4484 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4486 #ifdef CANNOT_CHANGE_MODE_CLASS
4489 && REGNO (to) < FIRST_PSEUDO_REGISTER
4490 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4493 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4496 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4500 /* If we are in a SET_DEST, suppress most cases unless we
4501 have gone inside a MEM, in which case we want to
4502 simplify the address. We assume here that things that
4503 are actually part of the destination have their inner
4504 parts in the first expression. This is true for SUBREG,
4505 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4506 things aside from REG and MEM that should appear in a
4508 new_rtx = subst (XEXP (x, i), from, to,
4510 && (code == SUBREG || code == STRICT_LOW_PART
4511 || code == ZERO_EXTRACT))
4513 && i == 0), unique_copy);
4515 /* If we found that we will have to reject this combination,
4516 indicate that by returning the CLOBBER ourselves, rather than
4517 an expression containing it. This will speed things up as
4518 well as prevent accidents where two CLOBBERs are considered
4519 to be equal, thus producing an incorrect simplification. */
4521 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4524 if (GET_CODE (x) == SUBREG
4525 && (CONST_INT_P (new_rtx)
4526 || GET_CODE (new_rtx) == CONST_DOUBLE))
4528 enum machine_mode mode = GET_MODE (x);
4530 x = simplify_subreg (GET_MODE (x), new_rtx,
4531 GET_MODE (SUBREG_REG (x)),
4534 x = gen_rtx_CLOBBER (mode, const0_rtx);
4536 else if (CONST_INT_P (new_rtx)
4537 && GET_CODE (x) == ZERO_EXTEND)
4539 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4540 new_rtx, GET_MODE (XEXP (x, 0)));
4544 SUBST (XEXP (x, i), new_rtx);
4549 /* Check if we are loading something from the constant pool via float
4550 extension; in this case we would undo compress_float_constant
4551 optimization and degenerate constant load to an immediate value. */
4552 if (GET_CODE (x) == FLOAT_EXTEND
4553 && MEM_P (XEXP (x, 0))
4554 && MEM_READONLY_P (XEXP (x, 0)))
4556 rtx tmp = avoid_constant_pool_reference (x);
4561 /* Try to simplify X. If the simplification changed the code, it is likely
4562 that further simplification will help, so loop, but limit the number
4563 of repetitions that will be performed. */
4565 for (i = 0; i < 4; i++)
4567 /* If X is sufficiently simple, don't bother trying to do anything
4569 if (code != CONST_INT && code != REG && code != CLOBBER)
4570 x = combine_simplify_rtx (x, op0_mode, in_dest);
4572 if (GET_CODE (x) == code)
4575 code = GET_CODE (x);
4577 /* We no longer know the original mode of operand 0 since we
4578 have changed the form of X) */
4579 op0_mode = VOIDmode;
4585 /* Simplify X, a piece of RTL. We just operate on the expression at the
4586 outer level; call `subst' to simplify recursively. Return the new
4589 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4590 if we are inside a SET_DEST. */
4593 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4595 enum rtx_code code = GET_CODE (x);
4596 enum machine_mode mode = GET_MODE (x);
4600 /* If this is a commutative operation, put a constant last and a complex
4601 expression first. We don't need to do this for comparisons here. */
4602 if (COMMUTATIVE_ARITH_P (x)
4603 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4606 SUBST (XEXP (x, 0), XEXP (x, 1));
4607 SUBST (XEXP (x, 1), temp);
4610 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4611 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4612 things. Check for cases where both arms are testing the same
4615 Don't do anything if all operands are very simple. */
4618 && ((!OBJECT_P (XEXP (x, 0))
4619 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4620 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4621 || (!OBJECT_P (XEXP (x, 1))
4622 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4623 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4625 && (!OBJECT_P (XEXP (x, 0))
4626 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4627 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4629 rtx cond, true_rtx, false_rtx;
4631 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4633 /* If everything is a comparison, what we have is highly unlikely
4634 to be simpler, so don't use it. */
4635 && ! (COMPARISON_P (x)
4636 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4638 rtx cop1 = const0_rtx;
4639 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4641 if (cond_code == NE && COMPARISON_P (cond))
4644 /* Simplify the alternative arms; this may collapse the true and
4645 false arms to store-flag values. Be careful to use copy_rtx
4646 here since true_rtx or false_rtx might share RTL with x as a
4647 result of the if_then_else_cond call above. */
4648 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4649 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4651 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4652 is unlikely to be simpler. */
4653 if (general_operand (true_rtx, VOIDmode)
4654 && general_operand (false_rtx, VOIDmode))
4656 enum rtx_code reversed;
4658 /* Restarting if we generate a store-flag expression will cause
4659 us to loop. Just drop through in this case. */
4661 /* If the result values are STORE_FLAG_VALUE and zero, we can
4662 just make the comparison operation. */
4663 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4664 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4666 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4667 && ((reversed = reversed_comparison_code_parts
4668 (cond_code, cond, cop1, NULL))
4670 x = simplify_gen_relational (reversed, mode, VOIDmode,
4673 /* Likewise, we can make the negate of a comparison operation
4674 if the result values are - STORE_FLAG_VALUE and zero. */
4675 else if (CONST_INT_P (true_rtx)
4676 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4677 && false_rtx == const0_rtx)
4678 x = simplify_gen_unary (NEG, mode,
4679 simplify_gen_relational (cond_code,
4683 else if (CONST_INT_P (false_rtx)
4684 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4685 && true_rtx == const0_rtx
4686 && ((reversed = reversed_comparison_code_parts
4687 (cond_code, cond, cop1, NULL))
4689 x = simplify_gen_unary (NEG, mode,
4690 simplify_gen_relational (reversed,
4695 return gen_rtx_IF_THEN_ELSE (mode,
4696 simplify_gen_relational (cond_code,
4701 true_rtx, false_rtx);
4703 code = GET_CODE (x);
4704 op0_mode = VOIDmode;
4709 /* Try to fold this expression in case we have constants that weren't
4712 switch (GET_RTX_CLASS (code))
4715 if (op0_mode == VOIDmode)
4716 op0_mode = GET_MODE (XEXP (x, 0));
4717 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4720 case RTX_COMM_COMPARE:
4722 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4723 if (cmp_mode == VOIDmode)
4725 cmp_mode = GET_MODE (XEXP (x, 1));
4726 if (cmp_mode == VOIDmode)
4727 cmp_mode = op0_mode;
4729 temp = simplify_relational_operation (code, mode, cmp_mode,
4730 XEXP (x, 0), XEXP (x, 1));
4733 case RTX_COMM_ARITH:
4735 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4737 case RTX_BITFIELD_OPS:
4739 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4740 XEXP (x, 1), XEXP (x, 2));
4749 code = GET_CODE (temp);
4750 op0_mode = VOIDmode;
4751 mode = GET_MODE (temp);
4754 /* First see if we can apply the inverse distributive law. */
4755 if (code == PLUS || code == MINUS
4756 || code == AND || code == IOR || code == XOR)
4758 x = apply_distributive_law (x);
4759 code = GET_CODE (x);
4760 op0_mode = VOIDmode;
4763 /* If CODE is an associative operation not otherwise handled, see if we
4764 can associate some operands. This can win if they are constants or
4765 if they are logically related (i.e. (a & b) & a). */
4766 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4767 || code == AND || code == IOR || code == XOR
4768 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4769 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4770 || (flag_associative_math && FLOAT_MODE_P (mode))))
4772 if (GET_CODE (XEXP (x, 0)) == code)
4774 rtx other = XEXP (XEXP (x, 0), 0);
4775 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4776 rtx inner_op1 = XEXP (x, 1);
4779 /* Make sure we pass the constant operand if any as the second
4780 one if this is a commutative operation. */
4781 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4783 rtx tem = inner_op0;
4784 inner_op0 = inner_op1;
4787 inner = simplify_binary_operation (code == MINUS ? PLUS
4788 : code == DIV ? MULT
4790 mode, inner_op0, inner_op1);
4792 /* For commutative operations, try the other pair if that one
4794 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4796 other = XEXP (XEXP (x, 0), 1);
4797 inner = simplify_binary_operation (code, mode,
4798 XEXP (XEXP (x, 0), 0),
4803 return simplify_gen_binary (code, mode, other, inner);
4807 /* A little bit of algebraic simplification here. */
4811 /* Ensure that our address has any ASHIFTs converted to MULT in case
4812 address-recognizing predicates are called later. */
4813 temp = make_compound_operation (XEXP (x, 0), MEM);
4814 SUBST (XEXP (x, 0), temp);
4818 if (op0_mode == VOIDmode)
4819 op0_mode = GET_MODE (SUBREG_REG (x));
4821 /* See if this can be moved to simplify_subreg. */
4822 if (CONSTANT_P (SUBREG_REG (x))
4823 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4824 /* Don't call gen_lowpart if the inner mode
4825 is VOIDmode and we cannot simplify it, as SUBREG without
4826 inner mode is invalid. */
4827 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4828 || gen_lowpart_common (mode, SUBREG_REG (x))))
4829 return gen_lowpart (mode, SUBREG_REG (x));
4831 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4835 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4841 /* Don't change the mode of the MEM if that would change the meaning
4843 if (MEM_P (SUBREG_REG (x))
4844 && (MEM_VOLATILE_P (SUBREG_REG (x))
4845 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4846 return gen_rtx_CLOBBER (mode, const0_rtx);
4848 /* Note that we cannot do any narrowing for non-constants since
4849 we might have been counting on using the fact that some bits were
4850 zero. We now do this in the SET. */
4855 temp = expand_compound_operation (XEXP (x, 0));
4857 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4858 replaced by (lshiftrt X C). This will convert
4859 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4861 if (GET_CODE (temp) == ASHIFTRT
4862 && CONST_INT_P (XEXP (temp, 1))
4863 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4864 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4865 INTVAL (XEXP (temp, 1)));
4867 /* If X has only a single bit that might be nonzero, say, bit I, convert
4868 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4869 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4870 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4871 or a SUBREG of one since we'd be making the expression more
4872 complex if it was just a register. */
4875 && ! (GET_CODE (temp) == SUBREG
4876 && REG_P (SUBREG_REG (temp)))
4877 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4879 rtx temp1 = simplify_shift_const
4880 (NULL_RTX, ASHIFTRT, mode,
4881 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4882 GET_MODE_BITSIZE (mode) - 1 - i),
4883 GET_MODE_BITSIZE (mode) - 1 - i);
4885 /* If all we did was surround TEMP with the two shifts, we
4886 haven't improved anything, so don't use it. Otherwise,
4887 we are better off with TEMP1. */
4888 if (GET_CODE (temp1) != ASHIFTRT
4889 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4890 || XEXP (XEXP (temp1, 0), 0) != temp)
4896 /* We can't handle truncation to a partial integer mode here
4897 because we don't know the real bitsize of the partial
4899 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4902 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4904 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4905 GET_MODE_MASK (mode), 0));
4907 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4908 whose value is a comparison can be replaced with a subreg if
4909 STORE_FLAG_VALUE permits. */
4910 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4911 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4912 && (temp = get_last_value (XEXP (x, 0)))
4913 && COMPARISON_P (temp))
4914 return gen_lowpart (mode, XEXP (x, 0));
4918 /* (const (const X)) can become (const X). Do it this way rather than
4919 returning the inner CONST since CONST can be shared with a
4921 if (GET_CODE (XEXP (x, 0)) == CONST)
4922 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4927 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4928 can add in an offset. find_split_point will split this address up
4929 again if it doesn't match. */
4930 if (GET_CODE (XEXP (x, 0)) == HIGH
4931 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4937 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4938 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4939 bit-field and can be replaced by either a sign_extend or a
4940 sign_extract. The `and' may be a zero_extend and the two
4941 <c>, -<c> constants may be reversed. */
4942 if (GET_CODE (XEXP (x, 0)) == XOR
4943 && CONST_INT_P (XEXP (x, 1))
4944 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4945 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4946 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4947 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4948 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4949 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4950 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4951 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4952 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4953 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4954 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4955 == (unsigned int) i + 1))))
4956 return simplify_shift_const
4957 (NULL_RTX, ASHIFTRT, mode,
4958 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4959 XEXP (XEXP (XEXP (x, 0), 0), 0),
4960 GET_MODE_BITSIZE (mode) - (i + 1)),
4961 GET_MODE_BITSIZE (mode) - (i + 1));
4963 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4964 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4965 the bitsize of the mode - 1. This allows simplification of
4966 "a = (b & 8) == 0;" */
4967 if (XEXP (x, 1) == constm1_rtx
4968 && !REG_P (XEXP (x, 0))
4969 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4970 && REG_P (SUBREG_REG (XEXP (x, 0))))
4971 && nonzero_bits (XEXP (x, 0), mode) == 1)
4972 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4973 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4974 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4975 GET_MODE_BITSIZE (mode) - 1),
4976 GET_MODE_BITSIZE (mode) - 1);
4978 /* If we are adding two things that have no bits in common, convert
4979 the addition into an IOR. This will often be further simplified,
4980 for example in cases like ((a & 1) + (a & 2)), which can
4983 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4984 && (nonzero_bits (XEXP (x, 0), mode)
4985 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4987 /* Try to simplify the expression further. */
4988 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4989 temp = combine_simplify_rtx (tor, mode, in_dest);
4991 /* If we could, great. If not, do not go ahead with the IOR
4992 replacement, since PLUS appears in many special purpose
4993 address arithmetic instructions. */
4994 if (GET_CODE (temp) != CLOBBER && temp != tor)
5000 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5001 (and <foo> (const_int pow2-1)) */
5002 if (GET_CODE (XEXP (x, 1)) == AND
5003 && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5004 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5005 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5006 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5007 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5011 /* If we have (mult (plus A B) C), apply the distributive law and then
5012 the inverse distributive law to see if things simplify. This
5013 occurs mostly in addresses, often when unrolling loops. */
5015 if (GET_CODE (XEXP (x, 0)) == PLUS)
5017 rtx result = distribute_and_simplify_rtx (x, 0);
5022 /* Try simplify a*(b/c) as (a*b)/c. */
5023 if (FLOAT_MODE_P (mode) && flag_associative_math
5024 && GET_CODE (XEXP (x, 0)) == DIV)
5026 rtx tem = simplify_binary_operation (MULT, mode,
5027 XEXP (XEXP (x, 0), 0),
5030 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5035 /* If this is a divide by a power of two, treat it as a shift if
5036 its first operand is a shift. */
5037 if (CONST_INT_P (XEXP (x, 1))
5038 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5039 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5040 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5041 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5042 || GET_CODE (XEXP (x, 0)) == ROTATE
5043 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5044 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5048 case GT: case GTU: case GE: case GEU:
5049 case LT: case LTU: case LE: case LEU:
5050 case UNEQ: case LTGT:
5051 case UNGT: case UNGE:
5052 case UNLT: case UNLE:
5053 case UNORDERED: case ORDERED:
5054 /* If the first operand is a condition code, we can't do anything
5056 if (GET_CODE (XEXP (x, 0)) == COMPARE
5057 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5058 && ! CC0_P (XEXP (x, 0))))
5060 rtx op0 = XEXP (x, 0);
5061 rtx op1 = XEXP (x, 1);
5062 enum rtx_code new_code;
5064 if (GET_CODE (op0) == COMPARE)
5065 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5067 /* Simplify our comparison, if possible. */
5068 new_code = simplify_comparison (code, &op0, &op1);
5070 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5071 if only the low-order bit is possibly nonzero in X (such as when
5072 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5073 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5074 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5077 Remove any ZERO_EXTRACT we made when thinking this was a
5078 comparison. It may now be simpler to use, e.g., an AND. If a
5079 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5080 the call to make_compound_operation in the SET case. */
5082 if (STORE_FLAG_VALUE == 1
5083 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5084 && op1 == const0_rtx
5085 && mode == GET_MODE (op0)
5086 && nonzero_bits (op0, mode) == 1)
5087 return gen_lowpart (mode,
5088 expand_compound_operation (op0));
5090 else if (STORE_FLAG_VALUE == 1
5091 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5092 && op1 == const0_rtx
5093 && mode == GET_MODE (op0)
5094 && (num_sign_bit_copies (op0, mode)
5095 == GET_MODE_BITSIZE (mode)))
5097 op0 = expand_compound_operation (op0);
5098 return simplify_gen_unary (NEG, mode,
5099 gen_lowpart (mode, op0),
5103 else if (STORE_FLAG_VALUE == 1
5104 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5105 && op1 == const0_rtx
5106 && mode == GET_MODE (op0)
5107 && nonzero_bits (op0, mode) == 1)
5109 op0 = expand_compound_operation (op0);
5110 return simplify_gen_binary (XOR, mode,
5111 gen_lowpart (mode, op0),
5115 else if (STORE_FLAG_VALUE == 1
5116 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5117 && op1 == const0_rtx
5118 && mode == GET_MODE (op0)
5119 && (num_sign_bit_copies (op0, mode)
5120 == GET_MODE_BITSIZE (mode)))
5122 op0 = expand_compound_operation (op0);
5123 return plus_constant (gen_lowpart (mode, op0), 1);
5126 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5128 if (STORE_FLAG_VALUE == -1
5129 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5130 && op1 == const0_rtx
5131 && (num_sign_bit_copies (op0, mode)
5132 == GET_MODE_BITSIZE (mode)))
5133 return gen_lowpart (mode,
5134 expand_compound_operation (op0));
5136 else if (STORE_FLAG_VALUE == -1
5137 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5138 && op1 == const0_rtx
5139 && mode == GET_MODE (op0)
5140 && nonzero_bits (op0, mode) == 1)
5142 op0 = expand_compound_operation (op0);
5143 return simplify_gen_unary (NEG, mode,
5144 gen_lowpart (mode, op0),
5148 else if (STORE_FLAG_VALUE == -1
5149 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5150 && op1 == const0_rtx
5151 && mode == GET_MODE (op0)
5152 && (num_sign_bit_copies (op0, mode)
5153 == GET_MODE_BITSIZE (mode)))
5155 op0 = expand_compound_operation (op0);
5156 return simplify_gen_unary (NOT, mode,
5157 gen_lowpart (mode, op0),
5161 /* If X is 0/1, (eq X 0) is X-1. */
5162 else if (STORE_FLAG_VALUE == -1
5163 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5164 && op1 == const0_rtx
5165 && mode == GET_MODE (op0)
5166 && nonzero_bits (op0, mode) == 1)
5168 op0 = expand_compound_operation (op0);
5169 return plus_constant (gen_lowpart (mode, op0), -1);
5172 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5173 one bit that might be nonzero, we can convert (ne x 0) to
5174 (ashift x c) where C puts the bit in the sign bit. Remove any
5175 AND with STORE_FLAG_VALUE when we are done, since we are only
5176 going to test the sign bit. */
5177 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5179 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5180 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5181 && op1 == const0_rtx
5182 && mode == GET_MODE (op0)
5183 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5185 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5186 expand_compound_operation (op0),
5187 GET_MODE_BITSIZE (mode) - 1 - i);
5188 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5194 /* If the code changed, return a whole new comparison. */
5195 if (new_code != code)
5196 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5198 /* Otherwise, keep this operation, but maybe change its operands.
5199 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5200 SUBST (XEXP (x, 0), op0);
5201 SUBST (XEXP (x, 1), op1);
5206 return simplify_if_then_else (x);
5212 /* If we are processing SET_DEST, we are done. */
5216 return expand_compound_operation (x);
5219 return simplify_set (x);
5223 return simplify_logical (x);
5230 /* If this is a shift by a constant amount, simplify it. */
5231 if (CONST_INT_P (XEXP (x, 1)))
5232 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5233 INTVAL (XEXP (x, 1)));
5235 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5237 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5239 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5251 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5254 simplify_if_then_else (rtx x)
5256 enum machine_mode mode = GET_MODE (x);
5257 rtx cond = XEXP (x, 0);
5258 rtx true_rtx = XEXP (x, 1);
5259 rtx false_rtx = XEXP (x, 2);
5260 enum rtx_code true_code = GET_CODE (cond);
5261 int comparison_p = COMPARISON_P (cond);
5264 enum rtx_code false_code;
5267 /* Simplify storing of the truth value. */
5268 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5269 return simplify_gen_relational (true_code, mode, VOIDmode,
5270 XEXP (cond, 0), XEXP (cond, 1));
5272 /* Also when the truth value has to be reversed. */
5274 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5275 && (reversed = reversed_comparison (cond, mode)))
5278 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5279 in it is being compared against certain values. Get the true and false
5280 comparisons and see if that says anything about the value of each arm. */
5283 && ((false_code = reversed_comparison_code (cond, NULL))
5285 && REG_P (XEXP (cond, 0)))
5288 rtx from = XEXP (cond, 0);
5289 rtx true_val = XEXP (cond, 1);
5290 rtx false_val = true_val;
5293 /* If FALSE_CODE is EQ, swap the codes and arms. */
5295 if (false_code == EQ)
5297 swapped = 1, true_code = EQ, false_code = NE;
5298 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5301 /* If we are comparing against zero and the expression being tested has
5302 only a single bit that might be nonzero, that is its value when it is
5303 not equal to zero. Similarly if it is known to be -1 or 0. */
5305 if (true_code == EQ && true_val == const0_rtx
5306 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5309 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5311 else if (true_code == EQ && true_val == const0_rtx
5312 && (num_sign_bit_copies (from, GET_MODE (from))
5313 == GET_MODE_BITSIZE (GET_MODE (from))))
5316 false_val = constm1_rtx;
5319 /* Now simplify an arm if we know the value of the register in the
5320 branch and it is used in the arm. Be careful due to the potential
5321 of locally-shared RTL. */
5323 if (reg_mentioned_p (from, true_rtx))
5324 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5326 pc_rtx, pc_rtx, 0, 0);
5327 if (reg_mentioned_p (from, false_rtx))
5328 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5330 pc_rtx, pc_rtx, 0, 0);
5332 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5333 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5335 true_rtx = XEXP (x, 1);
5336 false_rtx = XEXP (x, 2);
5337 true_code = GET_CODE (cond);
5340 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5341 reversed, do so to avoid needing two sets of patterns for
5342 subtract-and-branch insns. Similarly if we have a constant in the true
5343 arm, the false arm is the same as the first operand of the comparison, or
5344 the false arm is more complicated than the true arm. */
5347 && reversed_comparison_code (cond, NULL) != UNKNOWN
5348 && (true_rtx == pc_rtx
5349 || (CONSTANT_P (true_rtx)
5350 && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
5351 || true_rtx == const0_rtx
5352 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5353 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5354 && !OBJECT_P (false_rtx))
5355 || reg_mentioned_p (true_rtx, false_rtx)
5356 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5358 true_code = reversed_comparison_code (cond, NULL);
5359 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5360 SUBST (XEXP (x, 1), false_rtx);
5361 SUBST (XEXP (x, 2), true_rtx);
5363 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5366 /* It is possible that the conditional has been simplified out. */
5367 true_code = GET_CODE (cond);
5368 comparison_p = COMPARISON_P (cond);
5371 /* If the two arms are identical, we don't need the comparison. */
5373 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5376 /* Convert a == b ? b : a to "a". */
5377 if (true_code == EQ && ! side_effects_p (cond)
5378 && !HONOR_NANS (mode)
5379 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5380 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5382 else if (true_code == NE && ! side_effects_p (cond)
5383 && !HONOR_NANS (mode)
5384 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5385 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5388 /* Look for cases where we have (abs x) or (neg (abs X)). */
5390 if (GET_MODE_CLASS (mode) == MODE_INT
5392 && XEXP (cond, 1) == const0_rtx
5393 && GET_CODE (false_rtx) == NEG
5394 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5395 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5396 && ! side_effects_p (true_rtx))
5401 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5405 simplify_gen_unary (NEG, mode,
5406 simplify_gen_unary (ABS, mode, true_rtx, mode),
5412 /* Look for MIN or MAX. */
5414 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5416 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5417 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5418 && ! side_effects_p (cond))
5423 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5426 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5429 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5432 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5437 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5438 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5439 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5440 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5441 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5442 neither 1 or -1, but it isn't worth checking for. */
5444 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5446 && GET_MODE_CLASS (mode) == MODE_INT
5447 && ! side_effects_p (x))
5449 rtx t = make_compound_operation (true_rtx, SET);
5450 rtx f = make_compound_operation (false_rtx, SET);
5451 rtx cond_op0 = XEXP (cond, 0);
5452 rtx cond_op1 = XEXP (cond, 1);
5453 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5454 enum machine_mode m = mode;
5455 rtx z = 0, c1 = NULL_RTX;
5457 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5458 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5459 || GET_CODE (t) == ASHIFT
5460 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5461 && rtx_equal_p (XEXP (t, 0), f))
5462 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5464 /* If an identity-zero op is commutative, check whether there
5465 would be a match if we swapped the operands. */
5466 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5467 || GET_CODE (t) == XOR)
5468 && rtx_equal_p (XEXP (t, 1), f))
5469 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5470 else if (GET_CODE (t) == SIGN_EXTEND
5471 && (GET_CODE (XEXP (t, 0)) == PLUS
5472 || GET_CODE (XEXP (t, 0)) == MINUS
5473 || GET_CODE (XEXP (t, 0)) == IOR
5474 || GET_CODE (XEXP (t, 0)) == XOR
5475 || GET_CODE (XEXP (t, 0)) == ASHIFT
5476 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5477 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5478 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5479 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5480 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5481 && (num_sign_bit_copies (f, GET_MODE (f))
5483 (GET_MODE_BITSIZE (mode)
5484 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5486 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5487 extend_op = SIGN_EXTEND;
5488 m = GET_MODE (XEXP (t, 0));
5490 else if (GET_CODE (t) == SIGN_EXTEND
5491 && (GET_CODE (XEXP (t, 0)) == PLUS
5492 || GET_CODE (XEXP (t, 0)) == IOR
5493 || GET_CODE (XEXP (t, 0)) == XOR)
5494 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5495 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5496 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5497 && (num_sign_bit_copies (f, GET_MODE (f))
5499 (GET_MODE_BITSIZE (mode)
5500 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5502 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5503 extend_op = SIGN_EXTEND;
5504 m = GET_MODE (XEXP (t, 0));
5506 else if (GET_CODE (t) == ZERO_EXTEND
5507 && (GET_CODE (XEXP (t, 0)) == PLUS
5508 || GET_CODE (XEXP (t, 0)) == MINUS
5509 || GET_CODE (XEXP (t, 0)) == IOR
5510 || GET_CODE (XEXP (t, 0)) == XOR
5511 || GET_CODE (XEXP (t, 0)) == ASHIFT
5512 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5513 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5514 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5515 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5516 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5517 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5518 && ((nonzero_bits (f, GET_MODE (f))
5519 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5522 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5523 extend_op = ZERO_EXTEND;
5524 m = GET_MODE (XEXP (t, 0));
5526 else if (GET_CODE (t) == ZERO_EXTEND
5527 && (GET_CODE (XEXP (t, 0)) == PLUS
5528 || GET_CODE (XEXP (t, 0)) == IOR
5529 || GET_CODE (XEXP (t, 0)) == XOR)
5530 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5531 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5532 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5533 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5534 && ((nonzero_bits (f, GET_MODE (f))
5535 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5538 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5539 extend_op = ZERO_EXTEND;
5540 m = GET_MODE (XEXP (t, 0));
5545 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5546 cond_op0, cond_op1),
5547 pc_rtx, pc_rtx, 0, 0);
5548 temp = simplify_gen_binary (MULT, m, temp,
5549 simplify_gen_binary (MULT, m, c1,
5551 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5552 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5554 if (extend_op != UNKNOWN)
5555 temp = simplify_gen_unary (extend_op, mode, temp, m);
5561 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5562 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5563 negation of a single bit, we can convert this operation to a shift. We
5564 can actually do this more generally, but it doesn't seem worth it. */
5566 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5567 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5568 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5569 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5570 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5571 == GET_MODE_BITSIZE (mode))
5572 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5574 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5575 gen_lowpart (mode, XEXP (cond, 0)), i);
5577 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5578 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5579 && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
5580 && GET_MODE (XEXP (cond, 0)) == mode
5581 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5582 == nonzero_bits (XEXP (cond, 0), mode)
5583 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5584 return XEXP (cond, 0);
5589 /* Simplify X, a SET expression. Return the new expression. */
5592 simplify_set (rtx x)
5594 rtx src = SET_SRC (x);
5595 rtx dest = SET_DEST (x);
5596 enum machine_mode mode
5597 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5601 /* (set (pc) (return)) gets written as (return). */
5602 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5605 /* Now that we know for sure which bits of SRC we are using, see if we can
5606 simplify the expression for the object knowing that we only need the
5609 if (GET_MODE_CLASS (mode) == MODE_INT
5610 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5612 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5613 SUBST (SET_SRC (x), src);
5616 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5617 the comparison result and try to simplify it unless we already have used
5618 undobuf.other_insn. */
5619 if ((GET_MODE_CLASS (mode) == MODE_CC
5620 || GET_CODE (src) == COMPARE
5622 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5623 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5624 && COMPARISON_P (*cc_use)
5625 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5627 enum rtx_code old_code = GET_CODE (*cc_use);
5628 enum rtx_code new_code;
5630 int other_changed = 0;
5631 enum machine_mode compare_mode = GET_MODE (dest);
5633 if (GET_CODE (src) == COMPARE)
5634 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5636 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5638 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5641 new_code = old_code;
5642 else if (!CONSTANT_P (tmp))
5644 new_code = GET_CODE (tmp);
5645 op0 = XEXP (tmp, 0);
5646 op1 = XEXP (tmp, 1);
5650 rtx pat = PATTERN (other_insn);
5651 undobuf.other_insn = other_insn;
5652 SUBST (*cc_use, tmp);
5654 /* Attempt to simplify CC user. */
5655 if (GET_CODE (pat) == SET)
5657 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5658 if (new_rtx != NULL_RTX)
5659 SUBST (SET_SRC (pat), new_rtx);
5662 /* Convert X into a no-op move. */
5663 SUBST (SET_DEST (x), pc_rtx);
5664 SUBST (SET_SRC (x), pc_rtx);
5668 /* Simplify our comparison, if possible. */
5669 new_code = simplify_comparison (new_code, &op0, &op1);
5671 #ifdef SELECT_CC_MODE
5672 /* If this machine has CC modes other than CCmode, check to see if we
5673 need to use a different CC mode here. */
5674 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5675 compare_mode = GET_MODE (op0);
5677 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5680 /* If the mode changed, we have to change SET_DEST, the mode in the
5681 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5682 a hard register, just build new versions with the proper mode. If it
5683 is a pseudo, we lose unless it is only time we set the pseudo, in
5684 which case we can safely change its mode. */
5685 if (compare_mode != GET_MODE (dest))
5687 if (can_change_dest_mode (dest, 0, compare_mode))
5689 unsigned int regno = REGNO (dest);
5692 if (regno < FIRST_PSEUDO_REGISTER)
5693 new_dest = gen_rtx_REG (compare_mode, regno);
5696 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5697 new_dest = regno_reg_rtx[regno];
5700 SUBST (SET_DEST (x), new_dest);
5701 SUBST (XEXP (*cc_use, 0), new_dest);
5708 #endif /* SELECT_CC_MODE */
5710 /* If the code changed, we have to build a new comparison in
5711 undobuf.other_insn. */
5712 if (new_code != old_code)
5714 int other_changed_previously = other_changed;
5715 unsigned HOST_WIDE_INT mask;
5716 rtx old_cc_use = *cc_use;
5718 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5722 /* If the only change we made was to change an EQ into an NE or
5723 vice versa, OP0 has only one bit that might be nonzero, and OP1
5724 is zero, check if changing the user of the condition code will
5725 produce a valid insn. If it won't, we can keep the original code
5726 in that insn by surrounding our operation with an XOR. */
5728 if (((old_code == NE && new_code == EQ)
5729 || (old_code == EQ && new_code == NE))
5730 && ! other_changed_previously && op1 == const0_rtx
5731 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5732 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5734 rtx pat = PATTERN (other_insn), note = 0;
5736 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5737 && ! check_asm_operands (pat)))
5739 *cc_use = old_cc_use;
5742 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5743 op0, GEN_INT (mask));
5749 undobuf.other_insn = other_insn;
5751 /* Otherwise, if we didn't previously have a COMPARE in the
5752 correct mode, we need one. */
5753 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5755 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5758 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5760 SUBST (SET_SRC (x), op0);
5763 /* Otherwise, update the COMPARE if needed. */
5764 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5766 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5772 /* Get SET_SRC in a form where we have placed back any
5773 compound expressions. Then do the checks below. */
5774 src = make_compound_operation (src, SET);
5775 SUBST (SET_SRC (x), src);
5778 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5779 and X being a REG or (subreg (reg)), we may be able to convert this to
5780 (set (subreg:m2 x) (op)).
5782 We can always do this if M1 is narrower than M2 because that means that
5783 we only care about the low bits of the result.
5785 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5786 perform a narrower operation than requested since the high-order bits will
5787 be undefined. On machine where it is defined, this transformation is safe
5788 as long as M1 and M2 have the same number of words. */
5790 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5791 && !OBJECT_P (SUBREG_REG (src))
5792 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5794 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5795 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5796 #ifndef WORD_REGISTER_OPERATIONS
5797 && (GET_MODE_SIZE (GET_MODE (src))
5798 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5800 #ifdef CANNOT_CHANGE_MODE_CLASS
5801 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5802 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5803 GET_MODE (SUBREG_REG (src)),
5807 || (GET_CODE (dest) == SUBREG
5808 && REG_P (SUBREG_REG (dest)))))
5810 SUBST (SET_DEST (x),
5811 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5813 SUBST (SET_SRC (x), SUBREG_REG (src));
5815 src = SET_SRC (x), dest = SET_DEST (x);
5819 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5822 && GET_CODE (src) == SUBREG
5823 && subreg_lowpart_p (src)
5824 && (GET_MODE_BITSIZE (GET_MODE (src))
5825 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5827 rtx inner = SUBREG_REG (src);
5828 enum machine_mode inner_mode = GET_MODE (inner);
5830 /* Here we make sure that we don't have a sign bit on. */
5831 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5832 && (nonzero_bits (inner, inner_mode)
5833 < ((unsigned HOST_WIDE_INT) 1
5834 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5836 SUBST (SET_SRC (x), inner);
5842 #ifdef LOAD_EXTEND_OP
5843 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5844 would require a paradoxical subreg. Replace the subreg with a
5845 zero_extend to avoid the reload that would otherwise be required. */
5847 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5848 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
5849 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5850 && SUBREG_BYTE (src) == 0
5851 && (GET_MODE_SIZE (GET_MODE (src))
5852 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5853 && MEM_P (SUBREG_REG (src)))
5856 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5857 GET_MODE (src), SUBREG_REG (src)));
5863 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5864 are comparing an item known to be 0 or -1 against 0, use a logical
5865 operation instead. Check for one of the arms being an IOR of the other
5866 arm with some value. We compute three terms to be IOR'ed together. In
5867 practice, at most two will be nonzero. Then we do the IOR's. */
5869 if (GET_CODE (dest) != PC
5870 && GET_CODE (src) == IF_THEN_ELSE
5871 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5872 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5873 && XEXP (XEXP (src, 0), 1) == const0_rtx
5874 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5875 #ifdef HAVE_conditional_move
5876 && ! can_conditionally_move_p (GET_MODE (src))
5878 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5879 GET_MODE (XEXP (XEXP (src, 0), 0)))
5880 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5881 && ! side_effects_p (src))
5883 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5884 ? XEXP (src, 1) : XEXP (src, 2));
5885 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5886 ? XEXP (src, 2) : XEXP (src, 1));
5887 rtx term1 = const0_rtx, term2, term3;
5889 if (GET_CODE (true_rtx) == IOR
5890 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5891 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5892 else if (GET_CODE (true_rtx) == IOR
5893 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5894 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5895 else if (GET_CODE (false_rtx) == IOR
5896 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5897 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5898 else if (GET_CODE (false_rtx) == IOR
5899 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5900 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5902 term2 = simplify_gen_binary (AND, GET_MODE (src),
5903 XEXP (XEXP (src, 0), 0), true_rtx);
5904 term3 = simplify_gen_binary (AND, GET_MODE (src),
5905 simplify_gen_unary (NOT, GET_MODE (src),
5906 XEXP (XEXP (src, 0), 0),
5911 simplify_gen_binary (IOR, GET_MODE (src),
5912 simplify_gen_binary (IOR, GET_MODE (src),
5919 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5920 whole thing fail. */
5921 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5923 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5926 /* Convert this into a field assignment operation, if possible. */
5927 return make_field_assignment (x);
5930 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5934 simplify_logical (rtx x)
5936 enum machine_mode mode = GET_MODE (x);
5937 rtx op0 = XEXP (x, 0);
5938 rtx op1 = XEXP (x, 1);
5940 switch (GET_CODE (x))
5943 /* We can call simplify_and_const_int only if we don't lose
5944 any (sign) bits when converting INTVAL (op1) to
5945 "unsigned HOST_WIDE_INT". */
5946 if (CONST_INT_P (op1)
5947 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5948 || INTVAL (op1) > 0))
5950 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5951 if (GET_CODE (x) != AND)
5958 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5959 apply the distributive law and then the inverse distributive
5960 law to see if things simplify. */
5961 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5963 rtx result = distribute_and_simplify_rtx (x, 0);
5967 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5969 rtx result = distribute_and_simplify_rtx (x, 1);
5976 /* If we have (ior (and A B) C), apply the distributive law and then
5977 the inverse distributive law to see if things simplify. */
5979 if (GET_CODE (op0) == AND)
5981 rtx result = distribute_and_simplify_rtx (x, 0);
5986 if (GET_CODE (op1) == AND)
5988 rtx result = distribute_and_simplify_rtx (x, 1);
6001 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6002 operations" because they can be replaced with two more basic operations.
6003 ZERO_EXTEND is also considered "compound" because it can be replaced with
6004 an AND operation, which is simpler, though only one operation.
6006 The function expand_compound_operation is called with an rtx expression
6007 and will convert it to the appropriate shifts and AND operations,
6008 simplifying at each stage.
6010 The function make_compound_operation is called to convert an expression
6011 consisting of shifts and ANDs into the equivalent compound expression.
6012 It is the inverse of this function, loosely speaking. */
6015 expand_compound_operation (rtx x)
6017 unsigned HOST_WIDE_INT pos = 0, len;
6019 unsigned int modewidth;
6022 switch (GET_CODE (x))
6027 /* We can't necessarily use a const_int for a multiword mode;
6028 it depends on implicitly extending the value.
6029 Since we don't know the right way to extend it,
6030 we can't tell whether the implicit way is right.
6032 Even for a mode that is no wider than a const_int,
6033 we can't win, because we need to sign extend one of its bits through
6034 the rest of it, and we don't know which bit. */
6035 if (CONST_INT_P (XEXP (x, 0)))
6038 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6039 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6040 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6041 reloaded. If not for that, MEM's would very rarely be safe.
6043 Reject MODEs bigger than a word, because we might not be able
6044 to reference a two-register group starting with an arbitrary register
6045 (and currently gen_lowpart might crash for a SUBREG). */
6047 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6050 /* Reject MODEs that aren't scalar integers because turning vector
6051 or complex modes into shifts causes problems. */
6053 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6056 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6057 /* If the inner object has VOIDmode (the only way this can happen
6058 is if it is an ASM_OPERANDS), we can't do anything since we don't
6059 know how much masking to do. */
6068 /* ... fall through ... */
6071 /* If the operand is a CLOBBER, just return it. */
6072 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6075 if (!CONST_INT_P (XEXP (x, 1))
6076 || !CONST_INT_P (XEXP (x, 2))
6077 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6080 /* Reject MODEs that aren't scalar integers because turning vector
6081 or complex modes into shifts causes problems. */
6083 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6086 len = INTVAL (XEXP (x, 1));
6087 pos = INTVAL (XEXP (x, 2));
6089 /* This should stay within the object being extracted, fail otherwise. */
6090 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6093 if (BITS_BIG_ENDIAN)
6094 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6101 /* Convert sign extension to zero extension, if we know that the high
6102 bit is not set, as this is easier to optimize. It will be converted
6103 back to cheaper alternative in make_extraction. */
6104 if (GET_CODE (x) == SIGN_EXTEND
6105 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6106 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6107 & ~(((unsigned HOST_WIDE_INT)
6108 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6112 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6113 rtx temp2 = expand_compound_operation (temp);
6115 /* Make sure this is a profitable operation. */
6116 if (rtx_cost (x, SET, optimize_this_for_speed_p)
6117 > rtx_cost (temp2, SET, optimize_this_for_speed_p))
6119 else if (rtx_cost (x, SET, optimize_this_for_speed_p)
6120 > rtx_cost (temp, SET, optimize_this_for_speed_p))
6126 /* We can optimize some special cases of ZERO_EXTEND. */
6127 if (GET_CODE (x) == ZERO_EXTEND)
6129 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6130 know that the last value didn't have any inappropriate bits
6132 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6133 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6134 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6135 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6136 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6137 return XEXP (XEXP (x, 0), 0);
6139 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6140 if (GET_CODE (XEXP (x, 0)) == SUBREG
6141 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6142 && subreg_lowpart_p (XEXP (x, 0))
6143 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6144 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6145 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6146 return SUBREG_REG (XEXP (x, 0));
6148 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6149 is a comparison and STORE_FLAG_VALUE permits. This is like
6150 the first case, but it works even when GET_MODE (x) is larger
6151 than HOST_WIDE_INT. */
6152 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6153 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6154 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6155 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6156 <= HOST_BITS_PER_WIDE_INT)
6157 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6158 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6159 return XEXP (XEXP (x, 0), 0);
6161 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6162 if (GET_CODE (XEXP (x, 0)) == SUBREG
6163 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6164 && subreg_lowpart_p (XEXP (x, 0))
6165 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6166 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6167 <= HOST_BITS_PER_WIDE_INT)
6168 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6169 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6170 return SUBREG_REG (XEXP (x, 0));
6174 /* If we reach here, we want to return a pair of shifts. The inner
6175 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6176 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6177 logical depending on the value of UNSIGNEDP.
6179 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6180 converted into an AND of a shift.
6182 We must check for the case where the left shift would have a negative
6183 count. This can happen in a case like (x >> 31) & 255 on machines
6184 that can't shift by a constant. On those machines, we would first
6185 combine the shift with the AND to produce a variable-position
6186 extraction. Then the constant of 31 would be substituted in to produce
6187 a such a position. */
6189 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6190 if (modewidth + len >= pos)
6192 enum machine_mode mode = GET_MODE (x);
6193 tem = gen_lowpart (mode, XEXP (x, 0));
6194 if (!tem || GET_CODE (tem) == CLOBBER)
6196 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6197 tem, modewidth - pos - len);
6198 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6199 mode, tem, modewidth - len);
6201 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6202 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6203 simplify_shift_const (NULL_RTX, LSHIFTRT,
6206 ((HOST_WIDE_INT) 1 << len) - 1);
6208 /* Any other cases we can't handle. */
6211 /* If we couldn't do this for some reason, return the original
6213 if (GET_CODE (tem) == CLOBBER)
6219 /* X is a SET which contains an assignment of one object into
6220 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6221 or certain SUBREGS). If possible, convert it into a series of
6224 We half-heartedly support variable positions, but do not at all
6225 support variable lengths. */
6228 expand_field_assignment (const_rtx x)
6231 rtx pos; /* Always counts from low bit. */
6233 rtx mask, cleared, masked;
6234 enum machine_mode compute_mode;
6236 /* Loop until we find something we can't simplify. */
6239 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6240 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6242 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6243 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6244 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6246 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6247 && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6249 inner = XEXP (SET_DEST (x), 0);
6250 len = INTVAL (XEXP (SET_DEST (x), 1));
6251 pos = XEXP (SET_DEST (x), 2);
6253 /* A constant position should stay within the width of INNER. */
6254 if (CONST_INT_P (pos)
6255 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6258 if (BITS_BIG_ENDIAN)
6260 if (CONST_INT_P (pos))
6261 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6263 else if (GET_CODE (pos) == MINUS
6264 && CONST_INT_P (XEXP (pos, 1))
6265 && (INTVAL (XEXP (pos, 1))
6266 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6267 /* If position is ADJUST - X, new position is X. */
6268 pos = XEXP (pos, 0);
6270 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6271 GEN_INT (GET_MODE_BITSIZE (
6278 /* A SUBREG between two modes that occupy the same numbers of words
6279 can be done by moving the SUBREG to the source. */
6280 else if (GET_CODE (SET_DEST (x)) == SUBREG
6281 /* We need SUBREGs to compute nonzero_bits properly. */
6282 && nonzero_sign_valid
6283 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6284 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6285 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6286 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6288 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6290 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6297 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6298 inner = SUBREG_REG (inner);
6300 compute_mode = GET_MODE (inner);
6302 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6303 if (! SCALAR_INT_MODE_P (compute_mode))
6305 enum machine_mode imode;
6307 /* Don't do anything for vector or complex integral types. */
6308 if (! FLOAT_MODE_P (compute_mode))
6311 /* Try to find an integral mode to pun with. */
6312 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6313 if (imode == BLKmode)
6316 compute_mode = imode;
6317 inner = gen_lowpart (imode, inner);
6320 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6321 if (len >= HOST_BITS_PER_WIDE_INT)
6324 /* Now compute the equivalent expression. Make a copy of INNER
6325 for the SET_DEST in case it is a MEM into which we will substitute;
6326 we don't want shared RTL in that case. */
6327 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6328 cleared = simplify_gen_binary (AND, compute_mode,
6329 simplify_gen_unary (NOT, compute_mode,
6330 simplify_gen_binary (ASHIFT,
6335 masked = simplify_gen_binary (ASHIFT, compute_mode,
6336 simplify_gen_binary (
6338 gen_lowpart (compute_mode, SET_SRC (x)),
6342 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6343 simplify_gen_binary (IOR, compute_mode,
6350 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6351 it is an RTX that represents a variable starting position; otherwise,
6352 POS is the (constant) starting bit position (counted from the LSB).
6354 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6357 IN_DEST is nonzero if this is a reference in the destination of a
6358 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6359 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6362 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6363 ZERO_EXTRACT should be built even for bits starting at bit 0.
6365 MODE is the desired mode of the result (if IN_DEST == 0).
6367 The result is an RTX for the extraction or NULL_RTX if the target
6371 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6372 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6373 int in_dest, int in_compare)
6375 /* This mode describes the size of the storage area
6376 to fetch the overall value from. Within that, we
6377 ignore the POS lowest bits, etc. */
6378 enum machine_mode is_mode = GET_MODE (inner);
6379 enum machine_mode inner_mode;
6380 enum machine_mode wanted_inner_mode;
6381 enum machine_mode wanted_inner_reg_mode = word_mode;
6382 enum machine_mode pos_mode = word_mode;
6383 enum machine_mode extraction_mode = word_mode;
6384 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6386 rtx orig_pos_rtx = pos_rtx;
6387 HOST_WIDE_INT orig_pos;
6389 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6391 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6392 consider just the QI as the memory to extract from.
6393 The subreg adds or removes high bits; its mode is
6394 irrelevant to the meaning of this extraction,
6395 since POS and LEN count from the lsb. */
6396 if (MEM_P (SUBREG_REG (inner)))
6397 is_mode = GET_MODE (SUBREG_REG (inner));
6398 inner = SUBREG_REG (inner);
6400 else if (GET_CODE (inner) == ASHIFT
6401 && CONST_INT_P (XEXP (inner, 1))
6402 && pos_rtx == 0 && pos == 0
6403 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6405 /* We're extracting the least significant bits of an rtx
6406 (ashift X (const_int C)), where LEN > C. Extract the
6407 least significant (LEN - C) bits of X, giving an rtx
6408 whose mode is MODE, then shift it left C times. */
6409 new_rtx = make_extraction (mode, XEXP (inner, 0),
6410 0, 0, len - INTVAL (XEXP (inner, 1)),
6411 unsignedp, in_dest, in_compare);
6413 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6416 inner_mode = GET_MODE (inner);
6418 if (pos_rtx && CONST_INT_P (pos_rtx))
6419 pos = INTVAL (pos_rtx), pos_rtx = 0;
6421 /* See if this can be done without an extraction. We never can if the
6422 width of the field is not the same as that of some integer mode. For
6423 registers, we can only avoid the extraction if the position is at the
6424 low-order bit and this is either not in the destination or we have the
6425 appropriate STRICT_LOW_PART operation available.
6427 For MEM, we can avoid an extract if the field starts on an appropriate
6428 boundary and we can change the mode of the memory reference. */
6430 if (tmode != BLKmode
6431 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6433 && (inner_mode == tmode
6435 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6436 GET_MODE_BITSIZE (inner_mode))
6437 || reg_truncated_to_mode (tmode, inner))
6440 && have_insn_for (STRICT_LOW_PART, tmode))))
6441 || (MEM_P (inner) && pos_rtx == 0
6443 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6444 : BITS_PER_UNIT)) == 0
6445 /* We can't do this if we are widening INNER_MODE (it
6446 may not be aligned, for one thing). */
6447 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6448 && (inner_mode == tmode
6449 || (! mode_dependent_address_p (XEXP (inner, 0))
6450 && ! MEM_VOLATILE_P (inner))))))
6452 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6453 field. If the original and current mode are the same, we need not
6454 adjust the offset. Otherwise, we do if bytes big endian.
6456 If INNER is not a MEM, get a piece consisting of just the field
6457 of interest (in this case POS % BITS_PER_WORD must be 0). */
6461 HOST_WIDE_INT offset;
6463 /* POS counts from lsb, but make OFFSET count in memory order. */
6464 if (BYTES_BIG_ENDIAN)
6465 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6467 offset = pos / BITS_PER_UNIT;
6469 new_rtx = adjust_address_nv (inner, tmode, offset);
6471 else if (REG_P (inner))
6473 if (tmode != inner_mode)
6475 /* We can't call gen_lowpart in a DEST since we
6476 always want a SUBREG (see below) and it would sometimes
6477 return a new hard register. */
6480 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6482 if (WORDS_BIG_ENDIAN
6483 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6484 final_word = ((GET_MODE_SIZE (inner_mode)
6485 - GET_MODE_SIZE (tmode))
6486 / UNITS_PER_WORD) - final_word;
6488 final_word *= UNITS_PER_WORD;
6489 if (BYTES_BIG_ENDIAN &&
6490 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6491 final_word += (GET_MODE_SIZE (inner_mode)
6492 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6494 /* Avoid creating invalid subregs, for example when
6495 simplifying (x>>32)&255. */
6496 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6499 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6502 new_rtx = gen_lowpart (tmode, inner);
6508 new_rtx = force_to_mode (inner, tmode,
6509 len >= HOST_BITS_PER_WIDE_INT
6510 ? ~(unsigned HOST_WIDE_INT) 0
6511 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6514 /* If this extraction is going into the destination of a SET,
6515 make a STRICT_LOW_PART unless we made a MEM. */
6518 return (MEM_P (new_rtx) ? new_rtx
6519 : (GET_CODE (new_rtx) != SUBREG
6520 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6521 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6526 if (CONST_INT_P (new_rtx))
6527 return gen_int_mode (INTVAL (new_rtx), mode);
6529 /* If we know that no extraneous bits are set, and that the high
6530 bit is not set, convert the extraction to the cheaper of
6531 sign and zero extension, that are equivalent in these cases. */
6532 if (flag_expensive_optimizations
6533 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6534 && ((nonzero_bits (new_rtx, tmode)
6535 & ~(((unsigned HOST_WIDE_INT)
6536 GET_MODE_MASK (tmode))
6540 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6541 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6543 /* Prefer ZERO_EXTENSION, since it gives more information to
6545 if (rtx_cost (temp, SET, optimize_this_for_speed_p)
6546 <= rtx_cost (temp1, SET, optimize_this_for_speed_p))
6551 /* Otherwise, sign- or zero-extend unless we already are in the
6554 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6558 /* Unless this is a COMPARE or we have a funny memory reference,
6559 don't do anything with zero-extending field extracts starting at
6560 the low-order bit since they are simple AND operations. */
6561 if (pos_rtx == 0 && pos == 0 && ! in_dest
6562 && ! in_compare && unsignedp)
6565 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6566 if the position is not a constant and the length is not 1. In all
6567 other cases, we would only be going outside our object in cases when
6568 an original shift would have been undefined. */
6570 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6571 || (pos_rtx != 0 && len != 1)))
6574 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6575 and the mode for the result. */
6576 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6578 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6579 pos_mode = mode_for_extraction (EP_insv, 2);
6580 extraction_mode = mode_for_extraction (EP_insv, 3);
6583 if (! in_dest && unsignedp
6584 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6586 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6587 pos_mode = mode_for_extraction (EP_extzv, 3);
6588 extraction_mode = mode_for_extraction (EP_extzv, 0);
6591 if (! in_dest && ! unsignedp
6592 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6594 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6595 pos_mode = mode_for_extraction (EP_extv, 3);
6596 extraction_mode = mode_for_extraction (EP_extv, 0);
6599 /* Never narrow an object, since that might not be safe. */
6601 if (mode != VOIDmode
6602 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6603 extraction_mode = mode;
6605 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6606 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6607 pos_mode = GET_MODE (pos_rtx);
6609 /* If this is not from memory, the desired mode is the preferred mode
6610 for an extraction pattern's first input operand, or word_mode if there
6613 wanted_inner_mode = wanted_inner_reg_mode;
6616 /* Be careful not to go beyond the extracted object and maintain the
6617 natural alignment of the memory. */
6618 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6619 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6620 > GET_MODE_BITSIZE (wanted_inner_mode))
6622 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6623 gcc_assert (wanted_inner_mode != VOIDmode);
6626 /* If we have to change the mode of memory and cannot, the desired mode
6627 is EXTRACTION_MODE. */
6628 if (inner_mode != wanted_inner_mode
6629 && (mode_dependent_address_p (XEXP (inner, 0))
6630 || MEM_VOLATILE_P (inner)
6632 wanted_inner_mode = extraction_mode;
6637 if (BITS_BIG_ENDIAN)
6639 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6640 BITS_BIG_ENDIAN style. If position is constant, compute new
6641 position. Otherwise, build subtraction.
6642 Note that POS is relative to the mode of the original argument.
6643 If it's a MEM we need to recompute POS relative to that.
6644 However, if we're extracting from (or inserting into) a register,
6645 we want to recompute POS relative to wanted_inner_mode. */
6646 int width = (MEM_P (inner)
6647 ? GET_MODE_BITSIZE (is_mode)
6648 : GET_MODE_BITSIZE (wanted_inner_mode));
6651 pos = width - len - pos;
6654 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6655 /* POS may be less than 0 now, but we check for that below.
6656 Note that it can only be less than 0 if !MEM_P (inner). */
6659 /* If INNER has a wider mode, and this is a constant extraction, try to
6660 make it smaller and adjust the byte to point to the byte containing
6662 if (wanted_inner_mode != VOIDmode
6663 && inner_mode != wanted_inner_mode
6665 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6667 && ! mode_dependent_address_p (XEXP (inner, 0))
6668 && ! MEM_VOLATILE_P (inner))
6672 /* The computations below will be correct if the machine is big
6673 endian in both bits and bytes or little endian in bits and bytes.
6674 If it is mixed, we must adjust. */
6676 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6677 adjust OFFSET to compensate. */
6678 if (BYTES_BIG_ENDIAN
6679 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6680 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6682 /* We can now move to the desired byte. */
6683 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6684 * GET_MODE_SIZE (wanted_inner_mode);
6685 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6687 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6688 && is_mode != wanted_inner_mode)
6689 offset = (GET_MODE_SIZE (is_mode)
6690 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6692 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6695 /* If INNER is not memory, we can always get it into the proper mode. If we
6696 are changing its mode, POS must be a constant and smaller than the size
6698 else if (!MEM_P (inner))
6700 if (GET_MODE (inner) != wanted_inner_mode
6702 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6708 inner = force_to_mode (inner, wanted_inner_mode,
6710 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6711 ? ~(unsigned HOST_WIDE_INT) 0
6712 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6717 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6718 have to zero extend. Otherwise, we can just use a SUBREG. */
6720 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6722 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6724 /* If we know that no extraneous bits are set, and that the high
6725 bit is not set, convert extraction to cheaper one - either
6726 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6728 if (flag_expensive_optimizations
6729 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6730 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6731 & ~(((unsigned HOST_WIDE_INT)
6732 GET_MODE_MASK (GET_MODE (pos_rtx)))
6736 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6738 /* Prefer ZERO_EXTENSION, since it gives more information to
6740 if (rtx_cost (temp1, SET, optimize_this_for_speed_p)
6741 < rtx_cost (temp, SET, optimize_this_for_speed_p))
6746 else if (pos_rtx != 0
6747 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6748 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6750 /* Make POS_RTX unless we already have it and it is correct. If we don't
6751 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6753 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6754 pos_rtx = orig_pos_rtx;
6756 else if (pos_rtx == 0)
6757 pos_rtx = GEN_INT (pos);
6759 /* Make the required operation. See if we can use existing rtx. */
6760 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6761 extraction_mode, inner, GEN_INT (len), pos_rtx);
6763 new_rtx = gen_lowpart (mode, new_rtx);
6768 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6769 with any other operations in X. Return X without that shift if so. */
6772 extract_left_shift (rtx x, int count)
6774 enum rtx_code code = GET_CODE (x);
6775 enum machine_mode mode = GET_MODE (x);
6781 /* This is the shift itself. If it is wide enough, we will return
6782 either the value being shifted if the shift count is equal to
6783 COUNT or a shift for the difference. */
6784 if (CONST_INT_P (XEXP (x, 1))
6785 && INTVAL (XEXP (x, 1)) >= count)
6786 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6787 INTVAL (XEXP (x, 1)) - count);
6791 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6792 return simplify_gen_unary (code, mode, tem, mode);
6796 case PLUS: case IOR: case XOR: case AND:
6797 /* If we can safely shift this constant and we find the inner shift,
6798 make a new operation. */
6799 if (CONST_INT_P (XEXP (x, 1))
6800 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6801 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6802 return simplify_gen_binary (code, mode, tem,
6803 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6814 /* Look at the expression rooted at X. Look for expressions
6815 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6816 Form these expressions.
6818 Return the new rtx, usually just X.
6820 Also, for machines like the VAX that don't have logical shift insns,
6821 try to convert logical to arithmetic shift operations in cases where
6822 they are equivalent. This undoes the canonicalizations to logical
6823 shifts done elsewhere.
6825 We try, as much as possible, to re-use rtl expressions to save memory.
6827 IN_CODE says what kind of expression we are processing. Normally, it is
6828 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6829 being kludges), it is MEM. When processing the arguments of a comparison
6830 or a COMPARE against zero, it is COMPARE. */
6833 make_compound_operation (rtx x, enum rtx_code in_code)
6835 enum rtx_code code = GET_CODE (x);
6836 enum machine_mode mode = GET_MODE (x);
6837 int mode_width = GET_MODE_BITSIZE (mode);
6839 enum rtx_code next_code;
6845 /* Select the code to be used in recursive calls. Once we are inside an
6846 address, we stay there. If we have a comparison, set to COMPARE,
6847 but once inside, go back to our default of SET. */
6849 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6850 : ((code == COMPARE || COMPARISON_P (x))
6851 && XEXP (x, 1) == const0_rtx) ? COMPARE
6852 : in_code == COMPARE ? SET : in_code);
6854 /* Process depending on the code of this operation. If NEW is set
6855 nonzero, it will be returned. */
6860 /* Convert shifts by constants into multiplications if inside
6862 if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
6863 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6864 && INTVAL (XEXP (x, 1)) >= 0)
6866 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6867 new_rtx = gen_rtx_MULT (mode, new_rtx,
6868 GEN_INT ((HOST_WIDE_INT) 1
6869 << INTVAL (XEXP (x, 1))));
6874 /* If the second operand is not a constant, we can't do anything
6876 if (!CONST_INT_P (XEXP (x, 1)))
6879 /* If the constant is a power of two minus one and the first operand
6880 is a logical right shift, make an extraction. */
6881 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6882 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6884 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6885 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6886 0, in_code == COMPARE);
6889 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6890 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6891 && subreg_lowpart_p (XEXP (x, 0))
6892 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6893 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6895 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6897 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6898 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6899 0, in_code == COMPARE);
6901 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6902 else if ((GET_CODE (XEXP (x, 0)) == XOR
6903 || GET_CODE (XEXP (x, 0)) == IOR)
6904 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6905 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6906 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6908 /* Apply the distributive law, and then try to make extractions. */
6909 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6910 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6912 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6914 new_rtx = make_compound_operation (new_rtx, in_code);
6917 /* If we are have (and (rotate X C) M) and C is larger than the number
6918 of bits in M, this is an extraction. */
6920 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6921 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6922 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6923 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6925 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6926 new_rtx = make_extraction (mode, new_rtx,
6927 (GET_MODE_BITSIZE (mode)
6928 - INTVAL (XEXP (XEXP (x, 0), 1))),
6929 NULL_RTX, i, 1, 0, in_code == COMPARE);
6932 /* On machines without logical shifts, if the operand of the AND is
6933 a logical shift and our mask turns off all the propagated sign
6934 bits, we can replace the logical shift with an arithmetic shift. */
6935 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6936 && !have_insn_for (LSHIFTRT, mode)
6937 && have_insn_for (ASHIFTRT, mode)
6938 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
6939 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6940 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6941 && mode_width <= HOST_BITS_PER_WIDE_INT)
6943 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6945 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6946 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6948 gen_rtx_ASHIFTRT (mode,
6949 make_compound_operation
6950 (XEXP (XEXP (x, 0), 0), next_code),
6951 XEXP (XEXP (x, 0), 1)));
6954 /* If the constant is one less than a power of two, this might be
6955 representable by an extraction even if no shift is present.
6956 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6957 we are in a COMPARE. */
6958 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6959 new_rtx = make_extraction (mode,
6960 make_compound_operation (XEXP (x, 0),
6962 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6964 /* If we are in a comparison and this is an AND with a power of two,
6965 convert this into the appropriate bit extract. */
6966 else if (in_code == COMPARE
6967 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6968 new_rtx = make_extraction (mode,
6969 make_compound_operation (XEXP (x, 0),
6971 i, NULL_RTX, 1, 1, 0, 1);
6976 /* If the sign bit is known to be zero, replace this with an
6977 arithmetic shift. */
6978 if (have_insn_for (ASHIFTRT, mode)
6979 && ! have_insn_for (LSHIFTRT, mode)
6980 && mode_width <= HOST_BITS_PER_WIDE_INT
6981 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6983 new_rtx = gen_rtx_ASHIFTRT (mode,
6984 make_compound_operation (XEXP (x, 0),
6990 /* ... fall through ... */
6996 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6997 this is a SIGN_EXTRACT. */
6998 if (CONST_INT_P (rhs)
6999 && GET_CODE (lhs) == ASHIFT
7000 && CONST_INT_P (XEXP (lhs, 1))
7001 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7002 && INTVAL (rhs) < mode_width)
7004 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7005 new_rtx = make_extraction (mode, new_rtx,
7006 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7007 NULL_RTX, mode_width - INTVAL (rhs),
7008 code == LSHIFTRT, 0, in_code == COMPARE);
7012 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7013 If so, try to merge the shifts into a SIGN_EXTEND. We could
7014 also do this for some cases of SIGN_EXTRACT, but it doesn't
7015 seem worth the effort; the case checked for occurs on Alpha. */
7018 && ! (GET_CODE (lhs) == SUBREG
7019 && (OBJECT_P (SUBREG_REG (lhs))))
7020 && CONST_INT_P (rhs)
7021 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7022 && INTVAL (rhs) < mode_width
7023 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7024 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7025 0, NULL_RTX, mode_width - INTVAL (rhs),
7026 code == LSHIFTRT, 0, in_code == COMPARE);
7031 /* Call ourselves recursively on the inner expression. If we are
7032 narrowing the object and it has a different RTL code from
7033 what it originally did, do this SUBREG as a force_to_mode. */
7035 tem = make_compound_operation (SUBREG_REG (x), in_code);
7039 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7045 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7046 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7047 && subreg_lowpart_p (x))
7049 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7052 /* If we have something other than a SUBREG, we might have
7053 done an expansion, so rerun ourselves. */
7054 if (GET_CODE (newer) != SUBREG)
7055 newer = make_compound_operation (newer, in_code);
7071 x = gen_lowpart (mode, new_rtx);
7072 code = GET_CODE (x);
7075 /* Now recursively process each operand of this operation. */
7076 fmt = GET_RTX_FORMAT (code);
7077 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7080 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7081 SUBST (XEXP (x, i), new_rtx);
7083 else if (fmt[i] == 'E')
7084 for (j = 0; j < XVECLEN (x, i); j++)
7086 new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7087 SUBST (XVECEXP (x, i, j), new_rtx);
7090 /* If this is a commutative operation, the changes to the operands
7091 may have made it noncanonical. */
7092 if (COMMUTATIVE_ARITH_P (x)
7093 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7096 SUBST (XEXP (x, 0), XEXP (x, 1));
7097 SUBST (XEXP (x, 1), tem);
7103 /* Given M see if it is a value that would select a field of bits
7104 within an item, but not the entire word. Return -1 if not.
7105 Otherwise, return the starting position of the field, where 0 is the
7108 *PLEN is set to the length of the field. */
7111 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7113 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7114 int pos = exact_log2 (m & -m);
7118 /* Now shift off the low-order zero bits and see if we have a
7119 power of two minus 1. */
7120 len = exact_log2 ((m >> pos) + 1);
7129 /* If X refers to a register that equals REG in value, replace these
7130 references with REG. */
7132 canon_reg_for_combine (rtx x, rtx reg)
7139 enum rtx_code code = GET_CODE (x);
7140 switch (GET_RTX_CLASS (code))
7143 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7144 if (op0 != XEXP (x, 0))
7145 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7150 case RTX_COMM_ARITH:
7151 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7152 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7153 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7154 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7158 case RTX_COMM_COMPARE:
7159 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7160 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7161 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7162 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7163 GET_MODE (op0), op0, op1);
7167 case RTX_BITFIELD_OPS:
7168 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7169 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7170 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7171 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7172 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7173 GET_MODE (op0), op0, op1, op2);
7178 if (rtx_equal_p (get_last_value (reg), x)
7179 || rtx_equal_p (reg, get_last_value (x)))
7188 fmt = GET_RTX_FORMAT (code);
7190 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7193 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7194 if (op != XEXP (x, i))
7204 else if (fmt[i] == 'E')
7207 for (j = 0; j < XVECLEN (x, i); j++)
7209 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7210 if (op != XVECEXP (x, i, j))
7217 XVECEXP (x, i, j) = op;
7228 /* Return X converted to MODE. If the value is already truncated to
7229 MODE we can just return a subreg even though in the general case we
7230 would need an explicit truncation. */
7233 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7235 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7236 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7237 GET_MODE_BITSIZE (GET_MODE (x)))
7238 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7239 return gen_lowpart (mode, x);
7241 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7244 /* See if X can be simplified knowing that we will only refer to it in
7245 MODE and will only refer to those bits that are nonzero in MASK.
7246 If other bits are being computed or if masking operations are done
7247 that select a superset of the bits in MASK, they can sometimes be
7250 Return a possibly simplified expression, but always convert X to
7251 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7253 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7254 are all off in X. This is used when X will be complemented, by either
7255 NOT, NEG, or XOR. */
7258 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7261 enum rtx_code code = GET_CODE (x);
7262 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7263 enum machine_mode op_mode;
7264 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7267 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7268 code below will do the wrong thing since the mode of such an
7269 expression is VOIDmode.
7271 Also do nothing if X is a CLOBBER; this can happen if X was
7272 the return value from a call to gen_lowpart. */
7273 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7276 /* We want to perform the operation is its present mode unless we know
7277 that the operation is valid in MODE, in which case we do the operation
7279 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7280 && have_insn_for (code, mode))
7281 ? mode : GET_MODE (x));
7283 /* It is not valid to do a right-shift in a narrower mode
7284 than the one it came in with. */
7285 if ((code == LSHIFTRT || code == ASHIFTRT)
7286 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7287 op_mode = GET_MODE (x);
7289 /* Truncate MASK to fit OP_MODE. */
7291 mask &= GET_MODE_MASK (op_mode);
7293 /* When we have an arithmetic operation, or a shift whose count we
7294 do not know, we need to assume that all bits up to the highest-order
7295 bit in MASK will be needed. This is how we form such a mask. */
7296 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7297 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7299 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7302 /* Determine what bits of X are guaranteed to be (non)zero. */
7303 nonzero = nonzero_bits (x, mode);
7305 /* If none of the bits in X are needed, return a zero. */
7306 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7309 /* If X is a CONST_INT, return a new one. Do this here since the
7310 test below will fail. */
7311 if (CONST_INT_P (x))
7313 if (SCALAR_INT_MODE_P (mode))
7314 return gen_int_mode (INTVAL (x) & mask, mode);
7317 x = GEN_INT (INTVAL (x) & mask);
7318 return gen_lowpart_common (mode, x);
7322 /* If X is narrower than MODE and we want all the bits in X's mode, just
7323 get X in the proper mode. */
7324 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7325 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7326 return gen_lowpart (mode, x);
7328 /* The arithmetic simplifications here do the wrong thing on vector modes. */
7329 if (VECTOR_MODE_P (mode) || VECTOR_MODE_P (GET_MODE (x)))
7330 return gen_lowpart (mode, x);
7335 /* If X is a (clobber (const_int)), return it since we know we are
7336 generating something that won't match. */
7343 x = expand_compound_operation (x);
7344 if (GET_CODE (x) != code)
7345 return force_to_mode (x, mode, mask, next_select);
7349 if (subreg_lowpart_p (x)
7350 /* We can ignore the effect of this SUBREG if it narrows the mode or
7351 if the constant masks to zero all the bits the mode doesn't
7353 && ((GET_MODE_SIZE (GET_MODE (x))
7354 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7356 & GET_MODE_MASK (GET_MODE (x))
7357 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7358 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7362 /* If this is an AND with a constant, convert it into an AND
7363 whose constant is the AND of that constant with MASK. If it
7364 remains an AND of MASK, delete it since it is redundant. */
7366 if (CONST_INT_P (XEXP (x, 1)))
7368 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7369 mask & INTVAL (XEXP (x, 1)));
7371 /* If X is still an AND, see if it is an AND with a mask that
7372 is just some low-order bits. If so, and it is MASK, we don't
7375 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7376 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7380 /* If it remains an AND, try making another AND with the bits
7381 in the mode mask that aren't in MASK turned on. If the
7382 constant in the AND is wide enough, this might make a
7383 cheaper constant. */
7385 if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
7386 && GET_MODE_MASK (GET_MODE (x)) != mask
7387 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7389 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7390 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7391 int width = GET_MODE_BITSIZE (GET_MODE (x));
7394 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7395 number, sign extend it. */
7396 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7397 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7398 cval |= (HOST_WIDE_INT) -1 << width;
7400 y = simplify_gen_binary (AND, GET_MODE (x),
7401 XEXP (x, 0), GEN_INT (cval));
7402 if (rtx_cost (y, SET, optimize_this_for_speed_p)
7403 < rtx_cost (x, SET, optimize_this_for_speed_p))
7413 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7414 low-order bits (as in an alignment operation) and FOO is already
7415 aligned to that boundary, mask C1 to that boundary as well.
7416 This may eliminate that PLUS and, later, the AND. */
7419 unsigned int width = GET_MODE_BITSIZE (mode);
7420 unsigned HOST_WIDE_INT smask = mask;
7422 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7423 number, sign extend it. */
7425 if (width < HOST_BITS_PER_WIDE_INT
7426 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7427 smask |= (HOST_WIDE_INT) -1 << width;
7429 if (CONST_INT_P (XEXP (x, 1))
7430 && exact_log2 (- smask) >= 0
7431 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7432 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7433 return force_to_mode (plus_constant (XEXP (x, 0),
7434 (INTVAL (XEXP (x, 1)) & smask)),
7435 mode, smask, next_select);
7438 /* ... fall through ... */
7441 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7442 most significant bit in MASK since carries from those bits will
7443 affect the bits we are interested in. */
7448 /* If X is (minus C Y) where C's least set bit is larger than any bit
7449 in the mask, then we may replace with (neg Y). */
7450 if (CONST_INT_P (XEXP (x, 0))
7451 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7452 & -INTVAL (XEXP (x, 0))))
7455 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7457 return force_to_mode (x, mode, mask, next_select);
7460 /* Similarly, if C contains every bit in the fuller_mask, then we may
7461 replace with (not Y). */
7462 if (CONST_INT_P (XEXP (x, 0))
7463 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7464 == INTVAL (XEXP (x, 0))))
7466 x = simplify_gen_unary (NOT, GET_MODE (x),
7467 XEXP (x, 1), GET_MODE (x));
7468 return force_to_mode (x, mode, mask, next_select);
7476 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7477 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7478 operation which may be a bitfield extraction. Ensure that the
7479 constant we form is not wider than the mode of X. */
7481 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7482 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7483 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7484 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7485 && CONST_INT_P (XEXP (x, 1))
7486 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7487 + floor_log2 (INTVAL (XEXP (x, 1))))
7488 < GET_MODE_BITSIZE (GET_MODE (x)))
7489 && (INTVAL (XEXP (x, 1))
7490 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7492 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7493 << INTVAL (XEXP (XEXP (x, 0), 1)));
7494 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7495 XEXP (XEXP (x, 0), 0), temp);
7496 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7497 XEXP (XEXP (x, 0), 1));
7498 return force_to_mode (x, mode, mask, next_select);
7502 /* For most binary operations, just propagate into the operation and
7503 change the mode if we have an operation of that mode. */
7505 op0 = gen_lowpart_or_truncate (op_mode,
7506 force_to_mode (XEXP (x, 0), mode, mask,
7508 op1 = gen_lowpart_or_truncate (op_mode,
7509 force_to_mode (XEXP (x, 1), mode, mask,
7512 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7513 x = simplify_gen_binary (code, op_mode, op0, op1);
7517 /* For left shifts, do the same, but just for the first operand.
7518 However, we cannot do anything with shifts where we cannot
7519 guarantee that the counts are smaller than the size of the mode
7520 because such a count will have a different meaning in a
7523 if (! (CONST_INT_P (XEXP (x, 1))
7524 && INTVAL (XEXP (x, 1)) >= 0
7525 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7526 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7527 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7528 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7531 /* If the shift count is a constant and we can do arithmetic in
7532 the mode of the shift, refine which bits we need. Otherwise, use the
7533 conservative form of the mask. */
7534 if (CONST_INT_P (XEXP (x, 1))
7535 && INTVAL (XEXP (x, 1)) >= 0
7536 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7537 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7538 mask >>= INTVAL (XEXP (x, 1));
7542 op0 = gen_lowpart_or_truncate (op_mode,
7543 force_to_mode (XEXP (x, 0), op_mode,
7544 mask, next_select));
7546 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7547 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7551 /* Here we can only do something if the shift count is a constant,
7552 this shift constant is valid for the host, and we can do arithmetic
7555 if (CONST_INT_P (XEXP (x, 1))
7556 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7557 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7559 rtx inner = XEXP (x, 0);
7560 unsigned HOST_WIDE_INT inner_mask;
7562 /* Select the mask of the bits we need for the shift operand. */
7563 inner_mask = mask << INTVAL (XEXP (x, 1));
7565 /* We can only change the mode of the shift if we can do arithmetic
7566 in the mode of the shift and INNER_MASK is no wider than the
7567 width of X's mode. */
7568 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7569 op_mode = GET_MODE (x);
7571 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7573 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7574 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7577 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7578 shift and AND produces only copies of the sign bit (C2 is one less
7579 than a power of two), we can do this with just a shift. */
7581 if (GET_CODE (x) == LSHIFTRT
7582 && CONST_INT_P (XEXP (x, 1))
7583 /* The shift puts one of the sign bit copies in the least significant
7585 && ((INTVAL (XEXP (x, 1))
7586 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7587 >= GET_MODE_BITSIZE (GET_MODE (x)))
7588 && exact_log2 (mask + 1) >= 0
7589 /* Number of bits left after the shift must be more than the mask
7591 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7592 <= GET_MODE_BITSIZE (GET_MODE (x)))
7593 /* Must be more sign bit copies than the mask needs. */
7594 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7595 >= exact_log2 (mask + 1)))
7596 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7597 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7598 - exact_log2 (mask + 1)));
7603 /* If we are just looking for the sign bit, we don't need this shift at
7604 all, even if it has a variable count. */
7605 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7606 && (mask == ((unsigned HOST_WIDE_INT) 1
7607 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7608 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7610 /* If this is a shift by a constant, get a mask that contains those bits
7611 that are not copies of the sign bit. We then have two cases: If
7612 MASK only includes those bits, this can be a logical shift, which may
7613 allow simplifications. If MASK is a single-bit field not within
7614 those bits, we are requesting a copy of the sign bit and hence can
7615 shift the sign bit to the appropriate location. */
7617 if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
7618 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7622 /* If the considered data is wider than HOST_WIDE_INT, we can't
7623 represent a mask for all its bits in a single scalar.
7624 But we only care about the lower bits, so calculate these. */
7626 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7628 nonzero = ~(HOST_WIDE_INT) 0;
7630 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7631 is the number of bits a full-width mask would have set.
7632 We need only shift if these are fewer than nonzero can
7633 hold. If not, we must keep all bits set in nonzero. */
7635 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7636 < HOST_BITS_PER_WIDE_INT)
7637 nonzero >>= INTVAL (XEXP (x, 1))
7638 + HOST_BITS_PER_WIDE_INT
7639 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7643 nonzero = GET_MODE_MASK (GET_MODE (x));
7644 nonzero >>= INTVAL (XEXP (x, 1));
7647 if ((mask & ~nonzero) == 0)
7649 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7650 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7651 if (GET_CODE (x) != ASHIFTRT)
7652 return force_to_mode (x, mode, mask, next_select);
7655 else if ((i = exact_log2 (mask)) >= 0)
7657 x = simplify_shift_const
7658 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7659 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7661 if (GET_CODE (x) != ASHIFTRT)
7662 return force_to_mode (x, mode, mask, next_select);
7666 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7667 even if the shift count isn't a constant. */
7669 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7670 XEXP (x, 0), XEXP (x, 1));
7674 /* If this is a zero- or sign-extension operation that just affects bits
7675 we don't care about, remove it. Be sure the call above returned
7676 something that is still a shift. */
7678 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7679 && CONST_INT_P (XEXP (x, 1))
7680 && INTVAL (XEXP (x, 1)) >= 0
7681 && (INTVAL (XEXP (x, 1))
7682 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7683 && GET_CODE (XEXP (x, 0)) == ASHIFT
7684 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7685 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7692 /* If the shift count is constant and we can do computations
7693 in the mode of X, compute where the bits we care about are.
7694 Otherwise, we can't do anything. Don't change the mode of
7695 the shift or propagate MODE into the shift, though. */
7696 if (CONST_INT_P (XEXP (x, 1))
7697 && INTVAL (XEXP (x, 1)) >= 0)
7699 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7700 GET_MODE (x), GEN_INT (mask),
7702 if (temp && CONST_INT_P (temp))
7704 force_to_mode (XEXP (x, 0), GET_MODE (x),
7705 INTVAL (temp), next_select));
7710 /* If we just want the low-order bit, the NEG isn't needed since it
7711 won't change the low-order bit. */
7713 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7715 /* We need any bits less significant than the most significant bit in
7716 MASK since carries from those bits will affect the bits we are
7722 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7723 same as the XOR case above. Ensure that the constant we form is not
7724 wider than the mode of X. */
7726 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7727 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7728 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7729 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7730 < GET_MODE_BITSIZE (GET_MODE (x)))
7731 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7733 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7735 temp = simplify_gen_binary (XOR, GET_MODE (x),
7736 XEXP (XEXP (x, 0), 0), temp);
7737 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7738 temp, XEXP (XEXP (x, 0), 1));
7740 return force_to_mode (x, mode, mask, next_select);
7743 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7744 use the full mask inside the NOT. */
7748 op0 = gen_lowpart_or_truncate (op_mode,
7749 force_to_mode (XEXP (x, 0), mode, mask,
7751 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7752 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7756 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7757 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7758 which is equal to STORE_FLAG_VALUE. */
7759 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7760 && GET_MODE (XEXP (x, 0)) == mode
7761 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7762 && (nonzero_bits (XEXP (x, 0), mode)
7763 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7764 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7769 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7770 written in a narrower mode. We play it safe and do not do so. */
7773 gen_lowpart_or_truncate (GET_MODE (x),
7774 force_to_mode (XEXP (x, 1), mode,
7775 mask, next_select)));
7777 gen_lowpart_or_truncate (GET_MODE (x),
7778 force_to_mode (XEXP (x, 2), mode,
7779 mask, next_select)));
7786 /* Ensure we return a value of the proper mode. */
7787 return gen_lowpart_or_truncate (mode, x);
7790 /* Return nonzero if X is an expression that has one of two values depending on
7791 whether some other value is zero or nonzero. In that case, we return the
7792 value that is being tested, *PTRUE is set to the value if the rtx being
7793 returned has a nonzero value, and *PFALSE is set to the other alternative.
7795 If we return zero, we set *PTRUE and *PFALSE to X. */
7798 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7800 enum machine_mode mode = GET_MODE (x);
7801 enum rtx_code code = GET_CODE (x);
7802 rtx cond0, cond1, true0, true1, false0, false1;
7803 unsigned HOST_WIDE_INT nz;
7805 /* If we are comparing a value against zero, we are done. */
7806 if ((code == NE || code == EQ)
7807 && XEXP (x, 1) == const0_rtx)
7809 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7810 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7814 /* If this is a unary operation whose operand has one of two values, apply
7815 our opcode to compute those values. */
7816 else if (UNARY_P (x)
7817 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7819 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7820 *pfalse = simplify_gen_unary (code, mode, false0,
7821 GET_MODE (XEXP (x, 0)));
7825 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7826 make can't possibly match and would suppress other optimizations. */
7827 else if (code == COMPARE)
7830 /* If this is a binary operation, see if either side has only one of two
7831 values. If either one does or if both do and they are conditional on
7832 the same value, compute the new true and false values. */
7833 else if (BINARY_P (x))
7835 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7836 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7838 if ((cond0 != 0 || cond1 != 0)
7839 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7841 /* If if_then_else_cond returned zero, then true/false are the
7842 same rtl. We must copy one of them to prevent invalid rtl
7845 true0 = copy_rtx (true0);
7846 else if (cond1 == 0)
7847 true1 = copy_rtx (true1);
7849 if (COMPARISON_P (x))
7851 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7853 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7858 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7859 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7862 return cond0 ? cond0 : cond1;
7865 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7866 operands is zero when the other is nonzero, and vice-versa,
7867 and STORE_FLAG_VALUE is 1 or -1. */
7869 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7870 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7872 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7874 rtx op0 = XEXP (XEXP (x, 0), 1);
7875 rtx op1 = XEXP (XEXP (x, 1), 1);
7877 cond0 = XEXP (XEXP (x, 0), 0);
7878 cond1 = XEXP (XEXP (x, 1), 0);
7880 if (COMPARISON_P (cond0)
7881 && COMPARISON_P (cond1)
7882 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7883 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7884 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7885 || ((swap_condition (GET_CODE (cond0))
7886 == reversed_comparison_code (cond1, NULL))
7887 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7888 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7889 && ! side_effects_p (x))
7891 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7892 *pfalse = simplify_gen_binary (MULT, mode,
7894 ? simplify_gen_unary (NEG, mode,
7902 /* Similarly for MULT, AND and UMIN, except that for these the result
7904 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7905 && (code == MULT || code == AND || code == UMIN)
7906 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7908 cond0 = XEXP (XEXP (x, 0), 0);
7909 cond1 = XEXP (XEXP (x, 1), 0);
7911 if (COMPARISON_P (cond0)
7912 && COMPARISON_P (cond1)
7913 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7914 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7915 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7916 || ((swap_condition (GET_CODE (cond0))
7917 == reversed_comparison_code (cond1, NULL))
7918 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7919 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7920 && ! side_effects_p (x))
7922 *ptrue = *pfalse = const0_rtx;
7928 else if (code == IF_THEN_ELSE)
7930 /* If we have IF_THEN_ELSE already, extract the condition and
7931 canonicalize it if it is NE or EQ. */
7932 cond0 = XEXP (x, 0);
7933 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7934 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7935 return XEXP (cond0, 0);
7936 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7938 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7939 return XEXP (cond0, 0);
7945 /* If X is a SUBREG, we can narrow both the true and false values
7946 if the inner expression, if there is a condition. */
7947 else if (code == SUBREG
7948 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7951 true0 = simplify_gen_subreg (mode, true0,
7952 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7953 false0 = simplify_gen_subreg (mode, false0,
7954 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7955 if (true0 && false0)
7963 /* If X is a constant, this isn't special and will cause confusions
7964 if we treat it as such. Likewise if it is equivalent to a constant. */
7965 else if (CONSTANT_P (x)
7966 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7969 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7970 will be least confusing to the rest of the compiler. */
7971 else if (mode == BImode)
7973 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7977 /* If X is known to be either 0 or -1, those are the true and
7978 false values when testing X. */
7979 else if (x == constm1_rtx || x == const0_rtx
7980 || (mode != VOIDmode
7981 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7983 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7987 /* Likewise for 0 or a single bit. */
7988 else if (SCALAR_INT_MODE_P (mode)
7989 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7990 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7992 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7996 /* Otherwise fail; show no condition with true and false values the same. */
7997 *ptrue = *pfalse = x;
8001 /* Return the value of expression X given the fact that condition COND
8002 is known to be true when applied to REG as its first operand and VAL
8003 as its second. X is known to not be shared and so can be modified in
8006 We only handle the simplest cases, and specifically those cases that
8007 arise with IF_THEN_ELSE expressions. */
8010 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8012 enum rtx_code code = GET_CODE (x);
8017 if (side_effects_p (x))
8020 /* If either operand of the condition is a floating point value,
8021 then we have to avoid collapsing an EQ comparison. */
8023 && rtx_equal_p (x, reg)
8024 && ! FLOAT_MODE_P (GET_MODE (x))
8025 && ! FLOAT_MODE_P (GET_MODE (val)))
8028 if (cond == UNEQ && rtx_equal_p (x, reg))
8031 /* If X is (abs REG) and we know something about REG's relationship
8032 with zero, we may be able to simplify this. */
8034 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8037 case GE: case GT: case EQ:
8040 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8042 GET_MODE (XEXP (x, 0)));
8047 /* The only other cases we handle are MIN, MAX, and comparisons if the
8048 operands are the same as REG and VAL. */
8050 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8052 if (rtx_equal_p (XEXP (x, 0), val))
8053 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8055 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8057 if (COMPARISON_P (x))
8059 if (comparison_dominates_p (cond, code))
8060 return const_true_rtx;
8062 code = reversed_comparison_code (x, NULL);
8064 && comparison_dominates_p (cond, code))
8069 else if (code == SMAX || code == SMIN
8070 || code == UMIN || code == UMAX)
8072 int unsignedp = (code == UMIN || code == UMAX);
8074 /* Do not reverse the condition when it is NE or EQ.
8075 This is because we cannot conclude anything about
8076 the value of 'SMAX (x, y)' when x is not equal to y,
8077 but we can when x equals y. */
8078 if ((code == SMAX || code == UMAX)
8079 && ! (cond == EQ || cond == NE))
8080 cond = reverse_condition (cond);
8085 return unsignedp ? x : XEXP (x, 1);
8087 return unsignedp ? x : XEXP (x, 0);
8089 return unsignedp ? XEXP (x, 1) : x;
8091 return unsignedp ? XEXP (x, 0) : x;
8098 else if (code == SUBREG)
8100 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8101 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8103 if (SUBREG_REG (x) != r)
8105 /* We must simplify subreg here, before we lose track of the
8106 original inner_mode. */
8107 new_rtx = simplify_subreg (GET_MODE (x), r,
8108 inner_mode, SUBREG_BYTE (x));
8112 SUBST (SUBREG_REG (x), r);
8117 /* We don't have to handle SIGN_EXTEND here, because even in the
8118 case of replacing something with a modeless CONST_INT, a
8119 CONST_INT is already (supposed to be) a valid sign extension for
8120 its narrower mode, which implies it's already properly
8121 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8122 story is different. */
8123 else if (code == ZERO_EXTEND)
8125 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8126 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8128 if (XEXP (x, 0) != r)
8130 /* We must simplify the zero_extend here, before we lose
8131 track of the original inner_mode. */
8132 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8137 SUBST (XEXP (x, 0), r);
8143 fmt = GET_RTX_FORMAT (code);
8144 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8147 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8148 else if (fmt[i] == 'E')
8149 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8150 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8157 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8158 assignment as a field assignment. */
8161 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8163 if (x == y || rtx_equal_p (x, y))
8166 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8169 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8170 Note that all SUBREGs of MEM are paradoxical; otherwise they
8171 would have been rewritten. */
8172 if (MEM_P (x) && GET_CODE (y) == SUBREG
8173 && MEM_P (SUBREG_REG (y))
8174 && rtx_equal_p (SUBREG_REG (y),
8175 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8178 if (MEM_P (y) && GET_CODE (x) == SUBREG
8179 && MEM_P (SUBREG_REG (x))
8180 && rtx_equal_p (SUBREG_REG (x),
8181 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8184 /* We used to see if get_last_value of X and Y were the same but that's
8185 not correct. In one direction, we'll cause the assignment to have
8186 the wrong destination and in the case, we'll import a register into this
8187 insn that might have already have been dead. So fail if none of the
8188 above cases are true. */
8192 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8193 Return that assignment if so.
8195 We only handle the most common cases. */
8198 make_field_assignment (rtx x)
8200 rtx dest = SET_DEST (x);
8201 rtx src = SET_SRC (x);
8206 unsigned HOST_WIDE_INT len;
8208 enum machine_mode mode;
8210 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8211 a clear of a one-bit field. We will have changed it to
8212 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8215 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8216 && CONST_INT_P (XEXP (XEXP (src, 0), 0))
8217 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8218 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8220 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8223 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8227 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8228 && subreg_lowpart_p (XEXP (src, 0))
8229 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8230 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8231 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8232 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
8233 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8234 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8236 assign = make_extraction (VOIDmode, dest, 0,
8237 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8240 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8244 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8246 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8247 && XEXP (XEXP (src, 0), 0) == const1_rtx
8248 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8250 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8253 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8257 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8258 SRC is an AND with all bits of that field set, then we can discard
8260 if (GET_CODE (dest) == ZERO_EXTRACT
8261 && CONST_INT_P (XEXP (dest, 1))
8262 && GET_CODE (src) == AND
8263 && CONST_INT_P (XEXP (src, 1)))
8265 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8266 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8267 unsigned HOST_WIDE_INT ze_mask;
8269 if (width >= HOST_BITS_PER_WIDE_INT)
8272 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8274 /* Complete overlap. We can remove the source AND. */
8275 if ((and_mask & ze_mask) == ze_mask)
8276 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8278 /* Partial overlap. We can reduce the source AND. */
8279 if ((and_mask & ze_mask) != and_mask)
8281 mode = GET_MODE (src);
8282 src = gen_rtx_AND (mode, XEXP (src, 0),
8283 gen_int_mode (and_mask & ze_mask, mode));
8284 return gen_rtx_SET (VOIDmode, dest, src);
8288 /* The other case we handle is assignments into a constant-position
8289 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8290 a mask that has all one bits except for a group of zero bits and
8291 OTHER is known to have zeros where C1 has ones, this is such an
8292 assignment. Compute the position and length from C1. Shift OTHER
8293 to the appropriate position, force it to the required mode, and
8294 make the extraction. Check for the AND in both operands. */
8296 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8299 rhs = expand_compound_operation (XEXP (src, 0));
8300 lhs = expand_compound_operation (XEXP (src, 1));
8302 if (GET_CODE (rhs) == AND
8303 && CONST_INT_P (XEXP (rhs, 1))
8304 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8305 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8306 else if (GET_CODE (lhs) == AND
8307 && CONST_INT_P (XEXP (lhs, 1))
8308 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8309 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8313 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8314 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8315 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8316 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8319 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8323 /* The mode to use for the source is the mode of the assignment, or of
8324 what is inside a possible STRICT_LOW_PART. */
8325 mode = (GET_CODE (assign) == STRICT_LOW_PART
8326 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8328 /* Shift OTHER right POS places and make it the source, restricting it
8329 to the proper length and mode. */
8331 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8335 src = force_to_mode (src, mode,
8336 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8337 ? ~(unsigned HOST_WIDE_INT) 0
8338 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8341 /* If SRC is masked by an AND that does not make a difference in
8342 the value being stored, strip it. */
8343 if (GET_CODE (assign) == ZERO_EXTRACT
8344 && CONST_INT_P (XEXP (assign, 1))
8345 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8346 && GET_CODE (src) == AND
8347 && CONST_INT_P (XEXP (src, 1))
8348 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8349 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8350 src = XEXP (src, 0);
8352 return gen_rtx_SET (VOIDmode, assign, src);
8355 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8359 apply_distributive_law (rtx x)
8361 enum rtx_code code = GET_CODE (x);
8362 enum rtx_code inner_code;
8363 rtx lhs, rhs, other;
8366 /* Distributivity is not true for floating point as it can change the
8367 value. So we don't do it unless -funsafe-math-optimizations. */
8368 if (FLOAT_MODE_P (GET_MODE (x))
8369 && ! flag_unsafe_math_optimizations)
8372 /* The outer operation can only be one of the following: */
8373 if (code != IOR && code != AND && code != XOR
8374 && code != PLUS && code != MINUS)
8380 /* If either operand is a primitive we can't do anything, so get out
8382 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8385 lhs = expand_compound_operation (lhs);
8386 rhs = expand_compound_operation (rhs);
8387 inner_code = GET_CODE (lhs);
8388 if (inner_code != GET_CODE (rhs))
8391 /* See if the inner and outer operations distribute. */
8398 /* These all distribute except over PLUS. */
8399 if (code == PLUS || code == MINUS)
8404 if (code != PLUS && code != MINUS)
8409 /* This is also a multiply, so it distributes over everything. */
8413 /* Non-paradoxical SUBREGs distributes over all operations,
8414 provided the inner modes and byte offsets are the same, this
8415 is an extraction of a low-order part, we don't convert an fp
8416 operation to int or vice versa, this is not a vector mode,
8417 and we would not be converting a single-word operation into a
8418 multi-word operation. The latter test is not required, but
8419 it prevents generating unneeded multi-word operations. Some
8420 of the previous tests are redundant given the latter test,
8421 but are retained because they are required for correctness.
8423 We produce the result slightly differently in this case. */
8425 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8426 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8427 || ! subreg_lowpart_p (lhs)
8428 || (GET_MODE_CLASS (GET_MODE (lhs))
8429 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8430 || (GET_MODE_SIZE (GET_MODE (lhs))
8431 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8432 || VECTOR_MODE_P (GET_MODE (lhs))
8433 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8434 /* Result might need to be truncated. Don't change mode if
8435 explicit truncation is needed. */
8436 || !TRULY_NOOP_TRUNCATION
8437 (GET_MODE_BITSIZE (GET_MODE (x)),
8438 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8441 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8442 SUBREG_REG (lhs), SUBREG_REG (rhs));
8443 return gen_lowpart (GET_MODE (x), tem);
8449 /* Set LHS and RHS to the inner operands (A and B in the example
8450 above) and set OTHER to the common operand (C in the example).
8451 There is only one way to do this unless the inner operation is
8453 if (COMMUTATIVE_ARITH_P (lhs)
8454 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8455 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8456 else if (COMMUTATIVE_ARITH_P (lhs)
8457 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8458 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8459 else if (COMMUTATIVE_ARITH_P (lhs)
8460 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8461 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8462 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8463 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8467 /* Form the new inner operation, seeing if it simplifies first. */
8468 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8470 /* There is one exception to the general way of distributing:
8471 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8472 if (code == XOR && inner_code == IOR)
8475 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8478 /* We may be able to continuing distributing the result, so call
8479 ourselves recursively on the inner operation before forming the
8480 outer operation, which we return. */
8481 return simplify_gen_binary (inner_code, GET_MODE (x),
8482 apply_distributive_law (tem), other);
8485 /* See if X is of the form (* (+ A B) C), and if so convert to
8486 (+ (* A C) (* B C)) and try to simplify.
8488 Most of the time, this results in no change. However, if some of
8489 the operands are the same or inverses of each other, simplifications
8492 For example, (and (ior A B) (not B)) can occur as the result of
8493 expanding a bit field assignment. When we apply the distributive
8494 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8495 which then simplifies to (and (A (not B))).
8497 Note that no checks happen on the validity of applying the inverse
8498 distributive law. This is pointless since we can do it in the
8499 few places where this routine is called.
8501 N is the index of the term that is decomposed (the arithmetic operation,
8502 i.e. (+ A B) in the first example above). !N is the index of the term that
8503 is distributed, i.e. of C in the first example above. */
8505 distribute_and_simplify_rtx (rtx x, int n)
8507 enum machine_mode mode;
8508 enum rtx_code outer_code, inner_code;
8509 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8511 decomposed = XEXP (x, n);
8512 if (!ARITHMETIC_P (decomposed))
8515 mode = GET_MODE (x);
8516 outer_code = GET_CODE (x);
8517 distributed = XEXP (x, !n);
8519 inner_code = GET_CODE (decomposed);
8520 inner_op0 = XEXP (decomposed, 0);
8521 inner_op1 = XEXP (decomposed, 1);
8523 /* Special case (and (xor B C) (not A)), which is equivalent to
8524 (xor (ior A B) (ior A C)) */
8525 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8527 distributed = XEXP (distributed, 0);
8533 /* Distribute the second term. */
8534 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8535 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8539 /* Distribute the first term. */
8540 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8541 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8544 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8546 if (GET_CODE (tmp) != outer_code
8547 && rtx_cost (tmp, SET, optimize_this_for_speed_p)
8548 < rtx_cost (x, SET, optimize_this_for_speed_p))
8554 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8555 in MODE. Return an equivalent form, if different from (and VAROP
8556 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8559 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8560 unsigned HOST_WIDE_INT constop)
8562 unsigned HOST_WIDE_INT nonzero;
8563 unsigned HOST_WIDE_INT orig_constop;
8568 orig_constop = constop;
8569 if (GET_CODE (varop) == CLOBBER)
8572 /* Simplify VAROP knowing that we will be only looking at some of the
8575 Note by passing in CONSTOP, we guarantee that the bits not set in
8576 CONSTOP are not significant and will never be examined. We must
8577 ensure that is the case by explicitly masking out those bits
8578 before returning. */
8579 varop = force_to_mode (varop, mode, constop, 0);
8581 /* If VAROP is a CLOBBER, we will fail so return it. */
8582 if (GET_CODE (varop) == CLOBBER)
8585 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8586 to VAROP and return the new constant. */
8587 if (CONST_INT_P (varop))
8588 return gen_int_mode (INTVAL (varop) & constop, mode);
8590 /* See what bits may be nonzero in VAROP. Unlike the general case of
8591 a call to nonzero_bits, here we don't care about bits outside
8594 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8596 /* Turn off all bits in the constant that are known to already be zero.
8597 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8598 which is tested below. */
8602 /* If we don't have any bits left, return zero. */
8606 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8607 a power of two, we can replace this with an ASHIFT. */
8608 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8609 && (i = exact_log2 (constop)) >= 0)
8610 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8612 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8613 or XOR, then try to apply the distributive law. This may eliminate
8614 operations if either branch can be simplified because of the AND.
8615 It may also make some cases more complex, but those cases probably
8616 won't match a pattern either with or without this. */
8618 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8622 apply_distributive_law
8623 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8624 simplify_and_const_int (NULL_RTX,
8628 simplify_and_const_int (NULL_RTX,
8633 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8634 the AND and see if one of the operands simplifies to zero. If so, we
8635 may eliminate it. */
8637 if (GET_CODE (varop) == PLUS
8638 && exact_log2 (constop + 1) >= 0)
8642 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8643 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8644 if (o0 == const0_rtx)
8646 if (o1 == const0_rtx)
8650 /* Make a SUBREG if necessary. If we can't make it, fail. */
8651 varop = gen_lowpart (mode, varop);
8652 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8655 /* If we are only masking insignificant bits, return VAROP. */
8656 if (constop == nonzero)
8659 if (varop == orig_varop && constop == orig_constop)
8662 /* Otherwise, return an AND. */
8663 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8667 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8670 Return an equivalent form, if different from X. Otherwise, return X. If
8671 X is zero, we are to always construct the equivalent form. */
8674 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8675 unsigned HOST_WIDE_INT constop)
8677 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8682 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8683 gen_int_mode (constop, mode));
8684 if (GET_MODE (x) != mode)
8685 x = gen_lowpart (mode, x);
8689 /* Given a REG, X, compute which bits in X can be nonzero.
8690 We don't care about bits outside of those defined in MODE.
8692 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8693 a shift, AND, or zero_extract, we can do better. */
8696 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8697 const_rtx known_x ATTRIBUTE_UNUSED,
8698 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8699 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8700 unsigned HOST_WIDE_INT *nonzero)
8705 /* If X is a register whose nonzero bits value is current, use it.
8706 Otherwise, if X is a register whose value we can find, use that
8707 value. Otherwise, use the previously-computed global nonzero bits
8708 for this register. */
8710 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8711 if (rsp->last_set_value != 0
8712 && (rsp->last_set_mode == mode
8713 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8714 && GET_MODE_CLASS (mode) == MODE_INT))
8715 && ((rsp->last_set_label >= label_tick_ebb_start
8716 && rsp->last_set_label < label_tick)
8717 || (rsp->last_set_label == label_tick
8718 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8719 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8720 && REG_N_SETS (REGNO (x)) == 1
8722 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8724 *nonzero &= rsp->last_set_nonzero_bits;
8728 tem = get_last_value (x);
8732 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8733 /* If X is narrower than MODE and TEM is a non-negative
8734 constant that would appear negative in the mode of X,
8735 sign-extend it for use in reg_nonzero_bits because some
8736 machines (maybe most) will actually do the sign-extension
8737 and this is the conservative approach.
8739 ??? For 2.5, try to tighten up the MD files in this regard
8740 instead of this kludge. */
8742 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8743 && CONST_INT_P (tem)
8745 && 0 != (INTVAL (tem)
8746 & ((HOST_WIDE_INT) 1
8747 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8748 tem = GEN_INT (INTVAL (tem)
8749 | ((HOST_WIDE_INT) (-1)
8750 << GET_MODE_BITSIZE (GET_MODE (x))));
8754 else if (nonzero_sign_valid && rsp->nonzero_bits)
8756 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8758 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8759 /* We don't know anything about the upper bits. */
8760 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8767 /* Return the number of bits at the high-order end of X that are known to
8768 be equal to the sign bit. X will be used in mode MODE; if MODE is
8769 VOIDmode, X will be used in its own mode. The returned value will always
8770 be between 1 and the number of bits in MODE. */
8773 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8774 const_rtx known_x ATTRIBUTE_UNUSED,
8775 enum machine_mode known_mode
8777 unsigned int known_ret ATTRIBUTE_UNUSED,
8778 unsigned int *result)
8783 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8784 if (rsp->last_set_value != 0
8785 && rsp->last_set_mode == mode
8786 && ((rsp->last_set_label >= label_tick_ebb_start
8787 && rsp->last_set_label < label_tick)
8788 || (rsp->last_set_label == label_tick
8789 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8790 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8791 && REG_N_SETS (REGNO (x)) == 1
8793 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8795 *result = rsp->last_set_sign_bit_copies;
8799 tem = get_last_value (x);
8803 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8804 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8805 *result = rsp->sign_bit_copies;
8810 /* Return the number of "extended" bits there are in X, when interpreted
8811 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8812 unsigned quantities, this is the number of high-order zero bits.
8813 For signed quantities, this is the number of copies of the sign bit
8814 minus 1. In both case, this function returns the number of "spare"
8815 bits. For example, if two quantities for which this function returns
8816 at least 1 are added, the addition is known not to overflow.
8818 This function will always return 0 unless called during combine, which
8819 implies that it must be called from a define_split. */
8822 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8824 if (nonzero_sign_valid == 0)
8828 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8829 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8830 - floor_log2 (nonzero_bits (x, mode)))
8832 : num_sign_bit_copies (x, mode) - 1);
8835 /* This function is called from `simplify_shift_const' to merge two
8836 outer operations. Specifically, we have already found that we need
8837 to perform operation *POP0 with constant *PCONST0 at the outermost
8838 position. We would now like to also perform OP1 with constant CONST1
8839 (with *POP0 being done last).
8841 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8842 the resulting operation. *PCOMP_P is set to 1 if we would need to
8843 complement the innermost operand, otherwise it is unchanged.
8845 MODE is the mode in which the operation will be done. No bits outside
8846 the width of this mode matter. It is assumed that the width of this mode
8847 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8849 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8850 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8851 result is simply *PCONST0.
8853 If the resulting operation cannot be expressed as one operation, we
8854 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8857 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8859 enum rtx_code op0 = *pop0;
8860 HOST_WIDE_INT const0 = *pconst0;
8862 const0 &= GET_MODE_MASK (mode);
8863 const1 &= GET_MODE_MASK (mode);
8865 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8869 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8872 if (op1 == UNKNOWN || op0 == SET)
8875 else if (op0 == UNKNOWN)
8876 op0 = op1, const0 = const1;
8878 else if (op0 == op1)
8902 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8903 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8906 /* If the two constants aren't the same, we can't do anything. The
8907 remaining six cases can all be done. */
8908 else if (const0 != const1)
8916 /* (a & b) | b == b */
8918 else /* op1 == XOR */
8919 /* (a ^ b) | b == a | b */
8925 /* (a & b) ^ b == (~a) & b */
8926 op0 = AND, *pcomp_p = 1;
8927 else /* op1 == IOR */
8928 /* (a | b) ^ b == a & ~b */
8929 op0 = AND, const0 = ~const0;
8934 /* (a | b) & b == b */
8936 else /* op1 == XOR */
8937 /* (a ^ b) & b) == (~a) & b */
8944 /* Check for NO-OP cases. */
8945 const0 &= GET_MODE_MASK (mode);
8947 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8949 else if (const0 == 0 && op0 == AND)
8951 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8957 /* ??? Slightly redundant with the above mask, but not entirely.
8958 Moving this above means we'd have to sign-extend the mode mask
8959 for the final test. */
8960 if (op0 != UNKNOWN && op0 != NEG)
8961 *pconst0 = trunc_int_for_mode (const0, mode);
8966 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8967 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8968 simplify it. Otherwise, return a simplified value.
8970 The shift is normally computed in the widest mode we find in VAROP, as
8971 long as it isn't a different number of words than RESULT_MODE. Exceptions
8972 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8975 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8976 rtx varop, int orig_count)
8978 enum rtx_code orig_code = code;
8979 rtx orig_varop = varop;
8981 enum machine_mode mode = result_mode;
8982 enum machine_mode shift_mode, tmode;
8983 unsigned int mode_words
8984 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8985 /* We form (outer_op (code varop count) (outer_const)). */
8986 enum rtx_code outer_op = UNKNOWN;
8987 HOST_WIDE_INT outer_const = 0;
8988 int complement_p = 0;
8991 /* Make sure and truncate the "natural" shift on the way in. We don't
8992 want to do this inside the loop as it makes it more difficult to
8994 if (SHIFT_COUNT_TRUNCATED)
8995 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8997 /* If we were given an invalid count, don't do anything except exactly
8998 what was requested. */
9000 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
9005 /* Unless one of the branches of the `if' in this loop does a `continue',
9006 we will `break' the loop after the `if'. */
9010 /* If we have an operand of (clobber (const_int 0)), fail. */
9011 if (GET_CODE (varop) == CLOBBER)
9014 /* Convert ROTATERT to ROTATE. */
9015 if (code == ROTATERT)
9017 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
9019 if (VECTOR_MODE_P (result_mode))
9020 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9022 count = bitsize - count;
9025 /* We need to determine what mode we will do the shift in. If the
9026 shift is a right shift or a ROTATE, we must always do it in the mode
9027 it was originally done in. Otherwise, we can do it in MODE, the
9028 widest mode encountered. */
9030 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9031 ? result_mode : mode);
9033 /* Handle cases where the count is greater than the size of the mode
9034 minus 1. For ASHIFT, use the size minus one as the count (this can
9035 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9036 take the count modulo the size. For other shifts, the result is
9039 Since these shifts are being produced by the compiler by combining
9040 multiple operations, each of which are defined, we know what the
9041 result is supposed to be. */
9043 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9045 if (code == ASHIFTRT)
9046 count = GET_MODE_BITSIZE (shift_mode) - 1;
9047 else if (code == ROTATE || code == ROTATERT)
9048 count %= GET_MODE_BITSIZE (shift_mode);
9051 /* We can't simply return zero because there may be an
9059 /* If we discovered we had to complement VAROP, leave. Making a NOT
9060 here would cause an infinite loop. */
9064 /* An arithmetic right shift of a quantity known to be -1 or 0
9066 if (code == ASHIFTRT
9067 && (num_sign_bit_copies (varop, shift_mode)
9068 == GET_MODE_BITSIZE (shift_mode)))
9074 /* If we are doing an arithmetic right shift and discarding all but
9075 the sign bit copies, this is equivalent to doing a shift by the
9076 bitsize minus one. Convert it into that shift because it will often
9077 allow other simplifications. */
9079 if (code == ASHIFTRT
9080 && (count + num_sign_bit_copies (varop, shift_mode)
9081 >= GET_MODE_BITSIZE (shift_mode)))
9082 count = GET_MODE_BITSIZE (shift_mode) - 1;
9084 /* We simplify the tests below and elsewhere by converting
9085 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9086 `make_compound_operation' will convert it to an ASHIFTRT for
9087 those machines (such as VAX) that don't have an LSHIFTRT. */
9088 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9090 && ((nonzero_bits (varop, shift_mode)
9091 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9095 if (((code == LSHIFTRT
9096 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9097 && !(nonzero_bits (varop, shift_mode) >> count))
9099 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9100 && !((nonzero_bits (varop, shift_mode) << count)
9101 & GET_MODE_MASK (shift_mode))))
9102 && !side_effects_p (varop))
9105 switch (GET_CODE (varop))
9111 new_rtx = expand_compound_operation (varop);
9112 if (new_rtx != varop)
9120 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9121 minus the width of a smaller mode, we can do this with a
9122 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9123 if ((code == ASHIFTRT || code == LSHIFTRT)
9124 && ! mode_dependent_address_p (XEXP (varop, 0))
9125 && ! MEM_VOLATILE_P (varop)
9126 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9127 MODE_INT, 1)) != BLKmode)
9129 new_rtx = adjust_address_nv (varop, tmode,
9130 BYTES_BIG_ENDIAN ? 0
9131 : count / BITS_PER_UNIT);
9133 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9134 : ZERO_EXTEND, mode, new_rtx);
9141 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9142 the same number of words as what we've seen so far. Then store
9143 the widest mode in MODE. */
9144 if (subreg_lowpart_p (varop)
9145 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9146 > GET_MODE_SIZE (GET_MODE (varop)))
9147 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9148 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9151 varop = SUBREG_REG (varop);
9152 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9153 mode = GET_MODE (varop);
9159 /* Some machines use MULT instead of ASHIFT because MULT
9160 is cheaper. But it is still better on those machines to
9161 merge two shifts into one. */
9162 if (CONST_INT_P (XEXP (varop, 1))
9163 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9166 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9168 GEN_INT (exact_log2 (
9169 INTVAL (XEXP (varop, 1)))));
9175 /* Similar, for when divides are cheaper. */
9176 if (CONST_INT_P (XEXP (varop, 1))
9177 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9180 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9182 GEN_INT (exact_log2 (
9183 INTVAL (XEXP (varop, 1)))));
9189 /* If we are extracting just the sign bit of an arithmetic
9190 right shift, that shift is not needed. However, the sign
9191 bit of a wider mode may be different from what would be
9192 interpreted as the sign bit in a narrower mode, so, if
9193 the result is narrower, don't discard the shift. */
9194 if (code == LSHIFTRT
9195 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9196 && (GET_MODE_BITSIZE (result_mode)
9197 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9199 varop = XEXP (varop, 0);
9203 /* ... fall through ... */
9208 /* Here we have two nested shifts. The result is usually the
9209 AND of a new shift with a mask. We compute the result below. */
9210 if (CONST_INT_P (XEXP (varop, 1))
9211 && INTVAL (XEXP (varop, 1)) >= 0
9212 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9213 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9214 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9215 && !VECTOR_MODE_P (result_mode))
9217 enum rtx_code first_code = GET_CODE (varop);
9218 unsigned int first_count = INTVAL (XEXP (varop, 1));
9219 unsigned HOST_WIDE_INT mask;
9222 /* We have one common special case. We can't do any merging if
9223 the inner code is an ASHIFTRT of a smaller mode. However, if
9224 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9225 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9226 we can convert it to
9227 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9228 This simplifies certain SIGN_EXTEND operations. */
9229 if (code == ASHIFT && first_code == ASHIFTRT
9230 && count == (GET_MODE_BITSIZE (result_mode)
9231 - GET_MODE_BITSIZE (GET_MODE (varop))))
9233 /* C3 has the low-order C1 bits zero. */
9235 mask = (GET_MODE_MASK (mode)
9236 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9238 varop = simplify_and_const_int (NULL_RTX, result_mode,
9239 XEXP (varop, 0), mask);
9240 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9242 count = first_count;
9247 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9248 than C1 high-order bits equal to the sign bit, we can convert
9249 this to either an ASHIFT or an ASHIFTRT depending on the
9252 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9254 if (code == ASHIFTRT && first_code == ASHIFT
9255 && GET_MODE (varop) == shift_mode
9256 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9259 varop = XEXP (varop, 0);
9260 count -= first_count;
9270 /* There are some cases we can't do. If CODE is ASHIFTRT,
9271 we can only do this if FIRST_CODE is also ASHIFTRT.
9273 We can't do the case when CODE is ROTATE and FIRST_CODE is
9276 If the mode of this shift is not the mode of the outer shift,
9277 we can't do this if either shift is a right shift or ROTATE.
9279 Finally, we can't do any of these if the mode is too wide
9280 unless the codes are the same.
9282 Handle the case where the shift codes are the same
9285 if (code == first_code)
9287 if (GET_MODE (varop) != result_mode
9288 && (code == ASHIFTRT || code == LSHIFTRT
9292 count += first_count;
9293 varop = XEXP (varop, 0);
9297 if (code == ASHIFTRT
9298 || (code == ROTATE && first_code == ASHIFTRT)
9299 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9300 || (GET_MODE (varop) != result_mode
9301 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9302 || first_code == ROTATE
9303 || code == ROTATE)))
9306 /* To compute the mask to apply after the shift, shift the
9307 nonzero bits of the inner shift the same way the
9308 outer shift will. */
9310 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9313 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9316 /* Give up if we can't compute an outer operation to use. */
9318 || !CONST_INT_P (mask_rtx)
9319 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9321 result_mode, &complement_p))
9324 /* If the shifts are in the same direction, we add the
9325 counts. Otherwise, we subtract them. */
9326 if ((code == ASHIFTRT || code == LSHIFTRT)
9327 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9328 count += first_count;
9330 count -= first_count;
9332 /* If COUNT is positive, the new shift is usually CODE,
9333 except for the two exceptions below, in which case it is
9334 FIRST_CODE. If the count is negative, FIRST_CODE should
9337 && ((first_code == ROTATE && code == ASHIFT)
9338 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9341 code = first_code, count = -count;
9343 varop = XEXP (varop, 0);
9347 /* If we have (A << B << C) for any shift, we can convert this to
9348 (A << C << B). This wins if A is a constant. Only try this if
9349 B is not a constant. */
9351 else if (GET_CODE (varop) == code
9352 && CONST_INT_P (XEXP (varop, 0))
9353 && !CONST_INT_P (XEXP (varop, 1)))
9355 rtx new_rtx = simplify_const_binary_operation (code, mode,
9358 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9365 if (VECTOR_MODE_P (mode))
9368 /* Make this fit the case below. */
9369 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9370 GEN_INT (GET_MODE_MASK (mode)));
9376 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9377 with C the size of VAROP - 1 and the shift is logical if
9378 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9379 we have an (le X 0) operation. If we have an arithmetic shift
9380 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9381 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9383 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9384 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9385 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9386 && (code == LSHIFTRT || code == ASHIFTRT)
9387 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9388 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9391 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9394 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9395 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9400 /* If we have (shift (logical)), move the logical to the outside
9401 to allow it to possibly combine with another logical and the
9402 shift to combine with another shift. This also canonicalizes to
9403 what a ZERO_EXTRACT looks like. Also, some machines have
9404 (and (shift)) insns. */
9406 if (CONST_INT_P (XEXP (varop, 1))
9407 /* We can't do this if we have (ashiftrt (xor)) and the
9408 constant has its sign bit set in shift_mode. */
9409 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9410 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9412 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9414 GEN_INT (count))) != 0
9415 && CONST_INT_P (new_rtx)
9416 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9417 INTVAL (new_rtx), result_mode, &complement_p))
9419 varop = XEXP (varop, 0);
9423 /* If we can't do that, try to simplify the shift in each arm of the
9424 logical expression, make a new logical expression, and apply
9425 the inverse distributive law. This also can't be done
9426 for some (ashiftrt (xor)). */
9427 if (CONST_INT_P (XEXP (varop, 1))
9428 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9429 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9432 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9433 XEXP (varop, 0), count);
9434 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9435 XEXP (varop, 1), count);
9437 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9439 varop = apply_distributive_law (varop);
9447 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9448 says that the sign bit can be tested, FOO has mode MODE, C is
9449 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9450 that may be nonzero. */
9451 if (code == LSHIFTRT
9452 && XEXP (varop, 1) == const0_rtx
9453 && GET_MODE (XEXP (varop, 0)) == result_mode
9454 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9455 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9456 && STORE_FLAG_VALUE == -1
9457 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9458 && merge_outer_ops (&outer_op, &outer_const, XOR,
9459 (HOST_WIDE_INT) 1, result_mode,
9462 varop = XEXP (varop, 0);
9469 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9470 than the number of bits in the mode is equivalent to A. */
9471 if (code == LSHIFTRT
9472 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9473 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9475 varop = XEXP (varop, 0);
9480 /* NEG commutes with ASHIFT since it is multiplication. Move the
9481 NEG outside to allow shifts to combine. */
9483 && merge_outer_ops (&outer_op, &outer_const, NEG,
9484 (HOST_WIDE_INT) 0, result_mode,
9487 varop = XEXP (varop, 0);
9493 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9494 is one less than the number of bits in the mode is
9495 equivalent to (xor A 1). */
9496 if (code == LSHIFTRT
9497 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9498 && XEXP (varop, 1) == constm1_rtx
9499 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9500 && merge_outer_ops (&outer_op, &outer_const, XOR,
9501 (HOST_WIDE_INT) 1, result_mode,
9505 varop = XEXP (varop, 0);
9509 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9510 that might be nonzero in BAR are those being shifted out and those
9511 bits are known zero in FOO, we can replace the PLUS with FOO.
9512 Similarly in the other operand order. This code occurs when
9513 we are computing the size of a variable-size array. */
9515 if ((code == ASHIFTRT || code == LSHIFTRT)
9516 && count < HOST_BITS_PER_WIDE_INT
9517 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9518 && (nonzero_bits (XEXP (varop, 1), result_mode)
9519 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9521 varop = XEXP (varop, 0);
9524 else if ((code == ASHIFTRT || code == LSHIFTRT)
9525 && count < HOST_BITS_PER_WIDE_INT
9526 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9527 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9529 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9530 & nonzero_bits (XEXP (varop, 1),
9533 varop = XEXP (varop, 1);
9537 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9539 && CONST_INT_P (XEXP (varop, 1))
9540 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9542 GEN_INT (count))) != 0
9543 && CONST_INT_P (new_rtx)
9544 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9545 INTVAL (new_rtx), result_mode, &complement_p))
9547 varop = XEXP (varop, 0);
9551 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9552 signbit', and attempt to change the PLUS to an XOR and move it to
9553 the outer operation as is done above in the AND/IOR/XOR case
9554 leg for shift(logical). See details in logical handling above
9555 for reasoning in doing so. */
9556 if (code == LSHIFTRT
9557 && CONST_INT_P (XEXP (varop, 1))
9558 && mode_signbit_p (result_mode, XEXP (varop, 1))
9559 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9561 GEN_INT (count))) != 0
9562 && CONST_INT_P (new_rtx)
9563 && merge_outer_ops (&outer_op, &outer_const, XOR,
9564 INTVAL (new_rtx), result_mode, &complement_p))
9566 varop = XEXP (varop, 0);
9573 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9574 with C the size of VAROP - 1 and the shift is logical if
9575 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9576 we have a (gt X 0) operation. If the shift is arithmetic with
9577 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9578 we have a (neg (gt X 0)) operation. */
9580 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9581 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9582 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9583 && (code == LSHIFTRT || code == ASHIFTRT)
9584 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9585 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9586 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9589 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9592 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9593 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9600 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9601 if the truncate does not affect the value. */
9602 if (code == LSHIFTRT
9603 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9604 && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
9605 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9606 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9607 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9609 rtx varop_inner = XEXP (varop, 0);
9612 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9613 XEXP (varop_inner, 0),
9615 (count + INTVAL (XEXP (varop_inner, 1))));
9616 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9629 /* We need to determine what mode to do the shift in. If the shift is
9630 a right shift or ROTATE, we must always do it in the mode it was
9631 originally done in. Otherwise, we can do it in MODE, the widest mode
9632 encountered. The code we care about is that of the shift that will
9633 actually be done, not the shift that was originally requested. */
9635 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9636 ? result_mode : mode);
9638 /* We have now finished analyzing the shift. The result should be
9639 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9640 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9641 to the result of the shift. OUTER_CONST is the relevant constant,
9642 but we must turn off all bits turned off in the shift. */
9644 if (outer_op == UNKNOWN
9645 && orig_code == code && orig_count == count
9646 && varop == orig_varop
9647 && shift_mode == GET_MODE (varop))
9650 /* Make a SUBREG if necessary. If we can't make it, fail. */
9651 varop = gen_lowpart (shift_mode, varop);
9652 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9655 /* If we have an outer operation and we just made a shift, it is
9656 possible that we could have simplified the shift were it not
9657 for the outer operation. So try to do the simplification
9660 if (outer_op != UNKNOWN)
9661 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9666 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9668 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9669 turn off all the bits that the shift would have turned off. */
9670 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9671 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9672 GET_MODE_MASK (result_mode) >> orig_count);
9674 /* Do the remainder of the processing in RESULT_MODE. */
9675 x = gen_lowpart_or_truncate (result_mode, x);
9677 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9680 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9682 if (outer_op != UNKNOWN)
9684 if (GET_RTX_CLASS (outer_op) != RTX_UNARY
9685 && GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9686 outer_const = trunc_int_for_mode (outer_const, result_mode);
9688 if (outer_op == AND)
9689 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9690 else if (outer_op == SET)
9692 /* This means that we have determined that the result is
9693 equivalent to a constant. This should be rare. */
9694 if (!side_effects_p (x))
9695 x = GEN_INT (outer_const);
9697 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9698 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9700 x = simplify_gen_binary (outer_op, result_mode, x,
9701 GEN_INT (outer_const));
9707 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9708 The result of the shift is RESULT_MODE. If we cannot simplify it,
9709 return X or, if it is NULL, synthesize the expression with
9710 simplify_gen_binary. Otherwise, return a simplified value.
9712 The shift is normally computed in the widest mode we find in VAROP, as
9713 long as it isn't a different number of words than RESULT_MODE. Exceptions
9714 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9717 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9718 rtx varop, int count)
9720 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9725 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9726 if (GET_MODE (x) != result_mode)
9727 x = gen_lowpart (result_mode, x);
9732 /* Like recog, but we receive the address of a pointer to a new pattern.
9733 We try to match the rtx that the pointer points to.
9734 If that fails, we may try to modify or replace the pattern,
9735 storing the replacement into the same pointer object.
9737 Modifications include deletion or addition of CLOBBERs.
9739 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9740 the CLOBBERs are placed.
9742 The value is the final insn code from the pattern ultimately matched,
9746 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9749 int insn_code_number;
9750 int num_clobbers_to_add = 0;
9753 rtx old_notes, old_pat;
9755 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9756 we use to indicate that something didn't match. If we find such a
9757 thing, force rejection. */
9758 if (GET_CODE (pat) == PARALLEL)
9759 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9760 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9761 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9764 old_pat = PATTERN (insn);
9765 old_notes = REG_NOTES (insn);
9766 PATTERN (insn) = pat;
9767 REG_NOTES (insn) = 0;
9769 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9770 if (dump_file && (dump_flags & TDF_DETAILS))
9772 if (insn_code_number < 0)
9773 fputs ("Failed to match this instruction:\n", dump_file);
9775 fputs ("Successfully matched this instruction:\n", dump_file);
9776 print_rtl_single (dump_file, pat);
9779 /* If it isn't, there is the possibility that we previously had an insn
9780 that clobbered some register as a side effect, but the combined
9781 insn doesn't need to do that. So try once more without the clobbers
9782 unless this represents an ASM insn. */
9784 if (insn_code_number < 0 && ! check_asm_operands (pat)
9785 && GET_CODE (pat) == PARALLEL)
9789 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9790 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9793 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9797 SUBST_INT (XVECLEN (pat, 0), pos);
9800 pat = XVECEXP (pat, 0, 0);
9802 PATTERN (insn) = pat;
9803 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9804 if (dump_file && (dump_flags & TDF_DETAILS))
9806 if (insn_code_number < 0)
9807 fputs ("Failed to match this instruction:\n", dump_file);
9809 fputs ("Successfully matched this instruction:\n", dump_file);
9810 print_rtl_single (dump_file, pat);
9813 PATTERN (insn) = old_pat;
9814 REG_NOTES (insn) = old_notes;
9816 /* Recognize all noop sets, these will be killed by followup pass. */
9817 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9818 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9820 /* If we had any clobbers to add, make a new pattern than contains
9821 them. Then check to make sure that all of them are dead. */
9822 if (num_clobbers_to_add)
9824 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9825 rtvec_alloc (GET_CODE (pat) == PARALLEL
9827 + num_clobbers_to_add)
9828 : num_clobbers_to_add + 1));
9830 if (GET_CODE (pat) == PARALLEL)
9831 for (i = 0; i < XVECLEN (pat, 0); i++)
9832 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9834 XVECEXP (newpat, 0, 0) = pat;
9836 add_clobbers (newpat, insn_code_number);
9838 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9839 i < XVECLEN (newpat, 0); i++)
9841 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9842 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9844 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9846 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9847 notes = alloc_reg_note (REG_UNUSED,
9848 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9857 return insn_code_number;
9860 /* Like gen_lowpart_general but for use by combine. In combine it
9861 is not possible to create any new pseudoregs. However, it is
9862 safe to create invalid memory addresses, because combine will
9863 try to recognize them and all they will do is make the combine
9866 If for some reason this cannot do its job, an rtx
9867 (clobber (const_int 0)) is returned.
9868 An insn containing that will not be recognized. */
9871 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9873 enum machine_mode imode = GET_MODE (x);
9874 unsigned int osize = GET_MODE_SIZE (omode);
9875 unsigned int isize = GET_MODE_SIZE (imode);
9881 /* Return identity if this is a CONST or symbolic reference. */
9883 && (GET_CODE (x) == CONST
9884 || GET_CODE (x) == SYMBOL_REF
9885 || GET_CODE (x) == LABEL_REF))
9888 /* We can only support MODE being wider than a word if X is a
9889 constant integer or has a mode the same size. */
9890 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9891 && ! ((imode == VOIDmode
9893 || GET_CODE (x) == CONST_DOUBLE))
9897 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9898 won't know what to do. So we will strip off the SUBREG here and
9899 process normally. */
9900 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9904 /* For use in case we fall down into the address adjustments
9905 further below, we need to adjust the known mode and size of
9906 x; imode and isize, since we just adjusted x. */
9907 imode = GET_MODE (x);
9912 isize = GET_MODE_SIZE (imode);
9915 result = gen_lowpart_common (omode, x);
9924 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9926 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9929 /* If we want to refer to something bigger than the original memref,
9930 generate a paradoxical subreg instead. That will force a reload
9931 of the original memref X. */
9933 return gen_rtx_SUBREG (omode, x, 0);
9935 if (WORDS_BIG_ENDIAN)
9936 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9938 /* Adjust the address so that the address-after-the-data is
9940 if (BYTES_BIG_ENDIAN)
9941 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9943 return adjust_address_nv (x, omode, offset);
9946 /* If X is a comparison operator, rewrite it in a new mode. This
9947 probably won't match, but may allow further simplifications. */
9948 else if (COMPARISON_P (x))
9949 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9951 /* If we couldn't simplify X any other way, just enclose it in a
9952 SUBREG. Normally, this SUBREG won't match, but some patterns may
9953 include an explicit SUBREG or we may simplify it further in combine. */
9959 offset = subreg_lowpart_offset (omode, imode);
9960 if (imode == VOIDmode)
9962 imode = int_mode_for_mode (omode);
9963 x = gen_lowpart_common (imode, x);
9967 res = simplify_gen_subreg (omode, x, imode, offset);
9973 return gen_rtx_CLOBBER (omode, const0_rtx);
9976 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9977 comparison code that will be tested.
9979 The result is a possibly different comparison code to use. *POP0 and
9980 *POP1 may be updated.
9982 It is possible that we might detect that a comparison is either always
9983 true or always false. However, we do not perform general constant
9984 folding in combine, so this knowledge isn't useful. Such tautologies
9985 should have been detected earlier. Hence we ignore all such cases. */
9987 static enum rtx_code
9988 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9994 enum machine_mode mode, tmode;
9996 /* Try a few ways of applying the same transformation to both operands. */
9999 #ifndef WORD_REGISTER_OPERATIONS
10000 /* The test below this one won't handle SIGN_EXTENDs on these machines,
10001 so check specially. */
10002 if (code != GTU && code != GEU && code != LTU && code != LEU
10003 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
10004 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10005 && GET_CODE (XEXP (op1, 0)) == ASHIFT
10006 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
10007 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
10008 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
10009 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
10010 && CONST_INT_P (XEXP (op0, 1))
10011 && XEXP (op0, 1) == XEXP (op1, 1)
10012 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10013 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
10014 && (INTVAL (XEXP (op0, 1))
10015 == (GET_MODE_BITSIZE (GET_MODE (op0))
10016 - (GET_MODE_BITSIZE
10017 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
10019 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
10020 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
10024 /* If both operands are the same constant shift, see if we can ignore the
10025 shift. We can if the shift is a rotate or if the bits shifted out of
10026 this shift are known to be zero for both inputs and if the type of
10027 comparison is compatible with the shift. */
10028 if (GET_CODE (op0) == GET_CODE (op1)
10029 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10030 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10031 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10032 && (code != GT && code != LT && code != GE && code != LE))
10033 || (GET_CODE (op0) == ASHIFTRT
10034 && (code != GTU && code != LTU
10035 && code != GEU && code != LEU)))
10036 && CONST_INT_P (XEXP (op0, 1))
10037 && INTVAL (XEXP (op0, 1)) >= 0
10038 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10039 && XEXP (op0, 1) == XEXP (op1, 1))
10041 enum machine_mode mode = GET_MODE (op0);
10042 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10043 int shift_count = INTVAL (XEXP (op0, 1));
10045 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10046 mask &= (mask >> shift_count) << shift_count;
10047 else if (GET_CODE (op0) == ASHIFT)
10048 mask = (mask & (mask << shift_count)) >> shift_count;
10050 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10051 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10052 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10057 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10058 SUBREGs are of the same mode, and, in both cases, the AND would
10059 be redundant if the comparison was done in the narrower mode,
10060 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10061 and the operand's possibly nonzero bits are 0xffffff01; in that case
10062 if we only care about QImode, we don't need the AND). This case
10063 occurs if the output mode of an scc insn is not SImode and
10064 STORE_FLAG_VALUE == 1 (e.g., the 386).
10066 Similarly, check for a case where the AND's are ZERO_EXTEND
10067 operations from some narrower mode even though a SUBREG is not
10070 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10071 && CONST_INT_P (XEXP (op0, 1))
10072 && CONST_INT_P (XEXP (op1, 1)))
10074 rtx inner_op0 = XEXP (op0, 0);
10075 rtx inner_op1 = XEXP (op1, 0);
10076 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10077 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10080 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10081 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10082 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10083 && (GET_MODE (SUBREG_REG (inner_op0))
10084 == GET_MODE (SUBREG_REG (inner_op1)))
10085 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10086 <= HOST_BITS_PER_WIDE_INT)
10087 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10088 GET_MODE (SUBREG_REG (inner_op0)))))
10089 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10090 GET_MODE (SUBREG_REG (inner_op1))))))
10092 op0 = SUBREG_REG (inner_op0);
10093 op1 = SUBREG_REG (inner_op1);
10095 /* The resulting comparison is always unsigned since we masked
10096 off the original sign bit. */
10097 code = unsigned_condition (code);
10103 for (tmode = GET_CLASS_NARROWEST_MODE
10104 (GET_MODE_CLASS (GET_MODE (op0)));
10105 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10106 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10108 op0 = gen_lowpart (tmode, inner_op0);
10109 op1 = gen_lowpart (tmode, inner_op1);
10110 code = unsigned_condition (code);
10119 /* If both operands are NOT, we can strip off the outer operation
10120 and adjust the comparison code for swapped operands; similarly for
10121 NEG, except that this must be an equality comparison. */
10122 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10123 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10124 && (code == EQ || code == NE)))
10125 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10131 /* If the first operand is a constant, swap the operands and adjust the
10132 comparison code appropriately, but don't do this if the second operand
10133 is already a constant integer. */
10134 if (swap_commutative_operands_p (op0, op1))
10136 tem = op0, op0 = op1, op1 = tem;
10137 code = swap_condition (code);
10140 /* We now enter a loop during which we will try to simplify the comparison.
10141 For the most part, we only are concerned with comparisons with zero,
10142 but some things may really be comparisons with zero but not start
10143 out looking that way. */
10145 while (CONST_INT_P (op1))
10147 enum machine_mode mode = GET_MODE (op0);
10148 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10149 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10150 int equality_comparison_p;
10151 int sign_bit_comparison_p;
10152 int unsigned_comparison_p;
10153 HOST_WIDE_INT const_op;
10155 /* We only want to handle integral modes. This catches VOIDmode,
10156 CCmode, and the floating-point modes. An exception is that we
10157 can handle VOIDmode if OP0 is a COMPARE or a comparison
10160 if (GET_MODE_CLASS (mode) != MODE_INT
10161 && ! (mode == VOIDmode
10162 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10165 /* Get the constant we are comparing against and turn off all bits
10166 not on in our mode. */
10167 const_op = INTVAL (op1);
10168 if (mode != VOIDmode)
10169 const_op = trunc_int_for_mode (const_op, mode);
10170 op1 = GEN_INT (const_op);
10172 /* If we are comparing against a constant power of two and the value
10173 being compared can only have that single bit nonzero (e.g., it was
10174 `and'ed with that bit), we can replace this with a comparison
10177 && (code == EQ || code == NE || code == GE || code == GEU
10178 || code == LT || code == LTU)
10179 && mode_width <= HOST_BITS_PER_WIDE_INT
10180 && exact_log2 (const_op) >= 0
10181 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10183 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10184 op1 = const0_rtx, const_op = 0;
10187 /* Similarly, if we are comparing a value known to be either -1 or
10188 0 with -1, change it to the opposite comparison against zero. */
10191 && (code == EQ || code == NE || code == GT || code == LE
10192 || code == GEU || code == LTU)
10193 && num_sign_bit_copies (op0, mode) == mode_width)
10195 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10196 op1 = const0_rtx, const_op = 0;
10199 /* Do some canonicalizations based on the comparison code. We prefer
10200 comparisons against zero and then prefer equality comparisons.
10201 If we can reduce the size of a constant, we will do that too. */
10206 /* < C is equivalent to <= (C - 1) */
10210 op1 = GEN_INT (const_op);
10212 /* ... fall through to LE case below. */
10218 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10222 op1 = GEN_INT (const_op);
10226 /* If we are doing a <= 0 comparison on a value known to have
10227 a zero sign bit, we can replace this with == 0. */
10228 else if (const_op == 0
10229 && mode_width <= HOST_BITS_PER_WIDE_INT
10230 && (nonzero_bits (op0, mode)
10231 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10236 /* >= C is equivalent to > (C - 1). */
10240 op1 = GEN_INT (const_op);
10242 /* ... fall through to GT below. */
10248 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10252 op1 = GEN_INT (const_op);
10256 /* If we are doing a > 0 comparison on a value known to have
10257 a zero sign bit, we can replace this with != 0. */
10258 else if (const_op == 0
10259 && mode_width <= HOST_BITS_PER_WIDE_INT
10260 && (nonzero_bits (op0, mode)
10261 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10266 /* < C is equivalent to <= (C - 1). */
10270 op1 = GEN_INT (const_op);
10272 /* ... fall through ... */
10275 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10276 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10277 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10279 const_op = 0, op1 = const0_rtx;
10287 /* unsigned <= 0 is equivalent to == 0 */
10291 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10292 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10293 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10295 const_op = 0, op1 = const0_rtx;
10301 /* >= C is equivalent to > (C - 1). */
10305 op1 = GEN_INT (const_op);
10307 /* ... fall through ... */
10310 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10311 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10312 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10314 const_op = 0, op1 = const0_rtx;
10322 /* unsigned > 0 is equivalent to != 0 */
10326 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10327 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10328 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10330 const_op = 0, op1 = const0_rtx;
10339 /* Compute some predicates to simplify code below. */
10341 equality_comparison_p = (code == EQ || code == NE);
10342 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10343 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10346 /* If this is a sign bit comparison and we can do arithmetic in
10347 MODE, say that we will only be needing the sign bit of OP0. */
10348 if (sign_bit_comparison_p
10349 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10350 op0 = force_to_mode (op0, mode,
10352 << (GET_MODE_BITSIZE (mode) - 1)),
10355 /* Now try cases based on the opcode of OP0. If none of the cases
10356 does a "continue", we exit this loop immediately after the
10359 switch (GET_CODE (op0))
10362 /* If we are extracting a single bit from a variable position in
10363 a constant that has only a single bit set and are comparing it
10364 with zero, we can convert this into an equality comparison
10365 between the position and the location of the single bit. */
10366 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10367 have already reduced the shift count modulo the word size. */
10368 if (!SHIFT_COUNT_TRUNCATED
10369 && CONST_INT_P (XEXP (op0, 0))
10370 && XEXP (op0, 1) == const1_rtx
10371 && equality_comparison_p && const_op == 0
10372 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10374 if (BITS_BIG_ENDIAN)
10376 enum machine_mode new_mode
10377 = mode_for_extraction (EP_extzv, 1);
10378 if (new_mode == MAX_MACHINE_MODE)
10379 i = BITS_PER_WORD - 1 - i;
10383 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10387 op0 = XEXP (op0, 2);
10391 /* Result is nonzero iff shift count is equal to I. */
10392 code = reverse_condition (code);
10396 /* ... fall through ... */
10399 tem = expand_compound_operation (op0);
10408 /* If testing for equality, we can take the NOT of the constant. */
10409 if (equality_comparison_p
10410 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10412 op0 = XEXP (op0, 0);
10417 /* If just looking at the sign bit, reverse the sense of the
10419 if (sign_bit_comparison_p)
10421 op0 = XEXP (op0, 0);
10422 code = (code == GE ? LT : GE);
10428 /* If testing for equality, we can take the NEG of the constant. */
10429 if (equality_comparison_p
10430 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10432 op0 = XEXP (op0, 0);
10437 /* The remaining cases only apply to comparisons with zero. */
10441 /* When X is ABS or is known positive,
10442 (neg X) is < 0 if and only if X != 0. */
10444 if (sign_bit_comparison_p
10445 && (GET_CODE (XEXP (op0, 0)) == ABS
10446 || (mode_width <= HOST_BITS_PER_WIDE_INT
10447 && (nonzero_bits (XEXP (op0, 0), mode)
10448 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10450 op0 = XEXP (op0, 0);
10451 code = (code == LT ? NE : EQ);
10455 /* If we have NEG of something whose two high-order bits are the
10456 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10457 if (num_sign_bit_copies (op0, mode) >= 2)
10459 op0 = XEXP (op0, 0);
10460 code = swap_condition (code);
10466 /* If we are testing equality and our count is a constant, we
10467 can perform the inverse operation on our RHS. */
10468 if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
10469 && (tem = simplify_binary_operation (ROTATERT, mode,
10470 op1, XEXP (op0, 1))) != 0)
10472 op0 = XEXP (op0, 0);
10477 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10478 a particular bit. Convert it to an AND of a constant of that
10479 bit. This will be converted into a ZERO_EXTRACT. */
10480 if (const_op == 0 && sign_bit_comparison_p
10481 && CONST_INT_P (XEXP (op0, 1))
10482 && mode_width <= HOST_BITS_PER_WIDE_INT)
10484 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10487 - INTVAL (XEXP (op0, 1)))));
10488 code = (code == LT ? NE : EQ);
10492 /* Fall through. */
10495 /* ABS is ignorable inside an equality comparison with zero. */
10496 if (const_op == 0 && equality_comparison_p)
10498 op0 = XEXP (op0, 0);
10504 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10505 (compare FOO CONST) if CONST fits in FOO's mode and we
10506 are either testing inequality or have an unsigned
10507 comparison with ZERO_EXTEND or a signed comparison with
10508 SIGN_EXTEND. But don't do it if we don't have a compare
10509 insn of the given mode, since we'd have to revert it
10510 later on, and then we wouldn't know whether to sign- or
10512 mode = GET_MODE (XEXP (op0, 0));
10513 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10514 && ! unsigned_comparison_p
10515 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10516 && ((unsigned HOST_WIDE_INT) const_op
10517 < (((unsigned HOST_WIDE_INT) 1
10518 << (GET_MODE_BITSIZE (mode) - 1))))
10519 && have_insn_for (COMPARE, mode))
10521 op0 = XEXP (op0, 0);
10527 /* Check for the case where we are comparing A - C1 with C2, that is
10529 (subreg:MODE (plus (A) (-C1))) op (C2)
10531 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10532 comparison in the wider mode. One of the following two conditions
10533 must be true in order for this to be valid:
10535 1. The mode extension results in the same bit pattern being added
10536 on both sides and the comparison is equality or unsigned. As
10537 C2 has been truncated to fit in MODE, the pattern can only be
10540 2. The mode extension results in the sign bit being copied on
10543 The difficulty here is that we have predicates for A but not for
10544 (A - C1) so we need to check that C1 is within proper bounds so
10545 as to perturbate A as little as possible. */
10547 if (mode_width <= HOST_BITS_PER_WIDE_INT
10548 && subreg_lowpart_p (op0)
10549 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10550 && GET_CODE (SUBREG_REG (op0)) == PLUS
10551 && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
10553 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10554 rtx a = XEXP (SUBREG_REG (op0), 0);
10555 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10558 && (unsigned HOST_WIDE_INT) c1
10559 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10560 && (equality_comparison_p || unsigned_comparison_p)
10561 /* (A - C1) zero-extends if it is positive and sign-extends
10562 if it is negative, C2 both zero- and sign-extends. */
10563 && ((0 == (nonzero_bits (a, inner_mode)
10564 & ~GET_MODE_MASK (mode))
10566 /* (A - C1) sign-extends if it is positive and 1-extends
10567 if it is negative, C2 both sign- and 1-extends. */
10568 || (num_sign_bit_copies (a, inner_mode)
10569 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10572 || ((unsigned HOST_WIDE_INT) c1
10573 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10574 /* (A - C1) always sign-extends, like C2. */
10575 && num_sign_bit_copies (a, inner_mode)
10576 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10577 - (mode_width - 1))))
10579 op0 = SUBREG_REG (op0);
10584 /* If the inner mode is narrower and we are extracting the low part,
10585 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10586 if (subreg_lowpart_p (op0)
10587 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10588 /* Fall through */ ;
10592 /* ... fall through ... */
10595 mode = GET_MODE (XEXP (op0, 0));
10596 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10597 && (unsigned_comparison_p || equality_comparison_p)
10598 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10599 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10600 && have_insn_for (COMPARE, mode))
10602 op0 = XEXP (op0, 0);
10608 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10609 this for equality comparisons due to pathological cases involving
10611 if (equality_comparison_p
10612 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10613 op1, XEXP (op0, 1))))
10615 op0 = XEXP (op0, 0);
10620 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10621 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10622 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10624 op0 = XEXP (XEXP (op0, 0), 0);
10625 code = (code == LT ? EQ : NE);
10631 /* We used to optimize signed comparisons against zero, but that
10632 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10633 arrive here as equality comparisons, or (GEU, LTU) are
10634 optimized away. No need to special-case them. */
10636 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10637 (eq B (minus A C)), whichever simplifies. We can only do
10638 this for equality comparisons due to pathological cases involving
10640 if (equality_comparison_p
10641 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10642 XEXP (op0, 1), op1)))
10644 op0 = XEXP (op0, 0);
10649 if (equality_comparison_p
10650 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10651 XEXP (op0, 0), op1)))
10653 op0 = XEXP (op0, 1);
10658 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10659 of bits in X minus 1, is one iff X > 0. */
10660 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10661 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10662 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10664 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10666 op0 = XEXP (op0, 1);
10667 code = (code == GE ? LE : GT);
10673 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10674 if C is zero or B is a constant. */
10675 if (equality_comparison_p
10676 && 0 != (tem = simplify_binary_operation (XOR, mode,
10677 XEXP (op0, 1), op1)))
10679 op0 = XEXP (op0, 0);
10686 case UNEQ: case LTGT:
10687 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10688 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10689 case UNORDERED: case ORDERED:
10690 /* We can't do anything if OP0 is a condition code value, rather
10691 than an actual data value. */
10693 || CC0_P (XEXP (op0, 0))
10694 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10697 /* Get the two operands being compared. */
10698 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10699 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10701 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10703 /* Check for the cases where we simply want the result of the
10704 earlier test or the opposite of that result. */
10705 if (code == NE || code == EQ
10706 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10707 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10708 && (STORE_FLAG_VALUE
10709 & (((HOST_WIDE_INT) 1
10710 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10711 && (code == LT || code == GE)))
10713 enum rtx_code new_code;
10714 if (code == LT || code == NE)
10715 new_code = GET_CODE (op0);
10717 new_code = reversed_comparison_code (op0, NULL);
10719 if (new_code != UNKNOWN)
10730 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10732 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10733 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10734 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10736 op0 = XEXP (op0, 1);
10737 code = (code == GE ? GT : LE);
10743 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10744 will be converted to a ZERO_EXTRACT later. */
10745 if (const_op == 0 && equality_comparison_p
10746 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10747 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10749 op0 = simplify_and_const_int
10750 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10752 XEXP (XEXP (op0, 0), 1)),
10753 (HOST_WIDE_INT) 1);
10757 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10758 zero and X is a comparison and C1 and C2 describe only bits set
10759 in STORE_FLAG_VALUE, we can compare with X. */
10760 if (const_op == 0 && equality_comparison_p
10761 && mode_width <= HOST_BITS_PER_WIDE_INT
10762 && CONST_INT_P (XEXP (op0, 1))
10763 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10764 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10765 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10766 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10768 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10769 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10770 if ((~STORE_FLAG_VALUE & mask) == 0
10771 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10772 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10773 && COMPARISON_P (tem))))
10775 op0 = XEXP (XEXP (op0, 0), 0);
10780 /* If we are doing an equality comparison of an AND of a bit equal
10781 to the sign bit, replace this with a LT or GE comparison of
10782 the underlying value. */
10783 if (equality_comparison_p
10785 && CONST_INT_P (XEXP (op0, 1))
10786 && mode_width <= HOST_BITS_PER_WIDE_INT
10787 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10788 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10790 op0 = XEXP (op0, 0);
10791 code = (code == EQ ? GE : LT);
10795 /* If this AND operation is really a ZERO_EXTEND from a narrower
10796 mode, the constant fits within that mode, and this is either an
10797 equality or unsigned comparison, try to do this comparison in
10802 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10803 -> (ne:DI (reg:SI 4) (const_int 0))
10805 unless TRULY_NOOP_TRUNCATION allows it or the register is
10806 known to hold a value of the required mode the
10807 transformation is invalid. */
10808 if ((equality_comparison_p || unsigned_comparison_p)
10809 && CONST_INT_P (XEXP (op0, 1))
10810 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10811 & GET_MODE_MASK (mode))
10813 && const_op >> i == 0
10814 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10815 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10816 GET_MODE_BITSIZE (GET_MODE (op0)))
10817 || (REG_P (XEXP (op0, 0))
10818 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10820 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10824 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10825 fits in both M1 and M2 and the SUBREG is either paradoxical
10826 or represents the low part, permute the SUBREG and the AND
10828 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10830 unsigned HOST_WIDE_INT c1;
10831 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10832 /* Require an integral mode, to avoid creating something like
10834 if (SCALAR_INT_MODE_P (tmode)
10835 /* It is unsafe to commute the AND into the SUBREG if the
10836 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10837 not defined. As originally written the upper bits
10838 have a defined value due to the AND operation.
10839 However, if we commute the AND inside the SUBREG then
10840 they no longer have defined values and the meaning of
10841 the code has been changed. */
10843 #ifdef WORD_REGISTER_OPERATIONS
10844 || (mode_width > GET_MODE_BITSIZE (tmode)
10845 && mode_width <= BITS_PER_WORD)
10847 || (mode_width <= GET_MODE_BITSIZE (tmode)
10848 && subreg_lowpart_p (XEXP (op0, 0))))
10849 && CONST_INT_P (XEXP (op0, 1))
10850 && mode_width <= HOST_BITS_PER_WIDE_INT
10851 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10852 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10853 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10855 && c1 != GET_MODE_MASK (tmode))
10857 op0 = simplify_gen_binary (AND, tmode,
10858 SUBREG_REG (XEXP (op0, 0)),
10859 gen_int_mode (c1, tmode));
10860 op0 = gen_lowpart (mode, op0);
10865 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10866 if (const_op == 0 && equality_comparison_p
10867 && XEXP (op0, 1) == const1_rtx
10868 && GET_CODE (XEXP (op0, 0)) == NOT)
10870 op0 = simplify_and_const_int
10871 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10872 code = (code == NE ? EQ : NE);
10876 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10877 (eq (and (lshiftrt X) 1) 0).
10878 Also handle the case where (not X) is expressed using xor. */
10879 if (const_op == 0 && equality_comparison_p
10880 && XEXP (op0, 1) == const1_rtx
10881 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10883 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10884 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10886 if (GET_CODE (shift_op) == NOT
10887 || (GET_CODE (shift_op) == XOR
10888 && CONST_INT_P (XEXP (shift_op, 1))
10889 && CONST_INT_P (shift_count)
10890 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10891 && (INTVAL (XEXP (shift_op, 1))
10892 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10894 op0 = simplify_and_const_int
10896 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10897 (HOST_WIDE_INT) 1);
10898 code = (code == NE ? EQ : NE);
10905 /* If we have (compare (ashift FOO N) (const_int C)) and
10906 the high order N bits of FOO (N+1 if an inequality comparison)
10907 are known to be zero, we can do this by comparing FOO with C
10908 shifted right N bits so long as the low-order N bits of C are
10910 if (CONST_INT_P (XEXP (op0, 1))
10911 && INTVAL (XEXP (op0, 1)) >= 0
10912 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10913 < HOST_BITS_PER_WIDE_INT)
10915 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10916 && mode_width <= HOST_BITS_PER_WIDE_INT
10917 && (nonzero_bits (XEXP (op0, 0), mode)
10918 & ~(mask >> (INTVAL (XEXP (op0, 1))
10919 + ! equality_comparison_p))) == 0)
10921 /* We must perform a logical shift, not an arithmetic one,
10922 as we want the top N bits of C to be zero. */
10923 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10925 temp >>= INTVAL (XEXP (op0, 1));
10926 op1 = gen_int_mode (temp, mode);
10927 op0 = XEXP (op0, 0);
10931 /* If we are doing a sign bit comparison, it means we are testing
10932 a particular bit. Convert it to the appropriate AND. */
10933 if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
10934 && mode_width <= HOST_BITS_PER_WIDE_INT)
10936 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10939 - INTVAL (XEXP (op0, 1)))));
10940 code = (code == LT ? NE : EQ);
10944 /* If this an equality comparison with zero and we are shifting
10945 the low bit to the sign bit, we can convert this to an AND of the
10947 if (const_op == 0 && equality_comparison_p
10948 && CONST_INT_P (XEXP (op0, 1))
10949 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10952 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10953 (HOST_WIDE_INT) 1);
10959 /* If this is an equality comparison with zero, we can do this
10960 as a logical shift, which might be much simpler. */
10961 if (equality_comparison_p && const_op == 0
10962 && CONST_INT_P (XEXP (op0, 1)))
10964 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10966 INTVAL (XEXP (op0, 1)));
10970 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10971 do the comparison in a narrower mode. */
10972 if (! unsigned_comparison_p
10973 && CONST_INT_P (XEXP (op0, 1))
10974 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10975 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10976 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10977 MODE_INT, 1)) != BLKmode
10978 && (((unsigned HOST_WIDE_INT) const_op
10979 + (GET_MODE_MASK (tmode) >> 1) + 1)
10980 <= GET_MODE_MASK (tmode)))
10982 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10986 /* Likewise if OP0 is a PLUS of a sign extension with a
10987 constant, which is usually represented with the PLUS
10988 between the shifts. */
10989 if (! unsigned_comparison_p
10990 && CONST_INT_P (XEXP (op0, 1))
10991 && GET_CODE (XEXP (op0, 0)) == PLUS
10992 && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
10993 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10994 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10995 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10996 MODE_INT, 1)) != BLKmode
10997 && (((unsigned HOST_WIDE_INT) const_op
10998 + (GET_MODE_MASK (tmode) >> 1) + 1)
10999 <= GET_MODE_MASK (tmode)))
11001 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11002 rtx add_const = XEXP (XEXP (op0, 0), 1);
11003 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11004 add_const, XEXP (op0, 1));
11006 op0 = simplify_gen_binary (PLUS, tmode,
11007 gen_lowpart (tmode, inner),
11012 /* ... fall through ... */
11014 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11015 the low order N bits of FOO are known to be zero, we can do this
11016 by comparing FOO with C shifted left N bits so long as no
11017 overflow occurs. */
11018 if (CONST_INT_P (XEXP (op0, 1))
11019 && INTVAL (XEXP (op0, 1)) >= 0
11020 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11021 && mode_width <= HOST_BITS_PER_WIDE_INT
11022 && (nonzero_bits (XEXP (op0, 0), mode)
11023 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
11024 && (((unsigned HOST_WIDE_INT) const_op
11025 + (GET_CODE (op0) != LSHIFTRT
11026 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11029 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11031 /* If the shift was logical, then we must make the condition
11033 if (GET_CODE (op0) == LSHIFTRT)
11034 code = unsigned_condition (code);
11036 const_op <<= INTVAL (XEXP (op0, 1));
11037 op1 = GEN_INT (const_op);
11038 op0 = XEXP (op0, 0);
11042 /* If we are using this shift to extract just the sign bit, we
11043 can replace this with an LT or GE comparison. */
11045 && (equality_comparison_p || sign_bit_comparison_p)
11046 && CONST_INT_P (XEXP (op0, 1))
11047 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11050 op0 = XEXP (op0, 0);
11051 code = (code == NE || code == GT ? LT : GE);
11063 /* Now make any compound operations involved in this comparison. Then,
11064 check for an outmost SUBREG on OP0 that is not doing anything or is
11065 paradoxical. The latter transformation must only be performed when
11066 it is known that the "extra" bits will be the same in op0 and op1 or
11067 that they don't matter. There are three cases to consider:
11069 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11070 care bits and we can assume they have any convenient value. So
11071 making the transformation is safe.
11073 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11074 In this case the upper bits of op0 are undefined. We should not make
11075 the simplification in that case as we do not know the contents of
11078 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11079 UNKNOWN. In that case we know those bits are zeros or ones. We must
11080 also be sure that they are the same as the upper bits of op1.
11082 We can never remove a SUBREG for a non-equality comparison because
11083 the sign bit is in a different place in the underlying object. */
11085 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11086 op1 = make_compound_operation (op1, SET);
11088 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11089 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11090 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11091 && (code == NE || code == EQ))
11093 if (GET_MODE_SIZE (GET_MODE (op0))
11094 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11096 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11098 if (REG_P (SUBREG_REG (op0)))
11100 op0 = SUBREG_REG (op0);
11101 op1 = gen_lowpart (GET_MODE (op0), op1);
11104 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11105 <= HOST_BITS_PER_WIDE_INT)
11106 && (nonzero_bits (SUBREG_REG (op0),
11107 GET_MODE (SUBREG_REG (op0)))
11108 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11110 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11112 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11113 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11114 op0 = SUBREG_REG (op0), op1 = tem;
11118 /* We now do the opposite procedure: Some machines don't have compare
11119 insns in all modes. If OP0's mode is an integer mode smaller than a
11120 word and we can't do a compare in that mode, see if there is a larger
11121 mode for which we can do the compare. There are a number of cases in
11122 which we can use the wider mode. */
11124 mode = GET_MODE (op0);
11125 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11126 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11127 && ! have_insn_for (COMPARE, mode))
11128 for (tmode = GET_MODE_WIDER_MODE (mode);
11130 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11131 tmode = GET_MODE_WIDER_MODE (tmode))
11132 if (have_insn_for (COMPARE, tmode))
11136 /* If the only nonzero bits in OP0 and OP1 are those in the
11137 narrower mode and this is an equality or unsigned comparison,
11138 we can use the wider mode. Similarly for sign-extended
11139 values, in which case it is true for all comparisons. */
11140 zero_extended = ((code == EQ || code == NE
11141 || code == GEU || code == GTU
11142 || code == LEU || code == LTU)
11143 && (nonzero_bits (op0, tmode)
11144 & ~GET_MODE_MASK (mode)) == 0
11145 && ((CONST_INT_P (op1)
11146 || (nonzero_bits (op1, tmode)
11147 & ~GET_MODE_MASK (mode)) == 0)));
11150 || ((num_sign_bit_copies (op0, tmode)
11151 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11152 - GET_MODE_BITSIZE (mode)))
11153 && (num_sign_bit_copies (op1, tmode)
11154 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11155 - GET_MODE_BITSIZE (mode)))))
11157 /* If OP0 is an AND and we don't have an AND in MODE either,
11158 make a new AND in the proper mode. */
11159 if (GET_CODE (op0) == AND
11160 && !have_insn_for (AND, mode))
11161 op0 = simplify_gen_binary (AND, tmode,
11162 gen_lowpart (tmode,
11164 gen_lowpart (tmode,
11167 op0 = gen_lowpart (tmode, op0);
11168 if (zero_extended && CONST_INT_P (op1))
11169 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11170 op1 = gen_lowpart (tmode, op1);
11174 /* If this is a test for negative, we can make an explicit
11175 test of the sign bit. */
11177 if (op1 == const0_rtx && (code == LT || code == GE)
11178 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11180 op0 = simplify_gen_binary (AND, tmode,
11181 gen_lowpart (tmode, op0),
11182 GEN_INT ((HOST_WIDE_INT) 1
11183 << (GET_MODE_BITSIZE (mode)
11185 code = (code == LT) ? NE : EQ;
11190 #ifdef CANONICALIZE_COMPARISON
11191 /* If this machine only supports a subset of valid comparisons, see if we
11192 can convert an unsupported one into a supported one. */
11193 CANONICALIZE_COMPARISON (code, op0, op1);
11202 /* Utility function for record_value_for_reg. Count number of
11207 enum rtx_code code = GET_CODE (x);
11211 if (GET_RTX_CLASS (code) == '2'
11212 || GET_RTX_CLASS (code) == 'c')
11214 rtx x0 = XEXP (x, 0);
11215 rtx x1 = XEXP (x, 1);
11218 return 1 + 2 * count_rtxs (x0);
11220 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11221 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11222 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11223 return 2 + 2 * count_rtxs (x0)
11224 + count_rtxs (x == XEXP (x1, 0)
11225 ? XEXP (x1, 1) : XEXP (x1, 0));
11227 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11228 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11229 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11230 return 2 + 2 * count_rtxs (x1)
11231 + count_rtxs (x == XEXP (x0, 0)
11232 ? XEXP (x0, 1) : XEXP (x0, 0));
11235 fmt = GET_RTX_FORMAT (code);
11236 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11238 ret += count_rtxs (XEXP (x, i));
11239 else if (fmt[i] == 'E')
11240 for (j = 0; j < XVECLEN (x, i); j++)
11241 ret += count_rtxs (XVECEXP (x, i, j));
11246 /* Utility function for following routine. Called when X is part of a value
11247 being stored into last_set_value. Sets last_set_table_tick
11248 for each register mentioned. Similar to mention_regs in cse.c */
11251 update_table_tick (rtx x)
11253 enum rtx_code code = GET_CODE (x);
11254 const char *fmt = GET_RTX_FORMAT (code);
11259 unsigned int regno = REGNO (x);
11260 unsigned int endregno = END_REGNO (x);
11263 for (r = regno; r < endregno; r++)
11265 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11266 rsp->last_set_table_tick = label_tick;
11272 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11275 /* Check for identical subexpressions. If x contains
11276 identical subexpression we only have to traverse one of
11278 if (i == 0 && ARITHMETIC_P (x))
11280 /* Note that at this point x1 has already been
11282 rtx x0 = XEXP (x, 0);
11283 rtx x1 = XEXP (x, 1);
11285 /* If x0 and x1 are identical then there is no need to
11290 /* If x0 is identical to a subexpression of x1 then while
11291 processing x1, x0 has already been processed. Thus we
11292 are done with x. */
11293 if (ARITHMETIC_P (x1)
11294 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11297 /* If x1 is identical to a subexpression of x0 then we
11298 still have to process the rest of x0. */
11299 if (ARITHMETIC_P (x0)
11300 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11302 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11307 update_table_tick (XEXP (x, i));
11309 else if (fmt[i] == 'E')
11310 for (j = 0; j < XVECLEN (x, i); j++)
11311 update_table_tick (XVECEXP (x, i, j));
11314 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11315 are saying that the register is clobbered and we no longer know its
11316 value. If INSN is zero, don't update reg_stat[].last_set; this is
11317 only permitted with VALUE also zero and is used to invalidate the
11321 record_value_for_reg (rtx reg, rtx insn, rtx value)
11323 unsigned int regno = REGNO (reg);
11324 unsigned int endregno = END_REGNO (reg);
11326 reg_stat_type *rsp;
11328 /* If VALUE contains REG and we have a previous value for REG, substitute
11329 the previous value. */
11330 if (value && insn && reg_overlap_mentioned_p (reg, value))
11334 /* Set things up so get_last_value is allowed to see anything set up to
11336 subst_low_luid = DF_INSN_LUID (insn);
11337 tem = get_last_value (reg);
11339 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11340 it isn't going to be useful and will take a lot of time to process,
11341 so just use the CLOBBER. */
11345 if (ARITHMETIC_P (tem)
11346 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11347 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11348 tem = XEXP (tem, 0);
11349 else if (count_occurrences (value, reg, 1) >= 2)
11351 /* If there are two or more occurrences of REG in VALUE,
11352 prevent the value from growing too much. */
11353 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11354 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11357 value = replace_rtx (copy_rtx (value), reg, tem);
11361 /* For each register modified, show we don't know its value, that
11362 we don't know about its bitwise content, that its value has been
11363 updated, and that we don't know the location of the death of the
11365 for (i = regno; i < endregno; i++)
11367 rsp = VEC_index (reg_stat_type, reg_stat, i);
11370 rsp->last_set = insn;
11372 rsp->last_set_value = 0;
11373 rsp->last_set_mode = VOIDmode;
11374 rsp->last_set_nonzero_bits = 0;
11375 rsp->last_set_sign_bit_copies = 0;
11376 rsp->last_death = 0;
11377 rsp->truncated_to_mode = VOIDmode;
11380 /* Mark registers that are being referenced in this value. */
11382 update_table_tick (value);
11384 /* Now update the status of each register being set.
11385 If someone is using this register in this block, set this register
11386 to invalid since we will get confused between the two lives in this
11387 basic block. This makes using this register always invalid. In cse, we
11388 scan the table to invalidate all entries using this register, but this
11389 is too much work for us. */
11391 for (i = regno; i < endregno; i++)
11393 rsp = VEC_index (reg_stat_type, reg_stat, i);
11394 rsp->last_set_label = label_tick;
11396 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11397 rsp->last_set_invalid = 1;
11399 rsp->last_set_invalid = 0;
11402 /* The value being assigned might refer to X (like in "x++;"). In that
11403 case, we must replace it with (clobber (const_int 0)) to prevent
11405 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11406 if (value && ! get_last_value_validate (&value, insn,
11407 rsp->last_set_label, 0))
11409 value = copy_rtx (value);
11410 if (! get_last_value_validate (&value, insn,
11411 rsp->last_set_label, 1))
11415 /* For the main register being modified, update the value, the mode, the
11416 nonzero bits, and the number of sign bit copies. */
11418 rsp->last_set_value = value;
11422 enum machine_mode mode = GET_MODE (reg);
11423 subst_low_luid = DF_INSN_LUID (insn);
11424 rsp->last_set_mode = mode;
11425 if (GET_MODE_CLASS (mode) == MODE_INT
11426 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11427 mode = nonzero_bits_mode;
11428 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11429 rsp->last_set_sign_bit_copies
11430 = num_sign_bit_copies (value, GET_MODE (reg));
11434 /* Called via note_stores from record_dead_and_set_regs to handle one
11435 SET or CLOBBER in an insn. DATA is the instruction in which the
11436 set is occurring. */
11439 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11441 rtx record_dead_insn = (rtx) data;
11443 if (GET_CODE (dest) == SUBREG)
11444 dest = SUBREG_REG (dest);
11446 if (!record_dead_insn)
11449 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11455 /* If we are setting the whole register, we know its value. Otherwise
11456 show that we don't know the value. We can handle SUBREG in
11458 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11459 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11460 else if (GET_CODE (setter) == SET
11461 && GET_CODE (SET_DEST (setter)) == SUBREG
11462 && SUBREG_REG (SET_DEST (setter)) == dest
11463 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11464 && subreg_lowpart_p (SET_DEST (setter)))
11465 record_value_for_reg (dest, record_dead_insn,
11466 gen_lowpart (GET_MODE (dest),
11467 SET_SRC (setter)));
11469 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11471 else if (MEM_P (dest)
11472 /* Ignore pushes, they clobber nothing. */
11473 && ! push_operand (dest, GET_MODE (dest)))
11474 mem_last_set = DF_INSN_LUID (record_dead_insn);
11477 /* Update the records of when each REG was most recently set or killed
11478 for the things done by INSN. This is the last thing done in processing
11479 INSN in the combiner loop.
11481 We update reg_stat[], in particular fields last_set, last_set_value,
11482 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11483 last_death, and also the similar information mem_last_set (which insn
11484 most recently modified memory) and last_call_luid (which insn was the
11485 most recent subroutine call). */
11488 record_dead_and_set_regs (rtx insn)
11493 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11495 if (REG_NOTE_KIND (link) == REG_DEAD
11496 && REG_P (XEXP (link, 0)))
11498 unsigned int regno = REGNO (XEXP (link, 0));
11499 unsigned int endregno = END_REGNO (XEXP (link, 0));
11501 for (i = regno; i < endregno; i++)
11503 reg_stat_type *rsp;
11505 rsp = VEC_index (reg_stat_type, reg_stat, i);
11506 rsp->last_death = insn;
11509 else if (REG_NOTE_KIND (link) == REG_INC)
11510 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11515 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11516 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11518 reg_stat_type *rsp;
11520 rsp = VEC_index (reg_stat_type, reg_stat, i);
11521 rsp->last_set_invalid = 1;
11522 rsp->last_set = insn;
11523 rsp->last_set_value = 0;
11524 rsp->last_set_mode = VOIDmode;
11525 rsp->last_set_nonzero_bits = 0;
11526 rsp->last_set_sign_bit_copies = 0;
11527 rsp->last_death = 0;
11528 rsp->truncated_to_mode = VOIDmode;
11531 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11533 /* We can't combine into a call pattern. Remember, though, that
11534 the return value register is set at this LUID. We could
11535 still replace a register with the return value from the
11536 wrong subroutine call! */
11537 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11540 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11543 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11544 register present in the SUBREG, so for each such SUBREG go back and
11545 adjust nonzero and sign bit information of the registers that are
11546 known to have some zero/sign bits set.
11548 This is needed because when combine blows the SUBREGs away, the
11549 information on zero/sign bits is lost and further combines can be
11550 missed because of that. */
11553 record_promoted_value (rtx insn, rtx subreg)
11556 unsigned int regno = REGNO (SUBREG_REG (subreg));
11557 enum machine_mode mode = GET_MODE (subreg);
11559 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11562 for (links = LOG_LINKS (insn); links;)
11564 reg_stat_type *rsp;
11566 insn = XEXP (links, 0);
11567 set = single_set (insn);
11569 if (! set || !REG_P (SET_DEST (set))
11570 || REGNO (SET_DEST (set)) != regno
11571 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11573 links = XEXP (links, 1);
11577 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11578 if (rsp->last_set == insn)
11580 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11581 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11584 if (REG_P (SET_SRC (set)))
11586 regno = REGNO (SET_SRC (set));
11587 links = LOG_LINKS (insn);
11594 /* Check if X, a register, is known to contain a value already
11595 truncated to MODE. In this case we can use a subreg to refer to
11596 the truncated value even though in the generic case we would need
11597 an explicit truncation. */
11600 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11602 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11603 enum machine_mode truncated = rsp->truncated_to_mode;
11606 || rsp->truncation_label < label_tick_ebb_start)
11608 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11610 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11611 GET_MODE_BITSIZE (truncated)))
11616 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11617 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11618 might be able to turn a truncate into a subreg using this information.
11619 Return -1 if traversing *P is complete or 0 otherwise. */
11622 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11625 enum machine_mode truncated_mode;
11626 reg_stat_type *rsp;
11628 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11630 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11631 truncated_mode = GET_MODE (x);
11633 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11636 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11637 GET_MODE_BITSIZE (original_mode)))
11640 x = SUBREG_REG (x);
11642 /* ??? For hard-regs we now record everything. We might be able to
11643 optimize this using last_set_mode. */
11644 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11645 truncated_mode = GET_MODE (x);
11649 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11650 if (rsp->truncated_to_mode == 0
11651 || rsp->truncation_label < label_tick_ebb_start
11652 || (GET_MODE_SIZE (truncated_mode)
11653 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11655 rsp->truncated_to_mode = truncated_mode;
11656 rsp->truncation_label = label_tick;
11662 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11663 the modes they are used in. This can help truning TRUNCATEs into
11667 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11669 for_each_rtx (x, record_truncated_value, NULL);
11672 /* Scan X for promoted SUBREGs. For each one found,
11673 note what it implies to the registers used in it. */
11676 check_promoted_subreg (rtx insn, rtx x)
11678 if (GET_CODE (x) == SUBREG
11679 && SUBREG_PROMOTED_VAR_P (x)
11680 && REG_P (SUBREG_REG (x)))
11681 record_promoted_value (insn, x);
11684 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11687 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11691 check_promoted_subreg (insn, XEXP (x, i));
11695 if (XVEC (x, i) != 0)
11696 for (j = 0; j < XVECLEN (x, i); j++)
11697 check_promoted_subreg (insn, XVECEXP (x, i, j));
11703 /* Utility routine for the following function. Verify that all the registers
11704 mentioned in *LOC are valid when *LOC was part of a value set when
11705 label_tick == TICK. Return 0 if some are not.
11707 If REPLACE is nonzero, replace the invalid reference with
11708 (clobber (const_int 0)) and return 1. This replacement is useful because
11709 we often can get useful information about the form of a value (e.g., if
11710 it was produced by a shift that always produces -1 or 0) even though
11711 we don't know exactly what registers it was produced from. */
11714 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11717 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11718 int len = GET_RTX_LENGTH (GET_CODE (x));
11723 unsigned int regno = REGNO (x);
11724 unsigned int endregno = END_REGNO (x);
11727 for (j = regno; j < endregno; j++)
11729 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11730 if (rsp->last_set_invalid
11731 /* If this is a pseudo-register that was only set once and not
11732 live at the beginning of the function, it is always valid. */
11733 || (! (regno >= FIRST_PSEUDO_REGISTER
11734 && REG_N_SETS (regno) == 1
11735 && (!REGNO_REG_SET_P
11736 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11737 && rsp->last_set_label > tick))
11740 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11747 /* If this is a memory reference, make sure that there were
11748 no stores after it that might have clobbered the value. We don't
11749 have alias info, so we assume any store invalidates it. */
11750 else if (MEM_P (x) && !MEM_READONLY_P (x)
11751 && DF_INSN_LUID (insn) <= mem_last_set)
11754 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11758 for (i = 0; i < len; i++)
11762 /* Check for identical subexpressions. If x contains
11763 identical subexpression we only have to traverse one of
11765 if (i == 1 && ARITHMETIC_P (x))
11767 /* Note that at this point x0 has already been checked
11768 and found valid. */
11769 rtx x0 = XEXP (x, 0);
11770 rtx x1 = XEXP (x, 1);
11772 /* If x0 and x1 are identical then x is also valid. */
11776 /* If x1 is identical to a subexpression of x0 then
11777 while checking x0, x1 has already been checked. Thus
11778 it is valid and so as x. */
11779 if (ARITHMETIC_P (x0)
11780 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11783 /* If x0 is identical to a subexpression of x1 then x is
11784 valid iff the rest of x1 is valid. */
11785 if (ARITHMETIC_P (x1)
11786 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11788 get_last_value_validate (&XEXP (x1,
11789 x0 == XEXP (x1, 0) ? 1 : 0),
11790 insn, tick, replace);
11793 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11797 else if (fmt[i] == 'E')
11798 for (j = 0; j < XVECLEN (x, i); j++)
11799 if (get_last_value_validate (&XVECEXP (x, i, j),
11800 insn, tick, replace) == 0)
11804 /* If we haven't found a reason for it to be invalid, it is valid. */
11808 /* Get the last value assigned to X, if known. Some registers
11809 in the value may be replaced with (clobber (const_int 0)) if their value
11810 is known longer known reliably. */
11813 get_last_value (const_rtx x)
11815 unsigned int regno;
11817 reg_stat_type *rsp;
11819 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11820 then convert it to the desired mode. If this is a paradoxical SUBREG,
11821 we cannot predict what values the "extra" bits might have. */
11822 if (GET_CODE (x) == SUBREG
11823 && subreg_lowpart_p (x)
11824 && (GET_MODE_SIZE (GET_MODE (x))
11825 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11826 && (value = get_last_value (SUBREG_REG (x))) != 0)
11827 return gen_lowpart (GET_MODE (x), value);
11833 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11834 value = rsp->last_set_value;
11836 /* If we don't have a value, or if it isn't for this basic block and
11837 it's either a hard register, set more than once, or it's a live
11838 at the beginning of the function, return 0.
11840 Because if it's not live at the beginning of the function then the reg
11841 is always set before being used (is never used without being set).
11842 And, if it's set only once, and it's always set before use, then all
11843 uses must have the same last value, even if it's not from this basic
11847 || (rsp->last_set_label < label_tick_ebb_start
11848 && (regno < FIRST_PSEUDO_REGISTER
11849 || REG_N_SETS (regno) != 1
11851 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11854 /* If the value was set in a later insn than the ones we are processing,
11855 we can't use it even if the register was only set once. */
11856 if (rsp->last_set_label == label_tick
11857 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11860 /* If the value has all its registers valid, return it. */
11861 if (get_last_value_validate (&value, rsp->last_set,
11862 rsp->last_set_label, 0))
11865 /* Otherwise, make a copy and replace any invalid register with
11866 (clobber (const_int 0)). If that fails for some reason, return 0. */
11868 value = copy_rtx (value);
11869 if (get_last_value_validate (&value, rsp->last_set,
11870 rsp->last_set_label, 1))
11876 /* Return nonzero if expression X refers to a REG or to memory
11877 that is set in an instruction more recent than FROM_LUID. */
11880 use_crosses_set_p (const_rtx x, int from_luid)
11884 enum rtx_code code = GET_CODE (x);
11888 unsigned int regno = REGNO (x);
11889 unsigned endreg = END_REGNO (x);
11891 #ifdef PUSH_ROUNDING
11892 /* Don't allow uses of the stack pointer to be moved,
11893 because we don't know whether the move crosses a push insn. */
11894 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11897 for (; regno < endreg; regno++)
11899 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11901 && rsp->last_set_label == label_tick
11902 && DF_INSN_LUID (rsp->last_set) > from_luid)
11908 if (code == MEM && mem_last_set > from_luid)
11911 fmt = GET_RTX_FORMAT (code);
11913 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11918 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11919 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11922 else if (fmt[i] == 'e'
11923 && use_crosses_set_p (XEXP (x, i), from_luid))
11929 /* Define three variables used for communication between the following
11932 static unsigned int reg_dead_regno, reg_dead_endregno;
11933 static int reg_dead_flag;
11935 /* Function called via note_stores from reg_dead_at_p.
11937 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11938 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11941 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11943 unsigned int regno, endregno;
11948 regno = REGNO (dest);
11949 endregno = END_REGNO (dest);
11950 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11951 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11954 /* Return nonzero if REG is known to be dead at INSN.
11956 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11957 referencing REG, it is dead. If we hit a SET referencing REG, it is
11958 live. Otherwise, see if it is live or dead at the start of the basic
11959 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11960 must be assumed to be always live. */
11963 reg_dead_at_p (rtx reg, rtx insn)
11968 /* Set variables for reg_dead_at_p_1. */
11969 reg_dead_regno = REGNO (reg);
11970 reg_dead_endregno = END_REGNO (reg);
11974 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11975 we allow the machine description to decide whether use-and-clobber
11976 patterns are OK. */
11977 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11979 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11980 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11984 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
11985 beginning of basic block. */
11986 block = BLOCK_FOR_INSN (insn);
11991 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11993 return reg_dead_flag == 1 ? 1 : 0;
11995 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11999 if (insn == BB_HEAD (block))
12002 insn = PREV_INSN (insn);
12005 /* Look at live-in sets for the basic block that we were in. */
12006 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12007 if (REGNO_REG_SET_P (df_get_live_in (block), i))
12013 /* Note hard registers in X that are used. */
12016 mark_used_regs_combine (rtx x)
12018 RTX_CODE code = GET_CODE (x);
12019 unsigned int regno;
12032 case ADDR_DIFF_VEC:
12035 /* CC0 must die in the insn after it is set, so we don't need to take
12036 special note of it here. */
12042 /* If we are clobbering a MEM, mark any hard registers inside the
12043 address as used. */
12044 if (MEM_P (XEXP (x, 0)))
12045 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12050 /* A hard reg in a wide mode may really be multiple registers.
12051 If so, mark all of them just like the first. */
12052 if (regno < FIRST_PSEUDO_REGISTER)
12054 /* None of this applies to the stack, frame or arg pointers. */
12055 if (regno == STACK_POINTER_REGNUM
12056 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12057 || regno == HARD_FRAME_POINTER_REGNUM
12059 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12060 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12062 || regno == FRAME_POINTER_REGNUM)
12065 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12071 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12073 rtx testreg = SET_DEST (x);
12075 while (GET_CODE (testreg) == SUBREG
12076 || GET_CODE (testreg) == ZERO_EXTRACT
12077 || GET_CODE (testreg) == STRICT_LOW_PART)
12078 testreg = XEXP (testreg, 0);
12080 if (MEM_P (testreg))
12081 mark_used_regs_combine (XEXP (testreg, 0));
12083 mark_used_regs_combine (SET_SRC (x));
12091 /* Recursively scan the operands of this expression. */
12094 const char *fmt = GET_RTX_FORMAT (code);
12096 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12099 mark_used_regs_combine (XEXP (x, i));
12100 else if (fmt[i] == 'E')
12104 for (j = 0; j < XVECLEN (x, i); j++)
12105 mark_used_regs_combine (XVECEXP (x, i, j));
12111 /* Remove register number REGNO from the dead registers list of INSN.
12113 Return the note used to record the death, if there was one. */
12116 remove_death (unsigned int regno, rtx insn)
12118 rtx note = find_regno_note (insn, REG_DEAD, regno);
12121 remove_note (insn, note);
12126 /* For each register (hardware or pseudo) used within expression X, if its
12127 death is in an instruction with luid between FROM_LUID (inclusive) and
12128 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12129 list headed by PNOTES.
12131 That said, don't move registers killed by maybe_kill_insn.
12133 This is done when X is being merged by combination into TO_INSN. These
12134 notes will then be distributed as needed. */
12137 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12142 enum rtx_code code = GET_CODE (x);
12146 unsigned int regno = REGNO (x);
12147 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12149 /* Don't move the register if it gets killed in between from and to. */
12150 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12151 && ! reg_referenced_p (x, maybe_kill_insn))
12155 && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
12156 && DF_INSN_LUID (where_dead) >= from_luid
12157 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12159 rtx note = remove_death (regno, where_dead);
12161 /* It is possible for the call above to return 0. This can occur
12162 when last_death points to I2 or I1 that we combined with.
12163 In that case make a new note.
12165 We must also check for the case where X is a hard register
12166 and NOTE is a death note for a range of hard registers
12167 including X. In that case, we must put REG_DEAD notes for
12168 the remaining registers in place of NOTE. */
12170 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12171 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12172 > GET_MODE_SIZE (GET_MODE (x))))
12174 unsigned int deadregno = REGNO (XEXP (note, 0));
12175 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12176 unsigned int ourend = END_HARD_REGNO (x);
12179 for (i = deadregno; i < deadend; i++)
12180 if (i < regno || i >= ourend)
12181 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12184 /* If we didn't find any note, or if we found a REG_DEAD note that
12185 covers only part of the given reg, and we have a multi-reg hard
12186 register, then to be safe we must check for REG_DEAD notes
12187 for each register other than the first. They could have
12188 their own REG_DEAD notes lying around. */
12189 else if ((note == 0
12191 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12192 < GET_MODE_SIZE (GET_MODE (x)))))
12193 && regno < FIRST_PSEUDO_REGISTER
12194 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12196 unsigned int ourend = END_HARD_REGNO (x);
12197 unsigned int i, offset;
12201 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12205 for (i = regno + offset; i < ourend; i++)
12206 move_deaths (regno_reg_rtx[i],
12207 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12210 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12212 XEXP (note, 1) = *pnotes;
12216 *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
12222 else if (GET_CODE (x) == SET)
12224 rtx dest = SET_DEST (x);
12226 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12228 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12229 that accesses one word of a multi-word item, some
12230 piece of everything register in the expression is used by
12231 this insn, so remove any old death. */
12232 /* ??? So why do we test for equality of the sizes? */
12234 if (GET_CODE (dest) == ZERO_EXTRACT
12235 || GET_CODE (dest) == STRICT_LOW_PART
12236 || (GET_CODE (dest) == SUBREG
12237 && (((GET_MODE_SIZE (GET_MODE (dest))
12238 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12239 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12240 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12242 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12246 /* If this is some other SUBREG, we know it replaces the entire
12247 value, so use that as the destination. */
12248 if (GET_CODE (dest) == SUBREG)
12249 dest = SUBREG_REG (dest);
12251 /* If this is a MEM, adjust deaths of anything used in the address.
12252 For a REG (the only other possibility), the entire value is
12253 being replaced so the old value is not used in this insn. */
12256 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12261 else if (GET_CODE (x) == CLOBBER)
12264 len = GET_RTX_LENGTH (code);
12265 fmt = GET_RTX_FORMAT (code);
12267 for (i = 0; i < len; i++)
12272 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12273 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12276 else if (fmt[i] == 'e')
12277 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12281 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12282 pattern of an insn. X must be a REG. */
12285 reg_bitfield_target_p (rtx x, rtx body)
12289 if (GET_CODE (body) == SET)
12291 rtx dest = SET_DEST (body);
12293 unsigned int regno, tregno, endregno, endtregno;
12295 if (GET_CODE (dest) == ZERO_EXTRACT)
12296 target = XEXP (dest, 0);
12297 else if (GET_CODE (dest) == STRICT_LOW_PART)
12298 target = SUBREG_REG (XEXP (dest, 0));
12302 if (GET_CODE (target) == SUBREG)
12303 target = SUBREG_REG (target);
12305 if (!REG_P (target))
12308 tregno = REGNO (target), regno = REGNO (x);
12309 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12310 return target == x;
12312 endtregno = end_hard_regno (GET_MODE (target), tregno);
12313 endregno = end_hard_regno (GET_MODE (x), regno);
12315 return endregno > tregno && regno < endtregno;
12318 else if (GET_CODE (body) == PARALLEL)
12319 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12320 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12326 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12327 as appropriate. I3 and I2 are the insns resulting from the combination
12328 insns including FROM (I2 may be zero).
12330 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12331 not need REG_DEAD notes because they are being substituted for. This
12332 saves searching in the most common cases.
12334 Each note in the list is either ignored or placed on some insns, depending
12335 on the type of note. */
12338 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12341 rtx note, next_note;
12344 for (note = notes; note; note = next_note)
12346 rtx place = 0, place2 = 0;
12348 next_note = XEXP (note, 1);
12349 switch (REG_NOTE_KIND (note))
12353 /* Doesn't matter much where we put this, as long as it's somewhere.
12354 It is preferable to keep these notes on branches, which is most
12355 likely to be i3. */
12359 case REG_VALUE_PROFILE:
12360 /* Just get rid of this note, as it is unused later anyway. */
12363 case REG_NON_LOCAL_GOTO:
12368 gcc_assert (i2 && JUMP_P (i2));
12373 case REG_EH_REGION:
12374 /* These notes must remain with the call or trapping instruction. */
12377 else if (i2 && CALL_P (i2))
12381 gcc_assert (flag_non_call_exceptions);
12382 if (may_trap_p (i3))
12384 else if (i2 && may_trap_p (i2))
12386 /* ??? Otherwise assume we've combined things such that we
12387 can now prove that the instructions can't trap. Drop the
12388 note in this case. */
12394 /* These notes must remain with the call. It should not be
12395 possible for both I2 and I3 to be a call. */
12400 gcc_assert (i2 && CALL_P (i2));
12406 /* Any clobbers for i3 may still exist, and so we must process
12407 REG_UNUSED notes from that insn.
12409 Any clobbers from i2 or i1 can only exist if they were added by
12410 recog_for_combine. In that case, recog_for_combine created the
12411 necessary REG_UNUSED notes. Trying to keep any original
12412 REG_UNUSED notes from these insns can cause incorrect output
12413 if it is for the same register as the original i3 dest.
12414 In that case, we will notice that the register is set in i3,
12415 and then add a REG_UNUSED note for the destination of i3, which
12416 is wrong. However, it is possible to have REG_UNUSED notes from
12417 i2 or i1 for register which were both used and clobbered, so
12418 we keep notes from i2 or i1 if they will turn into REG_DEAD
12421 /* If this register is set or clobbered in I3, put the note there
12422 unless there is one already. */
12423 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12425 if (from_insn != i3)
12428 if (! (REG_P (XEXP (note, 0))
12429 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12430 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12433 /* Otherwise, if this register is used by I3, then this register
12434 now dies here, so we must put a REG_DEAD note here unless there
12436 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12437 && ! (REG_P (XEXP (note, 0))
12438 ? find_regno_note (i3, REG_DEAD,
12439 REGNO (XEXP (note, 0)))
12440 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12442 PUT_REG_NOTE_KIND (note, REG_DEAD);
12450 /* These notes say something about results of an insn. We can
12451 only support them if they used to be on I3 in which case they
12452 remain on I3. Otherwise they are ignored.
12454 If the note refers to an expression that is not a constant, we
12455 must also ignore the note since we cannot tell whether the
12456 equivalence is still true. It might be possible to do
12457 slightly better than this (we only have a problem if I2DEST
12458 or I1DEST is present in the expression), but it doesn't
12459 seem worth the trouble. */
12461 if (from_insn == i3
12462 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12467 /* These notes say something about how a register is used. They must
12468 be present on any use of the register in I2 or I3. */
12469 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12472 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12481 case REG_LABEL_TARGET:
12482 case REG_LABEL_OPERAND:
12483 /* This can show up in several ways -- either directly in the
12484 pattern, or hidden off in the constant pool with (or without?)
12485 a REG_EQUAL note. */
12486 /* ??? Ignore the without-reg_equal-note problem for now. */
12487 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12488 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12489 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12490 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12494 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12495 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12496 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12497 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12505 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12506 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12508 if (place && JUMP_P (place)
12509 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12510 && (JUMP_LABEL (place) == NULL
12511 || JUMP_LABEL (place) == XEXP (note, 0)))
12513 rtx label = JUMP_LABEL (place);
12516 JUMP_LABEL (place) = XEXP (note, 0);
12517 else if (LABEL_P (label))
12518 LABEL_NUSES (label)--;
12521 if (place2 && JUMP_P (place2)
12522 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12523 && (JUMP_LABEL (place2) == NULL
12524 || JUMP_LABEL (place2) == XEXP (note, 0)))
12526 rtx label = JUMP_LABEL (place2);
12529 JUMP_LABEL (place2) = XEXP (note, 0);
12530 else if (LABEL_P (label))
12531 LABEL_NUSES (label)--;
12537 /* This note says something about the value of a register prior
12538 to the execution of an insn. It is too much trouble to see
12539 if the note is still correct in all situations. It is better
12540 to simply delete it. */
12544 /* If we replaced the right hand side of FROM_INSN with a
12545 REG_EQUAL note, the original use of the dying register
12546 will not have been combined into I3 and I2. In such cases,
12547 FROM_INSN is guaranteed to be the first of the combined
12548 instructions, so we simply need to search back before
12549 FROM_INSN for the previous use or set of this register,
12550 then alter the notes there appropriately.
12552 If the register is used as an input in I3, it dies there.
12553 Similarly for I2, if it is nonzero and adjacent to I3.
12555 If the register is not used as an input in either I3 or I2
12556 and it is not one of the registers we were supposed to eliminate,
12557 there are two possibilities. We might have a non-adjacent I2
12558 or we might have somehow eliminated an additional register
12559 from a computation. For example, we might have had A & B where
12560 we discover that B will always be zero. In this case we will
12561 eliminate the reference to A.
12563 In both cases, we must search to see if we can find a previous
12564 use of A and put the death note there. */
12567 && from_insn == i2mod
12568 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12573 && CALL_P (from_insn)
12574 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12576 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12578 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12579 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12581 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12583 && reg_overlap_mentioned_p (XEXP (note, 0),
12585 || rtx_equal_p (XEXP (note, 0), elim_i1))
12592 basic_block bb = this_basic_block;
12594 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12596 if (! INSN_P (tem))
12598 if (tem == BB_HEAD (bb))
12603 /* If the register is being set at TEM, see if that is all
12604 TEM is doing. If so, delete TEM. Otherwise, make this
12605 into a REG_UNUSED note instead. Don't delete sets to
12606 global register vars. */
12607 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12608 || !global_regs[REGNO (XEXP (note, 0))])
12609 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12611 rtx set = single_set (tem);
12612 rtx inner_dest = 0;
12614 rtx cc0_setter = NULL_RTX;
12618 for (inner_dest = SET_DEST (set);
12619 (GET_CODE (inner_dest) == STRICT_LOW_PART
12620 || GET_CODE (inner_dest) == SUBREG
12621 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12622 inner_dest = XEXP (inner_dest, 0))
12625 /* Verify that it was the set, and not a clobber that
12626 modified the register.
12628 CC0 targets must be careful to maintain setter/user
12629 pairs. If we cannot delete the setter due to side
12630 effects, mark the user with an UNUSED note instead
12633 if (set != 0 && ! side_effects_p (SET_SRC (set))
12634 && rtx_equal_p (XEXP (note, 0), inner_dest)
12636 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12637 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12638 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12642 /* Move the notes and links of TEM elsewhere.
12643 This might delete other dead insns recursively.
12644 First set the pattern to something that won't use
12646 rtx old_notes = REG_NOTES (tem);
12648 PATTERN (tem) = pc_rtx;
12649 REG_NOTES (tem) = NULL;
12651 distribute_notes (old_notes, tem, tem, NULL_RTX,
12652 NULL_RTX, NULL_RTX);
12653 distribute_links (LOG_LINKS (tem));
12655 SET_INSN_DELETED (tem);
12660 /* Delete the setter too. */
12663 PATTERN (cc0_setter) = pc_rtx;
12664 old_notes = REG_NOTES (cc0_setter);
12665 REG_NOTES (cc0_setter) = NULL;
12667 distribute_notes (old_notes, cc0_setter,
12668 cc0_setter, NULL_RTX,
12669 NULL_RTX, NULL_RTX);
12670 distribute_links (LOG_LINKS (cc0_setter));
12672 SET_INSN_DELETED (cc0_setter);
12673 if (cc0_setter == i2)
12680 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12682 /* If there isn't already a REG_UNUSED note, put one
12683 here. Do not place a REG_DEAD note, even if
12684 the register is also used here; that would not
12685 match the algorithm used in lifetime analysis
12686 and can cause the consistency check in the
12687 scheduler to fail. */
12688 if (! find_regno_note (tem, REG_UNUSED,
12689 REGNO (XEXP (note, 0))))
12694 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12696 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12700 /* If we are doing a 3->2 combination, and we have a
12701 register which formerly died in i3 and was not used
12702 by i2, which now no longer dies in i3 and is used in
12703 i2 but does not die in i2, and place is between i2
12704 and i3, then we may need to move a link from place to
12706 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12708 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12709 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12711 rtx links = LOG_LINKS (place);
12712 LOG_LINKS (place) = 0;
12713 distribute_links (links);
12718 if (tem == BB_HEAD (bb))
12724 /* If the register is set or already dead at PLACE, we needn't do
12725 anything with this note if it is still a REG_DEAD note.
12726 We check here if it is set at all, not if is it totally replaced,
12727 which is what `dead_or_set_p' checks, so also check for it being
12730 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12732 unsigned int regno = REGNO (XEXP (note, 0));
12733 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12735 if (dead_or_set_p (place, XEXP (note, 0))
12736 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12738 /* Unless the register previously died in PLACE, clear
12739 last_death. [I no longer understand why this is
12741 if (rsp->last_death != place)
12742 rsp->last_death = 0;
12746 rsp->last_death = place;
12748 /* If this is a death note for a hard reg that is occupying
12749 multiple registers, ensure that we are still using all
12750 parts of the object. If we find a piece of the object
12751 that is unused, we must arrange for an appropriate REG_DEAD
12752 note to be added for it. However, we can't just emit a USE
12753 and tag the note to it, since the register might actually
12754 be dead; so we recourse, and the recursive call then finds
12755 the previous insn that used this register. */
12757 if (place && regno < FIRST_PSEUDO_REGISTER
12758 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12760 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12764 for (i = regno; i < endregno; i++)
12765 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12766 && ! find_regno_fusage (place, USE, i))
12767 || dead_or_set_regno_p (place, i))
12772 /* Put only REG_DEAD notes for pieces that are
12773 not already dead or set. */
12775 for (i = regno; i < endregno;
12776 i += hard_regno_nregs[i][reg_raw_mode[i]])
12778 rtx piece = regno_reg_rtx[i];
12779 basic_block bb = this_basic_block;
12781 if (! dead_or_set_p (place, piece)
12782 && ! reg_bitfield_target_p (piece,
12785 rtx new_note = alloc_reg_note (REG_DEAD, piece,
12788 distribute_notes (new_note, place, place,
12789 NULL_RTX, NULL_RTX, NULL_RTX);
12791 else if (! refers_to_regno_p (i, i + 1,
12792 PATTERN (place), 0)
12793 && ! find_regno_fusage (place, USE, i))
12794 for (tem = PREV_INSN (place); ;
12795 tem = PREV_INSN (tem))
12797 if (! INSN_P (tem))
12799 if (tem == BB_HEAD (bb))
12803 if (dead_or_set_p (tem, piece)
12804 || reg_bitfield_target_p (piece,
12807 add_reg_note (tem, REG_UNUSED, piece);
12821 /* Any other notes should not be present at this point in the
12823 gcc_unreachable ();
12828 XEXP (note, 1) = REG_NOTES (place);
12829 REG_NOTES (place) = note;
12833 add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
12837 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12838 I3, I2, and I1 to new locations. This is also called to add a link
12839 pointing at I3 when I3's destination is changed. */
12842 distribute_links (rtx links)
12844 rtx link, next_link;
12846 for (link = links; link; link = next_link)
12852 next_link = XEXP (link, 1);
12854 /* If the insn that this link points to is a NOTE or isn't a single
12855 set, ignore it. In the latter case, it isn't clear what we
12856 can do other than ignore the link, since we can't tell which
12857 register it was for. Such links wouldn't be used by combine
12860 It is not possible for the destination of the target of the link to
12861 have been changed by combine. The only potential of this is if we
12862 replace I3, I2, and I1 by I3 and I2. But in that case the
12863 destination of I2 also remains unchanged. */
12865 if (NOTE_P (XEXP (link, 0))
12866 || (set = single_set (XEXP (link, 0))) == 0)
12869 reg = SET_DEST (set);
12870 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12871 || GET_CODE (reg) == STRICT_LOW_PART)
12872 reg = XEXP (reg, 0);
12874 /* A LOG_LINK is defined as being placed on the first insn that uses
12875 a register and points to the insn that sets the register. Start
12876 searching at the next insn after the target of the link and stop
12877 when we reach a set of the register or the end of the basic block.
12879 Note that this correctly handles the link that used to point from
12880 I3 to I2. Also note that not much searching is typically done here
12881 since most links don't point very far away. */
12883 for (insn = NEXT_INSN (XEXP (link, 0));
12884 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12885 || BB_HEAD (this_basic_block->next_bb) != insn));
12886 insn = NEXT_INSN (insn))
12887 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12889 if (reg_referenced_p (reg, PATTERN (insn)))
12893 else if (CALL_P (insn)
12894 && find_reg_fusage (insn, USE, reg))
12899 else if (INSN_P (insn) && reg_set_p (reg, insn))
12902 /* If we found a place to put the link, place it there unless there
12903 is already a link to the same insn as LINK at that point. */
12909 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12910 if (XEXP (link2, 0) == XEXP (link, 0))
12915 XEXP (link, 1) = LOG_LINKS (place);
12916 LOG_LINKS (place) = link;
12918 /* Set added_links_insn to the earliest insn we added a
12920 if (added_links_insn == 0
12921 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12922 added_links_insn = place;
12928 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12929 Check whether the expression pointer to by LOC is a register or
12930 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12931 Otherwise return zero. */
12934 unmentioned_reg_p_1 (rtx *loc, void *expr)
12939 && (REG_P (x) || MEM_P (x))
12940 && ! reg_mentioned_p (x, (rtx) expr))
12945 /* Check for any register or memory mentioned in EQUIV that is not
12946 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12947 of EXPR where some registers may have been replaced by constants. */
12950 unmentioned_reg_p (rtx equiv, rtx expr)
12952 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12956 dump_combine_stats (FILE *file)
12960 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12961 combine_attempts, combine_merges, combine_extras, combine_successes);
12965 dump_combine_total_stats (FILE *file)
12969 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12970 total_attempts, total_merges, total_extras, total_successes);
12974 gate_handle_combine (void)
12976 return (optimize > 0);
12979 /* Try combining insns through substitution. */
12980 static unsigned int
12981 rest_of_handle_combine (void)
12983 int rebuild_jump_labels_after_combine;
12985 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
12986 df_note_add_problem ();
12989 regstat_init_n_sets_and_refs ();
12991 rebuild_jump_labels_after_combine
12992 = combine_instructions (get_insns (), max_reg_num ());
12994 /* Combining insns may have turned an indirect jump into a
12995 direct jump. Rebuild the JUMP_LABEL fields of jumping
12997 if (rebuild_jump_labels_after_combine)
12999 timevar_push (TV_JUMP);
13000 rebuild_jump_labels (get_insns ());
13002 timevar_pop (TV_JUMP);
13005 regstat_free_n_sets_and_refs ();
13009 struct rtl_opt_pass pass_combine =
13013 "combine", /* name */
13014 gate_handle_combine, /* gate */
13015 rest_of_handle_combine, /* execute */
13018 0, /* static_pass_number */
13019 TV_COMBINE, /* tv_id */
13020 PROP_cfglayout, /* properties_required */
13021 0, /* properties_provided */
13022 0, /* properties_destroyed */
13023 0, /* todo_flags_start */
13025 TODO_df_finish | TODO_verify_rtl_sharing |
13026 TODO_ggc_collect, /* todo_flags_finish */