1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992 Free Software Foundation, Inc.
4 This file is part of GNU CC.
6 GNU CC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GNU CC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GNU CC; see the file COPYING. If not, write to
18 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21 /* This module is essentially the "combiner" phase of the U. of Arizona
22 Portable Optimizer, but redone to work on our list-structured
23 representation for RTL instead of their string representation.
25 The LOG_LINKS of each insn identify the most recent assignment
26 to each REG used in the insn. It is a list of previous insns,
27 each of which contains a SET for a REG that is used in this insn
28 and not used or set in between. LOG_LINKs never cross basic blocks.
29 They were set up by the preceding pass (lifetime analysis).
31 We try to combine each pair of insns joined by a logical link.
32 We also try to combine triples of insns A, B and C when
33 C has a link back to B and B has a link back to A.
35 LOG_LINKS does not have links for use of the CC0. They don't
36 need to, because the insn that sets the CC0 is always immediately
37 before the insn that tests it. So we always regard a branch
38 insn as having a logical link to the preceding insn. The same is true
39 for an insn explicitly using CC0.
41 We check (with use_crosses_set_p) to avoid combining in such a way
42 as to move a computation to a place where its value would be different.
44 Combination is done by mathematically substituting the previous
45 insn(s) values for the regs they set into the expressions in
46 the later insns that refer to these regs. If the result is a valid insn
47 for our target machine, according to the machine description,
48 we install it, delete the earlier insns, and update the data flow
49 information (LOG_LINKS and REG_NOTES) for what we did.
51 There are a few exceptions where the dataflow information created by
52 flow.c aren't completely updated:
54 - reg_live_length is not updated
55 - reg_n_refs is not adjusted in the rare case when a register is
56 no longer required in a computation
57 - there are extremely rare cases (see distribute_regnotes) when a
59 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
60 removed because there is no way to know which register it was
63 To simplify substitution, we combine only when the earlier insn(s)
64 consist of only a single assignment. To simplify updating afterward,
65 we never combine when a subroutine call appears in the middle.
67 Since we do not represent assignments to CC0 explicitly except when that
68 is all an insn does, there is no LOG_LINKS entry in an insn that uses
69 the condition code for the insn that set the condition code.
70 Fortunately, these two insns must be consecutive.
71 Therefore, every JUMP_INSN is taken to have an implicit logical link
72 to the preceding insn. This is not quite right, since non-jumps can
73 also use the condition code; but in practice such insns would not
84 #include "basic-block.h"
85 #include "insn-config.h"
86 #include "insn-flags.h"
87 #include "insn-codes.h"
88 #include "insn-attr.h"
92 /* It is not safe to use ordinary gen_lowpart in combine.
93 Use gen_lowpart_for_combine instead. See comments there. */
94 #define gen_lowpart dont_use_gen_lowpart_you_dummy
96 /* Number of attempts to combine instructions in this function. */
98 static int combine_attempts;
100 /* Number of attempts that got as far as substitution in this function. */
102 static int combine_merges;
104 /* Number of instructions combined with added SETs in this function. */
106 static int combine_extras;
108 /* Number of instructions combined in this function. */
110 static int combine_successes;
112 /* Totals over entire compilation. */
114 static int total_attempts, total_merges, total_extras, total_successes;
116 /* Vector mapping INSN_UIDs to cuids.
117 The cuids are like uids but increase monotonically always.
118 Combine always uses cuids so that it can compare them.
119 But actually renumbering the uids, which we used to do,
120 proves to be a bad idea because it makes it hard to compare
121 the dumps produced by earlier passes with those from later passes. */
123 static int *uid_cuid;
125 /* Get the cuid of an insn. */
127 #define INSN_CUID(INSN) (uid_cuid[INSN_UID (INSN)])
129 /* Maximum register number, which is the size of the tables below. */
131 static int combine_max_regno;
133 /* Record last point of death of (hard or pseudo) register n. */
135 static rtx *reg_last_death;
137 /* Record last point of modification of (hard or pseudo) register n. */
139 static rtx *reg_last_set;
141 /* Record the cuid of the last insn that invalidated memory
142 (anything that writes memory, and subroutine calls, but not pushes). */
144 static int mem_last_set;
146 /* Record the cuid of the last CALL_INSN
147 so we can tell whether a potential combination crosses any calls. */
149 static int last_call_cuid;
151 /* When `subst' is called, this is the insn that is being modified
152 (by combining in a previous insn). The PATTERN of this insn
153 is still the old pattern partially modified and it should not be
154 looked at, but this may be used to examine the successors of the insn
155 to judge whether a simplification is valid. */
157 static rtx subst_insn;
159 /* This is the lowest CUID that `subst' is currently dealing with.
160 get_last_value will not return a value if the register was set at or
161 after this CUID. If not for this mechanism, we could get confused if
162 I2 or I1 in try_combine were an insn that used the old value of a register
163 to obtain a new value. In that case, we might erroneously get the
164 new value of the register when we wanted the old one. */
166 static int subst_low_cuid;
168 /* This is the value of undobuf.num_undo when we started processing this
169 substitution. This will prevent gen_rtx_combine from re-used a piece
170 from the previous expression. Doing so can produce circular rtl
173 static int previous_num_undos;
175 /* The next group of arrays allows the recording of the last value assigned
176 to (hard or pseudo) register n. We use this information to see if a
177 operation being processed is redundant given a prior operation performed
178 on the register. For example, an `and' with a constant is redundant if
179 all the zero bits are already known to be turned off.
181 We use an approach similar to that used by cse, but change it in the
184 (1) We do not want to reinitialize at each label.
185 (2) It is useful, but not critical, to know the actual value assigned
186 to a register. Often just its form is helpful.
188 Therefore, we maintain the following arrays:
190 reg_last_set_value the last value assigned
191 reg_last_set_label records the value of label_tick when the
192 register was assigned
193 reg_last_set_table_tick records the value of label_tick when a
194 value using the register is assigned
195 reg_last_set_invalid set to non-zero when it is not valid
196 to use the value of this register in some
199 To understand the usage of these tables, it is important to understand
200 the distinction between the value in reg_last_set_value being valid
201 and the register being validly contained in some other expression in the
204 Entry I in reg_last_set_value is valid if it is non-zero, and either
205 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
207 Register I may validly appear in any expression returned for the value
208 of another register if reg_n_sets[i] is 1. It may also appear in the
209 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
210 reg_last_set_invalid[j] is zero.
212 If an expression is found in the table containing a register which may
213 not validly appear in an expression, the register is replaced by
214 something that won't match, (clobber (const_int 0)).
216 reg_last_set_invalid[i] is set non-zero when register I is being assigned
217 to and reg_last_set_table_tick[i] == label_tick. */
219 /* Record last value assigned to (hard or pseudo) register n. */
221 static rtx *reg_last_set_value;
223 /* Record the value of label_tick when the value for register n is placed in
224 reg_last_set_value[n]. */
226 static short *reg_last_set_label;
228 /* Record the value of label_tick when an expression involving register n
229 is placed in reg_last_set_value. */
231 static short *reg_last_set_table_tick;
233 /* Set non-zero if references to register n in expressions should not be
236 static char *reg_last_set_invalid;
238 /* Incremented for each label. */
240 static short label_tick;
242 /* Some registers that are set more than once and used in more than one
243 basic block are nevertheless always set in similar ways. For example,
244 a QImode register may be loaded from memory in two places on a machine
245 where byte loads zero extend.
247 We record in the following array what we know about the significant
248 bits of a register, specifically which bits are known to be zero.
250 If an entry is zero, it means that we don't know anything special. */
252 static int *reg_significant;
254 /* Mode used to compute significance in reg_significant. It is the largest
255 integer mode that can fit in HOST_BITS_PER_INT. */
257 static enum machine_mode significant_mode;
259 /* Nonzero when reg_significant can be safely used. It is zero while
260 computing reg_significant. This prevents propagating values based
261 on previously set values, which can be incorrect if a variable
262 is modified in a loop. */
264 static int significant_valid;
266 /* Record one modification to rtl structure
267 to be undone by storing old_contents into *where.
268 is_int is 1 if the contents are an int. */
284 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
285 num_undo says how many are currently recorded.
287 storage is nonzero if we must undo the allocation of new storage.
288 The value of storage is what to pass to obfree.
290 other_insn is nonzero if we have modified some other insn in the process
291 of working on subst_insn. It must be verified too. */
299 struct undo undo[MAX_UNDO];
303 static struct undobuf undobuf;
305 /* Substitute NEWVAL, an rtx expression, into INTO, a place in a some
306 insn. The substitution can be undone by undo_all. If INTO is already
307 set to NEWVAL, do not record this change. */
309 #define SUBST(INTO, NEWVAL) \
310 do { if (undobuf.num_undo < MAX_UNDO) \
312 undobuf.undo[undobuf.num_undo].where = &INTO; \
313 undobuf.undo[undobuf.num_undo].old_contents = INTO; \
314 undobuf.undo[undobuf.num_undo].is_int = 0; \
316 if (undobuf.undo[undobuf.num_undo].old_contents != INTO) \
317 undobuf.num_undo++; \
321 /* Similar to SUBST, but NEWVAL is an int. INTO will normally be an XINT
323 Note that substitution for the value of a CONST_INT is not safe. */
325 #define SUBST_INT(INTO, NEWVAL) \
326 do { if (undobuf.num_undo < MAX_UNDO) \
329 = (struct undo_int *)&undobuf.undo[undobuf.num_undo]; \
330 u->where = (int *) &INTO; \
331 u->old_contents = INTO; \
334 if (u->old_contents != INTO) \
335 undobuf.num_undo++; \
339 /* Number of times the pseudo being substituted for
340 was found and replaced. */
342 static int n_occurrences;
344 static void set_significant ();
345 static void move_deaths ();
347 static void record_value_for_reg ();
348 static void record_dead_and_set_regs ();
349 static int use_crosses_set_p ();
350 static rtx try_combine ();
351 static rtx *find_split_point ();
353 static void undo_all ();
354 static int reg_dead_at_p ();
355 static rtx expand_compound_operation ();
356 static rtx expand_field_assignment ();
357 static rtx make_extraction ();
358 static int get_pos_from_mask ();
359 static rtx make_field_assignment ();
360 static rtx make_compound_operation ();
361 static rtx apply_distributive_law ();
362 static rtx simplify_and_const_int ();
363 static unsigned significant_bits ();
364 static int merge_outer_ops ();
365 static rtx simplify_shift_const ();
366 static int recog_for_combine ();
367 static rtx gen_lowpart_for_combine ();
368 static rtx gen_rtx_combine ();
369 static rtx gen_binary ();
370 static rtx gen_unary ();
371 static enum rtx_code simplify_comparison ();
372 static int reversible_comparison_p ();
373 static int get_last_value_validate ();
374 static rtx get_last_value ();
375 static void distribute_notes ();
376 static void distribute_links ();
378 /* Main entry point for combiner. F is the first insn of the function.
379 NREGS is the first unused pseudo-reg number. */
382 combine_instructions (f, nregs)
386 register rtx insn, next, prev;
388 register rtx links, nextlinks;
390 combine_attempts = 0;
393 combine_successes = 0;
395 combine_max_regno = nregs;
397 reg_last_death = (rtx *) alloca (nregs * sizeof (rtx));
398 reg_last_set = (rtx *) alloca (nregs * sizeof (rtx));
399 reg_last_set_value = (rtx *) alloca (nregs * sizeof (rtx));
400 reg_last_set_table_tick = (short *) alloca (nregs * sizeof (short));
401 reg_last_set_label = (short *) alloca (nregs * sizeof (short));
402 reg_last_set_invalid = (char *) alloca (nregs * sizeof (short));
403 reg_significant = (int *) alloca (nregs * sizeof (int));
405 bzero (reg_last_death, nregs * sizeof (rtx));
406 bzero (reg_last_set, nregs * sizeof (rtx));
407 bzero (reg_last_set_value, nregs * sizeof (rtx));
408 bzero (reg_last_set_table_tick, nregs * sizeof (short));
409 bzero (reg_last_set_invalid, nregs * sizeof (char));
410 bzero (reg_significant, nregs * sizeof (int));
412 init_recog_no_volatile ();
414 /* Compute maximum uid value so uid_cuid can be allocated. */
416 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
417 if (INSN_UID (insn) > i)
420 uid_cuid = (int *) alloca ((i + 1) * sizeof (int));
422 significant_mode = mode_for_size (HOST_BITS_PER_INT, MODE_INT, 0);
424 /* Don't use reg_significant when computing it. This can cause problems
425 when, for example, we have j <<= 1 in a loop. */
427 significant_valid = 0;
429 /* Compute the mapping from uids to cuids.
430 Cuids are numbers assigned to insns, like uids,
431 except that cuids increase monotonically through the code.
433 Scan all SETs and see if we can deduce anything about what
434 bits are significant for some registers. */
436 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
438 INSN_CUID (insn) = ++i;
439 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
440 note_stores (PATTERN (insn), set_significant);
443 significant_valid = 1;
445 /* Now scan all the insns in forward order. */
451 for (insn = f; insn; insn = next ? next : NEXT_INSN (insn))
455 if (GET_CODE (insn) == CODE_LABEL)
458 else if (GET_CODE (insn) == INSN
459 || GET_CODE (insn) == CALL_INSN
460 || GET_CODE (insn) == JUMP_INSN)
462 /* Try this insn with each insn it links back to. */
464 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
465 if ((next = try_combine (insn, XEXP (links, 0), 0)) != 0)
468 /* Try each sequence of three linked insns ending with this one. */
470 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
471 for (nextlinks = LOG_LINKS (XEXP (links, 0)); nextlinks;
472 nextlinks = XEXP (nextlinks, 1))
473 if ((next = try_combine (insn, XEXP (links, 0),
474 XEXP (nextlinks, 0))) != 0)
478 /* Try to combine a jump insn that uses CC0
479 with a preceding insn that sets CC0, and maybe with its
480 logical predecessor as well.
481 This is how we make decrement-and-branch insns.
482 We need this special code because data flow connections
483 via CC0 do not get entered in LOG_LINKS. */
485 if (GET_CODE (insn) == JUMP_INSN
486 && (prev = prev_nonnote_insn (insn)) != 0
487 && GET_CODE (prev) == INSN
488 && sets_cc0_p (PATTERN (prev)))
490 if ((next = try_combine (insn, prev, 0)) != 0)
493 for (nextlinks = LOG_LINKS (prev); nextlinks;
494 nextlinks = XEXP (nextlinks, 1))
495 if ((next = try_combine (insn, prev,
496 XEXP (nextlinks, 0))) != 0)
500 /* Do the same for an insn that explicitly references CC0. */
501 if (GET_CODE (insn) == INSN
502 && (prev = prev_nonnote_insn (insn)) != 0
503 && GET_CODE (prev) == INSN
504 && sets_cc0_p (PATTERN (prev))
505 && GET_CODE (PATTERN (insn)) == SET
506 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
508 if ((next = try_combine (insn, prev, 0)) != 0)
511 for (nextlinks = LOG_LINKS (prev); nextlinks;
512 nextlinks = XEXP (nextlinks, 1))
513 if ((next = try_combine (insn, prev,
514 XEXP (nextlinks, 0))) != 0)
518 /* Finally, see if any of the insns that this insn links to
519 explicitly references CC0. If so, try this insn, that insn,
520 and its predecessor if it sets CC0. */
521 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
522 if (GET_CODE (XEXP (links, 0)) == INSN
523 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
524 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
525 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
526 && GET_CODE (prev) == INSN
527 && sets_cc0_p (PATTERN (prev))
528 && (next = try_combine (insn, XEXP (links, 0), prev)) != 0)
532 /* Try combining an insn with two different insns whose results it
534 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
535 for (nextlinks = XEXP (links, 1); nextlinks;
536 nextlinks = XEXP (nextlinks, 1))
537 if ((next = try_combine (insn, XEXP (links, 0),
538 XEXP (nextlinks, 0))) != 0)
541 if (GET_CODE (insn) != NOTE)
542 record_dead_and_set_regs (insn);
549 total_attempts += combine_attempts;
550 total_merges += combine_merges;
551 total_extras += combine_extras;
552 total_successes += combine_successes;
555 /* Called via note_stores. If X is a pseudo that is used in more than
556 one basic block, is narrower that HOST_BITS_PER_INT, and is being
557 set, record what bits are significant. If we are clobbering X,
558 ignore this "set" because the clobbered value won't be used.
560 If we are setting only a portion of X and we can't figure out what
561 portion, assume all bits will be used since we don't know what will
565 set_significant (x, set)
569 if (GET_CODE (x) == REG
570 && REGNO (x) >= FIRST_PSEUDO_REGISTER
571 && reg_n_sets[REGNO (x)] > 1
572 && reg_basic_block[REGNO (x)] < 0
573 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_INT)
575 if (GET_CODE (set) == CLOBBER)
578 /* If this is a complex assignment, see if we can convert it into a
579 simple assignment. */
580 set = expand_field_assignment (set);
581 if (SET_DEST (set) == x)
582 reg_significant[REGNO (x)]
583 |= significant_bits (SET_SRC (set), significant_mode);
585 reg_significant[REGNO (x)] = GET_MODE_MASK (GET_MODE (x));
589 /* See if INSN can be combined into I3. PRED and SUCC are optionally
590 insns that were previously combined into I3 or that will be combined
591 into the merger of INSN and I3.
593 Return 0 if the combination is not allowed for any reason.
595 If the combination is allowed, *PDEST will be set to the single
596 destination of INSN and *PSRC to the single source, and this function
600 can_combine_p (insn, i3, pred, succ, pdest, psrc)
607 rtx set = 0, src, dest;
609 int all_adjacent = (succ ? (next_active_insn (insn) == succ
610 && next_active_insn (succ) == i3)
611 : next_active_insn (insn) == i3);
613 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
614 or a PARALLEL consisting of such a SET and CLOBBERs.
616 If INSN has CLOBBER parallel parts, ignore them for our processing.
617 By definition, these happen during the execution of the insn. When it
618 is merged with another insn, all bets are off. If they are, in fact,
619 needed and aren't also supplied in I3, they may be added by
620 recog_for_combine. Otherwise, it won't match.
622 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
625 Get the source and destination of INSN. If more than one, can't
628 if (GET_CODE (PATTERN (insn)) == SET)
629 set = PATTERN (insn);
630 else if (GET_CODE (PATTERN (insn)) == PARALLEL
631 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
633 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
635 rtx elt = XVECEXP (PATTERN (insn), 0, i);
637 switch (GET_CODE (elt))
639 /* We can ignore CLOBBERs. */
644 /* Ignore SETs whose result isn't used but not those that
645 have side-effects. */
646 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
647 && ! side_effects_p (elt))
650 /* If we have already found a SET, this is a second one and
651 so we cannot combine with this insn. */
659 /* Anything else means we can't combine. */
665 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
666 so don't do anything with it. */
667 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
676 set = expand_field_assignment (set);
677 src = SET_SRC (set), dest = SET_DEST (set);
679 /* Don't eliminate a store in the stack pointer. */
680 if (dest == stack_pointer_rtx
681 /* Don't install a subreg involving two modes not tieable.
682 It can worsen register allocation, and can even make invalid reload
683 insns, since the reg inside may need to be copied from in the
684 outside mode, and that may be invalid if it is an fp reg copied in
685 integer mode. As a special exception, we can allow this if
686 I3 is simply copying DEST, a REG, to CC0. */
687 || (GET_CODE (src) == SUBREG
688 && ! MODES_TIEABLE_P (GET_MODE (src), GET_MODE (SUBREG_REG (src)))
690 && ! (GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
691 && SET_DEST (PATTERN (i3)) == cc0_rtx
692 && GET_CODE (dest) == REG && dest == SET_SRC (PATTERN (i3)))
695 /* If we couldn't eliminate a field assignment, we can't combine. */
696 || GET_CODE (dest) == ZERO_EXTRACT || GET_CODE (dest) == STRICT_LOW_PART
697 /* Don't combine with an insn that sets a register to itself if it has
698 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
699 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, 0))
700 /* Can't merge a function call. */
701 || GET_CODE (src) == CALL
702 /* Don't substitute into an incremented register. */
703 || FIND_REG_INC_NOTE (i3, dest)
704 || (succ && FIND_REG_INC_NOTE (succ, dest))
705 /* Don't combine the end of a libcall into anything. */
706 || find_reg_note (insn, REG_RETVAL, 0)
707 /* Make sure that DEST is not used after SUCC but before I3. */
708 || (succ && ! all_adjacent
709 && reg_used_between_p (dest, succ, i3))
710 /* Make sure that the value that is to be substituted for the register
711 does not use any registers whose values alter in between. However,
712 If the insns are adjacent, a use can't cross a set even though we
713 think it might (this can happen for a sequence of insns each setting
714 the same destination; reg_last_set of that register might point to
715 a NOTE). Also, don't move a volatile asm across any other insns. */
717 && (use_crosses_set_p (src, INSN_CUID (insn))
718 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))))
719 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
720 better register allocation by not doing the combine. */
721 || find_reg_note (i3, REG_NO_CONFLICT, dest)
722 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
723 /* Don't combine across a CALL_INSN, because that would possibly
724 change whether the life span of some REGs crosses calls or not,
725 and it is a pain to update that information.
726 Exception: if source is a constant, moving it later can't hurt.
727 Accept that special case, because it helps -fforce-addr a lot. */
728 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
731 /* DEST must either be a REG or CC0. */
732 if (GET_CODE (dest) == REG)
734 /* If register alignment is being enforced for multi-word items in all
735 cases except for parameters, it is possible to have a register copy
736 insn referencing a hard register that is not allowed to contain the
737 mode being copied and which would not be valid as an operand of most
738 insns. Eliminate this problem by not combining with such an insn.
740 Also, on some machines we don't want to extend the life of a hard
743 if (GET_CODE (src) == REG
744 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
745 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
746 #ifdef SMALL_REGISTER_CLASSES
747 /* Don't extend the life of a hard register. */
748 || REGNO (src) < FIRST_PSEUDO_REGISTER
750 || (REGNO (src) < FIRST_PSEUDO_REGISTER
751 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))
756 else if (GET_CODE (dest) != CC0)
759 /* Don't substitute for a register intended as a clobberable operand. */
760 if (GET_CODE (PATTERN (i3)) == PARALLEL)
761 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
762 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER
763 && rtx_equal_p (XEXP (XVECEXP (PATTERN (i3), 0, i), 0), dest))
766 /* If INSN contains anything volatile, or is an `asm' (whether volatile
767 or not), reject, unless nothing volatile comes between it and I3,
768 with the exception of SUCC. */
770 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
771 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
772 if (GET_RTX_CLASS (GET_CODE (p)) == 'i'
773 && p != succ && volatile_refs_p (PATTERN (p)))
776 /* If INSN or I2 contains an autoincrement or autodecrement,
777 make sure that register is not used between there and I3,
778 and not already used in I3 either.
779 Also insist that I3 not be a jump; if it were one
780 and the incremented register were spilled, we would lose. */
783 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
784 if (REG_NOTE_KIND (link) == REG_INC
785 && (GET_CODE (i3) == JUMP_INSN
786 || reg_used_between_p (XEXP (link, 0), insn, i3)
787 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
792 /* Don't combine an insn that follows a CC0-setting insn.
793 An insn that uses CC0 must not be separated from the one that sets it.
794 We do, however, allow I2 to follow a CC0-setting insn if that insn
795 is passed as I1; in that case it will be deleted also.
796 We also allow combining in this case if all the insns are adjacent
797 because that would leave the two CC0 insns adjacent as well.
798 It would be more logical to test whether CC0 occurs inside I1 or I2,
799 but that would be much slower, and this ought to be equivalent. */
801 p = prev_nonnote_insn (insn);
802 if (p && p != pred && GET_CODE (p) == INSN && sets_cc0_p (PATTERN (p))
807 /* If we get here, we have passed all the tests and the combination is
816 /* LOC is the location within I3 that contains its pattern or the component
817 of a PARALLEL of the pattern. We validate that it is valid for combining.
819 One problem is if I3 modifies its output, as opposed to replacing it
820 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
821 so would produce an insn that is not equivalent to the original insns.
825 (set (reg:DI 101) (reg:DI 100))
826 (set (subreg:SI (reg:DI 101) 0) <foo>)
828 This is NOT equivalent to:
830 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
831 (set (reg:DI 101) (reg:DI 100))])
833 Not only does this modify 100 (in which case it might still be valid
834 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
836 We can also run into a problem if I2 sets a register that I1
837 uses and I1 gets directly substituted into I3 (not via I2). In that
838 case, we would be getting the wrong value of I2DEST into I3, so we
839 must reject the combination. This case occurs when I2 and I1 both
840 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
841 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
842 of a SET must prevent combination from occurring.
844 On machines where SMALL_REGISTER_CLASSES is defined, we don't combine
845 if the destination of a SET is a hard register.
847 Before doing the above check, we first try to expand a field assignment
848 into a set of logical operations.
850 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
851 we place a register that is both set and used within I3. If more than one
852 such register is detected, we fail.
854 Return 1 if the combination is valid, zero otherwise. */
857 combinable_i3pat (i3, loc, i2dest, i1dest, i1_not_in_src, pi3dest_killed)
867 if (GET_CODE (x) == SET)
869 rtx set = expand_field_assignment (x);
870 rtx dest = SET_DEST (set);
871 rtx src = SET_SRC (set);
872 rtx inner_dest = dest, inner_src = src;
876 while (GET_CODE (inner_dest) == STRICT_LOW_PART
877 || GET_CODE (inner_dest) == SUBREG
878 || GET_CODE (inner_dest) == ZERO_EXTRACT)
879 inner_dest = XEXP (inner_dest, 0);
881 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
884 while (GET_CODE (inner_src) == STRICT_LOW_PART
885 || GET_CODE (inner_src) == SUBREG
886 || GET_CODE (inner_src) == ZERO_EXTRACT)
887 inner_src = XEXP (inner_src, 0);
889 /* If it is better that two different modes keep two different pseudos,
890 avoid combining them. This avoids producing the following pattern
892 (set (subreg:SI (reg/v:QI 21) 0)
893 (lshiftrt:SI (reg/v:SI 20)
895 If that were made, reload could not handle the pair of
896 reg 20/21, since it would try to get any GENERAL_REGS
897 but some of them don't handle QImode. */
899 if (rtx_equal_p (inner_src, i2dest)
900 && GET_CODE (inner_dest) == REG
901 && ! MODES_TIEABLE_P (GET_MODE (i2dest), GET_MODE (inner_dest)))
905 /* Check for the case where I3 modifies its output, as
907 if ((inner_dest != dest
908 && (reg_overlap_mentioned_p (i2dest, inner_dest)
909 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
910 /* This is the same test done in can_combine_p. */
911 || (GET_CODE (inner_dest) == REG
912 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
913 #ifndef SMALL_REGISTER_CLASSES
914 && ! HARD_REGNO_MODE_OK (REGNO (inner_dest),
915 GET_MODE (inner_dest))
919 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
922 /* If DEST is used in I3, it is being killed in this insn,
923 so record that for later. */
924 if (pi3dest_killed && GET_CODE (dest) == REG
925 && reg_referenced_p (dest, PATTERN (i3)))
930 *pi3dest_killed = dest;
934 else if (GET_CODE (x) == PARALLEL)
938 for (i = 0; i < XVECLEN (x, 0); i++)
939 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
940 i1_not_in_src, pi3dest_killed))
947 /* Try to combine the insns I1 and I2 into I3.
948 Here I1 and I2 appear earlier than I3.
949 I1 can be zero; then we combine just I2 into I3.
951 It we are combining three insns and the resulting insn is not recognized,
952 try splitting it into two insns. If that happens, I2 and I3 are retained
953 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
956 If we created two insns, return I2; otherwise return I3.
957 Return 0 if the combination does not work. Then nothing is changed. */
960 try_combine (i3, i2, i1)
961 register rtx i3, i2, i1;
963 /* New patterns for I3 and I3, respectively. */
964 rtx newpat, newi2pat = 0;
965 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
966 int added_sets_1, added_sets_2;
967 /* Total number of SETs to put into I3. */
969 /* Nonzero is I2's body now appears in I3. */
971 /* INSN_CODEs for new I3, new I2, and user of condition code. */
972 int insn_code_number, i2_code_number, other_code_number;
973 /* Contains I3 if the destination of I3 is used in its source, which means
974 that the old life of I3 is being killed. If that usage is placed into
975 I2 and not in I3, a REG_DEAD note must be made. */
976 rtx i3dest_killed = 0;
977 /* SET_DEST and SET_SRC of I2 and I1. */
978 rtx i2dest, i2src, i1dest = 0, i1src = 0;
979 /* PATTERN (I2), or a copy of it in certain cases. */
981 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
982 int i2dest_in_i2src, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
984 /* Notes that must be added to REG_NOTES in I3 and I2. */
985 rtx new_i3_notes, new_i2_notes;
992 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
993 This can occur when flow deletes an insn that it has merged into an
994 auto-increment address. We also can't do anything if I3 has a
995 REG_LIBCALL note since we don't want to disrupt the contiguity of a
998 if (GET_RTX_CLASS (GET_CODE (i3)) != 'i'
999 || GET_RTX_CLASS (GET_CODE (i2)) != 'i'
1000 || (i1 && GET_RTX_CLASS (GET_CODE (i1)) != 'i')
1001 || find_reg_note (i3, REG_LIBCALL, 0))
1006 undobuf.num_undo = previous_num_undos = 0;
1007 undobuf.other_insn = 0;
1009 /* Save the current high-water-mark so we can free storage if we didn't
1010 accept this combination. */
1011 undobuf.storage = (char *) oballoc (0);
1013 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1014 code below, set I1 to be the earlier of the two insns. */
1015 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1016 temp = i1, i1 = i2, i2 = temp;
1018 /* First check for one important special-case that the code below will
1019 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1020 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1021 we may be able to replace that destination with the destination of I3.
1022 This occurs in the common code where we compute both a quotient and
1023 remainder into a structure, in which case we want to do the computation
1024 directly into the structure to avoid register-register copies.
1026 We make very conservative checks below and only try to handle the
1027 most common cases of this. For example, we only handle the case
1028 where I2 and I3 are adjacent to avoid making difficult register
1031 if (i1 == 0 && GET_CODE (i3) == INSN && GET_CODE (PATTERN (i3)) == SET
1032 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1033 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1034 #ifdef SMALL_REGISTER_CLASSES
1035 && (GET_CODE (SET_DEST (PATTERN (i3))) != REG
1036 || REGNO (SET_DEST (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER)
1038 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1039 && GET_CODE (PATTERN (i2)) == PARALLEL
1040 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1041 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1042 below would need to check what is inside (and reg_overlap_mentioned_p
1043 doesn't support those codes anyway). Don't allow those destinations;
1044 the resulting insn isn't likely to be recognized anyway. */
1045 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1046 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1047 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1048 SET_DEST (PATTERN (i3)))
1049 && next_real_insn (i2) == i3)
1051 rtx p2 = PATTERN (i2);
1053 /* Make sure that the destination of I3,
1054 which we are going to substitute into one output of I2,
1055 is not used within another output of I2. We must avoid making this:
1056 (parallel [(set (mem (reg 69)) ...)
1057 (set (reg 69) ...)])
1058 which is not well-defined as to order of actions.
1059 (Besides, reload can't handle output reloads for this.)
1061 The problem can also happen if the dest of I3 is a memory ref,
1062 if another dest in I2 is an indirect memory ref. */
1063 for (i = 0; i < XVECLEN (p2, 0); i++)
1064 if (GET_CODE (XVECEXP (p2, 0, i)) == SET
1065 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1066 SET_DEST (XVECEXP (p2, 0, i))))
1069 if (i == XVECLEN (p2, 0))
1070 for (i = 0; i < XVECLEN (p2, 0); i++)
1071 if (SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1076 subst_low_cuid = INSN_CUID (i2);
1079 i2dest = SET_SRC (PATTERN (i3));
1081 /* Replace the dest in I2 with our dest and make the resulting
1082 insn the new pattern for I3. Then skip to where we
1083 validate the pattern. Everything was set up above. */
1084 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1085 SET_DEST (PATTERN (i3)));
1088 goto validate_replacement;
1093 /* If we have no I1 and I2 looks like:
1094 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1096 make up a dummy I1 that is
1099 (set (reg:CC X) (compare:CC Y (const_int 0)))
1101 (We can ignore any trailing CLOBBERs.)
1103 This undoes a previous combination and allows us to match a branch-and-
1106 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1107 && XVECLEN (PATTERN (i2), 0) >= 2
1108 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1109 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1111 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1112 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1113 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1114 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 1))) == REG
1115 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1116 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1118 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1119 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1124 /* We make I1 with the same INSN_UID as I2. This gives it
1125 the same INSN_CUID for value tracking. Our fake I1 will
1126 never appear in the insn stream so giving it the same INSN_UID
1127 as I2 will not cause a problem. */
1129 i1 = gen_rtx (INSN, VOIDmode, INSN_UID (i2), 0, i2,
1130 XVECEXP (PATTERN (i2), 0, 1), -1, 0, 0);
1132 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1133 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1134 SET_DEST (PATTERN (i1)));
1139 /* Verify that I2 and I1 are valid for combining. */
1140 if (! can_combine_p (i2, i3, i1, 0, &i2dest, &i2src)
1141 || (i1 && ! can_combine_p (i1, i3, 0, i2, &i1dest, &i1src)))
1147 /* Record whether I2DEST is used in I2SRC and similarly for the other
1148 cases. Knowing this will help in register status updating below. */
1149 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1150 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1151 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1153 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1155 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1157 /* Ensure that I3's pattern can be the destination of combines. */
1158 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1159 i1 && i2dest_in_i1src && i1_feeds_i3,
1166 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1167 We used to do this EXCEPT in one case: I3 has a post-inc in an
1168 output operand. However, that exception can give rise to insns like
1170 which is a famous insn on the PDP-11 where the value of r3 used as the
1171 source was model-dependent. Avoid this sort of thing. */
1174 if (!(GET_CODE (PATTERN (i3)) == SET
1175 && GET_CODE (SET_SRC (PATTERN (i3))) == REG
1176 && GET_CODE (SET_DEST (PATTERN (i3))) == MEM
1177 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1178 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1179 /* It's not the exception. */
1182 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1183 if (REG_NOTE_KIND (link) == REG_INC
1184 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1186 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1193 /* See if the SETs in I1 or I2 need to be kept around in the merged
1194 instruction: whenever the value set there is still needed past I3.
1195 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1197 For the SET in I1, we have two cases: If I1 and I2 independently
1198 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1199 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1200 in I1 needs to be kept around unless I1DEST dies or is set in either
1201 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1202 I1DEST. If so, we know I1 feeds into I2. */
1204 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1207 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1208 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1210 /* If the set in I2 needs to be kept around, we must make a copy of
1211 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1212 PATTERN (I2), we are only substituting for the original I1DEST, not into
1213 an already-substituted copy. This also prevents making self-referential
1214 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1217 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1218 ? gen_rtx (SET, VOIDmode, i2dest, i2src)
1222 i2pat = copy_rtx (i2pat);
1226 /* Substitute in the latest insn for the regs set by the earlier ones. */
1228 maxreg = max_reg_num ();
1231 subst_low_cuid = i1 ? INSN_CUID (i1) : INSN_CUID (i2);
1233 /* It is possible that the source of I2 or I1 may be performing an
1234 unneeded operation, such as a ZERO_EXTEND of something that is known
1235 to have the high part zero. Handle that case by letting subst look at
1236 the innermost one of them.
1238 Another way to do this would be to have a function that tries to
1239 simplify a single insn instead of merging two or more insns. We don't
1240 do this because of the potential of infinite loops and because
1241 of the potential extra memory required. However, doing it the way
1242 we are is a bit of a kludge and doesn't catch all cases.
1244 But only do this if -fexpensive-optimizations since it slows things down
1245 and doesn't usually win. */
1247 if (flag_expensive_optimizations)
1249 /* Pass pc_rtx so no substitutions are done, just simplifications.
1250 The cases that we are interested in here do not involve the few
1251 cases were is_replaced is checked. */
1253 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1255 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1257 previous_num_undos = undobuf.num_undo;
1261 /* Many machines that don't use CC0 have insns that can both perform an
1262 arithmetic operation and set the condition code. These operations will
1263 be represented as a PARALLEL with the first element of the vector
1264 being a COMPARE of an arithmetic operation with the constant zero.
1265 The second element of the vector will set some pseudo to the result
1266 of the same arithmetic operation. If we simplify the COMPARE, we won't
1267 match such a pattern and so will generate an extra insn. Here we test
1268 for this case, where both the comparison and the operation result are
1269 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1270 I2SRC. Later we will make the PARALLEL that contains I2. */
1272 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1273 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1274 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1275 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1278 enum machine_mode compare_mode;
1280 newpat = PATTERN (i3);
1281 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1285 #ifdef EXTRA_CC_MODES
1286 /* See if a COMPARE with the operand we substituted in should be done
1287 with the mode that is currently being used. If not, do the same
1288 processing we do in `subst' for a SET; namely, if the destination
1289 is used only once, try to replace it with a register of the proper
1290 mode and also replace the COMPARE. */
1291 if (undobuf.other_insn == 0
1292 && (cc_use = find_single_use (SET_DEST (newpat), i3,
1293 &undobuf.other_insn))
1294 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use), i2src))
1295 != GET_MODE (SET_DEST (newpat))))
1297 int regno = REGNO (SET_DEST (newpat));
1298 rtx new_dest = gen_rtx (REG, compare_mode, regno);
1300 if (regno < FIRST_PSEUDO_REGISTER
1301 || (reg_n_sets[regno] == 1 && ! added_sets_2
1302 && ! REG_USERVAR_P (SET_DEST (newpat))))
1304 if (regno >= FIRST_PSEUDO_REGISTER)
1305 SUBST (regno_reg_rtx[regno], new_dest);
1307 SUBST (SET_DEST (newpat), new_dest);
1308 SUBST (XEXP (*cc_use, 0), new_dest);
1309 SUBST (SET_SRC (newpat),
1310 gen_rtx_combine (COMPARE, compare_mode,
1311 i2src, const0_rtx));
1314 undobuf.other_insn = 0;
1321 n_occurrences = 0; /* `subst' counts here */
1323 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1324 need to make a unique copy of I2SRC each time we substitute it
1325 to avoid self-referential rtl. */
1327 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
1328 ! i1_feeds_i3 && i1dest_in_i1src);
1329 previous_num_undos = undobuf.num_undo;
1331 /* Record whether i2's body now appears within i3's body. */
1332 i2_is_used = n_occurrences;
1335 /* If we already got a failure, don't try to do more. Otherwise,
1336 try to substitute in I1 if we have it. */
1338 if (i1 && GET_CODE (newpat) != CLOBBER)
1340 /* Before we can do this substitution, we must redo the test done
1341 above (see detailed comments there) that ensures that I1DEST
1342 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1344 if (! combinable_i3pat (0, &newpat, i1dest, 0, 0, 0))
1351 newpat = subst (newpat, i1dest, i1src, 0, 0);
1352 previous_num_undos = undobuf.num_undo;
1355 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1356 to count all the ways that I2SRC and I1SRC can be used. */
1357 if ((FIND_REG_INC_NOTE (i2, 0) != 0
1358 && i2_is_used + added_sets_2 > 1)
1359 || (i1 != 0 && FIND_REG_INC_NOTE (i1, 0) != 0
1360 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
1362 /* Fail if we tried to make a new register (we used to abort, but there's
1363 really no reason to). */
1364 || max_reg_num () != maxreg
1365 /* Fail if we couldn't do something and have a CLOBBER. */
1366 || GET_CODE (newpat) == CLOBBER)
1372 /* If the actions of the earlier insns must be kept
1373 in addition to substituting them into the latest one,
1374 we must make a new PARALLEL for the latest insn
1375 to hold additional the SETs. */
1377 if (added_sets_1 || added_sets_2)
1381 if (GET_CODE (newpat) == PARALLEL)
1383 rtvec old = XVEC (newpat, 0);
1384 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
1385 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1386 bcopy (&old->elem[0], &XVECEXP (newpat, 0, 0),
1387 sizeof (old->elem[0]) * old->num_elem);
1392 total_sets = 1 + added_sets_1 + added_sets_2;
1393 newpat = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (total_sets));
1394 XVECEXP (newpat, 0, 0) = old;
1398 XVECEXP (newpat, 0, --total_sets)
1399 = (GET_CODE (PATTERN (i1)) == PARALLEL
1400 ? gen_rtx (SET, VOIDmode, i1dest, i1src) : PATTERN (i1));
1404 /* If there is no I1, use I2's body as is. We used to also not do
1405 the subst call below if I2 was substituted into I3,
1406 but that could lose a simplification. */
1408 XVECEXP (newpat, 0, --total_sets) = i2pat;
1410 /* See comment where i2pat is assigned. */
1411 XVECEXP (newpat, 0, --total_sets)
1412 = subst (i2pat, i1dest, i1src, 0, 0);
1416 /* We come here when we are replacing a destination in I2 with the
1417 destination of I3. */
1418 validate_replacement:
1420 /* Is the result of combination a valid instruction? */
1421 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1423 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
1424 the second SET's destination is a register that is unused. In that case,
1425 we just need the first SET. This can occur when simplifying a divmod
1426 insn. We *must* test for this case here because the code below that
1427 splits two independent SETs doesn't handle this case correctly when it
1428 updates the register status. Also check the case where the first
1429 SET's destination is unused. That would not cause incorrect code, but
1430 does cause an unneeded insn to remain. */
1432 if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1433 && XVECLEN (newpat, 0) == 2
1434 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1435 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1436 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == REG
1437 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 1)))
1438 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 1)))
1439 && asm_noperands (newpat) < 0)
1441 newpat = XVECEXP (newpat, 0, 0);
1442 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1445 else if (insn_code_number < 0 && GET_CODE (newpat) == PARALLEL
1446 && XVECLEN (newpat, 0) == 2
1447 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1448 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1449 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) == REG
1450 && find_reg_note (i3, REG_UNUSED, SET_DEST (XVECEXP (newpat, 0, 0)))
1451 && ! side_effects_p (SET_SRC (XVECEXP (newpat, 0, 0)))
1452 && asm_noperands (newpat) < 0)
1454 newpat = XVECEXP (newpat, 0, 1);
1455 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1458 /* If we were combining three insns and the result is a simple SET
1459 with no ASM_OPERANDS that wasn't recognized, try to split it into two
1460 insns. There are two ways to do this. It can be split using a
1461 machine-specific method (like when you have an addition of a large
1462 constant) or by combine in the function find_split_point. */
1464 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
1465 && asm_noperands (newpat) < 0)
1467 rtx m_split, *split;
1469 /* See if the MD file can split NEWPAT. If it can't, see if letting it
1470 use I2DEST as a scratch register will help. */
1472 m_split = split_insns (newpat, i3);
1474 m_split = split_insns (gen_rtx (PARALLEL, VOIDmode,
1475 gen_rtvec (2, newpat,
1476 gen_rtx (CLOBBER, VOIDmode,
1480 if (m_split && GET_CODE (m_split) == SEQUENCE
1481 && XVECLEN (m_split, 0) == 2)
1483 newi2pat = PATTERN (XVECEXP (m_split, 0, 0));
1484 newpat = PATTERN (XVECEXP (m_split, 0, 1));
1486 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1487 if (i2_code_number >= 0)
1488 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1491 /* If we can split it and use I2DEST, go ahead and see if that
1492 helps things be recognized. Verify that none of the registers
1493 are set between I2 and I3. */
1494 else if ((split = find_split_point (&newpat)) != 0
1496 && GET_CODE (i2dest) == REG
1498 /* We need I2DEST in the proper mode. If it is a hard register
1499 or the only use of a pseudo, we can change its mode. */
1500 && (GET_MODE (*split) == GET_MODE (i2dest)
1501 || GET_MODE (*split) == VOIDmode
1502 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
1503 || (reg_n_sets[REGNO (i2dest)] == 1 && ! added_sets_2
1504 && ! REG_USERVAR_P (i2dest)))
1505 && (next_real_insn (i2) == i3
1506 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
1507 /* We can't overwrite I2DEST if its value is still used by
1509 && ! reg_referenced_p (i2dest, newpat))
1511 rtx newdest = i2dest;
1513 /* Get NEWDEST as a register in the proper mode. We have already
1514 validated that we can do this. */
1515 if (GET_MODE (i2dest) != GET_MODE (*split)
1516 && GET_MODE (*split) != VOIDmode)
1518 newdest = gen_rtx (REG, GET_MODE (*split), REGNO (i2dest));
1520 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
1521 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
1524 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
1525 an ASHIFT. This can occur if it was inside a PLUS and hence
1526 appeared to be a memory address. This is a kludge. */
1527 if (GET_CODE (*split) == MULT
1528 && GET_CODE (XEXP (*split, 1)) == CONST_INT
1529 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
1530 SUBST (*split, gen_rtx_combine (ASHIFT, GET_MODE (*split),
1532 gen_rtx (CONST_INT, VOIDmode, i)));
1534 #ifdef INSN_SCHEDULING
1535 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
1536 be written as a ZERO_EXTEND. */
1537 if (GET_CODE (*split) == SUBREG
1538 && GET_CODE (SUBREG_REG (*split)) == MEM)
1539 SUBST (*split, gen_rtx_combine (ZERO_EXTEND, GET_MODE (*split),
1543 newi2pat = gen_rtx_combine (SET, VOIDmode, newdest, *split);
1544 SUBST (*split, newdest);
1545 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1546 if (i2_code_number >= 0)
1547 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1551 /* Check for a case where we loaded from memory in a narrow mode and
1552 then sign extended it, but we need both registers. In that case,
1553 we have a PARALLEL with both loads from the same memory location.
1554 We can split this into a load from memory followed by a register-register
1555 copy. This saves at least one insn, more if register allocation can
1556 eliminate the copy. */
1558 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1559 && GET_CODE (newpat) == PARALLEL
1560 && XVECLEN (newpat, 0) == 2
1561 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1562 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
1563 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1564 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1565 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
1566 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1568 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1569 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1570 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1571 SET_SRC (XVECEXP (newpat, 0, 1)))
1572 && ! find_reg_note (i3, REG_UNUSED,
1573 SET_DEST (XVECEXP (newpat, 0, 0))))
1575 newi2pat = XVECEXP (newpat, 0, 0);
1576 newpat = XVECEXP (newpat, 0, 1);
1577 SUBST (SET_SRC (newpat),
1578 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat)),
1579 SET_DEST (newi2pat)));
1580 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1581 if (i2_code_number >= 0)
1582 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1584 if (insn_code_number >= 0)
1589 /* If we will be able to accept this, we have made a change to the
1590 destination of I3. This can invalidate a LOG_LINKS pointing
1591 to I3. No other part of combine.c makes such a transformation.
1593 The new I3 will have a destination that was previously the
1594 destination of I1 or I2 and which was used in i2 or I3. Call
1595 distribute_links to make a LOG_LINK from the next use of
1596 that destination. */
1598 PATTERN (i3) = newpat;
1599 distribute_links (gen_rtx (INSN_LIST, VOIDmode, i3, 0));
1601 /* I3 now uses what used to be its destination and which is
1602 now I2's destination. That means we need a LOG_LINK from
1603 I3 to I2. But we used to have one, so we still will.
1605 However, some later insn might be using I2's dest and have
1606 a LOG_LINK pointing at I3. We must remove this link.
1607 The simplest way to remove the link is to point it at I1,
1608 which we know will be a NOTE. */
1610 for (insn = NEXT_INSN (i3);
1611 insn && GET_CODE (insn) != CODE_LABEL
1612 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN;
1613 insn = NEXT_INSN (insn))
1615 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
1616 && reg_referenced_p (SET_DEST (newi2pat), PATTERN (insn)))
1618 for (link = LOG_LINKS (insn); link;
1619 link = XEXP (link, 1))
1620 if (XEXP (link, 0) == i3)
1621 XEXP (link, 0) = i1;
1629 /* Similarly, check for a case where we have a PARALLEL of two independent
1630 SETs but we started with three insns. In this case, we can do the sets
1631 as two separate insns. This case occurs when some SET allows two
1632 other insns to combine, but the destination of that SET is still live. */
1634 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
1635 && GET_CODE (newpat) == PARALLEL
1636 && XVECLEN (newpat, 0) == 2
1637 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
1638 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
1639 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
1640 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
1641 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
1642 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
1643 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
1645 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
1646 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
1647 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
1648 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
1649 XVECEXP (newpat, 0, 0))
1650 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
1651 XVECEXP (newpat, 0, 1)))
1653 newi2pat = XVECEXP (newpat, 0, 1);
1654 newpat = XVECEXP (newpat, 0, 0);
1656 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
1657 if (i2_code_number >= 0)
1658 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
1661 /* If it still isn't recognized, fail and change things back the way they
1663 if ((insn_code_number < 0
1664 /* Is the result a reasonable ASM_OPERANDS? */
1665 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
1671 /* If we had to change another insn, make sure it is valid also. */
1672 if (undobuf.other_insn)
1674 rtx other_notes = REG_NOTES (undobuf.other_insn);
1675 rtx other_pat = PATTERN (undobuf.other_insn);
1676 rtx new_other_notes;
1679 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
1682 if (other_code_number < 0 && ! check_asm_operands (other_pat))
1688 PATTERN (undobuf.other_insn) = other_pat;
1690 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
1691 are still valid. Then add any non-duplicate notes added by
1692 recog_for_combine. */
1693 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
1695 next = XEXP (note, 1);
1697 if (REG_NOTE_KIND (note) == REG_UNUSED
1698 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
1699 remove_note (undobuf.other_insn, note);
1702 distribute_notes (new_other_notes, undobuf.other_insn,
1703 undobuf.other_insn, 0, 0, 0);
1706 /* We now know that we can do this combination. Merge the insns and
1707 update the status of registers and LOG_LINKS. */
1710 rtx i3notes, i2notes, i1notes = 0;
1711 rtx i3links, i2links, i1links = 0;
1713 int all_adjacent = (next_real_insn (i2) == i3
1714 && (i1 == 0 || next_real_insn (i1) == i2));
1716 /* Compute which registers we expect to eliminate. */
1717 rtx elim_i2 = (newi2pat || i2dest_in_i2src || i2dest_in_i1src
1719 rtx elim_i1 = i1 == 0 || i1dest_in_i1src ? 0 : i1dest;
1721 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
1723 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
1724 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
1726 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
1728 /* Ensure that we do not have something that should not be shared but
1729 occurs multiple times in the new insns. Check this by first
1730 resetting all the `used' flags and then copying anything is shared. */
1732 reset_used_flags (i3notes);
1733 reset_used_flags (i2notes);
1734 reset_used_flags (i1notes);
1735 reset_used_flags (newpat);
1736 reset_used_flags (newi2pat);
1737 if (undobuf.other_insn)
1738 reset_used_flags (PATTERN (undobuf.other_insn));
1740 i3notes = copy_rtx_if_shared (i3notes);
1741 i2notes = copy_rtx_if_shared (i2notes);
1742 i1notes = copy_rtx_if_shared (i1notes);
1743 newpat = copy_rtx_if_shared (newpat);
1744 newi2pat = copy_rtx_if_shared (newi2pat);
1745 if (undobuf.other_insn)
1746 reset_used_flags (PATTERN (undobuf.other_insn));
1748 INSN_CODE (i3) = insn_code_number;
1749 PATTERN (i3) = newpat;
1750 if (undobuf.other_insn)
1751 INSN_CODE (undobuf.other_insn) = other_code_number;
1753 /* We had one special case above where I2 had more than one set and
1754 we replaced a destination of one of those sets with the destination
1755 of I3. In that case, we have to update LOG_LINKS of insns later
1756 in this basic block. Note that this (expensive) case is rare. */
1758 if (GET_CODE (PATTERN (i2)) == PARALLEL)
1759 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
1760 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2), 0, i))) == REG
1761 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
1762 && ! find_reg_note (i2, REG_UNUSED,
1763 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
1767 for (insn = NEXT_INSN (i2); insn; insn = NEXT_INSN (insn))
1769 if (insn != i3 && GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1770 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1771 if (XEXP (link, 0) == i2)
1772 XEXP (link, 0) = i3;
1774 if (GET_CODE (insn) == CODE_LABEL
1775 || GET_CODE (insn) == JUMP_INSN)
1787 INSN_CODE (i2) = i2_code_number;
1788 PATTERN (i2) = newi2pat;
1792 PUT_CODE (i2, NOTE);
1793 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
1794 NOTE_SOURCE_FILE (i2) = 0;
1801 PUT_CODE (i1, NOTE);
1802 NOTE_LINE_NUMBER (i1) = NOTE_INSN_DELETED;
1803 NOTE_SOURCE_FILE (i1) = 0;
1806 /* Get death notes for everything that is now used in either I3 or
1807 I2 and used to die in a previous insn. */
1809 move_deaths (newpat, i1 ? INSN_CUID (i1) : INSN_CUID (i2), i3, &midnotes);
1811 move_deaths (newi2pat, INSN_CUID (i1), i2, &midnotes);
1813 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
1815 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1817 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1819 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1821 distribute_notes (midnotes, 0, i3, newi2pat ? i2 : 0, elim_i2, elim_i1);
1823 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
1824 know these are REG_UNUSED and want them to go to the desired insn,
1825 so we always pass it as i3. */
1826 if (newi2pat && new_i2_notes)
1827 distribute_notes (new_i2_notes, i2, i2, 0, 0, 0);
1829 distribute_notes (new_i3_notes, i3, i3, 0, 0, 0);
1831 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
1832 put a REG_DEAD note for it somewhere. Similarly for I2 and I1. */
1834 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i3dest_killed, 0),
1835 0, i3, newi2pat ? i2 : 0, 0, 0);
1836 if (i2dest_in_i2src)
1837 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i2dest, 0),
1838 0, i3, newi2pat ? i2 : 0, 0, 0);
1839 if (i1dest_in_i1src)
1840 distribute_notes (gen_rtx (EXPR_LIST, REG_DEAD, i1dest, 0),
1841 0, i3, newi2pat ? i2 : 0, 0, 0);
1843 distribute_links (i3links);
1844 distribute_links (i2links);
1845 distribute_links (i1links);
1847 if (GET_CODE (i2dest) == REG)
1849 /* The insn that previously set this register doesn't exist, and
1850 this life of the register may not exist either. Show that
1851 we don't know its value any more. If we don't do this and
1852 I2 set the register to a value that depended on its old
1853 contents, we will get confused. If this insn is used, thing
1854 will be set correctly in combine_instructions. */
1855 record_value_for_reg (i2dest, 0, 0);
1857 /* If the reg formerly set in I2 died only once and that was in I3,
1858 zero its use count so it won't make `reload' do any work. */
1859 if (! added_sets_2 && newi2pat == 0)
1861 regno = REGNO (i2dest);
1862 reg_n_sets[regno]--;
1863 if (reg_n_sets[regno] == 0
1864 && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1865 & (1 << (regno % HOST_BITS_PER_INT))))
1866 reg_n_refs[regno] = 0;
1870 if (i1 && GET_CODE (i1dest) == REG)
1872 record_value_for_reg (i1dest, 0, 0);
1873 regno = REGNO (i1dest);
1876 reg_n_sets[regno]--;
1877 if (reg_n_sets[regno] == 0
1878 && ! (basic_block_live_at_start[0][regno / HOST_BITS_PER_INT]
1879 & (1 << (regno % HOST_BITS_PER_INT))))
1880 reg_n_refs[regno] = 0;
1884 /* If I3 is now an unconditional jump, ensure that it has a
1885 BARRIER following it since it may have initially been a
1886 conditional jump. */
1888 if ((GET_CODE (newpat) == RETURN || simplejump_p (i3))
1889 && GET_CODE (next_nonnote_insn (i3)) != BARRIER)
1890 emit_barrier_after (i3);
1893 combine_successes++;
1895 return newi2pat ? i2 : i3;
1898 /* Undo all the modifications recorded in undobuf. */
1904 if (undobuf.num_undo > MAX_UNDO)
1905 undobuf.num_undo = MAX_UNDO;
1906 for (i = undobuf.num_undo - 1; i >= 0; i--)
1907 *undobuf.undo[i].where = undobuf.undo[i].old_contents;
1909 obfree (undobuf.storage);
1910 undobuf.num_undo = 0;
1913 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
1914 where we have an arithmetic expression and return that point.
1916 try_combine will call this function to see if an insn can be split into
1920 find_split_point (loc)
1924 enum rtx_code code = GET_CODE (x);
1926 int len = 0, pos, unsignedp;
1929 /* First special-case some codes. */
1933 #ifdef INSN_SCHEDULING
1934 /* If we are making a paradoxical SUBREG invalid, it becomes a split
1936 if (GET_CODE (SUBREG_REG (x)) == MEM)
1939 return find_split_point (&SUBREG_REG (x));
1943 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
1944 using LO_SUM and HIGH. */
1945 if (GET_CODE (XEXP (x, 0)) == CONST
1946 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1949 gen_rtx_combine (LO_SUM, Pmode,
1950 gen_rtx_combine (HIGH, Pmode, XEXP (x, 0)),
1952 return &XEXP (XEXP (x, 0), 0);
1956 /* If we have a PLUS whose second operand is a constant and the
1957 address is not valid, perhaps will can split it up using
1958 the machine-specific way to split large constants. We use
1959 the first psuedo-reg (one of the virtual regs) as a placeholder;
1960 it will not remain in the result. */
1961 if (GET_CODE (XEXP (x, 0)) == PLUS
1962 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1963 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
1965 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
1966 rtx seq = split_insns (gen_rtx (SET, VOIDmode, reg, XEXP (x, 0)),
1969 /* This should have produced two insns, each of which sets our
1970 placeholder. If the source of the second is a valid address,
1971 we can make put both sources together and make a split point
1974 if (seq && XVECLEN (seq, 0) == 2
1975 && GET_CODE (XVECEXP (seq, 0, 0)) == INSN
1976 && GET_CODE (PATTERN (XVECEXP (seq, 0, 0))) == SET
1977 && SET_DEST (PATTERN (XVECEXP (seq, 0, 0))) == reg
1978 && ! reg_mentioned_p (reg,
1979 SET_SRC (PATTERN (XVECEXP (seq, 0, 0))))
1980 && GET_CODE (XVECEXP (seq, 0, 1)) == INSN
1981 && GET_CODE (PATTERN (XVECEXP (seq, 0, 1))) == SET
1982 && SET_DEST (PATTERN (XVECEXP (seq, 0, 1))) == reg
1983 && memory_address_p (GET_MODE (x),
1984 SET_SRC (PATTERN (XVECEXP (seq, 0, 1)))))
1986 rtx src1 = SET_SRC (PATTERN (XVECEXP (seq, 0, 0)));
1987 rtx src2 = SET_SRC (PATTERN (XVECEXP (seq, 0, 1)));
1989 /* Replace the placeholder in SRC2 with SRC1. If we can
1990 find where in SRC2 it was placed, that can become our
1991 split point and we can replace this address with SRC2.
1992 Just try two obvious places. */
1994 src2 = replace_rtx (src2, reg, src1);
1996 if (XEXP (src2, 0) == src1)
1997 split = &XEXP (src2, 0);
1998 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
1999 && XEXP (XEXP (src2, 0), 0) == src1)
2000 split = &XEXP (XEXP (src2, 0), 0);
2004 SUBST (XEXP (x, 0), src2);
2013 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2014 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2015 we need to put the operand into a register. So split at that
2018 if (SET_DEST (x) == cc0_rtx
2019 && GET_CODE (SET_SRC (x)) != COMPARE
2020 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
2021 && GET_RTX_CLASS (GET_CODE (SET_SRC (x))) != 'o'
2022 && ! (GET_CODE (SET_SRC (x)) == SUBREG
2023 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) == 'o'))
2024 return &SET_SRC (x);
2027 /* See if we can split SET_SRC as it stands. */
2028 split = find_split_point (&SET_SRC (x));
2029 if (split && split != &SET_SRC (x))
2032 /* See if this is a bitfield assignment with everything constant. If
2033 so, this is an IOR of an AND, so split it into that. */
2034 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
2035 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
2036 <= HOST_BITS_PER_INT)
2037 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
2038 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
2039 && GET_CODE (SET_SRC (x)) == CONST_INT
2040 && ((INTVAL (XEXP (SET_DEST (x), 1))
2041 + INTVAL (XEXP (SET_DEST (x), 2)))
2042 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
2043 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
2045 int pos = INTVAL (XEXP (SET_DEST (x), 2));
2046 int len = INTVAL (XEXP (SET_DEST (x), 1));
2047 int src = INTVAL (SET_SRC (x));
2048 rtx dest = XEXP (SET_DEST (x), 0);
2049 enum machine_mode mode = GET_MODE (dest);
2050 unsigned int mask = (1 << len) - 1;
2053 pos = GET_MODE_BITSIZE (mode) - len - pos;
2058 gen_binary (IOR, mode, dest,
2059 gen_rtx (CONST_INT, VOIDmode, src << pos)));
2062 gen_binary (IOR, mode,
2063 gen_binary (AND, mode, dest,
2064 gen_rtx (CONST_INT, VOIDmode,
2066 & GET_MODE_MASK (mode)))),
2067 gen_rtx (CONST_INT, VOIDmode, src << pos)));
2069 SUBST (SET_DEST (x), dest);
2071 split = find_split_point (&SET_SRC (x));
2072 if (split && split != &SET_SRC (x))
2076 /* Otherwise, see if this is an operation that we can split into two.
2077 If so, try to split that. */
2078 code = GET_CODE (SET_SRC (x));
2083 inner = XEXP (SET_SRC (x), 0);
2085 len = GET_MODE_BITSIZE (GET_MODE (inner));
2091 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2092 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
2094 inner = XEXP (SET_SRC (x), 0);
2095 len = INTVAL (XEXP (SET_SRC (x), 1));
2096 pos = INTVAL (XEXP (SET_SRC (x), 2));
2099 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
2101 unsignedp = (code == ZERO_EXTRACT);
2106 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
2108 enum machine_mode mode = GET_MODE (SET_SRC (x));
2110 if (unsignedp && len < HOST_BITS_PER_INT)
2115 gen_rtx_combine (LSHIFTRT, mode,
2116 gen_lowpart_for_combine (mode, inner),
2117 gen_rtx (CONST_INT, VOIDmode, pos)),
2118 gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1)));
2120 split = find_split_point (&SET_SRC (x));
2121 if (split && split != &SET_SRC (x))
2129 gen_rtx_combine (ASHIFT, mode,
2130 gen_lowpart_for_combine (mode, inner),
2131 gen_rtx (CONST_INT, VOIDmode,
2132 (GET_MODE_BITSIZE (mode)
2134 gen_rtx (CONST_INT, VOIDmode,
2135 GET_MODE_BITSIZE (mode) - len)));
2137 split = find_split_point (&SET_SRC (x));
2138 if (split && split != &SET_SRC (x))
2143 /* See if this is a simple operation with a constant as the second
2144 operand. It might be that this constant is out of range and hence
2145 could be used as a split point. */
2146 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2147 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2148 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<')
2149 && CONSTANT_P (XEXP (SET_SRC (x), 1))
2150 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x), 0))) == 'o'
2151 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
2152 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x), 0))))
2154 return &XEXP (SET_SRC (x), 1);
2156 /* Finally, see if this is a simple operation with its first operand
2157 not in a register. The operation might require this operand in a
2158 register, so return it as a split point. We can always do this
2159 because if the first operand were another operation, we would have
2160 already found it as a split point. */
2161 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '2'
2162 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == 'c'
2163 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '<'
2164 || GET_RTX_CLASS (GET_CODE (SET_SRC (x))) == '1')
2165 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
2166 return &XEXP (SET_SRC (x), 0);
2172 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
2173 it is better to write this as (not (ior A B)) so we can split it.
2174 Similarly for IOR. */
2175 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
2178 gen_rtx_combine (NOT, GET_MODE (x),
2179 gen_rtx_combine (code == IOR ? AND : IOR,
2181 XEXP (XEXP (x, 0), 0),
2182 XEXP (XEXP (x, 1), 0))));
2183 return find_split_point (loc);
2186 /* Many RISC machines have a large set of logical insns. If the
2187 second operand is a NOT, put it first so we will try to split the
2188 other operand first. */
2189 if (GET_CODE (XEXP (x, 1)) == NOT)
2191 rtx tem = XEXP (x, 0);
2192 SUBST (XEXP (x, 0), XEXP (x, 1));
2193 SUBST (XEXP (x, 1), tem);
2198 /* Otherwise, select our actions depending on our rtx class. */
2199 switch (GET_RTX_CLASS (code))
2201 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
2203 split = find_split_point (&XEXP (x, 2));
2206 /* ... fall through ... */
2210 split = find_split_point (&XEXP (x, 1));
2213 /* ... fall through ... */
2215 /* Some machines have (and (shift ...) ...) insns. If X is not
2216 an AND, but XEXP (X, 0) is, use it as our split point. */
2217 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
2218 return &XEXP (x, 0);
2220 split = find_split_point (&XEXP (x, 0));
2226 /* Otherwise, we don't have a split point. */
2230 /* Throughout X, replace FROM with TO, and return the result.
2231 The result is TO if X is FROM;
2232 otherwise the result is X, but its contents may have been modified.
2233 If they were modified, a record was made in undobuf so that
2234 undo_all will (among other things) return X to its original state.
2236 If the number of changes necessary is too much to record to undo,
2237 the excess changes are not made, so the result is invalid.
2238 The changes already made can still be undone.
2239 undobuf.num_undo is incremented for such changes, so by testing that
2240 the caller can tell whether the result is valid.
2242 `n_occurrences' is incremented each time FROM is replaced.
2244 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
2246 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
2247 by copying if `n_occurrences' is non-zero. */
2250 subst (x, from, to, in_dest, unique_copy)
2251 register rtx x, from, to;
2256 register int len, i;
2257 register enum rtx_code code = GET_CODE (x), orig_code = code;
2259 enum machine_mode mode = GET_MODE (x);
2260 enum machine_mode op0_mode = VOIDmode;
2265 /* FAKE_EXTEND_SAFE_P (MODE, FROM) is 1 if (subreg:MODE FROM 0) is a safe
2266 replacement for (zero_extend:MODE FROM) or (sign_extend:MODE FROM).
2267 If it is 0, that cannot be done. We can now do this for any MEM
2268 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be reloaded.
2269 If not for that, MEM's would very rarely be safe. */
2271 /* Reject MODEs bigger than a word, because we might not be able
2272 to reference a two-register group starting with an arbitrary register
2273 (and currently gen_lowpart might crash for a SUBREG). */
2275 #define FAKE_EXTEND_SAFE_P(MODE, FROM) \
2276 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)
2278 /* Two expressions are equal if they are identical copies of a shared
2279 RTX or if they are both registers with the same register number
2282 #define COMBINE_RTX_EQUAL_P(X,Y) \
2284 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
2285 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
2287 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
2290 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
2293 /* If X and FROM are the same register but different modes, they will
2294 not have been seen as equal above. However, flow.c will make a
2295 LOG_LINKS entry for that case. If we do nothing, we will try to
2296 rerecognize our original insn and, when it succeeds, we will
2297 delete the feeding insn, which is incorrect.
2299 So force this insn not to match in this (rare) case. */
2300 if (! in_dest && code == REG && GET_CODE (from) == REG
2301 && REGNO (x) == REGNO (from))
2302 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
2304 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
2305 of which may contain things that can be combined. */
2306 if (code != MEM && code != LO_SUM && GET_RTX_CLASS (code) == 'o')
2309 /* It is possible to have a subexpression appear twice in the insn.
2310 Suppose that FROM is a register that appears within TO.
2311 Then, after that subexpression has been scanned once by `subst',
2312 the second time it is scanned, TO may be found. If we were
2313 to scan TO here, we would find FROM within it and create a
2314 self-referent rtl structure which is completely wrong. */
2315 if (COMBINE_RTX_EQUAL_P (x, to))
2318 len = GET_RTX_LENGTH (code);
2319 fmt = GET_RTX_FORMAT (code);
2321 /* We don't need to process a SET_DEST that is a register, CC0, or PC, so
2322 set up to skip this common case. All other cases where we want to
2323 suppress replacing something inside a SET_SRC are handled via the
2326 && (GET_CODE (SET_DEST (x)) == REG
2327 || GET_CODE (SET_DEST (x)) == CC0
2328 || GET_CODE (SET_DEST (x)) == PC))
2331 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a constant. */
2333 op0_mode = GET_MODE (XEXP (x, 0));
2335 for (i = 0; i < len; i++)
2340 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2343 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
2345 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2350 new = subst (XVECEXP (x, i, j), from, to, 0, unique_copy);
2352 /* If this substitution failed, this whole thing fails. */
2353 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2357 SUBST (XVECEXP (x, i, j), new);
2360 else if (fmt[i] == 'e')
2364 if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
2366 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
2370 /* If we are in a SET_DEST, suppress most cases unless we
2371 have gone inside a MEM, in which case we want to
2372 simplify the address. We assume here that things that
2373 are actually part of the destination have their inner
2374 parts in the first expression. This is true for SUBREG,
2375 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
2376 things aside from REG and MEM that should appear in a
2378 new = subst (XEXP (x, i), from, to,
2380 && (code == SUBREG || code == STRICT_LOW_PART
2381 || code == ZERO_EXTRACT))
2383 && i == 0), unique_copy);
2385 /* If we found that we will have to reject this combination,
2386 indicate that by returning the CLOBBER ourselves, rather than
2387 an expression containing it. This will speed things up as
2388 well as prevent accidents where two CLOBBERs are considered
2389 to be equal, thus producing an incorrect simplification. */
2391 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
2394 SUBST (XEXP (x, i), new);
2398 /* If this is a commutative operation, put a constant last and a complex
2399 expression first. We don't need to do this for comparisons here. */
2400 if (GET_RTX_CLASS (code) == 'c'
2401 && ((CONSTANT_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 1)) != CONST_INT)
2402 || (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == 'o'
2403 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')
2404 || (GET_CODE (XEXP (x, 0)) == SUBREG
2405 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x, 0)))) == 'o'
2406 && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) != 'o')))
2409 SUBST (XEXP (x, 0), XEXP (x, 1));
2410 SUBST (XEXP (x, 1), temp);
2413 /* Try to fold this expression in case we have constants that weren't
2416 switch (GET_RTX_CLASS (code))
2419 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
2422 temp = simplify_relational_operation (code, op0_mode,
2423 XEXP (x, 0), XEXP (x, 1));
2427 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
2431 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
2432 XEXP (x, 1), XEXP (x, 2));
2439 /* We come back to here if we have replaced the expression with one of
2440 a different code and it is likely that further simplification will be
2445 /* If we have restarted more than 4 times, we are probably looping, so
2447 if (++n_restarts > 4)
2450 code = GET_CODE (x);
2452 /* First see if we can apply the inverse distributive law. */
2453 if (code == PLUS || code == MINUS || code == IOR || code == XOR)
2455 x = apply_distributive_law (x);
2456 code = GET_CODE (x);
2459 /* If CODE is an associative operation not otherwise handled, see if we
2460 can associate some operands. This can win if they are constants or
2461 if they are logically related (i.e. (a & b) & a. */
2462 if ((code == PLUS || code == MINUS
2463 || code == MULT || code == AND || code == IOR || code == XOR
2464 || code == DIV || code == UDIV
2465 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
2466 && GET_MODE_CLASS (mode) == MODE_INT)
2468 if (GET_CODE (XEXP (x, 0)) == code)
2470 rtx other = XEXP (XEXP (x, 0), 0);
2471 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
2472 rtx inner_op1 = XEXP (x, 1);
2475 /* Make sure we pass the constant operand if any as the second
2476 one if this is a commutative operation. */
2477 if (CONSTANT_P (inner_op0) && GET_RTX_CLASS (code) == 'c')
2479 rtx tem = inner_op0;
2480 inner_op0 = inner_op1;
2483 inner = simplify_binary_operation (code == MINUS ? PLUS
2484 : code == DIV ? MULT
2485 : code == UDIV ? MULT
2487 mode, inner_op0, inner_op1);
2489 /* For commutative operations, try the other pair if that one
2491 if (inner == 0 && GET_RTX_CLASS (code) == 'c')
2493 other = XEXP (XEXP (x, 0), 1);
2494 inner = simplify_binary_operation (code, mode,
2495 XEXP (XEXP (x, 0), 0),
2501 x = gen_binary (code, mode, other, inner);
2508 /* A little bit of algebraic simplification here. */
2512 /* Ensure that our address has any ASHIFTs converted to MULT in case
2513 address-recognizing predicates are called later. */
2514 temp = make_compound_operation (XEXP (x, 0), MEM);
2515 SUBST (XEXP (x, 0), temp);
2519 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
2520 is paradoxical. If we can't do that safely, then it becomes
2521 something nonsensical so that this combination won't take place. */
2523 if (GET_CODE (SUBREG_REG (x)) == MEM
2524 && (GET_MODE_SIZE (mode)
2525 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
2527 rtx inner = SUBREG_REG (x);
2528 int endian_offset = 0;
2529 /* Don't change the mode of the MEM
2530 if that would change the meaning of the address. */
2531 if (MEM_VOLATILE_P (SUBREG_REG (x))
2532 || mode_dependent_address_p (XEXP (inner, 0)))
2533 return gen_rtx (CLOBBER, mode, const0_rtx);
2535 #if BYTES_BIG_ENDIAN
2536 if (GET_MODE_SIZE (mode) < UNITS_PER_WORD)
2537 endian_offset += UNITS_PER_WORD - GET_MODE_SIZE (mode);
2538 if (GET_MODE_SIZE (GET_MODE (inner)) < UNITS_PER_WORD)
2539 endian_offset -= UNITS_PER_WORD - GET_MODE_SIZE (GET_MODE (inner));
2541 /* Note if the plus_constant doesn't make a valid address
2542 then this combination won't be accepted. */
2543 x = gen_rtx (MEM, mode,
2544 plus_constant (XEXP (inner, 0),
2545 (SUBREG_WORD (x) * UNITS_PER_WORD
2547 MEM_VOLATILE_P (x) = MEM_VOLATILE_P (inner);
2548 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (inner);
2549 MEM_IN_STRUCT_P (x) = MEM_IN_STRUCT_P (inner);
2553 /* If we are in a SET_DEST, these other cases can't apply. */
2557 /* Changing mode twice with SUBREG => just change it once,
2558 or not at all if changing back to starting mode. */
2559 if (GET_CODE (SUBREG_REG (x)) == SUBREG)
2561 if (mode == GET_MODE (SUBREG_REG (SUBREG_REG (x)))
2562 && SUBREG_WORD (x) == 0 && SUBREG_WORD (SUBREG_REG (x)) == 0)
2563 return SUBREG_REG (SUBREG_REG (x));
2565 SUBST_INT (SUBREG_WORD (x),
2566 SUBREG_WORD (x) + SUBREG_WORD (SUBREG_REG (x)));
2567 SUBST (SUBREG_REG (x), SUBREG_REG (SUBREG_REG (x)));
2570 /* SUBREG of a hard register => just change the register number
2571 and/or mode. If the hard register is not valid in that mode,
2572 suppress this combination. */
2574 if (GET_CODE (SUBREG_REG (x)) == REG
2575 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
2577 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x)) + SUBREG_WORD (x),
2579 return gen_rtx (REG, mode,
2580 REGNO (SUBREG_REG (x)) + SUBREG_WORD (x));
2582 return gen_rtx (CLOBBER, mode, const0_rtx);
2585 /* For a constant, try to pick up the part we want. Handle a full
2586 word and low-order part. Only do this if we are narrowing
2587 the constant; if it is being widened, we have no idea what
2588 the extra bits will have been set to. */
2590 if (CONSTANT_P (SUBREG_REG (x)) && op0_mode != VOIDmode
2591 && GET_MODE_SIZE (mode) == UNITS_PER_WORD
2592 && GET_MODE_SIZE (op0_mode) < UNITS_PER_WORD
2593 && GET_MODE_CLASS (mode) == MODE_INT)
2595 temp = operand_subword (SUBREG_REG (x), SUBREG_WORD (x),
2601 if (CONSTANT_P (SUBREG_REG (x)) && subreg_lowpart_p (x)
2602 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (op0_mode))
2603 return gen_lowpart_for_combine (mode, SUBREG_REG (x));
2605 /* If we are narrowing the object, we need to see if we can simplify
2606 the expression for the object knowing that we only need the
2607 low-order bits. We do this by computing an AND of the object
2608 with only the bits we care about. That will produce any needed
2609 simplifications. If the resulting computation is just the
2610 AND with the significant bits, our operand is the first operand
2611 of the AND. Otherwise, it is the resulting expression. */
2612 if (GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))
2613 && subreg_lowpart_p (x)
2614 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
2616 temp = simplify_and_const_int (0, GET_MODE (SUBREG_REG (x)),
2617 SUBREG_REG (x), GET_MODE_MASK (mode));
2618 if (GET_CODE (temp) == AND && GET_CODE (XEXP (temp, 1)) == CONST_INT
2619 && INTVAL (XEXP (temp, 1)) == GET_MODE_MASK (mode))
2620 temp = XEXP (temp, 0);
2621 return gen_lowpart_for_combine (mode, temp);
2627 /* (not (plus X -1)) can become (neg X). */
2628 if (GET_CODE (XEXP (x, 0)) == PLUS
2629 && XEXP (XEXP (x, 0), 1) == constm1_rtx)
2631 x = gen_rtx_combine (NEG, mode, XEXP (XEXP (x, 0), 0));
2635 /* Similarly, (not (neg X)) is (plus X -1). */
2636 if (GET_CODE (XEXP (x, 0)) == NEG)
2638 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
2642 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
2643 other than 1, but that is not valid. We could do a similar
2644 simplification for (not (lshiftrt C X)) where C is just the sign bit,
2645 but this doesn't seem common enough to bother with. */
2646 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2647 && XEXP (XEXP (x, 0), 0) == const1_rtx)
2649 x = gen_rtx (ROTATE, mode, gen_unary (NOT, mode, const1_rtx),
2650 XEXP (XEXP (x, 0), 1));
2654 if (GET_CODE (XEXP (x, 0)) == SUBREG
2655 && subreg_lowpart_p (XEXP (x, 0))
2656 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
2657 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
2658 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
2659 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
2661 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
2663 x = gen_rtx (ROTATE, inner_mode,
2664 gen_unary (NOT, inner_mode, const1_rtx),
2665 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
2666 x = gen_lowpart_for_combine (mode, x);
2670 #if STORE_FLAG_VALUE == -1
2671 /* (not (comparison foo bar)) can be done by reversing the comparison
2673 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
2674 && reversible_comparison_p (XEXP (x, 0)))
2675 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
2676 mode, XEXP (XEXP (x, 0), 0),
2677 XEXP (XEXP (x, 0), 1));
2680 /* Apply De Morgan's laws to reduce number of patterns for machines
2681 with negating logical insns (and-not, nand, etc.). If result has
2682 only one NOT, put it first, since that is how the patterns are
2685 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
2687 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
2689 if (GET_CODE (in1) == NOT)
2690 in1 = XEXP (in1, 0);
2692 in1 = gen_rtx_combine (NOT, GET_MODE (in1), in1);
2694 if (GET_CODE (in2) == NOT)
2695 in2 = XEXP (in2, 0);
2696 else if (GET_CODE (in2) == CONST_INT
2697 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
2698 in2 = gen_rtx (CONST_INT, VOIDmode,
2699 GET_MODE_MASK (mode) & ~ INTVAL (in2));
2701 in2 = gen_rtx_combine (NOT, GET_MODE (in2), in2);
2703 if (GET_CODE (in2) == NOT)
2706 in2 = in1; in1 = tem;
2709 x = gen_rtx_combine (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
2716 /* (neg (plus X 1)) can become (not X). */
2717 if (GET_CODE (XEXP (x, 0)) == PLUS
2718 && XEXP (XEXP (x, 0), 1) == const1_rtx)
2720 x = gen_rtx_combine (NOT, mode, XEXP (XEXP (x, 0), 0));
2724 /* Similarly, (neg (not X)) is (plus X 1). */
2725 if (GET_CODE (XEXP (x, 0)) == NOT)
2727 x = gen_rtx_combine (PLUS, mode, XEXP (XEXP (x, 0), 0), const1_rtx);
2731 /* (neg (abs X)) is X if X is a value known to be either -1 or 0. */
2732 if (GET_CODE (XEXP (x, 0)) == ABS
2733 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTRACT
2734 && XEXP (XEXP (XEXP (x, 0), 0), 1) == const1_rtx)
2735 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFTRT
2736 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2737 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2738 == GET_MODE_BITSIZE (mode) - 1))
2739 || ((temp = get_last_value (XEXP (XEXP (x, 0), 0))) != 0
2740 && ((GET_CODE (temp) == SIGN_EXTRACT
2741 && XEXP (temp, 1) == const1_rtx)
2742 || (GET_CODE (temp) == ASHIFTRT
2743 && GET_CODE (XEXP (temp, 1)) == CONST_INT
2744 && (INTVAL (XEXP (temp, 1))
2745 == GET_MODE_BITSIZE (mode) - 1))))))
2746 return XEXP (XEXP (x, 0), 0);
2748 /* (neg (minus X Y)) can become (minus Y X). */
2749 if (GET_CODE (XEXP (x, 0)) == MINUS
2750 && (GET_MODE_CLASS (mode) != MODE_FLOAT
2751 /* x-y != -(y-x) with IEEE floating point. */
2752 || TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT))
2754 x = gen_binary (MINUS, mode, XEXP (XEXP (x, 0), 1),
2755 XEXP (XEXP (x, 0), 0));
2759 /* NEG commutes with ASHIFT since it is multiplication. Only do this
2760 if we can then eliminate the NEG (e.g.,
2761 if the operand is a constant). */
2763 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
2765 temp = simplify_unary_operation (NEG, mode,
2766 XEXP (XEXP (x, 0), 0), mode);
2769 SUBST (XEXP (XEXP (x, 0), 0), temp);
2774 temp = expand_compound_operation (XEXP (x, 0));
2776 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
2777 replaced by (lshiftrt X C). This will convert
2778 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
2780 if (GET_CODE (temp) == ASHIFTRT
2781 && GET_CODE (XEXP (temp, 1)) == CONST_INT
2782 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
2784 x = simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
2785 INTVAL (XEXP (temp, 1)));
2789 /* If X has only a single bit significant, say, bit I, convert
2790 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
2791 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
2792 (sign_extract X 1 Y). But only do this if TEMP isn't a register
2793 or a SUBREG of one since we'd be making the expression more
2794 complex if it was just a register. */
2796 if (GET_CODE (temp) != REG
2797 && ! (GET_CODE (temp) == SUBREG
2798 && GET_CODE (SUBREG_REG (temp)) == REG)
2799 && (i = exact_log2 (significant_bits (temp, mode))) >= 0)
2801 rtx temp1 = simplify_shift_const
2803 simplify_shift_const (0, ASHIFT, mode, temp,
2804 GET_MODE_BITSIZE (mode) - 1 - i),
2805 GET_MODE_BITSIZE (mode) - 1 - i);
2807 /* If all we did was surround TEMP with the two shifts, we
2808 haven't improved anything, so don't use it. Otherwise,
2809 we are better off with TEMP1. */
2810 if (GET_CODE (temp1) != ASHIFTRT
2811 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
2812 || XEXP (XEXP (temp1, 0), 0) != temp)
2820 case FLOAT_TRUNCATE:
2821 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
2822 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
2823 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
2824 return XEXP (XEXP (x, 0), 0);
2829 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
2830 using cc0, in which case we want to leave it as a COMPARE
2831 so we can distinguish it from a register-register-copy. */
2832 if (XEXP (x, 1) == const0_rtx)
2835 /* In IEEE floating point, x-0 is not the same as x. */
2836 if ((TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
2837 || GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT)
2838 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
2844 /* (const (const X)) can become (const X). Do it this way rather than
2845 returning the inner CONST since CONST can be shared with a
2847 if (GET_CODE (XEXP (x, 0)) == CONST)
2848 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
2853 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
2854 can add in an offset. find_split_point will split this address up
2855 again if it doesn't match. */
2856 if (GET_CODE (XEXP (x, 0)) == HIGH
2857 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
2863 /* If we have (plus (plus (A const) B)), associate it so that CONST is
2864 outermost. That's because that's the way indexed addresses are
2865 supposed to appear. This code used to check many more cases, but
2866 they are now checked elsewhere. */
2867 if (GET_CODE (XEXP (x, 0)) == PLUS
2868 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
2869 return gen_binary (PLUS, mode,
2870 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
2872 XEXP (XEXP (x, 0), 1));
2874 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
2875 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
2876 bit-field and can be replaced by either a sign_extend or a
2877 sign_extract. The `and' may be a zero_extend. */
2878 if (GET_CODE (XEXP (x, 0)) == XOR
2879 && GET_CODE (XEXP (x, 1)) == CONST_INT
2880 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2881 && INTVAL (XEXP (x, 1)) == - INTVAL (XEXP (XEXP (x, 0), 1))
2882 && (i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
2883 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
2884 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
2885 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
2886 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
2887 == (1 << (i + 1)) - 1))
2888 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
2889 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
2892 x = simplify_shift_const
2894 simplify_shift_const (0, ASHIFT, mode,
2895 XEXP (XEXP (XEXP (x, 0), 0), 0),
2896 GET_MODE_BITSIZE (mode) - (i + 1)),
2897 GET_MODE_BITSIZE (mode) - (i + 1));
2901 /* If only the low-order bit of X is significant, (plus x -1)
2902 can become (ashiftrt (ashift (xor x 1) C) C) where C is
2903 the bitsize of the mode - 1. This allows simplification of
2904 "a = (b & 8) == 0;" */
2905 if (XEXP (x, 1) == constm1_rtx
2906 && GET_CODE (XEXP (x, 0)) != REG
2907 && ! (GET_CODE (XEXP (x,0)) == SUBREG
2908 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == REG)
2909 && significant_bits (XEXP (x, 0), mode) == 1)
2911 x = simplify_shift_const
2913 simplify_shift_const (0, ASHIFT, mode,
2914 gen_rtx_combine (XOR, mode,
2915 XEXP (x, 0), const1_rtx),
2916 GET_MODE_BITSIZE (mode) - 1),
2917 GET_MODE_BITSIZE (mode) - 1);
2923 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
2924 (and <foo> (const_int pow2-1)) */
2925 if (GET_CODE (XEXP (x, 1)) == AND
2926 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
2927 && exact_log2 (- INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
2928 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
2930 x = simplify_and_const_int (0, mode, XEXP (x, 0),
2931 - INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
2937 /* If we have (mult (plus A B) C), apply the distributive law and then
2938 the inverse distributive law to see if things simplify. This
2939 occurs mostly in addresses, often when unrolling loops. */
2941 if (GET_CODE (XEXP (x, 0)) == PLUS)
2943 x = apply_distributive_law
2944 (gen_binary (PLUS, mode,
2945 gen_binary (MULT, mode,
2946 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
2947 gen_binary (MULT, mode,
2948 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
2950 if (GET_CODE (x) != MULT)
2954 /* If this is multiplication by a power of two and its first operand is
2955 a shift, treat the multiply as a shift to allow the shifts to
2956 possibly combine. */
2957 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2958 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
2959 && (GET_CODE (XEXP (x, 0)) == ASHIFT
2960 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
2961 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
2962 || GET_CODE (XEXP (x, 0)) == ROTATE
2963 || GET_CODE (XEXP (x, 0)) == ROTATERT))
2965 x = simplify_shift_const (0, ASHIFT, mode, XEXP (x, 0), i);
2969 /* Convert (mult (ashift (const_int 1) A) B) to (ashift B A). */
2970 if (GET_CODE (XEXP (x, 0)) == ASHIFT
2971 && XEXP (XEXP (x, 0), 0) == const1_rtx)
2972 return gen_rtx_combine (ASHIFT, mode, XEXP (x, 1),
2973 XEXP (XEXP (x, 0), 1));
2977 /* If this is a divide by a power of two, treat it as a shift if
2978 its first operand is a shift. */
2979 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2980 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
2981 && (GET_CODE (XEXP (x, 0)) == ASHIFT
2982 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
2983 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
2984 || GET_CODE (XEXP (x, 0)) == ROTATE
2985 || GET_CODE (XEXP (x, 0)) == ROTATERT))
2987 x = simplify_shift_const (0, LSHIFTRT, mode, XEXP (x, 0), i);
2993 case GT: case GTU: case GE: case GEU:
2994 case LT: case LTU: case LE: case LEU:
2995 /* If the first operand is a condition code, we can't do anything
2997 if (GET_CODE (XEXP (x, 0)) == COMPARE
2998 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
3000 && XEXP (x, 0) != cc0_rtx
3004 rtx op0 = XEXP (x, 0);
3005 rtx op1 = XEXP (x, 1);
3006 enum rtx_code new_code;
3008 if (GET_CODE (op0) == COMPARE)
3009 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
3011 /* Simplify our comparison, if possible. */
3012 new_code = simplify_comparison (code, &op0, &op1);
3014 #if STORE_FLAG_VALUE == 1
3015 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
3016 if only the low-order bit is significant in X (such as when
3017 X is a ZERO_EXTRACT of one bit. Similarly, we can convert
3019 if (new_code == NE && mode != VOIDmode
3020 && op1 == const0_rtx
3021 && significant_bits (op0, GET_MODE (op0)) == 1)
3022 return gen_lowpart_for_combine (mode, op0);
3023 else if (new_code == EQ && mode != VOIDmode
3024 && op1 == const0_rtx
3025 && significant_bits (op0, GET_MODE (op0)) == 1)
3026 return gen_rtx_combine (XOR, mode,
3027 gen_lowpart_for_combine (mode, op0),
3031 #if STORE_FLAG_VALUE == -1
3032 /* If STORE_FLAG_VALUE is -1, we can convert (ne x 0)
3033 to (neg x) if only the low-order bit of X is significant.
3034 This converts (ne (zero_extract X 1 Y) 0) to
3035 (sign_extract X 1 Y). */
3036 if (new_code == NE && mode != VOIDmode
3037 && op1 == const0_rtx
3038 && significant_bits (op0, GET_MODE (op0)) == 1)
3040 x = gen_rtx_combine (NEG, mode,
3041 gen_lowpart_for_combine (mode, op0));
3046 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
3047 one significant bit, we can convert (ne x 0) to (ashift x c)
3048 where C puts the bit in the sign bit. Remove any AND with
3049 STORE_FLAG_VALUE when we are done, since we are only going to
3050 test the sign bit. */
3051 if (new_code == NE && mode != VOIDmode
3052 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3053 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3054 && op1 == const0_rtx
3055 && mode == GET_MODE (op0)
3056 && (i = exact_log2 (significant_bits (op0, GET_MODE (op0)))) >= 0)
3058 x = simplify_shift_const (0, ASHIFT, mode, op0,
3059 GET_MODE_BITSIZE (mode) - 1 - i);
3060 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
3066 /* If the code changed, return a whole new comparison. */
3067 if (new_code != code)
3068 return gen_rtx_combine (new_code, mode, op0, op1);
3070 /* Otherwise, keep this operation, but maybe change its operands.
3071 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
3072 SUBST (XEXP (x, 0), op0);
3073 SUBST (XEXP (x, 1), op1);
3078 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
3079 reversed, do so to avoid needing two sets of patterns for
3080 subtract-and-branch insns. */
3081 if (XEXP (x, 1) == pc_rtx && reversible_comparison_p (XEXP (x, 0)))
3084 gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3085 GET_MODE (XEXP (x, 0)),
3086 XEXP (XEXP (x, 0), 0),
3087 XEXP (XEXP (x, 0), 1)));
3088 SUBST (XEXP (x, 1), XEXP (x, 2));
3089 SUBST (XEXP (x, 2), pc_rtx);
3097 /* If we are processing SET_DEST, we are done. */
3101 x = expand_compound_operation (x);
3102 if (GET_CODE (x) != code)
3107 /* (set (pc) (return)) gets written as (return). */
3108 if (GET_CODE (SET_DEST (x)) == PC && GET_CODE (SET_SRC (x)) == RETURN)
3111 /* Convert this into a field assignment operation, if possible. */
3112 x = make_field_assignment (x);
3114 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some
3115 operation, and X being a REG or (subreg (reg)), we may be able to
3116 convert this to (set (subreg:m2 x) (op)).
3118 We can always do this if M1 is narrower than M2 because that
3119 means that we only care about the low bits of the result.
3121 However, on most machines (those with BYTE_LOADS_ZERO_EXTEND
3122 not defined), we cannot perform a narrower operation that
3123 requested since the high-order bits will be undefined. On
3124 machine where BYTE_LOADS_ZERO_EXTEND are defined, however, this
3125 transformation is safe as long as M1 and M2 have the same number
3128 if (GET_CODE (SET_SRC (x)) == SUBREG
3129 && subreg_lowpart_p (SET_SRC (x))
3130 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x)))) != 'o'
3131 && (((GET_MODE_SIZE (GET_MODE (SET_SRC (x))) + (UNITS_PER_WORD - 1))
3133 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x))))
3134 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
3135 #ifndef BYTE_LOADS_ZERO_EXTEND
3136 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3137 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3139 && (GET_CODE (SET_DEST (x)) == REG
3140 || (GET_CODE (SET_DEST (x)) == SUBREG
3141 && GET_CODE (SUBREG_REG (SET_DEST (x))) == REG)))
3143 /* Get the object that will be the SUBREG_REG of the
3144 SUBREG we are making. Note that SUBREG_WORD will always
3145 be zero because this will either be a paradoxical SUBREG
3146 or a SUBREG with the same number of words on the outside and
3148 rtx object = (GET_CODE (SET_DEST (x)) == REG ? SET_DEST (x)
3149 : SUBREG_REG (SET_DEST (x)));
3151 SUBST (SET_DEST (x),
3152 gen_rtx (SUBREG, GET_MODE (SUBREG_REG (SET_SRC (x))),
3154 SUBST (SET_SRC (x), SUBREG_REG (SET_SRC (x)));
3157 /* If we are setting CC0 or if the source is a COMPARE, look for the
3158 use of the comparison result and try to simplify it unless we already
3159 have used undobuf.other_insn. */
3160 if ((GET_CODE (SET_SRC (x)) == COMPARE
3162 || SET_DEST (x) == cc0_rtx
3165 && (cc_use = find_single_use (SET_DEST (x), subst_insn,
3167 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
3168 && GET_RTX_CLASS (GET_CODE (*cc_use)) == '<'
3169 && XEXP (*cc_use, 0) == SET_DEST (x))
3171 enum rtx_code old_code = GET_CODE (*cc_use);
3172 enum rtx_code new_code;
3174 int other_changed = 0;
3175 enum machine_mode compare_mode = GET_MODE (SET_DEST (x));
3177 if (GET_CODE (SET_SRC (x)) == COMPARE)
3178 op0 = XEXP (SET_SRC (x), 0), op1 = XEXP (SET_SRC (x), 1);
3180 op0 = SET_SRC (x), op1 = const0_rtx;
3182 /* Simplify our comparison, if possible. */
3183 new_code = simplify_comparison (old_code, &op0, &op1);
3185 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
3186 /* If this machine has CC modes other than CCmode, check to see
3187 if we need to use a different CC mode here. */
3188 compare_mode = SELECT_CC_MODE (new_code, op0);
3190 /* If the mode changed, we have to change SET_DEST, the mode
3191 in the compare, and the mode in the place SET_DEST is used.
3192 If SET_DEST is a hard register, just build new versions with
3193 the proper mode. If it is a pseudo, we lose unless it is only
3194 time we set the pseudo, in which case we can safely change
3196 if (compare_mode != GET_MODE (SET_DEST (x)))
3198 int regno = REGNO (SET_DEST (x));
3199 rtx new_dest = gen_rtx (REG, compare_mode, regno);
3201 if (regno < FIRST_PSEUDO_REGISTER
3202 || (reg_n_sets[regno] == 1
3203 && ! REG_USERVAR_P (SET_DEST (x))))
3205 if (regno >= FIRST_PSEUDO_REGISTER)
3206 SUBST (regno_reg_rtx[regno], new_dest);
3208 SUBST (SET_DEST (x), new_dest);
3209 SUBST (XEXP (*cc_use, 0), new_dest);
3215 /* If the code changed, we have to build a new comparison
3216 in undobuf.other_insn. */
3217 if (new_code != old_code)
3221 SUBST (*cc_use, gen_rtx_combine (new_code, GET_MODE (*cc_use),
3222 SET_DEST (x), const0_rtx));
3224 /* If the only change we made was to change an EQ into an
3225 NE or vice versa, OP0 has only one significant bit,
3226 and OP1 is zero, check if changing the user of the condition
3227 code will produce a valid insn. If it won't, we can keep
3228 the original code in that insn by surrounding our operation
3231 if (((old_code == NE && new_code == EQ)
3232 || (old_code == EQ && new_code == NE))
3233 && ! other_changed && op1 == const0_rtx
3234 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
3235 && (exact_log2 (mask = significant_bits (op0,
3239 rtx pat = PATTERN (other_insn), note = 0;
3241 if ((recog_for_combine (&pat, undobuf.other_insn, ¬e) < 0
3242 && ! check_asm_operands (pat)))
3244 PUT_CODE (*cc_use, old_code);
3247 op0 = gen_binary (XOR, GET_MODE (op0), op0,
3248 gen_rtx (CONST_INT, VOIDmode, mask));
3256 undobuf.other_insn = other_insn;
3259 /* If we are now comparing against zero, change our source if
3260 needed. If we do not use cc0, we always have a COMPARE. */
3261 if (op1 == const0_rtx && SET_DEST (x) == cc0_rtx)
3262 SUBST (SET_SRC (x), op0);
3266 /* Otherwise, if we didn't previously have a COMPARE in the
3267 correct mode, we need one. */
3268 if (GET_CODE (SET_SRC (x)) != COMPARE
3269 || GET_MODE (SET_SRC (x)) != compare_mode)
3270 SUBST (SET_SRC (x), gen_rtx_combine (COMPARE, compare_mode,
3274 /* Otherwise, update the COMPARE if needed. */
3275 SUBST (XEXP (SET_SRC (x), 0), op0);
3276 SUBST (XEXP (SET_SRC (x), 1), op1);
3281 /* Get SET_SRC in a form where we have placed back any
3282 compound expressions. Then do the checks below. */
3283 temp = make_compound_operation (SET_SRC (x), SET);
3284 SUBST (SET_SRC (x), temp);
3287 #ifdef BYTE_LOADS_ZERO_EXTEND
3288 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with
3289 M wider than N, this would require a paradoxical subreg.
3290 Replace the subreg with a zero_extend to avoid the reload that
3291 would otherwise be required. */
3292 if (GET_CODE (SET_SRC (x)) == SUBREG
3293 && subreg_lowpart_p (SET_SRC (x))
3294 && SUBREG_WORD (SET_SRC (x)) == 0
3295 && (GET_MODE_SIZE (GET_MODE (SET_SRC (x)))
3296 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_SRC (x)))))
3297 && GET_CODE (SUBREG_REG (SET_SRC (x))) == MEM)
3298 SUBST (SET_SRC (x), gen_rtx_combine (ZERO_EXTEND,
3299 GET_MODE (SET_SRC (x)),
3300 XEXP (SET_SRC (x), 0)));
3306 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3308 x = simplify_and_const_int (x, mode, XEXP (x, 0),
3309 INTVAL (XEXP (x, 1)));
3311 /* If we have (ior (and (X C1) C2)) and the next restart would be
3312 the last, simplify this by making C1 as small as possible
3314 if (n_restarts >= 3 && GET_CODE (x) == IOR
3315 && GET_CODE (XEXP (x, 0)) == AND
3316 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3317 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3319 temp = gen_binary (AND, mode, XEXP (XEXP (x, 0), 0),
3320 gen_rtx (CONST_INT, VOIDmode,
3321 (INTVAL (XEXP (XEXP (x, 0), 1))
3322 & ~ INTVAL (XEXP (x, 1)))));
3323 return gen_binary (IOR, mode, temp, XEXP (x, 1));
3326 if (GET_CODE (x) != AND)
3330 /* Convert (A | B) & A to A. */
3331 if (GET_CODE (XEXP (x, 0)) == IOR
3332 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3333 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3334 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3335 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3338 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
3339 insn (and may simplify more). */
3340 else if (GET_CODE (XEXP (x, 0)) == XOR
3341 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3342 && ! side_effects_p (XEXP (x, 1)))
3344 x = gen_binary (AND, mode,
3345 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3349 else if (GET_CODE (XEXP (x, 0)) == XOR
3350 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3351 && ! side_effects_p (XEXP (x, 1)))
3353 x = gen_binary (AND, mode,
3354 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3359 /* Similarly for (~ (A ^ B)) & A. */
3360 else if (GET_CODE (XEXP (x, 0)) == NOT
3361 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3362 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 0), XEXP (x, 1))
3363 && ! side_effects_p (XEXP (x, 1)))
3365 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 1),
3369 else if (GET_CODE (XEXP (x, 0)) == NOT
3370 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3371 && rtx_equal_p (XEXP (XEXP (XEXP (x, 0), 0), 1), XEXP (x, 1))
3372 && ! side_effects_p (XEXP (x, 1)))
3374 x = gen_binary (AND, mode, XEXP (XEXP (XEXP (x, 0), 0), 0),
3379 /* In the follow group of tests (and those in case IOR below),
3380 we start with some combination of logical operations and apply
3381 the distributive law followed by the inverse distributive law.
3382 Most of the time, this results in no change. However, if some of
3383 the operands are the same or inverses of each other, simplifications
3386 For example, (and (ior A B) (not B)) can occur as the result of
3387 expanding a bit field assignment. When we apply the distributive
3388 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
3389 which then simplifies to (and (A (not B))). */
3391 /* If we have (and (ior A B) C), apply the distributive law and then
3392 the inverse distributive law to see if things simplify. */
3394 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == XOR)
3396 x = apply_distributive_law
3397 (gen_binary (GET_CODE (XEXP (x, 0)), mode,
3398 gen_binary (AND, mode,
3399 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3400 gen_binary (AND, mode,
3401 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3402 if (GET_CODE (x) != AND)
3406 if (GET_CODE (XEXP (x, 1)) == IOR || GET_CODE (XEXP (x, 1)) == XOR)
3408 x = apply_distributive_law
3409 (gen_binary (GET_CODE (XEXP (x, 1)), mode,
3410 gen_binary (AND, mode,
3411 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3412 gen_binary (AND, mode,
3413 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3414 if (GET_CODE (x) != AND)
3418 /* Similarly, taking advantage of the fact that
3419 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
3421 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == XOR)
3423 x = apply_distributive_law
3424 (gen_binary (XOR, mode,
3425 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3426 XEXP (XEXP (x, 1), 0)),
3427 gen_binary (IOR, mode, XEXP (XEXP (x, 0), 0),
3428 XEXP (XEXP (x, 1), 1))));
3429 if (GET_CODE (x) != AND)
3433 else if (GET_CODE (XEXP (x, 1)) == NOT && GET_CODE (XEXP (x, 0)) == XOR)
3435 x = apply_distributive_law
3436 (gen_binary (XOR, mode,
3437 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3438 XEXP (XEXP (x, 0), 0)),
3439 gen_binary (IOR, mode, XEXP (XEXP (x, 1), 0),
3440 XEXP (XEXP (x, 0), 1))));
3441 if (GET_CODE (x) != AND)
3447 /* Convert (A & B) | A to A. */
3448 if (GET_CODE (XEXP (x, 0)) == AND
3449 && (rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3450 || rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1)))
3451 && ! side_effects_p (XEXP (XEXP (x, 0), 0))
3452 && ! side_effects_p (XEXP (XEXP (x, 0), 1)))
3455 /* If we have (ior (and A B) C), apply the distributive law and then
3456 the inverse distributive law to see if things simplify. */
3458 if (GET_CODE (XEXP (x, 0)) == AND)
3460 x = apply_distributive_law
3461 (gen_binary (AND, mode,
3462 gen_binary (IOR, mode,
3463 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
3464 gen_binary (IOR, mode,
3465 XEXP (XEXP (x, 0), 1), XEXP (x, 1))));
3467 if (GET_CODE (x) != IOR)
3471 if (GET_CODE (XEXP (x, 1)) == AND)
3473 x = apply_distributive_law
3474 (gen_binary (AND, mode,
3475 gen_binary (IOR, mode,
3476 XEXP (XEXP (x, 1), 0), XEXP (x, 0)),
3477 gen_binary (IOR, mode,
3478 XEXP (XEXP (x, 1), 1), XEXP (x, 0))));
3480 if (GET_CODE (x) != IOR)
3484 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
3485 mode size to (rotate A CX). */
3487 if (((GET_CODE (XEXP (x, 0)) == ASHIFT
3488 && GET_CODE (XEXP (x, 1)) == LSHIFTRT)
3489 || (GET_CODE (XEXP (x, 1)) == ASHIFT
3490 && GET_CODE (XEXP (x, 0)) == LSHIFTRT))
3491 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (XEXP (x, 1), 0))
3492 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3493 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3494 && (INTVAL (XEXP (XEXP (x, 0), 1)) + INTVAL (XEXP (XEXP (x, 1), 1))
3495 == GET_MODE_BITSIZE (mode)))
3499 if (GET_CODE (XEXP (x, 0)) == ASHIFT)
3500 shift_count = XEXP (XEXP (x, 0), 1);
3502 shift_count = XEXP (XEXP (x, 1), 1);
3503 x = gen_rtx (ROTATE, mode, XEXP (XEXP (x, 0), 0), shift_count);
3509 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
3510 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
3513 int num_negated = 0;
3514 rtx in1 = XEXP (x, 0), in2 = XEXP (x, 1);
3516 if (GET_CODE (in1) == NOT)
3517 num_negated++, in1 = XEXP (in1, 0);
3518 if (GET_CODE (in2) == NOT)
3519 num_negated++, in2 = XEXP (in2, 0);
3521 if (num_negated == 2)
3523 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3524 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3526 else if (num_negated == 1)
3527 return gen_rtx_combine (NOT, mode,
3528 gen_rtx_combine (XOR, mode, in1, in2));
3531 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
3532 correspond to a machine insn or result in further simplifications
3533 if B is a constant. */
3535 if (GET_CODE (XEXP (x, 0)) == AND
3536 && rtx_equal_p (XEXP (XEXP (x, 0), 1), XEXP (x, 1))
3537 && ! side_effects_p (XEXP (x, 1)))
3539 x = gen_binary (AND, mode,
3540 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 0)),
3544 else if (GET_CODE (XEXP (x, 0)) == AND
3545 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1))
3546 && ! side_effects_p (XEXP (x, 1)))
3548 x = gen_binary (AND, mode,
3549 gen_unary (NOT, mode, XEXP (XEXP (x, 0), 1)),
3555 #if STORE_FLAG_VALUE == 1
3556 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
3558 if (XEXP (x, 1) == const1_rtx
3559 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3560 && reversible_comparison_p (XEXP (x, 0)))
3561 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3562 mode, XEXP (XEXP (x, 0), 0),
3563 XEXP (XEXP (x, 0), 1));
3566 /* (xor (comparison foo bar) (const_int sign-bit))
3567 when STORE_FLAG_VALUE is the sign bit. */
3568 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT
3569 && STORE_FLAG_VALUE == 1 << (GET_MODE_BITSIZE (mode) - 1)
3570 && XEXP (x, 1) == const_true_rtx
3571 && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
3572 && reversible_comparison_p (XEXP (x, 0)))
3573 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x, 0))),
3574 mode, XEXP (XEXP (x, 0), 0),
3575 XEXP (XEXP (x, 0), 1));
3579 /* (abs (neg <foo>)) -> (abs <foo>) */
3580 if (GET_CODE (XEXP (x, 0)) == NEG)
3581 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3583 /* If operand is something known to be positive, ignore the ABS. */
3584 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
3585 || (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) <= HOST_BITS_PER_INT
3586 && ((significant_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
3587 & (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
3592 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
3593 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTRACT
3594 && XEXP (XEXP (x, 0), 1) == const1_rtx)
3595 || (GET_CODE (XEXP (x, 0)) == ASHIFTRT
3596 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3597 && INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode) - 1)
3598 || ((temp = get_last_value (XEXP (x, 0))) != 0
3599 && ((GET_CODE (temp) == SIGN_EXTRACT
3600 && XEXP (temp, 1) == const1_rtx)
3601 || (GET_CODE (temp) == ASHIFTRT
3602 && GET_CODE (XEXP (temp, 1)) == CONST_INT
3603 && (INTVAL (XEXP (temp, 1))
3604 == GET_MODE_BITSIZE (mode) - 1)))))
3606 x = gen_rtx_combine (NEG, mode, XEXP (x, 0));
3612 /* (ffs (*_extend <X>)) = (ffs <X>) */
3613 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
3614 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
3615 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3619 /* (float (sign_extend <X>)) = (float <X>). */
3620 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
3621 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
3630 #ifdef SHIFT_COUNT_TRUNCATED
3631 /* (*shift <X> (sign_extend <Y>)) = (*shift <X> <Y>) (most machines).
3632 True for all kinds of shifts and also for zero_extend. */
3633 if ((GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
3634 || GET_CODE (XEXP (x, 1)) == ZERO_EXTEND)
3635 && FAKE_EXTEND_SAFE_P (mode, XEXP (XEXP (x, 1), 0)))
3637 /* This is a perverse SUBREG, wider than its base. */
3638 gen_lowpart_for_combine (mode, XEXP (XEXP (x, 1), 0)));
3640 /* tege: Change (bitshifts ... (and ... mask), c)
3641 to (bitshifts ... c) if mask just masks the bits the bitshift
3642 insns do automatically on this machine. */
3643 if (GET_CODE (XEXP (x, 1)) == AND
3644 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
3645 && (~ INTVAL (XEXP (XEXP (x, 1), 1)) & GET_MODE_MASK (mode)) == 0)
3646 SUBST (XEXP (x, 1), XEXP (XEXP (x, 1), 0));
3649 /* If this is a shift by a constant amount, simplify it. */
3650 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
3652 x = simplify_shift_const (x, code, mode, XEXP (x, 0),
3653 INTVAL (XEXP (x, 1)));
3654 if (GET_CODE (x) != code)
3663 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
3664 operations" because they can be replaced with two more basic operations.
3665 ZERO_EXTEND is also considered "compound" because it can be replaced with
3666 an AND operation, which is simpler, though only one operation.
3668 The function expand_compound_operation is called with an rtx expression
3669 and will convert it to the appropriate shifts and AND operations,
3670 simplifying at each stage.
3672 The function make_compound_operation is called to convert an expression
3673 consisting of shifts and ANDs into the equivalent compound expression.
3674 It is the inverse of this function, loosely speaking. */
3677 expand_compound_operation (x)
3685 switch (GET_CODE (x))
3690 /* We can't necessarily use a const_int for a multiword mode;
3691 it depends on implicitly extending the value.
3692 Since we don't know the right way to extend it,
3693 we can't tell whether the implicit way is right.
3695 Even for a mode that is no wider than a const_int,
3696 we can't win, because we need to sign extend one of its bits through
3697 the rest of it, and we don't know which bit. */
3698 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
3701 if (! FAKE_EXTEND_SAFE_P (GET_MODE (XEXP (x, 0)), XEXP (x, 0)))
3704 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
3705 /* If the inner object has VOIDmode (the only way this can happen
3706 is if it is a ASM_OPERANDS), we can't do anything since we don't
3707 know how much masking to do. */
3716 /* If the operand is a CLOBBER, just return it. */
3717 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
3720 if (GET_CODE (XEXP (x, 1)) != CONST_INT
3721 || GET_CODE (XEXP (x, 2)) != CONST_INT
3722 || GET_MODE (XEXP (x, 0)) == VOIDmode)
3725 len = INTVAL (XEXP (x, 1));
3726 pos = INTVAL (XEXP (x, 2));
3728 /* If this goes outside the object being extracted, replace the object
3729 with a (use (mem ...)) construct that only combine understands
3730 and is used only for this purpose. */
3731 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
3732 SUBST (XEXP (x, 0), gen_rtx (USE, GET_MODE (x), XEXP (x, 0)));
3735 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
3743 /* If we reach here, we want to return a pair of shifts. The inner
3744 shift is a left shift of BITSIZE - POS - LEN bits. The outer
3745 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
3746 logical depending on the value of UNSIGNEDP.
3748 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
3749 converted into an AND of a shift.
3751 We must check for the case where the left shift would have a negative
3752 count. This can happen in a case like (x >> 31) & 255 on machines
3753 that can't shift by a constant. On those machines, we would first
3754 combine the shift with the AND to produce a variable-position
3755 extraction. Then the constant of 31 would be substituted in to produce
3756 a such a position. */
3758 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
3759 if (modewidth >= pos - len)
3760 tem = simplify_shift_const (0, unsignedp ? LSHIFTRT : ASHIFTRT,
3762 simplify_shift_const (0, ASHIFT, GET_MODE (x),
3764 modewidth - pos - len),
3767 else if (unsignedp && len < HOST_BITS_PER_INT)
3768 tem = simplify_and_const_int (0, GET_MODE (x),
3769 simplify_shift_const (0, LSHIFTRT,
3774 /* Any other cases we can't handle. */
3778 /* If we couldn't do this for some reason, return the original
3780 if (GET_CODE (tem) == CLOBBER)
3786 /* X is a SET which contains an assignment of one object into
3787 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
3788 or certain SUBREGS). If possible, convert it into a series of
3791 We half-heartedly support variable positions, but do not at all
3792 support variable lengths. */
3795 expand_field_assignment (x)
3799 rtx pos; /* Always counts from low bit. */
3802 enum machine_mode compute_mode;
3804 /* Loop until we find something we can't simplify. */
3807 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
3808 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
3810 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
3811 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
3814 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3815 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
3817 inner = XEXP (SET_DEST (x), 0);
3818 len = INTVAL (XEXP (SET_DEST (x), 1));
3819 pos = XEXP (SET_DEST (x), 2);
3821 /* If the position is constant and spans the width of INNER,
3822 surround INNER with a USE to indicate this. */
3823 if (GET_CODE (pos) == CONST_INT
3824 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
3825 inner = gen_rtx (USE, GET_MODE (SET_DEST (x)), inner);
3828 if (GET_CODE (pos) == CONST_INT)
3829 pos = gen_rtx (CONST_INT, VOIDmode,
3830 (GET_MODE_BITSIZE (GET_MODE (inner)) - len
3832 else if (GET_CODE (pos) == MINUS
3833 && GET_CODE (XEXP (pos, 1)) == CONST_INT
3834 && (INTVAL (XEXP (pos, 1))
3835 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
3836 /* If position is ADJUST - X, new position is X. */
3837 pos = XEXP (pos, 0);
3839 pos = gen_binary (MINUS, GET_MODE (pos),
3840 gen_rtx (CONST_INT, VOIDmode,
3841 (GET_MODE_BITSIZE (GET_MODE (inner))
3846 /* A SUBREG between two modes that occupy the same numbers of words
3847 can be done by moving the SUBREG to the source. */
3848 else if (GET_CODE (SET_DEST (x)) == SUBREG
3849 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
3850 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
3851 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
3852 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
3854 x = gen_rtx (SET, VOIDmode, SUBREG_REG (SET_DEST (x)),
3855 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (SET_DEST (x))),
3862 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3863 inner = SUBREG_REG (inner);
3865 compute_mode = GET_MODE (inner);
3867 /* Compute a mask of LEN bits, if we can do this on the host machine. */
3868 if (len < HOST_BITS_PER_INT)
3869 mask = gen_rtx (CONST_INT, VOIDmode, (1 << len) - 1);
3873 /* Now compute the equivalent expression. Make a copy of INNER
3874 for the SET_DEST in case it is a MEM into which we will substitute;
3875 we don't want shared RTL in that case. */
3876 x = gen_rtx (SET, VOIDmode, copy_rtx (inner),
3877 gen_binary (IOR, compute_mode,
3878 gen_binary (AND, compute_mode,
3879 gen_unary (NOT, compute_mode,
3884 gen_binary (ASHIFT, compute_mode,
3885 gen_binary (AND, compute_mode,
3886 gen_lowpart_for_combine
3896 /* Return an RTX for a reference to LEN bits of INNER. POS is the starting
3897 bit position (counted from the LSB) if >= 0; otherwise POS_RTX represents
3898 the starting bit position.
3900 INNER may be a USE. This will occur when we started with a bitfield
3901 that went outside the boundary of the object in memory, which is
3902 allowed on most machines. To isolate this case, we produce a USE
3903 whose mode is wide enough and surround the MEM with it. The only
3904 code that understands the USE is this routine. If it is not removed,
3905 it will cause the resulting insn not to match.
3907 UNSIGNEDP is non-zero for an unsigned reference and zero for a
3910 IN_DEST is non-zero if this is a reference in the destination of a
3911 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
3912 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
3915 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
3916 ZERO_EXTRACT should be built even for bits starting at bit 0.
3918 MODE is the desired mode of the result (if IN_DEST == 0). */
3921 make_extraction (mode, inner, pos, pos_rtx, len,
3922 unsignedp, in_dest, in_compare)
3923 enum machine_mode mode;
3929 int in_dest, in_compare;
3931 enum machine_mode is_mode = GET_MODE (inner);
3932 enum machine_mode inner_mode;
3933 enum machine_mode wanted_mem_mode = byte_mode;
3934 enum machine_mode pos_mode = word_mode;
3935 enum machine_mode extraction_mode = word_mode;
3936 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
3940 /* Get some information about INNER and get the innermost object. */
3941 if (GET_CODE (inner) == USE)
3942 /* We don't need to adjust the position because we set up the USE
3943 to pretend that it was a full-word object. */
3944 spans_byte = 1, inner = XEXP (inner, 0);
3945 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
3946 inner = SUBREG_REG (inner);
3948 inner_mode = GET_MODE (inner);
3950 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
3951 pos = INTVAL (pos_rtx);
3953 /* See if this can be done without an extraction. We never can if the
3954 width of the field is not the same as that of some integer mode. For
3955 registers, we can only avoid the extraction if the position is at the
3956 low-order bit and this is either not in the destination or we have the
3957 appropriate STRICT_LOW_PART operation available.
3959 For MEM, we can avoid an extract if the field starts on an appropriate
3960 boundary and we can change the mode of the memory reference. However,
3961 we cannot directly access the MEM if we have a USE and the underlying
3962 MEM is not TMODE. This combination means that MEM was being used in a
3963 context where bits outside its mode were being referenced; that is only
3964 valid in bit-field insns. */
3966 if (tmode != BLKmode
3967 && ! (spans_byte && inner_mode != tmode)
3968 && ((pos == 0 && GET_CODE (inner) == REG
3970 || (movstrict_optab->handlers[(int) tmode].insn_code
3971 != CODE_FOR_nothing)))
3972 || (GET_CODE (inner) == MEM && pos >= 0
3974 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
3975 : BITS_PER_UNIT)) == 0
3976 /* We can't do this if we are widening INNER_MODE (it
3977 may not be aligned, for one thing). */
3978 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
3979 && (inner_mode == tmode
3980 || (! mode_dependent_address_p (XEXP (inner, 0))
3981 && ! MEM_VOLATILE_P (inner))))))
3983 int offset = pos / BITS_PER_UNIT;
3985 /* If INNER is a MEM, make a new MEM that encompasses just the desired
3986 field. If the original and current mode are the same, we need not
3987 adjust the offset. Otherwise, we do if bytes big endian.
3989 If INNER is not a MEM, get a piece consisting of the just the field
3990 of interest (in this case INNER must be a REG and POS must be 0). */
3992 if (GET_CODE (inner) == MEM)
3994 #if BYTES_BIG_ENDIAN
3995 if (inner_mode != tmode)
3996 offset = (GET_MODE_SIZE (inner_mode)
3997 - GET_MODE_SIZE (tmode) - offset);
4000 new = gen_rtx (MEM, tmode, plus_constant (XEXP (inner, 0), offset));
4001 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner);
4002 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (inner);
4003 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (inner);
4006 new = gen_lowpart_for_combine (tmode, inner);
4008 /* If this extraction is going into the destination of a SET,
4009 make a STRICT_LOW_PART unless we made a MEM. */
4012 return (GET_CODE (new) == MEM ? new
4013 : gen_rtx_combine (STRICT_LOW_PART, VOIDmode, new));
4015 /* Otherwise, sign- or zero-extend unless we already are in the
4018 return (mode == tmode ? new
4019 : gen_rtx_combine (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
4023 /* Unless this is in a COMPARE or we have a funny memory reference,
4024 don't do anything with field extracts starting at the low-order
4025 bit since they are simple AND operations. */
4026 if (pos == 0 && ! in_dest && ! in_compare && ! spans_byte)
4029 /* Get the mode to use should INNER be a MEM, the mode for the position,
4030 and the mode for the result. */
4034 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_insv][0];
4035 pos_mode = insn_operand_mode[(int) CODE_FOR_insv][2];
4036 extraction_mode = insn_operand_mode[(int) CODE_FOR_insv][3];
4041 if (! in_dest && unsignedp)
4043 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extzv][1];
4044 pos_mode = insn_operand_mode[(int) CODE_FOR_extzv][3];
4045 extraction_mode = insn_operand_mode[(int) CODE_FOR_extzv][0];
4050 if (! in_dest && ! unsignedp)
4052 wanted_mem_mode = insn_operand_mode[(int) CODE_FOR_extv][1];
4053 pos_mode = insn_operand_mode[(int) CODE_FOR_extv][3];
4054 extraction_mode = insn_operand_mode[(int) CODE_FOR_extv][0];
4058 /* Never narrow an object, since that might not be safe. */
4060 if (mode != VOIDmode
4061 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
4062 extraction_mode = mode;
4064 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
4065 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4066 pos_mode = GET_MODE (pos_rtx);
4068 /* If this is not from memory or we have to change the mode of memory and
4069 cannot, the desired mode is EXTRACTION_MODE. */
4070 if (GET_CODE (inner) != MEM
4071 || (inner_mode != wanted_mem_mode
4072 && (mode_dependent_address_p (XEXP (inner, 0))
4073 || MEM_VOLATILE_P (inner))))
4074 wanted_mem_mode = extraction_mode;
4077 /* If position is constant, compute new position. Otherwise, build
4080 pos = (MAX (GET_MODE_BITSIZE (is_mode), GET_MODE_BITSIZE (wanted_mem_mode))
4084 = gen_rtx_combine (MINUS, GET_MODE (pos_rtx),
4085 gen_rtx (CONST_INT, VOIDmode,
4086 (MAX (GET_MODE_BITSIZE (is_mode),
4087 GET_MODE_BITSIZE (wanted_mem_mode))
4091 /* If INNER has a wider mode, make it smaller. If this is a constant
4092 extract, try to adjust the byte to point to the byte containing
4094 if (wanted_mem_mode != VOIDmode
4095 && GET_MODE_SIZE (wanted_mem_mode) < GET_MODE_SIZE (is_mode)
4096 && ((GET_CODE (inner) == MEM
4097 && (inner_mode == wanted_mem_mode
4098 || (! mode_dependent_address_p (XEXP (inner, 0))
4099 && ! MEM_VOLATILE_P (inner))))))
4103 /* The computations below will be correct if the machine is big
4104 endian in both bits and bytes or little endian in bits and bytes.
4105 If it is mixed, we must adjust. */
4107 #if BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
4108 if (! spans_byte && is_mode != wanted_mem_mode)
4109 offset = (GET_MODE_SIZE (is_mode)
4110 - GET_MODE_SIZE (wanted_mem_mode) - offset);
4113 /* If bytes are big endian and we had a paradoxical SUBREG, we must
4114 adjust OFFSET to compensate. */
4115 #if BYTES_BIG_ENDIAN
4117 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
4118 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
4121 /* If this is a constant position, we can move to the desired byte. */
4124 offset += pos / BITS_PER_UNIT;
4125 pos %= GET_MODE_BITSIZE (wanted_mem_mode);
4128 if (offset != 0 || inner_mode != wanted_mem_mode)
4130 rtx newmem = gen_rtx (MEM, wanted_mem_mode,
4131 plus_constant (XEXP (inner, 0), offset));
4132 RTX_UNCHANGING_P (newmem) = RTX_UNCHANGING_P (inner);
4133 MEM_VOLATILE_P (newmem) = MEM_VOLATILE_P (inner);
4134 MEM_IN_STRUCT_P (newmem) = MEM_IN_STRUCT_P (inner);
4139 /* If INNER is not memory, we can always get it into the proper mode. */
4140 else if (GET_CODE (inner) != MEM)
4141 inner = gen_lowpart_for_combine (extraction_mode, inner);
4143 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
4144 have to zero extend. Otherwise, we can just use a SUBREG. */
4146 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
4147 pos_rtx = gen_rtx_combine (ZERO_EXTEND, pos_mode, pos_rtx);
4149 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
4150 pos_rtx = gen_lowpart_for_combine (pos_mode, pos_rtx);
4152 /* Make POS_RTX unless we already have it and it is correct. */
4153 if (pos_rtx == 0 || (pos >= 0 && INTVAL (pos_rtx) != pos))
4154 pos_rtx = gen_rtx (CONST_INT, VOIDmode, pos);
4156 /* Make the required operation. See if we can use existing rtx. */
4157 new = gen_rtx_combine (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
4158 extraction_mode, inner,
4159 gen_rtx (CONST_INT, VOIDmode, len), pos_rtx);
4161 new = gen_lowpart_for_combine (mode, new);
4166 /* Look at the expression rooted at X. Look for expressions
4167 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
4168 Form these expressions.
4170 Return the new rtx, usually just X.
4172 Also, for machines like the Vax that don't have logical shift insns,
4173 try to convert logical to arithmetic shift operations in cases where
4174 they are equivalent. This undoes the canonicalizations to logical
4175 shifts done elsewhere.
4177 We try, as much as possible, to re-use rtl expressions to save memory.
4179 IN_CODE says what kind of expression we are processing. Normally, it is
4180 SET. In a memory address (inside a MEM or PLUS, the latter being a
4181 kludge), it is MEM. When processing the arguments of a comparison
4182 or a COMPARE against zero, it is COMPARE. */
4185 make_compound_operation (x, in_code)
4187 enum rtx_code in_code;
4189 enum rtx_code code = GET_CODE (x);
4190 enum machine_mode mode = GET_MODE (x);
4191 int mode_width = GET_MODE_BITSIZE (mode);
4192 enum rtx_code next_code;
4197 /* Select the code to be used in recursive calls. Once we are inside an
4198 address, we stay there. If we have a comparison, set to COMPARE,
4199 but once inside, go back to our default of SET. */
4201 next_code = (code == MEM || code == PLUS ? MEM
4202 : ((code == COMPARE || GET_RTX_CLASS (code) == '<')
4203 && XEXP (x, 1) == const0_rtx) ? COMPARE
4204 : in_code == COMPARE ? SET : in_code);
4206 /* Process depending on the code of this operation. If NEW is set
4207 non-zero, it will be returned. */
4213 /* Convert shifts by constants into multiplications if inside
4215 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
4216 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT
4217 && INTVAL (XEXP (x, 1)) >= 0)
4218 new = gen_rtx_combine (MULT, mode, XEXP (x, 0),
4219 gen_rtx (CONST_INT, VOIDmode,
4220 1 << INTVAL (XEXP (x, 1))));
4224 /* If the second operand is not a constant, we can't do anything
4226 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
4229 /* If the constant is a power of two minus one and the first operand
4230 is a logical right shift, make an extraction. */
4231 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4232 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4233 new = make_extraction (mode, XEXP (XEXP (x, 0), 0), -1,
4234 XEXP (XEXP (x, 0), 1), i, 1,
4235 0, in_code == COMPARE);
4237 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
4238 else if (GET_CODE (XEXP (x, 0)) == SUBREG
4239 && subreg_lowpart_p (XEXP (x, 0))
4240 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
4241 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4242 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))),
4243 XEXP (SUBREG_REG (XEXP (x, 0)), 0), -1,
4244 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
4245 0, in_code == COMPARE);
4248 /* If we are have (and (rotate X C) M) and C is larger than the number
4249 of bits in M, this is an extraction. */
4251 else if (GET_CODE (XEXP (x, 0)) == ROTATE
4252 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4253 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
4254 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
4255 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4256 (GET_MODE_BITSIZE (mode)
4257 - INTVAL (XEXP (XEXP (x, 0), 1))),
4258 0, i, 1, 0, in_code == COMPARE);
4260 /* On machines without logical shifts, if the operand of the AND is
4261 a logical shift and our mask turns off all the propagated sign
4262 bits, we can replace the logical shift with an arithmetic shift. */
4274 && GET_CODE (XEXP (x, 0)) == LSHIFTRT
4275 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4276 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
4277 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_INT
4278 && mode_width <= HOST_BITS_PER_INT)
4280 unsigned mask = GET_MODE_MASK (mode);
4282 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
4283 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
4285 gen_rtx_combine (ASHIFTRT, mode, XEXP (XEXP (x, 0), 0),
4286 XEXP (XEXP (x, 0), 1)));
4289 /* If the constant is one less than a power of two, this might be
4290 representable by an extraction even if no shift is present.
4291 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
4292 we are in a COMPARE. */
4293 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
4294 new = make_extraction (mode, XEXP (x, 0), 0, 0, i, 1,
4295 0, in_code == COMPARE);
4297 /* If we are in a comparison and this is an AND with a power of two,
4298 convert this into the appropriate bit extract. */
4299 else if (in_code == COMPARE
4300 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4301 new = make_extraction (mode, XEXP (x, 0), i, 0, 1, 1, 0, 1);
4306 /* If the sign bit is known to be zero, replace this with an
4307 arithmetic shift. */
4319 && mode_width <= HOST_BITS_PER_INT
4320 && (significant_bits (XEXP (x, 0), mode)
4321 & (1 << (mode_width - 1))) == 0)
4323 new = gen_rtx_combine (ASHIFTRT, mode, XEXP (x, 0), XEXP (x, 1));
4327 /* ... fall through ... */
4330 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
4331 this is a SIGN_EXTRACT. */
4332 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4333 && GET_CODE (XEXP (x, 0)) == ASHIFT
4334 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4335 && INTVAL (XEXP (x, 1)) >= INTVAL (XEXP (XEXP (x, 0), 1)))
4336 new = make_extraction (mode, XEXP (XEXP (x, 0), 0),
4337 (INTVAL (XEXP (x, 1))
4338 - INTVAL (XEXP (XEXP (x, 0), 1))),
4339 0, mode_width - INTVAL (XEXP (x, 1)),
4340 code == LSHIFTRT, 0, in_code == COMPARE);
4347 code = GET_CODE (x);
4350 /* Now recursively process each operand of this operation. */
4351 fmt = GET_RTX_FORMAT (code);
4352 for (i = 0; i < GET_RTX_LENGTH (code); i++)
4355 new = make_compound_operation (XEXP (x, i), next_code);
4356 SUBST (XEXP (x, i), new);
4362 /* Given M see if it is a value that would select a field of bits
4363 within an item, but not the entire word. Return -1 if not.
4364 Otherwise, return the starting position of the field, where 0 is the
4367 *PLEN is set to the length of the field. */
4370 get_pos_from_mask (m, plen)
4374 /* Get the bit number of the first 1 bit from the right, -1 if none. */
4375 int pos = exact_log2 (m & - m);
4380 /* Now shift off the low-order zero bits and see if we have a power of
4382 *plen = exact_log2 ((m >> pos) + 1);
4390 /* Rewrite X so that it is an expression in MODE. We only care about the
4391 low-order BITS bits so we can ignore AND operations that just clear
4394 Also, if REG is non-zero and X is a register equal in value to REG,
4395 replace X with REG. */
4398 force_to_mode (x, mode, bits, reg)
4400 enum machine_mode mode;
4404 enum rtx_code code = GET_CODE (x);
4406 /* If X is narrower than MODE or if BITS is larger than the size of MODE,
4407 just get X in the proper mode. */
4409 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
4410 || bits > GET_MODE_BITSIZE (mode))
4411 return gen_lowpart_for_combine (mode, x);
4419 x = expand_compound_operation (x);
4420 if (GET_CODE (x) != code)
4421 return force_to_mode (x, mode, bits, reg);
4425 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
4426 || rtx_equal_p (reg, get_last_value (x))))
4431 if (bits < HOST_BITS_PER_INT)
4432 x = gen_rtx (CONST_INT, VOIDmode, INTVAL (x) & ((1 << bits) - 1));
4436 /* Ignore low-order SUBREGs. */
4437 if (subreg_lowpart_p (x))
4438 return force_to_mode (SUBREG_REG (x), mode, bits, reg);
4442 /* If this is an AND with a constant. Otherwise, we fall through to
4443 do the general binary case. */
4445 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4447 int mask = INTVAL (XEXP (x, 1));
4448 int len = exact_log2 (mask + 1);
4449 rtx op = XEXP (x, 0);
4451 /* If this is masking some low-order bits, we may be able to
4452 impose a stricter constraint on what bits of the operand are
4455 op = force_to_mode (op, mode, len > 0 ? MIN (len, bits) : bits,
4458 if (bits < HOST_BITS_PER_INT)
4459 mask &= (1 << bits) - 1;
4461 x = simplify_and_const_int (x, mode, op, mask);
4463 /* If X is still an AND, see if it is an AND with a mask that
4464 is just some low-order bits. If so, and it is BITS wide (it
4465 can't be wider), we don't need it. */
4467 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
4468 && bits < HOST_BITS_PER_INT
4469 && INTVAL (XEXP (x, 1)) == (1 << bits) - 1)
4474 /* ... fall through ... */
4481 /* For most binary operations, just propagate into the operation and
4484 return gen_binary (code, mode,
4485 force_to_mode (XEXP (x, 0), mode, bits, reg),
4486 force_to_mode (XEXP (x, 1), mode, bits, reg));
4490 /* For left shifts, do the same, but just for the first operand.
4491 If the shift count is a constant, we need even fewer bits of the
4494 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) < bits)
4495 bits -= INTVAL (XEXP (x, 1));
4497 return gen_binary (code, mode,
4498 force_to_mode (XEXP (x, 0), mode, bits, reg),
4502 /* Here we can only do something if the shift count is a constant and
4503 the count plus BITS is no larger than the width of MODE, we can do
4504 the shift in MODE. */
4506 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4507 && INTVAL (XEXP (x, 1)) + bits <= GET_MODE_BITSIZE (mode))
4508 return gen_binary (LSHIFTRT, mode,
4509 force_to_mode (XEXP (x, 0), mode,
4510 bits + INTVAL (XEXP (x, 1)), reg),
4516 /* Handle these similarly to the way we handle most binary operations. */
4517 return gen_unary (code, mode,
4518 force_to_mode (XEXP (x, 0), mode, bits, reg));
4521 /* Otherwise, just do the operation canonically. */
4522 return gen_lowpart_for_combine (mode, x);
4525 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
4526 Return that assignment if so.
4528 We only handle the most common cases. */
4531 make_field_assignment (x)
4534 rtx dest = SET_DEST (x);
4535 rtx src = SET_SRC (x);
4540 enum machine_mode mode;
4542 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
4543 a clear of a one-bit field. We will have changed it to
4544 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
4547 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
4548 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
4549 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
4550 && (rtx_equal_p (dest, XEXP (src, 1))
4551 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4552 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4554 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4556 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
4559 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
4560 && subreg_lowpart_p (XEXP (src, 0))
4561 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
4562 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
4563 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
4564 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
4565 && (rtx_equal_p (dest, XEXP (src, 1))
4566 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4567 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4569 assign = make_extraction (VOIDmode, dest, -1,
4570 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
4572 return gen_rtx (SET, VOIDmode, assign, const0_rtx);
4575 /* If SRC is (ior (ashift (const_int 1) POS DEST)), this is a set of a
4577 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
4578 && XEXP (XEXP (src, 0), 0) == const1_rtx
4579 && (rtx_equal_p (dest, XEXP (src, 1))
4580 || rtx_equal_p (dest, get_last_value (XEXP (src, 1)))
4581 || rtx_equal_p (get_last_value (dest), XEXP (src, 1))))
4583 assign = make_extraction (VOIDmode, dest, -1, XEXP (XEXP (src, 0), 1),
4585 return gen_rtx (SET, VOIDmode, assign, const1_rtx);
4588 /* The other case we handle is assignments into a constant-position
4589 field. They look like (ior (and DEST C1) OTHER). If C1 represents
4590 a mask that has all one bits except for a group of zero bits and
4591 OTHER is known to have zeros where C1 has ones, this is such an
4592 assignment. Compute the position and length from C1. Shift OTHER
4593 to the appropriate position, force it to the required mode, and
4594 make the extraction. Check for the AND in both operands. */
4596 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == AND
4597 && GET_CODE (XEXP (XEXP (src, 0), 1)) == CONST_INT
4598 && (rtx_equal_p (XEXP (XEXP (src, 0), 0), dest)
4599 || rtx_equal_p (XEXP (XEXP (src, 0), 0), get_last_value (dest))
4600 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 0), 1)), dest)))
4601 c1 = INTVAL (XEXP (XEXP (src, 0), 1)), other = XEXP (src, 1);
4602 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 1)) == AND
4603 && GET_CODE (XEXP (XEXP (src, 1), 1)) == CONST_INT
4604 && (rtx_equal_p (XEXP (XEXP (src, 1), 0), dest)
4605 || rtx_equal_p (XEXP (XEXP (src, 1), 0), get_last_value (dest))
4606 || rtx_equal_p (get_last_value (XEXP (XEXP (src, 1), 0)),
4608 c1 = INTVAL (XEXP (XEXP (src, 1), 1)), other = XEXP (src, 0);
4612 pos = get_pos_from_mask (~c1, &len);
4613 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
4614 || (c1 & significant_bits (other, GET_MODE (other))) != 0)
4617 assign = make_extraction (VOIDmode, dest, pos, 0, len, 1, 1, 0);
4619 /* The mode to use for the source is the mode of the assignment, or of
4620 what is inside a possible STRICT_LOW_PART. */
4621 mode = (GET_CODE (assign) == STRICT_LOW_PART
4622 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
4624 /* Shift OTHER right POS places and make it the source, restricting it
4625 to the proper length and mode. */
4627 src = force_to_mode (simplify_shift_const (0, LSHIFTRT, GET_MODE (src),
4631 return gen_rtx_combine (SET, VOIDmode, assign, src);
4634 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
4638 apply_distributive_law (x)
4641 enum rtx_code code = GET_CODE (x);
4642 rtx lhs, rhs, other;
4644 enum rtx_code inner_code;
4646 /* The outer operation can only be one of the following: */
4647 if (code != IOR && code != AND && code != XOR
4648 && code != PLUS && code != MINUS)
4651 lhs = XEXP (x, 0), rhs = XEXP (x, 1);
4653 /* If either operand is a primitive we can't do anything, so get out fast. */
4654 if (GET_RTX_CLASS (GET_CODE (lhs)) == 'o'
4655 || GET_RTX_CLASS (GET_CODE (rhs)) == 'o')
4658 lhs = expand_compound_operation (lhs);
4659 rhs = expand_compound_operation (rhs);
4660 inner_code = GET_CODE (lhs);
4661 if (inner_code != GET_CODE (rhs))
4664 /* See if the inner and outer operations distribute. */
4671 /* These all distribute except over PLUS. */
4672 if (code == PLUS || code == MINUS)
4677 if (code != PLUS && code != MINUS)
4683 /* These are also multiplies, so they distribute over everything. */
4687 /* Non-paradoxical SUBREGs distributes over all operations, provided
4688 the inner modes and word numbers are the same, this is an extraction
4689 of a low-order part, we don't convert an fp operation to int or
4690 vice versa, and we would not be converting a single-word
4691 operation into a multi-word operation. The latter test is not
4692 required, but it prevents generating unneeded multi-word operations.
4693 Some of the previous tests are redundant given the latter test, but
4694 are retained because they are required for correctness.
4696 We produce the result slightly differently in this case. */
4698 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
4699 || SUBREG_WORD (lhs) != SUBREG_WORD (rhs)
4700 || ! subreg_lowpart_p (lhs)
4701 || (GET_MODE_CLASS (GET_MODE (lhs))
4702 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
4703 || (GET_MODE_SIZE (GET_MODE (lhs))
4704 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
4705 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
4708 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
4709 SUBREG_REG (lhs), SUBREG_REG (rhs));
4710 return gen_lowpart_for_combine (GET_MODE (x), tem);
4716 /* Set LHS and RHS to the inner operands (A and B in the example
4717 above) and set OTHER to the common operand (C in the example).
4718 These is only one way to do this unless the inner operation is
4720 if (GET_RTX_CLASS (inner_code) == 'c'
4721 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
4722 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
4723 else if (GET_RTX_CLASS (inner_code) == 'c'
4724 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
4725 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
4726 else if (GET_RTX_CLASS (inner_code) == 'c'
4727 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
4728 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
4729 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
4730 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
4734 /* Form the new inner operation, seeing if it simplifies first. */
4735 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
4737 /* There is one exception to the general way of distributing:
4738 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
4739 if (code == XOR && inner_code == IOR)
4742 other = gen_unary (NOT, GET_MODE (x), other);
4745 /* We may be able to continuing distributing the result, so call
4746 ourselves recursively on the inner operation before forming the
4747 outer operation, which we return. */
4748 return gen_binary (inner_code, GET_MODE (x),
4749 apply_distributive_law (tem), other);
4752 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
4755 Return an equivalent form, if different from X. Otherwise, return X. If
4756 X is zero, we are to always construct the equivalent form. */
4759 simplify_and_const_int (x, mode, varop, constop)
4761 enum machine_mode mode;
4765 register enum machine_mode tmode;
4767 unsigned significant;
4769 /* There is a large class of optimizations based on the principle that
4770 some operations produce results where certain bits are known to be zero,
4771 and hence are not significant to the AND. For example, if we have just
4772 done a left shift of one bit, the low-order bit is known to be zero and
4773 hence an AND with a mask of ~1 would not do anything.
4775 At the end of the following loop, we set:
4777 VAROP to be the item to be AND'ed with;
4778 CONSTOP to the constant value to AND it with. */
4782 /* If we ever encounter a mode wider than the host machine's word
4783 size, we can't compute the masks accurately, so give up. */
4784 if (GET_MODE_BITSIZE (GET_MODE (varop)) > HOST_BITS_PER_INT)
4787 /* Unless one of the cases below does a `continue',
4788 a `break' will be executed to exit the loop. */
4790 switch (GET_CODE (varop))
4793 /* If VAROP is a (clobber (const_int)), return it since we know
4794 we are generating something that won't match. */
4797 #if ! BITS_BIG_ENDIAN
4799 /* VAROP is a (use (mem ..)) that was made from a bit-field
4800 extraction that spanned the boundary of the MEM. If we are
4801 now masking so it is within that boundary, we don't need the
4803 if ((constop & ~ GET_MODE_MASK (GET_MODE (XEXP (varop, 0)))) == 0)
4805 varop = XEXP (varop, 0);
4812 if (subreg_lowpart_p (varop)
4813 /* We can ignore the effect this SUBREG if it narrows the mode
4814 or, on machines where byte operations zero extend, if the
4815 constant masks to zero all the bits the mode doesn't have. */
4816 && ((GET_MODE_SIZE (GET_MODE (varop))
4817 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop))))
4818 #ifdef BYTE_LOADS_ZERO_EXTEND
4820 & GET_MODE_MASK (GET_MODE (varop))
4821 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (varop)))))
4825 varop = SUBREG_REG (varop);
4834 /* Try to expand these into a series of shifts and then work
4835 with that result. If we can't, for example, if the extract
4836 isn't at a fixed position, give up. */
4837 temp = expand_compound_operation (varop);
4846 if (GET_CODE (XEXP (varop, 1)) == CONST_INT)
4848 constop &= INTVAL (XEXP (varop, 1));
4849 varop = XEXP (varop, 0);
4856 /* If VAROP is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
4857 LSHIFT so we end up with an (and (lshiftrt (ior ...) ...) ...)
4858 operation which may be a bitfield extraction. */
4860 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4861 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4862 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4863 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT
4864 && GET_CODE (XEXP (varop, 1)) == CONST_INT
4865 && (INTVAL (XEXP (varop, 1))
4866 & ~ significant_bits (XEXP (varop, 0),
4867 GET_MODE (varop)) == 0))
4869 temp = gen_rtx (CONST_INT, VOIDmode,
4870 ((INTVAL (XEXP (varop, 1)) & constop)
4871 << INTVAL (XEXP (XEXP (varop, 0), 1))));
4872 temp = gen_binary (GET_CODE (varop), GET_MODE (varop),
4873 XEXP (XEXP (varop, 0), 0), temp);
4874 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4875 temp, XEXP (varop, 1));
4879 /* Apply the AND to both branches of the IOR or XOR, then try to
4880 apply the distributive law. This may eliminate operations
4881 if either branch can be simplified because of the AND.
4882 It may also make some cases more complex, but those cases
4883 probably won't match a pattern either with or without this. */
4885 gen_lowpart_for_combine
4886 (mode, apply_distributive_law
4888 (GET_CODE (varop), GET_MODE (varop),
4889 simplify_and_const_int (0, GET_MODE (varop),
4890 XEXP (varop, 0), constop),
4891 simplify_and_const_int (0, GET_MODE (varop),
4892 XEXP (varop, 1), constop))));
4895 /* (and (not FOO)) is (and (xor FOO CONST_OP)) so if FOO is an
4896 LSHIFTRT we can do the same as above. */
4898 if (GET_CODE (XEXP (varop, 0)) == LSHIFTRT
4899 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
4900 && INTVAL (XEXP (XEXP (varop, 0), 1)) >= 0
4901 && INTVAL (XEXP (XEXP (varop, 0), 1)) < HOST_BITS_PER_INT)
4903 temp = gen_rtx (CONST_INT, VOIDmode,
4904 constop << INTVAL (XEXP (XEXP (varop, 0), 1)));
4905 temp = gen_binary (XOR, GET_MODE (varop),
4906 XEXP (XEXP (varop, 0), 0), temp);
4907 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4908 temp, XEXP (XEXP (varop, 0), 1));
4914 /* If we are just looking for the sign bit, we don't need this
4915 shift at all, even if it has a variable count. */
4916 if (constop == 1 << (GET_MODE_BITSIZE (GET_MODE (varop)) - 1))
4918 varop = XEXP (varop, 0);
4922 /* If this is a shift by a constant, get a mask that contains
4923 those bits that are not copies of the sign bit. We then have
4924 two cases: If CONSTOP only includes those bits, this can be
4925 a logical shift, which may allow simplifications. If CONSTOP
4926 is a single-bit field not within those bits, we are requesting
4927 a copy of the sign bit and hence can shift the sign bit to
4928 the appropriate location. */
4929 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4930 && INTVAL (XEXP (varop, 1)) >= 0
4931 && INTVAL (XEXP (varop, 1)) < HOST_BITS_PER_INT)
4935 significant = GET_MODE_MASK (GET_MODE (varop));
4936 significant >>= INTVAL (XEXP (varop, 1));
4938 if ((constop & ~significant) == 0
4939 || (i = exact_log2 (constop)) >= 0)
4941 varop = simplify_shift_const
4942 (varop, LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
4943 i < 0 ? INTVAL (XEXP (varop, 1))
4944 : GET_MODE_BITSIZE (GET_MODE (varop)) - 1 - i);
4945 if (GET_CODE (varop) != ASHIFTRT)
4950 /* If our mask is 1, convert this to a LSHIFTRT. This can be done
4951 even if the shift count isn't a constant. */
4953 varop = gen_rtx_combine (LSHIFTRT, GET_MODE (varop),
4954 XEXP (varop, 0), XEXP (varop, 1));
4958 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is
4959 included in STORE_FLAG_VALUE and FOO has no significant bits
4961 if ((constop & ~ STORE_FLAG_VALUE) == 0
4962 && XEXP (varop, 0) == const0_rtx
4963 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
4965 varop = XEXP (varop, 0);
4971 /* In (and (plus FOO C1) M), if M is a mask that just turns off
4972 low-order bits (as in an alignment operation) and FOO is already
4973 aligned to that boundary, we can convert remove this AND
4974 and possibly the PLUS if it is now adding zero. */
4975 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
4976 && exact_log2 (-constop) >= 0
4977 && (significant_bits (XEXP (varop, 0), mode) & ~ constop) == 0)
4979 varop = plus_constant (XEXP (varop, 0),
4980 INTVAL (XEXP (varop, 1)) & constop);
4985 /* ... fall through ... */
4988 /* In (and (plus (and FOO M1) BAR) M2), if M1 and M2 are one
4989 less than powers of two and M2 is narrower than M1, we can
4990 eliminate the inner AND. This occurs when incrementing
4993 if (GET_CODE (XEXP (varop, 0)) == ZERO_EXTRACT
4994 || GET_CODE (XEXP (varop, 0)) == ZERO_EXTEND)
4995 SUBST (XEXP (varop, 0),
4996 expand_compound_operation (XEXP (varop, 0)));
4998 if (GET_CODE (XEXP (varop, 0)) == AND
4999 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
5000 && exact_log2 (constop + 1) >= 0
5001 && exact_log2 (INTVAL (XEXP (XEXP (varop, 0), 1)) + 1) >= 0
5002 && (~ INTVAL (XEXP (XEXP (varop, 0), 1)) & constop) == 0)
5003 SUBST (XEXP (varop, 0), XEXP (XEXP (varop, 0), 0));
5010 /* If we have reached a constant, this whole thing is constant. */
5011 if (GET_CODE (varop) == CONST_INT)
5012 return gen_rtx (CONST_INT, VOIDmode, constop & INTVAL (varop));
5014 /* See what bits are significant in VAROP. */
5015 significant = significant_bits (varop, mode);
5017 /* Turn off all bits in the constant that are known to already be zero.
5018 Thus, if the AND isn't needed at all, we will have CONSTOP == SIGNIFICANT
5019 which is tested below. */
5021 constop &= significant;
5023 /* If we don't have any bits left, return zero. */
5027 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
5028 if we already had one (just check for the simplest cases). */
5029 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
5030 && GET_MODE (XEXP (x, 0)) == mode
5031 && SUBREG_REG (XEXP (x, 0)) == varop)
5032 varop = XEXP (x, 0);
5034 varop = gen_lowpart_for_combine (mode, varop);
5036 /* If we can't make the SUBREG, try to return what we were given. */
5037 if (GET_CODE (varop) == CLOBBER)
5038 return x ? x : varop;
5040 /* If we are only masking insignificant bits, return VAROP. */
5041 if (constop == significant)
5044 /* Otherwise, return an AND. See how much, if any, of X we can use. */
5045 else if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
5046 x = gen_rtx_combine (AND, mode, varop,
5047 gen_rtx (CONST_INT, VOIDmode, constop));
5051 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5052 || INTVAL (XEXP (x, 1)) != constop)
5053 SUBST (XEXP (x, 1), gen_rtx (CONST_INT, VOIDmode, constop));
5055 SUBST (XEXP (x, 0), varop);
5061 /* Given an expression, X, compute which bits in X can be non-zero.
5062 We don't care about bits outside of those defined in MODE.
5064 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
5065 a shift, AND, or zero_extract, we can do better. */
5068 significant_bits (x, mode)
5070 enum machine_mode mode;
5072 unsigned significant = GET_MODE_MASK (mode);
5075 int mode_width = GET_MODE_BITSIZE (mode);
5078 /* If X is wider than MODE, use its mode instead. */
5079 if (GET_MODE_BITSIZE (GET_MODE (x)) > mode_width)
5081 mode = GET_MODE (x);
5082 significant = GET_MODE_MASK (mode);
5083 mode_width = GET_MODE_BITSIZE (mode);
5086 if (mode_width > HOST_BITS_PER_INT)
5087 /* Our only callers in this case look for single bit values. So
5088 just return the mode mask. Those tests will then be false. */
5091 code = GET_CODE (x);
5095 #ifdef STACK_BOUNDARY
5096 /* If this is the stack pointer, we may know something about its
5097 alignment. If PUSH_ROUNDING is defined, it is possible for the
5098 stack to be momentarily aligned only to that amount, so we pick
5099 the least alignment. */
5101 if (x == stack_pointer_rtx)
5103 int sp_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
5105 #ifdef PUSH_ROUNDING
5106 sp_alignment = MIN (PUSH_ROUNDING (1), sp_alignment);
5109 return significant & ~ (sp_alignment - 1);
5113 /* If X is a register whose value we can find, use that value.
5114 Otherwise, use the previously-computed significant bits for this
5117 tem = get_last_value (x);
5119 return significant_bits (tem, mode);
5120 else if (significant_valid && reg_significant[REGNO (x)])
5121 return reg_significant[REGNO (x)] & significant;
5128 #ifdef BYTE_LOADS_ZERO_EXTEND
5130 /* In many, if not most, RISC machines, reading a byte from memory
5131 zeros the rest of the register. Noticing that fact saves a lot
5132 of extra zero-extends. */
5133 significant &= GET_MODE_MASK (GET_MODE (x));
5137 #if STORE_FLAG_VALUE == 1
5145 /* A comparison operation only sets the bits given by its mode. The
5146 rest are set undefined. */
5147 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5148 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5152 #if STORE_FLAG_VALUE == -1
5154 if (GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<'
5155 || ((tem = get_last_value (XEXP (x, 0))) != 0
5156 && GET_RTX_CLASS (GET_CODE (tem)) == '<'))
5159 if (GET_MODE_SIZE (GET_MODE (x)) < mode_width)
5160 significant |= (GET_MODE_MASK (mode) & ~ GET_MODE_MASK (GET_MODE (x)));
5165 significant &= (significant_bits (XEXP (x, 0), mode)
5166 & GET_MODE_MASK (mode));
5170 significant &= significant_bits (XEXP (x, 0), mode);
5171 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5172 significant &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5176 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
5177 Otherwise, show all the bits in the outer mode but not the inner
5179 inner_sig = significant_bits (XEXP (x, 0), mode);
5180 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
5182 inner_sig &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
5184 (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
5185 inner_sig |= (GET_MODE_MASK (mode)
5186 & ~ GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
5189 significant &= inner_sig;
5193 significant &= (significant_bits (XEXP (x, 0), mode)
5194 & significant_bits (XEXP (x, 1), mode));
5199 significant &= (significant_bits (XEXP (x, 0), mode)
5200 | significant_bits (XEXP (x, 1), mode));
5203 case PLUS: case MINUS:
5205 case DIV: case UDIV:
5206 case MOD: case UMOD:
5207 /* We can apply the rules of arithmetic to compute the number of
5208 high- and low-order zero bits of these operations. We start by
5209 computing the width (position of the highest-order non-zero bit)
5210 and the number of low-order zero bits for each value. */
5212 unsigned sig0 = significant_bits (XEXP (x, 0), mode);
5213 unsigned sig1 = significant_bits (XEXP (x, 1), mode);
5214 int width0 = floor_log2 (sig0) + 1;
5215 int width1 = floor_log2 (sig1) + 1;
5216 int low0 = floor_log2 (sig0 & -sig0);
5217 int low1 = floor_log2 (sig1 & -sig1);
5218 int op0_maybe_minusp = (sig0 & (1 << (mode_width - 1)));
5219 int op1_maybe_minusp = (sig1 & (1 << (mode_width - 1)));
5220 int result_width = mode_width;
5226 result_width = MAX (width0, width1) + 1;
5227 result_low = MIN (low0, low1);
5230 result_low = MIN (low0, low1);
5233 result_width = width0 + width1;
5234 result_low = low0 + low1;
5237 if (! op0_maybe_minusp && ! op1_maybe_minusp)
5238 result_width = width0;
5241 result_width = width0;
5244 if (! op0_maybe_minusp && ! op1_maybe_minusp)
5245 result_width = MIN (width0, width1);
5246 result_low = MIN (low0, low1);
5249 result_width = MIN (width0, width1);
5250 result_low = MIN (low0, low1);
5254 if (result_width < mode_width)
5255 significant &= (1 << result_width) - 1;
5258 significant &= ~ ((1 << result_low) - 1);
5263 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5264 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5265 significant &= (1 << INTVAL (XEXP (x, 1))) - 1;
5269 /* If the inner mode is a single word for both the host and target
5270 machines, we can compute this from which bits of the inner
5271 object are known significant. */
5272 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= BITS_PER_WORD
5273 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x))) <= HOST_BITS_PER_INT)
5275 significant &= significant_bits (SUBREG_REG (x), mode);
5276 #ifndef BYTE_LOADS_ZERO_EXTEND
5277 /* On many CISC machines, accessing an object in a wider mode
5278 causes the high-order bits to become undefined. So they are
5279 not known to be zero. */
5280 if (GET_MODE_SIZE (GET_MODE (x))
5281 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
5282 significant |= (GET_MODE_MASK (GET_MODE (x))
5283 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x))));
5293 /* The significant bits are in two classes: any bits within MODE
5294 that aren't in GET_MODE (x) are always significant. The rest of the
5295 significant bits are those that are significant in the operand of
5296 the shift when shifted the appropriate number of bits. This
5297 shows that high-order bits are cleared by the right shift and
5298 low-order bits by left shifts. */
5299 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5300 && INTVAL (XEXP (x, 1)) >= 0
5301 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_INT)
5303 enum machine_mode inner_mode = GET_MODE (x);
5304 int width = GET_MODE_BITSIZE (inner_mode);
5305 int count = INTVAL (XEXP (x, 1));
5306 unsigned mode_mask = GET_MODE_MASK (inner_mode);
5307 unsigned op_significant = significant_bits (XEXP (x, 0), mode);
5308 unsigned inner = op_significant & mode_mask;
5311 if (mode_width > width)
5312 outer = (op_significant & significant & ~ mode_mask);
5314 if (code == LSHIFTRT)
5316 else if (code == ASHIFTRT)
5320 /* If the sign bit was significant at before the shift, we
5321 need to mark all the places it could have been copied to
5322 by the shift significant. */
5323 if (inner & (1 << (width - 1 - count)))
5324 inner |= ((1 << count) - 1) << (width - count);
5326 else if (code == LSHIFT || code == ASHIFT)
5329 inner = ((inner << (count % width)
5330 | (inner >> (width - (count % width)))) & mode_mask);
5332 significant &= (outer | inner);
5337 /* This is at most the number of bits in the mode. */
5338 significant = (1 << (floor_log2 (mode_width) + 1)) - 1;
5345 /* This function is called from `simplify_shift_const' to merge two
5346 outer operations. Specifically, we have already found that we need
5347 to perform operation *POP0 with constant *PCONST0 at the outermost
5348 position. We would now like to also perform OP1 with constant CONST1
5349 (with *POP0 being done last).
5351 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
5352 the resulting operation. *PCOMP_P is set to 1 if we would need to
5353 complement the innermost operand, otherwise it is unchanged.
5355 MODE is the mode in which the operation will be done. No bits outside
5356 the width of this mode matter. It is assumed that the width of this mode
5357 is smaller than or equal to HOST_BITS_PER_INT.
5359 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
5360 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
5361 result is simply *PCONST0.
5363 If the resulting operation cannot be expressed as one operation, we
5364 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
5367 merge_outer_ops (pop0, pconst0, op1, const1, mode, pcomp_p)
5368 enum rtx_code *pop0;
5372 enum machine_mode mode;
5375 enum rtx_code op0 = *pop0;
5376 int const0 = *pconst0;
5378 const0 &= GET_MODE_MASK (mode);
5379 const1 &= GET_MODE_MASK (mode);
5381 /* If OP0 is an AND, clear unimportant bits in CONST1. */
5385 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
5388 if (op1 == NIL || op0 == SET)
5391 else if (op0 == NIL)
5392 op0 = op1, const0 = const1;
5394 else if (op0 == op1)
5416 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
5417 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
5420 /* If the two constants aren't the same, we can't do anything. The
5421 remaining six cases can all be done. */
5422 else if (const0 != const1)
5430 /* (a & b) | b == b */
5432 else /* op1 == XOR */
5433 /* (a ^ b) | b == a | b */
5439 /* (a & b) ^ b == (~a) & b */
5440 op0 = AND, *pcomp_p = 1;
5441 else /* op1 == IOR */
5442 /* (a | b) ^ b == a & ~b */
5443 op0 = AND, *pconst0 = ~ const0;
5448 /* (a | b) & b == b */
5450 else /* op1 == XOR */
5451 /* (a ^ b) & b) == (~a) & b */
5456 /* Check for NO-OP cases. */
5457 const0 &= GET_MODE_MASK (mode);
5459 && (op0 == IOR || op0 == XOR || op0 == PLUS))
5461 else if (const0 == 0 && op0 == AND)
5463 else if (const0 == GET_MODE_MASK (mode) && op0 == AND)
5472 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
5473 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
5474 that we started with.
5476 The shift is normally computed in the widest mode we find in VAROP, as
5477 long as it isn't a different number of words than RESULT_MODE. Exceptions
5478 are ASHIFTRT and ROTATE, which are always done in their original mode, */
5481 simplify_shift_const (x, code, result_mode, varop, count)
5484 enum machine_mode result_mode;
5488 enum rtx_code orig_code = code;
5489 int orig_count = count;
5490 enum machine_mode mode = result_mode;
5491 enum machine_mode shift_mode, tmode;
5493 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
5494 /* We form (outer_op (code varop count) (outer_const)). */
5495 enum rtx_code outer_op = NIL;
5498 int complement_p = 0;
5501 /* If we were given an invalid count, don't do anything except exactly
5502 what was requested. */
5504 if (count < 0 || count > GET_MODE_BITSIZE (mode))
5509 return gen_rtx (code, mode, varop, gen_rtx (CONST_INT, VOIDmode, count));
5512 /* Unless one of the branches of the `if' in this loop does a `continue',
5513 we will `break' the loop after the `if'. */
5517 /* If we have an operand of (clobber (const_int 0)), just return that
5519 if (GET_CODE (varop) == CLOBBER)
5522 /* If we discovered we had to complement VAROP, leave. Making a NOT
5523 here would cause an infinite loop. */
5527 /* Convert ROTATETRT to ROTATE. */
5528 if (code == ROTATERT)
5529 code = ROTATE, count = GET_MODE_BITSIZE (result_mode) - count;
5531 /* Canonicalize LSHIFT to ASHIFT. */
5535 /* We need to determine what mode we will do the shift in. If the
5536 shift is a ASHIFTRT or ROTATE, we must always do it in the mode it
5537 was originally done in. Otherwise, we can do it in MODE, the widest
5538 mode encountered. */
5539 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
5541 /* Handle cases where the count is greater than the size of the mode
5542 minus 1. For ASHIFT, use the size minus one as the count (this can
5543 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
5544 take the count modulo the size. For other shifts, the result is
5547 Since these shifts are being produced by the compiler by combining
5548 multiple operations, each of which are defined, we know what the
5549 result is supposed to be. */
5551 if (count > GET_MODE_BITSIZE (shift_mode) - 1)
5553 if (code == ASHIFTRT)
5554 count = GET_MODE_BITSIZE (shift_mode) - 1;
5555 else if (code == ROTATE || code == ROTATERT)
5556 count %= GET_MODE_BITSIZE (shift_mode);
5559 /* We can't simply return zero because there may be an
5567 /* Negative counts are invalid and should not have been made (a
5568 programmer-specified negative count should have been handled
5573 /* We simplify the tests below and elsewhere by converting
5574 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
5575 `make_compound_operation' will convert it to a ASHIFTRT for
5576 those machines (such as Vax) that don't have a LSHIFTRT. */
5577 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_INT
5579 && (significant_bits (varop, shift_mode)
5580 & (1 << (GET_MODE_BITSIZE (shift_mode) - 1))) == 0)
5583 switch (GET_CODE (varop))
5589 new = expand_compound_operation (varop);
5598 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
5599 minus the width of a smaller mode, we can do this with a
5600 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
5601 if ((code == ASHIFTRT || code == LSHIFTRT)
5602 && ! mode_dependent_address_p (XEXP (varop, 0))
5603 && ! MEM_VOLATILE_P (varop)
5604 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5605 MODE_INT, 1)) != BLKmode)
5607 #if BYTES_BIG_ENDIAN
5608 new = gen_rtx (MEM, tmode, XEXP (varop, 0));
5610 new = gen_rtx (MEM, tmode,
5611 plus_constant (XEXP (varop, 0),
5612 count / BITS_PER_UNIT));
5613 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop);
5614 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (varop);
5615 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (varop);
5617 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5618 : ZERO_EXTEND, mode, new);
5625 /* Similar to the case above, except that we can only do this if
5626 the resulting mode is the same as that of the underlying
5627 MEM and adjust the address depending on the *bits* endianness
5628 because of the way that bit-field extract insns are defined. */
5629 if ((code == ASHIFTRT || code == LSHIFTRT)
5630 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
5631 MODE_INT, 1)) != BLKmode
5632 && tmode == GET_MODE (XEXP (varop, 0)))
5635 new = XEXP (varop, 0);
5637 new = copy_rtx (XEXP (varop, 0));
5638 SUBST (XEXP (new, 0),
5639 plus_constant (XEXP (new, 0),
5640 count / BITS_PER_UNIT));
5643 varop = gen_rtx_combine (code == ASHIFTRT ? SIGN_EXTEND
5644 : ZERO_EXTEND, mode, new);
5651 /* If VAROP is a SUBREG, strip it as long as the inner operand has
5652 the same number of words as what we've seen so far. Then store
5653 the widest mode in MODE. */
5654 if (SUBREG_WORD (varop) == 0
5655 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
5656 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5659 varop = SUBREG_REG (varop);
5660 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
5661 mode = GET_MODE (varop);
5667 /* Some machines use MULT instead of ASHIFT because MULT
5668 is cheaper. But it is still better on those machines to
5669 merge two shifts into one. */
5670 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5671 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5673 varop = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
5674 gen_rtx (CONST_INT, VOIDmode,
5675 exact_log2 (INTVAL (XEXP (varop, 1)))));
5681 /* Similar, for when divides are cheaper. */
5682 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5683 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
5685 varop = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
5686 gen_rtx (CONST_INT, VOIDmode,
5687 exact_log2 (INTVAL (XEXP (varop, 1)))));
5693 /* If we are extracting just the sign bit of an arithmetic right
5694 shift, that shift is not needed. */
5695 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1)
5697 varop = XEXP (varop, 0);
5701 /* ... fall through ... */
5707 /* Here we have two nested shifts. The result is usually the
5708 AND of a new shift with a mask. We compute the result below. */
5709 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5710 && INTVAL (XEXP (varop, 1)) >= 0
5711 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
5712 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5713 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)
5715 enum rtx_code first_code = GET_CODE (varop);
5716 int first_count = INTVAL (XEXP (varop, 1));
5721 if (first_code == LSHIFT)
5722 first_code = ASHIFT;
5724 /* We have one common special case. We can't do any merging if
5725 the inner code is an ASHIFTRT of a smaller mode. However, if
5726 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
5727 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
5728 we can convert it to
5729 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
5730 This simplifies certain SIGN_EXTEND operations. */
5731 if (code == ASHIFT && first_code == ASHIFTRT
5732 && (GET_MODE_BITSIZE (result_mode)
5733 - GET_MODE_BITSIZE (GET_MODE (varop))) == count)
5735 /* C3 has the low-order C1 bits zero. */
5737 mask = GET_MODE_MASK (mode) & ~ ((1 << first_count) - 1);
5739 varop = simplify_and_const_int (0, result_mode,
5740 XEXP (varop, 0), mask);
5741 varop = simplify_shift_const (0, ASHIFT, result_mode,
5743 count = first_count;
5748 /* If this was (ashiftrt (ashift foo C1) C2) and we know
5749 something about FOO's previous value, we may be able to
5750 optimize this even though the code below can't handle this
5753 If FOO has J high-order bits equal to the sign bit with
5754 J > C1, then we can convert this to either an ASHIFT or
5755 a ASHIFTRT depending on the two counts.
5757 We cannot do this if VAROP's mode is not SHIFT_MODE. */
5759 if (code == ASHIFTRT && first_code == ASHIFT
5760 && GET_MODE (varop) == shift_mode
5761 && (inner = get_last_value (XEXP (varop, 0))) != 0)
5763 if ((GET_CODE (inner) == CONST_INT
5764 && (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == 0
5765 || (INTVAL (inner) >> (HOST_BITS_PER_INT - (first_count + 1)) == -1)))
5766 || (GET_CODE (inner) == SIGN_EXTEND
5767 && ((GET_MODE_BITSIZE (GET_MODE (inner))
5768 - GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner))))
5770 || (GET_CODE (inner) == ASHIFTRT
5771 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5772 && INTVAL (XEXP (inner, 1)) >= first_count))
5774 count -= first_count;
5776 count = - count, code = ASHIFT;
5777 varop = XEXP (varop, 0);
5782 /* There are some cases we can't do. If CODE is ASHIFTRT,
5783 we can only do this if FIRST_CODE is also ASHIFTRT.
5785 We can't do the case when CODE is ROTATE and FIRST_CODE is
5788 If the mode of this shift is not the mode of the outer shift,
5789 we can't do this if either shift is ASHIFTRT or ROTATE.
5791 Finally, we can't do any of these if the mode is too wide
5792 unless the codes are the same.
5794 Handle the case where the shift codes are the same
5797 if (code == first_code)
5799 if (GET_MODE (varop) != result_mode
5800 && (code == ASHIFTRT || code == ROTATE))
5803 count += first_count;
5804 varop = XEXP (varop, 0);
5808 if (code == ASHIFTRT
5809 || (code == ROTATE && first_code == ASHIFTRT)
5810 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_INT
5811 || (GET_MODE (varop) != result_mode
5812 && (first_code == ASHIFTRT || first_code == ROTATE
5813 || code == ROTATE)))
5816 /* To compute the mask to apply after the shift, shift the
5817 significant bits of the inner shift the same way the
5818 outer shift will. */
5820 mask_rtx = gen_rtx (CONST_INT, VOIDmode,
5821 significant_bits (varop, GET_MODE (varop)));
5824 = simplify_binary_operation (code, result_mode, mask_rtx,
5825 gen_rtx (CONST_INT, VOIDmode,
5828 /* Give up if we can't compute an outer operation to use. */
5830 || GET_CODE (mask_rtx) != CONST_INT
5831 || ! merge_outer_ops (&outer_op, &outer_const, AND,
5833 result_mode, &complement_p))
5836 /* If the shifts are in the same direction, we add the
5837 counts. Otherwise, we subtract them. */
5838 if ((code == ASHIFTRT || code == LSHIFTRT)
5839 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
5840 count += first_count;
5842 count -= first_count;
5844 /* If COUNT is positive, the new shift is usually CODE,
5845 except for the two exceptions below, in which case it is
5846 FIRST_CODE. If the count is negative, FIRST_CODE should
5849 && ((first_code == ROTATE && code == ASHIFT)
5850 || (first_code == ASHIFTRT && code == LSHIFTRT)))
5853 code = first_code, count = - count;
5855 varop = XEXP (varop, 0);
5859 /* If we have (A << B << C) for any shift, we can convert this to
5860 (A << C << B). This wins if A is a constant. Only try this if
5861 B is not a constant. */
5863 else if (GET_CODE (varop) == code
5864 && GET_CODE (XEXP (varop, 1)) != CONST_INT
5866 = simplify_binary_operation (code, mode,
5872 varop = gen_rtx_combine (code, mode, new, XEXP (varop, 1));
5879 /* Make this fit the case below. */
5880 varop = gen_rtx_combine (XOR, mode, XEXP (varop, 0),
5881 gen_rtx (CONST_INT, VOIDmode,
5882 GET_MODE_MASK (mode)));
5888 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
5889 with C the size of VAROP - 1 and the shift is logical if
5890 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
5891 we have an (le X 0) operation. If we have an arithmetic shift
5892 and STORE_FLAG_VALUE is 1 or we have a logical shift with
5893 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
5895 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
5896 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
5897 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5898 && (code == LSHIFTRT || code == ASHIFTRT)
5899 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
5900 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
5903 varop = gen_rtx_combine (LE, GET_MODE (varop), XEXP (varop, 1),
5906 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
5907 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
5912 /* If we have (shift (logical)), move the logical to the outside
5913 to allow it to possibly combine with another logical and the
5914 shift to combine with another shift. This also canonicalizes to
5915 what a ZERO_EXTRACT looks like. Also, some machines have
5916 (and (shift)) insns. */
5918 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
5919 && (new = simplify_binary_operation (code, result_mode,
5924 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
5925 INTVAL (new), result_mode, &complement_p))
5927 varop = XEXP (varop, 0);
5931 /* If we can't do that, try to simplify the shift in each arm of the
5932 logical expression, make a new logical expression, and apply
5933 the inverse distributive law. */
5935 rtx lhs = simplify_shift_const (0, code, result_mode,
5936 XEXP (varop, 0), count);
5937 rtx rhs = simplify_shift_const (0, code, result_mode,
5938 XEXP (varop, 1), count);
5940 varop = gen_binary (GET_CODE (varop), result_mode, lhs, rhs);
5941 varop = apply_distributive_law (varop);
5948 /* convert (lshift (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
5949 says that the sign bit can be tested, FOO has mode MODE, C is
5950 GET_MODE_BITSIZE (MODE) - 1, and FOO has only the low-order bit
5953 && XEXP (varop, 1) == const0_rtx
5954 && GET_MODE (XEXP (varop, 0)) == result_mode
5955 && count == GET_MODE_BITSIZE (result_mode) - 1
5956 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_INT
5957 && ((STORE_FLAG_VALUE
5958 & (1 << (GET_MODE_BITSIZE (result_mode) - 1))))
5959 && significant_bits (XEXP (varop, 0), result_mode) == 1
5960 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
5961 result_mode, &complement_p))
5963 varop = XEXP (varop, 0);
5970 /* If we are doing an arithmetic right shift of something known
5971 to be -1 or 0, we don't need the shift. */
5972 if (code == ASHIFTRT
5973 && significant_bits (XEXP (varop, 0), result_mode) == 1)
5979 /* NEG commutes with ASHIFT since it is multiplication. Move the
5980 NEG outside to allow shifts to combine. */
5982 && merge_outer_ops (&outer_op, &outer_const, NEG, 0,
5983 result_mode, &complement_p))
5985 varop = XEXP (varop, 0);
5991 /* Similar to case above. If X is 0 or 1 then X - 1 is -1 or 0. */
5992 if (XEXP (varop, 1) == constm1_rtx && code == ASHIFTRT
5993 && significant_bits (XEXP (varop, 0), result_mode) == 1)
5999 /* If we have the same operands as above but we are shifting the
6000 sign bit into the low-order bit, we are exclusive-or'ing
6001 the operand of the PLUS with a one. */
6002 if (code == LSHIFTRT && count == GET_MODE_BITSIZE (result_mode) - 1
6003 && XEXP (varop, 1) == constm1_rtx
6004 && significant_bits (XEXP (varop, 0), result_mode) == 1
6005 && merge_outer_ops (&outer_op, &outer_const, XOR, 1,
6006 result_mode, &complement_p))
6009 varop = XEXP (varop, 0);
6013 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
6015 && GET_CODE (XEXP (varop, 1)) == CONST_INT
6016 && (new = simplify_binary_operation (ASHIFT, result_mode,
6021 && merge_outer_ops (&outer_op, &outer_const, PLUS,
6022 INTVAL (new), result_mode, &complement_p))
6024 varop = XEXP (varop, 0);
6030 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
6031 with C the size of VAROP - 1 and the shift is logical if
6032 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
6033 we have a (gt X 0) operation. If the shift is arithmetic with
6034 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
6035 we have a (neg (gt X 0)) operation. */
6037 if (GET_CODE (XEXP (varop, 0)) == ASHIFTRT
6038 && count == GET_MODE_BITSIZE (GET_MODE (varop)) - 1
6039 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6040 && (code == LSHIFTRT || code == ASHIFTRT)
6041 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
6042 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
6043 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
6046 varop = gen_rtx_combine (GT, GET_MODE (varop), XEXP (varop, 1),
6049 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
6050 varop = gen_rtx_combine (NEG, GET_MODE (varop), varop);
6060 /* We need to determine what mode to do the shift in. If the shift is
6061 a ASHIFTRT or ROTATE, we must always do it in the mode it was originally
6062 done in. Otherwise, we can do it in MODE, the widest mode encountered.
6063 The code we care about is that of the shift that will actually be done,
6064 not the shift that was originally requested. */
6065 shift_mode = (code == ASHIFTRT || code == ROTATE ? result_mode : mode);
6067 /* We have now finished analyzing the shift. The result should be
6068 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
6069 OUTER_OP is non-NIL, it is an operation that needs to be applied
6070 to the result of the shift. OUTER_CONST is the relevant constant,
6071 but we must turn off all bits turned off in the shift.
6073 If we were passed a value for X, see if we can use any pieces of
6074 it. If not, make new rtx. */
6076 if (x && GET_RTX_CLASS (GET_CODE (x)) == '2'
6077 && GET_CODE (XEXP (x, 1)) == CONST_INT
6078 && INTVAL (XEXP (x, 1)) == count)
6079 const_rtx = XEXP (x, 1);
6081 const_rtx = gen_rtx (CONST_INT, VOIDmode, count);
6083 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
6084 && GET_MODE (XEXP (x, 0)) == shift_mode
6085 && SUBREG_REG (XEXP (x, 0)) == varop)
6086 varop = XEXP (x, 0);
6087 else if (GET_MODE (varop) != shift_mode)
6088 varop = gen_lowpart_for_combine (shift_mode, varop);
6090 /* If we can't make the SUBREG, try to return what we were given. */
6091 if (GET_CODE (varop) == CLOBBER)
6092 return x ? x : varop;
6094 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
6099 if (x == 0 || GET_CODE (x) != code || GET_MODE (x) != shift_mode)
6100 x = gen_rtx_combine (code, shift_mode, varop, const_rtx);
6102 SUBST (XEXP (x, 0), varop);
6103 SUBST (XEXP (x, 1), const_rtx);
6106 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
6107 turn off all the bits that the shift would have turned off. */
6108 if (orig_code == LSHIFTRT && result_mode != shift_mode)
6109 x = simplify_and_const_int (0, shift_mode, x,
6110 GET_MODE_MASK (result_mode) >> orig_count);
6112 /* Do the remainder of the processing in RESULT_MODE. */
6113 x = gen_lowpart_for_combine (result_mode, x);
6115 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
6118 x = gen_unary (NOT, result_mode, x);
6120 if (outer_op != NIL)
6122 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_INT)
6123 outer_const &= GET_MODE_MASK (result_mode);
6125 if (outer_op == AND)
6126 x = simplify_and_const_int (0, result_mode, x, outer_const);
6127 else if (outer_op == SET)
6128 /* This means that we have determined that the result is
6129 equivalent to a constant. This should be rare. */
6130 x = gen_rtx (CONST_INT, VOIDmode, outer_const);
6131 else if (GET_RTX_CLASS (outer_op) == '1')
6132 x = gen_unary (outer_op, result_mode, x);
6134 x = gen_binary (outer_op, result_mode, x,
6135 gen_rtx (CONST_INT, VOIDmode, outer_const));
6141 /* Like recog, but we receive the address of a pointer to a new pattern.
6142 We try to match the rtx that the pointer points to.
6143 If that fails, we may try to modify or replace the pattern,
6144 storing the replacement into the same pointer object.
6146 Modifications include deletion or addition of CLOBBERs.
6148 PNOTES is a pointer to a location where any REG_UNUSED notes added for
6149 the CLOBBERs are placed.
6151 The value is the final insn code from the pattern ultimately matched,
6155 recog_for_combine (pnewpat, insn, pnotes)
6160 register rtx pat = *pnewpat;
6161 int insn_code_number;
6162 int num_clobbers_to_add = 0;
6166 /* Is the result of combination a valid instruction? */
6167 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6169 /* If it isn't, there is the possibility that we previously had an insn
6170 that clobbered some register as a side effect, but the combined
6171 insn doesn't need to do that. So try once more without the clobbers
6172 unless this represents an ASM insn. */
6174 if (insn_code_number < 0 && ! check_asm_operands (pat)
6175 && GET_CODE (pat) == PARALLEL)
6179 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
6180 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
6183 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
6187 SUBST_INT (XVECLEN (pat, 0), pos);
6190 pat = XVECEXP (pat, 0, 0);
6192 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
6195 /* If we had any clobbers to add, make a new pattern than contains
6196 them. Then check to make sure that all of them are dead. */
6197 if (num_clobbers_to_add)
6199 rtx newpat = gen_rtx (PARALLEL, VOIDmode,
6200 gen_rtvec (GET_CODE (pat) == PARALLEL
6201 ? XVECLEN (pat, 0) + num_clobbers_to_add
6202 : num_clobbers_to_add + 1));
6204 if (GET_CODE (pat) == PARALLEL)
6205 for (i = 0; i < XVECLEN (pat, 0); i++)
6206 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
6208 XVECEXP (newpat, 0, 0) = pat;
6210 add_clobbers (newpat, insn_code_number);
6212 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
6213 i < XVECLEN (newpat, 0); i++)
6215 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) == REG
6216 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
6218 notes = gen_rtx (EXPR_LIST, REG_UNUSED,
6219 XEXP (XVECEXP (newpat, 0, i), 0), notes);
6227 return insn_code_number;
6230 /* Like gen_lowpart but for use by combine. In combine it is not possible
6231 to create any new pseudoregs. However, it is safe to create
6232 invalid memory addresses, because combine will try to recognize
6233 them and all they will do is make the combine attempt fail.
6235 If for some reason this cannot do its job, an rtx
6236 (clobber (const_int 0)) is returned.
6237 An insn containing that will not be recognized. */
6242 gen_lowpart_for_combine (mode, x)
6243 enum machine_mode mode;
6248 if (GET_MODE (x) == mode)
6251 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
6252 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6254 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
6255 won't know what to do. So we will strip off the SUBREG here and
6256 process normally. */
6257 if (GET_CODE (x) == SUBREG && GET_CODE (SUBREG_REG (x)) == MEM)
6260 if (GET_MODE (x) == mode)
6264 result = gen_lowpart_common (mode, x);
6268 if (GET_CODE (x) == MEM)
6270 register int offset = 0;
6273 /* Refuse to work on a volatile memory ref or one with a mode-dependent
6275 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
6276 return gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
6278 /* If we want to refer to something bigger than the original memref,
6279 generate a perverse subreg instead. That will force a reload
6280 of the original memref X. */
6281 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
6282 return gen_rtx (SUBREG, mode, x, 0);
6284 #if WORDS_BIG_ENDIAN
6285 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
6286 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
6288 #if BYTES_BIG_ENDIAN
6289 /* Adjust the address so that the address-after-the-data
6291 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
6292 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
6294 new = gen_rtx (MEM, mode, plus_constant (XEXP (x, 0), offset));
6295 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x);
6296 MEM_VOLATILE_P (new) = MEM_VOLATILE_P (x);
6297 MEM_IN_STRUCT_P (new) = MEM_IN_STRUCT_P (x);
6301 /* If X is a comparison operator, rewrite it in a new mode. This
6302 probably won't match, but may allow further simplifications. */
6303 else if (GET_RTX_CLASS (GET_CODE (x)) == '<')
6304 return gen_rtx_combine (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
6306 /* If we couldn't simplify X any other way, just enclose it in a
6307 SUBREG. Normally, this SUBREG won't match, but some patterns may
6308 include an explicit SUBREG or we may simplify it further in combine. */
6313 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
6314 word = ((GET_MODE_SIZE (GET_MODE (x))
6315 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD))
6317 return gen_rtx (SUBREG, mode, x, word);
6321 /* Make an rtx expression. This is a subset of gen_rtx and only supports
6322 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
6324 If the identical expression was previously in the insn (in the undobuf),
6325 it will be returned. Only if it is not found will a new expression
6330 gen_rtx_combine (va_alist)
6335 enum machine_mode mode;
6343 code = va_arg (p, enum rtx_code);
6344 mode = va_arg (p, enum machine_mode);
6345 n_args = GET_RTX_LENGTH (code);
6346 fmt = GET_RTX_FORMAT (code);
6348 if (n_args == 0 || n_args > 3)
6351 /* Get each arg and verify that it is supposed to be an expression. */
6352 for (j = 0; j < n_args; j++)
6357 args[j] = va_arg (p, rtx);
6360 /* See if this is in undobuf. Be sure we don't use objects that came
6361 from another insn; this could produce circular rtl structures. */
6363 for (i = previous_num_undos; i < undobuf.num_undo; i++)
6364 if (!undobuf.undo[i].is_int
6365 && GET_CODE (undobuf.undo[i].old_contents) == code
6366 && GET_MODE (undobuf.undo[i].old_contents) == mode)
6368 for (j = 0; j < n_args; j++)
6369 if (XEXP (undobuf.undo[i].old_contents, j) != args[j])
6373 return undobuf.undo[i].old_contents;
6376 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
6377 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
6378 rt = rtx_alloc (code);
6379 PUT_MODE (rt, mode);
6380 XEXP (rt, 0) = args[0];
6383 XEXP (rt, 1) = args[1];
6385 XEXP (rt, 2) = args[2];
6390 /* These routines make binary and unary operations by first seeing if they
6391 fold; if not, a new expression is allocated. */
6394 gen_binary (code, mode, op0, op1)
6396 enum machine_mode mode;
6401 if (GET_RTX_CLASS (code) == '<')
6403 enum machine_mode op_mode = GET_MODE (op0);
6404 if (op_mode == VOIDmode)
6405 op_mode = GET_MODE (op1);
6406 result = simplify_relational_operation (code, op_mode, op0, op1);
6409 result = simplify_binary_operation (code, mode, op0, op1);
6414 /* Put complex operands first and constants second. */
6415 if (GET_RTX_CLASS (code) == 'c'
6416 && ((CONSTANT_P (op0) && GET_CODE (op1) != CONST_INT)
6417 || (GET_RTX_CLASS (GET_CODE (op0)) == 'o'
6418 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')
6419 || (GET_CODE (op0) == SUBREG
6420 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0))) == 'o'
6421 && GET_RTX_CLASS (GET_CODE (op1)) != 'o')))
6422 return gen_rtx_combine (code, mode, op1, op0);
6424 return gen_rtx_combine (code, mode, op0, op1);
6428 gen_unary (code, mode, op0)
6430 enum machine_mode mode;
6433 rtx result = simplify_unary_operation (code, mode, op0, mode);
6438 return gen_rtx_combine (code, mode, op0);
6441 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
6442 comparison code that will be tested.
6444 The result is a possibly different comparison code to use. *POP0 and
6445 *POP1 may be updated.
6447 It is possible that we might detect that a comparison is either always
6448 true or always false. However, we do not perform general constant
6449 folding in combine, so this knowledge isn't useful. Such tautologies
6450 should have been detected earlier. Hence we ignore all such cases. */
6452 static enum rtx_code
6453 simplify_comparison (code, pop0, pop1)
6462 enum machine_mode mode, tmode;
6464 /* Try a few ways of applying the same transformation to both operands. */
6467 /* If both operands are the same constant shift, see if we can ignore the
6468 shift. We can if the shift is a rotate or if the bits shifted out of
6469 this shift are not significant for either input and if the type of
6470 comparison is compatible with the shift. */
6471 if (GET_CODE (op0) == GET_CODE (op1)
6472 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6473 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
6474 || ((GET_CODE (op0) == LSHIFTRT
6475 || GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6476 && (code != GT && code != LT && code != GE && code != LE))
6477 || (GET_CODE (op0) == ASHIFTRT
6478 && (code != GTU && code != LTU
6479 && code != GEU && code != GEU)))
6480 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6481 && INTVAL (XEXP (op0, 1)) >= 0
6482 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
6483 && XEXP (op0, 1) == XEXP (op1, 1))
6485 enum machine_mode mode = GET_MODE (op0);
6486 unsigned mask = GET_MODE_MASK (mode);
6487 int shift_count = INTVAL (XEXP (op0, 1));
6489 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
6490 mask &= (mask >> shift_count) << shift_count;
6491 else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFT)
6492 mask = (mask & (mask << shift_count)) >> shift_count;
6494 if ((significant_bits (XEXP (op0, 0), mode) & ~ mask) == 0
6495 && (significant_bits (XEXP (op1, 0), mode) & ~ mask) == 0)
6496 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
6501 /* If both operands are AND's of a paradoxical SUBREG by constant, the
6502 SUBREGs are of the same mode, and, in both cases, the AND would
6503 be redundant if the comparison was done in the narrower mode,
6504 do the comparison in the narrower mode (e.g., we are AND'ing with 1
6505 and the operand's significant bits are 0xffffff01; in that case if
6506 we only care about QImode, we don't need the AND). This case occurs
6507 if the output mode of an scc insn is not SImode and
6508 STORE_FLAG_VALUE == 1 (e.g., the 386). */
6510 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
6511 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6512 && GET_CODE (XEXP (op1, 1)) == CONST_INT
6513 && GET_CODE (XEXP (op0, 0)) == SUBREG
6514 && GET_CODE (XEXP (op1, 0)) == SUBREG
6515 && (GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)))
6516 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0, 0)))))
6517 && (GET_MODE (SUBREG_REG (XEXP (op0, 0)))
6518 == GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6519 && (significant_bits (SUBREG_REG (XEXP (op0, 0)),
6520 GET_MODE (SUBREG_REG (XEXP (op0, 0))))
6521 & ~ INTVAL (XEXP (op0, 1))) == 0
6522 && (significant_bits (SUBREG_REG (XEXP (op1, 0)),
6523 GET_MODE (SUBREG_REG (XEXP (op1, 0))))
6524 & ~ INTVAL (XEXP (op1, 1))) == 0)
6526 op0 = SUBREG_REG (XEXP (op0, 0));
6527 op1 = SUBREG_REG (XEXP (op1, 0));
6529 /* the resulting comparison is always unsigned since we masked off
6530 the original sign bit. */
6531 code = unsigned_condition (code);
6537 /* If the first operand is a constant, swap the operands and adjust the
6538 comparison code appropriately. */
6539 if (CONSTANT_P (op0))
6541 tem = op0, op0 = op1, op1 = tem;
6542 code = swap_condition (code);
6545 /* We now enter a loop during which we will try to simplify the comparison.
6546 For the most part, we only are concerned with comparisons with zero,
6547 but some things may really be comparisons with zero but not start
6548 out looking that way. */
6550 while (GET_CODE (op1) == CONST_INT)
6552 enum machine_mode mode = GET_MODE (op0);
6553 int mode_width = GET_MODE_BITSIZE (mode);
6554 unsigned mask = GET_MODE_MASK (mode);
6555 int equality_comparison_p;
6556 int sign_bit_comparison_p;
6557 int unsigned_comparison_p;
6560 /* We only want to handle integral modes. This catches VOIDmode,
6561 CCmode, and the floating-point modes. An exception is that we
6562 can handle VOIDmode if OP0 is a COMPARE or a comparison
6565 if (GET_MODE_CLASS (mode) != MODE_INT
6566 && ! (mode == VOIDmode
6567 && (GET_CODE (op0) == COMPARE
6568 || GET_RTX_CLASS (GET_CODE (op0)) == '<')))
6571 /* Get the constant we are comparing against and turn off all bits
6572 not on in our mode. */
6573 const_op = INTVAL (op1);
6574 if (mode_width <= HOST_BITS_PER_INT)
6575 const_op &= GET_MODE_MASK (mode);
6577 /* If we are comparing against a constant power of two and the value
6578 being compared has only that single significant bit (e.g., it was
6579 `and'ed with that bit), we can replace this with a comparison
6582 && (code == EQ || code == NE || code == GE || code == GEU
6583 || code == LT || code == LTU)
6584 && mode_width <= HOST_BITS_PER_INT
6585 && exact_log2 (const_op) >= 0
6586 && significant_bits (op0, mode) == const_op)
6588 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
6589 op1 = const0_rtx, const_op = 0;
6592 /* Do some canonicalizations based on the comparison code. We prefer
6593 comparisons against zero and then prefer equality comparisons. */
6598 /* < 1 is equivalent to <= 0 */
6604 /* ... fall through to LE case below. */
6610 /* <= -1 is equivalent to < 0 */
6611 if (op1 == constm1_rtx)
6612 op1 = const0_rtx, const_op = 0, code = LT;
6614 /* If we are doing a <= 0 comparison on a value known to have
6615 a zero sign bit, we can replace this with == 0. */
6616 else if (const_op == 0
6617 && mode_width <= HOST_BITS_PER_INT
6618 && (significant_bits (op0, mode)
6619 & (1 << (mode_width - 1))) == 0)
6624 /* >= 1 is equivalent to > 0. */
6630 /* ... fall through to GT below. */
6636 /* > -1 is equivalent to >= 0. */
6637 if (op1 == constm1_rtx)
6638 op1 = const0_rtx, const_op = 0, code = GE;
6640 /* If we are doing a > 0 comparison on a value known to have
6641 a zero sign bit, we can replace this with != 0. */
6642 else if (const_op == 0
6643 && mode_width <= HOST_BITS_PER_INT
6644 && (significant_bits (op0, mode)
6645 & (1 << (mode_width - 1))) == 0)
6650 /* unsigned >= 1 is equivalent to != 0 */
6652 op1 = const0_rtx, const_op = 0, code = NE;
6656 /* unsigned < 1 is equivalent to == 0 */
6658 op1 = const0_rtx, const_op = 0, code = EQ;
6662 /* unsigned <= 0 is equivalent to == 0 */
6668 /* unsigned > 0 is equivalent to != 0 */
6674 /* Compute some predicates to simplify code below. */
6676 equality_comparison_p = (code == EQ || code == NE);
6677 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
6678 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
6681 /* Now try cases based on the opcode of OP0. If none of the cases
6682 does a "continue", we exit this loop immediately after the
6685 switch (GET_CODE (op0))
6688 /* If we are extracting a single bit from a variable position in
6689 a constant that has only a single bit set and are comparing it
6690 with zero, we can convert this into an equality comparison
6691 between the position and the location of the single bit. We can't
6692 do this if bit endian and we don't have an extzv since we then
6693 can't know what mode to use for the endianness adjustment. */
6695 #if ! BITS_BIG_ENDIAN || defined (HAVE_extzv)
6696 if (GET_CODE (XEXP (op0, 0)) == CONST_INT
6697 && XEXP (op0, 1) == const1_rtx
6698 && equality_comparison_p && const_op == 0
6699 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
6702 i = (GET_MODE_BITSIZE
6703 (insn_operand_mode[(int) CODE_FOR_extzv][1]) - 1 - i);
6706 op0 = XEXP (op0, 2);
6707 op1 = gen_rtx (CONST_INT, VOIDmode, i);
6710 /* Result is nonzero iff shift count is equal to I. */
6711 code = reverse_condition (code);
6716 /* ... fall through ... */
6719 tem = expand_compound_operation (op0);
6728 /* If testing for equality, we can take the NOT of the constant. */
6729 if (equality_comparison_p
6730 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
6732 op0 = XEXP (op0, 0);
6737 /* If just looking at the sign bit, reverse the sense of the
6739 if (sign_bit_comparison_p)
6741 op0 = XEXP (op0, 0);
6742 code = (code == GE ? LT : GE);
6748 /* If testing for equality, we can take the NEG of the constant. */
6749 if (equality_comparison_p
6750 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
6752 op0 = XEXP (op0, 0);
6757 /* The remaining cases only apply to comparisons with zero. */
6761 /* When X is ABS or is known positive,
6762 (neg X) is < 0 if and only if X != 0. */
6764 if (sign_bit_comparison_p
6765 && (GET_CODE (XEXP (op0, 0)) == ABS
6766 || (mode_width <= HOST_BITS_PER_INT
6767 && (significant_bits (XEXP (op0, 0), mode)
6768 & (1 << (mode_width - 1))) == 0)))
6770 op0 = XEXP (op0, 0);
6771 code = (code == LT ? NE : EQ);
6775 /* If we have NEG of something that is the result of a
6776 SIGN_EXTEND, SIGN_EXTRACT, or ASHIFTRT, we know that the
6777 two high-order bits must be the same and hence that
6778 "(-a) < 0" is equivalent to "a > 0". Otherwise, we can't
6780 if (GET_CODE (XEXP (op0, 0)) == SIGN_EXTEND
6781 || (GET_CODE (XEXP (op0, 0)) == SIGN_EXTRACT
6782 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6783 && (INTVAL (XEXP (XEXP (op0, 0), 1))
6784 < GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (op0, 0), 0)))))
6785 || (GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6786 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6787 && XEXP (XEXP (op0, 0), 1) != const0_rtx)
6788 || ((tem = get_last_value (XEXP (op0, 0))) != 0
6789 && (GET_CODE (tem) == SIGN_EXTEND
6790 || (GET_CODE (tem) == SIGN_EXTRACT
6791 && GET_CODE (XEXP (tem, 1)) == CONST_INT
6792 && (INTVAL (XEXP (tem, 1))
6793 < GET_MODE_BITSIZE (GET_MODE (XEXP (tem, 0)))))
6794 || (GET_CODE (tem) == ASHIFTRT
6795 && GET_CODE (XEXP (tem, 1)) == CONST_INT
6796 && XEXP (tem, 1) != const0_rtx))))
6798 op0 = XEXP (op0, 0);
6799 code = swap_condition (code);
6805 /* If we are testing equality and our count is a constant, we
6806 can perform the inverse operation on our RHS. */
6807 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6808 && (tem = simplify_binary_operation (ROTATERT, mode,
6809 op1, XEXP (op0, 1))) != 0)
6811 op0 = XEXP (op0, 0);
6816 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
6817 a particular bit. Convert it to an AND of a constant of that
6818 bit. This will be converted into a ZERO_EXTRACT. */
6819 if (const_op == 0 && sign_bit_comparison_p
6820 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6821 && mode_width <= HOST_BITS_PER_INT)
6823 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
6824 1 << (mode_width - 1
6825 - INTVAL (XEXP (op0, 1))));
6826 code = (code == LT ? NE : EQ);
6830 /* ... fall through ... */
6833 /* ABS is ignorable inside an equality comparison with zero. */
6834 if (const_op == 0 && equality_comparison_p)
6836 op0 = XEXP (op0, 0);
6843 /* Can simplify (compare (zero/sign_extend FOO) CONST)
6844 to (compare FOO CONST) if CONST fits in FOO's mode and we
6845 are either testing inequality or have an unsigned comparison
6846 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
6847 if (! unsigned_comparison_p
6848 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6849 <= HOST_BITS_PER_INT)
6850 && ((unsigned) const_op
6851 < (1 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1))))
6853 op0 = XEXP (op0, 0);
6859 /* If the inner mode is smaller and we are extracting the low
6860 part, we can treat the SUBREG as if it were a ZERO_EXTEND. */
6861 if (! subreg_lowpart_p (op0)
6862 || GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) >= mode_width)
6865 /* ... fall through ... */
6868 if ((unsigned_comparison_p || equality_comparison_p)
6869 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
6870 <= HOST_BITS_PER_INT)
6871 && ((unsigned) const_op
6872 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
6874 op0 = XEXP (op0, 0);
6880 /* (eq (plus X C1) C2) -> (eq X (minus C2 C1)). We can only do
6881 this for equality comparisons due to pathological cases involving
6883 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
6884 && (tem = simplify_binary_operation (MINUS, mode, op1,
6885 XEXP (op0, 1))) != 0)
6887 op0 = XEXP (op0, 0);
6892 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
6893 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
6894 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
6896 op0 = XEXP (XEXP (op0, 0), 0);
6897 code = (code == LT ? EQ : NE);
6903 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
6904 of bits in X minus 1, is one iff X > 0. */
6905 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
6906 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
6907 && INTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
6908 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
6910 op0 = XEXP (op0, 1);
6911 code = (code == GE ? LE : GT);
6917 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
6918 if C is zero or B is a constant. */
6919 if (equality_comparison_p
6920 && 0 != (tem = simplify_binary_operation (XOR, mode,
6921 XEXP (op0, 1), op1)))
6923 op0 = XEXP (op0, 0);
6930 case LT: case LTU: case LE: case LEU:
6931 case GT: case GTU: case GE: case GEU:
6932 /* We can't do anything if OP0 is a condition code value, rather
6933 than an actual data value. */
6936 || XEXP (op0, 0) == cc0_rtx
6938 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
6941 /* Get the two operands being compared. */
6942 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
6943 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
6945 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
6947 /* Check for the cases where we simply want the result of the
6948 earlier test or the opposite of that result. */
6950 || (code == EQ && reversible_comparison_p (op0))
6951 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
6952 && (STORE_FLAG_VALUE
6953 & (1 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1)))
6955 || (code == GE && reversible_comparison_p (op0)))))
6957 code = (code == LT || code == NE
6958 ? GET_CODE (op0) : reverse_condition (GET_CODE (op0)));
6959 op0 = tem, op1 = tem1;
6965 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
6967 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
6968 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
6969 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
6971 op0 = XEXP (op0, 1);
6972 code = (code == GE ? GT : LE);
6978 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
6979 will be converted to a ZERO_EXTRACT later. */
6980 if (const_op == 0 && equality_comparison_p
6981 && (GET_CODE (XEXP (op0, 0)) == ASHIFT
6982 || GET_CODE (XEXP (op0, 0)) == LSHIFT)
6983 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
6985 op0 = simplify_and_const_int
6986 (op0, mode, gen_rtx_combine (LSHIFTRT, mode,
6988 XEXP (XEXP (op0, 0), 1)),
6993 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
6994 zero and X is a comparison and C1 and C2 describe only bits set
6995 in STORE_FLAG_VALUE, we can compare with X. */
6996 if (const_op == 0 && equality_comparison_p
6997 && mode_width <= HOST_BITS_PER_INT
6998 && GET_CODE (XEXP (op0, 1)) == CONST_INT
6999 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
7000 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
7001 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
7002 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_INT)
7004 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
7005 << INTVAL (XEXP (XEXP (op0, 0), 1)));
7006 if ((~ STORE_FLAG_VALUE & mask) == 0
7007 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0, 0), 0))) == '<'
7008 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
7009 && GET_RTX_CLASS (GET_CODE (tem)) == '<')))
7011 op0 = XEXP (XEXP (op0, 0), 0);
7016 /* If we are doing an equality comparison of an AND of a bit equal
7017 to the sign bit, replace this with a LT or GE comparison of
7018 the underlying value. */
7019 if (equality_comparison_p
7021 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7022 && mode_width <= HOST_BITS_PER_INT
7023 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
7024 == 1 << (mode_width - 1)))
7026 op0 = XEXP (op0, 0);
7027 code = (code == EQ ? GE : LT);
7031 /* If this AND operation is really a ZERO_EXTEND from a narrower
7032 mode, the constant fits within that mode, and this is either an
7033 equality or unsigned comparison, try to do this comparison in
7034 the narrower mode. */
7035 if ((equality_comparison_p || unsigned_comparison_p)
7036 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7037 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
7038 & GET_MODE_MASK (mode))
7040 && const_op >> i == 0
7041 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
7043 op0 = gen_lowpart_for_combine (tmode, XEXP (op0, 0));
7050 /* If we have (compare (xshift FOO N) (const_int C)) and
7051 the high order N bits of FOO (N+1 if an inequality comparison)
7052 are not significant, we can do this by comparing FOO with C
7053 shifted right N bits so long as the low-order N bits of C are
7055 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7056 && INTVAL (XEXP (op0, 1)) >= 0
7057 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
7058 < HOST_BITS_PER_INT)
7059 && (const_op & ~ ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7060 && mode_width <= HOST_BITS_PER_INT
7061 && (significant_bits (XEXP (op0, 0), mode)
7062 & ~ (mask >> (INTVAL (XEXP (op0, 1))
7063 + ! equality_comparison_p))) == 0)
7065 const_op >>= INTVAL (XEXP (op0, 1));
7066 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7067 op0 = XEXP (op0, 0);
7071 /* If we are doing a sign bit comparison, it means we are testing
7072 a particular bit. Convert it to the appropriate AND. */
7073 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
7074 && mode_width <= HOST_BITS_PER_INT)
7076 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0),
7077 1 << ( mode_width - 1
7078 - INTVAL (XEXP (op0, 1))));
7079 code = (code == LT ? NE : EQ);
7083 /* If this an equality comparison with zero and we are shifting
7084 the low bit to the sign bit, we can convert this to an AND of the
7086 if (const_op == 0 && equality_comparison_p
7087 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7088 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7090 op0 = simplify_and_const_int (0, mode, XEXP (op0, 0), 1);
7096 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
7097 do the comparison in a narrower mode. */
7098 if (! unsigned_comparison_p
7099 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7100 && GET_CODE (XEXP (op0, 0)) == ASHIFT
7101 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
7102 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
7103 MODE_INT, 1)) != VOIDmode
7104 && ((unsigned) const_op <= GET_MODE_MASK (tmode)
7105 || (unsigned) - const_op <= GET_MODE_MASK (tmode)))
7107 op0 = gen_lowpart_for_combine (tmode, XEXP (XEXP (op0, 0), 0));
7111 /* ... fall through ... */
7113 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
7114 the low order N bits of FOO are not significant, we can do this
7115 by comparing FOO with C shifted left N bits so long as no
7117 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
7118 && INTVAL (XEXP (op0, 1)) >= 0
7119 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_INT
7120 && mode_width <= HOST_BITS_PER_INT
7121 && (significant_bits (XEXP (op0, 0), mode)
7122 & ((1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
7124 || (floor_log2 (const_op) + INTVAL (XEXP (op0, 1))
7127 const_op <<= INTVAL (XEXP (op0, 1));
7128 op1 = gen_rtx (CONST_INT, VOIDmode, const_op);
7129 op0 = XEXP (op0, 0);
7133 /* If we are using this shift to extract just the sign bit, we
7134 can replace this with an LT or GE comparison. */
7136 && (equality_comparison_p || sign_bit_comparison_p)
7137 && GET_CODE (XEXP (op0, 1)) == CONST_INT
7138 && INTVAL (XEXP (op0, 1)) == mode_width - 1)
7140 op0 = XEXP (op0, 0);
7141 code = (code == NE || code == GT ? LT : GE);
7150 /* Now make any compound operations involved in this comparison. Then,
7151 check for an outmost SUBREG on OP0 that isn't doing anything or is
7152 paradoxical. The latter case can only occur when it is known that the
7153 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
7154 We can never remove a SUBREG for a non-equality comparison because the
7155 sign bit is in a different place in the underlying object. */
7157 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
7158 op1 = make_compound_operation (op1, SET);
7160 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7161 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7162 && (code == NE || code == EQ)
7163 && ((GET_MODE_SIZE (GET_MODE (op0))
7164 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))))
7166 op0 = SUBREG_REG (op0);
7167 op1 = gen_lowpart_for_combine (GET_MODE (op0), op1);
7170 else if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
7171 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
7172 && (code == NE || code == EQ)
7173 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_INT
7174 && (significant_bits (SUBREG_REG (op0), GET_MODE (SUBREG_REG (op0)))
7175 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0
7176 && (tem = gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0)),
7178 (significant_bits (tem, GET_MODE (SUBREG_REG (op0)))
7179 & ~ GET_MODE_MASK (GET_MODE (op0))) == 0))
7180 op0 = SUBREG_REG (op0), op1 = tem;
7182 /* We now do the opposite procedure: Some machines don't have compare
7183 insns in all modes. If OP0's mode is an integer mode smaller than a
7184 word and we can't do a compare in that mode, see if there is a larger
7185 mode for which we can do the compare and where the only significant
7186 bits in OP0 and OP1 are those in the narrower mode. We can do
7187 this if this is an equality comparison, in which case we can
7188 merely widen the operation, or if we are testing the sign bit, in
7189 which case we can explicitly put in the test. */
7191 mode = GET_MODE (op0);
7192 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
7193 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
7194 && cmp_optab->handlers[(int) mode].insn_code == CODE_FOR_nothing)
7195 for (tmode = GET_MODE_WIDER_MODE (mode);
7196 tmode != VOIDmode && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_INT;
7197 tmode = GET_MODE_WIDER_MODE (tmode))
7198 if (cmp_optab->handlers[(int) tmode].insn_code != CODE_FOR_nothing
7199 && (significant_bits (op0, tmode) & ~ GET_MODE_MASK (mode)) == 0
7200 && (significant_bits (op1, tmode) & ~ GET_MODE_MASK (mode)) == 0
7201 && (code == EQ || code == NE
7202 || (op1 == const0_rtx && (code == LT || code == GE)
7203 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_INT)))
7205 op0 = gen_lowpart_for_combine (tmode, op0);
7206 op1 = gen_lowpart_for_combine (tmode, op1);
7208 if (code == LT || code == GE)
7210 op0 = gen_binary (AND, tmode, op0,
7211 gen_rtx (CONST_INT, VOIDmode,
7212 1 << (GET_MODE_BITSIZE (mode) - 1)));
7213 code = (code == LT) ? NE : EQ;
7225 /* Return 1 if we know that X, a comparison operation, is not operating
7226 on a floating-point value or is EQ or NE, meaning that we can safely
7230 reversible_comparison_p (x)
7233 if (TARGET_FLOAT_FORMAT != IEEE_FLOAT_FORMAT
7234 || GET_CODE (x) == NE || GET_CODE (x) == EQ)
7237 switch (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))))
7243 x = get_last_value (XEXP (x, 0));
7244 return (x && GET_CODE (x) == COMPARE
7245 && GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) == MODE_INT);
7251 /* Utility function for following routine. Called when X is part of a value
7252 being stored into reg_last_set_value. Sets reg_last_set_table_tick
7253 for each register mentioned. Similar to mention_regs in cse.c */
7256 update_table_tick (x)
7259 register enum rtx_code code = GET_CODE (x);
7260 register char *fmt = GET_RTX_FORMAT (code);
7265 int regno = REGNO (x);
7266 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7267 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7269 for (i = regno; i < endregno; i++)
7270 reg_last_set_table_tick[i] = label_tick;
7275 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7276 /* Note that we can't have an "E" in values stored; see
7277 get_last_value_validate. */
7279 update_table_tick (XEXP (x, i));
7282 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
7283 are saying that the register is clobbered and we no longer know its
7284 value. If INSN is zero, don't update reg_last_set; this call is normally
7285 done with VALUE also zero to invalidate the register. */
7288 record_value_for_reg (reg, insn, value)
7293 int regno = REGNO (reg);
7294 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7295 ? HARD_REGNO_NREGS (regno, GET_MODE (reg)) : 1);
7298 /* If VALUE contains REG and we have a previous value for REG, substitute
7299 the previous value. */
7300 if (value && insn && reg_overlap_mentioned_p (reg, value))
7304 /* Set things up so get_last_value is allowed to see anything set up to
7306 subst_low_cuid = INSN_CUID (insn);
7307 tem = get_last_value (reg);
7310 value = replace_rtx (copy_rtx (value), reg, tem);
7313 /* For each register modified, show we don't know its value, that
7314 its value has been updated, and that we don't know the location of
7315 the death of the register. */
7316 for (i = regno; i < endregno; i ++)
7319 reg_last_set[i] = insn;
7320 reg_last_set_value[i] = 0;
7321 reg_last_death[i] = 0;
7324 /* Mark registers that are being referenced in this value. */
7326 update_table_tick (value);
7328 /* Now update the status of each register being set.
7329 If someone is using this register in this block, set this register
7330 to invalid since we will get confused between the two lives in this
7331 basic block. This makes using this register always invalid. In cse, we
7332 scan the table to invalidate all entries using this register, but this
7333 is too much work for us. */
7335 for (i = regno; i < endregno; i++)
7337 reg_last_set_label[i] = label_tick;
7338 if (value && reg_last_set_table_tick[i] == label_tick)
7339 reg_last_set_invalid[i] = 1;
7341 reg_last_set_invalid[i] = 0;
7344 /* The value being assigned might refer to X (like in "x++;"). In that
7345 case, we must replace it with (clobber (const_int 0)) to prevent
7347 if (value && ! get_last_value_validate (&value,
7348 reg_last_set_label[regno], 0))
7350 value = copy_rtx (value);
7351 if (! get_last_value_validate (&value, reg_last_set_label[regno], 1))
7355 /* For the main register being modified, update the value. */
7356 reg_last_set_value[regno] = value;
7360 /* Used for communication between the following two routines. */
7361 static rtx record_dead_insn;
7363 /* Called via note_stores from record_dead_and_set_regs to handle one
7364 SET or CLOBBER in an insn. */
7367 record_dead_and_set_regs_1 (dest, setter)
7370 if (GET_CODE (dest) == REG)
7372 /* If we are setting the whole register, we know its value. Otherwise
7373 show that we don't know the value. We can handle SUBREG in
7375 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
7376 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
7377 else if (GET_CODE (setter) == SET
7378 && GET_CODE (SET_DEST (setter)) == SUBREG
7379 && SUBREG_REG (SET_DEST (setter)) == dest
7380 && subreg_lowpart_p (SET_DEST (setter)))
7381 record_value_for_reg
7382 (dest, record_dead_insn,
7383 gen_lowpart_for_combine (GET_MODE (SET_DEST (setter)),
7386 record_value_for_reg (dest, record_dead_insn, 0);
7388 else if (GET_CODE (dest) == MEM
7389 /* Ignore pushes, they clobber nothing. */
7390 && ! push_operand (dest, GET_MODE (dest)))
7391 mem_last_set = INSN_CUID (record_dead_insn);
7394 /* Update the records of when each REG was most recently set or killed
7395 for the things done by INSN. This is the last thing done in processing
7396 INSN in the combiner loop.
7398 We update reg_last_set, reg_last_set_value, reg_last_death, and also the
7399 similar information mem_last_set (which insn most recently modified memory)
7400 and last_call_cuid (which insn was the most recent subroutine call). */
7403 record_dead_and_set_regs (insn)
7407 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7409 if (REG_NOTE_KIND (link) == REG_DEAD)
7410 reg_last_death[REGNO (XEXP (link, 0))] = insn;
7411 else if (REG_NOTE_KIND (link) == REG_INC)
7412 record_value_for_reg (XEXP (link, 0), insn, 0);
7415 if (GET_CODE (insn) == CALL_INSN)
7416 last_call_cuid = mem_last_set = INSN_CUID (insn);
7418 record_dead_insn = insn;
7419 note_stores (PATTERN (insn), record_dead_and_set_regs_1);
7422 /* Utility routine for the following function. Verify that all the registers
7423 mentioned in *LOC are valid when *LOC was part of a value set when
7424 label_tick == TICK. Return 0 if some are not.
7426 If REPLACE is non-zero, replace the invalid reference with
7427 (clobber (const_int 0)) and return 1. This replacement is useful because
7428 we often can get useful information about the form of a value (e.g., if
7429 it was produced by a shift that always produces -1 or 0) even though
7430 we don't know exactly what registers it was produced from. */
7433 get_last_value_validate (loc, tick, replace)
7439 char *fmt = GET_RTX_FORMAT (GET_CODE (x));
7440 int len = GET_RTX_LENGTH (GET_CODE (x));
7443 if (GET_CODE (x) == REG)
7445 int regno = REGNO (x);
7446 int endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7447 ? HARD_REGNO_NREGS (regno, GET_MODE (x)) : 1);
7450 for (j = regno; j < endregno; j++)
7451 if (reg_last_set_invalid[j]
7452 /* If this is a pseudo-register that was only set once, it is
7454 || (! (regno >= FIRST_PSEUDO_REGISTER && reg_n_sets[regno] == 1)
7455 && reg_last_set_label[j] > tick))
7458 *loc = gen_rtx (CLOBBER, GET_MODE (x), const0_rtx);
7465 for (i = 0; i < len; i++)
7467 && get_last_value_validate (&XEXP (x, i), tick, replace) == 0)
7468 /* Don't bother with these. They shouldn't occur anyway. */
7472 /* If we haven't found a reason for it to be invalid, it is valid. */
7476 /* Get the last value assigned to X, if known. Some registers
7477 in the value may be replaced with (clobber (const_int 0)) if their value
7478 is known longer known reliably. */
7487 /* If this is a non-paradoxical SUBREG, get the value of its operand and
7488 then convert it to the desired mode. If this is a paradoxical SUBREG,
7489 we cannot predict what values the "extra" bits might have. */
7490 if (GET_CODE (x) == SUBREG
7491 && subreg_lowpart_p (x)
7492 && (GET_MODE_SIZE (GET_MODE (x))
7493 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7494 && (value = get_last_value (SUBREG_REG (x))) != 0)
7495 return gen_lowpart_for_combine (GET_MODE (x), value);
7497 if (GET_CODE (x) != REG)
7501 value = reg_last_set_value[regno];
7503 /* If we don't have a value, it isn't for this basic block, or if it was
7504 set in a later insn that the ones we are processing, return 0. */
7507 || (reg_n_sets[regno] != 1
7508 && (reg_last_set_label[regno] != label_tick
7509 || INSN_CUID (reg_last_set[regno]) >= subst_low_cuid)))
7512 /* If the value has all its register valid, return it. */
7513 if (get_last_value_validate (&value, reg_last_set_label[regno], 0))
7516 /* Otherwise, make a copy and replace any invalid register with
7517 (clobber (const_int 0)). If that fails for some reason, return 0. */
7519 value = copy_rtx (value);
7520 if (get_last_value_validate (&value, reg_last_set_label[regno], 1))
7526 /* Return nonzero if expression X refers to a REG or to memory
7527 that is set in an instruction more recent than FROM_CUID. */
7530 use_crosses_set_p (x, from_cuid)
7536 register enum rtx_code code = GET_CODE (x);
7540 register int regno = REGNO (x);
7541 #ifdef PUSH_ROUNDING
7542 /* Don't allow uses of the stack pointer to be moved,
7543 because we don't know whether the move crosses a push insn. */
7544 if (regno == STACK_POINTER_REGNUM)
7547 return (reg_last_set[regno]
7548 && INSN_CUID (reg_last_set[regno]) > from_cuid);
7551 if (code == MEM && mem_last_set > from_cuid)
7554 fmt = GET_RTX_FORMAT (code);
7556 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7561 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7562 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
7565 else if (fmt[i] == 'e'
7566 && use_crosses_set_p (XEXP (x, i), from_cuid))
7572 /* Define three variables used for communication between the following
7575 static int reg_dead_regno, reg_dead_endregno;
7576 static int reg_dead_flag;
7578 /* Function called via note_stores from reg_dead_at_p.
7580 If DEST is within [reg_dead_rengno, reg_dead_endregno), set
7581 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
7584 reg_dead_at_p_1 (dest, x)
7588 int regno, endregno;
7590 if (GET_CODE (dest) != REG)
7593 regno = REGNO (dest);
7594 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
7595 ? HARD_REGNO_NREGS (regno, GET_MODE (dest)) : 1);
7597 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
7598 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
7601 /* Return non-zero if REG is known to be dead at INSN.
7603 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
7604 referencing REG, it is dead. If we hit a SET referencing REG, it is
7605 live. Otherwise, see if it is live or dead at the start of the basic
7609 reg_dead_at_p (reg, insn)
7615 /* Set variables for reg_dead_at_p_1. */
7616 reg_dead_regno = REGNO (reg);
7617 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
7618 ? HARD_REGNO_NREGS (reg_dead_regno,
7624 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
7625 beginning of function. */
7626 for (; insn && GET_CODE (insn) != CODE_LABEL;
7627 insn = prev_nonnote_insn (insn))
7629 note_stores (PATTERN (insn), reg_dead_at_p_1);
7631 return reg_dead_flag == 1 ? 1 : 0;
7633 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
7637 /* Get the basic block number that we were in. */
7642 for (block = 0; block < n_basic_blocks; block++)
7643 if (insn == basic_block_head[block])
7646 if (block == n_basic_blocks)
7650 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
7651 if (basic_block_live_at_start[block][i / HOST_BITS_PER_INT]
7652 & (1 << (i % HOST_BITS_PER_INT)))
7658 /* Remove register number REGNO from the dead registers list of INSN.
7660 Return the note used to record the death, if there was one. */
7663 remove_death (regno, insn)
7667 register rtx note = find_regno_note (insn, REG_DEAD, regno);
7670 remove_note (insn, note);
7675 /* For each register (hardware or pseudo) used within expression X, if its
7676 death is in an instruction with cuid between FROM_CUID (inclusive) and
7677 TO_INSN (exclusive), put a REG_DEAD note for that register in the
7678 list headed by PNOTES.
7680 This is done when X is being merged by combination into TO_INSN. These
7681 notes will then be distributed as needed. */
7684 move_deaths (x, from_cuid, to_insn, pnotes)
7691 register int len, i;
7692 register enum rtx_code code = GET_CODE (x);
7696 register int regno = REGNO (x);
7697 register rtx where_dead = reg_last_death[regno];
7699 if (where_dead && INSN_CUID (where_dead) >= from_cuid
7700 && INSN_CUID (where_dead) < INSN_CUID (to_insn))
7702 rtx note = remove_death (regno, reg_last_death[regno]);
7704 /* It is possible for the call above to return 0. This can occur
7705 when reg_last_death points to I2 or I1 that we combined with.
7706 In that case make a new note. */
7710 XEXP (note, 1) = *pnotes;
7714 *pnotes = gen_rtx (EXPR_LIST, REG_DEAD, x, *pnotes);
7720 else if (GET_CODE (x) == SET)
7722 rtx dest = SET_DEST (x);
7724 move_deaths (SET_SRC (x), from_cuid, to_insn, pnotes);
7726 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
7727 that accesses one word of a multi-word item, some
7728 piece of everything register in the expression is used by
7729 this insn, so remove any old death. */
7731 if (GET_CODE (dest) == ZERO_EXTRACT
7732 || GET_CODE (dest) == STRICT_LOW_PART
7733 || (GET_CODE (dest) == SUBREG
7734 && (((GET_MODE_SIZE (GET_MODE (dest))
7735 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
7736 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
7737 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
7739 move_deaths (dest, from_cuid, to_insn, pnotes);
7743 /* If this is some other SUBREG, we know it replaces the entire
7744 value, so use that as the destination. */
7745 if (GET_CODE (dest) == SUBREG)
7746 dest = SUBREG_REG (dest);
7748 /* If this is a MEM, adjust deaths of anything used in the address.
7749 For a REG (the only other possibility), the entire value is
7750 being replaced so the old value is not used in this insn. */
7752 if (GET_CODE (dest) == MEM)
7753 move_deaths (XEXP (dest, 0), from_cuid, to_insn, pnotes);
7757 else if (GET_CODE (x) == CLOBBER)
7760 len = GET_RTX_LENGTH (code);
7761 fmt = GET_RTX_FORMAT (code);
7763 for (i = 0; i < len; i++)
7768 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7769 move_deaths (XVECEXP (x, i, j), from_cuid, to_insn, pnotes);
7771 else if (fmt[i] == 'e')
7772 move_deaths (XEXP (x, i), from_cuid, to_insn, pnotes);
7776 /* Return 1 if X is the target of a bit-field assignment in BODY, the
7777 pattern of an insn. X must be a REG. */
7780 reg_bitfield_target_p (x, body)
7786 if (GET_CODE (body) == SET)
7788 rtx dest = SET_DEST (body);
7790 int regno, tregno, endregno, endtregno;
7792 if (GET_CODE (dest) == ZERO_EXTRACT)
7793 target = XEXP (dest, 0);
7794 else if (GET_CODE (dest) == STRICT_LOW_PART)
7795 target = SUBREG_REG (XEXP (dest, 0));
7799 if (GET_CODE (target) == SUBREG)
7800 target = SUBREG_REG (target);
7802 if (GET_CODE (target) != REG)
7805 tregno = REGNO (target), regno = REGNO (x);
7806 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
7809 endtregno = tregno + HARD_REGNO_NREGS (tregno, GET_MODE (target));
7810 endregno = regno + HARD_REGNO_NREGS (regno, GET_MODE (x));
7812 return endregno > tregno && regno < endtregno;
7815 else if (GET_CODE (body) == PARALLEL)
7816 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
7817 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
7823 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
7824 as appropriate. I3 and I2 are the insns resulting from the combination
7825 insns including FROM (I2 may be zero).
7827 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
7828 not need REG_DEAD notes because they are being substituted for. This
7829 saves searching in the most common cases.
7831 Each note in the list is either ignored or placed on some insns, depending
7832 on the type of note. */
7835 distribute_notes (notes, from_insn, i3, i2, elim_i2, elim_i1)
7839 rtx elim_i2, elim_i1;
7841 rtx note, next_note;
7844 for (note = notes; note; note = next_note)
7846 rtx place = 0, place2 = 0;
7848 /* If this NOTE references a pseudo register, ensure it references
7849 the latest copy of that register. */
7850 if (XEXP (note, 0) && GET_CODE (XEXP (note, 0)) == REG
7851 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
7852 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
7854 next_note = XEXP (note, 1);
7855 switch (REG_NOTE_KIND (note))
7858 /* If this register is set or clobbered in I3, put the note there
7859 unless there is one already. */
7860 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
7862 if (! (GET_CODE (XEXP (note, 0)) == REG
7863 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
7864 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
7867 /* Otherwise, if this register is used by I3, then this register
7868 now dies here, so we must put a REG_DEAD note here unless there
7870 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
7871 && ! (GET_CODE (XEXP (note, 0)) == REG
7872 ? find_regno_note (i3, REG_DEAD, REGNO (XEXP (note, 0)))
7873 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
7875 PUT_REG_NOTE_KIND (note, REG_DEAD);
7883 /* These notes say something about results of an insn. We can
7884 only support them if they used to be on I3 in which case they
7885 remain on I3. Otherwise they are ignored. */
7886 if (from_insn == i3)
7891 case REG_NO_CONFLICT:
7893 /* These notes say something about how a register is used. They must
7894 be present on any use of the register in I2 or I3. */
7895 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
7898 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
7908 /* It is too much trouble to try to see if this note is still
7909 correct in all situations. It is better to simply delete it. */
7913 /* If the insn previously containing this note still exists,
7914 put it back where it was. Otherwise move it to the previous
7915 insn. Adjust the corresponding REG_LIBCALL note. */
7916 if (GET_CODE (from_insn) != NOTE)
7920 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, 0);
7921 place = prev_real_insn (from_insn);
7923 XEXP (tem, 0) = place;
7928 /* This is handled similarly to REG_RETVAL. */
7929 if (GET_CODE (from_insn) != NOTE)
7933 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, 0);
7934 place = next_real_insn (from_insn);
7936 XEXP (tem, 0) = place;
7941 /* If the register is used as an input in I3, it dies there.
7942 Similarly for I2, if it is non-zero and adjacent to I3.
7944 If the register is not used as an input in either I3 or I2
7945 and it is not one of the registers we were supposed to eliminate,
7946 there are two possibilities. We might have a non-adjacent I2
7947 or we might have somehow eliminated an additional register
7948 from a computation. For example, we might have had A & B where
7949 we discover that B will always be zero. In this case we will
7950 eliminate the reference to A.
7952 In both cases, we must search to see if we can find a previous
7953 use of A and put the death note there. */
7955 if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
7957 else if (i2 != 0 && next_nonnote_insn (i2) == i3
7958 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
7961 if (XEXP (note, 0) == elim_i2 || XEXP (note, 0) == elim_i1)
7965 for (tem = prev_nonnote_insn (i3);
7966 tem && (GET_CODE (tem) == INSN
7967 || GET_CODE (tem) == CALL_INSN);
7968 tem = prev_nonnote_insn (tem))
7970 /* If the register is being set at TEM, see if that is all
7971 TEM is doing. If so, delete TEM. Otherwise, make this
7972 into a REG_UNUSED note instead. */
7973 if (reg_set_p (XEXP (note, 0), PATTERN (tem)))
7975 rtx set = single_set (tem);
7977 /* Verify that it was the set, and not a clobber that
7978 modified the register. */
7980 if (set != 0 && ! side_effects_p (SET_SRC (set))
7981 && rtx_equal_p (XEXP (note, 0), SET_DEST (set)))
7983 /* Move the notes and links of TEM elsewhere.
7984 This might delete other dead insns recursively.
7985 First set the pattern to something that won't use
7988 PATTERN (tem) = pc_rtx;
7990 distribute_notes (REG_NOTES (tem), tem, tem, 0, 0, 0);
7991 distribute_links (LOG_LINKS (tem));
7993 PUT_CODE (tem, NOTE);
7994 NOTE_LINE_NUMBER (tem) = NOTE_INSN_DELETED;
7995 NOTE_SOURCE_FILE (tem) = 0;
7999 PUT_REG_NOTE_KIND (note, REG_UNUSED);
8001 /* If there isn't already a REG_UNUSED note, put one
8003 if (! find_regno_note (tem, REG_UNUSED,
8004 REGNO (XEXP (note, 0))))
8009 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem)))
8016 /* If the register is set or already dead at PLACE, we needn't do
8017 anything with this note if it is still a REG_DEAD note.
8019 Note that we cannot use just `dead_or_set_p' here since we can
8020 convert an assignment to a register into a bit-field assignment.
8021 Therefore, we must also omit the note if the register is the
8022 target of a bitfield assignment. */
8024 if (place && REG_NOTE_KIND (note) == REG_DEAD)
8026 int regno = REGNO (XEXP (note, 0));
8028 if (dead_or_set_p (place, XEXP (note, 0))
8029 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
8031 /* Unless the register previously died in PLACE, clear
8032 reg_last_death. [I no longer understand why this is
8034 if (reg_last_death[regno] != place)
8035 reg_last_death[regno] = 0;
8039 reg_last_death[regno] = place;
8041 /* If this is a death note for a hard reg that is occupying
8042 multiple registers, ensure that we are still using all
8043 parts of the object. If we find a piece of the object
8044 that is unused, we must add a USE for that piece before
8045 PLACE and put the appropriate REG_DEAD note on it.
8047 An alternative would be to put a REG_UNUSED for the pieces
8048 on the insn that set the register, but that can't be done if
8049 it is not in the same block. It is simpler, though less
8050 efficient, to add the USE insns. */
8052 if (place && regno < FIRST_PSEUDO_REGISTER
8053 && HARD_REGNO_NREGS (regno, GET_MODE (XEXP (note, 0))) > 1)
8056 = regno + HARD_REGNO_NREGS (regno,
8057 GET_MODE (XEXP (note, 0)));
8061 for (i = regno; i < endregno; i++)
8062 if (! refers_to_regno_p (i, i + 1, PATTERN (place), 0))
8064 rtx piece = gen_rtx (REG, word_mode, i);
8067 /* See if we already placed a USE note for this
8068 register in front of PLACE. */
8070 GET_CODE (PREV_INSN (p)) == INSN
8071 && GET_CODE (PATTERN (PREV_INSN (p))) == USE;
8073 if (rtx_equal_p (piece,
8074 XEXP (PATTERN (PREV_INSN (p)), 0)))
8083 = emit_insn_before (gen_rtx (USE, VOIDmode,
8086 REG_NOTES (use_insn)
8087 = gen_rtx (EXPR_LIST, REG_DEAD, piece,
8088 REG_NOTES (use_insn));
8096 /* Put only REG_DEAD notes for pieces that are
8097 still used and that are not already dead or set. */
8099 for (i = regno; i < endregno; i++)
8101 rtx piece = gen_rtx (REG, word_mode, i);
8103 if (reg_referenced_p (piece, PATTERN (place))
8104 && ! dead_or_set_p (place, piece)
8105 && ! reg_bitfield_target_p (piece,
8107 REG_NOTES (place) = gen_rtx (EXPR_LIST, REG_DEAD,
8119 /* Any other notes should not be present at this point in the
8126 XEXP (note, 1) = REG_NOTES (place);
8127 REG_NOTES (place) = note;
8131 REG_NOTES (place2) = gen_rtx (GET_CODE (note), REG_NOTE_KIND (note),
8132 XEXP (note, 0), REG_NOTES (place2));
8136 /* Similarly to above, distribute the LOG_LINKS that used to be present on
8137 I3, I2, and I1 to new locations. This is also called in one case to
8138 add a link pointing at I3 when I3's destination is changed. */
8141 distribute_links (links)
8144 rtx link, next_link;
8146 for (link = links; link; link = next_link)
8152 next_link = XEXP (link, 1);
8154 /* If the insn that this link points to is a NOTE or isn't a single
8155 set, ignore it. In the latter case, it isn't clear what we
8156 can do other than ignore the link, since we can't tell which
8157 register it was for. Such links wouldn't be used by combine
8160 It is not possible for the destination of the target of the link to
8161 have been changed by combine. The only potential of this is if we
8162 replace I3, I2, and I1 by I3 and I2. But in that case the
8163 destination of I2 also remains unchanged. */
8165 if (GET_CODE (XEXP (link, 0)) == NOTE
8166 || (set = single_set (XEXP (link, 0))) == 0)
8169 reg = SET_DEST (set);
8170 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
8171 || GET_CODE (reg) == SIGN_EXTRACT
8172 || GET_CODE (reg) == STRICT_LOW_PART)
8173 reg = XEXP (reg, 0);
8175 /* A LOG_LINK is defined as being placed on the first insn that uses
8176 a register and points to the insn that sets the register. Start
8177 searching at the next insn after the target of the link and stop
8178 when we reach a set of the register or the end of the basic block.
8180 Note that this correctly handles the link that used to point from
8181 I3 to I2. Also note that not much searching is typically done here
8182 since most links don't point very far away. */
8184 for (insn = NEXT_INSN (XEXP (link, 0));
8185 (insn && GET_CODE (insn) != CODE_LABEL
8186 && GET_CODE (PREV_INSN (insn)) != JUMP_INSN);
8187 insn = NEXT_INSN (insn))
8188 if (GET_RTX_CLASS (GET_CODE (insn)) == 'i'
8189 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8191 if (reg_referenced_p (reg, PATTERN (insn)))
8196 /* If we found a place to put the link, place it there unless there
8197 is already a link to the same insn as LINK at that point. */
8203 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
8204 if (XEXP (link2, 0) == XEXP (link, 0))
8209 XEXP (link, 1) = LOG_LINKS (place);
8210 LOG_LINKS (place) = link;
8217 dump_combine_stats (file)
8222 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
8223 combine_attempts, combine_merges, combine_extras, combine_successes);
8227 dump_combine_total_stats (file)
8232 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
8233 total_attempts, total_merges, total_extras, total_successes);
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