1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
94 #include "insn-codes.h"
95 #include "rtlhooks-def.h"
96 /* Include output.h for dump_file. */
100 #include "tree-pass.h"
102 /* Number of attempts to combine instructions in this function. */
104 static int combine_attempts;
106 /* Number of attempts that got as far as substitution in this function. */
108 static int combine_merges;
110 /* Number of instructions combined with added SETs in this function. */
112 static int combine_extras;
114 /* Number of instructions combined in this function. */
116 static int combine_successes;
118 /* Totals over entire compilation. */
120 static int total_attempts, total_merges, total_extras, total_successes;
123 /* Vector mapping INSN_UIDs to cuids.
124 The cuids are like uids but increase monotonically always.
125 Combine always uses cuids so that it can compare them.
126 But actually renumbering the uids, which we used to do,
127 proves to be a bad idea because it makes it hard to compare
128 the dumps produced by earlier passes with those from later passes. */
130 static int *uid_cuid;
131 static int max_uid_cuid;
133 /* Get the cuid of an insn. */
135 #define INSN_CUID(INSN) \
136 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
138 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
139 BITS_PER_WORD would invoke undefined behavior. Work around it. */
141 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
142 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
144 /* Maximum register number, which is the size of the tables below. */
146 static unsigned int combine_max_regno;
149 /* Record last point of death of (hard or pseudo) register n. */
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
205 int last_set_table_tick;
207 /* Record the value of label_tick when the value for register n is placed in
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
217 unsigned HOST_WIDE_INT last_set_nonzero_bits;
218 char last_set_sign_bit_copies;
219 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
225 char last_set_invalid;
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
237 If an entry is zero, it means that we don't know anything special. */
239 unsigned char sign_bit_copies;
241 unsigned HOST_WIDE_INT nonzero_bits;
244 static struct reg_stat *reg_stat;
246 /* Record the cuid of the last insn that invalidated memory
247 (anything that writes memory, and subroutine calls, but not pushes). */
249 static int mem_last_set;
251 /* Record the cuid of the last CALL_INSN
252 so we can tell whether a potential combination crosses any calls. */
254 static int last_call_cuid;
256 /* When `subst' is called, this is the insn that is being modified
257 (by combining in a previous insn). The PATTERN of this insn
258 is still the old pattern partially modified and it should not be
259 looked at, but this may be used to examine the successors of the insn
260 to judge whether a simplification is valid. */
262 static rtx subst_insn;
264 /* This is the lowest CUID that `subst' is currently dealing with.
265 get_last_value will not return a value if the register was set at or
266 after this CUID. If not for this mechanism, we could get confused if
267 I2 or I1 in try_combine were an insn that used the old value of a register
268 to obtain a new value. In that case, we might erroneously get the
269 new value of the register when we wanted the old one. */
271 static int subst_low_cuid;
273 /* This contains any hard registers that are used in newpat; reg_dead_at_p
274 must consider all these registers to be always live. */
276 static HARD_REG_SET newpat_used_regs;
278 /* This is an insn to which a LOG_LINKS entry has been added. If this
279 insn is the earlier than I2 or I3, combine should rescan starting at
282 static rtx added_links_insn;
284 /* Basic block in which we are performing combines. */
285 static basic_block this_basic_block;
287 /* A bitmap indicating which blocks had registers go dead at entry.
288 After combine, we'll need to re-do global life analysis with
289 those blocks as starting points. */
290 static sbitmap refresh_blocks;
292 /* The following array records the insn_rtx_cost for every insn
293 in the instruction stream. */
295 static int *uid_insn_cost;
297 /* Length of the currently allocated uid_insn_cost array. */
299 static int last_insn_cost;
301 /* Incremented for each label. */
303 static int label_tick;
305 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
306 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
308 static enum machine_mode nonzero_bits_mode;
310 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
311 be safely used. It is zero while computing them and after combine has
312 completed. This former test prevents propagating values based on
313 previously set values, which can be incorrect if a variable is modified
316 static int nonzero_sign_valid;
319 /* Record one modification to rtl structure
320 to be undone by storing old_contents into *where.
321 is_int is 1 if the contents are an int. */
327 union {rtx r; int i;} old_contents;
328 union {rtx *r; int *i;} where;
331 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
332 num_undo says how many are currently recorded.
334 other_insn is nonzero if we have modified some other insn in the process
335 of working on subst_insn. It must be verified too. */
344 static struct undobuf undobuf;
346 /* Number of times the pseudo being substituted for
347 was found and replaced. */
349 static int n_occurrences;
351 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
353 unsigned HOST_WIDE_INT,
354 unsigned HOST_WIDE_INT *);
355 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
357 unsigned int, unsigned int *);
358 static void do_SUBST (rtx *, rtx);
359 static void do_SUBST_INT (int *, int);
360 static void init_reg_last (void);
361 static void setup_incoming_promotions (void);
362 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
363 static int cant_combine_insn_p (rtx);
364 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
365 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
366 static int contains_muldiv (rtx);
367 static rtx try_combine (rtx, rtx, rtx, int *);
368 static void undo_all (void);
369 static void undo_commit (void);
370 static rtx *find_split_point (rtx *, rtx);
371 static rtx subst (rtx, rtx, rtx, int, int);
372 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
373 static rtx simplify_if_then_else (rtx);
374 static rtx simplify_set (rtx);
375 static rtx simplify_logical (rtx);
376 static rtx expand_compound_operation (rtx);
377 static rtx expand_field_assignment (rtx);
378 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
379 rtx, unsigned HOST_WIDE_INT, int, int, int);
380 static rtx extract_left_shift (rtx, int);
381 static rtx make_compound_operation (rtx, enum rtx_code);
382 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
383 unsigned HOST_WIDE_INT *);
384 static rtx force_to_mode (rtx, enum machine_mode,
385 unsigned HOST_WIDE_INT, rtx, int);
386 static rtx if_then_else_cond (rtx, rtx *, rtx *);
387 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
388 static int rtx_equal_for_field_assignment_p (rtx, rtx);
389 static rtx make_field_assignment (rtx);
390 static rtx apply_distributive_law (rtx);
391 static rtx distribute_and_simplify_rtx (rtx, int);
392 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
393 unsigned HOST_WIDE_INT);
394 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
395 HOST_WIDE_INT, enum machine_mode, int *);
396 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
398 static int recog_for_combine (rtx *, rtx, rtx *);
399 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
400 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
401 static void update_table_tick (rtx);
402 static void record_value_for_reg (rtx, rtx, rtx);
403 static void check_promoted_subreg (rtx, rtx);
404 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
405 static void record_dead_and_set_regs (rtx);
406 static int get_last_value_validate (rtx *, rtx, int, int);
407 static rtx get_last_value (rtx);
408 static int use_crosses_set_p (rtx, int);
409 static void reg_dead_at_p_1 (rtx, rtx, void *);
410 static int reg_dead_at_p (rtx, rtx);
411 static void move_deaths (rtx, rtx, int, rtx, rtx *);
412 static int reg_bitfield_target_p (rtx, rtx);
413 static void distribute_notes (rtx, rtx, rtx, rtx);
414 static void distribute_links (rtx);
415 static void mark_used_regs_combine (rtx);
416 static int insn_cuid (rtx);
417 static void record_promoted_value (rtx, rtx);
418 static int unmentioned_reg_p_1 (rtx *, void *);
419 static bool unmentioned_reg_p (rtx, rtx);
422 /* It is not safe to use ordinary gen_lowpart in combine.
423 See comments in gen_lowpart_for_combine. */
424 #undef RTL_HOOKS_GEN_LOWPART
425 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
427 /* Our implementation of gen_lowpart never emits a new pseudo. */
428 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
429 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
431 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
432 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
434 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
435 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
437 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
440 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
441 insn. The substitution can be undone by undo_all. If INTO is already
442 set to NEWVAL, do not record this change. Because computing NEWVAL might
443 also call SUBST, we have to compute it before we put anything into
447 do_SUBST (rtx *into, rtx newval)
452 if (oldval == newval)
455 /* We'd like to catch as many invalid transformations here as
456 possible. Unfortunately, there are way too many mode changes
457 that are perfectly valid, so we'd waste too much effort for
458 little gain doing the checks here. Focus on catching invalid
459 transformations involving integer constants. */
460 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
461 && GET_CODE (newval) == CONST_INT)
463 /* Sanity check that we're replacing oldval with a CONST_INT
464 that is a valid sign-extension for the original mode. */
465 gcc_assert (INTVAL (newval)
466 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
468 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
469 CONST_INT is not valid, because after the replacement, the
470 original mode would be gone. Unfortunately, we can't tell
471 when do_SUBST is called to replace the operand thereof, so we
472 perform this test on oldval instead, checking whether an
473 invalid replacement took place before we got here. */
474 gcc_assert (!(GET_CODE (oldval) == SUBREG
475 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
476 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
477 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
481 buf = undobuf.frees, undobuf.frees = buf->next;
483 buf = xmalloc (sizeof (struct undo));
487 buf->old_contents.r = oldval;
490 buf->next = undobuf.undos, undobuf.undos = buf;
493 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
495 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
496 for the value of a HOST_WIDE_INT value (including CONST_INT) is
500 do_SUBST_INT (int *into, int newval)
505 if (oldval == newval)
509 buf = undobuf.frees, undobuf.frees = buf->next;
511 buf = xmalloc (sizeof (struct undo));
515 buf->old_contents.i = oldval;
518 buf->next = undobuf.undos, undobuf.undos = buf;
521 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
523 /* Subroutine of try_combine. Determine whether the combine replacement
524 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
525 that the original instruction sequence I1, I2 and I3. Note that I1
526 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
527 costs of all instructions can be estimated, and the replacements are
528 more expensive than the original sequence. */
531 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
533 int i1_cost, i2_cost, i3_cost;
534 int new_i2_cost, new_i3_cost;
535 int old_cost, new_cost;
537 /* Lookup the original insn_rtx_costs. */
538 i2_cost = INSN_UID (i2) <= last_insn_cost
539 ? uid_insn_cost[INSN_UID (i2)] : 0;
540 i3_cost = INSN_UID (i3) <= last_insn_cost
541 ? uid_insn_cost[INSN_UID (i3)] : 0;
545 i1_cost = INSN_UID (i1) <= last_insn_cost
546 ? uid_insn_cost[INSN_UID (i1)] : 0;
547 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
548 ? i1_cost + i2_cost + i3_cost : 0;
552 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
556 /* Calculate the replacement insn_rtx_costs. */
557 new_i3_cost = insn_rtx_cost (newpat);
560 new_i2_cost = insn_rtx_cost (newi2pat);
561 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
562 ? new_i2_cost + new_i3_cost : 0;
566 new_cost = new_i3_cost;
570 if (undobuf.other_insn)
572 int old_other_cost, new_other_cost;
574 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
575 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
576 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
577 if (old_other_cost > 0 && new_other_cost > 0)
579 old_cost += old_other_cost;
580 new_cost += new_other_cost;
586 /* Disallow this recombination if both new_cost and old_cost are
587 greater than zero, and new_cost is greater than old cost. */
589 && new_cost > old_cost)
596 "rejecting combination of insns %d, %d and %d\n",
597 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
598 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
599 i1_cost, i2_cost, i3_cost, old_cost);
604 "rejecting combination of insns %d and %d\n",
605 INSN_UID (i2), INSN_UID (i3));
606 fprintf (dump_file, "original costs %d + %d = %d\n",
607 i2_cost, i3_cost, old_cost);
612 fprintf (dump_file, "replacement costs %d + %d = %d\n",
613 new_i2_cost, new_i3_cost, new_cost);
616 fprintf (dump_file, "replacement cost %d\n", new_cost);
622 /* Update the uid_insn_cost array with the replacement costs. */
623 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
624 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
626 uid_insn_cost[INSN_UID (i1)] = 0;
631 /* Main entry point for combiner. F is the first insn of the function.
632 NREGS is the first unused pseudo-reg number.
634 Return nonzero if the combiner has turned an indirect jump
635 instruction into a direct jump. */
637 combine_instructions (rtx f, unsigned int nregs)
645 rtx links, nextlinks;
646 sbitmap_iterator sbi;
648 int new_direct_jump_p = 0;
650 combine_attempts = 0;
653 combine_successes = 0;
655 combine_max_regno = nregs;
657 rtl_hooks = combine_rtl_hooks;
659 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
661 init_recog_no_volatile ();
663 /* Compute maximum uid value so uid_cuid can be allocated. */
665 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
666 if (INSN_UID (insn) > i)
669 uid_cuid = xmalloc ((i + 1) * sizeof (int));
672 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
674 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
675 problems when, for example, we have j <<= 1 in a loop. */
677 nonzero_sign_valid = 0;
679 /* Compute the mapping from uids to cuids.
680 Cuids are numbers assigned to insns, like uids,
681 except that cuids increase monotonically through the code.
683 Scan all SETs and see if we can deduce anything about what
684 bits are known to be zero for some registers and how many copies
685 of the sign bit are known to exist for those registers.
687 Also set any known values so that we can use it while searching
688 for what bits are known to be set. */
692 setup_incoming_promotions ();
694 refresh_blocks = sbitmap_alloc (last_basic_block);
695 sbitmap_zero (refresh_blocks);
697 /* Allocate array of current insn_rtx_costs. */
698 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
699 last_insn_cost = max_uid_cuid;
701 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
703 uid_cuid[INSN_UID (insn)] = ++i;
709 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
711 record_dead_and_set_regs (insn);
714 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
715 if (REG_NOTE_KIND (links) == REG_INC)
716 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
720 /* Record the current insn_rtx_cost of this instruction. */
721 if (NONJUMP_INSN_P (insn))
722 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
724 fprintf(dump_file, "insn_cost %d: %d\n",
725 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
732 nonzero_sign_valid = 1;
734 /* Now scan all the insns in forward order. */
740 setup_incoming_promotions ();
742 FOR_EACH_BB (this_basic_block)
744 for (insn = BB_HEAD (this_basic_block);
745 insn != NEXT_INSN (BB_END (this_basic_block));
746 insn = next ? next : NEXT_INSN (insn))
753 else if (INSN_P (insn))
755 /* See if we know about function return values before this
756 insn based upon SUBREG flags. */
757 check_promoted_subreg (insn, PATTERN (insn));
759 /* Try this insn with each insn it links back to. */
761 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
762 if ((next = try_combine (insn, XEXP (links, 0),
763 NULL_RTX, &new_direct_jump_p)) != 0)
766 /* Try each sequence of three linked insns ending with this one. */
768 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
770 rtx link = XEXP (links, 0);
772 /* If the linked insn has been replaced by a note, then there
773 is no point in pursuing this chain any further. */
777 for (nextlinks = LOG_LINKS (link);
779 nextlinks = XEXP (nextlinks, 1))
780 if ((next = try_combine (insn, link,
782 &new_direct_jump_p)) != 0)
787 /* Try to combine a jump insn that uses CC0
788 with a preceding insn that sets CC0, and maybe with its
789 logical predecessor as well.
790 This is how we make decrement-and-branch insns.
791 We need this special code because data flow connections
792 via CC0 do not get entered in LOG_LINKS. */
795 && (prev = prev_nonnote_insn (insn)) != 0
796 && NONJUMP_INSN_P (prev)
797 && sets_cc0_p (PATTERN (prev)))
799 if ((next = try_combine (insn, prev,
800 NULL_RTX, &new_direct_jump_p)) != 0)
803 for (nextlinks = LOG_LINKS (prev); nextlinks;
804 nextlinks = XEXP (nextlinks, 1))
805 if ((next = try_combine (insn, prev,
807 &new_direct_jump_p)) != 0)
811 /* Do the same for an insn that explicitly references CC0. */
812 if (NONJUMP_INSN_P (insn)
813 && (prev = prev_nonnote_insn (insn)) != 0
814 && NONJUMP_INSN_P (prev)
815 && sets_cc0_p (PATTERN (prev))
816 && GET_CODE (PATTERN (insn)) == SET
817 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
819 if ((next = try_combine (insn, prev,
820 NULL_RTX, &new_direct_jump_p)) != 0)
823 for (nextlinks = LOG_LINKS (prev); nextlinks;
824 nextlinks = XEXP (nextlinks, 1))
825 if ((next = try_combine (insn, prev,
827 &new_direct_jump_p)) != 0)
831 /* Finally, see if any of the insns that this insn links to
832 explicitly references CC0. If so, try this insn, that insn,
833 and its predecessor if it sets CC0. */
834 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
835 if (NONJUMP_INSN_P (XEXP (links, 0))
836 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
837 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
838 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
839 && NONJUMP_INSN_P (prev)
840 && sets_cc0_p (PATTERN (prev))
841 && (next = try_combine (insn, XEXP (links, 0),
842 prev, &new_direct_jump_p)) != 0)
846 /* Try combining an insn with two different insns whose results it
848 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
849 for (nextlinks = XEXP (links, 1); nextlinks;
850 nextlinks = XEXP (nextlinks, 1))
851 if ((next = try_combine (insn, XEXP (links, 0),
853 &new_direct_jump_p)) != 0)
856 /* Try this insn with each REG_EQUAL note it links back to. */
857 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
860 rtx temp = XEXP (links, 0);
861 if ((set = single_set (temp)) != 0
862 && (note = find_reg_equal_equiv_note (temp)) != 0
863 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
864 /* Avoid using a register that may already been marked
865 dead by an earlier instruction. */
866 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
868 /* Temporarily replace the set's source with the
869 contents of the REG_EQUAL note. The insn will
870 be deleted or recognized by try_combine. */
871 rtx orig = SET_SRC (set);
872 SET_SRC (set) = XEXP (note, 0);
873 next = try_combine (insn, temp, NULL_RTX,
877 SET_SRC (set) = orig;
882 record_dead_and_set_regs (insn);
891 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
892 BASIC_BLOCK (j)->flags |= BB_DIRTY;
893 new_direct_jump_p |= purge_all_dead_edges ();
894 delete_noop_moves ();
896 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
897 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
898 | PROP_KILL_DEAD_CODE);
901 sbitmap_free (refresh_blocks);
902 free (uid_insn_cost);
907 struct undo *undo, *next;
908 for (undo = undobuf.frees; undo; undo = next)
916 total_attempts += combine_attempts;
917 total_merges += combine_merges;
918 total_extras += combine_extras;
919 total_successes += combine_successes;
921 nonzero_sign_valid = 0;
922 rtl_hooks = general_rtl_hooks;
924 /* Make recognizer allow volatile MEMs again. */
927 return new_direct_jump_p;
930 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
936 for (i = 0; i < combine_max_regno; i++)
937 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
940 /* Set up any promoted values for incoming argument registers. */
943 setup_incoming_promotions (void)
947 enum machine_mode mode;
949 rtx first = get_insns ();
951 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
953 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
954 /* Check whether this register can hold an incoming pointer
955 argument. FUNCTION_ARG_REGNO_P tests outgoing register
956 numbers, so translate if necessary due to register windows. */
957 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
958 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
961 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
964 gen_rtx_CLOBBER (mode, const0_rtx)));
969 /* Called via note_stores. If X is a pseudo that is narrower than
970 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
972 If we are setting only a portion of X and we can't figure out what
973 portion, assume all bits will be used since we don't know what will
976 Similarly, set how many bits of X are known to be copies of the sign bit
977 at all locations in the function. This is the smallest number implied
981 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
982 void *data ATTRIBUTE_UNUSED)
987 && REGNO (x) >= FIRST_PSEUDO_REGISTER
988 /* If this register is undefined at the start of the file, we can't
989 say what its contents were. */
991 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
992 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
994 if (set == 0 || GET_CODE (set) == CLOBBER)
996 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
997 reg_stat[REGNO (x)].sign_bit_copies = 1;
1001 /* If this is a complex assignment, see if we can convert it into a
1002 simple assignment. */
1003 set = expand_field_assignment (set);
1005 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1006 set what we know about X. */
1008 if (SET_DEST (set) == x
1009 || (GET_CODE (SET_DEST (set)) == SUBREG
1010 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1011 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1012 && SUBREG_REG (SET_DEST (set)) == x))
1014 rtx src = SET_SRC (set);
1016 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1017 /* If X is narrower than a word and SRC is a non-negative
1018 constant that would appear negative in the mode of X,
1019 sign-extend it for use in reg_stat[].nonzero_bits because some
1020 machines (maybe most) will actually do the sign-extension
1021 and this is the conservative approach.
1023 ??? For 2.5, try to tighten up the MD files in this regard
1024 instead of this kludge. */
1026 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1027 && GET_CODE (src) == CONST_INT
1029 && 0 != (INTVAL (src)
1030 & ((HOST_WIDE_INT) 1
1031 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1032 src = GEN_INT (INTVAL (src)
1033 | ((HOST_WIDE_INT) (-1)
1034 << GET_MODE_BITSIZE (GET_MODE (x))));
1037 /* Don't call nonzero_bits if it cannot change anything. */
1038 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1039 reg_stat[REGNO (x)].nonzero_bits
1040 |= nonzero_bits (src, nonzero_bits_mode);
1041 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1042 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1043 || reg_stat[REGNO (x)].sign_bit_copies > num)
1044 reg_stat[REGNO (x)].sign_bit_copies = num;
1048 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1049 reg_stat[REGNO (x)].sign_bit_copies = 1;
1054 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1055 insns that were previously combined into I3 or that will be combined
1056 into the merger of INSN and I3.
1058 Return 0 if the combination is not allowed for any reason.
1060 If the combination is allowed, *PDEST will be set to the single
1061 destination of INSN and *PSRC to the single source, and this function
1065 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1066 rtx *pdest, rtx *psrc)
1069 rtx set = 0, src, dest;
1074 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1075 && next_active_insn (succ) == i3)
1076 : next_active_insn (insn) == i3);
1078 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1079 or a PARALLEL consisting of such a SET and CLOBBERs.
1081 If INSN has CLOBBER parallel parts, ignore them for our processing.
1082 By definition, these happen during the execution of the insn. When it
1083 is merged with another insn, all bets are off. If they are, in fact,
1084 needed and aren't also supplied in I3, they may be added by
1085 recog_for_combine. Otherwise, it won't match.
1087 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1090 Get the source and destination of INSN. If more than one, can't
1093 if (GET_CODE (PATTERN (insn)) == SET)
1094 set = PATTERN (insn);
1095 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1096 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1098 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1100 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1103 switch (GET_CODE (elt))
1105 /* This is important to combine floating point insns
1106 for the SH4 port. */
1108 /* Combining an isolated USE doesn't make sense.
1109 We depend here on combinable_i3pat to reject them. */
1110 /* The code below this loop only verifies that the inputs of
1111 the SET in INSN do not change. We call reg_set_between_p
1112 to verify that the REG in the USE does not change between
1114 If the USE in INSN was for a pseudo register, the matching
1115 insn pattern will likely match any register; combining this
1116 with any other USE would only be safe if we knew that the
1117 used registers have identical values, or if there was
1118 something to tell them apart, e.g. different modes. For
1119 now, we forgo such complicated tests and simply disallow
1120 combining of USES of pseudo registers with any other USE. */
1121 if (REG_P (XEXP (elt, 0))
1122 && GET_CODE (PATTERN (i3)) == PARALLEL)
1124 rtx i3pat = PATTERN (i3);
1125 int i = XVECLEN (i3pat, 0) - 1;
1126 unsigned int regno = REGNO (XEXP (elt, 0));
1130 rtx i3elt = XVECEXP (i3pat, 0, i);
1132 if (GET_CODE (i3elt) == USE
1133 && REG_P (XEXP (i3elt, 0))
1134 && (REGNO (XEXP (i3elt, 0)) == regno
1135 ? reg_set_between_p (XEXP (elt, 0),
1136 PREV_INSN (insn), i3)
1137 : regno >= FIRST_PSEUDO_REGISTER))
1144 /* We can ignore CLOBBERs. */
1149 /* Ignore SETs whose result isn't used but not those that
1150 have side-effects. */
1151 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1152 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1153 || INTVAL (XEXP (note, 0)) <= 0)
1154 && ! side_effects_p (elt))
1157 /* If we have already found a SET, this is a second one and
1158 so we cannot combine with this insn. */
1166 /* Anything else means we can't combine. */
1172 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1173 so don't do anything with it. */
1174 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1183 set = expand_field_assignment (set);
1184 src = SET_SRC (set), dest = SET_DEST (set);
1186 /* Don't eliminate a store in the stack pointer. */
1187 if (dest == stack_pointer_rtx
1188 /* Don't combine with an insn that sets a register to itself if it has
1189 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1190 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1191 /* Can't merge an ASM_OPERANDS. */
1192 || GET_CODE (src) == ASM_OPERANDS
1193 /* Can't merge a function call. */
1194 || GET_CODE (src) == CALL
1195 /* Don't eliminate a function call argument. */
1197 && (find_reg_fusage (i3, USE, dest)
1199 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1200 && global_regs[REGNO (dest)])))
1201 /* Don't substitute into an incremented register. */
1202 || FIND_REG_INC_NOTE (i3, dest)
1203 || (succ && FIND_REG_INC_NOTE (succ, dest))
1204 /* Don't substitute into a non-local goto, this confuses CFG. */
1205 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1207 /* Don't combine the end of a libcall into anything. */
1208 /* ??? This gives worse code, and appears to be unnecessary, since no
1209 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1210 use REG_RETVAL notes for noconflict blocks, but other code here
1211 makes sure that those insns don't disappear. */
1212 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1214 /* Make sure that DEST is not used after SUCC but before I3. */
1215 || (succ && ! all_adjacent
1216 && reg_used_between_p (dest, succ, i3))
1217 /* Make sure that the value that is to be substituted for the register
1218 does not use any registers whose values alter in between. However,
1219 If the insns are adjacent, a use can't cross a set even though we
1220 think it might (this can happen for a sequence of insns each setting
1221 the same destination; last_set of that register might point to
1222 a NOTE). If INSN has a REG_EQUIV note, the register is always
1223 equivalent to the memory so the substitution is valid even if there
1224 are intervening stores. Also, don't move a volatile asm or
1225 UNSPEC_VOLATILE across any other insns. */
1228 || ! find_reg_note (insn, REG_EQUIV, src))
1229 && use_crosses_set_p (src, INSN_CUID (insn)))
1230 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1231 || GET_CODE (src) == UNSPEC_VOLATILE))
1232 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1233 better register allocation by not doing the combine. */
1234 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1235 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1236 /* Don't combine across a CALL_INSN, because that would possibly
1237 change whether the life span of some REGs crosses calls or not,
1238 and it is a pain to update that information.
1239 Exception: if source is a constant, moving it later can't hurt.
1240 Accept that special case, because it helps -fforce-addr a lot. */
1241 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1244 /* DEST must either be a REG or CC0. */
1247 /* If register alignment is being enforced for multi-word items in all
1248 cases except for parameters, it is possible to have a register copy
1249 insn referencing a hard register that is not allowed to contain the
1250 mode being copied and which would not be valid as an operand of most
1251 insns. Eliminate this problem by not combining with such an insn.
1253 Also, on some machines we don't want to extend the life of a hard
1257 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1258 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1259 /* Don't extend the life of a hard register unless it is
1260 user variable (if we have few registers) or it can't
1261 fit into the desired register (meaning something special
1263 Also avoid substituting a return register into I3, because
1264 reload can't handle a conflict with constraints of other
1266 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1267 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1270 else if (GET_CODE (dest) != CC0)
1274 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1275 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1276 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1278 /* Don't substitute for a register intended as a clobberable
1280 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1281 if (rtx_equal_p (reg, dest))
1284 /* If the clobber represents an earlyclobber operand, we must not
1285 substitute an expression containing the clobbered register.
1286 As we do not analyze the constraint strings here, we have to
1287 make the conservative assumption. However, if the register is
1288 a fixed hard reg, the clobber cannot represent any operand;
1289 we leave it up to the machine description to either accept or
1290 reject use-and-clobber patterns. */
1292 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1293 || !fixed_regs[REGNO (reg)])
1294 if (reg_overlap_mentioned_p (reg, src))
1298 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1299 or not), reject, unless nothing volatile comes between it and I3 */
1301 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1303 /* Make sure succ doesn't contain a volatile reference. */
1304 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1307 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1308 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1312 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1313 to be an explicit register variable, and was chosen for a reason. */
1315 if (GET_CODE (src) == ASM_OPERANDS
1316 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1319 /* If there are any volatile insns between INSN and I3, reject, because
1320 they might affect machine state. */
1322 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1323 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1326 /* If INSN contains an autoincrement or autodecrement, make sure that
1327 register is not used between there and I3, and not already used in
1328 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1329 Also insist that I3 not be a jump; if it were one
1330 and the incremented register were spilled, we would lose. */
1333 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1334 if (REG_NOTE_KIND (link) == REG_INC
1336 || reg_used_between_p (XEXP (link, 0), insn, i3)
1337 || (pred != NULL_RTX
1338 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1339 || (succ != NULL_RTX
1340 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1341 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1346 /* Don't combine an insn that follows a CC0-setting insn.
1347 An insn that uses CC0 must not be separated from the one that sets it.
1348 We do, however, allow I2 to follow a CC0-setting insn if that insn
1349 is passed as I1; in that case it will be deleted also.
1350 We also allow combining in this case if all the insns are adjacent
1351 because that would leave the two CC0 insns adjacent as well.
1352 It would be more logical to test whether CC0 occurs inside I1 or I2,
1353 but that would be much slower, and this ought to be equivalent. */
1355 p = prev_nonnote_insn (insn);
1356 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1361 /* If we get here, we have passed all the tests and the combination is
1370 /* LOC is the location within I3 that contains its pattern or the component
1371 of a PARALLEL of the pattern. We validate that it is valid for combining.
1373 One problem is if I3 modifies its output, as opposed to replacing it
1374 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1375 so would produce an insn that is not equivalent to the original insns.
1379 (set (reg:DI 101) (reg:DI 100))
1380 (set (subreg:SI (reg:DI 101) 0) <foo>)
1382 This is NOT equivalent to:
1384 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1385 (set (reg:DI 101) (reg:DI 100))])
1387 Not only does this modify 100 (in which case it might still be valid
1388 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1390 We can also run into a problem if I2 sets a register that I1
1391 uses and I1 gets directly substituted into I3 (not via I2). In that
1392 case, we would be getting the wrong value of I2DEST into I3, so we
1393 must reject the combination. This case occurs when I2 and I1 both
1394 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1395 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1396 of a SET must prevent combination from occurring.
1398 Before doing the above check, we first try to expand a field assignment
1399 into a set of logical operations.
1401 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1402 we place a register that is both set and used within I3. If more than one
1403 such register is detected, we fail.
1405 Return 1 if the combination is valid, zero otherwise. */
1408 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1409 int i1_not_in_src, rtx *pi3dest_killed)
1413 if (GET_CODE (x) == SET)
1416 rtx dest = SET_DEST (set);
1417 rtx src = SET_SRC (set);
1418 rtx inner_dest = dest;
1420 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1421 || GET_CODE (inner_dest) == SUBREG
1422 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1423 inner_dest = XEXP (inner_dest, 0);
1425 /* Check for the case where I3 modifies its output, as discussed
1426 above. We don't want to prevent pseudos from being combined
1427 into the address of a MEM, so only prevent the combination if
1428 i1 or i2 set the same MEM. */
1429 if ((inner_dest != dest &&
1430 (!MEM_P (inner_dest)
1431 || rtx_equal_p (i2dest, inner_dest)
1432 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1433 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1434 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1436 /* This is the same test done in can_combine_p except we can't test
1437 all_adjacent; we don't have to, since this instruction will stay
1438 in place, thus we are not considering increasing the lifetime of
1441 Also, if this insn sets a function argument, combining it with
1442 something that might need a spill could clobber a previous
1443 function argument; the all_adjacent test in can_combine_p also
1444 checks this; here, we do a more specific test for this case. */
1446 || (REG_P (inner_dest)
1447 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1448 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1449 GET_MODE (inner_dest))))
1450 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1453 /* If DEST is used in I3, it is being killed in this insn,
1454 so record that for later.
1455 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1456 STACK_POINTER_REGNUM, since these are always considered to be
1457 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1458 if (pi3dest_killed && REG_P (dest)
1459 && reg_referenced_p (dest, PATTERN (i3))
1460 && REGNO (dest) != FRAME_POINTER_REGNUM
1461 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1462 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1464 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1465 && (REGNO (dest) != ARG_POINTER_REGNUM
1466 || ! fixed_regs [REGNO (dest)])
1468 && REGNO (dest) != STACK_POINTER_REGNUM)
1470 if (*pi3dest_killed)
1473 *pi3dest_killed = dest;
1477 else if (GET_CODE (x) == PARALLEL)
1481 for (i = 0; i < XVECLEN (x, 0); i++)
1482 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1483 i1_not_in_src, pi3dest_killed))
1490 /* Return 1 if X is an arithmetic expression that contains a multiplication
1491 and division. We don't count multiplications by powers of two here. */
1494 contains_muldiv (rtx x)
1496 switch (GET_CODE (x))
1498 case MOD: case DIV: case UMOD: case UDIV:
1502 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1503 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1506 return contains_muldiv (XEXP (x, 0))
1507 || contains_muldiv (XEXP (x, 1));
1510 return contains_muldiv (XEXP (x, 0));
1516 /* Determine whether INSN can be used in a combination. Return nonzero if
1517 not. This is used in try_combine to detect early some cases where we
1518 can't perform combinations. */
1521 cant_combine_insn_p (rtx insn)
1526 /* If this isn't really an insn, we can't do anything.
1527 This can occur when flow deletes an insn that it has merged into an
1528 auto-increment address. */
1529 if (! INSN_P (insn))
1532 /* Never combine loads and stores involving hard regs that are likely
1533 to be spilled. The register allocator can usually handle such
1534 reg-reg moves by tying. If we allow the combiner to make
1535 substitutions of likely-spilled regs, reload might die.
1536 As an exception, we allow combinations involving fixed regs; these are
1537 not available to the register allocator so there's no risk involved. */
1539 set = single_set (insn);
1542 src = SET_SRC (set);
1543 dest = SET_DEST (set);
1544 if (GET_CODE (src) == SUBREG)
1545 src = SUBREG_REG (src);
1546 if (GET_CODE (dest) == SUBREG)
1547 dest = SUBREG_REG (dest);
1548 if (REG_P (src) && REG_P (dest)
1549 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1550 && ! fixed_regs[REGNO (src)]
1551 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1552 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1553 && ! fixed_regs[REGNO (dest)]
1554 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1560 /* Adjust INSN after we made a change to its destination.
1562 Changing the destination can invalidate notes that say something about
1563 the results of the insn and a LOG_LINK pointing to the insn. */
1566 adjust_for_new_dest (rtx insn)
1570 /* For notes, be conservative and simply remove them. */
1571 loc = ®_NOTES (insn);
1574 enum reg_note kind = REG_NOTE_KIND (*loc);
1575 if (kind == REG_EQUAL || kind == REG_EQUIV)
1576 *loc = XEXP (*loc, 1);
1578 loc = &XEXP (*loc, 1);
1581 /* The new insn will have a destination that was previously the destination
1582 of an insn just above it. Call distribute_links to make a LOG_LINK from
1583 the next use of that destination. */
1584 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1587 /* Try to combine the insns I1 and I2 into I3.
1588 Here I1 and I2 appear earlier than I3.
1589 I1 can be zero; then we combine just I2 into I3.
1591 If we are combining three insns and the resulting insn is not recognized,
1592 try splitting it into two insns. If that happens, I2 and I3 are retained
1593 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1596 Return 0 if the combination does not work. Then nothing is changed.
1597 If we did the combination, return the insn at which combine should
1600 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1601 new direct jump instruction. */
1604 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1606 /* New patterns for I3 and I2, respectively. */
1607 rtx newpat, newi2pat = 0;
1608 rtvec newpat_vec_with_clobbers = 0;
1609 int substed_i2 = 0, substed_i1 = 0;
1610 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1611 int added_sets_1, added_sets_2;
1612 /* Total number of SETs to put into I3. */
1614 /* Nonzero if I2's body now appears in I3. */
1616 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1617 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1618 /* Contains I3 if the destination of I3 is used in its source, which means
1619 that the old life of I3 is being killed. If that usage is placed into
1620 I2 and not in I3, a REG_DEAD note must be made. */
1621 rtx i3dest_killed = 0;
1622 /* SET_DEST and SET_SRC of I2 and I1. */
1623 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1624 /* PATTERN (I2), or a copy of it in certain cases. */
1626 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1627 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1628 int i1_feeds_i3 = 0;
1629 /* Notes that must be added to REG_NOTES in I3 and I2. */
1630 rtx new_i3_notes, new_i2_notes;
1631 /* Notes that we substituted I3 into I2 instead of the normal case. */
1632 int i3_subst_into_i2 = 0;
1633 /* Notes that I1, I2 or I3 is a MULT operation. */
1642 /* Exit early if one of the insns involved can't be used for
1644 if (cant_combine_insn_p (i3)
1645 || cant_combine_insn_p (i2)
1646 || (i1 && cant_combine_insn_p (i1))
1647 /* We also can't do anything if I3 has a
1648 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1651 /* ??? This gives worse code, and appears to be unnecessary, since no
1652 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1653 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1659 undobuf.other_insn = 0;
1661 /* Reset the hard register usage information. */
1662 CLEAR_HARD_REG_SET (newpat_used_regs);
1664 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1665 code below, set I1 to be the earlier of the two insns. */
1666 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1667 temp = i1, i1 = i2, i2 = temp;
1669 added_links_insn = 0;
1671 /* First check for one important special-case that the code below will
1672 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1673 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1674 we may be able to replace that destination with the destination of I3.
1675 This occurs in the common code where we compute both a quotient and
1676 remainder into a structure, in which case we want to do the computation
1677 directly into the structure to avoid register-register copies.
1679 Note that this case handles both multiple sets in I2 and also
1680 cases where I2 has a number of CLOBBER or PARALLELs.
1682 We make very conservative checks below and only try to handle the
1683 most common cases of this. For example, we only handle the case
1684 where I2 and I3 are adjacent to avoid making difficult register
1687 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1688 && REG_P (SET_SRC (PATTERN (i3)))
1689 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1690 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1691 && GET_CODE (PATTERN (i2)) == PARALLEL
1692 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1693 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1694 below would need to check what is inside (and reg_overlap_mentioned_p
1695 doesn't support those codes anyway). Don't allow those destinations;
1696 the resulting insn isn't likely to be recognized anyway. */
1697 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1698 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1699 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1700 SET_DEST (PATTERN (i3)))
1701 && next_real_insn (i2) == i3)
1703 rtx p2 = PATTERN (i2);
1705 /* Make sure that the destination of I3,
1706 which we are going to substitute into one output of I2,
1707 is not used within another output of I2. We must avoid making this:
1708 (parallel [(set (mem (reg 69)) ...)
1709 (set (reg 69) ...)])
1710 which is not well-defined as to order of actions.
1711 (Besides, reload can't handle output reloads for this.)
1713 The problem can also happen if the dest of I3 is a memory ref,
1714 if another dest in I2 is an indirect memory ref. */
1715 for (i = 0; i < XVECLEN (p2, 0); i++)
1716 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1717 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1718 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1719 SET_DEST (XVECEXP (p2, 0, i))))
1722 if (i == XVECLEN (p2, 0))
1723 for (i = 0; i < XVECLEN (p2, 0); i++)
1724 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1725 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1726 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1731 subst_low_cuid = INSN_CUID (i2);
1733 added_sets_2 = added_sets_1 = 0;
1734 i2dest = SET_SRC (PATTERN (i3));
1736 /* Replace the dest in I2 with our dest and make the resulting
1737 insn the new pattern for I3. Then skip to where we
1738 validate the pattern. Everything was set up above. */
1739 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1740 SET_DEST (PATTERN (i3)));
1743 i3_subst_into_i2 = 1;
1744 goto validate_replacement;
1748 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1749 one of those words to another constant, merge them by making a new
1752 && (temp = single_set (i2)) != 0
1753 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1754 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1755 && REG_P (SET_DEST (temp))
1756 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1757 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1758 && GET_CODE (PATTERN (i3)) == SET
1759 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1760 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1761 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1762 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1763 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1765 HOST_WIDE_INT lo, hi;
1767 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1768 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1771 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1772 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1775 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1777 /* We don't handle the case of the target word being wider
1778 than a host wide int. */
1779 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1781 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1782 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1783 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1785 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1786 hi = INTVAL (SET_SRC (PATTERN (i3)));
1787 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1789 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1790 >> (HOST_BITS_PER_WIDE_INT - 1));
1792 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1793 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1794 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1795 (INTVAL (SET_SRC (PATTERN (i3)))));
1797 hi = lo < 0 ? -1 : 0;
1800 /* We don't handle the case of the higher word not fitting
1801 entirely in either hi or lo. */
1806 subst_low_cuid = INSN_CUID (i2);
1807 added_sets_2 = added_sets_1 = 0;
1808 i2dest = SET_DEST (temp);
1810 SUBST (SET_SRC (temp),
1811 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1813 newpat = PATTERN (i2);
1814 goto validate_replacement;
1818 /* If we have no I1 and I2 looks like:
1819 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1821 make up a dummy I1 that is
1824 (set (reg:CC X) (compare:CC Y (const_int 0)))
1826 (We can ignore any trailing CLOBBERs.)
1828 This undoes a previous combination and allows us to match a branch-and-
1831 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1832 && XVECLEN (PATTERN (i2), 0) >= 2
1833 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1834 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1836 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1837 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1838 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1839 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1840 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1841 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1843 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1844 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1849 /* We make I1 with the same INSN_UID as I2. This gives it
1850 the same INSN_CUID for value tracking. Our fake I1 will
1851 never appear in the insn stream so giving it the same INSN_UID
1852 as I2 will not cause a problem. */
1854 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1855 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1856 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1859 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1860 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1861 SET_DEST (PATTERN (i1)));
1866 /* Verify that I2 and I1 are valid for combining. */
1867 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1868 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1874 /* Record whether I2DEST is used in I2SRC and similarly for the other
1875 cases. Knowing this will help in register status updating below. */
1876 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1877 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1878 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1880 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1882 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1884 /* Ensure that I3's pattern can be the destination of combines. */
1885 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1886 i1 && i2dest_in_i1src && i1_feeds_i3,
1893 /* See if any of the insns is a MULT operation. Unless one is, we will
1894 reject a combination that is, since it must be slower. Be conservative
1896 if (GET_CODE (i2src) == MULT
1897 || (i1 != 0 && GET_CODE (i1src) == MULT)
1898 || (GET_CODE (PATTERN (i3)) == SET
1899 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1902 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1903 We used to do this EXCEPT in one case: I3 has a post-inc in an
1904 output operand. However, that exception can give rise to insns like
1906 which is a famous insn on the PDP-11 where the value of r3 used as the
1907 source was model-dependent. Avoid this sort of thing. */
1910 if (!(GET_CODE (PATTERN (i3)) == SET
1911 && REG_P (SET_SRC (PATTERN (i3)))
1912 && MEM_P (SET_DEST (PATTERN (i3)))
1913 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1914 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1915 /* It's not the exception. */
1918 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1919 if (REG_NOTE_KIND (link) == REG_INC
1920 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1922 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1929 /* See if the SETs in I1 or I2 need to be kept around in the merged
1930 instruction: whenever the value set there is still needed past I3.
1931 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1933 For the SET in I1, we have two cases: If I1 and I2 independently
1934 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1935 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1936 in I1 needs to be kept around unless I1DEST dies or is set in either
1937 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1938 I1DEST. If so, we know I1 feeds into I2. */
1940 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1943 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1944 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1946 /* If the set in I2 needs to be kept around, we must make a copy of
1947 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1948 PATTERN (I2), we are only substituting for the original I1DEST, not into
1949 an already-substituted copy. This also prevents making self-referential
1950 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1953 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1954 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1958 i2pat = copy_rtx (i2pat);
1962 /* Substitute in the latest insn for the regs set by the earlier ones. */
1964 maxreg = max_reg_num ();
1968 /* It is possible that the source of I2 or I1 may be performing an
1969 unneeded operation, such as a ZERO_EXTEND of something that is known
1970 to have the high part zero. Handle that case by letting subst look at
1971 the innermost one of them.
1973 Another way to do this would be to have a function that tries to
1974 simplify a single insn instead of merging two or more insns. We don't
1975 do this because of the potential of infinite loops and because
1976 of the potential extra memory required. However, doing it the way
1977 we are is a bit of a kludge and doesn't catch all cases.
1979 But only do this if -fexpensive-optimizations since it slows things down
1980 and doesn't usually win. */
1982 if (flag_expensive_optimizations)
1984 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1987 subst_low_cuid = INSN_CUID (i1);
1988 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1992 subst_low_cuid = INSN_CUID (i2);
1993 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1998 /* Many machines that don't use CC0 have insns that can both perform an
1999 arithmetic operation and set the condition code. These operations will
2000 be represented as a PARALLEL with the first element of the vector
2001 being a COMPARE of an arithmetic operation with the constant zero.
2002 The second element of the vector will set some pseudo to the result
2003 of the same arithmetic operation. If we simplify the COMPARE, we won't
2004 match such a pattern and so will generate an extra insn. Here we test
2005 for this case, where both the comparison and the operation result are
2006 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2007 I2SRC. Later we will make the PARALLEL that contains I2. */
2009 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2010 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2011 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2012 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2014 #ifdef SELECT_CC_MODE
2016 enum machine_mode compare_mode;
2019 newpat = PATTERN (i3);
2020 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2024 #ifdef SELECT_CC_MODE
2025 /* See if a COMPARE with the operand we substituted in should be done
2026 with the mode that is currently being used. If not, do the same
2027 processing we do in `subst' for a SET; namely, if the destination
2028 is used only once, try to replace it with a register of the proper
2029 mode and also replace the COMPARE. */
2030 if (undobuf.other_insn == 0
2031 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2032 &undobuf.other_insn))
2033 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2035 != GET_MODE (SET_DEST (newpat))))
2037 unsigned int regno = REGNO (SET_DEST (newpat));
2038 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2040 if (regno < FIRST_PSEUDO_REGISTER
2041 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2042 && ! REG_USERVAR_P (SET_DEST (newpat))))
2044 if (regno >= FIRST_PSEUDO_REGISTER)
2045 SUBST (regno_reg_rtx[regno], new_dest);
2047 SUBST (SET_DEST (newpat), new_dest);
2048 SUBST (XEXP (*cc_use, 0), new_dest);
2049 SUBST (SET_SRC (newpat),
2050 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2053 undobuf.other_insn = 0;
2060 n_occurrences = 0; /* `subst' counts here */
2062 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2063 need to make a unique copy of I2SRC each time we substitute it
2064 to avoid self-referential rtl. */
2066 subst_low_cuid = INSN_CUID (i2);
2067 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2068 ! i1_feeds_i3 && i1dest_in_i1src);
2071 /* Record whether i2's body now appears within i3's body. */
2072 i2_is_used = n_occurrences;
2075 /* If we already got a failure, don't try to do more. Otherwise,
2076 try to substitute in I1 if we have it. */
2078 if (i1 && GET_CODE (newpat) != CLOBBER)
2080 /* Before we can do this substitution, we must redo the test done
2081 above (see detailed comments there) that ensures that I1DEST
2082 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2084 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2092 subst_low_cuid = INSN_CUID (i1);
2093 newpat = subst (newpat, i1dest, i1src, 0, 0);
2097 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2098 to count all the ways that I2SRC and I1SRC can be used. */
2099 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2100 && i2_is_used + added_sets_2 > 1)
2101 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2102 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2104 /* Fail if we tried to make a new register. */
2105 || max_reg_num () != maxreg
2106 /* Fail if we couldn't do something and have a CLOBBER. */
2107 || GET_CODE (newpat) == CLOBBER
2108 /* Fail if this new pattern is a MULT and we didn't have one before
2109 at the outer level. */
2110 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2117 /* If the actions of the earlier insns must be kept
2118 in addition to substituting them into the latest one,
2119 we must make a new PARALLEL for the latest insn
2120 to hold additional the SETs. */
2122 if (added_sets_1 || added_sets_2)
2126 if (GET_CODE (newpat) == PARALLEL)
2128 rtvec old = XVEC (newpat, 0);
2129 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2130 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2131 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2132 sizeof (old->elem[0]) * old->num_elem);
2137 total_sets = 1 + added_sets_1 + added_sets_2;
2138 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2139 XVECEXP (newpat, 0, 0) = old;
2143 XVECEXP (newpat, 0, --total_sets)
2144 = (GET_CODE (PATTERN (i1)) == PARALLEL
2145 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2149 /* If there is no I1, use I2's body as is. We used to also not do
2150 the subst call below if I2 was substituted into I3,
2151 but that could lose a simplification. */
2153 XVECEXP (newpat, 0, --total_sets) = i2pat;
2155 /* See comment where i2pat is assigned. */
2156 XVECEXP (newpat, 0, --total_sets)
2157 = subst (i2pat, i1dest, i1src, 0, 0);
2161 /* We come here when we are replacing a destination in I2 with the
2162 destination of I3. */
2163 validate_replacement:
2165 /* Note which hard regs this insn has as inputs. */
2166 mark_used_regs_combine (newpat);
2168 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2169 consider splitting this pattern, we might need these clobbers. */
2170 if (i1 && GET_CODE (newpat) == PARALLEL
2171 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2173 int len = XVECLEN (newpat, 0);
2175 newpat_vec_with_clobbers = rtvec_alloc (len);
2176 for (i = 0; i < len; i++)
2177 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2180 /* Is the result of combination a valid instruction? */
2181 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2183 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2184 the second SET's destination is a register that is unused and isn't
2185 marked as an instruction that might trap in an EH region. In that case,
2186 we just need the first SET. This can occur when simplifying a divmod
2187 insn. We *must* test for this case here because the code below that
2188 splits two independent SETs doesn't handle this case correctly when it
2189 updates the register status.
2191 It's pointless doing this if we originally had two sets, one from
2192 i3, and one from i2. Combining then splitting the parallel results
2193 in the original i2 again plus an invalid insn (which we delete).
2194 The net effect is only to move instructions around, which makes
2195 debug info less accurate.
2197 Also check the case where the first SET's destination is unused.
2198 That would not cause incorrect code, but does cause an unneeded
2201 if (insn_code_number < 0
2202 && !(added_sets_2 && i1 == 0)
2203 && GET_CODE (newpat) == PARALLEL
2204 && XVECLEN (newpat, 0) == 2
2205 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2206 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2207 && asm_noperands (newpat) < 0)
2209 rtx set0 = XVECEXP (newpat, 0, 0);
2210 rtx set1 = XVECEXP (newpat, 0, 1);
2213 if (((REG_P (SET_DEST (set1))
2214 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2215 || (GET_CODE (SET_DEST (set1)) == SUBREG
2216 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2217 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2218 || INTVAL (XEXP (note, 0)) <= 0)
2219 && ! side_effects_p (SET_SRC (set1)))
2222 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2225 else if (((REG_P (SET_DEST (set0))
2226 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2227 || (GET_CODE (SET_DEST (set0)) == SUBREG
2228 && find_reg_note (i3, REG_UNUSED,
2229 SUBREG_REG (SET_DEST (set0)))))
2230 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2231 || INTVAL (XEXP (note, 0)) <= 0)
2232 && ! side_effects_p (SET_SRC (set0)))
2235 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2237 if (insn_code_number >= 0)
2239 /* If we will be able to accept this, we have made a
2240 change to the destination of I3. This requires us to
2241 do a few adjustments. */
2243 PATTERN (i3) = newpat;
2244 adjust_for_new_dest (i3);
2249 /* If we were combining three insns and the result is a simple SET
2250 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2251 insns. There are two ways to do this. It can be split using a
2252 machine-specific method (like when you have an addition of a large
2253 constant) or by combine in the function find_split_point. */
2255 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2256 && asm_noperands (newpat) < 0)
2258 rtx m_split, *split;
2259 rtx ni2dest = i2dest;
2261 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2262 use I2DEST as a scratch register will help. In the latter case,
2263 convert I2DEST to the mode of the source of NEWPAT if we can. */
2265 m_split = split_insns (newpat, i3);
2267 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2268 inputs of NEWPAT. */
2270 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2271 possible to try that as a scratch reg. This would require adding
2272 more code to make it work though. */
2274 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2276 /* If I2DEST is a hard register or the only use of a pseudo,
2277 we can change its mode. */
2278 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2279 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2281 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2282 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2283 && ! REG_USERVAR_P (i2dest))))
2284 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2287 m_split = split_insns (gen_rtx_PARALLEL
2289 gen_rtvec (2, newpat,
2290 gen_rtx_CLOBBER (VOIDmode,
2293 /* If the split with the mode-changed register didn't work, try
2294 the original register. */
2295 if (! m_split && ni2dest != i2dest)
2298 m_split = split_insns (gen_rtx_PARALLEL
2300 gen_rtvec (2, newpat,
2301 gen_rtx_CLOBBER (VOIDmode,
2307 /* If recog_for_combine has discarded clobbers, try to use them
2308 again for the split. */
2309 if (m_split == 0 && newpat_vec_with_clobbers)
2311 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2312 newpat_vec_with_clobbers), i3);
2314 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2316 m_split = PATTERN (m_split);
2317 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2318 if (insn_code_number >= 0)
2321 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2322 && (next_real_insn (i2) == i3
2323 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2326 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2327 newi2pat = PATTERN (m_split);
2329 i3set = single_set (NEXT_INSN (m_split));
2330 i2set = single_set (m_split);
2332 /* In case we changed the mode of I2DEST, replace it in the
2333 pseudo-register table here. We can't do it above in case this
2334 code doesn't get executed and we do a split the other way. */
2336 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2337 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2339 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2341 /* If I2 or I3 has multiple SETs, we won't know how to track
2342 register status, so don't use these insns. If I2's destination
2343 is used between I2 and I3, we also can't use these insns. */
2345 if (i2_code_number >= 0 && i2set && i3set
2346 && (next_real_insn (i2) == i3
2347 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2348 insn_code_number = recog_for_combine (&newi3pat, i3,
2350 if (insn_code_number >= 0)
2353 /* It is possible that both insns now set the destination of I3.
2354 If so, we must show an extra use of it. */
2356 if (insn_code_number >= 0)
2358 rtx new_i3_dest = SET_DEST (i3set);
2359 rtx new_i2_dest = SET_DEST (i2set);
2361 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2362 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2363 || GET_CODE (new_i3_dest) == SUBREG)
2364 new_i3_dest = XEXP (new_i3_dest, 0);
2366 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2367 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2368 || GET_CODE (new_i2_dest) == SUBREG)
2369 new_i2_dest = XEXP (new_i2_dest, 0);
2371 if (REG_P (new_i3_dest)
2372 && REG_P (new_i2_dest)
2373 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2374 REG_N_SETS (REGNO (new_i2_dest))++;
2378 /* If we can split it and use I2DEST, go ahead and see if that
2379 helps things be recognized. Verify that none of the registers
2380 are set between I2 and I3. */
2381 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2385 /* We need I2DEST in the proper mode. If it is a hard register
2386 or the only use of a pseudo, we can change its mode.
2387 Make sure we don't change a hard register to have a mode that
2388 isn't valid for it, or change the number of registers. */
2389 && (GET_MODE (*split) == GET_MODE (i2dest)
2390 || GET_MODE (*split) == VOIDmode
2391 || (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2392 && HARD_REGNO_MODE_OK (REGNO (i2dest), GET_MODE (*split))
2393 && (hard_regno_nregs[REGNO (i2dest)][GET_MODE (i2dest)]
2394 == hard_regno_nregs[REGNO (i2dest)][GET_MODE (*split)]))
2395 || (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER
2396 && REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2397 && ! REG_USERVAR_P (i2dest)))
2398 && (next_real_insn (i2) == i3
2399 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2400 /* We can't overwrite I2DEST if its value is still used by
2402 && ! reg_referenced_p (i2dest, newpat))
2404 rtx newdest = i2dest;
2405 enum rtx_code split_code = GET_CODE (*split);
2406 enum machine_mode split_mode = GET_MODE (*split);
2408 /* Get NEWDEST as a register in the proper mode. We have already
2409 validated that we can do this. */
2410 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2412 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2414 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2415 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2418 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2419 an ASHIFT. This can occur if it was inside a PLUS and hence
2420 appeared to be a memory address. This is a kludge. */
2421 if (split_code == MULT
2422 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2423 && INTVAL (XEXP (*split, 1)) > 0
2424 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2426 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2427 XEXP (*split, 0), GEN_INT (i)));
2428 /* Update split_code because we may not have a multiply
2430 split_code = GET_CODE (*split);
2433 #ifdef INSN_SCHEDULING
2434 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2435 be written as a ZERO_EXTEND. */
2436 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2438 #ifdef LOAD_EXTEND_OP
2439 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2440 what it really is. */
2441 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2443 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2444 SUBREG_REG (*split)));
2447 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2448 SUBREG_REG (*split)));
2452 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2453 SUBST (*split, newdest);
2454 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2456 /* recog_for_combine might have added CLOBBERs to newi2pat.
2457 Make sure NEWPAT does not depend on the clobbered regs. */
2458 if (GET_CODE (newi2pat) == PARALLEL)
2459 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2460 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2462 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2463 if (reg_overlap_mentioned_p (reg, newpat))
2470 /* If the split point was a MULT and we didn't have one before,
2471 don't use one now. */
2472 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2473 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2477 /* Check for a case where we loaded from memory in a narrow mode and
2478 then sign extended it, but we need both registers. In that case,
2479 we have a PARALLEL with both loads from the same memory location.
2480 We can split this into a load from memory followed by a register-register
2481 copy. This saves at least one insn, more if register allocation can
2484 We cannot do this if the destination of the first assignment is a
2485 condition code register or cc0. We eliminate this case by making sure
2486 the SET_DEST and SET_SRC have the same mode.
2488 We cannot do this if the destination of the second assignment is
2489 a register that we have already assumed is zero-extended. Similarly
2490 for a SUBREG of such a register. */
2492 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2493 && GET_CODE (newpat) == PARALLEL
2494 && XVECLEN (newpat, 0) == 2
2495 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2496 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2497 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2498 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2499 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2500 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2501 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2502 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2504 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2505 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2506 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2508 && reg_stat[REGNO (temp)].nonzero_bits != 0
2509 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2510 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2511 && (reg_stat[REGNO (temp)].nonzero_bits
2512 != GET_MODE_MASK (word_mode))))
2513 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2514 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2516 && reg_stat[REGNO (temp)].nonzero_bits != 0
2517 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2518 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2519 && (reg_stat[REGNO (temp)].nonzero_bits
2520 != GET_MODE_MASK (word_mode)))))
2521 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2522 SET_SRC (XVECEXP (newpat, 0, 1)))
2523 && ! find_reg_note (i3, REG_UNUSED,
2524 SET_DEST (XVECEXP (newpat, 0, 0))))
2528 newi2pat = XVECEXP (newpat, 0, 0);
2529 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2530 newpat = XVECEXP (newpat, 0, 1);
2531 SUBST (SET_SRC (newpat),
2532 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2533 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2535 if (i2_code_number >= 0)
2536 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2538 if (insn_code_number >= 0)
2542 /* Similarly, check for a case where we have a PARALLEL of two independent
2543 SETs but we started with three insns. In this case, we can do the sets
2544 as two separate insns. This case occurs when some SET allows two
2545 other insns to combine, but the destination of that SET is still live. */
2547 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2548 && GET_CODE (newpat) == PARALLEL
2549 && XVECLEN (newpat, 0) == 2
2550 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2551 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2552 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2553 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2554 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2555 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2556 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2558 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2559 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2560 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2561 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2562 XVECEXP (newpat, 0, 0))
2563 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2564 XVECEXP (newpat, 0, 1))
2565 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2566 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2568 /* Normally, it doesn't matter which of the two is done first,
2569 but it does if one references cc0. In that case, it has to
2572 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2574 newi2pat = XVECEXP (newpat, 0, 0);
2575 newpat = XVECEXP (newpat, 0, 1);
2580 newi2pat = XVECEXP (newpat, 0, 1);
2581 newpat = XVECEXP (newpat, 0, 0);
2584 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2586 if (i2_code_number >= 0)
2587 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2590 /* If it still isn't recognized, fail and change things back the way they
2592 if ((insn_code_number < 0
2593 /* Is the result a reasonable ASM_OPERANDS? */
2594 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2600 /* If we had to change another insn, make sure it is valid also. */
2601 if (undobuf.other_insn)
2603 rtx other_pat = PATTERN (undobuf.other_insn);
2604 rtx new_other_notes;
2607 CLEAR_HARD_REG_SET (newpat_used_regs);
2609 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2612 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2618 PATTERN (undobuf.other_insn) = other_pat;
2620 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2621 are still valid. Then add any non-duplicate notes added by
2622 recog_for_combine. */
2623 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2625 next = XEXP (note, 1);
2627 if (REG_NOTE_KIND (note) == REG_UNUSED
2628 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2630 if (REG_P (XEXP (note, 0)))
2631 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2633 remove_note (undobuf.other_insn, note);
2637 for (note = new_other_notes; note; note = XEXP (note, 1))
2638 if (REG_P (XEXP (note, 0)))
2639 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2641 distribute_notes (new_other_notes, undobuf.other_insn,
2642 undobuf.other_insn, NULL_RTX);
2645 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2646 they are adjacent to each other or not. */
2648 rtx p = prev_nonnote_insn (i3);
2649 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2650 && sets_cc0_p (newi2pat))
2658 /* Only allow this combination if insn_rtx_costs reports that the
2659 replacement instructions are cheaper than the originals. */
2660 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2666 /* We now know that we can do this combination. Merge the insns and
2667 update the status of registers and LOG_LINKS. */
2675 /* I3 now uses what used to be its destination and which is now
2676 I2's destination. This requires us to do a few adjustments. */
2677 PATTERN (i3) = newpat;
2678 adjust_for_new_dest (i3);
2680 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2683 However, some later insn might be using I2's dest and have
2684 a LOG_LINK pointing at I3. We must remove this link.
2685 The simplest way to remove the link is to point it at I1,
2686 which we know will be a NOTE. */
2688 /* newi2pat is usually a SET here; however, recog_for_combine might
2689 have added some clobbers. */
2690 if (GET_CODE (newi2pat) == PARALLEL)
2691 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2693 ni2dest = SET_DEST (newi2pat);
2695 for (insn = NEXT_INSN (i3);
2696 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2697 || insn != BB_HEAD (this_basic_block->next_bb));
2698 insn = NEXT_INSN (insn))
2700 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2702 for (link = LOG_LINKS (insn); link;
2703 link = XEXP (link, 1))
2704 if (XEXP (link, 0) == i3)
2705 XEXP (link, 0) = i1;
2713 rtx i3notes, i2notes, i1notes = 0;
2714 rtx i3links, i2links, i1links = 0;
2718 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2720 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2721 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2723 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2725 /* Ensure that we do not have something that should not be shared but
2726 occurs multiple times in the new insns. Check this by first
2727 resetting all the `used' flags and then copying anything is shared. */
2729 reset_used_flags (i3notes);
2730 reset_used_flags (i2notes);
2731 reset_used_flags (i1notes);
2732 reset_used_flags (newpat);
2733 reset_used_flags (newi2pat);
2734 if (undobuf.other_insn)
2735 reset_used_flags (PATTERN (undobuf.other_insn));
2737 i3notes = copy_rtx_if_shared (i3notes);
2738 i2notes = copy_rtx_if_shared (i2notes);
2739 i1notes = copy_rtx_if_shared (i1notes);
2740 newpat = copy_rtx_if_shared (newpat);
2741 newi2pat = copy_rtx_if_shared (newi2pat);
2742 if (undobuf.other_insn)
2743 reset_used_flags (PATTERN (undobuf.other_insn));
2745 INSN_CODE (i3) = insn_code_number;
2746 PATTERN (i3) = newpat;
2748 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2750 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2752 reset_used_flags (call_usage);
2753 call_usage = copy_rtx (call_usage);
2756 replace_rtx (call_usage, i2dest, i2src);
2759 replace_rtx (call_usage, i1dest, i1src);
2761 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2764 if (undobuf.other_insn)
2765 INSN_CODE (undobuf.other_insn) = other_code_number;
2767 /* We had one special case above where I2 had more than one set and
2768 we replaced a destination of one of those sets with the destination
2769 of I3. In that case, we have to update LOG_LINKS of insns later
2770 in this basic block. Note that this (expensive) case is rare.
2772 Also, in this case, we must pretend that all REG_NOTEs for I2
2773 actually came from I3, so that REG_UNUSED notes from I2 will be
2774 properly handled. */
2776 if (i3_subst_into_i2)
2778 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2779 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2780 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2781 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2782 && ! find_reg_note (i2, REG_UNUSED,
2783 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2784 for (temp = NEXT_INSN (i2);
2785 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2786 || BB_HEAD (this_basic_block) != temp);
2787 temp = NEXT_INSN (temp))
2788 if (temp != i3 && INSN_P (temp))
2789 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2790 if (XEXP (link, 0) == i2)
2791 XEXP (link, 0) = i3;
2796 while (XEXP (link, 1))
2797 link = XEXP (link, 1);
2798 XEXP (link, 1) = i2notes;
2812 INSN_CODE (i2) = i2_code_number;
2813 PATTERN (i2) = newi2pat;
2816 SET_INSN_DELETED (i2);
2822 SET_INSN_DELETED (i1);
2825 /* Get death notes for everything that is now used in either I3 or
2826 I2 and used to die in a previous insn. If we built two new
2827 patterns, move from I1 to I2 then I2 to I3 so that we get the
2828 proper movement on registers that I2 modifies. */
2832 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2833 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2836 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2839 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2841 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2843 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2845 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2847 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2849 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2850 know these are REG_UNUSED and want them to go to the desired insn,
2851 so we always pass it as i3. We have not counted the notes in
2852 reg_n_deaths yet, so we need to do so now. */
2854 if (newi2pat && new_i2_notes)
2856 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2857 if (REG_P (XEXP (temp, 0)))
2858 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2860 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2865 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2866 if (REG_P (XEXP (temp, 0)))
2867 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2869 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2872 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2873 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2874 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2875 in that case, it might delete I2. Similarly for I2 and I1.
2876 Show an additional death due to the REG_DEAD note we make here. If
2877 we discard it in distribute_notes, we will decrement it again. */
2881 if (REG_P (i3dest_killed))
2882 REG_N_DEATHS (REGNO (i3dest_killed))++;
2884 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2885 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2887 NULL_RTX, i2, NULL_RTX);
2889 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2891 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2894 if (i2dest_in_i2src)
2897 REG_N_DEATHS (REGNO (i2dest))++;
2899 if (newi2pat && reg_set_p (i2dest, newi2pat))
2900 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2901 NULL_RTX, i2, NULL_RTX);
2903 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2904 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2907 if (i1dest_in_i1src)
2910 REG_N_DEATHS (REGNO (i1dest))++;
2912 if (newi2pat && reg_set_p (i1dest, newi2pat))
2913 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2914 NULL_RTX, i2, NULL_RTX);
2916 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2917 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2920 distribute_links (i3links);
2921 distribute_links (i2links);
2922 distribute_links (i1links);
2927 rtx i2_insn = 0, i2_val = 0, set;
2929 /* The insn that used to set this register doesn't exist, and
2930 this life of the register may not exist either. See if one of
2931 I3's links points to an insn that sets I2DEST. If it does,
2932 that is now the last known value for I2DEST. If we don't update
2933 this and I2 set the register to a value that depended on its old
2934 contents, we will get confused. If this insn is used, thing
2935 will be set correctly in combine_instructions. */
2937 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2938 if ((set = single_set (XEXP (link, 0))) != 0
2939 && rtx_equal_p (i2dest, SET_DEST (set)))
2940 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2942 record_value_for_reg (i2dest, i2_insn, i2_val);
2944 /* If the reg formerly set in I2 died only once and that was in I3,
2945 zero its use count so it won't make `reload' do any work. */
2947 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2948 && ! i2dest_in_i2src)
2950 regno = REGNO (i2dest);
2951 REG_N_SETS (regno)--;
2955 if (i1 && REG_P (i1dest))
2958 rtx i1_insn = 0, i1_val = 0, set;
2960 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2961 if ((set = single_set (XEXP (link, 0))) != 0
2962 && rtx_equal_p (i1dest, SET_DEST (set)))
2963 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2965 record_value_for_reg (i1dest, i1_insn, i1_val);
2967 regno = REGNO (i1dest);
2968 if (! added_sets_1 && ! i1dest_in_i1src)
2969 REG_N_SETS (regno)--;
2972 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2973 been made to this insn. The order of
2974 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2975 can affect nonzero_bits of newpat */
2977 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2978 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2980 /* Set new_direct_jump_p if a new return or simple jump instruction
2983 If I3 is now an unconditional jump, ensure that it has a
2984 BARRIER following it since it may have initially been a
2985 conditional jump. It may also be the last nonnote insn. */
2987 if (returnjump_p (i3) || any_uncondjump_p (i3))
2989 *new_direct_jump_p = 1;
2990 mark_jump_label (PATTERN (i3), i3, 0);
2992 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2993 || !BARRIER_P (temp))
2994 emit_barrier_after (i3);
2997 if (undobuf.other_insn != NULL_RTX
2998 && (returnjump_p (undobuf.other_insn)
2999 || any_uncondjump_p (undobuf.other_insn)))
3001 *new_direct_jump_p = 1;
3003 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3004 || !BARRIER_P (temp))
3005 emit_barrier_after (undobuf.other_insn);
3008 /* An NOOP jump does not need barrier, but it does need cleaning up
3010 if (GET_CODE (newpat) == SET
3011 && SET_SRC (newpat) == pc_rtx
3012 && SET_DEST (newpat) == pc_rtx)
3013 *new_direct_jump_p = 1;
3016 combine_successes++;
3019 if (added_links_insn
3020 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3021 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3022 return added_links_insn;
3024 return newi2pat ? i2 : i3;
3027 /* Undo all the modifications recorded in undobuf. */
3032 struct undo *undo, *next;
3034 for (undo = undobuf.undos; undo; undo = next)
3038 *undo->where.i = undo->old_contents.i;
3040 *undo->where.r = undo->old_contents.r;
3042 undo->next = undobuf.frees;
3043 undobuf.frees = undo;
3049 /* We've committed to accepting the changes we made. Move all
3050 of the undos to the free list. */
3055 struct undo *undo, *next;
3057 for (undo = undobuf.undos; undo; undo = next)
3060 undo->next = undobuf.frees;
3061 undobuf.frees = undo;
3067 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3068 where we have an arithmetic expression and return that point. LOC will
3071 try_combine will call this function to see if an insn can be split into
3075 find_split_point (rtx *loc, rtx insn)
3078 enum rtx_code code = GET_CODE (x);
3080 unsigned HOST_WIDE_INT len = 0;
3081 HOST_WIDE_INT pos = 0;
3083 rtx inner = NULL_RTX;
3085 /* First special-case some codes. */
3089 #ifdef INSN_SCHEDULING
3090 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3092 if (MEM_P (SUBREG_REG (x)))
3095 return find_split_point (&SUBREG_REG (x), insn);
3099 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3100 using LO_SUM and HIGH. */
3101 if (GET_CODE (XEXP (x, 0)) == CONST
3102 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3105 gen_rtx_LO_SUM (Pmode,
3106 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3108 return &XEXP (XEXP (x, 0), 0);
3112 /* If we have a PLUS whose second operand is a constant and the
3113 address is not valid, perhaps will can split it up using
3114 the machine-specific way to split large constants. We use
3115 the first pseudo-reg (one of the virtual regs) as a placeholder;
3116 it will not remain in the result. */
3117 if (GET_CODE (XEXP (x, 0)) == PLUS
3118 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3119 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3121 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3122 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3125 /* This should have produced two insns, each of which sets our
3126 placeholder. If the source of the second is a valid address,
3127 we can make put both sources together and make a split point
3131 && NEXT_INSN (seq) != NULL_RTX
3132 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3133 && NONJUMP_INSN_P (seq)
3134 && GET_CODE (PATTERN (seq)) == SET
3135 && SET_DEST (PATTERN (seq)) == reg
3136 && ! reg_mentioned_p (reg,
3137 SET_SRC (PATTERN (seq)))
3138 && NONJUMP_INSN_P (NEXT_INSN (seq))
3139 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3140 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3141 && memory_address_p (GET_MODE (x),
3142 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3144 rtx src1 = SET_SRC (PATTERN (seq));
3145 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3147 /* Replace the placeholder in SRC2 with SRC1. If we can
3148 find where in SRC2 it was placed, that can become our
3149 split point and we can replace this address with SRC2.
3150 Just try two obvious places. */
3152 src2 = replace_rtx (src2, reg, src1);
3154 if (XEXP (src2, 0) == src1)
3155 split = &XEXP (src2, 0);
3156 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3157 && XEXP (XEXP (src2, 0), 0) == src1)
3158 split = &XEXP (XEXP (src2, 0), 0);
3162 SUBST (XEXP (x, 0), src2);
3167 /* If that didn't work, perhaps the first operand is complex and
3168 needs to be computed separately, so make a split point there.
3169 This will occur on machines that just support REG + CONST
3170 and have a constant moved through some previous computation. */
3172 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3173 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3174 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3175 return &XEXP (XEXP (x, 0), 0);
3181 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3182 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3183 we need to put the operand into a register. So split at that
3186 if (SET_DEST (x) == cc0_rtx
3187 && GET_CODE (SET_SRC (x)) != COMPARE
3188 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3189 && !OBJECT_P (SET_SRC (x))
3190 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3191 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3192 return &SET_SRC (x);
3195 /* See if we can split SET_SRC as it stands. */
3196 split = find_split_point (&SET_SRC (x), insn);
3197 if (split && split != &SET_SRC (x))
3200 /* See if we can split SET_DEST as it stands. */
3201 split = find_split_point (&SET_DEST (x), insn);
3202 if (split && split != &SET_DEST (x))
3205 /* See if this is a bitfield assignment with everything constant. If
3206 so, this is an IOR of an AND, so split it into that. */
3207 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3208 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3209 <= HOST_BITS_PER_WIDE_INT)
3210 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3211 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3212 && GET_CODE (SET_SRC (x)) == CONST_INT
3213 && ((INTVAL (XEXP (SET_DEST (x), 1))
3214 + INTVAL (XEXP (SET_DEST (x), 2)))
3215 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3216 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3218 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3219 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3220 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3221 rtx dest = XEXP (SET_DEST (x), 0);
3222 enum machine_mode mode = GET_MODE (dest);
3223 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3225 if (BITS_BIG_ENDIAN)
3226 pos = GET_MODE_BITSIZE (mode) - len - pos;
3230 simplify_gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3233 rtx negmask = gen_int_mode (~(mask << pos), mode);
3235 simplify_gen_binary (IOR, mode,
3236 simplify_gen_binary (AND, mode,
3238 GEN_INT (src << pos)));
3241 SUBST (SET_DEST (x), dest);
3243 split = find_split_point (&SET_SRC (x), insn);
3244 if (split && split != &SET_SRC (x))
3248 /* Otherwise, see if this is an operation that we can split into two.
3249 If so, try to split that. */
3250 code = GET_CODE (SET_SRC (x));
3255 /* If we are AND'ing with a large constant that is only a single
3256 bit and the result is only being used in a context where we
3257 need to know if it is zero or nonzero, replace it with a bit
3258 extraction. This will avoid the large constant, which might
3259 have taken more than one insn to make. If the constant were
3260 not a valid argument to the AND but took only one insn to make,
3261 this is no worse, but if it took more than one insn, it will
3264 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3265 && REG_P (XEXP (SET_SRC (x), 0))
3266 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3267 && REG_P (SET_DEST (x))
3268 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3269 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3270 && XEXP (*split, 0) == SET_DEST (x)
3271 && XEXP (*split, 1) == const0_rtx)
3273 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3274 XEXP (SET_SRC (x), 0),
3275 pos, NULL_RTX, 1, 1, 0, 0);
3276 if (extraction != 0)
3278 SUBST (SET_SRC (x), extraction);
3279 return find_split_point (loc, insn);
3285 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3286 is known to be on, this can be converted into a NEG of a shift. */
3287 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3288 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3289 && 1 <= (pos = exact_log2
3290 (nonzero_bits (XEXP (SET_SRC (x), 0),
3291 GET_MODE (XEXP (SET_SRC (x), 0))))))
3293 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3297 gen_rtx_LSHIFTRT (mode,
3298 XEXP (SET_SRC (x), 0),
3301 split = find_split_point (&SET_SRC (x), insn);
3302 if (split && split != &SET_SRC (x))
3308 inner = XEXP (SET_SRC (x), 0);
3310 /* We can't optimize if either mode is a partial integer
3311 mode as we don't know how many bits are significant
3313 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3314 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3318 len = GET_MODE_BITSIZE (GET_MODE (inner));
3324 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3325 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3327 inner = XEXP (SET_SRC (x), 0);
3328 len = INTVAL (XEXP (SET_SRC (x), 1));
3329 pos = INTVAL (XEXP (SET_SRC (x), 2));
3331 if (BITS_BIG_ENDIAN)
3332 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3333 unsignedp = (code == ZERO_EXTRACT);
3341 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3343 enum machine_mode mode = GET_MODE (SET_SRC (x));
3345 /* For unsigned, we have a choice of a shift followed by an
3346 AND or two shifts. Use two shifts for field sizes where the
3347 constant might be too large. We assume here that we can
3348 always at least get 8-bit constants in an AND insn, which is
3349 true for every current RISC. */
3351 if (unsignedp && len <= 8)
3356 (mode, gen_lowpart (mode, inner),
3358 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3360 split = find_split_point (&SET_SRC (x), insn);
3361 if (split && split != &SET_SRC (x))
3368 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3369 gen_rtx_ASHIFT (mode,
3370 gen_lowpart (mode, inner),
3371 GEN_INT (GET_MODE_BITSIZE (mode)
3373 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3375 split = find_split_point (&SET_SRC (x), insn);
3376 if (split && split != &SET_SRC (x))
3381 /* See if this is a simple operation with a constant as the second
3382 operand. It might be that this constant is out of range and hence
3383 could be used as a split point. */
3384 if (BINARY_P (SET_SRC (x))
3385 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3386 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3387 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3388 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3389 return &XEXP (SET_SRC (x), 1);
3391 /* Finally, see if this is a simple operation with its first operand
3392 not in a register. The operation might require this operand in a
3393 register, so return it as a split point. We can always do this
3394 because if the first operand were another operation, we would have
3395 already found it as a split point. */
3396 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3397 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3398 return &XEXP (SET_SRC (x), 0);
3404 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3405 it is better to write this as (not (ior A B)) so we can split it.
3406 Similarly for IOR. */
3407 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3410 gen_rtx_NOT (GET_MODE (x),
3411 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3413 XEXP (XEXP (x, 0), 0),
3414 XEXP (XEXP (x, 1), 0))));
3415 return find_split_point (loc, insn);
3418 /* Many RISC machines have a large set of logical insns. If the
3419 second operand is a NOT, put it first so we will try to split the
3420 other operand first. */
3421 if (GET_CODE (XEXP (x, 1)) == NOT)
3423 rtx tem = XEXP (x, 0);
3424 SUBST (XEXP (x, 0), XEXP (x, 1));
3425 SUBST (XEXP (x, 1), tem);
3433 /* Otherwise, select our actions depending on our rtx class. */
3434 switch (GET_RTX_CLASS (code))
3436 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3438 split = find_split_point (&XEXP (x, 2), insn);
3441 /* ... fall through ... */
3443 case RTX_COMM_ARITH:
3445 case RTX_COMM_COMPARE:
3446 split = find_split_point (&XEXP (x, 1), insn);
3449 /* ... fall through ... */
3451 /* Some machines have (and (shift ...) ...) insns. If X is not
3452 an AND, but XEXP (X, 0) is, use it as our split point. */
3453 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3454 return &XEXP (x, 0);
3456 split = find_split_point (&XEXP (x, 0), insn);
3462 /* Otherwise, we don't have a split point. */
3467 /* Throughout X, replace FROM with TO, and return the result.
3468 The result is TO if X is FROM;
3469 otherwise the result is X, but its contents may have been modified.
3470 If they were modified, a record was made in undobuf so that
3471 undo_all will (among other things) return X to its original state.
3473 If the number of changes necessary is too much to record to undo,
3474 the excess changes are not made, so the result is invalid.
3475 The changes already made can still be undone.
3476 undobuf.num_undo is incremented for such changes, so by testing that
3477 the caller can tell whether the result is valid.
3479 `n_occurrences' is incremented each time FROM is replaced.
3481 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3483 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3484 by copying if `n_occurrences' is nonzero. */
3487 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3489 enum rtx_code code = GET_CODE (x);
3490 enum machine_mode op0_mode = VOIDmode;
3495 /* Two expressions are equal if they are identical copies of a shared
3496 RTX or if they are both registers with the same register number
3499 #define COMBINE_RTX_EQUAL_P(X,Y) \
3501 || (REG_P (X) && REG_P (Y) \
3502 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3504 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3507 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3510 /* If X and FROM are the same register but different modes, they will
3511 not have been seen as equal above. However, flow.c will make a
3512 LOG_LINKS entry for that case. If we do nothing, we will try to
3513 rerecognize our original insn and, when it succeeds, we will
3514 delete the feeding insn, which is incorrect.
3516 So force this insn not to match in this (rare) case. */
3517 if (! in_dest && code == REG && REG_P (from)
3518 && REGNO (x) == REGNO (from))
3519 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3521 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3522 of which may contain things that can be combined. */
3523 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3526 /* It is possible to have a subexpression appear twice in the insn.
3527 Suppose that FROM is a register that appears within TO.
3528 Then, after that subexpression has been scanned once by `subst',
3529 the second time it is scanned, TO may be found. If we were
3530 to scan TO here, we would find FROM within it and create a
3531 self-referent rtl structure which is completely wrong. */
3532 if (COMBINE_RTX_EQUAL_P (x, to))
3535 /* Parallel asm_operands need special attention because all of the
3536 inputs are shared across the arms. Furthermore, unsharing the
3537 rtl results in recognition failures. Failure to handle this case
3538 specially can result in circular rtl.
3540 Solve this by doing a normal pass across the first entry of the
3541 parallel, and only processing the SET_DESTs of the subsequent
3544 if (code == PARALLEL
3545 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3546 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3548 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3550 /* If this substitution failed, this whole thing fails. */
3551 if (GET_CODE (new) == CLOBBER
3552 && XEXP (new, 0) == const0_rtx)
3555 SUBST (XVECEXP (x, 0, 0), new);
3557 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3559 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3562 && GET_CODE (dest) != CC0
3563 && GET_CODE (dest) != PC)
3565 new = subst (dest, from, to, 0, unique_copy);
3567 /* If this substitution failed, this whole thing fails. */
3568 if (GET_CODE (new) == CLOBBER
3569 && XEXP (new, 0) == const0_rtx)
3572 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3578 len = GET_RTX_LENGTH (code);
3579 fmt = GET_RTX_FORMAT (code);
3581 /* We don't need to process a SET_DEST that is a register, CC0,
3582 or PC, so set up to skip this common case. All other cases
3583 where we want to suppress replacing something inside a
3584 SET_SRC are handled via the IN_DEST operand. */
3586 && (REG_P (SET_DEST (x))
3587 || GET_CODE (SET_DEST (x)) == CC0
3588 || GET_CODE (SET_DEST (x)) == PC))
3591 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3594 op0_mode = GET_MODE (XEXP (x, 0));
3596 for (i = 0; i < len; i++)
3601 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3603 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3605 new = (unique_copy && n_occurrences
3606 ? copy_rtx (to) : to);
3611 new = subst (XVECEXP (x, i, j), from, to, 0,
3614 /* If this substitution failed, this whole thing
3616 if (GET_CODE (new) == CLOBBER
3617 && XEXP (new, 0) == const0_rtx)
3621 SUBST (XVECEXP (x, i, j), new);
3624 else if (fmt[i] == 'e')
3626 /* If this is a register being set, ignore it. */
3630 && (((code == SUBREG || code == ZERO_EXTRACT)
3632 || code == STRICT_LOW_PART))
3635 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3637 /* In general, don't install a subreg involving two
3638 modes not tieable. It can worsen register
3639 allocation, and can even make invalid reload
3640 insns, since the reg inside may need to be copied
3641 from in the outside mode, and that may be invalid
3642 if it is an fp reg copied in integer mode.
3644 We allow two exceptions to this: It is valid if
3645 it is inside another SUBREG and the mode of that
3646 SUBREG and the mode of the inside of TO is
3647 tieable and it is valid if X is a SET that copies
3650 if (GET_CODE (to) == SUBREG
3651 && ! MODES_TIEABLE_P (GET_MODE (to),
3652 GET_MODE (SUBREG_REG (to)))
3653 && ! (code == SUBREG
3654 && MODES_TIEABLE_P (GET_MODE (x),
3655 GET_MODE (SUBREG_REG (to))))
3657 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3660 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3662 #ifdef CANNOT_CHANGE_MODE_CLASS
3665 && REGNO (to) < FIRST_PSEUDO_REGISTER
3666 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3669 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3672 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3676 /* If we are in a SET_DEST, suppress most cases unless we
3677 have gone inside a MEM, in which case we want to
3678 simplify the address. We assume here that things that
3679 are actually part of the destination have their inner
3680 parts in the first expression. This is true for SUBREG,
3681 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3682 things aside from REG and MEM that should appear in a
3684 new = subst (XEXP (x, i), from, to,
3686 && (code == SUBREG || code == STRICT_LOW_PART
3687 || code == ZERO_EXTRACT))
3689 && i == 0), unique_copy);
3691 /* If we found that we will have to reject this combination,
3692 indicate that by returning the CLOBBER ourselves, rather than
3693 an expression containing it. This will speed things up as
3694 well as prevent accidents where two CLOBBERs are considered
3695 to be equal, thus producing an incorrect simplification. */
3697 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3700 if (GET_CODE (x) == SUBREG
3701 && (GET_CODE (new) == CONST_INT
3702 || GET_CODE (new) == CONST_DOUBLE))
3704 enum machine_mode mode = GET_MODE (x);
3706 x = simplify_subreg (GET_MODE (x), new,
3707 GET_MODE (SUBREG_REG (x)),
3710 x = gen_rtx_CLOBBER (mode, const0_rtx);
3712 else if (GET_CODE (new) == CONST_INT
3713 && GET_CODE (x) == ZERO_EXTEND)
3715 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3716 new, GET_MODE (XEXP (x, 0)));
3720 SUBST (XEXP (x, i), new);
3725 /* Try to simplify X. If the simplification changed the code, it is likely
3726 that further simplification will help, so loop, but limit the number
3727 of repetitions that will be performed. */
3729 for (i = 0; i < 4; i++)
3731 /* If X is sufficiently simple, don't bother trying to do anything
3733 if (code != CONST_INT && code != REG && code != CLOBBER)
3734 x = combine_simplify_rtx (x, op0_mode, in_dest);
3736 if (GET_CODE (x) == code)
3739 code = GET_CODE (x);
3741 /* We no longer know the original mode of operand 0 since we
3742 have changed the form of X) */
3743 op0_mode = VOIDmode;
3749 /* Simplify X, a piece of RTL. We just operate on the expression at the
3750 outer level; call `subst' to simplify recursively. Return the new
3753 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3754 if we are inside a SET_DEST. */
3757 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3759 enum rtx_code code = GET_CODE (x);
3760 enum machine_mode mode = GET_MODE (x);
3765 /* If this is a commutative operation, put a constant last and a complex
3766 expression first. We don't need to do this for comparisons here. */
3767 if (COMMUTATIVE_ARITH_P (x)
3768 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3771 SUBST (XEXP (x, 0), XEXP (x, 1));
3772 SUBST (XEXP (x, 1), temp);
3775 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3776 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3777 things. Check for cases where both arms are testing the same
3780 Don't do anything if all operands are very simple. */
3783 && ((!OBJECT_P (XEXP (x, 0))
3784 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3785 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3786 || (!OBJECT_P (XEXP (x, 1))
3787 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3788 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3790 && (!OBJECT_P (XEXP (x, 0))
3791 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3792 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3794 rtx cond, true_rtx, false_rtx;
3796 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3798 /* If everything is a comparison, what we have is highly unlikely
3799 to be simpler, so don't use it. */
3800 && ! (COMPARISON_P (x)
3801 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3803 rtx cop1 = const0_rtx;
3804 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3806 if (cond_code == NE && COMPARISON_P (cond))
3809 /* Simplify the alternative arms; this may collapse the true and
3810 false arms to store-flag values. Be careful to use copy_rtx
3811 here since true_rtx or false_rtx might share RTL with x as a
3812 result of the if_then_else_cond call above. */
3813 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3814 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3816 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3817 is unlikely to be simpler. */
3818 if (general_operand (true_rtx, VOIDmode)
3819 && general_operand (false_rtx, VOIDmode))
3821 enum rtx_code reversed;
3823 /* Restarting if we generate a store-flag expression will cause
3824 us to loop. Just drop through in this case. */
3826 /* If the result values are STORE_FLAG_VALUE and zero, we can
3827 just make the comparison operation. */
3828 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3829 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3831 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3832 && ((reversed = reversed_comparison_code_parts
3833 (cond_code, cond, cop1, NULL))
3835 x = simplify_gen_relational (reversed, mode, VOIDmode,
3838 /* Likewise, we can make the negate of a comparison operation
3839 if the result values are - STORE_FLAG_VALUE and zero. */
3840 else if (GET_CODE (true_rtx) == CONST_INT
3841 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3842 && false_rtx == const0_rtx)
3843 x = simplify_gen_unary (NEG, mode,
3844 simplify_gen_relational (cond_code,
3848 else if (GET_CODE (false_rtx) == CONST_INT
3849 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3850 && true_rtx == const0_rtx
3851 && ((reversed = reversed_comparison_code_parts
3852 (cond_code, cond, cop1, NULL))
3854 x = simplify_gen_unary (NEG, mode,
3855 simplify_gen_relational (reversed,
3860 return gen_rtx_IF_THEN_ELSE (mode,
3861 simplify_gen_relational (cond_code,
3866 true_rtx, false_rtx);
3868 code = GET_CODE (x);
3869 op0_mode = VOIDmode;
3874 /* Try to fold this expression in case we have constants that weren't
3877 switch (GET_RTX_CLASS (code))
3880 if (op0_mode == VOIDmode)
3881 op0_mode = GET_MODE (XEXP (x, 0));
3882 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3885 case RTX_COMM_COMPARE:
3887 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3888 if (cmp_mode == VOIDmode)
3890 cmp_mode = GET_MODE (XEXP (x, 1));
3891 if (cmp_mode == VOIDmode)
3892 cmp_mode = op0_mode;
3894 temp = simplify_relational_operation (code, mode, cmp_mode,
3895 XEXP (x, 0), XEXP (x, 1));
3898 case RTX_COMM_ARITH:
3900 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3902 case RTX_BITFIELD_OPS:
3904 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3905 XEXP (x, 1), XEXP (x, 2));
3914 code = GET_CODE (temp);
3915 op0_mode = VOIDmode;
3916 mode = GET_MODE (temp);
3919 /* First see if we can apply the inverse distributive law. */
3920 if (code == PLUS || code == MINUS
3921 || code == AND || code == IOR || code == XOR)
3923 x = apply_distributive_law (x);
3924 code = GET_CODE (x);
3925 op0_mode = VOIDmode;
3928 /* If CODE is an associative operation not otherwise handled, see if we
3929 can associate some operands. This can win if they are constants or
3930 if they are logically related (i.e. (a & b) & a). */
3931 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3932 || code == AND || code == IOR || code == XOR
3933 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3934 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3935 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3937 if (GET_CODE (XEXP (x, 0)) == code)
3939 rtx other = XEXP (XEXP (x, 0), 0);
3940 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3941 rtx inner_op1 = XEXP (x, 1);
3944 /* Make sure we pass the constant operand if any as the second
3945 one if this is a commutative operation. */
3946 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3948 rtx tem = inner_op0;
3949 inner_op0 = inner_op1;
3952 inner = simplify_binary_operation (code == MINUS ? PLUS
3953 : code == DIV ? MULT
3955 mode, inner_op0, inner_op1);
3957 /* For commutative operations, try the other pair if that one
3959 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3961 other = XEXP (XEXP (x, 0), 1);
3962 inner = simplify_binary_operation (code, mode,
3963 XEXP (XEXP (x, 0), 0),
3968 return simplify_gen_binary (code, mode, other, inner);
3972 /* A little bit of algebraic simplification here. */
3976 /* Ensure that our address has any ASHIFTs converted to MULT in case
3977 address-recognizing predicates are called later. */
3978 temp = make_compound_operation (XEXP (x, 0), MEM);
3979 SUBST (XEXP (x, 0), temp);
3983 if (op0_mode == VOIDmode)
3984 op0_mode = GET_MODE (SUBREG_REG (x));
3986 /* See if this can be moved to simplify_subreg. */
3987 if (CONSTANT_P (SUBREG_REG (x))
3988 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3989 /* Don't call gen_lowpart if the inner mode
3990 is VOIDmode and we cannot simplify it, as SUBREG without
3991 inner mode is invalid. */
3992 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3993 || gen_lowpart_common (mode, SUBREG_REG (x))))
3994 return gen_lowpart (mode, SUBREG_REG (x));
3996 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4000 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4006 /* Don't change the mode of the MEM if that would change the meaning
4008 if (MEM_P (SUBREG_REG (x))
4009 && (MEM_VOLATILE_P (SUBREG_REG (x))
4010 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4011 return gen_rtx_CLOBBER (mode, const0_rtx);
4013 /* Note that we cannot do any narrowing for non-constants since
4014 we might have been counting on using the fact that some bits were
4015 zero. We now do this in the SET. */
4020 if (GET_CODE (XEXP (x, 0)) == SUBREG
4021 && subreg_lowpart_p (XEXP (x, 0))
4022 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
4023 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
4024 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
4025 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
4027 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
4029 x = gen_rtx_ROTATE (inner_mode,
4030 simplify_gen_unary (NOT, inner_mode, const1_rtx,
4032 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
4033 return gen_lowpart (mode, x);
4036 /* Apply De Morgan's laws to reduce number of patterns for machines
4037 with negating logical insns (and-not, nand, etc.). If result has
4038 only one NOT, put it first, since that is how the patterns are
4041 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
4043 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4044 enum machine_mode op_mode;
4046 op_mode = GET_MODE (in1);
4047 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4049 op_mode = GET_MODE (in2);
4050 if (op_mode == VOIDmode)
4052 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4054 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4057 in2 = in1; in1 = tem;
4060 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4066 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4067 if (GET_CODE (XEXP (x, 0)) == XOR
4068 && XEXP (XEXP (x, 0), 1) == const1_rtx
4069 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4070 return simplify_gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4073 temp = expand_compound_operation (XEXP (x, 0));
4075 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4076 replaced by (lshiftrt X C). This will convert
4077 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4079 if (GET_CODE (temp) == ASHIFTRT
4080 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4081 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4082 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4083 INTVAL (XEXP (temp, 1)));
4085 /* If X has only a single bit that might be nonzero, say, bit I, convert
4086 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4087 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4088 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4089 or a SUBREG of one since we'd be making the expression more
4090 complex if it was just a register. */
4093 && ! (GET_CODE (temp) == SUBREG
4094 && REG_P (SUBREG_REG (temp)))
4095 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4097 rtx temp1 = simplify_shift_const
4098 (NULL_RTX, ASHIFTRT, mode,
4099 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4100 GET_MODE_BITSIZE (mode) - 1 - i),
4101 GET_MODE_BITSIZE (mode) - 1 - i);
4103 /* If all we did was surround TEMP with the two shifts, we
4104 haven't improved anything, so don't use it. Otherwise,
4105 we are better off with TEMP1. */
4106 if (GET_CODE (temp1) != ASHIFTRT
4107 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4108 || XEXP (XEXP (temp1, 0), 0) != temp)
4114 /* We can't handle truncation to a partial integer mode here
4115 because we don't know the real bitsize of the partial
4117 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4120 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4121 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4122 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4124 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4125 GET_MODE_MASK (mode), NULL_RTX, 0));
4127 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4128 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4129 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4130 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4131 return XEXP (XEXP (x, 0), 0);
4133 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4134 (OP:SI foo:SI) if OP is NEG or ABS. */
4135 if ((GET_CODE (XEXP (x, 0)) == ABS
4136 || GET_CODE (XEXP (x, 0)) == NEG)
4137 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4138 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4139 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4140 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4141 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4143 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4145 if (GET_CODE (XEXP (x, 0)) == SUBREG
4146 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4147 && subreg_lowpart_p (XEXP (x, 0)))
4148 return SUBREG_REG (XEXP (x, 0));
4150 /* If we know that the value is already truncated, we can
4151 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4152 is nonzero for the corresponding modes. But don't do this
4153 for an (LSHIFTRT (MULT ...)) since this will cause problems
4154 with the umulXi3_highpart patterns. */
4155 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4156 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4157 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4158 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4159 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4160 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4161 return gen_lowpart (mode, XEXP (x, 0));
4163 /* A truncate of a comparison can be replaced with a subreg if
4164 STORE_FLAG_VALUE permits. This is like the previous test,
4165 but it works even if the comparison is done in a mode larger
4166 than HOST_BITS_PER_WIDE_INT. */
4167 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4168 && COMPARISON_P (XEXP (x, 0))
4169 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4170 return gen_lowpart (mode, XEXP (x, 0));
4172 /* Similarly, a truncate of a register whose value is a
4173 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4175 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4176 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4177 && (temp = get_last_value (XEXP (x, 0)))
4178 && COMPARISON_P (temp))
4179 return gen_lowpart (mode, XEXP (x, 0));
4183 case FLOAT_TRUNCATE:
4184 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4185 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4186 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4187 return XEXP (XEXP (x, 0), 0);
4189 /* (float_truncate:SF (float_truncate:DF foo:XF))
4190 = (float_truncate:SF foo:XF).
4191 This may eliminate double rounding, so it is unsafe.
4193 (float_truncate:SF (float_extend:XF foo:DF))
4194 = (float_truncate:SF foo:DF).
4196 (float_truncate:DF (float_extend:XF foo:SF))
4197 = (float_extend:SF foo:DF). */
4198 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4199 && flag_unsafe_math_optimizations)
4200 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4201 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4203 > GET_MODE_SIZE (mode)
4204 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4206 XEXP (XEXP (x, 0), 0), mode);
4208 /* (float_truncate (float x)) is (float x) */
4209 if (GET_CODE (XEXP (x, 0)) == FLOAT
4210 && (flag_unsafe_math_optimizations
4211 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4212 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4213 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4214 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4215 return simplify_gen_unary (FLOAT, mode,
4216 XEXP (XEXP (x, 0), 0),
4217 GET_MODE (XEXP (XEXP (x, 0), 0)));
4219 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4220 (OP:SF foo:SF) if OP is NEG or ABS. */
4221 if ((GET_CODE (XEXP (x, 0)) == ABS
4222 || GET_CODE (XEXP (x, 0)) == NEG)
4223 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4224 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4225 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4226 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4228 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4229 is (float_truncate:SF x). */
4230 if (GET_CODE (XEXP (x, 0)) == SUBREG
4231 && subreg_lowpart_p (XEXP (x, 0))
4232 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4233 return SUBREG_REG (XEXP (x, 0));
4236 /* (float_extend (float_extend x)) is (float_extend x)
4238 (float_extend (float x)) is (float x) assuming that double
4239 rounding can't happen.
4241 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4242 || (GET_CODE (XEXP (x, 0)) == FLOAT
4243 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4244 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4245 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4246 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4247 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4248 XEXP (XEXP (x, 0), 0),
4249 GET_MODE (XEXP (XEXP (x, 0), 0)));
4254 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4255 using cc0, in which case we want to leave it as a COMPARE
4256 so we can distinguish it from a register-register-copy. */
4257 if (XEXP (x, 1) == const0_rtx)
4260 /* x - 0 is the same as x unless x's mode has signed zeros and
4261 allows rounding towards -infinity. Under those conditions,
4263 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4264 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4265 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4271 /* (const (const X)) can become (const X). Do it this way rather than
4272 returning the inner CONST since CONST can be shared with a
4274 if (GET_CODE (XEXP (x, 0)) == CONST)
4275 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4280 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4281 can add in an offset. find_split_point will split this address up
4282 again if it doesn't match. */
4283 if (GET_CODE (XEXP (x, 0)) == HIGH
4284 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4290 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4292 if (GET_CODE (XEXP (x, 0)) == MULT
4293 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4297 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4298 in2 = XEXP (XEXP (x, 0), 1);
4299 return simplify_gen_binary (MINUS, mode, XEXP (x, 1),
4300 simplify_gen_binary (MULT, mode,
4304 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4305 outermost. That's because that's the way indexed addresses are
4306 supposed to appear. This code used to check many more cases, but
4307 they are now checked elsewhere. */
4308 if (GET_CODE (XEXP (x, 0)) == PLUS
4309 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4310 return simplify_gen_binary (PLUS, mode,
4311 simplify_gen_binary (PLUS, mode,
4312 XEXP (XEXP (x, 0), 0),
4314 XEXP (XEXP (x, 0), 1));
4316 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4317 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4318 bit-field and can be replaced by either a sign_extend or a
4319 sign_extract. The `and' may be a zero_extend and the two
4320 <c>, -<c> constants may be reversed. */
4321 if (GET_CODE (XEXP (x, 0)) == XOR
4322 && GET_CODE (XEXP (x, 1)) == CONST_INT
4323 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4324 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4325 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4326 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4327 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4328 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4329 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4330 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4331 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4332 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4333 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4334 == (unsigned int) i + 1))))
4335 return simplify_shift_const
4336 (NULL_RTX, ASHIFTRT, mode,
4337 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4338 XEXP (XEXP (XEXP (x, 0), 0), 0),
4339 GET_MODE_BITSIZE (mode) - (i + 1)),
4340 GET_MODE_BITSIZE (mode) - (i + 1));
4342 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4343 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4344 is 1. This produces better code than the alternative immediately
4346 if (COMPARISON_P (XEXP (x, 0))
4347 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4348 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4349 && (reversed = reversed_comparison (XEXP (x, 0), mode)))
4351 simplify_gen_unary (NEG, mode, reversed, mode);
4353 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4354 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4355 the bitsize of the mode - 1. This allows simplification of
4356 "a = (b & 8) == 0;" */
4357 if (XEXP (x, 1) == constm1_rtx
4358 && !REG_P (XEXP (x, 0))
4359 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4360 && REG_P (SUBREG_REG (XEXP (x, 0))))
4361 && nonzero_bits (XEXP (x, 0), mode) == 1)
4362 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4363 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4364 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4365 GET_MODE_BITSIZE (mode) - 1),
4366 GET_MODE_BITSIZE (mode) - 1);
4368 /* If we are adding two things that have no bits in common, convert
4369 the addition into an IOR. This will often be further simplified,
4370 for example in cases like ((a & 1) + (a & 2)), which can
4373 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4374 && (nonzero_bits (XEXP (x, 0), mode)
4375 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4377 /* Try to simplify the expression further. */
4378 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4379 temp = combine_simplify_rtx (tor, mode, in_dest);
4381 /* If we could, great. If not, do not go ahead with the IOR
4382 replacement, since PLUS appears in many special purpose
4383 address arithmetic instructions. */
4384 if (GET_CODE (temp) != CLOBBER && temp != tor)
4390 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4391 by reversing the comparison code if valid. */
4392 if (STORE_FLAG_VALUE == 1
4393 && XEXP (x, 0) == const1_rtx
4394 && COMPARISON_P (XEXP (x, 1))
4395 && (reversed = reversed_comparison (XEXP (x, 1), mode)))
4398 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4399 (and <foo> (const_int pow2-1)) */
4400 if (GET_CODE (XEXP (x, 1)) == AND
4401 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4402 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4403 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4404 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4405 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4407 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4409 if (GET_CODE (XEXP (x, 1)) == MULT
4410 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4414 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4415 in2 = XEXP (XEXP (x, 1), 1);
4416 return simplify_gen_binary (PLUS, mode,
4417 simplify_gen_binary (MULT, mode,
4422 /* Canonicalize (minus (neg A) (mult B C)) to
4423 (minus (mult (neg B) C) A). */
4424 if (GET_CODE (XEXP (x, 1)) == MULT
4425 && GET_CODE (XEXP (x, 0)) == NEG)
4429 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4430 in2 = XEXP (XEXP (x, 1), 1);
4431 return simplify_gen_binary (MINUS, mode,
4432 simplify_gen_binary (MULT, mode,
4434 XEXP (XEXP (x, 0), 0));
4437 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4439 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4440 return simplify_gen_binary (MINUS, mode,
4441 simplify_gen_binary (MINUS, mode,
4443 XEXP (XEXP (x, 1), 0)),
4444 XEXP (XEXP (x, 1), 1));
4448 /* If we have (mult (plus A B) C), apply the distributive law and then
4449 the inverse distributive law to see if things simplify. This
4450 occurs mostly in addresses, often when unrolling loops. */
4452 if (GET_CODE (XEXP (x, 0)) == PLUS)
4454 rtx result = distribute_and_simplify_rtx (x, 0);
4459 /* Try simplify a*(b/c) as (a*b)/c. */
4460 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4461 && GET_CODE (XEXP (x, 0)) == DIV)
4463 rtx tem = simplify_binary_operation (MULT, mode,
4464 XEXP (XEXP (x, 0), 0),
4467 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4472 /* If this is a divide by a power of two, treat it as a shift if
4473 its first operand is a shift. */
4474 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4475 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4476 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4477 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4478 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4479 || GET_CODE (XEXP (x, 0)) == ROTATE
4480 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4481 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4485 case GT: case GTU: case GE: case GEU:
4486 case LT: case LTU: case LE: case LEU:
4487 case UNEQ: case LTGT:
4488 case UNGT: case UNGE:
4489 case UNLT: case UNLE:
4490 case UNORDERED: case ORDERED:
4491 /* If the first operand is a condition code, we can't do anything
4493 if (GET_CODE (XEXP (x, 0)) == COMPARE
4494 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4495 && ! CC0_P (XEXP (x, 0))))
4497 rtx op0 = XEXP (x, 0);
4498 rtx op1 = XEXP (x, 1);
4499 enum rtx_code new_code;
4501 if (GET_CODE (op0) == COMPARE)
4502 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4504 /* Simplify our comparison, if possible. */
4505 new_code = simplify_comparison (code, &op0, &op1);
4507 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4508 if only the low-order bit is possibly nonzero in X (such as when
4509 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4510 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4511 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4514 Remove any ZERO_EXTRACT we made when thinking this was a
4515 comparison. It may now be simpler to use, e.g., an AND. If a
4516 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4517 the call to make_compound_operation in the SET case. */
4519 if (STORE_FLAG_VALUE == 1
4520 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4521 && op1 == const0_rtx
4522 && mode == GET_MODE (op0)
4523 && nonzero_bits (op0, mode) == 1)
4524 return gen_lowpart (mode,
4525 expand_compound_operation (op0));
4527 else if (STORE_FLAG_VALUE == 1
4528 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4529 && op1 == const0_rtx
4530 && mode == GET_MODE (op0)
4531 && (num_sign_bit_copies (op0, mode)
4532 == GET_MODE_BITSIZE (mode)))
4534 op0 = expand_compound_operation (op0);
4535 return simplify_gen_unary (NEG, mode,
4536 gen_lowpart (mode, op0),
4540 else if (STORE_FLAG_VALUE == 1
4541 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4542 && op1 == const0_rtx
4543 && mode == GET_MODE (op0)
4544 && nonzero_bits (op0, mode) == 1)
4546 op0 = expand_compound_operation (op0);
4547 return simplify_gen_binary (XOR, mode,
4548 gen_lowpart (mode, op0),
4552 else if (STORE_FLAG_VALUE == 1
4553 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4554 && op1 == const0_rtx
4555 && mode == GET_MODE (op0)
4556 && (num_sign_bit_copies (op0, mode)
4557 == GET_MODE_BITSIZE (mode)))
4559 op0 = expand_compound_operation (op0);
4560 return plus_constant (gen_lowpart (mode, op0), 1);
4563 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4565 if (STORE_FLAG_VALUE == -1
4566 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4567 && op1 == const0_rtx
4568 && (num_sign_bit_copies (op0, mode)
4569 == GET_MODE_BITSIZE (mode)))
4570 return gen_lowpart (mode,
4571 expand_compound_operation (op0));
4573 else if (STORE_FLAG_VALUE == -1
4574 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4575 && op1 == const0_rtx
4576 && mode == GET_MODE (op0)
4577 && nonzero_bits (op0, mode) == 1)
4579 op0 = expand_compound_operation (op0);
4580 return simplify_gen_unary (NEG, mode,
4581 gen_lowpart (mode, op0),
4585 else if (STORE_FLAG_VALUE == -1
4586 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4587 && op1 == const0_rtx
4588 && mode == GET_MODE (op0)
4589 && (num_sign_bit_copies (op0, mode)
4590 == GET_MODE_BITSIZE (mode)))
4592 op0 = expand_compound_operation (op0);
4593 return simplify_gen_unary (NOT, mode,
4594 gen_lowpart (mode, op0),
4598 /* If X is 0/1, (eq X 0) is X-1. */
4599 else if (STORE_FLAG_VALUE == -1
4600 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4601 && op1 == const0_rtx
4602 && mode == GET_MODE (op0)
4603 && nonzero_bits (op0, mode) == 1)
4605 op0 = expand_compound_operation (op0);
4606 return plus_constant (gen_lowpart (mode, op0), -1);
4609 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4610 one bit that might be nonzero, we can convert (ne x 0) to
4611 (ashift x c) where C puts the bit in the sign bit. Remove any
4612 AND with STORE_FLAG_VALUE when we are done, since we are only
4613 going to test the sign bit. */
4614 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4615 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4616 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4617 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4618 && op1 == const0_rtx
4619 && mode == GET_MODE (op0)
4620 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4622 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4623 expand_compound_operation (op0),
4624 GET_MODE_BITSIZE (mode) - 1 - i);
4625 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4631 /* If the code changed, return a whole new comparison. */
4632 if (new_code != code)
4633 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4635 /* Otherwise, keep this operation, but maybe change its operands.
4636 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4637 SUBST (XEXP (x, 0), op0);
4638 SUBST (XEXP (x, 1), op1);
4643 return simplify_if_then_else (x);
4649 /* If we are processing SET_DEST, we are done. */
4653 return expand_compound_operation (x);
4656 return simplify_set (x);
4661 return simplify_logical (x);
4664 /* (abs (neg <foo>)) -> (abs <foo>) */
4665 if (GET_CODE (XEXP (x, 0)) == NEG)
4666 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4668 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4670 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4673 /* If operand is something known to be positive, ignore the ABS. */
4674 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4675 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4676 <= HOST_BITS_PER_WIDE_INT)
4677 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4678 & ((HOST_WIDE_INT) 1
4679 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4683 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4684 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4685 return gen_rtx_NEG (mode, XEXP (x, 0));
4690 /* (ffs (*_extend <X>)) = (ffs <X>) */
4691 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4692 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4693 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4698 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4699 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4700 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4704 /* (float (sign_extend <X>)) = (float <X>). */
4705 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4706 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4714 /* If this is a shift by a constant amount, simplify it. */
4715 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4716 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4717 INTVAL (XEXP (x, 1)));
4719 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4721 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4723 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4730 rtx op0 = XEXP (x, 0);
4731 rtx op1 = XEXP (x, 1);
4734 gcc_assert (GET_CODE (op1) == PARALLEL);
4735 len = XVECLEN (op1, 0);
4737 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4738 && GET_CODE (op0) == VEC_CONCAT)
4740 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4742 /* Try to find the element in the VEC_CONCAT. */
4745 if (GET_MODE (op0) == GET_MODE (x))
4747 if (GET_CODE (op0) == VEC_CONCAT)
4749 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4750 if (offset < op0_size)
4751 op0 = XEXP (op0, 0);
4755 op0 = XEXP (op0, 1);
4773 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4776 simplify_if_then_else (rtx x)
4778 enum machine_mode mode = GET_MODE (x);
4779 rtx cond = XEXP (x, 0);
4780 rtx true_rtx = XEXP (x, 1);
4781 rtx false_rtx = XEXP (x, 2);
4782 enum rtx_code true_code = GET_CODE (cond);
4783 int comparison_p = COMPARISON_P (cond);
4786 enum rtx_code false_code;
4789 /* Simplify storing of the truth value. */
4790 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4791 return simplify_gen_relational (true_code, mode, VOIDmode,
4792 XEXP (cond, 0), XEXP (cond, 1));
4794 /* Also when the truth value has to be reversed. */
4796 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4797 && (reversed = reversed_comparison (cond, mode)))
4800 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4801 in it is being compared against certain values. Get the true and false
4802 comparisons and see if that says anything about the value of each arm. */
4805 && ((false_code = reversed_comparison_code (cond, NULL))
4807 && REG_P (XEXP (cond, 0)))
4810 rtx from = XEXP (cond, 0);
4811 rtx true_val = XEXP (cond, 1);
4812 rtx false_val = true_val;
4815 /* If FALSE_CODE is EQ, swap the codes and arms. */
4817 if (false_code == EQ)
4819 swapped = 1, true_code = EQ, false_code = NE;
4820 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4823 /* If we are comparing against zero and the expression being tested has
4824 only a single bit that might be nonzero, that is its value when it is
4825 not equal to zero. Similarly if it is known to be -1 or 0. */
4827 if (true_code == EQ && true_val == const0_rtx
4828 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4829 false_code = EQ, false_val = GEN_INT (nzb);
4830 else if (true_code == EQ && true_val == const0_rtx
4831 && (num_sign_bit_copies (from, GET_MODE (from))
4832 == GET_MODE_BITSIZE (GET_MODE (from))))
4833 false_code = EQ, false_val = constm1_rtx;
4835 /* Now simplify an arm if we know the value of the register in the
4836 branch and it is used in the arm. Be careful due to the potential
4837 of locally-shared RTL. */
4839 if (reg_mentioned_p (from, true_rtx))
4840 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4842 pc_rtx, pc_rtx, 0, 0);
4843 if (reg_mentioned_p (from, false_rtx))
4844 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4846 pc_rtx, pc_rtx, 0, 0);
4848 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4849 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4851 true_rtx = XEXP (x, 1);
4852 false_rtx = XEXP (x, 2);
4853 true_code = GET_CODE (cond);
4856 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4857 reversed, do so to avoid needing two sets of patterns for
4858 subtract-and-branch insns. Similarly if we have a constant in the true
4859 arm, the false arm is the same as the first operand of the comparison, or
4860 the false arm is more complicated than the true arm. */
4863 && reversed_comparison_code (cond, NULL) != UNKNOWN
4864 && (true_rtx == pc_rtx
4865 || (CONSTANT_P (true_rtx)
4866 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4867 || true_rtx == const0_rtx
4868 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4869 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4870 && !OBJECT_P (false_rtx))
4871 || reg_mentioned_p (true_rtx, false_rtx)
4872 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4874 true_code = reversed_comparison_code (cond, NULL);
4875 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4876 SUBST (XEXP (x, 1), false_rtx);
4877 SUBST (XEXP (x, 2), true_rtx);
4879 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4882 /* It is possible that the conditional has been simplified out. */
4883 true_code = GET_CODE (cond);
4884 comparison_p = COMPARISON_P (cond);
4887 /* If the two arms are identical, we don't need the comparison. */
4889 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4892 /* Convert a == b ? b : a to "a". */
4893 if (true_code == EQ && ! side_effects_p (cond)
4894 && !HONOR_NANS (mode)
4895 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4896 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4898 else if (true_code == NE && ! side_effects_p (cond)
4899 && !HONOR_NANS (mode)
4900 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4901 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4904 /* Look for cases where we have (abs x) or (neg (abs X)). */
4906 if (GET_MODE_CLASS (mode) == MODE_INT
4907 && GET_CODE (false_rtx) == NEG
4908 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4910 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4911 && ! side_effects_p (true_rtx))
4916 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4920 simplify_gen_unary (NEG, mode,
4921 simplify_gen_unary (ABS, mode, true_rtx, mode),
4927 /* Look for MIN or MAX. */
4929 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4931 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4932 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4933 && ! side_effects_p (cond))
4938 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4941 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4944 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4947 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4952 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4953 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4954 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4955 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4956 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4957 neither 1 or -1, but it isn't worth checking for. */
4959 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4961 && GET_MODE_CLASS (mode) == MODE_INT
4962 && ! side_effects_p (x))
4964 rtx t = make_compound_operation (true_rtx, SET);
4965 rtx f = make_compound_operation (false_rtx, SET);
4966 rtx cond_op0 = XEXP (cond, 0);
4967 rtx cond_op1 = XEXP (cond, 1);
4968 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4969 enum machine_mode m = mode;
4970 rtx z = 0, c1 = NULL_RTX;
4972 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4973 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4974 || GET_CODE (t) == ASHIFT
4975 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4976 && rtx_equal_p (XEXP (t, 0), f))
4977 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4979 /* If an identity-zero op is commutative, check whether there
4980 would be a match if we swapped the operands. */
4981 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4982 || GET_CODE (t) == XOR)
4983 && rtx_equal_p (XEXP (t, 1), f))
4984 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4985 else if (GET_CODE (t) == SIGN_EXTEND
4986 && (GET_CODE (XEXP (t, 0)) == PLUS
4987 || GET_CODE (XEXP (t, 0)) == MINUS
4988 || GET_CODE (XEXP (t, 0)) == IOR
4989 || GET_CODE (XEXP (t, 0)) == XOR
4990 || GET_CODE (XEXP (t, 0)) == ASHIFT
4991 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4992 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4993 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4994 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4995 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4996 && (num_sign_bit_copies (f, GET_MODE (f))
4998 (GET_MODE_BITSIZE (mode)
4999 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5001 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5002 extend_op = SIGN_EXTEND;
5003 m = GET_MODE (XEXP (t, 0));
5005 else if (GET_CODE (t) == SIGN_EXTEND
5006 && (GET_CODE (XEXP (t, 0)) == PLUS
5007 || GET_CODE (XEXP (t, 0)) == IOR
5008 || GET_CODE (XEXP (t, 0)) == XOR)
5009 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5010 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5011 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5012 && (num_sign_bit_copies (f, GET_MODE (f))
5014 (GET_MODE_BITSIZE (mode)
5015 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5017 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5018 extend_op = SIGN_EXTEND;
5019 m = GET_MODE (XEXP (t, 0));
5021 else if (GET_CODE (t) == ZERO_EXTEND
5022 && (GET_CODE (XEXP (t, 0)) == PLUS
5023 || GET_CODE (XEXP (t, 0)) == MINUS
5024 || GET_CODE (XEXP (t, 0)) == IOR
5025 || GET_CODE (XEXP (t, 0)) == XOR
5026 || GET_CODE (XEXP (t, 0)) == ASHIFT
5027 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5028 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5029 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5030 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5031 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5032 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5033 && ((nonzero_bits (f, GET_MODE (f))
5034 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5037 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5038 extend_op = ZERO_EXTEND;
5039 m = GET_MODE (XEXP (t, 0));
5041 else if (GET_CODE (t) == ZERO_EXTEND
5042 && (GET_CODE (XEXP (t, 0)) == PLUS
5043 || GET_CODE (XEXP (t, 0)) == IOR
5044 || GET_CODE (XEXP (t, 0)) == XOR)
5045 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5046 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5047 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5048 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5049 && ((nonzero_bits (f, GET_MODE (f))
5050 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5053 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5054 extend_op = ZERO_EXTEND;
5055 m = GET_MODE (XEXP (t, 0));
5060 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5061 cond_op0, cond_op1),
5062 pc_rtx, pc_rtx, 0, 0);
5063 temp = simplify_gen_binary (MULT, m, temp,
5064 simplify_gen_binary (MULT, m, c1,
5066 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5067 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5069 if (extend_op != UNKNOWN)
5070 temp = simplify_gen_unary (extend_op, mode, temp, m);
5076 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5077 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5078 negation of a single bit, we can convert this operation to a shift. We
5079 can actually do this more generally, but it doesn't seem worth it. */
5081 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5082 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5083 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5084 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5085 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5086 == GET_MODE_BITSIZE (mode))
5087 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5089 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5090 gen_lowpart (mode, XEXP (cond, 0)), i);
5092 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5093 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5094 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5095 && GET_MODE (XEXP (cond, 0)) == mode
5096 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5097 == nonzero_bits (XEXP (cond, 0), mode)
5098 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5099 return XEXP (cond, 0);
5104 /* Simplify X, a SET expression. Return the new expression. */
5107 simplify_set (rtx x)
5109 rtx src = SET_SRC (x);
5110 rtx dest = SET_DEST (x);
5111 enum machine_mode mode
5112 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5116 /* (set (pc) (return)) gets written as (return). */
5117 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5120 /* Now that we know for sure which bits of SRC we are using, see if we can
5121 simplify the expression for the object knowing that we only need the
5124 if (GET_MODE_CLASS (mode) == MODE_INT
5125 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5127 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5128 SUBST (SET_SRC (x), src);
5131 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5132 the comparison result and try to simplify it unless we already have used
5133 undobuf.other_insn. */
5134 if ((GET_MODE_CLASS (mode) == MODE_CC
5135 || GET_CODE (src) == COMPARE
5137 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5138 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5139 && COMPARISON_P (*cc_use)
5140 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5142 enum rtx_code old_code = GET_CODE (*cc_use);
5143 enum rtx_code new_code;
5145 int other_changed = 0;
5146 enum machine_mode compare_mode = GET_MODE (dest);
5148 if (GET_CODE (src) == COMPARE)
5149 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5151 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5153 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5156 new_code = old_code;
5157 else if (!CONSTANT_P (tmp))
5159 new_code = GET_CODE (tmp);
5160 op0 = XEXP (tmp, 0);
5161 op1 = XEXP (tmp, 1);
5165 rtx pat = PATTERN (other_insn);
5166 undobuf.other_insn = other_insn;
5167 SUBST (*cc_use, tmp);
5169 /* Attempt to simplify CC user. */
5170 if (GET_CODE (pat) == SET)
5172 rtx new = simplify_rtx (SET_SRC (pat));
5173 if (new != NULL_RTX)
5174 SUBST (SET_SRC (pat), new);
5177 /* Convert X into a no-op move. */
5178 SUBST (SET_DEST (x), pc_rtx);
5179 SUBST (SET_SRC (x), pc_rtx);
5183 /* Simplify our comparison, if possible. */
5184 new_code = simplify_comparison (new_code, &op0, &op1);
5186 #ifdef SELECT_CC_MODE
5187 /* If this machine has CC modes other than CCmode, check to see if we
5188 need to use a different CC mode here. */
5189 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5190 compare_mode = GET_MODE (op0);
5192 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5195 /* If the mode changed, we have to change SET_DEST, the mode in the
5196 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5197 a hard register, just build new versions with the proper mode. If it
5198 is a pseudo, we lose unless it is only time we set the pseudo, in
5199 which case we can safely change its mode. */
5200 if (compare_mode != GET_MODE (dest))
5202 unsigned int regno = REGNO (dest);
5203 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5205 if (regno < FIRST_PSEUDO_REGISTER
5206 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5208 if (regno >= FIRST_PSEUDO_REGISTER)
5209 SUBST (regno_reg_rtx[regno], new_dest);
5211 SUBST (SET_DEST (x), new_dest);
5212 SUBST (XEXP (*cc_use, 0), new_dest);
5219 #endif /* SELECT_CC_MODE */
5221 /* If the code changed, we have to build a new comparison in
5222 undobuf.other_insn. */
5223 if (new_code != old_code)
5225 int other_changed_previously = other_changed;
5226 unsigned HOST_WIDE_INT mask;
5228 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5232 /* If the only change we made was to change an EQ into an NE or
5233 vice versa, OP0 has only one bit that might be nonzero, and OP1
5234 is zero, check if changing the user of the condition code will
5235 produce a valid insn. If it won't, we can keep the original code
5236 in that insn by surrounding our operation with an XOR. */
5238 if (((old_code == NE && new_code == EQ)
5239 || (old_code == EQ && new_code == NE))
5240 && ! other_changed_previously && op1 == const0_rtx
5241 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5242 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5244 rtx pat = PATTERN (other_insn), note = 0;
5246 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5247 && ! check_asm_operands (pat)))
5249 PUT_CODE (*cc_use, old_code);
5252 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5253 op0, GEN_INT (mask));
5259 undobuf.other_insn = other_insn;
5262 /* If we are now comparing against zero, change our source if
5263 needed. If we do not use cc0, we always have a COMPARE. */
5264 if (op1 == const0_rtx && dest == cc0_rtx)
5266 SUBST (SET_SRC (x), op0);
5272 /* Otherwise, if we didn't previously have a COMPARE in the
5273 correct mode, we need one. */
5274 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5276 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5279 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5281 SUBST(SET_SRC (x), op0);
5286 /* Otherwise, update the COMPARE if needed. */
5287 SUBST (XEXP (src, 0), op0);
5288 SUBST (XEXP (src, 1), op1);
5293 /* Get SET_SRC in a form where we have placed back any
5294 compound expressions. Then do the checks below. */
5295 src = make_compound_operation (src, SET);
5296 SUBST (SET_SRC (x), src);
5299 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5300 and X being a REG or (subreg (reg)), we may be able to convert this to
5301 (set (subreg:m2 x) (op)).
5303 We can always do this if M1 is narrower than M2 because that means that
5304 we only care about the low bits of the result.
5306 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5307 perform a narrower operation than requested since the high-order bits will
5308 be undefined. On machine where it is defined, this transformation is safe
5309 as long as M1 and M2 have the same number of words. */
5311 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5312 && !OBJECT_P (SUBREG_REG (src))
5313 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5315 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5316 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5317 #ifndef WORD_REGISTER_OPERATIONS
5318 && (GET_MODE_SIZE (GET_MODE (src))
5319 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5321 #ifdef CANNOT_CHANGE_MODE_CLASS
5322 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5323 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5324 GET_MODE (SUBREG_REG (src)),
5328 || (GET_CODE (dest) == SUBREG
5329 && REG_P (SUBREG_REG (dest)))))
5331 SUBST (SET_DEST (x),
5332 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5334 SUBST (SET_SRC (x), SUBREG_REG (src));
5336 src = SET_SRC (x), dest = SET_DEST (x);
5340 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5343 && GET_CODE (src) == SUBREG
5344 && subreg_lowpart_p (src)
5345 && (GET_MODE_BITSIZE (GET_MODE (src))
5346 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5348 rtx inner = SUBREG_REG (src);
5349 enum machine_mode inner_mode = GET_MODE (inner);
5351 /* Here we make sure that we don't have a sign bit on. */
5352 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5353 && (nonzero_bits (inner, inner_mode)
5354 < ((unsigned HOST_WIDE_INT) 1
5355 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5357 SUBST (SET_SRC (x), inner);
5363 #ifdef LOAD_EXTEND_OP
5364 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5365 would require a paradoxical subreg. Replace the subreg with a
5366 zero_extend to avoid the reload that would otherwise be required. */
5368 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5369 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5370 && SUBREG_BYTE (src) == 0
5371 && (GET_MODE_SIZE (GET_MODE (src))
5372 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5373 && MEM_P (SUBREG_REG (src)))
5376 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5377 GET_MODE (src), SUBREG_REG (src)));
5383 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5384 are comparing an item known to be 0 or -1 against 0, use a logical
5385 operation instead. Check for one of the arms being an IOR of the other
5386 arm with some value. We compute three terms to be IOR'ed together. In
5387 practice, at most two will be nonzero. Then we do the IOR's. */
5389 if (GET_CODE (dest) != PC
5390 && GET_CODE (src) == IF_THEN_ELSE
5391 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5392 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5393 && XEXP (XEXP (src, 0), 1) == const0_rtx
5394 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5395 #ifdef HAVE_conditional_move
5396 && ! can_conditionally_move_p (GET_MODE (src))
5398 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5399 GET_MODE (XEXP (XEXP (src, 0), 0)))
5400 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5401 && ! side_effects_p (src))
5403 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5404 ? XEXP (src, 1) : XEXP (src, 2));
5405 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5406 ? XEXP (src, 2) : XEXP (src, 1));
5407 rtx term1 = const0_rtx, term2, term3;
5409 if (GET_CODE (true_rtx) == IOR
5410 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5411 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5412 else if (GET_CODE (true_rtx) == IOR
5413 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5414 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5415 else if (GET_CODE (false_rtx) == IOR
5416 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5417 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5418 else if (GET_CODE (false_rtx) == IOR
5419 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5420 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5422 term2 = simplify_gen_binary (AND, GET_MODE (src),
5423 XEXP (XEXP (src, 0), 0), true_rtx);
5424 term3 = simplify_gen_binary (AND, GET_MODE (src),
5425 simplify_gen_unary (NOT, GET_MODE (src),
5426 XEXP (XEXP (src, 0), 0),
5431 simplify_gen_binary (IOR, GET_MODE (src),
5432 simplify_gen_binary (IOR, GET_MODE (src),
5439 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5440 whole thing fail. */
5441 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5443 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5446 /* Convert this into a field assignment operation, if possible. */
5447 return make_field_assignment (x);
5450 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5454 simplify_logical (rtx x)
5456 enum machine_mode mode = GET_MODE (x);
5457 rtx op0 = XEXP (x, 0);
5458 rtx op1 = XEXP (x, 1);
5461 switch (GET_CODE (x))
5464 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5465 insn (and may simplify more). */
5466 if (GET_CODE (op0) == XOR
5467 && rtx_equal_p (XEXP (op0, 0), op1)
5468 && ! side_effects_p (op1))
5469 x = simplify_gen_binary (AND, mode,
5470 simplify_gen_unary (NOT, mode,
5471 XEXP (op0, 1), mode),
5474 if (GET_CODE (op0) == XOR
5475 && rtx_equal_p (XEXP (op0, 1), op1)
5476 && ! side_effects_p (op1))
5477 x = simplify_gen_binary (AND, mode,
5478 simplify_gen_unary (NOT, mode,
5479 XEXP (op0, 0), mode),
5482 /* Similarly for (~(A ^ B)) & A. */
5483 if (GET_CODE (op0) == NOT
5484 && GET_CODE (XEXP (op0, 0)) == XOR
5485 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5486 && ! side_effects_p (op1))
5487 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5489 if (GET_CODE (op0) == NOT
5490 && GET_CODE (XEXP (op0, 0)) == XOR
5491 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5492 && ! side_effects_p (op1))
5493 x = simplify_gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5495 /* We can call simplify_and_const_int only if we don't lose
5496 any (sign) bits when converting INTVAL (op1) to
5497 "unsigned HOST_WIDE_INT". */
5498 if (GET_CODE (op1) == CONST_INT
5499 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5500 || INTVAL (op1) > 0))
5502 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5504 /* If we have (ior (and (X C1) C2)) and the next restart would be
5505 the last, simplify this by making C1 as small as possible
5506 and then exit. Only do this if C1 actually changes: for now
5507 this only saves memory but, should this transformation be
5508 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5509 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5510 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5511 && GET_CODE (op1) == CONST_INT
5512 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5513 return simplify_gen_binary (IOR, mode,
5515 (AND, mode, XEXP (op0, 0),
5516 GEN_INT (INTVAL (XEXP (op0, 1))
5517 & ~INTVAL (op1))), op1);
5519 if (GET_CODE (x) != AND)
5526 /* Convert (A | B) & A to A. */
5527 if (GET_CODE (op0) == IOR
5528 && (rtx_equal_p (XEXP (op0, 0), op1)
5529 || rtx_equal_p (XEXP (op0, 1), op1))
5530 && ! side_effects_p (XEXP (op0, 0))
5531 && ! side_effects_p (XEXP (op0, 1)))
5534 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5535 apply the distributive law and then the inverse distributive
5536 law to see if things simplify. */
5537 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5539 rtx result = distribute_and_simplify_rtx (x, 0);
5543 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5545 rtx result = distribute_and_simplify_rtx (x, 1);
5552 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5553 if (GET_CODE (op1) == CONST_INT
5554 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5555 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5558 /* Convert (A & B) | A to A. */
5559 if (GET_CODE (op0) == AND
5560 && (rtx_equal_p (XEXP (op0, 0), op1)
5561 || rtx_equal_p (XEXP (op0, 1), op1))
5562 && ! side_effects_p (XEXP (op0, 0))
5563 && ! side_effects_p (XEXP (op0, 1)))
5566 /* If we have (ior (and A B) C), apply the distributive law and then
5567 the inverse distributive law to see if things simplify. */
5569 if (GET_CODE (op0) == AND)
5571 rtx result = distribute_and_simplify_rtx (x, 0);
5576 if (GET_CODE (op1) == AND)
5578 rtx result = distribute_and_simplify_rtx (x, 1);
5583 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5584 mode size to (rotate A CX). */
5586 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5587 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5588 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5589 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5590 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5591 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5592 == GET_MODE_BITSIZE (mode)))
5593 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5594 (GET_CODE (op0) == ASHIFT
5595 ? XEXP (op0, 1) : XEXP (op1, 1)));
5597 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5598 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5599 does not affect any of the bits in OP1, it can really be done
5600 as a PLUS and we can associate. We do this by seeing if OP1
5601 can be safely shifted left C bits. */
5602 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5603 && GET_CODE (XEXP (op0, 0)) == PLUS
5604 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5605 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5606 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5608 int count = INTVAL (XEXP (op0, 1));
5609 HOST_WIDE_INT mask = INTVAL (op1) << count;
5611 if (mask >> count == INTVAL (op1)
5612 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5614 SUBST (XEXP (XEXP (op0, 0), 1),
5615 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5622 /* If we are XORing two things that have no bits in common,
5623 convert them into an IOR. This helps to detect rotation encoded
5624 using those methods and possibly other simplifications. */
5626 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5627 && (nonzero_bits (op0, mode)
5628 & nonzero_bits (op1, mode)) == 0)
5629 return (simplify_gen_binary (IOR, mode, op0, op1));
5631 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5632 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5635 int num_negated = 0;
5637 if (GET_CODE (op0) == NOT)
5638 num_negated++, op0 = XEXP (op0, 0);
5639 if (GET_CODE (op1) == NOT)
5640 num_negated++, op1 = XEXP (op1, 0);
5642 if (num_negated == 2)
5644 SUBST (XEXP (x, 0), op0);
5645 SUBST (XEXP (x, 1), op1);
5647 else if (num_negated == 1)
5649 simplify_gen_unary (NOT, mode,
5650 simplify_gen_binary (XOR, mode, op0, op1),
5654 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5655 correspond to a machine insn or result in further simplifications
5656 if B is a constant. */
5658 if (GET_CODE (op0) == AND
5659 && rtx_equal_p (XEXP (op0, 1), op1)
5660 && ! side_effects_p (op1))
5661 return simplify_gen_binary (AND, mode,
5662 simplify_gen_unary (NOT, mode,
5663 XEXP (op0, 0), mode),
5666 else if (GET_CODE (op0) == AND
5667 && rtx_equal_p (XEXP (op0, 0), op1)
5668 && ! side_effects_p (op1))
5669 return simplify_gen_binary (AND, mode,
5670 simplify_gen_unary (NOT, mode,
5671 XEXP (op0, 1), mode),
5674 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5675 comparison if STORE_FLAG_VALUE is 1. */
5676 if (STORE_FLAG_VALUE == 1
5677 && op1 == const1_rtx
5678 && COMPARISON_P (op0)
5679 && (reversed = reversed_comparison (op0, mode)))
5682 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5683 is (lt foo (const_int 0)), so we can perform the above
5684 simplification if STORE_FLAG_VALUE is 1. */
5686 if (STORE_FLAG_VALUE == 1
5687 && op1 == const1_rtx
5688 && GET_CODE (op0) == LSHIFTRT
5689 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5690 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5691 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5693 /* (xor (comparison foo bar) (const_int sign-bit))
5694 when STORE_FLAG_VALUE is the sign bit. */
5695 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5696 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5697 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5698 && op1 == const_true_rtx
5699 && COMPARISON_P (op0)
5700 && (reversed = reversed_comparison (op0, mode)))
5712 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5713 operations" because they can be replaced with two more basic operations.
5714 ZERO_EXTEND is also considered "compound" because it can be replaced with
5715 an AND operation, which is simpler, though only one operation.
5717 The function expand_compound_operation is called with an rtx expression
5718 and will convert it to the appropriate shifts and AND operations,
5719 simplifying at each stage.
5721 The function make_compound_operation is called to convert an expression
5722 consisting of shifts and ANDs into the equivalent compound expression.
5723 It is the inverse of this function, loosely speaking. */
5726 expand_compound_operation (rtx x)
5728 unsigned HOST_WIDE_INT pos = 0, len;
5730 unsigned int modewidth;
5733 switch (GET_CODE (x))
5738 /* We can't necessarily use a const_int for a multiword mode;
5739 it depends on implicitly extending the value.
5740 Since we don't know the right way to extend it,
5741 we can't tell whether the implicit way is right.
5743 Even for a mode that is no wider than a const_int,
5744 we can't win, because we need to sign extend one of its bits through
5745 the rest of it, and we don't know which bit. */
5746 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5749 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5750 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5751 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5752 reloaded. If not for that, MEM's would very rarely be safe.
5754 Reject MODEs bigger than a word, because we might not be able
5755 to reference a two-register group starting with an arbitrary register
5756 (and currently gen_lowpart might crash for a SUBREG). */
5758 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5761 /* Reject MODEs that aren't scalar integers because turning vector
5762 or complex modes into shifts causes problems. */
5764 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5767 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5768 /* If the inner object has VOIDmode (the only way this can happen
5769 is if it is an ASM_OPERANDS), we can't do anything since we don't
5770 know how much masking to do. */
5779 /* ... fall through ... */
5782 /* If the operand is a CLOBBER, just return it. */
5783 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5786 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5787 || GET_CODE (XEXP (x, 2)) != CONST_INT
5788 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5791 /* Reject MODEs that aren't scalar integers because turning vector
5792 or complex modes into shifts causes problems. */
5794 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5797 len = INTVAL (XEXP (x, 1));
5798 pos = INTVAL (XEXP (x, 2));
5800 /* If this goes outside the object being extracted, replace the object
5801 with a (use (mem ...)) construct that only combine understands
5802 and is used only for this purpose. */
5803 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5804 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5806 if (BITS_BIG_ENDIAN)
5807 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5814 /* Convert sign extension to zero extension, if we know that the high
5815 bit is not set, as this is easier to optimize. It will be converted
5816 back to cheaper alternative in make_extraction. */
5817 if (GET_CODE (x) == SIGN_EXTEND
5818 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5819 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5820 & ~(((unsigned HOST_WIDE_INT)
5821 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5825 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5826 rtx temp2 = expand_compound_operation (temp);
5828 /* Make sure this is a profitable operation. */
5829 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5831 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5837 /* We can optimize some special cases of ZERO_EXTEND. */
5838 if (GET_CODE (x) == ZERO_EXTEND)
5840 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5841 know that the last value didn't have any inappropriate bits
5843 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5844 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5845 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5846 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5847 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5848 return XEXP (XEXP (x, 0), 0);
5850 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5851 if (GET_CODE (XEXP (x, 0)) == SUBREG
5852 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5853 && subreg_lowpart_p (XEXP (x, 0))
5854 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5855 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5856 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5857 return SUBREG_REG (XEXP (x, 0));
5859 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5860 is a comparison and STORE_FLAG_VALUE permits. This is like
5861 the first case, but it works even when GET_MODE (x) is larger
5862 than HOST_WIDE_INT. */
5863 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5864 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5865 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5866 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5867 <= HOST_BITS_PER_WIDE_INT)
5868 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5869 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5870 return XEXP (XEXP (x, 0), 0);
5872 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5873 if (GET_CODE (XEXP (x, 0)) == SUBREG
5874 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5875 && subreg_lowpart_p (XEXP (x, 0))
5876 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5877 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5878 <= HOST_BITS_PER_WIDE_INT)
5879 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5880 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5881 return SUBREG_REG (XEXP (x, 0));
5885 /* If we reach here, we want to return a pair of shifts. The inner
5886 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5887 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5888 logical depending on the value of UNSIGNEDP.
5890 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5891 converted into an AND of a shift.
5893 We must check for the case where the left shift would have a negative
5894 count. This can happen in a case like (x >> 31) & 255 on machines
5895 that can't shift by a constant. On those machines, we would first
5896 combine the shift with the AND to produce a variable-position
5897 extraction. Then the constant of 31 would be substituted in to produce
5898 a such a position. */
5900 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5901 if (modewidth + len >= pos)
5902 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5904 simplify_shift_const (NULL_RTX, ASHIFT,
5907 modewidth - pos - len),
5910 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5911 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5912 simplify_shift_const (NULL_RTX, LSHIFTRT,
5915 ((HOST_WIDE_INT) 1 << len) - 1);
5917 /* Any other cases we can't handle. */
5920 /* If we couldn't do this for some reason, return the original
5922 if (GET_CODE (tem) == CLOBBER)
5928 /* X is a SET which contains an assignment of one object into
5929 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5930 or certain SUBREGS). If possible, convert it into a series of
5933 We half-heartedly support variable positions, but do not at all
5934 support variable lengths. */
5937 expand_field_assignment (rtx x)
5940 rtx pos; /* Always counts from low bit. */
5942 rtx mask, cleared, masked;
5943 enum machine_mode compute_mode;
5945 /* Loop until we find something we can't simplify. */
5948 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5949 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5951 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5952 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5953 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5955 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5956 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5958 inner = XEXP (SET_DEST (x), 0);
5959 len = INTVAL (XEXP (SET_DEST (x), 1));
5960 pos = XEXP (SET_DEST (x), 2);
5962 /* If the position is constant and spans the width of INNER,
5963 surround INNER with a USE to indicate this. */
5964 if (GET_CODE (pos) == CONST_INT
5965 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5966 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5968 if (BITS_BIG_ENDIAN)
5970 if (GET_CODE (pos) == CONST_INT)
5971 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5973 else if (GET_CODE (pos) == MINUS
5974 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5975 && (INTVAL (XEXP (pos, 1))
5976 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5977 /* If position is ADJUST - X, new position is X. */
5978 pos = XEXP (pos, 0);
5980 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5981 GEN_INT (GET_MODE_BITSIZE (
5988 /* A SUBREG between two modes that occupy the same numbers of words
5989 can be done by moving the SUBREG to the source. */
5990 else if (GET_CODE (SET_DEST (x)) == SUBREG
5991 /* We need SUBREGs to compute nonzero_bits properly. */
5992 && nonzero_sign_valid
5993 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5994 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5995 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5996 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5998 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6000 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6007 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6008 inner = SUBREG_REG (inner);
6010 compute_mode = GET_MODE (inner);
6012 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6013 if (! SCALAR_INT_MODE_P (compute_mode))
6015 enum machine_mode imode;
6017 /* Don't do anything for vector or complex integral types. */
6018 if (! FLOAT_MODE_P (compute_mode))
6021 /* Try to find an integral mode to pun with. */
6022 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6023 if (imode == BLKmode)
6026 compute_mode = imode;
6027 inner = gen_lowpart (imode, inner);
6030 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6031 if (len >= HOST_BITS_PER_WIDE_INT)
6034 /* Now compute the equivalent expression. Make a copy of INNER
6035 for the SET_DEST in case it is a MEM into which we will substitute;
6036 we don't want shared RTL in that case. */
6037 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6038 cleared = simplify_gen_binary (AND, compute_mode,
6039 simplify_gen_unary (NOT, compute_mode,
6040 simplify_gen_binary (ASHIFT,
6045 masked = simplify_gen_binary (ASHIFT, compute_mode,
6046 simplify_gen_binary (
6048 gen_lowpart (compute_mode, SET_SRC (x)),
6052 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6053 simplify_gen_binary (IOR, compute_mode,
6060 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6061 it is an RTX that represents a variable starting position; otherwise,
6062 POS is the (constant) starting bit position (counted from the LSB).
6064 INNER may be a USE. This will occur when we started with a bitfield
6065 that went outside the boundary of the object in memory, which is
6066 allowed on most machines. To isolate this case, we produce a USE
6067 whose mode is wide enough and surround the MEM with it. The only
6068 code that understands the USE is this routine. If it is not removed,
6069 it will cause the resulting insn not to match.
6071 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6074 IN_DEST is nonzero if this is a reference in the destination of a
6075 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6076 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6079 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6080 ZERO_EXTRACT should be built even for bits starting at bit 0.
6082 MODE is the desired mode of the result (if IN_DEST == 0).
6084 The result is an RTX for the extraction or NULL_RTX if the target
6088 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6089 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6090 int in_dest, int in_compare)
6092 /* This mode describes the size of the storage area
6093 to fetch the overall value from. Within that, we
6094 ignore the POS lowest bits, etc. */
6095 enum machine_mode is_mode = GET_MODE (inner);
6096 enum machine_mode inner_mode;
6097 enum machine_mode wanted_inner_mode = byte_mode;
6098 enum machine_mode wanted_inner_reg_mode = word_mode;
6099 enum machine_mode pos_mode = word_mode;
6100 enum machine_mode extraction_mode = word_mode;
6101 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6104 rtx orig_pos_rtx = pos_rtx;
6105 HOST_WIDE_INT orig_pos;
6107 /* Get some information about INNER and get the innermost object. */
6108 if (GET_CODE (inner) == USE)
6109 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6110 /* We don't need to adjust the position because we set up the USE
6111 to pretend that it was a full-word object. */
6112 spans_byte = 1, inner = XEXP (inner, 0);
6113 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6115 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6116 consider just the QI as the memory to extract from.
6117 The subreg adds or removes high bits; its mode is
6118 irrelevant to the meaning of this extraction,
6119 since POS and LEN count from the lsb. */
6120 if (MEM_P (SUBREG_REG (inner)))
6121 is_mode = GET_MODE (SUBREG_REG (inner));
6122 inner = SUBREG_REG (inner);
6124 else if (GET_CODE (inner) == ASHIFT
6125 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6126 && pos_rtx == 0 && pos == 0
6127 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6129 /* We're extracting the least significant bits of an rtx
6130 (ashift X (const_int C)), where LEN > C. Extract the
6131 least significant (LEN - C) bits of X, giving an rtx
6132 whose mode is MODE, then shift it left C times. */
6133 new = make_extraction (mode, XEXP (inner, 0),
6134 0, 0, len - INTVAL (XEXP (inner, 1)),
6135 unsignedp, in_dest, in_compare);
6137 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6140 inner_mode = GET_MODE (inner);
6142 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6143 pos = INTVAL (pos_rtx), pos_rtx = 0;
6145 /* See if this can be done without an extraction. We never can if the
6146 width of the field is not the same as that of some integer mode. For
6147 registers, we can only avoid the extraction if the position is at the
6148 low-order bit and this is either not in the destination or we have the
6149 appropriate STRICT_LOW_PART operation available.
6151 For MEM, we can avoid an extract if the field starts on an appropriate
6152 boundary and we can change the mode of the memory reference. However,
6153 we cannot directly access the MEM if we have a USE and the underlying
6154 MEM is not TMODE. This combination means that MEM was being used in a
6155 context where bits outside its mode were being referenced; that is only
6156 valid in bit-field insns. */
6158 if (tmode != BLKmode
6159 && ! (spans_byte && inner_mode != tmode)
6160 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6164 && have_insn_for (STRICT_LOW_PART, tmode))))
6165 || (MEM_P (inner) && pos_rtx == 0
6167 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6168 : BITS_PER_UNIT)) == 0
6169 /* We can't do this if we are widening INNER_MODE (it
6170 may not be aligned, for one thing). */
6171 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6172 && (inner_mode == tmode
6173 || (! mode_dependent_address_p (XEXP (inner, 0))
6174 && ! MEM_VOLATILE_P (inner))))))
6176 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6177 field. If the original and current mode are the same, we need not
6178 adjust the offset. Otherwise, we do if bytes big endian.
6180 If INNER is not a MEM, get a piece consisting of just the field
6181 of interest (in this case POS % BITS_PER_WORD must be 0). */
6185 HOST_WIDE_INT offset;
6187 /* POS counts from lsb, but make OFFSET count in memory order. */
6188 if (BYTES_BIG_ENDIAN)
6189 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6191 offset = pos / BITS_PER_UNIT;
6193 new = adjust_address_nv (inner, tmode, offset);
6195 else if (REG_P (inner))
6197 if (tmode != inner_mode)
6199 /* We can't call gen_lowpart in a DEST since we
6200 always want a SUBREG (see below) and it would sometimes
6201 return a new hard register. */
6204 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6206 if (WORDS_BIG_ENDIAN
6207 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6208 final_word = ((GET_MODE_SIZE (inner_mode)
6209 - GET_MODE_SIZE (tmode))
6210 / UNITS_PER_WORD) - final_word;
6212 final_word *= UNITS_PER_WORD;
6213 if (BYTES_BIG_ENDIAN &&
6214 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6215 final_word += (GET_MODE_SIZE (inner_mode)
6216 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6218 /* Avoid creating invalid subregs, for example when
6219 simplifying (x>>32)&255. */
6220 if (final_word >= GET_MODE_SIZE (inner_mode))
6223 new = gen_rtx_SUBREG (tmode, inner, final_word);
6226 new = gen_lowpart (tmode, inner);
6232 new = force_to_mode (inner, tmode,
6233 len >= HOST_BITS_PER_WIDE_INT
6234 ? ~(unsigned HOST_WIDE_INT) 0
6235 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6238 /* If this extraction is going into the destination of a SET,
6239 make a STRICT_LOW_PART unless we made a MEM. */
6242 return (MEM_P (new) ? new
6243 : (GET_CODE (new) != SUBREG
6244 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6245 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6250 if (GET_CODE (new) == CONST_INT)
6251 return gen_int_mode (INTVAL (new), mode);
6253 /* If we know that no extraneous bits are set, and that the high
6254 bit is not set, convert the extraction to the cheaper of
6255 sign and zero extension, that are equivalent in these cases. */
6256 if (flag_expensive_optimizations
6257 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6258 && ((nonzero_bits (new, tmode)
6259 & ~(((unsigned HOST_WIDE_INT)
6260 GET_MODE_MASK (tmode))
6264 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6265 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6267 /* Prefer ZERO_EXTENSION, since it gives more information to
6269 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6274 /* Otherwise, sign- or zero-extend unless we already are in the
6277 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6281 /* Unless this is a COMPARE or we have a funny memory reference,
6282 don't do anything with zero-extending field extracts starting at
6283 the low-order bit since they are simple AND operations. */
6284 if (pos_rtx == 0 && pos == 0 && ! in_dest
6285 && ! in_compare && ! spans_byte && unsignedp)
6288 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6289 we would be spanning bytes or if the position is not a constant and the
6290 length is not 1. In all other cases, we would only be going outside
6291 our object in cases when an original shift would have been
6293 if (! spans_byte && MEM_P (inner)
6294 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6295 || (pos_rtx != 0 && len != 1)))
6298 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6299 and the mode for the result. */
6300 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6302 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6303 pos_mode = mode_for_extraction (EP_insv, 2);
6304 extraction_mode = mode_for_extraction (EP_insv, 3);
6307 if (! in_dest && unsignedp
6308 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6310 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6311 pos_mode = mode_for_extraction (EP_extzv, 3);
6312 extraction_mode = mode_for_extraction (EP_extzv, 0);
6315 if (! in_dest && ! unsignedp
6316 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6318 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6319 pos_mode = mode_for_extraction (EP_extv, 3);
6320 extraction_mode = mode_for_extraction (EP_extv, 0);
6323 /* Never narrow an object, since that might not be safe. */
6325 if (mode != VOIDmode
6326 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6327 extraction_mode = mode;
6329 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6330 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6331 pos_mode = GET_MODE (pos_rtx);
6333 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6334 if we have to change the mode of memory and cannot, the desired mode is
6337 wanted_inner_mode = wanted_inner_reg_mode;
6338 else if (inner_mode != wanted_inner_mode
6339 && (mode_dependent_address_p (XEXP (inner, 0))
6340 || MEM_VOLATILE_P (inner)))
6341 wanted_inner_mode = extraction_mode;
6345 if (BITS_BIG_ENDIAN)
6347 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6348 BITS_BIG_ENDIAN style. If position is constant, compute new
6349 position. Otherwise, build subtraction.
6350 Note that POS is relative to the mode of the original argument.
6351 If it's a MEM we need to recompute POS relative to that.
6352 However, if we're extracting from (or inserting into) a register,
6353 we want to recompute POS relative to wanted_inner_mode. */
6354 int width = (MEM_P (inner)
6355 ? GET_MODE_BITSIZE (is_mode)
6356 : GET_MODE_BITSIZE (wanted_inner_mode));
6359 pos = width - len - pos;
6362 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6363 /* POS may be less than 0 now, but we check for that below.
6364 Note that it can only be less than 0 if !MEM_P (inner). */
6367 /* If INNER has a wider mode, make it smaller. If this is a constant
6368 extract, try to adjust the byte to point to the byte containing
6370 if (wanted_inner_mode != VOIDmode
6371 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6373 && (inner_mode == wanted_inner_mode
6374 || (! mode_dependent_address_p (XEXP (inner, 0))
6375 && ! MEM_VOLATILE_P (inner))))))
6379 /* The computations below will be correct if the machine is big
6380 endian in both bits and bytes or little endian in bits and bytes.
6381 If it is mixed, we must adjust. */
6383 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6384 adjust OFFSET to compensate. */
6385 if (BYTES_BIG_ENDIAN
6387 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6388 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6390 /* If this is a constant position, we can move to the desired byte. */
6393 offset += pos / BITS_PER_UNIT;
6394 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6397 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6399 && is_mode != wanted_inner_mode)
6400 offset = (GET_MODE_SIZE (is_mode)
6401 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6403 if (offset != 0 || inner_mode != wanted_inner_mode)
6404 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6407 /* If INNER is not memory, we can always get it into the proper mode. If we
6408 are changing its mode, POS must be a constant and smaller than the size
6410 else if (!MEM_P (inner))
6412 if (GET_MODE (inner) != wanted_inner_mode
6414 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6417 inner = force_to_mode (inner, wanted_inner_mode,
6419 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6420 ? ~(unsigned HOST_WIDE_INT) 0
6421 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6426 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6427 have to zero extend. Otherwise, we can just use a SUBREG. */
6429 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6431 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6433 /* If we know that no extraneous bits are set, and that the high
6434 bit is not set, convert extraction to cheaper one - either
6435 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6437 if (flag_expensive_optimizations
6438 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6439 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6440 & ~(((unsigned HOST_WIDE_INT)
6441 GET_MODE_MASK (GET_MODE (pos_rtx)))
6445 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6447 /* Prefer ZERO_EXTENSION, since it gives more information to
6449 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6454 else if (pos_rtx != 0
6455 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6456 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6458 /* Make POS_RTX unless we already have it and it is correct. If we don't
6459 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6461 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6462 pos_rtx = orig_pos_rtx;
6464 else if (pos_rtx == 0)
6465 pos_rtx = GEN_INT (pos);
6467 /* Make the required operation. See if we can use existing rtx. */
6468 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6469 extraction_mode, inner, GEN_INT (len), pos_rtx);
6471 new = gen_lowpart (mode, new);
6476 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6477 with any other operations in X. Return X without that shift if so. */
6480 extract_left_shift (rtx x, int count)
6482 enum rtx_code code = GET_CODE (x);
6483 enum machine_mode mode = GET_MODE (x);
6489 /* This is the shift itself. If it is wide enough, we will return
6490 either the value being shifted if the shift count is equal to
6491 COUNT or a shift for the difference. */
6492 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6493 && INTVAL (XEXP (x, 1)) >= count)
6494 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6495 INTVAL (XEXP (x, 1)) - count);
6499 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6500 return simplify_gen_unary (code, mode, tem, mode);
6504 case PLUS: case IOR: case XOR: case AND:
6505 /* If we can safely shift this constant and we find the inner shift,
6506 make a new operation. */
6507 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6508 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6509 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6510 return simplify_gen_binary (code, mode, tem,
6511 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6522 /* Look at the expression rooted at X. Look for expressions
6523 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6524 Form these expressions.
6526 Return the new rtx, usually just X.
6528 Also, for machines like the VAX that don't have logical shift insns,
6529 try to convert logical to arithmetic shift operations in cases where
6530 they are equivalent. This undoes the canonicalizations to logical
6531 shifts done elsewhere.
6533 We try, as much as possible, to re-use rtl expressions to save memory.
6535 IN_CODE says what kind of expression we are processing. Normally, it is
6536 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6537 being kludges), it is MEM. When processing the arguments of a comparison
6538 or a COMPARE against zero, it is COMPARE. */
6541 make_compound_operation (rtx x, enum rtx_code in_code)
6543 enum rtx_code code = GET_CODE (x);
6544 enum machine_mode mode = GET_MODE (x);
6545 int mode_width = GET_MODE_BITSIZE (mode);
6547 enum rtx_code next_code;
6553 /* Select the code to be used in recursive calls. Once we are inside an
6554 address, we stay there. If we have a comparison, set to COMPARE,
6555 but once inside, go back to our default of SET. */
6557 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6558 : ((code == COMPARE || COMPARISON_P (x))
6559 && XEXP (x, 1) == const0_rtx) ? COMPARE
6560 : in_code == COMPARE ? SET : in_code);
6562 /* Process depending on the code of this operation. If NEW is set
6563 nonzero, it will be returned. */
6568 /* Convert shifts by constants into multiplications if inside
6570 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6571 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6572 && INTVAL (XEXP (x, 1)) >= 0)
6574 new = make_compound_operation (XEXP (x, 0), next_code);
6575 new = gen_rtx_MULT (mode, new,
6576 GEN_INT ((HOST_WIDE_INT) 1
6577 << INTVAL (XEXP (x, 1))));
6582 /* If the second operand is not a constant, we can't do anything
6584 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6587 /* If the constant is a power of two minus one and the first operand
6588 is a logical right shift, make an extraction. */
6589 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6590 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6592 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6593 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6594 0, in_code == COMPARE);
6597 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6598 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6599 && subreg_lowpart_p (XEXP (x, 0))
6600 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6601 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6603 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6605 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6606 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6607 0, in_code == COMPARE);
6609 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6610 else if ((GET_CODE (XEXP (x, 0)) == XOR
6611 || GET_CODE (XEXP (x, 0)) == IOR)
6612 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6613 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6614 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6616 /* Apply the distributive law, and then try to make extractions. */
6617 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6618 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6620 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6622 new = make_compound_operation (new, in_code);
6625 /* If we are have (and (rotate X C) M) and C is larger than the number
6626 of bits in M, this is an extraction. */
6628 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6629 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6630 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6631 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6633 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6634 new = make_extraction (mode, new,
6635 (GET_MODE_BITSIZE (mode)
6636 - INTVAL (XEXP (XEXP (x, 0), 1))),
6637 NULL_RTX, i, 1, 0, in_code == COMPARE);
6640 /* On machines without logical shifts, if the operand of the AND is
6641 a logical shift and our mask turns off all the propagated sign
6642 bits, we can replace the logical shift with an arithmetic shift. */
6643 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6644 && !have_insn_for (LSHIFTRT, mode)
6645 && have_insn_for (ASHIFTRT, mode)
6646 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6647 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6648 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6649 && mode_width <= HOST_BITS_PER_WIDE_INT)
6651 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6653 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6654 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6656 gen_rtx_ASHIFTRT (mode,
6657 make_compound_operation
6658 (XEXP (XEXP (x, 0), 0), next_code),
6659 XEXP (XEXP (x, 0), 1)));
6662 /* If the constant is one less than a power of two, this might be
6663 representable by an extraction even if no shift is present.
6664 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6665 we are in a COMPARE. */
6666 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6667 new = make_extraction (mode,
6668 make_compound_operation (XEXP (x, 0),
6670 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6672 /* If we are in a comparison and this is an AND with a power of two,
6673 convert this into the appropriate bit extract. */
6674 else if (in_code == COMPARE
6675 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6676 new = make_extraction (mode,
6677 make_compound_operation (XEXP (x, 0),
6679 i, NULL_RTX, 1, 1, 0, 1);
6684 /* If the sign bit is known to be zero, replace this with an
6685 arithmetic shift. */
6686 if (have_insn_for (ASHIFTRT, mode)
6687 && ! have_insn_for (LSHIFTRT, mode)
6688 && mode_width <= HOST_BITS_PER_WIDE_INT
6689 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6691 new = gen_rtx_ASHIFTRT (mode,
6692 make_compound_operation (XEXP (x, 0),
6698 /* ... fall through ... */
6704 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6705 this is a SIGN_EXTRACT. */
6706 if (GET_CODE (rhs) == CONST_INT
6707 && GET_CODE (lhs) == ASHIFT
6708 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6709 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6711 new = make_compound_operation (XEXP (lhs, 0), next_code);
6712 new = make_extraction (mode, new,
6713 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6714 NULL_RTX, mode_width - INTVAL (rhs),
6715 code == LSHIFTRT, 0, in_code == COMPARE);
6719 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6720 If so, try to merge the shifts into a SIGN_EXTEND. We could
6721 also do this for some cases of SIGN_EXTRACT, but it doesn't
6722 seem worth the effort; the case checked for occurs on Alpha. */
6725 && ! (GET_CODE (lhs) == SUBREG
6726 && (OBJECT_P (SUBREG_REG (lhs))))
6727 && GET_CODE (rhs) == CONST_INT
6728 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6729 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6730 new = make_extraction (mode, make_compound_operation (new, next_code),
6731 0, NULL_RTX, mode_width - INTVAL (rhs),
6732 code == LSHIFTRT, 0, in_code == COMPARE);
6737 /* Call ourselves recursively on the inner expression. If we are
6738 narrowing the object and it has a different RTL code from
6739 what it originally did, do this SUBREG as a force_to_mode. */
6741 tem = make_compound_operation (SUBREG_REG (x), in_code);
6745 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6751 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6752 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6753 && subreg_lowpart_p (x))
6755 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6758 /* If we have something other than a SUBREG, we might have
6759 done an expansion, so rerun ourselves. */
6760 if (GET_CODE (newer) != SUBREG)
6761 newer = make_compound_operation (newer, in_code);
6777 x = gen_lowpart (mode, new);
6778 code = GET_CODE (x);
6781 /* Now recursively process each operand of this operation. */
6782 fmt = GET_RTX_FORMAT (code);
6783 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6786 new = make_compound_operation (XEXP (x, i), next_code);
6787 SUBST (XEXP (x, i), new);
6793 /* Given M see if it is a value that would select a field of bits
6794 within an item, but not the entire word. Return -1 if not.
6795 Otherwise, return the starting position of the field, where 0 is the
6798 *PLEN is set to the length of the field. */
6801 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6803 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6804 int pos = exact_log2 (m & -m);
6808 /* Now shift off the low-order zero bits and see if we have a
6809 power of two minus 1. */
6810 len = exact_log2 ((m >> pos) + 1);
6819 /* See if X can be simplified knowing that we will only refer to it in
6820 MODE and will only refer to those bits that are nonzero in MASK.
6821 If other bits are being computed or if masking operations are done
6822 that select a superset of the bits in MASK, they can sometimes be
6825 Return a possibly simplified expression, but always convert X to
6826 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6828 Also, if REG is nonzero and X is a register equal in value to REG,
6831 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6832 are all off in X. This is used when X will be complemented, by either
6833 NOT, NEG, or XOR. */
6836 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6837 rtx reg, int just_select)
6839 enum rtx_code code = GET_CODE (x);
6840 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6841 enum machine_mode op_mode;
6842 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6845 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6846 code below will do the wrong thing since the mode of such an
6847 expression is VOIDmode.
6849 Also do nothing if X is a CLOBBER; this can happen if X was
6850 the return value from a call to gen_lowpart. */
6851 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6854 /* We want to perform the operation is its present mode unless we know
6855 that the operation is valid in MODE, in which case we do the operation
6857 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6858 && have_insn_for (code, mode))
6859 ? mode : GET_MODE (x));
6861 /* It is not valid to do a right-shift in a narrower mode
6862 than the one it came in with. */
6863 if ((code == LSHIFTRT || code == ASHIFTRT)
6864 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6865 op_mode = GET_MODE (x);
6867 /* Truncate MASK to fit OP_MODE. */
6869 mask &= GET_MODE_MASK (op_mode);
6871 /* When we have an arithmetic operation, or a shift whose count we
6872 do not know, we need to assume that all bits up to the highest-order
6873 bit in MASK will be needed. This is how we form such a mask. */
6874 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6875 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6877 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6880 /* Determine what bits of X are guaranteed to be (non)zero. */
6881 nonzero = nonzero_bits (x, mode);
6883 /* If none of the bits in X are needed, return a zero. */
6884 if (! just_select && (nonzero & mask) == 0)
6887 /* If X is a CONST_INT, return a new one. Do this here since the
6888 test below will fail. */
6889 if (GET_CODE (x) == CONST_INT)
6891 if (SCALAR_INT_MODE_P (mode))
6892 return gen_int_mode (INTVAL (x) & mask, mode);
6895 x = GEN_INT (INTVAL (x) & mask);
6896 return gen_lowpart_common (mode, x);
6900 /* If X is narrower than MODE and we want all the bits in X's mode, just
6901 get X in the proper mode. */
6902 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6903 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6904 return gen_lowpart (mode, x);
6909 /* If X is a (clobber (const_int)), return it since we know we are
6910 generating something that won't match. */
6914 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6915 spanned the boundary of the MEM. If we are now masking so it is
6916 within that boundary, we don't need the USE any more. */
6917 if (! BITS_BIG_ENDIAN
6918 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6919 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6926 x = expand_compound_operation (x);
6927 if (GET_CODE (x) != code)
6928 return force_to_mode (x, mode, mask, reg, next_select);
6932 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6933 || rtx_equal_p (reg, get_last_value (x))))
6938 if (subreg_lowpart_p (x)
6939 /* We can ignore the effect of this SUBREG if it narrows the mode or
6940 if the constant masks to zero all the bits the mode doesn't
6942 && ((GET_MODE_SIZE (GET_MODE (x))
6943 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6945 & GET_MODE_MASK (GET_MODE (x))
6946 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6947 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6951 /* If this is an AND with a constant, convert it into an AND
6952 whose constant is the AND of that constant with MASK. If it
6953 remains an AND of MASK, delete it since it is redundant. */
6955 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6957 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6958 mask & INTVAL (XEXP (x, 1)));
6960 /* If X is still an AND, see if it is an AND with a mask that
6961 is just some low-order bits. If so, and it is MASK, we don't
6964 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6965 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6969 /* If it remains an AND, try making another AND with the bits
6970 in the mode mask that aren't in MASK turned on. If the
6971 constant in the AND is wide enough, this might make a
6972 cheaper constant. */
6974 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6975 && GET_MODE_MASK (GET_MODE (x)) != mask
6976 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6978 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6979 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6980 int width = GET_MODE_BITSIZE (GET_MODE (x));
6983 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6984 number, sign extend it. */
6985 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6986 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6987 cval |= (HOST_WIDE_INT) -1 << width;
6989 y = simplify_gen_binary (AND, GET_MODE (x),
6990 XEXP (x, 0), GEN_INT (cval));
6991 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7001 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7002 low-order bits (as in an alignment operation) and FOO is already
7003 aligned to that boundary, mask C1 to that boundary as well.
7004 This may eliminate that PLUS and, later, the AND. */
7007 unsigned int width = GET_MODE_BITSIZE (mode);
7008 unsigned HOST_WIDE_INT smask = mask;
7010 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7011 number, sign extend it. */
7013 if (width < HOST_BITS_PER_WIDE_INT
7014 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7015 smask |= (HOST_WIDE_INT) -1 << width;
7017 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7018 && exact_log2 (- smask) >= 0
7019 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7020 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7021 return force_to_mode (plus_constant (XEXP (x, 0),
7022 (INTVAL (XEXP (x, 1)) & smask)),
7023 mode, smask, reg, next_select);
7026 /* ... fall through ... */
7029 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7030 most significant bit in MASK since carries from those bits will
7031 affect the bits we are interested in. */
7036 /* If X is (minus C Y) where C's least set bit is larger than any bit
7037 in the mask, then we may replace with (neg Y). */
7038 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7039 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7040 & -INTVAL (XEXP (x, 0))))
7043 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7045 return force_to_mode (x, mode, mask, reg, next_select);
7048 /* Similarly, if C contains every bit in the fuller_mask, then we may
7049 replace with (not Y). */
7050 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7051 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7052 == INTVAL (XEXP (x, 0))))
7054 x = simplify_gen_unary (NOT, GET_MODE (x),
7055 XEXP (x, 1), GET_MODE (x));
7056 return force_to_mode (x, mode, mask, reg, next_select);
7064 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7065 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7066 operation which may be a bitfield extraction. Ensure that the
7067 constant we form is not wider than the mode of X. */
7069 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7070 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7071 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7072 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7073 && GET_CODE (XEXP (x, 1)) == CONST_INT
7074 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7075 + floor_log2 (INTVAL (XEXP (x, 1))))
7076 < GET_MODE_BITSIZE (GET_MODE (x)))
7077 && (INTVAL (XEXP (x, 1))
7078 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7080 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7081 << INTVAL (XEXP (XEXP (x, 0), 1)));
7082 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7083 XEXP (XEXP (x, 0), 0), temp);
7084 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7085 XEXP (XEXP (x, 0), 1));
7086 return force_to_mode (x, mode, mask, reg, next_select);
7090 /* For most binary operations, just propagate into the operation and
7091 change the mode if we have an operation of that mode. */
7093 op0 = gen_lowpart (op_mode,
7094 force_to_mode (XEXP (x, 0), mode, mask,
7096 op1 = gen_lowpart (op_mode,
7097 force_to_mode (XEXP (x, 1), mode, mask,
7100 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7101 x = simplify_gen_binary (code, op_mode, op0, op1);
7105 /* For left shifts, do the same, but just for the first operand.
7106 However, we cannot do anything with shifts where we cannot
7107 guarantee that the counts are smaller than the size of the mode
7108 because such a count will have a different meaning in a
7111 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7112 && INTVAL (XEXP (x, 1)) >= 0
7113 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7114 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7115 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7116 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7119 /* If the shift count is a constant and we can do arithmetic in
7120 the mode of the shift, refine which bits we need. Otherwise, use the
7121 conservative form of the mask. */
7122 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7123 && INTVAL (XEXP (x, 1)) >= 0
7124 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7125 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7126 mask >>= INTVAL (XEXP (x, 1));
7130 op0 = gen_lowpart (op_mode,
7131 force_to_mode (XEXP (x, 0), op_mode,
7132 mask, reg, next_select));
7134 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7135 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7139 /* Here we can only do something if the shift count is a constant,
7140 this shift constant is valid for the host, and we can do arithmetic
7143 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7144 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7145 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7147 rtx inner = XEXP (x, 0);
7148 unsigned HOST_WIDE_INT inner_mask;
7150 /* Select the mask of the bits we need for the shift operand. */
7151 inner_mask = mask << INTVAL (XEXP (x, 1));
7153 /* We can only change the mode of the shift if we can do arithmetic
7154 in the mode of the shift and INNER_MASK is no wider than the
7155 width of X's mode. */
7156 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7157 op_mode = GET_MODE (x);
7159 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7161 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7162 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7165 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7166 shift and AND produces only copies of the sign bit (C2 is one less
7167 than a power of two), we can do this with just a shift. */
7169 if (GET_CODE (x) == LSHIFTRT
7170 && GET_CODE (XEXP (x, 1)) == CONST_INT
7171 /* The shift puts one of the sign bit copies in the least significant
7173 && ((INTVAL (XEXP (x, 1))
7174 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7175 >= GET_MODE_BITSIZE (GET_MODE (x)))
7176 && exact_log2 (mask + 1) >= 0
7177 /* Number of bits left after the shift must be more than the mask
7179 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7180 <= GET_MODE_BITSIZE (GET_MODE (x)))
7181 /* Must be more sign bit copies than the mask needs. */
7182 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7183 >= exact_log2 (mask + 1)))
7184 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7185 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7186 - exact_log2 (mask + 1)));
7191 /* If we are just looking for the sign bit, we don't need this shift at
7192 all, even if it has a variable count. */
7193 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7194 && (mask == ((unsigned HOST_WIDE_INT) 1
7195 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7196 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7198 /* If this is a shift by a constant, get a mask that contains those bits
7199 that are not copies of the sign bit. We then have two cases: If
7200 MASK only includes those bits, this can be a logical shift, which may
7201 allow simplifications. If MASK is a single-bit field not within
7202 those bits, we are requesting a copy of the sign bit and hence can
7203 shift the sign bit to the appropriate location. */
7205 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7206 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7210 /* If the considered data is wider than HOST_WIDE_INT, we can't
7211 represent a mask for all its bits in a single scalar.
7212 But we only care about the lower bits, so calculate these. */
7214 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7216 nonzero = ~(HOST_WIDE_INT) 0;
7218 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7219 is the number of bits a full-width mask would have set.
7220 We need only shift if these are fewer than nonzero can
7221 hold. If not, we must keep all bits set in nonzero. */
7223 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7224 < HOST_BITS_PER_WIDE_INT)
7225 nonzero >>= INTVAL (XEXP (x, 1))
7226 + HOST_BITS_PER_WIDE_INT
7227 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7231 nonzero = GET_MODE_MASK (GET_MODE (x));
7232 nonzero >>= INTVAL (XEXP (x, 1));
7235 if ((mask & ~nonzero) == 0
7236 || (i = exact_log2 (mask)) >= 0)
7238 x = simplify_shift_const
7239 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7240 i < 0 ? INTVAL (XEXP (x, 1))
7241 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7243 if (GET_CODE (x) != ASHIFTRT)
7244 return force_to_mode (x, mode, mask, reg, next_select);
7248 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7249 even if the shift count isn't a constant. */
7251 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7252 XEXP (x, 0), XEXP (x, 1));
7256 /* If this is a zero- or sign-extension operation that just affects bits
7257 we don't care about, remove it. Be sure the call above returned
7258 something that is still a shift. */
7260 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7261 && GET_CODE (XEXP (x, 1)) == CONST_INT
7262 && INTVAL (XEXP (x, 1)) >= 0
7263 && (INTVAL (XEXP (x, 1))
7264 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7265 && GET_CODE (XEXP (x, 0)) == ASHIFT
7266 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7267 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7274 /* If the shift count is constant and we can do computations
7275 in the mode of X, compute where the bits we care about are.
7276 Otherwise, we can't do anything. Don't change the mode of
7277 the shift or propagate MODE into the shift, though. */
7278 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7279 && INTVAL (XEXP (x, 1)) >= 0)
7281 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7282 GET_MODE (x), GEN_INT (mask),
7284 if (temp && GET_CODE (temp) == CONST_INT)
7286 force_to_mode (XEXP (x, 0), GET_MODE (x),
7287 INTVAL (temp), reg, next_select));
7292 /* If we just want the low-order bit, the NEG isn't needed since it
7293 won't change the low-order bit. */
7295 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7297 /* We need any bits less significant than the most significant bit in
7298 MASK since carries from those bits will affect the bits we are
7304 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7305 same as the XOR case above. Ensure that the constant we form is not
7306 wider than the mode of X. */
7308 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7309 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7310 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7311 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7312 < GET_MODE_BITSIZE (GET_MODE (x)))
7313 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7315 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7317 temp = simplify_gen_binary (XOR, GET_MODE (x),
7318 XEXP (XEXP (x, 0), 0), temp);
7319 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7320 temp, XEXP (XEXP (x, 0), 1));
7322 return force_to_mode (x, mode, mask, reg, next_select);
7325 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7326 use the full mask inside the NOT. */
7330 op0 = gen_lowpart (op_mode,
7331 force_to_mode (XEXP (x, 0), mode, mask,
7333 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7334 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7338 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7339 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7340 which is equal to STORE_FLAG_VALUE. */
7341 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7342 && GET_MODE (XEXP (x, 0)) == mode
7343 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7344 && (nonzero_bits (XEXP (x, 0), mode)
7345 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7346 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7351 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7352 written in a narrower mode. We play it safe and do not do so. */
7355 gen_lowpart (GET_MODE (x),
7356 force_to_mode (XEXP (x, 1), mode,
7357 mask, reg, next_select)));
7359 gen_lowpart (GET_MODE (x),
7360 force_to_mode (XEXP (x, 2), mode,
7361 mask, reg, next_select)));
7368 /* Ensure we return a value of the proper mode. */
7369 return gen_lowpart (mode, x);
7372 /* Return nonzero if X is an expression that has one of two values depending on
7373 whether some other value is zero or nonzero. In that case, we return the
7374 value that is being tested, *PTRUE is set to the value if the rtx being
7375 returned has a nonzero value, and *PFALSE is set to the other alternative.
7377 If we return zero, we set *PTRUE and *PFALSE to X. */
7380 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7382 enum machine_mode mode = GET_MODE (x);
7383 enum rtx_code code = GET_CODE (x);
7384 rtx cond0, cond1, true0, true1, false0, false1;
7385 unsigned HOST_WIDE_INT nz;
7387 /* If we are comparing a value against zero, we are done. */
7388 if ((code == NE || code == EQ)
7389 && XEXP (x, 1) == const0_rtx)
7391 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7392 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7396 /* If this is a unary operation whose operand has one of two values, apply
7397 our opcode to compute those values. */
7398 else if (UNARY_P (x)
7399 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7401 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7402 *pfalse = simplify_gen_unary (code, mode, false0,
7403 GET_MODE (XEXP (x, 0)));
7407 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7408 make can't possibly match and would suppress other optimizations. */
7409 else if (code == COMPARE)
7412 /* If this is a binary operation, see if either side has only one of two
7413 values. If either one does or if both do and they are conditional on
7414 the same value, compute the new true and false values. */
7415 else if (BINARY_P (x))
7417 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7418 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7420 if ((cond0 != 0 || cond1 != 0)
7421 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7423 /* If if_then_else_cond returned zero, then true/false are the
7424 same rtl. We must copy one of them to prevent invalid rtl
7427 true0 = copy_rtx (true0);
7428 else if (cond1 == 0)
7429 true1 = copy_rtx (true1);
7431 if (COMPARISON_P (x))
7433 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7435 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7440 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7441 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7444 return cond0 ? cond0 : cond1;
7447 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7448 operands is zero when the other is nonzero, and vice-versa,
7449 and STORE_FLAG_VALUE is 1 or -1. */
7451 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7452 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7454 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7456 rtx op0 = XEXP (XEXP (x, 0), 1);
7457 rtx op1 = XEXP (XEXP (x, 1), 1);
7459 cond0 = XEXP (XEXP (x, 0), 0);
7460 cond1 = XEXP (XEXP (x, 1), 0);
7462 if (COMPARISON_P (cond0)
7463 && COMPARISON_P (cond1)
7464 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7465 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7466 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7467 || ((swap_condition (GET_CODE (cond0))
7468 == reversed_comparison_code (cond1, NULL))
7469 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7470 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7471 && ! side_effects_p (x))
7473 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7474 *pfalse = simplify_gen_binary (MULT, mode,
7476 ? simplify_gen_unary (NEG, mode,
7484 /* Similarly for MULT, AND and UMIN, except that for these the result
7486 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7487 && (code == MULT || code == AND || code == UMIN)
7488 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7490 cond0 = XEXP (XEXP (x, 0), 0);
7491 cond1 = XEXP (XEXP (x, 1), 0);
7493 if (COMPARISON_P (cond0)
7494 && COMPARISON_P (cond1)
7495 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7496 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7497 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7498 || ((swap_condition (GET_CODE (cond0))
7499 == reversed_comparison_code (cond1, NULL))
7500 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7501 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7502 && ! side_effects_p (x))
7504 *ptrue = *pfalse = const0_rtx;
7510 else if (code == IF_THEN_ELSE)
7512 /* If we have IF_THEN_ELSE already, extract the condition and
7513 canonicalize it if it is NE or EQ. */
7514 cond0 = XEXP (x, 0);
7515 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7516 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7517 return XEXP (cond0, 0);
7518 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7520 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7521 return XEXP (cond0, 0);
7527 /* If X is a SUBREG, we can narrow both the true and false values
7528 if the inner expression, if there is a condition. */
7529 else if (code == SUBREG
7530 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7533 true0 = simplify_gen_subreg (mode, true0,
7534 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7535 false0 = simplify_gen_subreg (mode, false0,
7536 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7537 if (true0 && false0)
7545 /* If X is a constant, this isn't special and will cause confusions
7546 if we treat it as such. Likewise if it is equivalent to a constant. */
7547 else if (CONSTANT_P (x)
7548 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7551 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7552 will be least confusing to the rest of the compiler. */
7553 else if (mode == BImode)
7555 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7559 /* If X is known to be either 0 or -1, those are the true and
7560 false values when testing X. */
7561 else if (x == constm1_rtx || x == const0_rtx
7562 || (mode != VOIDmode
7563 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7565 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7569 /* Likewise for 0 or a single bit. */
7570 else if (SCALAR_INT_MODE_P (mode)
7571 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7572 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7574 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7578 /* Otherwise fail; show no condition with true and false values the same. */
7579 *ptrue = *pfalse = x;
7583 /* Return the value of expression X given the fact that condition COND
7584 is known to be true when applied to REG as its first operand and VAL
7585 as its second. X is known to not be shared and so can be modified in
7588 We only handle the simplest cases, and specifically those cases that
7589 arise with IF_THEN_ELSE expressions. */
7592 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7594 enum rtx_code code = GET_CODE (x);
7599 if (side_effects_p (x))
7602 /* If either operand of the condition is a floating point value,
7603 then we have to avoid collapsing an EQ comparison. */
7605 && rtx_equal_p (x, reg)
7606 && ! FLOAT_MODE_P (GET_MODE (x))
7607 && ! FLOAT_MODE_P (GET_MODE (val)))
7610 if (cond == UNEQ && rtx_equal_p (x, reg))
7613 /* If X is (abs REG) and we know something about REG's relationship
7614 with zero, we may be able to simplify this. */
7616 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7619 case GE: case GT: case EQ:
7622 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7624 GET_MODE (XEXP (x, 0)));
7629 /* The only other cases we handle are MIN, MAX, and comparisons if the
7630 operands are the same as REG and VAL. */
7632 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7634 if (rtx_equal_p (XEXP (x, 0), val))
7635 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7637 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7639 if (COMPARISON_P (x))
7641 if (comparison_dominates_p (cond, code))
7642 return const_true_rtx;
7644 code = reversed_comparison_code (x, NULL);
7646 && comparison_dominates_p (cond, code))
7651 else if (code == SMAX || code == SMIN
7652 || code == UMIN || code == UMAX)
7654 int unsignedp = (code == UMIN || code == UMAX);
7656 /* Do not reverse the condition when it is NE or EQ.
7657 This is because we cannot conclude anything about
7658 the value of 'SMAX (x, y)' when x is not equal to y,
7659 but we can when x equals y. */
7660 if ((code == SMAX || code == UMAX)
7661 && ! (cond == EQ || cond == NE))
7662 cond = reverse_condition (cond);
7667 return unsignedp ? x : XEXP (x, 1);
7669 return unsignedp ? x : XEXP (x, 0);
7671 return unsignedp ? XEXP (x, 1) : x;
7673 return unsignedp ? XEXP (x, 0) : x;
7680 else if (code == SUBREG)
7682 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7683 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7685 if (SUBREG_REG (x) != r)
7687 /* We must simplify subreg here, before we lose track of the
7688 original inner_mode. */
7689 new = simplify_subreg (GET_MODE (x), r,
7690 inner_mode, SUBREG_BYTE (x));
7694 SUBST (SUBREG_REG (x), r);
7699 /* We don't have to handle SIGN_EXTEND here, because even in the
7700 case of replacing something with a modeless CONST_INT, a
7701 CONST_INT is already (supposed to be) a valid sign extension for
7702 its narrower mode, which implies it's already properly
7703 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7704 story is different. */
7705 else if (code == ZERO_EXTEND)
7707 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7708 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7710 if (XEXP (x, 0) != r)
7712 /* We must simplify the zero_extend here, before we lose
7713 track of the original inner_mode. */
7714 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7719 SUBST (XEXP (x, 0), r);
7725 fmt = GET_RTX_FORMAT (code);
7726 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7729 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7730 else if (fmt[i] == 'E')
7731 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7732 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7739 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7740 assignment as a field assignment. */
7743 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7745 if (x == y || rtx_equal_p (x, y))
7748 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7751 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7752 Note that all SUBREGs of MEM are paradoxical; otherwise they
7753 would have been rewritten. */
7754 if (MEM_P (x) && GET_CODE (y) == SUBREG
7755 && MEM_P (SUBREG_REG (y))
7756 && rtx_equal_p (SUBREG_REG (y),
7757 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7760 if (MEM_P (y) && GET_CODE (x) == SUBREG
7761 && MEM_P (SUBREG_REG (x))
7762 && rtx_equal_p (SUBREG_REG (x),
7763 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7766 /* We used to see if get_last_value of X and Y were the same but that's
7767 not correct. In one direction, we'll cause the assignment to have
7768 the wrong destination and in the case, we'll import a register into this
7769 insn that might have already have been dead. So fail if none of the
7770 above cases are true. */
7774 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7775 Return that assignment if so.
7777 We only handle the most common cases. */
7780 make_field_assignment (rtx x)
7782 rtx dest = SET_DEST (x);
7783 rtx src = SET_SRC (x);
7788 unsigned HOST_WIDE_INT len;
7790 enum machine_mode mode;
7792 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7793 a clear of a one-bit field. We will have changed it to
7794 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7797 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7798 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7799 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7800 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7802 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7805 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7809 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7810 && subreg_lowpart_p (XEXP (src, 0))
7811 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7812 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7813 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7814 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7815 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7816 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7818 assign = make_extraction (VOIDmode, dest, 0,
7819 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7822 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7826 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7828 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7829 && XEXP (XEXP (src, 0), 0) == const1_rtx
7830 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7832 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7835 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7839 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7840 SRC is an AND with all bits of that field set, then we can discard
7842 if (GET_CODE (dest) == ZERO_EXTRACT
7843 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7844 && GET_CODE (src) == AND
7845 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7847 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7848 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7849 unsigned HOST_WIDE_INT ze_mask;
7851 if (width >= HOST_BITS_PER_WIDE_INT)
7854 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7856 /* Complete overlap. We can remove the source AND. */
7857 if ((and_mask & ze_mask) == ze_mask)
7858 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7860 /* Partial overlap. We can reduce the source AND. */
7861 if ((and_mask & ze_mask) != and_mask)
7863 mode = GET_MODE (src);
7864 src = gen_rtx_AND (mode, XEXP (src, 0),
7865 gen_int_mode (and_mask & ze_mask, mode));
7866 return gen_rtx_SET (VOIDmode, dest, src);
7870 /* The other case we handle is assignments into a constant-position
7871 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7872 a mask that has all one bits except for a group of zero bits and
7873 OTHER is known to have zeros where C1 has ones, this is such an
7874 assignment. Compute the position and length from C1. Shift OTHER
7875 to the appropriate position, force it to the required mode, and
7876 make the extraction. Check for the AND in both operands. */
7878 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7881 rhs = expand_compound_operation (XEXP (src, 0));
7882 lhs = expand_compound_operation (XEXP (src, 1));
7884 if (GET_CODE (rhs) == AND
7885 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7886 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7887 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7888 else if (GET_CODE (lhs) == AND
7889 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7890 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7891 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7895 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7896 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7897 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7898 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7901 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7905 /* The mode to use for the source is the mode of the assignment, or of
7906 what is inside a possible STRICT_LOW_PART. */
7907 mode = (GET_CODE (assign) == STRICT_LOW_PART
7908 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7910 /* Shift OTHER right POS places and make it the source, restricting it
7911 to the proper length and mode. */
7913 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7914 GET_MODE (src), other, pos),
7916 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7917 ? ~(unsigned HOST_WIDE_INT) 0
7918 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7921 /* If SRC is masked by an AND that does not make a difference in
7922 the value being stored, strip it. */
7923 if (GET_CODE (assign) == ZERO_EXTRACT
7924 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7925 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7926 && GET_CODE (src) == AND
7927 && GET_CODE (XEXP (src, 1)) == CONST_INT
7928 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7929 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7930 src = XEXP (src, 0);
7932 return gen_rtx_SET (VOIDmode, assign, src);
7935 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7939 apply_distributive_law (rtx x)
7941 enum rtx_code code = GET_CODE (x);
7942 enum rtx_code inner_code;
7943 rtx lhs, rhs, other;
7946 /* Distributivity is not true for floating point as it can change the
7947 value. So we don't do it unless -funsafe-math-optimizations. */
7948 if (FLOAT_MODE_P (GET_MODE (x))
7949 && ! flag_unsafe_math_optimizations)
7952 /* The outer operation can only be one of the following: */
7953 if (code != IOR && code != AND && code != XOR
7954 && code != PLUS && code != MINUS)
7960 /* If either operand is a primitive we can't do anything, so get out
7962 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7965 lhs = expand_compound_operation (lhs);
7966 rhs = expand_compound_operation (rhs);
7967 inner_code = GET_CODE (lhs);
7968 if (inner_code != GET_CODE (rhs))
7971 /* See if the inner and outer operations distribute. */
7978 /* These all distribute except over PLUS. */
7979 if (code == PLUS || code == MINUS)
7984 if (code != PLUS && code != MINUS)
7989 /* This is also a multiply, so it distributes over everything. */
7993 /* Non-paradoxical SUBREGs distributes over all operations, provided
7994 the inner modes and byte offsets are the same, this is an extraction
7995 of a low-order part, we don't convert an fp operation to int or
7996 vice versa, and we would not be converting a single-word
7997 operation into a multi-word operation. The latter test is not
7998 required, but it prevents generating unneeded multi-word operations.
7999 Some of the previous tests are redundant given the latter test, but
8000 are retained because they are required for correctness.
8002 We produce the result slightly differently in this case. */
8004 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8005 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8006 || ! subreg_lowpart_p (lhs)
8007 || (GET_MODE_CLASS (GET_MODE (lhs))
8008 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8009 || (GET_MODE_SIZE (GET_MODE (lhs))
8010 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8011 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
8014 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8015 SUBREG_REG (lhs), SUBREG_REG (rhs));
8016 return gen_lowpart (GET_MODE (x), tem);
8022 /* Set LHS and RHS to the inner operands (A and B in the example
8023 above) and set OTHER to the common operand (C in the example).
8024 There is only one way to do this unless the inner operation is
8026 if (COMMUTATIVE_ARITH_P (lhs)
8027 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8028 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8029 else if (COMMUTATIVE_ARITH_P (lhs)
8030 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8031 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8032 else if (COMMUTATIVE_ARITH_P (lhs)
8033 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8034 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8035 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8036 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8040 /* Form the new inner operation, seeing if it simplifies first. */
8041 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8043 /* There is one exception to the general way of distributing:
8044 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8045 if (code == XOR && inner_code == IOR)
8048 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8051 /* We may be able to continuing distributing the result, so call
8052 ourselves recursively on the inner operation before forming the
8053 outer operation, which we return. */
8054 return simplify_gen_binary (inner_code, GET_MODE (x),
8055 apply_distributive_law (tem), other);
8058 /* See if X is of the form (* (+ A B) C), and if so convert to
8059 (+ (* A C) (* B C)) and try to simplify.
8061 Most of the time, this results in no change. However, if some of
8062 the operands are the same or inverses of each other, simplifications
8065 For example, (and (ior A B) (not B)) can occur as the result of
8066 expanding a bit field assignment. When we apply the distributive
8067 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8068 which then simplifies to (and (A (not B))).
8070 Note that no checks happen on the validity of applying the inverse
8071 distributive law. This is pointless since we can do it in the
8072 few places where this routine is called.
8074 N is the index of the term that is decomposed (the arithmetic operation,
8075 i.e. (+ A B) in the first example above). !N is the index of the term that
8076 is distributed, i.e. of C in the first example above. */
8078 distribute_and_simplify_rtx (rtx x, int n)
8080 enum machine_mode mode;
8081 enum rtx_code outer_code, inner_code;
8082 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8084 decomposed = XEXP (x, n);
8085 if (!ARITHMETIC_P (decomposed))
8088 mode = GET_MODE (x);
8089 outer_code = GET_CODE (x);
8090 distributed = XEXP (x, !n);
8092 inner_code = GET_CODE (decomposed);
8093 inner_op0 = XEXP (decomposed, 0);
8094 inner_op1 = XEXP (decomposed, 1);
8096 /* Special case (and (xor B C) (not A)), which is equivalent to
8097 (xor (ior A B) (ior A C)) */
8098 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8100 distributed = XEXP (distributed, 0);
8106 /* Distribute the second term. */
8107 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8108 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8112 /* Distribute the first term. */
8113 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8114 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8117 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8119 if (GET_CODE (tmp) != outer_code
8120 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8126 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8129 Return an equivalent form, if different from X. Otherwise, return X. If
8130 X is zero, we are to always construct the equivalent form. */
8133 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8134 unsigned HOST_WIDE_INT constop)
8136 unsigned HOST_WIDE_INT nonzero;
8139 /* Simplify VAROP knowing that we will be only looking at some of the
8142 Note by passing in CONSTOP, we guarantee that the bits not set in
8143 CONSTOP are not significant and will never be examined. We must
8144 ensure that is the case by explicitly masking out those bits
8145 before returning. */
8146 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8148 /* If VAROP is a CLOBBER, we will fail so return it. */
8149 if (GET_CODE (varop) == CLOBBER)
8152 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8153 to VAROP and return the new constant. */
8154 if (GET_CODE (varop) == CONST_INT)
8155 return gen_int_mode (INTVAL (varop) & constop, mode);
8157 /* See what bits may be nonzero in VAROP. Unlike the general case of
8158 a call to nonzero_bits, here we don't care about bits outside
8161 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8163 /* Turn off all bits in the constant that are known to already be zero.
8164 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8165 which is tested below. */
8169 /* If we don't have any bits left, return zero. */
8173 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8174 a power of two, we can replace this with an ASHIFT. */
8175 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8176 && (i = exact_log2 (constop)) >= 0)
8177 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8179 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8180 or XOR, then try to apply the distributive law. This may eliminate
8181 operations if either branch can be simplified because of the AND.
8182 It may also make some cases more complex, but those cases probably
8183 won't match a pattern either with or without this. */
8185 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8189 apply_distributive_law
8190 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8191 simplify_and_const_int (NULL_RTX,
8195 simplify_and_const_int (NULL_RTX,
8200 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8201 the AND and see if one of the operands simplifies to zero. If so, we
8202 may eliminate it. */
8204 if (GET_CODE (varop) == PLUS
8205 && exact_log2 (constop + 1) >= 0)
8209 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8210 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8211 if (o0 == const0_rtx)
8213 if (o1 == const0_rtx)
8217 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8218 if we already had one (just check for the simplest cases). */
8219 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8220 && GET_MODE (XEXP (x, 0)) == mode
8221 && SUBREG_REG (XEXP (x, 0)) == varop)
8222 varop = XEXP (x, 0);
8224 varop = gen_lowpart (mode, varop);
8226 /* If we can't make the SUBREG, try to return what we were given. */
8227 if (GET_CODE (varop) == CLOBBER)
8228 return x ? x : varop;
8230 /* If we are only masking insignificant bits, return VAROP. */
8231 if (constop == nonzero)
8235 /* Otherwise, return an AND. */
8236 constop = trunc_int_for_mode (constop, mode);
8237 /* See how much, if any, of X we can use. */
8238 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8239 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
8243 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8244 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8245 SUBST (XEXP (x, 1), GEN_INT (constop));
8247 SUBST (XEXP (x, 0), varop);
8254 /* Given a REG, X, compute which bits in X can be nonzero.
8255 We don't care about bits outside of those defined in MODE.
8257 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8258 a shift, AND, or zero_extract, we can do better. */
8261 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8262 rtx known_x ATTRIBUTE_UNUSED,
8263 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8264 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8265 unsigned HOST_WIDE_INT *nonzero)
8269 /* If X is a register whose nonzero bits value is current, use it.
8270 Otherwise, if X is a register whose value we can find, use that
8271 value. Otherwise, use the previously-computed global nonzero bits
8272 for this register. */
8274 if (reg_stat[REGNO (x)].last_set_value != 0
8275 && (reg_stat[REGNO (x)].last_set_mode == mode
8276 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8277 && GET_MODE_CLASS (mode) == MODE_INT))
8278 && (reg_stat[REGNO (x)].last_set_label == label_tick
8279 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8280 && REG_N_SETS (REGNO (x)) == 1
8281 && ! REGNO_REG_SET_P
8282 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8284 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8286 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8290 tem = get_last_value (x);
8294 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8295 /* If X is narrower than MODE and TEM is a non-negative
8296 constant that would appear negative in the mode of X,
8297 sign-extend it for use in reg_nonzero_bits because some
8298 machines (maybe most) will actually do the sign-extension
8299 and this is the conservative approach.
8301 ??? For 2.5, try to tighten up the MD files in this regard
8302 instead of this kludge. */
8304 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8305 && GET_CODE (tem) == CONST_INT
8307 && 0 != (INTVAL (tem)
8308 & ((HOST_WIDE_INT) 1
8309 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8310 tem = GEN_INT (INTVAL (tem)
8311 | ((HOST_WIDE_INT) (-1)
8312 << GET_MODE_BITSIZE (GET_MODE (x))));
8316 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8318 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8320 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8321 /* We don't know anything about the upper bits. */
8322 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8329 /* Return the number of bits at the high-order end of X that are known to
8330 be equal to the sign bit. X will be used in mode MODE; if MODE is
8331 VOIDmode, X will be used in its own mode. The returned value will always
8332 be between 1 and the number of bits in MODE. */
8335 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8336 rtx known_x ATTRIBUTE_UNUSED,
8337 enum machine_mode known_mode
8339 unsigned int known_ret ATTRIBUTE_UNUSED,
8340 unsigned int *result)
8344 if (reg_stat[REGNO (x)].last_set_value != 0
8345 && reg_stat[REGNO (x)].last_set_mode == mode
8346 && (reg_stat[REGNO (x)].last_set_label == label_tick
8347 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8348 && REG_N_SETS (REGNO (x)) == 1
8349 && ! REGNO_REG_SET_P
8350 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8352 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8354 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8358 tem = get_last_value (x);
8362 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8363 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8364 *result = reg_stat[REGNO (x)].sign_bit_copies;
8369 /* Return the number of "extended" bits there are in X, when interpreted
8370 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8371 unsigned quantities, this is the number of high-order zero bits.
8372 For signed quantities, this is the number of copies of the sign bit
8373 minus 1. In both case, this function returns the number of "spare"
8374 bits. For example, if two quantities for which this function returns
8375 at least 1 are added, the addition is known not to overflow.
8377 This function will always return 0 unless called during combine, which
8378 implies that it must be called from a define_split. */
8381 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8383 if (nonzero_sign_valid == 0)
8387 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8388 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8389 - floor_log2 (nonzero_bits (x, mode)))
8391 : num_sign_bit_copies (x, mode) - 1);
8394 /* This function is called from `simplify_shift_const' to merge two
8395 outer operations. Specifically, we have already found that we need
8396 to perform operation *POP0 with constant *PCONST0 at the outermost
8397 position. We would now like to also perform OP1 with constant CONST1
8398 (with *POP0 being done last).
8400 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8401 the resulting operation. *PCOMP_P is set to 1 if we would need to
8402 complement the innermost operand, otherwise it is unchanged.
8404 MODE is the mode in which the operation will be done. No bits outside
8405 the width of this mode matter. It is assumed that the width of this mode
8406 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8408 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8409 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8410 result is simply *PCONST0.
8412 If the resulting operation cannot be expressed as one operation, we
8413 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8416 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8418 enum rtx_code op0 = *pop0;
8419 HOST_WIDE_INT const0 = *pconst0;
8421 const0 &= GET_MODE_MASK (mode);
8422 const1 &= GET_MODE_MASK (mode);
8424 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8428 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8431 if (op1 == UNKNOWN || op0 == SET)
8434 else if (op0 == UNKNOWN)
8435 op0 = op1, const0 = const1;
8437 else if (op0 == op1)
8461 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8462 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8465 /* If the two constants aren't the same, we can't do anything. The
8466 remaining six cases can all be done. */
8467 else if (const0 != const1)
8475 /* (a & b) | b == b */
8477 else /* op1 == XOR */
8478 /* (a ^ b) | b == a | b */
8484 /* (a & b) ^ b == (~a) & b */
8485 op0 = AND, *pcomp_p = 1;
8486 else /* op1 == IOR */
8487 /* (a | b) ^ b == a & ~b */
8488 op0 = AND, const0 = ~const0;
8493 /* (a | b) & b == b */
8495 else /* op1 == XOR */
8496 /* (a ^ b) & b) == (~a) & b */
8503 /* Check for NO-OP cases. */
8504 const0 &= GET_MODE_MASK (mode);
8506 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8508 else if (const0 == 0 && op0 == AND)
8510 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8514 /* ??? Slightly redundant with the above mask, but not entirely.
8515 Moving this above means we'd have to sign-extend the mode mask
8516 for the final test. */
8517 const0 = trunc_int_for_mode (const0, mode);
8525 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8526 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8527 that we started with.
8529 The shift is normally computed in the widest mode we find in VAROP, as
8530 long as it isn't a different number of words than RESULT_MODE. Exceptions
8531 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8534 simplify_shift_const (rtx x, enum rtx_code code,
8535 enum machine_mode result_mode, rtx varop,
8538 enum rtx_code orig_code = code;
8541 enum machine_mode mode = result_mode;
8542 enum machine_mode shift_mode, tmode;
8543 unsigned int mode_words
8544 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8545 /* We form (outer_op (code varop count) (outer_const)). */
8546 enum rtx_code outer_op = UNKNOWN;
8547 HOST_WIDE_INT outer_const = 0;
8549 int complement_p = 0;
8552 /* Make sure and truncate the "natural" shift on the way in. We don't
8553 want to do this inside the loop as it makes it more difficult to
8555 if (SHIFT_COUNT_TRUNCATED)
8556 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8558 /* If we were given an invalid count, don't do anything except exactly
8559 what was requested. */
8561 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8566 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8571 /* Unless one of the branches of the `if' in this loop does a `continue',
8572 we will `break' the loop after the `if'. */
8576 /* If we have an operand of (clobber (const_int 0)), just return that
8578 if (GET_CODE (varop) == CLOBBER)
8581 /* If we discovered we had to complement VAROP, leave. Making a NOT
8582 here would cause an infinite loop. */
8586 /* Convert ROTATERT to ROTATE. */
8587 if (code == ROTATERT)
8589 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8591 if (VECTOR_MODE_P (result_mode))
8592 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8594 count = bitsize - count;
8597 /* We need to determine what mode we will do the shift in. If the
8598 shift is a right shift or a ROTATE, we must always do it in the mode
8599 it was originally done in. Otherwise, we can do it in MODE, the
8600 widest mode encountered. */
8602 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8603 ? result_mode : mode);
8605 /* Handle cases where the count is greater than the size of the mode
8606 minus 1. For ASHIFT, use the size minus one as the count (this can
8607 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8608 take the count modulo the size. For other shifts, the result is
8611 Since these shifts are being produced by the compiler by combining
8612 multiple operations, each of which are defined, we know what the
8613 result is supposed to be. */
8615 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8617 if (code == ASHIFTRT)
8618 count = GET_MODE_BITSIZE (shift_mode) - 1;
8619 else if (code == ROTATE || code == ROTATERT)
8620 count %= GET_MODE_BITSIZE (shift_mode);
8623 /* We can't simply return zero because there may be an
8631 /* An arithmetic right shift of a quantity known to be -1 or 0
8633 if (code == ASHIFTRT
8634 && (num_sign_bit_copies (varop, shift_mode)
8635 == GET_MODE_BITSIZE (shift_mode)))
8641 /* If we are doing an arithmetic right shift and discarding all but
8642 the sign bit copies, this is equivalent to doing a shift by the
8643 bitsize minus one. Convert it into that shift because it will often
8644 allow other simplifications. */
8646 if (code == ASHIFTRT
8647 && (count + num_sign_bit_copies (varop, shift_mode)
8648 >= GET_MODE_BITSIZE (shift_mode)))
8649 count = GET_MODE_BITSIZE (shift_mode) - 1;
8651 /* We simplify the tests below and elsewhere by converting
8652 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8653 `make_compound_operation' will convert it to an ASHIFTRT for
8654 those machines (such as VAX) that don't have an LSHIFTRT. */
8655 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8657 && ((nonzero_bits (varop, shift_mode)
8658 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8662 if (code == LSHIFTRT
8663 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8664 && !(nonzero_bits (varop, shift_mode) >> count))
8667 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8668 && !((nonzero_bits (varop, shift_mode) << count)
8669 & GET_MODE_MASK (shift_mode)))
8672 switch (GET_CODE (varop))
8678 new = expand_compound_operation (varop);
8687 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8688 minus the width of a smaller mode, we can do this with a
8689 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8690 if ((code == ASHIFTRT || code == LSHIFTRT)
8691 && ! mode_dependent_address_p (XEXP (varop, 0))
8692 && ! MEM_VOLATILE_P (varop)
8693 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8694 MODE_INT, 1)) != BLKmode)
8696 new = adjust_address_nv (varop, tmode,
8697 BYTES_BIG_ENDIAN ? 0
8698 : count / BITS_PER_UNIT);
8700 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8701 : ZERO_EXTEND, mode, new);
8708 /* Similar to the case above, except that we can only do this if
8709 the resulting mode is the same as that of the underlying
8710 MEM and adjust the address depending on the *bits* endianness
8711 because of the way that bit-field extract insns are defined. */
8712 if ((code == ASHIFTRT || code == LSHIFTRT)
8713 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8714 MODE_INT, 1)) != BLKmode
8715 && tmode == GET_MODE (XEXP (varop, 0)))
8717 if (BITS_BIG_ENDIAN)
8718 new = XEXP (varop, 0);
8721 new = copy_rtx (XEXP (varop, 0));
8722 SUBST (XEXP (new, 0),
8723 plus_constant (XEXP (new, 0),
8724 count / BITS_PER_UNIT));
8727 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8728 : ZERO_EXTEND, mode, new);
8735 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8736 the same number of words as what we've seen so far. Then store
8737 the widest mode in MODE. */
8738 if (subreg_lowpart_p (varop)
8739 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8740 > GET_MODE_SIZE (GET_MODE (varop)))
8741 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8742 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8745 varop = SUBREG_REG (varop);
8746 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8747 mode = GET_MODE (varop);
8753 /* Some machines use MULT instead of ASHIFT because MULT
8754 is cheaper. But it is still better on those machines to
8755 merge two shifts into one. */
8756 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8757 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8760 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8762 GEN_INT (exact_log2 (
8763 INTVAL (XEXP (varop, 1)))));
8769 /* Similar, for when divides are cheaper. */
8770 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8771 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8774 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8776 GEN_INT (exact_log2 (
8777 INTVAL (XEXP (varop, 1)))));
8783 /* If we are extracting just the sign bit of an arithmetic
8784 right shift, that shift is not needed. However, the sign
8785 bit of a wider mode may be different from what would be
8786 interpreted as the sign bit in a narrower mode, so, if
8787 the result is narrower, don't discard the shift. */
8788 if (code == LSHIFTRT
8789 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8790 && (GET_MODE_BITSIZE (result_mode)
8791 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8793 varop = XEXP (varop, 0);
8797 /* ... fall through ... */
8802 /* Here we have two nested shifts. The result is usually the
8803 AND of a new shift with a mask. We compute the result below. */
8804 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8805 && INTVAL (XEXP (varop, 1)) >= 0
8806 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8807 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8808 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8810 enum rtx_code first_code = GET_CODE (varop);
8811 unsigned int first_count = INTVAL (XEXP (varop, 1));
8812 unsigned HOST_WIDE_INT mask;
8815 /* We have one common special case. We can't do any merging if
8816 the inner code is an ASHIFTRT of a smaller mode. However, if
8817 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8818 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8819 we can convert it to
8820 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8821 This simplifies certain SIGN_EXTEND operations. */
8822 if (code == ASHIFT && first_code == ASHIFTRT
8823 && count == (unsigned int)
8824 (GET_MODE_BITSIZE (result_mode)
8825 - GET_MODE_BITSIZE (GET_MODE (varop))))
8827 /* C3 has the low-order C1 bits zero. */
8829 mask = (GET_MODE_MASK (mode)
8830 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8832 varop = simplify_and_const_int (NULL_RTX, result_mode,
8833 XEXP (varop, 0), mask);
8834 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8836 count = first_count;
8841 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8842 than C1 high-order bits equal to the sign bit, we can convert
8843 this to either an ASHIFT or an ASHIFTRT depending on the
8846 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8848 if (code == ASHIFTRT && first_code == ASHIFT
8849 && GET_MODE (varop) == shift_mode
8850 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8853 varop = XEXP (varop, 0);
8855 signed_count = count - first_count;
8856 if (signed_count < 0)
8857 count = -signed_count, code = ASHIFT;
8859 count = signed_count;
8864 /* There are some cases we can't do. If CODE is ASHIFTRT,
8865 we can only do this if FIRST_CODE is also ASHIFTRT.
8867 We can't do the case when CODE is ROTATE and FIRST_CODE is
8870 If the mode of this shift is not the mode of the outer shift,
8871 we can't do this if either shift is a right shift or ROTATE.
8873 Finally, we can't do any of these if the mode is too wide
8874 unless the codes are the same.
8876 Handle the case where the shift codes are the same
8879 if (code == first_code)
8881 if (GET_MODE (varop) != result_mode
8882 && (code == ASHIFTRT || code == LSHIFTRT
8886 count += first_count;
8887 varop = XEXP (varop, 0);
8891 if (code == ASHIFTRT
8892 || (code == ROTATE && first_code == ASHIFTRT)
8893 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8894 || (GET_MODE (varop) != result_mode
8895 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8896 || first_code == ROTATE
8897 || code == ROTATE)))
8900 /* To compute the mask to apply after the shift, shift the
8901 nonzero bits of the inner shift the same way the
8902 outer shift will. */
8904 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8907 = simplify_binary_operation (code, result_mode, mask_rtx,
8910 /* Give up if we can't compute an outer operation to use. */
8912 || GET_CODE (mask_rtx) != CONST_INT
8913 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8915 result_mode, &complement_p))
8918 /* If the shifts are in the same direction, we add the
8919 counts. Otherwise, we subtract them. */
8920 signed_count = count;
8921 if ((code == ASHIFTRT || code == LSHIFTRT)
8922 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8923 signed_count += first_count;
8925 signed_count -= first_count;
8927 /* If COUNT is positive, the new shift is usually CODE,
8928 except for the two exceptions below, in which case it is
8929 FIRST_CODE. If the count is negative, FIRST_CODE should
8931 if (signed_count > 0
8932 && ((first_code == ROTATE && code == ASHIFT)
8933 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8934 code = first_code, count = signed_count;
8935 else if (signed_count < 0)
8936 code = first_code, count = -signed_count;
8938 count = signed_count;
8940 varop = XEXP (varop, 0);
8944 /* If we have (A << B << C) for any shift, we can convert this to
8945 (A << C << B). This wins if A is a constant. Only try this if
8946 B is not a constant. */
8948 else if (GET_CODE (varop) == code
8949 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8951 = simplify_binary_operation (code, mode,
8955 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8962 /* Make this fit the case below. */
8963 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8964 GEN_INT (GET_MODE_MASK (mode)));
8970 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8971 with C the size of VAROP - 1 and the shift is logical if
8972 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8973 we have an (le X 0) operation. If we have an arithmetic shift
8974 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8975 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8977 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8978 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8979 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8980 && (code == LSHIFTRT || code == ASHIFTRT)
8981 && count == (unsigned int)
8982 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8983 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8986 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8989 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8990 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8995 /* If we have (shift (logical)), move the logical to the outside
8996 to allow it to possibly combine with another logical and the
8997 shift to combine with another shift. This also canonicalizes to
8998 what a ZERO_EXTRACT looks like. Also, some machines have
8999 (and (shift)) insns. */
9001 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9002 /* We can't do this if we have (ashiftrt (xor)) and the
9003 constant has its sign bit set in shift_mode. */
9004 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9005 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9007 && (new = simplify_binary_operation (code, result_mode,
9009 GEN_INT (count))) != 0
9010 && GET_CODE (new) == CONST_INT
9011 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9012 INTVAL (new), result_mode, &complement_p))
9014 varop = XEXP (varop, 0);
9018 /* If we can't do that, try to simplify the shift in each arm of the
9019 logical expression, make a new logical expression, and apply
9020 the inverse distributive law. This also can't be done
9021 for some (ashiftrt (xor)). */
9022 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9023 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9024 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9027 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9028 XEXP (varop, 0), count);
9029 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9030 XEXP (varop, 1), count);
9032 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9034 varop = apply_distributive_law (varop);
9042 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9043 says that the sign bit can be tested, FOO has mode MODE, C is
9044 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9045 that may be nonzero. */
9046 if (code == LSHIFTRT
9047 && XEXP (varop, 1) == const0_rtx
9048 && GET_MODE (XEXP (varop, 0)) == result_mode
9049 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9050 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9051 && ((STORE_FLAG_VALUE
9052 & ((HOST_WIDE_INT) 1
9053 < (GET_MODE_BITSIZE (result_mode) - 1))))
9054 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9055 && merge_outer_ops (&outer_op, &outer_const, XOR,
9056 (HOST_WIDE_INT) 1, result_mode,
9059 varop = XEXP (varop, 0);
9066 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9067 than the number of bits in the mode is equivalent to A. */
9068 if (code == LSHIFTRT
9069 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9070 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9072 varop = XEXP (varop, 0);
9077 /* NEG commutes with ASHIFT since it is multiplication. Move the
9078 NEG outside to allow shifts to combine. */
9080 && merge_outer_ops (&outer_op, &outer_const, NEG,
9081 (HOST_WIDE_INT) 0, result_mode,
9084 varop = XEXP (varop, 0);
9090 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9091 is one less than the number of bits in the mode is
9092 equivalent to (xor A 1). */
9093 if (code == LSHIFTRT
9094 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
9095 && XEXP (varop, 1) == constm1_rtx
9096 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9097 && merge_outer_ops (&outer_op, &outer_const, XOR,
9098 (HOST_WIDE_INT) 1, result_mode,
9102 varop = XEXP (varop, 0);
9106 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9107 that might be nonzero in BAR are those being shifted out and those
9108 bits are known zero in FOO, we can replace the PLUS with FOO.
9109 Similarly in the other operand order. This code occurs when
9110 we are computing the size of a variable-size array. */
9112 if ((code == ASHIFTRT || code == LSHIFTRT)
9113 && count < HOST_BITS_PER_WIDE_INT
9114 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9115 && (nonzero_bits (XEXP (varop, 1), result_mode)
9116 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9118 varop = XEXP (varop, 0);
9121 else if ((code == ASHIFTRT || code == LSHIFTRT)
9122 && count < HOST_BITS_PER_WIDE_INT
9123 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9124 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9126 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9127 & nonzero_bits (XEXP (varop, 1),
9130 varop = XEXP (varop, 1);
9134 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9136 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9137 && (new = simplify_binary_operation (ASHIFT, result_mode,
9139 GEN_INT (count))) != 0
9140 && GET_CODE (new) == CONST_INT
9141 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9142 INTVAL (new), result_mode, &complement_p))
9144 varop = XEXP (varop, 0);
9148 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9149 signbit', and attempt to change the PLUS to an XOR and move it to
9150 the outer operation as is done above in the AND/IOR/XOR case
9151 leg for shift(logical). See details in logical handling above
9152 for reasoning in doing so. */
9153 if (code == LSHIFTRT
9154 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9155 && mode_signbit_p (result_mode, XEXP (varop, 1))
9156 && (new = simplify_binary_operation (code, result_mode,
9158 GEN_INT (count))) != 0
9159 && GET_CODE (new) == CONST_INT
9160 && merge_outer_ops (&outer_op, &outer_const, XOR,
9161 INTVAL (new), result_mode, &complement_p))
9163 varop = XEXP (varop, 0);
9170 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9171 with C the size of VAROP - 1 and the shift is logical if
9172 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9173 we have a (gt X 0) operation. If the shift is arithmetic with
9174 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9175 we have a (neg (gt X 0)) operation. */
9177 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9178 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9179 && count == (unsigned int)
9180 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9181 && (code == LSHIFTRT || code == ASHIFTRT)
9182 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9183 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9185 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9188 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9191 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9192 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9199 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9200 if the truncate does not affect the value. */
9201 if (code == LSHIFTRT
9202 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9203 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9204 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9205 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9206 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9208 rtx varop_inner = XEXP (varop, 0);
9211 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9212 XEXP (varop_inner, 0),
9214 (count + INTVAL (XEXP (varop_inner, 1))));
9215 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9228 /* We need to determine what mode to do the shift in. If the shift is
9229 a right shift or ROTATE, we must always do it in the mode it was
9230 originally done in. Otherwise, we can do it in MODE, the widest mode
9231 encountered. The code we care about is that of the shift that will
9232 actually be done, not the shift that was originally requested. */
9234 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9235 ? result_mode : mode);
9237 /* We have now finished analyzing the shift. The result should be
9238 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9239 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9240 to the result of the shift. OUTER_CONST is the relevant constant,
9241 but we must turn off all bits turned off in the shift.
9243 If we were passed a value for X, see if we can use any pieces of
9244 it. If not, make new rtx. */
9246 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9247 && GET_CODE (XEXP (x, 1)) == CONST_INT
9248 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9249 const_rtx = XEXP (x, 1);
9251 const_rtx = GEN_INT (count);
9253 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9254 && GET_MODE (XEXP (x, 0)) == shift_mode
9255 && SUBREG_REG (XEXP (x, 0)) == varop)
9256 varop = XEXP (x, 0);
9257 else if (GET_MODE (varop) != shift_mode)
9258 varop = gen_lowpart (shift_mode, varop);
9260 /* If we can't make the SUBREG, try to return what we were given. */
9261 if (GET_CODE (varop) == CLOBBER)
9262 return x ? x : varop;
9264 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9268 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9270 /* If we have an outer operation and we just made a shift, it is
9271 possible that we could have simplified the shift were it not
9272 for the outer operation. So try to do the simplification
9275 if (outer_op != UNKNOWN && GET_CODE (x) == code
9276 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9277 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9278 INTVAL (XEXP (x, 1)));
9280 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9281 turn off all the bits that the shift would have turned off. */
9282 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9283 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9284 GET_MODE_MASK (result_mode) >> orig_count);
9286 /* Do the remainder of the processing in RESULT_MODE. */
9287 x = gen_lowpart (result_mode, x);
9289 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9292 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9294 if (outer_op != UNKNOWN)
9296 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9297 outer_const = trunc_int_for_mode (outer_const, result_mode);
9299 if (outer_op == AND)
9300 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9301 else if (outer_op == SET)
9302 /* This means that we have determined that the result is
9303 equivalent to a constant. This should be rare. */
9304 x = GEN_INT (outer_const);
9305 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9306 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9308 x = simplify_gen_binary (outer_op, result_mode, x,
9309 GEN_INT (outer_const));
9315 /* Like recog, but we receive the address of a pointer to a new pattern.
9316 We try to match the rtx that the pointer points to.
9317 If that fails, we may try to modify or replace the pattern,
9318 storing the replacement into the same pointer object.
9320 Modifications include deletion or addition of CLOBBERs.
9322 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9323 the CLOBBERs are placed.
9325 The value is the final insn code from the pattern ultimately matched,
9329 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9332 int insn_code_number;
9333 int num_clobbers_to_add = 0;
9336 rtx old_notes, old_pat;
9338 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9339 we use to indicate that something didn't match. If we find such a
9340 thing, force rejection. */
9341 if (GET_CODE (pat) == PARALLEL)
9342 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9343 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9344 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9347 old_pat = PATTERN (insn);
9348 old_notes = REG_NOTES (insn);
9349 PATTERN (insn) = pat;
9350 REG_NOTES (insn) = 0;
9352 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9354 /* If it isn't, there is the possibility that we previously had an insn
9355 that clobbered some register as a side effect, but the combined
9356 insn doesn't need to do that. So try once more without the clobbers
9357 unless this represents an ASM insn. */
9359 if (insn_code_number < 0 && ! check_asm_operands (pat)
9360 && GET_CODE (pat) == PARALLEL)
9364 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9365 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9368 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9372 SUBST_INT (XVECLEN (pat, 0), pos);
9375 pat = XVECEXP (pat, 0, 0);
9377 PATTERN (insn) = pat;
9378 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9380 PATTERN (insn) = old_pat;
9381 REG_NOTES (insn) = old_notes;
9383 /* Recognize all noop sets, these will be killed by followup pass. */
9384 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9385 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9387 /* If we had any clobbers to add, make a new pattern than contains
9388 them. Then check to make sure that all of them are dead. */
9389 if (num_clobbers_to_add)
9391 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9392 rtvec_alloc (GET_CODE (pat) == PARALLEL
9394 + num_clobbers_to_add)
9395 : num_clobbers_to_add + 1));
9397 if (GET_CODE (pat) == PARALLEL)
9398 for (i = 0; i < XVECLEN (pat, 0); i++)
9399 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9401 XVECEXP (newpat, 0, 0) = pat;
9403 add_clobbers (newpat, insn_code_number);
9405 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9406 i < XVECLEN (newpat, 0); i++)
9408 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9409 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9411 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9412 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9420 return insn_code_number;
9423 /* Like gen_lowpart_general but for use by combine. In combine it
9424 is not possible to create any new pseudoregs. However, it is
9425 safe to create invalid memory addresses, because combine will
9426 try to recognize them and all they will do is make the combine
9429 If for some reason this cannot do its job, an rtx
9430 (clobber (const_int 0)) is returned.
9431 An insn containing that will not be recognized. */
9434 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9436 enum machine_mode imode = GET_MODE (x);
9437 unsigned int osize = GET_MODE_SIZE (omode);
9438 unsigned int isize = GET_MODE_SIZE (imode);
9444 /* Return identity if this is a CONST or symbolic reference. */
9446 && (GET_CODE (x) == CONST
9447 || GET_CODE (x) == SYMBOL_REF
9448 || GET_CODE (x) == LABEL_REF))
9451 /* We can only support MODE being wider than a word if X is a
9452 constant integer or has a mode the same size. */
9453 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9454 && ! ((imode == VOIDmode
9455 && (GET_CODE (x) == CONST_INT
9456 || GET_CODE (x) == CONST_DOUBLE))
9460 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9461 won't know what to do. So we will strip off the SUBREG here and
9462 process normally. */
9463 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9467 /* For use in case we fall down into the address adjustments
9468 further below, we need to adjust the known mode and size of
9469 x; imode and isize, since we just adjusted x. */
9470 imode = GET_MODE (x);
9475 isize = GET_MODE_SIZE (imode);
9478 result = gen_lowpart_common (omode, x);
9480 #ifdef CANNOT_CHANGE_MODE_CLASS
9481 if (result != 0 && GET_CODE (result) == SUBREG)
9482 record_subregs_of_mode (result);
9492 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9494 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9497 /* If we want to refer to something bigger than the original memref,
9498 generate a paradoxical subreg instead. That will force a reload
9499 of the original memref X. */
9501 return gen_rtx_SUBREG (omode, x, 0);
9503 if (WORDS_BIG_ENDIAN)
9504 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9506 /* Adjust the address so that the address-after-the-data is
9508 if (BYTES_BIG_ENDIAN)
9509 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9511 return adjust_address_nv (x, omode, offset);
9514 /* If X is a comparison operator, rewrite it in a new mode. This
9515 probably won't match, but may allow further simplifications. */
9516 else if (COMPARISON_P (x))
9517 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9519 /* If we couldn't simplify X any other way, just enclose it in a
9520 SUBREG. Normally, this SUBREG won't match, but some patterns may
9521 include an explicit SUBREG or we may simplify it further in combine. */
9527 offset = subreg_lowpart_offset (omode, imode);
9528 if (imode == VOIDmode)
9530 imode = int_mode_for_mode (omode);
9531 x = gen_lowpart_common (imode, x);
9535 res = simplify_gen_subreg (omode, x, imode, offset);
9541 return gen_rtx_CLOBBER (imode, const0_rtx);
9544 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9545 comparison code that will be tested.
9547 The result is a possibly different comparison code to use. *POP0 and
9548 *POP1 may be updated.
9550 It is possible that we might detect that a comparison is either always
9551 true or always false. However, we do not perform general constant
9552 folding in combine, so this knowledge isn't useful. Such tautologies
9553 should have been detected earlier. Hence we ignore all such cases. */
9555 static enum rtx_code
9556 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9562 enum machine_mode mode, tmode;
9564 /* Try a few ways of applying the same transformation to both operands. */
9567 #ifndef WORD_REGISTER_OPERATIONS
9568 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9569 so check specially. */
9570 if (code != GTU && code != GEU && code != LTU && code != LEU
9571 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9572 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9573 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9574 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9575 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9576 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9577 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9578 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9579 && XEXP (op0, 1) == XEXP (op1, 1)
9580 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9581 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9582 && (INTVAL (XEXP (op0, 1))
9583 == (GET_MODE_BITSIZE (GET_MODE (op0))
9585 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9587 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9588 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9592 /* If both operands are the same constant shift, see if we can ignore the
9593 shift. We can if the shift is a rotate or if the bits shifted out of
9594 this shift are known to be zero for both inputs and if the type of
9595 comparison is compatible with the shift. */
9596 if (GET_CODE (op0) == GET_CODE (op1)
9597 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9598 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9599 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9600 && (code != GT && code != LT && code != GE && code != LE))
9601 || (GET_CODE (op0) == ASHIFTRT
9602 && (code != GTU && code != LTU
9603 && code != GEU && code != LEU)))
9604 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9605 && INTVAL (XEXP (op0, 1)) >= 0
9606 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9607 && XEXP (op0, 1) == XEXP (op1, 1))
9609 enum machine_mode mode = GET_MODE (op0);
9610 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9611 int shift_count = INTVAL (XEXP (op0, 1));
9613 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9614 mask &= (mask >> shift_count) << shift_count;
9615 else if (GET_CODE (op0) == ASHIFT)
9616 mask = (mask & (mask << shift_count)) >> shift_count;
9618 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9619 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9620 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9625 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9626 SUBREGs are of the same mode, and, in both cases, the AND would
9627 be redundant if the comparison was done in the narrower mode,
9628 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9629 and the operand's possibly nonzero bits are 0xffffff01; in that case
9630 if we only care about QImode, we don't need the AND). This case
9631 occurs if the output mode of an scc insn is not SImode and
9632 STORE_FLAG_VALUE == 1 (e.g., the 386).
9634 Similarly, check for a case where the AND's are ZERO_EXTEND
9635 operations from some narrower mode even though a SUBREG is not
9638 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9639 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9640 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9642 rtx inner_op0 = XEXP (op0, 0);
9643 rtx inner_op1 = XEXP (op1, 0);
9644 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9645 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9648 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9649 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9650 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9651 && (GET_MODE (SUBREG_REG (inner_op0))
9652 == GET_MODE (SUBREG_REG (inner_op1)))
9653 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9654 <= HOST_BITS_PER_WIDE_INT)
9655 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9656 GET_MODE (SUBREG_REG (inner_op0)))))
9657 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9658 GET_MODE (SUBREG_REG (inner_op1))))))
9660 op0 = SUBREG_REG (inner_op0);
9661 op1 = SUBREG_REG (inner_op1);
9663 /* The resulting comparison is always unsigned since we masked
9664 off the original sign bit. */
9665 code = unsigned_condition (code);
9671 for (tmode = GET_CLASS_NARROWEST_MODE
9672 (GET_MODE_CLASS (GET_MODE (op0)));
9673 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9674 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9676 op0 = gen_lowpart (tmode, inner_op0);
9677 op1 = gen_lowpart (tmode, inner_op1);
9678 code = unsigned_condition (code);
9687 /* If both operands are NOT, we can strip off the outer operation
9688 and adjust the comparison code for swapped operands; similarly for
9689 NEG, except that this must be an equality comparison. */
9690 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9691 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9692 && (code == EQ || code == NE)))
9693 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9699 /* If the first operand is a constant, swap the operands and adjust the
9700 comparison code appropriately, but don't do this if the second operand
9701 is already a constant integer. */
9702 if (swap_commutative_operands_p (op0, op1))
9704 tem = op0, op0 = op1, op1 = tem;
9705 code = swap_condition (code);
9708 /* We now enter a loop during which we will try to simplify the comparison.
9709 For the most part, we only are concerned with comparisons with zero,
9710 but some things may really be comparisons with zero but not start
9711 out looking that way. */
9713 while (GET_CODE (op1) == CONST_INT)
9715 enum machine_mode mode = GET_MODE (op0);
9716 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9717 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9718 int equality_comparison_p;
9719 int sign_bit_comparison_p;
9720 int unsigned_comparison_p;
9721 HOST_WIDE_INT const_op;
9723 /* We only want to handle integral modes. This catches VOIDmode,
9724 CCmode, and the floating-point modes. An exception is that we
9725 can handle VOIDmode if OP0 is a COMPARE or a comparison
9728 if (GET_MODE_CLASS (mode) != MODE_INT
9729 && ! (mode == VOIDmode
9730 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9733 /* Get the constant we are comparing against and turn off all bits
9734 not on in our mode. */
9735 const_op = INTVAL (op1);
9736 if (mode != VOIDmode)
9737 const_op = trunc_int_for_mode (const_op, mode);
9738 op1 = GEN_INT (const_op);
9740 /* If we are comparing against a constant power of two and the value
9741 being compared can only have that single bit nonzero (e.g., it was
9742 `and'ed with that bit), we can replace this with a comparison
9745 && (code == EQ || code == NE || code == GE || code == GEU
9746 || code == LT || code == LTU)
9747 && mode_width <= HOST_BITS_PER_WIDE_INT
9748 && exact_log2 (const_op) >= 0
9749 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9751 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9752 op1 = const0_rtx, const_op = 0;
9755 /* Similarly, if we are comparing a value known to be either -1 or
9756 0 with -1, change it to the opposite comparison against zero. */
9759 && (code == EQ || code == NE || code == GT || code == LE
9760 || code == GEU || code == LTU)
9761 && num_sign_bit_copies (op0, mode) == mode_width)
9763 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9764 op1 = const0_rtx, const_op = 0;
9767 /* Do some canonicalizations based on the comparison code. We prefer
9768 comparisons against zero and then prefer equality comparisons.
9769 If we can reduce the size of a constant, we will do that too. */
9774 /* < C is equivalent to <= (C - 1) */
9778 op1 = GEN_INT (const_op);
9780 /* ... fall through to LE case below. */
9786 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9790 op1 = GEN_INT (const_op);
9794 /* If we are doing a <= 0 comparison on a value known to have
9795 a zero sign bit, we can replace this with == 0. */
9796 else if (const_op == 0
9797 && mode_width <= HOST_BITS_PER_WIDE_INT
9798 && (nonzero_bits (op0, mode)
9799 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9804 /* >= C is equivalent to > (C - 1). */
9808 op1 = GEN_INT (const_op);
9810 /* ... fall through to GT below. */
9816 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9820 op1 = GEN_INT (const_op);
9824 /* If we are doing a > 0 comparison on a value known to have
9825 a zero sign bit, we can replace this with != 0. */
9826 else if (const_op == 0
9827 && mode_width <= HOST_BITS_PER_WIDE_INT
9828 && (nonzero_bits (op0, mode)
9829 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9834 /* < C is equivalent to <= (C - 1). */
9838 op1 = GEN_INT (const_op);
9840 /* ... fall through ... */
9843 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9844 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9845 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9847 const_op = 0, op1 = const0_rtx;
9855 /* unsigned <= 0 is equivalent to == 0 */
9859 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9860 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9861 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9863 const_op = 0, op1 = const0_rtx;
9869 /* >= C is equivalent to > (C - 1). */
9873 op1 = GEN_INT (const_op);
9875 /* ... fall through ... */
9878 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9879 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9880 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9882 const_op = 0, op1 = const0_rtx;
9890 /* unsigned > 0 is equivalent to != 0 */
9894 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9895 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9896 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9898 const_op = 0, op1 = const0_rtx;
9907 /* Compute some predicates to simplify code below. */
9909 equality_comparison_p = (code == EQ || code == NE);
9910 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9911 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9914 /* If this is a sign bit comparison and we can do arithmetic in
9915 MODE, say that we will only be needing the sign bit of OP0. */
9916 if (sign_bit_comparison_p
9917 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9918 op0 = force_to_mode (op0, mode,
9920 << (GET_MODE_BITSIZE (mode) - 1)),
9923 /* Now try cases based on the opcode of OP0. If none of the cases
9924 does a "continue", we exit this loop immediately after the
9927 switch (GET_CODE (op0))
9930 /* If we are extracting a single bit from a variable position in
9931 a constant that has only a single bit set and are comparing it
9932 with zero, we can convert this into an equality comparison
9933 between the position and the location of the single bit. */
9934 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9935 have already reduced the shift count modulo the word size. */
9936 if (!SHIFT_COUNT_TRUNCATED
9937 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9938 && XEXP (op0, 1) == const1_rtx
9939 && equality_comparison_p && const_op == 0
9940 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9942 if (BITS_BIG_ENDIAN)
9944 enum machine_mode new_mode
9945 = mode_for_extraction (EP_extzv, 1);
9946 if (new_mode == MAX_MACHINE_MODE)
9947 i = BITS_PER_WORD - 1 - i;
9951 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9955 op0 = XEXP (op0, 2);
9959 /* Result is nonzero iff shift count is equal to I. */
9960 code = reverse_condition (code);
9964 /* ... fall through ... */
9967 tem = expand_compound_operation (op0);
9976 /* If testing for equality, we can take the NOT of the constant. */
9977 if (equality_comparison_p
9978 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9980 op0 = XEXP (op0, 0);
9985 /* If just looking at the sign bit, reverse the sense of the
9987 if (sign_bit_comparison_p)
9989 op0 = XEXP (op0, 0);
9990 code = (code == GE ? LT : GE);
9996 /* If testing for equality, we can take the NEG of the constant. */
9997 if (equality_comparison_p
9998 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10000 op0 = XEXP (op0, 0);
10005 /* The remaining cases only apply to comparisons with zero. */
10009 /* When X is ABS or is known positive,
10010 (neg X) is < 0 if and only if X != 0. */
10012 if (sign_bit_comparison_p
10013 && (GET_CODE (XEXP (op0, 0)) == ABS
10014 || (mode_width <= HOST_BITS_PER_WIDE_INT
10015 && (nonzero_bits (XEXP (op0, 0), mode)
10016 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10018 op0 = XEXP (op0, 0);
10019 code = (code == LT ? NE : EQ);
10023 /* If we have NEG of something whose two high-order bits are the
10024 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10025 if (num_sign_bit_copies (op0, mode) >= 2)
10027 op0 = XEXP (op0, 0);
10028 code = swap_condition (code);
10034 /* If we are testing equality and our count is a constant, we
10035 can perform the inverse operation on our RHS. */
10036 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10037 && (tem = simplify_binary_operation (ROTATERT, mode,
10038 op1, XEXP (op0, 1))) != 0)
10040 op0 = XEXP (op0, 0);
10045 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10046 a particular bit. Convert it to an AND of a constant of that
10047 bit. This will be converted into a ZERO_EXTRACT. */
10048 if (const_op == 0 && sign_bit_comparison_p
10049 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10050 && mode_width <= HOST_BITS_PER_WIDE_INT)
10052 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10055 - INTVAL (XEXP (op0, 1)))));
10056 code = (code == LT ? NE : EQ);
10060 /* Fall through. */
10063 /* ABS is ignorable inside an equality comparison with zero. */
10064 if (const_op == 0 && equality_comparison_p)
10066 op0 = XEXP (op0, 0);
10072 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10073 (compare FOO CONST) if CONST fits in FOO's mode and we
10074 are either testing inequality or have an unsigned
10075 comparison with ZERO_EXTEND or a signed comparison with
10076 SIGN_EXTEND. But don't do it if we don't have a compare
10077 insn of the given mode, since we'd have to revert it
10078 later on, and then we wouldn't know whether to sign- or
10080 mode = GET_MODE (XEXP (op0, 0));
10081 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10082 && ! unsigned_comparison_p
10083 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10084 && ((unsigned HOST_WIDE_INT) const_op
10085 < (((unsigned HOST_WIDE_INT) 1
10086 << (GET_MODE_BITSIZE (mode) - 1))))
10087 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10089 op0 = XEXP (op0, 0);
10095 /* Check for the case where we are comparing A - C1 with C2, that is
10097 (subreg:MODE (plus (A) (-C1))) op (C2)
10099 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10100 comparison in the wider mode. One of the following two conditions
10101 must be true in order for this to be valid:
10103 1. The mode extension results in the same bit pattern being added
10104 on both sides and the comparison is equality or unsigned. As
10105 C2 has been truncated to fit in MODE, the pattern can only be
10108 2. The mode extension results in the sign bit being copied on
10111 The difficulty here is that we have predicates for A but not for
10112 (A - C1) so we need to check that C1 is within proper bounds so
10113 as to perturbate A as little as possible. */
10115 if (mode_width <= HOST_BITS_PER_WIDE_INT
10116 && subreg_lowpart_p (op0)
10117 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10118 && GET_CODE (SUBREG_REG (op0)) == PLUS
10119 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10121 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10122 rtx a = XEXP (SUBREG_REG (op0), 0);
10123 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10126 && (unsigned HOST_WIDE_INT) c1
10127 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10128 && (equality_comparison_p || unsigned_comparison_p)
10129 /* (A - C1) zero-extends if it is positive and sign-extends
10130 if it is negative, C2 both zero- and sign-extends. */
10131 && ((0 == (nonzero_bits (a, inner_mode)
10132 & ~GET_MODE_MASK (mode))
10134 /* (A - C1) sign-extends if it is positive and 1-extends
10135 if it is negative, C2 both sign- and 1-extends. */
10136 || (num_sign_bit_copies (a, inner_mode)
10137 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10140 || ((unsigned HOST_WIDE_INT) c1
10141 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10142 /* (A - C1) always sign-extends, like C2. */
10143 && num_sign_bit_copies (a, inner_mode)
10144 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10145 - mode_width - 1)))
10147 op0 = SUBREG_REG (op0);
10152 /* If the inner mode is narrower and we are extracting the low part,
10153 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10154 if (subreg_lowpart_p (op0)
10155 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10156 /* Fall through */ ;
10160 /* ... fall through ... */
10163 mode = GET_MODE (XEXP (op0, 0));
10164 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10165 && (unsigned_comparison_p || equality_comparison_p)
10166 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10167 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10168 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
10170 op0 = XEXP (op0, 0);
10176 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10177 this for equality comparisons due to pathological cases involving
10179 if (equality_comparison_p
10180 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10181 op1, XEXP (op0, 1))))
10183 op0 = XEXP (op0, 0);
10188 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10189 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10190 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10192 op0 = XEXP (XEXP (op0, 0), 0);
10193 code = (code == LT ? EQ : NE);
10199 /* We used to optimize signed comparisons against zero, but that
10200 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10201 arrive here as equality comparisons, or (GEU, LTU) are
10202 optimized away. No need to special-case them. */
10204 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10205 (eq B (minus A C)), whichever simplifies. We can only do
10206 this for equality comparisons due to pathological cases involving
10208 if (equality_comparison_p
10209 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10210 XEXP (op0, 1), op1)))
10212 op0 = XEXP (op0, 0);
10217 if (equality_comparison_p
10218 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10219 XEXP (op0, 0), op1)))
10221 op0 = XEXP (op0, 1);
10226 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10227 of bits in X minus 1, is one iff X > 0. */
10228 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10229 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10230 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10232 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10234 op0 = XEXP (op0, 1);
10235 code = (code == GE ? LE : GT);
10241 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10242 if C is zero or B is a constant. */
10243 if (equality_comparison_p
10244 && 0 != (tem = simplify_binary_operation (XOR, mode,
10245 XEXP (op0, 1), op1)))
10247 op0 = XEXP (op0, 0);
10254 case UNEQ: case LTGT:
10255 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10256 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10257 case UNORDERED: case ORDERED:
10258 /* We can't do anything if OP0 is a condition code value, rather
10259 than an actual data value. */
10261 || CC0_P (XEXP (op0, 0))
10262 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10265 /* Get the two operands being compared. */
10266 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10267 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10269 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10271 /* Check for the cases where we simply want the result of the
10272 earlier test or the opposite of that result. */
10273 if (code == NE || code == EQ
10274 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10275 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10276 && (STORE_FLAG_VALUE
10277 & (((HOST_WIDE_INT) 1
10278 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10279 && (code == LT || code == GE)))
10281 enum rtx_code new_code;
10282 if (code == LT || code == NE)
10283 new_code = GET_CODE (op0);
10285 new_code = reversed_comparison_code (op0, NULL);
10287 if (new_code != UNKNOWN)
10298 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10300 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10301 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10302 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10304 op0 = XEXP (op0, 1);
10305 code = (code == GE ? GT : LE);
10311 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10312 will be converted to a ZERO_EXTRACT later. */
10313 if (const_op == 0 && equality_comparison_p
10314 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10315 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10317 op0 = simplify_and_const_int
10318 (op0, mode, gen_rtx_LSHIFTRT (mode,
10320 XEXP (XEXP (op0, 0), 1)),
10321 (HOST_WIDE_INT) 1);
10325 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10326 zero and X is a comparison and C1 and C2 describe only bits set
10327 in STORE_FLAG_VALUE, we can compare with X. */
10328 if (const_op == 0 && equality_comparison_p
10329 && mode_width <= HOST_BITS_PER_WIDE_INT
10330 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10331 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10332 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10333 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10334 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10336 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10337 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10338 if ((~STORE_FLAG_VALUE & mask) == 0
10339 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10340 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10341 && COMPARISON_P (tem))))
10343 op0 = XEXP (XEXP (op0, 0), 0);
10348 /* If we are doing an equality comparison of an AND of a bit equal
10349 to the sign bit, replace this with a LT or GE comparison of
10350 the underlying value. */
10351 if (equality_comparison_p
10353 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10354 && mode_width <= HOST_BITS_PER_WIDE_INT
10355 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10356 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10358 op0 = XEXP (op0, 0);
10359 code = (code == EQ ? GE : LT);
10363 /* If this AND operation is really a ZERO_EXTEND from a narrower
10364 mode, the constant fits within that mode, and this is either an
10365 equality or unsigned comparison, try to do this comparison in
10366 the narrower mode. */
10367 if ((equality_comparison_p || unsigned_comparison_p)
10368 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10369 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10370 & GET_MODE_MASK (mode))
10372 && const_op >> i == 0
10373 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10375 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10379 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10380 fits in both M1 and M2 and the SUBREG is either paradoxical
10381 or represents the low part, permute the SUBREG and the AND
10383 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10385 unsigned HOST_WIDE_INT c1;
10386 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10387 /* Require an integral mode, to avoid creating something like
10389 if (SCALAR_INT_MODE_P (tmode)
10390 /* It is unsafe to commute the AND into the SUBREG if the
10391 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10392 not defined. As originally written the upper bits
10393 have a defined value due to the AND operation.
10394 However, if we commute the AND inside the SUBREG then
10395 they no longer have defined values and the meaning of
10396 the code has been changed. */
10398 #ifdef WORD_REGISTER_OPERATIONS
10399 || (mode_width > GET_MODE_BITSIZE (tmode)
10400 && mode_width <= BITS_PER_WORD)
10402 || (mode_width <= GET_MODE_BITSIZE (tmode)
10403 && subreg_lowpart_p (XEXP (op0, 0))))
10404 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10405 && mode_width <= HOST_BITS_PER_WIDE_INT
10406 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10407 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10408 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10410 && c1 != GET_MODE_MASK (tmode))
10412 op0 = simplify_gen_binary (AND, tmode,
10413 SUBREG_REG (XEXP (op0, 0)),
10414 gen_int_mode (c1, tmode));
10415 op0 = gen_lowpart (mode, op0);
10420 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10421 if (const_op == 0 && equality_comparison_p
10422 && XEXP (op0, 1) == const1_rtx
10423 && GET_CODE (XEXP (op0, 0)) == NOT)
10425 op0 = simplify_and_const_int
10426 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10427 code = (code == NE ? EQ : NE);
10431 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10432 (eq (and (lshiftrt X) 1) 0).
10433 Also handle the case where (not X) is expressed using xor. */
10434 if (const_op == 0 && equality_comparison_p
10435 && XEXP (op0, 1) == const1_rtx
10436 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10438 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10439 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10441 if (GET_CODE (shift_op) == NOT
10442 || (GET_CODE (shift_op) == XOR
10443 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10444 && GET_CODE (shift_count) == CONST_INT
10445 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10446 && (INTVAL (XEXP (shift_op, 1))
10447 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10449 op0 = simplify_and_const_int
10451 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10452 (HOST_WIDE_INT) 1);
10453 code = (code == NE ? EQ : NE);
10460 /* If we have (compare (ashift FOO N) (const_int C)) and
10461 the high order N bits of FOO (N+1 if an inequality comparison)
10462 are known to be zero, we can do this by comparing FOO with C
10463 shifted right N bits so long as the low-order N bits of C are
10465 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10466 && INTVAL (XEXP (op0, 1)) >= 0
10467 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10468 < HOST_BITS_PER_WIDE_INT)
10470 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10471 && mode_width <= HOST_BITS_PER_WIDE_INT
10472 && (nonzero_bits (XEXP (op0, 0), mode)
10473 & ~(mask >> (INTVAL (XEXP (op0, 1))
10474 + ! equality_comparison_p))) == 0)
10476 /* We must perform a logical shift, not an arithmetic one,
10477 as we want the top N bits of C to be zero. */
10478 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10480 temp >>= INTVAL (XEXP (op0, 1));
10481 op1 = gen_int_mode (temp, mode);
10482 op0 = XEXP (op0, 0);
10486 /* If we are doing a sign bit comparison, it means we are testing
10487 a particular bit. Convert it to the appropriate AND. */
10488 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10489 && mode_width <= HOST_BITS_PER_WIDE_INT)
10491 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10494 - INTVAL (XEXP (op0, 1)))));
10495 code = (code == LT ? NE : EQ);
10499 /* If this an equality comparison with zero and we are shifting
10500 the low bit to the sign bit, we can convert this to an AND of the
10502 if (const_op == 0 && equality_comparison_p
10503 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10504 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10507 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10508 (HOST_WIDE_INT) 1);
10514 /* If this is an equality comparison with zero, we can do this
10515 as a logical shift, which might be much simpler. */
10516 if (equality_comparison_p && const_op == 0
10517 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10519 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10521 INTVAL (XEXP (op0, 1)));
10525 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10526 do the comparison in a narrower mode. */
10527 if (! unsigned_comparison_p
10528 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10529 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10530 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10531 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10532 MODE_INT, 1)) != BLKmode
10533 && (((unsigned HOST_WIDE_INT) const_op
10534 + (GET_MODE_MASK (tmode) >> 1) + 1)
10535 <= GET_MODE_MASK (tmode)))
10537 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10541 /* Likewise if OP0 is a PLUS of a sign extension with a
10542 constant, which is usually represented with the PLUS
10543 between the shifts. */
10544 if (! unsigned_comparison_p
10545 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10546 && GET_CODE (XEXP (op0, 0)) == PLUS
10547 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10548 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10549 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10550 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10551 MODE_INT, 1)) != BLKmode
10552 && (((unsigned HOST_WIDE_INT) const_op
10553 + (GET_MODE_MASK (tmode) >> 1) + 1)
10554 <= GET_MODE_MASK (tmode)))
10556 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10557 rtx add_const = XEXP (XEXP (op0, 0), 1);
10558 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10559 add_const, XEXP (op0, 1));
10561 op0 = simplify_gen_binary (PLUS, tmode,
10562 gen_lowpart (tmode, inner),
10567 /* ... fall through ... */
10569 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10570 the low order N bits of FOO are known to be zero, we can do this
10571 by comparing FOO with C shifted left N bits so long as no
10572 overflow occurs. */
10573 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10574 && INTVAL (XEXP (op0, 1)) >= 0
10575 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10576 && mode_width <= HOST_BITS_PER_WIDE_INT
10577 && (nonzero_bits (XEXP (op0, 0), mode)
10578 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10579 && (((unsigned HOST_WIDE_INT) const_op
10580 + (GET_CODE (op0) != LSHIFTRT
10581 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10584 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10586 /* If the shift was logical, then we must make the condition
10588 if (GET_CODE (op0) == LSHIFTRT)
10589 code = unsigned_condition (code);
10591 const_op <<= INTVAL (XEXP (op0, 1));
10592 op1 = GEN_INT (const_op);
10593 op0 = XEXP (op0, 0);
10597 /* If we are using this shift to extract just the sign bit, we
10598 can replace this with an LT or GE comparison. */
10600 && (equality_comparison_p || sign_bit_comparison_p)
10601 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10602 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10605 op0 = XEXP (op0, 0);
10606 code = (code == NE || code == GT ? LT : GE);
10618 /* Now make any compound operations involved in this comparison. Then,
10619 check for an outmost SUBREG on OP0 that is not doing anything or is
10620 paradoxical. The latter transformation must only be performed when
10621 it is known that the "extra" bits will be the same in op0 and op1 or
10622 that they don't matter. There are three cases to consider:
10624 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10625 care bits and we can assume they have any convenient value. So
10626 making the transformation is safe.
10628 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10629 In this case the upper bits of op0 are undefined. We should not make
10630 the simplification in that case as we do not know the contents of
10633 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10634 UNKNOWN. In that case we know those bits are zeros or ones. We must
10635 also be sure that they are the same as the upper bits of op1.
10637 We can never remove a SUBREG for a non-equality comparison because
10638 the sign bit is in a different place in the underlying object. */
10640 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10641 op1 = make_compound_operation (op1, SET);
10643 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10644 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10645 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10646 && (code == NE || code == EQ))
10648 if (GET_MODE_SIZE (GET_MODE (op0))
10649 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10651 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10653 if (REG_P (SUBREG_REG (op0)))
10655 op0 = SUBREG_REG (op0);
10656 op1 = gen_lowpart (GET_MODE (op0), op1);
10659 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10660 <= HOST_BITS_PER_WIDE_INT)
10661 && (nonzero_bits (SUBREG_REG (op0),
10662 GET_MODE (SUBREG_REG (op0)))
10663 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10665 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10667 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10668 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10669 op0 = SUBREG_REG (op0), op1 = tem;
10673 /* We now do the opposite procedure: Some machines don't have compare
10674 insns in all modes. If OP0's mode is an integer mode smaller than a
10675 word and we can't do a compare in that mode, see if there is a larger
10676 mode for which we can do the compare. There are a number of cases in
10677 which we can use the wider mode. */
10679 mode = GET_MODE (op0);
10680 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10681 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10682 && ! have_insn_for (COMPARE, mode))
10683 for (tmode = GET_MODE_WIDER_MODE (mode);
10685 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10686 tmode = GET_MODE_WIDER_MODE (tmode))
10687 if (have_insn_for (COMPARE, tmode))
10691 /* If the only nonzero bits in OP0 and OP1 are those in the
10692 narrower mode and this is an equality or unsigned comparison,
10693 we can use the wider mode. Similarly for sign-extended
10694 values, in which case it is true for all comparisons. */
10695 zero_extended = ((code == EQ || code == NE
10696 || code == GEU || code == GTU
10697 || code == LEU || code == LTU)
10698 && (nonzero_bits (op0, tmode)
10699 & ~GET_MODE_MASK (mode)) == 0
10700 && ((GET_CODE (op1) == CONST_INT
10701 || (nonzero_bits (op1, tmode)
10702 & ~GET_MODE_MASK (mode)) == 0)));
10705 || ((num_sign_bit_copies (op0, tmode)
10706 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10707 - GET_MODE_BITSIZE (mode)))
10708 && (num_sign_bit_copies (op1, tmode)
10709 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10710 - GET_MODE_BITSIZE (mode)))))
10712 /* If OP0 is an AND and we don't have an AND in MODE either,
10713 make a new AND in the proper mode. */
10714 if (GET_CODE (op0) == AND
10715 && !have_insn_for (AND, mode))
10716 op0 = simplify_gen_binary (AND, tmode,
10717 gen_lowpart (tmode,
10719 gen_lowpart (tmode,
10722 op0 = gen_lowpart (tmode, op0);
10723 if (zero_extended && GET_CODE (op1) == CONST_INT)
10724 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10725 op1 = gen_lowpart (tmode, op1);
10729 /* If this is a test for negative, we can make an explicit
10730 test of the sign bit. */
10732 if (op1 == const0_rtx && (code == LT || code == GE)
10733 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10735 op0 = simplify_gen_binary (AND, tmode,
10736 gen_lowpart (tmode, op0),
10737 GEN_INT ((HOST_WIDE_INT) 1
10738 << (GET_MODE_BITSIZE (mode)
10740 code = (code == LT) ? NE : EQ;
10745 #ifdef CANONICALIZE_COMPARISON
10746 /* If this machine only supports a subset of valid comparisons, see if we
10747 can convert an unsupported one into a supported one. */
10748 CANONICALIZE_COMPARISON (code, op0, op1);
10757 /* Utility function for record_value_for_reg. Count number of
10762 enum rtx_code code = GET_CODE (x);
10766 if (GET_RTX_CLASS (code) == '2'
10767 || GET_RTX_CLASS (code) == 'c')
10769 rtx x0 = XEXP (x, 0);
10770 rtx x1 = XEXP (x, 1);
10773 return 1 + 2 * count_rtxs (x0);
10775 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10776 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10777 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10778 return 2 + 2 * count_rtxs (x0)
10779 + count_rtxs (x == XEXP (x1, 0)
10780 ? XEXP (x1, 1) : XEXP (x1, 0));
10782 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10783 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10784 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10785 return 2 + 2 * count_rtxs (x1)
10786 + count_rtxs (x == XEXP (x0, 0)
10787 ? XEXP (x0, 1) : XEXP (x0, 0));
10790 fmt = GET_RTX_FORMAT (code);
10791 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10793 ret += count_rtxs (XEXP (x, i));
10798 /* Utility function for following routine. Called when X is part of a value
10799 being stored into last_set_value. Sets last_set_table_tick
10800 for each register mentioned. Similar to mention_regs in cse.c */
10803 update_table_tick (rtx x)
10805 enum rtx_code code = GET_CODE (x);
10806 const char *fmt = GET_RTX_FORMAT (code);
10811 unsigned int regno = REGNO (x);
10812 unsigned int endregno
10813 = regno + (regno < FIRST_PSEUDO_REGISTER
10814 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10817 for (r = regno; r < endregno; r++)
10818 reg_stat[r].last_set_table_tick = label_tick;
10823 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10824 /* Note that we can't have an "E" in values stored; see
10825 get_last_value_validate. */
10828 /* Check for identical subexpressions. If x contains
10829 identical subexpression we only have to traverse one of
10831 if (i == 0 && ARITHMETIC_P (x))
10833 /* Note that at this point x1 has already been
10835 rtx x0 = XEXP (x, 0);
10836 rtx x1 = XEXP (x, 1);
10838 /* If x0 and x1 are identical then there is no need to
10843 /* If x0 is identical to a subexpression of x1 then while
10844 processing x1, x0 has already been processed. Thus we
10845 are done with x. */
10846 if (ARITHMETIC_P (x1)
10847 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10850 /* If x1 is identical to a subexpression of x0 then we
10851 still have to process the rest of x0. */
10852 if (ARITHMETIC_P (x0)
10853 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10855 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10860 update_table_tick (XEXP (x, i));
10864 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10865 are saying that the register is clobbered and we no longer know its
10866 value. If INSN is zero, don't update reg_stat[].last_set; this is
10867 only permitted with VALUE also zero and is used to invalidate the
10871 record_value_for_reg (rtx reg, rtx insn, rtx value)
10873 unsigned int regno = REGNO (reg);
10874 unsigned int endregno
10875 = regno + (regno < FIRST_PSEUDO_REGISTER
10876 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10879 /* If VALUE contains REG and we have a previous value for REG, substitute
10880 the previous value. */
10881 if (value && insn && reg_overlap_mentioned_p (reg, value))
10885 /* Set things up so get_last_value is allowed to see anything set up to
10887 subst_low_cuid = INSN_CUID (insn);
10888 tem = get_last_value (reg);
10890 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10891 it isn't going to be useful and will take a lot of time to process,
10892 so just use the CLOBBER. */
10896 if (ARITHMETIC_P (tem)
10897 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10898 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10899 tem = XEXP (tem, 0);
10900 else if (count_occurrences (value, reg, 1) >= 2)
10902 /* If there are two or more occurrences of REG in VALUE,
10903 prevent the value from growing too much. */
10904 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10905 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10908 value = replace_rtx (copy_rtx (value), reg, tem);
10912 /* For each register modified, show we don't know its value, that
10913 we don't know about its bitwise content, that its value has been
10914 updated, and that we don't know the location of the death of the
10916 for (i = regno; i < endregno; i++)
10919 reg_stat[i].last_set = insn;
10921 reg_stat[i].last_set_value = 0;
10922 reg_stat[i].last_set_mode = 0;
10923 reg_stat[i].last_set_nonzero_bits = 0;
10924 reg_stat[i].last_set_sign_bit_copies = 0;
10925 reg_stat[i].last_death = 0;
10928 /* Mark registers that are being referenced in this value. */
10930 update_table_tick (value);
10932 /* Now update the status of each register being set.
10933 If someone is using this register in this block, set this register
10934 to invalid since we will get confused between the two lives in this
10935 basic block. This makes using this register always invalid. In cse, we
10936 scan the table to invalidate all entries using this register, but this
10937 is too much work for us. */
10939 for (i = regno; i < endregno; i++)
10941 reg_stat[i].last_set_label = label_tick;
10942 if (value && reg_stat[i].last_set_table_tick == label_tick)
10943 reg_stat[i].last_set_invalid = 1;
10945 reg_stat[i].last_set_invalid = 0;
10948 /* The value being assigned might refer to X (like in "x++;"). In that
10949 case, we must replace it with (clobber (const_int 0)) to prevent
10951 if (value && ! get_last_value_validate (&value, insn,
10952 reg_stat[regno].last_set_label, 0))
10954 value = copy_rtx (value);
10955 if (! get_last_value_validate (&value, insn,
10956 reg_stat[regno].last_set_label, 1))
10960 /* For the main register being modified, update the value, the mode, the
10961 nonzero bits, and the number of sign bit copies. */
10963 reg_stat[regno].last_set_value = value;
10967 enum machine_mode mode = GET_MODE (reg);
10968 subst_low_cuid = INSN_CUID (insn);
10969 reg_stat[regno].last_set_mode = mode;
10970 if (GET_MODE_CLASS (mode) == MODE_INT
10971 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10972 mode = nonzero_bits_mode;
10973 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10974 reg_stat[regno].last_set_sign_bit_copies
10975 = num_sign_bit_copies (value, GET_MODE (reg));
10979 /* Called via note_stores from record_dead_and_set_regs to handle one
10980 SET or CLOBBER in an insn. DATA is the instruction in which the
10981 set is occurring. */
10984 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10986 rtx record_dead_insn = (rtx) data;
10988 if (GET_CODE (dest) == SUBREG)
10989 dest = SUBREG_REG (dest);
10993 /* If we are setting the whole register, we know its value. Otherwise
10994 show that we don't know the value. We can handle SUBREG in
10996 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10997 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10998 else if (GET_CODE (setter) == SET
10999 && GET_CODE (SET_DEST (setter)) == SUBREG
11000 && SUBREG_REG (SET_DEST (setter)) == dest
11001 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11002 && subreg_lowpart_p (SET_DEST (setter)))
11003 record_value_for_reg (dest, record_dead_insn,
11004 gen_lowpart (GET_MODE (dest),
11005 SET_SRC (setter)));
11007 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11009 else if (MEM_P (dest)
11010 /* Ignore pushes, they clobber nothing. */
11011 && ! push_operand (dest, GET_MODE (dest)))
11012 mem_last_set = INSN_CUID (record_dead_insn);
11015 /* Update the records of when each REG was most recently set or killed
11016 for the things done by INSN. This is the last thing done in processing
11017 INSN in the combiner loop.
11019 We update reg_stat[], in particular fields last_set, last_set_value,
11020 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11021 last_death, and also the similar information mem_last_set (which insn
11022 most recently modified memory) and last_call_cuid (which insn was the
11023 most recent subroutine call). */
11026 record_dead_and_set_regs (rtx insn)
11031 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11033 if (REG_NOTE_KIND (link) == REG_DEAD
11034 && REG_P (XEXP (link, 0)))
11036 unsigned int regno = REGNO (XEXP (link, 0));
11037 unsigned int endregno
11038 = regno + (regno < FIRST_PSEUDO_REGISTER
11039 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
11042 for (i = regno; i < endregno; i++)
11043 reg_stat[i].last_death = insn;
11045 else if (REG_NOTE_KIND (link) == REG_INC)
11046 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11051 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11052 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11054 reg_stat[i].last_set_value = 0;
11055 reg_stat[i].last_set_mode = 0;
11056 reg_stat[i].last_set_nonzero_bits = 0;
11057 reg_stat[i].last_set_sign_bit_copies = 0;
11058 reg_stat[i].last_death = 0;
11061 last_call_cuid = mem_last_set = INSN_CUID (insn);
11063 /* Don't bother recording what this insn does. It might set the
11064 return value register, but we can't combine into a call
11065 pattern anyway, so there's no point trying (and it may cause
11066 a crash, if e.g. we wind up asking for last_set_value of a
11067 SUBREG of the return value register). */
11071 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11074 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11075 register present in the SUBREG, so for each such SUBREG go back and
11076 adjust nonzero and sign bit information of the registers that are
11077 known to have some zero/sign bits set.
11079 This is needed because when combine blows the SUBREGs away, the
11080 information on zero/sign bits is lost and further combines can be
11081 missed because of that. */
11084 record_promoted_value (rtx insn, rtx subreg)
11087 unsigned int regno = REGNO (SUBREG_REG (subreg));
11088 enum machine_mode mode = GET_MODE (subreg);
11090 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11093 for (links = LOG_LINKS (insn); links;)
11095 insn = XEXP (links, 0);
11096 set = single_set (insn);
11098 if (! set || !REG_P (SET_DEST (set))
11099 || REGNO (SET_DEST (set)) != regno
11100 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11102 links = XEXP (links, 1);
11106 if (reg_stat[regno].last_set == insn)
11108 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11109 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
11112 if (REG_P (SET_SRC (set)))
11114 regno = REGNO (SET_SRC (set));
11115 links = LOG_LINKS (insn);
11122 /* Scan X for promoted SUBREGs. For each one found,
11123 note what it implies to the registers used in it. */
11126 check_promoted_subreg (rtx insn, rtx x)
11128 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
11129 && REG_P (SUBREG_REG (x)))
11130 record_promoted_value (insn, x);
11133 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11136 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11140 check_promoted_subreg (insn, XEXP (x, i));
11144 if (XVEC (x, i) != 0)
11145 for (j = 0; j < XVECLEN (x, i); j++)
11146 check_promoted_subreg (insn, XVECEXP (x, i, j));
11152 /* Utility routine for the following function. Verify that all the registers
11153 mentioned in *LOC are valid when *LOC was part of a value set when
11154 label_tick == TICK. Return 0 if some are not.
11156 If REPLACE is nonzero, replace the invalid reference with
11157 (clobber (const_int 0)) and return 1. This replacement is useful because
11158 we often can get useful information about the form of a value (e.g., if
11159 it was produced by a shift that always produces -1 or 0) even though
11160 we don't know exactly what registers it was produced from. */
11163 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11166 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11167 int len = GET_RTX_LENGTH (GET_CODE (x));
11172 unsigned int regno = REGNO (x);
11173 unsigned int endregno
11174 = regno + (regno < FIRST_PSEUDO_REGISTER
11175 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11178 for (j = regno; j < endregno; j++)
11179 if (reg_stat[j].last_set_invalid
11180 /* If this is a pseudo-register that was only set once and not
11181 live at the beginning of the function, it is always valid. */
11182 || (! (regno >= FIRST_PSEUDO_REGISTER
11183 && REG_N_SETS (regno) == 1
11184 && (! REGNO_REG_SET_P
11185 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11187 && reg_stat[j].last_set_label > tick))
11190 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11196 /* If this is a memory reference, make sure that there were
11197 no stores after it that might have clobbered the value. We don't
11198 have alias info, so we assume any store invalidates it. */
11199 else if (MEM_P (x) && !MEM_READONLY_P (x)
11200 && INSN_CUID (insn) <= mem_last_set)
11203 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11207 for (i = 0; i < len; i++)
11211 /* Check for identical subexpressions. If x contains
11212 identical subexpression we only have to traverse one of
11214 if (i == 1 && ARITHMETIC_P (x))
11216 /* Note that at this point x0 has already been checked
11217 and found valid. */
11218 rtx x0 = XEXP (x, 0);
11219 rtx x1 = XEXP (x, 1);
11221 /* If x0 and x1 are identical then x is also valid. */
11225 /* If x1 is identical to a subexpression of x0 then
11226 while checking x0, x1 has already been checked. Thus
11227 it is valid and so as x. */
11228 if (ARITHMETIC_P (x0)
11229 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11232 /* If x0 is identical to a subexpression of x1 then x is
11233 valid iff the rest of x1 is valid. */
11234 if (ARITHMETIC_P (x1)
11235 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11237 get_last_value_validate (&XEXP (x1,
11238 x0 == XEXP (x1, 0) ? 1 : 0),
11239 insn, tick, replace);
11242 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11246 /* Don't bother with these. They shouldn't occur anyway. */
11247 else if (fmt[i] == 'E')
11251 /* If we haven't found a reason for it to be invalid, it is valid. */
11255 /* Get the last value assigned to X, if known. Some registers
11256 in the value may be replaced with (clobber (const_int 0)) if their value
11257 is known longer known reliably. */
11260 get_last_value (rtx x)
11262 unsigned int regno;
11265 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11266 then convert it to the desired mode. If this is a paradoxical SUBREG,
11267 we cannot predict what values the "extra" bits might have. */
11268 if (GET_CODE (x) == SUBREG
11269 && subreg_lowpart_p (x)
11270 && (GET_MODE_SIZE (GET_MODE (x))
11271 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11272 && (value = get_last_value (SUBREG_REG (x))) != 0)
11273 return gen_lowpart (GET_MODE (x), value);
11279 value = reg_stat[regno].last_set_value;
11281 /* If we don't have a value, or if it isn't for this basic block and
11282 it's either a hard register, set more than once, or it's a live
11283 at the beginning of the function, return 0.
11285 Because if it's not live at the beginning of the function then the reg
11286 is always set before being used (is never used without being set).
11287 And, if it's set only once, and it's always set before use, then all
11288 uses must have the same last value, even if it's not from this basic
11292 || (reg_stat[regno].last_set_label != label_tick
11293 && (regno < FIRST_PSEUDO_REGISTER
11294 || REG_N_SETS (regno) != 1
11295 || (REGNO_REG_SET_P
11296 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11300 /* If the value was set in a later insn than the ones we are processing,
11301 we can't use it even if the register was only set once. */
11302 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11305 /* If the value has all its registers valid, return it. */
11306 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11307 reg_stat[regno].last_set_label, 0))
11310 /* Otherwise, make a copy and replace any invalid register with
11311 (clobber (const_int 0)). If that fails for some reason, return 0. */
11313 value = copy_rtx (value);
11314 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11315 reg_stat[regno].last_set_label, 1))
11321 /* Return nonzero if expression X refers to a REG or to memory
11322 that is set in an instruction more recent than FROM_CUID. */
11325 use_crosses_set_p (rtx x, int from_cuid)
11329 enum rtx_code code = GET_CODE (x);
11333 unsigned int regno = REGNO (x);
11334 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11335 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11337 #ifdef PUSH_ROUNDING
11338 /* Don't allow uses of the stack pointer to be moved,
11339 because we don't know whether the move crosses a push insn. */
11340 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11343 for (; regno < endreg; regno++)
11344 if (reg_stat[regno].last_set
11345 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11350 if (code == MEM && mem_last_set > from_cuid)
11353 fmt = GET_RTX_FORMAT (code);
11355 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11360 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11361 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11364 else if (fmt[i] == 'e'
11365 && use_crosses_set_p (XEXP (x, i), from_cuid))
11371 /* Define three variables used for communication between the following
11374 static unsigned int reg_dead_regno, reg_dead_endregno;
11375 static int reg_dead_flag;
11377 /* Function called via note_stores from reg_dead_at_p.
11379 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11380 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11383 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11385 unsigned int regno, endregno;
11390 regno = REGNO (dest);
11391 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11392 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11394 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11395 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11398 /* Return nonzero if REG is known to be dead at INSN.
11400 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11401 referencing REG, it is dead. If we hit a SET referencing REG, it is
11402 live. Otherwise, see if it is live or dead at the start of the basic
11403 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11404 must be assumed to be always live. */
11407 reg_dead_at_p (rtx reg, rtx insn)
11412 /* Set variables for reg_dead_at_p_1. */
11413 reg_dead_regno = REGNO (reg);
11414 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11415 ? hard_regno_nregs[reg_dead_regno]
11421 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11422 we allow the machine description to decide whether use-and-clobber
11423 patterns are OK. */
11424 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11426 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11427 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11431 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11432 beginning of function. */
11433 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11434 insn = prev_nonnote_insn (insn))
11436 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11438 return reg_dead_flag == 1 ? 1 : 0;
11440 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11444 /* Get the basic block that we were in. */
11446 block = ENTRY_BLOCK_PTR->next_bb;
11449 FOR_EACH_BB (block)
11450 if (insn == BB_HEAD (block))
11453 if (block == EXIT_BLOCK_PTR)
11457 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11458 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11464 /* Note hard registers in X that are used. This code is similar to
11465 that in flow.c, but much simpler since we don't care about pseudos. */
11468 mark_used_regs_combine (rtx x)
11470 RTX_CODE code = GET_CODE (x);
11471 unsigned int regno;
11484 case ADDR_DIFF_VEC:
11487 /* CC0 must die in the insn after it is set, so we don't need to take
11488 special note of it here. */
11494 /* If we are clobbering a MEM, mark any hard registers inside the
11495 address as used. */
11496 if (MEM_P (XEXP (x, 0)))
11497 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11502 /* A hard reg in a wide mode may really be multiple registers.
11503 If so, mark all of them just like the first. */
11504 if (regno < FIRST_PSEUDO_REGISTER)
11506 unsigned int endregno, r;
11508 /* None of this applies to the stack, frame or arg pointers. */
11509 if (regno == STACK_POINTER_REGNUM
11510 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11511 || regno == HARD_FRAME_POINTER_REGNUM
11513 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11514 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11516 || regno == FRAME_POINTER_REGNUM)
11519 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11520 for (r = regno; r < endregno; r++)
11521 SET_HARD_REG_BIT (newpat_used_regs, r);
11527 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11529 rtx testreg = SET_DEST (x);
11531 while (GET_CODE (testreg) == SUBREG
11532 || GET_CODE (testreg) == ZERO_EXTRACT
11533 || GET_CODE (testreg) == STRICT_LOW_PART)
11534 testreg = XEXP (testreg, 0);
11536 if (MEM_P (testreg))
11537 mark_used_regs_combine (XEXP (testreg, 0));
11539 mark_used_regs_combine (SET_SRC (x));
11547 /* Recursively scan the operands of this expression. */
11550 const char *fmt = GET_RTX_FORMAT (code);
11552 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11555 mark_used_regs_combine (XEXP (x, i));
11556 else if (fmt[i] == 'E')
11560 for (j = 0; j < XVECLEN (x, i); j++)
11561 mark_used_regs_combine (XVECEXP (x, i, j));
11567 /* Remove register number REGNO from the dead registers list of INSN.
11569 Return the note used to record the death, if there was one. */
11572 remove_death (unsigned int regno, rtx insn)
11574 rtx note = find_regno_note (insn, REG_DEAD, regno);
11578 REG_N_DEATHS (regno)--;
11579 remove_note (insn, note);
11585 /* For each register (hardware or pseudo) used within expression X, if its
11586 death is in an instruction with cuid between FROM_CUID (inclusive) and
11587 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11588 list headed by PNOTES.
11590 That said, don't move registers killed by maybe_kill_insn.
11592 This is done when X is being merged by combination into TO_INSN. These
11593 notes will then be distributed as needed. */
11596 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11601 enum rtx_code code = GET_CODE (x);
11605 unsigned int regno = REGNO (x);
11606 rtx where_dead = reg_stat[regno].last_death;
11607 rtx before_dead, after_dead;
11609 /* Don't move the register if it gets killed in between from and to. */
11610 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11611 && ! reg_referenced_p (x, maybe_kill_insn))
11614 /* WHERE_DEAD could be a USE insn made by combine, so first we
11615 make sure that we have insns with valid INSN_CUID values. */
11616 before_dead = where_dead;
11617 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11618 before_dead = PREV_INSN (before_dead);
11620 after_dead = where_dead;
11621 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11622 after_dead = NEXT_INSN (after_dead);
11624 if (before_dead && after_dead
11625 && INSN_CUID (before_dead) >= from_cuid
11626 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11627 || (where_dead != after_dead
11628 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11630 rtx note = remove_death (regno, where_dead);
11632 /* It is possible for the call above to return 0. This can occur
11633 when last_death points to I2 or I1 that we combined with.
11634 In that case make a new note.
11636 We must also check for the case where X is a hard register
11637 and NOTE is a death note for a range of hard registers
11638 including X. In that case, we must put REG_DEAD notes for
11639 the remaining registers in place of NOTE. */
11641 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11642 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11643 > GET_MODE_SIZE (GET_MODE (x))))
11645 unsigned int deadregno = REGNO (XEXP (note, 0));
11646 unsigned int deadend
11647 = (deadregno + hard_regno_nregs[deadregno]
11648 [GET_MODE (XEXP (note, 0))]);
11649 unsigned int ourend
11650 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11653 for (i = deadregno; i < deadend; i++)
11654 if (i < regno || i >= ourend)
11655 REG_NOTES (where_dead)
11656 = gen_rtx_EXPR_LIST (REG_DEAD,
11658 REG_NOTES (where_dead));
11661 /* If we didn't find any note, or if we found a REG_DEAD note that
11662 covers only part of the given reg, and we have a multi-reg hard
11663 register, then to be safe we must check for REG_DEAD notes
11664 for each register other than the first. They could have
11665 their own REG_DEAD notes lying around. */
11666 else if ((note == 0
11668 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11669 < GET_MODE_SIZE (GET_MODE (x)))))
11670 && regno < FIRST_PSEUDO_REGISTER
11671 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11673 unsigned int ourend
11674 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11675 unsigned int i, offset;
11679 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11683 for (i = regno + offset; i < ourend; i++)
11684 move_deaths (regno_reg_rtx[i],
11685 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11688 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11690 XEXP (note, 1) = *pnotes;
11694 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11696 REG_N_DEATHS (regno)++;
11702 else if (GET_CODE (x) == SET)
11704 rtx dest = SET_DEST (x);
11706 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11708 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11709 that accesses one word of a multi-word item, some
11710 piece of everything register in the expression is used by
11711 this insn, so remove any old death. */
11712 /* ??? So why do we test for equality of the sizes? */
11714 if (GET_CODE (dest) == ZERO_EXTRACT
11715 || GET_CODE (dest) == STRICT_LOW_PART
11716 || (GET_CODE (dest) == SUBREG
11717 && (((GET_MODE_SIZE (GET_MODE (dest))
11718 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11719 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11720 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11722 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11726 /* If this is some other SUBREG, we know it replaces the entire
11727 value, so use that as the destination. */
11728 if (GET_CODE (dest) == SUBREG)
11729 dest = SUBREG_REG (dest);
11731 /* If this is a MEM, adjust deaths of anything used in the address.
11732 For a REG (the only other possibility), the entire value is
11733 being replaced so the old value is not used in this insn. */
11736 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11741 else if (GET_CODE (x) == CLOBBER)
11744 len = GET_RTX_LENGTH (code);
11745 fmt = GET_RTX_FORMAT (code);
11747 for (i = 0; i < len; i++)
11752 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11753 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11756 else if (fmt[i] == 'e')
11757 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11761 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11762 pattern of an insn. X must be a REG. */
11765 reg_bitfield_target_p (rtx x, rtx body)
11769 if (GET_CODE (body) == SET)
11771 rtx dest = SET_DEST (body);
11773 unsigned int regno, tregno, endregno, endtregno;
11775 if (GET_CODE (dest) == ZERO_EXTRACT)
11776 target = XEXP (dest, 0);
11777 else if (GET_CODE (dest) == STRICT_LOW_PART)
11778 target = SUBREG_REG (XEXP (dest, 0));
11782 if (GET_CODE (target) == SUBREG)
11783 target = SUBREG_REG (target);
11785 if (!REG_P (target))
11788 tregno = REGNO (target), regno = REGNO (x);
11789 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11790 return target == x;
11792 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11793 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11795 return endregno > tregno && regno < endtregno;
11798 else if (GET_CODE (body) == PARALLEL)
11799 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11800 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11806 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11807 as appropriate. I3 and I2 are the insns resulting from the combination
11808 insns including FROM (I2 may be zero).
11810 Each note in the list is either ignored or placed on some insns, depending
11811 on the type of note. */
11814 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11816 rtx note, next_note;
11819 for (note = notes; note; note = next_note)
11821 rtx place = 0, place2 = 0;
11823 /* If this NOTE references a pseudo register, ensure it references
11824 the latest copy of that register. */
11825 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11826 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11827 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11829 next_note = XEXP (note, 1);
11830 switch (REG_NOTE_KIND (note))
11834 /* Doesn't matter much where we put this, as long as it's somewhere.
11835 It is preferable to keep these notes on branches, which is most
11836 likely to be i3. */
11840 case REG_VALUE_PROFILE:
11841 /* Just get rid of this note, as it is unused later anyway. */
11844 case REG_NON_LOCAL_GOTO:
11849 gcc_assert (i2 && JUMP_P (i2));
11854 case REG_EH_REGION:
11855 /* These notes must remain with the call or trapping instruction. */
11858 else if (i2 && CALL_P (i2))
11862 gcc_assert (flag_non_call_exceptions);
11863 if (may_trap_p (i3))
11865 else if (i2 && may_trap_p (i2))
11867 /* ??? Otherwise assume we've combined things such that we
11868 can now prove that the instructions can't trap. Drop the
11869 note in this case. */
11875 /* These notes must remain with the call. It should not be
11876 possible for both I2 and I3 to be a call. */
11881 gcc_assert (i2 && CALL_P (i2));
11887 /* Any clobbers for i3 may still exist, and so we must process
11888 REG_UNUSED notes from that insn.
11890 Any clobbers from i2 or i1 can only exist if they were added by
11891 recog_for_combine. In that case, recog_for_combine created the
11892 necessary REG_UNUSED notes. Trying to keep any original
11893 REG_UNUSED notes from these insns can cause incorrect output
11894 if it is for the same register as the original i3 dest.
11895 In that case, we will notice that the register is set in i3,
11896 and then add a REG_UNUSED note for the destination of i3, which
11897 is wrong. However, it is possible to have REG_UNUSED notes from
11898 i2 or i1 for register which were both used and clobbered, so
11899 we keep notes from i2 or i1 if they will turn into REG_DEAD
11902 /* If this register is set or clobbered in I3, put the note there
11903 unless there is one already. */
11904 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11906 if (from_insn != i3)
11909 if (! (REG_P (XEXP (note, 0))
11910 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11911 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11914 /* Otherwise, if this register is used by I3, then this register
11915 now dies here, so we must put a REG_DEAD note here unless there
11917 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11918 && ! (REG_P (XEXP (note, 0))
11919 ? find_regno_note (i3, REG_DEAD,
11920 REGNO (XEXP (note, 0)))
11921 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11923 PUT_REG_NOTE_KIND (note, REG_DEAD);
11931 /* These notes say something about results of an insn. We can
11932 only support them if they used to be on I3 in which case they
11933 remain on I3. Otherwise they are ignored.
11935 If the note refers to an expression that is not a constant, we
11936 must also ignore the note since we cannot tell whether the
11937 equivalence is still true. It might be possible to do
11938 slightly better than this (we only have a problem if I2DEST
11939 or I1DEST is present in the expression), but it doesn't
11940 seem worth the trouble. */
11942 if (from_insn == i3
11943 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11948 case REG_NO_CONFLICT:
11949 /* These notes say something about how a register is used. They must
11950 be present on any use of the register in I2 or I3. */
11951 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11954 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11964 /* This can show up in several ways -- either directly in the
11965 pattern, or hidden off in the constant pool with (or without?)
11966 a REG_EQUAL note. */
11967 /* ??? Ignore the without-reg_equal-note problem for now. */
11968 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11969 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11970 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11971 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11975 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11976 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11977 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11978 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11986 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11987 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11988 if (place && JUMP_P (place))
11990 rtx label = JUMP_LABEL (place);
11993 JUMP_LABEL (place) = XEXP (note, 0);
11996 gcc_assert (label == XEXP (note, 0));
11997 if (LABEL_P (label))
11998 LABEL_NUSES (label)--;
12002 if (place2 && JUMP_P (place2))
12004 rtx label = JUMP_LABEL (place2);
12007 JUMP_LABEL (place2) = XEXP (note, 0);
12010 gcc_assert (label == XEXP (note, 0));
12011 if (LABEL_P (label))
12012 LABEL_NUSES (label)--;
12019 /* This note says something about the value of a register prior
12020 to the execution of an insn. It is too much trouble to see
12021 if the note is still correct in all situations. It is better
12022 to simply delete it. */
12026 /* If the insn previously containing this note still exists,
12027 put it back where it was. Otherwise move it to the previous
12028 insn. Adjust the corresponding REG_LIBCALL note. */
12029 if (!NOTE_P (from_insn))
12033 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
12034 place = prev_real_insn (from_insn);
12036 XEXP (tem, 0) = place;
12037 /* If we're deleting the last remaining instruction of a
12038 libcall sequence, don't add the notes. */
12039 else if (XEXP (note, 0) == from_insn)
12041 /* Don't add the dangling REG_RETVAL note. */
12048 /* This is handled similarly to REG_RETVAL. */
12049 if (!NOTE_P (from_insn))
12053 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
12054 place = next_real_insn (from_insn);
12056 XEXP (tem, 0) = place;
12057 /* If we're deleting the last remaining instruction of a
12058 libcall sequence, don't add the notes. */
12059 else if (XEXP (note, 0) == from_insn)
12061 /* Don't add the dangling REG_LIBCALL note. */
12068 /* If the register is used as an input in I3, it dies there.
12069 Similarly for I2, if it is nonzero and adjacent to I3.
12071 If the register is not used as an input in either I3 or I2
12072 and it is not one of the registers we were supposed to eliminate,
12073 there are two possibilities. We might have a non-adjacent I2
12074 or we might have somehow eliminated an additional register
12075 from a computation. For example, we might have had A & B where
12076 we discover that B will always be zero. In this case we will
12077 eliminate the reference to A.
12079 In both cases, we must search to see if we can find a previous
12080 use of A and put the death note there. */
12083 && CALL_P (from_insn)
12084 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12086 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12088 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12089 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12094 basic_block bb = this_basic_block;
12096 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
12098 if (! INSN_P (tem))
12100 if (tem == BB_HEAD (bb))
12105 /* If the register is being set at TEM, see if that is all
12106 TEM is doing. If so, delete TEM. Otherwise, make this
12107 into a REG_UNUSED note instead. Don't delete sets to
12108 global register vars. */
12109 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12110 || !global_regs[REGNO (XEXP (note, 0))])
12111 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12113 rtx set = single_set (tem);
12114 rtx inner_dest = 0;
12116 rtx cc0_setter = NULL_RTX;
12120 for (inner_dest = SET_DEST (set);
12121 (GET_CODE (inner_dest) == STRICT_LOW_PART
12122 || GET_CODE (inner_dest) == SUBREG
12123 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12124 inner_dest = XEXP (inner_dest, 0))
12127 /* Verify that it was the set, and not a clobber that
12128 modified the register.
12130 CC0 targets must be careful to maintain setter/user
12131 pairs. If we cannot delete the setter due to side
12132 effects, mark the user with an UNUSED note instead
12135 if (set != 0 && ! side_effects_p (SET_SRC (set))
12136 && rtx_equal_p (XEXP (note, 0), inner_dest)
12138 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12139 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12140 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12144 /* Move the notes and links of TEM elsewhere.
12145 This might delete other dead insns recursively.
12146 First set the pattern to something that won't use
12148 rtx old_notes = REG_NOTES (tem);
12150 PATTERN (tem) = pc_rtx;
12151 REG_NOTES (tem) = NULL;
12153 distribute_notes (old_notes, tem, tem, NULL_RTX);
12154 distribute_links (LOG_LINKS (tem));
12156 SET_INSN_DELETED (tem);
12159 /* Delete the setter too. */
12162 PATTERN (cc0_setter) = pc_rtx;
12163 old_notes = REG_NOTES (cc0_setter);
12164 REG_NOTES (cc0_setter) = NULL;
12166 distribute_notes (old_notes, cc0_setter,
12167 cc0_setter, NULL_RTX);
12168 distribute_links (LOG_LINKS (cc0_setter));
12170 SET_INSN_DELETED (cc0_setter);
12176 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12178 /* If there isn't already a REG_UNUSED note, put one
12179 here. Do not place a REG_DEAD note, even if
12180 the register is also used here; that would not
12181 match the algorithm used in lifetime analysis
12182 and can cause the consistency check in the
12183 scheduler to fail. */
12184 if (! find_regno_note (tem, REG_UNUSED,
12185 REGNO (XEXP (note, 0))))
12190 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12192 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12196 /* If we are doing a 3->2 combination, and we have a
12197 register which formerly died in i3 and was not used
12198 by i2, which now no longer dies in i3 and is used in
12199 i2 but does not die in i2, and place is between i2
12200 and i3, then we may need to move a link from place to
12202 if (i2 && INSN_UID (place) <= max_uid_cuid
12203 && INSN_CUID (place) > INSN_CUID (i2)
12205 && INSN_CUID (from_insn) > INSN_CUID (i2)
12206 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12208 rtx links = LOG_LINKS (place);
12209 LOG_LINKS (place) = 0;
12210 distribute_links (links);
12215 if (tem == BB_HEAD (bb))
12219 /* We haven't found an insn for the death note and it
12220 is still a REG_DEAD note, but we have hit the beginning
12221 of the block. If the existing life info says the reg
12222 was dead, there's nothing left to do. Otherwise, we'll
12223 need to do a global life update after combine. */
12224 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12225 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
12226 REGNO (XEXP (note, 0))))
12227 SET_BIT (refresh_blocks, this_basic_block->index);
12230 /* If the register is set or already dead at PLACE, we needn't do
12231 anything with this note if it is still a REG_DEAD note.
12232 We check here if it is set at all, not if is it totally replaced,
12233 which is what `dead_or_set_p' checks, so also check for it being
12236 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12238 unsigned int regno = REGNO (XEXP (note, 0));
12240 /* Similarly, if the instruction on which we want to place
12241 the note is a noop, we'll need do a global live update
12242 after we remove them in delete_noop_moves. */
12243 if (noop_move_p (place))
12244 SET_BIT (refresh_blocks, this_basic_block->index);
12246 if (dead_or_set_p (place, XEXP (note, 0))
12247 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12249 /* Unless the register previously died in PLACE, clear
12250 last_death. [I no longer understand why this is
12252 if (reg_stat[regno].last_death != place)
12253 reg_stat[regno].last_death = 0;
12257 reg_stat[regno].last_death = place;
12259 /* If this is a death note for a hard reg that is occupying
12260 multiple registers, ensure that we are still using all
12261 parts of the object. If we find a piece of the object
12262 that is unused, we must arrange for an appropriate REG_DEAD
12263 note to be added for it. However, we can't just emit a USE
12264 and tag the note to it, since the register might actually
12265 be dead; so we recourse, and the recursive call then finds
12266 the previous insn that used this register. */
12268 if (place && regno < FIRST_PSEUDO_REGISTER
12269 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12271 unsigned int endregno
12272 = regno + hard_regno_nregs[regno]
12273 [GET_MODE (XEXP (note, 0))];
12277 for (i = regno; i < endregno; i++)
12278 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12279 && ! find_regno_fusage (place, USE, i))
12280 || dead_or_set_regno_p (place, i))
12285 /* Put only REG_DEAD notes for pieces that are
12286 not already dead or set. */
12288 for (i = regno; i < endregno;
12289 i += hard_regno_nregs[i][reg_raw_mode[i]])
12291 rtx piece = regno_reg_rtx[i];
12292 basic_block bb = this_basic_block;
12294 if (! dead_or_set_p (place, piece)
12295 && ! reg_bitfield_target_p (piece,
12299 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12301 distribute_notes (new_note, place, place,
12304 else if (! refers_to_regno_p (i, i + 1,
12305 PATTERN (place), 0)
12306 && ! find_regno_fusage (place, USE, i))
12307 for (tem = PREV_INSN (place); ;
12308 tem = PREV_INSN (tem))
12310 if (! INSN_P (tem))
12312 if (tem == BB_HEAD (bb))
12314 SET_BIT (refresh_blocks,
12315 this_basic_block->index);
12320 if (dead_or_set_p (tem, piece)
12321 || reg_bitfield_target_p (piece,
12325 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12340 /* Any other notes should not be present at this point in the
12342 gcc_unreachable ();
12347 XEXP (note, 1) = REG_NOTES (place);
12348 REG_NOTES (place) = note;
12350 else if ((REG_NOTE_KIND (note) == REG_DEAD
12351 || REG_NOTE_KIND (note) == REG_UNUSED)
12352 && REG_P (XEXP (note, 0)))
12353 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12357 if ((REG_NOTE_KIND (note) == REG_DEAD
12358 || REG_NOTE_KIND (note) == REG_UNUSED)
12359 && REG_P (XEXP (note, 0)))
12360 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12362 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12363 REG_NOTE_KIND (note),
12365 REG_NOTES (place2));
12370 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12371 I3, I2, and I1 to new locations. This is also called to add a link
12372 pointing at I3 when I3's destination is changed. */
12375 distribute_links (rtx links)
12377 rtx link, next_link;
12379 for (link = links; link; link = next_link)
12385 next_link = XEXP (link, 1);
12387 /* If the insn that this link points to is a NOTE or isn't a single
12388 set, ignore it. In the latter case, it isn't clear what we
12389 can do other than ignore the link, since we can't tell which
12390 register it was for. Such links wouldn't be used by combine
12393 It is not possible for the destination of the target of the link to
12394 have been changed by combine. The only potential of this is if we
12395 replace I3, I2, and I1 by I3 and I2. But in that case the
12396 destination of I2 also remains unchanged. */
12398 if (NOTE_P (XEXP (link, 0))
12399 || (set = single_set (XEXP (link, 0))) == 0)
12402 reg = SET_DEST (set);
12403 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12404 || GET_CODE (reg) == STRICT_LOW_PART)
12405 reg = XEXP (reg, 0);
12407 /* A LOG_LINK is defined as being placed on the first insn that uses
12408 a register and points to the insn that sets the register. Start
12409 searching at the next insn after the target of the link and stop
12410 when we reach a set of the register or the end of the basic block.
12412 Note that this correctly handles the link that used to point from
12413 I3 to I2. Also note that not much searching is typically done here
12414 since most links don't point very far away. */
12416 for (insn = NEXT_INSN (XEXP (link, 0));
12417 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12418 || BB_HEAD (this_basic_block->next_bb) != insn));
12419 insn = NEXT_INSN (insn))
12420 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12422 if (reg_referenced_p (reg, PATTERN (insn)))
12426 else if (CALL_P (insn)
12427 && find_reg_fusage (insn, USE, reg))
12432 else if (INSN_P (insn) && reg_set_p (reg, insn))
12435 /* If we found a place to put the link, place it there unless there
12436 is already a link to the same insn as LINK at that point. */
12442 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12443 if (XEXP (link2, 0) == XEXP (link, 0))
12448 XEXP (link, 1) = LOG_LINKS (place);
12449 LOG_LINKS (place) = link;
12451 /* Set added_links_insn to the earliest insn we added a
12453 if (added_links_insn == 0
12454 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12455 added_links_insn = place;
12461 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12462 Check whether the expression pointer to by LOC is a register or
12463 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12464 Otherwise return zero. */
12467 unmentioned_reg_p_1 (rtx *loc, void *expr)
12472 && (REG_P (x) || MEM_P (x))
12473 && ! reg_mentioned_p (x, (rtx) expr))
12478 /* Check for any register or memory mentioned in EQUIV that is not
12479 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12480 of EXPR where some registers may have been replaced by constants. */
12483 unmentioned_reg_p (rtx equiv, rtx expr)
12485 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12488 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12491 insn_cuid (rtx insn)
12493 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12494 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12495 insn = NEXT_INSN (insn);
12497 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12499 return INSN_CUID (insn);
12503 dump_combine_stats (FILE *file)
12507 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12508 combine_attempts, combine_merges, combine_extras, combine_successes);
12512 dump_combine_total_stats (FILE *file)
12516 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12517 total_attempts, total_merges, total_extras, total_successes);
12522 gate_handle_combine (void)
12524 return (optimize > 0);
12527 /* Try combining insns through substitution. */
12529 rest_of_handle_combine (void)
12531 int rebuild_jump_labels_after_combine
12532 = combine_instructions (get_insns (), max_reg_num ());
12534 /* Combining insns may have turned an indirect jump into a
12535 direct jump. Rebuild the JUMP_LABEL fields of jumping
12537 if (rebuild_jump_labels_after_combine)
12539 timevar_push (TV_JUMP);
12540 rebuild_jump_labels (get_insns ());
12541 timevar_pop (TV_JUMP);
12543 delete_dead_jumptables ();
12544 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12548 struct tree_opt_pass pass_combine =
12550 "combine", /* name */
12551 gate_handle_combine, /* gate */
12552 rest_of_handle_combine, /* execute */
12555 0, /* static_pass_number */
12556 TV_COMBINE, /* tv_id */
12557 0, /* properties_required */
12558 0, /* properties_provided */
12559 0, /* properties_destroyed */
12560 0, /* todo_flags_start */
12562 TODO_ggc_collect, /* todo_flags_finish */