1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
87 #include "hard-reg-set.h"
88 #include "basic-block.h"
89 #include "insn-config.h"
91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
93 #include "insn-attr.h"
99 #include "insn-codes.h"
100 #include "rtlhooks-def.h"
101 /* Include output.h for dump_file. */
105 #include "tree-pass.h"
109 /* Number of attempts to combine instructions in this function. */
111 static int combine_attempts;
113 /* Number of attempts that got as far as substitution in this function. */
115 static int combine_merges;
117 /* Number of instructions combined with added SETs in this function. */
119 static int combine_extras;
121 /* Number of instructions combined in this function. */
123 static int combine_successes;
125 /* Totals over entire compilation. */
127 static int total_attempts, total_merges, total_extras, total_successes;
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
140 static rtx i2mod_old_rhs;
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 static rtx i2mod_new_rhs;
146 typedef struct reg_stat_struct {
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
203 int last_set_table_tick;
205 /* Record the value of label_tick when the value for register n is placed in
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
215 unsigned HOST_WIDE_INT last_set_nonzero_bits;
216 char last_set_sign_bit_copies;
217 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
223 char last_set_invalid;
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
235 If an entry is zero, it means that we don't know anything special. */
237 unsigned char sign_bit_copies;
239 unsigned HOST_WIDE_INT nonzero_bits;
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
245 int truncation_label;
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
252 ENUM_BITFIELD(machine_mode) truncated_to_mode : 8;
255 DEF_VEC_O(reg_stat_type);
256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
258 static VEC(reg_stat_type,heap) *reg_stat;
260 /* Record the luid of the last insn that invalidated memory
261 (anything that writes memory, and subroutine calls, but not pushes). */
263 static int mem_last_set;
265 /* Record the luid of the last CALL_INSN
266 so we can tell whether a potential combination crosses any calls. */
268 static int last_call_luid;
270 /* When `subst' is called, this is the insn that is being modified
271 (by combining in a previous insn). The PATTERN of this insn
272 is still the old pattern partially modified and it should not be
273 looked at, but this may be used to examine the successors of the insn
274 to judge whether a simplification is valid. */
276 static rtx subst_insn;
278 /* This is the lowest LUID that `subst' is currently dealing with.
279 get_last_value will not return a value if the register was set at or
280 after this LUID. If not for this mechanism, we could get confused if
281 I2 or I1 in try_combine were an insn that used the old value of a register
282 to obtain a new value. In that case, we might erroneously get the
283 new value of the register when we wanted the old one. */
285 static int subst_low_luid;
287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
288 must consider all these registers to be always live. */
290 static HARD_REG_SET newpat_used_regs;
292 /* This is an insn to which a LOG_LINKS entry has been added. If this
293 insn is the earlier than I2 or I3, combine should rescan starting at
296 static rtx added_links_insn;
298 /* Basic block in which we are performing combines. */
299 static basic_block this_basic_block;
302 /* Length of the currently allocated uid_insn_cost array. */
304 static int max_uid_known;
306 /* The following array records the insn_rtx_cost for every insn
307 in the instruction stream. */
309 static int *uid_insn_cost;
311 /* The following array records the LOG_LINKS for every insn in the
312 instruction stream as an INSN_LIST rtx. */
314 static rtx *uid_log_links;
316 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
317 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
319 /* Incremented for each basic block. */
321 static int label_tick;
323 /* Reset to label_tick for each label. */
325 static int label_tick_ebb_start;
327 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
328 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
330 static enum machine_mode nonzero_bits_mode;
332 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
333 be safely used. It is zero while computing them and after combine has
334 completed. This former test prevents propagating values based on
335 previously set values, which can be incorrect if a variable is modified
338 static int nonzero_sign_valid;
341 /* Record one modification to rtl structure
342 to be undone by storing old_contents into *where. */
347 enum { UNDO_RTX, UNDO_INT, UNDO_MODE } kind;
348 union { rtx r; int i; enum machine_mode m; } old_contents;
349 union { rtx *r; int *i; } where;
352 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
353 num_undo says how many are currently recorded.
355 other_insn is nonzero if we have modified some other insn in the process
356 of working on subst_insn. It must be verified too. */
365 static struct undobuf undobuf;
367 /* Number of times the pseudo being substituted for
368 was found and replaced. */
370 static int n_occurrences;
372 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
374 unsigned HOST_WIDE_INT,
375 unsigned HOST_WIDE_INT *);
376 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
378 unsigned int, unsigned int *);
379 static void do_SUBST (rtx *, rtx);
380 static void do_SUBST_INT (int *, int);
381 static void init_reg_last (void);
382 static void setup_incoming_promotions (rtx);
383 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
384 static int cant_combine_insn_p (rtx);
385 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
386 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
387 static int contains_muldiv (rtx);
388 static rtx try_combine (rtx, rtx, rtx, int *);
389 static void undo_all (void);
390 static void undo_commit (void);
391 static rtx *find_split_point (rtx *, rtx);
392 static rtx subst (rtx, rtx, rtx, int, int);
393 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
394 static rtx simplify_if_then_else (rtx);
395 static rtx simplify_set (rtx);
396 static rtx simplify_logical (rtx);
397 static rtx expand_compound_operation (rtx);
398 static const_rtx expand_field_assignment (const_rtx);
399 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
400 rtx, unsigned HOST_WIDE_INT, int, int, int);
401 static rtx extract_left_shift (rtx, int);
402 static rtx make_compound_operation (rtx, enum rtx_code);
403 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
404 unsigned HOST_WIDE_INT *);
405 static rtx canon_reg_for_combine (rtx, rtx);
406 static rtx force_to_mode (rtx, enum machine_mode,
407 unsigned HOST_WIDE_INT, int);
408 static rtx if_then_else_cond (rtx, rtx *, rtx *);
409 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
410 static int rtx_equal_for_field_assignment_p (rtx, rtx);
411 static rtx make_field_assignment (rtx);
412 static rtx apply_distributive_law (rtx);
413 static rtx distribute_and_simplify_rtx (rtx, int);
414 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
415 unsigned HOST_WIDE_INT);
416 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
417 unsigned HOST_WIDE_INT);
418 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
419 HOST_WIDE_INT, enum machine_mode, int *);
420 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
421 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
423 static int recog_for_combine (rtx *, rtx, rtx *);
424 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
425 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
426 static void update_table_tick (rtx);
427 static void record_value_for_reg (rtx, rtx, rtx);
428 static void check_promoted_subreg (rtx, rtx);
429 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
430 static void record_dead_and_set_regs (rtx);
431 static int get_last_value_validate (rtx *, rtx, int, int);
432 static rtx get_last_value (const_rtx);
433 static int use_crosses_set_p (const_rtx, int);
434 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
435 static int reg_dead_at_p (rtx, rtx);
436 static void move_deaths (rtx, rtx, int, rtx, rtx *);
437 static int reg_bitfield_target_p (rtx, rtx);
438 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
439 static void distribute_links (rtx);
440 static void mark_used_regs_combine (rtx);
441 static void record_promoted_value (rtx, rtx);
442 static int unmentioned_reg_p_1 (rtx *, void *);
443 static bool unmentioned_reg_p (rtx, rtx);
444 static int record_truncated_value (rtx *, void *);
445 static void record_truncated_values (rtx *, void *);
446 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
447 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
450 /* It is not safe to use ordinary gen_lowpart in combine.
451 See comments in gen_lowpart_for_combine. */
452 #undef RTL_HOOKS_GEN_LOWPART
453 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
455 /* Our implementation of gen_lowpart never emits a new pseudo. */
456 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
457 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
459 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
460 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
462 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
463 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
465 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
466 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
468 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
471 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
472 PATTERN can not be split. Otherwise, it returns an insn sequence.
473 This is a wrapper around split_insns which ensures that the
474 reg_stat vector is made larger if the splitter creates a new
478 combine_split_insns (rtx pattern, rtx insn)
483 ret = split_insns (pattern, insn);
484 nregs = max_reg_num ();
485 if (nregs > VEC_length (reg_stat_type, reg_stat))
486 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
490 /* This is used by find_single_use to locate an rtx in LOC that
491 contains exactly one use of DEST, which is typically either a REG
492 or CC0. It returns a pointer to the innermost rtx expression
493 containing DEST. Appearances of DEST that are being used to
494 totally replace it are not counted. */
497 find_single_use_1 (rtx dest, rtx *loc)
500 enum rtx_code code = GET_CODE (x);
518 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
519 of a REG that occupies all of the REG, the insn uses DEST if
520 it is mentioned in the destination or the source. Otherwise, we
521 need just check the source. */
522 if (GET_CODE (SET_DEST (x)) != CC0
523 && GET_CODE (SET_DEST (x)) != PC
524 && !REG_P (SET_DEST (x))
525 && ! (GET_CODE (SET_DEST (x)) == SUBREG
526 && REG_P (SUBREG_REG (SET_DEST (x)))
527 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
528 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
529 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
530 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
533 return find_single_use_1 (dest, &SET_SRC (x));
537 return find_single_use_1 (dest, &XEXP (x, 0));
543 /* If it wasn't one of the common cases above, check each expression and
544 vector of this code. Look for a unique usage of DEST. */
546 fmt = GET_RTX_FORMAT (code);
547 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
551 if (dest == XEXP (x, i)
552 || (REG_P (dest) && REG_P (XEXP (x, i))
553 && REGNO (dest) == REGNO (XEXP (x, i))))
556 this_result = find_single_use_1 (dest, &XEXP (x, i));
559 result = this_result;
560 else if (this_result)
561 /* Duplicate usage. */
564 else if (fmt[i] == 'E')
568 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
570 if (XVECEXP (x, i, j) == dest
572 && REG_P (XVECEXP (x, i, j))
573 && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
576 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
579 result = this_result;
580 else if (this_result)
590 /* See if DEST, produced in INSN, is used only a single time in the
591 sequel. If so, return a pointer to the innermost rtx expression in which
594 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
596 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
597 care about REG_DEAD notes or LOG_LINKS.
599 Otherwise, we find the single use by finding an insn that has a
600 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
601 only referenced once in that insn, we know that it must be the first
602 and last insn referencing DEST. */
605 find_single_use (rtx dest, rtx insn, rtx *ploc)
614 next = NEXT_INSN (insn);
616 || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
619 result = find_single_use_1 (dest, &PATTERN (next));
629 for (next = next_nonnote_insn (insn);
630 next != 0 && !LABEL_P (next);
631 next = next_nonnote_insn (next))
632 if (INSN_P (next) && dead_or_set_p (next, dest))
634 for (link = LOG_LINKS (next); link; link = XEXP (link, 1))
635 if (XEXP (link, 0) == insn)
640 result = find_single_use_1 (dest, &PATTERN (next));
650 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
651 insn. The substitution can be undone by undo_all. If INTO is already
652 set to NEWVAL, do not record this change. Because computing NEWVAL might
653 also call SUBST, we have to compute it before we put anything into
657 do_SUBST (rtx *into, rtx newval)
662 if (oldval == newval)
665 /* We'd like to catch as many invalid transformations here as
666 possible. Unfortunately, there are way too many mode changes
667 that are perfectly valid, so we'd waste too much effort for
668 little gain doing the checks here. Focus on catching invalid
669 transformations involving integer constants. */
670 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
671 && GET_CODE (newval) == CONST_INT)
673 /* Sanity check that we're replacing oldval with a CONST_INT
674 that is a valid sign-extension for the original mode. */
675 gcc_assert (INTVAL (newval)
676 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
678 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
679 CONST_INT is not valid, because after the replacement, the
680 original mode would be gone. Unfortunately, we can't tell
681 when do_SUBST is called to replace the operand thereof, so we
682 perform this test on oldval instead, checking whether an
683 invalid replacement took place before we got here. */
684 gcc_assert (!(GET_CODE (oldval) == SUBREG
685 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
686 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
687 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
691 buf = undobuf.frees, undobuf.frees = buf->next;
693 buf = XNEW (struct undo);
695 buf->kind = UNDO_RTX;
697 buf->old_contents.r = oldval;
700 buf->next = undobuf.undos, undobuf.undos = buf;
703 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
705 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
706 for the value of a HOST_WIDE_INT value (including CONST_INT) is
710 do_SUBST_INT (int *into, int newval)
715 if (oldval == newval)
719 buf = undobuf.frees, undobuf.frees = buf->next;
721 buf = XNEW (struct undo);
723 buf->kind = UNDO_INT;
725 buf->old_contents.i = oldval;
728 buf->next = undobuf.undos, undobuf.undos = buf;
731 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
733 /* Similar to SUBST, but just substitute the mode. This is used when
734 changing the mode of a pseudo-register, so that any other
735 references to the entry in the regno_reg_rtx array will change as
739 do_SUBST_MODE (rtx *into, enum machine_mode newval)
742 enum machine_mode oldval = GET_MODE (*into);
744 if (oldval == newval)
748 buf = undobuf.frees, undobuf.frees = buf->next;
750 buf = XNEW (struct undo);
752 buf->kind = UNDO_MODE;
754 buf->old_contents.m = oldval;
755 adjust_reg_mode (*into, newval);
757 buf->next = undobuf.undos, undobuf.undos = buf;
760 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE(&(INTO), (NEWVAL))
762 /* Subroutine of try_combine. Determine whether the combine replacement
763 patterns NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to
764 insn_rtx_cost that the original instruction sequence I1, I2, I3 and
765 undobuf.other_insn. Note that I1 and/or NEWI2PAT may be NULL_RTX.
766 NEWOTHERPAT and undobuf.other_insn may also both be NULL_RTX. This
767 function returns false, if the costs of all instructions can be
768 estimated, and the replacements are more expensive than the original
772 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat,
775 int i1_cost, i2_cost, i3_cost;
776 int new_i2_cost, new_i3_cost;
777 int old_cost, new_cost;
779 /* Lookup the original insn_rtx_costs. */
780 i2_cost = INSN_COST (i2);
781 i3_cost = INSN_COST (i3);
785 i1_cost = INSN_COST (i1);
786 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
787 ? i1_cost + i2_cost + i3_cost : 0;
791 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
795 /* Calculate the replacement insn_rtx_costs. */
796 new_i3_cost = insn_rtx_cost (newpat);
799 new_i2_cost = insn_rtx_cost (newi2pat);
800 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
801 ? new_i2_cost + new_i3_cost : 0;
805 new_cost = new_i3_cost;
809 if (undobuf.other_insn)
811 int old_other_cost, new_other_cost;
813 old_other_cost = INSN_COST (undobuf.other_insn);
814 new_other_cost = insn_rtx_cost (newotherpat);
815 if (old_other_cost > 0 && new_other_cost > 0)
817 old_cost += old_other_cost;
818 new_cost += new_other_cost;
824 /* Disallow this recombination if both new_cost and old_cost are
825 greater than zero, and new_cost is greater than old cost. */
827 && new_cost > old_cost)
834 "rejecting combination of insns %d, %d and %d\n",
835 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
836 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
837 i1_cost, i2_cost, i3_cost, old_cost);
842 "rejecting combination of insns %d and %d\n",
843 INSN_UID (i2), INSN_UID (i3));
844 fprintf (dump_file, "original costs %d + %d = %d\n",
845 i2_cost, i3_cost, old_cost);
850 fprintf (dump_file, "replacement costs %d + %d = %d\n",
851 new_i2_cost, new_i3_cost, new_cost);
854 fprintf (dump_file, "replacement cost %d\n", new_cost);
860 /* Update the uid_insn_cost array with the replacement costs. */
861 INSN_COST (i2) = new_i2_cost;
862 INSN_COST (i3) = new_i3_cost;
870 /* Delete any insns that copy a register to itself. */
873 delete_noop_moves (void)
880 for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
882 next = NEXT_INSN (insn);
883 if (INSN_P (insn) && noop_move_p (insn))
886 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
888 delete_insn_and_edges (insn);
895 /* Fill in log links field for all insns. */
898 create_log_links (void)
902 struct df_ref **def_vec, **use_vec;
904 next_use = XCNEWVEC (rtx, max_reg_num ());
906 /* Pass through each block from the end, recording the uses of each
907 register and establishing log links when def is encountered.
908 Note that we do not clear next_use array in order to save time,
909 so we have to test whether the use is in the same basic block as def.
911 There are a few cases below when we do not consider the definition or
912 usage -- these are taken from original flow.c did. Don't ask me why it is
913 done this way; I don't know and if it works, I don't want to know. */
917 FOR_BB_INSNS_REVERSE (bb, insn)
922 /* Log links are created only once. */
923 gcc_assert (!LOG_LINKS (insn));
925 for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
927 struct df_ref *def = *def_vec;
928 int regno = DF_REF_REGNO (def);
931 if (!next_use[regno])
934 /* Do not consider if it is pre/post modification in MEM. */
935 if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
938 /* Do not make the log link for frame pointer. */
939 if ((regno == FRAME_POINTER_REGNUM
940 && (! reload_completed || frame_pointer_needed))
941 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
942 || (regno == HARD_FRAME_POINTER_REGNUM
943 && (! reload_completed || frame_pointer_needed))
945 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
946 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
951 use_insn = next_use[regno];
952 if (BLOCK_FOR_INSN (use_insn) == bb)
956 We don't build a LOG_LINK for hard registers contained
957 in ASM_OPERANDs. If these registers get replaced,
958 we might wind up changing the semantics of the insn,
959 even if reload can make what appear to be valid
960 assignments later. */
961 if (regno >= FIRST_PSEUDO_REGISTER
962 || asm_noperands (PATTERN (use_insn)) < 0)
964 /* Don't add duplicate links between instructions. */
966 for (links = LOG_LINKS (use_insn); links;
967 links = XEXP (links, 1))
968 if (insn == XEXP (links, 0))
972 LOG_LINKS (use_insn) =
973 alloc_INSN_LIST (insn, LOG_LINKS (use_insn));
976 next_use[regno] = NULL_RTX;
979 for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
981 struct df_ref *use = *use_vec;
982 int regno = DF_REF_REGNO (use);
984 /* Do not consider the usage of the stack pointer
986 if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
989 next_use[regno] = insn;
997 /* Clear LOG_LINKS fields of insns. */
1000 clear_log_links (void)
1004 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
1006 free_INSN_LIST_list (&LOG_LINKS (insn));
1012 /* Main entry point for combiner. F is the first insn of the function.
1013 NREGS is the first unused pseudo-reg number.
1015 Return nonzero if the combiner has turned an indirect jump
1016 instruction into a direct jump. */
1018 combine_instructions (rtx f, unsigned int nregs)
1024 rtx links, nextlinks;
1027 int new_direct_jump_p = 0;
1029 for (first = f; first && !INSN_P (first); )
1030 first = NEXT_INSN (first);
1034 combine_attempts = 0;
1037 combine_successes = 0;
1039 rtl_hooks = combine_rtl_hooks;
1041 VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1043 init_recog_no_volatile ();
1045 /* Allocate array for insn info. */
1046 max_uid_known = get_max_uid ();
1047 uid_log_links = XCNEWVEC (rtx, max_uid_known + 1);
1048 uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1050 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1052 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1053 problems when, for example, we have j <<= 1 in a loop. */
1055 nonzero_sign_valid = 0;
1057 /* Scan all SETs and see if we can deduce anything about what
1058 bits are known to be zero for some registers and how many copies
1059 of the sign bit are known to exist for those registers.
1061 Also set any known values so that we can use it while searching
1062 for what bits are known to be set. */
1064 label_tick = label_tick_ebb_start = 1;
1066 setup_incoming_promotions (first);
1068 create_log_links ();
1069 FOR_EACH_BB (this_basic_block)
1074 FOR_BB_INSNS (this_basic_block, insn)
1075 if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1077 subst_low_luid = DF_INSN_LUID (insn);
1080 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1082 record_dead_and_set_regs (insn);
1085 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1086 if (REG_NOTE_KIND (links) == REG_INC)
1087 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1091 /* Record the current insn_rtx_cost of this instruction. */
1092 if (NONJUMP_INSN_P (insn))
1093 INSN_COST (insn) = insn_rtx_cost (PATTERN (insn));
1095 fprintf(dump_file, "insn_cost %d: %d\n",
1096 INSN_UID (insn), INSN_COST (insn));
1098 else if (LABEL_P (insn))
1099 label_tick_ebb_start = label_tick;
1102 nonzero_sign_valid = 1;
1104 /* Now scan all the insns in forward order. */
1106 label_tick = label_tick_ebb_start = 1;
1108 setup_incoming_promotions (first);
1110 FOR_EACH_BB (this_basic_block)
1115 for (insn = BB_HEAD (this_basic_block);
1116 insn != NEXT_INSN (BB_END (this_basic_block));
1117 insn = next ? next : NEXT_INSN (insn))
1122 /* See if we know about function return values before this
1123 insn based upon SUBREG flags. */
1124 check_promoted_subreg (insn, PATTERN (insn));
1126 /* See if we can find hardregs and subreg of pseudos in
1127 narrower modes. This could help turning TRUNCATEs
1129 note_uses (&PATTERN (insn), record_truncated_values, NULL);
1131 /* Try this insn with each insn it links back to. */
1133 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1134 if ((next = try_combine (insn, XEXP (links, 0),
1135 NULL_RTX, &new_direct_jump_p)) != 0)
1138 /* Try each sequence of three linked insns ending with this one. */
1140 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1142 rtx link = XEXP (links, 0);
1144 /* If the linked insn has been replaced by a note, then there
1145 is no point in pursuing this chain any further. */
1149 for (nextlinks = LOG_LINKS (link);
1151 nextlinks = XEXP (nextlinks, 1))
1152 if ((next = try_combine (insn, link,
1153 XEXP (nextlinks, 0),
1154 &new_direct_jump_p)) != 0)
1159 /* Try to combine a jump insn that uses CC0
1160 with a preceding insn that sets CC0, and maybe with its
1161 logical predecessor as well.
1162 This is how we make decrement-and-branch insns.
1163 We need this special code because data flow connections
1164 via CC0 do not get entered in LOG_LINKS. */
1167 && (prev = prev_nonnote_insn (insn)) != 0
1168 && NONJUMP_INSN_P (prev)
1169 && sets_cc0_p (PATTERN (prev)))
1171 if ((next = try_combine (insn, prev,
1172 NULL_RTX, &new_direct_jump_p)) != 0)
1175 for (nextlinks = LOG_LINKS (prev); nextlinks;
1176 nextlinks = XEXP (nextlinks, 1))
1177 if ((next = try_combine (insn, prev,
1178 XEXP (nextlinks, 0),
1179 &new_direct_jump_p)) != 0)
1183 /* Do the same for an insn that explicitly references CC0. */
1184 if (NONJUMP_INSN_P (insn)
1185 && (prev = prev_nonnote_insn (insn)) != 0
1186 && NONJUMP_INSN_P (prev)
1187 && sets_cc0_p (PATTERN (prev))
1188 && GET_CODE (PATTERN (insn)) == SET
1189 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1191 if ((next = try_combine (insn, prev,
1192 NULL_RTX, &new_direct_jump_p)) != 0)
1195 for (nextlinks = LOG_LINKS (prev); nextlinks;
1196 nextlinks = XEXP (nextlinks, 1))
1197 if ((next = try_combine (insn, prev,
1198 XEXP (nextlinks, 0),
1199 &new_direct_jump_p)) != 0)
1203 /* Finally, see if any of the insns that this insn links to
1204 explicitly references CC0. If so, try this insn, that insn,
1205 and its predecessor if it sets CC0. */
1206 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1207 if (NONJUMP_INSN_P (XEXP (links, 0))
1208 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
1209 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
1210 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
1211 && NONJUMP_INSN_P (prev)
1212 && sets_cc0_p (PATTERN (prev))
1213 && (next = try_combine (insn, XEXP (links, 0),
1214 prev, &new_direct_jump_p)) != 0)
1218 /* Try combining an insn with two different insns whose results it
1220 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1221 for (nextlinks = XEXP (links, 1); nextlinks;
1222 nextlinks = XEXP (nextlinks, 1))
1223 if ((next = try_combine (insn, XEXP (links, 0),
1224 XEXP (nextlinks, 0),
1225 &new_direct_jump_p)) != 0)
1228 /* Try this insn with each REG_EQUAL note it links back to. */
1229 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
1232 rtx temp = XEXP (links, 0);
1233 if ((set = single_set (temp)) != 0
1234 && (note = find_reg_equal_equiv_note (temp)) != 0
1235 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1236 /* Avoid using a register that may already been marked
1237 dead by an earlier instruction. */
1238 && ! unmentioned_reg_p (note, SET_SRC (set))
1239 && (GET_MODE (note) == VOIDmode
1240 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1241 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1243 /* Temporarily replace the set's source with the
1244 contents of the REG_EQUAL note. The insn will
1245 be deleted or recognized by try_combine. */
1246 rtx orig = SET_SRC (set);
1247 SET_SRC (set) = note;
1249 i2mod_old_rhs = copy_rtx (orig);
1250 i2mod_new_rhs = copy_rtx (note);
1251 next = try_combine (insn, i2mod, NULL_RTX,
1252 &new_direct_jump_p);
1256 SET_SRC (set) = orig;
1261 record_dead_and_set_regs (insn);
1266 else if (LABEL_P (insn))
1267 label_tick_ebb_start = label_tick;
1273 new_direct_jump_p |= purge_all_dead_edges ();
1274 delete_noop_moves ();
1277 free (uid_log_links);
1278 free (uid_insn_cost);
1279 VEC_free (reg_stat_type, heap, reg_stat);
1282 struct undo *undo, *next;
1283 for (undo = undobuf.frees; undo; undo = next)
1291 total_attempts += combine_attempts;
1292 total_merges += combine_merges;
1293 total_extras += combine_extras;
1294 total_successes += combine_successes;
1296 nonzero_sign_valid = 0;
1297 rtl_hooks = general_rtl_hooks;
1299 /* Make recognizer allow volatile MEMs again. */
1302 return new_direct_jump_p;
1305 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1308 init_reg_last (void)
1313 for (i = 0; VEC_iterate (reg_stat_type, reg_stat, i, p); ++i)
1314 memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1317 /* Set up any promoted values for incoming argument registers. */
1320 setup_incoming_promotions (rtx first)
1323 bool strictly_local = false;
1325 if (!targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
1328 for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1329 arg = TREE_CHAIN (arg))
1331 rtx reg = DECL_INCOMING_RTL (arg);
1333 enum machine_mode mode1, mode2, mode3, mode4;
1335 /* Only continue if the incoming argument is in a register. */
1339 /* Determine, if possible, whether all call sites of the current
1340 function lie within the current compilation unit. (This does
1341 take into account the exporting of a function via taking its
1342 address, and so forth.) */
1343 if (flag_unit_at_a_time)
1344 strictly_local = cgraph_local_info (current_function_decl)->local;
1346 /* The mode and signedness of the argument before any promotions happen
1347 (equal to the mode of the pseudo holding it at that stage). */
1348 mode1 = TYPE_MODE (TREE_TYPE (arg));
1349 uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1351 /* The mode and signedness of the argument after any source language and
1352 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1353 mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1354 uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1356 /* The mode and signedness of the argument as it is actually passed,
1357 after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions. */
1358 mode3 = promote_mode (DECL_ARG_TYPE (arg), mode2, &uns3, 1);
1360 /* The mode of the register in which the argument is being passed. */
1361 mode4 = GET_MODE (reg);
1363 /* Eliminate sign extensions in the callee when possible. Only
1365 (a) a mode promotion has occurred;
1366 (b) the mode of the register is the same as the mode of
1367 the argument as it is passed; and
1368 (c) the signedness does not change across any of the promotions; and
1369 (d) when no language-level promotions (which we cannot guarantee
1370 will have been done by an external caller) are necessary,
1371 unless we know that this function is only ever called from
1372 the current compilation unit -- all of whose call sites will
1373 do the mode1 --> mode2 promotion. */
1377 && (mode1 == mode2 || strictly_local))
1379 /* Record that the value was promoted from mode1 to mode3,
1380 so that any sign extension at the head of the current
1381 function may be eliminated. */
1383 x = gen_rtx_CLOBBER (mode1, const0_rtx);
1384 x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1385 record_value_for_reg (reg, first, x);
1390 /* Called via note_stores. If X is a pseudo that is narrower than
1391 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1393 If we are setting only a portion of X and we can't figure out what
1394 portion, assume all bits will be used since we don't know what will
1397 Similarly, set how many bits of X are known to be copies of the sign bit
1398 at all locations in the function. This is the smallest number implied
1402 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1404 rtx insn = (rtx) data;
1408 && REGNO (x) >= FIRST_PSEUDO_REGISTER
1409 /* If this register is undefined at the start of the file, we can't
1410 say what its contents were. */
1411 && ! REGNO_REG_SET_P
1412 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1413 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1415 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1417 if (set == 0 || GET_CODE (set) == CLOBBER)
1419 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1420 rsp->sign_bit_copies = 1;
1424 /* If this register is being initialized using itself, and the
1425 register is uninitialized in this basic block, and there are
1426 no LOG_LINKS which set the register, then part of the
1427 register is uninitialized. In that case we can't assume
1428 anything about the number of nonzero bits.
1430 ??? We could do better if we checked this in
1431 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1432 could avoid making assumptions about the insn which initially
1433 sets the register, while still using the information in other
1434 insns. We would have to be careful to check every insn
1435 involved in the combination. */
1438 && reg_referenced_p (x, PATTERN (insn))
1439 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1444 for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
1446 if (dead_or_set_p (XEXP (link, 0), x))
1451 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1452 rsp->sign_bit_copies = 1;
1457 /* If this is a complex assignment, see if we can convert it into a
1458 simple assignment. */
1459 set = expand_field_assignment (set);
1461 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1462 set what we know about X. */
1464 if (SET_DEST (set) == x
1465 || (GET_CODE (SET_DEST (set)) == SUBREG
1466 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1467 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1468 && SUBREG_REG (SET_DEST (set)) == x))
1470 rtx src = SET_SRC (set);
1472 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1473 /* If X is narrower than a word and SRC is a non-negative
1474 constant that would appear negative in the mode of X,
1475 sign-extend it for use in reg_stat[].nonzero_bits because some
1476 machines (maybe most) will actually do the sign-extension
1477 and this is the conservative approach.
1479 ??? For 2.5, try to tighten up the MD files in this regard
1480 instead of this kludge. */
1482 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1483 && GET_CODE (src) == CONST_INT
1485 && 0 != (INTVAL (src)
1486 & ((HOST_WIDE_INT) 1
1487 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1488 src = GEN_INT (INTVAL (src)
1489 | ((HOST_WIDE_INT) (-1)
1490 << GET_MODE_BITSIZE (GET_MODE (x))));
1493 /* Don't call nonzero_bits if it cannot change anything. */
1494 if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1495 rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1496 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1497 if (rsp->sign_bit_copies == 0
1498 || rsp->sign_bit_copies > num)
1499 rsp->sign_bit_copies = num;
1503 rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1504 rsp->sign_bit_copies = 1;
1509 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1510 insns that were previously combined into I3 or that will be combined
1511 into the merger of INSN and I3.
1513 Return 0 if the combination is not allowed for any reason.
1515 If the combination is allowed, *PDEST will be set to the single
1516 destination of INSN and *PSRC to the single source, and this function
1520 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1521 rtx *pdest, rtx *psrc)
1530 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1531 && next_active_insn (succ) == i3)
1532 : next_active_insn (insn) == i3);
1534 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1535 or a PARALLEL consisting of such a SET and CLOBBERs.
1537 If INSN has CLOBBER parallel parts, ignore them for our processing.
1538 By definition, these happen during the execution of the insn. When it
1539 is merged with another insn, all bets are off. If they are, in fact,
1540 needed and aren't also supplied in I3, they may be added by
1541 recog_for_combine. Otherwise, it won't match.
1543 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1546 Get the source and destination of INSN. If more than one, can't
1549 if (GET_CODE (PATTERN (insn)) == SET)
1550 set = PATTERN (insn);
1551 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1552 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1554 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1556 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1559 switch (GET_CODE (elt))
1561 /* This is important to combine floating point insns
1562 for the SH4 port. */
1564 /* Combining an isolated USE doesn't make sense.
1565 We depend here on combinable_i3pat to reject them. */
1566 /* The code below this loop only verifies that the inputs of
1567 the SET in INSN do not change. We call reg_set_between_p
1568 to verify that the REG in the USE does not change between
1570 If the USE in INSN was for a pseudo register, the matching
1571 insn pattern will likely match any register; combining this
1572 with any other USE would only be safe if we knew that the
1573 used registers have identical values, or if there was
1574 something to tell them apart, e.g. different modes. For
1575 now, we forgo such complicated tests and simply disallow
1576 combining of USES of pseudo registers with any other USE. */
1577 if (REG_P (XEXP (elt, 0))
1578 && GET_CODE (PATTERN (i3)) == PARALLEL)
1580 rtx i3pat = PATTERN (i3);
1581 int i = XVECLEN (i3pat, 0) - 1;
1582 unsigned int regno = REGNO (XEXP (elt, 0));
1586 rtx i3elt = XVECEXP (i3pat, 0, i);
1588 if (GET_CODE (i3elt) == USE
1589 && REG_P (XEXP (i3elt, 0))
1590 && (REGNO (XEXP (i3elt, 0)) == regno
1591 ? reg_set_between_p (XEXP (elt, 0),
1592 PREV_INSN (insn), i3)
1593 : regno >= FIRST_PSEUDO_REGISTER))
1600 /* We can ignore CLOBBERs. */
1605 /* Ignore SETs whose result isn't used but not those that
1606 have side-effects. */
1607 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1608 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1609 || INTVAL (XEXP (note, 0)) <= 0)
1610 && ! side_effects_p (elt))
1613 /* If we have already found a SET, this is a second one and
1614 so we cannot combine with this insn. */
1622 /* Anything else means we can't combine. */
1628 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1629 so don't do anything with it. */
1630 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1639 set = expand_field_assignment (set);
1640 src = SET_SRC (set), dest = SET_DEST (set);
1642 /* Don't eliminate a store in the stack pointer. */
1643 if (dest == stack_pointer_rtx
1644 /* Don't combine with an insn that sets a register to itself if it has
1645 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1646 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1647 /* Can't merge an ASM_OPERANDS. */
1648 || GET_CODE (src) == ASM_OPERANDS
1649 /* Can't merge a function call. */
1650 || GET_CODE (src) == CALL
1651 /* Don't eliminate a function call argument. */
1653 && (find_reg_fusage (i3, USE, dest)
1655 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1656 && global_regs[REGNO (dest)])))
1657 /* Don't substitute into an incremented register. */
1658 || FIND_REG_INC_NOTE (i3, dest)
1659 || (succ && FIND_REG_INC_NOTE (succ, dest))
1660 /* Don't substitute into a non-local goto, this confuses CFG. */
1661 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1662 /* Make sure that DEST is not used after SUCC but before I3. */
1663 || (succ && ! all_adjacent
1664 && reg_used_between_p (dest, succ, i3))
1665 /* Make sure that the value that is to be substituted for the register
1666 does not use any registers whose values alter in between. However,
1667 If the insns are adjacent, a use can't cross a set even though we
1668 think it might (this can happen for a sequence of insns each setting
1669 the same destination; last_set of that register might point to
1670 a NOTE). If INSN has a REG_EQUIV note, the register is always
1671 equivalent to the memory so the substitution is valid even if there
1672 are intervening stores. Also, don't move a volatile asm or
1673 UNSPEC_VOLATILE across any other insns. */
1676 || ! find_reg_note (insn, REG_EQUIV, src))
1677 && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1678 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1679 || GET_CODE (src) == UNSPEC_VOLATILE))
1680 /* Don't combine across a CALL_INSN, because that would possibly
1681 change whether the life span of some REGs crosses calls or not,
1682 and it is a pain to update that information.
1683 Exception: if source is a constant, moving it later can't hurt.
1684 Accept that as a special case. */
1685 || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1688 /* DEST must either be a REG or CC0. */
1691 /* If register alignment is being enforced for multi-word items in all
1692 cases except for parameters, it is possible to have a register copy
1693 insn referencing a hard register that is not allowed to contain the
1694 mode being copied and which would not be valid as an operand of most
1695 insns. Eliminate this problem by not combining with such an insn.
1697 Also, on some machines we don't want to extend the life of a hard
1701 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1702 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1703 /* Don't extend the life of a hard register unless it is
1704 user variable (if we have few registers) or it can't
1705 fit into the desired register (meaning something special
1707 Also avoid substituting a return register into I3, because
1708 reload can't handle a conflict with constraints of other
1710 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1711 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1714 else if (GET_CODE (dest) != CC0)
1718 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1719 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1720 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1722 /* Don't substitute for a register intended as a clobberable
1724 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1725 if (rtx_equal_p (reg, dest))
1728 /* If the clobber represents an earlyclobber operand, we must not
1729 substitute an expression containing the clobbered register.
1730 As we do not analyze the constraint strings here, we have to
1731 make the conservative assumption. However, if the register is
1732 a fixed hard reg, the clobber cannot represent any operand;
1733 we leave it up to the machine description to either accept or
1734 reject use-and-clobber patterns. */
1736 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1737 || !fixed_regs[REGNO (reg)])
1738 if (reg_overlap_mentioned_p (reg, src))
1742 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1743 or not), reject, unless nothing volatile comes between it and I3 */
1745 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1747 /* Make sure succ doesn't contain a volatile reference. */
1748 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1751 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1752 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1756 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1757 to be an explicit register variable, and was chosen for a reason. */
1759 if (GET_CODE (src) == ASM_OPERANDS
1760 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1763 /* If there are any volatile insns between INSN and I3, reject, because
1764 they might affect machine state. */
1766 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1767 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1770 /* If INSN contains an autoincrement or autodecrement, make sure that
1771 register is not used between there and I3, and not already used in
1772 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1773 Also insist that I3 not be a jump; if it were one
1774 and the incremented register were spilled, we would lose. */
1777 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1778 if (REG_NOTE_KIND (link) == REG_INC
1780 || reg_used_between_p (XEXP (link, 0), insn, i3)
1781 || (pred != NULL_RTX
1782 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1783 || (succ != NULL_RTX
1784 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1785 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1790 /* Don't combine an insn that follows a CC0-setting insn.
1791 An insn that uses CC0 must not be separated from the one that sets it.
1792 We do, however, allow I2 to follow a CC0-setting insn if that insn
1793 is passed as I1; in that case it will be deleted also.
1794 We also allow combining in this case if all the insns are adjacent
1795 because that would leave the two CC0 insns adjacent as well.
1796 It would be more logical to test whether CC0 occurs inside I1 or I2,
1797 but that would be much slower, and this ought to be equivalent. */
1799 p = prev_nonnote_insn (insn);
1800 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1805 /* If we get here, we have passed all the tests and the combination is
1814 /* LOC is the location within I3 that contains its pattern or the component
1815 of a PARALLEL of the pattern. We validate that it is valid for combining.
1817 One problem is if I3 modifies its output, as opposed to replacing it
1818 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1819 so would produce an insn that is not equivalent to the original insns.
1823 (set (reg:DI 101) (reg:DI 100))
1824 (set (subreg:SI (reg:DI 101) 0) <foo>)
1826 This is NOT equivalent to:
1828 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1829 (set (reg:DI 101) (reg:DI 100))])
1831 Not only does this modify 100 (in which case it might still be valid
1832 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1834 We can also run into a problem if I2 sets a register that I1
1835 uses and I1 gets directly substituted into I3 (not via I2). In that
1836 case, we would be getting the wrong value of I2DEST into I3, so we
1837 must reject the combination. This case occurs when I2 and I1 both
1838 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1839 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1840 of a SET must prevent combination from occurring.
1842 Before doing the above check, we first try to expand a field assignment
1843 into a set of logical operations.
1845 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1846 we place a register that is both set and used within I3. If more than one
1847 such register is detected, we fail.
1849 Return 1 if the combination is valid, zero otherwise. */
1852 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1853 int i1_not_in_src, rtx *pi3dest_killed)
1857 if (GET_CODE (x) == SET)
1860 rtx dest = SET_DEST (set);
1861 rtx src = SET_SRC (set);
1862 rtx inner_dest = dest;
1865 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1866 || GET_CODE (inner_dest) == SUBREG
1867 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1868 inner_dest = XEXP (inner_dest, 0);
1870 /* Check for the case where I3 modifies its output, as discussed
1871 above. We don't want to prevent pseudos from being combined
1872 into the address of a MEM, so only prevent the combination if
1873 i1 or i2 set the same MEM. */
1874 if ((inner_dest != dest &&
1875 (!MEM_P (inner_dest)
1876 || rtx_equal_p (i2dest, inner_dest)
1877 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1878 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1879 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1881 /* This is the same test done in can_combine_p except we can't test
1882 all_adjacent; we don't have to, since this instruction will stay
1883 in place, thus we are not considering increasing the lifetime of
1886 Also, if this insn sets a function argument, combining it with
1887 something that might need a spill could clobber a previous
1888 function argument; the all_adjacent test in can_combine_p also
1889 checks this; here, we do a more specific test for this case. */
1891 || (REG_P (inner_dest)
1892 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1893 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1894 GET_MODE (inner_dest))))
1895 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1898 /* If DEST is used in I3, it is being killed in this insn, so
1899 record that for later. We have to consider paradoxical
1900 subregs here, since they kill the whole register, but we
1901 ignore partial subregs, STRICT_LOW_PART, etc.
1902 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1903 STACK_POINTER_REGNUM, since these are always considered to be
1904 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1906 if (GET_CODE (subdest) == SUBREG
1907 && (GET_MODE_SIZE (GET_MODE (subdest))
1908 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1909 subdest = SUBREG_REG (subdest);
1912 && reg_referenced_p (subdest, PATTERN (i3))
1913 && REGNO (subdest) != FRAME_POINTER_REGNUM
1914 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1915 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1917 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1918 && (REGNO (subdest) != ARG_POINTER_REGNUM
1919 || ! fixed_regs [REGNO (subdest)])
1921 && REGNO (subdest) != STACK_POINTER_REGNUM)
1923 if (*pi3dest_killed)
1926 *pi3dest_killed = subdest;
1930 else if (GET_CODE (x) == PARALLEL)
1934 for (i = 0; i < XVECLEN (x, 0); i++)
1935 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1936 i1_not_in_src, pi3dest_killed))
1943 /* Return 1 if X is an arithmetic expression that contains a multiplication
1944 and division. We don't count multiplications by powers of two here. */
1947 contains_muldiv (rtx x)
1949 switch (GET_CODE (x))
1951 case MOD: case DIV: case UMOD: case UDIV:
1955 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1956 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1959 return contains_muldiv (XEXP (x, 0))
1960 || contains_muldiv (XEXP (x, 1));
1963 return contains_muldiv (XEXP (x, 0));
1969 /* Determine whether INSN can be used in a combination. Return nonzero if
1970 not. This is used in try_combine to detect early some cases where we
1971 can't perform combinations. */
1974 cant_combine_insn_p (rtx insn)
1979 /* If this isn't really an insn, we can't do anything.
1980 This can occur when flow deletes an insn that it has merged into an
1981 auto-increment address. */
1982 if (! INSN_P (insn))
1985 /* Never combine loads and stores involving hard regs that are likely
1986 to be spilled. The register allocator can usually handle such
1987 reg-reg moves by tying. If we allow the combiner to make
1988 substitutions of likely-spilled regs, reload might die.
1989 As an exception, we allow combinations involving fixed regs; these are
1990 not available to the register allocator so there's no risk involved. */
1992 set = single_set (insn);
1995 src = SET_SRC (set);
1996 dest = SET_DEST (set);
1997 if (GET_CODE (src) == SUBREG)
1998 src = SUBREG_REG (src);
1999 if (GET_CODE (dest) == SUBREG)
2000 dest = SUBREG_REG (dest);
2001 if (REG_P (src) && REG_P (dest)
2002 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
2003 && ! fixed_regs[REGNO (src)]
2004 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
2005 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
2006 && ! fixed_regs[REGNO (dest)]
2007 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
2013 struct likely_spilled_retval_info
2015 unsigned regno, nregs;
2019 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2020 hard registers that are known to be written to / clobbered in full. */
2022 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2024 struct likely_spilled_retval_info *const info =
2025 (struct likely_spilled_retval_info *) data;
2026 unsigned regno, nregs;
2029 if (!REG_P (XEXP (set, 0)))
2032 if (regno >= info->regno + info->nregs)
2034 nregs = hard_regno_nregs[regno][GET_MODE (x)];
2035 if (regno + nregs <= info->regno)
2037 new_mask = (2U << (nregs - 1)) - 1;
2038 if (regno < info->regno)
2039 new_mask >>= info->regno - regno;
2041 new_mask <<= regno - info->regno;
2042 info->mask &= ~new_mask;
2045 /* Return nonzero iff part of the return value is live during INSN, and
2046 it is likely spilled. This can happen when more than one insn is needed
2047 to copy the return value, e.g. when we consider to combine into the
2048 second copy insn for a complex value. */
2051 likely_spilled_retval_p (rtx insn)
2053 rtx use = BB_END (this_basic_block);
2055 unsigned regno, nregs;
2056 /* We assume here that no machine mode needs more than
2057 32 hard registers when the value overlaps with a register
2058 for which FUNCTION_VALUE_REGNO_P is true. */
2060 struct likely_spilled_retval_info info;
2062 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2064 reg = XEXP (PATTERN (use), 0);
2065 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
2067 regno = REGNO (reg);
2068 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2071 mask = (2U << (nregs - 1)) - 1;
2073 /* Disregard parts of the return value that are set later. */
2077 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2079 note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2082 /* Check if any of the (probably) live return value registers is
2087 if ((mask & 1 << nregs)
2088 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
2094 /* Adjust INSN after we made a change to its destination.
2096 Changing the destination can invalidate notes that say something about
2097 the results of the insn and a LOG_LINK pointing to the insn. */
2100 adjust_for_new_dest (rtx insn)
2102 /* For notes, be conservative and simply remove them. */
2103 remove_reg_equal_equiv_notes (insn);
2105 /* The new insn will have a destination that was previously the destination
2106 of an insn just above it. Call distribute_links to make a LOG_LINK from
2107 the next use of that destination. */
2108 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
2110 df_insn_rescan (insn);
2113 /* Return TRUE if combine can reuse reg X in mode MODE.
2114 ADDED_SETS is nonzero if the original set is still required. */
2116 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2124 /* Allow hard registers if the new mode is legal, and occupies no more
2125 registers than the old mode. */
2126 if (regno < FIRST_PSEUDO_REGISTER)
2127 return (HARD_REGNO_MODE_OK (regno, mode)
2128 && (hard_regno_nregs[regno][GET_MODE (x)]
2129 >= hard_regno_nregs[regno][mode]));
2131 /* Or a pseudo that is only used once. */
2132 return (REG_N_SETS (regno) == 1 && !added_sets
2133 && !REG_USERVAR_P (x));
2137 /* Check whether X, the destination of a set, refers to part of
2138 the register specified by REG. */
2141 reg_subword_p (rtx x, rtx reg)
2143 /* Check that reg is an integer mode register. */
2144 if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2147 if (GET_CODE (x) == STRICT_LOW_PART
2148 || GET_CODE (x) == ZERO_EXTRACT)
2151 return GET_CODE (x) == SUBREG
2152 && SUBREG_REG (x) == reg
2153 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2157 /* Try to combine the insns I1 and I2 into I3.
2158 Here I1 and I2 appear earlier than I3.
2159 I1 can be zero; then we combine just I2 into I3.
2161 If we are combining three insns and the resulting insn is not recognized,
2162 try splitting it into two insns. If that happens, I2 and I3 are retained
2163 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
2166 Return 0 if the combination does not work. Then nothing is changed.
2167 If we did the combination, return the insn at which combine should
2170 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2171 new direct jump instruction. */
2174 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
2176 /* New patterns for I3 and I2, respectively. */
2177 rtx newpat, newi2pat = 0;
2178 rtvec newpat_vec_with_clobbers = 0;
2179 int substed_i2 = 0, substed_i1 = 0;
2180 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
2181 int added_sets_1, added_sets_2;
2182 /* Total number of SETs to put into I3. */
2184 /* Nonzero if I2's body now appears in I3. */
2186 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2187 int insn_code_number, i2_code_number = 0, other_code_number = 0;
2188 /* Contains I3 if the destination of I3 is used in its source, which means
2189 that the old life of I3 is being killed. If that usage is placed into
2190 I2 and not in I3, a REG_DEAD note must be made. */
2191 rtx i3dest_killed = 0;
2192 /* SET_DEST and SET_SRC of I2 and I1. */
2193 rtx i2dest, i2src, i1dest = 0, i1src = 0;
2194 /* PATTERN (I1) and PATTERN (I2), or a copy of it in certain cases. */
2195 rtx i1pat = 0, i2pat = 0;
2196 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2197 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2198 int i2dest_killed = 0, i1dest_killed = 0;
2199 int i1_feeds_i3 = 0;
2200 /* Notes that must be added to REG_NOTES in I3 and I2. */
2201 rtx new_i3_notes, new_i2_notes;
2202 /* Notes that we substituted I3 into I2 instead of the normal case. */
2203 int i3_subst_into_i2 = 0;
2204 /* Notes that I1, I2 or I3 is a MULT operation. */
2212 rtx new_other_notes;
2215 /* Exit early if one of the insns involved can't be used for
2217 if (cant_combine_insn_p (i3)
2218 || cant_combine_insn_p (i2)
2219 || (i1 && cant_combine_insn_p (i1))
2220 || likely_spilled_retval_p (i3))
2224 undobuf.other_insn = 0;
2226 /* Reset the hard register usage information. */
2227 CLEAR_HARD_REG_SET (newpat_used_regs);
2229 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
2230 code below, set I1 to be the earlier of the two insns. */
2231 if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2232 temp = i1, i1 = i2, i2 = temp;
2234 added_links_insn = 0;
2236 /* First check for one important special-case that the code below will
2237 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2238 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2239 we may be able to replace that destination with the destination of I3.
2240 This occurs in the common code where we compute both a quotient and
2241 remainder into a structure, in which case we want to do the computation
2242 directly into the structure to avoid register-register copies.
2244 Note that this case handles both multiple sets in I2 and also
2245 cases where I2 has a number of CLOBBER or PARALLELs.
2247 We make very conservative checks below and only try to handle the
2248 most common cases of this. For example, we only handle the case
2249 where I2 and I3 are adjacent to avoid making difficult register
2252 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2253 && REG_P (SET_SRC (PATTERN (i3)))
2254 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2255 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2256 && GET_CODE (PATTERN (i2)) == PARALLEL
2257 && ! side_effects_p (SET_DEST (PATTERN (i3)))
2258 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2259 below would need to check what is inside (and reg_overlap_mentioned_p
2260 doesn't support those codes anyway). Don't allow those destinations;
2261 the resulting insn isn't likely to be recognized anyway. */
2262 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2263 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2264 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2265 SET_DEST (PATTERN (i3)))
2266 && next_real_insn (i2) == i3)
2268 rtx p2 = PATTERN (i2);
2270 /* Make sure that the destination of I3,
2271 which we are going to substitute into one output of I2,
2272 is not used within another output of I2. We must avoid making this:
2273 (parallel [(set (mem (reg 69)) ...)
2274 (set (reg 69) ...)])
2275 which is not well-defined as to order of actions.
2276 (Besides, reload can't handle output reloads for this.)
2278 The problem can also happen if the dest of I3 is a memory ref,
2279 if another dest in I2 is an indirect memory ref. */
2280 for (i = 0; i < XVECLEN (p2, 0); i++)
2281 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2282 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2283 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2284 SET_DEST (XVECEXP (p2, 0, i))))
2287 if (i == XVECLEN (p2, 0))
2288 for (i = 0; i < XVECLEN (p2, 0); i++)
2289 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2290 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2291 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2296 subst_low_luid = DF_INSN_LUID (i2);
2298 added_sets_2 = added_sets_1 = 0;
2299 i2dest = SET_SRC (PATTERN (i3));
2300 i2dest_killed = dead_or_set_p (i2, i2dest);
2302 /* Replace the dest in I2 with our dest and make the resulting
2303 insn the new pattern for I3. Then skip to where we
2304 validate the pattern. Everything was set up above. */
2305 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
2306 SET_DEST (PATTERN (i3)));
2309 i3_subst_into_i2 = 1;
2310 goto validate_replacement;
2314 /* If I2 is setting a pseudo to a constant and I3 is setting some
2315 sub-part of it to another constant, merge them by making a new
2318 && (temp = single_set (i2)) != 0
2319 && (GET_CODE (SET_SRC (temp)) == CONST_INT
2320 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2321 && GET_CODE (PATTERN (i3)) == SET
2322 && (GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT
2323 || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2324 && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2326 rtx dest = SET_DEST (PATTERN (i3));
2330 if (GET_CODE (dest) == ZERO_EXTRACT)
2332 if (GET_CODE (XEXP (dest, 1)) == CONST_INT
2333 && GET_CODE (XEXP (dest, 2)) == CONST_INT)
2335 width = INTVAL (XEXP (dest, 1));
2336 offset = INTVAL (XEXP (dest, 2));
2337 dest = XEXP (dest, 0);
2338 if (BITS_BIG_ENDIAN)
2339 offset = GET_MODE_BITSIZE (GET_MODE (dest)) - width - offset;
2344 if (GET_CODE (dest) == STRICT_LOW_PART)
2345 dest = XEXP (dest, 0);
2346 width = GET_MODE_BITSIZE (GET_MODE (dest));
2352 /* If this is the low part, we're done. */
2353 if (subreg_lowpart_p (dest))
2355 /* Handle the case where inner is twice the size of outer. */
2356 else if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2357 == 2 * GET_MODE_BITSIZE (GET_MODE (dest)))
2358 offset += GET_MODE_BITSIZE (GET_MODE (dest));
2359 /* Otherwise give up for now. */
2365 && (GET_MODE_BITSIZE (GET_MODE (SET_DEST (temp)))
2366 <= HOST_BITS_PER_WIDE_INT * 2))
2368 HOST_WIDE_INT mhi, ohi, ihi;
2369 HOST_WIDE_INT mlo, olo, ilo;
2370 rtx inner = SET_SRC (PATTERN (i3));
2371 rtx outer = SET_SRC (temp);
2373 if (GET_CODE (outer) == CONST_INT)
2375 olo = INTVAL (outer);
2376 ohi = olo < 0 ? -1 : 0;
2380 olo = CONST_DOUBLE_LOW (outer);
2381 ohi = CONST_DOUBLE_HIGH (outer);
2384 if (GET_CODE (inner) == CONST_INT)
2386 ilo = INTVAL (inner);
2387 ihi = ilo < 0 ? -1 : 0;
2391 ilo = CONST_DOUBLE_LOW (inner);
2392 ihi = CONST_DOUBLE_HIGH (inner);
2395 if (width < HOST_BITS_PER_WIDE_INT)
2397 mlo = ((unsigned HOST_WIDE_INT) 1 << width) - 1;
2400 else if (width < HOST_BITS_PER_WIDE_INT * 2)
2402 mhi = ((unsigned HOST_WIDE_INT) 1
2403 << (width - HOST_BITS_PER_WIDE_INT)) - 1;
2415 if (offset >= HOST_BITS_PER_WIDE_INT)
2417 mhi = mlo << (offset - HOST_BITS_PER_WIDE_INT);
2419 ihi = ilo << (offset - HOST_BITS_PER_WIDE_INT);
2422 else if (offset > 0)
2424 mhi = (mhi << offset) | ((unsigned HOST_WIDE_INT) mlo
2425 >> (HOST_BITS_PER_WIDE_INT - offset));
2426 mlo = mlo << offset;
2427 ihi = (ihi << offset) | ((unsigned HOST_WIDE_INT) ilo
2428 >> (HOST_BITS_PER_WIDE_INT - offset));
2429 ilo = ilo << offset;
2432 olo = (olo & ~mlo) | ilo;
2433 ohi = (ohi & ~mhi) | ihi;
2437 subst_low_luid = DF_INSN_LUID (i2);
2438 added_sets_2 = added_sets_1 = 0;
2439 i2dest = SET_DEST (temp);
2440 i2dest_killed = dead_or_set_p (i2, i2dest);
2442 SUBST (SET_SRC (temp),
2443 immed_double_const (olo, ohi, GET_MODE (SET_DEST (temp))));
2445 newpat = PATTERN (i2);
2446 goto validate_replacement;
2451 /* If we have no I1 and I2 looks like:
2452 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2454 make up a dummy I1 that is
2457 (set (reg:CC X) (compare:CC Y (const_int 0)))
2459 (We can ignore any trailing CLOBBERs.)
2461 This undoes a previous combination and allows us to match a branch-and-
2464 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2465 && XVECLEN (PATTERN (i2), 0) >= 2
2466 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2467 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2469 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2470 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2471 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2472 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2473 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2474 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2476 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2477 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2482 /* We make I1 with the same INSN_UID as I2. This gives it
2483 the same DF_INSN_LUID for value tracking. Our fake I1 will
2484 never appear in the insn stream so giving it the same INSN_UID
2485 as I2 will not cause a problem. */
2487 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2488 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
2489 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX);
2491 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2492 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2493 SET_DEST (PATTERN (i1)));
2498 /* Verify that I2 and I1 are valid for combining. */
2499 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
2500 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
2506 /* Record whether I2DEST is used in I2SRC and similarly for the other
2507 cases. Knowing this will help in register status updating below. */
2508 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2509 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2510 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2511 i2dest_killed = dead_or_set_p (i2, i2dest);
2512 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2514 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2516 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2518 /* Ensure that I3's pattern can be the destination of combines. */
2519 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2520 i1 && i2dest_in_i1src && i1_feeds_i3,
2527 /* See if any of the insns is a MULT operation. Unless one is, we will
2528 reject a combination that is, since it must be slower. Be conservative
2530 if (GET_CODE (i2src) == MULT
2531 || (i1 != 0 && GET_CODE (i1src) == MULT)
2532 || (GET_CODE (PATTERN (i3)) == SET
2533 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2536 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2537 We used to do this EXCEPT in one case: I3 has a post-inc in an
2538 output operand. However, that exception can give rise to insns like
2540 which is a famous insn on the PDP-11 where the value of r3 used as the
2541 source was model-dependent. Avoid this sort of thing. */
2544 if (!(GET_CODE (PATTERN (i3)) == SET
2545 && REG_P (SET_SRC (PATTERN (i3)))
2546 && MEM_P (SET_DEST (PATTERN (i3)))
2547 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2548 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2549 /* It's not the exception. */
2552 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2553 if (REG_NOTE_KIND (link) == REG_INC
2554 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2556 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2563 /* See if the SETs in I1 or I2 need to be kept around in the merged
2564 instruction: whenever the value set there is still needed past I3.
2565 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2567 For the SET in I1, we have two cases: If I1 and I2 independently
2568 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2569 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2570 in I1 needs to be kept around unless I1DEST dies or is set in either
2571 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2572 I1DEST. If so, we know I1 feeds into I2. */
2574 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2577 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2578 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2580 /* If the set in I2 needs to be kept around, we must make a copy of
2581 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2582 PATTERN (I2), we are only substituting for the original I1DEST, not into
2583 an already-substituted copy. This also prevents making self-referential
2584 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2589 if (GET_CODE (PATTERN (i2)) == PARALLEL)
2590 i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2592 i2pat = copy_rtx (PATTERN (i2));
2597 if (GET_CODE (PATTERN (i1)) == PARALLEL)
2598 i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2600 i1pat = copy_rtx (PATTERN (i1));
2605 /* Substitute in the latest insn for the regs set by the earlier ones. */
2607 maxreg = max_reg_num ();
2612 /* Many machines that don't use CC0 have insns that can both perform an
2613 arithmetic operation and set the condition code. These operations will
2614 be represented as a PARALLEL with the first element of the vector
2615 being a COMPARE of an arithmetic operation with the constant zero.
2616 The second element of the vector will set some pseudo to the result
2617 of the same arithmetic operation. If we simplify the COMPARE, we won't
2618 match such a pattern and so will generate an extra insn. Here we test
2619 for this case, where both the comparison and the operation result are
2620 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2621 I2SRC. Later we will make the PARALLEL that contains I2. */
2623 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2624 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2625 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2626 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2628 #ifdef SELECT_CC_MODE
2630 enum machine_mode compare_mode;
2633 newpat = PATTERN (i3);
2634 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2638 #ifdef SELECT_CC_MODE
2639 /* See if a COMPARE with the operand we substituted in should be done
2640 with the mode that is currently being used. If not, do the same
2641 processing we do in `subst' for a SET; namely, if the destination
2642 is used only once, try to replace it with a register of the proper
2643 mode and also replace the COMPARE. */
2644 if (undobuf.other_insn == 0
2645 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2646 &undobuf.other_insn))
2647 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2649 != GET_MODE (SET_DEST (newpat))))
2651 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2654 unsigned int regno = REGNO (SET_DEST (newpat));
2657 if (regno < FIRST_PSEUDO_REGISTER)
2658 new_dest = gen_rtx_REG (compare_mode, regno);
2661 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
2662 new_dest = regno_reg_rtx[regno];
2665 SUBST (SET_DEST (newpat), new_dest);
2666 SUBST (XEXP (*cc_use, 0), new_dest);
2667 SUBST (SET_SRC (newpat),
2668 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2671 undobuf.other_insn = 0;
2678 /* It is possible that the source of I2 or I1 may be performing
2679 an unneeded operation, such as a ZERO_EXTEND of something
2680 that is known to have the high part zero. Handle that case
2681 by letting subst look at the innermost one of them.
2683 Another way to do this would be to have a function that tries
2684 to simplify a single insn instead of merging two or more
2685 insns. We don't do this because of the potential of infinite
2686 loops and because of the potential extra memory required.
2687 However, doing it the way we are is a bit of a kludge and
2688 doesn't catch all cases.
2690 But only do this if -fexpensive-optimizations since it slows
2691 things down and doesn't usually win.
2693 This is not done in the COMPARE case above because the
2694 unmodified I2PAT is used in the PARALLEL and so a pattern
2695 with a modified I2SRC would not match. */
2697 if (flag_expensive_optimizations)
2699 /* Pass pc_rtx so no substitutions are done, just
2703 subst_low_luid = DF_INSN_LUID (i1);
2704 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2708 subst_low_luid = DF_INSN_LUID (i2);
2709 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2713 n_occurrences = 0; /* `subst' counts here */
2715 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2716 need to make a unique copy of I2SRC each time we substitute it
2717 to avoid self-referential rtl. */
2719 subst_low_luid = DF_INSN_LUID (i2);
2720 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2721 ! i1_feeds_i3 && i1dest_in_i1src);
2724 /* Record whether i2's body now appears within i3's body. */
2725 i2_is_used = n_occurrences;
2728 /* If we already got a failure, don't try to do more. Otherwise,
2729 try to substitute in I1 if we have it. */
2731 if (i1 && GET_CODE (newpat) != CLOBBER)
2733 /* Check that an autoincrement side-effect on I1 has not been lost.
2734 This happens if I1DEST is mentioned in I2 and dies there, and
2735 has disappeared from the new pattern. */
2736 if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2738 && dead_or_set_p (i2, i1dest)
2739 && !reg_overlap_mentioned_p (i1dest, newpat))
2740 /* Before we can do this substitution, we must redo the test done
2741 above (see detailed comments there) that ensures that I1DEST
2742 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2743 || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, 0, 0))
2750 subst_low_luid = DF_INSN_LUID (i1);
2751 newpat = subst (newpat, i1dest, i1src, 0, 0);
2755 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2756 to count all the ways that I2SRC and I1SRC can be used. */
2757 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2758 && i2_is_used + added_sets_2 > 1)
2759 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2760 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2762 /* Fail if we tried to make a new register. */
2763 || max_reg_num () != maxreg
2764 /* Fail if we couldn't do something and have a CLOBBER. */
2765 || GET_CODE (newpat) == CLOBBER
2766 /* Fail if this new pattern is a MULT and we didn't have one before
2767 at the outer level. */
2768 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2775 /* If the actions of the earlier insns must be kept
2776 in addition to substituting them into the latest one,
2777 we must make a new PARALLEL for the latest insn
2778 to hold additional the SETs. */
2780 if (added_sets_1 || added_sets_2)
2784 if (GET_CODE (newpat) == PARALLEL)
2786 rtvec old = XVEC (newpat, 0);
2787 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2788 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2789 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2790 sizeof (old->elem[0]) * old->num_elem);
2795 total_sets = 1 + added_sets_1 + added_sets_2;
2796 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2797 XVECEXP (newpat, 0, 0) = old;
2801 XVECEXP (newpat, 0, --total_sets) = i1pat;
2805 /* If there is no I1, use I2's body as is. We used to also not do
2806 the subst call below if I2 was substituted into I3,
2807 but that could lose a simplification. */
2809 XVECEXP (newpat, 0, --total_sets) = i2pat;
2811 /* See comment where i2pat is assigned. */
2812 XVECEXP (newpat, 0, --total_sets)
2813 = subst (i2pat, i1dest, i1src, 0, 0);
2817 /* We come here when we are replacing a destination in I2 with the
2818 destination of I3. */
2819 validate_replacement:
2821 /* Note which hard regs this insn has as inputs. */
2822 mark_used_regs_combine (newpat);
2824 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2825 consider splitting this pattern, we might need these clobbers. */
2826 if (i1 && GET_CODE (newpat) == PARALLEL
2827 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2829 int len = XVECLEN (newpat, 0);
2831 newpat_vec_with_clobbers = rtvec_alloc (len);
2832 for (i = 0; i < len; i++)
2833 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2836 /* Is the result of combination a valid instruction? */
2837 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2839 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2840 the second SET's destination is a register that is unused and isn't
2841 marked as an instruction that might trap in an EH region. In that case,
2842 we just need the first SET. This can occur when simplifying a divmod
2843 insn. We *must* test for this case here because the code below that
2844 splits two independent SETs doesn't handle this case correctly when it
2845 updates the register status.
2847 It's pointless doing this if we originally had two sets, one from
2848 i3, and one from i2. Combining then splitting the parallel results
2849 in the original i2 again plus an invalid insn (which we delete).
2850 The net effect is only to move instructions around, which makes
2851 debug info less accurate.
2853 Also check the case where the first SET's destination is unused.
2854 That would not cause incorrect code, but does cause an unneeded
2857 if (insn_code_number < 0
2858 && !(added_sets_2 && i1 == 0)
2859 && GET_CODE (newpat) == PARALLEL
2860 && XVECLEN (newpat, 0) == 2
2861 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2862 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2863 && asm_noperands (newpat) < 0)
2865 rtx set0 = XVECEXP (newpat, 0, 0);
2866 rtx set1 = XVECEXP (newpat, 0, 1);
2869 if (((REG_P (SET_DEST (set1))
2870 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2871 || (GET_CODE (SET_DEST (set1)) == SUBREG
2872 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2873 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2874 || INTVAL (XEXP (note, 0)) <= 0)
2875 && ! side_effects_p (SET_SRC (set1)))
2878 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2881 else if (((REG_P (SET_DEST (set0))
2882 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2883 || (GET_CODE (SET_DEST (set0)) == SUBREG
2884 && find_reg_note (i3, REG_UNUSED,
2885 SUBREG_REG (SET_DEST (set0)))))
2886 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2887 || INTVAL (XEXP (note, 0)) <= 0)
2888 && ! side_effects_p (SET_SRC (set0)))
2891 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2893 if (insn_code_number >= 0)
2895 /* If we will be able to accept this, we have made a
2896 change to the destination of I3. This requires us to
2897 do a few adjustments. */
2899 PATTERN (i3) = newpat;
2900 adjust_for_new_dest (i3);
2905 /* If we were combining three insns and the result is a simple SET
2906 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2907 insns. There are two ways to do this. It can be split using a
2908 machine-specific method (like when you have an addition of a large
2909 constant) or by combine in the function find_split_point. */
2911 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2912 && asm_noperands (newpat) < 0)
2914 rtx parallel, m_split, *split;
2916 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2917 use I2DEST as a scratch register will help. In the latter case,
2918 convert I2DEST to the mode of the source of NEWPAT if we can. */
2920 m_split = combine_split_insns (newpat, i3);
2922 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2923 inputs of NEWPAT. */
2925 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2926 possible to try that as a scratch reg. This would require adding
2927 more code to make it work though. */
2929 if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
2931 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2933 /* First try to split using the original register as a
2934 scratch register. */
2935 parallel = gen_rtx_PARALLEL (VOIDmode,
2936 gen_rtvec (2, newpat,
2937 gen_rtx_CLOBBER (VOIDmode,
2939 m_split = combine_split_insns (parallel, i3);
2941 /* If that didn't work, try changing the mode of I2DEST if
2944 && new_mode != GET_MODE (i2dest)
2945 && new_mode != VOIDmode
2946 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2948 enum machine_mode old_mode = GET_MODE (i2dest);
2951 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
2952 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
2955 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
2956 ni2dest = regno_reg_rtx[REGNO (i2dest)];
2959 parallel = (gen_rtx_PARALLEL
2961 gen_rtvec (2, newpat,
2962 gen_rtx_CLOBBER (VOIDmode,
2964 m_split = combine_split_insns (parallel, i3);
2967 && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2971 adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
2972 buf = undobuf.undos;
2973 undobuf.undos = buf->next;
2974 buf->next = undobuf.frees;
2975 undobuf.frees = buf;
2980 /* If recog_for_combine has discarded clobbers, try to use them
2981 again for the split. */
2982 if (m_split == 0 && newpat_vec_with_clobbers)
2984 parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
2985 m_split = combine_split_insns (parallel, i3);
2988 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2990 m_split = PATTERN (m_split);
2991 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2992 if (insn_code_number >= 0)
2995 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2996 && (next_real_insn (i2) == i3
2997 || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3000 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3001 newi2pat = PATTERN (m_split);
3003 i3set = single_set (NEXT_INSN (m_split));
3004 i2set = single_set (m_split);
3006 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3008 /* If I2 or I3 has multiple SETs, we won't know how to track
3009 register status, so don't use these insns. If I2's destination
3010 is used between I2 and I3, we also can't use these insns. */
3012 if (i2_code_number >= 0 && i2set && i3set
3013 && (next_real_insn (i2) == i3
3014 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3015 insn_code_number = recog_for_combine (&newi3pat, i3,
3017 if (insn_code_number >= 0)
3020 /* It is possible that both insns now set the destination of I3.
3021 If so, we must show an extra use of it. */
3023 if (insn_code_number >= 0)
3025 rtx new_i3_dest = SET_DEST (i3set);
3026 rtx new_i2_dest = SET_DEST (i2set);
3028 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3029 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3030 || GET_CODE (new_i3_dest) == SUBREG)
3031 new_i3_dest = XEXP (new_i3_dest, 0);
3033 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3034 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3035 || GET_CODE (new_i2_dest) == SUBREG)
3036 new_i2_dest = XEXP (new_i2_dest, 0);
3038 if (REG_P (new_i3_dest)
3039 && REG_P (new_i2_dest)
3040 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3041 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3045 /* If we can split it and use I2DEST, go ahead and see if that
3046 helps things be recognized. Verify that none of the registers
3047 are set between I2 and I3. */
3048 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
3052 /* We need I2DEST in the proper mode. If it is a hard register
3053 or the only use of a pseudo, we can change its mode.
3054 Make sure we don't change a hard register to have a mode that
3055 isn't valid for it, or change the number of registers. */
3056 && (GET_MODE (*split) == GET_MODE (i2dest)
3057 || GET_MODE (*split) == VOIDmode
3058 || can_change_dest_mode (i2dest, added_sets_2,
3060 && (next_real_insn (i2) == i3
3061 || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3062 /* We can't overwrite I2DEST if its value is still used by
3064 && ! reg_referenced_p (i2dest, newpat))
3066 rtx newdest = i2dest;
3067 enum rtx_code split_code = GET_CODE (*split);
3068 enum machine_mode split_mode = GET_MODE (*split);
3069 bool subst_done = false;
3070 newi2pat = NULL_RTX;
3072 /* Get NEWDEST as a register in the proper mode. We have already
3073 validated that we can do this. */
3074 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3076 if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3077 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3080 SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3081 newdest = regno_reg_rtx[REGNO (i2dest)];
3085 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3086 an ASHIFT. This can occur if it was inside a PLUS and hence
3087 appeared to be a memory address. This is a kludge. */
3088 if (split_code == MULT
3089 && GET_CODE (XEXP (*split, 1)) == CONST_INT
3090 && INTVAL (XEXP (*split, 1)) > 0
3091 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
3093 SUBST (*split, gen_rtx_ASHIFT (split_mode,
3094 XEXP (*split, 0), GEN_INT (i)));
3095 /* Update split_code because we may not have a multiply
3097 split_code = GET_CODE (*split);
3100 #ifdef INSN_SCHEDULING
3101 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3102 be written as a ZERO_EXTEND. */
3103 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3105 #ifdef LOAD_EXTEND_OP
3106 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3107 what it really is. */
3108 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3110 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3111 SUBREG_REG (*split)));
3114 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3115 SUBREG_REG (*split)));
3119 /* Attempt to split binary operators using arithmetic identities. */
3120 if (BINARY_P (SET_SRC (newpat))
3121 && split_mode == GET_MODE (SET_SRC (newpat))
3122 && ! side_effects_p (SET_SRC (newpat)))
3124 rtx setsrc = SET_SRC (newpat);
3125 enum machine_mode mode = GET_MODE (setsrc);
3126 enum rtx_code code = GET_CODE (setsrc);
3127 rtx src_op0 = XEXP (setsrc, 0);
3128 rtx src_op1 = XEXP (setsrc, 1);
3130 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3131 if (rtx_equal_p (src_op0, src_op1))
3133 newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3134 SUBST (XEXP (setsrc, 0), newdest);
3135 SUBST (XEXP (setsrc, 1), newdest);
3138 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3139 else if ((code == PLUS || code == MULT)
3140 && GET_CODE (src_op0) == code
3141 && GET_CODE (XEXP (src_op0, 0)) == code
3142 && (INTEGRAL_MODE_P (mode)
3143 || (FLOAT_MODE_P (mode)
3144 && flag_unsafe_math_optimizations)))
3146 rtx p = XEXP (XEXP (src_op0, 0), 0);
3147 rtx q = XEXP (XEXP (src_op0, 0), 1);
3148 rtx r = XEXP (src_op0, 1);
3151 /* Split both "((X op Y) op X) op Y" and
3152 "((X op Y) op Y) op X" as "T op T" where T is
3154 if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3155 || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3157 newi2pat = gen_rtx_SET (VOIDmode, newdest,
3159 SUBST (XEXP (setsrc, 0), newdest);
3160 SUBST (XEXP (setsrc, 1), newdest);
3163 /* Split "((X op X) op Y) op Y)" as "T op T" where
3165 else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3167 rtx tmp = simplify_gen_binary (code, mode, p, r);
3168 newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3169 SUBST (XEXP (setsrc, 0), newdest);
3170 SUBST (XEXP (setsrc, 1), newdest);
3178 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3179 SUBST (*split, newdest);
3182 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3184 /* recog_for_combine might have added CLOBBERs to newi2pat.
3185 Make sure NEWPAT does not depend on the clobbered regs. */
3186 if (GET_CODE (newi2pat) == PARALLEL)
3187 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3188 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3190 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3191 if (reg_overlap_mentioned_p (reg, newpat))
3198 /* If the split point was a MULT and we didn't have one before,
3199 don't use one now. */
3200 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3201 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3205 /* Check for a case where we loaded from memory in a narrow mode and
3206 then sign extended it, but we need both registers. In that case,
3207 we have a PARALLEL with both loads from the same memory location.
3208 We can split this into a load from memory followed by a register-register
3209 copy. This saves at least one insn, more if register allocation can
3212 We cannot do this if the destination of the first assignment is a
3213 condition code register or cc0. We eliminate this case by making sure
3214 the SET_DEST and SET_SRC have the same mode.
3216 We cannot do this if the destination of the second assignment is
3217 a register that we have already assumed is zero-extended. Similarly
3218 for a SUBREG of such a register. */
3220 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3221 && GET_CODE (newpat) == PARALLEL
3222 && XVECLEN (newpat, 0) == 2
3223 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3224 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3225 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3226 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3227 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3228 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3229 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3230 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3232 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3233 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3234 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3236 && VEC_index (reg_stat_type, reg_stat,
3237 REGNO (temp))->nonzero_bits != 0
3238 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3239 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3240 && (VEC_index (reg_stat_type, reg_stat,
3241 REGNO (temp))->nonzero_bits
3242 != GET_MODE_MASK (word_mode))))
3243 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3244 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3246 && VEC_index (reg_stat_type, reg_stat,
3247 REGNO (temp))->nonzero_bits != 0
3248 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
3249 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
3250 && (VEC_index (reg_stat_type, reg_stat,
3251 REGNO (temp))->nonzero_bits
3252 != GET_MODE_MASK (word_mode)))))
3253 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3254 SET_SRC (XVECEXP (newpat, 0, 1)))
3255 && ! find_reg_note (i3, REG_UNUSED,
3256 SET_DEST (XVECEXP (newpat, 0, 0))))
3260 newi2pat = XVECEXP (newpat, 0, 0);
3261 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3262 newpat = XVECEXP (newpat, 0, 1);
3263 SUBST (SET_SRC (newpat),
3264 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3265 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3267 if (i2_code_number >= 0)
3268 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3270 if (insn_code_number >= 0)
3274 /* Similarly, check for a case where we have a PARALLEL of two independent
3275 SETs but we started with three insns. In this case, we can do the sets
3276 as two separate insns. This case occurs when some SET allows two
3277 other insns to combine, but the destination of that SET is still live. */
3279 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3280 && GET_CODE (newpat) == PARALLEL
3281 && XVECLEN (newpat, 0) == 2
3282 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3283 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3284 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3285 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3286 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3287 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3288 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3290 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3291 XVECEXP (newpat, 0, 0))
3292 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3293 XVECEXP (newpat, 0, 1))
3294 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3295 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1))))
3297 /* We cannot split the parallel into two sets if both sets
3299 && ! (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3300 && reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1)))
3304 /* Normally, it doesn't matter which of the two is done first,
3305 but it does if one references cc0. In that case, it has to
3308 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
3310 newi2pat = XVECEXP (newpat, 0, 0);
3311 newpat = XVECEXP (newpat, 0, 1);
3316 newi2pat = XVECEXP (newpat, 0, 1);
3317 newpat = XVECEXP (newpat, 0, 0);
3320 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3322 if (i2_code_number >= 0)
3323 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3326 /* If it still isn't recognized, fail and change things back the way they
3328 if ((insn_code_number < 0
3329 /* Is the result a reasonable ASM_OPERANDS? */
3330 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3336 /* If we had to change another insn, make sure it is valid also. */
3337 if (undobuf.other_insn)
3339 CLEAR_HARD_REG_SET (newpat_used_regs);
3341 other_pat = PATTERN (undobuf.other_insn);
3342 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3345 if (other_code_number < 0 && ! check_asm_operands (other_pat))
3353 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3354 they are adjacent to each other or not. */
3356 rtx p = prev_nonnote_insn (i3);
3357 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3358 && sets_cc0_p (newi2pat))
3366 /* Only allow this combination if insn_rtx_costs reports that the
3367 replacement instructions are cheaper than the originals. */
3368 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat, other_pat))
3374 /* We now know that we can do this combination. Merge the insns and
3375 update the status of registers and LOG_LINKS. */
3377 if (undobuf.other_insn)
3381 PATTERN (undobuf.other_insn) = other_pat;
3383 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
3384 are still valid. Then add any non-duplicate notes added by
3385 recog_for_combine. */
3386 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3388 next = XEXP (note, 1);
3390 if (REG_NOTE_KIND (note) == REG_UNUSED
3391 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
3392 remove_note (undobuf.other_insn, note);
3395 distribute_notes (new_other_notes, undobuf.other_insn,
3396 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
3405 /* I3 now uses what used to be its destination and which is now
3406 I2's destination. This requires us to do a few adjustments. */
3407 PATTERN (i3) = newpat;
3408 adjust_for_new_dest (i3);
3410 /* We need a LOG_LINK from I3 to I2. But we used to have one,
3413 However, some later insn might be using I2's dest and have
3414 a LOG_LINK pointing at I3. We must remove this link.
3415 The simplest way to remove the link is to point it at I1,
3416 which we know will be a NOTE. */
3418 /* newi2pat is usually a SET here; however, recog_for_combine might
3419 have added some clobbers. */
3420 if (GET_CODE (newi2pat) == PARALLEL)
3421 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3423 ni2dest = SET_DEST (newi2pat);
3425 for (insn = NEXT_INSN (i3);
3426 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3427 || insn != BB_HEAD (this_basic_block->next_bb));
3428 insn = NEXT_INSN (insn))
3430 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3432 for (link = LOG_LINKS (insn); link;
3433 link = XEXP (link, 1))
3434 if (XEXP (link, 0) == i3)
3435 XEXP (link, 0) = i1;
3443 rtx i3notes, i2notes, i1notes = 0;
3444 rtx i3links, i2links, i1links = 0;
3447 /* Compute which registers we expect to eliminate. newi2pat may be setting
3448 either i3dest or i2dest, so we must check it. Also, i1dest may be the
3449 same as i3dest, in which case newi2pat may be setting i1dest. */
3450 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
3451 || i2dest_in_i2src || i2dest_in_i1src
3454 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
3455 || (newi2pat && reg_set_p (i1dest, newi2pat))
3459 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
3461 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
3462 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
3464 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
3466 /* Ensure that we do not have something that should not be shared but
3467 occurs multiple times in the new insns. Check this by first
3468 resetting all the `used' flags and then copying anything is shared. */
3470 reset_used_flags (i3notes);
3471 reset_used_flags (i2notes);
3472 reset_used_flags (i1notes);
3473 reset_used_flags (newpat);
3474 reset_used_flags (newi2pat);
3475 if (undobuf.other_insn)
3476 reset_used_flags (PATTERN (undobuf.other_insn));
3478 i3notes = copy_rtx_if_shared (i3notes);
3479 i2notes = copy_rtx_if_shared (i2notes);
3480 i1notes = copy_rtx_if_shared (i1notes);
3481 newpat = copy_rtx_if_shared (newpat);
3482 newi2pat = copy_rtx_if_shared (newi2pat);
3483 if (undobuf.other_insn)
3484 reset_used_flags (PATTERN (undobuf.other_insn));
3486 INSN_CODE (i3) = insn_code_number;
3487 PATTERN (i3) = newpat;
3489 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
3491 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
3493 reset_used_flags (call_usage);
3494 call_usage = copy_rtx (call_usage);
3497 replace_rtx (call_usage, i2dest, i2src);
3500 replace_rtx (call_usage, i1dest, i1src);
3502 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
3505 if (undobuf.other_insn)
3506 INSN_CODE (undobuf.other_insn) = other_code_number;
3508 /* We had one special case above where I2 had more than one set and
3509 we replaced a destination of one of those sets with the destination
3510 of I3. In that case, we have to update LOG_LINKS of insns later
3511 in this basic block. Note that this (expensive) case is rare.
3513 Also, in this case, we must pretend that all REG_NOTEs for I2
3514 actually came from I3, so that REG_UNUSED notes from I2 will be
3515 properly handled. */
3517 if (i3_subst_into_i2)
3519 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
3520 if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
3521 || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
3522 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
3523 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
3524 && ! find_reg_note (i2, REG_UNUSED,
3525 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
3526 for (temp = NEXT_INSN (i2);
3527 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
3528 || BB_HEAD (this_basic_block) != temp);
3529 temp = NEXT_INSN (temp))
3530 if (temp != i3 && INSN_P (temp))
3531 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
3532 if (XEXP (link, 0) == i2)
3533 XEXP (link, 0) = i3;
3538 while (XEXP (link, 1))
3539 link = XEXP (link, 1);
3540 XEXP (link, 1) = i2notes;
3554 INSN_CODE (i2) = i2_code_number;
3555 PATTERN (i2) = newi2pat;
3558 SET_INSN_DELETED (i2);
3564 SET_INSN_DELETED (i1);
3567 /* Get death notes for everything that is now used in either I3 or
3568 I2 and used to die in a previous insn. If we built two new
3569 patterns, move from I1 to I2 then I2 to I3 so that we get the
3570 proper movement on registers that I2 modifies. */
3574 move_deaths (newi2pat, NULL_RTX, DF_INSN_LUID (i1), i2, &midnotes);
3575 move_deaths (newpat, newi2pat, DF_INSN_LUID (i1), i3, &midnotes);
3578 move_deaths (newpat, NULL_RTX, i1 ? DF_INSN_LUID (i1) : DF_INSN_LUID (i2),
3581 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
3583 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
3586 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
3589 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
3592 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3595 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
3596 know these are REG_UNUSED and want them to go to the desired insn,
3597 so we always pass it as i3. */
3599 if (newi2pat && new_i2_notes)
3600 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3603 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3605 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3606 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3607 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3608 in that case, it might delete I2. Similarly for I2 and I1.
3609 Show an additional death due to the REG_DEAD note we make here. If
3610 we discard it in distribute_notes, we will decrement it again. */
3614 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3615 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3617 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3619 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3621 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3625 if (i2dest_in_i2src)
3627 if (newi2pat && reg_set_p (i2dest, newi2pat))
3628 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3629 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3631 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3632 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3633 NULL_RTX, NULL_RTX);
3636 if (i1dest_in_i1src)
3638 if (newi2pat && reg_set_p (i1dest, newi2pat))
3639 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3640 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3642 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3643 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3644 NULL_RTX, NULL_RTX);
3647 distribute_links (i3links);
3648 distribute_links (i2links);
3649 distribute_links (i1links);
3654 rtx i2_insn = 0, i2_val = 0, set;
3656 /* The insn that used to set this register doesn't exist, and
3657 this life of the register may not exist either. See if one of
3658 I3's links points to an insn that sets I2DEST. If it does,
3659 that is now the last known value for I2DEST. If we don't update
3660 this and I2 set the register to a value that depended on its old
3661 contents, we will get confused. If this insn is used, thing
3662 will be set correctly in combine_instructions. */
3664 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3665 if ((set = single_set (XEXP (link, 0))) != 0
3666 && rtx_equal_p (i2dest, SET_DEST (set)))
3667 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3669 record_value_for_reg (i2dest, i2_insn, i2_val);
3671 /* If the reg formerly set in I2 died only once and that was in I3,
3672 zero its use count so it won't make `reload' do any work. */
3674 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3675 && ! i2dest_in_i2src)
3677 regno = REGNO (i2dest);
3678 INC_REG_N_SETS (regno, -1);
3682 if (i1 && REG_P (i1dest))
3685 rtx i1_insn = 0, i1_val = 0, set;
3687 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3688 if ((set = single_set (XEXP (link, 0))) != 0
3689 && rtx_equal_p (i1dest, SET_DEST (set)))
3690 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3692 record_value_for_reg (i1dest, i1_insn, i1_val);
3694 regno = REGNO (i1dest);
3695 if (! added_sets_1 && ! i1dest_in_i1src)
3696 INC_REG_N_SETS (regno, -1);
3699 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3700 been made to this insn. The order of
3701 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3702 can affect nonzero_bits of newpat */
3704 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3705 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3707 /* Set new_direct_jump_p if a new return or simple jump instruction
3710 If I3 is now an unconditional jump, ensure that it has a
3711 BARRIER following it since it may have initially been a
3712 conditional jump. It may also be the last nonnote insn. */
3714 if (returnjump_p (i3) || any_uncondjump_p (i3))
3716 *new_direct_jump_p = 1;
3717 mark_jump_label (PATTERN (i3), i3, 0);
3719 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3720 || !BARRIER_P (temp))
3721 emit_barrier_after (i3);
3724 if (undobuf.other_insn != NULL_RTX
3725 && (returnjump_p (undobuf.other_insn)
3726 || any_uncondjump_p (undobuf.other_insn)))
3728 *new_direct_jump_p = 1;
3730 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3731 || !BARRIER_P (temp))
3732 emit_barrier_after (undobuf.other_insn);
3735 /* An NOOP jump does not need barrier, but it does need cleaning up
3737 if (GET_CODE (newpat) == SET
3738 && SET_SRC (newpat) == pc_rtx
3739 && SET_DEST (newpat) == pc_rtx)
3740 *new_direct_jump_p = 1;
3743 if (undobuf.other_insn != NULL_RTX)
3747 fprintf (dump_file, "modifying other_insn ");
3748 dump_insn_slim (dump_file, undobuf.other_insn);
3750 df_insn_rescan (undobuf.other_insn);
3753 if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
3757 fprintf (dump_file, "modifying insn i1 ");
3758 dump_insn_slim (dump_file, i1);
3760 df_insn_rescan (i1);
3763 if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
3767 fprintf (dump_file, "modifying insn i2 ");
3768 dump_insn_slim (dump_file, i2);
3770 df_insn_rescan (i2);
3773 if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
3777 fprintf (dump_file, "modifying insn i3 ");
3778 dump_insn_slim (dump_file, i3);
3780 df_insn_rescan (i3);
3783 combine_successes++;
3786 if (added_links_insn
3787 && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
3788 && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
3789 return added_links_insn;
3791 return newi2pat ? i2 : i3;
3794 /* Undo all the modifications recorded in undobuf. */
3799 struct undo *undo, *next;
3801 for (undo = undobuf.undos; undo; undo = next)
3807 *undo->where.r = undo->old_contents.r;
3810 *undo->where.i = undo->old_contents.i;
3813 adjust_reg_mode (*undo->where.r, undo->old_contents.m);
3819 undo->next = undobuf.frees;
3820 undobuf.frees = undo;
3826 /* We've committed to accepting the changes we made. Move all
3827 of the undos to the free list. */
3832 struct undo *undo, *next;
3834 for (undo = undobuf.undos; undo; undo = next)
3837 undo->next = undobuf.frees;
3838 undobuf.frees = undo;
3843 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3844 where we have an arithmetic expression and return that point. LOC will
3847 try_combine will call this function to see if an insn can be split into
3851 find_split_point (rtx *loc, rtx insn)
3854 enum rtx_code code = GET_CODE (x);
3856 unsigned HOST_WIDE_INT len = 0;
3857 HOST_WIDE_INT pos = 0;
3859 rtx inner = NULL_RTX;
3861 /* First special-case some codes. */
3865 #ifdef INSN_SCHEDULING
3866 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3868 if (MEM_P (SUBREG_REG (x)))
3871 return find_split_point (&SUBREG_REG (x), insn);
3875 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3876 using LO_SUM and HIGH. */
3877 if (GET_CODE (XEXP (x, 0)) == CONST
3878 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3881 gen_rtx_LO_SUM (Pmode,
3882 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3884 return &XEXP (XEXP (x, 0), 0);
3888 /* If we have a PLUS whose second operand is a constant and the
3889 address is not valid, perhaps will can split it up using
3890 the machine-specific way to split large constants. We use
3891 the first pseudo-reg (one of the virtual regs) as a placeholder;
3892 it will not remain in the result. */
3893 if (GET_CODE (XEXP (x, 0)) == PLUS
3894 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3895 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3897 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3898 rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
3902 /* This should have produced two insns, each of which sets our
3903 placeholder. If the source of the second is a valid address,
3904 we can make put both sources together and make a split point
3908 && NEXT_INSN (seq) != NULL_RTX
3909 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3910 && NONJUMP_INSN_P (seq)
3911 && GET_CODE (PATTERN (seq)) == SET
3912 && SET_DEST (PATTERN (seq)) == reg
3913 && ! reg_mentioned_p (reg,
3914 SET_SRC (PATTERN (seq)))
3915 && NONJUMP_INSN_P (NEXT_INSN (seq))
3916 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3917 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3918 && memory_address_p (GET_MODE (x),
3919 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3921 rtx src1 = SET_SRC (PATTERN (seq));
3922 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3924 /* Replace the placeholder in SRC2 with SRC1. If we can
3925 find where in SRC2 it was placed, that can become our
3926 split point and we can replace this address with SRC2.
3927 Just try two obvious places. */
3929 src2 = replace_rtx (src2, reg, src1);
3931 if (XEXP (src2, 0) == src1)
3932 split = &XEXP (src2, 0);
3933 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3934 && XEXP (XEXP (src2, 0), 0) == src1)
3935 split = &XEXP (XEXP (src2, 0), 0);
3939 SUBST (XEXP (x, 0), src2);
3944 /* If that didn't work, perhaps the first operand is complex and
3945 needs to be computed separately, so make a split point there.
3946 This will occur on machines that just support REG + CONST
3947 and have a constant moved through some previous computation. */
3949 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3950 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3951 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3952 return &XEXP (XEXP (x, 0), 0);
3955 /* If we have a PLUS whose first operand is complex, try computing it
3956 separately by making a split there. */
3957 if (GET_CODE (XEXP (x, 0)) == PLUS
3958 && ! memory_address_p (GET_MODE (x), XEXP (x, 0))
3959 && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
3960 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3961 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3962 return &XEXP (XEXP (x, 0), 0);
3967 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3968 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3969 we need to put the operand into a register. So split at that
3972 if (SET_DEST (x) == cc0_rtx
3973 && GET_CODE (SET_SRC (x)) != COMPARE
3974 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3975 && !OBJECT_P (SET_SRC (x))
3976 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3977 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3978 return &SET_SRC (x);
3981 /* See if we can split SET_SRC as it stands. */
3982 split = find_split_point (&SET_SRC (x), insn);
3983 if (split && split != &SET_SRC (x))
3986 /* See if we can split SET_DEST as it stands. */
3987 split = find_split_point (&SET_DEST (x), insn);
3988 if (split && split != &SET_DEST (x))
3991 /* See if this is a bitfield assignment with everything constant. If
3992 so, this is an IOR of an AND, so split it into that. */
3993 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3994 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3995 <= HOST_BITS_PER_WIDE_INT)
3996 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3997 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3998 && GET_CODE (SET_SRC (x)) == CONST_INT
3999 && ((INTVAL (XEXP (SET_DEST (x), 1))
4000 + INTVAL (XEXP (SET_DEST (x), 2)))
4001 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
4002 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4004 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4005 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4006 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4007 rtx dest = XEXP (SET_DEST (x), 0);
4008 enum machine_mode mode = GET_MODE (dest);
4009 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
4012 if (BITS_BIG_ENDIAN)
4013 pos = GET_MODE_BITSIZE (mode) - len - pos;
4015 or_mask = gen_int_mode (src << pos, mode);
4018 simplify_gen_binary (IOR, mode, dest, or_mask));
4021 rtx negmask = gen_int_mode (~(mask << pos), mode);
4023 simplify_gen_binary (IOR, mode,
4024 simplify_gen_binary (AND, mode,
4029 SUBST (SET_DEST (x), dest);
4031 split = find_split_point (&SET_SRC (x), insn);
4032 if (split && split != &SET_SRC (x))
4036 /* Otherwise, see if this is an operation that we can split into two.
4037 If so, try to split that. */
4038 code = GET_CODE (SET_SRC (x));
4043 /* If we are AND'ing with a large constant that is only a single
4044 bit and the result is only being used in a context where we
4045 need to know if it is zero or nonzero, replace it with a bit
4046 extraction. This will avoid the large constant, which might
4047 have taken more than one insn to make. If the constant were
4048 not a valid argument to the AND but took only one insn to make,
4049 this is no worse, but if it took more than one insn, it will
4052 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4053 && REG_P (XEXP (SET_SRC (x), 0))
4054 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4055 && REG_P (SET_DEST (x))
4056 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4057 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4058 && XEXP (*split, 0) == SET_DEST (x)
4059 && XEXP (*split, 1) == const0_rtx)
4061 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4062 XEXP (SET_SRC (x), 0),
4063 pos, NULL_RTX, 1, 1, 0, 0);
4064 if (extraction != 0)
4066 SUBST (SET_SRC (x), extraction);
4067 return find_split_point (loc, insn);
4073 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4074 is known to be on, this can be converted into a NEG of a shift. */
4075 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4076 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4077 && 1 <= (pos = exact_log2
4078 (nonzero_bits (XEXP (SET_SRC (x), 0),
4079 GET_MODE (XEXP (SET_SRC (x), 0))))))
4081 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4085 gen_rtx_LSHIFTRT (mode,
4086 XEXP (SET_SRC (x), 0),
4089 split = find_split_point (&SET_SRC (x), insn);
4090 if (split && split != &SET_SRC (x))
4096 inner = XEXP (SET_SRC (x), 0);
4098 /* We can't optimize if either mode is a partial integer
4099 mode as we don't know how many bits are significant
4101 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4102 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4106 len = GET_MODE_BITSIZE (GET_MODE (inner));
4112 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
4113 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
4115 inner = XEXP (SET_SRC (x), 0);
4116 len = INTVAL (XEXP (SET_SRC (x), 1));
4117 pos = INTVAL (XEXP (SET_SRC (x), 2));
4119 if (BITS_BIG_ENDIAN)
4120 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
4121 unsignedp = (code == ZERO_EXTRACT);
4129 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
4131 enum machine_mode mode = GET_MODE (SET_SRC (x));
4133 /* For unsigned, we have a choice of a shift followed by an
4134 AND or two shifts. Use two shifts for field sizes where the
4135 constant might be too large. We assume here that we can
4136 always at least get 8-bit constants in an AND insn, which is
4137 true for every current RISC. */
4139 if (unsignedp && len <= 8)
4144 (mode, gen_lowpart (mode, inner),
4146 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
4148 split = find_split_point (&SET_SRC (x), insn);
4149 if (split && split != &SET_SRC (x))
4156 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4157 gen_rtx_ASHIFT (mode,
4158 gen_lowpart (mode, inner),
4159 GEN_INT (GET_MODE_BITSIZE (mode)
4161 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
4163 split = find_split_point (&SET_SRC (x), insn);
4164 if (split && split != &SET_SRC (x))
4169 /* See if this is a simple operation with a constant as the second
4170 operand. It might be that this constant is out of range and hence
4171 could be used as a split point. */
4172 if (BINARY_P (SET_SRC (x))
4173 && CONSTANT_P (XEXP (SET_SRC (x), 1))
4174 && (OBJECT_P (XEXP (SET_SRC (x), 0))
4175 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4176 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4177 return &XEXP (SET_SRC (x), 1);
4179 /* Finally, see if this is a simple operation with its first operand
4180 not in a register. The operation might require this operand in a
4181 register, so return it as a split point. We can always do this
4182 because if the first operand were another operation, we would have
4183 already found it as a split point. */
4184 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4185 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4186 return &XEXP (SET_SRC (x), 0);
4192 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4193 it is better to write this as (not (ior A B)) so we can split it.
4194 Similarly for IOR. */
4195 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4198 gen_rtx_NOT (GET_MODE (x),
4199 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4201 XEXP (XEXP (x, 0), 0),
4202 XEXP (XEXP (x, 1), 0))));
4203 return find_split_point (loc, insn);
4206 /* Many RISC machines have a large set of logical insns. If the
4207 second operand is a NOT, put it first so we will try to split the
4208 other operand first. */
4209 if (GET_CODE (XEXP (x, 1)) == NOT)
4211 rtx tem = XEXP (x, 0);
4212 SUBST (XEXP (x, 0), XEXP (x, 1));
4213 SUBST (XEXP (x, 1), tem);
4221 /* Otherwise, select our actions depending on our rtx class. */
4222 switch (GET_RTX_CLASS (code))
4224 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
4226 split = find_split_point (&XEXP (x, 2), insn);
4229 /* ... fall through ... */
4231 case RTX_COMM_ARITH:
4233 case RTX_COMM_COMPARE:
4234 split = find_split_point (&XEXP (x, 1), insn);
4237 /* ... fall through ... */
4239 /* Some machines have (and (shift ...) ...) insns. If X is not
4240 an AND, but XEXP (X, 0) is, use it as our split point. */
4241 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4242 return &XEXP (x, 0);
4244 split = find_split_point (&XEXP (x, 0), insn);
4250 /* Otherwise, we don't have a split point. */
4255 /* Throughout X, replace FROM with TO, and return the result.
4256 The result is TO if X is FROM;
4257 otherwise the result is X, but its contents may have been modified.
4258 If they were modified, a record was made in undobuf so that
4259 undo_all will (among other things) return X to its original state.
4261 If the number of changes necessary is too much to record to undo,
4262 the excess changes are not made, so the result is invalid.
4263 The changes already made can still be undone.
4264 undobuf.num_undo is incremented for such changes, so by testing that
4265 the caller can tell whether the result is valid.
4267 `n_occurrences' is incremented each time FROM is replaced.
4269 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4271 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
4272 by copying if `n_occurrences' is nonzero. */
4275 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
4277 enum rtx_code code = GET_CODE (x);
4278 enum machine_mode op0_mode = VOIDmode;
4283 /* Two expressions are equal if they are identical copies of a shared
4284 RTX or if they are both registers with the same register number
4287 #define COMBINE_RTX_EQUAL_P(X,Y) \
4289 || (REG_P (X) && REG_P (Y) \
4290 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4292 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4295 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4298 /* If X and FROM are the same register but different modes, they
4299 will not have been seen as equal above. However, the log links code
4300 will make a LOG_LINKS entry for that case. If we do nothing, we
4301 will try to rerecognize our original insn and, when it succeeds,
4302 we will delete the feeding insn, which is incorrect.
4304 So force this insn not to match in this (rare) case. */
4305 if (! in_dest && code == REG && REG_P (from)
4306 && reg_overlap_mentioned_p (x, from))
4307 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4309 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4310 of which may contain things that can be combined. */
4311 if (code != MEM && code != LO_SUM && OBJECT_P (x))
4314 /* It is possible to have a subexpression appear twice in the insn.
4315 Suppose that FROM is a register that appears within TO.
4316 Then, after that subexpression has been scanned once by `subst',
4317 the second time it is scanned, TO may be found. If we were
4318 to scan TO here, we would find FROM within it and create a
4319 self-referent rtl structure which is completely wrong. */
4320 if (COMBINE_RTX_EQUAL_P (x, to))
4323 /* Parallel asm_operands need special attention because all of the
4324 inputs are shared across the arms. Furthermore, unsharing the
4325 rtl results in recognition failures. Failure to handle this case
4326 specially can result in circular rtl.
4328 Solve this by doing a normal pass across the first entry of the
4329 parallel, and only processing the SET_DESTs of the subsequent
4332 if (code == PARALLEL
4333 && GET_CODE (XVECEXP (x, 0, 0)) == SET
4334 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
4336 new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
4338 /* If this substitution failed, this whole thing fails. */
4339 if (GET_CODE (new_rtx) == CLOBBER
4340 && XEXP (new_rtx, 0) == const0_rtx)
4343 SUBST (XVECEXP (x, 0, 0), new_rtx);
4345 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
4347 rtx dest = SET_DEST (XVECEXP (x, 0, i));
4350 && GET_CODE (dest) != CC0
4351 && GET_CODE (dest) != PC)
4353 new_rtx = subst (dest, from, to, 0, unique_copy);
4355 /* If this substitution failed, this whole thing fails. */
4356 if (GET_CODE (new_rtx) == CLOBBER
4357 && XEXP (new_rtx, 0) == const0_rtx)
4360 SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
4366 len = GET_RTX_LENGTH (code);
4367 fmt = GET_RTX_FORMAT (code);
4369 /* We don't need to process a SET_DEST that is a register, CC0,
4370 or PC, so set up to skip this common case. All other cases
4371 where we want to suppress replacing something inside a
4372 SET_SRC are handled via the IN_DEST operand. */
4374 && (REG_P (SET_DEST (x))
4375 || GET_CODE (SET_DEST (x)) == CC0
4376 || GET_CODE (SET_DEST (x)) == PC))
4379 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
4382 op0_mode = GET_MODE (XEXP (x, 0));
4384 for (i = 0; i < len; i++)
4389 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4391 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
4393 new_rtx = (unique_copy && n_occurrences
4394 ? copy_rtx (to) : to);
4399 new_rtx = subst (XVECEXP (x, i, j), from, to, 0,
4402 /* If this substitution failed, this whole thing
4404 if (GET_CODE (new_rtx) == CLOBBER
4405 && XEXP (new_rtx, 0) == const0_rtx)
4409 SUBST (XVECEXP (x, i, j), new_rtx);
4412 else if (fmt[i] == 'e')
4414 /* If this is a register being set, ignore it. */
4415 new_rtx = XEXP (x, i);
4418 && (((code == SUBREG || code == ZERO_EXTRACT)
4420 || code == STRICT_LOW_PART))
4423 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
4425 /* In general, don't install a subreg involving two
4426 modes not tieable. It can worsen register
4427 allocation, and can even make invalid reload
4428 insns, since the reg inside may need to be copied
4429 from in the outside mode, and that may be invalid
4430 if it is an fp reg copied in integer mode.
4432 We allow two exceptions to this: It is valid if
4433 it is inside another SUBREG and the mode of that
4434 SUBREG and the mode of the inside of TO is
4435 tieable and it is valid if X is a SET that copies
4438 if (GET_CODE (to) == SUBREG
4439 && ! MODES_TIEABLE_P (GET_MODE (to),
4440 GET_MODE (SUBREG_REG (to)))
4441 && ! (code == SUBREG
4442 && MODES_TIEABLE_P (GET_MODE (x),
4443 GET_MODE (SUBREG_REG (to))))
4445 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
4448 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4450 #ifdef CANNOT_CHANGE_MODE_CLASS
4453 && REGNO (to) < FIRST_PSEUDO_REGISTER
4454 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
4457 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
4460 new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
4464 /* If we are in a SET_DEST, suppress most cases unless we
4465 have gone inside a MEM, in which case we want to
4466 simplify the address. We assume here that things that
4467 are actually part of the destination have their inner
4468 parts in the first expression. This is true for SUBREG,
4469 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
4470 things aside from REG and MEM that should appear in a
4472 new_rtx = subst (XEXP (x, i), from, to,
4474 && (code == SUBREG || code == STRICT_LOW_PART
4475 || code == ZERO_EXTRACT))
4477 && i == 0), unique_copy);
4479 /* If we found that we will have to reject this combination,
4480 indicate that by returning the CLOBBER ourselves, rather than
4481 an expression containing it. This will speed things up as
4482 well as prevent accidents where two CLOBBERs are considered
4483 to be equal, thus producing an incorrect simplification. */
4485 if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
4488 if (GET_CODE (x) == SUBREG
4489 && (GET_CODE (new_rtx) == CONST_INT
4490 || GET_CODE (new_rtx) == CONST_DOUBLE))
4492 enum machine_mode mode = GET_MODE (x);
4494 x = simplify_subreg (GET_MODE (x), new_rtx,
4495 GET_MODE (SUBREG_REG (x)),
4498 x = gen_rtx_CLOBBER (mode, const0_rtx);
4500 else if (GET_CODE (new_rtx) == CONST_INT
4501 && GET_CODE (x) == ZERO_EXTEND)
4503 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
4504 new_rtx, GET_MODE (XEXP (x, 0)));
4508 SUBST (XEXP (x, i), new_rtx);
4513 /* Check if we are loading something from the constant pool via float
4514 extension; in this case we would undo compress_float_constant
4515 optimization and degenerate constant load to an immediate value. */
4516 if (GET_CODE (x) == FLOAT_EXTEND
4517 && MEM_P (XEXP (x, 0))
4518 && MEM_READONLY_P (XEXP (x, 0)))
4520 rtx tmp = avoid_constant_pool_reference (x);
4525 /* Try to simplify X. If the simplification changed the code, it is likely
4526 that further simplification will help, so loop, but limit the number
4527 of repetitions that will be performed. */
4529 for (i = 0; i < 4; i++)
4531 /* If X is sufficiently simple, don't bother trying to do anything
4533 if (code != CONST_INT && code != REG && code != CLOBBER)
4534 x = combine_simplify_rtx (x, op0_mode, in_dest);
4536 if (GET_CODE (x) == code)
4539 code = GET_CODE (x);
4541 /* We no longer know the original mode of operand 0 since we
4542 have changed the form of X) */
4543 op0_mode = VOIDmode;
4549 /* Simplify X, a piece of RTL. We just operate on the expression at the
4550 outer level; call `subst' to simplify recursively. Return the new
4553 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
4554 if we are inside a SET_DEST. */
4557 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
4559 enum rtx_code code = GET_CODE (x);
4560 enum machine_mode mode = GET_MODE (x);
4564 /* If this is a commutative operation, put a constant last and a complex
4565 expression first. We don't need to do this for comparisons here. */
4566 if (COMMUTATIVE_ARITH_P (x)
4567 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
4570 SUBST (XEXP (x, 0), XEXP (x, 1));
4571 SUBST (XEXP (x, 1), temp);
4574 /* If this is a simple operation applied to an IF_THEN_ELSE, try
4575 applying it to the arms of the IF_THEN_ELSE. This often simplifies
4576 things. Check for cases where both arms are testing the same
4579 Don't do anything if all operands are very simple. */
4582 && ((!OBJECT_P (XEXP (x, 0))
4583 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4584 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
4585 || (!OBJECT_P (XEXP (x, 1))
4586 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
4587 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
4589 && (!OBJECT_P (XEXP (x, 0))
4590 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4591 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
4593 rtx cond, true_rtx, false_rtx;
4595 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
4597 /* If everything is a comparison, what we have is highly unlikely
4598 to be simpler, so don't use it. */
4599 && ! (COMPARISON_P (x)
4600 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
4602 rtx cop1 = const0_rtx;
4603 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
4605 if (cond_code == NE && COMPARISON_P (cond))
4608 /* Simplify the alternative arms; this may collapse the true and
4609 false arms to store-flag values. Be careful to use copy_rtx
4610 here since true_rtx or false_rtx might share RTL with x as a
4611 result of the if_then_else_cond call above. */
4612 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
4613 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
4615 /* If true_rtx and false_rtx are not general_operands, an if_then_else
4616 is unlikely to be simpler. */
4617 if (general_operand (true_rtx, VOIDmode)
4618 && general_operand (false_rtx, VOIDmode))
4620 enum rtx_code reversed;
4622 /* Restarting if we generate a store-flag expression will cause
4623 us to loop. Just drop through in this case. */
4625 /* If the result values are STORE_FLAG_VALUE and zero, we can
4626 just make the comparison operation. */
4627 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
4628 x = simplify_gen_relational (cond_code, mode, VOIDmode,
4630 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
4631 && ((reversed = reversed_comparison_code_parts
4632 (cond_code, cond, cop1, NULL))
4634 x = simplify_gen_relational (reversed, mode, VOIDmode,
4637 /* Likewise, we can make the negate of a comparison operation
4638 if the result values are - STORE_FLAG_VALUE and zero. */
4639 else if (GET_CODE (true_rtx) == CONST_INT
4640 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
4641 && false_rtx == const0_rtx)
4642 x = simplify_gen_unary (NEG, mode,
4643 simplify_gen_relational (cond_code,
4647 else if (GET_CODE (false_rtx) == CONST_INT
4648 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
4649 && true_rtx == const0_rtx
4650 && ((reversed = reversed_comparison_code_parts
4651 (cond_code, cond, cop1, NULL))
4653 x = simplify_gen_unary (NEG, mode,
4654 simplify_gen_relational (reversed,
4659 return gen_rtx_IF_THEN_ELSE (mode,
4660 simplify_gen_relational (cond_code,
4665 true_rtx, false_rtx);
4667 code = GET_CODE (x);
4668 op0_mode = VOIDmode;
4673 /* Try to fold this expression in case we have constants that weren't
4676 switch (GET_RTX_CLASS (code))
4679 if (op0_mode == VOIDmode)
4680 op0_mode = GET_MODE (XEXP (x, 0));
4681 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4684 case RTX_COMM_COMPARE:
4686 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4687 if (cmp_mode == VOIDmode)
4689 cmp_mode = GET_MODE (XEXP (x, 1));
4690 if (cmp_mode == VOIDmode)
4691 cmp_mode = op0_mode;
4693 temp = simplify_relational_operation (code, mode, cmp_mode,
4694 XEXP (x, 0), XEXP (x, 1));
4697 case RTX_COMM_ARITH:
4699 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4701 case RTX_BITFIELD_OPS:
4703 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4704 XEXP (x, 1), XEXP (x, 2));
4713 code = GET_CODE (temp);
4714 op0_mode = VOIDmode;
4715 mode = GET_MODE (temp);
4718 /* First see if we can apply the inverse distributive law. */
4719 if (code == PLUS || code == MINUS
4720 || code == AND || code == IOR || code == XOR)
4722 x = apply_distributive_law (x);
4723 code = GET_CODE (x);
4724 op0_mode = VOIDmode;
4727 /* If CODE is an associative operation not otherwise handled, see if we
4728 can associate some operands. This can win if they are constants or
4729 if they are logically related (i.e. (a & b) & a). */
4730 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4731 || code == AND || code == IOR || code == XOR
4732 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4733 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4734 || (flag_associative_math && FLOAT_MODE_P (mode))))
4736 if (GET_CODE (XEXP (x, 0)) == code)
4738 rtx other = XEXP (XEXP (x, 0), 0);
4739 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4740 rtx inner_op1 = XEXP (x, 1);
4743 /* Make sure we pass the constant operand if any as the second
4744 one if this is a commutative operation. */
4745 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4747 rtx tem = inner_op0;
4748 inner_op0 = inner_op1;
4751 inner = simplify_binary_operation (code == MINUS ? PLUS
4752 : code == DIV ? MULT
4754 mode, inner_op0, inner_op1);
4756 /* For commutative operations, try the other pair if that one
4758 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4760 other = XEXP (XEXP (x, 0), 1);
4761 inner = simplify_binary_operation (code, mode,
4762 XEXP (XEXP (x, 0), 0),
4767 return simplify_gen_binary (code, mode, other, inner);
4771 /* A little bit of algebraic simplification here. */
4775 /* Ensure that our address has any ASHIFTs converted to MULT in case
4776 address-recognizing predicates are called later. */
4777 temp = make_compound_operation (XEXP (x, 0), MEM);
4778 SUBST (XEXP (x, 0), temp);
4782 if (op0_mode == VOIDmode)
4783 op0_mode = GET_MODE (SUBREG_REG (x));
4785 /* See if this can be moved to simplify_subreg. */
4786 if (CONSTANT_P (SUBREG_REG (x))
4787 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4788 /* Don't call gen_lowpart if the inner mode
4789 is VOIDmode and we cannot simplify it, as SUBREG without
4790 inner mode is invalid. */
4791 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4792 || gen_lowpart_common (mode, SUBREG_REG (x))))
4793 return gen_lowpart (mode, SUBREG_REG (x));
4795 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4799 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4805 /* Don't change the mode of the MEM if that would change the meaning
4807 if (MEM_P (SUBREG_REG (x))
4808 && (MEM_VOLATILE_P (SUBREG_REG (x))
4809 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4810 return gen_rtx_CLOBBER (mode, const0_rtx);
4812 /* Note that we cannot do any narrowing for non-constants since
4813 we might have been counting on using the fact that some bits were
4814 zero. We now do this in the SET. */
4819 temp = expand_compound_operation (XEXP (x, 0));
4821 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4822 replaced by (lshiftrt X C). This will convert
4823 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4825 if (GET_CODE (temp) == ASHIFTRT
4826 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4827 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4828 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
4829 INTVAL (XEXP (temp, 1)));
4831 /* If X has only a single bit that might be nonzero, say, bit I, convert
4832 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4833 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4834 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4835 or a SUBREG of one since we'd be making the expression more
4836 complex if it was just a register. */
4839 && ! (GET_CODE (temp) == SUBREG
4840 && REG_P (SUBREG_REG (temp)))
4841 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4843 rtx temp1 = simplify_shift_const
4844 (NULL_RTX, ASHIFTRT, mode,
4845 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4846 GET_MODE_BITSIZE (mode) - 1 - i),
4847 GET_MODE_BITSIZE (mode) - 1 - i);
4849 /* If all we did was surround TEMP with the two shifts, we
4850 haven't improved anything, so don't use it. Otherwise,
4851 we are better off with TEMP1. */
4852 if (GET_CODE (temp1) != ASHIFTRT
4853 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4854 || XEXP (XEXP (temp1, 0), 0) != temp)
4860 /* We can't handle truncation to a partial integer mode here
4861 because we don't know the real bitsize of the partial
4863 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4866 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4867 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4868 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4870 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4871 GET_MODE_MASK (mode), 0));
4873 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4874 whose value is a comparison can be replaced with a subreg if
4875 STORE_FLAG_VALUE permits. */
4876 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4877 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4878 && (temp = get_last_value (XEXP (x, 0)))
4879 && COMPARISON_P (temp))
4880 return gen_lowpart (mode, XEXP (x, 0));
4885 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4886 using cc0, in which case we want to leave it as a COMPARE
4887 so we can distinguish it from a register-register-copy. */
4888 if (XEXP (x, 1) == const0_rtx)
4891 /* x - 0 is the same as x unless x's mode has signed zeros and
4892 allows rounding towards -infinity. Under those conditions,
4894 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4895 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4896 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4902 /* (const (const X)) can become (const X). Do it this way rather than
4903 returning the inner CONST since CONST can be shared with a
4905 if (GET_CODE (XEXP (x, 0)) == CONST)
4906 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4911 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4912 can add in an offset. find_split_point will split this address up
4913 again if it doesn't match. */
4914 if (GET_CODE (XEXP (x, 0)) == HIGH
4915 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4921 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4922 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4923 bit-field and can be replaced by either a sign_extend or a
4924 sign_extract. The `and' may be a zero_extend and the two
4925 <c>, -<c> constants may be reversed. */
4926 if (GET_CODE (XEXP (x, 0)) == XOR
4927 && GET_CODE (XEXP (x, 1)) == CONST_INT
4928 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4929 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4930 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4931 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4932 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4933 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4934 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4935 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4936 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4937 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4938 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4939 == (unsigned int) i + 1))))
4940 return simplify_shift_const
4941 (NULL_RTX, ASHIFTRT, mode,
4942 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4943 XEXP (XEXP (XEXP (x, 0), 0), 0),
4944 GET_MODE_BITSIZE (mode) - (i + 1)),
4945 GET_MODE_BITSIZE (mode) - (i + 1));
4947 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4948 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4949 the bitsize of the mode - 1. This allows simplification of
4950 "a = (b & 8) == 0;" */
4951 if (XEXP (x, 1) == constm1_rtx
4952 && !REG_P (XEXP (x, 0))
4953 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4954 && REG_P (SUBREG_REG (XEXP (x, 0))))
4955 && nonzero_bits (XEXP (x, 0), mode) == 1)
4956 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4957 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4958 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4959 GET_MODE_BITSIZE (mode) - 1),
4960 GET_MODE_BITSIZE (mode) - 1);
4962 /* If we are adding two things that have no bits in common, convert
4963 the addition into an IOR. This will often be further simplified,
4964 for example in cases like ((a & 1) + (a & 2)), which can
4967 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4968 && (nonzero_bits (XEXP (x, 0), mode)
4969 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4971 /* Try to simplify the expression further. */
4972 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4973 temp = combine_simplify_rtx (tor, mode, in_dest);
4975 /* If we could, great. If not, do not go ahead with the IOR
4976 replacement, since PLUS appears in many special purpose
4977 address arithmetic instructions. */
4978 if (GET_CODE (temp) != CLOBBER && temp != tor)
4984 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4985 (and <foo> (const_int pow2-1)) */
4986 if (GET_CODE (XEXP (x, 1)) == AND
4987 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4988 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4989 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4990 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4991 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4995 /* If we have (mult (plus A B) C), apply the distributive law and then
4996 the inverse distributive law to see if things simplify. This
4997 occurs mostly in addresses, often when unrolling loops. */
4999 if (GET_CODE (XEXP (x, 0)) == PLUS)
5001 rtx result = distribute_and_simplify_rtx (x, 0);
5006 /* Try simplify a*(b/c) as (a*b)/c. */
5007 if (FLOAT_MODE_P (mode) && flag_associative_math
5008 && GET_CODE (XEXP (x, 0)) == DIV)
5010 rtx tem = simplify_binary_operation (MULT, mode,
5011 XEXP (XEXP (x, 0), 0),
5014 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5019 /* If this is a divide by a power of two, treat it as a shift if
5020 its first operand is a shift. */
5021 if (GET_CODE (XEXP (x, 1)) == CONST_INT
5022 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
5023 && (GET_CODE (XEXP (x, 0)) == ASHIFT
5024 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5025 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5026 || GET_CODE (XEXP (x, 0)) == ROTATE
5027 || GET_CODE (XEXP (x, 0)) == ROTATERT))
5028 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5032 case GT: case GTU: case GE: case GEU:
5033 case LT: case LTU: case LE: case LEU:
5034 case UNEQ: case LTGT:
5035 case UNGT: case UNGE:
5036 case UNLT: case UNLE:
5037 case UNORDERED: case ORDERED:
5038 /* If the first operand is a condition code, we can't do anything
5040 if (GET_CODE (XEXP (x, 0)) == COMPARE
5041 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5042 && ! CC0_P (XEXP (x, 0))))
5044 rtx op0 = XEXP (x, 0);
5045 rtx op1 = XEXP (x, 1);
5046 enum rtx_code new_code;
5048 if (GET_CODE (op0) == COMPARE)
5049 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5051 /* Simplify our comparison, if possible. */
5052 new_code = simplify_comparison (code, &op0, &op1);
5054 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5055 if only the low-order bit is possibly nonzero in X (such as when
5056 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5057 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5058 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5061 Remove any ZERO_EXTRACT we made when thinking this was a
5062 comparison. It may now be simpler to use, e.g., an AND. If a
5063 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5064 the call to make_compound_operation in the SET case. */
5066 if (STORE_FLAG_VALUE == 1
5067 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5068 && op1 == const0_rtx
5069 && mode == GET_MODE (op0)
5070 && nonzero_bits (op0, mode) == 1)
5071 return gen_lowpart (mode,
5072 expand_compound_operation (op0));
5074 else if (STORE_FLAG_VALUE == 1
5075 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5076 && op1 == const0_rtx
5077 && mode == GET_MODE (op0)
5078 && (num_sign_bit_copies (op0, mode)
5079 == GET_MODE_BITSIZE (mode)))
5081 op0 = expand_compound_operation (op0);
5082 return simplify_gen_unary (NEG, mode,
5083 gen_lowpart (mode, op0),
5087 else if (STORE_FLAG_VALUE == 1
5088 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5089 && op1 == const0_rtx
5090 && mode == GET_MODE (op0)
5091 && nonzero_bits (op0, mode) == 1)
5093 op0 = expand_compound_operation (op0);
5094 return simplify_gen_binary (XOR, mode,
5095 gen_lowpart (mode, op0),
5099 else if (STORE_FLAG_VALUE == 1
5100 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5101 && op1 == const0_rtx
5102 && mode == GET_MODE (op0)
5103 && (num_sign_bit_copies (op0, mode)
5104 == GET_MODE_BITSIZE (mode)))
5106 op0 = expand_compound_operation (op0);
5107 return plus_constant (gen_lowpart (mode, op0), 1);
5110 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5112 if (STORE_FLAG_VALUE == -1
5113 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5114 && op1 == const0_rtx
5115 && (num_sign_bit_copies (op0, mode)
5116 == GET_MODE_BITSIZE (mode)))
5117 return gen_lowpart (mode,
5118 expand_compound_operation (op0));
5120 else if (STORE_FLAG_VALUE == -1
5121 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5122 && op1 == const0_rtx
5123 && mode == GET_MODE (op0)
5124 && nonzero_bits (op0, mode) == 1)
5126 op0 = expand_compound_operation (op0);
5127 return simplify_gen_unary (NEG, mode,
5128 gen_lowpart (mode, op0),
5132 else if (STORE_FLAG_VALUE == -1
5133 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5134 && op1 == const0_rtx
5135 && mode == GET_MODE (op0)
5136 && (num_sign_bit_copies (op0, mode)
5137 == GET_MODE_BITSIZE (mode)))
5139 op0 = expand_compound_operation (op0);
5140 return simplify_gen_unary (NOT, mode,
5141 gen_lowpart (mode, op0),
5145 /* If X is 0/1, (eq X 0) is X-1. */
5146 else if (STORE_FLAG_VALUE == -1
5147 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5148 && op1 == const0_rtx
5149 && mode == GET_MODE (op0)
5150 && nonzero_bits (op0, mode) == 1)
5152 op0 = expand_compound_operation (op0);
5153 return plus_constant (gen_lowpart (mode, op0), -1);
5156 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5157 one bit that might be nonzero, we can convert (ne x 0) to
5158 (ashift x c) where C puts the bit in the sign bit. Remove any
5159 AND with STORE_FLAG_VALUE when we are done, since we are only
5160 going to test the sign bit. */
5161 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5162 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5163 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5164 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5165 && op1 == const0_rtx
5166 && mode == GET_MODE (op0)
5167 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5169 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5170 expand_compound_operation (op0),
5171 GET_MODE_BITSIZE (mode) - 1 - i);
5172 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5178 /* If the code changed, return a whole new comparison. */
5179 if (new_code != code)
5180 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5182 /* Otherwise, keep this operation, but maybe change its operands.
5183 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5184 SUBST (XEXP (x, 0), op0);
5185 SUBST (XEXP (x, 1), op1);
5190 return simplify_if_then_else (x);
5196 /* If we are processing SET_DEST, we are done. */
5200 return expand_compound_operation (x);
5203 return simplify_set (x);
5207 return simplify_logical (x);
5214 /* If this is a shift by a constant amount, simplify it. */
5215 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5216 return simplify_shift_const (x, code, mode, XEXP (x, 0),
5217 INTVAL (XEXP (x, 1)));
5219 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5221 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5223 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5235 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
5238 simplify_if_then_else (rtx x)
5240 enum machine_mode mode = GET_MODE (x);
5241 rtx cond = XEXP (x, 0);
5242 rtx true_rtx = XEXP (x, 1);
5243 rtx false_rtx = XEXP (x, 2);
5244 enum rtx_code true_code = GET_CODE (cond);
5245 int comparison_p = COMPARISON_P (cond);
5248 enum rtx_code false_code;
5251 /* Simplify storing of the truth value. */
5252 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5253 return simplify_gen_relational (true_code, mode, VOIDmode,
5254 XEXP (cond, 0), XEXP (cond, 1));
5256 /* Also when the truth value has to be reversed. */
5258 && true_rtx == const0_rtx && false_rtx == const_true_rtx
5259 && (reversed = reversed_comparison (cond, mode)))
5262 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5263 in it is being compared against certain values. Get the true and false
5264 comparisons and see if that says anything about the value of each arm. */
5267 && ((false_code = reversed_comparison_code (cond, NULL))
5269 && REG_P (XEXP (cond, 0)))
5272 rtx from = XEXP (cond, 0);
5273 rtx true_val = XEXP (cond, 1);
5274 rtx false_val = true_val;
5277 /* If FALSE_CODE is EQ, swap the codes and arms. */
5279 if (false_code == EQ)
5281 swapped = 1, true_code = EQ, false_code = NE;
5282 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5285 /* If we are comparing against zero and the expression being tested has
5286 only a single bit that might be nonzero, that is its value when it is
5287 not equal to zero. Similarly if it is known to be -1 or 0. */
5289 if (true_code == EQ && true_val == const0_rtx
5290 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5293 false_val = GEN_INT (trunc_int_for_mode (nzb, GET_MODE (from)));
5295 else if (true_code == EQ && true_val == const0_rtx
5296 && (num_sign_bit_copies (from, GET_MODE (from))
5297 == GET_MODE_BITSIZE (GET_MODE (from))))
5300 false_val = constm1_rtx;
5303 /* Now simplify an arm if we know the value of the register in the
5304 branch and it is used in the arm. Be careful due to the potential
5305 of locally-shared RTL. */
5307 if (reg_mentioned_p (from, true_rtx))
5308 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
5310 pc_rtx, pc_rtx, 0, 0);
5311 if (reg_mentioned_p (from, false_rtx))
5312 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
5314 pc_rtx, pc_rtx, 0, 0);
5316 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
5317 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
5319 true_rtx = XEXP (x, 1);
5320 false_rtx = XEXP (x, 2);
5321 true_code = GET_CODE (cond);
5324 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
5325 reversed, do so to avoid needing two sets of patterns for
5326 subtract-and-branch insns. Similarly if we have a constant in the true
5327 arm, the false arm is the same as the first operand of the comparison, or
5328 the false arm is more complicated than the true arm. */
5331 && reversed_comparison_code (cond, NULL) != UNKNOWN
5332 && (true_rtx == pc_rtx
5333 || (CONSTANT_P (true_rtx)
5334 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
5335 || true_rtx == const0_rtx
5336 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
5337 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
5338 && !OBJECT_P (false_rtx))
5339 || reg_mentioned_p (true_rtx, false_rtx)
5340 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
5342 true_code = reversed_comparison_code (cond, NULL);
5343 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
5344 SUBST (XEXP (x, 1), false_rtx);
5345 SUBST (XEXP (x, 2), true_rtx);
5347 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5350 /* It is possible that the conditional has been simplified out. */
5351 true_code = GET_CODE (cond);
5352 comparison_p = COMPARISON_P (cond);
5355 /* If the two arms are identical, we don't need the comparison. */
5357 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
5360 /* Convert a == b ? b : a to "a". */
5361 if (true_code == EQ && ! side_effects_p (cond)
5362 && !HONOR_NANS (mode)
5363 && rtx_equal_p (XEXP (cond, 0), false_rtx)
5364 && rtx_equal_p (XEXP (cond, 1), true_rtx))
5366 else if (true_code == NE && ! side_effects_p (cond)
5367 && !HONOR_NANS (mode)
5368 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5369 && rtx_equal_p (XEXP (cond, 1), false_rtx))
5372 /* Look for cases where we have (abs x) or (neg (abs X)). */
5374 if (GET_MODE_CLASS (mode) == MODE_INT
5376 && XEXP (cond, 1) == const0_rtx
5377 && GET_CODE (false_rtx) == NEG
5378 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
5379 && rtx_equal_p (true_rtx, XEXP (cond, 0))
5380 && ! side_effects_p (true_rtx))
5385 return simplify_gen_unary (ABS, mode, true_rtx, mode);
5389 simplify_gen_unary (NEG, mode,
5390 simplify_gen_unary (ABS, mode, true_rtx, mode),
5396 /* Look for MIN or MAX. */
5398 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
5400 && rtx_equal_p (XEXP (cond, 0), true_rtx)
5401 && rtx_equal_p (XEXP (cond, 1), false_rtx)
5402 && ! side_effects_p (cond))
5407 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
5410 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
5413 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
5416 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
5421 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
5422 second operand is zero, this can be done as (OP Z (mult COND C2)) where
5423 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
5424 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
5425 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
5426 neither 1 or -1, but it isn't worth checking for. */
5428 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
5430 && GET_MODE_CLASS (mode) == MODE_INT
5431 && ! side_effects_p (x))
5433 rtx t = make_compound_operation (true_rtx, SET);
5434 rtx f = make_compound_operation (false_rtx, SET);
5435 rtx cond_op0 = XEXP (cond, 0);
5436 rtx cond_op1 = XEXP (cond, 1);
5437 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
5438 enum machine_mode m = mode;
5439 rtx z = 0, c1 = NULL_RTX;
5441 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
5442 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
5443 || GET_CODE (t) == ASHIFT
5444 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
5445 && rtx_equal_p (XEXP (t, 0), f))
5446 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
5448 /* If an identity-zero op is commutative, check whether there
5449 would be a match if we swapped the operands. */
5450 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
5451 || GET_CODE (t) == XOR)
5452 && rtx_equal_p (XEXP (t, 1), f))
5453 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
5454 else if (GET_CODE (t) == SIGN_EXTEND
5455 && (GET_CODE (XEXP (t, 0)) == PLUS
5456 || GET_CODE (XEXP (t, 0)) == MINUS
5457 || GET_CODE (XEXP (t, 0)) == IOR
5458 || GET_CODE (XEXP (t, 0)) == XOR
5459 || GET_CODE (XEXP (t, 0)) == ASHIFT
5460 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5461 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5462 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5463 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5464 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5465 && (num_sign_bit_copies (f, GET_MODE (f))
5467 (GET_MODE_BITSIZE (mode)
5468 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
5470 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5471 extend_op = SIGN_EXTEND;
5472 m = GET_MODE (XEXP (t, 0));
5474 else if (GET_CODE (t) == SIGN_EXTEND
5475 && (GET_CODE (XEXP (t, 0)) == PLUS
5476 || GET_CODE (XEXP (t, 0)) == IOR
5477 || GET_CODE (XEXP (t, 0)) == XOR)
5478 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5479 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5480 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5481 && (num_sign_bit_copies (f, GET_MODE (f))
5483 (GET_MODE_BITSIZE (mode)
5484 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
5486 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5487 extend_op = SIGN_EXTEND;
5488 m = GET_MODE (XEXP (t, 0));
5490 else if (GET_CODE (t) == ZERO_EXTEND
5491 && (GET_CODE (XEXP (t, 0)) == PLUS
5492 || GET_CODE (XEXP (t, 0)) == MINUS
5493 || GET_CODE (XEXP (t, 0)) == IOR
5494 || GET_CODE (XEXP (t, 0)) == XOR
5495 || GET_CODE (XEXP (t, 0)) == ASHIFT
5496 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
5497 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
5498 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
5499 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5500 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
5501 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
5502 && ((nonzero_bits (f, GET_MODE (f))
5503 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
5506 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
5507 extend_op = ZERO_EXTEND;
5508 m = GET_MODE (XEXP (t, 0));
5510 else if (GET_CODE (t) == ZERO_EXTEND
5511 && (GET_CODE (XEXP (t, 0)) == PLUS
5512 || GET_CODE (XEXP (t, 0)) == IOR
5513 || GET_CODE (XEXP (t, 0)) == XOR)
5514 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5515 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5516 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5517 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5518 && ((nonzero_bits (f, GET_MODE (f))
5519 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5522 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5523 extend_op = ZERO_EXTEND;
5524 m = GET_MODE (XEXP (t, 0));
5529 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
5530 cond_op0, cond_op1),
5531 pc_rtx, pc_rtx, 0, 0);
5532 temp = simplify_gen_binary (MULT, m, temp,
5533 simplify_gen_binary (MULT, m, c1,
5535 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5536 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
5538 if (extend_op != UNKNOWN)
5539 temp = simplify_gen_unary (extend_op, mode, temp, m);
5545 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5546 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5547 negation of a single bit, we can convert this operation to a shift. We
5548 can actually do this more generally, but it doesn't seem worth it. */
5550 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5551 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5552 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5553 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5554 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5555 == GET_MODE_BITSIZE (mode))
5556 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5558 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5559 gen_lowpart (mode, XEXP (cond, 0)), i);
5561 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5562 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5563 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5564 && GET_MODE (XEXP (cond, 0)) == mode
5565 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5566 == nonzero_bits (XEXP (cond, 0), mode)
5567 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5568 return XEXP (cond, 0);
5573 /* Simplify X, a SET expression. Return the new expression. */
5576 simplify_set (rtx x)
5578 rtx src = SET_SRC (x);
5579 rtx dest = SET_DEST (x);
5580 enum machine_mode mode
5581 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5585 /* (set (pc) (return)) gets written as (return). */
5586 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5589 /* Now that we know for sure which bits of SRC we are using, see if we can
5590 simplify the expression for the object knowing that we only need the
5593 if (GET_MODE_CLASS (mode) == MODE_INT
5594 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5596 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
5597 SUBST (SET_SRC (x), src);
5600 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5601 the comparison result and try to simplify it unless we already have used
5602 undobuf.other_insn. */
5603 if ((GET_MODE_CLASS (mode) == MODE_CC
5604 || GET_CODE (src) == COMPARE
5606 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5607 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5608 && COMPARISON_P (*cc_use)
5609 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5611 enum rtx_code old_code = GET_CODE (*cc_use);
5612 enum rtx_code new_code;
5614 int other_changed = 0;
5615 enum machine_mode compare_mode = GET_MODE (dest);
5617 if (GET_CODE (src) == COMPARE)
5618 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5620 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5622 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5625 new_code = old_code;
5626 else if (!CONSTANT_P (tmp))
5628 new_code = GET_CODE (tmp);
5629 op0 = XEXP (tmp, 0);
5630 op1 = XEXP (tmp, 1);
5634 rtx pat = PATTERN (other_insn);
5635 undobuf.other_insn = other_insn;
5636 SUBST (*cc_use, tmp);
5638 /* Attempt to simplify CC user. */
5639 if (GET_CODE (pat) == SET)
5641 rtx new_rtx = simplify_rtx (SET_SRC (pat));
5642 if (new_rtx != NULL_RTX)
5643 SUBST (SET_SRC (pat), new_rtx);
5646 /* Convert X into a no-op move. */
5647 SUBST (SET_DEST (x), pc_rtx);
5648 SUBST (SET_SRC (x), pc_rtx);
5652 /* Simplify our comparison, if possible. */
5653 new_code = simplify_comparison (new_code, &op0, &op1);
5655 #ifdef SELECT_CC_MODE
5656 /* If this machine has CC modes other than CCmode, check to see if we
5657 need to use a different CC mode here. */
5658 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5659 compare_mode = GET_MODE (op0);
5661 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5664 /* If the mode changed, we have to change SET_DEST, the mode in the
5665 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5666 a hard register, just build new versions with the proper mode. If it
5667 is a pseudo, we lose unless it is only time we set the pseudo, in
5668 which case we can safely change its mode. */
5669 if (compare_mode != GET_MODE (dest))
5671 if (can_change_dest_mode (dest, 0, compare_mode))
5673 unsigned int regno = REGNO (dest);
5676 if (regno < FIRST_PSEUDO_REGISTER)
5677 new_dest = gen_rtx_REG (compare_mode, regno);
5680 SUBST_MODE (regno_reg_rtx[regno], compare_mode);
5681 new_dest = regno_reg_rtx[regno];
5684 SUBST (SET_DEST (x), new_dest);
5685 SUBST (XEXP (*cc_use, 0), new_dest);
5692 #endif /* SELECT_CC_MODE */
5694 /* If the code changed, we have to build a new comparison in
5695 undobuf.other_insn. */
5696 if (new_code != old_code)
5698 int other_changed_previously = other_changed;
5699 unsigned HOST_WIDE_INT mask;
5701 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5705 /* If the only change we made was to change an EQ into an NE or
5706 vice versa, OP0 has only one bit that might be nonzero, and OP1
5707 is zero, check if changing the user of the condition code will
5708 produce a valid insn. If it won't, we can keep the original code
5709 in that insn by surrounding our operation with an XOR. */
5711 if (((old_code == NE && new_code == EQ)
5712 || (old_code == EQ && new_code == NE))
5713 && ! other_changed_previously && op1 == const0_rtx
5714 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5715 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5717 rtx pat = PATTERN (other_insn), note = 0;
5719 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5720 && ! check_asm_operands (pat)))
5722 PUT_CODE (*cc_use, old_code);
5725 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5726 op0, GEN_INT (mask));
5732 undobuf.other_insn = other_insn;
5735 /* If we are now comparing against zero, change our source if
5736 needed. If we do not use cc0, we always have a COMPARE. */
5737 if (op1 == const0_rtx && dest == cc0_rtx)
5739 SUBST (SET_SRC (x), op0);
5745 /* Otherwise, if we didn't previously have a COMPARE in the
5746 correct mode, we need one. */
5747 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5749 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5752 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5754 SUBST (SET_SRC (x), op0);
5757 /* Otherwise, update the COMPARE if needed. */
5758 else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
5760 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5766 /* Get SET_SRC in a form where we have placed back any
5767 compound expressions. Then do the checks below. */
5768 src = make_compound_operation (src, SET);
5769 SUBST (SET_SRC (x), src);
5772 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5773 and X being a REG or (subreg (reg)), we may be able to convert this to
5774 (set (subreg:m2 x) (op)).
5776 We can always do this if M1 is narrower than M2 because that means that
5777 we only care about the low bits of the result.
5779 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5780 perform a narrower operation than requested since the high-order bits will
5781 be undefined. On machine where it is defined, this transformation is safe
5782 as long as M1 and M2 have the same number of words. */
5784 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5785 && !OBJECT_P (SUBREG_REG (src))
5786 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5788 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5789 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5790 #ifndef WORD_REGISTER_OPERATIONS
5791 && (GET_MODE_SIZE (GET_MODE (src))
5792 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5794 #ifdef CANNOT_CHANGE_MODE_CLASS
5795 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5796 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5797 GET_MODE (SUBREG_REG (src)),
5801 || (GET_CODE (dest) == SUBREG
5802 && REG_P (SUBREG_REG (dest)))))
5804 SUBST (SET_DEST (x),
5805 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5807 SUBST (SET_SRC (x), SUBREG_REG (src));
5809 src = SET_SRC (x), dest = SET_DEST (x);
5813 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5816 && GET_CODE (src) == SUBREG
5817 && subreg_lowpart_p (src)
5818 && (GET_MODE_BITSIZE (GET_MODE (src))
5819 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5821 rtx inner = SUBREG_REG (src);
5822 enum machine_mode inner_mode = GET_MODE (inner);
5824 /* Here we make sure that we don't have a sign bit on. */
5825 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5826 && (nonzero_bits (inner, inner_mode)
5827 < ((unsigned HOST_WIDE_INT) 1
5828 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5830 SUBST (SET_SRC (x), inner);
5836 #ifdef LOAD_EXTEND_OP
5837 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5838 would require a paradoxical subreg. Replace the subreg with a
5839 zero_extend to avoid the reload that would otherwise be required. */
5841 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5842 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5843 && SUBREG_BYTE (src) == 0
5844 && (GET_MODE_SIZE (GET_MODE (src))
5845 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5846 && MEM_P (SUBREG_REG (src)))
5849 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5850 GET_MODE (src), SUBREG_REG (src)));
5856 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5857 are comparing an item known to be 0 or -1 against 0, use a logical
5858 operation instead. Check for one of the arms being an IOR of the other
5859 arm with some value. We compute three terms to be IOR'ed together. In
5860 practice, at most two will be nonzero. Then we do the IOR's. */
5862 if (GET_CODE (dest) != PC
5863 && GET_CODE (src) == IF_THEN_ELSE
5864 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5865 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5866 && XEXP (XEXP (src, 0), 1) == const0_rtx
5867 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5868 #ifdef HAVE_conditional_move
5869 && ! can_conditionally_move_p (GET_MODE (src))
5871 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5872 GET_MODE (XEXP (XEXP (src, 0), 0)))
5873 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5874 && ! side_effects_p (src))
5876 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5877 ? XEXP (src, 1) : XEXP (src, 2));
5878 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5879 ? XEXP (src, 2) : XEXP (src, 1));
5880 rtx term1 = const0_rtx, term2, term3;
5882 if (GET_CODE (true_rtx) == IOR
5883 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5884 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5885 else if (GET_CODE (true_rtx) == IOR
5886 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5887 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5888 else if (GET_CODE (false_rtx) == IOR
5889 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5890 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5891 else if (GET_CODE (false_rtx) == IOR
5892 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5893 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5895 term2 = simplify_gen_binary (AND, GET_MODE (src),
5896 XEXP (XEXP (src, 0), 0), true_rtx);
5897 term3 = simplify_gen_binary (AND, GET_MODE (src),
5898 simplify_gen_unary (NOT, GET_MODE (src),
5899 XEXP (XEXP (src, 0), 0),
5904 simplify_gen_binary (IOR, GET_MODE (src),
5905 simplify_gen_binary (IOR, GET_MODE (src),
5912 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5913 whole thing fail. */
5914 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5916 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5919 /* Convert this into a field assignment operation, if possible. */
5920 return make_field_assignment (x);
5923 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5927 simplify_logical (rtx x)
5929 enum machine_mode mode = GET_MODE (x);
5930 rtx op0 = XEXP (x, 0);
5931 rtx op1 = XEXP (x, 1);
5933 switch (GET_CODE (x))
5936 /* We can call simplify_and_const_int only if we don't lose
5937 any (sign) bits when converting INTVAL (op1) to
5938 "unsigned HOST_WIDE_INT". */
5939 if (GET_CODE (op1) == CONST_INT
5940 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5941 || INTVAL (op1) > 0))
5943 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5944 if (GET_CODE (x) != AND)
5951 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5952 apply the distributive law and then the inverse distributive
5953 law to see if things simplify. */
5954 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5956 rtx result = distribute_and_simplify_rtx (x, 0);
5960 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5962 rtx result = distribute_and_simplify_rtx (x, 1);
5969 /* If we have (ior (and A B) C), apply the distributive law and then
5970 the inverse distributive law to see if things simplify. */
5972 if (GET_CODE (op0) == AND)
5974 rtx result = distribute_and_simplify_rtx (x, 0);
5979 if (GET_CODE (op1) == AND)
5981 rtx result = distribute_and_simplify_rtx (x, 1);
5994 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5995 operations" because they can be replaced with two more basic operations.
5996 ZERO_EXTEND is also considered "compound" because it can be replaced with
5997 an AND operation, which is simpler, though only one operation.
5999 The function expand_compound_operation is called with an rtx expression
6000 and will convert it to the appropriate shifts and AND operations,
6001 simplifying at each stage.
6003 The function make_compound_operation is called to convert an expression
6004 consisting of shifts and ANDs into the equivalent compound expression.
6005 It is the inverse of this function, loosely speaking. */
6008 expand_compound_operation (rtx x)
6010 unsigned HOST_WIDE_INT pos = 0, len;
6012 unsigned int modewidth;
6015 switch (GET_CODE (x))
6020 /* We can't necessarily use a const_int for a multiword mode;
6021 it depends on implicitly extending the value.
6022 Since we don't know the right way to extend it,
6023 we can't tell whether the implicit way is right.
6025 Even for a mode that is no wider than a const_int,
6026 we can't win, because we need to sign extend one of its bits through
6027 the rest of it, and we don't know which bit. */
6028 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
6031 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6032 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6033 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6034 reloaded. If not for that, MEM's would very rarely be safe.
6036 Reject MODEs bigger than a word, because we might not be able
6037 to reference a two-register group starting with an arbitrary register
6038 (and currently gen_lowpart might crash for a SUBREG). */
6040 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6043 /* Reject MODEs that aren't scalar integers because turning vector
6044 or complex modes into shifts causes problems. */
6046 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6049 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
6050 /* If the inner object has VOIDmode (the only way this can happen
6051 is if it is an ASM_OPERANDS), we can't do anything since we don't
6052 know how much masking to do. */
6061 /* ... fall through ... */
6064 /* If the operand is a CLOBBER, just return it. */
6065 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6068 if (GET_CODE (XEXP (x, 1)) != CONST_INT
6069 || GET_CODE (XEXP (x, 2)) != CONST_INT
6070 || GET_MODE (XEXP (x, 0)) == VOIDmode)
6073 /* Reject MODEs that aren't scalar integers because turning vector
6074 or complex modes into shifts causes problems. */
6076 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6079 len = INTVAL (XEXP (x, 1));
6080 pos = INTVAL (XEXP (x, 2));
6082 /* This should stay within the object being extracted, fail otherwise. */
6083 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
6086 if (BITS_BIG_ENDIAN)
6087 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
6094 /* Convert sign extension to zero extension, if we know that the high
6095 bit is not set, as this is easier to optimize. It will be converted
6096 back to cheaper alternative in make_extraction. */
6097 if (GET_CODE (x) == SIGN_EXTEND
6098 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6099 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6100 & ~(((unsigned HOST_WIDE_INT)
6101 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6105 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6106 rtx temp2 = expand_compound_operation (temp);
6108 /* Make sure this is a profitable operation. */
6109 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
6111 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
6117 /* We can optimize some special cases of ZERO_EXTEND. */
6118 if (GET_CODE (x) == ZERO_EXTEND)
6120 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6121 know that the last value didn't have any inappropriate bits
6123 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6124 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6125 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6126 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6127 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6128 return XEXP (XEXP (x, 0), 0);
6130 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6131 if (GET_CODE (XEXP (x, 0)) == SUBREG
6132 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6133 && subreg_lowpart_p (XEXP (x, 0))
6134 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6135 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6136 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6137 return SUBREG_REG (XEXP (x, 0));
6139 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6140 is a comparison and STORE_FLAG_VALUE permits. This is like
6141 the first case, but it works even when GET_MODE (x) is larger
6142 than HOST_WIDE_INT. */
6143 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6144 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6145 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6146 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6147 <= HOST_BITS_PER_WIDE_INT)
6148 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6149 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6150 return XEXP (XEXP (x, 0), 0);
6152 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6153 if (GET_CODE (XEXP (x, 0)) == SUBREG
6154 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6155 && subreg_lowpart_p (XEXP (x, 0))
6156 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6157 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
6158 <= HOST_BITS_PER_WIDE_INT)
6159 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
6160 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6161 return SUBREG_REG (XEXP (x, 0));
6165 /* If we reach here, we want to return a pair of shifts. The inner
6166 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6167 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6168 logical depending on the value of UNSIGNEDP.
6170 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6171 converted into an AND of a shift.
6173 We must check for the case where the left shift would have a negative
6174 count. This can happen in a case like (x >> 31) & 255 on machines
6175 that can't shift by a constant. On those machines, we would first
6176 combine the shift with the AND to produce a variable-position
6177 extraction. Then the constant of 31 would be substituted in to produce
6178 a such a position. */
6180 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
6181 if (modewidth + len >= pos)
6183 enum machine_mode mode = GET_MODE (x);
6184 tem = gen_lowpart (mode, XEXP (x, 0));
6185 if (!tem || GET_CODE (tem) == CLOBBER)
6187 tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6188 tem, modewidth - pos - len);
6189 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6190 mode, tem, modewidth - len);
6192 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6193 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6194 simplify_shift_const (NULL_RTX, LSHIFTRT,
6197 ((HOST_WIDE_INT) 1 << len) - 1);
6199 /* Any other cases we can't handle. */
6202 /* If we couldn't do this for some reason, return the original
6204 if (GET_CODE (tem) == CLOBBER)
6210 /* X is a SET which contains an assignment of one object into
6211 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6212 or certain SUBREGS). If possible, convert it into a series of
6215 We half-heartedly support variable positions, but do not at all
6216 support variable lengths. */
6219 expand_field_assignment (const_rtx x)
6222 rtx pos; /* Always counts from low bit. */
6224 rtx mask, cleared, masked;
6225 enum machine_mode compute_mode;
6227 /* Loop until we find something we can't simplify. */
6230 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6231 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6233 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6234 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
6235 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6237 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6238 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
6240 inner = XEXP (SET_DEST (x), 0);
6241 len = INTVAL (XEXP (SET_DEST (x), 1));
6242 pos = XEXP (SET_DEST (x), 2);
6244 /* A constant position should stay within the width of INNER. */
6245 if (GET_CODE (pos) == CONST_INT
6246 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
6249 if (BITS_BIG_ENDIAN)
6251 if (GET_CODE (pos) == CONST_INT)
6252 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
6254 else if (GET_CODE (pos) == MINUS
6255 && GET_CODE (XEXP (pos, 1)) == CONST_INT
6256 && (INTVAL (XEXP (pos, 1))
6257 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
6258 /* If position is ADJUST - X, new position is X. */
6259 pos = XEXP (pos, 0);
6261 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6262 GEN_INT (GET_MODE_BITSIZE (
6269 /* A SUBREG between two modes that occupy the same numbers of words
6270 can be done by moving the SUBREG to the source. */
6271 else if (GET_CODE (SET_DEST (x)) == SUBREG
6272 /* We need SUBREGs to compute nonzero_bits properly. */
6273 && nonzero_sign_valid
6274 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6275 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6276 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6277 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6279 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6281 (GET_MODE (SUBREG_REG (SET_DEST (x))),
6288 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6289 inner = SUBREG_REG (inner);
6291 compute_mode = GET_MODE (inner);
6293 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6294 if (! SCALAR_INT_MODE_P (compute_mode))
6296 enum machine_mode imode;
6298 /* Don't do anything for vector or complex integral types. */
6299 if (! FLOAT_MODE_P (compute_mode))
6302 /* Try to find an integral mode to pun with. */
6303 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6304 if (imode == BLKmode)
6307 compute_mode = imode;
6308 inner = gen_lowpart (imode, inner);
6311 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6312 if (len >= HOST_BITS_PER_WIDE_INT)
6315 /* Now compute the equivalent expression. Make a copy of INNER
6316 for the SET_DEST in case it is a MEM into which we will substitute;
6317 we don't want shared RTL in that case. */
6318 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6319 cleared = simplify_gen_binary (AND, compute_mode,
6320 simplify_gen_unary (NOT, compute_mode,
6321 simplify_gen_binary (ASHIFT,
6326 masked = simplify_gen_binary (ASHIFT, compute_mode,
6327 simplify_gen_binary (
6329 gen_lowpart (compute_mode, SET_SRC (x)),
6333 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
6334 simplify_gen_binary (IOR, compute_mode,
6341 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6342 it is an RTX that represents a variable starting position; otherwise,
6343 POS is the (constant) starting bit position (counted from the LSB).
6345 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6348 IN_DEST is nonzero if this is a reference in the destination of a
6349 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6350 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6353 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6354 ZERO_EXTRACT should be built even for bits starting at bit 0.
6356 MODE is the desired mode of the result (if IN_DEST == 0).
6358 The result is an RTX for the extraction or NULL_RTX if the target
6362 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6363 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6364 int in_dest, int in_compare)
6366 /* This mode describes the size of the storage area
6367 to fetch the overall value from. Within that, we
6368 ignore the POS lowest bits, etc. */
6369 enum machine_mode is_mode = GET_MODE (inner);
6370 enum machine_mode inner_mode;
6371 enum machine_mode wanted_inner_mode;
6372 enum machine_mode wanted_inner_reg_mode = word_mode;
6373 enum machine_mode pos_mode = word_mode;
6374 enum machine_mode extraction_mode = word_mode;
6375 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6377 rtx orig_pos_rtx = pos_rtx;
6378 HOST_WIDE_INT orig_pos;
6380 if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6382 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6383 consider just the QI as the memory to extract from.
6384 The subreg adds or removes high bits; its mode is
6385 irrelevant to the meaning of this extraction,
6386 since POS and LEN count from the lsb. */
6387 if (MEM_P (SUBREG_REG (inner)))
6388 is_mode = GET_MODE (SUBREG_REG (inner));
6389 inner = SUBREG_REG (inner);
6391 else if (GET_CODE (inner) == ASHIFT
6392 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6393 && pos_rtx == 0 && pos == 0
6394 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6396 /* We're extracting the least significant bits of an rtx
6397 (ashift X (const_int C)), where LEN > C. Extract the
6398 least significant (LEN - C) bits of X, giving an rtx
6399 whose mode is MODE, then shift it left C times. */
6400 new_rtx = make_extraction (mode, XEXP (inner, 0),
6401 0, 0, len - INTVAL (XEXP (inner, 1)),
6402 unsignedp, in_dest, in_compare);
6404 return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
6407 inner_mode = GET_MODE (inner);
6409 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6410 pos = INTVAL (pos_rtx), pos_rtx = 0;
6412 /* See if this can be done without an extraction. We never can if the
6413 width of the field is not the same as that of some integer mode. For
6414 registers, we can only avoid the extraction if the position is at the
6415 low-order bit and this is either not in the destination or we have the
6416 appropriate STRICT_LOW_PART operation available.
6418 For MEM, we can avoid an extract if the field starts on an appropriate
6419 boundary and we can change the mode of the memory reference. */
6421 if (tmode != BLKmode
6422 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6424 && (inner_mode == tmode
6426 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
6427 GET_MODE_BITSIZE (inner_mode))
6428 || reg_truncated_to_mode (tmode, inner))
6431 && have_insn_for (STRICT_LOW_PART, tmode))))
6432 || (MEM_P (inner) && pos_rtx == 0
6434 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6435 : BITS_PER_UNIT)) == 0
6436 /* We can't do this if we are widening INNER_MODE (it
6437 may not be aligned, for one thing). */
6438 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6439 && (inner_mode == tmode
6440 || (! mode_dependent_address_p (XEXP (inner, 0))
6441 && ! MEM_VOLATILE_P (inner))))))
6443 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6444 field. If the original and current mode are the same, we need not
6445 adjust the offset. Otherwise, we do if bytes big endian.
6447 If INNER is not a MEM, get a piece consisting of just the field
6448 of interest (in this case POS % BITS_PER_WORD must be 0). */
6452 HOST_WIDE_INT offset;
6454 /* POS counts from lsb, but make OFFSET count in memory order. */
6455 if (BYTES_BIG_ENDIAN)
6456 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6458 offset = pos / BITS_PER_UNIT;
6460 new_rtx = adjust_address_nv (inner, tmode, offset);
6462 else if (REG_P (inner))
6464 if (tmode != inner_mode)
6466 /* We can't call gen_lowpart in a DEST since we
6467 always want a SUBREG (see below) and it would sometimes
6468 return a new hard register. */
6471 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6473 if (WORDS_BIG_ENDIAN
6474 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6475 final_word = ((GET_MODE_SIZE (inner_mode)
6476 - GET_MODE_SIZE (tmode))
6477 / UNITS_PER_WORD) - final_word;
6479 final_word *= UNITS_PER_WORD;
6480 if (BYTES_BIG_ENDIAN &&
6481 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6482 final_word += (GET_MODE_SIZE (inner_mode)
6483 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6485 /* Avoid creating invalid subregs, for example when
6486 simplifying (x>>32)&255. */
6487 if (!validate_subreg (tmode, inner_mode, inner, final_word))
6490 new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
6493 new_rtx = gen_lowpart (tmode, inner);
6499 new_rtx = force_to_mode (inner, tmode,
6500 len >= HOST_BITS_PER_WIDE_INT
6501 ? ~(unsigned HOST_WIDE_INT) 0
6502 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6505 /* If this extraction is going into the destination of a SET,
6506 make a STRICT_LOW_PART unless we made a MEM. */
6509 return (MEM_P (new_rtx) ? new_rtx
6510 : (GET_CODE (new_rtx) != SUBREG
6511 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6512 : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
6517 if (GET_CODE (new_rtx) == CONST_INT)
6518 return gen_int_mode (INTVAL (new_rtx), mode);
6520 /* If we know that no extraneous bits are set, and that the high
6521 bit is not set, convert the extraction to the cheaper of
6522 sign and zero extension, that are equivalent in these cases. */
6523 if (flag_expensive_optimizations
6524 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6525 && ((nonzero_bits (new_rtx, tmode)
6526 & ~(((unsigned HOST_WIDE_INT)
6527 GET_MODE_MASK (tmode))
6531 rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
6532 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
6534 /* Prefer ZERO_EXTENSION, since it gives more information to
6536 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6541 /* Otherwise, sign- or zero-extend unless we already are in the
6544 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6548 /* Unless this is a COMPARE or we have a funny memory reference,
6549 don't do anything with zero-extending field extracts starting at
6550 the low-order bit since they are simple AND operations. */
6551 if (pos_rtx == 0 && pos == 0 && ! in_dest
6552 && ! in_compare && unsignedp)
6555 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
6556 if the position is not a constant and the length is not 1. In all
6557 other cases, we would only be going outside our object in cases when
6558 an original shift would have been undefined. */
6560 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6561 || (pos_rtx != 0 && len != 1)))
6564 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6565 and the mode for the result. */
6566 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6568 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6569 pos_mode = mode_for_extraction (EP_insv, 2);
6570 extraction_mode = mode_for_extraction (EP_insv, 3);
6573 if (! in_dest && unsignedp
6574 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6576 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6577 pos_mode = mode_for_extraction (EP_extzv, 3);
6578 extraction_mode = mode_for_extraction (EP_extzv, 0);
6581 if (! in_dest && ! unsignedp
6582 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6584 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6585 pos_mode = mode_for_extraction (EP_extv, 3);
6586 extraction_mode = mode_for_extraction (EP_extv, 0);
6589 /* Never narrow an object, since that might not be safe. */
6591 if (mode != VOIDmode
6592 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6593 extraction_mode = mode;
6595 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6596 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6597 pos_mode = GET_MODE (pos_rtx);
6599 /* If this is not from memory, the desired mode is the preferred mode
6600 for an extraction pattern's first input operand, or word_mode if there
6603 wanted_inner_mode = wanted_inner_reg_mode;
6606 /* Be careful not to go beyond the extracted object and maintain the
6607 natural alignment of the memory. */
6608 wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
6609 while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
6610 > GET_MODE_BITSIZE (wanted_inner_mode))
6612 wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
6613 gcc_assert (wanted_inner_mode != VOIDmode);
6616 /* If we have to change the mode of memory and cannot, the desired mode
6617 is EXTRACTION_MODE. */
6618 if (inner_mode != wanted_inner_mode
6619 && (mode_dependent_address_p (XEXP (inner, 0))
6620 || MEM_VOLATILE_P (inner)
6622 wanted_inner_mode = extraction_mode;
6627 if (BITS_BIG_ENDIAN)
6629 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6630 BITS_BIG_ENDIAN style. If position is constant, compute new
6631 position. Otherwise, build subtraction.
6632 Note that POS is relative to the mode of the original argument.
6633 If it's a MEM we need to recompute POS relative to that.
6634 However, if we're extracting from (or inserting into) a register,
6635 we want to recompute POS relative to wanted_inner_mode. */
6636 int width = (MEM_P (inner)
6637 ? GET_MODE_BITSIZE (is_mode)
6638 : GET_MODE_BITSIZE (wanted_inner_mode));
6641 pos = width - len - pos;
6644 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6645 /* POS may be less than 0 now, but we check for that below.
6646 Note that it can only be less than 0 if !MEM_P (inner). */
6649 /* If INNER has a wider mode, and this is a constant extraction, try to
6650 make it smaller and adjust the byte to point to the byte containing
6652 if (wanted_inner_mode != VOIDmode
6653 && inner_mode != wanted_inner_mode
6655 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6657 && ! mode_dependent_address_p (XEXP (inner, 0))
6658 && ! MEM_VOLATILE_P (inner))
6662 /* The computations below will be correct if the machine is big
6663 endian in both bits and bytes or little endian in bits and bytes.
6664 If it is mixed, we must adjust. */
6666 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6667 adjust OFFSET to compensate. */
6668 if (BYTES_BIG_ENDIAN
6669 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6670 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6672 /* We can now move to the desired byte. */
6673 offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
6674 * GET_MODE_SIZE (wanted_inner_mode);
6675 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6677 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6678 && is_mode != wanted_inner_mode)
6679 offset = (GET_MODE_SIZE (is_mode)
6680 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6682 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6685 /* If INNER is not memory, we can always get it into the proper mode. If we
6686 are changing its mode, POS must be a constant and smaller than the size
6688 else if (!MEM_P (inner))
6690 if (GET_MODE (inner) != wanted_inner_mode
6692 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6698 inner = force_to_mode (inner, wanted_inner_mode,
6700 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6701 ? ~(unsigned HOST_WIDE_INT) 0
6702 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6707 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6708 have to zero extend. Otherwise, we can just use a SUBREG. */
6710 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6712 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6714 /* If we know that no extraneous bits are set, and that the high
6715 bit is not set, convert extraction to cheaper one - either
6716 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6718 if (flag_expensive_optimizations
6719 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6720 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6721 & ~(((unsigned HOST_WIDE_INT)
6722 GET_MODE_MASK (GET_MODE (pos_rtx)))
6726 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6728 /* Prefer ZERO_EXTENSION, since it gives more information to
6730 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6735 else if (pos_rtx != 0
6736 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6737 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6739 /* Make POS_RTX unless we already have it and it is correct. If we don't
6740 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6742 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6743 pos_rtx = orig_pos_rtx;
6745 else if (pos_rtx == 0)
6746 pos_rtx = GEN_INT (pos);
6748 /* Make the required operation. See if we can use existing rtx. */
6749 new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6750 extraction_mode, inner, GEN_INT (len), pos_rtx);
6752 new_rtx = gen_lowpart (mode, new_rtx);
6757 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6758 with any other operations in X. Return X without that shift if so. */
6761 extract_left_shift (rtx x, int count)
6763 enum rtx_code code = GET_CODE (x);
6764 enum machine_mode mode = GET_MODE (x);
6770 /* This is the shift itself. If it is wide enough, we will return
6771 either the value being shifted if the shift count is equal to
6772 COUNT or a shift for the difference. */
6773 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6774 && INTVAL (XEXP (x, 1)) >= count)
6775 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6776 INTVAL (XEXP (x, 1)) - count);
6780 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6781 return simplify_gen_unary (code, mode, tem, mode);
6785 case PLUS: case IOR: case XOR: case AND:
6786 /* If we can safely shift this constant and we find the inner shift,
6787 make a new operation. */
6788 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6789 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6790 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6791 return simplify_gen_binary (code, mode, tem,
6792 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6803 /* Look at the expression rooted at X. Look for expressions
6804 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6805 Form these expressions.
6807 Return the new rtx, usually just X.
6809 Also, for machines like the VAX that don't have logical shift insns,
6810 try to convert logical to arithmetic shift operations in cases where
6811 they are equivalent. This undoes the canonicalizations to logical
6812 shifts done elsewhere.
6814 We try, as much as possible, to re-use rtl expressions to save memory.
6816 IN_CODE says what kind of expression we are processing. Normally, it is
6817 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6818 being kludges), it is MEM. When processing the arguments of a comparison
6819 or a COMPARE against zero, it is COMPARE. */
6822 make_compound_operation (rtx x, enum rtx_code in_code)
6824 enum rtx_code code = GET_CODE (x);
6825 enum machine_mode mode = GET_MODE (x);
6826 int mode_width = GET_MODE_BITSIZE (mode);
6828 enum rtx_code next_code;
6834 /* Select the code to be used in recursive calls. Once we are inside an
6835 address, we stay there. If we have a comparison, set to COMPARE,
6836 but once inside, go back to our default of SET. */
6838 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6839 : ((code == COMPARE || COMPARISON_P (x))
6840 && XEXP (x, 1) == const0_rtx) ? COMPARE
6841 : in_code == COMPARE ? SET : in_code);
6843 /* Process depending on the code of this operation. If NEW is set
6844 nonzero, it will be returned. */
6849 /* Convert shifts by constants into multiplications if inside
6851 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6852 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6853 && INTVAL (XEXP (x, 1)) >= 0)
6855 new_rtx = make_compound_operation (XEXP (x, 0), next_code);
6856 new_rtx = gen_rtx_MULT (mode, new_rtx,
6857 GEN_INT ((HOST_WIDE_INT) 1
6858 << INTVAL (XEXP (x, 1))));
6863 /* If the second operand is not a constant, we can't do anything
6865 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6868 /* If the constant is a power of two minus one and the first operand
6869 is a logical right shift, make an extraction. */
6870 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6871 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6873 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6874 new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
6875 0, in_code == COMPARE);
6878 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6879 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6880 && subreg_lowpart_p (XEXP (x, 0))
6881 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6882 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6884 new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6886 new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
6887 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6888 0, in_code == COMPARE);
6890 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6891 else if ((GET_CODE (XEXP (x, 0)) == XOR
6892 || GET_CODE (XEXP (x, 0)) == IOR)
6893 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6894 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6895 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6897 /* Apply the distributive law, and then try to make extractions. */
6898 new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6899 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6901 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6903 new_rtx = make_compound_operation (new_rtx, in_code);
6906 /* If we are have (and (rotate X C) M) and C is larger than the number
6907 of bits in M, this is an extraction. */
6909 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6910 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6911 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6912 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6914 new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6915 new_rtx = make_extraction (mode, new_rtx,
6916 (GET_MODE_BITSIZE (mode)
6917 - INTVAL (XEXP (XEXP (x, 0), 1))),
6918 NULL_RTX, i, 1, 0, in_code == COMPARE);
6921 /* On machines without logical shifts, if the operand of the AND is
6922 a logical shift and our mask turns off all the propagated sign
6923 bits, we can replace the logical shift with an arithmetic shift. */
6924 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6925 && !have_insn_for (LSHIFTRT, mode)
6926 && have_insn_for (ASHIFTRT, mode)
6927 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6928 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6929 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6930 && mode_width <= HOST_BITS_PER_WIDE_INT)
6932 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6934 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6935 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6937 gen_rtx_ASHIFTRT (mode,
6938 make_compound_operation
6939 (XEXP (XEXP (x, 0), 0), next_code),
6940 XEXP (XEXP (x, 0), 1)));
6943 /* If the constant is one less than a power of two, this might be
6944 representable by an extraction even if no shift is present.
6945 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6946 we are in a COMPARE. */
6947 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6948 new_rtx = make_extraction (mode,
6949 make_compound_operation (XEXP (x, 0),
6951 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6953 /* If we are in a comparison and this is an AND with a power of two,
6954 convert this into the appropriate bit extract. */
6955 else if (in_code == COMPARE
6956 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6957 new_rtx = make_extraction (mode,
6958 make_compound_operation (XEXP (x, 0),
6960 i, NULL_RTX, 1, 1, 0, 1);
6965 /* If the sign bit is known to be zero, replace this with an
6966 arithmetic shift. */
6967 if (have_insn_for (ASHIFTRT, mode)
6968 && ! have_insn_for (LSHIFTRT, mode)
6969 && mode_width <= HOST_BITS_PER_WIDE_INT
6970 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6972 new_rtx = gen_rtx_ASHIFTRT (mode,
6973 make_compound_operation (XEXP (x, 0),
6979 /* ... fall through ... */
6985 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6986 this is a SIGN_EXTRACT. */
6987 if (GET_CODE (rhs) == CONST_INT
6988 && GET_CODE (lhs) == ASHIFT
6989 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6990 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6992 new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
6993 new_rtx = make_extraction (mode, new_rtx,
6994 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6995 NULL_RTX, mode_width - INTVAL (rhs),
6996 code == LSHIFTRT, 0, in_code == COMPARE);
7000 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7001 If so, try to merge the shifts into a SIGN_EXTEND. We could
7002 also do this for some cases of SIGN_EXTRACT, but it doesn't
7003 seem worth the effort; the case checked for occurs on Alpha. */
7006 && ! (GET_CODE (lhs) == SUBREG
7007 && (OBJECT_P (SUBREG_REG (lhs))))
7008 && GET_CODE (rhs) == CONST_INT
7009 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7010 && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7011 new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7012 0, NULL_RTX, mode_width - INTVAL (rhs),
7013 code == LSHIFTRT, 0, in_code == COMPARE);
7018 /* Call ourselves recursively on the inner expression. If we are
7019 narrowing the object and it has a different RTL code from
7020 what it originally did, do this SUBREG as a force_to_mode. */
7022 tem = make_compound_operation (SUBREG_REG (x), in_code);
7026 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
7032 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
7033 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
7034 && subreg_lowpart_p (x))
7036 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
7039 /* If we have something other than a SUBREG, we might have
7040 done an expansion, so rerun ourselves. */
7041 if (GET_CODE (newer) != SUBREG)
7042 newer = make_compound_operation (newer, in_code);
7058 x = gen_lowpart (mode, new_rtx);
7059 code = GET_CODE (x);
7062 /* Now recursively process each operand of this operation. */
7063 fmt = GET_RTX_FORMAT (code);
7064 for (i = 0; i < GET_RTX_LENGTH (code); i++)
7067 new_rtx = make_compound_operation (XEXP (x, i), next_code);
7068 SUBST (XEXP (x, i), new_rtx);
7071 /* If this is a commutative operation, the changes to the operands
7072 may have made it noncanonical. */
7073 if (COMMUTATIVE_ARITH_P (x)
7074 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7077 SUBST (XEXP (x, 0), XEXP (x, 1));
7078 SUBST (XEXP (x, 1), tem);
7084 /* Given M see if it is a value that would select a field of bits
7085 within an item, but not the entire word. Return -1 if not.
7086 Otherwise, return the starting position of the field, where 0 is the
7089 *PLEN is set to the length of the field. */
7092 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7094 /* Get the bit number of the first 1 bit from the right, -1 if none. */
7095 int pos = exact_log2 (m & -m);
7099 /* Now shift off the low-order zero bits and see if we have a
7100 power of two minus 1. */
7101 len = exact_log2 ((m >> pos) + 1);
7110 /* If X refers to a register that equals REG in value, replace these
7111 references with REG. */
7113 canon_reg_for_combine (rtx x, rtx reg)
7120 enum rtx_code code = GET_CODE (x);
7121 switch (GET_RTX_CLASS (code))
7124 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7125 if (op0 != XEXP (x, 0))
7126 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7131 case RTX_COMM_ARITH:
7132 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7133 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7134 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7135 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7139 case RTX_COMM_COMPARE:
7140 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7141 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7142 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7143 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7144 GET_MODE (op0), op0, op1);
7148 case RTX_BITFIELD_OPS:
7149 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7150 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7151 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7152 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7153 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7154 GET_MODE (op0), op0, op1, op2);
7159 if (rtx_equal_p (get_last_value (reg), x)
7160 || rtx_equal_p (reg, get_last_value (x)))
7169 fmt = GET_RTX_FORMAT (code);
7171 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7174 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7175 if (op != XEXP (x, i))
7185 else if (fmt[i] == 'E')
7188 for (j = 0; j < XVECLEN (x, i); j++)
7190 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
7191 if (op != XVECEXP (x, i, j))
7198 XVECEXP (x, i, j) = op;
7209 /* Return X converted to MODE. If the value is already truncated to
7210 MODE we can just return a subreg even though in the general case we
7211 would need an explicit truncation. */
7214 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
7216 if (GET_MODE_SIZE (GET_MODE (x)) <= GET_MODE_SIZE (mode)
7217 || TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
7218 GET_MODE_BITSIZE (GET_MODE (x)))
7219 || (REG_P (x) && reg_truncated_to_mode (mode, x)))
7220 return gen_lowpart (mode, x);
7222 return simplify_gen_unary (TRUNCATE, mode, x, GET_MODE (x));
7225 /* See if X can be simplified knowing that we will only refer to it in
7226 MODE and will only refer to those bits that are nonzero in MASK.
7227 If other bits are being computed or if masking operations are done
7228 that select a superset of the bits in MASK, they can sometimes be
7231 Return a possibly simplified expression, but always convert X to
7232 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
7234 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
7235 are all off in X. This is used when X will be complemented, by either
7236 NOT, NEG, or XOR. */
7239 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
7242 enum rtx_code code = GET_CODE (x);
7243 int next_select = just_select || code == XOR || code == NOT || code == NEG;
7244 enum machine_mode op_mode;
7245 unsigned HOST_WIDE_INT fuller_mask, nonzero;
7248 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
7249 code below will do the wrong thing since the mode of such an
7250 expression is VOIDmode.
7252 Also do nothing if X is a CLOBBER; this can happen if X was
7253 the return value from a call to gen_lowpart. */
7254 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
7257 /* We want to perform the operation is its present mode unless we know
7258 that the operation is valid in MODE, in which case we do the operation
7260 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
7261 && have_insn_for (code, mode))
7262 ? mode : GET_MODE (x));
7264 /* It is not valid to do a right-shift in a narrower mode
7265 than the one it came in with. */
7266 if ((code == LSHIFTRT || code == ASHIFTRT)
7267 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
7268 op_mode = GET_MODE (x);
7270 /* Truncate MASK to fit OP_MODE. */
7272 mask &= GET_MODE_MASK (op_mode);
7274 /* When we have an arithmetic operation, or a shift whose count we
7275 do not know, we need to assume that all bits up to the highest-order
7276 bit in MASK will be needed. This is how we form such a mask. */
7277 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
7278 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
7280 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
7283 /* Determine what bits of X are guaranteed to be (non)zero. */
7284 nonzero = nonzero_bits (x, mode);
7286 /* If none of the bits in X are needed, return a zero. */
7287 if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
7290 /* If X is a CONST_INT, return a new one. Do this here since the
7291 test below will fail. */
7292 if (GET_CODE (x) == CONST_INT)
7294 if (SCALAR_INT_MODE_P (mode))
7295 return gen_int_mode (INTVAL (x) & mask, mode);
7298 x = GEN_INT (INTVAL (x) & mask);
7299 return gen_lowpart_common (mode, x);
7303 /* If X is narrower than MODE and we want all the bits in X's mode, just
7304 get X in the proper mode. */
7305 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
7306 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
7307 return gen_lowpart (mode, x);
7312 /* If X is a (clobber (const_int)), return it since we know we are
7313 generating something that won't match. */
7320 x = expand_compound_operation (x);
7321 if (GET_CODE (x) != code)
7322 return force_to_mode (x, mode, mask, next_select);
7326 if (subreg_lowpart_p (x)
7327 /* We can ignore the effect of this SUBREG if it narrows the mode or
7328 if the constant masks to zero all the bits the mode doesn't
7330 && ((GET_MODE_SIZE (GET_MODE (x))
7331 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
7333 & GET_MODE_MASK (GET_MODE (x))
7334 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
7335 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
7339 /* If this is an AND with a constant, convert it into an AND
7340 whose constant is the AND of that constant with MASK. If it
7341 remains an AND of MASK, delete it since it is redundant. */
7343 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
7345 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
7346 mask & INTVAL (XEXP (x, 1)));
7348 /* If X is still an AND, see if it is an AND with a mask that
7349 is just some low-order bits. If so, and it is MASK, we don't
7352 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7353 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
7357 /* If it remains an AND, try making another AND with the bits
7358 in the mode mask that aren't in MASK turned on. If the
7359 constant in the AND is wide enough, this might make a
7360 cheaper constant. */
7362 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
7363 && GET_MODE_MASK (GET_MODE (x)) != mask
7364 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
7366 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
7367 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
7368 int width = GET_MODE_BITSIZE (GET_MODE (x));
7371 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
7372 number, sign extend it. */
7373 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
7374 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7375 cval |= (HOST_WIDE_INT) -1 << width;
7377 y = simplify_gen_binary (AND, GET_MODE (x),
7378 XEXP (x, 0), GEN_INT (cval));
7379 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7389 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7390 low-order bits (as in an alignment operation) and FOO is already
7391 aligned to that boundary, mask C1 to that boundary as well.
7392 This may eliminate that PLUS and, later, the AND. */
7395 unsigned int width = GET_MODE_BITSIZE (mode);
7396 unsigned HOST_WIDE_INT smask = mask;
7398 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7399 number, sign extend it. */
7401 if (width < HOST_BITS_PER_WIDE_INT
7402 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7403 smask |= (HOST_WIDE_INT) -1 << width;
7405 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7406 && exact_log2 (- smask) >= 0
7407 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7408 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7409 return force_to_mode (plus_constant (XEXP (x, 0),
7410 (INTVAL (XEXP (x, 1)) & smask)),
7411 mode, smask, next_select);
7414 /* ... fall through ... */
7417 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7418 most significant bit in MASK since carries from those bits will
7419 affect the bits we are interested in. */
7424 /* If X is (minus C Y) where C's least set bit is larger than any bit
7425 in the mask, then we may replace with (neg Y). */
7426 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7427 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7428 & -INTVAL (XEXP (x, 0))))
7431 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7433 return force_to_mode (x, mode, mask, next_select);
7436 /* Similarly, if C contains every bit in the fuller_mask, then we may
7437 replace with (not Y). */
7438 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7439 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7440 == INTVAL (XEXP (x, 0))))
7442 x = simplify_gen_unary (NOT, GET_MODE (x),
7443 XEXP (x, 1), GET_MODE (x));
7444 return force_to_mode (x, mode, mask, next_select);
7452 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7453 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7454 operation which may be a bitfield extraction. Ensure that the
7455 constant we form is not wider than the mode of X. */
7457 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7458 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7459 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7460 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7461 && GET_CODE (XEXP (x, 1)) == CONST_INT
7462 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7463 + floor_log2 (INTVAL (XEXP (x, 1))))
7464 < GET_MODE_BITSIZE (GET_MODE (x)))
7465 && (INTVAL (XEXP (x, 1))
7466 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7468 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7469 << INTVAL (XEXP (XEXP (x, 0), 1)));
7470 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
7471 XEXP (XEXP (x, 0), 0), temp);
7472 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
7473 XEXP (XEXP (x, 0), 1));
7474 return force_to_mode (x, mode, mask, next_select);
7478 /* For most binary operations, just propagate into the operation and
7479 change the mode if we have an operation of that mode. */
7481 op0 = gen_lowpart_or_truncate (op_mode,
7482 force_to_mode (XEXP (x, 0), mode, mask,
7484 op1 = gen_lowpart_or_truncate (op_mode,
7485 force_to_mode (XEXP (x, 1), mode, mask,
7488 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7489 x = simplify_gen_binary (code, op_mode, op0, op1);
7493 /* For left shifts, do the same, but just for the first operand.
7494 However, we cannot do anything with shifts where we cannot
7495 guarantee that the counts are smaller than the size of the mode
7496 because such a count will have a different meaning in a
7499 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7500 && INTVAL (XEXP (x, 1)) >= 0
7501 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7502 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7503 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7504 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7507 /* If the shift count is a constant and we can do arithmetic in
7508 the mode of the shift, refine which bits we need. Otherwise, use the
7509 conservative form of the mask. */
7510 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7511 && INTVAL (XEXP (x, 1)) >= 0
7512 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7513 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7514 mask >>= INTVAL (XEXP (x, 1));
7518 op0 = gen_lowpart_or_truncate (op_mode,
7519 force_to_mode (XEXP (x, 0), op_mode,
7520 mask, next_select));
7522 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7523 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
7527 /* Here we can only do something if the shift count is a constant,
7528 this shift constant is valid for the host, and we can do arithmetic
7531 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7532 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7533 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7535 rtx inner = XEXP (x, 0);
7536 unsigned HOST_WIDE_INT inner_mask;
7538 /* Select the mask of the bits we need for the shift operand. */
7539 inner_mask = mask << INTVAL (XEXP (x, 1));
7541 /* We can only change the mode of the shift if we can do arithmetic
7542 in the mode of the shift and INNER_MASK is no wider than the
7543 width of X's mode. */
7544 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7545 op_mode = GET_MODE (x);
7547 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
7549 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7550 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7553 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7554 shift and AND produces only copies of the sign bit (C2 is one less
7555 than a power of two), we can do this with just a shift. */
7557 if (GET_CODE (x) == LSHIFTRT
7558 && GET_CODE (XEXP (x, 1)) == CONST_INT
7559 /* The shift puts one of the sign bit copies in the least significant
7561 && ((INTVAL (XEXP (x, 1))
7562 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7563 >= GET_MODE_BITSIZE (GET_MODE (x)))
7564 && exact_log2 (mask + 1) >= 0
7565 /* Number of bits left after the shift must be more than the mask
7567 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7568 <= GET_MODE_BITSIZE (GET_MODE (x)))
7569 /* Must be more sign bit copies than the mask needs. */
7570 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7571 >= exact_log2 (mask + 1)))
7572 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7573 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7574 - exact_log2 (mask + 1)));
7579 /* If we are just looking for the sign bit, we don't need this shift at
7580 all, even if it has a variable count. */
7581 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7582 && (mask == ((unsigned HOST_WIDE_INT) 1
7583 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7584 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7586 /* If this is a shift by a constant, get a mask that contains those bits
7587 that are not copies of the sign bit. We then have two cases: If
7588 MASK only includes those bits, this can be a logical shift, which may
7589 allow simplifications. If MASK is a single-bit field not within
7590 those bits, we are requesting a copy of the sign bit and hence can
7591 shift the sign bit to the appropriate location. */
7593 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7594 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7598 /* If the considered data is wider than HOST_WIDE_INT, we can't
7599 represent a mask for all its bits in a single scalar.
7600 But we only care about the lower bits, so calculate these. */
7602 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7604 nonzero = ~(HOST_WIDE_INT) 0;
7606 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7607 is the number of bits a full-width mask would have set.
7608 We need only shift if these are fewer than nonzero can
7609 hold. If not, we must keep all bits set in nonzero. */
7611 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7612 < HOST_BITS_PER_WIDE_INT)
7613 nonzero >>= INTVAL (XEXP (x, 1))
7614 + HOST_BITS_PER_WIDE_INT
7615 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7619 nonzero = GET_MODE_MASK (GET_MODE (x));
7620 nonzero >>= INTVAL (XEXP (x, 1));
7623 if ((mask & ~nonzero) == 0)
7625 x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
7626 XEXP (x, 0), INTVAL (XEXP (x, 1)));
7627 if (GET_CODE (x) != ASHIFTRT)
7628 return force_to_mode (x, mode, mask, next_select);
7631 else if ((i = exact_log2 (mask)) >= 0)
7633 x = simplify_shift_const
7634 (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7635 GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7637 if (GET_CODE (x) != ASHIFTRT)
7638 return force_to_mode (x, mode, mask, next_select);
7642 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7643 even if the shift count isn't a constant. */
7645 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7646 XEXP (x, 0), XEXP (x, 1));
7650 /* If this is a zero- or sign-extension operation that just affects bits
7651 we don't care about, remove it. Be sure the call above returned
7652 something that is still a shift. */
7654 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7655 && GET_CODE (XEXP (x, 1)) == CONST_INT
7656 && INTVAL (XEXP (x, 1)) >= 0
7657 && (INTVAL (XEXP (x, 1))
7658 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7659 && GET_CODE (XEXP (x, 0)) == ASHIFT
7660 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7661 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7668 /* If the shift count is constant and we can do computations
7669 in the mode of X, compute where the bits we care about are.
7670 Otherwise, we can't do anything. Don't change the mode of
7671 the shift or propagate MODE into the shift, though. */
7672 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7673 && INTVAL (XEXP (x, 1)) >= 0)
7675 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7676 GET_MODE (x), GEN_INT (mask),
7678 if (temp && GET_CODE (temp) == CONST_INT)
7680 force_to_mode (XEXP (x, 0), GET_MODE (x),
7681 INTVAL (temp), next_select));
7686 /* If we just want the low-order bit, the NEG isn't needed since it
7687 won't change the low-order bit. */
7689 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7691 /* We need any bits less significant than the most significant bit in
7692 MASK since carries from those bits will affect the bits we are
7698 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7699 same as the XOR case above. Ensure that the constant we form is not
7700 wider than the mode of X. */
7702 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7703 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7704 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7705 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7706 < GET_MODE_BITSIZE (GET_MODE (x)))
7707 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7709 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7711 temp = simplify_gen_binary (XOR, GET_MODE (x),
7712 XEXP (XEXP (x, 0), 0), temp);
7713 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7714 temp, XEXP (XEXP (x, 0), 1));
7716 return force_to_mode (x, mode, mask, next_select);
7719 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7720 use the full mask inside the NOT. */
7724 op0 = gen_lowpart_or_truncate (op_mode,
7725 force_to_mode (XEXP (x, 0), mode, mask,
7727 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7728 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7732 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7733 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7734 which is equal to STORE_FLAG_VALUE. */
7735 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7736 && GET_MODE (XEXP (x, 0)) == mode
7737 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7738 && (nonzero_bits (XEXP (x, 0), mode)
7739 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7740 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7745 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7746 written in a narrower mode. We play it safe and do not do so. */
7749 gen_lowpart_or_truncate (GET_MODE (x),
7750 force_to_mode (XEXP (x, 1), mode,
7751 mask, next_select)));
7753 gen_lowpart_or_truncate (GET_MODE (x),
7754 force_to_mode (XEXP (x, 2), mode,
7755 mask, next_select)));
7762 /* Ensure we return a value of the proper mode. */
7763 return gen_lowpart_or_truncate (mode, x);
7766 /* Return nonzero if X is an expression that has one of two values depending on
7767 whether some other value is zero or nonzero. In that case, we return the
7768 value that is being tested, *PTRUE is set to the value if the rtx being
7769 returned has a nonzero value, and *PFALSE is set to the other alternative.
7771 If we return zero, we set *PTRUE and *PFALSE to X. */
7774 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7776 enum machine_mode mode = GET_MODE (x);
7777 enum rtx_code code = GET_CODE (x);
7778 rtx cond0, cond1, true0, true1, false0, false1;
7779 unsigned HOST_WIDE_INT nz;
7781 /* If we are comparing a value against zero, we are done. */
7782 if ((code == NE || code == EQ)
7783 && XEXP (x, 1) == const0_rtx)
7785 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7786 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7790 /* If this is a unary operation whose operand has one of two values, apply
7791 our opcode to compute those values. */
7792 else if (UNARY_P (x)
7793 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7795 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7796 *pfalse = simplify_gen_unary (code, mode, false0,
7797 GET_MODE (XEXP (x, 0)));
7801 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7802 make can't possibly match and would suppress other optimizations. */
7803 else if (code == COMPARE)
7806 /* If this is a binary operation, see if either side has only one of two
7807 values. If either one does or if both do and they are conditional on
7808 the same value, compute the new true and false values. */
7809 else if (BINARY_P (x))
7811 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7812 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7814 if ((cond0 != 0 || cond1 != 0)
7815 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7817 /* If if_then_else_cond returned zero, then true/false are the
7818 same rtl. We must copy one of them to prevent invalid rtl
7821 true0 = copy_rtx (true0);
7822 else if (cond1 == 0)
7823 true1 = copy_rtx (true1);
7825 if (COMPARISON_P (x))
7827 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7829 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7834 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7835 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7838 return cond0 ? cond0 : cond1;
7841 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7842 operands is zero when the other is nonzero, and vice-versa,
7843 and STORE_FLAG_VALUE is 1 or -1. */
7845 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7846 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7848 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7850 rtx op0 = XEXP (XEXP (x, 0), 1);
7851 rtx op1 = XEXP (XEXP (x, 1), 1);
7853 cond0 = XEXP (XEXP (x, 0), 0);
7854 cond1 = XEXP (XEXP (x, 1), 0);
7856 if (COMPARISON_P (cond0)
7857 && COMPARISON_P (cond1)
7858 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7859 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7860 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7861 || ((swap_condition (GET_CODE (cond0))
7862 == reversed_comparison_code (cond1, NULL))
7863 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7864 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7865 && ! side_effects_p (x))
7867 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7868 *pfalse = simplify_gen_binary (MULT, mode,
7870 ? simplify_gen_unary (NEG, mode,
7878 /* Similarly for MULT, AND and UMIN, except that for these the result
7880 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7881 && (code == MULT || code == AND || code == UMIN)
7882 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7884 cond0 = XEXP (XEXP (x, 0), 0);
7885 cond1 = XEXP (XEXP (x, 1), 0);
7887 if (COMPARISON_P (cond0)
7888 && COMPARISON_P (cond1)
7889 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7890 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7891 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7892 || ((swap_condition (GET_CODE (cond0))
7893 == reversed_comparison_code (cond1, NULL))
7894 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7895 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7896 && ! side_effects_p (x))
7898 *ptrue = *pfalse = const0_rtx;
7904 else if (code == IF_THEN_ELSE)
7906 /* If we have IF_THEN_ELSE already, extract the condition and
7907 canonicalize it if it is NE or EQ. */
7908 cond0 = XEXP (x, 0);
7909 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7910 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7911 return XEXP (cond0, 0);
7912 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7914 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7915 return XEXP (cond0, 0);
7921 /* If X is a SUBREG, we can narrow both the true and false values
7922 if the inner expression, if there is a condition. */
7923 else if (code == SUBREG
7924 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7927 true0 = simplify_gen_subreg (mode, true0,
7928 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7929 false0 = simplify_gen_subreg (mode, false0,
7930 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7931 if (true0 && false0)
7939 /* If X is a constant, this isn't special and will cause confusions
7940 if we treat it as such. Likewise if it is equivalent to a constant. */
7941 else if (CONSTANT_P (x)
7942 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7945 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7946 will be least confusing to the rest of the compiler. */
7947 else if (mode == BImode)
7949 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7953 /* If X is known to be either 0 or -1, those are the true and
7954 false values when testing X. */
7955 else if (x == constm1_rtx || x == const0_rtx
7956 || (mode != VOIDmode
7957 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7959 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7963 /* Likewise for 0 or a single bit. */
7964 else if (SCALAR_INT_MODE_P (mode)
7965 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7966 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7968 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7972 /* Otherwise fail; show no condition with true and false values the same. */
7973 *ptrue = *pfalse = x;
7977 /* Return the value of expression X given the fact that condition COND
7978 is known to be true when applied to REG as its first operand and VAL
7979 as its second. X is known to not be shared and so can be modified in
7982 We only handle the simplest cases, and specifically those cases that
7983 arise with IF_THEN_ELSE expressions. */
7986 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7988 enum rtx_code code = GET_CODE (x);
7993 if (side_effects_p (x))
7996 /* If either operand of the condition is a floating point value,
7997 then we have to avoid collapsing an EQ comparison. */
7999 && rtx_equal_p (x, reg)
8000 && ! FLOAT_MODE_P (GET_MODE (x))
8001 && ! FLOAT_MODE_P (GET_MODE (val)))
8004 if (cond == UNEQ && rtx_equal_p (x, reg))
8007 /* If X is (abs REG) and we know something about REG's relationship
8008 with zero, we may be able to simplify this. */
8010 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8013 case GE: case GT: case EQ:
8016 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8018 GET_MODE (XEXP (x, 0)));
8023 /* The only other cases we handle are MIN, MAX, and comparisons if the
8024 operands are the same as REG and VAL. */
8026 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8028 if (rtx_equal_p (XEXP (x, 0), val))
8029 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8031 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8033 if (COMPARISON_P (x))
8035 if (comparison_dominates_p (cond, code))
8036 return const_true_rtx;
8038 code = reversed_comparison_code (x, NULL);
8040 && comparison_dominates_p (cond, code))
8045 else if (code == SMAX || code == SMIN
8046 || code == UMIN || code == UMAX)
8048 int unsignedp = (code == UMIN || code == UMAX);
8050 /* Do not reverse the condition when it is NE or EQ.
8051 This is because we cannot conclude anything about
8052 the value of 'SMAX (x, y)' when x is not equal to y,
8053 but we can when x equals y. */
8054 if ((code == SMAX || code == UMAX)
8055 && ! (cond == EQ || cond == NE))
8056 cond = reverse_condition (cond);
8061 return unsignedp ? x : XEXP (x, 1);
8063 return unsignedp ? x : XEXP (x, 0);
8065 return unsignedp ? XEXP (x, 1) : x;
8067 return unsignedp ? XEXP (x, 0) : x;
8074 else if (code == SUBREG)
8076 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8077 rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8079 if (SUBREG_REG (x) != r)
8081 /* We must simplify subreg here, before we lose track of the
8082 original inner_mode. */
8083 new_rtx = simplify_subreg (GET_MODE (x), r,
8084 inner_mode, SUBREG_BYTE (x));
8088 SUBST (SUBREG_REG (x), r);
8093 /* We don't have to handle SIGN_EXTEND here, because even in the
8094 case of replacing something with a modeless CONST_INT, a
8095 CONST_INT is already (supposed to be) a valid sign extension for
8096 its narrower mode, which implies it's already properly
8097 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
8098 story is different. */
8099 else if (code == ZERO_EXTEND)
8101 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8102 rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8104 if (XEXP (x, 0) != r)
8106 /* We must simplify the zero_extend here, before we lose
8107 track of the original inner_mode. */
8108 new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8113 SUBST (XEXP (x, 0), r);
8119 fmt = GET_RTX_FORMAT (code);
8120 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8123 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8124 else if (fmt[i] == 'E')
8125 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8126 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8133 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8134 assignment as a field assignment. */
8137 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8139 if (x == y || rtx_equal_p (x, y))
8142 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8145 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8146 Note that all SUBREGs of MEM are paradoxical; otherwise they
8147 would have been rewritten. */
8148 if (MEM_P (x) && GET_CODE (y) == SUBREG
8149 && MEM_P (SUBREG_REG (y))
8150 && rtx_equal_p (SUBREG_REG (y),
8151 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8154 if (MEM_P (y) && GET_CODE (x) == SUBREG
8155 && MEM_P (SUBREG_REG (x))
8156 && rtx_equal_p (SUBREG_REG (x),
8157 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8160 /* We used to see if get_last_value of X and Y were the same but that's
8161 not correct. In one direction, we'll cause the assignment to have
8162 the wrong destination and in the case, we'll import a register into this
8163 insn that might have already have been dead. So fail if none of the
8164 above cases are true. */
8168 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
8169 Return that assignment if so.
8171 We only handle the most common cases. */
8174 make_field_assignment (rtx x)
8176 rtx dest = SET_DEST (x);
8177 rtx src = SET_SRC (x);
8182 unsigned HOST_WIDE_INT len;
8184 enum machine_mode mode;
8186 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
8187 a clear of a one-bit field. We will have changed it to
8188 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
8191 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
8192 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
8193 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
8194 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8196 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8199 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8203 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
8204 && subreg_lowpart_p (XEXP (src, 0))
8205 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
8206 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
8207 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
8208 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
8209 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
8210 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8212 assign = make_extraction (VOIDmode, dest, 0,
8213 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
8216 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
8220 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
8222 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
8223 && XEXP (XEXP (src, 0), 0) == const1_rtx
8224 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
8226 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
8229 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
8233 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
8234 SRC is an AND with all bits of that field set, then we can discard
8236 if (GET_CODE (dest) == ZERO_EXTRACT
8237 && GET_CODE (XEXP (dest, 1)) == CONST_INT
8238 && GET_CODE (src) == AND
8239 && GET_CODE (XEXP (src, 1)) == CONST_INT)
8241 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
8242 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
8243 unsigned HOST_WIDE_INT ze_mask;
8245 if (width >= HOST_BITS_PER_WIDE_INT)
8248 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
8250 /* Complete overlap. We can remove the source AND. */
8251 if ((and_mask & ze_mask) == ze_mask)
8252 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
8254 /* Partial overlap. We can reduce the source AND. */
8255 if ((and_mask & ze_mask) != and_mask)
8257 mode = GET_MODE (src);
8258 src = gen_rtx_AND (mode, XEXP (src, 0),
8259 gen_int_mode (and_mask & ze_mask, mode));
8260 return gen_rtx_SET (VOIDmode, dest, src);
8264 /* The other case we handle is assignments into a constant-position
8265 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
8266 a mask that has all one bits except for a group of zero bits and
8267 OTHER is known to have zeros where C1 has ones, this is such an
8268 assignment. Compute the position and length from C1. Shift OTHER
8269 to the appropriate position, force it to the required mode, and
8270 make the extraction. Check for the AND in both operands. */
8272 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
8275 rhs = expand_compound_operation (XEXP (src, 0));
8276 lhs = expand_compound_operation (XEXP (src, 1));
8278 if (GET_CODE (rhs) == AND
8279 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
8280 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
8281 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
8282 else if (GET_CODE (lhs) == AND
8283 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
8284 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
8285 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
8289 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
8290 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
8291 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
8292 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
8295 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
8299 /* The mode to use for the source is the mode of the assignment, or of
8300 what is inside a possible STRICT_LOW_PART. */
8301 mode = (GET_CODE (assign) == STRICT_LOW_PART
8302 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
8304 /* Shift OTHER right POS places and make it the source, restricting it
8305 to the proper length and mode. */
8307 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
8311 src = force_to_mode (src, mode,
8312 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
8313 ? ~(unsigned HOST_WIDE_INT) 0
8314 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
8317 /* If SRC is masked by an AND that does not make a difference in
8318 the value being stored, strip it. */
8319 if (GET_CODE (assign) == ZERO_EXTRACT
8320 && GET_CODE (XEXP (assign, 1)) == CONST_INT
8321 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
8322 && GET_CODE (src) == AND
8323 && GET_CODE (XEXP (src, 1)) == CONST_INT
8324 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
8325 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
8326 src = XEXP (src, 0);
8328 return gen_rtx_SET (VOIDmode, assign, src);
8331 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
8335 apply_distributive_law (rtx x)
8337 enum rtx_code code = GET_CODE (x);
8338 enum rtx_code inner_code;
8339 rtx lhs, rhs, other;
8342 /* Distributivity is not true for floating point as it can change the
8343 value. So we don't do it unless -funsafe-math-optimizations. */
8344 if (FLOAT_MODE_P (GET_MODE (x))
8345 && ! flag_unsafe_math_optimizations)
8348 /* The outer operation can only be one of the following: */
8349 if (code != IOR && code != AND && code != XOR
8350 && code != PLUS && code != MINUS)
8356 /* If either operand is a primitive we can't do anything, so get out
8358 if (OBJECT_P (lhs) || OBJECT_P (rhs))
8361 lhs = expand_compound_operation (lhs);
8362 rhs = expand_compound_operation (rhs);
8363 inner_code = GET_CODE (lhs);
8364 if (inner_code != GET_CODE (rhs))
8367 /* See if the inner and outer operations distribute. */
8374 /* These all distribute except over PLUS. */
8375 if (code == PLUS || code == MINUS)
8380 if (code != PLUS && code != MINUS)
8385 /* This is also a multiply, so it distributes over everything. */
8389 /* Non-paradoxical SUBREGs distributes over all operations,
8390 provided the inner modes and byte offsets are the same, this
8391 is an extraction of a low-order part, we don't convert an fp
8392 operation to int or vice versa, this is not a vector mode,
8393 and we would not be converting a single-word operation into a
8394 multi-word operation. The latter test is not required, but
8395 it prevents generating unneeded multi-word operations. Some
8396 of the previous tests are redundant given the latter test,
8397 but are retained because they are required for correctness.
8399 We produce the result slightly differently in this case. */
8401 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
8402 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
8403 || ! subreg_lowpart_p (lhs)
8404 || (GET_MODE_CLASS (GET_MODE (lhs))
8405 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
8406 || (GET_MODE_SIZE (GET_MODE (lhs))
8407 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
8408 || VECTOR_MODE_P (GET_MODE (lhs))
8409 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
8410 /* Result might need to be truncated. Don't change mode if
8411 explicit truncation is needed. */
8412 || !TRULY_NOOP_TRUNCATION
8413 (GET_MODE_BITSIZE (GET_MODE (x)),
8414 GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (lhs)))))
8417 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
8418 SUBREG_REG (lhs), SUBREG_REG (rhs));
8419 return gen_lowpart (GET_MODE (x), tem);
8425 /* Set LHS and RHS to the inner operands (A and B in the example
8426 above) and set OTHER to the common operand (C in the example).
8427 There is only one way to do this unless the inner operation is
8429 if (COMMUTATIVE_ARITH_P (lhs)
8430 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
8431 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
8432 else if (COMMUTATIVE_ARITH_P (lhs)
8433 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
8434 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
8435 else if (COMMUTATIVE_ARITH_P (lhs)
8436 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
8437 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
8438 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
8439 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
8443 /* Form the new inner operation, seeing if it simplifies first. */
8444 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
8446 /* There is one exception to the general way of distributing:
8447 (a | c) ^ (b | c) -> (a ^ b) & ~c */
8448 if (code == XOR && inner_code == IOR)
8451 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8454 /* We may be able to continuing distributing the result, so call
8455 ourselves recursively on the inner operation before forming the
8456 outer operation, which we return. */
8457 return simplify_gen_binary (inner_code, GET_MODE (x),
8458 apply_distributive_law (tem), other);
8461 /* See if X is of the form (* (+ A B) C), and if so convert to
8462 (+ (* A C) (* B C)) and try to simplify.
8464 Most of the time, this results in no change. However, if some of
8465 the operands are the same or inverses of each other, simplifications
8468 For example, (and (ior A B) (not B)) can occur as the result of
8469 expanding a bit field assignment. When we apply the distributive
8470 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
8471 which then simplifies to (and (A (not B))).
8473 Note that no checks happen on the validity of applying the inverse
8474 distributive law. This is pointless since we can do it in the
8475 few places where this routine is called.
8477 N is the index of the term that is decomposed (the arithmetic operation,
8478 i.e. (+ A B) in the first example above). !N is the index of the term that
8479 is distributed, i.e. of C in the first example above. */
8481 distribute_and_simplify_rtx (rtx x, int n)
8483 enum machine_mode mode;
8484 enum rtx_code outer_code, inner_code;
8485 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
8487 decomposed = XEXP (x, n);
8488 if (!ARITHMETIC_P (decomposed))
8491 mode = GET_MODE (x);
8492 outer_code = GET_CODE (x);
8493 distributed = XEXP (x, !n);
8495 inner_code = GET_CODE (decomposed);
8496 inner_op0 = XEXP (decomposed, 0);
8497 inner_op1 = XEXP (decomposed, 1);
8499 /* Special case (and (xor B C) (not A)), which is equivalent to
8500 (xor (ior A B) (ior A C)) */
8501 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
8503 distributed = XEXP (distributed, 0);
8509 /* Distribute the second term. */
8510 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
8511 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
8515 /* Distribute the first term. */
8516 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
8517 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
8520 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
8522 if (GET_CODE (tmp) != outer_code
8523 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
8529 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
8530 in MODE. Return an equivalent form, if different from (and VAROP
8531 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
8534 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
8535 unsigned HOST_WIDE_INT constop)
8537 unsigned HOST_WIDE_INT nonzero;
8538 unsigned HOST_WIDE_INT orig_constop;
8543 orig_constop = constop;
8544 if (GET_CODE (varop) == CLOBBER)
8547 /* Simplify VAROP knowing that we will be only looking at some of the
8550 Note by passing in CONSTOP, we guarantee that the bits not set in
8551 CONSTOP are not significant and will never be examined. We must
8552 ensure that is the case by explicitly masking out those bits
8553 before returning. */
8554 varop = force_to_mode (varop, mode, constop, 0);
8556 /* If VAROP is a CLOBBER, we will fail so return it. */
8557 if (GET_CODE (varop) == CLOBBER)
8560 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8561 to VAROP and return the new constant. */
8562 if (GET_CODE (varop) == CONST_INT)
8563 return gen_int_mode (INTVAL (varop) & constop, mode);
8565 /* See what bits may be nonzero in VAROP. Unlike the general case of
8566 a call to nonzero_bits, here we don't care about bits outside
8569 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8571 /* Turn off all bits in the constant that are known to already be zero.
8572 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8573 which is tested below. */
8577 /* If we don't have any bits left, return zero. */
8581 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8582 a power of two, we can replace this with an ASHIFT. */
8583 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8584 && (i = exact_log2 (constop)) >= 0)
8585 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8587 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8588 or XOR, then try to apply the distributive law. This may eliminate
8589 operations if either branch can be simplified because of the AND.
8590 It may also make some cases more complex, but those cases probably
8591 won't match a pattern either with or without this. */
8593 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8597 apply_distributive_law
8598 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
8599 simplify_and_const_int (NULL_RTX,
8603 simplify_and_const_int (NULL_RTX,
8608 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
8609 the AND and see if one of the operands simplifies to zero. If so, we
8610 may eliminate it. */
8612 if (GET_CODE (varop) == PLUS
8613 && exact_log2 (constop + 1) >= 0)
8617 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8618 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8619 if (o0 == const0_rtx)
8621 if (o1 == const0_rtx)
8625 /* Make a SUBREG if necessary. If we can't make it, fail. */
8626 varop = gen_lowpart (mode, varop);
8627 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
8630 /* If we are only masking insignificant bits, return VAROP. */
8631 if (constop == nonzero)
8634 if (varop == orig_varop && constop == orig_constop)
8637 /* Otherwise, return an AND. */
8638 return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
8642 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8645 Return an equivalent form, if different from X. Otherwise, return X. If
8646 X is zero, we are to always construct the equivalent form. */
8649 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8650 unsigned HOST_WIDE_INT constop)
8652 rtx tem = simplify_and_const_int_1 (mode, varop, constop);
8657 x = simplify_gen_binary (AND, GET_MODE (varop), varop,
8658 gen_int_mode (constop, mode));
8659 if (GET_MODE (x) != mode)
8660 x = gen_lowpart (mode, x);
8664 /* Given a REG, X, compute which bits in X can be nonzero.
8665 We don't care about bits outside of those defined in MODE.
8667 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8668 a shift, AND, or zero_extract, we can do better. */
8671 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
8672 const_rtx known_x ATTRIBUTE_UNUSED,
8673 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8674 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8675 unsigned HOST_WIDE_INT *nonzero)
8680 /* If X is a register whose nonzero bits value is current, use it.
8681 Otherwise, if X is a register whose value we can find, use that
8682 value. Otherwise, use the previously-computed global nonzero bits
8683 for this register. */
8685 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8686 if (rsp->last_set_value != 0
8687 && (rsp->last_set_mode == mode
8688 || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
8689 && GET_MODE_CLASS (mode) == MODE_INT))
8690 && ((rsp->last_set_label >= label_tick_ebb_start
8691 && rsp->last_set_label < label_tick)
8692 || (rsp->last_set_label == label_tick
8693 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8694 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8695 && REG_N_SETS (REGNO (x)) == 1
8697 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8699 *nonzero &= rsp->last_set_nonzero_bits;
8703 tem = get_last_value (x);
8707 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8708 /* If X is narrower than MODE and TEM is a non-negative
8709 constant that would appear negative in the mode of X,
8710 sign-extend it for use in reg_nonzero_bits because some
8711 machines (maybe most) will actually do the sign-extension
8712 and this is the conservative approach.
8714 ??? For 2.5, try to tighten up the MD files in this regard
8715 instead of this kludge. */
8717 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8718 && GET_CODE (tem) == CONST_INT
8720 && 0 != (INTVAL (tem)
8721 & ((HOST_WIDE_INT) 1
8722 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8723 tem = GEN_INT (INTVAL (tem)
8724 | ((HOST_WIDE_INT) (-1)
8725 << GET_MODE_BITSIZE (GET_MODE (x))));
8729 else if (nonzero_sign_valid && rsp->nonzero_bits)
8731 unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
8733 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8734 /* We don't know anything about the upper bits. */
8735 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8742 /* Return the number of bits at the high-order end of X that are known to
8743 be equal to the sign bit. X will be used in mode MODE; if MODE is
8744 VOIDmode, X will be used in its own mode. The returned value will always
8745 be between 1 and the number of bits in MODE. */
8748 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
8749 const_rtx known_x ATTRIBUTE_UNUSED,
8750 enum machine_mode known_mode
8752 unsigned int known_ret ATTRIBUTE_UNUSED,
8753 unsigned int *result)
8758 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
8759 if (rsp->last_set_value != 0
8760 && rsp->last_set_mode == mode
8761 && ((rsp->last_set_label >= label_tick_ebb_start
8762 && rsp->last_set_label < label_tick)
8763 || (rsp->last_set_label == label_tick
8764 && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
8765 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8766 && REG_N_SETS (REGNO (x)) == 1
8768 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
8770 *result = rsp->last_set_sign_bit_copies;
8774 tem = get_last_value (x);
8778 if (nonzero_sign_valid && rsp->sign_bit_copies != 0
8779 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8780 *result = rsp->sign_bit_copies;
8785 /* Return the number of "extended" bits there are in X, when interpreted
8786 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8787 unsigned quantities, this is the number of high-order zero bits.
8788 For signed quantities, this is the number of copies of the sign bit
8789 minus 1. In both case, this function returns the number of "spare"
8790 bits. For example, if two quantities for which this function returns
8791 at least 1 are added, the addition is known not to overflow.
8793 This function will always return 0 unless called during combine, which
8794 implies that it must be called from a define_split. */
8797 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
8799 if (nonzero_sign_valid == 0)
8803 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8804 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8805 - floor_log2 (nonzero_bits (x, mode)))
8807 : num_sign_bit_copies (x, mode) - 1);
8810 /* This function is called from `simplify_shift_const' to merge two
8811 outer operations. Specifically, we have already found that we need
8812 to perform operation *POP0 with constant *PCONST0 at the outermost
8813 position. We would now like to also perform OP1 with constant CONST1
8814 (with *POP0 being done last).
8816 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8817 the resulting operation. *PCOMP_P is set to 1 if we would need to
8818 complement the innermost operand, otherwise it is unchanged.
8820 MODE is the mode in which the operation will be done. No bits outside
8821 the width of this mode matter. It is assumed that the width of this mode
8822 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8824 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8825 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8826 result is simply *PCONST0.
8828 If the resulting operation cannot be expressed as one operation, we
8829 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8832 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8834 enum rtx_code op0 = *pop0;
8835 HOST_WIDE_INT const0 = *pconst0;
8837 const0 &= GET_MODE_MASK (mode);
8838 const1 &= GET_MODE_MASK (mode);
8840 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8844 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8847 if (op1 == UNKNOWN || op0 == SET)
8850 else if (op0 == UNKNOWN)
8851 op0 = op1, const0 = const1;
8853 else if (op0 == op1)
8877 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8878 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8881 /* If the two constants aren't the same, we can't do anything. The
8882 remaining six cases can all be done. */
8883 else if (const0 != const1)
8891 /* (a & b) | b == b */
8893 else /* op1 == XOR */
8894 /* (a ^ b) | b == a | b */
8900 /* (a & b) ^ b == (~a) & b */
8901 op0 = AND, *pcomp_p = 1;
8902 else /* op1 == IOR */
8903 /* (a | b) ^ b == a & ~b */
8904 op0 = AND, const0 = ~const0;
8909 /* (a | b) & b == b */
8911 else /* op1 == XOR */
8912 /* (a ^ b) & b) == (~a) & b */
8919 /* Check for NO-OP cases. */
8920 const0 &= GET_MODE_MASK (mode);
8922 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8924 else if (const0 == 0 && op0 == AND)
8926 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8930 /* ??? Slightly redundant with the above mask, but not entirely.
8931 Moving this above means we'd have to sign-extend the mode mask
8932 for the final test. */
8933 const0 = trunc_int_for_mode (const0, mode);
8941 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8942 The result of the shift is RESULT_MODE. Return NULL_RTX if we cannot
8943 simplify it. Otherwise, return a simplified value.
8945 The shift is normally computed in the widest mode we find in VAROP, as
8946 long as it isn't a different number of words than RESULT_MODE. Exceptions
8947 are ASHIFTRT and ROTATE, which are always done in their original mode. */
8950 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
8951 rtx varop, int orig_count)
8953 enum rtx_code orig_code = code;
8954 rtx orig_varop = varop;
8956 enum machine_mode mode = result_mode;
8957 enum machine_mode shift_mode, tmode;
8958 unsigned int mode_words
8959 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8960 /* We form (outer_op (code varop count) (outer_const)). */
8961 enum rtx_code outer_op = UNKNOWN;
8962 HOST_WIDE_INT outer_const = 0;
8963 int complement_p = 0;
8966 /* Make sure and truncate the "natural" shift on the way in. We don't
8967 want to do this inside the loop as it makes it more difficult to
8969 if (SHIFT_COUNT_TRUNCATED)
8970 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8972 /* If we were given an invalid count, don't do anything except exactly
8973 what was requested. */
8975 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8980 /* Unless one of the branches of the `if' in this loop does a `continue',
8981 we will `break' the loop after the `if'. */
8985 /* If we have an operand of (clobber (const_int 0)), fail. */
8986 if (GET_CODE (varop) == CLOBBER)
8989 /* If we discovered we had to complement VAROP, leave. Making a NOT
8990 here would cause an infinite loop. */
8994 /* Convert ROTATERT to ROTATE. */
8995 if (code == ROTATERT)
8997 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8999 if (VECTOR_MODE_P (result_mode))
9000 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9002 count = bitsize - count;
9005 /* We need to determine what mode we will do the shift in. If the
9006 shift is a right shift or a ROTATE, we must always do it in the mode
9007 it was originally done in. Otherwise, we can do it in MODE, the
9008 widest mode encountered. */
9010 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9011 ? result_mode : mode);
9013 /* Handle cases where the count is greater than the size of the mode
9014 minus 1. For ASHIFT, use the size minus one as the count (this can
9015 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
9016 take the count modulo the size. For other shifts, the result is
9019 Since these shifts are being produced by the compiler by combining
9020 multiple operations, each of which are defined, we know what the
9021 result is supposed to be. */
9023 if (count > (GET_MODE_BITSIZE (shift_mode) - 1))
9025 if (code == ASHIFTRT)
9026 count = GET_MODE_BITSIZE (shift_mode) - 1;
9027 else if (code == ROTATE || code == ROTATERT)
9028 count %= GET_MODE_BITSIZE (shift_mode);
9031 /* We can't simply return zero because there may be an
9039 /* An arithmetic right shift of a quantity known to be -1 or 0
9041 if (code == ASHIFTRT
9042 && (num_sign_bit_copies (varop, shift_mode)
9043 == GET_MODE_BITSIZE (shift_mode)))
9049 /* If we are doing an arithmetic right shift and discarding all but
9050 the sign bit copies, this is equivalent to doing a shift by the
9051 bitsize minus one. Convert it into that shift because it will often
9052 allow other simplifications. */
9054 if (code == ASHIFTRT
9055 && (count + num_sign_bit_copies (varop, shift_mode)
9056 >= GET_MODE_BITSIZE (shift_mode)))
9057 count = GET_MODE_BITSIZE (shift_mode) - 1;
9059 /* We simplify the tests below and elsewhere by converting
9060 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9061 `make_compound_operation' will convert it to an ASHIFTRT for
9062 those machines (such as VAX) that don't have an LSHIFTRT. */
9063 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9065 && ((nonzero_bits (varop, shift_mode)
9066 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
9070 if (((code == LSHIFTRT
9071 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9072 && !(nonzero_bits (varop, shift_mode) >> count))
9074 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
9075 && !((nonzero_bits (varop, shift_mode) << count)
9076 & GET_MODE_MASK (shift_mode))))
9077 && !side_effects_p (varop))
9080 switch (GET_CODE (varop))
9086 new_rtx = expand_compound_operation (varop);
9087 if (new_rtx != varop)
9095 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9096 minus the width of a smaller mode, we can do this with a
9097 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
9098 if ((code == ASHIFTRT || code == LSHIFTRT)
9099 && ! mode_dependent_address_p (XEXP (varop, 0))
9100 && ! MEM_VOLATILE_P (varop)
9101 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9102 MODE_INT, 1)) != BLKmode)
9104 new_rtx = adjust_address_nv (varop, tmode,
9105 BYTES_BIG_ENDIAN ? 0
9106 : count / BITS_PER_UNIT);
9108 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9109 : ZERO_EXTEND, mode, new_rtx);
9116 /* If VAROP is a SUBREG, strip it as long as the inner operand has
9117 the same number of words as what we've seen so far. Then store
9118 the widest mode in MODE. */
9119 if (subreg_lowpart_p (varop)
9120 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9121 > GET_MODE_SIZE (GET_MODE (varop)))
9122 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
9123 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
9126 varop = SUBREG_REG (varop);
9127 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
9128 mode = GET_MODE (varop);
9134 /* Some machines use MULT instead of ASHIFT because MULT
9135 is cheaper. But it is still better on those machines to
9136 merge two shifts into one. */
9137 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9138 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9141 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
9143 GEN_INT (exact_log2 (
9144 INTVAL (XEXP (varop, 1)))));
9150 /* Similar, for when divides are cheaper. */
9151 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9152 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
9155 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
9157 GEN_INT (exact_log2 (
9158 INTVAL (XEXP (varop, 1)))));
9164 /* If we are extracting just the sign bit of an arithmetic
9165 right shift, that shift is not needed. However, the sign
9166 bit of a wider mode may be different from what would be
9167 interpreted as the sign bit in a narrower mode, so, if
9168 the result is narrower, don't discard the shift. */
9169 if (code == LSHIFTRT
9170 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9171 && (GET_MODE_BITSIZE (result_mode)
9172 >= GET_MODE_BITSIZE (GET_MODE (varop))))
9174 varop = XEXP (varop, 0);
9178 /* ... fall through ... */
9183 /* Here we have two nested shifts. The result is usually the
9184 AND of a new shift with a mask. We compute the result below. */
9185 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9186 && INTVAL (XEXP (varop, 1)) >= 0
9187 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
9188 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9189 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9190 && !VECTOR_MODE_P (result_mode))
9192 enum rtx_code first_code = GET_CODE (varop);
9193 unsigned int first_count = INTVAL (XEXP (varop, 1));
9194 unsigned HOST_WIDE_INT mask;
9197 /* We have one common special case. We can't do any merging if
9198 the inner code is an ASHIFTRT of a smaller mode. However, if
9199 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
9200 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
9201 we can convert it to
9202 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
9203 This simplifies certain SIGN_EXTEND operations. */
9204 if (code == ASHIFT && first_code == ASHIFTRT
9205 && count == (GET_MODE_BITSIZE (result_mode)
9206 - GET_MODE_BITSIZE (GET_MODE (varop))))
9208 /* C3 has the low-order C1 bits zero. */
9210 mask = (GET_MODE_MASK (mode)
9211 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
9213 varop = simplify_and_const_int (NULL_RTX, result_mode,
9214 XEXP (varop, 0), mask);
9215 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
9217 count = first_count;
9222 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9223 than C1 high-order bits equal to the sign bit, we can convert
9224 this to either an ASHIFT or an ASHIFTRT depending on the
9227 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9229 if (code == ASHIFTRT && first_code == ASHIFT
9230 && GET_MODE (varop) == shift_mode
9231 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
9234 varop = XEXP (varop, 0);
9235 count -= first_count;
9245 /* There are some cases we can't do. If CODE is ASHIFTRT,
9246 we can only do this if FIRST_CODE is also ASHIFTRT.
9248 We can't do the case when CODE is ROTATE and FIRST_CODE is
9251 If the mode of this shift is not the mode of the outer shift,
9252 we can't do this if either shift is a right shift or ROTATE.
9254 Finally, we can't do any of these if the mode is too wide
9255 unless the codes are the same.
9257 Handle the case where the shift codes are the same
9260 if (code == first_code)
9262 if (GET_MODE (varop) != result_mode
9263 && (code == ASHIFTRT || code == LSHIFTRT
9267 count += first_count;
9268 varop = XEXP (varop, 0);
9272 if (code == ASHIFTRT
9273 || (code == ROTATE && first_code == ASHIFTRT)
9274 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
9275 || (GET_MODE (varop) != result_mode
9276 && (first_code == ASHIFTRT || first_code == LSHIFTRT
9277 || first_code == ROTATE
9278 || code == ROTATE)))
9281 /* To compute the mask to apply after the shift, shift the
9282 nonzero bits of the inner shift the same way the
9283 outer shift will. */
9285 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
9288 = simplify_const_binary_operation (code, result_mode, mask_rtx,
9291 /* Give up if we can't compute an outer operation to use. */
9293 || GET_CODE (mask_rtx) != CONST_INT
9294 || ! merge_outer_ops (&outer_op, &outer_const, AND,
9296 result_mode, &complement_p))
9299 /* If the shifts are in the same direction, we add the
9300 counts. Otherwise, we subtract them. */
9301 if ((code == ASHIFTRT || code == LSHIFTRT)
9302 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
9303 count += first_count;
9305 count -= first_count;
9307 /* If COUNT is positive, the new shift is usually CODE,
9308 except for the two exceptions below, in which case it is
9309 FIRST_CODE. If the count is negative, FIRST_CODE should
9312 && ((first_code == ROTATE && code == ASHIFT)
9313 || (first_code == ASHIFTRT && code == LSHIFTRT)))
9316 code = first_code, count = -count;
9318 varop = XEXP (varop, 0);
9322 /* If we have (A << B << C) for any shift, we can convert this to
9323 (A << C << B). This wins if A is a constant. Only try this if
9324 B is not a constant. */
9326 else if (GET_CODE (varop) == code
9327 && GET_CODE (XEXP (varop, 0)) == CONST_INT
9328 && GET_CODE (XEXP (varop, 1)) != CONST_INT)
9330 rtx new_rtx = simplify_const_binary_operation (code, mode,
9333 varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
9340 if (VECTOR_MODE_P (mode))
9343 /* Make this fit the case below. */
9344 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
9345 GEN_INT (GET_MODE_MASK (mode)));
9351 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9352 with C the size of VAROP - 1 and the shift is logical if
9353 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9354 we have an (le X 0) operation. If we have an arithmetic shift
9355 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9356 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9358 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
9359 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
9360 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9361 && (code == LSHIFTRT || code == ASHIFTRT)
9362 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9363 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9366 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
9369 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9370 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9375 /* If we have (shift (logical)), move the logical to the outside
9376 to allow it to possibly combine with another logical and the
9377 shift to combine with another shift. This also canonicalizes to
9378 what a ZERO_EXTRACT looks like. Also, some machines have
9379 (and (shift)) insns. */
9381 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9382 /* We can't do this if we have (ashiftrt (xor)) and the
9383 constant has its sign bit set in shift_mode. */
9384 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9385 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9387 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9389 GEN_INT (count))) != 0
9390 && GET_CODE (new_rtx) == CONST_INT
9391 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
9392 INTVAL (new_rtx), result_mode, &complement_p))
9394 varop = XEXP (varop, 0);
9398 /* If we can't do that, try to simplify the shift in each arm of the
9399 logical expression, make a new logical expression, and apply
9400 the inverse distributive law. This also can't be done
9401 for some (ashiftrt (xor)). */
9402 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
9403 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
9404 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
9407 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9408 XEXP (varop, 0), count);
9409 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
9410 XEXP (varop, 1), count);
9412 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
9414 varop = apply_distributive_law (varop);
9422 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9423 says that the sign bit can be tested, FOO has mode MODE, C is
9424 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9425 that may be nonzero. */
9426 if (code == LSHIFTRT
9427 && XEXP (varop, 1) == const0_rtx
9428 && GET_MODE (XEXP (varop, 0)) == result_mode
9429 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9430 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9431 && STORE_FLAG_VALUE == -1
9432 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9433 && merge_outer_ops (&outer_op, &outer_const, XOR,
9434 (HOST_WIDE_INT) 1, result_mode,
9437 varop = XEXP (varop, 0);
9444 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9445 than the number of bits in the mode is equivalent to A. */
9446 if (code == LSHIFTRT
9447 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9448 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
9450 varop = XEXP (varop, 0);
9455 /* NEG commutes with ASHIFT since it is multiplication. Move the
9456 NEG outside to allow shifts to combine. */
9458 && merge_outer_ops (&outer_op, &outer_const, NEG,
9459 (HOST_WIDE_INT) 0, result_mode,
9462 varop = XEXP (varop, 0);
9468 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9469 is one less than the number of bits in the mode is
9470 equivalent to (xor A 1). */
9471 if (code == LSHIFTRT
9472 && count == (GET_MODE_BITSIZE (result_mode) - 1)
9473 && XEXP (varop, 1) == constm1_rtx
9474 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
9475 && merge_outer_ops (&outer_op, &outer_const, XOR,
9476 (HOST_WIDE_INT) 1, result_mode,
9480 varop = XEXP (varop, 0);
9484 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9485 that might be nonzero in BAR are those being shifted out and those
9486 bits are known zero in FOO, we can replace the PLUS with FOO.
9487 Similarly in the other operand order. This code occurs when
9488 we are computing the size of a variable-size array. */
9490 if ((code == ASHIFTRT || code == LSHIFTRT)
9491 && count < HOST_BITS_PER_WIDE_INT
9492 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
9493 && (nonzero_bits (XEXP (varop, 1), result_mode)
9494 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
9496 varop = XEXP (varop, 0);
9499 else if ((code == ASHIFTRT || code == LSHIFTRT)
9500 && count < HOST_BITS_PER_WIDE_INT
9501 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
9502 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9504 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9505 & nonzero_bits (XEXP (varop, 1),
9508 varop = XEXP (varop, 1);
9512 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9514 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9515 && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
9517 GEN_INT (count))) != 0
9518 && GET_CODE (new_rtx) == CONST_INT
9519 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9520 INTVAL (new_rtx), result_mode, &complement_p))
9522 varop = XEXP (varop, 0);
9526 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
9527 signbit', and attempt to change the PLUS to an XOR and move it to
9528 the outer operation as is done above in the AND/IOR/XOR case
9529 leg for shift(logical). See details in logical handling above
9530 for reasoning in doing so. */
9531 if (code == LSHIFTRT
9532 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9533 && mode_signbit_p (result_mode, XEXP (varop, 1))
9534 && (new_rtx = simplify_const_binary_operation (code, result_mode,
9536 GEN_INT (count))) != 0
9537 && GET_CODE (new_rtx) == CONST_INT
9538 && merge_outer_ops (&outer_op, &outer_const, XOR,
9539 INTVAL (new_rtx), result_mode, &complement_p))
9541 varop = XEXP (varop, 0);
9548 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9549 with C the size of VAROP - 1 and the shift is logical if
9550 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9551 we have a (gt X 0) operation. If the shift is arithmetic with
9552 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9553 we have a (neg (gt X 0)) operation. */
9555 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9556 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9557 && count == (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9558 && (code == LSHIFTRT || code == ASHIFTRT)
9559 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9560 && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
9561 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9564 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9567 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9568 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9575 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9576 if the truncate does not affect the value. */
9577 if (code == LSHIFTRT
9578 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9579 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9580 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9581 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9582 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9584 rtx varop_inner = XEXP (varop, 0);
9587 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9588 XEXP (varop_inner, 0),
9590 (count + INTVAL (XEXP (varop_inner, 1))));
9591 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9604 /* We need to determine what mode to do the shift in. If the shift is
9605 a right shift or ROTATE, we must always do it in the mode it was
9606 originally done in. Otherwise, we can do it in MODE, the widest mode
9607 encountered. The code we care about is that of the shift that will
9608 actually be done, not the shift that was originally requested. */
9610 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9611 ? result_mode : mode);
9613 /* We have now finished analyzing the shift. The result should be
9614 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9615 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9616 to the result of the shift. OUTER_CONST is the relevant constant,
9617 but we must turn off all bits turned off in the shift. */
9619 if (outer_op == UNKNOWN
9620 && orig_code == code && orig_count == count
9621 && varop == orig_varop
9622 && shift_mode == GET_MODE (varop))
9625 /* Make a SUBREG if necessary. If we can't make it, fail. */
9626 varop = gen_lowpart (shift_mode, varop);
9627 if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9630 /* If we have an outer operation and we just made a shift, it is
9631 possible that we could have simplified the shift were it not
9632 for the outer operation. So try to do the simplification
9635 if (outer_op != UNKNOWN)
9636 x = simplify_shift_const_1 (code, shift_mode, varop, count);
9641 x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
9643 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9644 turn off all the bits that the shift would have turned off. */
9645 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9646 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9647 GET_MODE_MASK (result_mode) >> orig_count);
9649 /* Do the remainder of the processing in RESULT_MODE. */
9650 x = gen_lowpart_or_truncate (result_mode, x);
9652 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9655 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9657 if (outer_op != UNKNOWN)
9659 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9660 outer_const = trunc_int_for_mode (outer_const, result_mode);
9662 if (outer_op == AND)
9663 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9664 else if (outer_op == SET)
9666 /* This means that we have determined that the result is
9667 equivalent to a constant. This should be rare. */
9668 if (!side_effects_p (x))
9669 x = GEN_INT (outer_const);
9671 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9672 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9674 x = simplify_gen_binary (outer_op, result_mode, x,
9675 GEN_INT (outer_const));
9681 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
9682 The result of the shift is RESULT_MODE. If we cannot simplify it,
9683 return X or, if it is NULL, synthesize the expression with
9684 simplify_gen_binary. Otherwise, return a simplified value.
9686 The shift is normally computed in the widest mode we find in VAROP, as
9687 long as it isn't a different number of words than RESULT_MODE. Exceptions
9688 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9691 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
9692 rtx varop, int count)
9694 rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
9699 x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
9700 if (GET_MODE (x) != result_mode)
9701 x = gen_lowpart (result_mode, x);
9706 /* Like recog, but we receive the address of a pointer to a new pattern.
9707 We try to match the rtx that the pointer points to.
9708 If that fails, we may try to modify or replace the pattern,
9709 storing the replacement into the same pointer object.
9711 Modifications include deletion or addition of CLOBBERs.
9713 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9714 the CLOBBERs are placed.
9716 The value is the final insn code from the pattern ultimately matched,
9720 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9723 int insn_code_number;
9724 int num_clobbers_to_add = 0;
9727 rtx old_notes, old_pat;
9729 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9730 we use to indicate that something didn't match. If we find such a
9731 thing, force rejection. */
9732 if (GET_CODE (pat) == PARALLEL)
9733 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9734 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9735 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9738 old_pat = PATTERN (insn);
9739 old_notes = REG_NOTES (insn);
9740 PATTERN (insn) = pat;
9741 REG_NOTES (insn) = 0;
9743 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9744 if (dump_file && (dump_flags & TDF_DETAILS))
9746 if (insn_code_number < 0)
9747 fputs ("Failed to match this instruction:\n", dump_file);
9749 fputs ("Successfully matched this instruction:\n", dump_file);
9750 print_rtl_single (dump_file, pat);
9753 /* If it isn't, there is the possibility that we previously had an insn
9754 that clobbered some register as a side effect, but the combined
9755 insn doesn't need to do that. So try once more without the clobbers
9756 unless this represents an ASM insn. */
9758 if (insn_code_number < 0 && ! check_asm_operands (pat)
9759 && GET_CODE (pat) == PARALLEL)
9763 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9764 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9767 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9771 SUBST_INT (XVECLEN (pat, 0), pos);
9774 pat = XVECEXP (pat, 0, 0);
9776 PATTERN (insn) = pat;
9777 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9778 if (dump_file && (dump_flags & TDF_DETAILS))
9780 if (insn_code_number < 0)
9781 fputs ("Failed to match this instruction:\n", dump_file);
9783 fputs ("Successfully matched this instruction:\n", dump_file);
9784 print_rtl_single (dump_file, pat);
9787 PATTERN (insn) = old_pat;
9788 REG_NOTES (insn) = old_notes;
9790 /* Recognize all noop sets, these will be killed by followup pass. */
9791 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9792 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9794 /* If we had any clobbers to add, make a new pattern than contains
9795 them. Then check to make sure that all of them are dead. */
9796 if (num_clobbers_to_add)
9798 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9799 rtvec_alloc (GET_CODE (pat) == PARALLEL
9801 + num_clobbers_to_add)
9802 : num_clobbers_to_add + 1));
9804 if (GET_CODE (pat) == PARALLEL)
9805 for (i = 0; i < XVECLEN (pat, 0); i++)
9806 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9808 XVECEXP (newpat, 0, 0) = pat;
9810 add_clobbers (newpat, insn_code_number);
9812 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9813 i < XVECLEN (newpat, 0); i++)
9815 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9816 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9818 if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
9820 gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
9821 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9822 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9831 return insn_code_number;
9834 /* Like gen_lowpart_general but for use by combine. In combine it
9835 is not possible to create any new pseudoregs. However, it is
9836 safe to create invalid memory addresses, because combine will
9837 try to recognize them and all they will do is make the combine
9840 If for some reason this cannot do its job, an rtx
9841 (clobber (const_int 0)) is returned.
9842 An insn containing that will not be recognized. */
9845 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9847 enum machine_mode imode = GET_MODE (x);
9848 unsigned int osize = GET_MODE_SIZE (omode);
9849 unsigned int isize = GET_MODE_SIZE (imode);
9855 /* Return identity if this is a CONST or symbolic reference. */
9857 && (GET_CODE (x) == CONST
9858 || GET_CODE (x) == SYMBOL_REF
9859 || GET_CODE (x) == LABEL_REF))
9862 /* We can only support MODE being wider than a word if X is a
9863 constant integer or has a mode the same size. */
9864 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9865 && ! ((imode == VOIDmode
9866 && (GET_CODE (x) == CONST_INT
9867 || GET_CODE (x) == CONST_DOUBLE))
9871 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9872 won't know what to do. So we will strip off the SUBREG here and
9873 process normally. */
9874 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9878 /* For use in case we fall down into the address adjustments
9879 further below, we need to adjust the known mode and size of
9880 x; imode and isize, since we just adjusted x. */
9881 imode = GET_MODE (x);
9886 isize = GET_MODE_SIZE (imode);
9889 result = gen_lowpart_common (omode, x);
9898 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9900 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9903 /* If we want to refer to something bigger than the original memref,
9904 generate a paradoxical subreg instead. That will force a reload
9905 of the original memref X. */
9907 return gen_rtx_SUBREG (omode, x, 0);
9909 if (WORDS_BIG_ENDIAN)
9910 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9912 /* Adjust the address so that the address-after-the-data is
9914 if (BYTES_BIG_ENDIAN)
9915 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9917 return adjust_address_nv (x, omode, offset);
9920 /* If X is a comparison operator, rewrite it in a new mode. This
9921 probably won't match, but may allow further simplifications. */
9922 else if (COMPARISON_P (x))
9923 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9925 /* If we couldn't simplify X any other way, just enclose it in a
9926 SUBREG. Normally, this SUBREG won't match, but some patterns may
9927 include an explicit SUBREG or we may simplify it further in combine. */
9933 offset = subreg_lowpart_offset (omode, imode);
9934 if (imode == VOIDmode)
9936 imode = int_mode_for_mode (omode);
9937 x = gen_lowpart_common (imode, x);
9941 res = simplify_gen_subreg (omode, x, imode, offset);
9947 return gen_rtx_CLOBBER (imode, const0_rtx);
9950 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9951 comparison code that will be tested.
9953 The result is a possibly different comparison code to use. *POP0 and
9954 *POP1 may be updated.
9956 It is possible that we might detect that a comparison is either always
9957 true or always false. However, we do not perform general constant
9958 folding in combine, so this knowledge isn't useful. Such tautologies
9959 should have been detected earlier. Hence we ignore all such cases. */
9961 static enum rtx_code
9962 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9968 enum machine_mode mode, tmode;
9970 /* Try a few ways of applying the same transformation to both operands. */
9973 #ifndef WORD_REGISTER_OPERATIONS
9974 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9975 so check specially. */
9976 if (code != GTU && code != GEU && code != LTU && code != LEU
9977 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9978 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9979 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9980 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9981 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9982 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9983 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9984 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9985 && XEXP (op0, 1) == XEXP (op1, 1)
9986 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9987 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9988 && (INTVAL (XEXP (op0, 1))
9989 == (GET_MODE_BITSIZE (GET_MODE (op0))
9991 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9993 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9994 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9998 /* If both operands are the same constant shift, see if we can ignore the
9999 shift. We can if the shift is a rotate or if the bits shifted out of
10000 this shift are known to be zero for both inputs and if the type of
10001 comparison is compatible with the shift. */
10002 if (GET_CODE (op0) == GET_CODE (op1)
10003 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10004 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
10005 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
10006 && (code != GT && code != LT && code != GE && code != LE))
10007 || (GET_CODE (op0) == ASHIFTRT
10008 && (code != GTU && code != LTU
10009 && code != GEU && code != LEU)))
10010 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10011 && INTVAL (XEXP (op0, 1)) >= 0
10012 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10013 && XEXP (op0, 1) == XEXP (op1, 1))
10015 enum machine_mode mode = GET_MODE (op0);
10016 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10017 int shift_count = INTVAL (XEXP (op0, 1));
10019 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
10020 mask &= (mask >> shift_count) << shift_count;
10021 else if (GET_CODE (op0) == ASHIFT)
10022 mask = (mask & (mask << shift_count)) >> shift_count;
10024 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
10025 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
10026 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
10031 /* If both operands are AND's of a paradoxical SUBREG by constant, the
10032 SUBREGs are of the same mode, and, in both cases, the AND would
10033 be redundant if the comparison was done in the narrower mode,
10034 do the comparison in the narrower mode (e.g., we are AND'ing with 1
10035 and the operand's possibly nonzero bits are 0xffffff01; in that case
10036 if we only care about QImode, we don't need the AND). This case
10037 occurs if the output mode of an scc insn is not SImode and
10038 STORE_FLAG_VALUE == 1 (e.g., the 386).
10040 Similarly, check for a case where the AND's are ZERO_EXTEND
10041 operations from some narrower mode even though a SUBREG is not
10044 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
10045 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10046 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
10048 rtx inner_op0 = XEXP (op0, 0);
10049 rtx inner_op1 = XEXP (op1, 0);
10050 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
10051 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
10054 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
10055 && (GET_MODE_SIZE (GET_MODE (inner_op0))
10056 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
10057 && (GET_MODE (SUBREG_REG (inner_op0))
10058 == GET_MODE (SUBREG_REG (inner_op1)))
10059 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
10060 <= HOST_BITS_PER_WIDE_INT)
10061 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
10062 GET_MODE (SUBREG_REG (inner_op0)))))
10063 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
10064 GET_MODE (SUBREG_REG (inner_op1))))))
10066 op0 = SUBREG_REG (inner_op0);
10067 op1 = SUBREG_REG (inner_op1);
10069 /* The resulting comparison is always unsigned since we masked
10070 off the original sign bit. */
10071 code = unsigned_condition (code);
10077 for (tmode = GET_CLASS_NARROWEST_MODE
10078 (GET_MODE_CLASS (GET_MODE (op0)));
10079 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
10080 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
10082 op0 = gen_lowpart (tmode, inner_op0);
10083 op1 = gen_lowpart (tmode, inner_op1);
10084 code = unsigned_condition (code);
10093 /* If both operands are NOT, we can strip off the outer operation
10094 and adjust the comparison code for swapped operands; similarly for
10095 NEG, except that this must be an equality comparison. */
10096 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
10097 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
10098 && (code == EQ || code == NE)))
10099 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
10105 /* If the first operand is a constant, swap the operands and adjust the
10106 comparison code appropriately, but don't do this if the second operand
10107 is already a constant integer. */
10108 if (swap_commutative_operands_p (op0, op1))
10110 tem = op0, op0 = op1, op1 = tem;
10111 code = swap_condition (code);
10114 /* We now enter a loop during which we will try to simplify the comparison.
10115 For the most part, we only are concerned with comparisons with zero,
10116 but some things may really be comparisons with zero but not start
10117 out looking that way. */
10119 while (GET_CODE (op1) == CONST_INT)
10121 enum machine_mode mode = GET_MODE (op0);
10122 unsigned int mode_width = GET_MODE_BITSIZE (mode);
10123 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
10124 int equality_comparison_p;
10125 int sign_bit_comparison_p;
10126 int unsigned_comparison_p;
10127 HOST_WIDE_INT const_op;
10129 /* We only want to handle integral modes. This catches VOIDmode,
10130 CCmode, and the floating-point modes. An exception is that we
10131 can handle VOIDmode if OP0 is a COMPARE or a comparison
10134 if (GET_MODE_CLASS (mode) != MODE_INT
10135 && ! (mode == VOIDmode
10136 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
10139 /* Get the constant we are comparing against and turn off all bits
10140 not on in our mode. */
10141 const_op = INTVAL (op1);
10142 if (mode != VOIDmode)
10143 const_op = trunc_int_for_mode (const_op, mode);
10144 op1 = GEN_INT (const_op);
10146 /* If we are comparing against a constant power of two and the value
10147 being compared can only have that single bit nonzero (e.g., it was
10148 `and'ed with that bit), we can replace this with a comparison
10151 && (code == EQ || code == NE || code == GE || code == GEU
10152 || code == LT || code == LTU)
10153 && mode_width <= HOST_BITS_PER_WIDE_INT
10154 && exact_log2 (const_op) >= 0
10155 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10157 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10158 op1 = const0_rtx, const_op = 0;
10161 /* Similarly, if we are comparing a value known to be either -1 or
10162 0 with -1, change it to the opposite comparison against zero. */
10165 && (code == EQ || code == NE || code == GT || code == LE
10166 || code == GEU || code == LTU)
10167 && num_sign_bit_copies (op0, mode) == mode_width)
10169 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10170 op1 = const0_rtx, const_op = 0;
10173 /* Do some canonicalizations based on the comparison code. We prefer
10174 comparisons against zero and then prefer equality comparisons.
10175 If we can reduce the size of a constant, we will do that too. */
10180 /* < C is equivalent to <= (C - 1) */
10184 op1 = GEN_INT (const_op);
10186 /* ... fall through to LE case below. */
10192 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10196 op1 = GEN_INT (const_op);
10200 /* If we are doing a <= 0 comparison on a value known to have
10201 a zero sign bit, we can replace this with == 0. */
10202 else if (const_op == 0
10203 && mode_width <= HOST_BITS_PER_WIDE_INT
10204 && (nonzero_bits (op0, mode)
10205 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10210 /* >= C is equivalent to > (C - 1). */
10214 op1 = GEN_INT (const_op);
10216 /* ... fall through to GT below. */
10222 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
10226 op1 = GEN_INT (const_op);
10230 /* If we are doing a > 0 comparison on a value known to have
10231 a zero sign bit, we can replace this with != 0. */
10232 else if (const_op == 0
10233 && mode_width <= HOST_BITS_PER_WIDE_INT
10234 && (nonzero_bits (op0, mode)
10235 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
10240 /* < C is equivalent to <= (C - 1). */
10244 op1 = GEN_INT (const_op);
10246 /* ... fall through ... */
10249 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10250 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10251 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10253 const_op = 0, op1 = const0_rtx;
10261 /* unsigned <= 0 is equivalent to == 0 */
10265 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10266 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10267 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10269 const_op = 0, op1 = const0_rtx;
10275 /* >= C is equivalent to > (C - 1). */
10279 op1 = GEN_INT (const_op);
10281 /* ... fall through ... */
10284 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10285 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10286 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
10288 const_op = 0, op1 = const0_rtx;
10296 /* unsigned > 0 is equivalent to != 0 */
10300 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10301 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
10302 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
10304 const_op = 0, op1 = const0_rtx;
10313 /* Compute some predicates to simplify code below. */
10315 equality_comparison_p = (code == EQ || code == NE);
10316 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
10317 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
10320 /* If this is a sign bit comparison and we can do arithmetic in
10321 MODE, say that we will only be needing the sign bit of OP0. */
10322 if (sign_bit_comparison_p
10323 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10324 op0 = force_to_mode (op0, mode,
10326 << (GET_MODE_BITSIZE (mode) - 1)),
10329 /* Now try cases based on the opcode of OP0. If none of the cases
10330 does a "continue", we exit this loop immediately after the
10333 switch (GET_CODE (op0))
10336 /* If we are extracting a single bit from a variable position in
10337 a constant that has only a single bit set and are comparing it
10338 with zero, we can convert this into an equality comparison
10339 between the position and the location of the single bit. */
10340 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
10341 have already reduced the shift count modulo the word size. */
10342 if (!SHIFT_COUNT_TRUNCATED
10343 && GET_CODE (XEXP (op0, 0)) == CONST_INT
10344 && XEXP (op0, 1) == const1_rtx
10345 && equality_comparison_p && const_op == 0
10346 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
10348 if (BITS_BIG_ENDIAN)
10350 enum machine_mode new_mode
10351 = mode_for_extraction (EP_extzv, 1);
10352 if (new_mode == MAX_MACHINE_MODE)
10353 i = BITS_PER_WORD - 1 - i;
10357 i = (GET_MODE_BITSIZE (mode) - 1 - i);
10361 op0 = XEXP (op0, 2);
10365 /* Result is nonzero iff shift count is equal to I. */
10366 code = reverse_condition (code);
10370 /* ... fall through ... */
10373 tem = expand_compound_operation (op0);
10382 /* If testing for equality, we can take the NOT of the constant. */
10383 if (equality_comparison_p
10384 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
10386 op0 = XEXP (op0, 0);
10391 /* If just looking at the sign bit, reverse the sense of the
10393 if (sign_bit_comparison_p)
10395 op0 = XEXP (op0, 0);
10396 code = (code == GE ? LT : GE);
10402 /* If testing for equality, we can take the NEG of the constant. */
10403 if (equality_comparison_p
10404 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
10406 op0 = XEXP (op0, 0);
10411 /* The remaining cases only apply to comparisons with zero. */
10415 /* When X is ABS or is known positive,
10416 (neg X) is < 0 if and only if X != 0. */
10418 if (sign_bit_comparison_p
10419 && (GET_CODE (XEXP (op0, 0)) == ABS
10420 || (mode_width <= HOST_BITS_PER_WIDE_INT
10421 && (nonzero_bits (XEXP (op0, 0), mode)
10422 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
10424 op0 = XEXP (op0, 0);
10425 code = (code == LT ? NE : EQ);
10429 /* If we have NEG of something whose two high-order bits are the
10430 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10431 if (num_sign_bit_copies (op0, mode) >= 2)
10433 op0 = XEXP (op0, 0);
10434 code = swap_condition (code);
10440 /* If we are testing equality and our count is a constant, we
10441 can perform the inverse operation on our RHS. */
10442 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10443 && (tem = simplify_binary_operation (ROTATERT, mode,
10444 op1, XEXP (op0, 1))) != 0)
10446 op0 = XEXP (op0, 0);
10451 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10452 a particular bit. Convert it to an AND of a constant of that
10453 bit. This will be converted into a ZERO_EXTRACT. */
10454 if (const_op == 0 && sign_bit_comparison_p
10455 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10456 && mode_width <= HOST_BITS_PER_WIDE_INT)
10458 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10461 - INTVAL (XEXP (op0, 1)))));
10462 code = (code == LT ? NE : EQ);
10466 /* Fall through. */
10469 /* ABS is ignorable inside an equality comparison with zero. */
10470 if (const_op == 0 && equality_comparison_p)
10472 op0 = XEXP (op0, 0);
10478 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
10479 (compare FOO CONST) if CONST fits in FOO's mode and we
10480 are either testing inequality or have an unsigned
10481 comparison with ZERO_EXTEND or a signed comparison with
10482 SIGN_EXTEND. But don't do it if we don't have a compare
10483 insn of the given mode, since we'd have to revert it
10484 later on, and then we wouldn't know whether to sign- or
10486 mode = GET_MODE (XEXP (op0, 0));
10487 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10488 && ! unsigned_comparison_p
10489 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10490 && ((unsigned HOST_WIDE_INT) const_op
10491 < (((unsigned HOST_WIDE_INT) 1
10492 << (GET_MODE_BITSIZE (mode) - 1))))
10493 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10495 op0 = XEXP (op0, 0);
10501 /* Check for the case where we are comparing A - C1 with C2, that is
10503 (subreg:MODE (plus (A) (-C1))) op (C2)
10505 with C1 a constant, and try to lift the SUBREG, i.e. to do the
10506 comparison in the wider mode. One of the following two conditions
10507 must be true in order for this to be valid:
10509 1. The mode extension results in the same bit pattern being added
10510 on both sides and the comparison is equality or unsigned. As
10511 C2 has been truncated to fit in MODE, the pattern can only be
10514 2. The mode extension results in the sign bit being copied on
10517 The difficulty here is that we have predicates for A but not for
10518 (A - C1) so we need to check that C1 is within proper bounds so
10519 as to perturbate A as little as possible. */
10521 if (mode_width <= HOST_BITS_PER_WIDE_INT
10522 && subreg_lowpart_p (op0)
10523 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
10524 && GET_CODE (SUBREG_REG (op0)) == PLUS
10525 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
10527 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
10528 rtx a = XEXP (SUBREG_REG (op0), 0);
10529 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
10532 && (unsigned HOST_WIDE_INT) c1
10533 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
10534 && (equality_comparison_p || unsigned_comparison_p)
10535 /* (A - C1) zero-extends if it is positive and sign-extends
10536 if it is negative, C2 both zero- and sign-extends. */
10537 && ((0 == (nonzero_bits (a, inner_mode)
10538 & ~GET_MODE_MASK (mode))
10540 /* (A - C1) sign-extends if it is positive and 1-extends
10541 if it is negative, C2 both sign- and 1-extends. */
10542 || (num_sign_bit_copies (a, inner_mode)
10543 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10546 || ((unsigned HOST_WIDE_INT) c1
10547 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
10548 /* (A - C1) always sign-extends, like C2. */
10549 && num_sign_bit_copies (a, inner_mode)
10550 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
10551 - (mode_width - 1))))
10553 op0 = SUBREG_REG (op0);
10558 /* If the inner mode is narrower and we are extracting the low part,
10559 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10560 if (subreg_lowpart_p (op0)
10561 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10562 /* Fall through */ ;
10566 /* ... fall through ... */
10569 mode = GET_MODE (XEXP (op0, 0));
10570 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10571 && (unsigned_comparison_p || equality_comparison_p)
10572 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10573 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
10574 && optab_handler (cmp_optab, mode)->insn_code != CODE_FOR_nothing)
10576 op0 = XEXP (op0, 0);
10582 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10583 this for equality comparisons due to pathological cases involving
10585 if (equality_comparison_p
10586 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10587 op1, XEXP (op0, 1))))
10589 op0 = XEXP (op0, 0);
10594 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10595 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10596 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10598 op0 = XEXP (XEXP (op0, 0), 0);
10599 code = (code == LT ? EQ : NE);
10605 /* We used to optimize signed comparisons against zero, but that
10606 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10607 arrive here as equality comparisons, or (GEU, LTU) are
10608 optimized away. No need to special-case them. */
10610 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10611 (eq B (minus A C)), whichever simplifies. We can only do
10612 this for equality comparisons due to pathological cases involving
10614 if (equality_comparison_p
10615 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10616 XEXP (op0, 1), op1)))
10618 op0 = XEXP (op0, 0);
10623 if (equality_comparison_p
10624 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10625 XEXP (op0, 0), op1)))
10627 op0 = XEXP (op0, 1);
10632 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10633 of bits in X minus 1, is one iff X > 0. */
10634 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10635 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10636 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10638 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10640 op0 = XEXP (op0, 1);
10641 code = (code == GE ? LE : GT);
10647 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10648 if C is zero or B is a constant. */
10649 if (equality_comparison_p
10650 && 0 != (tem = simplify_binary_operation (XOR, mode,
10651 XEXP (op0, 1), op1)))
10653 op0 = XEXP (op0, 0);
10660 case UNEQ: case LTGT:
10661 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10662 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10663 case UNORDERED: case ORDERED:
10664 /* We can't do anything if OP0 is a condition code value, rather
10665 than an actual data value. */
10667 || CC0_P (XEXP (op0, 0))
10668 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10671 /* Get the two operands being compared. */
10672 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10673 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10675 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10677 /* Check for the cases where we simply want the result of the
10678 earlier test or the opposite of that result. */
10679 if (code == NE || code == EQ
10680 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10681 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10682 && (STORE_FLAG_VALUE
10683 & (((HOST_WIDE_INT) 1
10684 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10685 && (code == LT || code == GE)))
10687 enum rtx_code new_code;
10688 if (code == LT || code == NE)
10689 new_code = GET_CODE (op0);
10691 new_code = reversed_comparison_code (op0, NULL);
10693 if (new_code != UNKNOWN)
10704 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10706 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10707 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10708 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10710 op0 = XEXP (op0, 1);
10711 code = (code == GE ? GT : LE);
10717 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10718 will be converted to a ZERO_EXTRACT later. */
10719 if (const_op == 0 && equality_comparison_p
10720 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10721 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10723 op0 = simplify_and_const_int
10724 (NULL_RTX, mode, gen_rtx_LSHIFTRT (mode,
10726 XEXP (XEXP (op0, 0), 1)),
10727 (HOST_WIDE_INT) 1);
10731 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10732 zero and X is a comparison and C1 and C2 describe only bits set
10733 in STORE_FLAG_VALUE, we can compare with X. */
10734 if (const_op == 0 && equality_comparison_p
10735 && mode_width <= HOST_BITS_PER_WIDE_INT
10736 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10737 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10738 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10739 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10740 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10742 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10743 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10744 if ((~STORE_FLAG_VALUE & mask) == 0
10745 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10746 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10747 && COMPARISON_P (tem))))
10749 op0 = XEXP (XEXP (op0, 0), 0);
10754 /* If we are doing an equality comparison of an AND of a bit equal
10755 to the sign bit, replace this with a LT or GE comparison of
10756 the underlying value. */
10757 if (equality_comparison_p
10759 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10760 && mode_width <= HOST_BITS_PER_WIDE_INT
10761 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10762 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10764 op0 = XEXP (op0, 0);
10765 code = (code == EQ ? GE : LT);
10769 /* If this AND operation is really a ZERO_EXTEND from a narrower
10770 mode, the constant fits within that mode, and this is either an
10771 equality or unsigned comparison, try to do this comparison in
10776 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
10777 -> (ne:DI (reg:SI 4) (const_int 0))
10779 unless TRULY_NOOP_TRUNCATION allows it or the register is
10780 known to hold a value of the required mode the
10781 transformation is invalid. */
10782 if ((equality_comparison_p || unsigned_comparison_p)
10783 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10784 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10785 & GET_MODE_MASK (mode))
10787 && const_op >> i == 0
10788 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
10789 && (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (tmode),
10790 GET_MODE_BITSIZE (GET_MODE (op0)))
10791 || (REG_P (XEXP (op0, 0))
10792 && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
10794 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10798 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10799 fits in both M1 and M2 and the SUBREG is either paradoxical
10800 or represents the low part, permute the SUBREG and the AND
10802 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10804 unsigned HOST_WIDE_INT c1;
10805 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10806 /* Require an integral mode, to avoid creating something like
10808 if (SCALAR_INT_MODE_P (tmode)
10809 /* It is unsafe to commute the AND into the SUBREG if the
10810 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10811 not defined. As originally written the upper bits
10812 have a defined value due to the AND operation.
10813 However, if we commute the AND inside the SUBREG then
10814 they no longer have defined values and the meaning of
10815 the code has been changed. */
10817 #ifdef WORD_REGISTER_OPERATIONS
10818 || (mode_width > GET_MODE_BITSIZE (tmode)
10819 && mode_width <= BITS_PER_WORD)
10821 || (mode_width <= GET_MODE_BITSIZE (tmode)
10822 && subreg_lowpart_p (XEXP (op0, 0))))
10823 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10824 && mode_width <= HOST_BITS_PER_WIDE_INT
10825 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10826 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10827 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10829 && c1 != GET_MODE_MASK (tmode))
10831 op0 = simplify_gen_binary (AND, tmode,
10832 SUBREG_REG (XEXP (op0, 0)),
10833 gen_int_mode (c1, tmode));
10834 op0 = gen_lowpart (mode, op0);
10839 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10840 if (const_op == 0 && equality_comparison_p
10841 && XEXP (op0, 1) == const1_rtx
10842 && GET_CODE (XEXP (op0, 0)) == NOT)
10844 op0 = simplify_and_const_int
10845 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10846 code = (code == NE ? EQ : NE);
10850 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10851 (eq (and (lshiftrt X) 1) 0).
10852 Also handle the case where (not X) is expressed using xor. */
10853 if (const_op == 0 && equality_comparison_p
10854 && XEXP (op0, 1) == const1_rtx
10855 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10857 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10858 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10860 if (GET_CODE (shift_op) == NOT
10861 || (GET_CODE (shift_op) == XOR
10862 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10863 && GET_CODE (shift_count) == CONST_INT
10864 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10865 && (INTVAL (XEXP (shift_op, 1))
10866 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10868 op0 = simplify_and_const_int
10870 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10871 (HOST_WIDE_INT) 1);
10872 code = (code == NE ? EQ : NE);
10879 /* If we have (compare (ashift FOO N) (const_int C)) and
10880 the high order N bits of FOO (N+1 if an inequality comparison)
10881 are known to be zero, we can do this by comparing FOO with C
10882 shifted right N bits so long as the low-order N bits of C are
10884 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10885 && INTVAL (XEXP (op0, 1)) >= 0
10886 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10887 < HOST_BITS_PER_WIDE_INT)
10889 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10890 && mode_width <= HOST_BITS_PER_WIDE_INT
10891 && (nonzero_bits (XEXP (op0, 0), mode)
10892 & ~(mask >> (INTVAL (XEXP (op0, 1))
10893 + ! equality_comparison_p))) == 0)
10895 /* We must perform a logical shift, not an arithmetic one,
10896 as we want the top N bits of C to be zero. */
10897 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10899 temp >>= INTVAL (XEXP (op0, 1));
10900 op1 = gen_int_mode (temp, mode);
10901 op0 = XEXP (op0, 0);
10905 /* If we are doing a sign bit comparison, it means we are testing
10906 a particular bit. Convert it to the appropriate AND. */
10907 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10908 && mode_width <= HOST_BITS_PER_WIDE_INT)
10910 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10913 - INTVAL (XEXP (op0, 1)))));
10914 code = (code == LT ? NE : EQ);
10918 /* If this an equality comparison with zero and we are shifting
10919 the low bit to the sign bit, we can convert this to an AND of the
10921 if (const_op == 0 && equality_comparison_p
10922 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10923 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10926 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10927 (HOST_WIDE_INT) 1);
10933 /* If this is an equality comparison with zero, we can do this
10934 as a logical shift, which might be much simpler. */
10935 if (equality_comparison_p && const_op == 0
10936 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10938 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10940 INTVAL (XEXP (op0, 1)));
10944 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10945 do the comparison in a narrower mode. */
10946 if (! unsigned_comparison_p
10947 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10948 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10949 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10950 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10951 MODE_INT, 1)) != BLKmode
10952 && (((unsigned HOST_WIDE_INT) const_op
10953 + (GET_MODE_MASK (tmode) >> 1) + 1)
10954 <= GET_MODE_MASK (tmode)))
10956 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10960 /* Likewise if OP0 is a PLUS of a sign extension with a
10961 constant, which is usually represented with the PLUS
10962 between the shifts. */
10963 if (! unsigned_comparison_p
10964 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10965 && GET_CODE (XEXP (op0, 0)) == PLUS
10966 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10967 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10968 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10969 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10970 MODE_INT, 1)) != BLKmode
10971 && (((unsigned HOST_WIDE_INT) const_op
10972 + (GET_MODE_MASK (tmode) >> 1) + 1)
10973 <= GET_MODE_MASK (tmode)))
10975 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10976 rtx add_const = XEXP (XEXP (op0, 0), 1);
10977 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10978 add_const, XEXP (op0, 1));
10980 op0 = simplify_gen_binary (PLUS, tmode,
10981 gen_lowpart (tmode, inner),
10986 /* ... fall through ... */
10988 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10989 the low order N bits of FOO are known to be zero, we can do this
10990 by comparing FOO with C shifted left N bits so long as no
10991 overflow occurs. */
10992 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10993 && INTVAL (XEXP (op0, 1)) >= 0
10994 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10995 && mode_width <= HOST_BITS_PER_WIDE_INT
10996 && (nonzero_bits (XEXP (op0, 0), mode)
10997 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10998 && (((unsigned HOST_WIDE_INT) const_op
10999 + (GET_CODE (op0) != LSHIFTRT
11000 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11003 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11005 /* If the shift was logical, then we must make the condition
11007 if (GET_CODE (op0) == LSHIFTRT)
11008 code = unsigned_condition (code);
11010 const_op <<= INTVAL (XEXP (op0, 1));
11011 op1 = GEN_INT (const_op);
11012 op0 = XEXP (op0, 0);
11016 /* If we are using this shift to extract just the sign bit, we
11017 can replace this with an LT or GE comparison. */
11019 && (equality_comparison_p || sign_bit_comparison_p)
11020 && GET_CODE (XEXP (op0, 1)) == CONST_INT
11021 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
11024 op0 = XEXP (op0, 0);
11025 code = (code == NE || code == GT ? LT : GE);
11037 /* Now make any compound operations involved in this comparison. Then,
11038 check for an outmost SUBREG on OP0 that is not doing anything or is
11039 paradoxical. The latter transformation must only be performed when
11040 it is known that the "extra" bits will be the same in op0 and op1 or
11041 that they don't matter. There are three cases to consider:
11043 1. SUBREG_REG (op0) is a register. In this case the bits are don't
11044 care bits and we can assume they have any convenient value. So
11045 making the transformation is safe.
11047 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11048 In this case the upper bits of op0 are undefined. We should not make
11049 the simplification in that case as we do not know the contents of
11052 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11053 UNKNOWN. In that case we know those bits are zeros or ones. We must
11054 also be sure that they are the same as the upper bits of op1.
11056 We can never remove a SUBREG for a non-equality comparison because
11057 the sign bit is in a different place in the underlying object. */
11059 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11060 op1 = make_compound_operation (op1, SET);
11062 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11063 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11064 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11065 && (code == NE || code == EQ))
11067 if (GET_MODE_SIZE (GET_MODE (op0))
11068 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
11070 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
11072 if (REG_P (SUBREG_REG (op0)))
11074 op0 = SUBREG_REG (op0);
11075 op1 = gen_lowpart (GET_MODE (op0), op1);
11078 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
11079 <= HOST_BITS_PER_WIDE_INT)
11080 && (nonzero_bits (SUBREG_REG (op0),
11081 GET_MODE (SUBREG_REG (op0)))
11082 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11084 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
11086 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
11087 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11088 op0 = SUBREG_REG (op0), op1 = tem;
11092 /* We now do the opposite procedure: Some machines don't have compare
11093 insns in all modes. If OP0's mode is an integer mode smaller than a
11094 word and we can't do a compare in that mode, see if there is a larger
11095 mode for which we can do the compare. There are a number of cases in
11096 which we can use the wider mode. */
11098 mode = GET_MODE (op0);
11099 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
11100 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
11101 && ! have_insn_for (COMPARE, mode))
11102 for (tmode = GET_MODE_WIDER_MODE (mode);
11104 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
11105 tmode = GET_MODE_WIDER_MODE (tmode))
11106 if (have_insn_for (COMPARE, tmode))
11110 /* If the only nonzero bits in OP0 and OP1 are those in the
11111 narrower mode and this is an equality or unsigned comparison,
11112 we can use the wider mode. Similarly for sign-extended
11113 values, in which case it is true for all comparisons. */
11114 zero_extended = ((code == EQ || code == NE
11115 || code == GEU || code == GTU
11116 || code == LEU || code == LTU)
11117 && (nonzero_bits (op0, tmode)
11118 & ~GET_MODE_MASK (mode)) == 0
11119 && ((GET_CODE (op1) == CONST_INT
11120 || (nonzero_bits (op1, tmode)
11121 & ~GET_MODE_MASK (mode)) == 0)));
11124 || ((num_sign_bit_copies (op0, tmode)
11125 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11126 - GET_MODE_BITSIZE (mode)))
11127 && (num_sign_bit_copies (op1, tmode)
11128 > (unsigned int) (GET_MODE_BITSIZE (tmode)
11129 - GET_MODE_BITSIZE (mode)))))
11131 /* If OP0 is an AND and we don't have an AND in MODE either,
11132 make a new AND in the proper mode. */
11133 if (GET_CODE (op0) == AND
11134 && !have_insn_for (AND, mode))
11135 op0 = simplify_gen_binary (AND, tmode,
11136 gen_lowpart (tmode,
11138 gen_lowpart (tmode,
11141 op0 = gen_lowpart (tmode, op0);
11142 if (zero_extended && GET_CODE (op1) == CONST_INT)
11143 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
11144 op1 = gen_lowpart (tmode, op1);
11148 /* If this is a test for negative, we can make an explicit
11149 test of the sign bit. */
11151 if (op1 == const0_rtx && (code == LT || code == GE)
11152 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11154 op0 = simplify_gen_binary (AND, tmode,
11155 gen_lowpart (tmode, op0),
11156 GEN_INT ((HOST_WIDE_INT) 1
11157 << (GET_MODE_BITSIZE (mode)
11159 code = (code == LT) ? NE : EQ;
11164 #ifdef CANONICALIZE_COMPARISON
11165 /* If this machine only supports a subset of valid comparisons, see if we
11166 can convert an unsupported one into a supported one. */
11167 CANONICALIZE_COMPARISON (code, op0, op1);
11176 /* Utility function for record_value_for_reg. Count number of
11181 enum rtx_code code = GET_CODE (x);
11185 if (GET_RTX_CLASS (code) == '2'
11186 || GET_RTX_CLASS (code) == 'c')
11188 rtx x0 = XEXP (x, 0);
11189 rtx x1 = XEXP (x, 1);
11192 return 1 + 2 * count_rtxs (x0);
11194 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
11195 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
11196 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11197 return 2 + 2 * count_rtxs (x0)
11198 + count_rtxs (x == XEXP (x1, 0)
11199 ? XEXP (x1, 1) : XEXP (x1, 0));
11201 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
11202 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
11203 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11204 return 2 + 2 * count_rtxs (x1)
11205 + count_rtxs (x == XEXP (x0, 0)
11206 ? XEXP (x0, 1) : XEXP (x0, 0));
11209 fmt = GET_RTX_FORMAT (code);
11210 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11212 ret += count_rtxs (XEXP (x, i));
11217 /* Utility function for following routine. Called when X is part of a value
11218 being stored into last_set_value. Sets last_set_table_tick
11219 for each register mentioned. Similar to mention_regs in cse.c */
11222 update_table_tick (rtx x)
11224 enum rtx_code code = GET_CODE (x);
11225 const char *fmt = GET_RTX_FORMAT (code);
11230 unsigned int regno = REGNO (x);
11231 unsigned int endregno = END_REGNO (x);
11234 for (r = regno; r < endregno; r++)
11236 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
11237 rsp->last_set_table_tick = label_tick;
11243 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11244 /* Note that we can't have an "E" in values stored; see
11245 get_last_value_validate. */
11248 /* Check for identical subexpressions. If x contains
11249 identical subexpression we only have to traverse one of
11251 if (i == 0 && ARITHMETIC_P (x))
11253 /* Note that at this point x1 has already been
11255 rtx x0 = XEXP (x, 0);
11256 rtx x1 = XEXP (x, 1);
11258 /* If x0 and x1 are identical then there is no need to
11263 /* If x0 is identical to a subexpression of x1 then while
11264 processing x1, x0 has already been processed. Thus we
11265 are done with x. */
11266 if (ARITHMETIC_P (x1)
11267 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11270 /* If x1 is identical to a subexpression of x0 then we
11271 still have to process the rest of x0. */
11272 if (ARITHMETIC_P (x0)
11273 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11275 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
11280 update_table_tick (XEXP (x, i));
11284 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
11285 are saying that the register is clobbered and we no longer know its
11286 value. If INSN is zero, don't update reg_stat[].last_set; this is
11287 only permitted with VALUE also zero and is used to invalidate the
11291 record_value_for_reg (rtx reg, rtx insn, rtx value)
11293 unsigned int regno = REGNO (reg);
11294 unsigned int endregno = END_REGNO (reg);
11296 reg_stat_type *rsp;
11298 /* If VALUE contains REG and we have a previous value for REG, substitute
11299 the previous value. */
11300 if (value && insn && reg_overlap_mentioned_p (reg, value))
11304 /* Set things up so get_last_value is allowed to see anything set up to
11306 subst_low_luid = DF_INSN_LUID (insn);
11307 tem = get_last_value (reg);
11309 /* If TEM is simply a binary operation with two CLOBBERs as operands,
11310 it isn't going to be useful and will take a lot of time to process,
11311 so just use the CLOBBER. */
11315 if (ARITHMETIC_P (tem)
11316 && GET_CODE (XEXP (tem, 0)) == CLOBBER
11317 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
11318 tem = XEXP (tem, 0);
11319 else if (count_occurrences (value, reg, 1) >= 2)
11321 /* If there are two or more occurrences of REG in VALUE,
11322 prevent the value from growing too much. */
11323 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
11324 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
11327 value = replace_rtx (copy_rtx (value), reg, tem);
11331 /* For each register modified, show we don't know its value, that
11332 we don't know about its bitwise content, that its value has been
11333 updated, and that we don't know the location of the death of the
11335 for (i = regno; i < endregno; i++)
11337 rsp = VEC_index (reg_stat_type, reg_stat, i);
11340 rsp->last_set = insn;
11342 rsp->last_set_value = 0;
11343 rsp->last_set_mode = 0;
11344 rsp->last_set_nonzero_bits = 0;
11345 rsp->last_set_sign_bit_copies = 0;
11346 rsp->last_death = 0;
11347 rsp->truncated_to_mode = 0;
11350 /* Mark registers that are being referenced in this value. */
11352 update_table_tick (value);
11354 /* Now update the status of each register being set.
11355 If someone is using this register in this block, set this register
11356 to invalid since we will get confused between the two lives in this
11357 basic block. This makes using this register always invalid. In cse, we
11358 scan the table to invalidate all entries using this register, but this
11359 is too much work for us. */
11361 for (i = regno; i < endregno; i++)
11363 rsp = VEC_index (reg_stat_type, reg_stat, i);
11364 rsp->last_set_label = label_tick;
11366 || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
11367 rsp->last_set_invalid = 1;
11369 rsp->last_set_invalid = 0;
11372 /* The value being assigned might refer to X (like in "x++;"). In that
11373 case, we must replace it with (clobber (const_int 0)) to prevent
11375 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11376 if (value && ! get_last_value_validate (&value, insn,
11377 rsp->last_set_label, 0))
11379 value = copy_rtx (value);
11380 if (! get_last_value_validate (&value, insn,
11381 rsp->last_set_label, 1))
11385 /* For the main register being modified, update the value, the mode, the
11386 nonzero bits, and the number of sign bit copies. */
11388 rsp->last_set_value = value;
11392 enum machine_mode mode = GET_MODE (reg);
11393 subst_low_luid = DF_INSN_LUID (insn);
11394 rsp->last_set_mode = mode;
11395 if (GET_MODE_CLASS (mode) == MODE_INT
11396 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
11397 mode = nonzero_bits_mode;
11398 rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
11399 rsp->last_set_sign_bit_copies
11400 = num_sign_bit_copies (value, GET_MODE (reg));
11404 /* Called via note_stores from record_dead_and_set_regs to handle one
11405 SET or CLOBBER in an insn. DATA is the instruction in which the
11406 set is occurring. */
11409 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
11411 rtx record_dead_insn = (rtx) data;
11413 if (GET_CODE (dest) == SUBREG)
11414 dest = SUBREG_REG (dest);
11416 if (!record_dead_insn)
11419 record_value_for_reg (dest, NULL_RTX, NULL_RTX);
11425 /* If we are setting the whole register, we know its value. Otherwise
11426 show that we don't know the value. We can handle SUBREG in
11428 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
11429 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
11430 else if (GET_CODE (setter) == SET
11431 && GET_CODE (SET_DEST (setter)) == SUBREG
11432 && SUBREG_REG (SET_DEST (setter)) == dest
11433 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
11434 && subreg_lowpart_p (SET_DEST (setter)))
11435 record_value_for_reg (dest, record_dead_insn,
11436 gen_lowpart (GET_MODE (dest),
11437 SET_SRC (setter)));
11439 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
11441 else if (MEM_P (dest)
11442 /* Ignore pushes, they clobber nothing. */
11443 && ! push_operand (dest, GET_MODE (dest)))
11444 mem_last_set = DF_INSN_LUID (record_dead_insn);
11447 /* Update the records of when each REG was most recently set or killed
11448 for the things done by INSN. This is the last thing done in processing
11449 INSN in the combiner loop.
11451 We update reg_stat[], in particular fields last_set, last_set_value,
11452 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
11453 last_death, and also the similar information mem_last_set (which insn
11454 most recently modified memory) and last_call_luid (which insn was the
11455 most recent subroutine call). */
11458 record_dead_and_set_regs (rtx insn)
11463 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
11465 if (REG_NOTE_KIND (link) == REG_DEAD
11466 && REG_P (XEXP (link, 0)))
11468 unsigned int regno = REGNO (XEXP (link, 0));
11469 unsigned int endregno = END_REGNO (XEXP (link, 0));
11471 for (i = regno; i < endregno; i++)
11473 reg_stat_type *rsp;
11475 rsp = VEC_index (reg_stat_type, reg_stat, i);
11476 rsp->last_death = insn;
11479 else if (REG_NOTE_KIND (link) == REG_INC)
11480 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
11485 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
11486 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
11488 reg_stat_type *rsp;
11490 rsp = VEC_index (reg_stat_type, reg_stat, i);
11491 rsp->last_set_invalid = 1;
11492 rsp->last_set = insn;
11493 rsp->last_set_value = 0;
11494 rsp->last_set_mode = 0;
11495 rsp->last_set_nonzero_bits = 0;
11496 rsp->last_set_sign_bit_copies = 0;
11497 rsp->last_death = 0;
11498 rsp->truncated_to_mode = 0;
11501 last_call_luid = mem_last_set = DF_INSN_LUID (insn);
11503 /* We can't combine into a call pattern. Remember, though, that
11504 the return value register is set at this LUID. We could
11505 still replace a register with the return value from the
11506 wrong subroutine call! */
11507 note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
11510 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
11513 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11514 register present in the SUBREG, so for each such SUBREG go back and
11515 adjust nonzero and sign bit information of the registers that are
11516 known to have some zero/sign bits set.
11518 This is needed because when combine blows the SUBREGs away, the
11519 information on zero/sign bits is lost and further combines can be
11520 missed because of that. */
11523 record_promoted_value (rtx insn, rtx subreg)
11526 unsigned int regno = REGNO (SUBREG_REG (subreg));
11527 enum machine_mode mode = GET_MODE (subreg);
11529 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
11532 for (links = LOG_LINKS (insn); links;)
11534 reg_stat_type *rsp;
11536 insn = XEXP (links, 0);
11537 set = single_set (insn);
11539 if (! set || !REG_P (SET_DEST (set))
11540 || REGNO (SET_DEST (set)) != regno
11541 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
11543 links = XEXP (links, 1);
11547 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11548 if (rsp->last_set == insn)
11550 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
11551 rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
11554 if (REG_P (SET_SRC (set)))
11556 regno = REGNO (SET_SRC (set));
11557 links = LOG_LINKS (insn);
11564 /* Check if X, a register, is known to contain a value already
11565 truncated to MODE. In this case we can use a subreg to refer to
11566 the truncated value even though in the generic case we would need
11567 an explicit truncation. */
11570 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
11572 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11573 enum machine_mode truncated = rsp->truncated_to_mode;
11576 || rsp->truncation_label < label_tick_ebb_start)
11578 if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
11580 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
11581 GET_MODE_BITSIZE (truncated)))
11586 /* Callback for for_each_rtx. If *P is a hard reg or a subreg record the mode
11587 that the register is accessed in. For non-TRULY_NOOP_TRUNCATION targets we
11588 might be able to turn a truncate into a subreg using this information.
11589 Return -1 if traversing *P is complete or 0 otherwise. */
11592 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
11595 enum machine_mode truncated_mode;
11596 reg_stat_type *rsp;
11598 if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
11600 enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
11601 truncated_mode = GET_MODE (x);
11603 if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
11606 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (truncated_mode),
11607 GET_MODE_BITSIZE (original_mode)))
11610 x = SUBREG_REG (x);
11612 /* ??? For hard-regs we now record everything. We might be able to
11613 optimize this using last_set_mode. */
11614 else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
11615 truncated_mode = GET_MODE (x);
11619 rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
11620 if (rsp->truncated_to_mode == 0
11621 || rsp->truncation_label < label_tick_ebb_start
11622 || (GET_MODE_SIZE (truncated_mode)
11623 < GET_MODE_SIZE (rsp->truncated_to_mode)))
11625 rsp->truncated_to_mode = truncated_mode;
11626 rsp->truncation_label = label_tick;
11632 /* Callback for note_uses. Find hardregs and subregs of pseudos and
11633 the modes they are used in. This can help truning TRUNCATEs into
11637 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
11639 for_each_rtx (x, record_truncated_value, NULL);
11642 /* Scan X for promoted SUBREGs. For each one found,
11643 note what it implies to the registers used in it. */
11646 check_promoted_subreg (rtx insn, rtx x)
11648 if (GET_CODE (x) == SUBREG
11649 && SUBREG_PROMOTED_VAR_P (x)
11650 && REG_P (SUBREG_REG (x)))
11651 record_promoted_value (insn, x);
11654 const char *format = GET_RTX_FORMAT (GET_CODE (x));
11657 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
11661 check_promoted_subreg (insn, XEXP (x, i));
11665 if (XVEC (x, i) != 0)
11666 for (j = 0; j < XVECLEN (x, i); j++)
11667 check_promoted_subreg (insn, XVECEXP (x, i, j));
11673 /* Utility routine for the following function. Verify that all the registers
11674 mentioned in *LOC are valid when *LOC was part of a value set when
11675 label_tick == TICK. Return 0 if some are not.
11677 If REPLACE is nonzero, replace the invalid reference with
11678 (clobber (const_int 0)) and return 1. This replacement is useful because
11679 we often can get useful information about the form of a value (e.g., if
11680 it was produced by a shift that always produces -1 or 0) even though
11681 we don't know exactly what registers it was produced from. */
11684 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11687 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11688 int len = GET_RTX_LENGTH (GET_CODE (x));
11693 unsigned int regno = REGNO (x);
11694 unsigned int endregno = END_REGNO (x);
11697 for (j = regno; j < endregno; j++)
11699 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
11700 if (rsp->last_set_invalid
11701 /* If this is a pseudo-register that was only set once and not
11702 live at the beginning of the function, it is always valid. */
11703 || (! (regno >= FIRST_PSEUDO_REGISTER
11704 && REG_N_SETS (regno) == 1
11705 && (!REGNO_REG_SET_P
11706 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
11707 && rsp->last_set_label > tick))
11710 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11717 /* If this is a memory reference, make sure that there were
11718 no stores after it that might have clobbered the value. We don't
11719 have alias info, so we assume any store invalidates it. */
11720 else if (MEM_P (x) && !MEM_READONLY_P (x)
11721 && DF_INSN_LUID (insn) <= mem_last_set)
11724 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11728 for (i = 0; i < len; i++)
11732 /* Check for identical subexpressions. If x contains
11733 identical subexpression we only have to traverse one of
11735 if (i == 1 && ARITHMETIC_P (x))
11737 /* Note that at this point x0 has already been checked
11738 and found valid. */
11739 rtx x0 = XEXP (x, 0);
11740 rtx x1 = XEXP (x, 1);
11742 /* If x0 and x1 are identical then x is also valid. */
11746 /* If x1 is identical to a subexpression of x0 then
11747 while checking x0, x1 has already been checked. Thus
11748 it is valid and so as x. */
11749 if (ARITHMETIC_P (x0)
11750 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11753 /* If x0 is identical to a subexpression of x1 then x is
11754 valid iff the rest of x1 is valid. */
11755 if (ARITHMETIC_P (x1)
11756 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11758 get_last_value_validate (&XEXP (x1,
11759 x0 == XEXP (x1, 0) ? 1 : 0),
11760 insn, tick, replace);
11763 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11767 /* Don't bother with these. They shouldn't occur anyway. */
11768 else if (fmt[i] == 'E')
11772 /* If we haven't found a reason for it to be invalid, it is valid. */
11776 /* Get the last value assigned to X, if known. Some registers
11777 in the value may be replaced with (clobber (const_int 0)) if their value
11778 is known longer known reliably. */
11781 get_last_value (const_rtx x)
11783 unsigned int regno;
11785 reg_stat_type *rsp;
11787 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11788 then convert it to the desired mode. If this is a paradoxical SUBREG,
11789 we cannot predict what values the "extra" bits might have. */
11790 if (GET_CODE (x) == SUBREG
11791 && subreg_lowpart_p (x)
11792 && (GET_MODE_SIZE (GET_MODE (x))
11793 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11794 && (value = get_last_value (SUBREG_REG (x))) != 0)
11795 return gen_lowpart (GET_MODE (x), value);
11801 rsp = VEC_index (reg_stat_type, reg_stat, regno);
11802 value = rsp->last_set_value;
11804 /* If we don't have a value, or if it isn't for this basic block and
11805 it's either a hard register, set more than once, or it's a live
11806 at the beginning of the function, return 0.
11808 Because if it's not live at the beginning of the function then the reg
11809 is always set before being used (is never used without being set).
11810 And, if it's set only once, and it's always set before use, then all
11811 uses must have the same last value, even if it's not from this basic
11815 || (rsp->last_set_label < label_tick_ebb_start
11816 && (regno < FIRST_PSEUDO_REGISTER
11817 || REG_N_SETS (regno) != 1
11819 (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
11822 /* If the value was set in a later insn than the ones we are processing,
11823 we can't use it even if the register was only set once. */
11824 if (rsp->last_set_label == label_tick
11825 && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
11828 /* If the value has all its registers valid, return it. */
11829 if (get_last_value_validate (&value, rsp->last_set,
11830 rsp->last_set_label, 0))
11833 /* Otherwise, make a copy and replace any invalid register with
11834 (clobber (const_int 0)). If that fails for some reason, return 0. */
11836 value = copy_rtx (value);
11837 if (get_last_value_validate (&value, rsp->last_set,
11838 rsp->last_set_label, 1))
11844 /* Return nonzero if expression X refers to a REG or to memory
11845 that is set in an instruction more recent than FROM_LUID. */
11848 use_crosses_set_p (const_rtx x, int from_luid)
11852 enum rtx_code code = GET_CODE (x);
11856 unsigned int regno = REGNO (x);
11857 unsigned endreg = END_REGNO (x);
11859 #ifdef PUSH_ROUNDING
11860 /* Don't allow uses of the stack pointer to be moved,
11861 because we don't know whether the move crosses a push insn. */
11862 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11865 for (; regno < endreg; regno++)
11867 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
11869 && rsp->last_set_label == label_tick
11870 && DF_INSN_LUID (rsp->last_set) > from_luid)
11876 if (code == MEM && mem_last_set > from_luid)
11879 fmt = GET_RTX_FORMAT (code);
11881 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11886 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11887 if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
11890 else if (fmt[i] == 'e'
11891 && use_crosses_set_p (XEXP (x, i), from_luid))
11897 /* Define three variables used for communication between the following
11900 static unsigned int reg_dead_regno, reg_dead_endregno;
11901 static int reg_dead_flag;
11903 /* Function called via note_stores from reg_dead_at_p.
11905 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11906 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11909 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
11911 unsigned int regno, endregno;
11916 regno = REGNO (dest);
11917 endregno = END_REGNO (dest);
11918 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11919 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11922 /* Return nonzero if REG is known to be dead at INSN.
11924 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11925 referencing REG, it is dead. If we hit a SET referencing REG, it is
11926 live. Otherwise, see if it is live or dead at the start of the basic
11927 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11928 must be assumed to be always live. */
11931 reg_dead_at_p (rtx reg, rtx insn)
11936 /* Set variables for reg_dead_at_p_1. */
11937 reg_dead_regno = REGNO (reg);
11938 reg_dead_endregno = END_REGNO (reg);
11942 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11943 we allow the machine description to decide whether use-and-clobber
11944 patterns are OK. */
11945 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11947 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11948 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11952 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11953 beginning of function. */
11954 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11955 insn = prev_nonnote_insn (insn))
11957 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11959 return reg_dead_flag == 1 ? 1 : 0;
11961 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11965 /* Get the basic block that we were in. */
11967 block = ENTRY_BLOCK_PTR->next_bb;
11970 FOR_EACH_BB (block)
11971 if (insn == BB_HEAD (block))
11974 if (block == EXIT_BLOCK_PTR)
11978 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11979 if (REGNO_REG_SET_P (df_get_live_in (block), i))
11985 /* Note hard registers in X that are used. */
11988 mark_used_regs_combine (rtx x)
11990 RTX_CODE code = GET_CODE (x);
11991 unsigned int regno;
12004 case ADDR_DIFF_VEC:
12007 /* CC0 must die in the insn after it is set, so we don't need to take
12008 special note of it here. */
12014 /* If we are clobbering a MEM, mark any hard registers inside the
12015 address as used. */
12016 if (MEM_P (XEXP (x, 0)))
12017 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12022 /* A hard reg in a wide mode may really be multiple registers.
12023 If so, mark all of them just like the first. */
12024 if (regno < FIRST_PSEUDO_REGISTER)
12026 /* None of this applies to the stack, frame or arg pointers. */
12027 if (regno == STACK_POINTER_REGNUM
12028 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
12029 || regno == HARD_FRAME_POINTER_REGNUM
12031 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12032 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12034 || regno == FRAME_POINTER_REGNUM)
12037 add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12043 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12045 rtx testreg = SET_DEST (x);
12047 while (GET_CODE (testreg) == SUBREG
12048 || GET_CODE (testreg) == ZERO_EXTRACT
12049 || GET_CODE (testreg) == STRICT_LOW_PART)
12050 testreg = XEXP (testreg, 0);
12052 if (MEM_P (testreg))
12053 mark_used_regs_combine (XEXP (testreg, 0));
12055 mark_used_regs_combine (SET_SRC (x));
12063 /* Recursively scan the operands of this expression. */
12066 const char *fmt = GET_RTX_FORMAT (code);
12068 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12071 mark_used_regs_combine (XEXP (x, i));
12072 else if (fmt[i] == 'E')
12076 for (j = 0; j < XVECLEN (x, i); j++)
12077 mark_used_regs_combine (XVECEXP (x, i, j));
12083 /* Remove register number REGNO from the dead registers list of INSN.
12085 Return the note used to record the death, if there was one. */
12088 remove_death (unsigned int regno, rtx insn)
12090 rtx note = find_regno_note (insn, REG_DEAD, regno);
12093 remove_note (insn, note);
12098 /* For each register (hardware or pseudo) used within expression X, if its
12099 death is in an instruction with luid between FROM_LUID (inclusive) and
12100 TO_INSN (exclusive), put a REG_DEAD note for that register in the
12101 list headed by PNOTES.
12103 That said, don't move registers killed by maybe_kill_insn.
12105 This is done when X is being merged by combination into TO_INSN. These
12106 notes will then be distributed as needed. */
12109 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
12114 enum rtx_code code = GET_CODE (x);
12118 unsigned int regno = REGNO (x);
12119 rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
12121 /* Don't move the register if it gets killed in between from and to. */
12122 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
12123 && ! reg_referenced_p (x, maybe_kill_insn))
12127 && DF_INSN_LUID (where_dead) >= from_luid
12128 && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
12130 rtx note = remove_death (regno, where_dead);
12132 /* It is possible for the call above to return 0. This can occur
12133 when last_death points to I2 or I1 that we combined with.
12134 In that case make a new note.
12136 We must also check for the case where X is a hard register
12137 and NOTE is a death note for a range of hard registers
12138 including X. In that case, we must put REG_DEAD notes for
12139 the remaining registers in place of NOTE. */
12141 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
12142 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12143 > GET_MODE_SIZE (GET_MODE (x))))
12145 unsigned int deadregno = REGNO (XEXP (note, 0));
12146 unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
12147 unsigned int ourend = END_HARD_REGNO (x);
12150 for (i = deadregno; i < deadend; i++)
12151 if (i < regno || i >= ourend)
12152 add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
12155 /* If we didn't find any note, or if we found a REG_DEAD note that
12156 covers only part of the given reg, and we have a multi-reg hard
12157 register, then to be safe we must check for REG_DEAD notes
12158 for each register other than the first. They could have
12159 their own REG_DEAD notes lying around. */
12160 else if ((note == 0
12162 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
12163 < GET_MODE_SIZE (GET_MODE (x)))))
12164 && regno < FIRST_PSEUDO_REGISTER
12165 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
12167 unsigned int ourend = END_HARD_REGNO (x);
12168 unsigned int i, offset;
12172 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
12176 for (i = regno + offset; i < ourend; i++)
12177 move_deaths (regno_reg_rtx[i],
12178 maybe_kill_insn, from_luid, to_insn, &oldnotes);
12181 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
12183 XEXP (note, 1) = *pnotes;
12187 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
12193 else if (GET_CODE (x) == SET)
12195 rtx dest = SET_DEST (x);
12197 move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
12199 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
12200 that accesses one word of a multi-word item, some
12201 piece of everything register in the expression is used by
12202 this insn, so remove any old death. */
12203 /* ??? So why do we test for equality of the sizes? */
12205 if (GET_CODE (dest) == ZERO_EXTRACT
12206 || GET_CODE (dest) == STRICT_LOW_PART
12207 || (GET_CODE (dest) == SUBREG
12208 && (((GET_MODE_SIZE (GET_MODE (dest))
12209 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
12210 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
12211 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
12213 move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
12217 /* If this is some other SUBREG, we know it replaces the entire
12218 value, so use that as the destination. */
12219 if (GET_CODE (dest) == SUBREG)
12220 dest = SUBREG_REG (dest);
12222 /* If this is a MEM, adjust deaths of anything used in the address.
12223 For a REG (the only other possibility), the entire value is
12224 being replaced so the old value is not used in this insn. */
12227 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
12232 else if (GET_CODE (x) == CLOBBER)
12235 len = GET_RTX_LENGTH (code);
12236 fmt = GET_RTX_FORMAT (code);
12238 for (i = 0; i < len; i++)
12243 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12244 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
12247 else if (fmt[i] == 'e')
12248 move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
12252 /* Return 1 if X is the target of a bit-field assignment in BODY, the
12253 pattern of an insn. X must be a REG. */
12256 reg_bitfield_target_p (rtx x, rtx body)
12260 if (GET_CODE (body) == SET)
12262 rtx dest = SET_DEST (body);
12264 unsigned int regno, tregno, endregno, endtregno;
12266 if (GET_CODE (dest) == ZERO_EXTRACT)
12267 target = XEXP (dest, 0);
12268 else if (GET_CODE (dest) == STRICT_LOW_PART)
12269 target = SUBREG_REG (XEXP (dest, 0));
12273 if (GET_CODE (target) == SUBREG)
12274 target = SUBREG_REG (target);
12276 if (!REG_P (target))
12279 tregno = REGNO (target), regno = REGNO (x);
12280 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
12281 return target == x;
12283 endtregno = end_hard_regno (GET_MODE (target), tregno);
12284 endregno = end_hard_regno (GET_MODE (x), regno);
12286 return endregno > tregno && regno < endtregno;
12289 else if (GET_CODE (body) == PARALLEL)
12290 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
12291 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
12297 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
12298 as appropriate. I3 and I2 are the insns resulting from the combination
12299 insns including FROM (I2 may be zero).
12301 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
12302 not need REG_DEAD notes because they are being substituted for. This
12303 saves searching in the most common cases.
12305 Each note in the list is either ignored or placed on some insns, depending
12306 on the type of note. */
12309 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
12312 rtx note, next_note;
12315 for (note = notes; note; note = next_note)
12317 rtx place = 0, place2 = 0;
12319 next_note = XEXP (note, 1);
12320 switch (REG_NOTE_KIND (note))
12324 /* Doesn't matter much where we put this, as long as it's somewhere.
12325 It is preferable to keep these notes on branches, which is most
12326 likely to be i3. */
12330 case REG_VALUE_PROFILE:
12331 /* Just get rid of this note, as it is unused later anyway. */
12334 case REG_NON_LOCAL_GOTO:
12339 gcc_assert (i2 && JUMP_P (i2));
12344 case REG_EH_REGION:
12345 /* These notes must remain with the call or trapping instruction. */
12348 else if (i2 && CALL_P (i2))
12352 gcc_assert (flag_non_call_exceptions);
12353 if (may_trap_p (i3))
12355 else if (i2 && may_trap_p (i2))
12357 /* ??? Otherwise assume we've combined things such that we
12358 can now prove that the instructions can't trap. Drop the
12359 note in this case. */
12365 /* These notes must remain with the call. It should not be
12366 possible for both I2 and I3 to be a call. */
12371 gcc_assert (i2 && CALL_P (i2));
12377 /* Any clobbers for i3 may still exist, and so we must process
12378 REG_UNUSED notes from that insn.
12380 Any clobbers from i2 or i1 can only exist if they were added by
12381 recog_for_combine. In that case, recog_for_combine created the
12382 necessary REG_UNUSED notes. Trying to keep any original
12383 REG_UNUSED notes from these insns can cause incorrect output
12384 if it is for the same register as the original i3 dest.
12385 In that case, we will notice that the register is set in i3,
12386 and then add a REG_UNUSED note for the destination of i3, which
12387 is wrong. However, it is possible to have REG_UNUSED notes from
12388 i2 or i1 for register which were both used and clobbered, so
12389 we keep notes from i2 or i1 if they will turn into REG_DEAD
12392 /* If this register is set or clobbered in I3, put the note there
12393 unless there is one already. */
12394 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
12396 if (from_insn != i3)
12399 if (! (REG_P (XEXP (note, 0))
12400 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
12401 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
12404 /* Otherwise, if this register is used by I3, then this register
12405 now dies here, so we must put a REG_DEAD note here unless there
12407 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
12408 && ! (REG_P (XEXP (note, 0))
12409 ? find_regno_note (i3, REG_DEAD,
12410 REGNO (XEXP (note, 0)))
12411 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
12413 PUT_REG_NOTE_KIND (note, REG_DEAD);
12421 /* These notes say something about results of an insn. We can
12422 only support them if they used to be on I3 in which case they
12423 remain on I3. Otherwise they are ignored.
12425 If the note refers to an expression that is not a constant, we
12426 must also ignore the note since we cannot tell whether the
12427 equivalence is still true. It might be possible to do
12428 slightly better than this (we only have a problem if I2DEST
12429 or I1DEST is present in the expression), but it doesn't
12430 seem worth the trouble. */
12432 if (from_insn == i3
12433 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
12438 /* These notes say something about how a register is used. They must
12439 be present on any use of the register in I2 or I3. */
12440 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
12443 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
12452 case REG_LABEL_TARGET:
12453 case REG_LABEL_OPERAND:
12454 /* This can show up in several ways -- either directly in the
12455 pattern, or hidden off in the constant pool with (or without?)
12456 a REG_EQUAL note. */
12457 /* ??? Ignore the without-reg_equal-note problem for now. */
12458 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
12459 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
12460 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12461 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
12465 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
12466 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
12467 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
12468 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
12476 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
12477 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
12479 if (place && JUMP_P (place)
12480 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12481 && (JUMP_LABEL (place) == NULL
12482 || JUMP_LABEL (place) == XEXP (note, 0)))
12484 rtx label = JUMP_LABEL (place);
12487 JUMP_LABEL (place) = XEXP (note, 0);
12488 else if (LABEL_P (label))
12489 LABEL_NUSES (label)--;
12492 if (place2 && JUMP_P (place2)
12493 && REG_NOTE_KIND (note) == REG_LABEL_TARGET
12494 && (JUMP_LABEL (place2) == NULL
12495 || JUMP_LABEL (place2) == XEXP (note, 0)))
12497 rtx label = JUMP_LABEL (place2);
12500 JUMP_LABEL (place2) = XEXP (note, 0);
12501 else if (LABEL_P (label))
12502 LABEL_NUSES (label)--;
12508 /* This note says something about the value of a register prior
12509 to the execution of an insn. It is too much trouble to see
12510 if the note is still correct in all situations. It is better
12511 to simply delete it. */
12515 /* If we replaced the right hand side of FROM_INSN with a
12516 REG_EQUAL note, the original use of the dying register
12517 will not have been combined into I3 and I2. In such cases,
12518 FROM_INSN is guaranteed to be the first of the combined
12519 instructions, so we simply need to search back before
12520 FROM_INSN for the previous use or set of this register,
12521 then alter the notes there appropriately.
12523 If the register is used as an input in I3, it dies there.
12524 Similarly for I2, if it is nonzero and adjacent to I3.
12526 If the register is not used as an input in either I3 or I2
12527 and it is not one of the registers we were supposed to eliminate,
12528 there are two possibilities. We might have a non-adjacent I2
12529 or we might have somehow eliminated an additional register
12530 from a computation. For example, we might have had A & B where
12531 we discover that B will always be zero. In this case we will
12532 eliminate the reference to A.
12534 In both cases, we must search to see if we can find a previous
12535 use of A and put the death note there. */
12538 && from_insn == i2mod
12539 && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
12544 && CALL_P (from_insn)
12545 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
12547 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
12549 else if (i2 != 0 && next_nonnote_insn (i2) == i3
12550 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12552 else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
12554 && reg_overlap_mentioned_p (XEXP (note, 0),
12556 || rtx_equal_p (XEXP (note, 0), elim_i1))
12563 basic_block bb = this_basic_block;
12565 for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
12567 if (! INSN_P (tem))
12569 if (tem == BB_HEAD (bb))
12574 /* If the register is being set at TEM, see if that is all
12575 TEM is doing. If so, delete TEM. Otherwise, make this
12576 into a REG_UNUSED note instead. Don't delete sets to
12577 global register vars. */
12578 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
12579 || !global_regs[REGNO (XEXP (note, 0))])
12580 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
12582 rtx set = single_set (tem);
12583 rtx inner_dest = 0;
12585 rtx cc0_setter = NULL_RTX;
12589 for (inner_dest = SET_DEST (set);
12590 (GET_CODE (inner_dest) == STRICT_LOW_PART
12591 || GET_CODE (inner_dest) == SUBREG
12592 || GET_CODE (inner_dest) == ZERO_EXTRACT);
12593 inner_dest = XEXP (inner_dest, 0))
12596 /* Verify that it was the set, and not a clobber that
12597 modified the register.
12599 CC0 targets must be careful to maintain setter/user
12600 pairs. If we cannot delete the setter due to side
12601 effects, mark the user with an UNUSED note instead
12604 if (set != 0 && ! side_effects_p (SET_SRC (set))
12605 && rtx_equal_p (XEXP (note, 0), inner_dest)
12607 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
12608 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
12609 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12613 /* Move the notes and links of TEM elsewhere.
12614 This might delete other dead insns recursively.
12615 First set the pattern to something that won't use
12617 rtx old_notes = REG_NOTES (tem);
12619 PATTERN (tem) = pc_rtx;
12620 REG_NOTES (tem) = NULL;
12622 distribute_notes (old_notes, tem, tem, NULL_RTX,
12623 NULL_RTX, NULL_RTX);
12624 distribute_links (LOG_LINKS (tem));
12626 SET_INSN_DELETED (tem);
12629 /* Delete the setter too. */
12632 PATTERN (cc0_setter) = pc_rtx;
12633 old_notes = REG_NOTES (cc0_setter);
12634 REG_NOTES (cc0_setter) = NULL;
12636 distribute_notes (old_notes, cc0_setter,
12637 cc0_setter, NULL_RTX,
12638 NULL_RTX, NULL_RTX);
12639 distribute_links (LOG_LINKS (cc0_setter));
12641 SET_INSN_DELETED (cc0_setter);
12647 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12649 /* If there isn't already a REG_UNUSED note, put one
12650 here. Do not place a REG_DEAD note, even if
12651 the register is also used here; that would not
12652 match the algorithm used in lifetime analysis
12653 and can cause the consistency check in the
12654 scheduler to fail. */
12655 if (! find_regno_note (tem, REG_UNUSED,
12656 REGNO (XEXP (note, 0))))
12661 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12663 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12667 /* If we are doing a 3->2 combination, and we have a
12668 register which formerly died in i3 and was not used
12669 by i2, which now no longer dies in i3 and is used in
12670 i2 but does not die in i2, and place is between i2
12671 and i3, then we may need to move a link from place to
12673 if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
12675 && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
12676 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12678 rtx links = LOG_LINKS (place);
12679 LOG_LINKS (place) = 0;
12680 distribute_links (links);
12685 if (tem == BB_HEAD (bb))
12691 /* If the register is set or already dead at PLACE, we needn't do
12692 anything with this note if it is still a REG_DEAD note.
12693 We check here if it is set at all, not if is it totally replaced,
12694 which is what `dead_or_set_p' checks, so also check for it being
12697 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12699 unsigned int regno = REGNO (XEXP (note, 0));
12700 reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12702 if (dead_or_set_p (place, XEXP (note, 0))
12703 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12705 /* Unless the register previously died in PLACE, clear
12706 last_death. [I no longer understand why this is
12708 if (rsp->last_death != place)
12709 rsp->last_death = 0;
12713 rsp->last_death = place;
12715 /* If this is a death note for a hard reg that is occupying
12716 multiple registers, ensure that we are still using all
12717 parts of the object. If we find a piece of the object
12718 that is unused, we must arrange for an appropriate REG_DEAD
12719 note to be added for it. However, we can't just emit a USE
12720 and tag the note to it, since the register might actually
12721 be dead; so we recourse, and the recursive call then finds
12722 the previous insn that used this register. */
12724 if (place && regno < FIRST_PSEUDO_REGISTER
12725 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12727 unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
12731 for (i = regno; i < endregno; i++)
12732 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12733 && ! find_regno_fusage (place, USE, i))
12734 || dead_or_set_regno_p (place, i))
12739 /* Put only REG_DEAD notes for pieces that are
12740 not already dead or set. */
12742 for (i = regno; i < endregno;
12743 i += hard_regno_nregs[i][reg_raw_mode[i]])
12745 rtx piece = regno_reg_rtx[i];
12746 basic_block bb = this_basic_block;
12748 if (! dead_or_set_p (place, piece)
12749 && ! reg_bitfield_target_p (piece,
12753 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12755 distribute_notes (new_note, place, place,
12756 NULL_RTX, NULL_RTX, NULL_RTX);
12758 else if (! refers_to_regno_p (i, i + 1,
12759 PATTERN (place), 0)
12760 && ! find_regno_fusage (place, USE, i))
12761 for (tem = PREV_INSN (place); ;
12762 tem = PREV_INSN (tem))
12764 if (! INSN_P (tem))
12766 if (tem == BB_HEAD (bb))
12770 if (dead_or_set_p (tem, piece)
12771 || reg_bitfield_target_p (piece,
12774 add_reg_note (tem, REG_UNUSED, piece);
12788 /* Any other notes should not be present at this point in the
12790 gcc_unreachable ();
12795 XEXP (note, 1) = REG_NOTES (place);
12796 REG_NOTES (place) = note;
12801 = gen_rtx_fmt_ee (GET_CODE (note), REG_NOTE_KIND (note),
12802 XEXP (note, 0), REG_NOTES (place2));
12806 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12807 I3, I2, and I1 to new locations. This is also called to add a link
12808 pointing at I3 when I3's destination is changed. */
12811 distribute_links (rtx links)
12813 rtx link, next_link;
12815 for (link = links; link; link = next_link)
12821 next_link = XEXP (link, 1);
12823 /* If the insn that this link points to is a NOTE or isn't a single
12824 set, ignore it. In the latter case, it isn't clear what we
12825 can do other than ignore the link, since we can't tell which
12826 register it was for. Such links wouldn't be used by combine
12829 It is not possible for the destination of the target of the link to
12830 have been changed by combine. The only potential of this is if we
12831 replace I3, I2, and I1 by I3 and I2. But in that case the
12832 destination of I2 also remains unchanged. */
12834 if (NOTE_P (XEXP (link, 0))
12835 || (set = single_set (XEXP (link, 0))) == 0)
12838 reg = SET_DEST (set);
12839 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12840 || GET_CODE (reg) == STRICT_LOW_PART)
12841 reg = XEXP (reg, 0);
12843 /* A LOG_LINK is defined as being placed on the first insn that uses
12844 a register and points to the insn that sets the register. Start
12845 searching at the next insn after the target of the link and stop
12846 when we reach a set of the register or the end of the basic block.
12848 Note that this correctly handles the link that used to point from
12849 I3 to I2. Also note that not much searching is typically done here
12850 since most links don't point very far away. */
12852 for (insn = NEXT_INSN (XEXP (link, 0));
12853 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12854 || BB_HEAD (this_basic_block->next_bb) != insn));
12855 insn = NEXT_INSN (insn))
12856 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12858 if (reg_referenced_p (reg, PATTERN (insn)))
12862 else if (CALL_P (insn)
12863 && find_reg_fusage (insn, USE, reg))
12868 else if (INSN_P (insn) && reg_set_p (reg, insn))
12871 /* If we found a place to put the link, place it there unless there
12872 is already a link to the same insn as LINK at that point. */
12878 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12879 if (XEXP (link2, 0) == XEXP (link, 0))
12884 XEXP (link, 1) = LOG_LINKS (place);
12885 LOG_LINKS (place) = link;
12887 /* Set added_links_insn to the earliest insn we added a
12889 if (added_links_insn == 0
12890 || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
12891 added_links_insn = place;
12897 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12898 Check whether the expression pointer to by LOC is a register or
12899 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12900 Otherwise return zero. */
12903 unmentioned_reg_p_1 (rtx *loc, void *expr)
12908 && (REG_P (x) || MEM_P (x))
12909 && ! reg_mentioned_p (x, (rtx) expr))
12914 /* Check for any register or memory mentioned in EQUIV that is not
12915 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12916 of EXPR where some registers may have been replaced by constants. */
12919 unmentioned_reg_p (rtx equiv, rtx expr)
12921 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12925 dump_combine_stats (FILE *file)
12929 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12930 combine_attempts, combine_merges, combine_extras, combine_successes);
12934 dump_combine_total_stats (FILE *file)
12938 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12939 total_attempts, total_merges, total_extras, total_successes);
12943 gate_handle_combine (void)
12945 return (optimize > 0);
12948 /* Try combining insns through substitution. */
12949 static unsigned int
12950 rest_of_handle_combine (void)
12952 int rebuild_jump_labels_after_combine;
12954 df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
12955 df_note_add_problem ();
12958 regstat_init_n_sets_and_refs ();
12960 rebuild_jump_labels_after_combine
12961 = combine_instructions (get_insns (), max_reg_num ());
12963 /* Combining insns may have turned an indirect jump into a
12964 direct jump. Rebuild the JUMP_LABEL fields of jumping
12966 if (rebuild_jump_labels_after_combine)
12968 timevar_push (TV_JUMP);
12969 rebuild_jump_labels (get_insns ());
12971 timevar_pop (TV_JUMP);
12974 regstat_free_n_sets_and_refs ();
12978 struct rtl_opt_pass pass_combine =
12982 "combine", /* name */
12983 gate_handle_combine, /* gate */
12984 rest_of_handle_combine, /* execute */
12987 0, /* static_pass_number */
12988 TV_COMBINE, /* tv_id */
12989 0, /* properties_required */
12990 0, /* properties_provided */
12991 0, /* properties_destroyed */
12992 0, /* todo_flags_start */
12994 TODO_df_finish | TODO_verify_rtl_sharing |
12995 TODO_ggc_collect, /* todo_flags_finish */