1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
57 removed because there is no way to know which register it was
60 To simplify substitution, we combine only when the earlier insn(s)
61 consist of only a single assignment. To simplify updating afterward,
62 we never combine when a subroutine call appears in the middle.
64 Since we do not represent assignments to CC0 explicitly except when that
65 is all an insn does, there is no LOG_LINKS entry in an insn that uses
66 the condition code for the insn that set the condition code.
67 Fortunately, these two insns must be consecutive.
68 Therefore, every JUMP_INSN is taken to have an implicit logical link
69 to the preceding insn. This is not quite right, since non-jumps can
70 also use the condition code; but in practice such insns would not
75 #include "coretypes.h"
82 #include "hard-reg-set.h"
83 #include "basic-block.h"
84 #include "insn-config.h"
86 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
88 #include "insn-attr.h"
93 #include "rtlhooks-def.h"
94 /* Include output.h for dump_file. */
97 /* Number of attempts to combine instructions in this function. */
99 static int combine_attempts;
101 /* Number of attempts that got as far as substitution in this function. */
103 static int combine_merges;
105 /* Number of instructions combined with added SETs in this function. */
107 static int combine_extras;
109 /* Number of instructions combined in this function. */
111 static int combine_successes;
113 /* Totals over entire compilation. */
115 static int total_attempts, total_merges, total_extras, total_successes;
118 /* Vector mapping INSN_UIDs to cuids.
119 The cuids are like uids but increase monotonically always.
120 Combine always uses cuids so that it can compare them.
121 But actually renumbering the uids, which we used to do,
122 proves to be a bad idea because it makes it hard to compare
123 the dumps produced by earlier passes with those from later passes. */
125 static int *uid_cuid;
126 static int max_uid_cuid;
128 /* Get the cuid of an insn. */
130 #define INSN_CUID(INSN) \
131 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
133 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
134 BITS_PER_WORD would invoke undefined behavior. Work around it. */
136 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
137 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
139 /* Maximum register number, which is the size of the tables below. */
141 static unsigned int combine_max_regno;
144 /* Record last point of death of (hard or pseudo) register n. */
147 /* Record last point of modification of (hard or pseudo) register n. */
150 /* The next group of fields allows the recording of the last value assigned
151 to (hard or pseudo) register n. We use this information to see if an
152 operation being processed is redundant given a prior operation performed
153 on the register. For example, an `and' with a constant is redundant if
154 all the zero bits are already known to be turned off.
156 We use an approach similar to that used by cse, but change it in the
159 (1) We do not want to reinitialize at each label.
160 (2) It is useful, but not critical, to know the actual value assigned
161 to a register. Often just its form is helpful.
163 Therefore, we maintain the following fields:
165 last_set_value the last value assigned
166 last_set_label records the value of label_tick when the
167 register was assigned
168 last_set_table_tick records the value of label_tick when a
169 value using the register is assigned
170 last_set_invalid set to nonzero when it is not valid
171 to use the value of this register in some
174 To understand the usage of these tables, it is important to understand
175 the distinction between the value in last_set_value being valid and
176 the register being validly contained in some other expression in the
179 (The next two parameters are out of date).
181 reg_stat[i].last_set_value is valid if it is nonzero, and either
182 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
184 Register I may validly appear in any expression returned for the value
185 of another register if reg_n_sets[i] is 1. It may also appear in the
186 value for register J if reg_stat[j].last_set_invalid is zero, or
187 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
189 If an expression is found in the table containing a register which may
190 not validly appear in an expression, the register is replaced by
191 something that won't match, (clobber (const_int 0)). */
193 /* Record last value assigned to (hard or pseudo) register n. */
197 /* Record the value of label_tick when an expression involving register n
198 is placed in last_set_value. */
200 int last_set_table_tick;
202 /* Record the value of label_tick when the value for register n is placed in
207 /* These fields are maintained in parallel with last_set_value and are
208 used to store the mode in which the register was last set, the bits
209 that were known to be zero when it was last set, and the number of
210 sign bits copies it was known to have when it was last set. */
212 unsigned HOST_WIDE_INT last_set_nonzero_bits;
213 char last_set_sign_bit_copies;
214 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
216 /* Set nonzero if references to register n in expressions should not be
217 used. last_set_invalid is set nonzero when this register is being
218 assigned to and last_set_table_tick == label_tick. */
220 char last_set_invalid;
222 /* Some registers that are set more than once and used in more than one
223 basic block are nevertheless always set in similar ways. For example,
224 a QImode register may be loaded from memory in two places on a machine
225 where byte loads zero extend.
227 We record in the following fields if a register has some leading bits
228 that are always equal to the sign bit, and what we know about the
229 nonzero bits of a register, specifically which bits are known to be
232 If an entry is zero, it means that we don't know anything special. */
234 unsigned char sign_bit_copies;
236 unsigned HOST_WIDE_INT nonzero_bits;
239 static struct reg_stat *reg_stat;
241 /* Record the cuid of the last insn that invalidated memory
242 (anything that writes memory, and subroutine calls, but not pushes). */
244 static int mem_last_set;
246 /* Record the cuid of the last CALL_INSN
247 so we can tell whether a potential combination crosses any calls. */
249 static int last_call_cuid;
251 /* When `subst' is called, this is the insn that is being modified
252 (by combining in a previous insn). The PATTERN of this insn
253 is still the old pattern partially modified and it should not be
254 looked at, but this may be used to examine the successors of the insn
255 to judge whether a simplification is valid. */
257 static rtx subst_insn;
259 /* This is the lowest CUID that `subst' is currently dealing with.
260 get_last_value will not return a value if the register was set at or
261 after this CUID. If not for this mechanism, we could get confused if
262 I2 or I1 in try_combine were an insn that used the old value of a register
263 to obtain a new value. In that case, we might erroneously get the
264 new value of the register when we wanted the old one. */
266 static int subst_low_cuid;
268 /* This contains any hard registers that are used in newpat; reg_dead_at_p
269 must consider all these registers to be always live. */
271 static HARD_REG_SET newpat_used_regs;
273 /* This is an insn to which a LOG_LINKS entry has been added. If this
274 insn is the earlier than I2 or I3, combine should rescan starting at
277 static rtx added_links_insn;
279 /* Basic block in which we are performing combines. */
280 static basic_block this_basic_block;
282 /* A bitmap indicating which blocks had registers go dead at entry.
283 After combine, we'll need to re-do global life analysis with
284 those blocks as starting points. */
285 static sbitmap refresh_blocks;
287 /* The following array records the insn_rtx_cost for every insn
288 in the instruction stream. */
290 static int *uid_insn_cost;
292 /* Length of the currently allocated uid_insn_cost array. */
294 static int last_insn_cost;
296 /* Incremented for each label. */
298 static int label_tick;
300 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
301 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
303 static enum machine_mode nonzero_bits_mode;
305 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
306 be safely used. It is zero while computing them and after combine has
307 completed. This former test prevents propagating values based on
308 previously set values, which can be incorrect if a variable is modified
311 static int nonzero_sign_valid;
314 /* Record one modification to rtl structure
315 to be undone by storing old_contents into *where.
316 is_int is 1 if the contents are an int. */
322 union {rtx r; int i;} old_contents;
323 union {rtx *r; int *i;} where;
326 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
327 num_undo says how many are currently recorded.
329 other_insn is nonzero if we have modified some other insn in the process
330 of working on subst_insn. It must be verified too. */
339 static struct undobuf undobuf;
341 /* Number of times the pseudo being substituted for
342 was found and replaced. */
344 static int n_occurrences;
346 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
348 unsigned HOST_WIDE_INT,
349 unsigned HOST_WIDE_INT *);
350 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
352 unsigned int, unsigned int *);
353 static void do_SUBST (rtx *, rtx);
354 static void do_SUBST_INT (int *, int);
355 static void init_reg_last (void);
356 static void setup_incoming_promotions (void);
357 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
358 static int cant_combine_insn_p (rtx);
359 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
360 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
361 static int contains_muldiv (rtx);
362 static rtx try_combine (rtx, rtx, rtx, int *);
363 static void undo_all (void);
364 static void undo_commit (void);
365 static rtx *find_split_point (rtx *, rtx);
366 static rtx subst (rtx, rtx, rtx, int, int);
367 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
368 static rtx simplify_if_then_else (rtx);
369 static rtx simplify_set (rtx);
370 static rtx simplify_logical (rtx);
371 static rtx expand_compound_operation (rtx);
372 static rtx expand_field_assignment (rtx);
373 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
374 rtx, unsigned HOST_WIDE_INT, int, int, int);
375 static rtx extract_left_shift (rtx, int);
376 static rtx make_compound_operation (rtx, enum rtx_code);
377 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
378 unsigned HOST_WIDE_INT *);
379 static rtx force_to_mode (rtx, enum machine_mode,
380 unsigned HOST_WIDE_INT, rtx, int);
381 static rtx if_then_else_cond (rtx, rtx *, rtx *);
382 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
383 static int rtx_equal_for_field_assignment_p (rtx, rtx);
384 static rtx make_field_assignment (rtx);
385 static rtx apply_distributive_law (rtx);
386 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
387 unsigned HOST_WIDE_INT);
388 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
389 HOST_WIDE_INT, enum machine_mode, int *);
390 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
392 static int recog_for_combine (rtx *, rtx, rtx *);
393 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
394 static rtx gen_binary (enum rtx_code, enum machine_mode, rtx, rtx);
395 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
396 static void update_table_tick (rtx);
397 static void record_value_for_reg (rtx, rtx, rtx);
398 static void check_promoted_subreg (rtx, rtx);
399 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
400 static void record_dead_and_set_regs (rtx);
401 static int get_last_value_validate (rtx *, rtx, int, int);
402 static rtx get_last_value (rtx);
403 static int use_crosses_set_p (rtx, int);
404 static void reg_dead_at_p_1 (rtx, rtx, void *);
405 static int reg_dead_at_p (rtx, rtx);
406 static void move_deaths (rtx, rtx, int, rtx, rtx *);
407 static int reg_bitfield_target_p (rtx, rtx);
408 static void distribute_notes (rtx, rtx, rtx, rtx);
409 static void distribute_links (rtx);
410 static void mark_used_regs_combine (rtx);
411 static int insn_cuid (rtx);
412 static void record_promoted_value (rtx, rtx);
413 static rtx reversed_comparison (rtx, enum machine_mode, rtx, rtx);
414 static enum rtx_code combine_reversed_comparison_code (rtx);
415 static int unmentioned_reg_p_1 (rtx *, void *);
416 static bool unmentioned_reg_p (rtx, rtx);
419 /* It is not safe to use ordinary gen_lowpart in combine.
420 See comments in gen_lowpart_for_combine. */
421 #undef RTL_HOOKS_GEN_LOWPART
422 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
424 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
425 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
427 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
428 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
430 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
433 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
434 insn. The substitution can be undone by undo_all. If INTO is already
435 set to NEWVAL, do not record this change. Because computing NEWVAL might
436 also call SUBST, we have to compute it before we put anything into
440 do_SUBST (rtx *into, rtx newval)
445 if (oldval == newval)
448 /* We'd like to catch as many invalid transformations here as
449 possible. Unfortunately, there are way too many mode changes
450 that are perfectly valid, so we'd waste too much effort for
451 little gain doing the checks here. Focus on catching invalid
452 transformations involving integer constants. */
453 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
454 && GET_CODE (newval) == CONST_INT)
456 /* Sanity check that we're replacing oldval with a CONST_INT
457 that is a valid sign-extension for the original mode. */
458 gcc_assert (INTVAL (newval)
459 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
461 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
462 CONST_INT is not valid, because after the replacement, the
463 original mode would be gone. Unfortunately, we can't tell
464 when do_SUBST is called to replace the operand thereof, so we
465 perform this test on oldval instead, checking whether an
466 invalid replacement took place before we got here. */
467 gcc_assert (!(GET_CODE (oldval) == SUBREG
468 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
469 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
470 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
474 buf = undobuf.frees, undobuf.frees = buf->next;
476 buf = xmalloc (sizeof (struct undo));
480 buf->old_contents.r = oldval;
483 buf->next = undobuf.undos, undobuf.undos = buf;
486 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
488 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
489 for the value of a HOST_WIDE_INT value (including CONST_INT) is
493 do_SUBST_INT (int *into, int newval)
498 if (oldval == newval)
502 buf = undobuf.frees, undobuf.frees = buf->next;
504 buf = xmalloc (sizeof (struct undo));
508 buf->old_contents.i = oldval;
511 buf->next = undobuf.undos, undobuf.undos = buf;
514 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
516 /* Subroutine of try_combine. Determine whether the combine replacement
517 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
518 that the original instruction sequence I1, I2 and I3. Note that I1
519 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
520 costs of all instructions can be estimated, and the replacements are
521 more expensive than the original sequence. */
524 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
526 int i1_cost, i2_cost, i3_cost;
527 int new_i2_cost, new_i3_cost;
528 int old_cost, new_cost;
530 /* Lookup the original insn_rtx_costs. */
531 i2_cost = INSN_UID (i2) <= last_insn_cost
532 ? uid_insn_cost[INSN_UID (i2)] : 0;
533 i3_cost = INSN_UID (i3) <= last_insn_cost
534 ? uid_insn_cost[INSN_UID (i3)] : 0;
538 i1_cost = INSN_UID (i1) <= last_insn_cost
539 ? uid_insn_cost[INSN_UID (i1)] : 0;
540 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
541 ? i1_cost + i2_cost + i3_cost : 0;
545 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
549 /* Calculate the replacement insn_rtx_costs. */
550 new_i3_cost = insn_rtx_cost (newpat);
553 new_i2_cost = insn_rtx_cost (newi2pat);
554 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
555 ? new_i2_cost + new_i3_cost : 0;
559 new_cost = new_i3_cost;
563 /* Disallow this recombination if both new_cost and old_cost are
564 greater than zero, and new_cost is greater than old cost. */
565 if (!undobuf.other_insn
567 && new_cost > old_cost)
574 "rejecting combination of insns %d, %d and %d\n",
575 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
576 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
577 i1_cost, i2_cost, i3_cost, old_cost);
582 "rejecting combination of insns %d and %d\n",
583 INSN_UID (i2), INSN_UID (i3));
584 fprintf (dump_file, "original costs %d + %d = %d\n",
585 i2_cost, i3_cost, old_cost);
590 fprintf (dump_file, "replacement costs %d + %d = %d\n",
591 new_i2_cost, new_i3_cost, new_cost);
594 fprintf (dump_file, "replacement cost %d\n", new_cost);
600 /* Update the uid_insn_cost array with the replacement costs. */
601 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
602 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
604 uid_insn_cost[INSN_UID (i1)] = 0;
609 /* Main entry point for combiner. F is the first insn of the function.
610 NREGS is the first unused pseudo-reg number.
612 Return nonzero if the combiner has turned an indirect jump
613 instruction into a direct jump. */
615 combine_instructions (rtx f, unsigned int nregs)
622 rtx links, nextlinks;
624 int new_direct_jump_p = 0;
626 combine_attempts = 0;
629 combine_successes = 0;
631 combine_max_regno = nregs;
633 rtl_hooks = combine_rtl_hooks;
635 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
637 init_recog_no_volatile ();
639 /* Compute maximum uid value so uid_cuid can be allocated. */
641 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
642 if (INSN_UID (insn) > i)
645 uid_cuid = xmalloc ((i + 1) * sizeof (int));
648 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
650 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
651 problems when, for example, we have j <<= 1 in a loop. */
653 nonzero_sign_valid = 0;
655 /* Compute the mapping from uids to cuids.
656 Cuids are numbers assigned to insns, like uids,
657 except that cuids increase monotonically through the code.
659 Scan all SETs and see if we can deduce anything about what
660 bits are known to be zero for some registers and how many copies
661 of the sign bit are known to exist for those registers.
663 Also set any known values so that we can use it while searching
664 for what bits are known to be set. */
668 setup_incoming_promotions ();
670 refresh_blocks = sbitmap_alloc (last_basic_block);
671 sbitmap_zero (refresh_blocks);
673 /* Allocate array of current insn_rtx_costs. */
674 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
675 last_insn_cost = max_uid_cuid;
677 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
679 uid_cuid[INSN_UID (insn)] = ++i;
685 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
687 record_dead_and_set_regs (insn);
690 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
691 if (REG_NOTE_KIND (links) == REG_INC)
692 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
696 /* Record the current insn_rtx_cost of this instruction. */
697 if (NONJUMP_INSN_P (insn))
698 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
700 fprintf(dump_file, "insn_cost %d: %d\n",
701 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
708 nonzero_sign_valid = 1;
710 /* Now scan all the insns in forward order. */
716 setup_incoming_promotions ();
718 FOR_EACH_BB (this_basic_block)
720 for (insn = BB_HEAD (this_basic_block);
721 insn != NEXT_INSN (BB_END (this_basic_block));
722 insn = next ? next : NEXT_INSN (insn))
729 else if (INSN_P (insn))
731 /* See if we know about function return values before this
732 insn based upon SUBREG flags. */
733 check_promoted_subreg (insn, PATTERN (insn));
735 /* Try this insn with each insn it links back to. */
737 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
738 if ((next = try_combine (insn, XEXP (links, 0),
739 NULL_RTX, &new_direct_jump_p)) != 0)
742 /* Try each sequence of three linked insns ending with this one. */
744 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
746 rtx link = XEXP (links, 0);
748 /* If the linked insn has been replaced by a note, then there
749 is no point in pursuing this chain any further. */
753 for (nextlinks = LOG_LINKS (link);
755 nextlinks = XEXP (nextlinks, 1))
756 if ((next = try_combine (insn, link,
758 &new_direct_jump_p)) != 0)
763 /* Try to combine a jump insn that uses CC0
764 with a preceding insn that sets CC0, and maybe with its
765 logical predecessor as well.
766 This is how we make decrement-and-branch insns.
767 We need this special code because data flow connections
768 via CC0 do not get entered in LOG_LINKS. */
771 && (prev = prev_nonnote_insn (insn)) != 0
772 && NONJUMP_INSN_P (prev)
773 && sets_cc0_p (PATTERN (prev)))
775 if ((next = try_combine (insn, prev,
776 NULL_RTX, &new_direct_jump_p)) != 0)
779 for (nextlinks = LOG_LINKS (prev); nextlinks;
780 nextlinks = XEXP (nextlinks, 1))
781 if ((next = try_combine (insn, prev,
783 &new_direct_jump_p)) != 0)
787 /* Do the same for an insn that explicitly references CC0. */
788 if (NONJUMP_INSN_P (insn)
789 && (prev = prev_nonnote_insn (insn)) != 0
790 && NONJUMP_INSN_P (prev)
791 && sets_cc0_p (PATTERN (prev))
792 && GET_CODE (PATTERN (insn)) == SET
793 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
795 if ((next = try_combine (insn, prev,
796 NULL_RTX, &new_direct_jump_p)) != 0)
799 for (nextlinks = LOG_LINKS (prev); nextlinks;
800 nextlinks = XEXP (nextlinks, 1))
801 if ((next = try_combine (insn, prev,
803 &new_direct_jump_p)) != 0)
807 /* Finally, see if any of the insns that this insn links to
808 explicitly references CC0. If so, try this insn, that insn,
809 and its predecessor if it sets CC0. */
810 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
811 if (NONJUMP_INSN_P (XEXP (links, 0))
812 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
813 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
814 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
815 && NONJUMP_INSN_P (prev)
816 && sets_cc0_p (PATTERN (prev))
817 && (next = try_combine (insn, XEXP (links, 0),
818 prev, &new_direct_jump_p)) != 0)
822 /* Try combining an insn with two different insns whose results it
824 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
825 for (nextlinks = XEXP (links, 1); nextlinks;
826 nextlinks = XEXP (nextlinks, 1))
827 if ((next = try_combine (insn, XEXP (links, 0),
829 &new_direct_jump_p)) != 0)
832 /* Try this insn with each REG_EQUAL note it links back to. */
833 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
836 rtx temp = XEXP (links, 0);
837 if ((set = single_set (temp)) != 0
838 && (note = find_reg_equal_equiv_note (temp)) != 0
839 && GET_CODE (XEXP (note, 0)) != EXPR_LIST
840 /* Avoid using a register that may already been marked
841 dead by an earlier instruction. */
842 && ! unmentioned_reg_p (XEXP (note, 0), SET_SRC (set)))
844 /* Temporarily replace the set's source with the
845 contents of the REG_EQUAL note. The insn will
846 be deleted or recognized by try_combine. */
847 rtx orig = SET_SRC (set);
848 SET_SRC (set) = XEXP (note, 0);
849 next = try_combine (insn, temp, NULL_RTX,
853 SET_SRC (set) = orig;
858 record_dead_and_set_regs (insn);
867 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, i,
868 BASIC_BLOCK (i)->flags |= BB_DIRTY);
869 new_direct_jump_p |= purge_all_dead_edges (0);
870 delete_noop_moves ();
872 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
873 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
874 | PROP_KILL_DEAD_CODE);
877 sbitmap_free (refresh_blocks);
878 free (uid_insn_cost);
883 struct undo *undo, *next;
884 for (undo = undobuf.frees; undo; undo = next)
892 total_attempts += combine_attempts;
893 total_merges += combine_merges;
894 total_extras += combine_extras;
895 total_successes += combine_successes;
897 nonzero_sign_valid = 0;
898 rtl_hooks = general_rtl_hooks;
900 /* Make recognizer allow volatile MEMs again. */
903 return new_direct_jump_p;
906 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
912 for (i = 0; i < combine_max_regno; i++)
913 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
916 /* Set up any promoted values for incoming argument registers. */
919 setup_incoming_promotions (void)
923 enum machine_mode mode;
925 rtx first = get_insns ();
927 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
929 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
930 /* Check whether this register can hold an incoming pointer
931 argument. FUNCTION_ARG_REGNO_P tests outgoing register
932 numbers, so translate if necessary due to register windows. */
933 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
934 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
937 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
940 gen_rtx_CLOBBER (mode, const0_rtx)));
945 /* Called via note_stores. If X is a pseudo that is narrower than
946 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
948 If we are setting only a portion of X and we can't figure out what
949 portion, assume all bits will be used since we don't know what will
952 Similarly, set how many bits of X are known to be copies of the sign bit
953 at all locations in the function. This is the smallest number implied
957 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
958 void *data ATTRIBUTE_UNUSED)
963 && REGNO (x) >= FIRST_PSEUDO_REGISTER
964 /* If this register is undefined at the start of the file, we can't
965 say what its contents were. */
966 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, REGNO (x))
967 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
969 if (set == 0 || GET_CODE (set) == CLOBBER)
971 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
972 reg_stat[REGNO (x)].sign_bit_copies = 1;
976 /* If this is a complex assignment, see if we can convert it into a
977 simple assignment. */
978 set = expand_field_assignment (set);
980 /* If this is a simple assignment, or we have a paradoxical SUBREG,
981 set what we know about X. */
983 if (SET_DEST (set) == x
984 || (GET_CODE (SET_DEST (set)) == SUBREG
985 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
986 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
987 && SUBREG_REG (SET_DEST (set)) == x))
989 rtx src = SET_SRC (set);
991 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
992 /* If X is narrower than a word and SRC is a non-negative
993 constant that would appear negative in the mode of X,
994 sign-extend it for use in reg_stat[].nonzero_bits because some
995 machines (maybe most) will actually do the sign-extension
996 and this is the conservative approach.
998 ??? For 2.5, try to tighten up the MD files in this regard
999 instead of this kludge. */
1001 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1002 && GET_CODE (src) == CONST_INT
1004 && 0 != (INTVAL (src)
1005 & ((HOST_WIDE_INT) 1
1006 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1007 src = GEN_INT (INTVAL (src)
1008 | ((HOST_WIDE_INT) (-1)
1009 << GET_MODE_BITSIZE (GET_MODE (x))));
1012 /* Don't call nonzero_bits if it cannot change anything. */
1013 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1014 reg_stat[REGNO (x)].nonzero_bits
1015 |= nonzero_bits (src, nonzero_bits_mode);
1016 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1017 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1018 || reg_stat[REGNO (x)].sign_bit_copies > num)
1019 reg_stat[REGNO (x)].sign_bit_copies = num;
1023 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1024 reg_stat[REGNO (x)].sign_bit_copies = 1;
1029 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1030 insns that were previously combined into I3 or that will be combined
1031 into the merger of INSN and I3.
1033 Return 0 if the combination is not allowed for any reason.
1035 If the combination is allowed, *PDEST will be set to the single
1036 destination of INSN and *PSRC to the single source, and this function
1040 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1041 rtx *pdest, rtx *psrc)
1044 rtx set = 0, src, dest;
1049 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1050 && next_active_insn (succ) == i3)
1051 : next_active_insn (insn) == i3);
1053 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1054 or a PARALLEL consisting of such a SET and CLOBBERs.
1056 If INSN has CLOBBER parallel parts, ignore them for our processing.
1057 By definition, these happen during the execution of the insn. When it
1058 is merged with another insn, all bets are off. If they are, in fact,
1059 needed and aren't also supplied in I3, they may be added by
1060 recog_for_combine. Otherwise, it won't match.
1062 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1065 Get the source and destination of INSN. If more than one, can't
1068 if (GET_CODE (PATTERN (insn)) == SET)
1069 set = PATTERN (insn);
1070 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1071 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1073 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1075 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1078 switch (GET_CODE (elt))
1080 /* This is important to combine floating point insns
1081 for the SH4 port. */
1083 /* Combining an isolated USE doesn't make sense.
1084 We depend here on combinable_i3pat to reject them. */
1085 /* The code below this loop only verifies that the inputs of
1086 the SET in INSN do not change. We call reg_set_between_p
1087 to verify that the REG in the USE does not change between
1089 If the USE in INSN was for a pseudo register, the matching
1090 insn pattern will likely match any register; combining this
1091 with any other USE would only be safe if we knew that the
1092 used registers have identical values, or if there was
1093 something to tell them apart, e.g. different modes. For
1094 now, we forgo such complicated tests and simply disallow
1095 combining of USES of pseudo registers with any other USE. */
1096 if (REG_P (XEXP (elt, 0))
1097 && GET_CODE (PATTERN (i3)) == PARALLEL)
1099 rtx i3pat = PATTERN (i3);
1100 int i = XVECLEN (i3pat, 0) - 1;
1101 unsigned int regno = REGNO (XEXP (elt, 0));
1105 rtx i3elt = XVECEXP (i3pat, 0, i);
1107 if (GET_CODE (i3elt) == USE
1108 && REG_P (XEXP (i3elt, 0))
1109 && (REGNO (XEXP (i3elt, 0)) == regno
1110 ? reg_set_between_p (XEXP (elt, 0),
1111 PREV_INSN (insn), i3)
1112 : regno >= FIRST_PSEUDO_REGISTER))
1119 /* We can ignore CLOBBERs. */
1124 /* Ignore SETs whose result isn't used but not those that
1125 have side-effects. */
1126 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1127 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1128 || INTVAL (XEXP (note, 0)) <= 0)
1129 && ! side_effects_p (elt))
1132 /* If we have already found a SET, this is a second one and
1133 so we cannot combine with this insn. */
1141 /* Anything else means we can't combine. */
1147 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1148 so don't do anything with it. */
1149 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1158 set = expand_field_assignment (set);
1159 src = SET_SRC (set), dest = SET_DEST (set);
1161 /* Don't eliminate a store in the stack pointer. */
1162 if (dest == stack_pointer_rtx
1163 /* Don't combine with an insn that sets a register to itself if it has
1164 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1165 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1166 /* Can't merge an ASM_OPERANDS. */
1167 || GET_CODE (src) == ASM_OPERANDS
1168 /* Can't merge a function call. */
1169 || GET_CODE (src) == CALL
1170 /* Don't eliminate a function call argument. */
1172 && (find_reg_fusage (i3, USE, dest)
1174 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1175 && global_regs[REGNO (dest)])))
1176 /* Don't substitute into an incremented register. */
1177 || FIND_REG_INC_NOTE (i3, dest)
1178 || (succ && FIND_REG_INC_NOTE (succ, dest))
1180 /* Don't combine the end of a libcall into anything. */
1181 /* ??? This gives worse code, and appears to be unnecessary, since no
1182 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1183 use REG_RETVAL notes for noconflict blocks, but other code here
1184 makes sure that those insns don't disappear. */
1185 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1187 /* Make sure that DEST is not used after SUCC but before I3. */
1188 || (succ && ! all_adjacent
1189 && reg_used_between_p (dest, succ, i3))
1190 /* Make sure that the value that is to be substituted for the register
1191 does not use any registers whose values alter in between. However,
1192 If the insns are adjacent, a use can't cross a set even though we
1193 think it might (this can happen for a sequence of insns each setting
1194 the same destination; last_set of that register might point to
1195 a NOTE). If INSN has a REG_EQUIV note, the register is always
1196 equivalent to the memory so the substitution is valid even if there
1197 are intervening stores. Also, don't move a volatile asm or
1198 UNSPEC_VOLATILE across any other insns. */
1201 || ! find_reg_note (insn, REG_EQUIV, src))
1202 && use_crosses_set_p (src, INSN_CUID (insn)))
1203 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1204 || GET_CODE (src) == UNSPEC_VOLATILE))
1205 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1206 better register allocation by not doing the combine. */
1207 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1208 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1209 /* Don't combine across a CALL_INSN, because that would possibly
1210 change whether the life span of some REGs crosses calls or not,
1211 and it is a pain to update that information.
1212 Exception: if source is a constant, moving it later can't hurt.
1213 Accept that special case, because it helps -fforce-addr a lot. */
1214 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1217 /* DEST must either be a REG or CC0. */
1220 /* If register alignment is being enforced for multi-word items in all
1221 cases except for parameters, it is possible to have a register copy
1222 insn referencing a hard register that is not allowed to contain the
1223 mode being copied and which would not be valid as an operand of most
1224 insns. Eliminate this problem by not combining with such an insn.
1226 Also, on some machines we don't want to extend the life of a hard
1230 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1231 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1232 /* Don't extend the life of a hard register unless it is
1233 user variable (if we have few registers) or it can't
1234 fit into the desired register (meaning something special
1236 Also avoid substituting a return register into I3, because
1237 reload can't handle a conflict with constraints of other
1239 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1240 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1243 else if (GET_CODE (dest) != CC0)
1247 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1248 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1249 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1251 /* Don't substitute for a register intended as a clobberable
1253 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1254 if (rtx_equal_p (reg, dest))
1257 /* If the clobber represents an earlyclobber operand, we must not
1258 substitute an expression containing the clobbered register.
1259 As we do not analyse the constraint strings here, we have to
1260 make the conservative assumption. However, if the register is
1261 a fixed hard reg, the clobber cannot represent any operand;
1262 we leave it up to the machine description to either accept or
1263 reject use-and-clobber patterns. */
1265 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1266 || !fixed_regs[REGNO (reg)])
1267 if (reg_overlap_mentioned_p (reg, src))
1271 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1272 or not), reject, unless nothing volatile comes between it and I3 */
1274 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1276 /* Make sure succ doesn't contain a volatile reference. */
1277 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1280 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1281 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1285 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1286 to be an explicit register variable, and was chosen for a reason. */
1288 if (GET_CODE (src) == ASM_OPERANDS
1289 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1292 /* If there are any volatile insns between INSN and I3, reject, because
1293 they might affect machine state. */
1295 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1296 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1299 /* If INSN or I2 contains an autoincrement or autodecrement,
1300 make sure that register is not used between there and I3,
1301 and not already used in I3 either.
1302 Also insist that I3 not be a jump; if it were one
1303 and the incremented register were spilled, we would lose. */
1306 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1307 if (REG_NOTE_KIND (link) == REG_INC
1309 || reg_used_between_p (XEXP (link, 0), insn, i3)
1310 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1315 /* Don't combine an insn that follows a CC0-setting insn.
1316 An insn that uses CC0 must not be separated from the one that sets it.
1317 We do, however, allow I2 to follow a CC0-setting insn if that insn
1318 is passed as I1; in that case it will be deleted also.
1319 We also allow combining in this case if all the insns are adjacent
1320 because that would leave the two CC0 insns adjacent as well.
1321 It would be more logical to test whether CC0 occurs inside I1 or I2,
1322 but that would be much slower, and this ought to be equivalent. */
1324 p = prev_nonnote_insn (insn);
1325 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1330 /* If we get here, we have passed all the tests and the combination is
1339 /* LOC is the location within I3 that contains its pattern or the component
1340 of a PARALLEL of the pattern. We validate that it is valid for combining.
1342 One problem is if I3 modifies its output, as opposed to replacing it
1343 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1344 so would produce an insn that is not equivalent to the original insns.
1348 (set (reg:DI 101) (reg:DI 100))
1349 (set (subreg:SI (reg:DI 101) 0) <foo>)
1351 This is NOT equivalent to:
1353 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1354 (set (reg:DI 101) (reg:DI 100))])
1356 Not only does this modify 100 (in which case it might still be valid
1357 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1359 We can also run into a problem if I2 sets a register that I1
1360 uses and I1 gets directly substituted into I3 (not via I2). In that
1361 case, we would be getting the wrong value of I2DEST into I3, so we
1362 must reject the combination. This case occurs when I2 and I1 both
1363 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1364 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1365 of a SET must prevent combination from occurring.
1367 Before doing the above check, we first try to expand a field assignment
1368 into a set of logical operations.
1370 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1371 we place a register that is both set and used within I3. If more than one
1372 such register is detected, we fail.
1374 Return 1 if the combination is valid, zero otherwise. */
1377 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1378 int i1_not_in_src, rtx *pi3dest_killed)
1382 if (GET_CODE (x) == SET)
1385 rtx dest = SET_DEST (set);
1386 rtx src = SET_SRC (set);
1387 rtx inner_dest = dest;
1389 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1390 || GET_CODE (inner_dest) == SUBREG
1391 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1392 inner_dest = XEXP (inner_dest, 0);
1394 /* Check for the case where I3 modifies its output, as discussed
1395 above. We don't want to prevent pseudos from being combined
1396 into the address of a MEM, so only prevent the combination if
1397 i1 or i2 set the same MEM. */
1398 if ((inner_dest != dest &&
1399 (!MEM_P (inner_dest)
1400 || rtx_equal_p (i2dest, inner_dest)
1401 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1402 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1403 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1405 /* This is the same test done in can_combine_p except we can't test
1406 all_adjacent; we don't have to, since this instruction will stay
1407 in place, thus we are not considering increasing the lifetime of
1410 Also, if this insn sets a function argument, combining it with
1411 something that might need a spill could clobber a previous
1412 function argument; the all_adjacent test in can_combine_p also
1413 checks this; here, we do a more specific test for this case. */
1415 || (REG_P (inner_dest)
1416 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1417 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1418 GET_MODE (inner_dest))))
1419 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1422 /* If DEST is used in I3, it is being killed in this insn,
1423 so record that for later.
1424 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1425 STACK_POINTER_REGNUM, since these are always considered to be
1426 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1427 if (pi3dest_killed && REG_P (dest)
1428 && reg_referenced_p (dest, PATTERN (i3))
1429 && REGNO (dest) != FRAME_POINTER_REGNUM
1430 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1431 && REGNO (dest) != HARD_FRAME_POINTER_REGNUM
1433 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1434 && (REGNO (dest) != ARG_POINTER_REGNUM
1435 || ! fixed_regs [REGNO (dest)])
1437 && REGNO (dest) != STACK_POINTER_REGNUM)
1439 if (*pi3dest_killed)
1442 *pi3dest_killed = dest;
1446 else if (GET_CODE (x) == PARALLEL)
1450 for (i = 0; i < XVECLEN (x, 0); i++)
1451 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1452 i1_not_in_src, pi3dest_killed))
1459 /* Return 1 if X is an arithmetic expression that contains a multiplication
1460 and division. We don't count multiplications by powers of two here. */
1463 contains_muldiv (rtx x)
1465 switch (GET_CODE (x))
1467 case MOD: case DIV: case UMOD: case UDIV:
1471 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1472 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1475 return contains_muldiv (XEXP (x, 0))
1476 || contains_muldiv (XEXP (x, 1));
1479 return contains_muldiv (XEXP (x, 0));
1485 /* Determine whether INSN can be used in a combination. Return nonzero if
1486 not. This is used in try_combine to detect early some cases where we
1487 can't perform combinations. */
1490 cant_combine_insn_p (rtx insn)
1495 /* If this isn't really an insn, we can't do anything.
1496 This can occur when flow deletes an insn that it has merged into an
1497 auto-increment address. */
1498 if (! INSN_P (insn))
1501 /* Never combine loads and stores involving hard regs that are likely
1502 to be spilled. The register allocator can usually handle such
1503 reg-reg moves by tying. If we allow the combiner to make
1504 substitutions of likely-spilled regs, we may abort in reload.
1505 As an exception, we allow combinations involving fixed regs; these are
1506 not available to the register allocator so there's no risk involved. */
1508 set = single_set (insn);
1511 src = SET_SRC (set);
1512 dest = SET_DEST (set);
1513 if (GET_CODE (src) == SUBREG)
1514 src = SUBREG_REG (src);
1515 if (GET_CODE (dest) == SUBREG)
1516 dest = SUBREG_REG (dest);
1517 if (REG_P (src) && REG_P (dest)
1518 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1519 && ! fixed_regs[REGNO (src)]
1520 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1521 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1522 && ! fixed_regs[REGNO (dest)]
1523 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1529 /* Adjust INSN after we made a change to its destination.
1531 Changing the destination can invalidate notes that say something about
1532 the results of the insn and a LOG_LINK pointing to the insn. */
1535 adjust_for_new_dest (rtx insn)
1539 /* For notes, be conservative and simply remove them. */
1540 loc = ®_NOTES (insn);
1543 enum reg_note kind = REG_NOTE_KIND (*loc);
1544 if (kind == REG_EQUAL || kind == REG_EQUIV)
1545 *loc = XEXP (*loc, 1);
1547 loc = &XEXP (*loc, 1);
1550 /* The new insn will have a destination that was previously the destination
1551 of an insn just above it. Call distribute_links to make a LOG_LINK from
1552 the next use of that destination. */
1553 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1556 /* Try to combine the insns I1 and I2 into I3.
1557 Here I1 and I2 appear earlier than I3.
1558 I1 can be zero; then we combine just I2 into I3.
1560 If we are combining three insns and the resulting insn is not recognized,
1561 try splitting it into two insns. If that happens, I2 and I3 are retained
1562 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1565 Return 0 if the combination does not work. Then nothing is changed.
1566 If we did the combination, return the insn at which combine should
1569 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1570 new direct jump instruction. */
1573 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1575 /* New patterns for I3 and I2, respectively. */
1576 rtx newpat, newi2pat = 0;
1577 int substed_i2 = 0, substed_i1 = 0;
1578 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1579 int added_sets_1, added_sets_2;
1580 /* Total number of SETs to put into I3. */
1582 /* Nonzero if I2's body now appears in I3. */
1584 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1585 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1586 /* Contains I3 if the destination of I3 is used in its source, which means
1587 that the old life of I3 is being killed. If that usage is placed into
1588 I2 and not in I3, a REG_DEAD note must be made. */
1589 rtx i3dest_killed = 0;
1590 /* SET_DEST and SET_SRC of I2 and I1. */
1591 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1592 /* PATTERN (I2), or a copy of it in certain cases. */
1594 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1595 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1596 int i1_feeds_i3 = 0;
1597 /* Notes that must be added to REG_NOTES in I3 and I2. */
1598 rtx new_i3_notes, new_i2_notes;
1599 /* Notes that we substituted I3 into I2 instead of the normal case. */
1600 int i3_subst_into_i2 = 0;
1601 /* Notes that I1, I2 or I3 is a MULT operation. */
1610 /* Exit early if one of the insns involved can't be used for
1612 if (cant_combine_insn_p (i3)
1613 || cant_combine_insn_p (i2)
1614 || (i1 && cant_combine_insn_p (i1))
1615 /* We also can't do anything if I3 has a
1616 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1619 /* ??? This gives worse code, and appears to be unnecessary, since no
1620 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1621 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1627 undobuf.other_insn = 0;
1629 /* Reset the hard register usage information. */
1630 CLEAR_HARD_REG_SET (newpat_used_regs);
1632 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1633 code below, set I1 to be the earlier of the two insns. */
1634 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1635 temp = i1, i1 = i2, i2 = temp;
1637 added_links_insn = 0;
1639 /* First check for one important special-case that the code below will
1640 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1641 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1642 we may be able to replace that destination with the destination of I3.
1643 This occurs in the common code where we compute both a quotient and
1644 remainder into a structure, in which case we want to do the computation
1645 directly into the structure to avoid register-register copies.
1647 Note that this case handles both multiple sets in I2 and also
1648 cases where I2 has a number of CLOBBER or PARALLELs.
1650 We make very conservative checks below and only try to handle the
1651 most common cases of this. For example, we only handle the case
1652 where I2 and I3 are adjacent to avoid making difficult register
1655 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1656 && REG_P (SET_SRC (PATTERN (i3)))
1657 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1658 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1659 && GET_CODE (PATTERN (i2)) == PARALLEL
1660 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1661 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1662 below would need to check what is inside (and reg_overlap_mentioned_p
1663 doesn't support those codes anyway). Don't allow those destinations;
1664 the resulting insn isn't likely to be recognized anyway. */
1665 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1666 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1667 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1668 SET_DEST (PATTERN (i3)))
1669 && next_real_insn (i2) == i3)
1671 rtx p2 = PATTERN (i2);
1673 /* Make sure that the destination of I3,
1674 which we are going to substitute into one output of I2,
1675 is not used within another output of I2. We must avoid making this:
1676 (parallel [(set (mem (reg 69)) ...)
1677 (set (reg 69) ...)])
1678 which is not well-defined as to order of actions.
1679 (Besides, reload can't handle output reloads for this.)
1681 The problem can also happen if the dest of I3 is a memory ref,
1682 if another dest in I2 is an indirect memory ref. */
1683 for (i = 0; i < XVECLEN (p2, 0); i++)
1684 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1685 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1686 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1687 SET_DEST (XVECEXP (p2, 0, i))))
1690 if (i == XVECLEN (p2, 0))
1691 for (i = 0; i < XVECLEN (p2, 0); i++)
1692 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1693 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1694 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1699 subst_low_cuid = INSN_CUID (i2);
1701 added_sets_2 = added_sets_1 = 0;
1702 i2dest = SET_SRC (PATTERN (i3));
1704 /* Replace the dest in I2 with our dest and make the resulting
1705 insn the new pattern for I3. Then skip to where we
1706 validate the pattern. Everything was set up above. */
1707 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1708 SET_DEST (PATTERN (i3)));
1711 i3_subst_into_i2 = 1;
1712 goto validate_replacement;
1716 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1717 one of those words to another constant, merge them by making a new
1720 && (temp = single_set (i2)) != 0
1721 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1722 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1723 && REG_P (SET_DEST (temp))
1724 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1725 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1726 && GET_CODE (PATTERN (i3)) == SET
1727 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1728 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1729 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1730 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1731 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1733 HOST_WIDE_INT lo, hi;
1735 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1736 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1739 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1740 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1743 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1745 /* We don't handle the case of the target word being wider
1746 than a host wide int. */
1747 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1749 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1750 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1751 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1753 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1754 hi = INTVAL (SET_SRC (PATTERN (i3)));
1755 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1757 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1758 >> (HOST_BITS_PER_WIDE_INT - 1));
1760 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1761 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1762 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1763 (INTVAL (SET_SRC (PATTERN (i3)))));
1765 hi = lo < 0 ? -1 : 0;
1768 /* We don't handle the case of the higher word not fitting
1769 entirely in either hi or lo. */
1774 subst_low_cuid = INSN_CUID (i2);
1775 added_sets_2 = added_sets_1 = 0;
1776 i2dest = SET_DEST (temp);
1778 SUBST (SET_SRC (temp),
1779 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1781 newpat = PATTERN (i2);
1782 goto validate_replacement;
1786 /* If we have no I1 and I2 looks like:
1787 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1789 make up a dummy I1 that is
1792 (set (reg:CC X) (compare:CC Y (const_int 0)))
1794 (We can ignore any trailing CLOBBERs.)
1796 This undoes a previous combination and allows us to match a branch-and-
1799 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1800 && XVECLEN (PATTERN (i2), 0) >= 2
1801 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1802 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1804 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1805 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1806 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1807 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1808 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1809 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1811 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1812 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1817 /* We make I1 with the same INSN_UID as I2. This gives it
1818 the same INSN_CUID for value tracking. Our fake I1 will
1819 never appear in the insn stream so giving it the same INSN_UID
1820 as I2 will not cause a problem. */
1822 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1823 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1824 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1827 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1828 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1829 SET_DEST (PATTERN (i1)));
1834 /* Verify that I2 and I1 are valid for combining. */
1835 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1836 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1842 /* Record whether I2DEST is used in I2SRC and similarly for the other
1843 cases. Knowing this will help in register status updating below. */
1844 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
1845 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
1846 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
1848 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1850 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
1852 /* Ensure that I3's pattern can be the destination of combines. */
1853 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
1854 i1 && i2dest_in_i1src && i1_feeds_i3,
1861 /* See if any of the insns is a MULT operation. Unless one is, we will
1862 reject a combination that is, since it must be slower. Be conservative
1864 if (GET_CODE (i2src) == MULT
1865 || (i1 != 0 && GET_CODE (i1src) == MULT)
1866 || (GET_CODE (PATTERN (i3)) == SET
1867 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
1870 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1871 We used to do this EXCEPT in one case: I3 has a post-inc in an
1872 output operand. However, that exception can give rise to insns like
1874 which is a famous insn on the PDP-11 where the value of r3 used as the
1875 source was model-dependent. Avoid this sort of thing. */
1878 if (!(GET_CODE (PATTERN (i3)) == SET
1879 && REG_P (SET_SRC (PATTERN (i3)))
1880 && MEM_P (SET_DEST (PATTERN (i3)))
1881 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
1882 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
1883 /* It's not the exception. */
1886 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
1887 if (REG_NOTE_KIND (link) == REG_INC
1888 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
1890 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
1897 /* See if the SETs in I1 or I2 need to be kept around in the merged
1898 instruction: whenever the value set there is still needed past I3.
1899 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1901 For the SET in I1, we have two cases: If I1 and I2 independently
1902 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1903 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1904 in I1 needs to be kept around unless I1DEST dies or is set in either
1905 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1906 I1DEST. If so, we know I1 feeds into I2. */
1908 added_sets_2 = ! dead_or_set_p (i3, i2dest);
1911 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
1912 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
1914 /* If the set in I2 needs to be kept around, we must make a copy of
1915 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1916 PATTERN (I2), we are only substituting for the original I1DEST, not into
1917 an already-substituted copy. This also prevents making self-referential
1918 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1921 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
1922 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
1926 i2pat = copy_rtx (i2pat);
1930 /* Substitute in the latest insn for the regs set by the earlier ones. */
1932 maxreg = max_reg_num ();
1936 /* It is possible that the source of I2 or I1 may be performing an
1937 unneeded operation, such as a ZERO_EXTEND of something that is known
1938 to have the high part zero. Handle that case by letting subst look at
1939 the innermost one of them.
1941 Another way to do this would be to have a function that tries to
1942 simplify a single insn instead of merging two or more insns. We don't
1943 do this because of the potential of infinite loops and because
1944 of the potential extra memory required. However, doing it the way
1945 we are is a bit of a kludge and doesn't catch all cases.
1947 But only do this if -fexpensive-optimizations since it slows things down
1948 and doesn't usually win. */
1950 if (flag_expensive_optimizations)
1952 /* Pass pc_rtx so no substitutions are done, just simplifications. */
1955 subst_low_cuid = INSN_CUID (i1);
1956 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
1960 subst_low_cuid = INSN_CUID (i2);
1961 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
1966 /* Many machines that don't use CC0 have insns that can both perform an
1967 arithmetic operation and set the condition code. These operations will
1968 be represented as a PARALLEL with the first element of the vector
1969 being a COMPARE of an arithmetic operation with the constant zero.
1970 The second element of the vector will set some pseudo to the result
1971 of the same arithmetic operation. If we simplify the COMPARE, we won't
1972 match such a pattern and so will generate an extra insn. Here we test
1973 for this case, where both the comparison and the operation result are
1974 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1975 I2SRC. Later we will make the PARALLEL that contains I2. */
1977 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
1978 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
1979 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
1980 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
1982 #ifdef SELECT_CC_MODE
1984 enum machine_mode compare_mode;
1987 newpat = PATTERN (i3);
1988 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
1992 #ifdef SELECT_CC_MODE
1993 /* See if a COMPARE with the operand we substituted in should be done
1994 with the mode that is currently being used. If not, do the same
1995 processing we do in `subst' for a SET; namely, if the destination
1996 is used only once, try to replace it with a register of the proper
1997 mode and also replace the COMPARE. */
1998 if (undobuf.other_insn == 0
1999 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2000 &undobuf.other_insn))
2001 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2003 != GET_MODE (SET_DEST (newpat))))
2005 unsigned int regno = REGNO (SET_DEST (newpat));
2006 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2008 if (regno < FIRST_PSEUDO_REGISTER
2009 || (REG_N_SETS (regno) == 1 && ! added_sets_2
2010 && ! REG_USERVAR_P (SET_DEST (newpat))))
2012 if (regno >= FIRST_PSEUDO_REGISTER)
2013 SUBST (regno_reg_rtx[regno], new_dest);
2015 SUBST (SET_DEST (newpat), new_dest);
2016 SUBST (XEXP (*cc_use, 0), new_dest);
2017 SUBST (SET_SRC (newpat),
2018 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2021 undobuf.other_insn = 0;
2028 n_occurrences = 0; /* `subst' counts here */
2030 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2031 need to make a unique copy of I2SRC each time we substitute it
2032 to avoid self-referential rtl. */
2034 subst_low_cuid = INSN_CUID (i2);
2035 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2036 ! i1_feeds_i3 && i1dest_in_i1src);
2039 /* Record whether i2's body now appears within i3's body. */
2040 i2_is_used = n_occurrences;
2043 /* If we already got a failure, don't try to do more. Otherwise,
2044 try to substitute in I1 if we have it. */
2046 if (i1 && GET_CODE (newpat) != CLOBBER)
2048 /* Before we can do this substitution, we must redo the test done
2049 above (see detailed comments there) that ensures that I1DEST
2050 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2052 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2060 subst_low_cuid = INSN_CUID (i1);
2061 newpat = subst (newpat, i1dest, i1src, 0, 0);
2065 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2066 to count all the ways that I2SRC and I1SRC can be used. */
2067 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2068 && i2_is_used + added_sets_2 > 1)
2069 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2070 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2072 /* Fail if we tried to make a new register (we used to abort, but there's
2073 really no reason to). */
2074 || max_reg_num () != maxreg
2075 /* Fail if we couldn't do something and have a CLOBBER. */
2076 || GET_CODE (newpat) == CLOBBER
2077 /* Fail if this new pattern is a MULT and we didn't have one before
2078 at the outer level. */
2079 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2086 /* If the actions of the earlier insns must be kept
2087 in addition to substituting them into the latest one,
2088 we must make a new PARALLEL for the latest insn
2089 to hold additional the SETs. */
2091 if (added_sets_1 || added_sets_2)
2095 if (GET_CODE (newpat) == PARALLEL)
2097 rtvec old = XVEC (newpat, 0);
2098 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2099 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2100 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2101 sizeof (old->elem[0]) * old->num_elem);
2106 total_sets = 1 + added_sets_1 + added_sets_2;
2107 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2108 XVECEXP (newpat, 0, 0) = old;
2112 XVECEXP (newpat, 0, --total_sets)
2113 = (GET_CODE (PATTERN (i1)) == PARALLEL
2114 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2118 /* If there is no I1, use I2's body as is. We used to also not do
2119 the subst call below if I2 was substituted into I3,
2120 but that could lose a simplification. */
2122 XVECEXP (newpat, 0, --total_sets) = i2pat;
2124 /* See comment where i2pat is assigned. */
2125 XVECEXP (newpat, 0, --total_sets)
2126 = subst (i2pat, i1dest, i1src, 0, 0);
2130 /* We come here when we are replacing a destination in I2 with the
2131 destination of I3. */
2132 validate_replacement:
2134 /* Note which hard regs this insn has as inputs. */
2135 mark_used_regs_combine (newpat);
2137 /* Is the result of combination a valid instruction? */
2138 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2140 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2141 the second SET's destination is a register that is unused and isn't
2142 marked as an instruction that might trap in an EH region. In that case,
2143 we just need the first SET. This can occur when simplifying a divmod
2144 insn. We *must* test for this case here because the code below that
2145 splits two independent SETs doesn't handle this case correctly when it
2146 updates the register status.
2148 It's pointless doing this if we originally had two sets, one from
2149 i3, and one from i2. Combining then splitting the parallel results
2150 in the original i2 again plus an invalid insn (which we delete).
2151 The net effect is only to move instructions around, which makes
2152 debug info less accurate.
2154 Also check the case where the first SET's destination is unused.
2155 That would not cause incorrect code, but does cause an unneeded
2158 if (insn_code_number < 0
2159 && !(added_sets_2 && i1 == 0)
2160 && GET_CODE (newpat) == PARALLEL
2161 && XVECLEN (newpat, 0) == 2
2162 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2163 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2164 && asm_noperands (newpat) < 0)
2166 rtx set0 = XVECEXP (newpat, 0, 0);
2167 rtx set1 = XVECEXP (newpat, 0, 1);
2170 if (((REG_P (SET_DEST (set1))
2171 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2172 || (GET_CODE (SET_DEST (set1)) == SUBREG
2173 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2174 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2175 || INTVAL (XEXP (note, 0)) <= 0)
2176 && ! side_effects_p (SET_SRC (set1)))
2179 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2182 else if (((REG_P (SET_DEST (set0))
2183 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2184 || (GET_CODE (SET_DEST (set0)) == SUBREG
2185 && find_reg_note (i3, REG_UNUSED,
2186 SUBREG_REG (SET_DEST (set0)))))
2187 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2188 || INTVAL (XEXP (note, 0)) <= 0)
2189 && ! side_effects_p (SET_SRC (set0)))
2192 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2194 if (insn_code_number >= 0)
2196 /* If we will be able to accept this, we have made a
2197 change to the destination of I3. This requires us to
2198 do a few adjustments. */
2200 PATTERN (i3) = newpat;
2201 adjust_for_new_dest (i3);
2206 /* If we were combining three insns and the result is a simple SET
2207 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2208 insns. There are two ways to do this. It can be split using a
2209 machine-specific method (like when you have an addition of a large
2210 constant) or by combine in the function find_split_point. */
2212 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2213 && asm_noperands (newpat) < 0)
2215 rtx m_split, *split;
2216 rtx ni2dest = i2dest;
2218 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2219 use I2DEST as a scratch register will help. In the latter case,
2220 convert I2DEST to the mode of the source of NEWPAT if we can. */
2222 m_split = split_insns (newpat, i3);
2224 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2225 inputs of NEWPAT. */
2227 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2228 possible to try that as a scratch reg. This would require adding
2229 more code to make it work though. */
2231 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2233 /* If I2DEST is a hard register or the only use of a pseudo,
2234 we can change its mode. */
2235 if (GET_MODE (SET_DEST (newpat)) != GET_MODE (i2dest)
2236 && GET_MODE (SET_DEST (newpat)) != VOIDmode
2238 && (REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2239 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2240 && ! REG_USERVAR_P (i2dest))))
2241 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2244 m_split = split_insns (gen_rtx_PARALLEL
2246 gen_rtvec (2, newpat,
2247 gen_rtx_CLOBBER (VOIDmode,
2250 /* If the split with the mode-changed register didn't work, try
2251 the original register. */
2252 if (! m_split && ni2dest != i2dest)
2255 m_split = split_insns (gen_rtx_PARALLEL
2257 gen_rtvec (2, newpat,
2258 gen_rtx_CLOBBER (VOIDmode,
2264 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2266 m_split = PATTERN (m_split);
2267 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2268 if (insn_code_number >= 0)
2271 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2272 && (next_real_insn (i2) == i3
2273 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2276 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2277 newi2pat = PATTERN (m_split);
2279 i3set = single_set (NEXT_INSN (m_split));
2280 i2set = single_set (m_split);
2282 /* In case we changed the mode of I2DEST, replace it in the
2283 pseudo-register table here. We can't do it above in case this
2284 code doesn't get executed and we do a split the other way. */
2286 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2287 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2289 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2291 /* If I2 or I3 has multiple SETs, we won't know how to track
2292 register status, so don't use these insns. If I2's destination
2293 is used between I2 and I3, we also can't use these insns. */
2295 if (i2_code_number >= 0 && i2set && i3set
2296 && (next_real_insn (i2) == i3
2297 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2298 insn_code_number = recog_for_combine (&newi3pat, i3,
2300 if (insn_code_number >= 0)
2303 /* It is possible that both insns now set the destination of I3.
2304 If so, we must show an extra use of it. */
2306 if (insn_code_number >= 0)
2308 rtx new_i3_dest = SET_DEST (i3set);
2309 rtx new_i2_dest = SET_DEST (i2set);
2311 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2312 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2313 || GET_CODE (new_i3_dest) == SUBREG)
2314 new_i3_dest = XEXP (new_i3_dest, 0);
2316 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2317 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2318 || GET_CODE (new_i2_dest) == SUBREG)
2319 new_i2_dest = XEXP (new_i2_dest, 0);
2321 if (REG_P (new_i3_dest)
2322 && REG_P (new_i2_dest)
2323 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2324 REG_N_SETS (REGNO (new_i2_dest))++;
2328 /* If we can split it and use I2DEST, go ahead and see if that
2329 helps things be recognized. Verify that none of the registers
2330 are set between I2 and I3. */
2331 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2335 /* We need I2DEST in the proper mode. If it is a hard register
2336 or the only use of a pseudo, we can change its mode. */
2337 && (GET_MODE (*split) == GET_MODE (i2dest)
2338 || GET_MODE (*split) == VOIDmode
2339 || REGNO (i2dest) < FIRST_PSEUDO_REGISTER
2340 || (REG_N_SETS (REGNO (i2dest)) == 1 && ! added_sets_2
2341 && ! REG_USERVAR_P (i2dest)))
2342 && (next_real_insn (i2) == i3
2343 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2344 /* We can't overwrite I2DEST if its value is still used by
2346 && ! reg_referenced_p (i2dest, newpat))
2348 rtx newdest = i2dest;
2349 enum rtx_code split_code = GET_CODE (*split);
2350 enum machine_mode split_mode = GET_MODE (*split);
2352 /* Get NEWDEST as a register in the proper mode. We have already
2353 validated that we can do this. */
2354 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2356 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2358 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2359 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2362 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2363 an ASHIFT. This can occur if it was inside a PLUS and hence
2364 appeared to be a memory address. This is a kludge. */
2365 if (split_code == MULT
2366 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2367 && INTVAL (XEXP (*split, 1)) > 0
2368 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2370 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2371 XEXP (*split, 0), GEN_INT (i)));
2372 /* Update split_code because we may not have a multiply
2374 split_code = GET_CODE (*split);
2377 #ifdef INSN_SCHEDULING
2378 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2379 be written as a ZERO_EXTEND. */
2380 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2382 #ifdef LOAD_EXTEND_OP
2383 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2384 what it really is. */
2385 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2387 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2388 SUBREG_REG (*split)));
2391 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2392 SUBREG_REG (*split)));
2396 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2397 SUBST (*split, newdest);
2398 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2400 /* If the split point was a MULT and we didn't have one before,
2401 don't use one now. */
2402 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2403 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2407 /* Check for a case where we loaded from memory in a narrow mode and
2408 then sign extended it, but we need both registers. In that case,
2409 we have a PARALLEL with both loads from the same memory location.
2410 We can split this into a load from memory followed by a register-register
2411 copy. This saves at least one insn, more if register allocation can
2414 We cannot do this if the destination of the first assignment is a
2415 condition code register or cc0. We eliminate this case by making sure
2416 the SET_DEST and SET_SRC have the same mode.
2418 We cannot do this if the destination of the second assignment is
2419 a register that we have already assumed is zero-extended. Similarly
2420 for a SUBREG of such a register. */
2422 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2423 && GET_CODE (newpat) == PARALLEL
2424 && XVECLEN (newpat, 0) == 2
2425 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2426 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2427 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2428 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2429 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2430 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2431 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2432 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2434 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2435 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2436 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2438 && reg_stat[REGNO (temp)].nonzero_bits != 0
2439 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2440 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2441 && (reg_stat[REGNO (temp)].nonzero_bits
2442 != GET_MODE_MASK (word_mode))))
2443 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2444 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2446 && reg_stat[REGNO (temp)].nonzero_bits != 0
2447 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2448 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2449 && (reg_stat[REGNO (temp)].nonzero_bits
2450 != GET_MODE_MASK (word_mode)))))
2451 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2452 SET_SRC (XVECEXP (newpat, 0, 1)))
2453 && ! find_reg_note (i3, REG_UNUSED,
2454 SET_DEST (XVECEXP (newpat, 0, 0))))
2458 newi2pat = XVECEXP (newpat, 0, 0);
2459 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2460 newpat = XVECEXP (newpat, 0, 1);
2461 SUBST (SET_SRC (newpat),
2462 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2463 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2465 if (i2_code_number >= 0)
2466 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2468 if (insn_code_number >= 0)
2472 /* Similarly, check for a case where we have a PARALLEL of two independent
2473 SETs but we started with three insns. In this case, we can do the sets
2474 as two separate insns. This case occurs when some SET allows two
2475 other insns to combine, but the destination of that SET is still live. */
2477 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2478 && GET_CODE (newpat) == PARALLEL
2479 && XVECLEN (newpat, 0) == 2
2480 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2481 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2482 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2483 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2484 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2485 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2486 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2488 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2489 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2490 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2491 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2492 XVECEXP (newpat, 0, 0))
2493 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2494 XVECEXP (newpat, 0, 1))
2495 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2496 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2498 /* Normally, it doesn't matter which of the two is done first,
2499 but it does if one references cc0. In that case, it has to
2502 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2504 newi2pat = XVECEXP (newpat, 0, 0);
2505 newpat = XVECEXP (newpat, 0, 1);
2510 newi2pat = XVECEXP (newpat, 0, 1);
2511 newpat = XVECEXP (newpat, 0, 0);
2514 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2516 if (i2_code_number >= 0)
2517 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2520 /* If it still isn't recognized, fail and change things back the way they
2522 if ((insn_code_number < 0
2523 /* Is the result a reasonable ASM_OPERANDS? */
2524 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2530 /* If we had to change another insn, make sure it is valid also. */
2531 if (undobuf.other_insn)
2533 rtx other_pat = PATTERN (undobuf.other_insn);
2534 rtx new_other_notes;
2537 CLEAR_HARD_REG_SET (newpat_used_regs);
2539 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2542 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2548 PATTERN (undobuf.other_insn) = other_pat;
2550 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2551 are still valid. Then add any non-duplicate notes added by
2552 recog_for_combine. */
2553 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2555 next = XEXP (note, 1);
2557 if (REG_NOTE_KIND (note) == REG_UNUSED
2558 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2560 if (REG_P (XEXP (note, 0)))
2561 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2563 remove_note (undobuf.other_insn, note);
2567 for (note = new_other_notes; note; note = XEXP (note, 1))
2568 if (REG_P (XEXP (note, 0)))
2569 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2571 distribute_notes (new_other_notes, undobuf.other_insn,
2572 undobuf.other_insn, NULL_RTX);
2575 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2576 they are adjacent to each other or not. */
2578 rtx p = prev_nonnote_insn (i3);
2579 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2580 && sets_cc0_p (newi2pat))
2588 /* Only allow this combination if insn_rtx_costs reports that the
2589 replacement instructions are cheaper than the originals. */
2590 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2596 /* We now know that we can do this combination. Merge the insns and
2597 update the status of registers and LOG_LINKS. */
2605 /* I3 now uses what used to be its destination and which is now
2606 I2's destination. This requires us to do a few adjustments. */
2607 PATTERN (i3) = newpat;
2608 adjust_for_new_dest (i3);
2610 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2613 However, some later insn might be using I2's dest and have
2614 a LOG_LINK pointing at I3. We must remove this link.
2615 The simplest way to remove the link is to point it at I1,
2616 which we know will be a NOTE. */
2618 ni2dest = SET_DEST (newi2pat);
2619 for (insn = NEXT_INSN (i3);
2620 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2621 || insn != BB_HEAD (this_basic_block->next_bb));
2622 insn = NEXT_INSN (insn))
2624 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2626 for (link = LOG_LINKS (insn); link;
2627 link = XEXP (link, 1))
2628 if (XEXP (link, 0) == i3)
2629 XEXP (link, 0) = i1;
2637 rtx i3notes, i2notes, i1notes = 0;
2638 rtx i3links, i2links, i1links = 0;
2642 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2644 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2645 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2647 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2649 /* Ensure that we do not have something that should not be shared but
2650 occurs multiple times in the new insns. Check this by first
2651 resetting all the `used' flags and then copying anything is shared. */
2653 reset_used_flags (i3notes);
2654 reset_used_flags (i2notes);
2655 reset_used_flags (i1notes);
2656 reset_used_flags (newpat);
2657 reset_used_flags (newi2pat);
2658 if (undobuf.other_insn)
2659 reset_used_flags (PATTERN (undobuf.other_insn));
2661 i3notes = copy_rtx_if_shared (i3notes);
2662 i2notes = copy_rtx_if_shared (i2notes);
2663 i1notes = copy_rtx_if_shared (i1notes);
2664 newpat = copy_rtx_if_shared (newpat);
2665 newi2pat = copy_rtx_if_shared (newi2pat);
2666 if (undobuf.other_insn)
2667 reset_used_flags (PATTERN (undobuf.other_insn));
2669 INSN_CODE (i3) = insn_code_number;
2670 PATTERN (i3) = newpat;
2672 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2674 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2676 reset_used_flags (call_usage);
2677 call_usage = copy_rtx (call_usage);
2680 replace_rtx (call_usage, i2dest, i2src);
2683 replace_rtx (call_usage, i1dest, i1src);
2685 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2688 if (undobuf.other_insn)
2689 INSN_CODE (undobuf.other_insn) = other_code_number;
2691 /* We had one special case above where I2 had more than one set and
2692 we replaced a destination of one of those sets with the destination
2693 of I3. In that case, we have to update LOG_LINKS of insns later
2694 in this basic block. Note that this (expensive) case is rare.
2696 Also, in this case, we must pretend that all REG_NOTEs for I2
2697 actually came from I3, so that REG_UNUSED notes from I2 will be
2698 properly handled. */
2700 if (i3_subst_into_i2)
2702 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2703 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2704 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2705 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2706 && ! find_reg_note (i2, REG_UNUSED,
2707 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2708 for (temp = NEXT_INSN (i2);
2709 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2710 || BB_HEAD (this_basic_block) != temp);
2711 temp = NEXT_INSN (temp))
2712 if (temp != i3 && INSN_P (temp))
2713 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2714 if (XEXP (link, 0) == i2)
2715 XEXP (link, 0) = i3;
2720 while (XEXP (link, 1))
2721 link = XEXP (link, 1);
2722 XEXP (link, 1) = i2notes;
2736 INSN_CODE (i2) = i2_code_number;
2737 PATTERN (i2) = newi2pat;
2740 SET_INSN_DELETED (i2);
2746 SET_INSN_DELETED (i1);
2749 /* Get death notes for everything that is now used in either I3 or
2750 I2 and used to die in a previous insn. If we built two new
2751 patterns, move from I1 to I2 then I2 to I3 so that we get the
2752 proper movement on registers that I2 modifies. */
2756 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2757 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2760 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2763 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2765 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX);
2767 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX);
2769 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX);
2771 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2773 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2774 know these are REG_UNUSED and want them to go to the desired insn,
2775 so we always pass it as i3. We have not counted the notes in
2776 reg_n_deaths yet, so we need to do so now. */
2778 if (newi2pat && new_i2_notes)
2780 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2781 if (REG_P (XEXP (temp, 0)))
2782 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2784 distribute_notes (new_i2_notes, i2, i2, NULL_RTX);
2789 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
2790 if (REG_P (XEXP (temp, 0)))
2791 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2793 distribute_notes (new_i3_notes, i3, i3, NULL_RTX);
2796 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2797 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2798 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2799 in that case, it might delete I2. Similarly for I2 and I1.
2800 Show an additional death due to the REG_DEAD note we make here. If
2801 we discard it in distribute_notes, we will decrement it again. */
2805 if (REG_P (i3dest_killed))
2806 REG_N_DEATHS (REGNO (i3dest_killed))++;
2808 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
2809 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2811 NULL_RTX, i2, NULL_RTX);
2813 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
2815 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2818 if (i2dest_in_i2src)
2821 REG_N_DEATHS (REGNO (i2dest))++;
2823 if (newi2pat && reg_set_p (i2dest, newi2pat))
2824 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2825 NULL_RTX, i2, NULL_RTX);
2827 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
2828 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2831 if (i1dest_in_i1src)
2834 REG_N_DEATHS (REGNO (i1dest))++;
2836 if (newi2pat && reg_set_p (i1dest, newi2pat))
2837 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2838 NULL_RTX, i2, NULL_RTX);
2840 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
2841 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX);
2844 distribute_links (i3links);
2845 distribute_links (i2links);
2846 distribute_links (i1links);
2851 rtx i2_insn = 0, i2_val = 0, set;
2853 /* The insn that used to set this register doesn't exist, and
2854 this life of the register may not exist either. See if one of
2855 I3's links points to an insn that sets I2DEST. If it does,
2856 that is now the last known value for I2DEST. If we don't update
2857 this and I2 set the register to a value that depended on its old
2858 contents, we will get confused. If this insn is used, thing
2859 will be set correctly in combine_instructions. */
2861 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2862 if ((set = single_set (XEXP (link, 0))) != 0
2863 && rtx_equal_p (i2dest, SET_DEST (set)))
2864 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
2866 record_value_for_reg (i2dest, i2_insn, i2_val);
2868 /* If the reg formerly set in I2 died only once and that was in I3,
2869 zero its use count so it won't make `reload' do any work. */
2871 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
2872 && ! i2dest_in_i2src)
2874 regno = REGNO (i2dest);
2875 REG_N_SETS (regno)--;
2879 if (i1 && REG_P (i1dest))
2882 rtx i1_insn = 0, i1_val = 0, set;
2884 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
2885 if ((set = single_set (XEXP (link, 0))) != 0
2886 && rtx_equal_p (i1dest, SET_DEST (set)))
2887 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
2889 record_value_for_reg (i1dest, i1_insn, i1_val);
2891 regno = REGNO (i1dest);
2892 if (! added_sets_1 && ! i1dest_in_i1src)
2893 REG_N_SETS (regno)--;
2896 /* Update reg_stat[].nonzero_bits et al for any changes that may have
2897 been made to this insn. The order of
2898 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
2899 can affect nonzero_bits of newpat */
2901 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
2902 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
2904 /* Set new_direct_jump_p if a new return or simple jump instruction
2907 If I3 is now an unconditional jump, ensure that it has a
2908 BARRIER following it since it may have initially been a
2909 conditional jump. It may also be the last nonnote insn. */
2911 if (returnjump_p (i3) || any_uncondjump_p (i3))
2913 *new_direct_jump_p = 1;
2914 mark_jump_label (PATTERN (i3), i3, 0);
2916 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
2917 || !BARRIER_P (temp))
2918 emit_barrier_after (i3);
2921 if (undobuf.other_insn != NULL_RTX
2922 && (returnjump_p (undobuf.other_insn)
2923 || any_uncondjump_p (undobuf.other_insn)))
2925 *new_direct_jump_p = 1;
2927 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
2928 || !BARRIER_P (temp))
2929 emit_barrier_after (undobuf.other_insn);
2932 /* An NOOP jump does not need barrier, but it does need cleaning up
2934 if (GET_CODE (newpat) == SET
2935 && SET_SRC (newpat) == pc_rtx
2936 && SET_DEST (newpat) == pc_rtx)
2937 *new_direct_jump_p = 1;
2940 combine_successes++;
2943 if (added_links_insn
2944 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
2945 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
2946 return added_links_insn;
2948 return newi2pat ? i2 : i3;
2951 /* Undo all the modifications recorded in undobuf. */
2956 struct undo *undo, *next;
2958 for (undo = undobuf.undos; undo; undo = next)
2962 *undo->where.i = undo->old_contents.i;
2964 *undo->where.r = undo->old_contents.r;
2966 undo->next = undobuf.frees;
2967 undobuf.frees = undo;
2973 /* We've committed to accepting the changes we made. Move all
2974 of the undos to the free list. */
2979 struct undo *undo, *next;
2981 for (undo = undobuf.undos; undo; undo = next)
2984 undo->next = undobuf.frees;
2985 undobuf.frees = undo;
2991 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2992 where we have an arithmetic expression and return that point. LOC will
2995 try_combine will call this function to see if an insn can be split into
2999 find_split_point (rtx *loc, rtx insn)
3002 enum rtx_code code = GET_CODE (x);
3004 unsigned HOST_WIDE_INT len = 0;
3005 HOST_WIDE_INT pos = 0;
3007 rtx inner = NULL_RTX;
3009 /* First special-case some codes. */
3013 #ifdef INSN_SCHEDULING
3014 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3016 if (MEM_P (SUBREG_REG (x)))
3019 return find_split_point (&SUBREG_REG (x), insn);
3023 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3024 using LO_SUM and HIGH. */
3025 if (GET_CODE (XEXP (x, 0)) == CONST
3026 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3029 gen_rtx_LO_SUM (Pmode,
3030 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3032 return &XEXP (XEXP (x, 0), 0);
3036 /* If we have a PLUS whose second operand is a constant and the
3037 address is not valid, perhaps will can split it up using
3038 the machine-specific way to split large constants. We use
3039 the first pseudo-reg (one of the virtual regs) as a placeholder;
3040 it will not remain in the result. */
3041 if (GET_CODE (XEXP (x, 0)) == PLUS
3042 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3043 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3045 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3046 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3049 /* This should have produced two insns, each of which sets our
3050 placeholder. If the source of the second is a valid address,
3051 we can make put both sources together and make a split point
3055 && NEXT_INSN (seq) != NULL_RTX
3056 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3057 && NONJUMP_INSN_P (seq)
3058 && GET_CODE (PATTERN (seq)) == SET
3059 && SET_DEST (PATTERN (seq)) == reg
3060 && ! reg_mentioned_p (reg,
3061 SET_SRC (PATTERN (seq)))
3062 && NONJUMP_INSN_P (NEXT_INSN (seq))
3063 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3064 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3065 && memory_address_p (GET_MODE (x),
3066 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3068 rtx src1 = SET_SRC (PATTERN (seq));
3069 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3071 /* Replace the placeholder in SRC2 with SRC1. If we can
3072 find where in SRC2 it was placed, that can become our
3073 split point and we can replace this address with SRC2.
3074 Just try two obvious places. */
3076 src2 = replace_rtx (src2, reg, src1);
3078 if (XEXP (src2, 0) == src1)
3079 split = &XEXP (src2, 0);
3080 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3081 && XEXP (XEXP (src2, 0), 0) == src1)
3082 split = &XEXP (XEXP (src2, 0), 0);
3086 SUBST (XEXP (x, 0), src2);
3091 /* If that didn't work, perhaps the first operand is complex and
3092 needs to be computed separately, so make a split point there.
3093 This will occur on machines that just support REG + CONST
3094 and have a constant moved through some previous computation. */
3096 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3097 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3098 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3099 return &XEXP (XEXP (x, 0), 0);
3105 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3106 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3107 we need to put the operand into a register. So split at that
3110 if (SET_DEST (x) == cc0_rtx
3111 && GET_CODE (SET_SRC (x)) != COMPARE
3112 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3113 && !OBJECT_P (SET_SRC (x))
3114 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3115 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3116 return &SET_SRC (x);
3119 /* See if we can split SET_SRC as it stands. */
3120 split = find_split_point (&SET_SRC (x), insn);
3121 if (split && split != &SET_SRC (x))
3124 /* See if we can split SET_DEST as it stands. */
3125 split = find_split_point (&SET_DEST (x), insn);
3126 if (split && split != &SET_DEST (x))
3129 /* See if this is a bitfield assignment with everything constant. If
3130 so, this is an IOR of an AND, so split it into that. */
3131 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3132 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3133 <= HOST_BITS_PER_WIDE_INT)
3134 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3135 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3136 && GET_CODE (SET_SRC (x)) == CONST_INT
3137 && ((INTVAL (XEXP (SET_DEST (x), 1))
3138 + INTVAL (XEXP (SET_DEST (x), 2)))
3139 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3140 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3142 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3143 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3144 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3145 rtx dest = XEXP (SET_DEST (x), 0);
3146 enum machine_mode mode = GET_MODE (dest);
3147 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3149 if (BITS_BIG_ENDIAN)
3150 pos = GET_MODE_BITSIZE (mode) - len - pos;
3154 gen_binary (IOR, mode, dest, GEN_INT (src << pos)));
3157 gen_binary (IOR, mode,
3158 gen_binary (AND, mode, dest,
3159 gen_int_mode (~(mask << pos),
3161 GEN_INT (src << pos)));
3163 SUBST (SET_DEST (x), dest);
3165 split = find_split_point (&SET_SRC (x), insn);
3166 if (split && split != &SET_SRC (x))
3170 /* Otherwise, see if this is an operation that we can split into two.
3171 If so, try to split that. */
3172 code = GET_CODE (SET_SRC (x));
3177 /* If we are AND'ing with a large constant that is only a single
3178 bit and the result is only being used in a context where we
3179 need to know if it is zero or nonzero, replace it with a bit
3180 extraction. This will avoid the large constant, which might
3181 have taken more than one insn to make. If the constant were
3182 not a valid argument to the AND but took only one insn to make,
3183 this is no worse, but if it took more than one insn, it will
3186 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3187 && REG_P (XEXP (SET_SRC (x), 0))
3188 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3189 && REG_P (SET_DEST (x))
3190 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3191 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3192 && XEXP (*split, 0) == SET_DEST (x)
3193 && XEXP (*split, 1) == const0_rtx)
3195 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3196 XEXP (SET_SRC (x), 0),
3197 pos, NULL_RTX, 1, 1, 0, 0);
3198 if (extraction != 0)
3200 SUBST (SET_SRC (x), extraction);
3201 return find_split_point (loc, insn);
3207 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3208 is known to be on, this can be converted into a NEG of a shift. */
3209 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3210 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3211 && 1 <= (pos = exact_log2
3212 (nonzero_bits (XEXP (SET_SRC (x), 0),
3213 GET_MODE (XEXP (SET_SRC (x), 0))))))
3215 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3219 gen_rtx_LSHIFTRT (mode,
3220 XEXP (SET_SRC (x), 0),
3223 split = find_split_point (&SET_SRC (x), insn);
3224 if (split && split != &SET_SRC (x))
3230 inner = XEXP (SET_SRC (x), 0);
3232 /* We can't optimize if either mode is a partial integer
3233 mode as we don't know how many bits are significant
3235 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3236 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3240 len = GET_MODE_BITSIZE (GET_MODE (inner));
3246 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3247 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3249 inner = XEXP (SET_SRC (x), 0);
3250 len = INTVAL (XEXP (SET_SRC (x), 1));
3251 pos = INTVAL (XEXP (SET_SRC (x), 2));
3253 if (BITS_BIG_ENDIAN)
3254 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3255 unsignedp = (code == ZERO_EXTRACT);
3263 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3265 enum machine_mode mode = GET_MODE (SET_SRC (x));
3267 /* For unsigned, we have a choice of a shift followed by an
3268 AND or two shifts. Use two shifts for field sizes where the
3269 constant might be too large. We assume here that we can
3270 always at least get 8-bit constants in an AND insn, which is
3271 true for every current RISC. */
3273 if (unsignedp && len <= 8)
3278 (mode, gen_lowpart (mode, inner),
3280 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3282 split = find_split_point (&SET_SRC (x), insn);
3283 if (split && split != &SET_SRC (x))
3290 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3291 gen_rtx_ASHIFT (mode,
3292 gen_lowpart (mode, inner),
3293 GEN_INT (GET_MODE_BITSIZE (mode)
3295 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3297 split = find_split_point (&SET_SRC (x), insn);
3298 if (split && split != &SET_SRC (x))
3303 /* See if this is a simple operation with a constant as the second
3304 operand. It might be that this constant is out of range and hence
3305 could be used as a split point. */
3306 if (BINARY_P (SET_SRC (x))
3307 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3308 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3309 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3310 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3311 return &XEXP (SET_SRC (x), 1);
3313 /* Finally, see if this is a simple operation with its first operand
3314 not in a register. The operation might require this operand in a
3315 register, so return it as a split point. We can always do this
3316 because if the first operand were another operation, we would have
3317 already found it as a split point. */
3318 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3319 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3320 return &XEXP (SET_SRC (x), 0);
3326 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3327 it is better to write this as (not (ior A B)) so we can split it.
3328 Similarly for IOR. */
3329 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3332 gen_rtx_NOT (GET_MODE (x),
3333 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3335 XEXP (XEXP (x, 0), 0),
3336 XEXP (XEXP (x, 1), 0))));
3337 return find_split_point (loc, insn);
3340 /* Many RISC machines have a large set of logical insns. If the
3341 second operand is a NOT, put it first so we will try to split the
3342 other operand first. */
3343 if (GET_CODE (XEXP (x, 1)) == NOT)
3345 rtx tem = XEXP (x, 0);
3346 SUBST (XEXP (x, 0), XEXP (x, 1));
3347 SUBST (XEXP (x, 1), tem);
3355 /* Otherwise, select our actions depending on our rtx class. */
3356 switch (GET_RTX_CLASS (code))
3358 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3360 split = find_split_point (&XEXP (x, 2), insn);
3363 /* ... fall through ... */
3365 case RTX_COMM_ARITH:
3367 case RTX_COMM_COMPARE:
3368 split = find_split_point (&XEXP (x, 1), insn);
3371 /* ... fall through ... */
3373 /* Some machines have (and (shift ...) ...) insns. If X is not
3374 an AND, but XEXP (X, 0) is, use it as our split point. */
3375 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3376 return &XEXP (x, 0);
3378 split = find_split_point (&XEXP (x, 0), insn);
3384 /* Otherwise, we don't have a split point. */
3389 /* Throughout X, replace FROM with TO, and return the result.
3390 The result is TO if X is FROM;
3391 otherwise the result is X, but its contents may have been modified.
3392 If they were modified, a record was made in undobuf so that
3393 undo_all will (among other things) return X to its original state.
3395 If the number of changes necessary is too much to record to undo,
3396 the excess changes are not made, so the result is invalid.
3397 The changes already made can still be undone.
3398 undobuf.num_undo is incremented for such changes, so by testing that
3399 the caller can tell whether the result is valid.
3401 `n_occurrences' is incremented each time FROM is replaced.
3403 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3405 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3406 by copying if `n_occurrences' is nonzero. */
3409 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3411 enum rtx_code code = GET_CODE (x);
3412 enum machine_mode op0_mode = VOIDmode;
3417 /* Two expressions are equal if they are identical copies of a shared
3418 RTX or if they are both registers with the same register number
3421 #define COMBINE_RTX_EQUAL_P(X,Y) \
3423 || (REG_P (X) && REG_P (Y) \
3424 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3426 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3429 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3432 /* If X and FROM are the same register but different modes, they will
3433 not have been seen as equal above. However, flow.c will make a
3434 LOG_LINKS entry for that case. If we do nothing, we will try to
3435 rerecognize our original insn and, when it succeeds, we will
3436 delete the feeding insn, which is incorrect.
3438 So force this insn not to match in this (rare) case. */
3439 if (! in_dest && code == REG && REG_P (from)
3440 && REGNO (x) == REGNO (from))
3441 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3443 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3444 of which may contain things that can be combined. */
3445 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3448 /* It is possible to have a subexpression appear twice in the insn.
3449 Suppose that FROM is a register that appears within TO.
3450 Then, after that subexpression has been scanned once by `subst',
3451 the second time it is scanned, TO may be found. If we were
3452 to scan TO here, we would find FROM within it and create a
3453 self-referent rtl structure which is completely wrong. */
3454 if (COMBINE_RTX_EQUAL_P (x, to))
3457 /* Parallel asm_operands need special attention because all of the
3458 inputs are shared across the arms. Furthermore, unsharing the
3459 rtl results in recognition failures. Failure to handle this case
3460 specially can result in circular rtl.
3462 Solve this by doing a normal pass across the first entry of the
3463 parallel, and only processing the SET_DESTs of the subsequent
3466 if (code == PARALLEL
3467 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3468 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3470 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3472 /* If this substitution failed, this whole thing fails. */
3473 if (GET_CODE (new) == CLOBBER
3474 && XEXP (new, 0) == const0_rtx)
3477 SUBST (XVECEXP (x, 0, 0), new);
3479 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3481 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3484 && GET_CODE (dest) != CC0
3485 && GET_CODE (dest) != PC)
3487 new = subst (dest, from, to, 0, unique_copy);
3489 /* If this substitution failed, this whole thing fails. */
3490 if (GET_CODE (new) == CLOBBER
3491 && XEXP (new, 0) == const0_rtx)
3494 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3500 len = GET_RTX_LENGTH (code);
3501 fmt = GET_RTX_FORMAT (code);
3503 /* We don't need to process a SET_DEST that is a register, CC0,
3504 or PC, so set up to skip this common case. All other cases
3505 where we want to suppress replacing something inside a
3506 SET_SRC are handled via the IN_DEST operand. */
3508 && (REG_P (SET_DEST (x))
3509 || GET_CODE (SET_DEST (x)) == CC0
3510 || GET_CODE (SET_DEST (x)) == PC))
3513 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3516 op0_mode = GET_MODE (XEXP (x, 0));
3518 for (i = 0; i < len; i++)
3523 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3525 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3527 new = (unique_copy && n_occurrences
3528 ? copy_rtx (to) : to);
3533 new = subst (XVECEXP (x, i, j), from, to, 0,
3536 /* If this substitution failed, this whole thing
3538 if (GET_CODE (new) == CLOBBER
3539 && XEXP (new, 0) == const0_rtx)
3543 SUBST (XVECEXP (x, i, j), new);
3546 else if (fmt[i] == 'e')
3548 /* If this is a register being set, ignore it. */
3551 && (code == SUBREG || code == STRICT_LOW_PART
3552 || code == ZERO_EXTRACT)
3557 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3559 /* In general, don't install a subreg involving two
3560 modes not tieable. It can worsen register
3561 allocation, and can even make invalid reload
3562 insns, since the reg inside may need to be copied
3563 from in the outside mode, and that may be invalid
3564 if it is an fp reg copied in integer mode.
3566 We allow two exceptions to this: It is valid if
3567 it is inside another SUBREG and the mode of that
3568 SUBREG and the mode of the inside of TO is
3569 tieable and it is valid if X is a SET that copies
3572 if (GET_CODE (to) == SUBREG
3573 && ! MODES_TIEABLE_P (GET_MODE (to),
3574 GET_MODE (SUBREG_REG (to)))
3575 && ! (code == SUBREG
3576 && MODES_TIEABLE_P (GET_MODE (x),
3577 GET_MODE (SUBREG_REG (to))))
3579 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3582 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3584 #ifdef CANNOT_CHANGE_MODE_CLASS
3587 && REGNO (to) < FIRST_PSEUDO_REGISTER
3588 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3591 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3594 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3598 /* If we are in a SET_DEST, suppress most cases unless we
3599 have gone inside a MEM, in which case we want to
3600 simplify the address. We assume here that things that
3601 are actually part of the destination have their inner
3602 parts in the first expression. This is true for SUBREG,
3603 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3604 things aside from REG and MEM that should appear in a
3606 new = subst (XEXP (x, i), from, to,
3608 && (code == SUBREG || code == STRICT_LOW_PART
3609 || code == ZERO_EXTRACT))
3611 && i == 0), unique_copy);
3613 /* If we found that we will have to reject this combination,
3614 indicate that by returning the CLOBBER ourselves, rather than
3615 an expression containing it. This will speed things up as
3616 well as prevent accidents where two CLOBBERs are considered
3617 to be equal, thus producing an incorrect simplification. */
3619 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3622 if (GET_CODE (x) == SUBREG
3623 && (GET_CODE (new) == CONST_INT
3624 || GET_CODE (new) == CONST_DOUBLE))
3626 enum machine_mode mode = GET_MODE (x);
3628 x = simplify_subreg (GET_MODE (x), new,
3629 GET_MODE (SUBREG_REG (x)),
3632 x = gen_rtx_CLOBBER (mode, const0_rtx);
3634 else if (GET_CODE (new) == CONST_INT
3635 && GET_CODE (x) == ZERO_EXTEND)
3637 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3638 new, GET_MODE (XEXP (x, 0)));
3642 SUBST (XEXP (x, i), new);
3647 /* Try to simplify X. If the simplification changed the code, it is likely
3648 that further simplification will help, so loop, but limit the number
3649 of repetitions that will be performed. */
3651 for (i = 0; i < 4; i++)
3653 /* If X is sufficiently simple, don't bother trying to do anything
3655 if (code != CONST_INT && code != REG && code != CLOBBER)
3656 x = combine_simplify_rtx (x, op0_mode, in_dest);
3658 if (GET_CODE (x) == code)
3661 code = GET_CODE (x);
3663 /* We no longer know the original mode of operand 0 since we
3664 have changed the form of X) */
3665 op0_mode = VOIDmode;
3671 /* Simplify X, a piece of RTL. We just operate on the expression at the
3672 outer level; call `subst' to simplify recursively. Return the new
3675 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3676 if we are inside a SET_DEST. */
3679 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3681 enum rtx_code code = GET_CODE (x);
3682 enum machine_mode mode = GET_MODE (x);
3687 /* If this is a commutative operation, put a constant last and a complex
3688 expression first. We don't need to do this for comparisons here. */
3689 if (COMMUTATIVE_ARITH_P (x)
3690 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3693 SUBST (XEXP (x, 0), XEXP (x, 1));
3694 SUBST (XEXP (x, 1), temp);
3697 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3698 sign extension of a PLUS with a constant, reverse the order of the sign
3699 extension and the addition. Note that this not the same as the original
3700 code, but overflow is undefined for signed values. Also note that the
3701 PLUS will have been partially moved "inside" the sign-extension, so that
3702 the first operand of X will really look like:
3703 (ashiftrt (plus (ashift A C4) C5) C4).
3705 (plus (ashiftrt (ashift A C4) C2) C4)
3706 and replace the first operand of X with that expression. Later parts
3707 of this function may simplify the expression further.
3709 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3710 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3711 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3713 We do this to simplify address expressions. */
3715 if ((code == PLUS || code == MINUS || code == MULT)
3716 && GET_CODE (XEXP (x, 0)) == ASHIFTRT
3717 && GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
3718 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == ASHIFT
3719 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1)) == CONST_INT
3720 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3721 && XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 1) == XEXP (XEXP (x, 0), 1)
3722 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
3723 && (temp = simplify_binary_operation (ASHIFTRT, mode,
3724 XEXP (XEXP (XEXP (x, 0), 0), 1),
3725 XEXP (XEXP (x, 0), 1))) != 0)
3728 = simplify_shift_const (NULL_RTX, ASHIFT, mode,
3729 XEXP (XEXP (XEXP (XEXP (x, 0), 0), 0), 0),
3730 INTVAL (XEXP (XEXP (x, 0), 1)));
3732 new = simplify_shift_const (NULL_RTX, ASHIFTRT, mode, new,
3733 INTVAL (XEXP (XEXP (x, 0), 1)));
3735 SUBST (XEXP (x, 0), gen_binary (PLUS, mode, new, temp));
3738 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3739 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3740 things. Check for cases where both arms are testing the same
3743 Don't do anything if all operands are very simple. */
3746 && ((!OBJECT_P (XEXP (x, 0))
3747 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3748 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3749 || (!OBJECT_P (XEXP (x, 1))
3750 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3751 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3753 && (!OBJECT_P (XEXP (x, 0))
3754 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3755 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3757 rtx cond, true_rtx, false_rtx;
3759 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3761 /* If everything is a comparison, what we have is highly unlikely
3762 to be simpler, so don't use it. */
3763 && ! (COMPARISON_P (x)
3764 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3766 rtx cop1 = const0_rtx;
3767 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3769 if (cond_code == NE && COMPARISON_P (cond))
3772 /* Simplify the alternative arms; this may collapse the true and
3773 false arms to store-flag values. Be careful to use copy_rtx
3774 here since true_rtx or false_rtx might share RTL with x as a
3775 result of the if_then_else_cond call above. */
3776 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3777 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3779 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3780 is unlikely to be simpler. */
3781 if (general_operand (true_rtx, VOIDmode)
3782 && general_operand (false_rtx, VOIDmode))
3784 enum rtx_code reversed;
3786 /* Restarting if we generate a store-flag expression will cause
3787 us to loop. Just drop through in this case. */
3789 /* If the result values are STORE_FLAG_VALUE and zero, we can
3790 just make the comparison operation. */
3791 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3792 x = gen_binary (cond_code, mode, cond, cop1);
3793 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3794 && ((reversed = reversed_comparison_code_parts
3795 (cond_code, cond, cop1, NULL))
3797 x = gen_binary (reversed, mode, cond, cop1);
3799 /* Likewise, we can make the negate of a comparison operation
3800 if the result values are - STORE_FLAG_VALUE and zero. */
3801 else if (GET_CODE (true_rtx) == CONST_INT
3802 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3803 && false_rtx == const0_rtx)
3804 x = simplify_gen_unary (NEG, mode,
3805 gen_binary (cond_code, mode, cond,
3808 else if (GET_CODE (false_rtx) == CONST_INT
3809 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3810 && true_rtx == const0_rtx
3811 && ((reversed = reversed_comparison_code_parts
3812 (cond_code, cond, cop1, NULL))
3814 x = simplify_gen_unary (NEG, mode,
3815 gen_binary (reversed, mode,
3819 return gen_rtx_IF_THEN_ELSE (mode,
3820 gen_binary (cond_code, VOIDmode,
3822 true_rtx, false_rtx);
3824 code = GET_CODE (x);
3825 op0_mode = VOIDmode;
3830 /* Try to fold this expression in case we have constants that weren't
3833 switch (GET_RTX_CLASS (code))
3836 if (op0_mode == VOIDmode)
3837 op0_mode = GET_MODE (XEXP (x, 0));
3838 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
3841 case RTX_COMM_COMPARE:
3843 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
3844 if (cmp_mode == VOIDmode)
3846 cmp_mode = GET_MODE (XEXP (x, 1));
3847 if (cmp_mode == VOIDmode)
3848 cmp_mode = op0_mode;
3850 temp = simplify_relational_operation (code, mode, cmp_mode,
3851 XEXP (x, 0), XEXP (x, 1));
3854 case RTX_COMM_ARITH:
3856 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
3858 case RTX_BITFIELD_OPS:
3860 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
3861 XEXP (x, 1), XEXP (x, 2));
3870 code = GET_CODE (temp);
3871 op0_mode = VOIDmode;
3872 mode = GET_MODE (temp);
3875 /* First see if we can apply the inverse distributive law. */
3876 if (code == PLUS || code == MINUS
3877 || code == AND || code == IOR || code == XOR)
3879 x = apply_distributive_law (x);
3880 code = GET_CODE (x);
3881 op0_mode = VOIDmode;
3884 /* If CODE is an associative operation not otherwise handled, see if we
3885 can associate some operands. This can win if they are constants or
3886 if they are logically related (i.e. (a & b) & a). */
3887 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
3888 || code == AND || code == IOR || code == XOR
3889 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
3890 && ((INTEGRAL_MODE_P (mode) && code != DIV)
3891 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
3893 if (GET_CODE (XEXP (x, 0)) == code)
3895 rtx other = XEXP (XEXP (x, 0), 0);
3896 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
3897 rtx inner_op1 = XEXP (x, 1);
3900 /* Make sure we pass the constant operand if any as the second
3901 one if this is a commutative operation. */
3902 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
3904 rtx tem = inner_op0;
3905 inner_op0 = inner_op1;
3908 inner = simplify_binary_operation (code == MINUS ? PLUS
3909 : code == DIV ? MULT
3911 mode, inner_op0, inner_op1);
3913 /* For commutative operations, try the other pair if that one
3915 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
3917 other = XEXP (XEXP (x, 0), 1);
3918 inner = simplify_binary_operation (code, mode,
3919 XEXP (XEXP (x, 0), 0),
3924 return gen_binary (code, mode, other, inner);
3928 /* A little bit of algebraic simplification here. */
3932 /* Ensure that our address has any ASHIFTs converted to MULT in case
3933 address-recognizing predicates are called later. */
3934 temp = make_compound_operation (XEXP (x, 0), MEM);
3935 SUBST (XEXP (x, 0), temp);
3939 if (op0_mode == VOIDmode)
3940 op0_mode = GET_MODE (SUBREG_REG (x));
3942 /* See if this can be moved to simplify_subreg. */
3943 if (CONSTANT_P (SUBREG_REG (x))
3944 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
3945 /* Don't call gen_lowpart if the inner mode
3946 is VOIDmode and we cannot simplify it, as SUBREG without
3947 inner mode is invalid. */
3948 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
3949 || gen_lowpart_common (mode, SUBREG_REG (x))))
3950 return gen_lowpart (mode, SUBREG_REG (x));
3952 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
3956 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
3962 /* Don't change the mode of the MEM if that would change the meaning
3964 if (MEM_P (SUBREG_REG (x))
3965 && (MEM_VOLATILE_P (SUBREG_REG (x))
3966 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
3967 return gen_rtx_CLOBBER (mode, const0_rtx);
3969 /* Note that we cannot do any narrowing for non-constants since
3970 we might have been counting on using the fact that some bits were
3971 zero. We now do this in the SET. */
3976 if (GET_CODE (XEXP (x, 0)) == SUBREG
3977 && subreg_lowpart_p (XEXP (x, 0))
3978 && (GET_MODE_SIZE (GET_MODE (XEXP (x, 0)))
3979 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x, 0)))))
3980 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == ASHIFT
3981 && XEXP (SUBREG_REG (XEXP (x, 0)), 0) == const1_rtx)
3983 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (XEXP (x, 0)));
3985 x = gen_rtx_ROTATE (inner_mode,
3986 simplify_gen_unary (NOT, inner_mode, const1_rtx,
3988 XEXP (SUBREG_REG (XEXP (x, 0)), 1));
3989 return gen_lowpart (mode, x);
3992 /* Apply De Morgan's laws to reduce number of patterns for machines
3993 with negating logical insns (and-not, nand, etc.). If result has
3994 only one NOT, put it first, since that is how the patterns are
3997 if (GET_CODE (XEXP (x, 0)) == IOR || GET_CODE (XEXP (x, 0)) == AND)
3999 rtx in1 = XEXP (XEXP (x, 0), 0), in2 = XEXP (XEXP (x, 0), 1);
4000 enum machine_mode op_mode;
4002 op_mode = GET_MODE (in1);
4003 in1 = simplify_gen_unary (NOT, op_mode, in1, op_mode);
4005 op_mode = GET_MODE (in2);
4006 if (op_mode == VOIDmode)
4008 in2 = simplify_gen_unary (NOT, op_mode, in2, op_mode);
4010 if (GET_CODE (in2) == NOT && GET_CODE (in1) != NOT)
4013 in2 = in1; in1 = tem;
4016 return gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)) == IOR ? AND : IOR,
4022 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
4023 if (GET_CODE (XEXP (x, 0)) == XOR
4024 && XEXP (XEXP (x, 0), 1) == const1_rtx
4025 && nonzero_bits (XEXP (XEXP (x, 0), 0), mode) == 1)
4026 return gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0), constm1_rtx);
4028 temp = expand_compound_operation (XEXP (x, 0));
4030 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4031 replaced by (lshiftrt X C). This will convert
4032 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4034 if (GET_CODE (temp) == ASHIFTRT
4035 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4036 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4037 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4038 INTVAL (XEXP (temp, 1)));
4040 /* If X has only a single bit that might be nonzero, say, bit I, convert
4041 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4042 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4043 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4044 or a SUBREG of one since we'd be making the expression more
4045 complex if it was just a register. */
4048 && ! (GET_CODE (temp) == SUBREG
4049 && REG_P (SUBREG_REG (temp)))
4050 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4052 rtx temp1 = simplify_shift_const
4053 (NULL_RTX, ASHIFTRT, mode,
4054 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4055 GET_MODE_BITSIZE (mode) - 1 - i),
4056 GET_MODE_BITSIZE (mode) - 1 - i);
4058 /* If all we did was surround TEMP with the two shifts, we
4059 haven't improved anything, so don't use it. Otherwise,
4060 we are better off with TEMP1. */
4061 if (GET_CODE (temp1) != ASHIFTRT
4062 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4063 || XEXP (XEXP (temp1, 0), 0) != temp)
4069 /* We can't handle truncation to a partial integer mode here
4070 because we don't know the real bitsize of the partial
4072 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4075 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4076 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4077 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4079 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4080 GET_MODE_MASK (mode), NULL_RTX, 0));
4082 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4083 if ((GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4084 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4085 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4086 return XEXP (XEXP (x, 0), 0);
4088 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4089 (OP:SI foo:SI) if OP is NEG or ABS. */
4090 if ((GET_CODE (XEXP (x, 0)) == ABS
4091 || GET_CODE (XEXP (x, 0)) == NEG)
4092 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SIGN_EXTEND
4093 || GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND)
4094 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4095 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4096 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4098 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4100 if (GET_CODE (XEXP (x, 0)) == SUBREG
4101 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == TRUNCATE
4102 && subreg_lowpart_p (XEXP (x, 0)))
4103 return SUBREG_REG (XEXP (x, 0));
4105 /* If we know that the value is already truncated, we can
4106 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4107 is nonzero for the corresponding modes. But don't do this
4108 for an (LSHIFTRT (MULT ...)) since this will cause problems
4109 with the umulXi3_highpart patterns. */
4110 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4111 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
4112 && num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4113 >= (unsigned int) (GET_MODE_BITSIZE (mode) + 1)
4114 && ! (GET_CODE (XEXP (x, 0)) == LSHIFTRT
4115 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT))
4116 return gen_lowpart (mode, XEXP (x, 0));
4118 /* A truncate of a comparison can be replaced with a subreg if
4119 STORE_FLAG_VALUE permits. This is like the previous test,
4120 but it works even if the comparison is done in a mode larger
4121 than HOST_BITS_PER_WIDE_INT. */
4122 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4123 && COMPARISON_P (XEXP (x, 0))
4124 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0)
4125 return gen_lowpart (mode, XEXP (x, 0));
4127 /* Similarly, a truncate of a register whose value is a
4128 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4130 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4131 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4132 && (temp = get_last_value (XEXP (x, 0)))
4133 && COMPARISON_P (temp))
4134 return gen_lowpart (mode, XEXP (x, 0));
4138 case FLOAT_TRUNCATE:
4139 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4140 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4141 && GET_MODE (XEXP (XEXP (x, 0), 0)) == mode)
4142 return XEXP (XEXP (x, 0), 0);
4144 /* (float_truncate:SF (float_truncate:DF foo:XF))
4145 = (float_truncate:SF foo:XF).
4146 This may eliminate double rounding, so it is unsafe.
4148 (float_truncate:SF (float_extend:XF foo:DF))
4149 = (float_truncate:SF foo:DF).
4151 (float_truncate:DF (float_extend:XF foo:SF))
4152 = (float_extend:SF foo:DF). */
4153 if ((GET_CODE (XEXP (x, 0)) == FLOAT_TRUNCATE
4154 && flag_unsafe_math_optimizations)
4155 || GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND)
4156 return simplify_gen_unary (GET_MODE_SIZE (GET_MODE (XEXP (XEXP (x, 0),
4158 > GET_MODE_SIZE (mode)
4159 ? FLOAT_TRUNCATE : FLOAT_EXTEND,
4161 XEXP (XEXP (x, 0), 0), mode);
4163 /* (float_truncate (float x)) is (float x) */
4164 if (GET_CODE (XEXP (x, 0)) == FLOAT
4165 && (flag_unsafe_math_optimizations
4166 || ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4167 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4168 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4169 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4170 return simplify_gen_unary (FLOAT, mode,
4171 XEXP (XEXP (x, 0), 0),
4172 GET_MODE (XEXP (XEXP (x, 0), 0)));
4174 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4175 (OP:SF foo:SF) if OP is NEG or ABS. */
4176 if ((GET_CODE (XEXP (x, 0)) == ABS
4177 || GET_CODE (XEXP (x, 0)) == NEG)
4178 && GET_CODE (XEXP (XEXP (x, 0), 0)) == FLOAT_EXTEND
4179 && GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == mode)
4180 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4181 XEXP (XEXP (XEXP (x, 0), 0), 0), mode);
4183 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4184 is (float_truncate:SF x). */
4185 if (GET_CODE (XEXP (x, 0)) == SUBREG
4186 && subreg_lowpart_p (XEXP (x, 0))
4187 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == FLOAT_TRUNCATE)
4188 return SUBREG_REG (XEXP (x, 0));
4191 /* (float_extend (float_extend x)) is (float_extend x)
4193 (float_extend (float x)) is (float x) assuming that double
4194 rounding can't happen.
4196 if (GET_CODE (XEXP (x, 0)) == FLOAT_EXTEND
4197 || (GET_CODE (XEXP (x, 0)) == FLOAT
4198 && ((unsigned)significand_size (GET_MODE (XEXP (x, 0)))
4199 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (x, 0), 0)))
4200 - num_sign_bit_copies (XEXP (XEXP (x, 0), 0),
4201 GET_MODE (XEXP (XEXP (x, 0), 0)))))))
4202 return simplify_gen_unary (GET_CODE (XEXP (x, 0)), mode,
4203 XEXP (XEXP (x, 0), 0),
4204 GET_MODE (XEXP (XEXP (x, 0), 0)));
4209 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4210 using cc0, in which case we want to leave it as a COMPARE
4211 so we can distinguish it from a register-register-copy. */
4212 if (XEXP (x, 1) == const0_rtx)
4215 /* x - 0 is the same as x unless x's mode has signed zeros and
4216 allows rounding towards -infinity. Under those conditions,
4218 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4219 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4220 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4226 /* (const (const X)) can become (const X). Do it this way rather than
4227 returning the inner CONST since CONST can be shared with a
4229 if (GET_CODE (XEXP (x, 0)) == CONST)
4230 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4235 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4236 can add in an offset. find_split_point will split this address up
4237 again if it doesn't match. */
4238 if (GET_CODE (XEXP (x, 0)) == HIGH
4239 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4245 /* Canonicalize (plus (mult (neg B) C) A) to (minus A (mult B C)).
4247 if (GET_CODE (XEXP (x, 0)) == MULT
4248 && GET_CODE (XEXP (XEXP (x, 0), 0)) == NEG)
4252 in1 = XEXP (XEXP (XEXP (x, 0), 0), 0);
4253 in2 = XEXP (XEXP (x, 0), 1);
4254 return gen_binary (MINUS, mode, XEXP (x, 1),
4255 gen_binary (MULT, mode, in1, in2));
4258 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4259 outermost. That's because that's the way indexed addresses are
4260 supposed to appear. This code used to check many more cases, but
4261 they are now checked elsewhere. */
4262 if (GET_CODE (XEXP (x, 0)) == PLUS
4263 && CONSTANT_ADDRESS_P (XEXP (XEXP (x, 0), 1)))
4264 return gen_binary (PLUS, mode,
4265 gen_binary (PLUS, mode, XEXP (XEXP (x, 0), 0),
4267 XEXP (XEXP (x, 0), 1));
4269 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4270 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4271 bit-field and can be replaced by either a sign_extend or a
4272 sign_extract. The `and' may be a zero_extend and the two
4273 <c>, -<c> constants may be reversed. */
4274 if (GET_CODE (XEXP (x, 0)) == XOR
4275 && GET_CODE (XEXP (x, 1)) == CONST_INT
4276 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4277 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4278 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4279 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4280 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4281 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4282 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4283 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4284 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4285 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4286 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4287 == (unsigned int) i + 1))))
4288 return simplify_shift_const
4289 (NULL_RTX, ASHIFTRT, mode,
4290 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4291 XEXP (XEXP (XEXP (x, 0), 0), 0),
4292 GET_MODE_BITSIZE (mode) - (i + 1)),
4293 GET_MODE_BITSIZE (mode) - (i + 1));
4295 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4296 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4297 is 1. This produces better code than the alternative immediately
4299 if (COMPARISON_P (XEXP (x, 0))
4300 && ((STORE_FLAG_VALUE == -1 && XEXP (x, 1) == const1_rtx)
4301 || (STORE_FLAG_VALUE == 1 && XEXP (x, 1) == constm1_rtx))
4302 && (reversed = reversed_comparison (XEXP (x, 0), mode,
4303 XEXP (XEXP (x, 0), 0),
4304 XEXP (XEXP (x, 0), 1))))
4306 simplify_gen_unary (NEG, mode, reversed, mode);
4308 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4309 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4310 the bitsize of the mode - 1. This allows simplification of
4311 "a = (b & 8) == 0;" */
4312 if (XEXP (x, 1) == constm1_rtx
4313 && !REG_P (XEXP (x, 0))
4314 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4315 && REG_P (SUBREG_REG (XEXP (x, 0))))
4316 && nonzero_bits (XEXP (x, 0), mode) == 1)
4317 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4318 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4319 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4320 GET_MODE_BITSIZE (mode) - 1),
4321 GET_MODE_BITSIZE (mode) - 1);
4323 /* If we are adding two things that have no bits in common, convert
4324 the addition into an IOR. This will often be further simplified,
4325 for example in cases like ((a & 1) + (a & 2)), which can
4328 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4329 && (nonzero_bits (XEXP (x, 0), mode)
4330 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4332 /* Try to simplify the expression further. */
4333 rtx tor = gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4334 temp = combine_simplify_rtx (tor, mode, in_dest);
4336 /* If we could, great. If not, do not go ahead with the IOR
4337 replacement, since PLUS appears in many special purpose
4338 address arithmetic instructions. */
4339 if (GET_CODE (temp) != CLOBBER && temp != tor)
4345 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4346 by reversing the comparison code if valid. */
4347 if (STORE_FLAG_VALUE == 1
4348 && XEXP (x, 0) == const1_rtx
4349 && COMPARISON_P (XEXP (x, 1))
4350 && (reversed = reversed_comparison (XEXP (x, 1), mode,
4351 XEXP (XEXP (x, 1), 0),
4352 XEXP (XEXP (x, 1), 1))))
4355 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4356 (and <foo> (const_int pow2-1)) */
4357 if (GET_CODE (XEXP (x, 1)) == AND
4358 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4359 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4360 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4361 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4362 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4364 /* Canonicalize (minus A (mult (neg B) C)) to (plus (mult B C) A).
4366 if (GET_CODE (XEXP (x, 1)) == MULT
4367 && GET_CODE (XEXP (XEXP (x, 1), 0)) == NEG)
4371 in1 = XEXP (XEXP (XEXP (x, 1), 0), 0);
4372 in2 = XEXP (XEXP (x, 1), 1);
4373 return gen_binary (PLUS, mode, gen_binary (MULT, mode, in1, in2),
4377 /* Canonicalize (minus (neg A) (mult B C)) to
4378 (minus (mult (neg B) C) A). */
4379 if (GET_CODE (XEXP (x, 1)) == MULT
4380 && GET_CODE (XEXP (x, 0)) == NEG)
4384 in1 = simplify_gen_unary (NEG, mode, XEXP (XEXP (x, 1), 0), mode);
4385 in2 = XEXP (XEXP (x, 1), 1);
4386 return gen_binary (MINUS, mode, gen_binary (MULT, mode, in1, in2),
4387 XEXP (XEXP (x, 0), 0));
4390 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4392 if (GET_CODE (XEXP (x, 1)) == PLUS && INTEGRAL_MODE_P (mode))
4393 return gen_binary (MINUS, mode,
4394 gen_binary (MINUS, mode, XEXP (x, 0),
4395 XEXP (XEXP (x, 1), 0)),
4396 XEXP (XEXP (x, 1), 1));
4400 /* If we have (mult (plus A B) C), apply the distributive law and then
4401 the inverse distributive law to see if things simplify. This
4402 occurs mostly in addresses, often when unrolling loops. */
4404 if (GET_CODE (XEXP (x, 0)) == PLUS)
4406 x = apply_distributive_law
4407 (gen_binary (PLUS, mode,
4408 gen_binary (MULT, mode,
4409 XEXP (XEXP (x, 0), 0), XEXP (x, 1)),
4410 gen_binary (MULT, mode,
4411 XEXP (XEXP (x, 0), 1),
4412 copy_rtx (XEXP (x, 1)))));
4414 if (GET_CODE (x) != MULT)
4417 /* Try simplify a*(b/c) as (a*b)/c. */
4418 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4419 && GET_CODE (XEXP (x, 0)) == DIV)
4421 rtx tem = simplify_binary_operation (MULT, mode,
4422 XEXP (XEXP (x, 0), 0),
4425 return gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4430 /* If this is a divide by a power of two, treat it as a shift if
4431 its first operand is a shift. */
4432 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4433 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4434 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4435 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4436 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4437 || GET_CODE (XEXP (x, 0)) == ROTATE
4438 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4439 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4443 case GT: case GTU: case GE: case GEU:
4444 case LT: case LTU: case LE: case LEU:
4445 case UNEQ: case LTGT:
4446 case UNGT: case UNGE:
4447 case UNLT: case UNLE:
4448 case UNORDERED: case ORDERED:
4449 /* If the first operand is a condition code, we can't do anything
4451 if (GET_CODE (XEXP (x, 0)) == COMPARE
4452 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4453 && ! CC0_P (XEXP (x, 0))))
4455 rtx op0 = XEXP (x, 0);
4456 rtx op1 = XEXP (x, 1);
4457 enum rtx_code new_code;
4459 if (GET_CODE (op0) == COMPARE)
4460 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4462 /* Simplify our comparison, if possible. */
4463 new_code = simplify_comparison (code, &op0, &op1);
4465 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4466 if only the low-order bit is possibly nonzero in X (such as when
4467 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4468 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4469 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4472 Remove any ZERO_EXTRACT we made when thinking this was a
4473 comparison. It may now be simpler to use, e.g., an AND. If a
4474 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4475 the call to make_compound_operation in the SET case. */
4477 if (STORE_FLAG_VALUE == 1
4478 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4479 && op1 == const0_rtx
4480 && mode == GET_MODE (op0)
4481 && nonzero_bits (op0, mode) == 1)
4482 return gen_lowpart (mode,
4483 expand_compound_operation (op0));
4485 else if (STORE_FLAG_VALUE == 1
4486 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4487 && op1 == const0_rtx
4488 && mode == GET_MODE (op0)
4489 && (num_sign_bit_copies (op0, mode)
4490 == GET_MODE_BITSIZE (mode)))
4492 op0 = expand_compound_operation (op0);
4493 return simplify_gen_unary (NEG, mode,
4494 gen_lowpart (mode, op0),
4498 else if (STORE_FLAG_VALUE == 1
4499 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4500 && op1 == const0_rtx
4501 && mode == GET_MODE (op0)
4502 && nonzero_bits (op0, mode) == 1)
4504 op0 = expand_compound_operation (op0);
4505 return gen_binary (XOR, mode,
4506 gen_lowpart (mode, op0),
4510 else if (STORE_FLAG_VALUE == 1
4511 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4512 && op1 == const0_rtx
4513 && mode == GET_MODE (op0)
4514 && (num_sign_bit_copies (op0, mode)
4515 == GET_MODE_BITSIZE (mode)))
4517 op0 = expand_compound_operation (op0);
4518 return plus_constant (gen_lowpart (mode, op0), 1);
4521 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4523 if (STORE_FLAG_VALUE == -1
4524 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4525 && op1 == const0_rtx
4526 && (num_sign_bit_copies (op0, mode)
4527 == GET_MODE_BITSIZE (mode)))
4528 return gen_lowpart (mode,
4529 expand_compound_operation (op0));
4531 else if (STORE_FLAG_VALUE == -1
4532 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4533 && op1 == const0_rtx
4534 && mode == GET_MODE (op0)
4535 && nonzero_bits (op0, mode) == 1)
4537 op0 = expand_compound_operation (op0);
4538 return simplify_gen_unary (NEG, mode,
4539 gen_lowpart (mode, op0),
4543 else if (STORE_FLAG_VALUE == -1
4544 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4545 && op1 == const0_rtx
4546 && mode == GET_MODE (op0)
4547 && (num_sign_bit_copies (op0, mode)
4548 == GET_MODE_BITSIZE (mode)))
4550 op0 = expand_compound_operation (op0);
4551 return simplify_gen_unary (NOT, mode,
4552 gen_lowpart (mode, op0),
4556 /* If X is 0/1, (eq X 0) is X-1. */
4557 else if (STORE_FLAG_VALUE == -1
4558 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4559 && op1 == const0_rtx
4560 && mode == GET_MODE (op0)
4561 && nonzero_bits (op0, mode) == 1)
4563 op0 = expand_compound_operation (op0);
4564 return plus_constant (gen_lowpart (mode, op0), -1);
4567 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4568 one bit that might be nonzero, we can convert (ne x 0) to
4569 (ashift x c) where C puts the bit in the sign bit. Remove any
4570 AND with STORE_FLAG_VALUE when we are done, since we are only
4571 going to test the sign bit. */
4572 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4573 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4574 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4575 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4576 && op1 == const0_rtx
4577 && mode == GET_MODE (op0)
4578 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4580 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4581 expand_compound_operation (op0),
4582 GET_MODE_BITSIZE (mode) - 1 - i);
4583 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4589 /* If the code changed, return a whole new comparison. */
4590 if (new_code != code)
4591 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4593 /* Otherwise, keep this operation, but maybe change its operands.
4594 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4595 SUBST (XEXP (x, 0), op0);
4596 SUBST (XEXP (x, 1), op1);
4601 return simplify_if_then_else (x);
4607 /* If we are processing SET_DEST, we are done. */
4611 return expand_compound_operation (x);
4614 return simplify_set (x);
4619 return simplify_logical (x);
4622 /* (abs (neg <foo>)) -> (abs <foo>) */
4623 if (GET_CODE (XEXP (x, 0)) == NEG)
4624 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4626 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4628 if (GET_MODE (XEXP (x, 0)) == VOIDmode)
4631 /* If operand is something known to be positive, ignore the ABS. */
4632 if (GET_CODE (XEXP (x, 0)) == FFS || GET_CODE (XEXP (x, 0)) == ABS
4633 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
4634 <= HOST_BITS_PER_WIDE_INT)
4635 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
4636 & ((HOST_WIDE_INT) 1
4637 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - 1)))
4641 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4642 if (num_sign_bit_copies (XEXP (x, 0), mode) == GET_MODE_BITSIZE (mode))
4643 return gen_rtx_NEG (mode, XEXP (x, 0));
4648 /* (ffs (*_extend <X>)) = (ffs <X>) */
4649 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
4650 || GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4651 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4656 /* (pop* (zero_extend <X>)) = (pop* <X>) */
4657 if (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND)
4658 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4662 /* (float (sign_extend <X>)) = (float <X>). */
4663 if (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
4664 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4672 /* If this is a shift by a constant amount, simplify it. */
4673 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4674 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4675 INTVAL (XEXP (x, 1)));
4677 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4679 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4681 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4688 rtx op0 = XEXP (x, 0);
4689 rtx op1 = XEXP (x, 1);
4692 gcc_assert (GET_CODE (op1) == PARALLEL);
4693 len = XVECLEN (op1, 0);
4695 && GET_CODE (XVECEXP (op1, 0, 0)) == CONST_INT
4696 && GET_CODE (op0) == VEC_CONCAT)
4698 int offset = INTVAL (XVECEXP (op1, 0, 0)) * GET_MODE_SIZE (GET_MODE (x));
4700 /* Try to find the element in the VEC_CONCAT. */
4703 if (GET_MODE (op0) == GET_MODE (x))
4705 if (GET_CODE (op0) == VEC_CONCAT)
4707 HOST_WIDE_INT op0_size = GET_MODE_SIZE (GET_MODE (XEXP (op0, 0)));
4708 if (op0_size < offset)
4709 op0 = XEXP (op0, 0);
4713 op0 = XEXP (op0, 1);
4731 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4734 simplify_if_then_else (rtx x)
4736 enum machine_mode mode = GET_MODE (x);
4737 rtx cond = XEXP (x, 0);
4738 rtx true_rtx = XEXP (x, 1);
4739 rtx false_rtx = XEXP (x, 2);
4740 enum rtx_code true_code = GET_CODE (cond);
4741 int comparison_p = COMPARISON_P (cond);
4744 enum rtx_code false_code;
4747 /* Simplify storing of the truth value. */
4748 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4749 return gen_binary (true_code, mode, XEXP (cond, 0), XEXP (cond, 1));
4751 /* Also when the truth value has to be reversed. */
4753 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4754 && (reversed = reversed_comparison (cond, mode, XEXP (cond, 0),
4758 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4759 in it is being compared against certain values. Get the true and false
4760 comparisons and see if that says anything about the value of each arm. */
4763 && ((false_code = combine_reversed_comparison_code (cond))
4765 && REG_P (XEXP (cond, 0)))
4768 rtx from = XEXP (cond, 0);
4769 rtx true_val = XEXP (cond, 1);
4770 rtx false_val = true_val;
4773 /* If FALSE_CODE is EQ, swap the codes and arms. */
4775 if (false_code == EQ)
4777 swapped = 1, true_code = EQ, false_code = NE;
4778 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4781 /* If we are comparing against zero and the expression being tested has
4782 only a single bit that might be nonzero, that is its value when it is
4783 not equal to zero. Similarly if it is known to be -1 or 0. */
4785 if (true_code == EQ && true_val == const0_rtx
4786 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4787 false_code = EQ, false_val = GEN_INT (nzb);
4788 else if (true_code == EQ && true_val == const0_rtx
4789 && (num_sign_bit_copies (from, GET_MODE (from))
4790 == GET_MODE_BITSIZE (GET_MODE (from))))
4791 false_code = EQ, false_val = constm1_rtx;
4793 /* Now simplify an arm if we know the value of the register in the
4794 branch and it is used in the arm. Be careful due to the potential
4795 of locally-shared RTL. */
4797 if (reg_mentioned_p (from, true_rtx))
4798 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4800 pc_rtx, pc_rtx, 0, 0);
4801 if (reg_mentioned_p (from, false_rtx))
4802 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4804 pc_rtx, pc_rtx, 0, 0);
4806 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4807 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4809 true_rtx = XEXP (x, 1);
4810 false_rtx = XEXP (x, 2);
4811 true_code = GET_CODE (cond);
4814 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4815 reversed, do so to avoid needing two sets of patterns for
4816 subtract-and-branch insns. Similarly if we have a constant in the true
4817 arm, the false arm is the same as the first operand of the comparison, or
4818 the false arm is more complicated than the true arm. */
4821 && combine_reversed_comparison_code (cond) != UNKNOWN
4822 && (true_rtx == pc_rtx
4823 || (CONSTANT_P (true_rtx)
4824 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4825 || true_rtx == const0_rtx
4826 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4827 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4828 && !OBJECT_P (false_rtx))
4829 || reg_mentioned_p (true_rtx, false_rtx)
4830 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4832 true_code = reversed_comparison_code (cond, NULL);
4834 reversed_comparison (cond, GET_MODE (cond), XEXP (cond, 0),
4837 SUBST (XEXP (x, 1), false_rtx);
4838 SUBST (XEXP (x, 2), true_rtx);
4840 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4843 /* It is possible that the conditional has been simplified out. */
4844 true_code = GET_CODE (cond);
4845 comparison_p = COMPARISON_P (cond);
4848 /* If the two arms are identical, we don't need the comparison. */
4850 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4853 /* Convert a == b ? b : a to "a". */
4854 if (true_code == EQ && ! side_effects_p (cond)
4855 && !HONOR_NANS (mode)
4856 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4857 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4859 else if (true_code == NE && ! side_effects_p (cond)
4860 && !HONOR_NANS (mode)
4861 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4862 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4865 /* Look for cases where we have (abs x) or (neg (abs X)). */
4867 if (GET_MODE_CLASS (mode) == MODE_INT
4868 && GET_CODE (false_rtx) == NEG
4869 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4871 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4872 && ! side_effects_p (true_rtx))
4877 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4881 simplify_gen_unary (NEG, mode,
4882 simplify_gen_unary (ABS, mode, true_rtx, mode),
4888 /* Look for MIN or MAX. */
4890 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4892 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4893 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4894 && ! side_effects_p (cond))
4899 return gen_binary (SMAX, mode, true_rtx, false_rtx);
4902 return gen_binary (SMIN, mode, true_rtx, false_rtx);
4905 return gen_binary (UMAX, mode, true_rtx, false_rtx);
4908 return gen_binary (UMIN, mode, true_rtx, false_rtx);
4913 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4914 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4915 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4916 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4917 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4918 neither 1 or -1, but it isn't worth checking for. */
4920 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4922 && GET_MODE_CLASS (mode) == MODE_INT
4923 && ! side_effects_p (x))
4925 rtx t = make_compound_operation (true_rtx, SET);
4926 rtx f = make_compound_operation (false_rtx, SET);
4927 rtx cond_op0 = XEXP (cond, 0);
4928 rtx cond_op1 = XEXP (cond, 1);
4929 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4930 enum machine_mode m = mode;
4931 rtx z = 0, c1 = NULL_RTX;
4933 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4934 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4935 || GET_CODE (t) == ASHIFT
4936 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4937 && rtx_equal_p (XEXP (t, 0), f))
4938 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4940 /* If an identity-zero op is commutative, check whether there
4941 would be a match if we swapped the operands. */
4942 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4943 || GET_CODE (t) == XOR)
4944 && rtx_equal_p (XEXP (t, 1), f))
4945 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4946 else if (GET_CODE (t) == SIGN_EXTEND
4947 && (GET_CODE (XEXP (t, 0)) == PLUS
4948 || GET_CODE (XEXP (t, 0)) == MINUS
4949 || GET_CODE (XEXP (t, 0)) == IOR
4950 || GET_CODE (XEXP (t, 0)) == XOR
4951 || GET_CODE (XEXP (t, 0)) == ASHIFT
4952 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4953 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4954 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4955 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4956 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4957 && (num_sign_bit_copies (f, GET_MODE (f))
4959 (GET_MODE_BITSIZE (mode)
4960 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4962 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4963 extend_op = SIGN_EXTEND;
4964 m = GET_MODE (XEXP (t, 0));
4966 else if (GET_CODE (t) == SIGN_EXTEND
4967 && (GET_CODE (XEXP (t, 0)) == PLUS
4968 || GET_CODE (XEXP (t, 0)) == IOR
4969 || GET_CODE (XEXP (t, 0)) == XOR)
4970 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4971 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4972 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4973 && (num_sign_bit_copies (f, GET_MODE (f))
4975 (GET_MODE_BITSIZE (mode)
4976 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4978 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4979 extend_op = SIGN_EXTEND;
4980 m = GET_MODE (XEXP (t, 0));
4982 else if (GET_CODE (t) == ZERO_EXTEND
4983 && (GET_CODE (XEXP (t, 0)) == PLUS
4984 || GET_CODE (XEXP (t, 0)) == MINUS
4985 || GET_CODE (XEXP (t, 0)) == IOR
4986 || GET_CODE (XEXP (t, 0)) == XOR
4987 || GET_CODE (XEXP (t, 0)) == ASHIFT
4988 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4989 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4990 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4991 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4992 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4993 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4994 && ((nonzero_bits (f, GET_MODE (f))
4995 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4998 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4999 extend_op = ZERO_EXTEND;
5000 m = GET_MODE (XEXP (t, 0));
5002 else if (GET_CODE (t) == ZERO_EXTEND
5003 && (GET_CODE (XEXP (t, 0)) == PLUS
5004 || GET_CODE (XEXP (t, 0)) == IOR
5005 || GET_CODE (XEXP (t, 0)) == XOR)
5006 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
5007 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5008 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
5009 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
5010 && ((nonzero_bits (f, GET_MODE (f))
5011 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
5014 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
5015 extend_op = ZERO_EXTEND;
5016 m = GET_MODE (XEXP (t, 0));
5021 temp = subst (gen_binary (true_code, m, cond_op0, cond_op1),
5022 pc_rtx, pc_rtx, 0, 0);
5023 temp = gen_binary (MULT, m, temp,
5024 gen_binary (MULT, m, c1, const_true_rtx));
5025 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
5026 temp = gen_binary (op, m, gen_lowpart (m, z), temp);
5028 if (extend_op != UNKNOWN)
5029 temp = simplify_gen_unary (extend_op, mode, temp, m);
5035 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
5036 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
5037 negation of a single bit, we can convert this operation to a shift. We
5038 can actually do this more generally, but it doesn't seem worth it. */
5040 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5041 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5042 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
5043 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
5044 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
5045 == GET_MODE_BITSIZE (mode))
5046 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
5048 simplify_shift_const (NULL_RTX, ASHIFT, mode,
5049 gen_lowpart (mode, XEXP (cond, 0)), i);
5051 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
5052 if (true_code == NE && XEXP (cond, 1) == const0_rtx
5053 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
5054 && GET_MODE (XEXP (cond, 0)) == mode
5055 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
5056 == nonzero_bits (XEXP (cond, 0), mode)
5057 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
5058 return XEXP (cond, 0);
5063 /* Simplify X, a SET expression. Return the new expression. */
5066 simplify_set (rtx x)
5068 rtx src = SET_SRC (x);
5069 rtx dest = SET_DEST (x);
5070 enum machine_mode mode
5071 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
5075 /* (set (pc) (return)) gets written as (return). */
5076 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
5079 /* Now that we know for sure which bits of SRC we are using, see if we can
5080 simplify the expression for the object knowing that we only need the
5083 if (GET_MODE_CLASS (mode) == MODE_INT
5084 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
5086 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, NULL_RTX, 0);
5087 SUBST (SET_SRC (x), src);
5090 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
5091 the comparison result and try to simplify it unless we already have used
5092 undobuf.other_insn. */
5093 if ((GET_MODE_CLASS (mode) == MODE_CC
5094 || GET_CODE (src) == COMPARE
5096 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
5097 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
5098 && COMPARISON_P (*cc_use)
5099 && rtx_equal_p (XEXP (*cc_use, 0), dest))
5101 enum rtx_code old_code = GET_CODE (*cc_use);
5102 enum rtx_code new_code;
5104 int other_changed = 0;
5105 enum machine_mode compare_mode = GET_MODE (dest);
5107 if (GET_CODE (src) == COMPARE)
5108 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
5110 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
5112 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
5115 new_code = old_code;
5116 else if (!CONSTANT_P (tmp))
5118 new_code = GET_CODE (tmp);
5119 op0 = XEXP (tmp, 0);
5120 op1 = XEXP (tmp, 1);
5124 rtx pat = PATTERN (other_insn);
5125 undobuf.other_insn = other_insn;
5126 SUBST (*cc_use, tmp);
5128 /* Attempt to simplify CC user. */
5129 if (GET_CODE (pat) == SET)
5131 rtx new = simplify_rtx (SET_SRC (pat));
5132 if (new != NULL_RTX)
5133 SUBST (SET_SRC (pat), new);
5136 /* Convert X into a no-op move. */
5137 SUBST (SET_DEST (x), pc_rtx);
5138 SUBST (SET_SRC (x), pc_rtx);
5142 /* Simplify our comparison, if possible. */
5143 new_code = simplify_comparison (new_code, &op0, &op1);
5145 #ifdef SELECT_CC_MODE
5146 /* If this machine has CC modes other than CCmode, check to see if we
5147 need to use a different CC mode here. */
5148 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
5149 compare_mode = GET_MODE (op0);
5151 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5154 /* If the mode changed, we have to change SET_DEST, the mode in the
5155 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5156 a hard register, just build new versions with the proper mode. If it
5157 is a pseudo, we lose unless it is only time we set the pseudo, in
5158 which case we can safely change its mode. */
5159 if (compare_mode != GET_MODE (dest))
5161 unsigned int regno = REGNO (dest);
5162 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5164 if (regno < FIRST_PSEUDO_REGISTER
5165 || (REG_N_SETS (regno) == 1 && ! REG_USERVAR_P (dest)))
5167 if (regno >= FIRST_PSEUDO_REGISTER)
5168 SUBST (regno_reg_rtx[regno], new_dest);
5170 SUBST (SET_DEST (x), new_dest);
5171 SUBST (XEXP (*cc_use, 0), new_dest);
5178 #endif /* SELECT_CC_MODE */
5180 /* If the code changed, we have to build a new comparison in
5181 undobuf.other_insn. */
5182 if (new_code != old_code)
5184 int other_changed_previously = other_changed;
5185 unsigned HOST_WIDE_INT mask;
5187 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5191 /* If the only change we made was to change an EQ into an NE or
5192 vice versa, OP0 has only one bit that might be nonzero, and OP1
5193 is zero, check if changing the user of the condition code will
5194 produce a valid insn. If it won't, we can keep the original code
5195 in that insn by surrounding our operation with an XOR. */
5197 if (((old_code == NE && new_code == EQ)
5198 || (old_code == EQ && new_code == NE))
5199 && ! other_changed_previously && op1 == const0_rtx
5200 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5201 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5203 rtx pat = PATTERN (other_insn), note = 0;
5205 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5206 && ! check_asm_operands (pat)))
5208 PUT_CODE (*cc_use, old_code);
5211 op0 = gen_binary (XOR, GET_MODE (op0), op0, GEN_INT (mask));
5217 undobuf.other_insn = other_insn;
5220 /* If we are now comparing against zero, change our source if
5221 needed. If we do not use cc0, we always have a COMPARE. */
5222 if (op1 == const0_rtx && dest == cc0_rtx)
5224 SUBST (SET_SRC (x), op0);
5230 /* Otherwise, if we didn't previously have a COMPARE in the
5231 correct mode, we need one. */
5232 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5234 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5239 /* Otherwise, update the COMPARE if needed. */
5240 SUBST (XEXP (src, 0), op0);
5241 SUBST (XEXP (src, 1), op1);
5246 /* Get SET_SRC in a form where we have placed back any
5247 compound expressions. Then do the checks below. */
5248 src = make_compound_operation (src, SET);
5249 SUBST (SET_SRC (x), src);
5252 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5253 and X being a REG or (subreg (reg)), we may be able to convert this to
5254 (set (subreg:m2 x) (op)).
5256 We can always do this if M1 is narrower than M2 because that means that
5257 we only care about the low bits of the result.
5259 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5260 perform a narrower operation than requested since the high-order bits will
5261 be undefined. On machine where it is defined, this transformation is safe
5262 as long as M1 and M2 have the same number of words. */
5264 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5265 && !OBJECT_P (SUBREG_REG (src))
5266 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5268 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5269 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5270 #ifndef WORD_REGISTER_OPERATIONS
5271 && (GET_MODE_SIZE (GET_MODE (src))
5272 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5274 #ifdef CANNOT_CHANGE_MODE_CLASS
5275 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5276 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5277 GET_MODE (SUBREG_REG (src)),
5281 || (GET_CODE (dest) == SUBREG
5282 && REG_P (SUBREG_REG (dest)))))
5284 SUBST (SET_DEST (x),
5285 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5287 SUBST (SET_SRC (x), SUBREG_REG (src));
5289 src = SET_SRC (x), dest = SET_DEST (x);
5293 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5296 && GET_CODE (src) == SUBREG
5297 && subreg_lowpart_p (src)
5298 && (GET_MODE_BITSIZE (GET_MODE (src))
5299 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5301 rtx inner = SUBREG_REG (src);
5302 enum machine_mode inner_mode = GET_MODE (inner);
5304 /* Here we make sure that we don't have a sign bit on. */
5305 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5306 && (nonzero_bits (inner, inner_mode)
5307 < ((unsigned HOST_WIDE_INT) 1
5308 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5310 SUBST (SET_SRC (x), inner);
5316 #ifdef LOAD_EXTEND_OP
5317 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5318 would require a paradoxical subreg. Replace the subreg with a
5319 zero_extend to avoid the reload that would otherwise be required. */
5321 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5322 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5323 && SUBREG_BYTE (src) == 0
5324 && (GET_MODE_SIZE (GET_MODE (src))
5325 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5326 && MEM_P (SUBREG_REG (src)))
5329 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5330 GET_MODE (src), SUBREG_REG (src)));
5336 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5337 are comparing an item known to be 0 or -1 against 0, use a logical
5338 operation instead. Check for one of the arms being an IOR of the other
5339 arm with some value. We compute three terms to be IOR'ed together. In
5340 practice, at most two will be nonzero. Then we do the IOR's. */
5342 if (GET_CODE (dest) != PC
5343 && GET_CODE (src) == IF_THEN_ELSE
5344 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5345 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5346 && XEXP (XEXP (src, 0), 1) == const0_rtx
5347 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5348 #ifdef HAVE_conditional_move
5349 && ! can_conditionally_move_p (GET_MODE (src))
5351 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5352 GET_MODE (XEXP (XEXP (src, 0), 0)))
5353 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5354 && ! side_effects_p (src))
5356 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5357 ? XEXP (src, 1) : XEXP (src, 2));
5358 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5359 ? XEXP (src, 2) : XEXP (src, 1));
5360 rtx term1 = const0_rtx, term2, term3;
5362 if (GET_CODE (true_rtx) == IOR
5363 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5364 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5365 else if (GET_CODE (true_rtx) == IOR
5366 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5367 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5368 else if (GET_CODE (false_rtx) == IOR
5369 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5370 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5371 else if (GET_CODE (false_rtx) == IOR
5372 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5373 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5375 term2 = gen_binary (AND, GET_MODE (src),
5376 XEXP (XEXP (src, 0), 0), true_rtx);
5377 term3 = gen_binary (AND, GET_MODE (src),
5378 simplify_gen_unary (NOT, GET_MODE (src),
5379 XEXP (XEXP (src, 0), 0),
5384 gen_binary (IOR, GET_MODE (src),
5385 gen_binary (IOR, GET_MODE (src), term1, term2),
5391 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5392 whole thing fail. */
5393 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5395 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5398 /* Convert this into a field assignment operation, if possible. */
5399 return make_field_assignment (x);
5402 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5406 simplify_logical (rtx x)
5408 enum machine_mode mode = GET_MODE (x);
5409 rtx op0 = XEXP (x, 0);
5410 rtx op1 = XEXP (x, 1);
5413 switch (GET_CODE (x))
5416 /* Convert (A ^ B) & A to A & (~B) since the latter is often a single
5417 insn (and may simplify more). */
5418 if (GET_CODE (op0) == XOR
5419 && rtx_equal_p (XEXP (op0, 0), op1)
5420 && ! side_effects_p (op1))
5421 x = gen_binary (AND, mode,
5422 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5425 if (GET_CODE (op0) == XOR
5426 && rtx_equal_p (XEXP (op0, 1), op1)
5427 && ! side_effects_p (op1))
5428 x = gen_binary (AND, mode,
5429 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5432 /* Similarly for (~(A ^ B)) & A. */
5433 if (GET_CODE (op0) == NOT
5434 && GET_CODE (XEXP (op0, 0)) == XOR
5435 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), op1)
5436 && ! side_effects_p (op1))
5437 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 1), op1);
5439 if (GET_CODE (op0) == NOT
5440 && GET_CODE (XEXP (op0, 0)) == XOR
5441 && rtx_equal_p (XEXP (XEXP (op0, 0), 1), op1)
5442 && ! side_effects_p (op1))
5443 x = gen_binary (AND, mode, XEXP (XEXP (op0, 0), 0), op1);
5445 /* We can call simplify_and_const_int only if we don't lose
5446 any (sign) bits when converting INTVAL (op1) to
5447 "unsigned HOST_WIDE_INT". */
5448 if (GET_CODE (op1) == CONST_INT
5449 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5450 || INTVAL (op1) > 0))
5452 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5454 /* If we have (ior (and (X C1) C2)) and the next restart would be
5455 the last, simplify this by making C1 as small as possible
5456 and then exit. Only do this if C1 actually changes: for now
5457 this only saves memory but, should this transformation be
5458 moved to simplify-rtx.c, we'd risk unbounded recursion there. */
5459 if (GET_CODE (x) == IOR && GET_CODE (op0) == AND
5460 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5461 && GET_CODE (op1) == CONST_INT
5462 && (INTVAL (XEXP (op0, 1)) & INTVAL (op1)) != 0)
5463 return gen_binary (IOR, mode,
5464 gen_binary (AND, mode, XEXP (op0, 0),
5465 GEN_INT (INTVAL (XEXP (op0, 1))
5466 & ~INTVAL (op1))), op1);
5468 if (GET_CODE (x) != AND)
5475 /* Convert (A | B) & A to A. */
5476 if (GET_CODE (op0) == IOR
5477 && (rtx_equal_p (XEXP (op0, 0), op1)
5478 || rtx_equal_p (XEXP (op0, 1), op1))
5479 && ! side_effects_p (XEXP (op0, 0))
5480 && ! side_effects_p (XEXP (op0, 1)))
5483 /* In the following group of tests (and those in case IOR below),
5484 we start with some combination of logical operations and apply
5485 the distributive law followed by the inverse distributive law.
5486 Most of the time, this results in no change. However, if some of
5487 the operands are the same or inverses of each other, simplifications
5490 For example, (and (ior A B) (not B)) can occur as the result of
5491 expanding a bit field assignment. When we apply the distributive
5492 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5493 which then simplifies to (and (A (not B))).
5495 If we have (and (ior A B) C), apply the distributive law and then
5496 the inverse distributive law to see if things simplify. */
5498 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5500 x = apply_distributive_law
5501 (gen_binary (GET_CODE (op0), mode,
5502 gen_binary (AND, mode, XEXP (op0, 0), op1),
5503 gen_binary (AND, mode, XEXP (op0, 1),
5505 if (GET_CODE (x) != AND)
5509 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5510 return apply_distributive_law
5511 (gen_binary (GET_CODE (op1), mode,
5512 gen_binary (AND, mode, XEXP (op1, 0), op0),
5513 gen_binary (AND, mode, XEXP (op1, 1),
5516 /* Similarly, taking advantage of the fact that
5517 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5519 if (GET_CODE (op0) == NOT && GET_CODE (op1) == XOR)
5520 return apply_distributive_law
5521 (gen_binary (XOR, mode,
5522 gen_binary (IOR, mode, XEXP (op0, 0), XEXP (op1, 0)),
5523 gen_binary (IOR, mode, copy_rtx (XEXP (op0, 0)),
5526 else if (GET_CODE (op1) == NOT && GET_CODE (op0) == XOR)
5527 return apply_distributive_law
5528 (gen_binary (XOR, mode,
5529 gen_binary (IOR, mode, XEXP (op1, 0), XEXP (op0, 0)),
5530 gen_binary (IOR, mode, copy_rtx (XEXP (op1, 0)), XEXP (op0, 1))));
5534 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5535 if (GET_CODE (op1) == CONST_INT
5536 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5537 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
5540 /* Convert (A & B) | A to A. */
5541 if (GET_CODE (op0) == AND
5542 && (rtx_equal_p (XEXP (op0, 0), op1)
5543 || rtx_equal_p (XEXP (op0, 1), op1))
5544 && ! side_effects_p (XEXP (op0, 0))
5545 && ! side_effects_p (XEXP (op0, 1)))
5548 /* If we have (ior (and A B) C), apply the distributive law and then
5549 the inverse distributive law to see if things simplify. */
5551 if (GET_CODE (op0) == AND)
5553 x = apply_distributive_law
5554 (gen_binary (AND, mode,
5555 gen_binary (IOR, mode, XEXP (op0, 0), op1),
5556 gen_binary (IOR, mode, XEXP (op0, 1),
5559 if (GET_CODE (x) != IOR)
5563 if (GET_CODE (op1) == AND)
5565 x = apply_distributive_law
5566 (gen_binary (AND, mode,
5567 gen_binary (IOR, mode, XEXP (op1, 0), op0),
5568 gen_binary (IOR, mode, XEXP (op1, 1),
5571 if (GET_CODE (x) != IOR)
5575 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5576 mode size to (rotate A CX). */
5578 if (((GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
5579 || (GET_CODE (op1) == ASHIFT && GET_CODE (op0) == LSHIFTRT))
5580 && rtx_equal_p (XEXP (op0, 0), XEXP (op1, 0))
5581 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5582 && GET_CODE (XEXP (op1, 1)) == CONST_INT
5583 && (INTVAL (XEXP (op0, 1)) + INTVAL (XEXP (op1, 1))
5584 == GET_MODE_BITSIZE (mode)))
5585 return gen_rtx_ROTATE (mode, XEXP (op0, 0),
5586 (GET_CODE (op0) == ASHIFT
5587 ? XEXP (op0, 1) : XEXP (op1, 1)));
5589 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5590 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5591 does not affect any of the bits in OP1, it can really be done
5592 as a PLUS and we can associate. We do this by seeing if OP1
5593 can be safely shifted left C bits. */
5594 if (GET_CODE (op1) == CONST_INT && GET_CODE (op0) == ASHIFTRT
5595 && GET_CODE (XEXP (op0, 0)) == PLUS
5596 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
5597 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5598 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT)
5600 int count = INTVAL (XEXP (op0, 1));
5601 HOST_WIDE_INT mask = INTVAL (op1) << count;
5603 if (mask >> count == INTVAL (op1)
5604 && (mask & nonzero_bits (XEXP (op0, 0), mode)) == 0)
5606 SUBST (XEXP (XEXP (op0, 0), 1),
5607 GEN_INT (INTVAL (XEXP (XEXP (op0, 0), 1)) | mask));
5614 /* If we are XORing two things that have no bits in common,
5615 convert them into an IOR. This helps to detect rotation encoded
5616 using those methods and possibly other simplifications. */
5618 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5619 && (nonzero_bits (op0, mode)
5620 & nonzero_bits (op1, mode)) == 0)
5621 return (gen_binary (IOR, mode, op0, op1));
5623 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5624 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5627 int num_negated = 0;
5629 if (GET_CODE (op0) == NOT)
5630 num_negated++, op0 = XEXP (op0, 0);
5631 if (GET_CODE (op1) == NOT)
5632 num_negated++, op1 = XEXP (op1, 0);
5634 if (num_negated == 2)
5636 SUBST (XEXP (x, 0), op0);
5637 SUBST (XEXP (x, 1), op1);
5639 else if (num_negated == 1)
5641 simplify_gen_unary (NOT, mode, gen_binary (XOR, mode, op0, op1),
5645 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5646 correspond to a machine insn or result in further simplifications
5647 if B is a constant. */
5649 if (GET_CODE (op0) == AND
5650 && rtx_equal_p (XEXP (op0, 1), op1)
5651 && ! side_effects_p (op1))
5652 return gen_binary (AND, mode,
5653 simplify_gen_unary (NOT, mode, XEXP (op0, 0), mode),
5656 else if (GET_CODE (op0) == AND
5657 && rtx_equal_p (XEXP (op0, 0), op1)
5658 && ! side_effects_p (op1))
5659 return gen_binary (AND, mode,
5660 simplify_gen_unary (NOT, mode, XEXP (op0, 1), mode),
5663 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5664 comparison if STORE_FLAG_VALUE is 1. */
5665 if (STORE_FLAG_VALUE == 1
5666 && op1 == const1_rtx
5667 && COMPARISON_P (op0)
5668 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5672 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5673 is (lt foo (const_int 0)), so we can perform the above
5674 simplification if STORE_FLAG_VALUE is 1. */
5676 if (STORE_FLAG_VALUE == 1
5677 && op1 == const1_rtx
5678 && GET_CODE (op0) == LSHIFTRT
5679 && GET_CODE (XEXP (op0, 1)) == CONST_INT
5680 && INTVAL (XEXP (op0, 1)) == GET_MODE_BITSIZE (mode) - 1)
5681 return gen_rtx_GE (mode, XEXP (op0, 0), const0_rtx);
5683 /* (xor (comparison foo bar) (const_int sign-bit))
5684 when STORE_FLAG_VALUE is the sign bit. */
5685 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5686 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
5687 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
5688 && op1 == const_true_rtx
5689 && COMPARISON_P (op0)
5690 && (reversed = reversed_comparison (op0, mode, XEXP (op0, 0),
5703 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5704 operations" because they can be replaced with two more basic operations.
5705 ZERO_EXTEND is also considered "compound" because it can be replaced with
5706 an AND operation, which is simpler, though only one operation.
5708 The function expand_compound_operation is called with an rtx expression
5709 and will convert it to the appropriate shifts and AND operations,
5710 simplifying at each stage.
5712 The function make_compound_operation is called to convert an expression
5713 consisting of shifts and ANDs into the equivalent compound expression.
5714 It is the inverse of this function, loosely speaking. */
5717 expand_compound_operation (rtx x)
5719 unsigned HOST_WIDE_INT pos = 0, len;
5721 unsigned int modewidth;
5724 switch (GET_CODE (x))
5729 /* We can't necessarily use a const_int for a multiword mode;
5730 it depends on implicitly extending the value.
5731 Since we don't know the right way to extend it,
5732 we can't tell whether the implicit way is right.
5734 Even for a mode that is no wider than a const_int,
5735 we can't win, because we need to sign extend one of its bits through
5736 the rest of it, and we don't know which bit. */
5737 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5740 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5741 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5742 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5743 reloaded. If not for that, MEM's would very rarely be safe.
5745 Reject MODEs bigger than a word, because we might not be able
5746 to reference a two-register group starting with an arbitrary register
5747 (and currently gen_lowpart might crash for a SUBREG). */
5749 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5752 /* Reject MODEs that aren't scalar integers because turning vector
5753 or complex modes into shifts causes problems. */
5755 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5758 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5759 /* If the inner object has VOIDmode (the only way this can happen
5760 is if it is an ASM_OPERANDS), we can't do anything since we don't
5761 know how much masking to do. */
5770 /* If the operand is a CLOBBER, just return it. */
5771 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5774 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5775 || GET_CODE (XEXP (x, 2)) != CONST_INT
5776 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5779 /* Reject MODEs that aren't scalar integers because turning vector
5780 or complex modes into shifts causes problems. */
5782 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5785 len = INTVAL (XEXP (x, 1));
5786 pos = INTVAL (XEXP (x, 2));
5788 /* If this goes outside the object being extracted, replace the object
5789 with a (use (mem ...)) construct that only combine understands
5790 and is used only for this purpose. */
5791 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5792 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5794 if (BITS_BIG_ENDIAN)
5795 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5802 /* Convert sign extension to zero extension, if we know that the high
5803 bit is not set, as this is easier to optimize. It will be converted
5804 back to cheaper alternative in make_extraction. */
5805 if (GET_CODE (x) == SIGN_EXTEND
5806 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5807 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5808 & ~(((unsigned HOST_WIDE_INT)
5809 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5813 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5814 rtx temp2 = expand_compound_operation (temp);
5816 /* Make sure this is a profitable operation. */
5817 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5819 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5825 /* We can optimize some special cases of ZERO_EXTEND. */
5826 if (GET_CODE (x) == ZERO_EXTEND)
5828 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5829 know that the last value didn't have any inappropriate bits
5831 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5832 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5833 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5834 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5835 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5836 return XEXP (XEXP (x, 0), 0);
5838 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5839 if (GET_CODE (XEXP (x, 0)) == SUBREG
5840 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5841 && subreg_lowpart_p (XEXP (x, 0))
5842 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5843 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5844 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5845 return SUBREG_REG (XEXP (x, 0));
5847 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5848 is a comparison and STORE_FLAG_VALUE permits. This is like
5849 the first case, but it works even when GET_MODE (x) is larger
5850 than HOST_WIDE_INT. */
5851 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5852 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5853 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5854 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5855 <= HOST_BITS_PER_WIDE_INT)
5856 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5857 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5858 return XEXP (XEXP (x, 0), 0);
5860 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5861 if (GET_CODE (XEXP (x, 0)) == SUBREG
5862 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5863 && subreg_lowpart_p (XEXP (x, 0))
5864 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5865 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5866 <= HOST_BITS_PER_WIDE_INT)
5867 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5868 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5869 return SUBREG_REG (XEXP (x, 0));
5873 /* If we reach here, we want to return a pair of shifts. The inner
5874 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5875 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5876 logical depending on the value of UNSIGNEDP.
5878 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5879 converted into an AND of a shift.
5881 We must check for the case where the left shift would have a negative
5882 count. This can happen in a case like (x >> 31) & 255 on machines
5883 that can't shift by a constant. On those machines, we would first
5884 combine the shift with the AND to produce a variable-position
5885 extraction. Then the constant of 31 would be substituted in to produce
5886 a such a position. */
5888 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5889 if (modewidth + len >= pos)
5890 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5892 simplify_shift_const (NULL_RTX, ASHIFT,
5895 modewidth - pos - len),
5898 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5899 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5900 simplify_shift_const (NULL_RTX, LSHIFTRT,
5903 ((HOST_WIDE_INT) 1 << len) - 1);
5905 /* Any other cases we can't handle. */
5908 /* If we couldn't do this for some reason, return the original
5910 if (GET_CODE (tem) == CLOBBER)
5916 /* X is a SET which contains an assignment of one object into
5917 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5918 or certain SUBREGS). If possible, convert it into a series of
5921 We half-heartedly support variable positions, but do not at all
5922 support variable lengths. */
5925 expand_field_assignment (rtx x)
5928 rtx pos; /* Always counts from low bit. */
5931 enum machine_mode compute_mode;
5933 /* Loop until we find something we can't simplify. */
5936 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5937 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5939 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5940 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5941 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5943 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5944 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5946 inner = XEXP (SET_DEST (x), 0);
5947 len = INTVAL (XEXP (SET_DEST (x), 1));
5948 pos = XEXP (SET_DEST (x), 2);
5950 /* If the position is constant and spans the width of INNER,
5951 surround INNER with a USE to indicate this. */
5952 if (GET_CODE (pos) == CONST_INT
5953 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5954 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5956 if (BITS_BIG_ENDIAN)
5958 if (GET_CODE (pos) == CONST_INT)
5959 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5961 else if (GET_CODE (pos) == MINUS
5962 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5963 && (INTVAL (XEXP (pos, 1))
5964 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5965 /* If position is ADJUST - X, new position is X. */
5966 pos = XEXP (pos, 0);
5968 pos = gen_binary (MINUS, GET_MODE (pos),
5969 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner))
5975 /* A SUBREG between two modes that occupy the same numbers of words
5976 can be done by moving the SUBREG to the source. */
5977 else if (GET_CODE (SET_DEST (x)) == SUBREG
5978 /* We need SUBREGs to compute nonzero_bits properly. */
5979 && nonzero_sign_valid
5980 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5981 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5982 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5983 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5985 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5987 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5994 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5995 inner = SUBREG_REG (inner);
5997 compute_mode = GET_MODE (inner);
5999 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
6000 if (! SCALAR_INT_MODE_P (compute_mode))
6002 enum machine_mode imode;
6004 /* Don't do anything for vector or complex integral types. */
6005 if (! FLOAT_MODE_P (compute_mode))
6008 /* Try to find an integral mode to pun with. */
6009 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
6010 if (imode == BLKmode)
6013 compute_mode = imode;
6014 inner = gen_lowpart (imode, inner);
6017 /* Compute a mask of LEN bits, if we can do this on the host machine. */
6018 if (len < HOST_BITS_PER_WIDE_INT)
6019 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
6023 /* Now compute the equivalent expression. Make a copy of INNER
6024 for the SET_DEST in case it is a MEM into which we will substitute;
6025 we don't want shared RTL in that case. */
6027 (VOIDmode, copy_rtx (inner),
6028 gen_binary (IOR, compute_mode,
6029 gen_binary (AND, compute_mode,
6030 simplify_gen_unary (NOT, compute_mode,
6036 gen_binary (ASHIFT, compute_mode,
6037 gen_binary (AND, compute_mode,
6039 (compute_mode, SET_SRC (x)),
6047 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
6048 it is an RTX that represents a variable starting position; otherwise,
6049 POS is the (constant) starting bit position (counted from the LSB).
6051 INNER may be a USE. This will occur when we started with a bitfield
6052 that went outside the boundary of the object in memory, which is
6053 allowed on most machines. To isolate this case, we produce a USE
6054 whose mode is wide enough and surround the MEM with it. The only
6055 code that understands the USE is this routine. If it is not removed,
6056 it will cause the resulting insn not to match.
6058 UNSIGNEDP is nonzero for an unsigned reference and zero for a
6061 IN_DEST is nonzero if this is a reference in the destination of a
6062 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
6063 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
6066 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
6067 ZERO_EXTRACT should be built even for bits starting at bit 0.
6069 MODE is the desired mode of the result (if IN_DEST == 0).
6071 The result is an RTX for the extraction or NULL_RTX if the target
6075 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
6076 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
6077 int in_dest, int in_compare)
6079 /* This mode describes the size of the storage area
6080 to fetch the overall value from. Within that, we
6081 ignore the POS lowest bits, etc. */
6082 enum machine_mode is_mode = GET_MODE (inner);
6083 enum machine_mode inner_mode;
6084 enum machine_mode wanted_inner_mode = byte_mode;
6085 enum machine_mode wanted_inner_reg_mode = word_mode;
6086 enum machine_mode pos_mode = word_mode;
6087 enum machine_mode extraction_mode = word_mode;
6088 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
6091 rtx orig_pos_rtx = pos_rtx;
6092 HOST_WIDE_INT orig_pos;
6094 /* Get some information about INNER and get the innermost object. */
6095 if (GET_CODE (inner) == USE)
6096 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
6097 /* We don't need to adjust the position because we set up the USE
6098 to pretend that it was a full-word object. */
6099 spans_byte = 1, inner = XEXP (inner, 0);
6100 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6102 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
6103 consider just the QI as the memory to extract from.
6104 The subreg adds or removes high bits; its mode is
6105 irrelevant to the meaning of this extraction,
6106 since POS and LEN count from the lsb. */
6107 if (MEM_P (SUBREG_REG (inner)))
6108 is_mode = GET_MODE (SUBREG_REG (inner));
6109 inner = SUBREG_REG (inner);
6111 else if (GET_CODE (inner) == ASHIFT
6112 && GET_CODE (XEXP (inner, 1)) == CONST_INT
6113 && pos_rtx == 0 && pos == 0
6114 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
6116 /* We're extracting the least significant bits of an rtx
6117 (ashift X (const_int C)), where LEN > C. Extract the
6118 least significant (LEN - C) bits of X, giving an rtx
6119 whose mode is MODE, then shift it left C times. */
6120 new = make_extraction (mode, XEXP (inner, 0),
6121 0, 0, len - INTVAL (XEXP (inner, 1)),
6122 unsignedp, in_dest, in_compare);
6124 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
6127 inner_mode = GET_MODE (inner);
6129 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
6130 pos = INTVAL (pos_rtx), pos_rtx = 0;
6132 /* See if this can be done without an extraction. We never can if the
6133 width of the field is not the same as that of some integer mode. For
6134 registers, we can only avoid the extraction if the position is at the
6135 low-order bit and this is either not in the destination or we have the
6136 appropriate STRICT_LOW_PART operation available.
6138 For MEM, we can avoid an extract if the field starts on an appropriate
6139 boundary and we can change the mode of the memory reference. However,
6140 we cannot directly access the MEM if we have a USE and the underlying
6141 MEM is not TMODE. This combination means that MEM was being used in a
6142 context where bits outside its mode were being referenced; that is only
6143 valid in bit-field insns. */
6145 if (tmode != BLKmode
6146 && ! (spans_byte && inner_mode != tmode)
6147 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
6151 && have_insn_for (STRICT_LOW_PART, tmode))))
6152 || (MEM_P (inner) && pos_rtx == 0
6154 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
6155 : BITS_PER_UNIT)) == 0
6156 /* We can't do this if we are widening INNER_MODE (it
6157 may not be aligned, for one thing). */
6158 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
6159 && (inner_mode == tmode
6160 || (! mode_dependent_address_p (XEXP (inner, 0))
6161 && ! MEM_VOLATILE_P (inner))))))
6163 /* If INNER is a MEM, make a new MEM that encompasses just the desired
6164 field. If the original and current mode are the same, we need not
6165 adjust the offset. Otherwise, we do if bytes big endian.
6167 If INNER is not a MEM, get a piece consisting of just the field
6168 of interest (in this case POS % BITS_PER_WORD must be 0). */
6172 HOST_WIDE_INT offset;
6174 /* POS counts from lsb, but make OFFSET count in memory order. */
6175 if (BYTES_BIG_ENDIAN)
6176 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
6178 offset = pos / BITS_PER_UNIT;
6180 new = adjust_address_nv (inner, tmode, offset);
6182 else if (REG_P (inner))
6184 if (tmode != inner_mode)
6186 /* We can't call gen_lowpart in a DEST since we
6187 always want a SUBREG (see below) and it would sometimes
6188 return a new hard register. */
6191 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
6193 if (WORDS_BIG_ENDIAN
6194 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
6195 final_word = ((GET_MODE_SIZE (inner_mode)
6196 - GET_MODE_SIZE (tmode))
6197 / UNITS_PER_WORD) - final_word;
6199 final_word *= UNITS_PER_WORD;
6200 if (BYTES_BIG_ENDIAN &&
6201 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
6202 final_word += (GET_MODE_SIZE (inner_mode)
6203 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
6205 /* Avoid creating invalid subregs, for example when
6206 simplifying (x>>32)&255. */
6207 if (final_word >= GET_MODE_SIZE (inner_mode))
6210 new = gen_rtx_SUBREG (tmode, inner, final_word);
6213 new = gen_lowpart (tmode, inner);
6219 new = force_to_mode (inner, tmode,
6220 len >= HOST_BITS_PER_WIDE_INT
6221 ? ~(unsigned HOST_WIDE_INT) 0
6222 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
6225 /* If this extraction is going into the destination of a SET,
6226 make a STRICT_LOW_PART unless we made a MEM. */
6229 return (MEM_P (new) ? new
6230 : (GET_CODE (new) != SUBREG
6231 ? gen_rtx_CLOBBER (tmode, const0_rtx)
6232 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
6237 if (GET_CODE (new) == CONST_INT)
6238 return gen_int_mode (INTVAL (new), mode);
6240 /* If we know that no extraneous bits are set, and that the high
6241 bit is not set, convert the extraction to the cheaper of
6242 sign and zero extension, that are equivalent in these cases. */
6243 if (flag_expensive_optimizations
6244 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
6245 && ((nonzero_bits (new, tmode)
6246 & ~(((unsigned HOST_WIDE_INT)
6247 GET_MODE_MASK (tmode))
6251 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
6252 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
6254 /* Prefer ZERO_EXTENSION, since it gives more information to
6256 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
6261 /* Otherwise, sign- or zero-extend unless we already are in the
6264 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
6268 /* Unless this is a COMPARE or we have a funny memory reference,
6269 don't do anything with zero-extending field extracts starting at
6270 the low-order bit since they are simple AND operations. */
6271 if (pos_rtx == 0 && pos == 0 && ! in_dest
6272 && ! in_compare && ! spans_byte && unsignedp)
6275 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
6276 we would be spanning bytes or if the position is not a constant and the
6277 length is not 1. In all other cases, we would only be going outside
6278 our object in cases when an original shift would have been
6280 if (! spans_byte && MEM_P (inner)
6281 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
6282 || (pos_rtx != 0 && len != 1)))
6285 /* Get the mode to use should INNER not be a MEM, the mode for the position,
6286 and the mode for the result. */
6287 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
6289 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
6290 pos_mode = mode_for_extraction (EP_insv, 2);
6291 extraction_mode = mode_for_extraction (EP_insv, 3);
6294 if (! in_dest && unsignedp
6295 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
6297 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
6298 pos_mode = mode_for_extraction (EP_extzv, 3);
6299 extraction_mode = mode_for_extraction (EP_extzv, 0);
6302 if (! in_dest && ! unsignedp
6303 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
6305 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
6306 pos_mode = mode_for_extraction (EP_extv, 3);
6307 extraction_mode = mode_for_extraction (EP_extv, 0);
6310 /* Never narrow an object, since that might not be safe. */
6312 if (mode != VOIDmode
6313 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
6314 extraction_mode = mode;
6316 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
6317 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6318 pos_mode = GET_MODE (pos_rtx);
6320 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6321 if we have to change the mode of memory and cannot, the desired mode is
6324 wanted_inner_mode = wanted_inner_reg_mode;
6325 else if (inner_mode != wanted_inner_mode
6326 && (mode_dependent_address_p (XEXP (inner, 0))
6327 || MEM_VOLATILE_P (inner)))
6328 wanted_inner_mode = extraction_mode;
6332 if (BITS_BIG_ENDIAN)
6334 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6335 BITS_BIG_ENDIAN style. If position is constant, compute new
6336 position. Otherwise, build subtraction.
6337 Note that POS is relative to the mode of the original argument.
6338 If it's a MEM we need to recompute POS relative to that.
6339 However, if we're extracting from (or inserting into) a register,
6340 we want to recompute POS relative to wanted_inner_mode. */
6341 int width = (MEM_P (inner)
6342 ? GET_MODE_BITSIZE (is_mode)
6343 : GET_MODE_BITSIZE (wanted_inner_mode));
6346 pos = width - len - pos;
6349 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
6350 /* POS may be less than 0 now, but we check for that below.
6351 Note that it can only be less than 0 if !MEM_P (inner). */
6354 /* If INNER has a wider mode, make it smaller. If this is a constant
6355 extract, try to adjust the byte to point to the byte containing
6357 if (wanted_inner_mode != VOIDmode
6358 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
6360 && (inner_mode == wanted_inner_mode
6361 || (! mode_dependent_address_p (XEXP (inner, 0))
6362 && ! MEM_VOLATILE_P (inner))))))
6366 /* The computations below will be correct if the machine is big
6367 endian in both bits and bytes or little endian in bits and bytes.
6368 If it is mixed, we must adjust. */
6370 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6371 adjust OFFSET to compensate. */
6372 if (BYTES_BIG_ENDIAN
6374 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6375 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6377 /* If this is a constant position, we can move to the desired byte. */
6380 offset += pos / BITS_PER_UNIT;
6381 pos %= GET_MODE_BITSIZE (wanted_inner_mode);
6384 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6386 && is_mode != wanted_inner_mode)
6387 offset = (GET_MODE_SIZE (is_mode)
6388 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6390 if (offset != 0 || inner_mode != wanted_inner_mode)
6391 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6394 /* If INNER is not memory, we can always get it into the proper mode. If we
6395 are changing its mode, POS must be a constant and smaller than the size
6397 else if (!MEM_P (inner))
6399 if (GET_MODE (inner) != wanted_inner_mode
6401 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6404 inner = force_to_mode (inner, wanted_inner_mode,
6406 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6407 ? ~(unsigned HOST_WIDE_INT) 0
6408 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6413 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6414 have to zero extend. Otherwise, we can just use a SUBREG. */
6416 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6418 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6420 /* If we know that no extraneous bits are set, and that the high
6421 bit is not set, convert extraction to cheaper one - either
6422 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6424 if (flag_expensive_optimizations
6425 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6426 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6427 & ~(((unsigned HOST_WIDE_INT)
6428 GET_MODE_MASK (GET_MODE (pos_rtx)))
6432 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6434 /* Prefer ZERO_EXTENSION, since it gives more information to
6436 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6441 else if (pos_rtx != 0
6442 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6443 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6445 /* Make POS_RTX unless we already have it and it is correct. If we don't
6446 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6448 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6449 pos_rtx = orig_pos_rtx;
6451 else if (pos_rtx == 0)
6452 pos_rtx = GEN_INT (pos);
6454 /* Make the required operation. See if we can use existing rtx. */
6455 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6456 extraction_mode, inner, GEN_INT (len), pos_rtx);
6458 new = gen_lowpart (mode, new);
6463 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6464 with any other operations in X. Return X without that shift if so. */
6467 extract_left_shift (rtx x, int count)
6469 enum rtx_code code = GET_CODE (x);
6470 enum machine_mode mode = GET_MODE (x);
6476 /* This is the shift itself. If it is wide enough, we will return
6477 either the value being shifted if the shift count is equal to
6478 COUNT or a shift for the difference. */
6479 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6480 && INTVAL (XEXP (x, 1)) >= count)
6481 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6482 INTVAL (XEXP (x, 1)) - count);
6486 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6487 return simplify_gen_unary (code, mode, tem, mode);
6491 case PLUS: case IOR: case XOR: case AND:
6492 /* If we can safely shift this constant and we find the inner shift,
6493 make a new operation. */
6494 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6495 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6496 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6497 return gen_binary (code, mode, tem,
6498 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6509 /* Look at the expression rooted at X. Look for expressions
6510 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6511 Form these expressions.
6513 Return the new rtx, usually just X.
6515 Also, for machines like the VAX that don't have logical shift insns,
6516 try to convert logical to arithmetic shift operations in cases where
6517 they are equivalent. This undoes the canonicalizations to logical
6518 shifts done elsewhere.
6520 We try, as much as possible, to re-use rtl expressions to save memory.
6522 IN_CODE says what kind of expression we are processing. Normally, it is
6523 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6524 being kludges), it is MEM. When processing the arguments of a comparison
6525 or a COMPARE against zero, it is COMPARE. */
6528 make_compound_operation (rtx x, enum rtx_code in_code)
6530 enum rtx_code code = GET_CODE (x);
6531 enum machine_mode mode = GET_MODE (x);
6532 int mode_width = GET_MODE_BITSIZE (mode);
6534 enum rtx_code next_code;
6540 /* Select the code to be used in recursive calls. Once we are inside an
6541 address, we stay there. If we have a comparison, set to COMPARE,
6542 but once inside, go back to our default of SET. */
6544 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6545 : ((code == COMPARE || COMPARISON_P (x))
6546 && XEXP (x, 1) == const0_rtx) ? COMPARE
6547 : in_code == COMPARE ? SET : in_code);
6549 /* Process depending on the code of this operation. If NEW is set
6550 nonzero, it will be returned. */
6555 /* Convert shifts by constants into multiplications if inside
6557 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6558 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6559 && INTVAL (XEXP (x, 1)) >= 0)
6561 new = make_compound_operation (XEXP (x, 0), next_code);
6562 new = gen_rtx_MULT (mode, new,
6563 GEN_INT ((HOST_WIDE_INT) 1
6564 << INTVAL (XEXP (x, 1))));
6569 /* If the second operand is not a constant, we can't do anything
6571 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6574 /* If the constant is a power of two minus one and the first operand
6575 is a logical right shift, make an extraction. */
6576 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6577 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6579 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6580 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6581 0, in_code == COMPARE);
6584 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6585 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6586 && subreg_lowpart_p (XEXP (x, 0))
6587 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6588 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6590 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6592 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6593 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6594 0, in_code == COMPARE);
6596 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6597 else if ((GET_CODE (XEXP (x, 0)) == XOR
6598 || GET_CODE (XEXP (x, 0)) == IOR)
6599 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6600 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6601 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6603 /* Apply the distributive law, and then try to make extractions. */
6604 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6605 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6607 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6609 new = make_compound_operation (new, in_code);
6612 /* If we are have (and (rotate X C) M) and C is larger than the number
6613 of bits in M, this is an extraction. */
6615 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6616 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6617 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6618 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6620 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6621 new = make_extraction (mode, new,
6622 (GET_MODE_BITSIZE (mode)
6623 - INTVAL (XEXP (XEXP (x, 0), 1))),
6624 NULL_RTX, i, 1, 0, in_code == COMPARE);
6627 /* On machines without logical shifts, if the operand of the AND is
6628 a logical shift and our mask turns off all the propagated sign
6629 bits, we can replace the logical shift with an arithmetic shift. */
6630 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6631 && !have_insn_for (LSHIFTRT, mode)
6632 && have_insn_for (ASHIFTRT, mode)
6633 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6634 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6635 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6636 && mode_width <= HOST_BITS_PER_WIDE_INT)
6638 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6640 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6641 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6643 gen_rtx_ASHIFTRT (mode,
6644 make_compound_operation
6645 (XEXP (XEXP (x, 0), 0), next_code),
6646 XEXP (XEXP (x, 0), 1)));
6649 /* If the constant is one less than a power of two, this might be
6650 representable by an extraction even if no shift is present.
6651 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6652 we are in a COMPARE. */
6653 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6654 new = make_extraction (mode,
6655 make_compound_operation (XEXP (x, 0),
6657 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6659 /* If we are in a comparison and this is an AND with a power of two,
6660 convert this into the appropriate bit extract. */
6661 else if (in_code == COMPARE
6662 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6663 new = make_extraction (mode,
6664 make_compound_operation (XEXP (x, 0),
6666 i, NULL_RTX, 1, 1, 0, 1);
6671 /* If the sign bit is known to be zero, replace this with an
6672 arithmetic shift. */
6673 if (have_insn_for (ASHIFTRT, mode)
6674 && ! have_insn_for (LSHIFTRT, mode)
6675 && mode_width <= HOST_BITS_PER_WIDE_INT
6676 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6678 new = gen_rtx_ASHIFTRT (mode,
6679 make_compound_operation (XEXP (x, 0),
6685 /* ... fall through ... */
6691 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6692 this is a SIGN_EXTRACT. */
6693 if (GET_CODE (rhs) == CONST_INT
6694 && GET_CODE (lhs) == ASHIFT
6695 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6696 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6698 new = make_compound_operation (XEXP (lhs, 0), next_code);
6699 new = make_extraction (mode, new,
6700 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6701 NULL_RTX, mode_width - INTVAL (rhs),
6702 code == LSHIFTRT, 0, in_code == COMPARE);
6706 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6707 If so, try to merge the shifts into a SIGN_EXTEND. We could
6708 also do this for some cases of SIGN_EXTRACT, but it doesn't
6709 seem worth the effort; the case checked for occurs on Alpha. */
6712 && ! (GET_CODE (lhs) == SUBREG
6713 && (OBJECT_P (SUBREG_REG (lhs))))
6714 && GET_CODE (rhs) == CONST_INT
6715 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6716 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6717 new = make_extraction (mode, make_compound_operation (new, next_code),
6718 0, NULL_RTX, mode_width - INTVAL (rhs),
6719 code == LSHIFTRT, 0, in_code == COMPARE);
6724 /* Call ourselves recursively on the inner expression. If we are
6725 narrowing the object and it has a different RTL code from
6726 what it originally did, do this SUBREG as a force_to_mode. */
6728 tem = make_compound_operation (SUBREG_REG (x), in_code);
6729 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6730 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6731 && subreg_lowpart_p (x))
6733 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6736 /* If we have something other than a SUBREG, we might have
6737 done an expansion, so rerun ourselves. */
6738 if (GET_CODE (newer) != SUBREG)
6739 newer = make_compound_operation (newer, in_code);
6744 /* If this is a paradoxical subreg, and the new code is a sign or
6745 zero extension, omit the subreg and widen the extension. If it
6746 is a regular subreg, we can still get rid of the subreg by not
6747 widening so much, or in fact removing the extension entirely. */
6748 if ((GET_CODE (tem) == SIGN_EXTEND
6749 || GET_CODE (tem) == ZERO_EXTEND)
6750 && subreg_lowpart_p (x))
6752 if (GET_MODE_SIZE (mode) > GET_MODE_SIZE (GET_MODE (tem))
6753 || (GET_MODE_SIZE (mode) >
6754 GET_MODE_SIZE (GET_MODE (XEXP (tem, 0)))))
6756 if (! SCALAR_INT_MODE_P (mode))
6758 tem = gen_rtx_fmt_e (GET_CODE (tem), mode, XEXP (tem, 0));
6761 tem = gen_lowpart (mode, XEXP (tem, 0));
6772 x = gen_lowpart (mode, new);
6773 code = GET_CODE (x);
6776 /* Now recursively process each operand of this operation. */
6777 fmt = GET_RTX_FORMAT (code);
6778 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6781 new = make_compound_operation (XEXP (x, i), next_code);
6782 SUBST (XEXP (x, i), new);
6788 /* Given M see if it is a value that would select a field of bits
6789 within an item, but not the entire word. Return -1 if not.
6790 Otherwise, return the starting position of the field, where 0 is the
6793 *PLEN is set to the length of the field. */
6796 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6798 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6799 int pos = exact_log2 (m & -m);
6803 /* Now shift off the low-order zero bits and see if we have a
6804 power of two minus 1. */
6805 len = exact_log2 ((m >> pos) + 1);
6814 /* See if X can be simplified knowing that we will only refer to it in
6815 MODE and will only refer to those bits that are nonzero in MASK.
6816 If other bits are being computed or if masking operations are done
6817 that select a superset of the bits in MASK, they can sometimes be
6820 Return a possibly simplified expression, but always convert X to
6821 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6823 Also, if REG is nonzero and X is a register equal in value to REG,
6826 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6827 are all off in X. This is used when X will be complemented, by either
6828 NOT, NEG, or XOR. */
6831 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6832 rtx reg, int just_select)
6834 enum rtx_code code = GET_CODE (x);
6835 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6836 enum machine_mode op_mode;
6837 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6840 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6841 code below will do the wrong thing since the mode of such an
6842 expression is VOIDmode.
6844 Also do nothing if X is a CLOBBER; this can happen if X was
6845 the return value from a call to gen_lowpart. */
6846 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6849 /* We want to perform the operation is its present mode unless we know
6850 that the operation is valid in MODE, in which case we do the operation
6852 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6853 && have_insn_for (code, mode))
6854 ? mode : GET_MODE (x));
6856 /* It is not valid to do a right-shift in a narrower mode
6857 than the one it came in with. */
6858 if ((code == LSHIFTRT || code == ASHIFTRT)
6859 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6860 op_mode = GET_MODE (x);
6862 /* Truncate MASK to fit OP_MODE. */
6864 mask &= GET_MODE_MASK (op_mode);
6866 /* When we have an arithmetic operation, or a shift whose count we
6867 do not know, we need to assume that all bits up to the highest-order
6868 bit in MASK will be needed. This is how we form such a mask. */
6869 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6870 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6872 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6875 /* Determine what bits of X are guaranteed to be (non)zero. */
6876 nonzero = nonzero_bits (x, mode);
6878 /* If none of the bits in X are needed, return a zero. */
6879 if (! just_select && (nonzero & mask) == 0)
6882 /* If X is a CONST_INT, return a new one. Do this here since the
6883 test below will fail. */
6884 if (GET_CODE (x) == CONST_INT)
6886 if (SCALAR_INT_MODE_P (mode))
6887 return gen_int_mode (INTVAL (x) & mask, mode);
6890 x = GEN_INT (INTVAL (x) & mask);
6891 return gen_lowpart_common (mode, x);
6895 /* If X is narrower than MODE and we want all the bits in X's mode, just
6896 get X in the proper mode. */
6897 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6898 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6899 return gen_lowpart (mode, x);
6901 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6902 MASK are already known to be zero in X, we need not do anything. */
6903 if (GET_MODE (x) == mode && code != SUBREG && (~mask & nonzero) == 0)
6909 /* If X is a (clobber (const_int)), return it since we know we are
6910 generating something that won't match. */
6914 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6915 spanned the boundary of the MEM. If we are now masking so it is
6916 within that boundary, we don't need the USE any more. */
6917 if (! BITS_BIG_ENDIAN
6918 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6919 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
6926 x = expand_compound_operation (x);
6927 if (GET_CODE (x) != code)
6928 return force_to_mode (x, mode, mask, reg, next_select);
6932 if (reg != 0 && (rtx_equal_p (get_last_value (reg), x)
6933 || rtx_equal_p (reg, get_last_value (x))))
6938 if (subreg_lowpart_p (x)
6939 /* We can ignore the effect of this SUBREG if it narrows the mode or
6940 if the constant masks to zero all the bits the mode doesn't
6942 && ((GET_MODE_SIZE (GET_MODE (x))
6943 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6945 & GET_MODE_MASK (GET_MODE (x))
6946 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6947 return force_to_mode (SUBREG_REG (x), mode, mask, reg, next_select);
6951 /* If this is an AND with a constant, convert it into an AND
6952 whose constant is the AND of that constant with MASK. If it
6953 remains an AND of MASK, delete it since it is redundant. */
6955 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6957 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6958 mask & INTVAL (XEXP (x, 1)));
6960 /* If X is still an AND, see if it is an AND with a mask that
6961 is just some low-order bits. If so, and it is MASK, we don't
6964 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6965 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6969 /* If it remains an AND, try making another AND with the bits
6970 in the mode mask that aren't in MASK turned on. If the
6971 constant in the AND is wide enough, this might make a
6972 cheaper constant. */
6974 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6975 && GET_MODE_MASK (GET_MODE (x)) != mask
6976 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6978 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6979 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6980 int width = GET_MODE_BITSIZE (GET_MODE (x));
6983 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6984 number, sign extend it. */
6985 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6986 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6987 cval |= (HOST_WIDE_INT) -1 << width;
6989 y = gen_binary (AND, GET_MODE (x), XEXP (x, 0), GEN_INT (cval));
6990 if (rtx_cost (y, SET) < rtx_cost (x, SET))
7000 /* In (and (plus FOO C1) M), if M is a mask that just turns off
7001 low-order bits (as in an alignment operation) and FOO is already
7002 aligned to that boundary, mask C1 to that boundary as well.
7003 This may eliminate that PLUS and, later, the AND. */
7006 unsigned int width = GET_MODE_BITSIZE (mode);
7007 unsigned HOST_WIDE_INT smask = mask;
7009 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
7010 number, sign extend it. */
7012 if (width < HOST_BITS_PER_WIDE_INT
7013 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
7014 smask |= (HOST_WIDE_INT) -1 << width;
7016 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7017 && exact_log2 (- smask) >= 0
7018 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
7019 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
7020 return force_to_mode (plus_constant (XEXP (x, 0),
7021 (INTVAL (XEXP (x, 1)) & smask)),
7022 mode, smask, reg, next_select);
7025 /* ... fall through ... */
7028 /* For PLUS, MINUS and MULT, we need any bits less significant than the
7029 most significant bit in MASK since carries from those bits will
7030 affect the bits we are interested in. */
7035 /* If X is (minus C Y) where C's least set bit is larger than any bit
7036 in the mask, then we may replace with (neg Y). */
7037 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7038 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
7039 & -INTVAL (XEXP (x, 0))))
7042 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
7044 return force_to_mode (x, mode, mask, reg, next_select);
7047 /* Similarly, if C contains every bit in the fuller_mask, then we may
7048 replace with (not Y). */
7049 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7050 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
7051 == INTVAL (XEXP (x, 0))))
7053 x = simplify_gen_unary (NOT, GET_MODE (x),
7054 XEXP (x, 1), GET_MODE (x));
7055 return force_to_mode (x, mode, mask, reg, next_select);
7063 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
7064 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
7065 operation which may be a bitfield extraction. Ensure that the
7066 constant we form is not wider than the mode of X. */
7068 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7069 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7070 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7071 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7072 && GET_CODE (XEXP (x, 1)) == CONST_INT
7073 && ((INTVAL (XEXP (XEXP (x, 0), 1))
7074 + floor_log2 (INTVAL (XEXP (x, 1))))
7075 < GET_MODE_BITSIZE (GET_MODE (x)))
7076 && (INTVAL (XEXP (x, 1))
7077 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
7079 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
7080 << INTVAL (XEXP (XEXP (x, 0), 1)));
7081 temp = gen_binary (GET_CODE (x), GET_MODE (x),
7082 XEXP (XEXP (x, 0), 0), temp);
7083 x = gen_binary (LSHIFTRT, GET_MODE (x), temp,
7084 XEXP (XEXP (x, 0), 1));
7085 return force_to_mode (x, mode, mask, reg, next_select);
7089 /* For most binary operations, just propagate into the operation and
7090 change the mode if we have an operation of that mode. */
7092 op0 = gen_lowpart (op_mode,
7093 force_to_mode (XEXP (x, 0), mode, mask,
7095 op1 = gen_lowpart (op_mode,
7096 force_to_mode (XEXP (x, 1), mode, mask,
7099 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7100 x = gen_binary (code, op_mode, op0, op1);
7104 /* For left shifts, do the same, but just for the first operand.
7105 However, we cannot do anything with shifts where we cannot
7106 guarantee that the counts are smaller than the size of the mode
7107 because such a count will have a different meaning in a
7110 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
7111 && INTVAL (XEXP (x, 1)) >= 0
7112 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
7113 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
7114 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
7115 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
7118 /* If the shift count is a constant and we can do arithmetic in
7119 the mode of the shift, refine which bits we need. Otherwise, use the
7120 conservative form of the mask. */
7121 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7122 && INTVAL (XEXP (x, 1)) >= 0
7123 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
7124 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7125 mask >>= INTVAL (XEXP (x, 1));
7129 op0 = gen_lowpart (op_mode,
7130 force_to_mode (XEXP (x, 0), op_mode,
7131 mask, reg, next_select));
7133 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7134 x = gen_binary (code, op_mode, op0, XEXP (x, 1));
7138 /* Here we can only do something if the shift count is a constant,
7139 this shift constant is valid for the host, and we can do arithmetic
7142 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7143 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7144 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
7146 rtx inner = XEXP (x, 0);
7147 unsigned HOST_WIDE_INT inner_mask;
7149 /* Select the mask of the bits we need for the shift operand. */
7150 inner_mask = mask << INTVAL (XEXP (x, 1));
7152 /* We can only change the mode of the shift if we can do arithmetic
7153 in the mode of the shift and INNER_MASK is no wider than the
7154 width of X's mode. */
7155 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
7156 op_mode = GET_MODE (x);
7158 inner = force_to_mode (inner, op_mode, inner_mask, reg, next_select);
7160 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
7161 x = gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
7164 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
7165 shift and AND produces only copies of the sign bit (C2 is one less
7166 than a power of two), we can do this with just a shift. */
7168 if (GET_CODE (x) == LSHIFTRT
7169 && GET_CODE (XEXP (x, 1)) == CONST_INT
7170 /* The shift puts one of the sign bit copies in the least significant
7172 && ((INTVAL (XEXP (x, 1))
7173 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
7174 >= GET_MODE_BITSIZE (GET_MODE (x)))
7175 && exact_log2 (mask + 1) >= 0
7176 /* Number of bits left after the shift must be more than the mask
7178 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
7179 <= GET_MODE_BITSIZE (GET_MODE (x)))
7180 /* Must be more sign bit copies than the mask needs. */
7181 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
7182 >= exact_log2 (mask + 1)))
7183 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7184 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
7185 - exact_log2 (mask + 1)));
7190 /* If we are just looking for the sign bit, we don't need this shift at
7191 all, even if it has a variable count. */
7192 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
7193 && (mask == ((unsigned HOST_WIDE_INT) 1
7194 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
7195 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7197 /* If this is a shift by a constant, get a mask that contains those bits
7198 that are not copies of the sign bit. We then have two cases: If
7199 MASK only includes those bits, this can be a logical shift, which may
7200 allow simplifications. If MASK is a single-bit field not within
7201 those bits, we are requesting a copy of the sign bit and hence can
7202 shift the sign bit to the appropriate location. */
7204 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
7205 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
7209 /* If the considered data is wider than HOST_WIDE_INT, we can't
7210 represent a mask for all its bits in a single scalar.
7211 But we only care about the lower bits, so calculate these. */
7213 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
7215 nonzero = ~(HOST_WIDE_INT) 0;
7217 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7218 is the number of bits a full-width mask would have set.
7219 We need only shift if these are fewer than nonzero can
7220 hold. If not, we must keep all bits set in nonzero. */
7222 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
7223 < HOST_BITS_PER_WIDE_INT)
7224 nonzero >>= INTVAL (XEXP (x, 1))
7225 + HOST_BITS_PER_WIDE_INT
7226 - GET_MODE_BITSIZE (GET_MODE (x)) ;
7230 nonzero = GET_MODE_MASK (GET_MODE (x));
7231 nonzero >>= INTVAL (XEXP (x, 1));
7234 if ((mask & ~nonzero) == 0
7235 || (i = exact_log2 (mask)) >= 0)
7237 x = simplify_shift_const
7238 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
7239 i < 0 ? INTVAL (XEXP (x, 1))
7240 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
7242 if (GET_CODE (x) != ASHIFTRT)
7243 return force_to_mode (x, mode, mask, reg, next_select);
7247 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
7248 even if the shift count isn't a constant. */
7250 x = gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0), XEXP (x, 1));
7254 /* If this is a zero- or sign-extension operation that just affects bits
7255 we don't care about, remove it. Be sure the call above returned
7256 something that is still a shift. */
7258 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
7259 && GET_CODE (XEXP (x, 1)) == CONST_INT
7260 && INTVAL (XEXP (x, 1)) >= 0
7261 && (INTVAL (XEXP (x, 1))
7262 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
7263 && GET_CODE (XEXP (x, 0)) == ASHIFT
7264 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
7265 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
7272 /* If the shift count is constant and we can do computations
7273 in the mode of X, compute where the bits we care about are.
7274 Otherwise, we can't do anything. Don't change the mode of
7275 the shift or propagate MODE into the shift, though. */
7276 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7277 && INTVAL (XEXP (x, 1)) >= 0)
7279 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
7280 GET_MODE (x), GEN_INT (mask),
7282 if (temp && GET_CODE (temp) == CONST_INT)
7284 force_to_mode (XEXP (x, 0), GET_MODE (x),
7285 INTVAL (temp), reg, next_select));
7290 /* If we just want the low-order bit, the NEG isn't needed since it
7291 won't change the low-order bit. */
7293 return force_to_mode (XEXP (x, 0), mode, mask, reg, just_select);
7295 /* We need any bits less significant than the most significant bit in
7296 MASK since carries from those bits will affect the bits we are
7302 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7303 same as the XOR case above. Ensure that the constant we form is not
7304 wider than the mode of X. */
7306 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7307 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7308 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7309 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7310 < GET_MODE_BITSIZE (GET_MODE (x)))
7311 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7313 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7315 temp = gen_binary (XOR, GET_MODE (x), XEXP (XEXP (x, 0), 0), temp);
7316 x = gen_binary (LSHIFTRT, GET_MODE (x), temp, XEXP (XEXP (x, 0), 1));
7318 return force_to_mode (x, mode, mask, reg, next_select);
7321 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7322 use the full mask inside the NOT. */
7326 op0 = gen_lowpart (op_mode,
7327 force_to_mode (XEXP (x, 0), mode, mask,
7329 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7330 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7334 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7335 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7336 which is equal to STORE_FLAG_VALUE. */
7337 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7338 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7339 && (nonzero_bits (XEXP (x, 0), mode)
7340 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7341 return force_to_mode (XEXP (x, 0), mode, mask, reg, next_select);
7346 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7347 written in a narrower mode. We play it safe and do not do so. */
7350 gen_lowpart (GET_MODE (x),
7351 force_to_mode (XEXP (x, 1), mode,
7352 mask, reg, next_select)));
7354 gen_lowpart (GET_MODE (x),
7355 force_to_mode (XEXP (x, 2), mode,
7356 mask, reg, next_select)));
7363 /* Ensure we return a value of the proper mode. */
7364 return gen_lowpart (mode, x);
7367 /* Return nonzero if X is an expression that has one of two values depending on
7368 whether some other value is zero or nonzero. In that case, we return the
7369 value that is being tested, *PTRUE is set to the value if the rtx being
7370 returned has a nonzero value, and *PFALSE is set to the other alternative.
7372 If we return zero, we set *PTRUE and *PFALSE to X. */
7375 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7377 enum machine_mode mode = GET_MODE (x);
7378 enum rtx_code code = GET_CODE (x);
7379 rtx cond0, cond1, true0, true1, false0, false1;
7380 unsigned HOST_WIDE_INT nz;
7382 /* If we are comparing a value against zero, we are done. */
7383 if ((code == NE || code == EQ)
7384 && XEXP (x, 1) == const0_rtx)
7386 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7387 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7391 /* If this is a unary operation whose operand has one of two values, apply
7392 our opcode to compute those values. */
7393 else if (UNARY_P (x)
7394 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7396 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7397 *pfalse = simplify_gen_unary (code, mode, false0,
7398 GET_MODE (XEXP (x, 0)));
7402 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7403 make can't possibly match and would suppress other optimizations. */
7404 else if (code == COMPARE)
7407 /* If this is a binary operation, see if either side has only one of two
7408 values. If either one does or if both do and they are conditional on
7409 the same value, compute the new true and false values. */
7410 else if (BINARY_P (x))
7412 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7413 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7415 if ((cond0 != 0 || cond1 != 0)
7416 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7418 /* If if_then_else_cond returned zero, then true/false are the
7419 same rtl. We must copy one of them to prevent invalid rtl
7422 true0 = copy_rtx (true0);
7423 else if (cond1 == 0)
7424 true1 = copy_rtx (true1);
7426 *ptrue = gen_binary (code, mode, true0, true1);
7427 *pfalse = gen_binary (code, mode, false0, false1);
7428 return cond0 ? cond0 : cond1;
7431 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7432 operands is zero when the other is nonzero, and vice-versa,
7433 and STORE_FLAG_VALUE is 1 or -1. */
7435 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7436 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7438 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7440 rtx op0 = XEXP (XEXP (x, 0), 1);
7441 rtx op1 = XEXP (XEXP (x, 1), 1);
7443 cond0 = XEXP (XEXP (x, 0), 0);
7444 cond1 = XEXP (XEXP (x, 1), 0);
7446 if (COMPARISON_P (cond0)
7447 && COMPARISON_P (cond1)
7448 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7449 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7450 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7451 || ((swap_condition (GET_CODE (cond0))
7452 == combine_reversed_comparison_code (cond1))
7453 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7454 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7455 && ! side_effects_p (x))
7457 *ptrue = gen_binary (MULT, mode, op0, const_true_rtx);
7458 *pfalse = gen_binary (MULT, mode,
7460 ? simplify_gen_unary (NEG, mode, op1,
7468 /* Similarly for MULT, AND and UMIN, except that for these the result
7470 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7471 && (code == MULT || code == AND || code == UMIN)
7472 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7474 cond0 = XEXP (XEXP (x, 0), 0);
7475 cond1 = XEXP (XEXP (x, 1), 0);
7477 if (COMPARISON_P (cond0)
7478 && COMPARISON_P (cond1)
7479 && ((GET_CODE (cond0) == combine_reversed_comparison_code (cond1)
7480 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7481 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7482 || ((swap_condition (GET_CODE (cond0))
7483 == combine_reversed_comparison_code (cond1))
7484 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7485 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7486 && ! side_effects_p (x))
7488 *ptrue = *pfalse = const0_rtx;
7494 else if (code == IF_THEN_ELSE)
7496 /* If we have IF_THEN_ELSE already, extract the condition and
7497 canonicalize it if it is NE or EQ. */
7498 cond0 = XEXP (x, 0);
7499 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7500 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7501 return XEXP (cond0, 0);
7502 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7504 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7505 return XEXP (cond0, 0);
7511 /* If X is a SUBREG, we can narrow both the true and false values
7512 if the inner expression, if there is a condition. */
7513 else if (code == SUBREG
7514 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7517 true0 = simplify_gen_subreg (mode, true0,
7518 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7519 false0 = simplify_gen_subreg (mode, false0,
7520 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7521 if (true0 && false0)
7529 /* If X is a constant, this isn't special and will cause confusions
7530 if we treat it as such. Likewise if it is equivalent to a constant. */
7531 else if (CONSTANT_P (x)
7532 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7535 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7536 will be least confusing to the rest of the compiler. */
7537 else if (mode == BImode)
7539 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7543 /* If X is known to be either 0 or -1, those are the true and
7544 false values when testing X. */
7545 else if (x == constm1_rtx || x == const0_rtx
7546 || (mode != VOIDmode
7547 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7549 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7553 /* Likewise for 0 or a single bit. */
7554 else if (SCALAR_INT_MODE_P (mode)
7555 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7556 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7558 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7562 /* Otherwise fail; show no condition with true and false values the same. */
7563 *ptrue = *pfalse = x;
7567 /* Return the value of expression X given the fact that condition COND
7568 is known to be true when applied to REG as its first operand and VAL
7569 as its second. X is known to not be shared and so can be modified in
7572 We only handle the simplest cases, and specifically those cases that
7573 arise with IF_THEN_ELSE expressions. */
7576 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7578 enum rtx_code code = GET_CODE (x);
7583 if (side_effects_p (x))
7586 /* If either operand of the condition is a floating point value,
7587 then we have to avoid collapsing an EQ comparison. */
7589 && rtx_equal_p (x, reg)
7590 && ! FLOAT_MODE_P (GET_MODE (x))
7591 && ! FLOAT_MODE_P (GET_MODE (val)))
7594 if (cond == UNEQ && rtx_equal_p (x, reg))
7597 /* If X is (abs REG) and we know something about REG's relationship
7598 with zero, we may be able to simplify this. */
7600 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7603 case GE: case GT: case EQ:
7606 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7608 GET_MODE (XEXP (x, 0)));
7613 /* The only other cases we handle are MIN, MAX, and comparisons if the
7614 operands are the same as REG and VAL. */
7616 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7618 if (rtx_equal_p (XEXP (x, 0), val))
7619 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7621 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7623 if (COMPARISON_P (x))
7625 if (comparison_dominates_p (cond, code))
7626 return const_true_rtx;
7628 code = combine_reversed_comparison_code (x);
7630 && comparison_dominates_p (cond, code))
7635 else if (code == SMAX || code == SMIN
7636 || code == UMIN || code == UMAX)
7638 int unsignedp = (code == UMIN || code == UMAX);
7640 /* Do not reverse the condition when it is NE or EQ.
7641 This is because we cannot conclude anything about
7642 the value of 'SMAX (x, y)' when x is not equal to y,
7643 but we can when x equals y. */
7644 if ((code == SMAX || code == UMAX)
7645 && ! (cond == EQ || cond == NE))
7646 cond = reverse_condition (cond);
7651 return unsignedp ? x : XEXP (x, 1);
7653 return unsignedp ? x : XEXP (x, 0);
7655 return unsignedp ? XEXP (x, 1) : x;
7657 return unsignedp ? XEXP (x, 0) : x;
7664 else if (code == SUBREG)
7666 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7667 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7669 if (SUBREG_REG (x) != r)
7671 /* We must simplify subreg here, before we lose track of the
7672 original inner_mode. */
7673 new = simplify_subreg (GET_MODE (x), r,
7674 inner_mode, SUBREG_BYTE (x));
7678 SUBST (SUBREG_REG (x), r);
7683 /* We don't have to handle SIGN_EXTEND here, because even in the
7684 case of replacing something with a modeless CONST_INT, a
7685 CONST_INT is already (supposed to be) a valid sign extension for
7686 its narrower mode, which implies it's already properly
7687 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7688 story is different. */
7689 else if (code == ZERO_EXTEND)
7691 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7692 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7694 if (XEXP (x, 0) != r)
7696 /* We must simplify the zero_extend here, before we lose
7697 track of the original inner_mode. */
7698 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7703 SUBST (XEXP (x, 0), r);
7709 fmt = GET_RTX_FORMAT (code);
7710 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7713 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7714 else if (fmt[i] == 'E')
7715 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7716 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7723 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7724 assignment as a field assignment. */
7727 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7729 if (x == y || rtx_equal_p (x, y))
7732 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7735 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7736 Note that all SUBREGs of MEM are paradoxical; otherwise they
7737 would have been rewritten. */
7738 if (MEM_P (x) && GET_CODE (y) == SUBREG
7739 && MEM_P (SUBREG_REG (y))
7740 && rtx_equal_p (SUBREG_REG (y),
7741 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7744 if (MEM_P (y) && GET_CODE (x) == SUBREG
7745 && MEM_P (SUBREG_REG (x))
7746 && rtx_equal_p (SUBREG_REG (x),
7747 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7750 /* We used to see if get_last_value of X and Y were the same but that's
7751 not correct. In one direction, we'll cause the assignment to have
7752 the wrong destination and in the case, we'll import a register into this
7753 insn that might have already have been dead. So fail if none of the
7754 above cases are true. */
7758 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7759 Return that assignment if so.
7761 We only handle the most common cases. */
7764 make_field_assignment (rtx x)
7766 rtx dest = SET_DEST (x);
7767 rtx src = SET_SRC (x);
7772 unsigned HOST_WIDE_INT len;
7774 enum machine_mode mode;
7776 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7777 a clear of a one-bit field. We will have changed it to
7778 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7781 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7782 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7783 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7784 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7786 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7789 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7793 else if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7794 && subreg_lowpart_p (XEXP (src, 0))
7795 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7796 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7797 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7798 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7799 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7800 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7802 assign = make_extraction (VOIDmode, dest, 0,
7803 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7806 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7810 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7812 else if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7813 && XEXP (XEXP (src, 0), 0) == const1_rtx
7814 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7816 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7819 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7823 /* The other case we handle is assignments into a constant-position
7824 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7825 a mask that has all one bits except for a group of zero bits and
7826 OTHER is known to have zeros where C1 has ones, this is such an
7827 assignment. Compute the position and length from C1. Shift OTHER
7828 to the appropriate position, force it to the required mode, and
7829 make the extraction. Check for the AND in both operands. */
7831 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7834 rhs = expand_compound_operation (XEXP (src, 0));
7835 lhs = expand_compound_operation (XEXP (src, 1));
7837 if (GET_CODE (rhs) == AND
7838 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7839 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7840 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7841 else if (GET_CODE (lhs) == AND
7842 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7843 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7844 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7848 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7849 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7850 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7851 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7854 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7858 /* The mode to use for the source is the mode of the assignment, or of
7859 what is inside a possible STRICT_LOW_PART. */
7860 mode = (GET_CODE (assign) == STRICT_LOW_PART
7861 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7863 /* Shift OTHER right POS places and make it the source, restricting it
7864 to the proper length and mode. */
7866 src = force_to_mode (simplify_shift_const (NULL_RTX, LSHIFTRT,
7867 GET_MODE (src), other, pos),
7869 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7870 ? ~(unsigned HOST_WIDE_INT) 0
7871 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7874 /* If SRC is masked by an AND that does not make a difference in
7875 the value being stored, strip it. */
7876 if (GET_CODE (assign) == ZERO_EXTRACT
7877 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7878 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7879 && GET_CODE (src) == AND
7880 && GET_CODE (XEXP (src, 1)) == CONST_INT
7881 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7882 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7883 src = XEXP (src, 0);
7885 return gen_rtx_SET (VOIDmode, assign, src);
7888 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7892 apply_distributive_law (rtx x)
7894 enum rtx_code code = GET_CODE (x);
7895 enum rtx_code inner_code;
7896 rtx lhs, rhs, other;
7899 /* Distributivity is not true for floating point as it can change the
7900 value. So we don't do it unless -funsafe-math-optimizations. */
7901 if (FLOAT_MODE_P (GET_MODE (x))
7902 && ! flag_unsafe_math_optimizations)
7905 /* The outer operation can only be one of the following: */
7906 if (code != IOR && code != AND && code != XOR
7907 && code != PLUS && code != MINUS)
7913 /* If either operand is a primitive we can't do anything, so get out
7915 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7918 lhs = expand_compound_operation (lhs);
7919 rhs = expand_compound_operation (rhs);
7920 inner_code = GET_CODE (lhs);
7921 if (inner_code != GET_CODE (rhs))
7924 /* See if the inner and outer operations distribute. */
7931 /* These all distribute except over PLUS. */
7932 if (code == PLUS || code == MINUS)
7937 if (code != PLUS && code != MINUS)
7942 /* This is also a multiply, so it distributes over everything. */
7946 /* Non-paradoxical SUBREGs distributes over all operations, provided
7947 the inner modes and byte offsets are the same, this is an extraction
7948 of a low-order part, we don't convert an fp operation to int or
7949 vice versa, and we would not be converting a single-word
7950 operation into a multi-word operation. The latter test is not
7951 required, but it prevents generating unneeded multi-word operations.
7952 Some of the previous tests are redundant given the latter test, but
7953 are retained because they are required for correctness.
7955 We produce the result slightly differently in this case. */
7957 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7958 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7959 || ! subreg_lowpart_p (lhs)
7960 || (GET_MODE_CLASS (GET_MODE (lhs))
7961 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7962 || (GET_MODE_SIZE (GET_MODE (lhs))
7963 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7964 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7967 tem = gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7968 SUBREG_REG (lhs), SUBREG_REG (rhs));
7969 return gen_lowpart (GET_MODE (x), tem);
7975 /* Set LHS and RHS to the inner operands (A and B in the example
7976 above) and set OTHER to the common operand (C in the example).
7977 There is only one way to do this unless the inner operation is
7979 if (COMMUTATIVE_ARITH_P (lhs)
7980 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7981 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7982 else if (COMMUTATIVE_ARITH_P (lhs)
7983 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7984 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7985 else if (COMMUTATIVE_ARITH_P (lhs)
7986 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7987 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7988 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7989 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7993 /* Form the new inner operation, seeing if it simplifies first. */
7994 tem = gen_binary (code, GET_MODE (x), lhs, rhs);
7996 /* There is one exception to the general way of distributing:
7997 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7998 if (code == XOR && inner_code == IOR)
8001 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
8004 /* We may be able to continuing distributing the result, so call
8005 ourselves recursively on the inner operation before forming the
8006 outer operation, which we return. */
8007 return gen_binary (inner_code, GET_MODE (x),
8008 apply_distributive_law (tem), other);
8011 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
8014 Return an equivalent form, if different from X. Otherwise, return X. If
8015 X is zero, we are to always construct the equivalent form. */
8018 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
8019 unsigned HOST_WIDE_INT constop)
8021 unsigned HOST_WIDE_INT nonzero;
8024 /* Simplify VAROP knowing that we will be only looking at some of the
8027 Note by passing in CONSTOP, we guarantee that the bits not set in
8028 CONSTOP are not significant and will never be examined. We must
8029 ensure that is the case by explicitly masking out those bits
8030 before returning. */
8031 varop = force_to_mode (varop, mode, constop, NULL_RTX, 0);
8033 /* If VAROP is a CLOBBER, we will fail so return it. */
8034 if (GET_CODE (varop) == CLOBBER)
8037 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
8038 to VAROP and return the new constant. */
8039 if (GET_CODE (varop) == CONST_INT)
8040 return GEN_INT (trunc_int_for_mode (INTVAL (varop) & constop, mode));
8042 /* See what bits may be nonzero in VAROP. Unlike the general case of
8043 a call to nonzero_bits, here we don't care about bits outside
8046 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
8048 /* Turn off all bits in the constant that are known to already be zero.
8049 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
8050 which is tested below. */
8054 /* If we don't have any bits left, return zero. */
8058 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
8059 a power of two, we can replace this with an ASHIFT. */
8060 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
8061 && (i = exact_log2 (constop)) >= 0)
8062 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
8064 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
8065 or XOR, then try to apply the distributive law. This may eliminate
8066 operations if either branch can be simplified because of the AND.
8067 It may also make some cases more complex, but those cases probably
8068 won't match a pattern either with or without this. */
8070 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
8074 apply_distributive_law
8075 (gen_binary (GET_CODE (varop), GET_MODE (varop),
8076 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8077 XEXP (varop, 0), constop),
8078 simplify_and_const_int (NULL_RTX, GET_MODE (varop),
8079 XEXP (varop, 1), constop))));
8081 /* If VAROP is PLUS, and the constant is a mask of low bite, distribute
8082 the AND and see if one of the operands simplifies to zero. If so, we
8083 may eliminate it. */
8085 if (GET_CODE (varop) == PLUS
8086 && exact_log2 (constop + 1) >= 0)
8090 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
8091 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
8092 if (o0 == const0_rtx)
8094 if (o1 == const0_rtx)
8098 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
8099 if we already had one (just check for the simplest cases). */
8100 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8101 && GET_MODE (XEXP (x, 0)) == mode
8102 && SUBREG_REG (XEXP (x, 0)) == varop)
8103 varop = XEXP (x, 0);
8105 varop = gen_lowpart (mode, varop);
8107 /* If we can't make the SUBREG, try to return what we were given. */
8108 if (GET_CODE (varop) == CLOBBER)
8109 return x ? x : varop;
8111 /* If we are only masking insignificant bits, return VAROP. */
8112 if (constop == nonzero)
8116 /* Otherwise, return an AND. */
8117 constop = trunc_int_for_mode (constop, mode);
8118 /* See how much, if any, of X we can use. */
8119 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
8120 x = gen_binary (AND, mode, varop, GEN_INT (constop));
8124 if (GET_CODE (XEXP (x, 1)) != CONST_INT
8125 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
8126 SUBST (XEXP (x, 1), GEN_INT (constop));
8128 SUBST (XEXP (x, 0), varop);
8135 /* Given a REG, X, compute which bits in X can be nonzero.
8136 We don't care about bits outside of those defined in MODE.
8138 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
8139 a shift, AND, or zero_extract, we can do better. */
8142 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
8143 rtx known_x ATTRIBUTE_UNUSED,
8144 enum machine_mode known_mode ATTRIBUTE_UNUSED,
8145 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
8146 unsigned HOST_WIDE_INT *nonzero)
8150 /* If X is a register whose nonzero bits value is current, use it.
8151 Otherwise, if X is a register whose value we can find, use that
8152 value. Otherwise, use the previously-computed global nonzero bits
8153 for this register. */
8155 if (reg_stat[REGNO (x)].last_set_value != 0
8156 && (reg_stat[REGNO (x)].last_set_mode == mode
8157 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
8158 && GET_MODE_CLASS (mode) == MODE_INT))
8159 && (reg_stat[REGNO (x)].last_set_label == label_tick
8160 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8161 && REG_N_SETS (REGNO (x)) == 1
8162 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8164 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8166 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8170 tem = get_last_value (x);
8174 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8175 /* If X is narrower than MODE and TEM is a non-negative
8176 constant that would appear negative in the mode of X,
8177 sign-extend it for use in reg_nonzero_bits because some
8178 machines (maybe most) will actually do the sign-extension
8179 and this is the conservative approach.
8181 ??? For 2.5, try to tighten up the MD files in this regard
8182 instead of this kludge. */
8184 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8185 && GET_CODE (tem) == CONST_INT
8187 && 0 != (INTVAL (tem)
8188 & ((HOST_WIDE_INT) 1
8189 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8190 tem = GEN_INT (INTVAL (tem)
8191 | ((HOST_WIDE_INT) (-1)
8192 << GET_MODE_BITSIZE (GET_MODE (x))));
8196 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8198 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8200 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8201 /* We don't know anything about the upper bits. */
8202 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8209 /* Return the number of bits at the high-order end of X that are known to
8210 be equal to the sign bit. X will be used in mode MODE; if MODE is
8211 VOIDmode, X will be used in its own mode. The returned value will always
8212 be between 1 and the number of bits in MODE. */
8215 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8216 rtx known_x ATTRIBUTE_UNUSED,
8217 enum machine_mode known_mode
8219 unsigned int known_ret ATTRIBUTE_UNUSED,
8220 unsigned int *result)
8224 if (reg_stat[REGNO (x)].last_set_value != 0
8225 && reg_stat[REGNO (x)].last_set_mode == mode
8226 && (reg_stat[REGNO (x)].last_set_label == label_tick
8227 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8228 && REG_N_SETS (REGNO (x)) == 1
8229 && ! REGNO_REG_SET_P (ENTRY_BLOCK_PTR->next_bb->global_live_at_start,
8231 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8233 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8237 tem = get_last_value (x);
8241 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8242 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8243 *result = reg_stat[REGNO (x)].sign_bit_copies;
8248 /* Return the number of "extended" bits there are in X, when interpreted
8249 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8250 unsigned quantities, this is the number of high-order zero bits.
8251 For signed quantities, this is the number of copies of the sign bit
8252 minus 1. In both case, this function returns the number of "spare"
8253 bits. For example, if two quantities for which this function returns
8254 at least 1 are added, the addition is known not to overflow.
8256 This function will always return 0 unless called during combine, which
8257 implies that it must be called from a define_split. */
8260 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8262 if (nonzero_sign_valid == 0)
8266 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8267 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8268 - floor_log2 (nonzero_bits (x, mode)))
8270 : num_sign_bit_copies (x, mode) - 1);
8273 /* This function is called from `simplify_shift_const' to merge two
8274 outer operations. Specifically, we have already found that we need
8275 to perform operation *POP0 with constant *PCONST0 at the outermost
8276 position. We would now like to also perform OP1 with constant CONST1
8277 (with *POP0 being done last).
8279 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8280 the resulting operation. *PCOMP_P is set to 1 if we would need to
8281 complement the innermost operand, otherwise it is unchanged.
8283 MODE is the mode in which the operation will be done. No bits outside
8284 the width of this mode matter. It is assumed that the width of this mode
8285 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8287 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8288 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8289 result is simply *PCONST0.
8291 If the resulting operation cannot be expressed as one operation, we
8292 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8295 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8297 enum rtx_code op0 = *pop0;
8298 HOST_WIDE_INT const0 = *pconst0;
8300 const0 &= GET_MODE_MASK (mode);
8301 const1 &= GET_MODE_MASK (mode);
8303 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8307 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8310 if (op1 == UNKNOWN || op0 == SET)
8313 else if (op0 == UNKNOWN)
8314 op0 = op1, const0 = const1;
8316 else if (op0 == op1)
8340 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8341 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8344 /* If the two constants aren't the same, we can't do anything. The
8345 remaining six cases can all be done. */
8346 else if (const0 != const1)
8354 /* (a & b) | b == b */
8356 else /* op1 == XOR */
8357 /* (a ^ b) | b == a | b */
8363 /* (a & b) ^ b == (~a) & b */
8364 op0 = AND, *pcomp_p = 1;
8365 else /* op1 == IOR */
8366 /* (a | b) ^ b == a & ~b */
8367 op0 = AND, const0 = ~const0;
8372 /* (a | b) & b == b */
8374 else /* op1 == XOR */
8375 /* (a ^ b) & b) == (~a) & b */
8382 /* Check for NO-OP cases. */
8383 const0 &= GET_MODE_MASK (mode);
8385 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8387 else if (const0 == 0 && op0 == AND)
8389 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8393 /* ??? Slightly redundant with the above mask, but not entirely.
8394 Moving this above means we'd have to sign-extend the mode mask
8395 for the final test. */
8396 const0 = trunc_int_for_mode (const0, mode);
8404 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8405 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8406 that we started with.
8408 The shift is normally computed in the widest mode we find in VAROP, as
8409 long as it isn't a different number of words than RESULT_MODE. Exceptions
8410 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8413 simplify_shift_const (rtx x, enum rtx_code code,
8414 enum machine_mode result_mode, rtx varop,
8417 enum rtx_code orig_code = code;
8420 enum machine_mode mode = result_mode;
8421 enum machine_mode shift_mode, tmode;
8422 unsigned int mode_words
8423 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8424 /* We form (outer_op (code varop count) (outer_const)). */
8425 enum rtx_code outer_op = UNKNOWN;
8426 HOST_WIDE_INT outer_const = 0;
8428 int complement_p = 0;
8431 /* Make sure and truncate the "natural" shift on the way in. We don't
8432 want to do this inside the loop as it makes it more difficult to
8434 if (SHIFT_COUNT_TRUNCATED)
8435 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8437 /* If we were given an invalid count, don't do anything except exactly
8438 what was requested. */
8440 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8445 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8450 /* Unless one of the branches of the `if' in this loop does a `continue',
8451 we will `break' the loop after the `if'. */
8455 /* If we have an operand of (clobber (const_int 0)), just return that
8457 if (GET_CODE (varop) == CLOBBER)
8460 /* If we discovered we had to complement VAROP, leave. Making a NOT
8461 here would cause an infinite loop. */
8465 /* Convert ROTATERT to ROTATE. */
8466 if (code == ROTATERT)
8468 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8470 if (VECTOR_MODE_P (result_mode))
8471 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8473 count = bitsize - count;
8476 /* We need to determine what mode we will do the shift in. If the
8477 shift is a right shift or a ROTATE, we must always do it in the mode
8478 it was originally done in. Otherwise, we can do it in MODE, the
8479 widest mode encountered. */
8481 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8482 ? result_mode : mode);
8484 /* Handle cases where the count is greater than the size of the mode
8485 minus 1. For ASHIFT, use the size minus one as the count (this can
8486 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8487 take the count modulo the size. For other shifts, the result is
8490 Since these shifts are being produced by the compiler by combining
8491 multiple operations, each of which are defined, we know what the
8492 result is supposed to be. */
8494 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8496 if (code == ASHIFTRT)
8497 count = GET_MODE_BITSIZE (shift_mode) - 1;
8498 else if (code == ROTATE || code == ROTATERT)
8499 count %= GET_MODE_BITSIZE (shift_mode);
8502 /* We can't simply return zero because there may be an
8510 /* An arithmetic right shift of a quantity known to be -1 or 0
8512 if (code == ASHIFTRT
8513 && (num_sign_bit_copies (varop, shift_mode)
8514 == GET_MODE_BITSIZE (shift_mode)))
8520 /* If we are doing an arithmetic right shift and discarding all but
8521 the sign bit copies, this is equivalent to doing a shift by the
8522 bitsize minus one. Convert it into that shift because it will often
8523 allow other simplifications. */
8525 if (code == ASHIFTRT
8526 && (count + num_sign_bit_copies (varop, shift_mode)
8527 >= GET_MODE_BITSIZE (shift_mode)))
8528 count = GET_MODE_BITSIZE (shift_mode) - 1;
8530 /* We simplify the tests below and elsewhere by converting
8531 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8532 `make_compound_operation' will convert it to an ASHIFTRT for
8533 those machines (such as VAX) that don't have an LSHIFTRT. */
8534 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8536 && ((nonzero_bits (varop, shift_mode)
8537 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8541 if (code == LSHIFTRT
8542 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8543 && !(nonzero_bits (varop, shift_mode) >> count))
8546 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8547 && !((nonzero_bits (varop, shift_mode) << count)
8548 & GET_MODE_MASK (shift_mode)))
8551 switch (GET_CODE (varop))
8557 new = expand_compound_operation (varop);
8566 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8567 minus the width of a smaller mode, we can do this with a
8568 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8569 if ((code == ASHIFTRT || code == LSHIFTRT)
8570 && ! mode_dependent_address_p (XEXP (varop, 0))
8571 && ! MEM_VOLATILE_P (varop)
8572 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8573 MODE_INT, 1)) != BLKmode)
8575 new = adjust_address_nv (varop, tmode,
8576 BYTES_BIG_ENDIAN ? 0
8577 : count / BITS_PER_UNIT);
8579 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8580 : ZERO_EXTEND, mode, new);
8587 /* Similar to the case above, except that we can only do this if
8588 the resulting mode is the same as that of the underlying
8589 MEM and adjust the address depending on the *bits* endianness
8590 because of the way that bit-field extract insns are defined. */
8591 if ((code == ASHIFTRT || code == LSHIFTRT)
8592 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8593 MODE_INT, 1)) != BLKmode
8594 && tmode == GET_MODE (XEXP (varop, 0)))
8596 if (BITS_BIG_ENDIAN)
8597 new = XEXP (varop, 0);
8600 new = copy_rtx (XEXP (varop, 0));
8601 SUBST (XEXP (new, 0),
8602 plus_constant (XEXP (new, 0),
8603 count / BITS_PER_UNIT));
8606 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8607 : ZERO_EXTEND, mode, new);
8614 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8615 the same number of words as what we've seen so far. Then store
8616 the widest mode in MODE. */
8617 if (subreg_lowpart_p (varop)
8618 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8619 > GET_MODE_SIZE (GET_MODE (varop)))
8620 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8621 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8624 varop = SUBREG_REG (varop);
8625 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8626 mode = GET_MODE (varop);
8632 /* Some machines use MULT instead of ASHIFT because MULT
8633 is cheaper. But it is still better on those machines to
8634 merge two shifts into one. */
8635 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8636 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8639 = gen_binary (ASHIFT, GET_MODE (varop), XEXP (varop, 0),
8640 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8646 /* Similar, for when divides are cheaper. */
8647 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8648 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8651 = gen_binary (LSHIFTRT, GET_MODE (varop), XEXP (varop, 0),
8652 GEN_INT (exact_log2 (INTVAL (XEXP (varop, 1)))));
8658 /* If we are extracting just the sign bit of an arithmetic
8659 right shift, that shift is not needed. However, the sign
8660 bit of a wider mode may be different from what would be
8661 interpreted as the sign bit in a narrower mode, so, if
8662 the result is narrower, don't discard the shift. */
8663 if (code == LSHIFTRT
8664 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8665 && (GET_MODE_BITSIZE (result_mode)
8666 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8668 varop = XEXP (varop, 0);
8672 /* ... fall through ... */
8677 /* Here we have two nested shifts. The result is usually the
8678 AND of a new shift with a mask. We compute the result below. */
8679 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8680 && INTVAL (XEXP (varop, 1)) >= 0
8681 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8682 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8683 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8685 enum rtx_code first_code = GET_CODE (varop);
8686 unsigned int first_count = INTVAL (XEXP (varop, 1));
8687 unsigned HOST_WIDE_INT mask;
8690 /* We have one common special case. We can't do any merging if
8691 the inner code is an ASHIFTRT of a smaller mode. However, if
8692 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8693 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8694 we can convert it to
8695 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8696 This simplifies certain SIGN_EXTEND operations. */
8697 if (code == ASHIFT && first_code == ASHIFTRT
8698 && count == (unsigned int)
8699 (GET_MODE_BITSIZE (result_mode)
8700 - GET_MODE_BITSIZE (GET_MODE (varop))))
8702 /* C3 has the low-order C1 bits zero. */
8704 mask = (GET_MODE_MASK (mode)
8705 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8707 varop = simplify_and_const_int (NULL_RTX, result_mode,
8708 XEXP (varop, 0), mask);
8709 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8711 count = first_count;
8716 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8717 than C1 high-order bits equal to the sign bit, we can convert
8718 this to either an ASHIFT or an ASHIFTRT depending on the
8721 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8723 if (code == ASHIFTRT && first_code == ASHIFT
8724 && GET_MODE (varop) == shift_mode
8725 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8728 varop = XEXP (varop, 0);
8730 signed_count = count - first_count;
8731 if (signed_count < 0)
8732 count = -signed_count, code = ASHIFT;
8734 count = signed_count;
8739 /* There are some cases we can't do. If CODE is ASHIFTRT,
8740 we can only do this if FIRST_CODE is also ASHIFTRT.
8742 We can't do the case when CODE is ROTATE and FIRST_CODE is
8745 If the mode of this shift is not the mode of the outer shift,
8746 we can't do this if either shift is a right shift or ROTATE.
8748 Finally, we can't do any of these if the mode is too wide
8749 unless the codes are the same.
8751 Handle the case where the shift codes are the same
8754 if (code == first_code)
8756 if (GET_MODE (varop) != result_mode
8757 && (code == ASHIFTRT || code == LSHIFTRT
8761 count += first_count;
8762 varop = XEXP (varop, 0);
8766 if (code == ASHIFTRT
8767 || (code == ROTATE && first_code == ASHIFTRT)
8768 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8769 || (GET_MODE (varop) != result_mode
8770 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8771 || first_code == ROTATE
8772 || code == ROTATE)))
8775 /* To compute the mask to apply after the shift, shift the
8776 nonzero bits of the inner shift the same way the
8777 outer shift will. */
8779 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8782 = simplify_binary_operation (code, result_mode, mask_rtx,
8785 /* Give up if we can't compute an outer operation to use. */
8787 || GET_CODE (mask_rtx) != CONST_INT
8788 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8790 result_mode, &complement_p))
8793 /* If the shifts are in the same direction, we add the
8794 counts. Otherwise, we subtract them. */
8795 signed_count = count;
8796 if ((code == ASHIFTRT || code == LSHIFTRT)
8797 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8798 signed_count += first_count;
8800 signed_count -= first_count;
8802 /* If COUNT is positive, the new shift is usually CODE,
8803 except for the two exceptions below, in which case it is
8804 FIRST_CODE. If the count is negative, FIRST_CODE should
8806 if (signed_count > 0
8807 && ((first_code == ROTATE && code == ASHIFT)
8808 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8809 code = first_code, count = signed_count;
8810 else if (signed_count < 0)
8811 code = first_code, count = -signed_count;
8813 count = signed_count;
8815 varop = XEXP (varop, 0);
8819 /* If we have (A << B << C) for any shift, we can convert this to
8820 (A << C << B). This wins if A is a constant. Only try this if
8821 B is not a constant. */
8823 else if (GET_CODE (varop) == code
8824 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8826 = simplify_binary_operation (code, mode,
8830 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8837 /* Make this fit the case below. */
8838 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8839 GEN_INT (GET_MODE_MASK (mode)));
8845 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8846 with C the size of VAROP - 1 and the shift is logical if
8847 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8848 we have an (le X 0) operation. If we have an arithmetic shift
8849 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8850 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8852 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8853 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8854 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8855 && (code == LSHIFTRT || code == ASHIFTRT)
8856 && count == (unsigned int)
8857 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8858 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8861 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8864 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8865 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8870 /* If we have (shift (logical)), move the logical to the outside
8871 to allow it to possibly combine with another logical and the
8872 shift to combine with another shift. This also canonicalizes to
8873 what a ZERO_EXTRACT looks like. Also, some machines have
8874 (and (shift)) insns. */
8876 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8877 /* We can't do this if we have (ashiftrt (xor)) and the
8878 constant has its sign bit set in shift_mode. */
8879 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8880 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8882 && (new = simplify_binary_operation (code, result_mode,
8884 GEN_INT (count))) != 0
8885 && GET_CODE (new) == CONST_INT
8886 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8887 INTVAL (new), result_mode, &complement_p))
8889 varop = XEXP (varop, 0);
8893 /* If we can't do that, try to simplify the shift in each arm of the
8894 logical expression, make a new logical expression, and apply
8895 the inverse distributive law. This also can't be done
8896 for some (ashiftrt (xor)). */
8897 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8898 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8899 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8902 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8903 XEXP (varop, 0), count);
8904 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8905 XEXP (varop, 1), count);
8907 varop = gen_binary (GET_CODE (varop), shift_mode, lhs, rhs);
8908 varop = apply_distributive_law (varop);
8916 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8917 says that the sign bit can be tested, FOO has mode MODE, C is
8918 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8919 that may be nonzero. */
8920 if (code == LSHIFTRT
8921 && XEXP (varop, 1) == const0_rtx
8922 && GET_MODE (XEXP (varop, 0)) == result_mode
8923 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8924 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8925 && ((STORE_FLAG_VALUE
8926 & ((HOST_WIDE_INT) 1
8927 < (GET_MODE_BITSIZE (result_mode) - 1))))
8928 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8929 && merge_outer_ops (&outer_op, &outer_const, XOR,
8930 (HOST_WIDE_INT) 1, result_mode,
8933 varop = XEXP (varop, 0);
8940 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8941 than the number of bits in the mode is equivalent to A. */
8942 if (code == LSHIFTRT
8943 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8944 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8946 varop = XEXP (varop, 0);
8951 /* NEG commutes with ASHIFT since it is multiplication. Move the
8952 NEG outside to allow shifts to combine. */
8954 && merge_outer_ops (&outer_op, &outer_const, NEG,
8955 (HOST_WIDE_INT) 0, result_mode,
8958 varop = XEXP (varop, 0);
8964 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8965 is one less than the number of bits in the mode is
8966 equivalent to (xor A 1). */
8967 if (code == LSHIFTRT
8968 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8969 && XEXP (varop, 1) == constm1_rtx
8970 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8971 && merge_outer_ops (&outer_op, &outer_const, XOR,
8972 (HOST_WIDE_INT) 1, result_mode,
8976 varop = XEXP (varop, 0);
8980 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8981 that might be nonzero in BAR are those being shifted out and those
8982 bits are known zero in FOO, we can replace the PLUS with FOO.
8983 Similarly in the other operand order. This code occurs when
8984 we are computing the size of a variable-size array. */
8986 if ((code == ASHIFTRT || code == LSHIFTRT)
8987 && count < HOST_BITS_PER_WIDE_INT
8988 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8989 && (nonzero_bits (XEXP (varop, 1), result_mode)
8990 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8992 varop = XEXP (varop, 0);
8995 else if ((code == ASHIFTRT || code == LSHIFTRT)
8996 && count < HOST_BITS_PER_WIDE_INT
8997 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8998 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9000 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
9001 & nonzero_bits (XEXP (varop, 1),
9004 varop = XEXP (varop, 1);
9008 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9010 && GET_CODE (XEXP (varop, 1)) == CONST_INT
9011 && (new = simplify_binary_operation (ASHIFT, result_mode,
9013 GEN_INT (count))) != 0
9014 && GET_CODE (new) == CONST_INT
9015 && merge_outer_ops (&outer_op, &outer_const, PLUS,
9016 INTVAL (new), result_mode, &complement_p))
9018 varop = XEXP (varop, 0);
9024 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9025 with C the size of VAROP - 1 and the shift is logical if
9026 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9027 we have a (gt X 0) operation. If the shift is arithmetic with
9028 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9029 we have a (neg (gt X 0)) operation. */
9031 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9032 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
9033 && count == (unsigned int)
9034 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
9035 && (code == LSHIFTRT || code == ASHIFTRT)
9036 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9037 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
9039 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
9042 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
9045 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
9046 varop = gen_rtx_NEG (GET_MODE (varop), varop);
9053 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9054 if the truncate does not affect the value. */
9055 if (code == LSHIFTRT
9056 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
9057 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
9058 && (INTVAL (XEXP (XEXP (varop, 0), 1))
9059 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
9060 - GET_MODE_BITSIZE (GET_MODE (varop)))))
9062 rtx varop_inner = XEXP (varop, 0);
9065 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
9066 XEXP (varop_inner, 0),
9068 (count + INTVAL (XEXP (varop_inner, 1))));
9069 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
9082 /* We need to determine what mode to do the shift in. If the shift is
9083 a right shift or ROTATE, we must always do it in the mode it was
9084 originally done in. Otherwise, we can do it in MODE, the widest mode
9085 encountered. The code we care about is that of the shift that will
9086 actually be done, not the shift that was originally requested. */
9088 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
9089 ? result_mode : mode);
9091 /* We have now finished analyzing the shift. The result should be
9092 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9093 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
9094 to the result of the shift. OUTER_CONST is the relevant constant,
9095 but we must turn off all bits turned off in the shift.
9097 If we were passed a value for X, see if we can use any pieces of
9098 it. If not, make new rtx. */
9100 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
9101 && GET_CODE (XEXP (x, 1)) == CONST_INT
9102 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
9103 const_rtx = XEXP (x, 1);
9105 const_rtx = GEN_INT (count);
9107 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
9108 && GET_MODE (XEXP (x, 0)) == shift_mode
9109 && SUBREG_REG (XEXP (x, 0)) == varop)
9110 varop = XEXP (x, 0);
9111 else if (GET_MODE (varop) != shift_mode)
9112 varop = gen_lowpart (shift_mode, varop);
9114 /* If we can't make the SUBREG, try to return what we were given. */
9115 if (GET_CODE (varop) == CLOBBER)
9116 return x ? x : varop;
9118 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
9122 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
9124 /* If we have an outer operation and we just made a shift, it is
9125 possible that we could have simplified the shift were it not
9126 for the outer operation. So try to do the simplification
9129 if (outer_op != UNKNOWN && GET_CODE (x) == code
9130 && GET_CODE (XEXP (x, 1)) == CONST_INT)
9131 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
9132 INTVAL (XEXP (x, 1)));
9134 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
9135 turn off all the bits that the shift would have turned off. */
9136 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9137 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9138 GET_MODE_MASK (result_mode) >> orig_count);
9140 /* Do the remainder of the processing in RESULT_MODE. */
9141 x = gen_lowpart (result_mode, x);
9143 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9146 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9148 if (outer_op != UNKNOWN)
9150 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9151 outer_const = trunc_int_for_mode (outer_const, result_mode);
9153 if (outer_op == AND)
9154 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9155 else if (outer_op == SET)
9156 /* This means that we have determined that the result is
9157 equivalent to a constant. This should be rare. */
9158 x = GEN_INT (outer_const);
9159 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9160 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9162 x = gen_binary (outer_op, result_mode, x, GEN_INT (outer_const));
9168 /* Like recog, but we receive the address of a pointer to a new pattern.
9169 We try to match the rtx that the pointer points to.
9170 If that fails, we may try to modify or replace the pattern,
9171 storing the replacement into the same pointer object.
9173 Modifications include deletion or addition of CLOBBERs.
9175 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9176 the CLOBBERs are placed.
9178 The value is the final insn code from the pattern ultimately matched,
9182 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9185 int insn_code_number;
9186 int num_clobbers_to_add = 0;
9189 rtx old_notes, old_pat;
9191 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9192 we use to indicate that something didn't match. If we find such a
9193 thing, force rejection. */
9194 if (GET_CODE (pat) == PARALLEL)
9195 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9196 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9197 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9200 old_pat = PATTERN (insn);
9201 old_notes = REG_NOTES (insn);
9202 PATTERN (insn) = pat;
9203 REG_NOTES (insn) = 0;
9205 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9207 /* If it isn't, there is the possibility that we previously had an insn
9208 that clobbered some register as a side effect, but the combined
9209 insn doesn't need to do that. So try once more without the clobbers
9210 unless this represents an ASM insn. */
9212 if (insn_code_number < 0 && ! check_asm_operands (pat)
9213 && GET_CODE (pat) == PARALLEL)
9217 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9218 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9221 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9225 SUBST_INT (XVECLEN (pat, 0), pos);
9228 pat = XVECEXP (pat, 0, 0);
9230 PATTERN (insn) = pat;
9231 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9233 PATTERN (insn) = old_pat;
9234 REG_NOTES (insn) = old_notes;
9236 /* Recognize all noop sets, these will be killed by followup pass. */
9237 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9238 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9240 /* If we had any clobbers to add, make a new pattern than contains
9241 them. Then check to make sure that all of them are dead. */
9242 if (num_clobbers_to_add)
9244 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9245 rtvec_alloc (GET_CODE (pat) == PARALLEL
9247 + num_clobbers_to_add)
9248 : num_clobbers_to_add + 1));
9250 if (GET_CODE (pat) == PARALLEL)
9251 for (i = 0; i < XVECLEN (pat, 0); i++)
9252 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9254 XVECEXP (newpat, 0, 0) = pat;
9256 add_clobbers (newpat, insn_code_number);
9258 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9259 i < XVECLEN (newpat, 0); i++)
9261 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9262 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9264 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9265 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9273 return insn_code_number;
9276 /* Like gen_lowpart_general but for use by combine. In combine it
9277 is not possible to create any new pseudoregs. However, it is
9278 safe to create invalid memory addresses, because combine will
9279 try to recognize them and all they will do is make the combine
9282 If for some reason this cannot do its job, an rtx
9283 (clobber (const_int 0)) is returned.
9284 An insn containing that will not be recognized. */
9287 gen_lowpart_for_combine (enum machine_mode mode, rtx x)
9291 if (GET_MODE (x) == mode)
9294 /* Return identity if this is a CONST or symbolic
9297 && (GET_CODE (x) == CONST
9298 || GET_CODE (x) == SYMBOL_REF
9299 || GET_CODE (x) == LABEL_REF))
9302 /* We can only support MODE being wider than a word if X is a
9303 constant integer or has a mode the same size. */
9305 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD
9306 && ! ((GET_MODE (x) == VOIDmode
9307 && (GET_CODE (x) == CONST_INT
9308 || GET_CODE (x) == CONST_DOUBLE))
9309 || GET_MODE_SIZE (GET_MODE (x)) == GET_MODE_SIZE (mode)))
9310 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9312 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9313 won't know what to do. So we will strip off the SUBREG here and
9314 process normally. */
9315 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9318 if (GET_MODE (x) == mode)
9322 result = gen_lowpart_common (mode, x);
9323 #ifdef CANNOT_CHANGE_MODE_CLASS
9325 && GET_CODE (result) == SUBREG
9326 && REG_P (SUBREG_REG (result))
9327 && REGNO (SUBREG_REG (result)) >= FIRST_PSEUDO_REGISTER)
9328 bitmap_set_bit (&subregs_of_mode, REGNO (SUBREG_REG (result))
9330 + GET_MODE (result));
9340 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9342 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9343 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9345 /* If we want to refer to something bigger than the original memref,
9346 generate a paradoxical subreg instead. That will force a reload
9347 of the original memref X. */
9348 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode))
9349 return gen_rtx_SUBREG (mode, x, 0);
9351 if (WORDS_BIG_ENDIAN)
9352 offset = (MAX (GET_MODE_SIZE (GET_MODE (x)), UNITS_PER_WORD)
9353 - MAX (GET_MODE_SIZE (mode), UNITS_PER_WORD));
9355 if (BYTES_BIG_ENDIAN)
9357 /* Adjust the address so that the address-after-the-data is
9359 offset -= (MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode))
9360 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (GET_MODE (x))));
9363 return adjust_address_nv (x, mode, offset);
9366 /* If X is a comparison operator, rewrite it in a new mode. This
9367 probably won't match, but may allow further simplifications. */
9368 else if (COMPARISON_P (x))
9369 return gen_rtx_fmt_ee (GET_CODE (x), mode, XEXP (x, 0), XEXP (x, 1));
9371 /* If we couldn't simplify X any other way, just enclose it in a
9372 SUBREG. Normally, this SUBREG won't match, but some patterns may
9373 include an explicit SUBREG or we may simplify it further in combine. */
9378 enum machine_mode sub_mode = GET_MODE (x);
9380 offset = subreg_lowpart_offset (mode, sub_mode);
9381 if (sub_mode == VOIDmode)
9383 sub_mode = int_mode_for_mode (mode);
9384 x = gen_lowpart_common (sub_mode, x);
9386 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
9388 res = simplify_gen_subreg (mode, x, sub_mode, offset);
9391 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
9395 /* These routines make binary and unary operations by first seeing if they
9396 fold; if not, a new expression is allocated. */
9399 gen_binary (enum rtx_code code, enum machine_mode mode, rtx op0, rtx op1)
9404 if (GET_CODE (op0) == CLOBBER)
9406 else if (GET_CODE (op1) == CLOBBER)
9409 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9410 && swap_commutative_operands_p (op0, op1))
9411 tem = op0, op0 = op1, op1 = tem;
9413 if (GET_RTX_CLASS (code) == RTX_COMPARE
9414 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9416 enum machine_mode op_mode = GET_MODE (op0);
9418 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9419 just (REL_OP X Y). */
9420 if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
9422 op1 = XEXP (op0, 1);
9423 op0 = XEXP (op0, 0);
9424 op_mode = GET_MODE (op0);
9427 if (op_mode == VOIDmode)
9428 op_mode = GET_MODE (op1);
9429 result = simplify_relational_operation (code, mode, op_mode, op0, op1);
9432 result = simplify_binary_operation (code, mode, op0, op1);
9437 /* Put complex operands first and constants second. */
9438 if (GET_RTX_CLASS (code) == RTX_COMM_ARITH
9439 && swap_commutative_operands_p (op0, op1))
9440 return gen_rtx_fmt_ee (code, mode, op1, op0);
9442 /* If we are turning off bits already known off in OP0, we need not do
9444 else if (code == AND && GET_CODE (op1) == CONST_INT
9445 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
9446 && (nonzero_bits (op0, mode) & ~INTVAL (op1)) == 0)
9449 return gen_rtx_fmt_ee (code, mode, op0, op1);
9452 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9453 comparison code that will be tested.
9455 The result is a possibly different comparison code to use. *POP0 and
9456 *POP1 may be updated.
9458 It is possible that we might detect that a comparison is either always
9459 true or always false. However, we do not perform general constant
9460 folding in combine, so this knowledge isn't useful. Such tautologies
9461 should have been detected earlier. Hence we ignore all such cases. */
9463 static enum rtx_code
9464 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9470 enum machine_mode mode, tmode;
9472 /* Try a few ways of applying the same transformation to both operands. */
9475 #ifndef WORD_REGISTER_OPERATIONS
9476 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9477 so check specially. */
9478 if (code != GTU && code != GEU && code != LTU && code != LEU
9479 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9480 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9481 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9482 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9483 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9484 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9485 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9486 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9487 && XEXP (op0, 1) == XEXP (op1, 1)
9488 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9489 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9490 && (INTVAL (XEXP (op0, 1))
9491 == (GET_MODE_BITSIZE (GET_MODE (op0))
9493 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9495 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9496 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9500 /* If both operands are the same constant shift, see if we can ignore the
9501 shift. We can if the shift is a rotate or if the bits shifted out of
9502 this shift are known to be zero for both inputs and if the type of
9503 comparison is compatible with the shift. */
9504 if (GET_CODE (op0) == GET_CODE (op1)
9505 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9506 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9507 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9508 && (code != GT && code != LT && code != GE && code != LE))
9509 || (GET_CODE (op0) == ASHIFTRT
9510 && (code != GTU && code != LTU
9511 && code != GEU && code != LEU)))
9512 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9513 && INTVAL (XEXP (op0, 1)) >= 0
9514 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9515 && XEXP (op0, 1) == XEXP (op1, 1))
9517 enum machine_mode mode = GET_MODE (op0);
9518 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9519 int shift_count = INTVAL (XEXP (op0, 1));
9521 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9522 mask &= (mask >> shift_count) << shift_count;
9523 else if (GET_CODE (op0) == ASHIFT)
9524 mask = (mask & (mask << shift_count)) >> shift_count;
9526 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9527 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9528 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9533 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9534 SUBREGs are of the same mode, and, in both cases, the AND would
9535 be redundant if the comparison was done in the narrower mode,
9536 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9537 and the operand's possibly nonzero bits are 0xffffff01; in that case
9538 if we only care about QImode, we don't need the AND). This case
9539 occurs if the output mode of an scc insn is not SImode and
9540 STORE_FLAG_VALUE == 1 (e.g., the 386).
9542 Similarly, check for a case where the AND's are ZERO_EXTEND
9543 operations from some narrower mode even though a SUBREG is not
9546 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9547 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9548 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9550 rtx inner_op0 = XEXP (op0, 0);
9551 rtx inner_op1 = XEXP (op1, 0);
9552 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9553 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9556 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9557 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9558 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9559 && (GET_MODE (SUBREG_REG (inner_op0))
9560 == GET_MODE (SUBREG_REG (inner_op1)))
9561 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9562 <= HOST_BITS_PER_WIDE_INT)
9563 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9564 GET_MODE (SUBREG_REG (inner_op0)))))
9565 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9566 GET_MODE (SUBREG_REG (inner_op1))))))
9568 op0 = SUBREG_REG (inner_op0);
9569 op1 = SUBREG_REG (inner_op1);
9571 /* The resulting comparison is always unsigned since we masked
9572 off the original sign bit. */
9573 code = unsigned_condition (code);
9579 for (tmode = GET_CLASS_NARROWEST_MODE
9580 (GET_MODE_CLASS (GET_MODE (op0)));
9581 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9582 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9584 op0 = gen_lowpart (tmode, inner_op0);
9585 op1 = gen_lowpart (tmode, inner_op1);
9586 code = unsigned_condition (code);
9595 /* If both operands are NOT, we can strip off the outer operation
9596 and adjust the comparison code for swapped operands; similarly for
9597 NEG, except that this must be an equality comparison. */
9598 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9599 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9600 && (code == EQ || code == NE)))
9601 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9607 /* If the first operand is a constant, swap the operands and adjust the
9608 comparison code appropriately, but don't do this if the second operand
9609 is already a constant integer. */
9610 if (swap_commutative_operands_p (op0, op1))
9612 tem = op0, op0 = op1, op1 = tem;
9613 code = swap_condition (code);
9616 /* We now enter a loop during which we will try to simplify the comparison.
9617 For the most part, we only are concerned with comparisons with zero,
9618 but some things may really be comparisons with zero but not start
9619 out looking that way. */
9621 while (GET_CODE (op1) == CONST_INT)
9623 enum machine_mode mode = GET_MODE (op0);
9624 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9625 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9626 int equality_comparison_p;
9627 int sign_bit_comparison_p;
9628 int unsigned_comparison_p;
9629 HOST_WIDE_INT const_op;
9631 /* We only want to handle integral modes. This catches VOIDmode,
9632 CCmode, and the floating-point modes. An exception is that we
9633 can handle VOIDmode if OP0 is a COMPARE or a comparison
9636 if (GET_MODE_CLASS (mode) != MODE_INT
9637 && ! (mode == VOIDmode
9638 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9641 /* Get the constant we are comparing against and turn off all bits
9642 not on in our mode. */
9643 const_op = INTVAL (op1);
9644 if (mode != VOIDmode)
9645 const_op = trunc_int_for_mode (const_op, mode);
9646 op1 = GEN_INT (const_op);
9648 /* If we are comparing against a constant power of two and the value
9649 being compared can only have that single bit nonzero (e.g., it was
9650 `and'ed with that bit), we can replace this with a comparison
9653 && (code == EQ || code == NE || code == GE || code == GEU
9654 || code == LT || code == LTU)
9655 && mode_width <= HOST_BITS_PER_WIDE_INT
9656 && exact_log2 (const_op) >= 0
9657 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9659 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9660 op1 = const0_rtx, const_op = 0;
9663 /* Similarly, if we are comparing a value known to be either -1 or
9664 0 with -1, change it to the opposite comparison against zero. */
9667 && (code == EQ || code == NE || code == GT || code == LE
9668 || code == GEU || code == LTU)
9669 && num_sign_bit_copies (op0, mode) == mode_width)
9671 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9672 op1 = const0_rtx, const_op = 0;
9675 /* Do some canonicalizations based on the comparison code. We prefer
9676 comparisons against zero and then prefer equality comparisons.
9677 If we can reduce the size of a constant, we will do that too. */
9682 /* < C is equivalent to <= (C - 1) */
9686 op1 = GEN_INT (const_op);
9688 /* ... fall through to LE case below. */
9694 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9698 op1 = GEN_INT (const_op);
9702 /* If we are doing a <= 0 comparison on a value known to have
9703 a zero sign bit, we can replace this with == 0. */
9704 else if (const_op == 0
9705 && mode_width <= HOST_BITS_PER_WIDE_INT
9706 && (nonzero_bits (op0, mode)
9707 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9712 /* >= C is equivalent to > (C - 1). */
9716 op1 = GEN_INT (const_op);
9718 /* ... fall through to GT below. */
9724 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9728 op1 = GEN_INT (const_op);
9732 /* If we are doing a > 0 comparison on a value known to have
9733 a zero sign bit, we can replace this with != 0. */
9734 else if (const_op == 0
9735 && mode_width <= HOST_BITS_PER_WIDE_INT
9736 && (nonzero_bits (op0, mode)
9737 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9742 /* < C is equivalent to <= (C - 1). */
9746 op1 = GEN_INT (const_op);
9748 /* ... fall through ... */
9751 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9752 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9753 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9755 const_op = 0, op1 = const0_rtx;
9763 /* unsigned <= 0 is equivalent to == 0 */
9767 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9768 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9769 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9771 const_op = 0, op1 = const0_rtx;
9777 /* >= C is equivalent to > (C - 1). */
9781 op1 = GEN_INT (const_op);
9783 /* ... fall through ... */
9786 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9787 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9788 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9790 const_op = 0, op1 = const0_rtx;
9798 /* unsigned > 0 is equivalent to != 0 */
9802 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9803 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9804 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9806 const_op = 0, op1 = const0_rtx;
9815 /* Compute some predicates to simplify code below. */
9817 equality_comparison_p = (code == EQ || code == NE);
9818 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9819 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9822 /* If this is a sign bit comparison and we can do arithmetic in
9823 MODE, say that we will only be needing the sign bit of OP0. */
9824 if (sign_bit_comparison_p
9825 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9826 op0 = force_to_mode (op0, mode,
9828 << (GET_MODE_BITSIZE (mode) - 1)),
9831 /* Now try cases based on the opcode of OP0. If none of the cases
9832 does a "continue", we exit this loop immediately after the
9835 switch (GET_CODE (op0))
9838 /* If we are extracting a single bit from a variable position in
9839 a constant that has only a single bit set and are comparing it
9840 with zero, we can convert this into an equality comparison
9841 between the position and the location of the single bit. */
9842 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9843 have already reduced the shift count modulo the word size. */
9844 if (!SHIFT_COUNT_TRUNCATED
9845 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9846 && XEXP (op0, 1) == const1_rtx
9847 && equality_comparison_p && const_op == 0
9848 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9850 if (BITS_BIG_ENDIAN)
9852 enum machine_mode new_mode
9853 = mode_for_extraction (EP_extzv, 1);
9854 if (new_mode == MAX_MACHINE_MODE)
9855 i = BITS_PER_WORD - 1 - i;
9859 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9863 op0 = XEXP (op0, 2);
9867 /* Result is nonzero iff shift count is equal to I. */
9868 code = reverse_condition (code);
9872 /* ... fall through ... */
9875 tem = expand_compound_operation (op0);
9884 /* If testing for equality, we can take the NOT of the constant. */
9885 if (equality_comparison_p
9886 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9888 op0 = XEXP (op0, 0);
9893 /* If just looking at the sign bit, reverse the sense of the
9895 if (sign_bit_comparison_p)
9897 op0 = XEXP (op0, 0);
9898 code = (code == GE ? LT : GE);
9904 /* If testing for equality, we can take the NEG of the constant. */
9905 if (equality_comparison_p
9906 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9908 op0 = XEXP (op0, 0);
9913 /* The remaining cases only apply to comparisons with zero. */
9917 /* When X is ABS or is known positive,
9918 (neg X) is < 0 if and only if X != 0. */
9920 if (sign_bit_comparison_p
9921 && (GET_CODE (XEXP (op0, 0)) == ABS
9922 || (mode_width <= HOST_BITS_PER_WIDE_INT
9923 && (nonzero_bits (XEXP (op0, 0), mode)
9924 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9926 op0 = XEXP (op0, 0);
9927 code = (code == LT ? NE : EQ);
9931 /* If we have NEG of something whose two high-order bits are the
9932 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9933 if (num_sign_bit_copies (op0, mode) >= 2)
9935 op0 = XEXP (op0, 0);
9936 code = swap_condition (code);
9942 /* If we are testing equality and our count is a constant, we
9943 can perform the inverse operation on our RHS. */
9944 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9945 && (tem = simplify_binary_operation (ROTATERT, mode,
9946 op1, XEXP (op0, 1))) != 0)
9948 op0 = XEXP (op0, 0);
9953 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9954 a particular bit. Convert it to an AND of a constant of that
9955 bit. This will be converted into a ZERO_EXTRACT. */
9956 if (const_op == 0 && sign_bit_comparison_p
9957 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9958 && mode_width <= HOST_BITS_PER_WIDE_INT)
9960 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9963 - INTVAL (XEXP (op0, 1)))));
9964 code = (code == LT ? NE : EQ);
9971 /* ABS is ignorable inside an equality comparison with zero. */
9972 if (const_op == 0 && equality_comparison_p)
9974 op0 = XEXP (op0, 0);
9980 /* Can simplify (compare (zero/sign_extend FOO) CONST)
9981 to (compare FOO CONST) if CONST fits in FOO's mode and we
9982 are either testing inequality or have an unsigned comparison
9983 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
9984 if (! unsigned_comparison_p
9985 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
9986 <= HOST_BITS_PER_WIDE_INT)
9987 && ((unsigned HOST_WIDE_INT) const_op
9988 < (((unsigned HOST_WIDE_INT) 1
9989 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0))) - 1)))))
9991 op0 = XEXP (op0, 0);
9997 /* Check for the case where we are comparing A - C1 with C2,
9998 both constants are smaller than 1/2 the maximum positive
9999 value in MODE, and the comparison is equality or unsigned.
10000 In that case, if A is either zero-extended to MODE or has
10001 sufficient sign bits so that the high-order bit in MODE
10002 is a copy of the sign in the inner mode, we can prove that it is
10003 safe to do the operation in the wider mode. This simplifies
10004 many range checks. */
10006 if (mode_width <= HOST_BITS_PER_WIDE_INT
10007 && subreg_lowpart_p (op0)
10008 && GET_CODE (SUBREG_REG (op0)) == PLUS
10009 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT
10010 && INTVAL (XEXP (SUBREG_REG (op0), 1)) < 0
10011 && (-INTVAL (XEXP (SUBREG_REG (op0), 1))
10012 < (HOST_WIDE_INT) (GET_MODE_MASK (mode) / 2))
10013 && (unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode) / 2
10014 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0), 0),
10015 GET_MODE (SUBREG_REG (op0)))
10016 & ~GET_MODE_MASK (mode))
10017 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0), 0),
10018 GET_MODE (SUBREG_REG (op0)))
10020 (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10021 - GET_MODE_BITSIZE (mode)))))
10023 op0 = SUBREG_REG (op0);
10027 /* If the inner mode is narrower and we are extracting the low part,
10028 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10029 if (subreg_lowpart_p (op0)
10030 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
10031 /* Fall through */ ;
10035 /* ... fall through ... */
10038 if ((unsigned_comparison_p || equality_comparison_p)
10039 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0, 0)))
10040 <= HOST_BITS_PER_WIDE_INT)
10041 && ((unsigned HOST_WIDE_INT) const_op
10042 < GET_MODE_MASK (GET_MODE (XEXP (op0, 0)))))
10044 op0 = XEXP (op0, 0);
10050 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10051 this for equality comparisons due to pathological cases involving
10053 if (equality_comparison_p
10054 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10055 op1, XEXP (op0, 1))))
10057 op0 = XEXP (op0, 0);
10062 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10063 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
10064 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
10066 op0 = XEXP (XEXP (op0, 0), 0);
10067 code = (code == LT ? EQ : NE);
10073 /* We used to optimize signed comparisons against zero, but that
10074 was incorrect. Unsigned comparisons against zero (GTU, LEU)
10075 arrive here as equality comparisons, or (GEU, LTU) are
10076 optimized away. No need to special-case them. */
10078 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10079 (eq B (minus A C)), whichever simplifies. We can only do
10080 this for equality comparisons due to pathological cases involving
10082 if (equality_comparison_p
10083 && 0 != (tem = simplify_binary_operation (PLUS, mode,
10084 XEXP (op0, 1), op1)))
10086 op0 = XEXP (op0, 0);
10091 if (equality_comparison_p
10092 && 0 != (tem = simplify_binary_operation (MINUS, mode,
10093 XEXP (op0, 0), op1)))
10095 op0 = XEXP (op0, 1);
10100 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10101 of bits in X minus 1, is one iff X > 0. */
10102 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
10103 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10104 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
10106 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10108 op0 = XEXP (op0, 1);
10109 code = (code == GE ? LE : GT);
10115 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10116 if C is zero or B is a constant. */
10117 if (equality_comparison_p
10118 && 0 != (tem = simplify_binary_operation (XOR, mode,
10119 XEXP (op0, 1), op1)))
10121 op0 = XEXP (op0, 0);
10128 case UNEQ: case LTGT:
10129 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
10130 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
10131 case UNORDERED: case ORDERED:
10132 /* We can't do anything if OP0 is a condition code value, rather
10133 than an actual data value. */
10135 || CC0_P (XEXP (op0, 0))
10136 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
10139 /* Get the two operands being compared. */
10140 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
10141 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
10143 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
10145 /* Check for the cases where we simply want the result of the
10146 earlier test or the opposite of that result. */
10147 if (code == NE || code == EQ
10148 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
10149 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10150 && (STORE_FLAG_VALUE
10151 & (((HOST_WIDE_INT) 1
10152 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
10153 && (code == LT || code == GE)))
10155 enum rtx_code new_code;
10156 if (code == LT || code == NE)
10157 new_code = GET_CODE (op0);
10159 new_code = combine_reversed_comparison_code (op0);
10161 if (new_code != UNKNOWN)
10172 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10174 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10175 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10176 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10178 op0 = XEXP (op0, 1);
10179 code = (code == GE ? GT : LE);
10185 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10186 will be converted to a ZERO_EXTRACT later. */
10187 if (const_op == 0 && equality_comparison_p
10188 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10189 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10191 op0 = simplify_and_const_int
10192 (op0, mode, gen_rtx_LSHIFTRT (mode,
10194 XEXP (XEXP (op0, 0), 1)),
10195 (HOST_WIDE_INT) 1);
10199 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10200 zero and X is a comparison and C1 and C2 describe only bits set
10201 in STORE_FLAG_VALUE, we can compare with X. */
10202 if (const_op == 0 && equality_comparison_p
10203 && mode_width <= HOST_BITS_PER_WIDE_INT
10204 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10205 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10206 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10207 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10208 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10210 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10211 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10212 if ((~STORE_FLAG_VALUE & mask) == 0
10213 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10214 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10215 && COMPARISON_P (tem))))
10217 op0 = XEXP (XEXP (op0, 0), 0);
10222 /* If we are doing an equality comparison of an AND of a bit equal
10223 to the sign bit, replace this with a LT or GE comparison of
10224 the underlying value. */
10225 if (equality_comparison_p
10227 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10228 && mode_width <= HOST_BITS_PER_WIDE_INT
10229 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10230 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10232 op0 = XEXP (op0, 0);
10233 code = (code == EQ ? GE : LT);
10237 /* If this AND operation is really a ZERO_EXTEND from a narrower
10238 mode, the constant fits within that mode, and this is either an
10239 equality or unsigned comparison, try to do this comparison in
10240 the narrower mode. */
10241 if ((equality_comparison_p || unsigned_comparison_p)
10242 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10243 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10244 & GET_MODE_MASK (mode))
10246 && const_op >> i == 0
10247 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10249 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10253 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10254 fits in both M1 and M2 and the SUBREG is either paradoxical
10255 or represents the low part, permute the SUBREG and the AND
10257 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10259 unsigned HOST_WIDE_INT c1;
10260 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10261 /* Require an integral mode, to avoid creating something like
10263 if (SCALAR_INT_MODE_P (tmode)
10264 /* It is unsafe to commute the AND into the SUBREG if the
10265 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10266 not defined. As originally written the upper bits
10267 have a defined value due to the AND operation.
10268 However, if we commute the AND inside the SUBREG then
10269 they no longer have defined values and the meaning of
10270 the code has been changed. */
10272 #ifdef WORD_REGISTER_OPERATIONS
10273 || (mode_width > GET_MODE_BITSIZE (tmode)
10274 && mode_width <= BITS_PER_WORD)
10276 || (mode_width <= GET_MODE_BITSIZE (tmode)
10277 && subreg_lowpart_p (XEXP (op0, 0))))
10278 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10279 && mode_width <= HOST_BITS_PER_WIDE_INT
10280 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10281 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10282 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10284 && c1 != GET_MODE_MASK (tmode))
10286 op0 = gen_binary (AND, tmode,
10287 SUBREG_REG (XEXP (op0, 0)),
10288 gen_int_mode (c1, tmode));
10289 op0 = gen_lowpart (mode, op0);
10294 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10295 if (const_op == 0 && equality_comparison_p
10296 && XEXP (op0, 1) == const1_rtx
10297 && GET_CODE (XEXP (op0, 0)) == NOT)
10299 op0 = simplify_and_const_int
10300 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10301 code = (code == NE ? EQ : NE);
10305 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10306 (eq (and (lshiftrt X) 1) 0).
10307 Also handle the case where (not X) is expressed using xor. */
10308 if (const_op == 0 && equality_comparison_p
10309 && XEXP (op0, 1) == const1_rtx
10310 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10312 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10313 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10315 if (GET_CODE (shift_op) == NOT
10316 || (GET_CODE (shift_op) == XOR
10317 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10318 && GET_CODE (shift_count) == CONST_INT
10319 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10320 && (INTVAL (XEXP (shift_op, 1))
10321 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10323 op0 = simplify_and_const_int
10325 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10326 (HOST_WIDE_INT) 1);
10327 code = (code == NE ? EQ : NE);
10334 /* If we have (compare (ashift FOO N) (const_int C)) and
10335 the high order N bits of FOO (N+1 if an inequality comparison)
10336 are known to be zero, we can do this by comparing FOO with C
10337 shifted right N bits so long as the low-order N bits of C are
10339 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10340 && INTVAL (XEXP (op0, 1)) >= 0
10341 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10342 < HOST_BITS_PER_WIDE_INT)
10344 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10345 && mode_width <= HOST_BITS_PER_WIDE_INT
10346 && (nonzero_bits (XEXP (op0, 0), mode)
10347 & ~(mask >> (INTVAL (XEXP (op0, 1))
10348 + ! equality_comparison_p))) == 0)
10350 /* We must perform a logical shift, not an arithmetic one,
10351 as we want the top N bits of C to be zero. */
10352 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10354 temp >>= INTVAL (XEXP (op0, 1));
10355 op1 = gen_int_mode (temp, mode);
10356 op0 = XEXP (op0, 0);
10360 /* If we are doing a sign bit comparison, it means we are testing
10361 a particular bit. Convert it to the appropriate AND. */
10362 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10363 && mode_width <= HOST_BITS_PER_WIDE_INT)
10365 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10368 - INTVAL (XEXP (op0, 1)))));
10369 code = (code == LT ? NE : EQ);
10373 /* If this an equality comparison with zero and we are shifting
10374 the low bit to the sign bit, we can convert this to an AND of the
10376 if (const_op == 0 && equality_comparison_p
10377 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10378 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10381 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10382 (HOST_WIDE_INT) 1);
10388 /* If this is an equality comparison with zero, we can do this
10389 as a logical shift, which might be much simpler. */
10390 if (equality_comparison_p && const_op == 0
10391 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10393 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10395 INTVAL (XEXP (op0, 1)));
10399 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10400 do the comparison in a narrower mode. */
10401 if (! unsigned_comparison_p
10402 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10403 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10404 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10405 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10406 MODE_INT, 1)) != BLKmode
10407 && (((unsigned HOST_WIDE_INT) const_op
10408 + (GET_MODE_MASK (tmode) >> 1) + 1)
10409 <= GET_MODE_MASK (tmode)))
10411 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10415 /* Likewise if OP0 is a PLUS of a sign extension with a
10416 constant, which is usually represented with the PLUS
10417 between the shifts. */
10418 if (! unsigned_comparison_p
10419 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10420 && GET_CODE (XEXP (op0, 0)) == PLUS
10421 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10422 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10423 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10424 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10425 MODE_INT, 1)) != BLKmode
10426 && (((unsigned HOST_WIDE_INT) const_op
10427 + (GET_MODE_MASK (tmode) >> 1) + 1)
10428 <= GET_MODE_MASK (tmode)))
10430 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10431 rtx add_const = XEXP (XEXP (op0, 0), 1);
10432 rtx new_const = gen_binary (ASHIFTRT, GET_MODE (op0), add_const,
10435 op0 = gen_binary (PLUS, tmode,
10436 gen_lowpart (tmode, inner),
10441 /* ... fall through ... */
10443 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10444 the low order N bits of FOO are known to be zero, we can do this
10445 by comparing FOO with C shifted left N bits so long as no
10446 overflow occurs. */
10447 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10448 && INTVAL (XEXP (op0, 1)) >= 0
10449 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10450 && mode_width <= HOST_BITS_PER_WIDE_INT
10451 && (nonzero_bits (XEXP (op0, 0), mode)
10452 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10453 && (((unsigned HOST_WIDE_INT) const_op
10454 + (GET_CODE (op0) != LSHIFTRT
10455 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10458 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10460 /* If the shift was logical, then we must make the condition
10462 if (GET_CODE (op0) == LSHIFTRT)
10463 code = unsigned_condition (code);
10465 const_op <<= INTVAL (XEXP (op0, 1));
10466 op1 = GEN_INT (const_op);
10467 op0 = XEXP (op0, 0);
10471 /* If we are using this shift to extract just the sign bit, we
10472 can replace this with an LT or GE comparison. */
10474 && (equality_comparison_p || sign_bit_comparison_p)
10475 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10476 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10479 op0 = XEXP (op0, 0);
10480 code = (code == NE || code == GT ? LT : GE);
10492 /* Now make any compound operations involved in this comparison. Then,
10493 check for an outmost SUBREG on OP0 that is not doing anything or is
10494 paradoxical. The latter transformation must only be performed when
10495 it is known that the "extra" bits will be the same in op0 and op1 or
10496 that they don't matter. There are three cases to consider:
10498 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10499 care bits and we can assume they have any convenient value. So
10500 making the transformation is safe.
10502 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10503 In this case the upper bits of op0 are undefined. We should not make
10504 the simplification in that case as we do not know the contents of
10507 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10508 UNKNOWN. In that case we know those bits are zeros or ones. We must
10509 also be sure that they are the same as the upper bits of op1.
10511 We can never remove a SUBREG for a non-equality comparison because
10512 the sign bit is in a different place in the underlying object. */
10514 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10515 op1 = make_compound_operation (op1, SET);
10517 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10518 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10519 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10520 && (code == NE || code == EQ))
10522 if (GET_MODE_SIZE (GET_MODE (op0))
10523 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10525 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10527 if (REG_P (SUBREG_REG (op0)))
10529 op0 = SUBREG_REG (op0);
10530 op1 = gen_lowpart (GET_MODE (op0), op1);
10533 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10534 <= HOST_BITS_PER_WIDE_INT)
10535 && (nonzero_bits (SUBREG_REG (op0),
10536 GET_MODE (SUBREG_REG (op0)))
10537 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10539 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10541 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10542 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10543 op0 = SUBREG_REG (op0), op1 = tem;
10547 /* We now do the opposite procedure: Some machines don't have compare
10548 insns in all modes. If OP0's mode is an integer mode smaller than a
10549 word and we can't do a compare in that mode, see if there is a larger
10550 mode for which we can do the compare. There are a number of cases in
10551 which we can use the wider mode. */
10553 mode = GET_MODE (op0);
10554 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10555 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10556 && ! have_insn_for (COMPARE, mode))
10557 for (tmode = GET_MODE_WIDER_MODE (mode);
10559 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10560 tmode = GET_MODE_WIDER_MODE (tmode))
10561 if (have_insn_for (COMPARE, tmode))
10565 /* If the only nonzero bits in OP0 and OP1 are those in the
10566 narrower mode and this is an equality or unsigned comparison,
10567 we can use the wider mode. Similarly for sign-extended
10568 values, in which case it is true for all comparisons. */
10569 zero_extended = ((code == EQ || code == NE
10570 || code == GEU || code == GTU
10571 || code == LEU || code == LTU)
10572 && (nonzero_bits (op0, tmode)
10573 & ~GET_MODE_MASK (mode)) == 0
10574 && ((GET_CODE (op1) == CONST_INT
10575 || (nonzero_bits (op1, tmode)
10576 & ~GET_MODE_MASK (mode)) == 0)));
10579 || ((num_sign_bit_copies (op0, tmode)
10580 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10581 - GET_MODE_BITSIZE (mode)))
10582 && (num_sign_bit_copies (op1, tmode)
10583 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10584 - GET_MODE_BITSIZE (mode)))))
10586 /* If OP0 is an AND and we don't have an AND in MODE either,
10587 make a new AND in the proper mode. */
10588 if (GET_CODE (op0) == AND
10589 && !have_insn_for (AND, mode))
10590 op0 = gen_binary (AND, tmode,
10591 gen_lowpart (tmode,
10593 gen_lowpart (tmode,
10596 op0 = gen_lowpart (tmode, op0);
10597 if (zero_extended && GET_CODE (op1) == CONST_INT)
10598 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10599 op1 = gen_lowpart (tmode, op1);
10603 /* If this is a test for negative, we can make an explicit
10604 test of the sign bit. */
10606 if (op1 == const0_rtx && (code == LT || code == GE)
10607 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10609 op0 = gen_binary (AND, tmode,
10610 gen_lowpart (tmode, op0),
10611 GEN_INT ((HOST_WIDE_INT) 1
10612 << (GET_MODE_BITSIZE (mode) - 1)));
10613 code = (code == LT) ? NE : EQ;
10618 #ifdef CANONICALIZE_COMPARISON
10619 /* If this machine only supports a subset of valid comparisons, see if we
10620 can convert an unsupported one into a supported one. */
10621 CANONICALIZE_COMPARISON (code, op0, op1);
10630 /* Like jump.c' reversed_comparison_code, but use combine infrastructure for
10631 searching backward. */
10632 static enum rtx_code
10633 combine_reversed_comparison_code (rtx exp)
10635 enum rtx_code code1 = reversed_comparison_code (exp, NULL);
10638 if (code1 != UNKNOWN
10639 || GET_MODE_CLASS (GET_MODE (XEXP (exp, 0))) != MODE_CC)
10641 /* Otherwise try and find where the condition codes were last set and
10643 x = get_last_value (XEXP (exp, 0));
10644 if (!x || GET_CODE (x) != COMPARE)
10646 return reversed_comparison_code_parts (GET_CODE (exp),
10647 XEXP (x, 0), XEXP (x, 1), NULL);
10650 /* Return comparison with reversed code of EXP and operands OP0 and OP1.
10651 Return NULL_RTX in case we fail to do the reversal. */
10653 reversed_comparison (rtx exp, enum machine_mode mode, rtx op0, rtx op1)
10655 enum rtx_code reversed_code = combine_reversed_comparison_code (exp);
10656 if (reversed_code == UNKNOWN)
10659 return gen_binary (reversed_code, mode, op0, op1);
10662 /* Utility function for following routine. Called when X is part of a value
10663 being stored into last_set_value. Sets last_set_table_tick
10664 for each register mentioned. Similar to mention_regs in cse.c */
10667 update_table_tick (rtx x)
10669 enum rtx_code code = GET_CODE (x);
10670 const char *fmt = GET_RTX_FORMAT (code);
10675 unsigned int regno = REGNO (x);
10676 unsigned int endregno
10677 = regno + (regno < FIRST_PSEUDO_REGISTER
10678 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10681 for (r = regno; r < endregno; r++)
10682 reg_stat[r].last_set_table_tick = label_tick;
10687 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10688 /* Note that we can't have an "E" in values stored; see
10689 get_last_value_validate. */
10692 /* Check for identical subexpressions. If x contains
10693 identical subexpression we only have to traverse one of
10695 if (i == 0 && ARITHMETIC_P (x))
10697 /* Note that at this point x1 has already been
10699 rtx x0 = XEXP (x, 0);
10700 rtx x1 = XEXP (x, 1);
10702 /* If x0 and x1 are identical then there is no need to
10707 /* If x0 is identical to a subexpression of x1 then while
10708 processing x1, x0 has already been processed. Thus we
10709 are done with x. */
10710 if (ARITHMETIC_P (x1)
10711 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10714 /* If x1 is identical to a subexpression of x0 then we
10715 still have to process the rest of x0. */
10716 if (ARITHMETIC_P (x0)
10717 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10719 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10724 update_table_tick (XEXP (x, i));
10728 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10729 are saying that the register is clobbered and we no longer know its
10730 value. If INSN is zero, don't update reg_stat[].last_set; this is
10731 only permitted with VALUE also zero and is used to invalidate the
10735 record_value_for_reg (rtx reg, rtx insn, rtx value)
10737 unsigned int regno = REGNO (reg);
10738 unsigned int endregno
10739 = regno + (regno < FIRST_PSEUDO_REGISTER
10740 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10743 /* If VALUE contains REG and we have a previous value for REG, substitute
10744 the previous value. */
10745 if (value && insn && reg_overlap_mentioned_p (reg, value))
10749 /* Set things up so get_last_value is allowed to see anything set up to
10751 subst_low_cuid = INSN_CUID (insn);
10752 tem = get_last_value (reg);
10754 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10755 it isn't going to be useful and will take a lot of time to process,
10756 so just use the CLOBBER. */
10760 if (ARITHMETIC_P (tem)
10761 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10762 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10763 tem = XEXP (tem, 0);
10765 value = replace_rtx (copy_rtx (value), reg, tem);
10769 /* For each register modified, show we don't know its value, that
10770 we don't know about its bitwise content, that its value has been
10771 updated, and that we don't know the location of the death of the
10773 for (i = regno; i < endregno; i++)
10776 reg_stat[i].last_set = insn;
10778 reg_stat[i].last_set_value = 0;
10779 reg_stat[i].last_set_mode = 0;
10780 reg_stat[i].last_set_nonzero_bits = 0;
10781 reg_stat[i].last_set_sign_bit_copies = 0;
10782 reg_stat[i].last_death = 0;
10785 /* Mark registers that are being referenced in this value. */
10787 update_table_tick (value);
10789 /* Now update the status of each register being set.
10790 If someone is using this register in this block, set this register
10791 to invalid since we will get confused between the two lives in this
10792 basic block. This makes using this register always invalid. In cse, we
10793 scan the table to invalidate all entries using this register, but this
10794 is too much work for us. */
10796 for (i = regno; i < endregno; i++)
10798 reg_stat[i].last_set_label = label_tick;
10799 if (value && reg_stat[i].last_set_table_tick == label_tick)
10800 reg_stat[i].last_set_invalid = 1;
10802 reg_stat[i].last_set_invalid = 0;
10805 /* The value being assigned might refer to X (like in "x++;"). In that
10806 case, we must replace it with (clobber (const_int 0)) to prevent
10808 if (value && ! get_last_value_validate (&value, insn,
10809 reg_stat[regno].last_set_label, 0))
10811 value = copy_rtx (value);
10812 if (! get_last_value_validate (&value, insn,
10813 reg_stat[regno].last_set_label, 1))
10817 /* For the main register being modified, update the value, the mode, the
10818 nonzero bits, and the number of sign bit copies. */
10820 reg_stat[regno].last_set_value = value;
10824 enum machine_mode mode = GET_MODE (reg);
10825 subst_low_cuid = INSN_CUID (insn);
10826 reg_stat[regno].last_set_mode = mode;
10827 if (GET_MODE_CLASS (mode) == MODE_INT
10828 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10829 mode = nonzero_bits_mode;
10830 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10831 reg_stat[regno].last_set_sign_bit_copies
10832 = num_sign_bit_copies (value, GET_MODE (reg));
10836 /* Called via note_stores from record_dead_and_set_regs to handle one
10837 SET or CLOBBER in an insn. DATA is the instruction in which the
10838 set is occurring. */
10841 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10843 rtx record_dead_insn = (rtx) data;
10845 if (GET_CODE (dest) == SUBREG)
10846 dest = SUBREG_REG (dest);
10850 /* If we are setting the whole register, we know its value. Otherwise
10851 show that we don't know the value. We can handle SUBREG in
10853 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10854 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10855 else if (GET_CODE (setter) == SET
10856 && GET_CODE (SET_DEST (setter)) == SUBREG
10857 && SUBREG_REG (SET_DEST (setter)) == dest
10858 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10859 && subreg_lowpart_p (SET_DEST (setter)))
10860 record_value_for_reg (dest, record_dead_insn,
10861 gen_lowpart (GET_MODE (dest),
10862 SET_SRC (setter)));
10864 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10866 else if (MEM_P (dest)
10867 /* Ignore pushes, they clobber nothing. */
10868 && ! push_operand (dest, GET_MODE (dest)))
10869 mem_last_set = INSN_CUID (record_dead_insn);
10872 /* Update the records of when each REG was most recently set or killed
10873 for the things done by INSN. This is the last thing done in processing
10874 INSN in the combiner loop.
10876 We update reg_stat[], in particular fields last_set, last_set_value,
10877 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10878 last_death, and also the similar information mem_last_set (which insn
10879 most recently modified memory) and last_call_cuid (which insn was the
10880 most recent subroutine call). */
10883 record_dead_and_set_regs (rtx insn)
10888 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10890 if (REG_NOTE_KIND (link) == REG_DEAD
10891 && REG_P (XEXP (link, 0)))
10893 unsigned int regno = REGNO (XEXP (link, 0));
10894 unsigned int endregno
10895 = regno + (regno < FIRST_PSEUDO_REGISTER
10896 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10899 for (i = regno; i < endregno; i++)
10900 reg_stat[i].last_death = insn;
10902 else if (REG_NOTE_KIND (link) == REG_INC)
10903 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10908 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10909 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10911 reg_stat[i].last_set_value = 0;
10912 reg_stat[i].last_set_mode = 0;
10913 reg_stat[i].last_set_nonzero_bits = 0;
10914 reg_stat[i].last_set_sign_bit_copies = 0;
10915 reg_stat[i].last_death = 0;
10918 last_call_cuid = mem_last_set = INSN_CUID (insn);
10920 /* Don't bother recording what this insn does. It might set the
10921 return value register, but we can't combine into a call
10922 pattern anyway, so there's no point trying (and it may cause
10923 a crash, if e.g. we wind up asking for last_set_value of a
10924 SUBREG of the return value register). */
10928 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10931 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10932 register present in the SUBREG, so for each such SUBREG go back and
10933 adjust nonzero and sign bit information of the registers that are
10934 known to have some zero/sign bits set.
10936 This is needed because when combine blows the SUBREGs away, the
10937 information on zero/sign bits is lost and further combines can be
10938 missed because of that. */
10941 record_promoted_value (rtx insn, rtx subreg)
10944 unsigned int regno = REGNO (SUBREG_REG (subreg));
10945 enum machine_mode mode = GET_MODE (subreg);
10947 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10950 for (links = LOG_LINKS (insn); links;)
10952 insn = XEXP (links, 0);
10953 set = single_set (insn);
10955 if (! set || !REG_P (SET_DEST (set))
10956 || REGNO (SET_DEST (set)) != regno
10957 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10959 links = XEXP (links, 1);
10963 if (reg_stat[regno].last_set == insn)
10965 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
10966 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
10969 if (REG_P (SET_SRC (set)))
10971 regno = REGNO (SET_SRC (set));
10972 links = LOG_LINKS (insn);
10979 /* Scan X for promoted SUBREGs. For each one found,
10980 note what it implies to the registers used in it. */
10983 check_promoted_subreg (rtx insn, rtx x)
10985 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
10986 && REG_P (SUBREG_REG (x)))
10987 record_promoted_value (insn, x);
10990 const char *format = GET_RTX_FORMAT (GET_CODE (x));
10993 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
10997 check_promoted_subreg (insn, XEXP (x, i));
11001 if (XVEC (x, i) != 0)
11002 for (j = 0; j < XVECLEN (x, i); j++)
11003 check_promoted_subreg (insn, XVECEXP (x, i, j));
11009 /* Utility routine for the following function. Verify that all the registers
11010 mentioned in *LOC are valid when *LOC was part of a value set when
11011 label_tick == TICK. Return 0 if some are not.
11013 If REPLACE is nonzero, replace the invalid reference with
11014 (clobber (const_int 0)) and return 1. This replacement is useful because
11015 we often can get useful information about the form of a value (e.g., if
11016 it was produced by a shift that always produces -1 or 0) even though
11017 we don't know exactly what registers it was produced from. */
11020 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
11023 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
11024 int len = GET_RTX_LENGTH (GET_CODE (x));
11029 unsigned int regno = REGNO (x);
11030 unsigned int endregno
11031 = regno + (regno < FIRST_PSEUDO_REGISTER
11032 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11035 for (j = regno; j < endregno; j++)
11036 if (reg_stat[j].last_set_invalid
11037 /* If this is a pseudo-register that was only set once and not
11038 live at the beginning of the function, it is always valid. */
11039 || (! (regno >= FIRST_PSEUDO_REGISTER
11040 && REG_N_SETS (regno) == 1
11041 && (! REGNO_REG_SET_P
11042 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))
11043 && reg_stat[j].last_set_label > tick))
11046 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11052 /* If this is a memory reference, make sure that there were
11053 no stores after it that might have clobbered the value. We don't
11054 have alias info, so we assume any store invalidates it. */
11055 else if (MEM_P (x) && !MEM_READONLY_P (x)
11056 && INSN_CUID (insn) <= mem_last_set)
11059 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
11063 for (i = 0; i < len; i++)
11067 /* Check for identical subexpressions. If x contains
11068 identical subexpression we only have to traverse one of
11070 if (i == 1 && ARITHMETIC_P (x))
11072 /* Note that at this point x0 has already been checked
11073 and found valid. */
11074 rtx x0 = XEXP (x, 0);
11075 rtx x1 = XEXP (x, 1);
11077 /* If x0 and x1 are identical then x is also valid. */
11081 /* If x1 is identical to a subexpression of x0 then
11082 while checking x0, x1 has already been checked. Thus
11083 it is valid and so as x. */
11084 if (ARITHMETIC_P (x0)
11085 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
11088 /* If x0 is identical to a subexpression of x1 then x is
11089 valid iff the rest of x1 is valid. */
11090 if (ARITHMETIC_P (x1)
11091 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
11093 get_last_value_validate (&XEXP (x1,
11094 x0 == XEXP (x1, 0) ? 1 : 0),
11095 insn, tick, replace);
11098 if (get_last_value_validate (&XEXP (x, i), insn, tick,
11102 /* Don't bother with these. They shouldn't occur anyway. */
11103 else if (fmt[i] == 'E')
11107 /* If we haven't found a reason for it to be invalid, it is valid. */
11111 /* Get the last value assigned to X, if known. Some registers
11112 in the value may be replaced with (clobber (const_int 0)) if their value
11113 is known longer known reliably. */
11116 get_last_value (rtx x)
11118 unsigned int regno;
11121 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11122 then convert it to the desired mode. If this is a paradoxical SUBREG,
11123 we cannot predict what values the "extra" bits might have. */
11124 if (GET_CODE (x) == SUBREG
11125 && subreg_lowpart_p (x)
11126 && (GET_MODE_SIZE (GET_MODE (x))
11127 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
11128 && (value = get_last_value (SUBREG_REG (x))) != 0)
11129 return gen_lowpart (GET_MODE (x), value);
11135 value = reg_stat[regno].last_set_value;
11137 /* If we don't have a value, or if it isn't for this basic block and
11138 it's either a hard register, set more than once, or it's a live
11139 at the beginning of the function, return 0.
11141 Because if it's not live at the beginning of the function then the reg
11142 is always set before being used (is never used without being set).
11143 And, if it's set only once, and it's always set before use, then all
11144 uses must have the same last value, even if it's not from this basic
11148 || (reg_stat[regno].last_set_label != label_tick
11149 && (regno < FIRST_PSEUDO_REGISTER
11150 || REG_N_SETS (regno) != 1
11151 || (REGNO_REG_SET_P
11152 (ENTRY_BLOCK_PTR->next_bb->global_live_at_start, regno)))))
11155 /* If the value was set in a later insn than the ones we are processing,
11156 we can't use it even if the register was only set once. */
11157 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11160 /* If the value has all its registers valid, return it. */
11161 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11162 reg_stat[regno].last_set_label, 0))
11165 /* Otherwise, make a copy and replace any invalid register with
11166 (clobber (const_int 0)). If that fails for some reason, return 0. */
11168 value = copy_rtx (value);
11169 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11170 reg_stat[regno].last_set_label, 1))
11176 /* Return nonzero if expression X refers to a REG or to memory
11177 that is set in an instruction more recent than FROM_CUID. */
11180 use_crosses_set_p (rtx x, int from_cuid)
11184 enum rtx_code code = GET_CODE (x);
11188 unsigned int regno = REGNO (x);
11189 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11190 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11192 #ifdef PUSH_ROUNDING
11193 /* Don't allow uses of the stack pointer to be moved,
11194 because we don't know whether the move crosses a push insn. */
11195 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11198 for (; regno < endreg; regno++)
11199 if (reg_stat[regno].last_set
11200 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11205 if (code == MEM && mem_last_set > from_cuid)
11208 fmt = GET_RTX_FORMAT (code);
11210 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11215 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11216 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11219 else if (fmt[i] == 'e'
11220 && use_crosses_set_p (XEXP (x, i), from_cuid))
11226 /* Define three variables used for communication between the following
11229 static unsigned int reg_dead_regno, reg_dead_endregno;
11230 static int reg_dead_flag;
11232 /* Function called via note_stores from reg_dead_at_p.
11234 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11235 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11238 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11240 unsigned int regno, endregno;
11245 regno = REGNO (dest);
11246 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11247 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11249 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11250 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11253 /* Return nonzero if REG is known to be dead at INSN.
11255 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11256 referencing REG, it is dead. If we hit a SET referencing REG, it is
11257 live. Otherwise, see if it is live or dead at the start of the basic
11258 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11259 must be assumed to be always live. */
11262 reg_dead_at_p (rtx reg, rtx insn)
11267 /* Set variables for reg_dead_at_p_1. */
11268 reg_dead_regno = REGNO (reg);
11269 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11270 ? hard_regno_nregs[reg_dead_regno]
11276 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11277 we allow the machine description to decide whether use-and-clobber
11278 patterns are OK. */
11279 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11281 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11282 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11286 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11287 beginning of function. */
11288 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11289 insn = prev_nonnote_insn (insn))
11291 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11293 return reg_dead_flag == 1 ? 1 : 0;
11295 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11299 /* Get the basic block that we were in. */
11301 block = ENTRY_BLOCK_PTR->next_bb;
11304 FOR_EACH_BB (block)
11305 if (insn == BB_HEAD (block))
11308 if (block == EXIT_BLOCK_PTR)
11312 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11313 if (REGNO_REG_SET_P (block->global_live_at_start, i))
11319 /* Note hard registers in X that are used. This code is similar to
11320 that in flow.c, but much simpler since we don't care about pseudos. */
11323 mark_used_regs_combine (rtx x)
11325 RTX_CODE code = GET_CODE (x);
11326 unsigned int regno;
11339 case ADDR_DIFF_VEC:
11342 /* CC0 must die in the insn after it is set, so we don't need to take
11343 special note of it here. */
11349 /* If we are clobbering a MEM, mark any hard registers inside the
11350 address as used. */
11351 if (MEM_P (XEXP (x, 0)))
11352 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11357 /* A hard reg in a wide mode may really be multiple registers.
11358 If so, mark all of them just like the first. */
11359 if (regno < FIRST_PSEUDO_REGISTER)
11361 unsigned int endregno, r;
11363 /* None of this applies to the stack, frame or arg pointers. */
11364 if (regno == STACK_POINTER_REGNUM
11365 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11366 || regno == HARD_FRAME_POINTER_REGNUM
11368 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11369 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11371 || regno == FRAME_POINTER_REGNUM)
11374 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11375 for (r = regno; r < endregno; r++)
11376 SET_HARD_REG_BIT (newpat_used_regs, r);
11382 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11384 rtx testreg = SET_DEST (x);
11386 while (GET_CODE (testreg) == SUBREG
11387 || GET_CODE (testreg) == ZERO_EXTRACT
11388 || GET_CODE (testreg) == SIGN_EXTRACT
11389 || GET_CODE (testreg) == STRICT_LOW_PART)
11390 testreg = XEXP (testreg, 0);
11392 if (MEM_P (testreg))
11393 mark_used_regs_combine (XEXP (testreg, 0));
11395 mark_used_regs_combine (SET_SRC (x));
11403 /* Recursively scan the operands of this expression. */
11406 const char *fmt = GET_RTX_FORMAT (code);
11408 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11411 mark_used_regs_combine (XEXP (x, i));
11412 else if (fmt[i] == 'E')
11416 for (j = 0; j < XVECLEN (x, i); j++)
11417 mark_used_regs_combine (XVECEXP (x, i, j));
11423 /* Remove register number REGNO from the dead registers list of INSN.
11425 Return the note used to record the death, if there was one. */
11428 remove_death (unsigned int regno, rtx insn)
11430 rtx note = find_regno_note (insn, REG_DEAD, regno);
11434 REG_N_DEATHS (regno)--;
11435 remove_note (insn, note);
11441 /* For each register (hardware or pseudo) used within expression X, if its
11442 death is in an instruction with cuid between FROM_CUID (inclusive) and
11443 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11444 list headed by PNOTES.
11446 That said, don't move registers killed by maybe_kill_insn.
11448 This is done when X is being merged by combination into TO_INSN. These
11449 notes will then be distributed as needed. */
11452 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11457 enum rtx_code code = GET_CODE (x);
11461 unsigned int regno = REGNO (x);
11462 rtx where_dead = reg_stat[regno].last_death;
11463 rtx before_dead, after_dead;
11465 /* Don't move the register if it gets killed in between from and to. */
11466 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11467 && ! reg_referenced_p (x, maybe_kill_insn))
11470 /* WHERE_DEAD could be a USE insn made by combine, so first we
11471 make sure that we have insns with valid INSN_CUID values. */
11472 before_dead = where_dead;
11473 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11474 before_dead = PREV_INSN (before_dead);
11476 after_dead = where_dead;
11477 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11478 after_dead = NEXT_INSN (after_dead);
11480 if (before_dead && after_dead
11481 && INSN_CUID (before_dead) >= from_cuid
11482 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11483 || (where_dead != after_dead
11484 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11486 rtx note = remove_death (regno, where_dead);
11488 /* It is possible for the call above to return 0. This can occur
11489 when last_death points to I2 or I1 that we combined with.
11490 In that case make a new note.
11492 We must also check for the case where X is a hard register
11493 and NOTE is a death note for a range of hard registers
11494 including X. In that case, we must put REG_DEAD notes for
11495 the remaining registers in place of NOTE. */
11497 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11498 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11499 > GET_MODE_SIZE (GET_MODE (x))))
11501 unsigned int deadregno = REGNO (XEXP (note, 0));
11502 unsigned int deadend
11503 = (deadregno + hard_regno_nregs[deadregno]
11504 [GET_MODE (XEXP (note, 0))]);
11505 unsigned int ourend
11506 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11509 for (i = deadregno; i < deadend; i++)
11510 if (i < regno || i >= ourend)
11511 REG_NOTES (where_dead)
11512 = gen_rtx_EXPR_LIST (REG_DEAD,
11514 REG_NOTES (where_dead));
11517 /* If we didn't find any note, or if we found a REG_DEAD note that
11518 covers only part of the given reg, and we have a multi-reg hard
11519 register, then to be safe we must check for REG_DEAD notes
11520 for each register other than the first. They could have
11521 their own REG_DEAD notes lying around. */
11522 else if ((note == 0
11524 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11525 < GET_MODE_SIZE (GET_MODE (x)))))
11526 && regno < FIRST_PSEUDO_REGISTER
11527 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11529 unsigned int ourend
11530 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11531 unsigned int i, offset;
11535 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11539 for (i = regno + offset; i < ourend; i++)
11540 move_deaths (regno_reg_rtx[i],
11541 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11544 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11546 XEXP (note, 1) = *pnotes;
11550 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11552 REG_N_DEATHS (regno)++;
11558 else if (GET_CODE (x) == SET)
11560 rtx dest = SET_DEST (x);
11562 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11564 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11565 that accesses one word of a multi-word item, some
11566 piece of everything register in the expression is used by
11567 this insn, so remove any old death. */
11568 /* ??? So why do we test for equality of the sizes? */
11570 if (GET_CODE (dest) == ZERO_EXTRACT
11571 || GET_CODE (dest) == STRICT_LOW_PART
11572 || (GET_CODE (dest) == SUBREG
11573 && (((GET_MODE_SIZE (GET_MODE (dest))
11574 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11575 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11576 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11578 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11582 /* If this is some other SUBREG, we know it replaces the entire
11583 value, so use that as the destination. */
11584 if (GET_CODE (dest) == SUBREG)
11585 dest = SUBREG_REG (dest);
11587 /* If this is a MEM, adjust deaths of anything used in the address.
11588 For a REG (the only other possibility), the entire value is
11589 being replaced so the old value is not used in this insn. */
11592 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11597 else if (GET_CODE (x) == CLOBBER)
11600 len = GET_RTX_LENGTH (code);
11601 fmt = GET_RTX_FORMAT (code);
11603 for (i = 0; i < len; i++)
11608 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11609 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11612 else if (fmt[i] == 'e')
11613 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11617 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11618 pattern of an insn. X must be a REG. */
11621 reg_bitfield_target_p (rtx x, rtx body)
11625 if (GET_CODE (body) == SET)
11627 rtx dest = SET_DEST (body);
11629 unsigned int regno, tregno, endregno, endtregno;
11631 if (GET_CODE (dest) == ZERO_EXTRACT)
11632 target = XEXP (dest, 0);
11633 else if (GET_CODE (dest) == STRICT_LOW_PART)
11634 target = SUBREG_REG (XEXP (dest, 0));
11638 if (GET_CODE (target) == SUBREG)
11639 target = SUBREG_REG (target);
11641 if (!REG_P (target))
11644 tregno = REGNO (target), regno = REGNO (x);
11645 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11646 return target == x;
11648 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11649 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11651 return endregno > tregno && regno < endtregno;
11654 else if (GET_CODE (body) == PARALLEL)
11655 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11656 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11662 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11663 as appropriate. I3 and I2 are the insns resulting from the combination
11664 insns including FROM (I2 may be zero).
11666 Each note in the list is either ignored or placed on some insns, depending
11667 on the type of note. */
11670 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2)
11672 rtx note, next_note;
11675 for (note = notes; note; note = next_note)
11677 rtx place = 0, place2 = 0;
11679 /* If this NOTE references a pseudo register, ensure it references
11680 the latest copy of that register. */
11681 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11682 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11683 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11685 next_note = XEXP (note, 1);
11686 switch (REG_NOTE_KIND (note))
11690 /* Doesn't matter much where we put this, as long as it's somewhere.
11691 It is preferable to keep these notes on branches, which is most
11692 likely to be i3. */
11696 case REG_VALUE_PROFILE:
11697 /* Just get rid of this note, as it is unused later anyway. */
11700 case REG_NON_LOCAL_GOTO:
11705 gcc_assert (i2 && JUMP_P (i2));
11710 case REG_EH_REGION:
11711 /* These notes must remain with the call or trapping instruction. */
11714 else if (i2 && CALL_P (i2))
11718 gcc_assert (flag_non_call_exceptions);
11719 if (may_trap_p (i3))
11721 else if (i2 && may_trap_p (i2))
11723 /* ??? Otherwise assume we've combined things such that we
11724 can now prove that the instructions can't trap. Drop the
11725 note in this case. */
11729 case REG_ALWAYS_RETURN:
11732 /* These notes must remain with the call. It should not be
11733 possible for both I2 and I3 to be a call. */
11738 gcc_assert (i2 && CALL_P (i2));
11744 /* Any clobbers for i3 may still exist, and so we must process
11745 REG_UNUSED notes from that insn.
11747 Any clobbers from i2 or i1 can only exist if they were added by
11748 recog_for_combine. In that case, recog_for_combine created the
11749 necessary REG_UNUSED notes. Trying to keep any original
11750 REG_UNUSED notes from these insns can cause incorrect output
11751 if it is for the same register as the original i3 dest.
11752 In that case, we will notice that the register is set in i3,
11753 and then add a REG_UNUSED note for the destination of i3, which
11754 is wrong. However, it is possible to have REG_UNUSED notes from
11755 i2 or i1 for register which were both used and clobbered, so
11756 we keep notes from i2 or i1 if they will turn into REG_DEAD
11759 /* If this register is set or clobbered in I3, put the note there
11760 unless there is one already. */
11761 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11763 if (from_insn != i3)
11766 if (! (REG_P (XEXP (note, 0))
11767 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11768 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11771 /* Otherwise, if this register is used by I3, then this register
11772 now dies here, so we must put a REG_DEAD note here unless there
11774 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11775 && ! (REG_P (XEXP (note, 0))
11776 ? find_regno_note (i3, REG_DEAD,
11777 REGNO (XEXP (note, 0)))
11778 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11780 PUT_REG_NOTE_KIND (note, REG_DEAD);
11788 /* These notes say something about results of an insn. We can
11789 only support them if they used to be on I3 in which case they
11790 remain on I3. Otherwise they are ignored.
11792 If the note refers to an expression that is not a constant, we
11793 must also ignore the note since we cannot tell whether the
11794 equivalence is still true. It might be possible to do
11795 slightly better than this (we only have a problem if I2DEST
11796 or I1DEST is present in the expression), but it doesn't
11797 seem worth the trouble. */
11799 if (from_insn == i3
11800 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11805 case REG_NO_CONFLICT:
11806 /* These notes say something about how a register is used. They must
11807 be present on any use of the register in I2 or I3. */
11808 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11811 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11821 /* This can show up in several ways -- either directly in the
11822 pattern, or hidden off in the constant pool with (or without?)
11823 a REG_EQUAL note. */
11824 /* ??? Ignore the without-reg_equal-note problem for now. */
11825 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11826 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11827 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11828 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11832 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11833 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11834 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11835 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11843 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11844 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11845 if (place && JUMP_P (place))
11847 rtx label = JUMP_LABEL (place);
11850 JUMP_LABEL (place) = XEXP (note, 0);
11853 gcc_assert (label == XEXP (note, 0));
11854 if (LABEL_P (label))
11855 LABEL_NUSES (label)--;
11859 if (place2 && JUMP_P (place2))
11861 rtx label = JUMP_LABEL (place2);
11864 JUMP_LABEL (place2) = XEXP (note, 0);
11867 gcc_assert (label == XEXP (note, 0));
11868 if (LABEL_P (label))
11869 LABEL_NUSES (label)--;
11876 /* This note says something about the value of a register prior
11877 to the execution of an insn. It is too much trouble to see
11878 if the note is still correct in all situations. It is better
11879 to simply delete it. */
11883 /* If the insn previously containing this note still exists,
11884 put it back where it was. Otherwise move it to the previous
11885 insn. Adjust the corresponding REG_LIBCALL note. */
11886 if (!NOTE_P (from_insn))
11890 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11891 place = prev_real_insn (from_insn);
11893 XEXP (tem, 0) = place;
11894 /* If we're deleting the last remaining instruction of a
11895 libcall sequence, don't add the notes. */
11896 else if (XEXP (note, 0) == from_insn)
11898 /* Don't add the dangling REG_RETVAL note. */
11905 /* This is handled similarly to REG_RETVAL. */
11906 if (!NOTE_P (from_insn))
11910 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11911 place = next_real_insn (from_insn);
11913 XEXP (tem, 0) = place;
11914 /* If we're deleting the last remaining instruction of a
11915 libcall sequence, don't add the notes. */
11916 else if (XEXP (note, 0) == from_insn)
11918 /* Don't add the dangling REG_LIBCALL note. */
11925 /* If the register is used as an input in I3, it dies there.
11926 Similarly for I2, if it is nonzero and adjacent to I3.
11928 If the register is not used as an input in either I3 or I2
11929 and it is not one of the registers we were supposed to eliminate,
11930 there are two possibilities. We might have a non-adjacent I2
11931 or we might have somehow eliminated an additional register
11932 from a computation. For example, we might have had A & B where
11933 we discover that B will always be zero. In this case we will
11934 eliminate the reference to A.
11936 In both cases, we must search to see if we can find a previous
11937 use of A and put the death note there. */
11940 && CALL_P (from_insn)
11941 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11943 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11945 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11946 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11951 basic_block bb = this_basic_block;
11953 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11955 if (! INSN_P (tem))
11957 if (tem == BB_HEAD (bb))
11962 /* If the register is being set at TEM, see if that is all
11963 TEM is doing. If so, delete TEM. Otherwise, make this
11964 into a REG_UNUSED note instead. Don't delete sets to
11965 global register vars. */
11966 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
11967 || !global_regs[REGNO (XEXP (note, 0))])
11968 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
11970 rtx set = single_set (tem);
11971 rtx inner_dest = 0;
11973 rtx cc0_setter = NULL_RTX;
11977 for (inner_dest = SET_DEST (set);
11978 (GET_CODE (inner_dest) == STRICT_LOW_PART
11979 || GET_CODE (inner_dest) == SUBREG
11980 || GET_CODE (inner_dest) == ZERO_EXTRACT);
11981 inner_dest = XEXP (inner_dest, 0))
11984 /* Verify that it was the set, and not a clobber that
11985 modified the register.
11987 CC0 targets must be careful to maintain setter/user
11988 pairs. If we cannot delete the setter due to side
11989 effects, mark the user with an UNUSED note instead
11992 if (set != 0 && ! side_effects_p (SET_SRC (set))
11993 && rtx_equal_p (XEXP (note, 0), inner_dest)
11995 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11996 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11997 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
12001 /* Move the notes and links of TEM elsewhere.
12002 This might delete other dead insns recursively.
12003 First set the pattern to something that won't use
12005 rtx old_notes = REG_NOTES (tem);
12007 PATTERN (tem) = pc_rtx;
12008 REG_NOTES (tem) = NULL;
12010 distribute_notes (old_notes, tem, tem, NULL_RTX);
12011 distribute_links (LOG_LINKS (tem));
12013 SET_INSN_DELETED (tem);
12016 /* Delete the setter too. */
12019 PATTERN (cc0_setter) = pc_rtx;
12020 old_notes = REG_NOTES (cc0_setter);
12021 REG_NOTES (cc0_setter) = NULL;
12023 distribute_notes (old_notes, cc0_setter,
12024 cc0_setter, NULL_RTX);
12025 distribute_links (LOG_LINKS (cc0_setter));
12027 SET_INSN_DELETED (cc0_setter);
12033 PUT_REG_NOTE_KIND (note, REG_UNUSED);
12035 /* If there isn't already a REG_UNUSED note, put one
12036 here. Do not place a REG_DEAD note, even if
12037 the register is also used here; that would not
12038 match the algorithm used in lifetime analysis
12039 and can cause the consistency check in the
12040 scheduler to fail. */
12041 if (! find_regno_note (tem, REG_UNUSED,
12042 REGNO (XEXP (note, 0))))
12047 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
12049 && find_reg_fusage (tem, USE, XEXP (note, 0))))
12053 /* If we are doing a 3->2 combination, and we have a
12054 register which formerly died in i3 and was not used
12055 by i2, which now no longer dies in i3 and is used in
12056 i2 but does not die in i2, and place is between i2
12057 and i3, then we may need to move a link from place to
12059 if (i2 && INSN_UID (place) <= max_uid_cuid
12060 && INSN_CUID (place) > INSN_CUID (i2)
12062 && INSN_CUID (from_insn) > INSN_CUID (i2)
12063 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
12065 rtx links = LOG_LINKS (place);
12066 LOG_LINKS (place) = 0;
12067 distribute_links (links);
12072 if (tem == BB_HEAD (bb))
12076 /* We haven't found an insn for the death note and it
12077 is still a REG_DEAD note, but we have hit the beginning
12078 of the block. If the existing life info says the reg
12079 was dead, there's nothing left to do. Otherwise, we'll
12080 need to do a global life update after combine. */
12081 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
12082 && REGNO_REG_SET_P (bb->global_live_at_start,
12083 REGNO (XEXP (note, 0))))
12084 SET_BIT (refresh_blocks, this_basic_block->index);
12087 /* If the register is set or already dead at PLACE, we needn't do
12088 anything with this note if it is still a REG_DEAD note.
12089 We check here if it is set at all, not if is it totally replaced,
12090 which is what `dead_or_set_p' checks, so also check for it being
12093 if (place && REG_NOTE_KIND (note) == REG_DEAD)
12095 unsigned int regno = REGNO (XEXP (note, 0));
12097 /* Similarly, if the instruction on which we want to place
12098 the note is a noop, we'll need do a global live update
12099 after we remove them in delete_noop_moves. */
12100 if (noop_move_p (place))
12101 SET_BIT (refresh_blocks, this_basic_block->index);
12103 if (dead_or_set_p (place, XEXP (note, 0))
12104 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
12106 /* Unless the register previously died in PLACE, clear
12107 last_death. [I no longer understand why this is
12109 if (reg_stat[regno].last_death != place)
12110 reg_stat[regno].last_death = 0;
12114 reg_stat[regno].last_death = place;
12116 /* If this is a death note for a hard reg that is occupying
12117 multiple registers, ensure that we are still using all
12118 parts of the object. If we find a piece of the object
12119 that is unused, we must arrange for an appropriate REG_DEAD
12120 note to be added for it. However, we can't just emit a USE
12121 and tag the note to it, since the register might actually
12122 be dead; so we recourse, and the recursive call then finds
12123 the previous insn that used this register. */
12125 if (place && regno < FIRST_PSEUDO_REGISTER
12126 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12128 unsigned int endregno
12129 = regno + hard_regno_nregs[regno]
12130 [GET_MODE (XEXP (note, 0))];
12134 for (i = regno; i < endregno; i++)
12135 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12136 && ! find_regno_fusage (place, USE, i))
12137 || dead_or_set_regno_p (place, i))
12142 /* Put only REG_DEAD notes for pieces that are
12143 not already dead or set. */
12145 for (i = regno; i < endregno;
12146 i += hard_regno_nregs[i][reg_raw_mode[i]])
12148 rtx piece = regno_reg_rtx[i];
12149 basic_block bb = this_basic_block;
12151 if (! dead_or_set_p (place, piece)
12152 && ! reg_bitfield_target_p (piece,
12156 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12158 distribute_notes (new_note, place, place,
12161 else if (! refers_to_regno_p (i, i + 1,
12162 PATTERN (place), 0)
12163 && ! find_regno_fusage (place, USE, i))
12164 for (tem = PREV_INSN (place); ;
12165 tem = PREV_INSN (tem))
12167 if (! INSN_P (tem))
12169 if (tem == BB_HEAD (bb))
12171 SET_BIT (refresh_blocks,
12172 this_basic_block->index);
12177 if (dead_or_set_p (tem, piece)
12178 || reg_bitfield_target_p (piece,
12182 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12197 /* Any other notes should not be present at this point in the
12199 gcc_unreachable ();
12204 XEXP (note, 1) = REG_NOTES (place);
12205 REG_NOTES (place) = note;
12207 else if ((REG_NOTE_KIND (note) == REG_DEAD
12208 || REG_NOTE_KIND (note) == REG_UNUSED)
12209 && REG_P (XEXP (note, 0)))
12210 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12214 if ((REG_NOTE_KIND (note) == REG_DEAD
12215 || REG_NOTE_KIND (note) == REG_UNUSED)
12216 && REG_P (XEXP (note, 0)))
12217 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12219 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12220 REG_NOTE_KIND (note),
12222 REG_NOTES (place2));
12227 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12228 I3, I2, and I1 to new locations. This is also called to add a link
12229 pointing at I3 when I3's destination is changed. */
12232 distribute_links (rtx links)
12234 rtx link, next_link;
12236 for (link = links; link; link = next_link)
12242 next_link = XEXP (link, 1);
12244 /* If the insn that this link points to is a NOTE or isn't a single
12245 set, ignore it. In the latter case, it isn't clear what we
12246 can do other than ignore the link, since we can't tell which
12247 register it was for. Such links wouldn't be used by combine
12250 It is not possible for the destination of the target of the link to
12251 have been changed by combine. The only potential of this is if we
12252 replace I3, I2, and I1 by I3 and I2. But in that case the
12253 destination of I2 also remains unchanged. */
12255 if (NOTE_P (XEXP (link, 0))
12256 || (set = single_set (XEXP (link, 0))) == 0)
12259 reg = SET_DEST (set);
12260 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12261 || GET_CODE (reg) == SIGN_EXTRACT
12262 || GET_CODE (reg) == STRICT_LOW_PART)
12263 reg = XEXP (reg, 0);
12265 /* A LOG_LINK is defined as being placed on the first insn that uses
12266 a register and points to the insn that sets the register. Start
12267 searching at the next insn after the target of the link and stop
12268 when we reach a set of the register or the end of the basic block.
12270 Note that this correctly handles the link that used to point from
12271 I3 to I2. Also note that not much searching is typically done here
12272 since most links don't point very far away. */
12274 for (insn = NEXT_INSN (XEXP (link, 0));
12275 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12276 || BB_HEAD (this_basic_block->next_bb) != insn));
12277 insn = NEXT_INSN (insn))
12278 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12280 if (reg_referenced_p (reg, PATTERN (insn)))
12284 else if (CALL_P (insn)
12285 && find_reg_fusage (insn, USE, reg))
12290 else if (INSN_P (insn) && reg_set_p (reg, insn))
12293 /* If we found a place to put the link, place it there unless there
12294 is already a link to the same insn as LINK at that point. */
12300 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12301 if (XEXP (link2, 0) == XEXP (link, 0))
12306 XEXP (link, 1) = LOG_LINKS (place);
12307 LOG_LINKS (place) = link;
12309 /* Set added_links_insn to the earliest insn we added a
12311 if (added_links_insn == 0
12312 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12313 added_links_insn = place;
12319 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12320 Check whether the expression pointer to by LOC is a register or
12321 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12322 Otherwise return zero. */
12325 unmentioned_reg_p_1 (rtx *loc, void *expr)
12330 && (REG_P (x) || MEM_P (x))
12331 && ! reg_mentioned_p (x, (rtx) expr))
12336 /* Check for any register or memory mentioned in EQUIV that is not
12337 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12338 of EXPR where some registers may have been replaced by constants. */
12341 unmentioned_reg_p (rtx equiv, rtx expr)
12343 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12346 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12349 insn_cuid (rtx insn)
12351 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12352 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12353 insn = NEXT_INSN (insn);
12355 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12357 return INSN_CUID (insn);
12361 dump_combine_stats (FILE *file)
12365 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12366 combine_attempts, combine_merges, combine_extras, combine_successes);
12370 dump_combine_total_stats (FILE *file)
12374 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12375 total_attempts, total_merges, total_extras, total_successes);